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kvm: forward INIT signals coming from the chipset
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
5ef57876
EH		 266typedef struct FeatureWordInfo {
267 const char **feat_names;
04d104b6
EH		 268 uint32_t cpuid_eax; /* Input EAX for CPUID */
269 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
270 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
271 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 272} FeatureWordInfo;
273
274static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 275 [FEAT_1_EDX] = {
276 .feat_names = feature_name,
277 .cpuid_eax = 1, .cpuid_reg = R_EDX,
278 },
279 [FEAT_1_ECX] = {
280 .feat_names = ext_feature_name,
281 .cpuid_eax = 1, .cpuid_reg = R_ECX,
282 },
283 [FEAT_8000_0001_EDX] = {
284 .feat_names = ext2_feature_name,
285 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
286 },
287 [FEAT_8000_0001_ECX] = {
288 .feat_names = ext3_feature_name,
289 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
290 },
89e49c8b
EH		 291 [FEAT_C000_0001_EDX] = {
292 .feat_names = ext4_feature_name,
293 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
294 },
bffd67b0
EH		 295 [FEAT_KVM] = {
296 .feat_names = kvm_feature_name,
297 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
298 },
299 [FEAT_SVM] = {
300 .feat_names = svm_feature_name,
301 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
302 },
303 [FEAT_7_0_EBX] = {
304 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 305 .cpuid_eax = 7,
306 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
307 .cpuid_reg = R_EBX,
bffd67b0 308 },
5ef57876
EH		 309};
310
8e8aba50
EH		 311typedef struct X86RegisterInfo32 {
312 /* Name of register */
313 const char *name;
314 /* QAPI enum value register */
315 X86CPURegister32 qapi_enum;
316} X86RegisterInfo32;
317
318#define REGISTER(reg) \
5d371f41 319 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 320static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 321 REGISTER(EAX),
322 REGISTER(ECX),
323 REGISTER(EDX),
324 REGISTER(EBX),
325 REGISTER(ESP),
326 REGISTER(EBP),
327 REGISTER(ESI),
328 REGISTER(EDI),
329};
330#undef REGISTER
331
2560f19f
PB		 332typedef struct ExtSaveArea {
333 uint32_t feature, bits;
334 uint32_t offset, size;
335} ExtSaveArea;
336
337static const ExtSaveArea ext_save_areas[] = {
338 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 339 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 340 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
341 .offset = 0x3c0, .size = 0x40 },
342 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 343 .offset = 0x400, .size = 0x40 },
2560f19f 344};
8e8aba50 345
8b4beddc
EH		 346const char *get_register_name_32(unsigned int reg)
347{
31ccdde2 348 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 349 return NULL;
350 }
8e8aba50 351 return x86_reg_info_32[reg].name;
8b4beddc
EH		 352}
353
c6dc6f63
AP		 354/* collects per-function cpuid data
355 */
356typedef struct model_features_t {
357 uint32_t *guest_feat;
358 uint32_t *host_feat;
bffd67b0 359 FeatureWord feat_word;
8b4beddc 360} model_features_t;
c6dc6f63 361
5fcca9ff
EH		 362/* KVM-specific features that are automatically added to all CPU models
363 * when KVM is enabled.
364 */
365static uint32_t kvm_default_features[FEATURE_WORDS] = {
366 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 367 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 368 (1 << KVM_FEATURE_CLOCKSOURCE2) |
369 (1 << KVM_FEATURE_ASYNC_PF) |
370 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 371 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 372 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 373 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 374};
dc59944b 375
8fb4f821 376void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 377{
8fb4f821 378 kvm_default_features[w] &= ~features;
dc59944b
MT		 379}
380
bb44e0d1
JK		 381void host_cpuid(uint32_t function, uint32_t count,
382 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 383{
a1fd24af
AL		 384 uint32_t vec[4];
385
386#ifdef __x86_64__
387 asm volatile("cpuid"
388 : "=a"(vec[0]), "=b"(vec[1]),
389 "=c"(vec[2]), "=d"(vec[3])
390 : "0"(function), "c"(count) : "cc");
c1f41226 391#elif defined(__i386__)
a1fd24af
AL		 392 asm volatile("pusha \n\t"
393 "cpuid \n\t"
394 "mov %%eax, 0(%2) \n\t"
395 "mov %%ebx, 4(%2) \n\t"
396 "mov %%ecx, 8(%2) \n\t"
397 "mov %%edx, 12(%2) \n\t"
398 "popa"
399 : : "a"(function), "c"(count), "S"(vec)
400 : "memory", "cc");
c1f41226
EH		 401#else
402 abort();
a1fd24af
AL		 403#endif
404
bdde476a 405 if (eax)
a1fd24af 406 *eax = vec[0];
bdde476a 407 if (ebx)
a1fd24af 408 *ebx = vec[1];
bdde476a 409 if (ecx)
a1fd24af 410 *ecx = vec[2];
bdde476a 411 if (edx)
a1fd24af 412 *edx = vec[3];
bdde476a 413}
c6dc6f63
AP		 414
415#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
416
417/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
418 * a substring. ex if !NULL points to the first char after a substring,
419 * otherwise the string is assumed to sized by a terminating nul.
420 * Return lexical ordering of *s1:*s2.
421 */
422static int sstrcmp(const char *s1, const char *e1, const char *s2,
423 const char *e2)
424{
425 for (;;) {
426 if (!*s1 || !*s2 || *s1 != *s2)
427 return (*s1 - *s2);
428 ++s1, ++s2;
429 if (s1 == e1 && s2 == e2)
430 return (0);
431 else if (s1 == e1)
432 return (*s2);
433 else if (s2 == e2)
434 return (*s1);
435 }
436}
437
438/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
439 * '|' delimited (possibly empty) strings in which case search for a match
440 * within the alternatives proceeds left to right. Return 0 for success,
441 * non-zero otherwise.
442 */
443static int altcmp(const char *s, const char *e, const char *altstr)
444{
445 const char *p, *q;
446
447 for (q = p = altstr; ; ) {
448 while (*p && *p != '|')
449 ++p;
450 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
451 return (0);
452 if (!*p)
453 return (1);
454 else
455 q = ++p;
456 }
457}
458
459/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 460 * *pval and return true, otherwise return false
c6dc6f63 461 */
e41e0fc6
JK		 462static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
463 const char **featureset)
c6dc6f63
AP		 464{
465 uint32_t mask;
466 const char **ppc;
e41e0fc6 467 bool found = false;
c6dc6f63 468
e41e0fc6 469 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 470 if (*ppc && !altcmp(s, e, *ppc)) {
471 *pval |= mask;
e41e0fc6 472 found = true;
c6dc6f63 473 }
e41e0fc6
JK		 474 }
475 return found;
c6dc6f63
AP		 476}
477
5ef57876
EH		 478static void add_flagname_to_bitmaps(const char *flagname,
479 FeatureWordArray words)
c6dc6f63 480{
5ef57876
EH		 481 FeatureWord w;
482 for (w = 0; w < FEATURE_WORDS; w++) {
483 FeatureWordInfo *wi = &feature_word_info[w];
484 if (wi->feat_names &&
485 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
486 break;
487 }
488 }
489 if (w == FEATURE_WORDS) {
490 fprintf(stderr, "CPU feature %s not found\n", flagname);
491 }
c6dc6f63
AP		 492}
493
d940ee9b
EH		 494/* CPU class name definitions: */
495
496#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
497#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
498
499/* Return type name for a given CPU model name
500 * Caller is responsible for freeing the returned string.
501 */
502static char *x86_cpu_type_name(const char *model_name)
503{
504 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
505}
506
500050d1
AF		 507static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
508{
d940ee9b
EH		 509 ObjectClass *oc;
510 char *typename;
511
500050d1
AF		 512 if (cpu_model == NULL) {
513 return NULL;
514 }
515
d940ee9b
EH		 516 typename = x86_cpu_type_name(cpu_model);
517 oc = object_class_by_name(typename);
518 g_free(typename);
519 return oc;
500050d1
AF		 520}
521
d940ee9b 522struct X86CPUDefinition {
c6dc6f63
AP		 523 const char *name;
524 uint32_t level;
90e4b0c3
EH		 525 uint32_t xlevel;
526 uint32_t xlevel2;
99b88a17
IM		 527 /* vendor is zero-terminated, 12 character ASCII string */
528 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 529 int family;
530 int model;
531 int stepping;
0514ef2f 532 FeatureWordArray features;
c6dc6f63 533 char model_id[48];
787aaf57 534 bool cache_info_passthrough;
d940ee9b 535};
c6dc6f63
AP		 536
537#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
538#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
539 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
540#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
541 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
542 CPUID_PSE36 | CPUID_FXSR)
543#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
544#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
545 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
546 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
547 CPUID_PAE | CPUID_SEP | CPUID_APIC)
548
551a2dec
AP		 549#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
550 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
551 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
552 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
553 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 554 /* partly implemented:
555 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
556 CPUID_PSE36 (needed for Solaris) */
557 /* missing:
558 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 559#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
560 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
561 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 562 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 563 /* missing:
e71827bc
AJ		 564 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
565 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
566 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 567 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
568 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 569 CPUID_EXT_RDRAND */
60032ac0 570#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec
AP		 571 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
572 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 573 /* missing:
574 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 575#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
576 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 577#define TCG_SVM_FEATURES 0
7073fbad 578#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 579 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 580 /* missing:
7073fbad
RH		 581 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
582 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 583 CPUID_7_0_EBX_RDSEED */
551a2dec 584
9576de75 585static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 586 {
587 .name = "qemu64",
588 .level = 4,
99b88a17 589 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 590 .family = 6,
f8e6a11a 591 .model = 6,
c6dc6f63 592 .stepping = 3,
0514ef2f 593 .features[FEAT_1_EDX] =
27861ecc 594 PPRO_FEATURES |
c6dc6f63 595 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 596 CPUID_PSE36,
0514ef2f 597 .features[FEAT_1_ECX] =
27861ecc 598 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 599 .features[FEAT_8000_0001_EDX] =
27861ecc 600 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 601 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 602 .features[FEAT_8000_0001_ECX] =
27861ecc 603 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 604 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
605 .xlevel = 0x8000000A,
c6dc6f63
AP		 606 },
607 {
608 .name = "phenom",
609 .level = 5,
99b88a17 610 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 611 .family = 16,
612 .model = 2,
613 .stepping = 3,
0514ef2f 614 .features[FEAT_1_EDX] =
27861ecc 615 PPRO_FEATURES |
c6dc6f63 616 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 617 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 618 .features[FEAT_1_ECX] =
27861ecc 619 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 620 CPUID_EXT_POPCNT,
0514ef2f 621 .features[FEAT_8000_0001_EDX] =
27861ecc 622 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 623 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
624 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 625 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 626 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
627 CPUID_EXT3_CR8LEG,
628 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
629 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 630 .features[FEAT_8000_0001_ECX] =
27861ecc 631 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 632 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 633 .features[FEAT_SVM] =
27861ecc 634 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 635 .xlevel = 0x8000001A,
636 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
637 },
638 {
639 .name = "core2duo",
640 .level = 10,
99b88a17 641 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 642 .family = 6,
643 .model = 15,
644 .stepping = 11,
0514ef2f 645 .features[FEAT_1_EDX] =
27861ecc 646 PPRO_FEATURES |
c6dc6f63 647 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 648 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
649 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 650 .features[FEAT_1_ECX] =
27861ecc 651 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 652 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
653 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 654 .features[FEAT_8000_0001_EDX] =
27861ecc 655 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 656 .features[FEAT_8000_0001_ECX] =
27861ecc 657 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 658 .xlevel = 0x80000008,
659 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
660 },
661 {
662 .name = "kvm64",
663 .level = 5,
99b88a17 664 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 665 .family = 15,
666 .model = 6,
667 .stepping = 1,
668 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 669 .features[FEAT_1_EDX] =
27861ecc 670 PPRO_FEATURES |
c6dc6f63
AP		 671 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
672 CPUID_PSE36,
673 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 674 .features[FEAT_1_ECX] =
27861ecc 675 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 676 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 677 .features[FEAT_8000_0001_EDX] =
27861ecc 678 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 679 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
680 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
681 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
682 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
683 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 684 .features[FEAT_8000_0001_ECX] =
27861ecc 685 0,
c6dc6f63
AP		 686 .xlevel = 0x80000008,
687 .model_id = "Common KVM processor"
688 },
c6dc6f63
AP		 689 {
690 .name = "qemu32",
691 .level = 4,
99b88a17 692 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 693 .family = 6,
f8e6a11a 694 .model = 6,
c6dc6f63 695 .stepping = 3,
0514ef2f 696 .features[FEAT_1_EDX] =
27861ecc 697 PPRO_FEATURES,
0514ef2f 698 .features[FEAT_1_ECX] =
27861ecc 699 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 700 .xlevel = 0x80000004,
c6dc6f63 701 },
eafaf1e5
AP		 702 {
703 .name = "kvm32",
704 .level = 5,
99b88a17 705 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 706 .family = 15,
707 .model = 6,
708 .stepping = 1,
0514ef2f 709 .features[FEAT_1_EDX] =
27861ecc 710 PPRO_FEATURES |
eafaf1e5 711 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 712 .features[FEAT_1_ECX] =
27861ecc 713 CPUID_EXT_SSE3,
0514ef2f 714 .features[FEAT_8000_0001_EDX] =
27861ecc 715 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 716 .features[FEAT_8000_0001_ECX] =
27861ecc 717 0,
eafaf1e5
AP		 718 .xlevel = 0x80000008,
719 .model_id = "Common 32-bit KVM processor"
720 },
c6dc6f63
AP		 721 {
722 .name = "coreduo",
723 .level = 10,
99b88a17 724 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 725 .family = 6,
726 .model = 14,
727 .stepping = 8,
0514ef2f 728 .features[FEAT_1_EDX] =
27861ecc 729 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 730 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
731 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 732 .features[FEAT_1_ECX] =
27861ecc 733 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 734 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 735 .features[FEAT_8000_0001_EDX] =
27861ecc 736 CPUID_EXT2_NX,
c6dc6f63
AP		 737 .xlevel = 0x80000008,
738 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
739 },
740 {
741 .name = "486",
58012d66 742 .level = 1,
99b88a17 743 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 744 .family = 4,
b2a856d9 745 .model = 8,
c6dc6f63 746 .stepping = 0,
0514ef2f 747 .features[FEAT_1_EDX] =
27861ecc 748 I486_FEATURES,
c6dc6f63
AP		 749 .xlevel = 0,
750 },
751 {
752 .name = "pentium",
753 .level = 1,
99b88a17 754 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 755 .family = 5,
756 .model = 4,
757 .stepping = 3,
0514ef2f 758 .features[FEAT_1_EDX] =
27861ecc 759 PENTIUM_FEATURES,
c6dc6f63
AP		 760 .xlevel = 0,
761 },
762 {
763 .name = "pentium2",
764 .level = 2,
99b88a17 765 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 766 .family = 6,
767 .model = 5,
768 .stepping = 2,
0514ef2f 769 .features[FEAT_1_EDX] =
27861ecc 770 PENTIUM2_FEATURES,
c6dc6f63
AP		 771 .xlevel = 0,
772 },
773 {
774 .name = "pentium3",
775 .level = 2,
99b88a17 776 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 777 .family = 6,
778 .model = 7,
779 .stepping = 3,
0514ef2f 780 .features[FEAT_1_EDX] =
27861ecc 781 PENTIUM3_FEATURES,
c6dc6f63
AP		 782 .xlevel = 0,
783 },
784 {
785 .name = "athlon",
786 .level = 2,
99b88a17 787 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 788 .family = 6,
789 .model = 2,
790 .stepping = 3,
0514ef2f 791 .features[FEAT_1_EDX] =
27861ecc 792 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 793 CPUID_MCA,
0514ef2f 794 .features[FEAT_8000_0001_EDX] =
27861ecc 795 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 796 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 797 .xlevel = 0x80000008,
c6dc6f63
AP		 798 },
799 {
800 .name = "n270",
801 /* original is on level 10 */
802 .level = 5,
99b88a17 803 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 804 .family = 6,
805 .model = 28,
806 .stepping = 2,
0514ef2f 807 .features[FEAT_1_EDX] =
27861ecc 808 PPRO_FEATURES |
8560efed
AJ		 809 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
810 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 811 /* Some CPUs got no CPUID_SEP */
0514ef2f 812 .features[FEAT_1_ECX] =
27861ecc 813 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 814 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
815 CPUID_EXT_MOVBE,
0514ef2f 816 .features[FEAT_8000_0001_EDX] =
27861ecc 817 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 818 CPUID_EXT2_NX,
0514ef2f 819 .features[FEAT_8000_0001_ECX] =
27861ecc 820 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 821 .xlevel = 0x8000000A,
822 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
823 },
3eca4642
EH		 824 {
825 .name = "Conroe",
6b11322e 826 .level = 4,
99b88a17 827 .vendor = CPUID_VENDOR_INTEL,
3eca4642 828 .family = 6,
ffce9ebb 829 .model = 15,
3eca4642 830 .stepping = 3,
0514ef2f 831 .features[FEAT_1_EDX] =
27861ecc 832 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 833 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
834 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
835 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
836 CPUID_DE | CPUID_FP87,
0514ef2f 837 .features[FEAT_1_ECX] =
27861ecc 838 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 839 .features[FEAT_8000_0001_EDX] =
27861ecc 840 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 841 .features[FEAT_8000_0001_ECX] =
27861ecc 842 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 843 .xlevel = 0x8000000A,
844 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
845 },
846 {
847 .name = "Penryn",
6b11322e 848 .level = 4,
99b88a17 849 .vendor = CPUID_VENDOR_INTEL,
3eca4642 850 .family = 6,
ffce9ebb 851 .model = 23,
3eca4642 852 .stepping = 3,
0514ef2f 853 .features[FEAT_1_EDX] =
27861ecc 854 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 855 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
856 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
857 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
858 CPUID_DE | CPUID_FP87,
0514ef2f 859 .features[FEAT_1_ECX] =
27861ecc 860 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 861 CPUID_EXT_SSE3,
0514ef2f 862 .features[FEAT_8000_0001_EDX] =
27861ecc 863 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 864 .features[FEAT_8000_0001_ECX] =
27861ecc 865 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 866 .xlevel = 0x8000000A,
867 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
868 },
869 {
870 .name = "Nehalem",
6b11322e 871 .level = 4,
99b88a17 872 .vendor = CPUID_VENDOR_INTEL,
3eca4642 873 .family = 6,
ffce9ebb 874 .model = 26,
3eca4642 875 .stepping = 3,
0514ef2f 876 .features[FEAT_1_EDX] =
27861ecc 877 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 878 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
879 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
880 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
881 CPUID_DE | CPUID_FP87,
0514ef2f 882 .features[FEAT_1_ECX] =
27861ecc 883 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 884 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 885 .features[FEAT_8000_0001_EDX] =
27861ecc 886 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 887 .features[FEAT_8000_0001_ECX] =
27861ecc 888 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 889 .xlevel = 0x8000000A,
890 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
891 },
892 {
893 .name = "Westmere",
894 .level = 11,
99b88a17 895 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 896 .family = 6,
897 .model = 44,
898 .stepping = 1,
0514ef2f 899 .features[FEAT_1_EDX] =
27861ecc 900 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 901 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
902 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
903 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
904 CPUID_DE | CPUID_FP87,
0514ef2f 905 .features[FEAT_1_ECX] =
27861ecc 906 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 907 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 908 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 909 .features[FEAT_8000_0001_EDX] =
27861ecc 910 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 911 .features[FEAT_8000_0001_ECX] =
27861ecc 912 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 913 .xlevel = 0x8000000A,
914 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
915 },
916 {
917 .name = "SandyBridge",
918 .level = 0xd,
99b88a17 919 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 920 .family = 6,
921 .model = 42,
922 .stepping = 1,
0514ef2f 923 .features[FEAT_1_EDX] =
27861ecc 924 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 925 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
926 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
927 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
928 CPUID_DE | CPUID_FP87,
0514ef2f 929 .features[FEAT_1_ECX] =
27861ecc 930 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 931 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
932 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
933 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
934 CPUID_EXT_SSE3,
0514ef2f 935 .features[FEAT_8000_0001_EDX] =
27861ecc 936 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 937 CPUID_EXT2_SYSCALL,
0514ef2f 938 .features[FEAT_8000_0001_ECX] =
27861ecc 939 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 940 .xlevel = 0x8000000A,
941 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
942 },
37507094
EH		 943 {
944 .name = "Haswell",
945 .level = 0xd,
99b88a17 946 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 947 .family = 6,
948 .model = 60,
949 .stepping = 1,
0514ef2f 950 .features[FEAT_1_EDX] =
27861ecc 951 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
955 CPUID_DE | CPUID_FP87,
0514ef2f 956 .features[FEAT_1_ECX] =
27861ecc 957 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 958 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
959 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
960 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
961 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
962 CPUID_EXT_PCID,
0514ef2f 963 .features[FEAT_8000_0001_EDX] =
27861ecc 964 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 965 CPUID_EXT2_SYSCALL,
0514ef2f 966 .features[FEAT_8000_0001_ECX] =
27861ecc 967 CPUID_EXT3_LAHF_LM,
0514ef2f 968 .features[FEAT_7_0_EBX] =
27861ecc 969 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 970 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
971 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
972 CPUID_7_0_EBX_RTM,
973 .xlevel = 0x8000000A,
974 .model_id = "Intel Core Processor (Haswell)",
975 },
3eca4642
EH		 976 {
977 .name = "Opteron_G1",
978 .level = 5,
99b88a17 979 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 980 .family = 15,
981 .model = 6,
982 .stepping = 1,
0514ef2f 983 .features[FEAT_1_EDX] =
27861ecc 984 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 985 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
986 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
987 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
988 CPUID_DE | CPUID_FP87,
0514ef2f 989 .features[FEAT_1_ECX] =
27861ecc 990 CPUID_EXT_SSE3,
0514ef2f 991 .features[FEAT_8000_0001_EDX] =
27861ecc 992 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 993 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
994 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
995 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
996 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
997 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
998 .xlevel = 0x80000008,
999 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1000 },
1001 {
1002 .name = "Opteron_G2",
1003 .level = 5,
99b88a17 1004 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1005 .family = 15,
1006 .model = 6,
1007 .stepping = 1,
0514ef2f 1008 .features[FEAT_1_EDX] =
27861ecc 1009 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1013 CPUID_DE | CPUID_FP87,
0514ef2f 1014 .features[FEAT_1_ECX] =
27861ecc 1015 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1016 .features[FEAT_8000_0001_EDX] =
27861ecc 1017 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1018 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1019 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1020 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1021 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1022 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1023 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1024 .features[FEAT_8000_0001_ECX] =
27861ecc 1025 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1026 .xlevel = 0x80000008,
1027 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1028 },
1029 {
1030 .name = "Opteron_G3",
1031 .level = 5,
99b88a17 1032 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1033 .family = 15,
1034 .model = 6,
1035 .stepping = 1,
0514ef2f 1036 .features[FEAT_1_EDX] =
27861ecc 1037 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1038 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1039 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1040 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1041 CPUID_DE | CPUID_FP87,
0514ef2f 1042 .features[FEAT_1_ECX] =
27861ecc 1043 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1044 CPUID_EXT_SSE3,
0514ef2f 1045 .features[FEAT_8000_0001_EDX] =
27861ecc 1046 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1047 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1048 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1049 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1050 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1051 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1052 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1053 .features[FEAT_8000_0001_ECX] =
27861ecc 1054 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1055 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1056 .xlevel = 0x80000008,
1057 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1058 },
1059 {
1060 .name = "Opteron_G4",
1061 .level = 0xd,
99b88a17 1062 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1063 .family = 21,
1064 .model = 1,
1065 .stepping = 2,
0514ef2f 1066 .features[FEAT_1_EDX] =
27861ecc 1067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1068 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071 CPUID_DE | CPUID_FP87,
0514ef2f 1072 .features[FEAT_1_ECX] =
27861ecc 1073 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1074 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1075 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1076 CPUID_EXT_SSE3,
0514ef2f 1077 .features[FEAT_8000_0001_EDX] =
27861ecc 1078 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1079 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1080 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1081 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1082 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1083 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1084 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1085 .features[FEAT_8000_0001_ECX] =
27861ecc 1086 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1087 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1088 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1089 CPUID_EXT3_LAHF_LM,
1090 .xlevel = 0x8000001A,
1091 .model_id = "AMD Opteron 62xx class CPU",
1092 },
021941b9
AP		 1093 {
1094 .name = "Opteron_G5",
1095 .level = 0xd,
99b88a17 1096 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1097 .family = 21,
1098 .model = 2,
1099 .stepping = 0,
0514ef2f 1100 .features[FEAT_1_EDX] =
27861ecc 1101 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1102 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1103 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1104 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1105 CPUID_DE | CPUID_FP87,
0514ef2f 1106 .features[FEAT_1_ECX] =
27861ecc 1107 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1108 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1109 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1110 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1111 .features[FEAT_8000_0001_EDX] =
27861ecc 1112 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1113 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1114 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1115 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1116 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1117 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1118 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1119 .features[FEAT_8000_0001_ECX] =
27861ecc 1120 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1121 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1122 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1123 CPUID_EXT3_LAHF_LM,
1124 .xlevel = 0x8000001A,
1125 .model_id = "AMD Opteron 63xx class CPU",
1126 },
c6dc6f63
AP		 1127};
1128
0668af54
EH		 1129/**
1130 * x86_cpu_compat_set_features:
1131 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1132 * @w: Identifies the feature word to be changed.
1133 * @feat_add: Feature bits to be added to feature word
1134 * @feat_remove: Feature bits to be removed from feature word
1135 *
1136 * Change CPU model feature bits for compatibility.
1137 *
1138 * This function may be used by machine-type compatibility functions
1139 * to enable or disable feature bits on specific CPU models.
1140 */
1141void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1142 uint32_t feat_add, uint32_t feat_remove)
1143{
9576de75 1144 X86CPUDefinition *def;
0668af54
EH		 1145 int i;
1146 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1147 def = &builtin_x86_defs[i];
1148 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1149 def->features[w] |= feat_add;
1150 def->features[w] &= ~feat_remove;
1151 }
1152 }
1153}
1154
d940ee9b
EH		 1155#ifdef CONFIG_KVM
1156
c6dc6f63
AP		 1157static int cpu_x86_fill_model_id(char *str)
1158{
1159 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1160 int i;
1161
1162 for (i = 0; i < 3; i++) {
1163 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1164 memcpy(str + i * 16 + 0, &eax, 4);
1165 memcpy(str + i * 16 + 4, &ebx, 4);
1166 memcpy(str + i * 16 + 8, &ecx, 4);
1167 memcpy(str + i * 16 + 12, &edx, 4);
1168 }
1169 return 0;
1170}
1171
d940ee9b
EH		 1172static X86CPUDefinition host_cpudef;
1173
1174/* class_init for the "host" CPU model
6e746f30 1175 *
d940ee9b 1176 * This function may be called before KVM is initialized.
6e746f30 1177 */
d940ee9b 1178static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1179{
d940ee9b 1180 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1181 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1182
d940ee9b 1183 xcc->kvm_required = true;
6e746f30 1184
c6dc6f63 1185 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1186 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1187
1188 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1189 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1190 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1191 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1192
d940ee9b 1193 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1194
d940ee9b
EH		 1195 xcc->cpu_def = &host_cpudef;
1196 host_cpudef.cache_info_passthrough = true;
1197
1198 /* level, xlevel, xlevel2, and the feature words are initialized on
1199 * instance_init, because they require KVM to be initialized.
1200 */
1201}
1202
1203static void host_x86_cpu_initfn(Object *obj)
1204{
1205 X86CPU *cpu = X86_CPU(obj);
1206 CPUX86State *env = &cpu->env;
1207 KVMState *s = kvm_state;
1208 FeatureWord w;
1209
1210 assert(kvm_enabled());
1211
1212 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1213 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1214 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1215
2bc65d2b
EH		 1216 for (w = 0; w < FEATURE_WORDS; w++) {
1217 FeatureWordInfo *wi = &feature_word_info[w];
d940ee9b 1218 env->features[w] =
2bc65d2b
EH		 1219 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1220 wi->cpuid_reg);
1221 }
d940ee9b 1222 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1223}
1224
d940ee9b
EH		 1225static const TypeInfo host_x86_cpu_type_info = {
1226 .name = X86_CPU_TYPE_NAME("host"),
1227 .parent = TYPE_X86_CPU,
1228 .instance_init = host_x86_cpu_initfn,
1229 .class_init = host_x86_cpu_class_init,
1230};
1231
1232#endif
1233
bffd67b0 1234static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1235{
1236 int i;
1237
1238 for (i = 0; i < 32; ++i)
1239 if (1 << i & mask) {
bffd67b0 1240 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1241 assert(reg);
1242 fprintf(stderr, "warning: host doesn't support requested feature: "
1243 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1244 f->cpuid_eax, reg,
1245 f->feat_names[i] ? "." : "",
1246 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1247 break;
1248 }
1249 return 0;
1250}
1251
07ca5945
EH		 1252/* Check if all requested cpu flags are making their way to the guest
1253 *
1254 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1255 *
1256 * This function may be called only if KVM is enabled.
c6dc6f63 1257 */
f0b9b111 1258static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
c6dc6f63 1259{
5ec01c2e 1260 CPUX86State *env = &cpu->env;
f0b9b111
EH		 1261 int rv = 0;
1262 FeatureWord w;
c6dc6f63 1263
6e746f30
EH		 1264 assert(kvm_enabled());
1265
f0b9b111 1266 for (w = 0; w < FEATURE_WORDS; w++) {
bffd67b0 1267 FeatureWordInfo *wi = &feature_word_info[w];
f0b9b111
EH		 1268 uint32_t guest_feat = env->features[w];
1269 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1270 wi->cpuid_ecx,
1271 wi->cpuid_reg);
1272 uint32_t mask;
bffd67b0 1273 for (mask = 1; mask; mask <<= 1) {
f0b9b111 1274 if (guest_feat & mask && !(host_feat & mask)) {
bffd67b0
EH		 1275 unavailable_host_feature(wi, mask);
1276 rv = 1;
1277 }
1278 }
1279 }
c6dc6f63
AP		 1280 return rv;
1281}
1282
95b8519d
AF		 1283static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1284 const char *name, Error **errp)
1285{
1286 X86CPU *cpu = X86_CPU(obj);
1287 CPUX86State *env = &cpu->env;
1288 int64_t value;
1289
1290 value = (env->cpuid_version >> 8) & 0xf;
1291 if (value == 0xf) {
1292 value += (env->cpuid_version >> 20) & 0xff;
1293 }
1294 visit_type_int(v, &value, name, errp);
1295}
1296
71ad61d3
AF		 1297static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1298 const char *name, Error **errp)
ed5e1ec3 1299{
71ad61d3
AF		 1300 X86CPU *cpu = X86_CPU(obj);
1301 CPUX86State *env = &cpu->env;
1302 const int64_t min = 0;
1303 const int64_t max = 0xff + 0xf;
65cd9064 1304 Error *local_err = NULL;
71ad61d3
AF		 1305 int64_t value;
1306
65cd9064
MA		 1307 visit_type_int(v, &value, name, &local_err);
1308 if (local_err) {
1309 error_propagate(errp, local_err);
71ad61d3
AF		 1310 return;
1311 }
1312 if (value < min || value > max) {
1313 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1314 name ? name : "null", value, min, max);
1315 return;
1316 }
1317
ed5e1ec3 1318 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1319 if (value > 0x0f) {
1320 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1321 } else {
71ad61d3 1322 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1323 }
1324}
1325
67e30c83
AF		 1326static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1327 const char *name, Error **errp)
1328{
1329 X86CPU *cpu = X86_CPU(obj);
1330 CPUX86State *env = &cpu->env;
1331 int64_t value;
1332
1333 value = (env->cpuid_version >> 4) & 0xf;
1334 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1335 visit_type_int(v, &value, name, errp);
1336}
1337
c5291a4f
AF		 1338static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1339 const char *name, Error **errp)
b0704cbd 1340{
c5291a4f
AF		 1341 X86CPU *cpu = X86_CPU(obj);
1342 CPUX86State *env = &cpu->env;
1343 const int64_t min = 0;
1344 const int64_t max = 0xff;
65cd9064 1345 Error *local_err = NULL;
c5291a4f
AF		 1346 int64_t value;
1347
65cd9064
MA		 1348 visit_type_int(v, &value, name, &local_err);
1349 if (local_err) {
1350 error_propagate(errp, local_err);
c5291a4f
AF		 1351 return;
1352 }
1353 if (value < min || value > max) {
1354 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1355 name ? name : "null", value, min, max);
1356 return;
1357 }
1358
b0704cbd 1359 env->cpuid_version &= ~0xf00f0;
c5291a4f 1360 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1361}
1362
35112e41
AF		 1363static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1364 void *opaque, const char *name,
1365 Error **errp)
1366{
1367 X86CPU *cpu = X86_CPU(obj);
1368 CPUX86State *env = &cpu->env;
1369 int64_t value;
1370
1371 value = env->cpuid_version & 0xf;
1372 visit_type_int(v, &value, name, errp);
1373}
1374
036e2222
AF		 1375static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1376 void *opaque, const char *name,
1377 Error **errp)
38c3dc46 1378{
036e2222
AF		 1379 X86CPU *cpu = X86_CPU(obj);
1380 CPUX86State *env = &cpu->env;
1381 const int64_t min = 0;
1382 const int64_t max = 0xf;
65cd9064 1383 Error *local_err = NULL;
036e2222
AF		 1384 int64_t value;
1385
65cd9064
MA		 1386 visit_type_int(v, &value, name, &local_err);
1387 if (local_err) {
1388 error_propagate(errp, local_err);
036e2222
AF		 1389 return;
1390 }
1391 if (value < min || value > max) {
1392 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1393 name ? name : "null", value, min, max);
1394 return;
1395 }
1396
38c3dc46 1397 env->cpuid_version &= ~0xf;
036e2222 1398 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1399}
1400
8e1898bf
AF		 1401static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1402 const char *name, Error **errp)
1403{
1404 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1405
fa029887 1406 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1407}
1408
1409static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1410 const char *name, Error **errp)
1411{
1412 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1413
fa029887 1414 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1415}
1416
16b93aa8
AF		 1417static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1418 const char *name, Error **errp)
1419{
1420 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1421
fa029887 1422 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1423}
1424
1425static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1426 const char *name, Error **errp)
1427{
1428 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1429
fa029887 1430 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1431}
1432
d480e1af
AF		 1433static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1434{
1435 X86CPU *cpu = X86_CPU(obj);
1436 CPUX86State *env = &cpu->env;
1437 char *value;
d480e1af 1438
9df694ee 1439 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1440 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1441 env->cpuid_vendor3);
d480e1af
AF		 1442 return value;
1443}
1444
1445static void x86_cpuid_set_vendor(Object *obj, const char *value,
1446 Error **errp)
1447{
1448 X86CPU *cpu = X86_CPU(obj);
1449 CPUX86State *env = &cpu->env;
1450 int i;
1451
9df694ee 1452 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1453 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1454 "vendor", value);
1455 return;
1456 }
1457
1458 env->cpuid_vendor1 = 0;
1459 env->cpuid_vendor2 = 0;
1460 env->cpuid_vendor3 = 0;
1461 for (i = 0; i < 4; i++) {
1462 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1463 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1464 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1465 }
d480e1af
AF		 1466}
1467
63e886eb
AF		 1468static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1469{
1470 X86CPU *cpu = X86_CPU(obj);
1471 CPUX86State *env = &cpu->env;
1472 char *value;
1473 int i;
1474
1475 value = g_malloc(48 + 1);
1476 for (i = 0; i < 48; i++) {
1477 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1478 }
1479 value[48] = '\0';
1480 return value;
1481}
1482
938d4c25
AF		 1483static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1484 Error **errp)
dcce6675 1485{
938d4c25
AF		 1486 X86CPU *cpu = X86_CPU(obj);
1487 CPUX86State *env = &cpu->env;
dcce6675
AF		 1488 int c, len, i;
1489
1490 if (model_id == NULL) {
1491 model_id = "";
1492 }
1493 len = strlen(model_id);
d0a6acf4 1494 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1495 for (i = 0; i < 48; i++) {
1496 if (i >= len) {
1497 c = '\0';
1498 } else {
1499 c = (uint8_t)model_id[i];
1500 }
1501 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1502 }
1503}
1504
89e48965
AF		 1505static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1506 const char *name, Error **errp)
1507{
1508 X86CPU *cpu = X86_CPU(obj);
1509 int64_t value;
1510
1511 value = cpu->env.tsc_khz * 1000;
1512 visit_type_int(v, &value, name, errp);
1513}
1514
1515static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1516 const char *name, Error **errp)
1517{
1518 X86CPU *cpu = X86_CPU(obj);
1519 const int64_t min = 0;
2e84849a 1520 const int64_t max = INT64_MAX;
65cd9064 1521 Error *local_err = NULL;
89e48965
AF		 1522 int64_t value;
1523
65cd9064
MA		 1524 visit_type_int(v, &value, name, &local_err);
1525 if (local_err) {
1526 error_propagate(errp, local_err);
89e48965
AF		 1527 return;
1528 }
1529 if (value < min || value > max) {
1530 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1531 name ? name : "null", value, min, max);
1532 return;
1533 }
1534
1535 cpu->env.tsc_khz = value / 1000;
1536}
1537
31050930
IM		 1538static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1539 const char *name, Error **errp)
1540{
1541 X86CPU *cpu = X86_CPU(obj);
1542 int64_t value = cpu->env.cpuid_apic_id;
1543
1544 visit_type_int(v, &value, name, errp);
1545}
1546
1547static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1548 const char *name, Error **errp)
1549{
1550 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1551 DeviceState *dev = DEVICE(obj);
31050930
IM		 1552 const int64_t min = 0;
1553 const int64_t max = UINT32_MAX;
1554 Error *error = NULL;
1555 int64_t value;
1556
8d6d4980
IM		 1557 if (dev->realized) {
1558 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1559 "it was realized", name, object_get_typename(obj));
1560 return;
1561 }
1562
31050930
IM		 1563 visit_type_int(v, &value, name, &error);
1564 if (error) {
1565 error_propagate(errp, error);
1566 return;
1567 }
1568 if (value < min || value > max) {
1569 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1570 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1571 object_get_typename(obj), name, value, min, max);
1572 return;
1573 }
1574
1575 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1576 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1577 return;
1578 }
1579 cpu->env.cpuid_apic_id = value;
1580}
1581
7e5292b5 1582/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1583static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1584 const char *name, Error **errp)
1585{
7e5292b5 1586 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1587 FeatureWord w;
1588 Error *err = NULL;
1589 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1590 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1591 X86CPUFeatureWordInfoList *list = NULL;
1592
1593 for (w = 0; w < FEATURE_WORDS; w++) {
1594 FeatureWordInfo *wi = &feature_word_info[w];
1595 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1596 qwi->cpuid_input_eax = wi->cpuid_eax;
1597 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1598 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1599 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1600 qwi->features = array[w];
8e8aba50
EH		 1601
1602 /* List will be in reverse order, but order shouldn't matter */
1603 list_entries[w].next = list;
1604 list_entries[w].value = &word_infos[w];
1605 list = &list_entries[w];
1606 }
1607
1608 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1609 error_propagate(errp, err);
1610}
1611
c8f0f88e
IM		 1612static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1613 const char *name, Error **errp)
1614{
1615 X86CPU *cpu = X86_CPU(obj);
1616 int64_t value = cpu->hyperv_spinlock_attempts;
1617
1618 visit_type_int(v, &value, name, errp);
1619}
1620
1621static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1622 const char *name, Error **errp)
1623{
1624 const int64_t min = 0xFFF;
1625 const int64_t max = UINT_MAX;
1626 X86CPU *cpu = X86_CPU(obj);
1627 Error *err = NULL;
1628 int64_t value;
1629
1630 visit_type_int(v, &value, name, &err);
1631 if (err) {
1632 error_propagate(errp, err);
1633 return;
1634 }
1635
1636 if (value < min || value > max) {
1637 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1638 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1639 object_get_typename(obj), name ? name : "null",
1640 value, min, max);
1641 return;
1642 }
1643 cpu->hyperv_spinlock_attempts = value;
1644}
1645
1646static PropertyInfo qdev_prop_spinlocks = {
1647 .name = "int",
1648 .get = x86_get_hv_spinlocks,
1649 .set = x86_set_hv_spinlocks,
1650};
1651
72ac2e87
IM		 1652/* Convert all '_' in a feature string option name to '-', to make feature
1653 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1654 */
1655static inline void feat2prop(char *s)
1656{
1657 while ((s = strchr(s, '_'))) {
1658 *s = '-';
1659 }
1660}
1661
8f961357
EH		 1662/* Parse "+feature,-feature,feature=foo" CPU feature string
1663 */
94a444b2
AF		 1664static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1665 Error **errp)
8f961357 1666{
94a444b2 1667 X86CPU *cpu = X86_CPU(cs);
8f961357
EH		 1668 char *featurestr; /* Single 'key=value" string being parsed */
1669 /* Features to be added */
077c68c3 1670 FeatureWordArray plus_features = { 0 };
8f961357 1671 /* Features to be removed */
5ef57876 1672 FeatureWordArray minus_features = { 0 };
8f961357 1673 uint32_t numvalue;
a91987c2 1674 CPUX86State *env = &cpu->env;
94a444b2 1675 Error *local_err = NULL;
8f961357 1676
8f961357 1677 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1678
1679 while (featurestr) {
1680 char *val;
1681 if (featurestr[0] == '+') {
5ef57876 1682 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1683 } else if (featurestr[0] == '-') {
5ef57876 1684 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1685 } else if ((val = strchr(featurestr, '='))) {
1686 *val = 0; val++;
72ac2e87 1687 feat2prop(featurestr);
d024d209 1688 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1689 char *err;
a91987c2
IM		 1690 char num[32];
1691
c6dc6f63
AP		 1692 numvalue = strtoul(val, &err, 0);
1693 if (!*val || *err) {
94a444b2 1694 error_setg(&local_err, "bad numerical value %s", val);
a91987c2 1695 goto out;
c6dc6f63
AP		 1696 }
1697 if (numvalue < 0x80000000) {
94a444b2
AF		 1698 error_report("xlevel value shall always be >= 0x80000000"
1699 ", fixup will be removed in future versions");
2f7a21c4 1700 numvalue += 0x80000000;
c6dc6f63 1701 }
a91987c2 1702 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1703 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1704 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1705 int64_t tsc_freq;
1706 char *err;
a91987c2 1707 char num[32];
b862d1fe
JR		 1708
1709 tsc_freq = strtosz_suffix_unit(val, &err,
1710 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1711 if (tsc_freq < 0 || *err) {
94a444b2 1712 error_setg(&local_err, "bad numerical value %s", val);
a91987c2 1713 goto out;
b862d1fe 1714 }
a91987c2 1715 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1716 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1717 &local_err);
72ac2e87 1718 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1719 char *err;
92067bf4 1720 const int min = 0xFFF;
c8f0f88e 1721 char num[32];
28f52cc0
VR		 1722 numvalue = strtoul(val, &err, 0);
1723 if (!*val || *err) {
94a444b2 1724 error_setg(&local_err, "bad numerical value %s", val);
a91987c2 1725 goto out;
28f52cc0 1726 }
92067bf4 1727 if (numvalue < min) {
94a444b2
AF		 1728 error_report("hv-spinlocks value shall always be >= 0x%x"
1729 ", fixup will be removed in future versions",
92067bf4
IM		 1730 min);
1731 numvalue = min;
1732 }
c8f0f88e 1733 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1734 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1735 } else {
94a444b2 1736 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1737 }
c6dc6f63 1738 } else {
258f5abe 1739 feat2prop(featurestr);
94a444b2 1740 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1741 }
94a444b2
AF		 1742 if (local_err) {
1743 error_propagate(errp, local_err);
a91987c2 1744 goto out;
c6dc6f63
AP		 1745 }
1746 featurestr = strtok(NULL, ",");
1747 }
0514ef2f
EH		 1748 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1749 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1750 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1751 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1752 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1753 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1754 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1755 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1756 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1757 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1758 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1759 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1760 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1761 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1762 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1763 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63 1764
a91987c2
IM		 1765out:
1766 return;
c6dc6f63
AP		 1767}
1768
1769/* generate a composite string into buf of all cpuid names in featureset
1770 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1771 * if flags, suppress names undefined in featureset.
1772 */
1773static void listflags(char *buf, int bufsize, uint32_t fbits,
1774 const char **featureset, uint32_t flags)
1775{
1776 const char **p = &featureset[31];
1777 char *q, *b, bit;
1778 int nc;
1779
1780 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1781 *buf = '\0';
1782 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1783 if (fbits & 1 << bit && (*p || !flags)) {
1784 if (*p)
1785 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1786 else
1787 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1788 if (bufsize <= nc) {
1789 if (b) {
1790 memcpy(b, "...", sizeof("..."));
1791 }
1792 return;
1793 }
1794 q += nc;
1795 bufsize -= nc;
1796 }
1797}
1798
e916cbf8
PM		 1799/* generate CPU information. */
1800void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1801{
9576de75 1802 X86CPUDefinition *def;
c6dc6f63 1803 char buf[256];
7fc9b714 1804 int i;
c6dc6f63 1805
7fc9b714
AF		 1806 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1807 def = &builtin_x86_defs[i];
c04321b3 1808 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1809 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1810 }
21ad7789
JK		 1811#ifdef CONFIG_KVM
1812 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1813 "KVM processor with all supported host features "
1814 "(only available in KVM mode)");
1815#endif
1816
6cdf8854 1817 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1818 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1819 FeatureWordInfo *fw = &feature_word_info[i];
1820
1821 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1822 (*cpu_fprintf)(f, " %s\n", buf);
1823 }
c6dc6f63
AP		 1824}
1825
76b64a7a 1826CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1827{
1828 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1829 X86CPUDefinition *def;
7fc9b714 1830 int i;
e3966126 1831
7fc9b714 1832 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1833 CpuDefinitionInfoList *entry;
1834 CpuDefinitionInfo *info;
1835
7fc9b714 1836 def = &builtin_x86_defs[i];
e3966126
AL		 1837 info = g_malloc0(sizeof(*info));
1838 info->name = g_strdup(def->name);
1839
1840 entry = g_malloc0(sizeof(*entry));
1841 entry->value = info;
1842 entry->next = cpu_list;
1843 cpu_list = entry;
1844 }
1845
1846 return cpu_list;
1847}
1848
bc74b7db
EH		 1849static void filter_features_for_kvm(X86CPU *cpu)
1850{
1851 CPUX86State *env = &cpu->env;
1852 KVMState *s = kvm_state;
bd87d2a2 1853 FeatureWord w;
bc74b7db 1854
bd87d2a2
EH		 1855 for (w = 0; w < FEATURE_WORDS; w++) {
1856 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1857 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1858 wi->cpuid_ecx,
1859 wi->cpuid_reg);
1860 uint32_t requested_features = env->features[w];
1861 env->features[w] &= host_feat;
1862 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1863 }
bc74b7db 1864}
bc74b7db 1865
d940ee9b 1866/* Load data from X86CPUDefinition
c080e30e 1867 */
d940ee9b 1868static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1869{
61dcd775 1870 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1871 const char *vendor;
1872 char host_vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63 1873
2d64255b
AF		 1874 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1875 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1876 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1877 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1878 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1879 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1880 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1881 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1882 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1883 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1884 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1885 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1886 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1887 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1888 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1889
2d64255b 1890 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
82beb536 1891
9576de75 1892 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1893 if (kvm_enabled()) {
5fcca9ff
EH		 1894 FeatureWord w;
1895 for (w = 0; w < FEATURE_WORDS; w++) {
1896 env->features[w] |= kvm_default_features[w];
1897 }
82beb536 1898 }
5fcca9ff 1899
82beb536 1900 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1901
1902 /* sysenter isn't supported in compatibility mode on AMD,
1903 * syscall isn't supported in compatibility mode on Intel.
1904 * Normally we advertise the actual CPU vendor, but you can
1905 * override this using the 'vendor' property if you want to use
1906 * KVM's sysenter/syscall emulation in compatibility mode and
1907 * when doing cross vendor migration
1908 */
74f54bc4 1909 vendor = def->vendor;
7c08db30
EH		 1910 if (kvm_enabled()) {
1911 uint32_t ebx = 0, ecx = 0, edx = 0;
1912 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1913 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1914 vendor = host_vendor;
1915 }
1916
1917 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1918
c6dc6f63
AP		 1919}
1920
62fc403f
IM		 1921X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1922 Error **errp)
5c3c6a68 1923{
2d64255b 1924 X86CPU *cpu = NULL;
d940ee9b 1925 X86CPUClass *xcc;
500050d1 1926 ObjectClass *oc;
2d64255b
AF		 1927 gchar **model_pieces;
1928 char *name, *features;
5c3c6a68
AF		 1929 Error *error = NULL;
1930
2d64255b
AF		 1931 model_pieces = g_strsplit(cpu_model, ",", 2);
1932 if (!model_pieces[0]) {
1933 error_setg(&error, "Invalid/empty CPU model name");
1934 goto out;
1935 }
1936 name = model_pieces[0];
1937 features = model_pieces[1];
1938
500050d1
AF		 1939 oc = x86_cpu_class_by_name(name);
1940 if (oc == NULL) {
1941 error_setg(&error, "Unable to find CPU definition: %s", name);
1942 goto out;
1943 }
d940ee9b
EH		 1944 xcc = X86_CPU_CLASS(oc);
1945
1946 if (xcc->kvm_required && !kvm_enabled()) {
1947 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 1948 goto out;
1949 }
1950
d940ee9b
EH		 1951 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1952
62fc403f
IM		 1953#ifndef CONFIG_USER_ONLY
1954 if (icc_bridge == NULL) {
1955 error_setg(&error, "Invalid icc-bridge value");
1956 goto out;
1957 }
1958 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1959 object_unref(OBJECT(cpu));
1960#endif
5c3c6a68 1961
94a444b2 1962 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 1963 if (error) {
1964 goto out;
5c3c6a68
AF		 1965 }
1966
7f833247 1967out:
cd7b87ff
AF		 1968 if (error != NULL) {
1969 error_propagate(errp, error);
500050d1
AF		 1970 if (cpu) {
1971 object_unref(OBJECT(cpu));
1972 cpu = NULL;
1973 }
cd7b87ff 1974 }
7f833247
IM		 1975 g_strfreev(model_pieces);
1976 return cpu;
1977}
1978
1979X86CPU *cpu_x86_init(const char *cpu_model)
1980{
1981 Error *error = NULL;
1982 X86CPU *cpu;
1983
62fc403f 1984 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1985 if (error) {
2d64255b
AF		 1986 goto out;
1987 }
1988
7f833247
IM		 1989 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1990
2d64255b 1991out:
2d64255b 1992 if (error) {
4a44d85e 1993 error_report("%s", error_get_pretty(error));
5c3c6a68 1994 error_free(error);
2d64255b
AF		 1995 if (cpu != NULL) {
1996 object_unref(OBJECT(cpu));
1997 cpu = NULL;
1998 }
5c3c6a68
AF		 1999 }
2000 return cpu;
2001}
2002
d940ee9b
EH		 2003static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2004{
2005 X86CPUDefinition *cpudef = data;
2006 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2007
2008 xcc->cpu_def = cpudef;
2009}
2010
2011static void x86_register_cpudef_type(X86CPUDefinition *def)
2012{
2013 char *typename = x86_cpu_type_name(def->name);
2014 TypeInfo ti = {
2015 .name = typename,
2016 .parent = TYPE_X86_CPU,
2017 .class_init = x86_cpu_cpudef_class_init,
2018 .class_data = def,
2019 };
2020
2021 type_register(&ti);
2022 g_free(typename);
2023}
2024
c6dc6f63 2025#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2026
0e26b7b8
BS		 2027void cpu_clear_apic_feature(CPUX86State *env)
2028{
0514ef2f 2029 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2030}
2031
c6dc6f63
AP		 2032#endif /* !CONFIG_USER_ONLY */
2033
c04321b3 2034/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2035 */
2036void x86_cpudef_setup(void)
2037{
93bfef4c
CV		 2038 int i, j;
2039 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2040
2041 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2042 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2043
2044 /* Look for specific "cpudef" models that */
09faecf2 2045 /* have the QEMU version in .model_id */
93bfef4c 2046 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2047 if (strcmp(model_with_versions[j], def->name) == 0) {
2048 pstrcpy(def->model_id, sizeof(def->model_id),
2049 "QEMU Virtual CPU version ");
2050 pstrcat(def->model_id, sizeof(def->model_id),
2051 qemu_get_version());
93bfef4c
CV		 2052 break;
2053 }
2054 }
c6dc6f63 2055 }
c6dc6f63
AP		 2056}
2057
c6dc6f63
AP		 2058static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2059 uint32_t *ecx, uint32_t *edx)
2060{
2061 *ebx = env->cpuid_vendor1;
2062 *edx = env->cpuid_vendor2;
2063 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2064}
2065
2066void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2067 uint32_t *eax, uint32_t *ebx,
2068 uint32_t *ecx, uint32_t *edx)
2069{
a60f24b5
AF		 2070 X86CPU *cpu = x86_env_get_cpu(env);
2071 CPUState *cs = CPU(cpu);
2072
c6dc6f63
AP		 2073 /* test if maximum index reached */
2074 if (index & 0x80000000) {
b3baa152
BW		 2075 if (index > env->cpuid_xlevel) {
2076 if (env->cpuid_xlevel2 > 0) {
2077 /* Handle the Centaur's CPUID instruction. */
2078 if (index > env->cpuid_xlevel2) {
2079 index = env->cpuid_xlevel2;
2080 } else if (index < 0xC0000000) {
2081 index = env->cpuid_xlevel;
2082 }
2083 } else {
57f26ae7
EH		 2084 /* Intel documentation states that invalid EAX input will
2085 * return the same information as EAX=cpuid_level
2086 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2087 */
2088 index = env->cpuid_level;
b3baa152
BW		 2089 }
2090 }
c6dc6f63
AP		 2091 } else {
2092 if (index > env->cpuid_level)
2093 index = env->cpuid_level;
2094 }
2095
2096 switch(index) {
2097 case 0:
2098 *eax = env->cpuid_level;
2099 get_cpuid_vendor(env, ebx, ecx, edx);
2100 break;
2101 case 1:
2102 *eax = env->cpuid_version;
2103 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2104 *ecx = env->features[FEAT_1_ECX];
2105 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2106 if (cs->nr_cores * cs->nr_threads > 1) {
2107 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2108 *edx |= 1 << 28; /* HTT bit */
2109 }
2110 break;
2111 case 2:
2112 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2113 if (cpu->cache_info_passthrough) {
2114 host_cpuid(index, 0, eax, ebx, ecx, edx);
2115 break;
2116 }
5e891bf8 2117 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2118 *ebx = 0;
2119 *ecx = 0;
5e891bf8
EH		 2120 *edx = (L1D_DESCRIPTOR << 16) | \
2121 (L1I_DESCRIPTOR << 8) | \
2122 (L2_DESCRIPTOR);
c6dc6f63
AP		 2123 break;
2124 case 4:
2125 /* cache info: needed for Core compatibility */
787aaf57
BC		 2126 if (cpu->cache_info_passthrough) {
2127 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2128 *eax &= ~0xFC000000;
c6dc6f63 2129 } else {
2f7a21c4 2130 *eax = 0;
76c2975a 2131 switch (count) {
c6dc6f63 2132 case 0: /* L1 dcache info */
5e891bf8
EH		 2133 *eax |= CPUID_4_TYPE_DCACHE | \
2134 CPUID_4_LEVEL(1) | \
2135 CPUID_4_SELF_INIT_LEVEL;
2136 *ebx = (L1D_LINE_SIZE - 1) | \
2137 ((L1D_PARTITIONS - 1) << 12) | \
2138 ((L1D_ASSOCIATIVITY - 1) << 22);
2139 *ecx = L1D_SETS - 1;
2140 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2141 break;
2142 case 1: /* L1 icache info */
5e891bf8
EH		 2143 *eax |= CPUID_4_TYPE_ICACHE | \
2144 CPUID_4_LEVEL(1) | \
2145 CPUID_4_SELF_INIT_LEVEL;
2146 *ebx = (L1I_LINE_SIZE - 1) | \
2147 ((L1I_PARTITIONS - 1) << 12) | \
2148 ((L1I_ASSOCIATIVITY - 1) << 22);
2149 *ecx = L1I_SETS - 1;
2150 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2151 break;
2152 case 2: /* L2 cache info */
5e891bf8
EH		 2153 *eax |= CPUID_4_TYPE_UNIFIED | \
2154 CPUID_4_LEVEL(2) | \
2155 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2156 if (cs->nr_threads > 1) {
2157 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2158 }
5e891bf8
EH		 2159 *ebx = (L2_LINE_SIZE - 1) | \
2160 ((L2_PARTITIONS - 1) << 12) | \
2161 ((L2_ASSOCIATIVITY - 1) << 22);
2162 *ecx = L2_SETS - 1;
2163 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2164 break;
2165 default: /* end of info */
2166 *eax = 0;
2167 *ebx = 0;
2168 *ecx = 0;
2169 *edx = 0;
2170 break;
76c2975a
PB		 2171 }
2172 }
2173
2174 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2175 if ((*eax & 31) && cs->nr_cores > 1) {
2176 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2177 }
2178 break;
2179 case 5:
2180 /* mwait info: needed for Core compatibility */
2181 *eax = 0; /* Smallest monitor-line size in bytes */
2182 *ebx = 0; /* Largest monitor-line size in bytes */
2183 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2184 *edx = 0;
2185 break;
2186 case 6:
2187 /* Thermal and Power Leaf */
2188 *eax = 0;
2189 *ebx = 0;
2190 *ecx = 0;
2191 *edx = 0;
2192 break;
f7911686 2193 case 7:
13526728
EH		 2194 /* Structured Extended Feature Flags Enumeration Leaf */
2195 if (count == 0) {
2196 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2197 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2198 *ecx = 0; /* Reserved */
2199 *edx = 0; /* Reserved */
f7911686
YW		 2200 } else {
2201 *eax = 0;
2202 *ebx = 0;
2203 *ecx = 0;
2204 *edx = 0;
2205 }
2206 break;
c6dc6f63
AP		 2207 case 9:
2208 /* Direct Cache Access Information Leaf */
2209 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2210 *ebx = 0;
2211 *ecx = 0;
2212 *edx = 0;
2213 break;
2214 case 0xA:
2215 /* Architectural Performance Monitoring Leaf */
9337e3b6 2216 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2217 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2218
2219 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2220 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2221 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2222 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2223 } else {
2224 *eax = 0;
2225 *ebx = 0;
2226 *ecx = 0;
2227 *edx = 0;
2228 }
c6dc6f63 2229 break;
2560f19f
PB		 2230 case 0xD: {
2231 KVMState *s = cs->kvm_state;
2232 uint64_t kvm_mask;
2233 int i;
2234
51e49430 2235 /* Processor Extended State */
2560f19f
PB		 2236 *eax = 0;
2237 *ebx = 0;
2238 *ecx = 0;
2239 *edx = 0;
2240 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2241 break;
2242 }
2560f19f
PB		 2243 kvm_mask =
2244 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2245 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2246
2560f19f
PB		 2247 if (count == 0) {
2248 *ecx = 0x240;
2249 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2250 const ExtSaveArea *esa = &ext_save_areas[i];
2251 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2252 (kvm_mask & (1 << i)) != 0) {
2253 if (i < 32) {
2254 *eax |= 1 << i;
2255 } else {
2256 *edx |= 1 << (i - 32);
2257 }
2258 *ecx = MAX(*ecx, esa->offset + esa->size);
2259 }
2260 }
2261 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2262 *ebx = *ecx;
2263 } else if (count == 1) {
2264 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2265 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2266 const ExtSaveArea *esa = &ext_save_areas[count];
2267 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2268 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2269 *eax = esa->size;
2270 *ebx = esa->offset;
2560f19f 2271 }
51e49430
SY		 2272 }
2273 break;
2560f19f 2274 }
c6dc6f63
AP		 2275 case 0x80000000:
2276 *eax = env->cpuid_xlevel;
2277 *ebx = env->cpuid_vendor1;
2278 *edx = env->cpuid_vendor2;
2279 *ecx = env->cpuid_vendor3;
2280 break;
2281 case 0x80000001:
2282 *eax = env->cpuid_version;
2283 *ebx = 0;
0514ef2f
EH		 2284 *ecx = env->features[FEAT_8000_0001_ECX];
2285 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2286
2287 /* The Linux kernel checks for the CMPLegacy bit and
2288 * discards multiple thread information if it is set.
2289 * So dont set it here for Intel to make Linux guests happy.
2290 */
ce3960eb 2291 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2292 uint32_t tebx, tecx, tedx;
2293 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2294 if (tebx != CPUID_VENDOR_INTEL_1 ||
2295 tedx != CPUID_VENDOR_INTEL_2 ||
2296 tecx != CPUID_VENDOR_INTEL_3) {
2297 *ecx |= 1 << 1; /* CmpLegacy bit */
2298 }
2299 }
c6dc6f63
AP		 2300 break;
2301 case 0x80000002:
2302 case 0x80000003:
2303 case 0x80000004:
2304 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2305 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2306 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2307 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2308 break;
2309 case 0x80000005:
2310 /* cache info (L1 cache) */
787aaf57
BC		 2311 if (cpu->cache_info_passthrough) {
2312 host_cpuid(index, 0, eax, ebx, ecx, edx);
2313 break;
2314 }
5e891bf8
EH		 2315 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2316 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2317 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2318 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2319 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2320 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2321 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2322 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2323 break;
2324 case 0x80000006:
2325 /* cache info (L2 cache) */
787aaf57
BC		 2326 if (cpu->cache_info_passthrough) {
2327 host_cpuid(index, 0, eax, ebx, ecx, edx);
2328 break;
2329 }
5e891bf8
EH		 2330 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2331 (L2_DTLB_2M_ENTRIES << 16) | \
2332 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2333 (L2_ITLB_2M_ENTRIES);
2334 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2335 (L2_DTLB_4K_ENTRIES << 16) | \
2336 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2337 (L2_ITLB_4K_ENTRIES);
2338 *ecx = (L2_SIZE_KB_AMD << 16) | \
2339 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2340 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2341 *edx = ((L3_SIZE_KB/512) << 18) | \
2342 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2343 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2344 break;
2345 case 0x80000008:
2346 /* virtual & phys address size in low 2 bytes. */
2347/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2348 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2349 /* 64 bit processor */
2350/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2351 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2352 } else {
0514ef2f 2353 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2354 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2355 } else {
c6dc6f63 2356 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2357 }
c6dc6f63
AP		 2358 }
2359 *ebx = 0;
2360 *ecx = 0;
2361 *edx = 0;
ce3960eb
AF		 2362 if (cs->nr_cores * cs->nr_threads > 1) {
2363 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2364 }
2365 break;
2366 case 0x8000000A:
0514ef2f 2367 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2368 *eax = 0x00000001; /* SVM Revision */
2369 *ebx = 0x00000010; /* nr of ASIDs */
2370 *ecx = 0;
0514ef2f 2371 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2372 } else {
2373 *eax = 0;
2374 *ebx = 0;
2375 *ecx = 0;
2376 *edx = 0;
2377 }
c6dc6f63 2378 break;
b3baa152
BW		 2379 case 0xC0000000:
2380 *eax = env->cpuid_xlevel2;
2381 *ebx = 0;
2382 *ecx = 0;
2383 *edx = 0;
2384 break;
2385 case 0xC0000001:
2386 /* Support for VIA CPU's CPUID instruction */
2387 *eax = env->cpuid_version;
2388 *ebx = 0;
2389 *ecx = 0;
0514ef2f 2390 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2391 break;
2392 case 0xC0000002:
2393 case 0xC0000003:
2394 case 0xC0000004:
2395 /* Reserved for the future, and now filled with zero */
2396 *eax = 0;
2397 *ebx = 0;
2398 *ecx = 0;
2399 *edx = 0;
2400 break;
c6dc6f63
AP		 2401 default:
2402 /* reserved values: zero */
2403 *eax = 0;
2404 *ebx = 0;
2405 *ecx = 0;
2406 *edx = 0;
2407 break;
2408 }
2409}
5fd2087a
AF		 2410
2411/* CPUClass::reset() */
2412static void x86_cpu_reset(CPUState *s)
2413{
2414 X86CPU *cpu = X86_CPU(s);
2415 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2416 CPUX86State *env = &cpu->env;
c1958aea
AF		 2417 int i;
2418
5fd2087a
AF		 2419 xcc->parent_reset(s);
2420
c1958aea 2421
f0c3c505 2422 memset(env, 0, offsetof(CPUX86State, pat));
c1958aea 2423
00c8cb0a 2424 tlb_flush(s, 1);
c1958aea
AF		 2425
2426 env->old_exception = -1;
2427
2428 /* init to reset state */
2429
2430#ifdef CONFIG_SOFTMMU
2431 env->hflags |= HF_SOFTMMU_MASK;
2432#endif
2433 env->hflags2 |= HF2_GIF_MASK;
2434
2435 cpu_x86_update_cr0(env, 0x60000010);
2436 env->a20_mask = ~0x0;
2437 env->smbase = 0x30000;
2438
2439 env->idt.limit = 0xffff;
2440 env->gdt.limit = 0xffff;
2441 env->ldt.limit = 0xffff;
2442 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2443 env->tr.limit = 0xffff;
2444 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2445
2446 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2447 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2448 DESC_R_MASK | DESC_A_MASK);
2449 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2450 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2451 DESC_A_MASK);
2452 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2453 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2454 DESC_A_MASK);
2455 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2456 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2457 DESC_A_MASK);
2458 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2459 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2460 DESC_A_MASK);
2461 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2462 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2463 DESC_A_MASK);
2464
2465 env->eip = 0xfff0;
2466 env->regs[R_EDX] = env->cpuid_version;
2467
2468 env->eflags = 0x2;
2469
2470 /* FPU init */
2471 for (i = 0; i < 8; i++) {
2472 env->fptags[i] = 1;
2473 }
2474 env->fpuc = 0x37f;
2475
2476 env->mxcsr = 0x1f80;
c74f41bb 2477 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2478
2479 env->pat = 0x0007040600070406ULL;
2480 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2481
2482 memset(env->dr, 0, sizeof(env->dr));
2483 env->dr[6] = DR6_FIXED_1;
2484 env->dr[7] = DR7_FIXED_1;
b3310ab3 2485 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2486 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2487
0522604b
FLVC		 2488 env->tsc_adjust = 0;
2489 env->tsc = 0;
2490
dd673288
IM		 2491#if !defined(CONFIG_USER_ONLY)
2492 /* We hard-wire the BSP to the first CPU. */
55e5c285 2493 if (s->cpu_index == 0) {
02e51483 2494 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2495 }
2496
259186a7 2497 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2498
2499 if (kvm_enabled()) {
2500 kvm_arch_reset_vcpu(cpu);
2501 }
dd673288 2502#endif
5fd2087a
AF		 2503}
2504
dd673288
IM		 2505#ifndef CONFIG_USER_ONLY
2506bool cpu_is_bsp(X86CPU *cpu)
2507{
02e51483 2508 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2509}
65dee380
IM		 2510
2511/* TODO: remove me, when reset over QOM tree is implemented */
2512static void x86_cpu_machine_reset_cb(void *opaque)
2513{
2514 X86CPU *cpu = opaque;
2515 cpu_reset(CPU(cpu));
2516}
dd673288
IM		 2517#endif
2518
de024815
AF		 2519static void mce_init(X86CPU *cpu)
2520{
2521 CPUX86State *cenv = &cpu->env;
2522 unsigned int bank;
2523
2524 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2525 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2526 (CPUID_MCE | CPUID_MCA)) {
2527 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2528 cenv->mcg_ctl = ~(uint64_t)0;
2529 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2530 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2531 }
2532 }
2533}
2534
bdeec802 2535#ifndef CONFIG_USER_ONLY
d3c64d6a 2536static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2537{
bdeec802 2538 CPUX86State *env = &cpu->env;
53a89e26 2539 DeviceState *dev = DEVICE(cpu);
449994eb 2540 APICCommonState *apic;
bdeec802
IM		 2541 const char *apic_type = "apic";
2542
2543 if (kvm_irqchip_in_kernel()) {
2544 apic_type = "kvm-apic";
2545 } else if (xen_enabled()) {
2546 apic_type = "xen-apic";
2547 }
2548
02e51483
CF		 2549 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2550 if (cpu->apic_state == NULL) {
bdeec802
IM		 2551 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2552 return;
2553 }
2554
2555 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2556 OBJECT(cpu->apic_state), NULL);
2557 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2558 /* TODO: convert to link<> */
02e51483 2559 apic = APIC_COMMON(cpu->apic_state);
60671e58 2560 apic->cpu = cpu;
d3c64d6a
IM		 2561}
2562
2563static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2564{
02e51483 2565 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2566 return;
2567 }
bdeec802 2568
02e51483 2569 if (qdev_init(cpu->apic_state)) {
bdeec802 2570 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2571 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2572 return;
2573 }
bdeec802 2574}
d3c64d6a
IM		 2575#else
2576static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2577{
2578}
bdeec802
IM		 2579#endif
2580
2b6f294c 2581static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2582{
14a10fc3 2583 CPUState *cs = CPU(dev);
2b6f294c
AF		 2584 X86CPU *cpu = X86_CPU(dev);
2585 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2586 CPUX86State *env = &cpu->env;
2b6f294c 2587 Error *local_err = NULL;
b34d12d1 2588
0514ef2f 2589 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2590 env->cpuid_level = 7;
2591 }
7a059953 2592
9b15cd9e
IM		 2593 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2594 * CPUID[1].EDX.
2595 */
2596 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2597 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2598 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2599 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2600 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2601 & CPUID_EXT2_AMD_ALIASES);
2602 }
2603
4586f157 2604 if (!kvm_enabled()) {
0514ef2f
EH		 2605 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2606 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2607 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2608#ifdef TARGET_X86_64
2609 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2610#endif
2611 );
0514ef2f
EH		 2612 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2613 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2614 } else {
f0b9b111 2615 KVMState *s = kvm_state;
912ffc47 2616 if ((cpu->check_cpuid || cpu->enforce_cpuid)
f0b9b111 2617 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2618 error_setg(&local_err,
2619 "Host's CPU doesn't support requested features");
2620 goto out;
5ec01c2e 2621 }
a509d632 2622 filter_features_for_kvm(cpu);
4586f157
IM		 2623 }
2624
65dee380
IM		 2625#ifndef CONFIG_USER_ONLY
2626 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2627
0514ef2f 2628 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2629 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2630 if (local_err != NULL) {
4dc1f449 2631 goto out;
bdeec802
IM		 2632 }
2633 }
65dee380
IM		 2634#endif
2635
7a059953 2636 mce_init(cpu);
14a10fc3 2637 qemu_init_vcpu(cs);
d3c64d6a
IM		 2638
2639 x86_cpu_apic_realize(cpu, &local_err);
2640 if (local_err != NULL) {
2641 goto out;
2642 }
14a10fc3 2643 cpu_reset(cs);
2b6f294c 2644
4dc1f449
IM		 2645 xcc->parent_realize(dev, &local_err);
2646out:
2647 if (local_err != NULL) {
2648 error_propagate(errp, local_err);
2649 return;
2650 }
7a059953
AF		 2651}
2652
8932cfdf
EH		 2653/* Enables contiguous-apic-ID mode, for compatibility */
2654static bool compat_apic_id_mode;
2655
2656void enable_compat_apic_id_mode(void)
2657{
2658 compat_apic_id_mode = true;
2659}
2660
cb41bad3
EH		 2661/* Calculates initial APIC ID for a specific CPU index
2662 *
2663 * Currently we need to be able to calculate the APIC ID from the CPU index
2664 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2665 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2666 * all CPUs up to max_cpus.
2667 */
2668uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2669{
8932cfdf
EH		 2670 uint32_t correct_id;
2671 static bool warned;
2672
2673 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2674 if (compat_apic_id_mode) {
2675 if (cpu_index != correct_id && !warned) {
2676 error_report("APIC IDs set in compatibility mode, "
2677 "CPU topology won't match the configuration");
2678 warned = true;
2679 }
2680 return cpu_index;
2681 } else {
2682 return correct_id;
2683 }
cb41bad3
EH		 2684}
2685
de024815
AF		 2686static void x86_cpu_initfn(Object *obj)
2687{
55e5c285 2688 CPUState *cs = CPU(obj);
de024815 2689 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2690 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2691 CPUX86State *env = &cpu->env;
d65e9815 2692 static int inited;
de024815 2693
c05efcb1 2694 cs->env_ptr = env;
de024815 2695 cpu_exec_init(env);
71ad61d3
AF		 2696
2697 object_property_add(obj, "family", "int",
95b8519d 2698 x86_cpuid_version_get_family,
71ad61d3 2699 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2700 object_property_add(obj, "model", "int",
67e30c83 2701 x86_cpuid_version_get_model,
c5291a4f 2702 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2703 object_property_add(obj, "stepping", "int",
35112e41 2704 x86_cpuid_version_get_stepping,
036e2222 2705 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2706 object_property_add(obj, "level", "int",
2707 x86_cpuid_get_level,
2708 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2709 object_property_add(obj, "xlevel", "int",
2710 x86_cpuid_get_xlevel,
2711 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2712 object_property_add_str(obj, "vendor",
2713 x86_cpuid_get_vendor,
2714 x86_cpuid_set_vendor, NULL);
938d4c25 2715 object_property_add_str(obj, "model-id",
63e886eb 2716 x86_cpuid_get_model_id,
938d4c25 2717 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2718 object_property_add(obj, "tsc-frequency", "int",
2719 x86_cpuid_get_tsc_freq,
2720 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2721 object_property_add(obj, "apic-id", "int",
2722 x86_cpuid_get_apic_id,
2723 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2724 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2725 x86_cpu_get_feature_words,
7e5292b5
EH		 2726 NULL, NULL, (void *)env->features, NULL);
2727 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2728 x86_cpu_get_feature_words,
2729 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2730
92067bf4 2731 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2732 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2733
d940ee9b
EH		 2734 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2735
d65e9815
IM		 2736 /* init various static tables used in TCG mode */
2737 if (tcg_enabled() && !inited) {
2738 inited = 1;
2739 optimize_flags_init();
2740#ifndef CONFIG_USER_ONLY
2741 cpu_set_debug_excp_handler(breakpoint_handler);
2742#endif
2743 }
de024815
AF		 2744}
2745
997395d3
IM		 2746static int64_t x86_cpu_get_arch_id(CPUState *cs)
2747{
2748 X86CPU *cpu = X86_CPU(cs);
2749 CPUX86State *env = &cpu->env;
2750
2751 return env->cpuid_apic_id;
2752}
2753
444d5590
AF		 2754static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2755{
2756 X86CPU *cpu = X86_CPU(cs);
2757
2758 return cpu->env.cr[0] & CR0_PG_MASK;
2759}
2760
f45748f1
AF		 2761static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2762{
2763 X86CPU *cpu = X86_CPU(cs);
2764
2765 cpu->env.eip = value;
2766}
2767
bdf7ae5b
AF		 2768static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2769{
2770 X86CPU *cpu = X86_CPU(cs);
2771
2772 cpu->env.eip = tb->pc - tb->cs_base;
2773}
2774
8c2e1b00
AF		 2775static bool x86_cpu_has_work(CPUState *cs)
2776{
2777 X86CPU *cpu = X86_CPU(cs);
2778 CPUX86State *env = &cpu->env;
2779
2780 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2781 CPU_INTERRUPT_POLL)) &&
2782 (env->eflags & IF_MASK)) ||
2783 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2784 CPU_INTERRUPT_INIT |
2785 CPU_INTERRUPT_SIPI |
2786 CPU_INTERRUPT_MCE));
2787}
2788
9337e3b6
EH		 2789static Property x86_cpu_properties[] = {
2790 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2791 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2792 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2793 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2794 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2795 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2796 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
9337e3b6
EH		 2797 DEFINE_PROP_END_OF_LIST()
2798};
2799
5fd2087a
AF		 2800static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2801{
2802 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2803 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2804 DeviceClass *dc = DEVICE_CLASS(oc);
2805
2806 xcc->parent_realize = dc->realize;
2807 dc->realize = x86_cpu_realizefn;
62fc403f 2808 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2809 dc->props = x86_cpu_properties;
5fd2087a
AF		 2810
2811 xcc->parent_reset = cc->reset;
2812 cc->reset = x86_cpu_reset;
91b1df8c 2813 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2814
500050d1 2815 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2816 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2817 cc->has_work = x86_cpu_has_work;
97a8ea5a 2818 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2819 cc->dump_state = x86_cpu_dump_state;
f45748f1 2820 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2821 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2822 cc->gdb_read_register = x86_cpu_gdb_read_register;
2823 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2824 cc->get_arch_id = x86_cpu_get_arch_id;
2825 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2826#ifdef CONFIG_USER_ONLY
2827 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2828#else
a23bbfda 2829 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2830 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2831 cc->write_elf64_note = x86_cpu_write_elf64_note;
2832 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2833 cc->write_elf32_note = x86_cpu_write_elf32_note;
2834 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2835 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2836#endif
a0e372f0 2837 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2838}
2839
2840static const TypeInfo x86_cpu_type_info = {
2841 .name = TYPE_X86_CPU,
2842 .parent = TYPE_CPU,
2843 .instance_size = sizeof(X86CPU),
de024815 2844 .instance_init = x86_cpu_initfn,
d940ee9b 2845 .abstract = true,
5fd2087a
AF		 2846 .class_size = sizeof(X86CPUClass),
2847 .class_init = x86_cpu_common_class_init,
2848};
2849
2850static void x86_cpu_register_types(void)
2851{
d940ee9b
EH		 2852 int i;
2853
5fd2087a 2854 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2855 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2856 x86_register_cpudef_type(&builtin_x86_defs[i]);
2857 }
2858#ifdef CONFIG_KVM
2859 type_register_static(&host_x86_cpu_type_info);
2860#endif
5fd2087a
AF		 2861}
2862
2863type_init(x86_cpu_register_types)
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