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target-i386: kvm: Don't enable MONITOR by default on any CPU model
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
5ef57876
EH		 266typedef struct FeatureWordInfo {
267 const char **feat_names;
04d104b6
EH		 268 uint32_t cpuid_eax; /* Input EAX for CPUID */
269 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
270 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
271 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 272} FeatureWordInfo;
273
274static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 275 [FEAT_1_EDX] = {
276 .feat_names = feature_name,
277 .cpuid_eax = 1, .cpuid_reg = R_EDX,
278 },
279 [FEAT_1_ECX] = {
280 .feat_names = ext_feature_name,
281 .cpuid_eax = 1, .cpuid_reg = R_ECX,
282 },
283 [FEAT_8000_0001_EDX] = {
284 .feat_names = ext2_feature_name,
285 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
286 },
287 [FEAT_8000_0001_ECX] = {
288 .feat_names = ext3_feature_name,
289 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
290 },
89e49c8b
EH		 291 [FEAT_C000_0001_EDX] = {
292 .feat_names = ext4_feature_name,
293 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
294 },
bffd67b0
EH		 295 [FEAT_KVM] = {
296 .feat_names = kvm_feature_name,
297 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
298 },
299 [FEAT_SVM] = {
300 .feat_names = svm_feature_name,
301 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
302 },
303 [FEAT_7_0_EBX] = {
304 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 305 .cpuid_eax = 7,
306 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
307 .cpuid_reg = R_EBX,
bffd67b0 308 },
5ef57876
EH		 309};
310
8e8aba50
EH		 311typedef struct X86RegisterInfo32 {
312 /* Name of register */
313 const char *name;
314 /* QAPI enum value register */
315 X86CPURegister32 qapi_enum;
316} X86RegisterInfo32;
317
318#define REGISTER(reg) \
5d371f41 319 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 320static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 321 REGISTER(EAX),
322 REGISTER(ECX),
323 REGISTER(EDX),
324 REGISTER(EBX),
325 REGISTER(ESP),
326 REGISTER(EBP),
327 REGISTER(ESI),
328 REGISTER(EDI),
329};
330#undef REGISTER
331
2560f19f
PB		 332typedef struct ExtSaveArea {
333 uint32_t feature, bits;
334 uint32_t offset, size;
335} ExtSaveArea;
336
337static const ExtSaveArea ext_save_areas[] = {
338 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 339 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 340 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
341 .offset = 0x3c0, .size = 0x40 },
342 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 343 .offset = 0x400, .size = 0x40 },
2560f19f 344};
8e8aba50 345
8b4beddc
EH		 346const char *get_register_name_32(unsigned int reg)
347{
31ccdde2 348 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 349 return NULL;
350 }
8e8aba50 351 return x86_reg_info_32[reg].name;
8b4beddc
EH		 352}
353
c6dc6f63
AP		 354/* collects per-function cpuid data
355 */
356typedef struct model_features_t {
357 uint32_t *guest_feat;
358 uint32_t *host_feat;
bffd67b0 359 FeatureWord feat_word;
8b4beddc 360} model_features_t;
c6dc6f63 361
5fcca9ff
EH		 362/* KVM-specific features that are automatically added to all CPU models
363 * when KVM is enabled.
364 */
365static uint32_t kvm_default_features[FEATURE_WORDS] = {
366 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 367 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 368 (1 << KVM_FEATURE_CLOCKSOURCE2) |
369 (1 << KVM_FEATURE_ASYNC_PF) |
370 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 371 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 372 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 373 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 374};
dc59944b 375
136a7e9a
EH		 376/* Features that are not added by default to any CPU model when KVM is enabled.
377 */
378static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
379 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
380};
381
8fb4f821 382void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 383{
8fb4f821 384 kvm_default_features[w] &= ~features;
dc59944b
MT		 385}
386
bb44e0d1
JK		 387void host_cpuid(uint32_t function, uint32_t count,
388 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 389{
a1fd24af
AL		 390 uint32_t vec[4];
391
392#ifdef __x86_64__
393 asm volatile("cpuid"
394 : "=a"(vec[0]), "=b"(vec[1]),
395 "=c"(vec[2]), "=d"(vec[3])
396 : "0"(function), "c"(count) : "cc");
c1f41226 397#elif defined(__i386__)
a1fd24af
AL		 398 asm volatile("pusha \n\t"
399 "cpuid \n\t"
400 "mov %%eax, 0(%2) \n\t"
401 "mov %%ebx, 4(%2) \n\t"
402 "mov %%ecx, 8(%2) \n\t"
403 "mov %%edx, 12(%2) \n\t"
404 "popa"
405 : : "a"(function), "c"(count), "S"(vec)
406 : "memory", "cc");
c1f41226
EH		 407#else
408 abort();
a1fd24af
AL		 409#endif
410
bdde476a 411 if (eax)
a1fd24af 412 *eax = vec[0];
bdde476a 413 if (ebx)
a1fd24af 414 *ebx = vec[1];
bdde476a 415 if (ecx)
a1fd24af 416 *ecx = vec[2];
bdde476a 417 if (edx)
a1fd24af 418 *edx = vec[3];
bdde476a 419}
c6dc6f63
AP		 420
421#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
422
423/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
424 * a substring. ex if !NULL points to the first char after a substring,
425 * otherwise the string is assumed to sized by a terminating nul.
426 * Return lexical ordering of *s1:*s2.
427 */
428static int sstrcmp(const char *s1, const char *e1, const char *s2,
429 const char *e2)
430{
431 for (;;) {
432 if (!*s1 || !*s2 || *s1 != *s2)
433 return (*s1 - *s2);
434 ++s1, ++s2;
435 if (s1 == e1 && s2 == e2)
436 return (0);
437 else if (s1 == e1)
438 return (*s2);
439 else if (s2 == e2)
440 return (*s1);
441 }
442}
443
444/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
445 * '|' delimited (possibly empty) strings in which case search for a match
446 * within the alternatives proceeds left to right. Return 0 for success,
447 * non-zero otherwise.
448 */
449static int altcmp(const char *s, const char *e, const char *altstr)
450{
451 const char *p, *q;
452
453 for (q = p = altstr; ; ) {
454 while (*p && *p != '|')
455 ++p;
456 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
457 return (0);
458 if (!*p)
459 return (1);
460 else
461 q = ++p;
462 }
463}
464
465/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 466 * *pval and return true, otherwise return false
c6dc6f63 467 */
e41e0fc6
JK		 468static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
469 const char **featureset)
c6dc6f63
AP		 470{
471 uint32_t mask;
472 const char **ppc;
e41e0fc6 473 bool found = false;
c6dc6f63 474
e41e0fc6 475 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 476 if (*ppc && !altcmp(s, e, *ppc)) {
477 *pval |= mask;
e41e0fc6 478 found = true;
c6dc6f63 479 }
e41e0fc6
JK		 480 }
481 return found;
c6dc6f63
AP		 482}
483
5ef57876
EH		 484static void add_flagname_to_bitmaps(const char *flagname,
485 FeatureWordArray words)
c6dc6f63 486{
5ef57876
EH		 487 FeatureWord w;
488 for (w = 0; w < FEATURE_WORDS; w++) {
489 FeatureWordInfo *wi = &feature_word_info[w];
490 if (wi->feat_names &&
491 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
492 break;
493 }
494 }
495 if (w == FEATURE_WORDS) {
496 fprintf(stderr, "CPU feature %s not found\n", flagname);
497 }
c6dc6f63
AP		 498}
499
d940ee9b
EH		 500/* CPU class name definitions: */
501
502#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
503#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
504
505/* Return type name for a given CPU model name
506 * Caller is responsible for freeing the returned string.
507 */
508static char *x86_cpu_type_name(const char *model_name)
509{
510 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
511}
512
500050d1
AF		 513static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
514{
d940ee9b
EH		 515 ObjectClass *oc;
516 char *typename;
517
500050d1
AF		 518 if (cpu_model == NULL) {
519 return NULL;
520 }
521
d940ee9b
EH		 522 typename = x86_cpu_type_name(cpu_model);
523 oc = object_class_by_name(typename);
524 g_free(typename);
525 return oc;
500050d1
AF		 526}
527
d940ee9b 528struct X86CPUDefinition {
c6dc6f63
AP		 529 const char *name;
530 uint32_t level;
90e4b0c3
EH		 531 uint32_t xlevel;
532 uint32_t xlevel2;
99b88a17
IM		 533 /* vendor is zero-terminated, 12 character ASCII string */
534 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 535 int family;
536 int model;
537 int stepping;
0514ef2f 538 FeatureWordArray features;
c6dc6f63 539 char model_id[48];
787aaf57 540 bool cache_info_passthrough;
d940ee9b 541};
c6dc6f63
AP		 542
543#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
544#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
545 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
546#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
547 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
548 CPUID_PSE36 | CPUID_FXSR)
549#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
550#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
551 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
552 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
553 CPUID_PAE | CPUID_SEP | CPUID_APIC)
554
551a2dec
AP		 555#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
556 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
557 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
558 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
559 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed 560 /* partly implemented:
de431a65 561 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
8560efed
AJ		 562 /* missing:
563 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
e71827bc
AJ		 564#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
565 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
566 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
d640045a 567 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
8560efed 568 /* missing:
e71827bc
AJ		 569 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
570 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
571 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
d640045a
AJ		 572 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
573 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
83f7dc28 574 CPUID_EXT_RDRAND */
60032ac0 575#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
551a2dec 576 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
77549a78 577 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB)
551a2dec
AP		 578#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
579 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 580#define TCG_SVM_FEATURES 0
7073fbad 581#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
cd7f97ca 582 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
111994ee 583 /* missing:
7073fbad
RH		 584 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
585 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
cd7f97ca 586 CPUID_7_0_EBX_RDSEED */
551a2dec 587
9576de75 588static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 589 {
590 .name = "qemu64",
591 .level = 4,
99b88a17 592 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 593 .family = 6,
f8e6a11a 594 .model = 6,
c6dc6f63 595 .stepping = 3,
0514ef2f 596 .features[FEAT_1_EDX] =
27861ecc 597 PPRO_FEATURES |
c6dc6f63 598 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 599 CPUID_PSE36,
0514ef2f 600 .features[FEAT_1_ECX] =
27861ecc 601 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 602 .features[FEAT_8000_0001_EDX] =
27861ecc 603 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 604 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 605 .features[FEAT_8000_0001_ECX] =
27861ecc 606 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 607 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
608 .xlevel = 0x8000000A,
c6dc6f63
AP		 609 },
610 {
611 .name = "phenom",
612 .level = 5,
99b88a17 613 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 614 .family = 16,
615 .model = 2,
616 .stepping = 3,
0514ef2f 617 .features[FEAT_1_EDX] =
27861ecc 618 PPRO_FEATURES |
c6dc6f63 619 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 620 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 621 .features[FEAT_1_ECX] =
27861ecc 622 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 623 CPUID_EXT_POPCNT,
0514ef2f 624 .features[FEAT_8000_0001_EDX] =
27861ecc 625 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 626 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
627 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 628 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 629 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
630 CPUID_EXT3_CR8LEG,
631 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
632 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 633 .features[FEAT_8000_0001_ECX] =
27861ecc 634 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 635 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 636 .features[FEAT_SVM] =
27861ecc 637 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 638 .xlevel = 0x8000001A,
639 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
640 },
641 {
642 .name = "core2duo",
643 .level = 10,
99b88a17 644 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 645 .family = 6,
646 .model = 15,
647 .stepping = 11,
0514ef2f 648 .features[FEAT_1_EDX] =
27861ecc 649 PPRO_FEATURES |
c6dc6f63 650 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 651 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
652 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 653 .features[FEAT_1_ECX] =
27861ecc 654 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 655 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
656 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 657 .features[FEAT_8000_0001_EDX] =
27861ecc 658 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 659 .features[FEAT_8000_0001_ECX] =
27861ecc 660 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 661 .xlevel = 0x80000008,
662 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
663 },
664 {
665 .name = "kvm64",
666 .level = 5,
99b88a17 667 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 668 .family = 15,
669 .model = 6,
670 .stepping = 1,
671 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 672 .features[FEAT_1_EDX] =
27861ecc 673 PPRO_FEATURES |
c6dc6f63
AP		 674 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
675 CPUID_PSE36,
676 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 677 .features[FEAT_1_ECX] =
27861ecc 678 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 679 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 680 .features[FEAT_8000_0001_EDX] =
27861ecc 681 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 682 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
683 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
684 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
685 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
686 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 687 .features[FEAT_8000_0001_ECX] =
27861ecc 688 0,
c6dc6f63
AP		 689 .xlevel = 0x80000008,
690 .model_id = "Common KVM processor"
691 },
c6dc6f63
AP		 692 {
693 .name = "qemu32",
694 .level = 4,
99b88a17 695 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 696 .family = 6,
f8e6a11a 697 .model = 6,
c6dc6f63 698 .stepping = 3,
0514ef2f 699 .features[FEAT_1_EDX] =
27861ecc 700 PPRO_FEATURES,
0514ef2f 701 .features[FEAT_1_ECX] =
27861ecc 702 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 703 .xlevel = 0x80000004,
c6dc6f63 704 },
eafaf1e5
AP		 705 {
706 .name = "kvm32",
707 .level = 5,
99b88a17 708 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 709 .family = 15,
710 .model = 6,
711 .stepping = 1,
0514ef2f 712 .features[FEAT_1_EDX] =
27861ecc 713 PPRO_FEATURES |
eafaf1e5 714 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 715 .features[FEAT_1_ECX] =
27861ecc 716 CPUID_EXT_SSE3,
0514ef2f 717 .features[FEAT_8000_0001_EDX] =
27861ecc 718 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 719 .features[FEAT_8000_0001_ECX] =
27861ecc 720 0,
eafaf1e5
AP		 721 .xlevel = 0x80000008,
722 .model_id = "Common 32-bit KVM processor"
723 },
c6dc6f63
AP		 724 {
725 .name = "coreduo",
726 .level = 10,
99b88a17 727 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 728 .family = 6,
729 .model = 14,
730 .stepping = 8,
0514ef2f 731 .features[FEAT_1_EDX] =
27861ecc 732 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 733 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
734 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 735 .features[FEAT_1_ECX] =
27861ecc 736 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 737 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 738 .features[FEAT_8000_0001_EDX] =
27861ecc 739 CPUID_EXT2_NX,
c6dc6f63
AP		 740 .xlevel = 0x80000008,
741 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
742 },
743 {
744 .name = "486",
58012d66 745 .level = 1,
99b88a17 746 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 747 .family = 4,
b2a856d9 748 .model = 8,
c6dc6f63 749 .stepping = 0,
0514ef2f 750 .features[FEAT_1_EDX] =
27861ecc 751 I486_FEATURES,
c6dc6f63
AP		 752 .xlevel = 0,
753 },
754 {
755 .name = "pentium",
756 .level = 1,
99b88a17 757 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 758 .family = 5,
759 .model = 4,
760 .stepping = 3,
0514ef2f 761 .features[FEAT_1_EDX] =
27861ecc 762 PENTIUM_FEATURES,
c6dc6f63
AP		 763 .xlevel = 0,
764 },
765 {
766 .name = "pentium2",
767 .level = 2,
99b88a17 768 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 769 .family = 6,
770 .model = 5,
771 .stepping = 2,
0514ef2f 772 .features[FEAT_1_EDX] =
27861ecc 773 PENTIUM2_FEATURES,
c6dc6f63
AP		 774 .xlevel = 0,
775 },
776 {
777 .name = "pentium3",
778 .level = 2,
99b88a17 779 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 780 .family = 6,
781 .model = 7,
782 .stepping = 3,
0514ef2f 783 .features[FEAT_1_EDX] =
27861ecc 784 PENTIUM3_FEATURES,
c6dc6f63
AP		 785 .xlevel = 0,
786 },
787 {
788 .name = "athlon",
789 .level = 2,
99b88a17 790 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 791 .family = 6,
792 .model = 2,
793 .stepping = 3,
0514ef2f 794 .features[FEAT_1_EDX] =
27861ecc 795 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 796 CPUID_MCA,
0514ef2f 797 .features[FEAT_8000_0001_EDX] =
27861ecc 798 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 799 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 800 .xlevel = 0x80000008,
c6dc6f63
AP		 801 },
802 {
803 .name = "n270",
804 /* original is on level 10 */
805 .level = 5,
99b88a17 806 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 807 .family = 6,
808 .model = 28,
809 .stepping = 2,
0514ef2f 810 .features[FEAT_1_EDX] =
27861ecc 811 PPRO_FEATURES |
8560efed
AJ		 812 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
813 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 814 /* Some CPUs got no CPUID_SEP */
0514ef2f 815 .features[FEAT_1_ECX] =
27861ecc 816 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 817 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
818 CPUID_EXT_MOVBE,
0514ef2f 819 .features[FEAT_8000_0001_EDX] =
27861ecc 820 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 821 CPUID_EXT2_NX,
0514ef2f 822 .features[FEAT_8000_0001_ECX] =
27861ecc 823 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 824 .xlevel = 0x8000000A,
825 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
826 },
3eca4642
EH		 827 {
828 .name = "Conroe",
6b11322e 829 .level = 4,
99b88a17 830 .vendor = CPUID_VENDOR_INTEL,
3eca4642 831 .family = 6,
ffce9ebb 832 .model = 15,
3eca4642 833 .stepping = 3,
0514ef2f 834 .features[FEAT_1_EDX] =
27861ecc 835 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 836 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
837 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
838 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
839 CPUID_DE | CPUID_FP87,
0514ef2f 840 .features[FEAT_1_ECX] =
27861ecc 841 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 842 .features[FEAT_8000_0001_EDX] =
27861ecc 843 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 844 .features[FEAT_8000_0001_ECX] =
27861ecc 845 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 846 .xlevel = 0x8000000A,
847 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
848 },
849 {
850 .name = "Penryn",
6b11322e 851 .level = 4,
99b88a17 852 .vendor = CPUID_VENDOR_INTEL,
3eca4642 853 .family = 6,
ffce9ebb 854 .model = 23,
3eca4642 855 .stepping = 3,
0514ef2f 856 .features[FEAT_1_EDX] =
27861ecc 857 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 858 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
859 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
860 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
861 CPUID_DE | CPUID_FP87,
0514ef2f 862 .features[FEAT_1_ECX] =
27861ecc 863 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 864 CPUID_EXT_SSE3,
0514ef2f 865 .features[FEAT_8000_0001_EDX] =
27861ecc 866 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 867 .features[FEAT_8000_0001_ECX] =
27861ecc 868 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 869 .xlevel = 0x8000000A,
870 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
871 },
872 {
873 .name = "Nehalem",
6b11322e 874 .level = 4,
99b88a17 875 .vendor = CPUID_VENDOR_INTEL,
3eca4642 876 .family = 6,
ffce9ebb 877 .model = 26,
3eca4642 878 .stepping = 3,
0514ef2f 879 .features[FEAT_1_EDX] =
27861ecc 880 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 881 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
882 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
883 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
884 CPUID_DE | CPUID_FP87,
0514ef2f 885 .features[FEAT_1_ECX] =
27861ecc 886 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 887 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 888 .features[FEAT_8000_0001_EDX] =
27861ecc 889 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 890 .features[FEAT_8000_0001_ECX] =
27861ecc 891 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 892 .xlevel = 0x8000000A,
893 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
894 },
895 {
896 .name = "Westmere",
897 .level = 11,
99b88a17 898 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 899 .family = 6,
900 .model = 44,
901 .stepping = 1,
0514ef2f 902 .features[FEAT_1_EDX] =
27861ecc 903 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 904 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
905 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
906 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
907 CPUID_DE | CPUID_FP87,
0514ef2f 908 .features[FEAT_1_ECX] =
27861ecc 909 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 910 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 911 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 912 .features[FEAT_8000_0001_EDX] =
27861ecc 913 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 914 .features[FEAT_8000_0001_ECX] =
27861ecc 915 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 916 .xlevel = 0x8000000A,
917 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
918 },
919 {
920 .name = "SandyBridge",
921 .level = 0xd,
99b88a17 922 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 923 .family = 6,
924 .model = 42,
925 .stepping = 1,
0514ef2f 926 .features[FEAT_1_EDX] =
27861ecc 927 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 928 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
929 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
930 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
931 CPUID_DE | CPUID_FP87,
0514ef2f 932 .features[FEAT_1_ECX] =
27861ecc 933 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 934 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
935 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
936 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
937 CPUID_EXT_SSE3,
0514ef2f 938 .features[FEAT_8000_0001_EDX] =
27861ecc 939 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 940 CPUID_EXT2_SYSCALL,
0514ef2f 941 .features[FEAT_8000_0001_ECX] =
27861ecc 942 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 943 .xlevel = 0x8000000A,
944 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
945 },
37507094
EH		 946 {
947 .name = "Haswell",
948 .level = 0xd,
99b88a17 949 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 950 .family = 6,
951 .model = 60,
952 .stepping = 1,
0514ef2f 953 .features[FEAT_1_EDX] =
27861ecc 954 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 955 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 956 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 957 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
958 CPUID_DE | CPUID_FP87,
0514ef2f 959 .features[FEAT_1_ECX] =
27861ecc 960 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 961 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
962 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
963 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
964 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
965 CPUID_EXT_PCID,
0514ef2f 966 .features[FEAT_8000_0001_EDX] =
27861ecc 967 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 968 CPUID_EXT2_SYSCALL,
0514ef2f 969 .features[FEAT_8000_0001_ECX] =
27861ecc 970 CPUID_EXT3_LAHF_LM,
0514ef2f 971 .features[FEAT_7_0_EBX] =
27861ecc 972 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 973 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
974 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
975 CPUID_7_0_EBX_RTM,
976 .xlevel = 0x8000000A,
977 .model_id = "Intel Core Processor (Haswell)",
978 },
3eca4642
EH		 979 {
980 .name = "Opteron_G1",
981 .level = 5,
99b88a17 982 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 983 .family = 15,
984 .model = 6,
985 .stepping = 1,
0514ef2f 986 .features[FEAT_1_EDX] =
27861ecc 987 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 988 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
989 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
990 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
991 CPUID_DE | CPUID_FP87,
0514ef2f 992 .features[FEAT_1_ECX] =
27861ecc 993 CPUID_EXT_SSE3,
0514ef2f 994 .features[FEAT_8000_0001_EDX] =
27861ecc 995 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 996 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
997 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
998 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
999 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1000 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1001 .xlevel = 0x80000008,
1002 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1003 },
1004 {
1005 .name = "Opteron_G2",
1006 .level = 5,
99b88a17 1007 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1008 .family = 15,
1009 .model = 6,
1010 .stepping = 1,
0514ef2f 1011 .features[FEAT_1_EDX] =
27861ecc 1012 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1013 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1014 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1015 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1016 CPUID_DE | CPUID_FP87,
0514ef2f 1017 .features[FEAT_1_ECX] =
27861ecc 1018 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1019 .features[FEAT_8000_0001_EDX] =
27861ecc 1020 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1021 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1022 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1023 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1024 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1025 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1026 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1027 .features[FEAT_8000_0001_ECX] =
27861ecc 1028 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1029 .xlevel = 0x80000008,
1030 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1031 },
1032 {
1033 .name = "Opteron_G3",
1034 .level = 5,
99b88a17 1035 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1036 .family = 15,
1037 .model = 6,
1038 .stepping = 1,
0514ef2f 1039 .features[FEAT_1_EDX] =
27861ecc 1040 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1041 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1042 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1043 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1044 CPUID_DE | CPUID_FP87,
0514ef2f 1045 .features[FEAT_1_ECX] =
27861ecc 1046 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1047 CPUID_EXT_SSE3,
0514ef2f 1048 .features[FEAT_8000_0001_EDX] =
27861ecc 1049 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1050 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1051 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1052 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1053 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1054 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1055 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1056 .features[FEAT_8000_0001_ECX] =
27861ecc 1057 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1058 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1059 .xlevel = 0x80000008,
1060 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1061 },
1062 {
1063 .name = "Opteron_G4",
1064 .level = 0xd,
99b88a17 1065 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1066 .family = 21,
1067 .model = 1,
1068 .stepping = 2,
0514ef2f 1069 .features[FEAT_1_EDX] =
27861ecc 1070 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1071 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1072 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1073 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1074 CPUID_DE | CPUID_FP87,
0514ef2f 1075 .features[FEAT_1_ECX] =
27861ecc 1076 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1077 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1078 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1079 CPUID_EXT_SSE3,
0514ef2f 1080 .features[FEAT_8000_0001_EDX] =
27861ecc 1081 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1082 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1083 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1084 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1085 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1086 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1087 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1088 .features[FEAT_8000_0001_ECX] =
27861ecc 1089 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1090 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1091 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1092 CPUID_EXT3_LAHF_LM,
1093 .xlevel = 0x8000001A,
1094 .model_id = "AMD Opteron 62xx class CPU",
1095 },
021941b9
AP		 1096 {
1097 .name = "Opteron_G5",
1098 .level = 0xd,
99b88a17 1099 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1100 .family = 21,
1101 .model = 2,
1102 .stepping = 0,
0514ef2f 1103 .features[FEAT_1_EDX] =
27861ecc 1104 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1105 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1106 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1107 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1108 CPUID_DE | CPUID_FP87,
0514ef2f 1109 .features[FEAT_1_ECX] =
27861ecc 1110 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1111 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1112 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1113 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1114 .features[FEAT_8000_0001_EDX] =
27861ecc 1115 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1116 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1117 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1118 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1119 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1120 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1121 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1122 .features[FEAT_8000_0001_ECX] =
27861ecc 1123 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1124 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1125 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1126 CPUID_EXT3_LAHF_LM,
1127 .xlevel = 0x8000001A,
1128 .model_id = "AMD Opteron 63xx class CPU",
1129 },
c6dc6f63
AP		 1130};
1131
0668af54
EH		 1132/**
1133 * x86_cpu_compat_set_features:
1134 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1135 * @w: Identifies the feature word to be changed.
1136 * @feat_add: Feature bits to be added to feature word
1137 * @feat_remove: Feature bits to be removed from feature word
1138 *
1139 * Change CPU model feature bits for compatibility.
1140 *
1141 * This function may be used by machine-type compatibility functions
1142 * to enable or disable feature bits on specific CPU models.
1143 */
1144void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1145 uint32_t feat_add, uint32_t feat_remove)
1146{
9576de75 1147 X86CPUDefinition *def;
0668af54
EH		 1148 int i;
1149 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1150 def = &builtin_x86_defs[i];
1151 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1152 def->features[w] |= feat_add;
1153 def->features[w] &= ~feat_remove;
1154 }
1155 }
1156}
1157
d940ee9b
EH		 1158#ifdef CONFIG_KVM
1159
c6dc6f63
AP		 1160static int cpu_x86_fill_model_id(char *str)
1161{
1162 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1163 int i;
1164
1165 for (i = 0; i < 3; i++) {
1166 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1167 memcpy(str + i * 16 + 0, &eax, 4);
1168 memcpy(str + i * 16 + 4, &ebx, 4);
1169 memcpy(str + i * 16 + 8, &ecx, 4);
1170 memcpy(str + i * 16 + 12, &edx, 4);
1171 }
1172 return 0;
1173}
1174
d940ee9b
EH		 1175static X86CPUDefinition host_cpudef;
1176
1177/* class_init for the "host" CPU model
6e746f30 1178 *
d940ee9b 1179 * This function may be called before KVM is initialized.
6e746f30 1180 */
d940ee9b 1181static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1182{
d940ee9b 1183 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1184 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1185
d940ee9b 1186 xcc->kvm_required = true;
6e746f30 1187
c6dc6f63 1188 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1189 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1190
1191 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1192 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1193 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1194 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1195
d940ee9b 1196 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1197
d940ee9b
EH		 1198 xcc->cpu_def = &host_cpudef;
1199 host_cpudef.cache_info_passthrough = true;
1200
1201 /* level, xlevel, xlevel2, and the feature words are initialized on
1202 * instance_init, because they require KVM to be initialized.
1203 */
1204}
1205
1206static void host_x86_cpu_initfn(Object *obj)
1207{
1208 X86CPU *cpu = X86_CPU(obj);
1209 CPUX86State *env = &cpu->env;
1210 KVMState *s = kvm_state;
1211 FeatureWord w;
1212
1213 assert(kvm_enabled());
1214
1215 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1216 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1217 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1218
2bc65d2b
EH		 1219 for (w = 0; w < FEATURE_WORDS; w++) {
1220 FeatureWordInfo *wi = &feature_word_info[w];
d940ee9b 1221 env->features[w] =
2bc65d2b
EH		 1222 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1223 wi->cpuid_reg);
1224 }
d940ee9b 1225 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1226}
1227
d940ee9b
EH		 1228static const TypeInfo host_x86_cpu_type_info = {
1229 .name = X86_CPU_TYPE_NAME("host"),
1230 .parent = TYPE_X86_CPU,
1231 .instance_init = host_x86_cpu_initfn,
1232 .class_init = host_x86_cpu_class_init,
1233};
1234
1235#endif
1236
bffd67b0 1237static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
c6dc6f63
AP		 1238{
1239 int i;
1240
1241 for (i = 0; i < 32; ++i)
1242 if (1 << i & mask) {
bffd67b0 1243 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1244 assert(reg);
1245 fprintf(stderr, "warning: host doesn't support requested feature: "
1246 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1247 f->cpuid_eax, reg,
1248 f->feat_names[i] ? "." : "",
1249 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63
AP		 1250 break;
1251 }
1252 return 0;
1253}
1254
07ca5945
EH		 1255/* Check if all requested cpu flags are making their way to the guest
1256 *
1257 * Returns 0 if all flags are supported by the host, non-zero otherwise.
6e746f30
EH		 1258 *
1259 * This function may be called only if KVM is enabled.
c6dc6f63 1260 */
f0b9b111 1261static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
c6dc6f63 1262{
5ec01c2e 1263 CPUX86State *env = &cpu->env;
f0b9b111
EH		 1264 int rv = 0;
1265 FeatureWord w;
c6dc6f63 1266
6e746f30
EH		 1267 assert(kvm_enabled());
1268
f0b9b111 1269 for (w = 0; w < FEATURE_WORDS; w++) {
bffd67b0 1270 FeatureWordInfo *wi = &feature_word_info[w];
f0b9b111
EH		 1271 uint32_t guest_feat = env->features[w];
1272 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1273 wi->cpuid_ecx,
1274 wi->cpuid_reg);
1275 uint32_t mask;
bffd67b0 1276 for (mask = 1; mask; mask <<= 1) {
f0b9b111 1277 if (guest_feat & mask && !(host_feat & mask)) {
bffd67b0
EH		 1278 unavailable_host_feature(wi, mask);
1279 rv = 1;
1280 }
1281 }
1282 }
c6dc6f63
AP		 1283 return rv;
1284}
1285
95b8519d
AF		 1286static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1287 const char *name, Error **errp)
1288{
1289 X86CPU *cpu = X86_CPU(obj);
1290 CPUX86State *env = &cpu->env;
1291 int64_t value;
1292
1293 value = (env->cpuid_version >> 8) & 0xf;
1294 if (value == 0xf) {
1295 value += (env->cpuid_version >> 20) & 0xff;
1296 }
1297 visit_type_int(v, &value, name, errp);
1298}
1299
71ad61d3
AF		 1300static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1301 const char *name, Error **errp)
ed5e1ec3 1302{
71ad61d3
AF		 1303 X86CPU *cpu = X86_CPU(obj);
1304 CPUX86State *env = &cpu->env;
1305 const int64_t min = 0;
1306 const int64_t max = 0xff + 0xf;
65cd9064 1307 Error *local_err = NULL;
71ad61d3
AF		 1308 int64_t value;
1309
65cd9064
MA		 1310 visit_type_int(v, &value, name, &local_err);
1311 if (local_err) {
1312 error_propagate(errp, local_err);
71ad61d3
AF		 1313 return;
1314 }
1315 if (value < min || value > max) {
1316 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1317 name ? name : "null", value, min, max);
1318 return;
1319 }
1320
ed5e1ec3 1321 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1322 if (value > 0x0f) {
1323 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1324 } else {
71ad61d3 1325 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1326 }
1327}
1328
67e30c83
AF		 1329static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1330 const char *name, Error **errp)
1331{
1332 X86CPU *cpu = X86_CPU(obj);
1333 CPUX86State *env = &cpu->env;
1334 int64_t value;
1335
1336 value = (env->cpuid_version >> 4) & 0xf;
1337 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1338 visit_type_int(v, &value, name, errp);
1339}
1340
c5291a4f
AF		 1341static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1342 const char *name, Error **errp)
b0704cbd 1343{
c5291a4f
AF		 1344 X86CPU *cpu = X86_CPU(obj);
1345 CPUX86State *env = &cpu->env;
1346 const int64_t min = 0;
1347 const int64_t max = 0xff;
65cd9064 1348 Error *local_err = NULL;
c5291a4f
AF		 1349 int64_t value;
1350
65cd9064
MA		 1351 visit_type_int(v, &value, name, &local_err);
1352 if (local_err) {
1353 error_propagate(errp, local_err);
c5291a4f
AF		 1354 return;
1355 }
1356 if (value < min || value > max) {
1357 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1358 name ? name : "null", value, min, max);
1359 return;
1360 }
1361
b0704cbd 1362 env->cpuid_version &= ~0xf00f0;
c5291a4f 1363 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1364}
1365
35112e41
AF		 1366static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1367 void *opaque, const char *name,
1368 Error **errp)
1369{
1370 X86CPU *cpu = X86_CPU(obj);
1371 CPUX86State *env = &cpu->env;
1372 int64_t value;
1373
1374 value = env->cpuid_version & 0xf;
1375 visit_type_int(v, &value, name, errp);
1376}
1377
036e2222
AF		 1378static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1379 void *opaque, const char *name,
1380 Error **errp)
38c3dc46 1381{
036e2222
AF		 1382 X86CPU *cpu = X86_CPU(obj);
1383 CPUX86State *env = &cpu->env;
1384 const int64_t min = 0;
1385 const int64_t max = 0xf;
65cd9064 1386 Error *local_err = NULL;
036e2222
AF		 1387 int64_t value;
1388
65cd9064
MA		 1389 visit_type_int(v, &value, name, &local_err);
1390 if (local_err) {
1391 error_propagate(errp, local_err);
036e2222
AF		 1392 return;
1393 }
1394 if (value < min || value > max) {
1395 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1396 name ? name : "null", value, min, max);
1397 return;
1398 }
1399
38c3dc46 1400 env->cpuid_version &= ~0xf;
036e2222 1401 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1402}
1403
8e1898bf
AF		 1404static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1405 const char *name, Error **errp)
1406{
1407 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1408
fa029887 1409 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1410}
1411
1412static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1413 const char *name, Error **errp)
1414{
1415 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1416
fa029887 1417 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1418}
1419
16b93aa8
AF		 1420static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1421 const char *name, Error **errp)
1422{
1423 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1424
fa029887 1425 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1426}
1427
1428static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1429 const char *name, Error **errp)
1430{
1431 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1432
fa029887 1433 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1434}
1435
d480e1af
AF		 1436static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1437{
1438 X86CPU *cpu = X86_CPU(obj);
1439 CPUX86State *env = &cpu->env;
1440 char *value;
d480e1af 1441
9df694ee 1442 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1443 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1444 env->cpuid_vendor3);
d480e1af
AF		 1445 return value;
1446}
1447
1448static void x86_cpuid_set_vendor(Object *obj, const char *value,
1449 Error **errp)
1450{
1451 X86CPU *cpu = X86_CPU(obj);
1452 CPUX86State *env = &cpu->env;
1453 int i;
1454
9df694ee 1455 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1456 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1457 "vendor", value);
1458 return;
1459 }
1460
1461 env->cpuid_vendor1 = 0;
1462 env->cpuid_vendor2 = 0;
1463 env->cpuid_vendor3 = 0;
1464 for (i = 0; i < 4; i++) {
1465 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1466 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1467 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1468 }
d480e1af
AF		 1469}
1470
63e886eb
AF		 1471static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1472{
1473 X86CPU *cpu = X86_CPU(obj);
1474 CPUX86State *env = &cpu->env;
1475 char *value;
1476 int i;
1477
1478 value = g_malloc(48 + 1);
1479 for (i = 0; i < 48; i++) {
1480 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1481 }
1482 value[48] = '\0';
1483 return value;
1484}
1485
938d4c25
AF		 1486static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1487 Error **errp)
dcce6675 1488{
938d4c25
AF		 1489 X86CPU *cpu = X86_CPU(obj);
1490 CPUX86State *env = &cpu->env;
dcce6675
AF		 1491 int c, len, i;
1492
1493 if (model_id == NULL) {
1494 model_id = "";
1495 }
1496 len = strlen(model_id);
d0a6acf4 1497 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1498 for (i = 0; i < 48; i++) {
1499 if (i >= len) {
1500 c = '\0';
1501 } else {
1502 c = (uint8_t)model_id[i];
1503 }
1504 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1505 }
1506}
1507
89e48965
AF		 1508static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1509 const char *name, Error **errp)
1510{
1511 X86CPU *cpu = X86_CPU(obj);
1512 int64_t value;
1513
1514 value = cpu->env.tsc_khz * 1000;
1515 visit_type_int(v, &value, name, errp);
1516}
1517
1518static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1519 const char *name, Error **errp)
1520{
1521 X86CPU *cpu = X86_CPU(obj);
1522 const int64_t min = 0;
2e84849a 1523 const int64_t max = INT64_MAX;
65cd9064 1524 Error *local_err = NULL;
89e48965
AF		 1525 int64_t value;
1526
65cd9064
MA		 1527 visit_type_int(v, &value, name, &local_err);
1528 if (local_err) {
1529 error_propagate(errp, local_err);
89e48965
AF		 1530 return;
1531 }
1532 if (value < min || value > max) {
1533 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1534 name ? name : "null", value, min, max);
1535 return;
1536 }
1537
1538 cpu->env.tsc_khz = value / 1000;
1539}
1540
31050930
IM		 1541static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1542 const char *name, Error **errp)
1543{
1544 X86CPU *cpu = X86_CPU(obj);
1545 int64_t value = cpu->env.cpuid_apic_id;
1546
1547 visit_type_int(v, &value, name, errp);
1548}
1549
1550static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1551 const char *name, Error **errp)
1552{
1553 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1554 DeviceState *dev = DEVICE(obj);
31050930
IM		 1555 const int64_t min = 0;
1556 const int64_t max = UINT32_MAX;
1557 Error *error = NULL;
1558 int64_t value;
1559
8d6d4980
IM		 1560 if (dev->realized) {
1561 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1562 "it was realized", name, object_get_typename(obj));
1563 return;
1564 }
1565
31050930
IM		 1566 visit_type_int(v, &value, name, &error);
1567 if (error) {
1568 error_propagate(errp, error);
1569 return;
1570 }
1571 if (value < min || value > max) {
1572 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1573 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1574 object_get_typename(obj), name, value, min, max);
1575 return;
1576 }
1577
1578 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1579 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1580 return;
1581 }
1582 cpu->env.cpuid_apic_id = value;
1583}
1584
7e5292b5 1585/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1586static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1587 const char *name, Error **errp)
1588{
7e5292b5 1589 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1590 FeatureWord w;
1591 Error *err = NULL;
1592 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1593 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1594 X86CPUFeatureWordInfoList *list = NULL;
1595
1596 for (w = 0; w < FEATURE_WORDS; w++) {
1597 FeatureWordInfo *wi = &feature_word_info[w];
1598 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1599 qwi->cpuid_input_eax = wi->cpuid_eax;
1600 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1601 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1602 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1603 qwi->features = array[w];
8e8aba50
EH		 1604
1605 /* List will be in reverse order, but order shouldn't matter */
1606 list_entries[w].next = list;
1607 list_entries[w].value = &word_infos[w];
1608 list = &list_entries[w];
1609 }
1610
1611 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1612 error_propagate(errp, err);
1613}
1614
c8f0f88e
IM		 1615static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1616 const char *name, Error **errp)
1617{
1618 X86CPU *cpu = X86_CPU(obj);
1619 int64_t value = cpu->hyperv_spinlock_attempts;
1620
1621 visit_type_int(v, &value, name, errp);
1622}
1623
1624static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1625 const char *name, Error **errp)
1626{
1627 const int64_t min = 0xFFF;
1628 const int64_t max = UINT_MAX;
1629 X86CPU *cpu = X86_CPU(obj);
1630 Error *err = NULL;
1631 int64_t value;
1632
1633 visit_type_int(v, &value, name, &err);
1634 if (err) {
1635 error_propagate(errp, err);
1636 return;
1637 }
1638
1639 if (value < min || value > max) {
1640 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1641 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1642 object_get_typename(obj), name ? name : "null",
1643 value, min, max);
1644 return;
1645 }
1646 cpu->hyperv_spinlock_attempts = value;
1647}
1648
1649static PropertyInfo qdev_prop_spinlocks = {
1650 .name = "int",
1651 .get = x86_get_hv_spinlocks,
1652 .set = x86_set_hv_spinlocks,
1653};
1654
72ac2e87
IM		 1655/* Convert all '_' in a feature string option name to '-', to make feature
1656 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1657 */
1658static inline void feat2prop(char *s)
1659{
1660 while ((s = strchr(s, '_'))) {
1661 *s = '-';
1662 }
1663}
1664
8f961357
EH		 1665/* Parse "+feature,-feature,feature=foo" CPU feature string
1666 */
94a444b2
AF		 1667static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1668 Error **errp)
8f961357 1669{
94a444b2 1670 X86CPU *cpu = X86_CPU(cs);
8f961357
EH		 1671 char *featurestr; /* Single 'key=value" string being parsed */
1672 /* Features to be added */
077c68c3 1673 FeatureWordArray plus_features = { 0 };
8f961357 1674 /* Features to be removed */
5ef57876 1675 FeatureWordArray minus_features = { 0 };
8f961357 1676 uint32_t numvalue;
a91987c2 1677 CPUX86State *env = &cpu->env;
94a444b2 1678 Error *local_err = NULL;
8f961357 1679
8f961357 1680 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1681
1682 while (featurestr) {
1683 char *val;
1684 if (featurestr[0] == '+') {
5ef57876 1685 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1686 } else if (featurestr[0] == '-') {
5ef57876 1687 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1688 } else if ((val = strchr(featurestr, '='))) {
1689 *val = 0; val++;
72ac2e87 1690 feat2prop(featurestr);
d024d209 1691 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1692 char *err;
a91987c2
IM		 1693 char num[32];
1694
c6dc6f63
AP		 1695 numvalue = strtoul(val, &err, 0);
1696 if (!*val || *err) {
6b1dd54b
PB		 1697 error_setg(errp, "bad numerical value %s", val);
1698 return;
c6dc6f63
AP		 1699 }
1700 if (numvalue < 0x80000000) {
94a444b2
AF		 1701 error_report("xlevel value shall always be >= 0x80000000"
1702 ", fixup will be removed in future versions");
2f7a21c4 1703 numvalue += 0x80000000;
c6dc6f63 1704 }
a91987c2 1705 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1706 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1707 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1708 int64_t tsc_freq;
1709 char *err;
a91987c2 1710 char num[32];
b862d1fe
JR		 1711
1712 tsc_freq = strtosz_suffix_unit(val, &err,
1713 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1714 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1715 error_setg(errp, "bad numerical value %s", val);
1716 return;
b862d1fe 1717 }
a91987c2 1718 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1719 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1720 &local_err);
72ac2e87 1721 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1722 char *err;
92067bf4 1723 const int min = 0xFFF;
c8f0f88e 1724 char num[32];
28f52cc0
VR		 1725 numvalue = strtoul(val, &err, 0);
1726 if (!*val || *err) {
6b1dd54b
PB		 1727 error_setg(errp, "bad numerical value %s", val);
1728 return;
28f52cc0 1729 }
92067bf4 1730 if (numvalue < min) {
94a444b2
AF		 1731 error_report("hv-spinlocks value shall always be >= 0x%x"
1732 ", fixup will be removed in future versions",
92067bf4
IM		 1733 min);
1734 numvalue = min;
1735 }
c8f0f88e 1736 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1737 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1738 } else {
94a444b2 1739 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1740 }
c6dc6f63 1741 } else {
258f5abe 1742 feat2prop(featurestr);
94a444b2 1743 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1744 }
94a444b2
AF		 1745 if (local_err) {
1746 error_propagate(errp, local_err);
6b1dd54b 1747 return;
c6dc6f63
AP		 1748 }
1749 featurestr = strtok(NULL, ",");
1750 }
0514ef2f
EH		 1751 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1752 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1753 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1754 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1755 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1756 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1757 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1758 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1759 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1760 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1761 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1762 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1763 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1764 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1765 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1766 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
c6dc6f63
AP		 1767}
1768
1769/* generate a composite string into buf of all cpuid names in featureset
1770 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1771 * if flags, suppress names undefined in featureset.
1772 */
1773static void listflags(char *buf, int bufsize, uint32_t fbits,
1774 const char **featureset, uint32_t flags)
1775{
1776 const char **p = &featureset[31];
1777 char *q, *b, bit;
1778 int nc;
1779
1780 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1781 *buf = '\0';
1782 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1783 if (fbits & 1 << bit && (*p || !flags)) {
1784 if (*p)
1785 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1786 else
1787 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1788 if (bufsize <= nc) {
1789 if (b) {
1790 memcpy(b, "...", sizeof("..."));
1791 }
1792 return;
1793 }
1794 q += nc;
1795 bufsize -= nc;
1796 }
1797}
1798
e916cbf8
PM		 1799/* generate CPU information. */
1800void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1801{
9576de75 1802 X86CPUDefinition *def;
c6dc6f63 1803 char buf[256];
7fc9b714 1804 int i;
c6dc6f63 1805
7fc9b714
AF		 1806 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1807 def = &builtin_x86_defs[i];
c04321b3 1808 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1809 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1810 }
21ad7789
JK		 1811#ifdef CONFIG_KVM
1812 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1813 "KVM processor with all supported host features "
1814 "(only available in KVM mode)");
1815#endif
1816
6cdf8854 1817 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1818 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1819 FeatureWordInfo *fw = &feature_word_info[i];
1820
1821 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1822 (*cpu_fprintf)(f, " %s\n", buf);
1823 }
c6dc6f63
AP		 1824}
1825
76b64a7a 1826CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1827{
1828 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1829 X86CPUDefinition *def;
7fc9b714 1830 int i;
e3966126 1831
7fc9b714 1832 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1833 CpuDefinitionInfoList *entry;
1834 CpuDefinitionInfo *info;
1835
7fc9b714 1836 def = &builtin_x86_defs[i];
e3966126
AL		 1837 info = g_malloc0(sizeof(*info));
1838 info->name = g_strdup(def->name);
1839
1840 entry = g_malloc0(sizeof(*entry));
1841 entry->value = info;
1842 entry->next = cpu_list;
1843 cpu_list = entry;
1844 }
1845
1846 return cpu_list;
1847}
1848
bc74b7db
EH		 1849static void filter_features_for_kvm(X86CPU *cpu)
1850{
1851 CPUX86State *env = &cpu->env;
1852 KVMState *s = kvm_state;
bd87d2a2 1853 FeatureWord w;
bc74b7db 1854
bd87d2a2
EH		 1855 for (w = 0; w < FEATURE_WORDS; w++) {
1856 FeatureWordInfo *wi = &feature_word_info[w];
034acf4a
EH		 1857 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1858 wi->cpuid_ecx,
1859 wi->cpuid_reg);
1860 uint32_t requested_features = env->features[w];
1861 env->features[w] &= host_feat;
1862 cpu->filtered_features[w] = requested_features & ~env->features[w];
bd87d2a2 1863 }
bc74b7db 1864}
bc74b7db 1865
d940ee9b 1866/* Load data from X86CPUDefinition
c080e30e 1867 */
d940ee9b 1868static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1869{
61dcd775 1870 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1871 const char *vendor;
1872 char host_vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63 1873
2d64255b
AF		 1874 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1875 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1876 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1877 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
0514ef2f
EH		 1878 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1879 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1880 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1881 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
2d64255b 1882 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
0514ef2f
EH		 1883 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1884 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1885 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1886 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
b3baa152 1887 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1888 cpu->cache_info_passthrough = def->cache_info_passthrough;
3b671a40 1889
2d64255b 1890 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
82beb536 1891
9576de75 1892 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1893 if (kvm_enabled()) {
5fcca9ff
EH		 1894 FeatureWord w;
1895 for (w = 0; w < FEATURE_WORDS; w++) {
1896 env->features[w] |= kvm_default_features[w];
136a7e9a 1897 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 1898 }
82beb536 1899 }
5fcca9ff 1900
82beb536 1901 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1902
1903 /* sysenter isn't supported in compatibility mode on AMD,
1904 * syscall isn't supported in compatibility mode on Intel.
1905 * Normally we advertise the actual CPU vendor, but you can
1906 * override this using the 'vendor' property if you want to use
1907 * KVM's sysenter/syscall emulation in compatibility mode and
1908 * when doing cross vendor migration
1909 */
74f54bc4 1910 vendor = def->vendor;
7c08db30
EH		 1911 if (kvm_enabled()) {
1912 uint32_t ebx = 0, ecx = 0, edx = 0;
1913 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1914 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1915 vendor = host_vendor;
1916 }
1917
1918 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1919
c6dc6f63
AP		 1920}
1921
62fc403f
IM		 1922X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1923 Error **errp)
5c3c6a68 1924{
2d64255b 1925 X86CPU *cpu = NULL;
d940ee9b 1926 X86CPUClass *xcc;
500050d1 1927 ObjectClass *oc;
2d64255b
AF		 1928 gchar **model_pieces;
1929 char *name, *features;
5c3c6a68
AF		 1930 Error *error = NULL;
1931
2d64255b
AF		 1932 model_pieces = g_strsplit(cpu_model, ",", 2);
1933 if (!model_pieces[0]) {
1934 error_setg(&error, "Invalid/empty CPU model name");
1935 goto out;
1936 }
1937 name = model_pieces[0];
1938 features = model_pieces[1];
1939
500050d1
AF		 1940 oc = x86_cpu_class_by_name(name);
1941 if (oc == NULL) {
1942 error_setg(&error, "Unable to find CPU definition: %s", name);
1943 goto out;
1944 }
d940ee9b
EH		 1945 xcc = X86_CPU_CLASS(oc);
1946
1947 if (xcc->kvm_required && !kvm_enabled()) {
1948 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 1949 goto out;
1950 }
1951
d940ee9b
EH		 1952 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1953
62fc403f
IM		 1954#ifndef CONFIG_USER_ONLY
1955 if (icc_bridge == NULL) {
1956 error_setg(&error, "Invalid icc-bridge value");
1957 goto out;
1958 }
1959 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1960 object_unref(OBJECT(cpu));
1961#endif
5c3c6a68 1962
94a444b2 1963 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 1964 if (error) {
1965 goto out;
5c3c6a68
AF		 1966 }
1967
7f833247 1968out:
cd7b87ff
AF		 1969 if (error != NULL) {
1970 error_propagate(errp, error);
500050d1
AF		 1971 if (cpu) {
1972 object_unref(OBJECT(cpu));
1973 cpu = NULL;
1974 }
cd7b87ff 1975 }
7f833247
IM		 1976 g_strfreev(model_pieces);
1977 return cpu;
1978}
1979
1980X86CPU *cpu_x86_init(const char *cpu_model)
1981{
1982 Error *error = NULL;
1983 X86CPU *cpu;
1984
62fc403f 1985 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1986 if (error) {
2d64255b
AF		 1987 goto out;
1988 }
1989
7f833247
IM		 1990 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1991
2d64255b 1992out:
2d64255b 1993 if (error) {
4a44d85e 1994 error_report("%s", error_get_pretty(error));
5c3c6a68 1995 error_free(error);
2d64255b
AF		 1996 if (cpu != NULL) {
1997 object_unref(OBJECT(cpu));
1998 cpu = NULL;
1999 }
5c3c6a68
AF		 2000 }
2001 return cpu;
2002}
2003
d940ee9b
EH		 2004static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2005{
2006 X86CPUDefinition *cpudef = data;
2007 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2008
2009 xcc->cpu_def = cpudef;
2010}
2011
2012static void x86_register_cpudef_type(X86CPUDefinition *def)
2013{
2014 char *typename = x86_cpu_type_name(def->name);
2015 TypeInfo ti = {
2016 .name = typename,
2017 .parent = TYPE_X86_CPU,
2018 .class_init = x86_cpu_cpudef_class_init,
2019 .class_data = def,
2020 };
2021
2022 type_register(&ti);
2023 g_free(typename);
2024}
2025
c6dc6f63 2026#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2027
0e26b7b8
BS		 2028void cpu_clear_apic_feature(CPUX86State *env)
2029{
0514ef2f 2030 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2031}
2032
c6dc6f63
AP		 2033#endif /* !CONFIG_USER_ONLY */
2034
c04321b3 2035/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2036 */
2037void x86_cpudef_setup(void)
2038{
93bfef4c
CV		 2039 int i, j;
2040 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2041
2042 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2043 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2044
2045 /* Look for specific "cpudef" models that */
09faecf2 2046 /* have the QEMU version in .model_id */
93bfef4c 2047 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2048 if (strcmp(model_with_versions[j], def->name) == 0) {
2049 pstrcpy(def->model_id, sizeof(def->model_id),
2050 "QEMU Virtual CPU version ");
2051 pstrcat(def->model_id, sizeof(def->model_id),
2052 qemu_get_version());
93bfef4c
CV		 2053 break;
2054 }
2055 }
c6dc6f63 2056 }
c6dc6f63
AP		 2057}
2058
c6dc6f63
AP		 2059static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2060 uint32_t *ecx, uint32_t *edx)
2061{
2062 *ebx = env->cpuid_vendor1;
2063 *edx = env->cpuid_vendor2;
2064 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2065}
2066
2067void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2068 uint32_t *eax, uint32_t *ebx,
2069 uint32_t *ecx, uint32_t *edx)
2070{
a60f24b5
AF		 2071 X86CPU *cpu = x86_env_get_cpu(env);
2072 CPUState *cs = CPU(cpu);
2073
c6dc6f63
AP		 2074 /* test if maximum index reached */
2075 if (index & 0x80000000) {
b3baa152
BW		 2076 if (index > env->cpuid_xlevel) {
2077 if (env->cpuid_xlevel2 > 0) {
2078 /* Handle the Centaur's CPUID instruction. */
2079 if (index > env->cpuid_xlevel2) {
2080 index = env->cpuid_xlevel2;
2081 } else if (index < 0xC0000000) {
2082 index = env->cpuid_xlevel;
2083 }
2084 } else {
57f26ae7
EH		 2085 /* Intel documentation states that invalid EAX input will
2086 * return the same information as EAX=cpuid_level
2087 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2088 */
2089 index = env->cpuid_level;
b3baa152
BW		 2090 }
2091 }
c6dc6f63
AP		 2092 } else {
2093 if (index > env->cpuid_level)
2094 index = env->cpuid_level;
2095 }
2096
2097 switch(index) {
2098 case 0:
2099 *eax = env->cpuid_level;
2100 get_cpuid_vendor(env, ebx, ecx, edx);
2101 break;
2102 case 1:
2103 *eax = env->cpuid_version;
2104 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2105 *ecx = env->features[FEAT_1_ECX];
2106 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2107 if (cs->nr_cores * cs->nr_threads > 1) {
2108 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2109 *edx |= 1 << 28; /* HTT bit */
2110 }
2111 break;
2112 case 2:
2113 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2114 if (cpu->cache_info_passthrough) {
2115 host_cpuid(index, 0, eax, ebx, ecx, edx);
2116 break;
2117 }
5e891bf8 2118 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2119 *ebx = 0;
2120 *ecx = 0;
5e891bf8
EH		 2121 *edx = (L1D_DESCRIPTOR << 16) | \
2122 (L1I_DESCRIPTOR << 8) | \
2123 (L2_DESCRIPTOR);
c6dc6f63
AP		 2124 break;
2125 case 4:
2126 /* cache info: needed for Core compatibility */
787aaf57
BC		 2127 if (cpu->cache_info_passthrough) {
2128 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2129 *eax &= ~0xFC000000;
c6dc6f63 2130 } else {
2f7a21c4 2131 *eax = 0;
76c2975a 2132 switch (count) {
c6dc6f63 2133 case 0: /* L1 dcache info */
5e891bf8
EH		 2134 *eax |= CPUID_4_TYPE_DCACHE | \
2135 CPUID_4_LEVEL(1) | \
2136 CPUID_4_SELF_INIT_LEVEL;
2137 *ebx = (L1D_LINE_SIZE - 1) | \
2138 ((L1D_PARTITIONS - 1) << 12) | \
2139 ((L1D_ASSOCIATIVITY - 1) << 22);
2140 *ecx = L1D_SETS - 1;
2141 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2142 break;
2143 case 1: /* L1 icache info */
5e891bf8
EH		 2144 *eax |= CPUID_4_TYPE_ICACHE | \
2145 CPUID_4_LEVEL(1) | \
2146 CPUID_4_SELF_INIT_LEVEL;
2147 *ebx = (L1I_LINE_SIZE - 1) | \
2148 ((L1I_PARTITIONS - 1) << 12) | \
2149 ((L1I_ASSOCIATIVITY - 1) << 22);
2150 *ecx = L1I_SETS - 1;
2151 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2152 break;
2153 case 2: /* L2 cache info */
5e891bf8
EH		 2154 *eax |= CPUID_4_TYPE_UNIFIED | \
2155 CPUID_4_LEVEL(2) | \
2156 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2157 if (cs->nr_threads > 1) {
2158 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2159 }
5e891bf8
EH		 2160 *ebx = (L2_LINE_SIZE - 1) | \
2161 ((L2_PARTITIONS - 1) << 12) | \
2162 ((L2_ASSOCIATIVITY - 1) << 22);
2163 *ecx = L2_SETS - 1;
2164 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2165 break;
2166 default: /* end of info */
2167 *eax = 0;
2168 *ebx = 0;
2169 *ecx = 0;
2170 *edx = 0;
2171 break;
76c2975a
PB		 2172 }
2173 }
2174
2175 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2176 if ((*eax & 31) && cs->nr_cores > 1) {
2177 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2178 }
2179 break;
2180 case 5:
2181 /* mwait info: needed for Core compatibility */
2182 *eax = 0; /* Smallest monitor-line size in bytes */
2183 *ebx = 0; /* Largest monitor-line size in bytes */
2184 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2185 *edx = 0;
2186 break;
2187 case 6:
2188 /* Thermal and Power Leaf */
2189 *eax = 0;
2190 *ebx = 0;
2191 *ecx = 0;
2192 *edx = 0;
2193 break;
f7911686 2194 case 7:
13526728
EH		 2195 /* Structured Extended Feature Flags Enumeration Leaf */
2196 if (count == 0) {
2197 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2198 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2199 *ecx = 0; /* Reserved */
2200 *edx = 0; /* Reserved */
f7911686
YW		 2201 } else {
2202 *eax = 0;
2203 *ebx = 0;
2204 *ecx = 0;
2205 *edx = 0;
2206 }
2207 break;
c6dc6f63
AP		 2208 case 9:
2209 /* Direct Cache Access Information Leaf */
2210 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2211 *ebx = 0;
2212 *ecx = 0;
2213 *edx = 0;
2214 break;
2215 case 0xA:
2216 /* Architectural Performance Monitoring Leaf */
9337e3b6 2217 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2218 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2219
2220 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2221 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2222 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2223 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2224 } else {
2225 *eax = 0;
2226 *ebx = 0;
2227 *ecx = 0;
2228 *edx = 0;
2229 }
c6dc6f63 2230 break;
2560f19f
PB		 2231 case 0xD: {
2232 KVMState *s = cs->kvm_state;
2233 uint64_t kvm_mask;
2234 int i;
2235
51e49430 2236 /* Processor Extended State */
2560f19f
PB		 2237 *eax = 0;
2238 *ebx = 0;
2239 *ecx = 0;
2240 *edx = 0;
2241 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2242 break;
2243 }
2560f19f
PB		 2244 kvm_mask =
2245 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2246 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2247
2560f19f
PB		 2248 if (count == 0) {
2249 *ecx = 0x240;
2250 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2251 const ExtSaveArea *esa = &ext_save_areas[i];
2252 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2253 (kvm_mask & (1 << i)) != 0) {
2254 if (i < 32) {
2255 *eax |= 1 << i;
2256 } else {
2257 *edx |= 1 << (i - 32);
2258 }
2259 *ecx = MAX(*ecx, esa->offset + esa->size);
2260 }
2261 }
2262 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2263 *ebx = *ecx;
2264 } else if (count == 1) {
2265 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2266 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2267 const ExtSaveArea *esa = &ext_save_areas[count];
2268 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2269 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2270 *eax = esa->size;
2271 *ebx = esa->offset;
2560f19f 2272 }
51e49430
SY		 2273 }
2274 break;
2560f19f 2275 }
c6dc6f63
AP		 2276 case 0x80000000:
2277 *eax = env->cpuid_xlevel;
2278 *ebx = env->cpuid_vendor1;
2279 *edx = env->cpuid_vendor2;
2280 *ecx = env->cpuid_vendor3;
2281 break;
2282 case 0x80000001:
2283 *eax = env->cpuid_version;
2284 *ebx = 0;
0514ef2f
EH		 2285 *ecx = env->features[FEAT_8000_0001_ECX];
2286 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2287
2288 /* The Linux kernel checks for the CMPLegacy bit and
2289 * discards multiple thread information if it is set.
2290 * So dont set it here for Intel to make Linux guests happy.
2291 */
ce3960eb 2292 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2293 uint32_t tebx, tecx, tedx;
2294 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2295 if (tebx != CPUID_VENDOR_INTEL_1 ||
2296 tedx != CPUID_VENDOR_INTEL_2 ||
2297 tecx != CPUID_VENDOR_INTEL_3) {
2298 *ecx |= 1 << 1; /* CmpLegacy bit */
2299 }
2300 }
c6dc6f63
AP		 2301 break;
2302 case 0x80000002:
2303 case 0x80000003:
2304 case 0x80000004:
2305 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2306 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2307 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2308 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2309 break;
2310 case 0x80000005:
2311 /* cache info (L1 cache) */
787aaf57
BC		 2312 if (cpu->cache_info_passthrough) {
2313 host_cpuid(index, 0, eax, ebx, ecx, edx);
2314 break;
2315 }
5e891bf8
EH		 2316 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2317 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2318 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2319 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2320 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2321 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2322 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2323 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2324 break;
2325 case 0x80000006:
2326 /* cache info (L2 cache) */
787aaf57
BC		 2327 if (cpu->cache_info_passthrough) {
2328 host_cpuid(index, 0, eax, ebx, ecx, edx);
2329 break;
2330 }
5e891bf8
EH		 2331 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2332 (L2_DTLB_2M_ENTRIES << 16) | \
2333 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2334 (L2_ITLB_2M_ENTRIES);
2335 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2336 (L2_DTLB_4K_ENTRIES << 16) | \
2337 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2338 (L2_ITLB_4K_ENTRIES);
2339 *ecx = (L2_SIZE_KB_AMD << 16) | \
2340 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2341 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2342 *edx = ((L3_SIZE_KB/512) << 18) | \
2343 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2344 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2345 break;
2346 case 0x80000008:
2347 /* virtual & phys address size in low 2 bytes. */
2348/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2349 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2350 /* 64 bit processor */
2351/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2352 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2353 } else {
0514ef2f 2354 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2355 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2356 } else {
c6dc6f63 2357 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2358 }
c6dc6f63
AP		 2359 }
2360 *ebx = 0;
2361 *ecx = 0;
2362 *edx = 0;
ce3960eb
AF		 2363 if (cs->nr_cores * cs->nr_threads > 1) {
2364 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2365 }
2366 break;
2367 case 0x8000000A:
0514ef2f 2368 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2369 *eax = 0x00000001; /* SVM Revision */
2370 *ebx = 0x00000010; /* nr of ASIDs */
2371 *ecx = 0;
0514ef2f 2372 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2373 } else {
2374 *eax = 0;
2375 *ebx = 0;
2376 *ecx = 0;
2377 *edx = 0;
2378 }
c6dc6f63 2379 break;
b3baa152
BW		 2380 case 0xC0000000:
2381 *eax = env->cpuid_xlevel2;
2382 *ebx = 0;
2383 *ecx = 0;
2384 *edx = 0;
2385 break;
2386 case 0xC0000001:
2387 /* Support for VIA CPU's CPUID instruction */
2388 *eax = env->cpuid_version;
2389 *ebx = 0;
2390 *ecx = 0;
0514ef2f 2391 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2392 break;
2393 case 0xC0000002:
2394 case 0xC0000003:
2395 case 0xC0000004:
2396 /* Reserved for the future, and now filled with zero */
2397 *eax = 0;
2398 *ebx = 0;
2399 *ecx = 0;
2400 *edx = 0;
2401 break;
c6dc6f63
AP		 2402 default:
2403 /* reserved values: zero */
2404 *eax = 0;
2405 *ebx = 0;
2406 *ecx = 0;
2407 *edx = 0;
2408 break;
2409 }
2410}
5fd2087a
AF		 2411
2412/* CPUClass::reset() */
2413static void x86_cpu_reset(CPUState *s)
2414{
2415 X86CPU *cpu = X86_CPU(s);
2416 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2417 CPUX86State *env = &cpu->env;
c1958aea
AF		 2418 int i;
2419
5fd2087a
AF		 2420 xcc->parent_reset(s);
2421
43175fa9 2422 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2423
00c8cb0a 2424 tlb_flush(s, 1);
c1958aea
AF		 2425
2426 env->old_exception = -1;
2427
2428 /* init to reset state */
2429
2430#ifdef CONFIG_SOFTMMU
2431 env->hflags |= HF_SOFTMMU_MASK;
2432#endif
2433 env->hflags2 |= HF2_GIF_MASK;
2434
2435 cpu_x86_update_cr0(env, 0x60000010);
2436 env->a20_mask = ~0x0;
2437 env->smbase = 0x30000;
2438
2439 env->idt.limit = 0xffff;
2440 env->gdt.limit = 0xffff;
2441 env->ldt.limit = 0xffff;
2442 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2443 env->tr.limit = 0xffff;
2444 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2445
2446 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2447 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2448 DESC_R_MASK | DESC_A_MASK);
2449 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2450 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2451 DESC_A_MASK);
2452 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2453 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2454 DESC_A_MASK);
2455 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2456 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2457 DESC_A_MASK);
2458 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2459 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2460 DESC_A_MASK);
2461 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2462 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2463 DESC_A_MASK);
2464
2465 env->eip = 0xfff0;
2466 env->regs[R_EDX] = env->cpuid_version;
2467
2468 env->eflags = 0x2;
2469
2470 /* FPU init */
2471 for (i = 0; i < 8; i++) {
2472 env->fptags[i] = 1;
2473 }
2474 env->fpuc = 0x37f;
2475
2476 env->mxcsr = 0x1f80;
c74f41bb 2477 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2478
2479 env->pat = 0x0007040600070406ULL;
2480 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2481
2482 memset(env->dr, 0, sizeof(env->dr));
2483 env->dr[6] = DR6_FIXED_1;
2484 env->dr[7] = DR7_FIXED_1;
b3310ab3 2485 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2486 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2487
05e7e819 2488 env->xcr0 = 1;
0522604b 2489
dd673288
IM		 2490#if !defined(CONFIG_USER_ONLY)
2491 /* We hard-wire the BSP to the first CPU. */
55e5c285 2492 if (s->cpu_index == 0) {
02e51483 2493 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2494 }
2495
259186a7 2496 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2497
2498 if (kvm_enabled()) {
2499 kvm_arch_reset_vcpu(cpu);
2500 }
dd673288 2501#endif
5fd2087a
AF		 2502}
2503
dd673288
IM		 2504#ifndef CONFIG_USER_ONLY
2505bool cpu_is_bsp(X86CPU *cpu)
2506{
02e51483 2507 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2508}
65dee380
IM		 2509
2510/* TODO: remove me, when reset over QOM tree is implemented */
2511static void x86_cpu_machine_reset_cb(void *opaque)
2512{
2513 X86CPU *cpu = opaque;
2514 cpu_reset(CPU(cpu));
2515}
dd673288
IM		 2516#endif
2517
de024815
AF		 2518static void mce_init(X86CPU *cpu)
2519{
2520 CPUX86State *cenv = &cpu->env;
2521 unsigned int bank;
2522
2523 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2524 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2525 (CPUID_MCE | CPUID_MCA)) {
2526 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2527 cenv->mcg_ctl = ~(uint64_t)0;
2528 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2529 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2530 }
2531 }
2532}
2533
bdeec802 2534#ifndef CONFIG_USER_ONLY
d3c64d6a 2535static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2536{
bdeec802 2537 CPUX86State *env = &cpu->env;
53a89e26 2538 DeviceState *dev = DEVICE(cpu);
449994eb 2539 APICCommonState *apic;
bdeec802
IM		 2540 const char *apic_type = "apic";
2541
2542 if (kvm_irqchip_in_kernel()) {
2543 apic_type = "kvm-apic";
2544 } else if (xen_enabled()) {
2545 apic_type = "xen-apic";
2546 }
2547
02e51483
CF		 2548 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2549 if (cpu->apic_state == NULL) {
bdeec802
IM		 2550 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2551 return;
2552 }
2553
2554 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2555 OBJECT(cpu->apic_state), NULL);
2556 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2557 /* TODO: convert to link<> */
02e51483 2558 apic = APIC_COMMON(cpu->apic_state);
60671e58 2559 apic->cpu = cpu;
d3c64d6a
IM		 2560}
2561
2562static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2563{
02e51483 2564 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2565 return;
2566 }
bdeec802 2567
02e51483 2568 if (qdev_init(cpu->apic_state)) {
bdeec802 2569 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2570 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2571 return;
2572 }
bdeec802 2573}
d3c64d6a
IM		 2574#else
2575static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2576{
2577}
bdeec802
IM		 2578#endif
2579
2b6f294c 2580static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2581{
14a10fc3 2582 CPUState *cs = CPU(dev);
2b6f294c
AF		 2583 X86CPU *cpu = X86_CPU(dev);
2584 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2585 CPUX86State *env = &cpu->env;
2b6f294c 2586 Error *local_err = NULL;
b34d12d1 2587
0514ef2f 2588 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2589 env->cpuid_level = 7;
2590 }
7a059953 2591
9b15cd9e
IM		 2592 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2593 * CPUID[1].EDX.
2594 */
2595 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2596 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2597 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2598 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2599 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2600 & CPUID_EXT2_AMD_ALIASES);
2601 }
2602
4586f157 2603 if (!kvm_enabled()) {
0514ef2f
EH		 2604 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2605 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2606 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
4586f157
IM		 2607#ifdef TARGET_X86_64
2608 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2609#endif
2610 );
0514ef2f
EH		 2611 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2612 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
4586f157 2613 } else {
f0b9b111 2614 KVMState *s = kvm_state;
912ffc47 2615 if ((cpu->check_cpuid || cpu->enforce_cpuid)
f0b9b111 2616 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2617 error_setg(&local_err,
2618 "Host's CPU doesn't support requested features");
2619 goto out;
5ec01c2e 2620 }
a509d632 2621 filter_features_for_kvm(cpu);
4586f157
IM		 2622 }
2623
65dee380
IM		 2624#ifndef CONFIG_USER_ONLY
2625 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2626
0514ef2f 2627 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2628 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2629 if (local_err != NULL) {
4dc1f449 2630 goto out;
bdeec802
IM		 2631 }
2632 }
65dee380
IM		 2633#endif
2634
7a059953 2635 mce_init(cpu);
14a10fc3 2636 qemu_init_vcpu(cs);
d3c64d6a
IM		 2637
2638 x86_cpu_apic_realize(cpu, &local_err);
2639 if (local_err != NULL) {
2640 goto out;
2641 }
14a10fc3 2642 cpu_reset(cs);
2b6f294c 2643
4dc1f449
IM		 2644 xcc->parent_realize(dev, &local_err);
2645out:
2646 if (local_err != NULL) {
2647 error_propagate(errp, local_err);
2648 return;
2649 }
7a059953
AF		 2650}
2651
8932cfdf
EH		 2652/* Enables contiguous-apic-ID mode, for compatibility */
2653static bool compat_apic_id_mode;
2654
2655void enable_compat_apic_id_mode(void)
2656{
2657 compat_apic_id_mode = true;
2658}
2659
cb41bad3
EH		 2660/* Calculates initial APIC ID for a specific CPU index
2661 *
2662 * Currently we need to be able to calculate the APIC ID from the CPU index
2663 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2664 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2665 * all CPUs up to max_cpus.
2666 */
2667uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2668{
8932cfdf
EH		 2669 uint32_t correct_id;
2670 static bool warned;
2671
2672 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2673 if (compat_apic_id_mode) {
2674 if (cpu_index != correct_id && !warned) {
2675 error_report("APIC IDs set in compatibility mode, "
2676 "CPU topology won't match the configuration");
2677 warned = true;
2678 }
2679 return cpu_index;
2680 } else {
2681 return correct_id;
2682 }
cb41bad3
EH		 2683}
2684
de024815
AF		 2685static void x86_cpu_initfn(Object *obj)
2686{
55e5c285 2687 CPUState *cs = CPU(obj);
de024815 2688 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2689 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2690 CPUX86State *env = &cpu->env;
d65e9815 2691 static int inited;
de024815 2692
c05efcb1 2693 cs->env_ptr = env;
de024815 2694 cpu_exec_init(env);
71ad61d3
AF		 2695
2696 object_property_add(obj, "family", "int",
95b8519d 2697 x86_cpuid_version_get_family,
71ad61d3 2698 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2699 object_property_add(obj, "model", "int",
67e30c83 2700 x86_cpuid_version_get_model,
c5291a4f 2701 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2702 object_property_add(obj, "stepping", "int",
35112e41 2703 x86_cpuid_version_get_stepping,
036e2222 2704 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2705 object_property_add(obj, "level", "int",
2706 x86_cpuid_get_level,
2707 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2708 object_property_add(obj, "xlevel", "int",
2709 x86_cpuid_get_xlevel,
2710 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2711 object_property_add_str(obj, "vendor",
2712 x86_cpuid_get_vendor,
2713 x86_cpuid_set_vendor, NULL);
938d4c25 2714 object_property_add_str(obj, "model-id",
63e886eb 2715 x86_cpuid_get_model_id,
938d4c25 2716 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2717 object_property_add(obj, "tsc-frequency", "int",
2718 x86_cpuid_get_tsc_freq,
2719 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2720 object_property_add(obj, "apic-id", "int",
2721 x86_cpuid_get_apic_id,
2722 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2723 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2724 x86_cpu_get_feature_words,
7e5292b5
EH		 2725 NULL, NULL, (void *)env->features, NULL);
2726 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2727 x86_cpu_get_feature_words,
2728 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2729
92067bf4 2730 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2731 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2732
d940ee9b
EH		 2733 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2734
d65e9815
IM		 2735 /* init various static tables used in TCG mode */
2736 if (tcg_enabled() && !inited) {
2737 inited = 1;
2738 optimize_flags_init();
2739#ifndef CONFIG_USER_ONLY
2740 cpu_set_debug_excp_handler(breakpoint_handler);
2741#endif
2742 }
de024815
AF		 2743}
2744
997395d3
IM		 2745static int64_t x86_cpu_get_arch_id(CPUState *cs)
2746{
2747 X86CPU *cpu = X86_CPU(cs);
2748 CPUX86State *env = &cpu->env;
2749
2750 return env->cpuid_apic_id;
2751}
2752
444d5590
AF		 2753static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2754{
2755 X86CPU *cpu = X86_CPU(cs);
2756
2757 return cpu->env.cr[0] & CR0_PG_MASK;
2758}
2759
f45748f1
AF		 2760static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2761{
2762 X86CPU *cpu = X86_CPU(cs);
2763
2764 cpu->env.eip = value;
2765}
2766
bdf7ae5b
AF		 2767static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2768{
2769 X86CPU *cpu = X86_CPU(cs);
2770
2771 cpu->env.eip = tb->pc - tb->cs_base;
2772}
2773
8c2e1b00
AF		 2774static bool x86_cpu_has_work(CPUState *cs)
2775{
2776 X86CPU *cpu = X86_CPU(cs);
2777 CPUX86State *env = &cpu->env;
2778
2779 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2780 CPU_INTERRUPT_POLL)) &&
2781 (env->eflags & IF_MASK)) ||
2782 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2783 CPU_INTERRUPT_INIT |
2784 CPU_INTERRUPT_SIPI |
2785 CPU_INTERRUPT_MCE));
2786}
2787
9337e3b6
EH		 2788static Property x86_cpu_properties[] = {
2789 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2790 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2791 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2792 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2793 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2794 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2795 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2796 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2797 DEFINE_PROP_END_OF_LIST()
2798};
2799
5fd2087a
AF		 2800static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2801{
2802 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2803 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2804 DeviceClass *dc = DEVICE_CLASS(oc);
2805
2806 xcc->parent_realize = dc->realize;
2807 dc->realize = x86_cpu_realizefn;
62fc403f 2808 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2809 dc->props = x86_cpu_properties;
5fd2087a
AF		 2810
2811 xcc->parent_reset = cc->reset;
2812 cc->reset = x86_cpu_reset;
91b1df8c 2813 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2814
500050d1 2815 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2816 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2817 cc->has_work = x86_cpu_has_work;
97a8ea5a 2818 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2819 cc->dump_state = x86_cpu_dump_state;
f45748f1 2820 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2821 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2822 cc->gdb_read_register = x86_cpu_gdb_read_register;
2823 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2824 cc->get_arch_id = x86_cpu_get_arch_id;
2825 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2826#ifdef CONFIG_USER_ONLY
2827 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2828#else
a23bbfda 2829 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2830 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2831 cc->write_elf64_note = x86_cpu_write_elf64_note;
2832 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2833 cc->write_elf32_note = x86_cpu_write_elf32_note;
2834 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2835 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2836#endif
a0e372f0 2837 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2838}
2839
2840static const TypeInfo x86_cpu_type_info = {
2841 .name = TYPE_X86_CPU,
2842 .parent = TYPE_CPU,
2843 .instance_size = sizeof(X86CPU),
de024815 2844 .instance_init = x86_cpu_initfn,
d940ee9b 2845 .abstract = true,
5fd2087a
AF		 2846 .class_size = sizeof(X86CPUClass),
2847 .class_init = x86_cpu_common_class_init,
2848};
2849
2850static void x86_cpu_register_types(void)
2851{
d940ee9b
EH		 2852 int i;
2853
5fd2087a 2854 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2855 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2856 x86_register_cpudef_type(&builtin_x86_defs[i]);
2857 }
2858#ifdef CONFIG_KVM
2859 type_register_static(&host_x86_cpu_type_info);
2860#endif
5fd2087a
AF		 2861}
2862
2863type_init(x86_cpu_register_types)
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