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KVM: VMX: fix memory order between loading vmcs and clearing vmcs
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
a27685c3 77static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
83287ea4
AK		 130extern const ulong vmx_return;
131
8bf00a52 132#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 133#define VMCS02_POOL_SIZE 1
61d2ef2c 134
a2fa3e9f
GH		 135struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139};
140
d462b819
NHE		 141/*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151};
152
26bb0981
AK		 153struct shared_msr_entry {
154 unsigned index;
155 u64 data;
d5696725 156 u64 mask;
26bb0981
AK		 157};
158
a9d30f33
NHE		 159/*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
22bd0358 172typedef u64 natural_width;
a9d30f33
NHE		 173struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
22bd0358 179
27d6c865
NHE		 180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
22bd0358
NHE		 183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
302 u32 padding32[8]; /* room for future expansion */
303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
a9d30f33
NHE		 319};
320
321/*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326#define VMCS12_REVISION 0x11e57ed0
327
328/*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333#define VMCS12_SIZE 0x1000
334
ff2f6fe9
NHE		 335/* Used to remember the last vmcs02 used for some recently used vmcs12s */
336struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340};
341
ec378aee
NHE		 342/*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
a9d30f33
NHE		 349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
fe3ef05c 359 u64 vmcs01_tsc_offset;
644d711a
NHE		 360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
fe3ef05c
NHE		 362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
ec378aee
NHE		 367};
368
a2fa3e9f 369struct vcpu_vmx {
fb3f0f51 370 struct kvm_vcpu vcpu;
313dbd49 371 unsigned long host_rsp;
29bd8a78 372 u8 fail;
69c73028 373 u8 cpl;
9d58b931 374 bool nmi_known_unmasked;
51aa01d1 375 u32 exit_intr_info;
1155f76a 376 u32 idt_vectoring_info;
6de12732 377 ulong rflags;
26bb0981 378 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 379 int nmsrs;
380 int save_nmsrs;
a2fa3e9f 381#ifdef CONFIG_X86_64
44ea2b17
AK		 382 u64 msr_host_kernel_gs_base;
383 u64 msr_guest_kernel_gs_base;
a2fa3e9f 384#endif
d462b819
NHE		 385 /*
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
389 */
390 struct loaded_vmcs vmcs01;
391 struct loaded_vmcs *loaded_vmcs;
392 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 393 struct msr_autoload {
394 unsigned nr;
395 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
396 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
397 } msr_autoload;
a2fa3e9f
GH		 398 struct {
399 int loaded;
400 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 401#ifdef CONFIG_X86_64
402 u16 ds_sel, es_sel;
403#endif
152d3f2f
LV		 404 int gs_ldt_reload_needed;
405 int fs_reload_needed;
d77c26fc 406 } host_state;
9c8cba37 407 struct {
7ffd92c5 408 int vm86_active;
78ac8b47 409 ulong save_rflags;
f5f7b2fe
AK		 410 struct kvm_segment segs[8];
411 } rmode;
412 struct {
413 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 414 struct kvm_save_segment {
415 u16 selector;
416 unsigned long base;
417 u32 limit;
418 u32 ar;
f5f7b2fe 419 } seg[8];
2fb92db1 420 } segment_cache;
2384d2b3 421 int vpid;
04fa4d32 422 bool emulation_required;
3b86cd99
JK		 423
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked;
426 ktime_t entry_time;
427 s64 vnmi_blocked_time;
a0861c02 428 u32 exit_reason;
4e47c7a6
SY		 429
430 bool rdtscp_enabled;
ec378aee
NHE		 431
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested;
a2fa3e9f
GH		 434};
435
2fb92db1
AK		 436enum segment_cache_field {
437 SEG_FIELD_SEL = 0,
438 SEG_FIELD_BASE = 1,
439 SEG_FIELD_LIMIT = 2,
440 SEG_FIELD_AR = 3,
441
442 SEG_FIELD_NR = 4
443};
444
a2fa3e9f
GH		 445static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446{
fb3f0f51 447 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 448}
449
22bd0358
NHE		 450#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
454
772e0318 455static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 456 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
457 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
458 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
459 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
460 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
461 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
462 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
463 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
464 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
465 FIELD(HOST_ES_SELECTOR, host_es_selector),
466 FIELD(HOST_CS_SELECTOR, host_cs_selector),
467 FIELD(HOST_SS_SELECTOR, host_ss_selector),
468 FIELD(HOST_DS_SELECTOR, host_ds_selector),
469 FIELD(HOST_FS_SELECTOR, host_fs_selector),
470 FIELD(HOST_GS_SELECTOR, host_gs_selector),
471 FIELD(HOST_TR_SELECTOR, host_tr_selector),
472 FIELD64(IO_BITMAP_A, io_bitmap_a),
473 FIELD64(IO_BITMAP_B, io_bitmap_b),
474 FIELD64(MSR_BITMAP, msr_bitmap),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
478 FIELD64(TSC_OFFSET, tsc_offset),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
480 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
481 FIELD64(EPT_POINTER, ept_pointer),
482 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
483 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
484 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
485 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
486 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
488 FIELD64(GUEST_PDPTR0, guest_pdptr0),
489 FIELD64(GUEST_PDPTR1, guest_pdptr1),
490 FIELD64(GUEST_PDPTR2, guest_pdptr2),
491 FIELD64(GUEST_PDPTR3, guest_pdptr3),
492 FIELD64(HOST_IA32_PAT, host_ia32_pat),
493 FIELD64(HOST_IA32_EFER, host_ia32_efer),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
497 FIELD(EXCEPTION_BITMAP, exception_bitmap),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
500 FIELD(CR3_TARGET_COUNT, cr3_target_count),
501 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
502 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
504 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
509 FIELD(TPR_THRESHOLD, tpr_threshold),
510 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
511 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
512 FIELD(VM_EXIT_REASON, vm_exit_reason),
513 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
514 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
515 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
516 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
517 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
518 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
519 FIELD(GUEST_ES_LIMIT, guest_es_limit),
520 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
521 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
522 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
523 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
524 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
525 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
526 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
527 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
528 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
529 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
530 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
531 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
532 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
533 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
534 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
535 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
536 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
538 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
539 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
540 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
541 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
542 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
543 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
544 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
545 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
546 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
547 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
548 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
549 FIELD(EXIT_QUALIFICATION, exit_qualification),
550 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
551 FIELD(GUEST_CR0, guest_cr0),
552 FIELD(GUEST_CR3, guest_cr3),
553 FIELD(GUEST_CR4, guest_cr4),
554 FIELD(GUEST_ES_BASE, guest_es_base),
555 FIELD(GUEST_CS_BASE, guest_cs_base),
556 FIELD(GUEST_SS_BASE, guest_ss_base),
557 FIELD(GUEST_DS_BASE, guest_ds_base),
558 FIELD(GUEST_FS_BASE, guest_fs_base),
559 FIELD(GUEST_GS_BASE, guest_gs_base),
560 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
561 FIELD(GUEST_TR_BASE, guest_tr_base),
562 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
563 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
564 FIELD(GUEST_DR7, guest_dr7),
565 FIELD(GUEST_RSP, guest_rsp),
566 FIELD(GUEST_RIP, guest_rip),
567 FIELD(GUEST_RFLAGS, guest_rflags),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
569 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
570 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
571 FIELD(HOST_CR0, host_cr0),
572 FIELD(HOST_CR3, host_cr3),
573 FIELD(HOST_CR4, host_cr4),
574 FIELD(HOST_FS_BASE, host_fs_base),
575 FIELD(HOST_GS_BASE, host_gs_base),
576 FIELD(HOST_TR_BASE, host_tr_base),
577 FIELD(HOST_GDTR_BASE, host_gdtr_base),
578 FIELD(HOST_IDTR_BASE, host_idtr_base),
579 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
580 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
581 FIELD(HOST_RSP, host_rsp),
582 FIELD(HOST_RIP, host_rip),
583};
584static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585
586static inline short vmcs_field_to_offset(unsigned long field)
587{
588 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return -1;
590 return vmcs_field_to_offset_table[field];
591}
592
a9d30f33
NHE		 593static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594{
595 return to_vmx(vcpu)->nested.current_vmcs12;
596}
597
598static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599{
600 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 601 if (is_error_page(page))
a9d30f33 602 return NULL;
32cad84f 603
a9d30f33
NHE		 604 return page;
605}
606
607static void nested_release_page(struct page *page)
608{
609 kvm_release_page_dirty(page);
610}
611
612static void nested_release_page_clean(struct page *page)
613{
614 kvm_release_page_clean(page);
615}
616
4e1096d2 617static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 618static void kvm_cpu_vmxon(u64 addr);
619static void kvm_cpu_vmxoff(void);
aff48baa 620static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 621static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 622static void vmx_set_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
624static void vmx_get_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
75880a01 626
6aa8b732
AK		 627static DEFINE_PER_CPU(struct vmcs *, vmxarea);
628static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 629/*
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 */
633static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 634static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 635
3e7c73e9
AK		 636static unsigned long *vmx_io_bitmap_a;
637static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 638static unsigned long *vmx_msr_bitmap_legacy;
639static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 640
110312c8 641static bool cpu_has_load_ia32_efer;
8bf00a52 642static bool cpu_has_load_perf_global_ctrl;
110312c8 643
2384d2b3
SY		 644static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
645static DEFINE_SPINLOCK(vmx_vpid_lock);
646
1c3d14fe 647static struct vmcs_config {
6aa8b732
AK		 648 int size;
649 int order;
650 u32 revision_id;
1c3d14fe
YS		 651 u32 pin_based_exec_ctrl;
652 u32 cpu_based_exec_ctrl;
f78e0e2e 653 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 654 u32 vmexit_ctrl;
655 u32 vmentry_ctrl;
656} vmcs_config;
6aa8b732 657
efff9e53 658static struct vmx_capability {
d56f546d
SY		 659 u32 ept;
660 u32 vpid;
661} vmx_capability;
662
6aa8b732
AK		 663#define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
669 }
670
772e0318 671static const struct kvm_vmx_segment_field {
6aa8b732
AK		 672 unsigned selector;
673 unsigned base;
674 unsigned limit;
675 unsigned ar_bytes;
676} kvm_vmx_segment_fields[] = {
677 VMX_SEGMENT_FIELD(CS),
678 VMX_SEGMENT_FIELD(DS),
679 VMX_SEGMENT_FIELD(ES),
680 VMX_SEGMENT_FIELD(FS),
681 VMX_SEGMENT_FIELD(GS),
682 VMX_SEGMENT_FIELD(SS),
683 VMX_SEGMENT_FIELD(TR),
684 VMX_SEGMENT_FIELD(LDTR),
685};
686
26bb0981
AK		 687static u64 host_efer;
688
6de4f3ad
AK		 689static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
690
4d56c8a7 691/*
8c06585d 692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 693 * away by decrementing the array size.
694 */
6aa8b732 695static const u32 vmx_msr_index[] = {
05b3e0c2 696#ifdef CONFIG_X86_64
44ea2b17 697 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 698#endif
8c06585d 699 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 700};
9d8f549d 701#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 702
31299944 703static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 704{
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
706 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 707 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 708}
709
31299944 710static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 711{
712 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
713 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 714 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 715}
716
31299944 717static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 718{
719 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
720 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 721 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 722}
723
31299944 724static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 725{
726 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
727 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
728}
729
31299944 730static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 731{
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
733 INTR_INFO_VALID_MASK)) ==
734 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
735}
736
31299944 737static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 738{
04547156 739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 740}
741
31299944 742static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 743{
04547156 744 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 745}
746
31299944 747static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 748{
04547156 749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 750}
751
31299944 752static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 753{
04547156
SY		 754 return vmcs_config.cpu_based_exec_ctrl &
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 756}
757
774ead3a 758static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 759{
04547156
SY		 760 return vmcs_config.cpu_based_2nd_exec_ctrl &
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
762}
763
764static inline bool cpu_has_vmx_flexpriority(void)
765{
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 768}
769
e799794e
MT		 770static inline bool cpu_has_vmx_ept_execute_only(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 773}
774
775static inline bool cpu_has_vmx_eptp_uncacheable(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 778}
779
780static inline bool cpu_has_vmx_eptp_writeback(void)
781{
31299944 782 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 783}
784
785static inline bool cpu_has_vmx_ept_2m_page(void)
786{
31299944 787 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 788}
789
878403b7
SY		 790static inline bool cpu_has_vmx_ept_1g_page(void)
791{
31299944 792 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 793}
794
4bc9b982
SY		 795static inline bool cpu_has_vmx_ept_4levels(void)
796{
797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
798}
799
83c3a331
XH		 800static inline bool cpu_has_vmx_ept_ad_bits(void)
801{
802 return vmx_capability.ept & VMX_EPT_AD_BIT;
803}
804
31299944 805static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 806{
31299944 807 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 808}
809
31299944 810static inline bool cpu_has_vmx_invept_context(void)
d56f546d 811{
31299944 812 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 813}
814
31299944 815static inline bool cpu_has_vmx_invept_global(void)
d56f546d 816{
31299944 817 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 818}
819
518c8aee
GJ		 820static inline bool cpu_has_vmx_invvpid_single(void)
821{
822 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
823}
824
b9d762fa
GJ		 825static inline bool cpu_has_vmx_invvpid_global(void)
826{
827 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
828}
829
31299944 830static inline bool cpu_has_vmx_ept(void)
d56f546d 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_UNRESTRICTED_GUEST;
840}
841
31299944 842static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 843{
844 return vmcs_config.cpu_based_2nd_exec_ctrl &
845 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
846}
847
31299944 848static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 849{
6d3e435e 850 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 851}
852
31299944 853static inline bool cpu_has_vmx_vpid(void)
2384d2b3 854{
04547156
SY		 855 return vmcs_config.cpu_based_2nd_exec_ctrl &
856 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 857}
858
31299944 859static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 860{
861 return vmcs_config.cpu_based_2nd_exec_ctrl &
862 SECONDARY_EXEC_RDTSCP;
863}
864
ad756a16
MJ		 865static inline bool cpu_has_vmx_invpcid(void)
866{
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_ENABLE_INVPCID;
869}
870
31299944 871static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 872{
873 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
874}
875
f5f48ee1
SY		 876static inline bool cpu_has_vmx_wbinvd_exit(void)
877{
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_WBINVD_EXITING;
880}
881
04547156
SY		 882static inline bool report_flexpriority(void)
883{
884 return flexpriority_enabled;
885}
886
fe3ef05c
NHE		 887static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
888{
889 return vmcs12->cpu_based_vm_exec_control & bit;
890}
891
892static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
893{
894 return (vmcs12->cpu_based_vm_exec_control &
895 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
896 (vmcs12->secondary_vm_exec_control & bit);
897}
898
644d711a
NHE		 899static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
900 struct kvm_vcpu *vcpu)
901{
902 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
903}
904
905static inline bool is_exception(u32 intr_info)
906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
908 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
909}
910
911static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 912static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
913 struct vmcs12 *vmcs12,
914 u32 reason, unsigned long qualification);
915
8b9cf98c 916static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 917{
918 int i;
919
a2fa3e9f 920 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 921 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 922 return i;
923 return -1;
924}
925
2384d2b3
SY		 926static inline void __invvpid(int ext, u16 vpid, gva_t gva)
927{
928 struct {
929 u64 vpid : 16;
930 u64 rsvd : 48;
931 u64 gva;
932 } operand = { vpid, 0, gva };
933
4ecac3fd 934 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 935 /* CF==1 or ZF==1 --> rc = -1 */
936 "; ja 1f ; ud2 ; 1:"
937 : : "a"(&operand), "c"(ext) : "cc", "memory");
938}
939
1439442c
SY		 940static inline void __invept(int ext, u64 eptp, gpa_t gpa)
941{
942 struct {
943 u64 eptp, gpa;
944 } operand = {eptp, gpa};
945
4ecac3fd 946 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 947 /* CF==1 or ZF==1 --> rc = -1 */
948 "; ja 1f ; ud2 ; 1:\n"
949 : : "a" (&operand), "c" (ext) : "cc", "memory");
950}
951
26bb0981 952static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 953{
954 int i;
955
8b9cf98c 956 i = __find_msr_index(vmx, msr);
a75beee6 957 if (i >= 0)
a2fa3e9f 958 return &vmx->guest_msrs[i];
8b6d44c7 959 return NULL;
7725f0ba
AK		 960}
961
6aa8b732
AK		 962static void vmcs_clear(struct vmcs *vmcs)
963{
964 u64 phys_addr = __pa(vmcs);
965 u8 error;
966
4ecac3fd 967 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 968 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 969 : "cc", "memory");
970 if (error)
971 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
972 vmcs, phys_addr);
973}
974
d462b819
NHE		 975static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
976{
977 vmcs_clear(loaded_vmcs->vmcs);
978 loaded_vmcs->cpu = -1;
979 loaded_vmcs->launched = 0;
980}
981
7725b894
DX		 982static void vmcs_load(struct vmcs *vmcs)
983{
984 u64 phys_addr = __pa(vmcs);
985 u8 error;
986
987 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 988 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 989 : "cc", "memory");
990 if (error)
2844d849 991 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 992 vmcs, phys_addr);
993}
994
d462b819 995static void __loaded_vmcs_clear(void *arg)
6aa8b732 996{
d462b819 997 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 998 int cpu = raw_smp_processor_id();
6aa8b732 999
d462b819
NHE		 1000 if (loaded_vmcs->cpu != cpu)
1001 return; /* vcpu migration can race with cpu offline */
1002 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1003 per_cpu(current_vmcs, cpu) = NULL;
d462b819 1004 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1005
1006 /*
1007 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1008 * is before setting loaded_vmcs->vcpu to -1 which is done in
1009 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1010 * then adds the vmcs into percpu list before it is deleted.
1011 */
1012 smp_wmb();
1013
d462b819 1014 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 1015}
1016
d462b819 1017static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1018{
e6c7d321
XG		 1019 int cpu = loaded_vmcs->cpu;
1020
1021 if (cpu != -1)
1022 smp_call_function_single(cpu,
1023 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1024}
1025
1760dd49 1026static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1027{
1028 if (vmx->vpid == 0)
1029 return;
1030
518c8aee
GJ		 1031 if (cpu_has_vmx_invvpid_single())
1032 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1033}
1034
b9d762fa
GJ		 1035static inline void vpid_sync_vcpu_global(void)
1036{
1037 if (cpu_has_vmx_invvpid_global())
1038 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1039}
1040
1041static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1042{
1043 if (cpu_has_vmx_invvpid_single())
1760dd49 1044 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1045 else
1046 vpid_sync_vcpu_global();
1047}
1048
1439442c
SY		 1049static inline void ept_sync_global(void)
1050{
1051 if (cpu_has_vmx_invept_global())
1052 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1053}
1054
1055static inline void ept_sync_context(u64 eptp)
1056{
089d034e 1057 if (enable_ept) {
1439442c
SY		 1058 if (cpu_has_vmx_invept_context())
1059 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1060 else
1061 ept_sync_global();
1062 }
1063}
1064
1065static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1066{
089d034e 1067 if (enable_ept) {
1439442c
SY		 1068 if (cpu_has_vmx_invept_individual_addr())
1069 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1070 eptp, gpa);
1071 else
1072 ept_sync_context(eptp);
1073 }
1074}
1075
96304217 1076static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1077{
5e520e62 1078 unsigned long value;
6aa8b732 1079
5e520e62
AK		 1080 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1081 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1082 return value;
1083}
1084
96304217 1085static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1086{
1087 return vmcs_readl(field);
1088}
1089
96304217 1090static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1091{
1092 return vmcs_readl(field);
1093}
1094
96304217 1095static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1096{
05b3e0c2 1097#ifdef CONFIG_X86_64
6aa8b732
AK		 1098 return vmcs_readl(field);
1099#else
1100 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1101#endif
1102}
1103
e52de1b8
AK		 1104static noinline void vmwrite_error(unsigned long field, unsigned long value)
1105{
1106 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1107 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1108 dump_stack();
1109}
1110
6aa8b732
AK		 1111static void vmcs_writel(unsigned long field, unsigned long value)
1112{
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1116 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1117 if (unlikely(error))
1118 vmwrite_error(field, value);
6aa8b732
AK		 1119}
1120
1121static void vmcs_write16(unsigned long field, u16 value)
1122{
1123 vmcs_writel(field, value);
1124}
1125
1126static void vmcs_write32(unsigned long field, u32 value)
1127{
1128 vmcs_writel(field, value);
1129}
1130
1131static void vmcs_write64(unsigned long field, u64 value)
1132{
6aa8b732 1133 vmcs_writel(field, value);
7682f2d0 1134#ifndef CONFIG_X86_64
6aa8b732
AK		 1135 asm volatile ("");
1136 vmcs_writel(field+1, value >> 32);
1137#endif
1138}
1139
2ab455cc
AL		 1140static void vmcs_clear_bits(unsigned long field, u32 mask)
1141{
1142 vmcs_writel(field, vmcs_readl(field) & ~mask);
1143}
1144
1145static void vmcs_set_bits(unsigned long field, u32 mask)
1146{
1147 vmcs_writel(field, vmcs_readl(field) | mask);
1148}
1149
2fb92db1
AK		 1150static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1151{
1152 vmx->segment_cache.bitmask = 0;
1153}
1154
1155static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1156 unsigned field)
1157{
1158 bool ret;
1159 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1160
1161 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1162 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1163 vmx->segment_cache.bitmask = 0;
1164 }
1165 ret = vmx->segment_cache.bitmask & mask;
1166 vmx->segment_cache.bitmask |= mask;
1167 return ret;
1168}
1169
1170static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1171{
1172 u16 *p = &vmx->segment_cache.seg[seg].selector;
1173
1174 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1175 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1176 return *p;
1177}
1178
1179static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1180{
1181 ulong *p = &vmx->segment_cache.seg[seg].base;
1182
1183 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1184 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1185 return *p;
1186}
1187
1188static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1189{
1190 u32 *p = &vmx->segment_cache.seg[seg].limit;
1191
1192 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1193 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1194 return *p;
1195}
1196
1197static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1198{
1199 u32 *p = &vmx->segment_cache.seg[seg].ar;
1200
1201 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1202 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1203 return *p;
1204}
1205
abd3f2d6
AK		 1206static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1207{
1208 u32 eb;
1209
fd7373cc
JK		 1210 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1211 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1212 if ((vcpu->guest_debug &
1213 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1214 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1215 eb |= 1u << BP_VECTOR;
7ffd92c5 1216 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1217 eb = ~0;
089d034e 1218 if (enable_ept)
1439442c 1219 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1220 if (vcpu->fpu_active)
1221 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1222
1223 /* When we are running a nested L2 guest and L1 specified for it a
1224 * certain exception bitmap, we must trap the same exceptions and pass
1225 * them to L1. When running L2, we will only handle the exceptions
1226 * specified above if L1 did not want them.
1227 */
1228 if (is_guest_mode(vcpu))
1229 eb |= get_vmcs12(vcpu)->exception_bitmap;
1230
abd3f2d6
AK		 1231 vmcs_write32(EXCEPTION_BITMAP, eb);
1232}
1233
8bf00a52
GN		 1234static void clear_atomic_switch_msr_special(unsigned long entry,
1235 unsigned long exit)
1236{
1237 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1238 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1239}
1240
61d2ef2c
AK		 1241static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1242{
1243 unsigned i;
1244 struct msr_autoload *m = &vmx->msr_autoload;
1245
8bf00a52
GN		 1246 switch (msr) {
1247 case MSR_EFER:
1248 if (cpu_has_load_ia32_efer) {
1249 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1250 VM_EXIT_LOAD_IA32_EFER);
1251 return;
1252 }
1253 break;
1254 case MSR_CORE_PERF_GLOBAL_CTRL:
1255 if (cpu_has_load_perf_global_ctrl) {
1256 clear_atomic_switch_msr_special(
1257 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1258 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1259 return;
1260 }
1261 break;
110312c8
AK		 1262 }
1263
61d2ef2c
AK		 1264 for (i = 0; i < m->nr; ++i)
1265 if (m->guest[i].index == msr)
1266 break;
1267
1268 if (i == m->nr)
1269 return;
1270 --m->nr;
1271 m->guest[i] = m->guest[m->nr];
1272 m->host[i] = m->host[m->nr];
1273 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1274 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1275}
1276
8bf00a52
GN		 1277static void add_atomic_switch_msr_special(unsigned long entry,
1278 unsigned long exit, unsigned long guest_val_vmcs,
1279 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1280{
1281 vmcs_write64(guest_val_vmcs, guest_val);
1282 vmcs_write64(host_val_vmcs, host_val);
1283 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1284 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1285}
1286
61d2ef2c
AK		 1287static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1288 u64 guest_val, u64 host_val)
1289{
1290 unsigned i;
1291 struct msr_autoload *m = &vmx->msr_autoload;
1292
8bf00a52
GN		 1293 switch (msr) {
1294 case MSR_EFER:
1295 if (cpu_has_load_ia32_efer) {
1296 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297 VM_EXIT_LOAD_IA32_EFER,
1298 GUEST_IA32_EFER,
1299 HOST_IA32_EFER,
1300 guest_val, host_val);
1301 return;
1302 }
1303 break;
1304 case MSR_CORE_PERF_GLOBAL_CTRL:
1305 if (cpu_has_load_perf_global_ctrl) {
1306 add_atomic_switch_msr_special(
1307 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1308 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1309 GUEST_IA32_PERF_GLOBAL_CTRL,
1310 HOST_IA32_PERF_GLOBAL_CTRL,
1311 guest_val, host_val);
1312 return;
1313 }
1314 break;
110312c8
AK		 1315 }
1316
61d2ef2c
AK		 1317 for (i = 0; i < m->nr; ++i)
1318 if (m->guest[i].index == msr)
1319 break;
1320
e7fc6f93
GN		 1321 if (i == NR_AUTOLOAD_MSRS) {
1322 printk_once(KERN_WARNING"Not enough mst switch entries. "
1323 "Can't add msr %x\n", msr);
1324 return;
1325 } else if (i == m->nr) {
61d2ef2c
AK		 1326 ++m->nr;
1327 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1328 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1329 }
1330
1331 m->guest[i].index = msr;
1332 m->guest[i].value = guest_val;
1333 m->host[i].index = msr;
1334 m->host[i].value = host_val;
1335}
1336
33ed6329
AK		 1337static void reload_tss(void)
1338{
33ed6329
AK		 1339 /*
1340 * VT restores TR but not its size. Useless.
1341 */
d359192f 1342 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1343 struct desc_struct *descs;
33ed6329 1344
d359192f 1345 descs = (void *)gdt->address;
33ed6329
AK		 1346 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1347 load_TR_desc();
33ed6329
AK		 1348}
1349
92c0d900 1350static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1351{
3a34a881 1352 u64 guest_efer;
51c6cf66
AK		 1353 u64 ignore_bits;
1354
f6801dff 1355 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1356
51c6cf66 1357 /*
0fa06071 1358 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1359 * outside long mode
1360 */
1361 ignore_bits = EFER_NX | EFER_SCE;
1362#ifdef CONFIG_X86_64
1363 ignore_bits |= EFER_LMA | EFER_LME;
1364 /* SCE is meaningful only in long mode on Intel */
1365 if (guest_efer & EFER_LMA)
1366 ignore_bits &= ~(u64)EFER_SCE;
1367#endif
51c6cf66
AK		 1368 guest_efer &= ~ignore_bits;
1369 guest_efer |= host_efer & ignore_bits;
26bb0981 1370 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1371 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1372
1373 clear_atomic_switch_msr(vmx, MSR_EFER);
1374 /* On ept, can't emulate nx, and must switch nx atomically */
1375 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1376 guest_efer = vmx->vcpu.arch.efer;
1377 if (!(guest_efer & EFER_LMA))
1378 guest_efer &= ~EFER_LME;
1379 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1380 return false;
1381 }
1382
26bb0981 1383 return true;
51c6cf66
AK		 1384}
1385
2d49ec72
GN		 1386static unsigned long segment_base(u16 selector)
1387{
d359192f 1388 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1389 struct desc_struct *d;
1390 unsigned long table_base;
1391 unsigned long v;
1392
1393 if (!(selector & ~3))
1394 return 0;
1395
d359192f 1396 table_base = gdt->address;
2d49ec72
GN		 1397
1398 if (selector & 4) { /* from ldt */
1399 u16 ldt_selector = kvm_read_ldt();
1400
1401 if (!(ldt_selector & ~3))
1402 return 0;
1403
1404 table_base = segment_base(ldt_selector);
1405 }
1406 d = (struct desc_struct *)(table_base + (selector & ~7));
1407 v = get_desc_base(d);
1408#ifdef CONFIG_X86_64
1409 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1410 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1411#endif
1412 return v;
1413}
1414
1415static inline unsigned long kvm_read_tr_base(void)
1416{
1417 u16 tr;
1418 asm("str %0" : "=g"(tr));
1419 return segment_base(tr);
1420}
1421
04d2cc77 1422static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1423{
04d2cc77 1424 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1425 int i;
04d2cc77 1426
a2fa3e9f 1427 if (vmx->host_state.loaded)
33ed6329
AK		 1428 return;
1429
a2fa3e9f 1430 vmx->host_state.loaded = 1;
33ed6329
AK		 1431 /*
1432 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1433 * allow segment selectors with cpl > 0 or ti == 1.
1434 */
d6e88aec 1435 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1436 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1437 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1438 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1439 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1440 vmx->host_state.fs_reload_needed = 0;
1441 } else {
33ed6329 1442 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1443 vmx->host_state.fs_reload_needed = 1;
33ed6329 1444 }
9581d442 1445 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1446 if (!(vmx->host_state.gs_sel & 7))
1447 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1448 else {
1449 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1450 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1451 }
1452
b2da15ac
AK		 1453#ifdef CONFIG_X86_64
1454 savesegment(ds, vmx->host_state.ds_sel);
1455 savesegment(es, vmx->host_state.es_sel);
1456#endif
1457
33ed6329
AK		 1458#ifdef CONFIG_X86_64
1459 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1460 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1461#else
a2fa3e9f
GH		 1462 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1463 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1464#endif
707c0874
AK		 1465
1466#ifdef CONFIG_X86_64
c8770e7b
AK		 1467 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1468 if (is_long_mode(&vmx->vcpu))
44ea2b17 1469 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1470#endif
26bb0981
AK		 1471 for (i = 0; i < vmx->save_nmsrs; ++i)
1472 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1473 vmx->guest_msrs[i].data,
1474 vmx->guest_msrs[i].mask);
33ed6329
AK		 1475}
1476
a9b21b62 1477static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1478{
a2fa3e9f 1479 if (!vmx->host_state.loaded)
33ed6329
AK		 1480 return;
1481
e1beb1d3 1482 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1483 vmx->host_state.loaded = 0;
c8770e7b
AK		 1484#ifdef CONFIG_X86_64
1485 if (is_long_mode(&vmx->vcpu))
1486 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1487#endif
152d3f2f 1488 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1489 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1490#ifdef CONFIG_X86_64
9581d442 1491 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1492#else
1493 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1494#endif
33ed6329 1495 }
0a77fe4c
AK		 1496 if (vmx->host_state.fs_reload_needed)
1497 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1498#ifdef CONFIG_X86_64
1499 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1500 loadsegment(ds, vmx->host_state.ds_sel);
1501 loadsegment(es, vmx->host_state.es_sel);
1502 }
b2da15ac 1503#endif
152d3f2f 1504 reload_tss();
44ea2b17 1505#ifdef CONFIG_X86_64
c8770e7b 1506 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1507#endif
b1a74bf8
SS		 1508 /*
1509 * If the FPU is not active (through the host task or
1510 * the guest vcpu), then restore the cr0.TS bit.
1511 */
1512 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1513 stts();
3444d7da 1514 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1515}
1516
a9b21b62
AK		 1517static void vmx_load_host_state(struct vcpu_vmx *vmx)
1518{
1519 preempt_disable();
1520 __vmx_load_host_state(vmx);
1521 preempt_enable();
1522}
1523
6aa8b732
AK		 1524/*
1525 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1526 * vcpu mutex is already taken.
1527 */
15ad7146 1528static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1529{
a2fa3e9f 1530 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1531 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1532
4610c9cc
DX		 1533 if (!vmm_exclusive)
1534 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1535 else if (vmx->loaded_vmcs->cpu != cpu)
1536 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1537
d462b819
NHE		 1538 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1539 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1540 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1541 }
1542
d462b819 1543 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1544 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1545 unsigned long sysenter_esp;
1546
a8eeb04a 1547 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1548 local_irq_disable();
5a560f8b
XG		 1549
1550 /*
1551 * Read loaded_vmcs->cpu should be before fetching
1552 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1553 * See the comments in __loaded_vmcs_clear().
1554 */
1555 smp_rmb();
1556
d462b819
NHE		 1557 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1558 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1559 local_irq_enable();
1560
6aa8b732
AK		 1561 /*
1562 * Linux uses per-cpu TSS and GDT, so set these when switching
1563 * processors.
1564 */
d6e88aec 1565 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1566 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1567
1568 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1569 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1570 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1571 }
6aa8b732
AK		 1572}
1573
1574static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1575{
a9b21b62 1576 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1577 if (!vmm_exclusive) {
d462b819
NHE		 1578 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1579 vcpu->cpu = -1;
4610c9cc
DX		 1580 kvm_cpu_vmxoff();
1581 }
6aa8b732
AK		 1582}
1583
5fd86fcf
AK		 1584static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1585{
81231c69
AK		 1586 ulong cr0;
1587
5fd86fcf
AK		 1588 if (vcpu->fpu_active)
1589 return;
1590 vcpu->fpu_active = 1;
81231c69
AK		 1591 cr0 = vmcs_readl(GUEST_CR0);
1592 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1593 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1594 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1595 update_exception_bitmap(vcpu);
edcafe3c 1596 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1597 if (is_guest_mode(vcpu))
1598 vcpu->arch.cr0_guest_owned_bits &=
1599 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1600 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1601}
1602
edcafe3c
AK		 1603static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1604
fe3ef05c
NHE		 1605/*
1606 * Return the cr0 value that a nested guest would read. This is a combination
1607 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1608 * its hypervisor (cr0_read_shadow).
1609 */
1610static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1611{
1612 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1613 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1614}
1615static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1616{
1617 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1618 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1619}
1620
5fd86fcf
AK		 1621static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1622{
36cf24e0
NHE		 1623 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1624 * set this *before* calling this function.
1625 */
edcafe3c 1626 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1627 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1628 update_exception_bitmap(vcpu);
edcafe3c
AK		 1629 vcpu->arch.cr0_guest_owned_bits = 0;
1630 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1631 if (is_guest_mode(vcpu)) {
1632 /*
1633 * L1's specified read shadow might not contain the TS bit,
1634 * so now that we turned on shadowing of this bit, we need to
1635 * set this bit of the shadow. Like in nested_vmx_run we need
1636 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1637 * up-to-date here because we just decached cr0.TS (and we'll
1638 * only update vmcs12->guest_cr0 on nested exit).
1639 */
1640 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1641 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1642 (vcpu->arch.cr0 & X86_CR0_TS);
1643 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1644 } else
1645 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1646}
1647
6aa8b732
AK		 1648static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1649{
78ac8b47 1650 unsigned long rflags, save_rflags;
345dcaa8 1651
6de12732
AK		 1652 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1653 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1654 rflags = vmcs_readl(GUEST_RFLAGS);
1655 if (to_vmx(vcpu)->rmode.vm86_active) {
1656 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1657 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1658 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1659 }
1660 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1661 }
6de12732 1662 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1663}
1664
1665static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1666{
6de12732 1667 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1668 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1669 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1670 if (to_vmx(vcpu)->rmode.vm86_active) {
1671 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1672 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1673 }
6aa8b732
AK		 1674 vmcs_writel(GUEST_RFLAGS, rflags);
1675}
1676
2809f5d2
GC		 1677static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1678{
1679 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1680 int ret = 0;
1681
1682 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1683 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1684 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1685 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1686
1687 return ret & mask;
1688}
1689
1690static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1691{
1692 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1693 u32 interruptibility = interruptibility_old;
1694
1695 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1696
48005f64 1697 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1698 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1699 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1700 interruptibility |= GUEST_INTR_STATE_STI;
1701
1702 if ((interruptibility != interruptibility_old))
1703 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1704}
1705
6aa8b732
AK		 1706static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1707{
1708 unsigned long rip;
6aa8b732 1709
5fdbf976 1710 rip = kvm_rip_read(vcpu);
6aa8b732 1711 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1712 kvm_rip_write(vcpu, rip);
6aa8b732 1713
2809f5d2
GC		 1714 /* skipping an emulated instruction also counts */
1715 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1716}
1717
0b6ac343
NHE		 1718/*
1719 * KVM wants to inject page-faults which it got to the guest. This function
1720 * checks whether in a nested guest, we need to inject them to L1 or L2.
1721 * This function assumes it is called with the exit reason in vmcs02 being
1722 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1723 * is running).
1724 */
1725static int nested_pf_handled(struct kvm_vcpu *vcpu)
1726{
1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728
1729 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1730 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1731 return 0;
1732
1733 nested_vmx_vmexit(vcpu);
1734 return 1;
1735}
1736
298101da 1737static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1738 bool has_error_code, u32 error_code,
1739 bool reinject)
298101da 1740{
77ab6db0 1741 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1742 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1743
0b6ac343
NHE		 1744 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1745 nested_pf_handled(vcpu))
1746 return;
1747
8ab2d2e2 1748 if (has_error_code) {
77ab6db0 1749 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1750 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1751 }
77ab6db0 1752
7ffd92c5 1753 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1754 int inc_eip = 0;
1755 if (kvm_exception_is_soft(nr))
1756 inc_eip = vcpu->arch.event_exit_inst_len;
1757 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1758 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1759 return;
1760 }
1761
66fd3f7f
GN		 1762 if (kvm_exception_is_soft(nr)) {
1763 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1764 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1765 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1766 } else
1767 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1768
1769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1770}
1771
4e47c7a6
SY		 1772static bool vmx_rdtscp_supported(void)
1773{
1774 return cpu_has_vmx_rdtscp();
1775}
1776
ad756a16
MJ		 1777static bool vmx_invpcid_supported(void)
1778{
1779 return cpu_has_vmx_invpcid() && enable_ept;
1780}
1781
a75beee6
ED		 1782/*
1783 * Swap MSR entry in host/guest MSR entry array.
1784 */
8b9cf98c 1785static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1786{
26bb0981 1787 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1788
1789 tmp = vmx->guest_msrs[to];
1790 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1791 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1792}
1793
e38aea3e
AK		 1794/*
1795 * Set up the vmcs to automatically save and restore system
1796 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1797 * mode, as fiddling with msrs is very expensive.
1798 */
8b9cf98c 1799static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1800{
26bb0981 1801 int save_nmsrs, index;
5897297b 1802 unsigned long *msr_bitmap;
e38aea3e 1803
a75beee6
ED		 1804 save_nmsrs = 0;
1805#ifdef CONFIG_X86_64
8b9cf98c 1806 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1807 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1808 if (index >= 0)
8b9cf98c
RR		 1809 move_msr_up(vmx, index, save_nmsrs++);
1810 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1811 if (index >= 0)
8b9cf98c
RR		 1812 move_msr_up(vmx, index, save_nmsrs++);
1813 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1814 if (index >= 0)
8b9cf98c 1815 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1816 index = __find_msr_index(vmx, MSR_TSC_AUX);
1817 if (index >= 0 && vmx->rdtscp_enabled)
1818 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1819 /*
8c06585d 1820 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1821 * if efer.sce is enabled.
1822 */
8c06585d 1823 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1824 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1825 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1826 }
1827#endif
92c0d900
AK		 1828 index = __find_msr_index(vmx, MSR_EFER);
1829 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1830 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1831
26bb0981 1832 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1833
1834 if (cpu_has_vmx_msr_bitmap()) {
1835 if (is_long_mode(&vmx->vcpu))
1836 msr_bitmap = vmx_msr_bitmap_longmode;
1837 else
1838 msr_bitmap = vmx_msr_bitmap_legacy;
1839
1840 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1841 }
e38aea3e
AK		 1842}
1843
6aa8b732
AK		 1844/*
1845 * reads and returns guest's timestamp counter "register"
1846 * guest_tsc = host_tsc + tsc_offset -- 21.3
1847 */
1848static u64 guest_read_tsc(void)
1849{
1850 u64 host_tsc, tsc_offset;
1851
1852 rdtscll(host_tsc);
1853 tsc_offset = vmcs_read64(TSC_OFFSET);
1854 return host_tsc + tsc_offset;
1855}
1856
d5c1785d
NHE		 1857/*
1858 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1859 * counter, even if a nested guest (L2) is currently running.
1860 */
886b470c 1861u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1862{
886b470c 1863 u64 tsc_offset;
d5c1785d 1864
d5c1785d
NHE		 1865 tsc_offset = is_guest_mode(vcpu) ?
1866 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1867 vmcs_read64(TSC_OFFSET);
1868 return host_tsc + tsc_offset;
1869}
1870
4051b188 1871/*
cc578287
ZA		 1872 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1873 * software catchup for faster rates on slower CPUs.
4051b188 1874 */
cc578287 1875static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1876{
cc578287
ZA		 1877 if (!scale)
1878 return;
1879
1880 if (user_tsc_khz > tsc_khz) {
1881 vcpu->arch.tsc_catchup = 1;
1882 vcpu->arch.tsc_always_catchup = 1;
1883 } else
1884 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1885}
1886
6aa8b732 1887/*
99e3e30a 1888 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1889 */
99e3e30a 1890static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1891{
27fc51b2 1892 if (is_guest_mode(vcpu)) {
7991825b 1893 /*
27fc51b2
NHE		 1894 * We're here if L1 chose not to trap WRMSR to TSC. According
1895 * to the spec, this should set L1's TSC; The offset that L1
1896 * set for L2 remains unchanged, and still needs to be added
1897 * to the newly set TSC to get L2's TSC.
7991825b 1898 */
27fc51b2
NHE		 1899 struct vmcs12 *vmcs12;
1900 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1901 /* recalculate vmcs02.TSC_OFFSET: */
1902 vmcs12 = get_vmcs12(vcpu);
1903 vmcs_write64(TSC_OFFSET, offset +
1904 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1905 vmcs12->tsc_offset : 0));
1906 } else {
1907 vmcs_write64(TSC_OFFSET, offset);
1908 }
6aa8b732
AK		 1909}
1910
f1e2b260 1911static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1912{
1913 u64 offset = vmcs_read64(TSC_OFFSET);
1914 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1915 if (is_guest_mode(vcpu)) {
1916 /* Even when running L2, the adjustment needs to apply to L1 */
1917 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1918 }
e48672fa
ZA		 1919}
1920
857e4099
JR		 1921static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1922{
1923 return target_tsc - native_read_tsc();
1924}
1925
801d3424
NHE		 1926static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1927{
1928 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1929 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1930}
1931
1932/*
1933 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1934 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1935 * all guests if the "nested" module option is off, and can also be disabled
1936 * for a single guest by disabling its VMX cpuid bit.
1937 */
1938static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1939{
1940 return nested && guest_cpuid_has_vmx(vcpu);
1941}
1942
b87a51ae
NHE		 1943/*
1944 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1945 * returned for the various VMX controls MSRs when nested VMX is enabled.
1946 * The same values should also be used to verify that vmcs12 control fields are
1947 * valid during nested entry from L1 to L2.
1948 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1949 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1950 * bit in the high half is on if the corresponding bit in the control field
1951 * may be on. See also vmx_control_verify().
1952 * TODO: allow these variables to be modified (downgraded) by module options
1953 * or other means.
1954 */
1955static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1956static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1957static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1958static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1959static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1960static __init void nested_vmx_setup_ctls_msrs(void)
1961{
1962 /*
1963 * Note that as a general rule, the high half of the MSRs (bits in
1964 * the control fields which may be 1) should be initialized by the
1965 * intersection of the underlying hardware's MSR (i.e., features which
1966 * can be supported) and the list of features we want to expose -
1967 * because they are known to be properly supported in our code.
1968 * Also, usually, the low half of the MSRs (bits which must be 1) can
1969 * be set to 0, meaning that L1 may turn off any of these bits. The
1970 * reason is that if one of these bits is necessary, it will appear
1971 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1972 * fields of vmcs01 and vmcs02, will turn these bits off - and
1973 * nested_vmx_exit_handled() will not pass related exits to L1.
1974 * These rules have exceptions below.
1975 */
1976
1977 /* pin-based controls */
1978 /*
1979 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1980 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1981 */
1982 nested_vmx_pinbased_ctls_low = 0x16 ;
1983 nested_vmx_pinbased_ctls_high = 0x16 |
1984 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1985 PIN_BASED_VIRTUAL_NMIS;
1986
1987 /* exit controls */
1988 nested_vmx_exit_ctls_low = 0;
b6f1250e 1989 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1990#ifdef CONFIG_X86_64
1991 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1992#else
1993 nested_vmx_exit_ctls_high = 0;
1994#endif
1995
1996 /* entry controls */
1997 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1998 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1999 nested_vmx_entry_ctls_low = 0;
2000 nested_vmx_entry_ctls_high &=
2001 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2002
2003 /* cpu-based controls */
2004 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2005 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2006 nested_vmx_procbased_ctls_low = 0;
2007 nested_vmx_procbased_ctls_high &=
2008 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2009 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2010 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2011 CPU_BASED_CR3_STORE_EXITING |
2012#ifdef CONFIG_X86_64
2013 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2014#endif
2015 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2016 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2017 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2018 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2019 /*
2020 * We can allow some features even when not supported by the
2021 * hardware. For example, L1 can specify an MSR bitmap - and we
2022 * can use it to avoid exits to L1 - even when L0 runs L2
2023 * without MSR bitmaps.
2024 */
2025 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2026
2027 /* secondary cpu-based controls */
2028 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2029 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2030 nested_vmx_secondary_ctls_low = 0;
2031 nested_vmx_secondary_ctls_high &=
2032 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2033}
2034
2035static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2036{
2037 /*
2038 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2039 */
2040 return ((control & high) | low) == control;
2041}
2042
2043static inline u64 vmx_control_msr(u32 low, u32 high)
2044{
2045 return low | ((u64)high << 32);
2046}
2047
2048/*
2049 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2050 * also let it use VMX-specific MSRs.
2051 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2052 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2053 * like all other MSRs).
2054 */
2055static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2056{
2057 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2058 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2059 /*
2060 * According to the spec, processors which do not support VMX
2061 * should throw a #GP(0) when VMX capability MSRs are read.
2062 */
2063 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2064 return 1;
2065 }
2066
2067 switch (msr_index) {
2068 case MSR_IA32_FEATURE_CONTROL:
2069 *pdata = 0;
2070 break;
2071 case MSR_IA32_VMX_BASIC:
2072 /*
2073 * This MSR reports some information about VMX support. We
2074 * should return information about the VMX we emulate for the
2075 * guest, and the VMCS structure we give it - not about the
2076 * VMX support of the underlying hardware.
2077 */
2078 *pdata = VMCS12_REVISION |
2079 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2080 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2081 break;
2082 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2083 case MSR_IA32_VMX_PINBASED_CTLS:
2084 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2085 nested_vmx_pinbased_ctls_high);
2086 break;
2087 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2088 case MSR_IA32_VMX_PROCBASED_CTLS:
2089 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2090 nested_vmx_procbased_ctls_high);
2091 break;
2092 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2093 case MSR_IA32_VMX_EXIT_CTLS:
2094 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2095 nested_vmx_exit_ctls_high);
2096 break;
2097 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2098 case MSR_IA32_VMX_ENTRY_CTLS:
2099 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2100 nested_vmx_entry_ctls_high);
2101 break;
2102 case MSR_IA32_VMX_MISC:
2103 *pdata = 0;
2104 break;
2105 /*
2106 * These MSRs specify bits which the guest must keep fixed (on or off)
2107 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2108 * We picked the standard core2 setting.
2109 */
2110#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2111#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2112 case MSR_IA32_VMX_CR0_FIXED0:
2113 *pdata = VMXON_CR0_ALWAYSON;
2114 break;
2115 case MSR_IA32_VMX_CR0_FIXED1:
2116 *pdata = -1ULL;
2117 break;
2118 case MSR_IA32_VMX_CR4_FIXED0:
2119 *pdata = VMXON_CR4_ALWAYSON;
2120 break;
2121 case MSR_IA32_VMX_CR4_FIXED1:
2122 *pdata = -1ULL;
2123 break;
2124 case MSR_IA32_VMX_VMCS_ENUM:
2125 *pdata = 0x1f;
2126 break;
2127 case MSR_IA32_VMX_PROCBASED_CTLS2:
2128 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2129 nested_vmx_secondary_ctls_high);
2130 break;
2131 case MSR_IA32_VMX_EPT_VPID_CAP:
2132 /* Currently, no nested ept or nested vpid */
2133 *pdata = 0;
2134 break;
2135 default:
2136 return 0;
2137 }
2138
2139 return 1;
2140}
2141
2142static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2143{
2144 if (!nested_vmx_allowed(vcpu))
2145 return 0;
2146
2147 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2148 /* TODO: the right thing. */
2149 return 1;
2150 /*
2151 * No need to treat VMX capability MSRs specially: If we don't handle
2152 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2153 */
2154 return 0;
2155}
2156
6aa8b732
AK		 2157/*
2158 * Reads an msr value (of 'msr_index') into 'pdata'.
2159 * Returns 0 on success, non-0 otherwise.
2160 * Assumes vcpu_load() was already called.
2161 */
2162static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2163{
2164 u64 data;
26bb0981 2165 struct shared_msr_entry *msr;
6aa8b732
AK		 2166
2167 if (!pdata) {
2168 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2169 return -EINVAL;
2170 }
2171
2172 switch (msr_index) {
05b3e0c2 2173#ifdef CONFIG_X86_64
6aa8b732
AK		 2174 case MSR_FS_BASE:
2175 data = vmcs_readl(GUEST_FS_BASE);
2176 break;
2177 case MSR_GS_BASE:
2178 data = vmcs_readl(GUEST_GS_BASE);
2179 break;
44ea2b17
AK		 2180 case MSR_KERNEL_GS_BASE:
2181 vmx_load_host_state(to_vmx(vcpu));
2182 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2183 break;
26bb0981 2184#endif
6aa8b732 2185 case MSR_EFER:
3bab1f5d 2186 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2187 case MSR_IA32_TSC:
6aa8b732
AK		 2188 data = guest_read_tsc();
2189 break;
2190 case MSR_IA32_SYSENTER_CS:
2191 data = vmcs_read32(GUEST_SYSENTER_CS);
2192 break;
2193 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2194 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2195 break;
2196 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2197 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2198 break;
4e47c7a6
SY		 2199 case MSR_TSC_AUX:
2200 if (!to_vmx(vcpu)->rdtscp_enabled)
2201 return 1;
2202 /* Otherwise falls through */
6aa8b732 2203 default:
b87a51ae
NHE		 2204 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2205 return 0;
8b9cf98c 2206 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2207 if (msr) {
2208 data = msr->data;
2209 break;
6aa8b732 2210 }
3bab1f5d 2211 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2212 }
2213
2214 *pdata = data;
2215 return 0;
2216}
2217
2218/*
2219 * Writes msr value into into the appropriate "register".
2220 * Returns 0 on success, non-0 otherwise.
2221 * Assumes vcpu_load() was already called.
2222 */
2223static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2224{
a2fa3e9f 2225 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2226 struct shared_msr_entry *msr;
2cc51560
ED		 2227 int ret = 0;
2228
6aa8b732 2229 switch (msr_index) {
3bab1f5d 2230 case MSR_EFER:
2cc51560 2231 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2232 break;
16175a79 2233#ifdef CONFIG_X86_64
6aa8b732 2234 case MSR_FS_BASE:
2fb92db1 2235 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2236 vmcs_writel(GUEST_FS_BASE, data);
2237 break;
2238 case MSR_GS_BASE:
2fb92db1 2239 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2240 vmcs_writel(GUEST_GS_BASE, data);
2241 break;
44ea2b17
AK		 2242 case MSR_KERNEL_GS_BASE:
2243 vmx_load_host_state(vmx);
2244 vmx->msr_guest_kernel_gs_base = data;
2245 break;
6aa8b732
AK		 2246#endif
2247 case MSR_IA32_SYSENTER_CS:
2248 vmcs_write32(GUEST_SYSENTER_CS, data);
2249 break;
2250 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2251 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2252 break;
2253 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2254 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2255 break;
af24a4e4 2256 case MSR_IA32_TSC:
99e3e30a 2257 kvm_write_tsc(vcpu, data);
6aa8b732 2258 break;
468d472f
SY		 2259 case MSR_IA32_CR_PAT:
2260 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2261 vmcs_write64(GUEST_IA32_PAT, data);
2262 vcpu->arch.pat = data;
2263 break;
2264 }
4e47c7a6
SY		 2265 ret = kvm_set_msr_common(vcpu, msr_index, data);
2266 break;
2267 case MSR_TSC_AUX:
2268 if (!vmx->rdtscp_enabled)
2269 return 1;
2270 /* Check reserved bit, higher 32 bits should be zero */
2271 if ((data >> 32) != 0)
2272 return 1;
2273 /* Otherwise falls through */
6aa8b732 2274 default:
b87a51ae
NHE		 2275 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2276 break;
8b9cf98c 2277 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2278 if (msr) {
2279 msr->data = data;
2225fd56
AK		 2280 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2281 preempt_disable();
9ee73970
AK		 2282 kvm_set_shared_msr(msr->index, msr->data,
2283 msr->mask);
2225fd56
AK		 2284 preempt_enable();
2285 }
3bab1f5d 2286 break;
6aa8b732 2287 }
2cc51560 2288 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2289 }
2290
2cc51560 2291 return ret;
6aa8b732
AK		 2292}
2293
5fdbf976 2294static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2295{
5fdbf976
MT		 2296 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2297 switch (reg) {
2298 case VCPU_REGS_RSP:
2299 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2300 break;
2301 case VCPU_REGS_RIP:
2302 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2303 break;
6de4f3ad
AK		 2304 case VCPU_EXREG_PDPTR:
2305 if (enable_ept)
2306 ept_save_pdptrs(vcpu);
2307 break;
5fdbf976
MT		 2308 default:
2309 break;
2310 }
6aa8b732
AK		 2311}
2312
6aa8b732
AK		 2313static __init int cpu_has_kvm_support(void)
2314{
6210e37b 2315 return cpu_has_vmx();
6aa8b732
AK		 2316}
2317
2318static __init int vmx_disabled_by_bios(void)
2319{
2320 u64 msr;
2321
2322 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2323 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2324 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2325 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2326 && tboot_enabled())
2327 return 1;
23f3e991 2328 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2329 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2330 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2331 && !tboot_enabled()) {
2332 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2333 "activate TXT before enabling KVM\n");
cafd6659 2334 return 1;
f9335afe 2335 }
23f3e991
JC		 2336 /* launched w/o TXT and VMX disabled */
2337 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2338 && !tboot_enabled())
2339 return 1;
cafd6659
SW		 2340 }
2341
2342 return 0;
6aa8b732
AK		 2343}
2344
7725b894
DX		 2345static void kvm_cpu_vmxon(u64 addr)
2346{
2347 asm volatile (ASM_VMX_VMXON_RAX
2348 : : "a"(&addr), "m"(addr)
2349 : "memory", "cc");
2350}
2351
10474ae8 2352static int hardware_enable(void *garbage)
6aa8b732
AK		 2353{
2354 int cpu = raw_smp_processor_id();
2355 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2356 u64 old, test_bits;
6aa8b732 2357
10474ae8
AG		 2358 if (read_cr4() & X86_CR4_VMXE)
2359 return -EBUSY;
2360
d462b819 2361 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2362 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2363
2364 test_bits = FEATURE_CONTROL_LOCKED;
2365 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2366 if (tboot_enabled())
2367 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2368
2369 if ((old & test_bits) != test_bits) {
6aa8b732 2370 /* enable and lock */
cafd6659
SW		 2371 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2372 }
66aee91a 2373 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2374
4610c9cc
DX		 2375 if (vmm_exclusive) {
2376 kvm_cpu_vmxon(phys_addr);
2377 ept_sync_global();
2378 }
10474ae8 2379
3444d7da
AK		 2380 store_gdt(&__get_cpu_var(host_gdt));
2381
10474ae8 2382 return 0;
6aa8b732
AK		 2383}
2384
d462b819 2385static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2386{
2387 int cpu = raw_smp_processor_id();
d462b819 2388 struct loaded_vmcs *v, *n;
543e4243 2389
d462b819
NHE		 2390 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2391 loaded_vmcss_on_cpu_link)
2392 __loaded_vmcs_clear(v);
543e4243
AK		 2393}
2394
710ff4a8
EH		 2395
2396/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2397 * tricks.
2398 */
2399static void kvm_cpu_vmxoff(void)
6aa8b732 2400{
4ecac3fd 2401 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2402}
2403
710ff4a8
EH		 2404static void hardware_disable(void *garbage)
2405{
4610c9cc 2406 if (vmm_exclusive) {
d462b819 2407 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2408 kvm_cpu_vmxoff();
2409 }
7725b894 2410 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2411}
2412
1c3d14fe 2413static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2414 u32 msr, u32 *result)
1c3d14fe
YS		 2415{
2416 u32 vmx_msr_low, vmx_msr_high;
2417 u32 ctl = ctl_min | ctl_opt;
2418
2419 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2420
2421 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2422 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2423
2424 /* Ensure minimum (required) set of control bits are supported. */
2425 if (ctl_min & ~ctl)
002c7f7c 2426 return -EIO;
1c3d14fe
YS		 2427
2428 *result = ctl;
2429 return 0;
2430}
2431
110312c8
AK		 2432static __init bool allow_1_setting(u32 msr, u32 ctl)
2433{
2434 u32 vmx_msr_low, vmx_msr_high;
2435
2436 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2437 return vmx_msr_high & ctl;
2438}
2439
002c7f7c 2440static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2441{
2442 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2443 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2444 u32 _pin_based_exec_control = 0;
2445 u32 _cpu_based_exec_control = 0;
f78e0e2e 2446 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2447 u32 _vmexit_control = 0;
2448 u32 _vmentry_control = 0;
2449
2450 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2451 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2452 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2453 &_pin_based_exec_control) < 0)
002c7f7c 2454 return -EIO;
1c3d14fe 2455
10166744 2456 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2457#ifdef CONFIG_X86_64
2458 CPU_BASED_CR8_LOAD_EXITING |
2459 CPU_BASED_CR8_STORE_EXITING |
2460#endif
d56f546d
SY		 2461 CPU_BASED_CR3_LOAD_EXITING |
2462 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2463 CPU_BASED_USE_IO_BITMAPS |
2464 CPU_BASED_MOV_DR_EXITING |
a7052897 2465 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2466 CPU_BASED_MWAIT_EXITING |
2467 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2468 CPU_BASED_INVLPG_EXITING |
2469 CPU_BASED_RDPMC_EXITING;
443381a8 2470
f78e0e2e 2471 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2472 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2473 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2474 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2475 &_cpu_based_exec_control) < 0)
002c7f7c 2476 return -EIO;
6e5d865c
YS		 2477#ifdef CONFIG_X86_64
2478 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2479 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2480 ~CPU_BASED_CR8_STORE_EXITING;
2481#endif
f78e0e2e 2482 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2483 min2 = 0;
2484 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2485 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2486 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2487 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2488 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2489 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2490 SECONDARY_EXEC_RDTSCP |
2491 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2492 if (adjust_vmx_controls(min2, opt2,
2493 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2494 &_cpu_based_2nd_exec_control) < 0)
2495 return -EIO;
2496 }
2497#ifndef CONFIG_X86_64
2498 if (!(_cpu_based_2nd_exec_control &
2499 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2500 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2501#endif
d56f546d 2502 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2503 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2504 enabled */
5fff7d27
GN		 2505 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2506 CPU_BASED_CR3_STORE_EXITING |
2507 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2508 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2509 vmx_capability.ept, vmx_capability.vpid);
2510 }
1c3d14fe
YS		 2511
2512 min = 0;
2513#ifdef CONFIG_X86_64
2514 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2515#endif
468d472f 2516 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2517 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2518 &_vmexit_control) < 0)
002c7f7c 2519 return -EIO;
1c3d14fe 2520
468d472f
SY		 2521 min = 0;
2522 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2523 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2524 &_vmentry_control) < 0)
002c7f7c 2525 return -EIO;
6aa8b732 2526
c68876fd 2527 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2528
2529 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2530 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2531 return -EIO;
1c3d14fe
YS		 2532
2533#ifdef CONFIG_X86_64
2534 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2535 if (vmx_msr_high & (1u<<16))
002c7f7c 2536 return -EIO;
1c3d14fe
YS		 2537#endif
2538
2539 /* Require Write-Back (WB) memory type for VMCS accesses. */
2540 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2541 return -EIO;
1c3d14fe 2542
002c7f7c
YS		 2543 vmcs_conf->size = vmx_msr_high & 0x1fff;
2544 vmcs_conf->order = get_order(vmcs_config.size);
2545 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2546
002c7f7c
YS		 2547 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2548 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2549 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2550 vmcs_conf->vmexit_ctrl = _vmexit_control;
2551 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2552
110312c8
AK		 2553 cpu_has_load_ia32_efer =
2554 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2555 VM_ENTRY_LOAD_IA32_EFER)
2556 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2557 VM_EXIT_LOAD_IA32_EFER);
2558
8bf00a52
GN		 2559 cpu_has_load_perf_global_ctrl =
2560 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2561 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2562 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2563 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2564
2565 /*
2566 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2567 * but due to arrata below it can't be used. Workaround is to use
2568 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2569 *
2570 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2571 *
2572 * AAK155 (model 26)
2573 * AAP115 (model 30)
2574 * AAT100 (model 37)
2575 * BC86,AAY89,BD102 (model 44)
2576 * BA97 (model 46)
2577 *
2578 */
2579 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2580 switch (boot_cpu_data.x86_model) {
2581 case 26:
2582 case 30:
2583 case 37:
2584 case 44:
2585 case 46:
2586 cpu_has_load_perf_global_ctrl = false;
2587 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2588 "does not work properly. Using workaround\n");
2589 break;
2590 default:
2591 break;
2592 }
2593 }
2594
1c3d14fe 2595 return 0;
c68876fd 2596}
6aa8b732
AK		 2597
2598static struct vmcs *alloc_vmcs_cpu(int cpu)
2599{
2600 int node = cpu_to_node(cpu);
2601 struct page *pages;
2602 struct vmcs *vmcs;
2603
6484eb3e 2604 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2605 if (!pages)
2606 return NULL;
2607 vmcs = page_address(pages);
1c3d14fe
YS		 2608 memset(vmcs, 0, vmcs_config.size);
2609 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2610 return vmcs;
2611}
2612
2613static struct vmcs *alloc_vmcs(void)
2614{
d3b2c338 2615 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2616}
2617
2618static void free_vmcs(struct vmcs *vmcs)
2619{
1c3d14fe 2620 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2621}
2622
d462b819
NHE		 2623/*
2624 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2625 */
2626static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2627{
2628 if (!loaded_vmcs->vmcs)
2629 return;
2630 loaded_vmcs_clear(loaded_vmcs);
2631 free_vmcs(loaded_vmcs->vmcs);
2632 loaded_vmcs->vmcs = NULL;
2633}
2634
39959588 2635static void free_kvm_area(void)
6aa8b732
AK		 2636{
2637 int cpu;
2638
3230bb47 2639 for_each_possible_cpu(cpu) {
6aa8b732 2640 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2641 per_cpu(vmxarea, cpu) = NULL;
2642 }
6aa8b732
AK		 2643}
2644
6aa8b732
AK		 2645static __init int alloc_kvm_area(void)
2646{
2647 int cpu;
2648
3230bb47 2649 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2650 struct vmcs *vmcs;
2651
2652 vmcs = alloc_vmcs_cpu(cpu);
2653 if (!vmcs) {
2654 free_kvm_area();
2655 return -ENOMEM;
2656 }
2657
2658 per_cpu(vmxarea, cpu) = vmcs;
2659 }
2660 return 0;
2661}
2662
2663static __init int hardware_setup(void)
2664{
002c7f7c
YS		 2665 if (setup_vmcs_config(&vmcs_config) < 0)
2666 return -EIO;
50a37eb4
JR		 2667
2668 if (boot_cpu_has(X86_FEATURE_NX))
2669 kvm_enable_efer_bits(EFER_NX);
2670
93ba03c2
SY		 2671 if (!cpu_has_vmx_vpid())
2672 enable_vpid = 0;
2673
4bc9b982
SY		 2674 if (!cpu_has_vmx_ept() ||
2675 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2676 enable_ept = 0;
3a624e29 2677 enable_unrestricted_guest = 0;
83c3a331 2678 enable_ept_ad_bits = 0;
3a624e29
NK		 2679 }
2680
83c3a331
XH		 2681 if (!cpu_has_vmx_ept_ad_bits())
2682 enable_ept_ad_bits = 0;
2683
3a624e29
NK		 2684 if (!cpu_has_vmx_unrestricted_guest())
2685 enable_unrestricted_guest = 0;
93ba03c2
SY		 2686
2687 if (!cpu_has_vmx_flexpriority())
2688 flexpriority_enabled = 0;
2689
95ba8273
GN		 2690 if (!cpu_has_vmx_tpr_shadow())
2691 kvm_x86_ops->update_cr8_intercept = NULL;
2692
54dee993
MT		 2693 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2694 kvm_disable_largepages();
2695
4b8d54f9
ZE		 2696 if (!cpu_has_vmx_ple())
2697 ple_gap = 0;
2698
b87a51ae
NHE		 2699 if (nested)
2700 nested_vmx_setup_ctls_msrs();
2701
6aa8b732
AK		 2702 return alloc_kvm_area();
2703}
2704
2705static __exit void hardware_unsetup(void)
2706{
2707 free_kvm_area();
2708}
2709
f5f7b2fe 2710static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
6aa8b732 2711{
772e0318 2712 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
c865c43d 2713 struct kvm_segment tmp = *save;
6aa8b732 2714
c865c43d
AK		 2715 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2716 tmp.base = vmcs_readl(sf->base);
2717 tmp.selector = vmcs_read16(sf->selector);
2718 tmp.s = 1;
6aa8b732 2719 }
c865c43d 2720 vmx_set_segment(vcpu, &tmp, seg);
6aa8b732
AK		 2721}
2722
2723static void enter_pmode(struct kvm_vcpu *vcpu)
2724{
2725 unsigned long flags;
a89a8fb9 2726 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2727
a89a8fb9 2728 vmx->emulation_required = 1;
7ffd92c5 2729 vmx->rmode.vm86_active = 0;
6aa8b732 2730
2fb92db1
AK		 2731 vmx_segment_cache_clear(vmx);
2732
f5f7b2fe 2733 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2734
2735 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2736 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2737 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2738 vmcs_writel(GUEST_RFLAGS, flags);
2739
66aee91a
RR		 2740 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2741 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2742
2743 update_exception_bitmap(vcpu);
2744
a89a8fb9
MG		 2745 if (emulate_invalid_guest_state)
2746 return;
2747
f5f7b2fe
AK		 2748 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2749 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2750 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2751 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732 2752
2fb92db1
AK		 2753 vmx_segment_cache_clear(vmx);
2754
6aa8b732
AK		 2755 vmcs_write16(GUEST_SS_SELECTOR, 0);
2756 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2757
2758 vmcs_write16(GUEST_CS_SELECTOR,
2759 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2760 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2761}
2762
d77c26fc 2763static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2764{
bfc6d222 2765 if (!kvm->arch.tss_addr) {
bc6678a3 2766 struct kvm_memslots *slots;
28a37544 2767 struct kvm_memory_slot *slot;
bc6678a3
MT		 2768 gfn_t base_gfn;
2769
90d83dc3 2770 slots = kvm_memslots(kvm);
28a37544
XG		 2771 slot = id_to_memslot(slots, 0);
2772 base_gfn = slot->base_gfn + slot->npages - 3;
2773
cbc94022
IE		 2774 return base_gfn << PAGE_SHIFT;
2775 }
bfc6d222 2776 return kvm->arch.tss_addr;
6aa8b732
AK		 2777}
2778
f5f7b2fe 2779static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2780{
772e0318 2781 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
6aa8b732 2782
15b00f32 2783 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2784 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2785 vmcs_write32(sf->limit, 0xffff);
2786 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2787 if (save->base & 0xf)
2788 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2789 " aligned when entering protected mode (seg=%d)",
2790 seg);
6aa8b732
AK		 2791}
2792
2793static void enter_rmode(struct kvm_vcpu *vcpu)
2794{
2795 unsigned long flags;
a89a8fb9 2796 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2797 struct kvm_segment var;
6aa8b732 2798
3a624e29
NK		 2799 if (enable_unrestricted_guest)
2800 return;
2801
f5f7b2fe
AK		 2802 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2803 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2804 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2805 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2806 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2807
a89a8fb9 2808 vmx->emulation_required = 1;
7ffd92c5 2809 vmx->rmode.vm86_active = 1;
6aa8b732 2810
baa7e81e 2811
776e58ea
GN		 2812 /*
2813 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2814 * vcpu. Call it here with phys address pointing 16M below 4G.
2815 */
2816 if (!vcpu->kvm->arch.tss_addr) {
2817 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2818 "called before entering vcpu\n");
2819 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2820 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2821 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2822 }
2823
2fb92db1
AK		 2824 vmx_segment_cache_clear(vmx);
2825
6aa8b732 2826 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2827 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2828 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2829
2830 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2831 vmx->rmode.save_rflags = flags;
6aa8b732 2832
053de044 2833 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2834
2835 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2836 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2837 update_exception_bitmap(vcpu);
2838
a89a8fb9
MG		 2839 if (emulate_invalid_guest_state)
2840 goto continue_rmode;
2841
b246dd5d
OW		 2842 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2843 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2844
2845 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2846 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2847
2848 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2849 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2850
2851 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2852 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2853
b246dd5d
OW		 2854 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2855 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2856
b246dd5d
OW		 2857 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2858 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2859
a89a8fb9 2860continue_rmode:
8668a3c4 2861 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2862}
2863
401d10de
AS		 2864static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2865{
2866 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2867 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2868
2869 if (!msr)
2870 return;
401d10de 2871
44ea2b17
AK		 2872 /*
2873 * Force kernel_gs_base reloading before EFER changes, as control
2874 * of this msr depends on is_long_mode().
2875 */
2876 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2877 vcpu->arch.efer = efer;
401d10de
AS		 2878 if (efer & EFER_LMA) {
2879 vmcs_write32(VM_ENTRY_CONTROLS,
2880 vmcs_read32(VM_ENTRY_CONTROLS) |
2881 VM_ENTRY_IA32E_MODE);
2882 msr->data = efer;
2883 } else {
2884 vmcs_write32(VM_ENTRY_CONTROLS,
2885 vmcs_read32(VM_ENTRY_CONTROLS) &
2886 ~VM_ENTRY_IA32E_MODE);
2887
2888 msr->data = efer & ~EFER_LME;
2889 }
2890 setup_msrs(vmx);
2891}
2892
05b3e0c2 2893#ifdef CONFIG_X86_64
6aa8b732
AK		 2894
2895static void enter_lmode(struct kvm_vcpu *vcpu)
2896{
2897 u32 guest_tr_ar;
2898
2fb92db1
AK		 2899 vmx_segment_cache_clear(to_vmx(vcpu));
2900
6aa8b732
AK		 2901 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2902 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2903 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2904 __func__);
6aa8b732
AK		 2905 vmcs_write32(GUEST_TR_AR_BYTES,
2906 (guest_tr_ar & ~AR_TYPE_MASK)
2907 | AR_TYPE_BUSY_64_TSS);
2908 }
da38f438 2909 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2910}
2911
2912static void exit_lmode(struct kvm_vcpu *vcpu)
2913{
6aa8b732
AK		 2914 vmcs_write32(VM_ENTRY_CONTROLS,
2915 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2916 & ~VM_ENTRY_IA32E_MODE);
da38f438 2917 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2918}
2919
2920#endif
2921
2384d2b3
SY		 2922static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2923{
b9d762fa 2924 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2925 if (enable_ept) {
2926 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2927 return;
4e1096d2 2928 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2929 }
2384d2b3
SY		 2930}
2931
e8467fda
AK		 2932static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2933{
2934 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2935
2936 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2937 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2938}
2939
aff48baa
AK		 2940static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2941{
2942 if (enable_ept && is_paging(vcpu))
2943 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2944 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2945}
2946
25c4c276 2947static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2948{
fc78f519
AK		 2949 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2950
2951 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2952 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2953}
2954
1439442c
SY		 2955static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2956{
6de4f3ad
AK		 2957 if (!test_bit(VCPU_EXREG_PDPTR,
2958 (unsigned long *)&vcpu->arch.regs_dirty))
2959 return;
2960
1439442c 2961 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2962 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2963 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2964 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2965 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2966 }
2967}
2968
8f5d549f
AK		 2969static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2970{
2971 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2972 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2973 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2974 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2975 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2976 }
6de4f3ad
AK		 2977
2978 __set_bit(VCPU_EXREG_PDPTR,
2979 (unsigned long *)&vcpu->arch.regs_avail);
2980 __set_bit(VCPU_EXREG_PDPTR,
2981 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2982}
2983
5e1746d6 2984static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2985
2986static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2987 unsigned long cr0,
2988 struct kvm_vcpu *vcpu)
2989{
5233dd51
MT		 2990 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2991 vmx_decache_cr3(vcpu);
1439442c
SY		 2992 if (!(cr0 & X86_CR0_PG)) {
2993 /* From paging/starting to nonpaging */
2994 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2995 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2996 (CPU_BASED_CR3_LOAD_EXITING |
2997 CPU_BASED_CR3_STORE_EXITING));
2998 vcpu->arch.cr0 = cr0;
fc78f519 2999 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3000 } else if (!is_paging(vcpu)) {
3001 /* From nonpaging to paging */
3002 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3003 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3004 ~(CPU_BASED_CR3_LOAD_EXITING |
3005 CPU_BASED_CR3_STORE_EXITING));
3006 vcpu->arch.cr0 = cr0;
fc78f519 3007 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3008 }
95eb84a7
SY		 3009
3010 if (!(cr0 & X86_CR0_WP))
3011 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3012}
3013
6aa8b732
AK		 3014static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3015{
7ffd92c5 3016 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3017 unsigned long hw_cr0;
3018
3019 if (enable_unrestricted_guest)
3020 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3021 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3022 else
3023 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3024
7ffd92c5 3025 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3026 enter_pmode(vcpu);
3027
7ffd92c5 3028 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3029 enter_rmode(vcpu);
3030
05b3e0c2 3031#ifdef CONFIG_X86_64
f6801dff 3032 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3033 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3034 enter_lmode(vcpu);
707d92fa 3035 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3036 exit_lmode(vcpu);
3037 }
3038#endif
3039
089d034e 3040 if (enable_ept)
1439442c
SY		 3041 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3042
02daab21 3043 if (!vcpu->fpu_active)
81231c69 3044 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3045
6aa8b732 3046 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3047 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3048 vcpu->arch.cr0 = cr0;
69c73028 3049 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3050}
3051
1439442c
SY		 3052static u64 construct_eptp(unsigned long root_hpa)
3053{
3054 u64 eptp;
3055
3056 /* TODO write the value reading from MSR */
3057 eptp = VMX_EPT_DEFAULT_MT |
3058 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3059 if (enable_ept_ad_bits)
3060 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3061 eptp |= (root_hpa & PAGE_MASK);
3062
3063 return eptp;
3064}
3065
6aa8b732
AK		 3066static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3067{
1439442c
SY		 3068 unsigned long guest_cr3;
3069 u64 eptp;
3070
3071 guest_cr3 = cr3;
089d034e 3072 if (enable_ept) {
1439442c
SY		 3073 eptp = construct_eptp(cr3);
3074 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3075 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3076 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3077 ept_load_pdptrs(vcpu);
1439442c
SY		 3078 }
3079
2384d2b3 3080 vmx_flush_tlb(vcpu);
1439442c 3081 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3082}
3083
5e1746d6 3084static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3085{
7ffd92c5 3086 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3087 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3088
5e1746d6
NHE		 3089 if (cr4 & X86_CR4_VMXE) {
3090 /*
3091 * To use VMXON (and later other VMX instructions), a guest
3092 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3093 * So basically the check on whether to allow nested VMX
3094 * is here.
3095 */
3096 if (!nested_vmx_allowed(vcpu))
3097 return 1;
3098 } else if (to_vmx(vcpu)->nested.vmxon)
3099 return 1;
3100
ad312c7c 3101 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3102 if (enable_ept) {
3103 if (!is_paging(vcpu)) {
3104 hw_cr4 &= ~X86_CR4_PAE;
3105 hw_cr4 |= X86_CR4_PSE;
3106 } else if (!(cr4 & X86_CR4_PAE)) {
3107 hw_cr4 &= ~X86_CR4_PAE;
3108 }
3109 }
1439442c
SY		 3110
3111 vmcs_writel(CR4_READ_SHADOW, cr4);
3112 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3113 return 0;
6aa8b732
AK		 3114}
3115
6aa8b732
AK		 3116static void vmx_get_segment(struct kvm_vcpu *vcpu,
3117 struct kvm_segment *var, int seg)
3118{
a9179499 3119 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3120 u32 ar;
3121
a9179499
AK		 3122 if (vmx->rmode.vm86_active
3123 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3124 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
72636420 3125 || seg == VCPU_SREG_GS)) {
f5f7b2fe 3126 *var = vmx->rmode.segs[seg];
a9179499 3127 if (seg == VCPU_SREG_TR
2fb92db1 3128 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3129 return;
1390a28b
AK		 3130 var->base = vmx_read_guest_seg_base(vmx, seg);
3131 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3132 return;
a9179499 3133 }
2fb92db1
AK		 3134 var->base = vmx_read_guest_seg_base(vmx, seg);
3135 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3136 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3137 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3138 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3139 ar = 0;
3140 var->type = ar & 15;
3141 var->s = (ar >> 4) & 1;
3142 var->dpl = (ar >> 5) & 3;
3143 var->present = (ar >> 7) & 1;
3144 var->avl = (ar >> 12) & 1;
3145 var->l = (ar >> 13) & 1;
3146 var->db = (ar >> 14) & 1;
3147 var->g = (ar >> 15) & 1;
3148 var->unusable = (ar >> 16) & 1;
3149}
3150
a9179499
AK		 3151static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3152{
a9179499
AK		 3153 struct kvm_segment s;
3154
3155 if (to_vmx(vcpu)->rmode.vm86_active) {
3156 vmx_get_segment(vcpu, &s, seg);
3157 return s.base;
3158 }
2fb92db1 3159 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3160}
3161
69c73028 3162static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3163{
3eeb3288 3164 if (!is_protmode(vcpu))
2e4d2653
IE		 3165 return 0;
3166
f4c63e5d
AK		 3167 if (!is_long_mode(vcpu)
3168 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3169 return 3;
3170
2fb92db1 3171 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3172}
3173
69c73028
AK		 3174static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3175{
d881e6f6
AK		 3176 struct vcpu_vmx *vmx = to_vmx(vcpu);
3177
3178 /*
3179 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3180 * fail; use the cache instead.
3181 */
3182 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3183 return vmx->cpl;
3184 }
3185
69c73028
AK		 3186 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3187 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3188 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3189 }
d881e6f6
AK		 3190
3191 return vmx->cpl;
69c73028
AK		 3192}
3193
3194
653e3108 3195static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3196{
6aa8b732
AK		 3197 u32 ar;
3198
f0495f9b 3199 if (var->unusable || !var->present)
6aa8b732
AK		 3200 ar = 1 << 16;
3201 else {
3202 ar = var->type & 15;
3203 ar |= (var->s & 1) << 4;
3204 ar |= (var->dpl & 3) << 5;
3205 ar |= (var->present & 1) << 7;
3206 ar |= (var->avl & 1) << 12;
3207 ar |= (var->l & 1) << 13;
3208 ar |= (var->db & 1) << 14;
3209 ar |= (var->g & 1) << 15;
3210 }
653e3108
AK		 3211
3212 return ar;
3213}
3214
3215static void vmx_set_segment(struct kvm_vcpu *vcpu,
3216 struct kvm_segment *var, int seg)
3217{
7ffd92c5 3218 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3219 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108
AK		 3220 u32 ar;
3221
2fb92db1
AK		 3222 vmx_segment_cache_clear(vmx);
3223
7ffd92c5 3224 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3225 vmcs_write16(sf->selector, var->selector);
f5f7b2fe 3226 vmx->rmode.segs[VCPU_SREG_TR] = *var;
653e3108
AK		 3227 return;
3228 }
3229 vmcs_writel(sf->base, var->base);
3230 vmcs_write32(sf->limit, var->limit);
3231 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3232 if (vmx->rmode.vm86_active && var->s) {
ce566803 3233 vmx->rmode.segs[seg] = *var;
653e3108
AK		 3234 /*
3235 * Hack real-mode segments into vm86 compatibility.
3236 */
3237 if (var->base == 0xffff0000 && var->selector == 0xf000)
3238 vmcs_writel(sf->base, 0xf0000);
3239 ar = 0xf3;
3240 } else
3241 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3242
3243 /*
3244 * Fix the "Accessed" bit in AR field of segment registers for older
3245 * qemu binaries.
3246 * IA32 arch specifies that at the time of processor reset the
3247 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3248 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3249 * state vmexit when "unrestricted guest" mode is turned on.
3250 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3251 * tree. Newer qemu binaries with that qemu fix would not need this
3252 * kvm hack.
3253 */
3254 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3255 ar |= 0x1; /* Accessed */
3256
6aa8b732 3257 vmcs_write32(sf->ar_bytes, ar);
69c73028 3258 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3259
3260 /*
3261 * Fix segments for real mode guest in hosts that don't have
3262 * "unrestricted_mode" or it was disabled.
3263 * This is done to allow migration of the guests from hosts with
3264 * unrestricted guest like Westmere to older host that don't have
3265 * unrestricted guest like Nehelem.
3266 */
3267 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3268 switch (seg) {
3269 case VCPU_SREG_CS:
3270 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3271 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3272 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3273 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3274 vmcs_write16(GUEST_CS_SELECTOR,
3275 vmcs_readl(GUEST_CS_BASE) >> 4);
3276 break;
3277 case VCPU_SREG_ES:
b246dd5d 3278 case VCPU_SREG_DS:
b246dd5d 3279 case VCPU_SREG_GS:
b246dd5d 3280 case VCPU_SREG_FS:
f5f7b2fe 3281 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
b246dd5d
OW		 3282 break;
3283 case VCPU_SREG_SS:
3284 vmcs_write16(GUEST_SS_SELECTOR,
3285 vmcs_readl(GUEST_SS_BASE) >> 4);
3286 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3287 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3288 break;
3289 }
3290 }
6aa8b732
AK		 3291}
3292
6aa8b732
AK		 3293static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3294{
2fb92db1 3295 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3296
3297 *db = (ar >> 14) & 1;
3298 *l = (ar >> 13) & 1;
3299}
3300
89a27f4d 3301static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3302{
89a27f4d
GN		 3303 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3304 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3305}
3306
89a27f4d 3307static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3308{
89a27f4d
GN		 3309 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3310 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3311}
3312
89a27f4d 3313static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3314{
89a27f4d
GN		 3315 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3316 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3317}
3318
89a27f4d 3319static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3320{
89a27f4d
GN		 3321 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3322 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3323}
3324
648dfaa7
MG		 3325static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3326{
3327 struct kvm_segment var;
3328 u32 ar;
3329
3330 vmx_get_segment(vcpu, &var, seg);
3331 ar = vmx_segment_access_rights(&var);
3332
3333 if (var.base != (var.selector << 4))
3334 return false;
e2a610d7 3335 if (var.limit < 0xffff)
648dfaa7 3336 return false;
a81aba14 3337 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
648dfaa7
MG		 3338 return false;
3339
3340 return true;
3341}
3342
3343static bool code_segment_valid(struct kvm_vcpu *vcpu)
3344{
3345 struct kvm_segment cs;
3346 unsigned int cs_rpl;
3347
3348 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3349 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3350
1872a3f4
AK		 3351 if (cs.unusable)
3352 return false;
648dfaa7
MG		 3353 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3354 return false;
3355 if (!cs.s)
3356 return false;
1872a3f4 3357 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3358 if (cs.dpl > cs_rpl)
3359 return false;
1872a3f4 3360 } else {
648dfaa7
MG		 3361 if (cs.dpl != cs_rpl)
3362 return false;
3363 }
3364 if (!cs.present)
3365 return false;
3366
3367 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3368 return true;
3369}
3370
3371static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3372{
3373 struct kvm_segment ss;
3374 unsigned int ss_rpl;
3375
3376 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3377 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3378
1872a3f4
AK		 3379 if (ss.unusable)
3380 return true;
3381 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3382 return false;
3383 if (!ss.s)
3384 return false;
3385 if (ss.dpl != ss_rpl) /* DPL != RPL */
3386 return false;
3387 if (!ss.present)
3388 return false;
3389
3390 return true;
3391}
3392
3393static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3394{
3395 struct kvm_segment var;
3396 unsigned int rpl;
3397
3398 vmx_get_segment(vcpu, &var, seg);
3399 rpl = var.selector & SELECTOR_RPL_MASK;
3400
1872a3f4
AK		 3401 if (var.unusable)
3402 return true;
648dfaa7
MG		 3403 if (!var.s)
3404 return false;
3405 if (!var.present)
3406 return false;
3407 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3408 if (var.dpl < rpl) /* DPL < RPL */
3409 return false;
3410 }
3411
3412 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3413 * rights flags
3414 */
3415 return true;
3416}
3417
3418static bool tr_valid(struct kvm_vcpu *vcpu)
3419{
3420 struct kvm_segment tr;
3421
3422 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3423
1872a3f4
AK		 3424 if (tr.unusable)
3425 return false;
648dfaa7
MG		 3426 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3427 return false;
1872a3f4 3428 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3429 return false;
3430 if (!tr.present)
3431 return false;
3432
3433 return true;
3434}
3435
3436static bool ldtr_valid(struct kvm_vcpu *vcpu)
3437{
3438 struct kvm_segment ldtr;
3439
3440 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3441
1872a3f4
AK		 3442 if (ldtr.unusable)
3443 return true;
648dfaa7
MG		 3444 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3445 return false;
3446 if (ldtr.type != 2)
3447 return false;
3448 if (!ldtr.present)
3449 return false;
3450
3451 return true;
3452}
3453
3454static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3455{
3456 struct kvm_segment cs, ss;
3457
3458 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3459 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3460
3461 return ((cs.selector & SELECTOR_RPL_MASK) ==
3462 (ss.selector & SELECTOR_RPL_MASK));
3463}
3464
3465/*
3466 * Check if guest state is valid. Returns true if valid, false if
3467 * not.
3468 * We assume that registers are always usable
3469 */
3470static bool guest_state_valid(struct kvm_vcpu *vcpu)
3471{
3472 /* real mode guest state checks */
3eeb3288 3473 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3474 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3475 return false;
3476 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3477 return false;
3478 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3479 return false;
3480 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3481 return false;
3482 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3483 return false;
3484 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3485 return false;
3486 } else {
3487 /* protected mode guest state checks */
3488 if (!cs_ss_rpl_check(vcpu))
3489 return false;
3490 if (!code_segment_valid(vcpu))
3491 return false;
3492 if (!stack_segment_valid(vcpu))
3493 return false;
3494 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3495 return false;
3496 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3497 return false;
3498 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3499 return false;
3500 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3501 return false;
3502 if (!tr_valid(vcpu))
3503 return false;
3504 if (!ldtr_valid(vcpu))
3505 return false;
3506 }
3507 /* TODO:
3508 * - Add checks on RIP
3509 * - Add checks on RFLAGS
3510 */
3511
3512 return true;
3513}
3514
d77c26fc 3515static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3516{
40dcaa9f 3517 gfn_t fn;
195aefde 3518 u16 data = 0;
40dcaa9f 3519 int r, idx, ret = 0;
6aa8b732 3520
40dcaa9f
XG		 3521 idx = srcu_read_lock(&kvm->srcu);
3522 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3523 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3524 if (r < 0)
10589a46 3525 goto out;
195aefde 3526 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3527 r = kvm_write_guest_page(kvm, fn++, &data,
3528 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3529 if (r < 0)
10589a46 3530 goto out;
195aefde
IE		 3531 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3532 if (r < 0)
10589a46 3533 goto out;
195aefde
IE		 3534 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3535 if (r < 0)
10589a46 3536 goto out;
195aefde 3537 data = ~0;
10589a46
MT		 3538 r = kvm_write_guest_page(kvm, fn, &data,
3539 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3540 sizeof(u8));
195aefde 3541 if (r < 0)
10589a46
MT		 3542 goto out;
3543
3544 ret = 1;
3545out:
40dcaa9f 3546 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3547 return ret;
6aa8b732
AK		 3548}
3549
b7ebfb05
SY		 3550static int init_rmode_identity_map(struct kvm *kvm)
3551{
40dcaa9f 3552 int i, idx, r, ret;
b7ebfb05
SY		 3553 pfn_t identity_map_pfn;
3554 u32 tmp;
3555
089d034e 3556 if (!enable_ept)
b7ebfb05
SY		 3557 return 1;
3558 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3559 printk(KERN_ERR "EPT: identity-mapping pagetable "
3560 "haven't been allocated!\n");
3561 return 0;
3562 }
3563 if (likely(kvm->arch.ept_identity_pagetable_done))
3564 return 1;
3565 ret = 0;
b927a3ce 3566 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3567 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3568 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3569 if (r < 0)
3570 goto out;
3571 /* Set up identity-mapping pagetable for EPT in real mode */
3572 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3573 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3574 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3575 r = kvm_write_guest_page(kvm, identity_map_pfn,
3576 &tmp, i * sizeof(tmp), sizeof(tmp));
3577 if (r < 0)
3578 goto out;
3579 }
3580 kvm->arch.ept_identity_pagetable_done = true;
3581 ret = 1;
3582out:
40dcaa9f 3583 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3584 return ret;
3585}
3586
6aa8b732
AK		 3587static void seg_setup(int seg)
3588{
772e0318 3589 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3590 unsigned int ar;
6aa8b732
AK		 3591
3592 vmcs_write16(sf->selector, 0);
3593 vmcs_writel(sf->base, 0);
3594 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3595 if (enable_unrestricted_guest) {
3596 ar = 0x93;
3597 if (seg == VCPU_SREG_CS)
3598 ar |= 0x08; /* code segment */
3599 } else
3600 ar = 0xf3;
3601
3602 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3603}
3604
f78e0e2e
SY		 3605static int alloc_apic_access_page(struct kvm *kvm)
3606{
4484141a 3607 struct page *page;
f78e0e2e
SY		 3608 struct kvm_userspace_memory_region kvm_userspace_mem;
3609 int r = 0;
3610
79fac95e 3611 mutex_lock(&kvm->slots_lock);
bfc6d222 3612 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3613 goto out;
3614 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3615 kvm_userspace_mem.flags = 0;
3616 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3617 kvm_userspace_mem.memory_size = PAGE_SIZE;
3618 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3619 if (r)
3620 goto out;
72dc67a6 3621
4484141a
XG		 3622 page = gfn_to_page(kvm, 0xfee00);
3623 if (is_error_page(page)) {
3624 r = -EFAULT;
3625 goto out;
3626 }
3627
3628 kvm->arch.apic_access_page = page;
f78e0e2e 3629out:
79fac95e 3630 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3631 return r;
3632}
3633
b7ebfb05
SY		 3634static int alloc_identity_pagetable(struct kvm *kvm)
3635{
4484141a 3636 struct page *page;
b7ebfb05
SY		 3637 struct kvm_userspace_memory_region kvm_userspace_mem;
3638 int r = 0;
3639
79fac95e 3640 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3641 if (kvm->arch.ept_identity_pagetable)
3642 goto out;
3643 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3644 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3645 kvm_userspace_mem.guest_phys_addr =
3646 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3647 kvm_userspace_mem.memory_size = PAGE_SIZE;
3648 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3649 if (r)
3650 goto out;
3651
4484141a
XG		 3652 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3653 if (is_error_page(page)) {
3654 r = -EFAULT;
3655 goto out;
3656 }
3657
3658 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3659out:
79fac95e 3660 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3661 return r;
3662}
3663
2384d2b3
SY		 3664static void allocate_vpid(struct vcpu_vmx *vmx)
3665{
3666 int vpid;
3667
3668 vmx->vpid = 0;
919818ab 3669 if (!enable_vpid)
2384d2b3
SY		 3670 return;
3671 spin_lock(&vmx_vpid_lock);
3672 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3673 if (vpid < VMX_NR_VPIDS) {
3674 vmx->vpid = vpid;
3675 __set_bit(vpid, vmx_vpid_bitmap);
3676 }
3677 spin_unlock(&vmx_vpid_lock);
3678}
3679
cdbecfc3
LJ		 3680static void free_vpid(struct vcpu_vmx *vmx)
3681{
3682 if (!enable_vpid)
3683 return;
3684 spin_lock(&vmx_vpid_lock);
3685 if (vmx->vpid != 0)
3686 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3687 spin_unlock(&vmx_vpid_lock);
3688}
3689
5897297b 3690static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3691{
3e7c73e9 3692 int f = sizeof(unsigned long);
25c5f225
SY		 3693
3694 if (!cpu_has_vmx_msr_bitmap())
3695 return;
3696
3697 /*
3698 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3699 * have the write-low and read-high bitmap offsets the wrong way round.
3700 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3701 */
25c5f225 3702 if (msr <= 0x1fff) {
3e7c73e9
AK		 3703 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3704 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3705 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3706 msr &= 0x1fff;
3e7c73e9
AK		 3707 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3708 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3709 }
25c5f225
SY		 3710}
3711
5897297b
AK		 3712static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3713{
3714 if (!longmode_only)
3715 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3716 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3717}
3718
a3a8ff8e
NHE		 3719/*
3720 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3721 * will not change in the lifetime of the guest.
3722 * Note that host-state that does change is set elsewhere. E.g., host-state
3723 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3724 */
3725static void vmx_set_constant_host_state(void)
3726{
3727 u32 low32, high32;
3728 unsigned long tmpl;
3729 struct desc_ptr dt;
3730
b1a74bf8 3731 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3732 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3733 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3734
3735 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3736#ifdef CONFIG_X86_64
3737 /*
3738 * Load null selectors, so we can avoid reloading them in
3739 * __vmx_load_host_state(), in case userspace uses the null selectors
3740 * too (the expected case).
3741 */
3742 vmcs_write16(HOST_DS_SELECTOR, 0);
3743 vmcs_write16(HOST_ES_SELECTOR, 0);
3744#else
a3a8ff8e
NHE		 3745 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3746 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3747#endif
a3a8ff8e
NHE		 3748 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3749 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3750
3751 native_store_idt(&dt);
3752 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3753
83287ea4 3754 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3755
3756 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3757 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3758 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3759 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3760
3761 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3762 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3763 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3764 }
3765}
3766
bf8179a0
NHE		 3767static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3768{
3769 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3770 if (enable_ept)
3771 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3772 if (is_guest_mode(&vmx->vcpu))
3773 vmx->vcpu.arch.cr4_guest_owned_bits &=
3774 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3775 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3776}
3777
3778static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3779{
3780 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3781 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3782 exec_control &= ~CPU_BASED_TPR_SHADOW;
3783#ifdef CONFIG_X86_64
3784 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3785 CPU_BASED_CR8_LOAD_EXITING;
3786#endif
3787 }
3788 if (!enable_ept)
3789 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3790 CPU_BASED_CR3_LOAD_EXITING |
3791 CPU_BASED_INVLPG_EXITING;
3792 return exec_control;
3793}
3794
3795static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3796{
3797 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3798 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3799 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3800 if (vmx->vpid == 0)
3801 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3802 if (!enable_ept) {
3803 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3804 enable_unrestricted_guest = 0;
ad756a16
MJ		 3805 /* Enable INVPCID for non-ept guests may cause performance regression. */
3806 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3807 }
3808 if (!enable_unrestricted_guest)
3809 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3810 if (!ple_gap)
3811 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3812 return exec_control;
3813}
3814
ce88decf
XG		 3815static void ept_set_mmio_spte_mask(void)
3816{
3817 /*
3818 * EPT Misconfigurations can be generated if the value of bits 2:0
3819 * of an EPT paging-structure entry is 110b (write/execute).
3820 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3821 * spte.
3822 */
3823 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3824}
3825
6aa8b732
AK		 3826/*
3827 * Sets up the vmcs for emulated real mode.
3828 */
8b9cf98c 3829static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3830{
2e4ce7f5 3831#ifdef CONFIG_X86_64
6aa8b732 3832 unsigned long a;
2e4ce7f5 3833#endif
6aa8b732 3834 int i;
6aa8b732 3835
6aa8b732 3836 /* I/O */
3e7c73e9
AK		 3837 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3838 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3839
25c5f225 3840 if (cpu_has_vmx_msr_bitmap())
5897297b 3841 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3842
6aa8b732
AK		 3843 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3844
6aa8b732 3845 /* Control */
1c3d14fe
YS		 3846 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3847 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3848
bf8179a0 3849 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3850
83ff3b9d 3851 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3852 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3853 vmx_secondary_exec_control(vmx));
83ff3b9d 3854 }
f78e0e2e 3855
4b8d54f9
ZE		 3856 if (ple_gap) {
3857 vmcs_write32(PLE_GAP, ple_gap);
3858 vmcs_write32(PLE_WINDOW, ple_window);
3859 }
3860
c3707958
XG		 3861 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3862 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3863 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3864
9581d442
AK		 3865 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3866 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3867 vmx_set_constant_host_state();
05b3e0c2 3868#ifdef CONFIG_X86_64
6aa8b732
AK		 3869 rdmsrl(MSR_FS_BASE, a);
3870 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3871 rdmsrl(MSR_GS_BASE, a);
3872 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3873#else
3874 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3875 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3876#endif
3877
2cc51560
ED		 3878 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3879 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3880 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3881 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3882 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3883
468d472f 3884 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3885 u32 msr_low, msr_high;
3886 u64 host_pat;
468d472f
SY		 3887 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3888 host_pat = msr_low | ((u64) msr_high << 32);
3889 /* Write the default value follow host pat */
3890 vmcs_write64(GUEST_IA32_PAT, host_pat);
3891 /* Keep arch.pat sync with GUEST_IA32_PAT */
3892 vmx->vcpu.arch.pat = host_pat;
3893 }
3894
6aa8b732
AK		 3895 for (i = 0; i < NR_VMX_MSR; ++i) {
3896 u32 index = vmx_msr_index[i];
3897 u32 data_low, data_high;
a2fa3e9f 3898 int j = vmx->nmsrs;
6aa8b732
AK		 3899
3900 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3901 continue;
432bd6cb
AK		 3902 if (wrmsr_safe(index, data_low, data_high) < 0)
3903 continue;
26bb0981
AK		 3904 vmx->guest_msrs[j].index = i;
3905 vmx->guest_msrs[j].data = 0;
d5696725 3906 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3907 ++vmx->nmsrs;
6aa8b732 3908 }
6aa8b732 3909
1c3d14fe 3910 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3911
3912 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3913 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3914
e00c8cf2 3915 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3916 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3917
3918 return 0;
3919}
3920
3921static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3922{
3923 struct vcpu_vmx *vmx = to_vmx(vcpu);
3924 u64 msr;
4b9d3a04 3925 int ret;
e00c8cf2 3926
5fdbf976 3927 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3928
7ffd92c5 3929 vmx->rmode.vm86_active = 0;
e00c8cf2 3930
3b86cd99
JK		 3931 vmx->soft_vnmi_blocked = 0;
3932
ad312c7c 3933 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3934 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3935 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3936 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3937 msr |= MSR_IA32_APICBASE_BSP;
3938 kvm_set_apic_base(&vmx->vcpu, msr);
3939
10ab25cd
JK		 3940 ret = fx_init(&vmx->vcpu);
3941 if (ret != 0)
3942 goto out;
e00c8cf2 3943
2fb92db1
AK		 3944 vmx_segment_cache_clear(vmx);
3945
5706be0d 3946 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3947 /*
3948 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3949 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3950 */
c5af89b6 3951 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3952 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3953 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3954 } else {
ad312c7c
ZX		 3955 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3956 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3957 }
e00c8cf2
AK		 3958
3959 seg_setup(VCPU_SREG_DS);
3960 seg_setup(VCPU_SREG_ES);
3961 seg_setup(VCPU_SREG_FS);
3962 seg_setup(VCPU_SREG_GS);
3963 seg_setup(VCPU_SREG_SS);
3964
3965 vmcs_write16(GUEST_TR_SELECTOR, 0);
3966 vmcs_writel(GUEST_TR_BASE, 0);
3967 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3968 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3969
3970 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3971 vmcs_writel(GUEST_LDTR_BASE, 0);
3972 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3973 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3974
3975 vmcs_write32(GUEST_SYSENTER_CS, 0);
3976 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3977 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3978
3979 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3980 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3981 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3982 else
5fdbf976
MT		 3983 kvm_rip_write(vcpu, 0);
3984 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3985
e00c8cf2
AK		 3986 vmcs_writel(GUEST_GDTR_BASE, 0);
3987 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3988
3989 vmcs_writel(GUEST_IDTR_BASE, 0);
3990 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3991
443381a8 3992 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3993 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3994 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3995
e00c8cf2
AK		 3996 /* Special registers */
3997 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3998
3999 setup_msrs(vmx);
4000
6aa8b732
AK		 4001 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4002
f78e0e2e
SY		 4003 if (cpu_has_vmx_tpr_shadow()) {
4004 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4005 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4006 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4007 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4008 vmcs_write32(TPR_THRESHOLD, 0);
4009 }
4010
4011 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4012 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4013 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4014
2384d2b3
SY		 4015 if (vmx->vpid != 0)
4016 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4017
fa40052c 4018 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4019 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4020 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4021 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4022 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4023 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4024 vmx_fpu_activate(&vmx->vcpu);
4025 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4026
b9d762fa 4027 vpid_sync_context(vmx);
2384d2b3 4028
3200f405 4029 ret = 0;
6aa8b732 4030
a89a8fb9
MG		 4031 /* HACK: Don't enable emulation on guest boot/reset */
4032 vmx->emulation_required = 0;
4033
6aa8b732
AK		 4034out:
4035 return ret;
4036}
4037
b6f1250e
NHE		 4038/*
4039 * In nested virtualization, check if L1 asked to exit on external interrupts.
4040 * For most existing hypervisors, this will always return true.
4041 */
4042static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4043{
4044 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4045 PIN_BASED_EXT_INTR_MASK;
4046}
4047
3b86cd99
JK		 4048static void enable_irq_window(struct kvm_vcpu *vcpu)
4049{
4050 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4051 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4052 /*
4053 * We get here if vmx_interrupt_allowed() said we can't
4054 * inject to L1 now because L2 must run. Ask L2 to exit
4055 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4056 */
d6185f20 4057 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4058 return;
d6185f20 4059 }
3b86cd99
JK		 4060
4061 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4062 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4063 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4064}
4065
4066static void enable_nmi_window(struct kvm_vcpu *vcpu)
4067{
4068 u32 cpu_based_vm_exec_control;
4069
4070 if (!cpu_has_virtual_nmis()) {
4071 enable_irq_window(vcpu);
4072 return;
4073 }
4074
30bd0c4c
AK		 4075 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4076 enable_irq_window(vcpu);
4077 return;
4078 }
3b86cd99
JK		 4079 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4080 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4081 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4082}
4083
66fd3f7f 4084static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4085{
9c8cba37 4086 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4087 uint32_t intr;
4088 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4089
229456fc 4090 trace_kvm_inj_virq(irq);
2714d1d3 4091
fa89a817 4092 ++vcpu->stat.irq_injections;
7ffd92c5 4093 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4094 int inc_eip = 0;
4095 if (vcpu->arch.interrupt.soft)
4096 inc_eip = vcpu->arch.event_exit_inst_len;
4097 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4098 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4099 return;
4100 }
66fd3f7f
GN		 4101 intr = irq | INTR_INFO_VALID_MASK;
4102 if (vcpu->arch.interrupt.soft) {
4103 intr |= INTR_TYPE_SOFT_INTR;
4104 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4105 vmx->vcpu.arch.event_exit_inst_len);
4106 } else
4107 intr |= INTR_TYPE_EXT_INTR;
4108 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4109}
4110
f08864b4
SY		 4111static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4112{
66a5a347
JK		 4113 struct vcpu_vmx *vmx = to_vmx(vcpu);
4114
0b6ac343
NHE		 4115 if (is_guest_mode(vcpu))
4116 return;
4117
3b86cd99
JK		 4118 if (!cpu_has_virtual_nmis()) {
4119 /*
4120 * Tracking the NMI-blocked state in software is built upon
4121 * finding the next open IRQ window. This, in turn, depends on
4122 * well-behaving guests: They have to keep IRQs disabled at
4123 * least as long as the NMI handler runs. Otherwise we may
4124 * cause NMI nesting, maybe breaking the guest. But as this is
4125 * highly unlikely, we can live with the residual risk.
4126 */
4127 vmx->soft_vnmi_blocked = 1;
4128 vmx->vnmi_blocked_time = 0;
4129 }
4130
487b391d 4131 ++vcpu->stat.nmi_injections;
9d58b931 4132 vmx->nmi_known_unmasked = false;
7ffd92c5 4133 if (vmx->rmode.vm86_active) {
71f9833b 4134 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4135 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4136 return;
4137 }
f08864b4
SY		 4138 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4139 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4140}
4141
c4282df9 4142static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4143{
3b86cd99 4144 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4145 return 0;
33f089ca 4146
c4282df9 4147 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4148 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4149 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4150}
4151
3cfc3092
JK		 4152static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4153{
4154 if (!cpu_has_virtual_nmis())
4155 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4156 if (to_vmx(vcpu)->nmi_known_unmasked)
4157 return false;
c332c83a 4158 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4159}
4160
4161static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4162{
4163 struct vcpu_vmx *vmx = to_vmx(vcpu);
4164
4165 if (!cpu_has_virtual_nmis()) {
4166 if (vmx->soft_vnmi_blocked != masked) {
4167 vmx->soft_vnmi_blocked = masked;
4168 vmx->vnmi_blocked_time = 0;
4169 }
4170 } else {
9d58b931 4171 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4172 if (masked)
4173 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4174 GUEST_INTR_STATE_NMI);
4175 else
4176 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4177 GUEST_INTR_STATE_NMI);
4178 }
4179}
4180
78646121
GN		 4181static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4182{
b6f1250e 4183 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4184 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4185 if (to_vmx(vcpu)->nested.nested_run_pending ||
4186 (vmcs12->idt_vectoring_info_field &
4187 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4188 return 0;
4189 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4190 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4191 vmcs12->vm_exit_intr_info = 0;
4192 /* fall through to normal code, but now in L1, not L2 */
4193 }
4194
c4282df9
GN		 4195 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4196 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4197 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4198}
4199
cbc94022
IE		 4200static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4201{
4202 int ret;
4203 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4204 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4205 .guest_phys_addr = addr,
4206 .memory_size = PAGE_SIZE * 3,
4207 .flags = 0,
4208 };
4209
4210 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4211 if (ret)
4212 return ret;
bfc6d222 4213 kvm->arch.tss_addr = addr;
93ea5388
GN		 4214 if (!init_rmode_tss(kvm))
4215 return -ENOMEM;
4216
cbc94022
IE		 4217 return 0;
4218}
4219
6aa8b732
AK		 4220static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4221 int vec, u32 err_code)
4222{
b3f37707
NK		 4223 /*
4224 * Instruction with address size override prefix opcode 0x67
4225 * Cause the #SS fault with 0 error code in VM86 mode.
4226 */
4227 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4228 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4229 return 1;
77ab6db0
JK		 4230 /*
4231 * Forward all other exceptions that are valid in real mode.
4232 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4233 * the required debugging infrastructure rework.
4234 */
4235 switch (vec) {
77ab6db0 4236 case DB_VECTOR:
d0bfb940
JK		 4237 if (vcpu->guest_debug &
4238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4239 return 0;
4240 kvm_queue_exception(vcpu, vec);
4241 return 1;
77ab6db0 4242 case BP_VECTOR:
c573cd22
JK		 4243 /*
4244 * Update instruction length as we may reinject the exception
4245 * from user space while in guest debugging mode.
4246 */
4247 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4248 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4249 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4250 return 0;
4251 /* fall through */
4252 case DE_VECTOR:
77ab6db0
JK		 4253 case OF_VECTOR:
4254 case BR_VECTOR:
4255 case UD_VECTOR:
4256 case DF_VECTOR:
4257 case SS_VECTOR:
4258 case GP_VECTOR:
4259 case MF_VECTOR:
4260 kvm_queue_exception(vcpu, vec);
4261 return 1;
4262 }
6aa8b732
AK		 4263 return 0;
4264}
4265
a0861c02
AK		 4266/*
4267 * Trigger machine check on the host. We assume all the MSRs are already set up
4268 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4269 * We pass a fake environment to the machine check handler because we want
4270 * the guest to be always treated like user space, no matter what context
4271 * it used internally.
4272 */
4273static void kvm_machine_check(void)
4274{
4275#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4276 struct pt_regs regs = {
4277 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4278 .flags = X86_EFLAGS_IF,
4279 };
4280
4281 do_machine_check(&regs, 0);
4282#endif
4283}
4284
851ba692 4285static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4286{
4287 /* already handled by vcpu_run */
4288 return 1;
4289}
4290
851ba692 4291static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4292{
1155f76a 4293 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4294 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4295 u32 intr_info, ex_no, error_code;
42dbaa5a 4296 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4297 u32 vect_info;
4298 enum emulation_result er;
4299
1155f76a 4300 vect_info = vmx->idt_vectoring_info;
88786475 4301 intr_info = vmx->exit_intr_info;
6aa8b732 4302
a0861c02 4303 if (is_machine_check(intr_info))
851ba692 4304 return handle_machine_check(vcpu);
a0861c02 4305
e4a41889 4306 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4307 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4308
4309 if (is_no_device(intr_info)) {
5fd86fcf 4310 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4311 return 1;
4312 }
4313
7aa81cc0 4314 if (is_invalid_opcode(intr_info)) {
51d8b661 4315 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4316 if (er != EMULATE_DONE)
7ee5d940 4317 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4318 return 1;
4319 }
4320
6aa8b732 4321 error_code = 0;
2e11384c 4322 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4323 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4324
4325 /*
4326 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4327 * MMIO, it is better to report an internal error.
4328 * See the comments in vmx_handle_exit.
4329 */
4330 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4331 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4332 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4333 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4334 vcpu->run->internal.ndata = 2;
4335 vcpu->run->internal.data[0] = vect_info;
4336 vcpu->run->internal.data[1] = intr_info;
4337 return 0;
4338 }
4339
6aa8b732 4340 if (is_page_fault(intr_info)) {
1439442c 4341 /* EPT won't cause page fault directly */
cf3ace79 4342 BUG_ON(enable_ept);
6aa8b732 4343 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4344 trace_kvm_page_fault(cr2, error_code);
4345
3298b75c 4346 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4347 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4348 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4349 }
4350
7ffd92c5 4351 if (vmx->rmode.vm86_active &&
6aa8b732 4352 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4353 error_code)) {
ad312c7c
ZX		 4354 if (vcpu->arch.halt_request) {
4355 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4356 return kvm_emulate_halt(vcpu);
4357 }
6aa8b732 4358 return 1;
72d6e5a0 4359 }
6aa8b732 4360
d0bfb940 4361 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4362 switch (ex_no) {
4363 case DB_VECTOR:
4364 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4365 if (!(vcpu->guest_debug &
4366 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4367 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4368 kvm_queue_exception(vcpu, DB_VECTOR);
4369 return 1;
4370 }
4371 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4372 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4373 /* fall through */
4374 case BP_VECTOR:
c573cd22
JK		 4375 /*
4376 * Update instruction length as we may reinject #BP from
4377 * user space while in guest debugging mode. Reading it for
4378 * #DB as well causes no harm, it is not used in that case.
4379 */
4380 vmx->vcpu.arch.event_exit_inst_len =
4381 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4382 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4383 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4384 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4385 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4386 break;
4387 default:
d0bfb940
JK		 4388 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4389 kvm_run->ex.exception = ex_no;
4390 kvm_run->ex.error_code = error_code;
42dbaa5a 4391 break;
6aa8b732 4392 }
6aa8b732
AK		 4393 return 0;
4394}
4395
851ba692 4396static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4397{
1165f5fe 4398 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4399 return 1;
4400}
4401
851ba692 4402static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4403{
851ba692 4404 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4405 return 0;
4406}
6aa8b732 4407
851ba692 4408static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4409{
bfdaab09 4410 unsigned long exit_qualification;
34c33d16 4411 int size, in, string;
039576c0 4412 unsigned port;
6aa8b732 4413
bfdaab09 4414 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4415 string = (exit_qualification & 16) != 0;
cf8f70bf 4416 in = (exit_qualification & 8) != 0;
e70669ab 4417
cf8f70bf 4418 ++vcpu->stat.io_exits;
e70669ab 4419
cf8f70bf 4420 if (string || in)
51d8b661 4421 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4422
cf8f70bf
GN		 4423 port = exit_qualification >> 16;
4424 size = (exit_qualification & 7) + 1;
e93f36bc 4425 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4426
4427 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4428}
4429
102d8325
IM		 4430static void
4431vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4432{
4433 /*
4434 * Patch in the VMCALL instruction:
4435 */
4436 hypercall[0] = 0x0f;
4437 hypercall[1] = 0x01;
4438 hypercall[2] = 0xc1;
102d8325
IM		 4439}
4440
0fa06071 4441/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4442static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4443{
4444 if (to_vmx(vcpu)->nested.vmxon &&
4445 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4446 return 1;
4447
4448 if (is_guest_mode(vcpu)) {
4449 /*
4450 * We get here when L2 changed cr0 in a way that did not change
4451 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4452 * but did change L0 shadowed bits. This can currently happen
4453 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4454 * loading) while pretending to allow the guest to change it.
4455 */
4456 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4457 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4458 return 1;
4459 vmcs_writel(CR0_READ_SHADOW, val);
4460 return 0;
4461 } else
4462 return kvm_set_cr0(vcpu, val);
4463}
4464
4465static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4466{
4467 if (is_guest_mode(vcpu)) {
4468 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4469 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4470 return 1;
4471 vmcs_writel(CR4_READ_SHADOW, val);
4472 return 0;
4473 } else
4474 return kvm_set_cr4(vcpu, val);
4475}
4476
4477/* called to set cr0 as approriate for clts instruction exit. */
4478static void handle_clts(struct kvm_vcpu *vcpu)
4479{
4480 if (is_guest_mode(vcpu)) {
4481 /*
4482 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4483 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4484 * just pretend it's off (also in arch.cr0 for fpu_activate).
4485 */
4486 vmcs_writel(CR0_READ_SHADOW,
4487 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4488 vcpu->arch.cr0 &= ~X86_CR0_TS;
4489 } else
4490 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4491}
4492
851ba692 4493static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4494{
229456fc 4495 unsigned long exit_qualification, val;
6aa8b732
AK		 4496 int cr;
4497 int reg;
49a9b07e 4498 int err;
6aa8b732 4499
bfdaab09 4500 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4501 cr = exit_qualification & 15;
4502 reg = (exit_qualification >> 8) & 15;
4503 switch ((exit_qualification >> 4) & 3) {
4504 case 0: /* mov to cr */
229456fc
MT		 4505 val = kvm_register_read(vcpu, reg);
4506 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4507 switch (cr) {
4508 case 0:
eeadf9e7 4509 err = handle_set_cr0(vcpu, val);
db8fcefa 4510 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4511 return 1;
4512 case 3:
2390218b 4513 err = kvm_set_cr3(vcpu, val);
db8fcefa 4514 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4515 return 1;
4516 case 4:
eeadf9e7 4517 err = handle_set_cr4(vcpu, val);
db8fcefa 4518 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4519 return 1;
0a5fff19
GN		 4520 case 8: {
4521 u8 cr8_prev = kvm_get_cr8(vcpu);
4522 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4523 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4524 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4525 if (irqchip_in_kernel(vcpu->kvm))
4526 return 1;
4527 if (cr8_prev <= cr8)
4528 return 1;
851ba692 4529 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4530 return 0;
4531 }
4b8073e4 4532 }
6aa8b732 4533 break;
25c4c276 4534 case 2: /* clts */
eeadf9e7 4535 handle_clts(vcpu);
4d4ec087 4536 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4537 skip_emulated_instruction(vcpu);
6b52d186 4538 vmx_fpu_activate(vcpu);
25c4c276 4539 return 1;
6aa8b732
AK		 4540 case 1: /*mov from cr*/
4541 switch (cr) {
4542 case 3:
9f8fe504
AK		 4543 val = kvm_read_cr3(vcpu);
4544 kvm_register_write(vcpu, reg, val);
4545 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4546 skip_emulated_instruction(vcpu);
4547 return 1;
4548 case 8:
229456fc
MT		 4549 val = kvm_get_cr8(vcpu);
4550 kvm_register_write(vcpu, reg, val);
4551 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4552 skip_emulated_instruction(vcpu);
4553 return 1;
4554 }
4555 break;
4556 case 3: /* lmsw */
a1f83a74 4557 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4558 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4559 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4560
4561 skip_emulated_instruction(vcpu);
4562 return 1;
4563 default:
4564 break;
4565 }
851ba692 4566 vcpu->run->exit_reason = 0;
a737f256 4567 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4568 (int)(exit_qualification >> 4) & 3, cr);
4569 return 0;
4570}
4571
851ba692 4572static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4573{
bfdaab09 4574 unsigned long exit_qualification;
6aa8b732
AK		 4575 int dr, reg;
4576
f2483415 4577 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4578 if (!kvm_require_cpl(vcpu, 0))
4579 return 1;
42dbaa5a
JK		 4580 dr = vmcs_readl(GUEST_DR7);
4581 if (dr & DR7_GD) {
4582 /*
4583 * As the vm-exit takes precedence over the debug trap, we
4584 * need to emulate the latter, either for the host or the
4585 * guest debugging itself.
4586 */
4587 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4588 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4589 vcpu->run->debug.arch.dr7 = dr;
4590 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4591 vmcs_readl(GUEST_CS_BASE) +
4592 vmcs_readl(GUEST_RIP);
851ba692
AK		 4593 vcpu->run->debug.arch.exception = DB_VECTOR;
4594 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4595 return 0;
4596 } else {
4597 vcpu->arch.dr7 &= ~DR7_GD;
4598 vcpu->arch.dr6 |= DR6_BD;
4599 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4600 kvm_queue_exception(vcpu, DB_VECTOR);
4601 return 1;
4602 }
4603 }
4604
bfdaab09 4605 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4606 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4607 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4608 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4609 unsigned long val;
4610 if (!kvm_get_dr(vcpu, dr, &val))
4611 kvm_register_write(vcpu, reg, val);
4612 } else
4613 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4614 skip_emulated_instruction(vcpu);
4615 return 1;
4616}
4617
020df079
GN		 4618static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4619{
4620 vmcs_writel(GUEST_DR7, val);
4621}
4622
851ba692 4623static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4624{
06465c5a
AK		 4625 kvm_emulate_cpuid(vcpu);
4626 return 1;
6aa8b732
AK		 4627}
4628
851ba692 4629static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4630{
ad312c7c 4631 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4632 u64 data;
4633
4634 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4635 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4636 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4637 return 1;
4638 }
4639
229456fc 4640 trace_kvm_msr_read(ecx, data);
2714d1d3 4641
6aa8b732 4642 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4643 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4644 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4645 skip_emulated_instruction(vcpu);
4646 return 1;
4647}
4648
851ba692 4649static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4650{
ad312c7c
ZX		 4651 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4652 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4653 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4654
4655 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4656 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4657 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4658 return 1;
4659 }
4660
59200273 4661 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4662 skip_emulated_instruction(vcpu);
4663 return 1;
4664}
4665
851ba692 4666static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4667{
3842d135 4668 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4669 return 1;
4670}
4671
851ba692 4672static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4673{
85f455f7
ED		 4674 u32 cpu_based_vm_exec_control;
4675
4676 /* clear pending irq */
4677 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4678 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4679 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4680
3842d135
AK		 4681 kvm_make_request(KVM_REQ_EVENT, vcpu);
4682
a26bf12a 4683 ++vcpu->stat.irq_window_exits;
2714d1d3 4684
c1150d8c
DL		 4685 /*
4686 * If the user space waits to inject interrupts, exit as soon as
4687 * possible
4688 */
8061823a 4689 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4690 vcpu->run->request_interrupt_window &&
8061823a 4691 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4692 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4693 return 0;
4694 }
6aa8b732
AK		 4695 return 1;
4696}
4697
851ba692 4698static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4699{
4700 skip_emulated_instruction(vcpu);
d3bef15f 4701 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4702}
4703
851ba692 4704static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4705{
510043da 4706 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4707 kvm_emulate_hypercall(vcpu);
4708 return 1;
c21415e8
IM		 4709}
4710
ec25d5e6
GN		 4711static int handle_invd(struct kvm_vcpu *vcpu)
4712{
51d8b661 4713 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4714}
4715
851ba692 4716static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4717{
f9c617f6 4718 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4719
4720 kvm_mmu_invlpg(vcpu, exit_qualification);
4721 skip_emulated_instruction(vcpu);
4722 return 1;
4723}
4724
fee84b07
AK		 4725static int handle_rdpmc(struct kvm_vcpu *vcpu)
4726{
4727 int err;
4728
4729 err = kvm_rdpmc(vcpu);
4730 kvm_complete_insn_gp(vcpu, err);
4731
4732 return 1;
4733}
4734
851ba692 4735static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4736{
4737 skip_emulated_instruction(vcpu);
f5f48ee1 4738 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4739 return 1;
4740}
4741
2acf923e
DC		 4742static int handle_xsetbv(struct kvm_vcpu *vcpu)
4743{
4744 u64 new_bv = kvm_read_edx_eax(vcpu);
4745 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4746
4747 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4748 skip_emulated_instruction(vcpu);
4749 return 1;
4750}
4751
851ba692 4752static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4753{
58fbbf26
KT		 4754 if (likely(fasteoi)) {
4755 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4756 int access_type, offset;
4757
4758 access_type = exit_qualification & APIC_ACCESS_TYPE;
4759 offset = exit_qualification & APIC_ACCESS_OFFSET;
4760 /*
4761 * Sane guest uses MOV to write EOI, with written value
4762 * not cared. So make a short-circuit here by avoiding
4763 * heavy instruction emulation.
4764 */
4765 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4766 (offset == APIC_EOI)) {
4767 kvm_lapic_set_eoi(vcpu);
4768 skip_emulated_instruction(vcpu);
4769 return 1;
4770 }
4771 }
51d8b661 4772 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4773}
4774
851ba692 4775static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4776{
60637aac 4777 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4778 unsigned long exit_qualification;
e269fb21
JK		 4779 bool has_error_code = false;
4780 u32 error_code = 0;
37817f29 4781 u16 tss_selector;
7f3d35fd 4782 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4783
4784 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4785 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4786 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4787
4788 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4789
4790 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4791 if (reason == TASK_SWITCH_GATE && idt_v) {
4792 switch (type) {
4793 case INTR_TYPE_NMI_INTR:
4794 vcpu->arch.nmi_injected = false;
654f06fc 4795 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4796 break;
4797 case INTR_TYPE_EXT_INTR:
66fd3f7f 4798 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4799 kvm_clear_interrupt_queue(vcpu);
4800 break;
4801 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4802 if (vmx->idt_vectoring_info &
4803 VECTORING_INFO_DELIVER_CODE_MASK) {
4804 has_error_code = true;
4805 error_code =
4806 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4807 }
4808 /* fall through */
64a7ec06
GN		 4809 case INTR_TYPE_SOFT_EXCEPTION:
4810 kvm_clear_exception_queue(vcpu);
4811 break;
4812 default:
4813 break;
4814 }
60637aac 4815 }
37817f29
IE		 4816 tss_selector = exit_qualification;
4817
64a7ec06
GN		 4818 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4819 type != INTR_TYPE_EXT_INTR &&
4820 type != INTR_TYPE_NMI_INTR))
4821 skip_emulated_instruction(vcpu);
4822
7f3d35fd
KW		 4823 if (kvm_task_switch(vcpu, tss_selector,
4824 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4825 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4826 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4827 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4828 vcpu->run->internal.ndata = 0;
42dbaa5a 4829 return 0;
acb54517 4830 }
42dbaa5a
JK		 4831
4832 /* clear all local breakpoint enable flags */
4833 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4834
4835 /*
4836 * TODO: What about debug traps on tss switch?
4837 * Are we supposed to inject them and update dr6?
4838 */
4839
4840 return 1;
37817f29
IE		 4841}
4842
851ba692 4843static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4844{
f9c617f6 4845 unsigned long exit_qualification;
1439442c 4846 gpa_t gpa;
4f5982a5 4847 u32 error_code;
1439442c 4848 int gla_validity;
1439442c 4849
f9c617f6 4850 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4851
4852 if (exit_qualification & (1 << 6)) {
4853 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4854 return -EINVAL;
1439442c
SY		 4855 }
4856
4857 gla_validity = (exit_qualification >> 7) & 0x3;
4858 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4859 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4860 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4861 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4862 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4863 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4864 (long unsigned int)exit_qualification);
851ba692
AK		 4865 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4866 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4867 return 0;
1439442c
SY		 4868 }
4869
4870 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4871 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4872
4873 /* It is a write fault? */
4874 error_code = exit_qualification & (1U << 1);
4875 /* ept page table is present? */
4876 error_code |= (exit_qualification >> 3) & 0x1;
4877
4878 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4879}
4880
68f89400
MT		 4881static u64 ept_rsvd_mask(u64 spte, int level)
4882{
4883 int i;
4884 u64 mask = 0;
4885
4886 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4887 mask |= (1ULL << i);
4888
4889 if (level > 2)
4890 /* bits 7:3 reserved */
4891 mask |= 0xf8;
4892 else if (level == 2) {
4893 if (spte & (1ULL << 7))
4894 /* 2MB ref, bits 20:12 reserved */
4895 mask |= 0x1ff000;
4896 else
4897 /* bits 6:3 reserved */
4898 mask |= 0x78;
4899 }
4900
4901 return mask;
4902}
4903
4904static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4905 int level)
4906{
4907 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4908
4909 /* 010b (write-only) */
4910 WARN_ON((spte & 0x7) == 0x2);
4911
4912 /* 110b (write/execute) */
4913 WARN_ON((spte & 0x7) == 0x6);
4914
4915 /* 100b (execute-only) and value not supported by logical processor */
4916 if (!cpu_has_vmx_ept_execute_only())
4917 WARN_ON((spte & 0x7) == 0x4);
4918
4919 /* not 000b */
4920 if ((spte & 0x7)) {
4921 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4922
4923 if (rsvd_bits != 0) {
4924 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4925 __func__, rsvd_bits);
4926 WARN_ON(1);
4927 }
4928
4929 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4930 u64 ept_mem_type = (spte & 0x38) >> 3;
4931
4932 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4933 ept_mem_type == 7) {
4934 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4935 __func__, ept_mem_type);
4936 WARN_ON(1);
4937 }
4938 }
4939 }
4940}
4941
851ba692 4942static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4943{
4944 u64 sptes[4];
ce88decf 4945 int nr_sptes, i, ret;
68f89400
MT		 4946 gpa_t gpa;
4947
4948 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4949
ce88decf
XG		 4950 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4951 if (likely(ret == 1))
4952 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4953 EMULATE_DONE;
4954 if (unlikely(!ret))
4955 return 1;
4956
4957 /* It is the real ept misconfig */
68f89400
MT		 4958 printk(KERN_ERR "EPT: Misconfiguration.\n");
4959 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4960
4961 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4962
4963 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4964 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4965
851ba692
AK		 4966 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4967 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4968
4969 return 0;
4970}
4971
851ba692 4972static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4973{
4974 u32 cpu_based_vm_exec_control;
4975
4976 /* clear pending NMI */
4977 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4978 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4979 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4980 ++vcpu->stat.nmi_window_exits;
3842d135 4981 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4982
4983 return 1;
4984}
4985
80ced186 4986static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4987{
8b3079a5
AK		 4988 struct vcpu_vmx *vmx = to_vmx(vcpu);
4989 enum emulation_result err = EMULATE_DONE;
80ced186 4990 int ret = 1;
49e9d557
AK		 4991 u32 cpu_exec_ctrl;
4992 bool intr_window_requested;
b8405c18 4993 unsigned count = 130;
49e9d557
AK		 4994
4995 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4996 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 4997
b8405c18 4998 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 4999 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5000 return handle_interrupt_window(&vmx->vcpu);
5001
de87dcdd
AK		 5002 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5003 return 1;
5004
51d8b661 5005 err = emulate_instruction(vcpu, 0);
ea953ef0 5006
80ced186
MG		 5007 if (err == EMULATE_DO_MMIO) {
5008 ret = 0;
5009 goto out;
5010 }
1d5a4d9b 5011
de5f70e0
AK		 5012 if (err != EMULATE_DONE) {
5013 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5014 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5015 vcpu->run->internal.ndata = 0;
6d77dbfc 5016 return 0;
de5f70e0 5017 }
ea953ef0
MG		 5018
5019 if (signal_pending(current))
80ced186 5020 goto out;
ea953ef0
MG		 5021 if (need_resched())
5022 schedule();
5023 }
5024
7c068e45 5025 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5026out:
5027 return ret;
ea953ef0
MG		 5028}
5029
4b8d54f9
ZE		 5030/*
5031 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5032 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5033 */
9fb41ba8 5034static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5035{
5036 skip_emulated_instruction(vcpu);
5037 kvm_vcpu_on_spin(vcpu);
5038
5039 return 1;
5040}
5041
59708670
SY		 5042static int handle_invalid_op(struct kvm_vcpu *vcpu)
5043{
5044 kvm_queue_exception(vcpu, UD_VECTOR);
5045 return 1;
5046}
5047
ff2f6fe9
NHE		 5048/*
5049 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5050 * We could reuse a single VMCS for all the L2 guests, but we also want the
5051 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5052 * allows keeping them loaded on the processor, and in the future will allow
5053 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5054 * every entry if they never change.
5055 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5056 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5057 *
5058 * The following functions allocate and free a vmcs02 in this pool.
5059 */
5060
5061/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5062static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5063{
5064 struct vmcs02_list *item;
5065 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5066 if (item->vmptr == vmx->nested.current_vmptr) {
5067 list_move(&item->list, &vmx->nested.vmcs02_pool);
5068 return &item->vmcs02;
5069 }
5070
5071 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5072 /* Recycle the least recently used VMCS. */
5073 item = list_entry(vmx->nested.vmcs02_pool.prev,
5074 struct vmcs02_list, list);
5075 item->vmptr = vmx->nested.current_vmptr;
5076 list_move(&item->list, &vmx->nested.vmcs02_pool);
5077 return &item->vmcs02;
5078 }
5079
5080 /* Create a new VMCS */
5081 item = (struct vmcs02_list *)
5082 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5083 if (!item)
5084 return NULL;
5085 item->vmcs02.vmcs = alloc_vmcs();
5086 if (!item->vmcs02.vmcs) {
5087 kfree(item);
5088 return NULL;
5089 }
5090 loaded_vmcs_init(&item->vmcs02);
5091 item->vmptr = vmx->nested.current_vmptr;
5092 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5093 vmx->nested.vmcs02_num++;
5094 return &item->vmcs02;
5095}
5096
5097/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5098static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5099{
5100 struct vmcs02_list *item;
5101 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5102 if (item->vmptr == vmptr) {
5103 free_loaded_vmcs(&item->vmcs02);
5104 list_del(&item->list);
5105 kfree(item);
5106 vmx->nested.vmcs02_num--;
5107 return;
5108 }
5109}
5110
5111/*
5112 * Free all VMCSs saved for this vcpu, except the one pointed by
5113 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5114 * currently used, if running L2), and vmcs01 when running L2.
5115 */
5116static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5117{
5118 struct vmcs02_list *item, *n;
5119 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5120 if (vmx->loaded_vmcs != &item->vmcs02)
5121 free_loaded_vmcs(&item->vmcs02);
5122 list_del(&item->list);
5123 kfree(item);
5124 }
5125 vmx->nested.vmcs02_num = 0;
5126
5127 if (vmx->loaded_vmcs != &vmx->vmcs01)
5128 free_loaded_vmcs(&vmx->vmcs01);
5129}
5130
ec378aee
NHE		 5131/*
5132 * Emulate the VMXON instruction.
5133 * Currently, we just remember that VMX is active, and do not save or even
5134 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5135 * do not currently need to store anything in that guest-allocated memory
5136 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5137 * argument is different from the VMXON pointer (which the spec says they do).
5138 */
5139static int handle_vmon(struct kvm_vcpu *vcpu)
5140{
5141 struct kvm_segment cs;
5142 struct vcpu_vmx *vmx = to_vmx(vcpu);
5143
5144 /* The Intel VMX Instruction Reference lists a bunch of bits that
5145 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5146 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5147 * Otherwise, we should fail with #UD. We test these now:
5148 */
5149 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5150 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5151 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5152 kvm_queue_exception(vcpu, UD_VECTOR);
5153 return 1;
5154 }
5155
5156 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5157 if (is_long_mode(vcpu) && !cs.l) {
5158 kvm_queue_exception(vcpu, UD_VECTOR);
5159 return 1;
5160 }
5161
5162 if (vmx_get_cpl(vcpu)) {
5163 kvm_inject_gp(vcpu, 0);
5164 return 1;
5165 }
5166
ff2f6fe9
NHE		 5167 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5168 vmx->nested.vmcs02_num = 0;
5169
ec378aee
NHE		 5170 vmx->nested.vmxon = true;
5171
5172 skip_emulated_instruction(vcpu);
5173 return 1;
5174}
5175
5176/*
5177 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5178 * for running VMX instructions (except VMXON, whose prerequisites are
5179 * slightly different). It also specifies what exception to inject otherwise.
5180 */
5181static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5182{
5183 struct kvm_segment cs;
5184 struct vcpu_vmx *vmx = to_vmx(vcpu);
5185
5186 if (!vmx->nested.vmxon) {
5187 kvm_queue_exception(vcpu, UD_VECTOR);
5188 return 0;
5189 }
5190
5191 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5192 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5193 (is_long_mode(vcpu) && !cs.l)) {
5194 kvm_queue_exception(vcpu, UD_VECTOR);
5195 return 0;
5196 }
5197
5198 if (vmx_get_cpl(vcpu)) {
5199 kvm_inject_gp(vcpu, 0);
5200 return 0;
5201 }
5202
5203 return 1;
5204}
5205
5206/*
5207 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5208 * just stops using VMX.
5209 */
5210static void free_nested(struct vcpu_vmx *vmx)
5211{
5212 if (!vmx->nested.vmxon)
5213 return;
5214 vmx->nested.vmxon = false;
a9d30f33
NHE		 5215 if (vmx->nested.current_vmptr != -1ull) {
5216 kunmap(vmx->nested.current_vmcs12_page);
5217 nested_release_page(vmx->nested.current_vmcs12_page);
5218 vmx->nested.current_vmptr = -1ull;
5219 vmx->nested.current_vmcs12 = NULL;
5220 }
fe3ef05c
NHE		 5221 /* Unpin physical memory we referred to in current vmcs02 */
5222 if (vmx->nested.apic_access_page) {
5223 nested_release_page(vmx->nested.apic_access_page);
5224 vmx->nested.apic_access_page = 0;
5225 }
ff2f6fe9
NHE		 5226
5227 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5228}
5229
5230/* Emulate the VMXOFF instruction */
5231static int handle_vmoff(struct kvm_vcpu *vcpu)
5232{
5233 if (!nested_vmx_check_permission(vcpu))
5234 return 1;
5235 free_nested(to_vmx(vcpu));
5236 skip_emulated_instruction(vcpu);
5237 return 1;
5238}
5239
064aea77
NHE		 5240/*
5241 * Decode the memory-address operand of a vmx instruction, as recorded on an
5242 * exit caused by such an instruction (run by a guest hypervisor).
5243 * On success, returns 0. When the operand is invalid, returns 1 and throws
5244 * #UD or #GP.
5245 */
5246static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5247 unsigned long exit_qualification,
5248 u32 vmx_instruction_info, gva_t *ret)
5249{
5250 /*
5251 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5252 * Execution", on an exit, vmx_instruction_info holds most of the
5253 * addressing components of the operand. Only the displacement part
5254 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5255 * For how an actual address is calculated from all these components,
5256 * refer to Vol. 1, "Operand Addressing".
5257 */
5258 int scaling = vmx_instruction_info & 3;
5259 int addr_size = (vmx_instruction_info >> 7) & 7;
5260 bool is_reg = vmx_instruction_info & (1u << 10);
5261 int seg_reg = (vmx_instruction_info >> 15) & 7;
5262 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5263 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5264 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5265 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5266
5267 if (is_reg) {
5268 kvm_queue_exception(vcpu, UD_VECTOR);
5269 return 1;
5270 }
5271
5272 /* Addr = segment_base + offset */
5273 /* offset = base + [index * scale] + displacement */
5274 *ret = vmx_get_segment_base(vcpu, seg_reg);
5275 if (base_is_valid)
5276 *ret += kvm_register_read(vcpu, base_reg);
5277 if (index_is_valid)
5278 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5279 *ret += exit_qualification; /* holds the displacement */
5280
5281 if (addr_size == 1) /* 32 bit */
5282 *ret &= 0xffffffff;
5283
5284 /*
5285 * TODO: throw #GP (and return 1) in various cases that the VM*
5286 * instructions require it - e.g., offset beyond segment limit,
5287 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5288 * address, and so on. Currently these are not checked.
5289 */
5290 return 0;
5291}
5292
0140caea
NHE		 5293/*
5294 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5295 * set the success or error code of an emulated VMX instruction, as specified
5296 * by Vol 2B, VMX Instruction Reference, "Conventions".
5297 */
5298static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5299{
5300 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5301 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5302 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5303}
5304
5305static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5306{
5307 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5308 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5309 X86_EFLAGS_SF | X86_EFLAGS_OF))
5310 | X86_EFLAGS_CF);
5311}
5312
5313static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5314 u32 vm_instruction_error)
5315{
5316 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5317 /*
5318 * failValid writes the error number to the current VMCS, which
5319 * can't be done there isn't a current VMCS.
5320 */
5321 nested_vmx_failInvalid(vcpu);
5322 return;
5323 }
5324 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5325 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5326 X86_EFLAGS_SF | X86_EFLAGS_OF))
5327 | X86_EFLAGS_ZF);
5328 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5329}
5330
27d6c865
NHE		 5331/* Emulate the VMCLEAR instruction */
5332static int handle_vmclear(struct kvm_vcpu *vcpu)
5333{
5334 struct vcpu_vmx *vmx = to_vmx(vcpu);
5335 gva_t gva;
5336 gpa_t vmptr;
5337 struct vmcs12 *vmcs12;
5338 struct page *page;
5339 struct x86_exception e;
5340
5341 if (!nested_vmx_check_permission(vcpu))
5342 return 1;
5343
5344 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5345 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5346 return 1;
5347
5348 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5349 sizeof(vmptr), &e)) {
5350 kvm_inject_page_fault(vcpu, &e);
5351 return 1;
5352 }
5353
5354 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5355 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5356 skip_emulated_instruction(vcpu);
5357 return 1;
5358 }
5359
5360 if (vmptr == vmx->nested.current_vmptr) {
5361 kunmap(vmx->nested.current_vmcs12_page);
5362 nested_release_page(vmx->nested.current_vmcs12_page);
5363 vmx->nested.current_vmptr = -1ull;
5364 vmx->nested.current_vmcs12 = NULL;
5365 }
5366
5367 page = nested_get_page(vcpu, vmptr);
5368 if (page == NULL) {
5369 /*
5370 * For accurate processor emulation, VMCLEAR beyond available
5371 * physical memory should do nothing at all. However, it is
5372 * possible that a nested vmx bug, not a guest hypervisor bug,
5373 * resulted in this case, so let's shut down before doing any
5374 * more damage:
5375 */
5376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5377 return 1;
5378 }
5379 vmcs12 = kmap(page);
5380 vmcs12->launch_state = 0;
5381 kunmap(page);
5382 nested_release_page(page);
5383
5384 nested_free_vmcs02(vmx, vmptr);
5385
5386 skip_emulated_instruction(vcpu);
5387 nested_vmx_succeed(vcpu);
5388 return 1;
5389}
5390
cd232ad0
NHE		 5391static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5392
5393/* Emulate the VMLAUNCH instruction */
5394static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5395{
5396 return nested_vmx_run(vcpu, true);
5397}
5398
5399/* Emulate the VMRESUME instruction */
5400static int handle_vmresume(struct kvm_vcpu *vcpu)
5401{
5402
5403 return nested_vmx_run(vcpu, false);
5404}
5405
49f705c5
NHE		 5406enum vmcs_field_type {
5407 VMCS_FIELD_TYPE_U16 = 0,
5408 VMCS_FIELD_TYPE_U64 = 1,
5409 VMCS_FIELD_TYPE_U32 = 2,
5410 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5411};
5412
5413static inline int vmcs_field_type(unsigned long field)
5414{
5415 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5416 return VMCS_FIELD_TYPE_U32;
5417 return (field >> 13) & 0x3 ;
5418}
5419
5420static inline int vmcs_field_readonly(unsigned long field)
5421{
5422 return (((field >> 10) & 0x3) == 1);
5423}
5424
5425/*
5426 * Read a vmcs12 field. Since these can have varying lengths and we return
5427 * one type, we chose the biggest type (u64) and zero-extend the return value
5428 * to that size. Note that the caller, handle_vmread, might need to use only
5429 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5430 * 64-bit fields are to be returned).
5431 */
5432static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5433 unsigned long field, u64 *ret)
5434{
5435 short offset = vmcs_field_to_offset(field);
5436 char *p;
5437
5438 if (offset < 0)
5439 return 0;
5440
5441 p = ((char *)(get_vmcs12(vcpu))) + offset;
5442
5443 switch (vmcs_field_type(field)) {
5444 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5445 *ret = *((natural_width *)p);
5446 return 1;
5447 case VMCS_FIELD_TYPE_U16:
5448 *ret = *((u16 *)p);
5449 return 1;
5450 case VMCS_FIELD_TYPE_U32:
5451 *ret = *((u32 *)p);
5452 return 1;
5453 case VMCS_FIELD_TYPE_U64:
5454 *ret = *((u64 *)p);
5455 return 1;
5456 default:
5457 return 0; /* can never happen. */
5458 }
5459}
5460
5461/*
5462 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5463 * used before) all generate the same failure when it is missing.
5464 */
5465static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5466{
5467 struct vcpu_vmx *vmx = to_vmx(vcpu);
5468 if (vmx->nested.current_vmptr == -1ull) {
5469 nested_vmx_failInvalid(vcpu);
5470 skip_emulated_instruction(vcpu);
5471 return 0;
5472 }
5473 return 1;
5474}
5475
5476static int handle_vmread(struct kvm_vcpu *vcpu)
5477{
5478 unsigned long field;
5479 u64 field_value;
5480 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5481 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5482 gva_t gva = 0;
5483
5484 if (!nested_vmx_check_permission(vcpu) ||
5485 !nested_vmx_check_vmcs12(vcpu))
5486 return 1;
5487
5488 /* Decode instruction info and find the field to read */
5489 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5490 /* Read the field, zero-extended to a u64 field_value */
5491 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5492 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5493 skip_emulated_instruction(vcpu);
5494 return 1;
5495 }
5496 /*
5497 * Now copy part of this value to register or memory, as requested.
5498 * Note that the number of bits actually copied is 32 or 64 depending
5499 * on the guest's mode (32 or 64 bit), not on the given field's length.
5500 */
5501 if (vmx_instruction_info & (1u << 10)) {
5502 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5503 field_value);
5504 } else {
5505 if (get_vmx_mem_address(vcpu, exit_qualification,
5506 vmx_instruction_info, &gva))
5507 return 1;
5508 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5509 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5510 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5511 }
5512
5513 nested_vmx_succeed(vcpu);
5514 skip_emulated_instruction(vcpu);
5515 return 1;
5516}
5517
5518
5519static int handle_vmwrite(struct kvm_vcpu *vcpu)
5520{
5521 unsigned long field;
5522 gva_t gva;
5523 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5524 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5525 char *p;
5526 short offset;
5527 /* The value to write might be 32 or 64 bits, depending on L1's long
5528 * mode, and eventually we need to write that into a field of several
5529 * possible lengths. The code below first zero-extends the value to 64
5530 * bit (field_value), and then copies only the approriate number of
5531 * bits into the vmcs12 field.
5532 */
5533 u64 field_value = 0;
5534 struct x86_exception e;
5535
5536 if (!nested_vmx_check_permission(vcpu) ||
5537 !nested_vmx_check_vmcs12(vcpu))
5538 return 1;
5539
5540 if (vmx_instruction_info & (1u << 10))
5541 field_value = kvm_register_read(vcpu,
5542 (((vmx_instruction_info) >> 3) & 0xf));
5543 else {
5544 if (get_vmx_mem_address(vcpu, exit_qualification,
5545 vmx_instruction_info, &gva))
5546 return 1;
5547 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5548 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5549 kvm_inject_page_fault(vcpu, &e);
5550 return 1;
5551 }
5552 }
5553
5554
5555 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5556 if (vmcs_field_readonly(field)) {
5557 nested_vmx_failValid(vcpu,
5558 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5559 skip_emulated_instruction(vcpu);
5560 return 1;
5561 }
5562
5563 offset = vmcs_field_to_offset(field);
5564 if (offset < 0) {
5565 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5566 skip_emulated_instruction(vcpu);
5567 return 1;
5568 }
5569 p = ((char *) get_vmcs12(vcpu)) + offset;
5570
5571 switch (vmcs_field_type(field)) {
5572 case VMCS_FIELD_TYPE_U16:
5573 *(u16 *)p = field_value;
5574 break;
5575 case VMCS_FIELD_TYPE_U32:
5576 *(u32 *)p = field_value;
5577 break;
5578 case VMCS_FIELD_TYPE_U64:
5579 *(u64 *)p = field_value;
5580 break;
5581 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5582 *(natural_width *)p = field_value;
5583 break;
5584 default:
5585 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5586 skip_emulated_instruction(vcpu);
5587 return 1;
5588 }
5589
5590 nested_vmx_succeed(vcpu);
5591 skip_emulated_instruction(vcpu);
5592 return 1;
5593}
5594
63846663
NHE		 5595/* Emulate the VMPTRLD instruction */
5596static int handle_vmptrld(struct kvm_vcpu *vcpu)
5597{
5598 struct vcpu_vmx *vmx = to_vmx(vcpu);
5599 gva_t gva;
5600 gpa_t vmptr;
5601 struct x86_exception e;
5602
5603 if (!nested_vmx_check_permission(vcpu))
5604 return 1;
5605
5606 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5607 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5608 return 1;
5609
5610 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5611 sizeof(vmptr), &e)) {
5612 kvm_inject_page_fault(vcpu, &e);
5613 return 1;
5614 }
5615
5616 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5617 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5618 skip_emulated_instruction(vcpu);
5619 return 1;
5620 }
5621
5622 if (vmx->nested.current_vmptr != vmptr) {
5623 struct vmcs12 *new_vmcs12;
5624 struct page *page;
5625 page = nested_get_page(vcpu, vmptr);
5626 if (page == NULL) {
5627 nested_vmx_failInvalid(vcpu);
5628 skip_emulated_instruction(vcpu);
5629 return 1;
5630 }
5631 new_vmcs12 = kmap(page);
5632 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5633 kunmap(page);
5634 nested_release_page_clean(page);
5635 nested_vmx_failValid(vcpu,
5636 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5637 skip_emulated_instruction(vcpu);
5638 return 1;
5639 }
5640 if (vmx->nested.current_vmptr != -1ull) {
5641 kunmap(vmx->nested.current_vmcs12_page);
5642 nested_release_page(vmx->nested.current_vmcs12_page);
5643 }
5644
5645 vmx->nested.current_vmptr = vmptr;
5646 vmx->nested.current_vmcs12 = new_vmcs12;
5647 vmx->nested.current_vmcs12_page = page;
5648 }
5649
5650 nested_vmx_succeed(vcpu);
5651 skip_emulated_instruction(vcpu);
5652 return 1;
5653}
5654
6a4d7550
NHE		 5655/* Emulate the VMPTRST instruction */
5656static int handle_vmptrst(struct kvm_vcpu *vcpu)
5657{
5658 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5659 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5660 gva_t vmcs_gva;
5661 struct x86_exception e;
5662
5663 if (!nested_vmx_check_permission(vcpu))
5664 return 1;
5665
5666 if (get_vmx_mem_address(vcpu, exit_qualification,
5667 vmx_instruction_info, &vmcs_gva))
5668 return 1;
5669 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5670 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5671 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5672 sizeof(u64), &e)) {
5673 kvm_inject_page_fault(vcpu, &e);
5674 return 1;
5675 }
5676 nested_vmx_succeed(vcpu);
5677 skip_emulated_instruction(vcpu);
5678 return 1;
5679}
5680
6aa8b732
AK		 5681/*
5682 * The exit handlers return 1 if the exit was handled fully and guest execution
5683 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5684 * to be done to userspace and return 0.
5685 */
772e0318 5686static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5687 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5688 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5689 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5690 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5691 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5692 [EXIT_REASON_CR_ACCESS] = handle_cr,
5693 [EXIT_REASON_DR_ACCESS] = handle_dr,
5694 [EXIT_REASON_CPUID] = handle_cpuid,
5695 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5696 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5697 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5698 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5699 [EXIT_REASON_INVD] = handle_invd,
a7052897 5700 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5701 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5702 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5703 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5704 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5705 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5706 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5707 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5708 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5709 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5710 [EXIT_REASON_VMOFF] = handle_vmoff,
5711 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5712 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5713 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5714 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5715 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5716 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5717 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5718 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5719 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5720 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5721 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5722 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5723};
5724
5725static const int kvm_vmx_max_exit_handlers =
50a3485c 5726 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5727
644d711a
NHE		 5728/*
5729 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5730 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5731 * disinterest in the current event (read or write a specific MSR) by using an
5732 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5733 */
5734static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5735 struct vmcs12 *vmcs12, u32 exit_reason)
5736{
5737 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5738 gpa_t bitmap;
5739
5740 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5741 return 1;
5742
5743 /*
5744 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5745 * for the four combinations of read/write and low/high MSR numbers.
5746 * First we need to figure out which of the four to use:
5747 */
5748 bitmap = vmcs12->msr_bitmap;
5749 if (exit_reason == EXIT_REASON_MSR_WRITE)
5750 bitmap += 2048;
5751 if (msr_index >= 0xc0000000) {
5752 msr_index -= 0xc0000000;
5753 bitmap += 1024;
5754 }
5755
5756 /* Then read the msr_index'th bit from this bitmap: */
5757 if (msr_index < 1024*8) {
5758 unsigned char b;
5759 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5760 return 1 & (b >> (msr_index & 7));
5761 } else
5762 return 1; /* let L1 handle the wrong parameter */
5763}
5764
5765/*
5766 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5767 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5768 * intercept (via guest_host_mask etc.) the current event.
5769 */
5770static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5771 struct vmcs12 *vmcs12)
5772{
5773 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5774 int cr = exit_qualification & 15;
5775 int reg = (exit_qualification >> 8) & 15;
5776 unsigned long val = kvm_register_read(vcpu, reg);
5777
5778 switch ((exit_qualification >> 4) & 3) {
5779 case 0: /* mov to cr */
5780 switch (cr) {
5781 case 0:
5782 if (vmcs12->cr0_guest_host_mask &
5783 (val ^ vmcs12->cr0_read_shadow))
5784 return 1;
5785 break;
5786 case 3:
5787 if ((vmcs12->cr3_target_count >= 1 &&
5788 vmcs12->cr3_target_value0 == val) ||
5789 (vmcs12->cr3_target_count >= 2 &&
5790 vmcs12->cr3_target_value1 == val) ||
5791 (vmcs12->cr3_target_count >= 3 &&
5792 vmcs12->cr3_target_value2 == val) ||
5793 (vmcs12->cr3_target_count >= 4 &&
5794 vmcs12->cr3_target_value3 == val))
5795 return 0;
5796 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5797 return 1;
5798 break;
5799 case 4:
5800 if (vmcs12->cr4_guest_host_mask &
5801 (vmcs12->cr4_read_shadow ^ val))
5802 return 1;
5803 break;
5804 case 8:
5805 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5806 return 1;
5807 break;
5808 }
5809 break;
5810 case 2: /* clts */
5811 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5812 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5813 return 1;
5814 break;
5815 case 1: /* mov from cr */
5816 switch (cr) {
5817 case 3:
5818 if (vmcs12->cpu_based_vm_exec_control &
5819 CPU_BASED_CR3_STORE_EXITING)
5820 return 1;
5821 break;
5822 case 8:
5823 if (vmcs12->cpu_based_vm_exec_control &
5824 CPU_BASED_CR8_STORE_EXITING)
5825 return 1;
5826 break;
5827 }
5828 break;
5829 case 3: /* lmsw */
5830 /*
5831 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5832 * cr0. Other attempted changes are ignored, with no exit.
5833 */
5834 if (vmcs12->cr0_guest_host_mask & 0xe &
5835 (val ^ vmcs12->cr0_read_shadow))
5836 return 1;
5837 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5838 !(vmcs12->cr0_read_shadow & 0x1) &&
5839 (val & 0x1))
5840 return 1;
5841 break;
5842 }
5843 return 0;
5844}
5845
5846/*
5847 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5848 * should handle it ourselves in L0 (and then continue L2). Only call this
5849 * when in is_guest_mode (L2).
5850 */
5851static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5852{
5853 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5854 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5855 struct vcpu_vmx *vmx = to_vmx(vcpu);
5856 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5857
5858 if (vmx->nested.nested_run_pending)
5859 return 0;
5860
5861 if (unlikely(vmx->fail)) {
bd80158a
JK		 5862 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5863 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5864 return 1;
5865 }
5866
5867 switch (exit_reason) {
5868 case EXIT_REASON_EXCEPTION_NMI:
5869 if (!is_exception(intr_info))
5870 return 0;
5871 else if (is_page_fault(intr_info))
5872 return enable_ept;
5873 return vmcs12->exception_bitmap &
5874 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5875 case EXIT_REASON_EXTERNAL_INTERRUPT:
5876 return 0;
5877 case EXIT_REASON_TRIPLE_FAULT:
5878 return 1;
5879 case EXIT_REASON_PENDING_INTERRUPT:
5880 case EXIT_REASON_NMI_WINDOW:
5881 /*
5882 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5883 * (aka Interrupt Window Exiting) only when L1 turned it on,
5884 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5885 * Same for NMI Window Exiting.
5886 */
5887 return 1;
5888 case EXIT_REASON_TASK_SWITCH:
5889 return 1;
5890 case EXIT_REASON_CPUID:
5891 return 1;
5892 case EXIT_REASON_HLT:
5893 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5894 case EXIT_REASON_INVD:
5895 return 1;
5896 case EXIT_REASON_INVLPG:
5897 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5898 case EXIT_REASON_RDPMC:
5899 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5900 case EXIT_REASON_RDTSC:
5901 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5902 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5903 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5904 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5905 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5906 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5907 /*
5908 * VMX instructions trap unconditionally. This allows L1 to
5909 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5910 */
5911 return 1;
5912 case EXIT_REASON_CR_ACCESS:
5913 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5914 case EXIT_REASON_DR_ACCESS:
5915 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5916 case EXIT_REASON_IO_INSTRUCTION:
5917 /* TODO: support IO bitmaps */
5918 return 1;
5919 case EXIT_REASON_MSR_READ:
5920 case EXIT_REASON_MSR_WRITE:
5921 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5922 case EXIT_REASON_INVALID_STATE:
5923 return 1;
5924 case EXIT_REASON_MWAIT_INSTRUCTION:
5925 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5926 case EXIT_REASON_MONITOR_INSTRUCTION:
5927 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5928 case EXIT_REASON_PAUSE_INSTRUCTION:
5929 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5930 nested_cpu_has2(vmcs12,
5931 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5932 case EXIT_REASON_MCE_DURING_VMENTRY:
5933 return 0;
5934 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5935 return 1;
5936 case EXIT_REASON_APIC_ACCESS:
5937 return nested_cpu_has2(vmcs12,
5938 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5939 case EXIT_REASON_EPT_VIOLATION:
5940 case EXIT_REASON_EPT_MISCONFIG:
5941 return 0;
5942 case EXIT_REASON_WBINVD:
5943 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5944 case EXIT_REASON_XSETBV:
5945 return 1;
5946 default:
5947 return 1;
5948 }
5949}
5950
586f9607
AK		 5951static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5952{
5953 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5954 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5955}
5956
6aa8b732
AK		 5957/*
5958 * The guest has exited. See if we can fix it or if we need userspace
5959 * assistance.
5960 */
851ba692 5961static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5962{
29bd8a78 5963 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5964 u32 exit_reason = vmx->exit_reason;
1155f76a 5965 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5966
80ced186
MG		 5967 /* If guest state is invalid, start emulating */
5968 if (vmx->emulation_required && emulate_invalid_guest_state)
5969 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5970
b6f1250e
NHE		 5971 /*
5972 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5973 * we did not inject a still-pending event to L1 now because of
5974 * nested_run_pending, we need to re-enable this bit.
5975 */
5976 if (vmx->nested.nested_run_pending)
5977 kvm_make_request(KVM_REQ_EVENT, vcpu);
5978
509c75ea
NHE		 5979 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5980 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5981 vmx->nested.nested_run_pending = 1;
5982 else
5983 vmx->nested.nested_run_pending = 0;
5984
5985 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5986 nested_vmx_vmexit(vcpu);
5987 return 1;
5988 }
5989
5120702e
MG		 5990 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5991 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5992 vcpu->run->fail_entry.hardware_entry_failure_reason
5993 = exit_reason;
5994 return 0;
5995 }
5996
29bd8a78 5997 if (unlikely(vmx->fail)) {
851ba692
AK		 5998 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5999 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6000 = vmcs_read32(VM_INSTRUCTION_ERROR);
6001 return 0;
6002 }
6aa8b732 6003
b9bf6882
XG		 6004 /*
6005 * Note:
6006 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6007 * delivery event since it indicates guest is accessing MMIO.
6008 * The vm-exit can be triggered again after return to guest that
6009 * will cause infinite loop.
6010 */
d77c26fc 6011 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6012 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6013 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6014 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6015 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6016 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6017 vcpu->run->internal.ndata = 2;
6018 vcpu->run->internal.data[0] = vectoring_info;
6019 vcpu->run->internal.data[1] = exit_reason;
6020 return 0;
6021 }
3b86cd99 6022
644d711a
NHE		 6023 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6024 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6025 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6026 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6027 vmx->soft_vnmi_blocked = 0;
3b86cd99 6028 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6029 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6030 /*
6031 * This CPU don't support us in finding the end of an
6032 * NMI-blocked window if the guest runs with IRQs
6033 * disabled. So we pull the trigger after 1 s of
6034 * futile waiting, but inform the user about this.
6035 */
6036 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6037 "state on VCPU %d after 1 s timeout\n",
6038 __func__, vcpu->vcpu_id);
6039 vmx->soft_vnmi_blocked = 0;
3b86cd99 6040 }
3b86cd99
JK		 6041 }
6042
6aa8b732
AK		 6043 if (exit_reason < kvm_vmx_max_exit_handlers
6044 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6045 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6046 else {
851ba692
AK		 6047 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6048 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6049 }
6050 return 0;
6051}
6052
95ba8273 6053static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6054{
95ba8273 6055 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6056 vmcs_write32(TPR_THRESHOLD, 0);
6057 return;
6058 }
6059
95ba8273 6060 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6061}
6062
51aa01d1 6063static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6064{
00eba012
AK		 6065 u32 exit_intr_info;
6066
6067 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6068 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6069 return;
6070
c5ca8e57 6071 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6072 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6073
6074 /* Handle machine checks before interrupts are enabled */
00eba012 6075 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6076 kvm_machine_check();
6077
20f65983 6078 /* We need to handle NMIs before interrupts are enabled */
00eba012 6079 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6080 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6081 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6082 asm("int $2");
ff9d07a0
ZY		 6083 kvm_after_handle_nmi(&vmx->vcpu);
6084 }
51aa01d1 6085}
20f65983 6086
51aa01d1
AK		 6087static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6088{
c5ca8e57 6089 u32 exit_intr_info;
51aa01d1
AK		 6090 bool unblock_nmi;
6091 u8 vector;
6092 bool idtv_info_valid;
6093
6094 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6095
cf393f75 6096 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6097 if (vmx->nmi_known_unmasked)
6098 return;
c5ca8e57
AK		 6099 /*
6100 * Can't use vmx->exit_intr_info since we're not sure what
6101 * the exit reason is.
6102 */
6103 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6104 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6105 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6106 /*
7b4a25cb 6107 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6108 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6109 * a guest IRET fault.
7b4a25cb
GN		 6110 * SDM 3: 23.2.2 (September 2008)
6111 * Bit 12 is undefined in any of the following cases:
6112 * If the VM exit sets the valid bit in the IDT-vectoring
6113 * information field.
6114 * If the VM exit is due to a double fault.
cf393f75 6115 */
7b4a25cb
GN		 6116 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6117 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6118 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6119 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6120 else
6121 vmx->nmi_known_unmasked =
6122 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6123 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6124 } else if (unlikely(vmx->soft_vnmi_blocked))
6125 vmx->vnmi_blocked_time +=
6126 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6127}
6128
83422e17
AK		 6129static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6130 u32 idt_vectoring_info,
6131 int instr_len_field,
6132 int error_code_field)
51aa01d1 6133{
51aa01d1
AK		 6134 u8 vector;
6135 int type;
6136 bool idtv_info_valid;
6137
6138 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6139
37b96e98
GN		 6140 vmx->vcpu.arch.nmi_injected = false;
6141 kvm_clear_exception_queue(&vmx->vcpu);
6142 kvm_clear_interrupt_queue(&vmx->vcpu);
6143
6144 if (!idtv_info_valid)
6145 return;
6146
3842d135
AK		 6147 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6148
668f612f
AK		 6149 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6150 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6151
64a7ec06 6152 switch (type) {
37b96e98
GN		 6153 case INTR_TYPE_NMI_INTR:
6154 vmx->vcpu.arch.nmi_injected = true;
668f612f 6155 /*
7b4a25cb 6156 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6157 * Clear bit "block by NMI" before VM entry if a NMI
6158 * delivery faulted.
668f612f 6159 */
654f06fc 6160 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6161 break;
37b96e98 6162 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6163 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6164 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6165 /* fall through */
6166 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6167 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6168 u32 err = vmcs_read32(error_code_field);
37b96e98 6169 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6170 } else
6171 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6172 break;
66fd3f7f
GN		 6173 case INTR_TYPE_SOFT_INTR:
6174 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6175 vmcs_read32(instr_len_field);
66fd3f7f 6176 /* fall through */
37b96e98 6177 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6178 kvm_queue_interrupt(&vmx->vcpu, vector,
6179 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6180 break;
6181 default:
6182 break;
f7d9238f 6183 }
cf393f75
AK		 6184}
6185
83422e17
AK		 6186static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6187{
66c78ae4
NHE		 6188 if (is_guest_mode(&vmx->vcpu))
6189 return;
83422e17
AK		 6190 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6191 VM_EXIT_INSTRUCTION_LEN,
6192 IDT_VECTORING_ERROR_CODE);
6193}
6194
b463a6f7
AK		 6195static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6196{
66c78ae4
NHE		 6197 if (is_guest_mode(vcpu))
6198 return;
b463a6f7
AK		 6199 __vmx_complete_interrupts(to_vmx(vcpu),
6200 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6201 VM_ENTRY_INSTRUCTION_LEN,
6202 VM_ENTRY_EXCEPTION_ERROR_CODE);
6203
6204 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6205}
6206
d7cd9796
GN		 6207static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6208{
6209 int i, nr_msrs;
6210 struct perf_guest_switch_msr *msrs;
6211
6212 msrs = perf_guest_get_msrs(&nr_msrs);
6213
6214 if (!msrs)
6215 return;
6216
6217 for (i = 0; i < nr_msrs; i++)
6218 if (msrs[i].host == msrs[i].guest)
6219 clear_atomic_switch_msr(vmx, msrs[i].msr);
6220 else
6221 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6222 msrs[i].host);
6223}
6224
a3b5ba49 6225static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6226{
a2fa3e9f 6227 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6228 unsigned long debugctlmsr;
104f226b 6229
66c78ae4
NHE		 6230 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6231 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6232 if (vmcs12->idt_vectoring_info_field &
6233 VECTORING_INFO_VALID_MASK) {
6234 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6235 vmcs12->idt_vectoring_info_field);
6236 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6237 vmcs12->vm_exit_instruction_len);
6238 if (vmcs12->idt_vectoring_info_field &
6239 VECTORING_INFO_DELIVER_CODE_MASK)
6240 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6241 vmcs12->idt_vectoring_error_code);
6242 }
6243 }
6244
104f226b
AK		 6245 /* Record the guest's net vcpu time for enforced NMI injections. */
6246 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6247 vmx->entry_time = ktime_get();
6248
6249 /* Don't enter VMX if guest state is invalid, let the exit handler
6250 start emulation until we arrive back to a valid state */
6251 if (vmx->emulation_required && emulate_invalid_guest_state)
6252 return;
6253
6254 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6255 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6256 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6257 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6258
6259 /* When single-stepping over STI and MOV SS, we must clear the
6260 * corresponding interruptibility bits in the guest state. Otherwise
6261 * vmentry fails as it then expects bit 14 (BS) in pending debug
6262 * exceptions being set, but that's not correct for the guest debugging
6263 * case. */
6264 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6265 vmx_set_interrupt_shadow(vcpu, 0);
6266
d7cd9796 6267 atomic_switch_perf_msrs(vmx);
2a7921b7 6268 debugctlmsr = get_debugctlmsr();
d7cd9796 6269
d462b819 6270 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6271 asm(
6aa8b732 6272 /* Store host registers */
b188c81f
AK		 6273 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6274 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6275 "push %%" _ASM_CX " \n\t"
6276 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6277 "je 1f \n\t"
b188c81f 6278 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6279 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6280 "1: \n\t"
d3edefc0 6281 /* Reload cr2 if changed */
b188c81f
AK		 6282 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6283 "mov %%cr2, %%" _ASM_DX " \n\t"
6284 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6285 "je 2f \n\t"
b188c81f 6286 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6287 "2: \n\t"
6aa8b732 6288 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6289 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6290 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6291 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6292 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6293 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6294 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6295 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6296 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6297#ifdef CONFIG_X86_64
e08aa78a
AK		 6298 "mov %c[r8](%0), %%r8 \n\t"
6299 "mov %c[r9](%0), %%r9 \n\t"
6300 "mov %c[r10](%0), %%r10 \n\t"
6301 "mov %c[r11](%0), %%r11 \n\t"
6302 "mov %c[r12](%0), %%r12 \n\t"
6303 "mov %c[r13](%0), %%r13 \n\t"
6304 "mov %c[r14](%0), %%r14 \n\t"
6305 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6306#endif
b188c81f 6307 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6308
6aa8b732 6309 /* Enter guest mode */
83287ea4 6310 "jne 1f \n\t"
4ecac3fd 6311 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6312 "jmp 2f \n\t"
6313 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6314 "2: "
6aa8b732 6315 /* Save guest registers, load host registers, keep flags */
b188c81f 6316 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6317 "pop %0 \n\t"
b188c81f
AK		 6318 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6319 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6320 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6321 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6322 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6323 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6324 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6325#ifdef CONFIG_X86_64
e08aa78a
AK		 6326 "mov %%r8, %c[r8](%0) \n\t"
6327 "mov %%r9, %c[r9](%0) \n\t"
6328 "mov %%r10, %c[r10](%0) \n\t"
6329 "mov %%r11, %c[r11](%0) \n\t"
6330 "mov %%r12, %c[r12](%0) \n\t"
6331 "mov %%r13, %c[r13](%0) \n\t"
6332 "mov %%r14, %c[r14](%0) \n\t"
6333 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6334#endif
b188c81f
AK		 6335 "mov %%cr2, %%" _ASM_AX " \n\t"
6336 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6337
b188c81f 6338 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6339 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6340 ".pushsection .rodata \n\t"
6341 ".global vmx_return \n\t"
6342 "vmx_return: " _ASM_PTR " 2b \n\t"
6343 ".popsection"
e08aa78a 6344 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6345 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6346 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6347 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6348 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6349 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6350 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6351 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6352 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6353 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6354 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6355#ifdef CONFIG_X86_64
ad312c7c
ZX		 6356 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6357 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6358 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6359 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6360 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6361 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6362 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6363 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6364#endif
40712fae
AK		 6365 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6366 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6367 : "cc", "memory"
6368#ifdef CONFIG_X86_64
b188c81f 6369 , "rax", "rbx", "rdi", "rsi"
c2036300 6370 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6371#else
6372 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6373#endif
6374 );
6aa8b732 6375
2a7921b7
GN		 6376 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6377 if (debugctlmsr)
6378 update_debugctlmsr(debugctlmsr);
6379
aa67f609
AK		 6380#ifndef CONFIG_X86_64
6381 /*
6382 * The sysexit path does not restore ds/es, so we must set them to
6383 * a reasonable value ourselves.
6384 *
6385 * We can't defer this to vmx_load_host_state() since that function
6386 * may be executed in interrupt context, which saves and restore segments
6387 * around it, nullifying its effect.
6388 */
6389 loadsegment(ds, __USER_DS);
6390 loadsegment(es, __USER_DS);
6391#endif
6392
6de4f3ad 6393 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6394 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6395 | (1 << VCPU_EXREG_CPL)
aff48baa 6396 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6397 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6398 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6399 vcpu->arch.regs_dirty = 0;
6400
1155f76a
AK		 6401 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6402
66c78ae4
NHE		 6403 if (is_guest_mode(vcpu)) {
6404 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6405 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6406 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6407 vmcs12->idt_vectoring_error_code =
6408 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6409 vmcs12->vm_exit_instruction_len =
6410 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6411 }
6412 }
6413
d462b819 6414 vmx->loaded_vmcs->launched = 1;
1b6269db 6415
51aa01d1 6416 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6417 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6418
6419 vmx_complete_atomic_exit(vmx);
6420 vmx_recover_nmi_blocking(vmx);
cf393f75 6421 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6422}
6423
6aa8b732
AK		 6424static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6425{
fb3f0f51
RR		 6426 struct vcpu_vmx *vmx = to_vmx(vcpu);
6427
cdbecfc3 6428 free_vpid(vmx);
ec378aee 6429 free_nested(vmx);
d462b819 6430 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6431 kfree(vmx->guest_msrs);
6432 kvm_vcpu_uninit(vcpu);
a4770347 6433 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6434}
6435
fb3f0f51 6436static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6437{
fb3f0f51 6438 int err;
c16f862d 6439 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6440 int cpu;
6aa8b732 6441
a2fa3e9f 6442 if (!vmx)
fb3f0f51
RR		 6443 return ERR_PTR(-ENOMEM);
6444
2384d2b3
SY		 6445 allocate_vpid(vmx);
6446
fb3f0f51
RR		 6447 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6448 if (err)
6449 goto free_vcpu;
965b58a5 6450
a2fa3e9f 6451 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6452 err = -ENOMEM;
fb3f0f51 6453 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6454 goto uninit_vcpu;
6455 }
965b58a5 6456
d462b819
NHE		 6457 vmx->loaded_vmcs = &vmx->vmcs01;
6458 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6459 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6460 goto free_msrs;
d462b819
NHE		 6461 if (!vmm_exclusive)
6462 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6463 loaded_vmcs_init(vmx->loaded_vmcs);
6464 if (!vmm_exclusive)
6465 kvm_cpu_vmxoff();
a2fa3e9f 6466
15ad7146
AK		 6467 cpu = get_cpu();
6468 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6469 vmx->vcpu.cpu = cpu;
8b9cf98c 6470 err = vmx_vcpu_setup(vmx);
fb3f0f51 6471 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6472 put_cpu();
fb3f0f51
RR		 6473 if (err)
6474 goto free_vmcs;
5e4a0b3c 6475 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6476 err = alloc_apic_access_page(kvm);
6477 if (err)
5e4a0b3c 6478 goto free_vmcs;
fb3f0f51 6479
b927a3ce
SY		 6480 if (enable_ept) {
6481 if (!kvm->arch.ept_identity_map_addr)
6482 kvm->arch.ept_identity_map_addr =
6483 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6484 err = -ENOMEM;
b7ebfb05
SY		 6485 if (alloc_identity_pagetable(kvm) != 0)
6486 goto free_vmcs;
93ea5388
GN		 6487 if (!init_rmode_identity_map(kvm))
6488 goto free_vmcs;
b927a3ce 6489 }
b7ebfb05 6490
a9d30f33
NHE		 6491 vmx->nested.current_vmptr = -1ull;
6492 vmx->nested.current_vmcs12 = NULL;
6493
fb3f0f51
RR		 6494 return &vmx->vcpu;
6495
6496free_vmcs:
5f3fbc34 6497 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6498free_msrs:
fb3f0f51
RR		 6499 kfree(vmx->guest_msrs);
6500uninit_vcpu:
6501 kvm_vcpu_uninit(&vmx->vcpu);
6502free_vcpu:
cdbecfc3 6503 free_vpid(vmx);
a4770347 6504 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6505 return ERR_PTR(err);
6aa8b732
AK		 6506}
6507
002c7f7c
YS		 6508static void __init vmx_check_processor_compat(void *rtn)
6509{
6510 struct vmcs_config vmcs_conf;
6511
6512 *(int *)rtn = 0;
6513 if (setup_vmcs_config(&vmcs_conf) < 0)
6514 *(int *)rtn = -EIO;
6515 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6516 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6517 smp_processor_id());
6518 *(int *)rtn = -EIO;
6519 }
6520}
6521
67253af5
SY		 6522static int get_ept_level(void)
6523{
6524 return VMX_EPT_DEFAULT_GAW + 1;
6525}
6526
4b12f0de 6527static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6528{
4b12f0de
SY		 6529 u64 ret;
6530
522c68c4
SY		 6531 /* For VT-d and EPT combination
6532 * 1. MMIO: always map as UC
6533 * 2. EPT with VT-d:
6534 * a. VT-d without snooping control feature: can't guarantee the
6535 * result, try to trust guest.
6536 * b. VT-d with snooping control feature: snooping control feature of
6537 * VT-d engine can guarantee the cache correctness. Just set it
6538 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6539 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6540 * consistent with host MTRR
6541 */
4b12f0de
SY		 6542 if (is_mmio)
6543 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6544 else if (vcpu->kvm->arch.iommu_domain &&
6545 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6546 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6547 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6548 else
522c68c4 6549 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6550 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6551
6552 return ret;
64d4d521
SY		 6553}
6554
17cc3935 6555static int vmx_get_lpage_level(void)
344f414f 6556{
878403b7
SY		 6557 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6558 return PT_DIRECTORY_LEVEL;
6559 else
6560 /* For shadow and EPT supported 1GB page */
6561 return PT_PDPE_LEVEL;
344f414f
JR		 6562}
6563
0e851880
SY		 6564static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6565{
4e47c7a6
SY		 6566 struct kvm_cpuid_entry2 *best;
6567 struct vcpu_vmx *vmx = to_vmx(vcpu);
6568 u32 exec_control;
6569
6570 vmx->rdtscp_enabled = false;
6571 if (vmx_rdtscp_supported()) {
6572 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6573 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6574 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6575 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6576 vmx->rdtscp_enabled = true;
6577 else {
6578 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6579 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6580 exec_control);
6581 }
6582 }
6583 }
ad756a16
MJ		 6584
6585 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6586 /* Exposing INVPCID only when PCID is exposed */
6587 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6588 if (vmx_invpcid_supported() &&
4f977045 6589 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16
MJ		 6590 guest_cpuid_has_pcid(vcpu)) {
6591 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6592 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6593 exec_control);
6594 } else {
6595 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6596 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6597 exec_control);
6598 if (best)
4f977045 6599 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6600 }
0e851880
SY		 6601}
6602
d4330ef2
JR		 6603static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6604{
7b8050f5
NHE		 6605 if (func == 1 && nested)
6606 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6607}
6608
fe3ef05c
NHE		 6609/*
6610 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6611 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6612 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6613 * guest in a way that will both be appropriate to L1's requests, and our
6614 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6615 * function also has additional necessary side-effects, like setting various
6616 * vcpu->arch fields.
6617 */
6618static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6619{
6620 struct vcpu_vmx *vmx = to_vmx(vcpu);
6621 u32 exec_control;
6622
6623 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6624 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6625 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6626 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6627 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6628 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6629 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6630 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6631 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6632 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6633 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6634 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6635 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6636 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6637 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6638 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6639 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6640 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6641 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6642 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6643 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6644 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6645 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6646 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6647 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6648 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6649 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6650 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6651 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6652 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6653 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6654 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6655 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6656 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6657 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6658 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6659
6660 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6661 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6662 vmcs12->vm_entry_intr_info_field);
6663 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6664 vmcs12->vm_entry_exception_error_code);
6665 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6666 vmcs12->vm_entry_instruction_len);
6667 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6668 vmcs12->guest_interruptibility_info);
6669 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6670 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6671 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6672 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6673 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6674 vmcs12->guest_pending_dbg_exceptions);
6675 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6676 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6677
6678 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6679
6680 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6681 (vmcs_config.pin_based_exec_ctrl |
6682 vmcs12->pin_based_vm_exec_control));
6683
6684 /*
6685 * Whether page-faults are trapped is determined by a combination of
6686 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6687 * If enable_ept, L0 doesn't care about page faults and we should
6688 * set all of these to L1's desires. However, if !enable_ept, L0 does
6689 * care about (at least some) page faults, and because it is not easy
6690 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6691 * to exit on each and every L2 page fault. This is done by setting
6692 * MASK=MATCH=0 and (see below) EB.PF=1.
6693 * Note that below we don't need special code to set EB.PF beyond the
6694 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6695 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6696 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6697 *
6698 * A problem with this approach (when !enable_ept) is that L1 may be
6699 * injected with more page faults than it asked for. This could have
6700 * caused problems, but in practice existing hypervisors don't care.
6701 * To fix this, we will need to emulate the PFEC checking (on the L1
6702 * page tables), using walk_addr(), when injecting PFs to L1.
6703 */
6704 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6705 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6706 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6707 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6708
6709 if (cpu_has_secondary_exec_ctrls()) {
6710 u32 exec_control = vmx_secondary_exec_control(vmx);
6711 if (!vmx->rdtscp_enabled)
6712 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6713 /* Take the following fields only from vmcs12 */
6714 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6715 if (nested_cpu_has(vmcs12,
6716 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6717 exec_control |= vmcs12->secondary_vm_exec_control;
6718
6719 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6720 /*
6721 * Translate L1 physical address to host physical
6722 * address for vmcs02. Keep the page pinned, so this
6723 * physical address remains valid. We keep a reference
6724 * to it so we can release it later.
6725 */
6726 if (vmx->nested.apic_access_page) /* shouldn't happen */
6727 nested_release_page(vmx->nested.apic_access_page);
6728 vmx->nested.apic_access_page =
6729 nested_get_page(vcpu, vmcs12->apic_access_addr);
6730 /*
6731 * If translation failed, no matter: This feature asks
6732 * to exit when accessing the given address, and if it
6733 * can never be accessed, this feature won't do
6734 * anything anyway.
6735 */
6736 if (!vmx->nested.apic_access_page)
6737 exec_control &=
6738 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6739 else
6740 vmcs_write64(APIC_ACCESS_ADDR,
6741 page_to_phys(vmx->nested.apic_access_page));
6742 }
6743
6744 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6745 }
6746
6747
6748 /*
6749 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6750 * Some constant fields are set here by vmx_set_constant_host_state().
6751 * Other fields are different per CPU, and will be set later when
6752 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6753 */
6754 vmx_set_constant_host_state();
6755
6756 /*
6757 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6758 * entry, but only if the current (host) sp changed from the value
6759 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6760 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6761 * here we just force the write to happen on entry.
6762 */
6763 vmx->host_rsp = 0;
6764
6765 exec_control = vmx_exec_control(vmx); /* L0's desires */
6766 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6767 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6768 exec_control &= ~CPU_BASED_TPR_SHADOW;
6769 exec_control |= vmcs12->cpu_based_vm_exec_control;
6770 /*
6771 * Merging of IO and MSR bitmaps not currently supported.
6772 * Rather, exit every time.
6773 */
6774 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6775 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6776 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6777
6778 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6779
6780 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6781 * bitwise-or of what L1 wants to trap for L2, and what we want to
6782 * trap. Note that CR0.TS also needs updating - we do this later.
6783 */
6784 update_exception_bitmap(vcpu);
6785 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6786 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6787
6788 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6789 vmcs_write32(VM_EXIT_CONTROLS,
6790 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6791 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6792 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6793
6794 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6795 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6796 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6797 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6798
6799
6800 set_cr4_guest_host_mask(vmx);
6801
27fc51b2
NHE		 6802 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6803 vmcs_write64(TSC_OFFSET,
6804 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6805 else
6806 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6807
6808 if (enable_vpid) {
6809 /*
6810 * Trivially support vpid by letting L2s share their parent
6811 * L1's vpid. TODO: move to a more elaborate solution, giving
6812 * each L2 its own vpid and exposing the vpid feature to L1.
6813 */
6814 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6815 vmx_flush_tlb(vcpu);
6816 }
6817
6818 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6819 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6820 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6821 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6822 else
6823 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6824 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6825 vmx_set_efer(vcpu, vcpu->arch.efer);
6826
6827 /*
6828 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6829 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6830 * The CR0_READ_SHADOW is what L2 should have expected to read given
6831 * the specifications by L1; It's not enough to take
6832 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6833 * have more bits than L1 expected.
6834 */
6835 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6836 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6837
6838 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6839 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6840
6841 /* shadow page tables on either EPT or shadow page tables */
6842 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6843 kvm_mmu_reset_context(vcpu);
6844
6845 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6846 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6847}
6848
cd232ad0
NHE		 6849/*
6850 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6851 * for running an L2 nested guest.
6852 */
6853static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6854{
6855 struct vmcs12 *vmcs12;
6856 struct vcpu_vmx *vmx = to_vmx(vcpu);
6857 int cpu;
6858 struct loaded_vmcs *vmcs02;
6859
6860 if (!nested_vmx_check_permission(vcpu) ||
6861 !nested_vmx_check_vmcs12(vcpu))
6862 return 1;
6863
6864 skip_emulated_instruction(vcpu);
6865 vmcs12 = get_vmcs12(vcpu);
6866
7c177938
NHE		 6867 /*
6868 * The nested entry process starts with enforcing various prerequisites
6869 * on vmcs12 as required by the Intel SDM, and act appropriately when
6870 * they fail: As the SDM explains, some conditions should cause the
6871 * instruction to fail, while others will cause the instruction to seem
6872 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6873 * To speed up the normal (success) code path, we should avoid checking
6874 * for misconfigurations which will anyway be caught by the processor
6875 * when using the merged vmcs02.
6876 */
6877 if (vmcs12->launch_state == launch) {
6878 nested_vmx_failValid(vcpu,
6879 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6880 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6881 return 1;
6882 }
6883
6884 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6885 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6886 /*TODO: Also verify bits beyond physical address width are 0*/
6887 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6888 return 1;
6889 }
6890
6891 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6892 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6893 /*TODO: Also verify bits beyond physical address width are 0*/
6894 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6895 return 1;
6896 }
6897
6898 if (vmcs12->vm_entry_msr_load_count > 0 ||
6899 vmcs12->vm_exit_msr_load_count > 0 ||
6900 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6901 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6902 __func__);
7c177938
NHE		 6903 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6904 return 1;
6905 }
6906
6907 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6908 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6909 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6910 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6911 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6912 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6913 !vmx_control_verify(vmcs12->vm_exit_controls,
6914 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6915 !vmx_control_verify(vmcs12->vm_entry_controls,
6916 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6917 {
6918 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6919 return 1;
6920 }
6921
6922 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6923 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6924 nested_vmx_failValid(vcpu,
6925 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6926 return 1;
6927 }
6928
6929 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6930 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6931 nested_vmx_entry_failure(vcpu, vmcs12,
6932 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6933 return 1;
6934 }
6935 if (vmcs12->vmcs_link_pointer != -1ull) {
6936 nested_vmx_entry_failure(vcpu, vmcs12,
6937 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6938 return 1;
6939 }
6940
6941 /*
6942 * We're finally done with prerequisite checking, and can start with
6943 * the nested entry.
6944 */
6945
cd232ad0
NHE		 6946 vmcs02 = nested_get_current_vmcs02(vmx);
6947 if (!vmcs02)
6948 return -ENOMEM;
6949
6950 enter_guest_mode(vcpu);
6951
6952 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6953
6954 cpu = get_cpu();
6955 vmx->loaded_vmcs = vmcs02;
6956 vmx_vcpu_put(vcpu);
6957 vmx_vcpu_load(vcpu, cpu);
6958 vcpu->cpu = cpu;
6959 put_cpu();
6960
6961 vmcs12->launch_state = 1;
6962
6963 prepare_vmcs02(vcpu, vmcs12);
6964
6965 /*
6966 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6967 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6968 * returned as far as L1 is concerned. It will only return (and set
6969 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6970 */
6971 return 1;
6972}
6973
4704d0be
NHE		 6974/*
6975 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6976 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6977 * This function returns the new value we should put in vmcs12.guest_cr0.
6978 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6979 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6980 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6981 * didn't trap the bit, because if L1 did, so would L0).
6982 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6983 * been modified by L2, and L1 knows it. So just leave the old value of
6984 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6985 * isn't relevant, because if L0 traps this bit it can set it to anything.
6986 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6987 * changed these bits, and therefore they need to be updated, but L0
6988 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6989 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6990 */
6991static inline unsigned long
6992vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6993{
6994 return
6995 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6996 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6997 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6998 vcpu->arch.cr0_guest_owned_bits));
6999}
7000
7001static inline unsigned long
7002vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7003{
7004 return
7005 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7006 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7007 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7008 vcpu->arch.cr4_guest_owned_bits));
7009}
7010
7011/*
7012 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7013 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7014 * and this function updates it to reflect the changes to the guest state while
7015 * L2 was running (and perhaps made some exits which were handled directly by L0
7016 * without going back to L1), and to reflect the exit reason.
7017 * Note that we do not have to copy here all VMCS fields, just those that
7018 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7019 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7020 * which already writes to vmcs12 directly.
7021 */
7022void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7023{
7024 /* update guest state fields: */
7025 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7026 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7027
7028 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7029 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7030 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7031 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7032
7033 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7034 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7035 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7036 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7037 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7038 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7039 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7040 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7041 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7042 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7043 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7044 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7045 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7046 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7047 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7048 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7049 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7050 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7051 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7052 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7053 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7054 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7055 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7056 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7057 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7058 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7059 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7060 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7061 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7062 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7063 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7064 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7065 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7066 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7067 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7068 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7069
7070 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7071 vmcs12->guest_interruptibility_info =
7072 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7073 vmcs12->guest_pending_dbg_exceptions =
7074 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7075
7076 /* TODO: These cannot have changed unless we have MSR bitmaps and
7077 * the relevant bit asks not to trap the change */
7078 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7079 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7080 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7081 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7082 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7083 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7084
7085 /* update exit information fields: */
7086
7087 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7088 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7089
7090 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7091 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7092 vmcs12->idt_vectoring_info_field =
7093 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7094 vmcs12->idt_vectoring_error_code =
7095 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7096 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7097 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7098
7099 /* clear vm-entry fields which are to be cleared on exit */
7100 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7101 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7102}
7103
7104/*
7105 * A part of what we need to when the nested L2 guest exits and we want to
7106 * run its L1 parent, is to reset L1's guest state to the host state specified
7107 * in vmcs12.
7108 * This function is to be called not only on normal nested exit, but also on
7109 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7110 * Failures During or After Loading Guest State").
7111 * This function should be called when the active VMCS is L1's (vmcs01).
7112 */
7113void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7114{
7115 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7116 vcpu->arch.efer = vmcs12->host_ia32_efer;
7117 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7118 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7119 else
7120 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7121 vmx_set_efer(vcpu, vcpu->arch.efer);
7122
7123 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7124 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7125 /*
7126 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7127 * actually changed, because it depends on the current state of
7128 * fpu_active (which may have changed).
7129 * Note that vmx_set_cr0 refers to efer set above.
7130 */
7131 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7132 /*
7133 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7134 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7135 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7136 */
7137 update_exception_bitmap(vcpu);
7138 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7139 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7140
7141 /*
7142 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7143 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7144 */
7145 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7146 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7147
7148 /* shadow page tables on either EPT or shadow page tables */
7149 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7150 kvm_mmu_reset_context(vcpu);
7151
7152 if (enable_vpid) {
7153 /*
7154 * Trivially support vpid by letting L2s share their parent
7155 * L1's vpid. TODO: move to a more elaborate solution, giving
7156 * each L2 its own vpid and exposing the vpid feature to L1.
7157 */
7158 vmx_flush_tlb(vcpu);
7159 }
7160
7161
7162 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7163 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7164 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7165 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7166 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7167 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7168 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7169 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7170 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7171 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7172 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7173 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7174 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7175 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7176 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7177
7178 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7179 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7180 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7181 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7182 vmcs12->host_ia32_perf_global_ctrl);
7183}
7184
7185/*
7186 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7187 * and modify vmcs12 to make it see what it would expect to see there if
7188 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7189 */
7190static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7191{
7192 struct vcpu_vmx *vmx = to_vmx(vcpu);
7193 int cpu;
7194 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7195
7196 leave_guest_mode(vcpu);
7197 prepare_vmcs12(vcpu, vmcs12);
7198
7199 cpu = get_cpu();
7200 vmx->loaded_vmcs = &vmx->vmcs01;
7201 vmx_vcpu_put(vcpu);
7202 vmx_vcpu_load(vcpu, cpu);
7203 vcpu->cpu = cpu;
7204 put_cpu();
7205
7206 /* if no vmcs02 cache requested, remove the one we used */
7207 if (VMCS02_POOL_SIZE == 0)
7208 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7209
7210 load_vmcs12_host_state(vcpu, vmcs12);
7211
27fc51b2 7212 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7213 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7214
7215 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7216 vmx->host_rsp = 0;
7217
7218 /* Unpin physical memory we referred to in vmcs02 */
7219 if (vmx->nested.apic_access_page) {
7220 nested_release_page(vmx->nested.apic_access_page);
7221 vmx->nested.apic_access_page = 0;
7222 }
7223
7224 /*
7225 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7226 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7227 * success or failure flag accordingly.
7228 */
7229 if (unlikely(vmx->fail)) {
7230 vmx->fail = 0;
7231 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7232 } else
7233 nested_vmx_succeed(vcpu);
7234}
7235
7c177938
NHE		 7236/*
7237 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7238 * 23.7 "VM-entry failures during or after loading guest state" (this also
7239 * lists the acceptable exit-reason and exit-qualification parameters).
7240 * It should only be called before L2 actually succeeded to run, and when
7241 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7242 */
7243static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7244 struct vmcs12 *vmcs12,
7245 u32 reason, unsigned long qualification)
7246{
7247 load_vmcs12_host_state(vcpu, vmcs12);
7248 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7249 vmcs12->exit_qualification = qualification;
7250 nested_vmx_succeed(vcpu);
7251}
7252
8a76d7f2
JR		 7253static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7254 struct x86_instruction_info *info,
7255 enum x86_intercept_stage stage)
7256{
7257 return X86EMUL_CONTINUE;
7258}
7259
cbdd1bea 7260static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7261 .cpu_has_kvm_support = cpu_has_kvm_support,
7262 .disabled_by_bios = vmx_disabled_by_bios,
7263 .hardware_setup = hardware_setup,
7264 .hardware_unsetup = hardware_unsetup,
002c7f7c 7265 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7266 .hardware_enable = hardware_enable,
7267 .hardware_disable = hardware_disable,
04547156 7268 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7269
7270 .vcpu_create = vmx_create_vcpu,
7271 .vcpu_free = vmx_free_vcpu,
04d2cc77 7272 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7273
04d2cc77 7274 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7275 .vcpu_load = vmx_vcpu_load,
7276 .vcpu_put = vmx_vcpu_put,
7277
c8639010 7278 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7279 .get_msr = vmx_get_msr,
7280 .set_msr = vmx_set_msr,
7281 .get_segment_base = vmx_get_segment_base,
7282 .get_segment = vmx_get_segment,
7283 .set_segment = vmx_set_segment,
2e4d2653 7284 .get_cpl = vmx_get_cpl,
6aa8b732 7285 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7286 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7287 .decache_cr3 = vmx_decache_cr3,
25c4c276 7288 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7289 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7290 .set_cr3 = vmx_set_cr3,
7291 .set_cr4 = vmx_set_cr4,
6aa8b732 7292 .set_efer = vmx_set_efer,
6aa8b732
AK		 7293 .get_idt = vmx_get_idt,
7294 .set_idt = vmx_set_idt,
7295 .get_gdt = vmx_get_gdt,
7296 .set_gdt = vmx_set_gdt,
020df079 7297 .set_dr7 = vmx_set_dr7,
5fdbf976 7298 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7299 .get_rflags = vmx_get_rflags,
7300 .set_rflags = vmx_set_rflags,
ebcbab4c 7301 .fpu_activate = vmx_fpu_activate,
02daab21 7302 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7303
7304 .tlb_flush = vmx_flush_tlb,
6aa8b732 7305
6aa8b732 7306 .run = vmx_vcpu_run,
6062d012 7307 .handle_exit = vmx_handle_exit,
6aa8b732 7308 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7309 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7310 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7311 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7312 .set_irq = vmx_inject_irq,
95ba8273 7313 .set_nmi = vmx_inject_nmi,
298101da 7314 .queue_exception = vmx_queue_exception,
b463a6f7 7315 .cancel_injection = vmx_cancel_injection,
78646121 7316 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7317 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7318 .get_nmi_mask = vmx_get_nmi_mask,
7319 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7320 .enable_nmi_window = enable_nmi_window,
7321 .enable_irq_window = enable_irq_window,
7322 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7323
cbc94022 7324 .set_tss_addr = vmx_set_tss_addr,
67253af5 7325 .get_tdp_level = get_ept_level,
4b12f0de 7326 .get_mt_mask = vmx_get_mt_mask,
229456fc 7327
586f9607 7328 .get_exit_info = vmx_get_exit_info,
586f9607 7329
17cc3935 7330 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7331
7332 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7333
7334 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7335 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7336
7337 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7338
7339 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7340
4051b188 7341 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7342 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7343 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7344 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7345 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7346
7347 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7348
7349 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7350};
7351
7352static int __init vmx_init(void)
7353{
26bb0981
AK		 7354 int r, i;
7355
7356 rdmsrl_safe(MSR_EFER, &host_efer);
7357
7358 for (i = 0; i < NR_VMX_MSR; ++i)
7359 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7360
3e7c73e9 7361 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7362 if (!vmx_io_bitmap_a)
7363 return -ENOMEM;
7364
2106a548
GC		 7365 r = -ENOMEM;
7366
3e7c73e9 7367 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7368 if (!vmx_io_bitmap_b)
fdef3ad1 7369 goto out;
fdef3ad1 7370
5897297b 7371 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7372 if (!vmx_msr_bitmap_legacy)
25c5f225 7373 goto out1;
2106a548 7374
25c5f225 7375
5897297b 7376 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7377 if (!vmx_msr_bitmap_longmode)
5897297b 7378 goto out2;
2106a548 7379
5897297b 7380
fdef3ad1
HQ		 7381 /*
7382 * Allow direct access to the PC debug port (it is often used for I/O
7383 * delays, but the vmexits simply slow things down).
7384 */
3e7c73e9
AK		 7385 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7386 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7387
3e7c73e9 7388 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7389
5897297b
AK		 7390 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7391 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7392
2384d2b3
SY		 7393 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7394
0ee75bea
AK		 7395 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7396 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7397 if (r)
5897297b 7398 goto out3;
25c5f225 7399
5897297b
AK		 7400 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7401 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7402 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7403 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7404 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7405 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7406
089d034e 7407 if (enable_ept) {
3f6d8c8a
XH		 7408 kvm_mmu_set_mask_ptes(0ull,
7409 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7410 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7411 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7412 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7413 kvm_enable_tdp();
7414 } else
7415 kvm_disable_tdp();
1439442c 7416
fdef3ad1
HQ		 7417 return 0;
7418
5897297b
AK		 7419out3:
7420 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7421out2:
5897297b 7422 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7423out1:
3e7c73e9 7424 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7425out:
3e7c73e9 7426 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7427 return r;
6aa8b732
AK		 7428}
7429
7430static void __exit vmx_exit(void)
7431{
5897297b
AK		 7432 free_page((unsigned long)vmx_msr_bitmap_legacy);
7433 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7434 free_page((unsigned long)vmx_io_bitmap_b);
7435 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7436
cb498ea2 7437 kvm_exit();
6aa8b732
AK		 7438}
7439
7440module_init(vmx_init)
7441module_exit(vmx_exit)
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