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target-i386: Loop-based copying and setting/unsetting of feature words
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
621626ce
EH		 266#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
267#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
268 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
269#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
270 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
271 CPUID_PSE36 | CPUID_FXSR)
272#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
273#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
274 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
275 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
276 CPUID_PAE | CPUID_SEP | CPUID_APIC)
277
278#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
279 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
280 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
281 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
282 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
283 /* partly implemented:
284 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
285 /* missing:
286 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
287#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
288 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
289 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
290 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
291 /* missing:
292 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
293 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
294 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
295 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
296 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
297 CPUID_EXT_RDRAND */
298
299#ifdef TARGET_X86_64
300#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
301#else
302#define TCG_EXT2_X86_64_FEATURES 0
303#endif
304
305#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
306 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
307 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
308 TCG_EXT2_X86_64_FEATURES)
309#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
310 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
311#define TCG_EXT4_FEATURES 0
312#define TCG_SVM_FEATURES 0
313#define TCG_KVM_FEATURES 0
314#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
315 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
316 /* missing:
317 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
318 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
319 CPUID_7_0_EBX_RDSEED */
320
321
5ef57876
EH		 322typedef struct FeatureWordInfo {
323 const char **feat_names;
04d104b6
EH		 324 uint32_t cpuid_eax; /* Input EAX for CPUID */
325 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
326 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
327 int cpuid_reg; /* output register (R_* constant) */
5ef57876
EH		 328} FeatureWordInfo;
329
330static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 331 [FEAT_1_EDX] = {
332 .feat_names = feature_name,
333 .cpuid_eax = 1, .cpuid_reg = R_EDX,
334 },
335 [FEAT_1_ECX] = {
336 .feat_names = ext_feature_name,
337 .cpuid_eax = 1, .cpuid_reg = R_ECX,
338 },
339 [FEAT_8000_0001_EDX] = {
340 .feat_names = ext2_feature_name,
341 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
342 },
343 [FEAT_8000_0001_ECX] = {
344 .feat_names = ext3_feature_name,
345 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
346 },
89e49c8b
EH		 347 [FEAT_C000_0001_EDX] = {
348 .feat_names = ext4_feature_name,
349 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
350 },
bffd67b0
EH		 351 [FEAT_KVM] = {
352 .feat_names = kvm_feature_name,
353 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
354 },
355 [FEAT_SVM] = {
356 .feat_names = svm_feature_name,
357 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
358 },
359 [FEAT_7_0_EBX] = {
360 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 361 .cpuid_eax = 7,
362 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
363 .cpuid_reg = R_EBX,
bffd67b0 364 },
5ef57876
EH		 365};
366
8e8aba50
EH		 367typedef struct X86RegisterInfo32 {
368 /* Name of register */
369 const char *name;
370 /* QAPI enum value register */
371 X86CPURegister32 qapi_enum;
372} X86RegisterInfo32;
373
374#define REGISTER(reg) \
5d371f41 375 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 376static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 377 REGISTER(EAX),
378 REGISTER(ECX),
379 REGISTER(EDX),
380 REGISTER(EBX),
381 REGISTER(ESP),
382 REGISTER(EBP),
383 REGISTER(ESI),
384 REGISTER(EDI),
385};
386#undef REGISTER
387
2560f19f
PB		 388typedef struct ExtSaveArea {
389 uint32_t feature, bits;
390 uint32_t offset, size;
391} ExtSaveArea;
392
393static const ExtSaveArea ext_save_areas[] = {
394 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 395 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 396 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
397 .offset = 0x3c0, .size = 0x40 },
398 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 399 .offset = 0x400, .size = 0x40 },
2560f19f 400};
8e8aba50 401
8b4beddc
EH		 402const char *get_register_name_32(unsigned int reg)
403{
31ccdde2 404 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 405 return NULL;
406 }
8e8aba50 407 return x86_reg_info_32[reg].name;
8b4beddc
EH		 408}
409
c6dc6f63
AP		 410/* collects per-function cpuid data
411 */
412typedef struct model_features_t {
413 uint32_t *guest_feat;
414 uint32_t *host_feat;
bffd67b0 415 FeatureWord feat_word;
8b4beddc 416} model_features_t;
c6dc6f63 417
5fcca9ff
EH		 418/* KVM-specific features that are automatically added to all CPU models
419 * when KVM is enabled.
420 */
421static uint32_t kvm_default_features[FEATURE_WORDS] = {
422 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 423 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 424 (1 << KVM_FEATURE_CLOCKSOURCE2) |
425 (1 << KVM_FEATURE_ASYNC_PF) |
426 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 427 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 428 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 429 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 430};
dc59944b 431
136a7e9a
EH		 432/* Features that are not added by default to any CPU model when KVM is enabled.
433 */
434static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
435 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
436};
437
8fb4f821 438void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 439{
8fb4f821 440 kvm_default_features[w] &= ~features;
dc59944b
MT		 441}
442
bb44e0d1
JK		 443void host_cpuid(uint32_t function, uint32_t count,
444 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 445{
a1fd24af
AL		 446 uint32_t vec[4];
447
448#ifdef __x86_64__
449 asm volatile("cpuid"
450 : "=a"(vec[0]), "=b"(vec[1]),
451 "=c"(vec[2]), "=d"(vec[3])
452 : "0"(function), "c"(count) : "cc");
c1f41226 453#elif defined(__i386__)
a1fd24af
AL		 454 asm volatile("pusha \n\t"
455 "cpuid \n\t"
456 "mov %%eax, 0(%2) \n\t"
457 "mov %%ebx, 4(%2) \n\t"
458 "mov %%ecx, 8(%2) \n\t"
459 "mov %%edx, 12(%2) \n\t"
460 "popa"
461 : : "a"(function), "c"(count), "S"(vec)
462 : "memory", "cc");
c1f41226
EH		 463#else
464 abort();
a1fd24af
AL		 465#endif
466
bdde476a 467 if (eax)
a1fd24af 468 *eax = vec[0];
bdde476a 469 if (ebx)
a1fd24af 470 *ebx = vec[1];
bdde476a 471 if (ecx)
a1fd24af 472 *ecx = vec[2];
bdde476a 473 if (edx)
a1fd24af 474 *edx = vec[3];
bdde476a 475}
c6dc6f63
AP		 476
477#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
478
479/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
480 * a substring. ex if !NULL points to the first char after a substring,
481 * otherwise the string is assumed to sized by a terminating nul.
482 * Return lexical ordering of *s1:*s2.
483 */
484static int sstrcmp(const char *s1, const char *e1, const char *s2,
485 const char *e2)
486{
487 for (;;) {
488 if (!*s1 || !*s2 || *s1 != *s2)
489 return (*s1 - *s2);
490 ++s1, ++s2;
491 if (s1 == e1 && s2 == e2)
492 return (0);
493 else if (s1 == e1)
494 return (*s2);
495 else if (s2 == e2)
496 return (*s1);
497 }
498}
499
500/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
501 * '|' delimited (possibly empty) strings in which case search for a match
502 * within the alternatives proceeds left to right. Return 0 for success,
503 * non-zero otherwise.
504 */
505static int altcmp(const char *s, const char *e, const char *altstr)
506{
507 const char *p, *q;
508
509 for (q = p = altstr; ; ) {
510 while (*p && *p != '|')
511 ++p;
512 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
513 return (0);
514 if (!*p)
515 return (1);
516 else
517 q = ++p;
518 }
519}
520
521/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 522 * *pval and return true, otherwise return false
c6dc6f63 523 */
e41e0fc6
JK		 524static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
525 const char **featureset)
c6dc6f63
AP		 526{
527 uint32_t mask;
528 const char **ppc;
e41e0fc6 529 bool found = false;
c6dc6f63 530
e41e0fc6 531 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 532 if (*ppc && !altcmp(s, e, *ppc)) {
533 *pval |= mask;
e41e0fc6 534 found = true;
c6dc6f63 535 }
e41e0fc6
JK		 536 }
537 return found;
c6dc6f63
AP		 538}
539
5ef57876
EH		 540static void add_flagname_to_bitmaps(const char *flagname,
541 FeatureWordArray words)
c6dc6f63 542{
5ef57876
EH		 543 FeatureWord w;
544 for (w = 0; w < FEATURE_WORDS; w++) {
545 FeatureWordInfo *wi = &feature_word_info[w];
546 if (wi->feat_names &&
547 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
548 break;
549 }
550 }
551 if (w == FEATURE_WORDS) {
552 fprintf(stderr, "CPU feature %s not found\n", flagname);
553 }
c6dc6f63
AP		 554}
555
d940ee9b
EH		 556/* CPU class name definitions: */
557
558#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
559#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
560
561/* Return type name for a given CPU model name
562 * Caller is responsible for freeing the returned string.
563 */
564static char *x86_cpu_type_name(const char *model_name)
565{
566 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
567}
568
500050d1
AF		 569static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
570{
d940ee9b
EH		 571 ObjectClass *oc;
572 char *typename;
573
500050d1
AF		 574 if (cpu_model == NULL) {
575 return NULL;
576 }
577
d940ee9b
EH		 578 typename = x86_cpu_type_name(cpu_model);
579 oc = object_class_by_name(typename);
580 g_free(typename);
581 return oc;
500050d1
AF		 582}
583
d940ee9b 584struct X86CPUDefinition {
c6dc6f63
AP		 585 const char *name;
586 uint32_t level;
90e4b0c3
EH		 587 uint32_t xlevel;
588 uint32_t xlevel2;
99b88a17
IM		 589 /* vendor is zero-terminated, 12 character ASCII string */
590 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 591 int family;
592 int model;
593 int stepping;
0514ef2f 594 FeatureWordArray features;
c6dc6f63 595 char model_id[48];
787aaf57 596 bool cache_info_passthrough;
d940ee9b 597};
c6dc6f63 598
9576de75 599static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 600 {
601 .name = "qemu64",
602 .level = 4,
99b88a17 603 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 604 .family = 6,
f8e6a11a 605 .model = 6,
c6dc6f63 606 .stepping = 3,
0514ef2f 607 .features[FEAT_1_EDX] =
27861ecc 608 PPRO_FEATURES |
c6dc6f63 609 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 610 CPUID_PSE36,
0514ef2f 611 .features[FEAT_1_ECX] =
27861ecc 612 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 613 .features[FEAT_8000_0001_EDX] =
27861ecc 614 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 615 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 616 .features[FEAT_8000_0001_ECX] =
27861ecc 617 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 618 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
619 .xlevel = 0x8000000A,
c6dc6f63
AP		 620 },
621 {
622 .name = "phenom",
623 .level = 5,
99b88a17 624 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 625 .family = 16,
626 .model = 2,
627 .stepping = 3,
0514ef2f 628 .features[FEAT_1_EDX] =
27861ecc 629 PPRO_FEATURES |
c6dc6f63 630 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 631 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 632 .features[FEAT_1_ECX] =
27861ecc 633 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 634 CPUID_EXT_POPCNT,
0514ef2f 635 .features[FEAT_8000_0001_EDX] =
27861ecc 636 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 637 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
638 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 639 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 640 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
641 CPUID_EXT3_CR8LEG,
642 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
643 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 644 .features[FEAT_8000_0001_ECX] =
27861ecc 645 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 646 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 647 .features[FEAT_SVM] =
27861ecc 648 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 649 .xlevel = 0x8000001A,
650 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
651 },
652 {
653 .name = "core2duo",
654 .level = 10,
99b88a17 655 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 656 .family = 6,
657 .model = 15,
658 .stepping = 11,
0514ef2f 659 .features[FEAT_1_EDX] =
27861ecc 660 PPRO_FEATURES |
c6dc6f63 661 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 662 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
663 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 664 .features[FEAT_1_ECX] =
27861ecc 665 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 666 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
667 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 668 .features[FEAT_8000_0001_EDX] =
27861ecc 669 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 670 .features[FEAT_8000_0001_ECX] =
27861ecc 671 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 672 .xlevel = 0x80000008,
673 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
674 },
675 {
676 .name = "kvm64",
677 .level = 5,
99b88a17 678 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 679 .family = 15,
680 .model = 6,
681 .stepping = 1,
682 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 683 .features[FEAT_1_EDX] =
27861ecc 684 PPRO_FEATURES |
c6dc6f63
AP		 685 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
686 CPUID_PSE36,
687 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 688 .features[FEAT_1_ECX] =
27861ecc 689 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 690 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 691 .features[FEAT_8000_0001_EDX] =
27861ecc 692 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 693 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
694 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
695 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
696 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
697 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 698 .features[FEAT_8000_0001_ECX] =
27861ecc 699 0,
c6dc6f63
AP		 700 .xlevel = 0x80000008,
701 .model_id = "Common KVM processor"
702 },
c6dc6f63
AP		 703 {
704 .name = "qemu32",
705 .level = 4,
99b88a17 706 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 707 .family = 6,
f8e6a11a 708 .model = 6,
c6dc6f63 709 .stepping = 3,
0514ef2f 710 .features[FEAT_1_EDX] =
27861ecc 711 PPRO_FEATURES,
0514ef2f 712 .features[FEAT_1_ECX] =
27861ecc 713 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 714 .xlevel = 0x80000004,
c6dc6f63 715 },
eafaf1e5
AP		 716 {
717 .name = "kvm32",
718 .level = 5,
99b88a17 719 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 720 .family = 15,
721 .model = 6,
722 .stepping = 1,
0514ef2f 723 .features[FEAT_1_EDX] =
27861ecc 724 PPRO_FEATURES |
eafaf1e5 725 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 726 .features[FEAT_1_ECX] =
27861ecc 727 CPUID_EXT_SSE3,
0514ef2f 728 .features[FEAT_8000_0001_EDX] =
27861ecc 729 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 730 .features[FEAT_8000_0001_ECX] =
27861ecc 731 0,
eafaf1e5
AP		 732 .xlevel = 0x80000008,
733 .model_id = "Common 32-bit KVM processor"
734 },
c6dc6f63
AP		 735 {
736 .name = "coreduo",
737 .level = 10,
99b88a17 738 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 739 .family = 6,
740 .model = 14,
741 .stepping = 8,
0514ef2f 742 .features[FEAT_1_EDX] =
27861ecc 743 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 744 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
745 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 746 .features[FEAT_1_ECX] =
27861ecc 747 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 748 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 749 .features[FEAT_8000_0001_EDX] =
27861ecc 750 CPUID_EXT2_NX,
c6dc6f63
AP		 751 .xlevel = 0x80000008,
752 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
753 },
754 {
755 .name = "486",
58012d66 756 .level = 1,
99b88a17 757 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 758 .family = 4,
b2a856d9 759 .model = 8,
c6dc6f63 760 .stepping = 0,
0514ef2f 761 .features[FEAT_1_EDX] =
27861ecc 762 I486_FEATURES,
c6dc6f63
AP		 763 .xlevel = 0,
764 },
765 {
766 .name = "pentium",
767 .level = 1,
99b88a17 768 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 769 .family = 5,
770 .model = 4,
771 .stepping = 3,
0514ef2f 772 .features[FEAT_1_EDX] =
27861ecc 773 PENTIUM_FEATURES,
c6dc6f63
AP		 774 .xlevel = 0,
775 },
776 {
777 .name = "pentium2",
778 .level = 2,
99b88a17 779 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 780 .family = 6,
781 .model = 5,
782 .stepping = 2,
0514ef2f 783 .features[FEAT_1_EDX] =
27861ecc 784 PENTIUM2_FEATURES,
c6dc6f63
AP		 785 .xlevel = 0,
786 },
787 {
788 .name = "pentium3",
789 .level = 2,
99b88a17 790 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 791 .family = 6,
792 .model = 7,
793 .stepping = 3,
0514ef2f 794 .features[FEAT_1_EDX] =
27861ecc 795 PENTIUM3_FEATURES,
c6dc6f63
AP		 796 .xlevel = 0,
797 },
798 {
799 .name = "athlon",
800 .level = 2,
99b88a17 801 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 802 .family = 6,
803 .model = 2,
804 .stepping = 3,
0514ef2f 805 .features[FEAT_1_EDX] =
27861ecc 806 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 807 CPUID_MCA,
0514ef2f 808 .features[FEAT_8000_0001_EDX] =
27861ecc 809 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 810 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 811 .xlevel = 0x80000008,
c6dc6f63
AP		 812 },
813 {
814 .name = "n270",
815 /* original is on level 10 */
816 .level = 5,
99b88a17 817 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 818 .family = 6,
819 .model = 28,
820 .stepping = 2,
0514ef2f 821 .features[FEAT_1_EDX] =
27861ecc 822 PPRO_FEATURES |
8560efed
AJ		 823 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
824 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 825 /* Some CPUs got no CPUID_SEP */
0514ef2f 826 .features[FEAT_1_ECX] =
27861ecc 827 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 828 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
829 CPUID_EXT_MOVBE,
0514ef2f 830 .features[FEAT_8000_0001_EDX] =
27861ecc 831 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 832 CPUID_EXT2_NX,
0514ef2f 833 .features[FEAT_8000_0001_ECX] =
27861ecc 834 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 835 .xlevel = 0x8000000A,
836 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
837 },
3eca4642
EH		 838 {
839 .name = "Conroe",
6b11322e 840 .level = 4,
99b88a17 841 .vendor = CPUID_VENDOR_INTEL,
3eca4642 842 .family = 6,
ffce9ebb 843 .model = 15,
3eca4642 844 .stepping = 3,
0514ef2f 845 .features[FEAT_1_EDX] =
27861ecc 846 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
850 CPUID_DE | CPUID_FP87,
0514ef2f 851 .features[FEAT_1_ECX] =
27861ecc 852 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 853 .features[FEAT_8000_0001_EDX] =
27861ecc 854 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 855 .features[FEAT_8000_0001_ECX] =
27861ecc 856 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 857 .xlevel = 0x8000000A,
858 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
859 },
860 {
861 .name = "Penryn",
6b11322e 862 .level = 4,
99b88a17 863 .vendor = CPUID_VENDOR_INTEL,
3eca4642 864 .family = 6,
ffce9ebb 865 .model = 23,
3eca4642 866 .stepping = 3,
0514ef2f 867 .features[FEAT_1_EDX] =
27861ecc 868 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 869 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
870 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
871 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
872 CPUID_DE | CPUID_FP87,
0514ef2f 873 .features[FEAT_1_ECX] =
27861ecc 874 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 875 CPUID_EXT_SSE3,
0514ef2f 876 .features[FEAT_8000_0001_EDX] =
27861ecc 877 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 878 .features[FEAT_8000_0001_ECX] =
27861ecc 879 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 880 .xlevel = 0x8000000A,
881 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
882 },
883 {
884 .name = "Nehalem",
6b11322e 885 .level = 4,
99b88a17 886 .vendor = CPUID_VENDOR_INTEL,
3eca4642 887 .family = 6,
ffce9ebb 888 .model = 26,
3eca4642 889 .stepping = 3,
0514ef2f 890 .features[FEAT_1_EDX] =
27861ecc 891 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 892 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
893 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
894 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
895 CPUID_DE | CPUID_FP87,
0514ef2f 896 .features[FEAT_1_ECX] =
27861ecc 897 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 898 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 899 .features[FEAT_8000_0001_EDX] =
27861ecc 900 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 901 .features[FEAT_8000_0001_ECX] =
27861ecc 902 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 903 .xlevel = 0x8000000A,
904 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
905 },
906 {
907 .name = "Westmere",
908 .level = 11,
99b88a17 909 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 910 .family = 6,
911 .model = 44,
912 .stepping = 1,
0514ef2f 913 .features[FEAT_1_EDX] =
27861ecc 914 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 915 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
916 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
917 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
918 CPUID_DE | CPUID_FP87,
0514ef2f 919 .features[FEAT_1_ECX] =
27861ecc 920 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 921 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 922 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 923 .features[FEAT_8000_0001_EDX] =
27861ecc 924 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 925 .features[FEAT_8000_0001_ECX] =
27861ecc 926 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 927 .xlevel = 0x8000000A,
928 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
929 },
930 {
931 .name = "SandyBridge",
932 .level = 0xd,
99b88a17 933 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 934 .family = 6,
935 .model = 42,
936 .stepping = 1,
0514ef2f 937 .features[FEAT_1_EDX] =
27861ecc 938 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 939 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
940 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
941 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
942 CPUID_DE | CPUID_FP87,
0514ef2f 943 .features[FEAT_1_ECX] =
27861ecc 944 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 945 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
946 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
947 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
948 CPUID_EXT_SSE3,
0514ef2f 949 .features[FEAT_8000_0001_EDX] =
27861ecc 950 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 951 CPUID_EXT2_SYSCALL,
0514ef2f 952 .features[FEAT_8000_0001_ECX] =
27861ecc 953 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 954 .xlevel = 0x8000000A,
955 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
956 },
37507094
EH		 957 {
958 .name = "Haswell",
959 .level = 0xd,
99b88a17 960 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 961 .family = 6,
962 .model = 60,
963 .stepping = 1,
0514ef2f 964 .features[FEAT_1_EDX] =
27861ecc 965 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 966 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 967 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 968 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
969 CPUID_DE | CPUID_FP87,
0514ef2f 970 .features[FEAT_1_ECX] =
27861ecc 971 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 972 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
973 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
974 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
975 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
976 CPUID_EXT_PCID,
0514ef2f 977 .features[FEAT_8000_0001_EDX] =
27861ecc 978 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 979 CPUID_EXT2_SYSCALL,
0514ef2f 980 .features[FEAT_8000_0001_ECX] =
27861ecc 981 CPUID_EXT3_LAHF_LM,
0514ef2f 982 .features[FEAT_7_0_EBX] =
27861ecc 983 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 984 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
985 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
986 CPUID_7_0_EBX_RTM,
987 .xlevel = 0x8000000A,
988 .model_id = "Intel Core Processor (Haswell)",
989 },
3eca4642
EH		 990 {
991 .name = "Opteron_G1",
992 .level = 5,
99b88a17 993 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 994 .family = 15,
995 .model = 6,
996 .stepping = 1,
0514ef2f 997 .features[FEAT_1_EDX] =
27861ecc 998 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 999 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1000 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1001 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1002 CPUID_DE | CPUID_FP87,
0514ef2f 1003 .features[FEAT_1_ECX] =
27861ecc 1004 CPUID_EXT_SSE3,
0514ef2f 1005 .features[FEAT_8000_0001_EDX] =
27861ecc 1006 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 1007 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1008 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1009 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1010 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1011 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1012 .xlevel = 0x80000008,
1013 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1014 },
1015 {
1016 .name = "Opteron_G2",
1017 .level = 5,
99b88a17 1018 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1019 .family = 15,
1020 .model = 6,
1021 .stepping = 1,
0514ef2f 1022 .features[FEAT_1_EDX] =
27861ecc 1023 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1024 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1025 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1026 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1027 CPUID_DE | CPUID_FP87,
0514ef2f 1028 .features[FEAT_1_ECX] =
27861ecc 1029 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1030 .features[FEAT_8000_0001_EDX] =
27861ecc 1031 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1032 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1033 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1034 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1035 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1036 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1037 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1038 .features[FEAT_8000_0001_ECX] =
27861ecc 1039 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1040 .xlevel = 0x80000008,
1041 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1042 },
1043 {
1044 .name = "Opteron_G3",
1045 .level = 5,
99b88a17 1046 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1047 .family = 15,
1048 .model = 6,
1049 .stepping = 1,
0514ef2f 1050 .features[FEAT_1_EDX] =
27861ecc 1051 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1055 CPUID_DE | CPUID_FP87,
0514ef2f 1056 .features[FEAT_1_ECX] =
27861ecc 1057 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1058 CPUID_EXT_SSE3,
0514ef2f 1059 .features[FEAT_8000_0001_EDX] =
27861ecc 1060 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1061 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1062 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1063 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1064 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1065 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1066 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1067 .features[FEAT_8000_0001_ECX] =
27861ecc 1068 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1069 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1070 .xlevel = 0x80000008,
1071 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1072 },
1073 {
1074 .name = "Opteron_G4",
1075 .level = 0xd,
99b88a17 1076 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1077 .family = 21,
1078 .model = 1,
1079 .stepping = 2,
0514ef2f 1080 .features[FEAT_1_EDX] =
27861ecc 1081 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1082 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1083 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1084 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1085 CPUID_DE | CPUID_FP87,
0514ef2f 1086 .features[FEAT_1_ECX] =
27861ecc 1087 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1088 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1089 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1090 CPUID_EXT_SSE3,
0514ef2f 1091 .features[FEAT_8000_0001_EDX] =
27861ecc 1092 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1093 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1094 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1095 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1096 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1097 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1098 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1099 .features[FEAT_8000_0001_ECX] =
27861ecc 1100 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1101 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1102 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1103 CPUID_EXT3_LAHF_LM,
1104 .xlevel = 0x8000001A,
1105 .model_id = "AMD Opteron 62xx class CPU",
1106 },
021941b9
AP		 1107 {
1108 .name = "Opteron_G5",
1109 .level = 0xd,
99b88a17 1110 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1111 .family = 21,
1112 .model = 2,
1113 .stepping = 0,
0514ef2f 1114 .features[FEAT_1_EDX] =
27861ecc 1115 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1116 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1117 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1118 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1119 CPUID_DE | CPUID_FP87,
0514ef2f 1120 .features[FEAT_1_ECX] =
27861ecc 1121 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1122 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1123 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1124 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1125 .features[FEAT_8000_0001_EDX] =
27861ecc 1126 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1127 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1128 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1129 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1130 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1131 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1132 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1133 .features[FEAT_8000_0001_ECX] =
27861ecc 1134 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1135 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1136 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1137 CPUID_EXT3_LAHF_LM,
1138 .xlevel = 0x8000001A,
1139 .model_id = "AMD Opteron 63xx class CPU",
1140 },
c6dc6f63
AP		 1141};
1142
0668af54
EH		 1143/**
1144 * x86_cpu_compat_set_features:
1145 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1146 * @w: Identifies the feature word to be changed.
1147 * @feat_add: Feature bits to be added to feature word
1148 * @feat_remove: Feature bits to be removed from feature word
1149 *
1150 * Change CPU model feature bits for compatibility.
1151 *
1152 * This function may be used by machine-type compatibility functions
1153 * to enable or disable feature bits on specific CPU models.
1154 */
1155void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1156 uint32_t feat_add, uint32_t feat_remove)
1157{
9576de75 1158 X86CPUDefinition *def;
0668af54
EH		 1159 int i;
1160 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1161 def = &builtin_x86_defs[i];
1162 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1163 def->features[w] |= feat_add;
1164 def->features[w] &= ~feat_remove;
1165 }
1166 }
1167}
1168
d940ee9b
EH		 1169#ifdef CONFIG_KVM
1170
c6dc6f63
AP		 1171static int cpu_x86_fill_model_id(char *str)
1172{
1173 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1174 int i;
1175
1176 for (i = 0; i < 3; i++) {
1177 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1178 memcpy(str + i * 16 + 0, &eax, 4);
1179 memcpy(str + i * 16 + 4, &ebx, 4);
1180 memcpy(str + i * 16 + 8, &ecx, 4);
1181 memcpy(str + i * 16 + 12, &edx, 4);
1182 }
1183 return 0;
1184}
1185
d940ee9b
EH		 1186static X86CPUDefinition host_cpudef;
1187
1188/* class_init for the "host" CPU model
6e746f30 1189 *
d940ee9b 1190 * This function may be called before KVM is initialized.
6e746f30 1191 */
d940ee9b 1192static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1193{
d940ee9b 1194 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1195 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1196
d940ee9b 1197 xcc->kvm_required = true;
6e746f30 1198
c6dc6f63 1199 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1200 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1201
1202 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1203 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1204 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1205 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1206
d940ee9b 1207 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1208
d940ee9b
EH		 1209 xcc->cpu_def = &host_cpudef;
1210 host_cpudef.cache_info_passthrough = true;
1211
1212 /* level, xlevel, xlevel2, and the feature words are initialized on
1213 * instance_init, because they require KVM to be initialized.
1214 */
1215}
1216
1217static void host_x86_cpu_initfn(Object *obj)
1218{
1219 X86CPU *cpu = X86_CPU(obj);
1220 CPUX86State *env = &cpu->env;
1221 KVMState *s = kvm_state;
1222 FeatureWord w;
1223
1224 assert(kvm_enabled());
1225
1226 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1227 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1228 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1229
2bc65d2b
EH		 1230 for (w = 0; w < FEATURE_WORDS; w++) {
1231 FeatureWordInfo *wi = &feature_word_info[w];
d940ee9b 1232 env->features[w] =
2bc65d2b
EH		 1233 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1234 wi->cpuid_reg);
1235 }
d940ee9b 1236 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1237}
1238
d940ee9b
EH		 1239static const TypeInfo host_x86_cpu_type_info = {
1240 .name = X86_CPU_TYPE_NAME("host"),
1241 .parent = TYPE_X86_CPU,
1242 .instance_init = host_x86_cpu_initfn,
1243 .class_init = host_x86_cpu_class_init,
1244};
1245
1246#endif
1247
8459e396 1248static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1249{
8459e396 1250 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1251 int i;
1252
857aee33 1253 for (i = 0; i < 32; ++i) {
c6dc6f63 1254 if (1 << i & mask) {
bffd67b0 1255 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1256 assert(reg);
1257 fprintf(stderr, "warning: host doesn't support requested feature: "
1258 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1259 f->cpuid_eax, reg,
1260 f->feat_names[i] ? "." : "",
1261 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1262 }
857aee33 1263 }
c6dc6f63
AP		 1264}
1265
95b8519d
AF		 1266static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1267 const char *name, Error **errp)
1268{
1269 X86CPU *cpu = X86_CPU(obj);
1270 CPUX86State *env = &cpu->env;
1271 int64_t value;
1272
1273 value = (env->cpuid_version >> 8) & 0xf;
1274 if (value == 0xf) {
1275 value += (env->cpuid_version >> 20) & 0xff;
1276 }
1277 visit_type_int(v, &value, name, errp);
1278}
1279
71ad61d3
AF		 1280static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1281 const char *name, Error **errp)
ed5e1ec3 1282{
71ad61d3
AF		 1283 X86CPU *cpu = X86_CPU(obj);
1284 CPUX86State *env = &cpu->env;
1285 const int64_t min = 0;
1286 const int64_t max = 0xff + 0xf;
65cd9064 1287 Error *local_err = NULL;
71ad61d3
AF		 1288 int64_t value;
1289
65cd9064
MA		 1290 visit_type_int(v, &value, name, &local_err);
1291 if (local_err) {
1292 error_propagate(errp, local_err);
71ad61d3
AF		 1293 return;
1294 }
1295 if (value < min || value > max) {
1296 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1297 name ? name : "null", value, min, max);
1298 return;
1299 }
1300
ed5e1ec3 1301 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1302 if (value > 0x0f) {
1303 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1304 } else {
71ad61d3 1305 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1306 }
1307}
1308
67e30c83
AF		 1309static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1310 const char *name, Error **errp)
1311{
1312 X86CPU *cpu = X86_CPU(obj);
1313 CPUX86State *env = &cpu->env;
1314 int64_t value;
1315
1316 value = (env->cpuid_version >> 4) & 0xf;
1317 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1318 visit_type_int(v, &value, name, errp);
1319}
1320
c5291a4f
AF		 1321static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1322 const char *name, Error **errp)
b0704cbd 1323{
c5291a4f
AF		 1324 X86CPU *cpu = X86_CPU(obj);
1325 CPUX86State *env = &cpu->env;
1326 const int64_t min = 0;
1327 const int64_t max = 0xff;
65cd9064 1328 Error *local_err = NULL;
c5291a4f
AF		 1329 int64_t value;
1330
65cd9064
MA		 1331 visit_type_int(v, &value, name, &local_err);
1332 if (local_err) {
1333 error_propagate(errp, local_err);
c5291a4f
AF		 1334 return;
1335 }
1336 if (value < min || value > max) {
1337 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1338 name ? name : "null", value, min, max);
1339 return;
1340 }
1341
b0704cbd 1342 env->cpuid_version &= ~0xf00f0;
c5291a4f 1343 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1344}
1345
35112e41
AF		 1346static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1347 void *opaque, const char *name,
1348 Error **errp)
1349{
1350 X86CPU *cpu = X86_CPU(obj);
1351 CPUX86State *env = &cpu->env;
1352 int64_t value;
1353
1354 value = env->cpuid_version & 0xf;
1355 visit_type_int(v, &value, name, errp);
1356}
1357
036e2222
AF		 1358static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1359 void *opaque, const char *name,
1360 Error **errp)
38c3dc46 1361{
036e2222
AF		 1362 X86CPU *cpu = X86_CPU(obj);
1363 CPUX86State *env = &cpu->env;
1364 const int64_t min = 0;
1365 const int64_t max = 0xf;
65cd9064 1366 Error *local_err = NULL;
036e2222
AF		 1367 int64_t value;
1368
65cd9064
MA		 1369 visit_type_int(v, &value, name, &local_err);
1370 if (local_err) {
1371 error_propagate(errp, local_err);
036e2222
AF		 1372 return;
1373 }
1374 if (value < min || value > max) {
1375 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1376 name ? name : "null", value, min, max);
1377 return;
1378 }
1379
38c3dc46 1380 env->cpuid_version &= ~0xf;
036e2222 1381 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1382}
1383
8e1898bf
AF		 1384static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1385 const char *name, Error **errp)
1386{
1387 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1388
fa029887 1389 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1390}
1391
1392static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1393 const char *name, Error **errp)
1394{
1395 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1396
fa029887 1397 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1398}
1399
16b93aa8
AF		 1400static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1401 const char *name, Error **errp)
1402{
1403 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1404
fa029887 1405 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1406}
1407
1408static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1409 const char *name, Error **errp)
1410{
1411 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1412
fa029887 1413 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1414}
1415
d480e1af
AF		 1416static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1417{
1418 X86CPU *cpu = X86_CPU(obj);
1419 CPUX86State *env = &cpu->env;
1420 char *value;
d480e1af 1421
9df694ee 1422 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1423 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1424 env->cpuid_vendor3);
d480e1af
AF		 1425 return value;
1426}
1427
1428static void x86_cpuid_set_vendor(Object *obj, const char *value,
1429 Error **errp)
1430{
1431 X86CPU *cpu = X86_CPU(obj);
1432 CPUX86State *env = &cpu->env;
1433 int i;
1434
9df694ee 1435 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1436 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1437 "vendor", value);
1438 return;
1439 }
1440
1441 env->cpuid_vendor1 = 0;
1442 env->cpuid_vendor2 = 0;
1443 env->cpuid_vendor3 = 0;
1444 for (i = 0; i < 4; i++) {
1445 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1446 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1447 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1448 }
d480e1af
AF		 1449}
1450
63e886eb
AF		 1451static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1452{
1453 X86CPU *cpu = X86_CPU(obj);
1454 CPUX86State *env = &cpu->env;
1455 char *value;
1456 int i;
1457
1458 value = g_malloc(48 + 1);
1459 for (i = 0; i < 48; i++) {
1460 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1461 }
1462 value[48] = '\0';
1463 return value;
1464}
1465
938d4c25
AF		 1466static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1467 Error **errp)
dcce6675 1468{
938d4c25
AF		 1469 X86CPU *cpu = X86_CPU(obj);
1470 CPUX86State *env = &cpu->env;
dcce6675
AF		 1471 int c, len, i;
1472
1473 if (model_id == NULL) {
1474 model_id = "";
1475 }
1476 len = strlen(model_id);
d0a6acf4 1477 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1478 for (i = 0; i < 48; i++) {
1479 if (i >= len) {
1480 c = '\0';
1481 } else {
1482 c = (uint8_t)model_id[i];
1483 }
1484 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1485 }
1486}
1487
89e48965
AF		 1488static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1489 const char *name, Error **errp)
1490{
1491 X86CPU *cpu = X86_CPU(obj);
1492 int64_t value;
1493
1494 value = cpu->env.tsc_khz * 1000;
1495 visit_type_int(v, &value, name, errp);
1496}
1497
1498static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1499 const char *name, Error **errp)
1500{
1501 X86CPU *cpu = X86_CPU(obj);
1502 const int64_t min = 0;
2e84849a 1503 const int64_t max = INT64_MAX;
65cd9064 1504 Error *local_err = NULL;
89e48965
AF		 1505 int64_t value;
1506
65cd9064
MA		 1507 visit_type_int(v, &value, name, &local_err);
1508 if (local_err) {
1509 error_propagate(errp, local_err);
89e48965
AF		 1510 return;
1511 }
1512 if (value < min || value > max) {
1513 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1514 name ? name : "null", value, min, max);
1515 return;
1516 }
1517
1518 cpu->env.tsc_khz = value / 1000;
1519}
1520
31050930
IM		 1521static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1522 const char *name, Error **errp)
1523{
1524 X86CPU *cpu = X86_CPU(obj);
1525 int64_t value = cpu->env.cpuid_apic_id;
1526
1527 visit_type_int(v, &value, name, errp);
1528}
1529
1530static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1531 const char *name, Error **errp)
1532{
1533 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1534 DeviceState *dev = DEVICE(obj);
31050930
IM		 1535 const int64_t min = 0;
1536 const int64_t max = UINT32_MAX;
1537 Error *error = NULL;
1538 int64_t value;
1539
8d6d4980
IM		 1540 if (dev->realized) {
1541 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1542 "it was realized", name, object_get_typename(obj));
1543 return;
1544 }
1545
31050930
IM		 1546 visit_type_int(v, &value, name, &error);
1547 if (error) {
1548 error_propagate(errp, error);
1549 return;
1550 }
1551 if (value < min || value > max) {
1552 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1553 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1554 object_get_typename(obj), name, value, min, max);
1555 return;
1556 }
1557
1558 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1559 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1560 return;
1561 }
1562 cpu->env.cpuid_apic_id = value;
1563}
1564
7e5292b5 1565/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1566static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1567 const char *name, Error **errp)
1568{
7e5292b5 1569 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1570 FeatureWord w;
1571 Error *err = NULL;
1572 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1573 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1574 X86CPUFeatureWordInfoList *list = NULL;
1575
1576 for (w = 0; w < FEATURE_WORDS; w++) {
1577 FeatureWordInfo *wi = &feature_word_info[w];
1578 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1579 qwi->cpuid_input_eax = wi->cpuid_eax;
1580 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1581 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1582 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1583 qwi->features = array[w];
8e8aba50
EH		 1584
1585 /* List will be in reverse order, but order shouldn't matter */
1586 list_entries[w].next = list;
1587 list_entries[w].value = &word_infos[w];
1588 list = &list_entries[w];
1589 }
1590
1591 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1592 error_propagate(errp, err);
1593}
1594
c8f0f88e
IM		 1595static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1596 const char *name, Error **errp)
1597{
1598 X86CPU *cpu = X86_CPU(obj);
1599 int64_t value = cpu->hyperv_spinlock_attempts;
1600
1601 visit_type_int(v, &value, name, errp);
1602}
1603
1604static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1605 const char *name, Error **errp)
1606{
1607 const int64_t min = 0xFFF;
1608 const int64_t max = UINT_MAX;
1609 X86CPU *cpu = X86_CPU(obj);
1610 Error *err = NULL;
1611 int64_t value;
1612
1613 visit_type_int(v, &value, name, &err);
1614 if (err) {
1615 error_propagate(errp, err);
1616 return;
1617 }
1618
1619 if (value < min || value > max) {
1620 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1621 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1622 object_get_typename(obj), name ? name : "null",
1623 value, min, max);
1624 return;
1625 }
1626 cpu->hyperv_spinlock_attempts = value;
1627}
1628
1629static PropertyInfo qdev_prop_spinlocks = {
1630 .name = "int",
1631 .get = x86_get_hv_spinlocks,
1632 .set = x86_set_hv_spinlocks,
1633};
1634
72ac2e87
IM		 1635/* Convert all '_' in a feature string option name to '-', to make feature
1636 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1637 */
1638static inline void feat2prop(char *s)
1639{
1640 while ((s = strchr(s, '_'))) {
1641 *s = '-';
1642 }
1643}
1644
8f961357
EH		 1645/* Parse "+feature,-feature,feature=foo" CPU feature string
1646 */
94a444b2
AF		 1647static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1648 Error **errp)
8f961357 1649{
94a444b2 1650 X86CPU *cpu = X86_CPU(cs);
8f961357 1651 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1652 FeatureWord w;
8f961357 1653 /* Features to be added */
077c68c3 1654 FeatureWordArray plus_features = { 0 };
8f961357 1655 /* Features to be removed */
5ef57876 1656 FeatureWordArray minus_features = { 0 };
8f961357 1657 uint32_t numvalue;
a91987c2 1658 CPUX86State *env = &cpu->env;
94a444b2 1659 Error *local_err = NULL;
8f961357 1660
8f961357 1661 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1662
1663 while (featurestr) {
1664 char *val;
1665 if (featurestr[0] == '+') {
5ef57876 1666 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1667 } else if (featurestr[0] == '-') {
5ef57876 1668 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1669 } else if ((val = strchr(featurestr, '='))) {
1670 *val = 0; val++;
72ac2e87 1671 feat2prop(featurestr);
d024d209 1672 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1673 char *err;
a91987c2
IM		 1674 char num[32];
1675
c6dc6f63
AP		 1676 numvalue = strtoul(val, &err, 0);
1677 if (!*val || *err) {
6b1dd54b
PB		 1678 error_setg(errp, "bad numerical value %s", val);
1679 return;
c6dc6f63
AP		 1680 }
1681 if (numvalue < 0x80000000) {
94a444b2
AF		 1682 error_report("xlevel value shall always be >= 0x80000000"
1683 ", fixup will be removed in future versions");
2f7a21c4 1684 numvalue += 0x80000000;
c6dc6f63 1685 }
a91987c2 1686 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1687 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1688 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1689 int64_t tsc_freq;
1690 char *err;
a91987c2 1691 char num[32];
b862d1fe
JR		 1692
1693 tsc_freq = strtosz_suffix_unit(val, &err,
1694 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1695 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1696 error_setg(errp, "bad numerical value %s", val);
1697 return;
b862d1fe 1698 }
a91987c2 1699 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1700 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1701 &local_err);
72ac2e87 1702 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1703 char *err;
92067bf4 1704 const int min = 0xFFF;
c8f0f88e 1705 char num[32];
28f52cc0
VR		 1706 numvalue = strtoul(val, &err, 0);
1707 if (!*val || *err) {
6b1dd54b
PB		 1708 error_setg(errp, "bad numerical value %s", val);
1709 return;
28f52cc0 1710 }
92067bf4 1711 if (numvalue < min) {
94a444b2
AF		 1712 error_report("hv-spinlocks value shall always be >= 0x%x"
1713 ", fixup will be removed in future versions",
92067bf4
IM		 1714 min);
1715 numvalue = min;
1716 }
c8f0f88e 1717 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1718 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1719 } else {
94a444b2 1720 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1721 }
c6dc6f63 1722 } else {
258f5abe 1723 feat2prop(featurestr);
94a444b2 1724 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1725 }
94a444b2
AF		 1726 if (local_err) {
1727 error_propagate(errp, local_err);
6b1dd54b 1728 return;
c6dc6f63
AP		 1729 }
1730 featurestr = strtok(NULL, ",");
1731 }
e1c224b4
EH		 1732
1733 for (w = 0; w < FEATURE_WORDS; w++) {
1734 env->features[w] |= plus_features[w];
1735 env->features[w] &= ~minus_features[w];
1736 }
c6dc6f63
AP		 1737}
1738
1739/* generate a composite string into buf of all cpuid names in featureset
1740 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1741 * if flags, suppress names undefined in featureset.
1742 */
1743static void listflags(char *buf, int bufsize, uint32_t fbits,
1744 const char **featureset, uint32_t flags)
1745{
1746 const char **p = &featureset[31];
1747 char *q, *b, bit;
1748 int nc;
1749
1750 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1751 *buf = '\0';
1752 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1753 if (fbits & 1 << bit && (*p || !flags)) {
1754 if (*p)
1755 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1756 else
1757 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1758 if (bufsize <= nc) {
1759 if (b) {
1760 memcpy(b, "...", sizeof("..."));
1761 }
1762 return;
1763 }
1764 q += nc;
1765 bufsize -= nc;
1766 }
1767}
1768
e916cbf8
PM		 1769/* generate CPU information. */
1770void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1771{
9576de75 1772 X86CPUDefinition *def;
c6dc6f63 1773 char buf[256];
7fc9b714 1774 int i;
c6dc6f63 1775
7fc9b714
AF		 1776 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1777 def = &builtin_x86_defs[i];
c04321b3 1778 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1779 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1780 }
21ad7789
JK		 1781#ifdef CONFIG_KVM
1782 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1783 "KVM processor with all supported host features "
1784 "(only available in KVM mode)");
1785#endif
1786
6cdf8854 1787 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1788 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1789 FeatureWordInfo *fw = &feature_word_info[i];
1790
1791 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1792 (*cpu_fprintf)(f, " %s\n", buf);
1793 }
c6dc6f63
AP		 1794}
1795
76b64a7a 1796CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1797{
1798 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1799 X86CPUDefinition *def;
7fc9b714 1800 int i;
e3966126 1801
7fc9b714 1802 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1803 CpuDefinitionInfoList *entry;
1804 CpuDefinitionInfo *info;
1805
7fc9b714 1806 def = &builtin_x86_defs[i];
e3966126
AL		 1807 info = g_malloc0(sizeof(*info));
1808 info->name = g_strdup(def->name);
1809
1810 entry = g_malloc0(sizeof(*entry));
1811 entry->value = info;
1812 entry->next = cpu_list;
1813 cpu_list = entry;
1814 }
1815
1816 return cpu_list;
1817}
1818
27418adf
EH		 1819static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w)
1820{
1821 FeatureWordInfo *wi = &feature_word_info[w];
1822
1823 assert(kvm_enabled());
1824 return kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1825 wi->cpuid_ecx,
1826 wi->cpuid_reg);
1827}
1828
51f63aed
EH		 1829/*
1830 * Filters CPU feature words based on host availability of each feature.
1831 *
1832 * This function may be called only if KVM is enabled.
1833 *
1834 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1835 */
27418adf 1836static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 1837{
1838 CPUX86State *env = &cpu->env;
bd87d2a2 1839 FeatureWord w;
51f63aed
EH		 1840 int rv = 0;
1841
bd87d2a2 1842 for (w = 0; w < FEATURE_WORDS; w++) {
27418adf 1843 uint32_t host_feat = x86_cpu_get_supported_feature_word(w);
034acf4a
EH		 1844 uint32_t requested_features = env->features[w];
1845 env->features[w] &= host_feat;
1846 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 1847 if (cpu->filtered_features[w]) {
1848 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 1849 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 1850 }
1851 rv = 1;
1852 }
bd87d2a2 1853 }
51f63aed
EH		 1854
1855 return rv;
bc74b7db 1856}
bc74b7db 1857
d940ee9b 1858/* Load data from X86CPUDefinition
c080e30e 1859 */
d940ee9b 1860static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1861{
61dcd775 1862 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1863 const char *vendor;
1864 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 1865 FeatureWord w;
c6dc6f63 1866
2d64255b
AF		 1867 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1868 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1869 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1870 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 1871 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 1872 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1873 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 1874 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 1875 for (w = 0; w < FEATURE_WORDS; w++) {
1876 env->features[w] = def->features[w];
1877 }
82beb536 1878
9576de75 1879 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1880 if (kvm_enabled()) {
5fcca9ff
EH		 1881 FeatureWord w;
1882 for (w = 0; w < FEATURE_WORDS; w++) {
1883 env->features[w] |= kvm_default_features[w];
136a7e9a 1884 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 1885 }
82beb536 1886 }
5fcca9ff 1887
82beb536 1888 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1889
1890 /* sysenter isn't supported in compatibility mode on AMD,
1891 * syscall isn't supported in compatibility mode on Intel.
1892 * Normally we advertise the actual CPU vendor, but you can
1893 * override this using the 'vendor' property if you want to use
1894 * KVM's sysenter/syscall emulation in compatibility mode and
1895 * when doing cross vendor migration
1896 */
74f54bc4 1897 vendor = def->vendor;
7c08db30
EH		 1898 if (kvm_enabled()) {
1899 uint32_t ebx = 0, ecx = 0, edx = 0;
1900 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1901 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1902 vendor = host_vendor;
1903 }
1904
1905 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1906
c6dc6f63
AP		 1907}
1908
62fc403f
IM		 1909X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1910 Error **errp)
5c3c6a68 1911{
2d64255b 1912 X86CPU *cpu = NULL;
d940ee9b 1913 X86CPUClass *xcc;
500050d1 1914 ObjectClass *oc;
2d64255b
AF		 1915 gchar **model_pieces;
1916 char *name, *features;
5c3c6a68
AF		 1917 Error *error = NULL;
1918
2d64255b
AF		 1919 model_pieces = g_strsplit(cpu_model, ",", 2);
1920 if (!model_pieces[0]) {
1921 error_setg(&error, "Invalid/empty CPU model name");
1922 goto out;
1923 }
1924 name = model_pieces[0];
1925 features = model_pieces[1];
1926
500050d1
AF		 1927 oc = x86_cpu_class_by_name(name);
1928 if (oc == NULL) {
1929 error_setg(&error, "Unable to find CPU definition: %s", name);
1930 goto out;
1931 }
d940ee9b
EH		 1932 xcc = X86_CPU_CLASS(oc);
1933
1934 if (xcc->kvm_required && !kvm_enabled()) {
1935 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 1936 goto out;
1937 }
1938
d940ee9b
EH		 1939 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1940
62fc403f
IM		 1941#ifndef CONFIG_USER_ONLY
1942 if (icc_bridge == NULL) {
1943 error_setg(&error, "Invalid icc-bridge value");
1944 goto out;
1945 }
1946 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1947 object_unref(OBJECT(cpu));
1948#endif
5c3c6a68 1949
94a444b2 1950 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 1951 if (error) {
1952 goto out;
5c3c6a68
AF		 1953 }
1954
7f833247 1955out:
cd7b87ff
AF		 1956 if (error != NULL) {
1957 error_propagate(errp, error);
500050d1
AF		 1958 if (cpu) {
1959 object_unref(OBJECT(cpu));
1960 cpu = NULL;
1961 }
cd7b87ff 1962 }
7f833247
IM		 1963 g_strfreev(model_pieces);
1964 return cpu;
1965}
1966
1967X86CPU *cpu_x86_init(const char *cpu_model)
1968{
1969 Error *error = NULL;
1970 X86CPU *cpu;
1971
62fc403f 1972 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1973 if (error) {
2d64255b
AF		 1974 goto out;
1975 }
1976
7f833247
IM		 1977 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1978
2d64255b 1979out:
2d64255b 1980 if (error) {
4a44d85e 1981 error_report("%s", error_get_pretty(error));
5c3c6a68 1982 error_free(error);
2d64255b
AF		 1983 if (cpu != NULL) {
1984 object_unref(OBJECT(cpu));
1985 cpu = NULL;
1986 }
5c3c6a68
AF		 1987 }
1988 return cpu;
1989}
1990
d940ee9b
EH		 1991static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
1992{
1993 X86CPUDefinition *cpudef = data;
1994 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1995
1996 xcc->cpu_def = cpudef;
1997}
1998
1999static void x86_register_cpudef_type(X86CPUDefinition *def)
2000{
2001 char *typename = x86_cpu_type_name(def->name);
2002 TypeInfo ti = {
2003 .name = typename,
2004 .parent = TYPE_X86_CPU,
2005 .class_init = x86_cpu_cpudef_class_init,
2006 .class_data = def,
2007 };
2008
2009 type_register(&ti);
2010 g_free(typename);
2011}
2012
c6dc6f63 2013#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2014
0e26b7b8
BS		 2015void cpu_clear_apic_feature(CPUX86State *env)
2016{
0514ef2f 2017 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2018}
2019
c6dc6f63
AP		 2020#endif /* !CONFIG_USER_ONLY */
2021
c04321b3 2022/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2023 */
2024void x86_cpudef_setup(void)
2025{
93bfef4c
CV		 2026 int i, j;
2027 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2028
2029 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2030 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2031
2032 /* Look for specific "cpudef" models that */
09faecf2 2033 /* have the QEMU version in .model_id */
93bfef4c 2034 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2035 if (strcmp(model_with_versions[j], def->name) == 0) {
2036 pstrcpy(def->model_id, sizeof(def->model_id),
2037 "QEMU Virtual CPU version ");
2038 pstrcat(def->model_id, sizeof(def->model_id),
2039 qemu_get_version());
93bfef4c
CV		 2040 break;
2041 }
2042 }
c6dc6f63 2043 }
c6dc6f63
AP		 2044}
2045
c6dc6f63
AP		 2046static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2047 uint32_t *ecx, uint32_t *edx)
2048{
2049 *ebx = env->cpuid_vendor1;
2050 *edx = env->cpuid_vendor2;
2051 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2052}
2053
2054void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2055 uint32_t *eax, uint32_t *ebx,
2056 uint32_t *ecx, uint32_t *edx)
2057{
a60f24b5
AF		 2058 X86CPU *cpu = x86_env_get_cpu(env);
2059 CPUState *cs = CPU(cpu);
2060
c6dc6f63
AP		 2061 /* test if maximum index reached */
2062 if (index & 0x80000000) {
b3baa152
BW		 2063 if (index > env->cpuid_xlevel) {
2064 if (env->cpuid_xlevel2 > 0) {
2065 /* Handle the Centaur's CPUID instruction. */
2066 if (index > env->cpuid_xlevel2) {
2067 index = env->cpuid_xlevel2;
2068 } else if (index < 0xC0000000) {
2069 index = env->cpuid_xlevel;
2070 }
2071 } else {
57f26ae7
EH		 2072 /* Intel documentation states that invalid EAX input will
2073 * return the same information as EAX=cpuid_level
2074 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2075 */
2076 index = env->cpuid_level;
b3baa152
BW		 2077 }
2078 }
c6dc6f63
AP		 2079 } else {
2080 if (index > env->cpuid_level)
2081 index = env->cpuid_level;
2082 }
2083
2084 switch(index) {
2085 case 0:
2086 *eax = env->cpuid_level;
2087 get_cpuid_vendor(env, ebx, ecx, edx);
2088 break;
2089 case 1:
2090 *eax = env->cpuid_version;
2091 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2092 *ecx = env->features[FEAT_1_ECX];
2093 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2094 if (cs->nr_cores * cs->nr_threads > 1) {
2095 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2096 *edx |= 1 << 28; /* HTT bit */
2097 }
2098 break;
2099 case 2:
2100 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2101 if (cpu->cache_info_passthrough) {
2102 host_cpuid(index, 0, eax, ebx, ecx, edx);
2103 break;
2104 }
5e891bf8 2105 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2106 *ebx = 0;
2107 *ecx = 0;
5e891bf8
EH		 2108 *edx = (L1D_DESCRIPTOR << 16) | \
2109 (L1I_DESCRIPTOR << 8) | \
2110 (L2_DESCRIPTOR);
c6dc6f63
AP		 2111 break;
2112 case 4:
2113 /* cache info: needed for Core compatibility */
787aaf57
BC		 2114 if (cpu->cache_info_passthrough) {
2115 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2116 *eax &= ~0xFC000000;
c6dc6f63 2117 } else {
2f7a21c4 2118 *eax = 0;
76c2975a 2119 switch (count) {
c6dc6f63 2120 case 0: /* L1 dcache info */
5e891bf8
EH		 2121 *eax |= CPUID_4_TYPE_DCACHE | \
2122 CPUID_4_LEVEL(1) | \
2123 CPUID_4_SELF_INIT_LEVEL;
2124 *ebx = (L1D_LINE_SIZE - 1) | \
2125 ((L1D_PARTITIONS - 1) << 12) | \
2126 ((L1D_ASSOCIATIVITY - 1) << 22);
2127 *ecx = L1D_SETS - 1;
2128 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2129 break;
2130 case 1: /* L1 icache info */
5e891bf8
EH		 2131 *eax |= CPUID_4_TYPE_ICACHE | \
2132 CPUID_4_LEVEL(1) | \
2133 CPUID_4_SELF_INIT_LEVEL;
2134 *ebx = (L1I_LINE_SIZE - 1) | \
2135 ((L1I_PARTITIONS - 1) << 12) | \
2136 ((L1I_ASSOCIATIVITY - 1) << 22);
2137 *ecx = L1I_SETS - 1;
2138 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2139 break;
2140 case 2: /* L2 cache info */
5e891bf8
EH		 2141 *eax |= CPUID_4_TYPE_UNIFIED | \
2142 CPUID_4_LEVEL(2) | \
2143 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2144 if (cs->nr_threads > 1) {
2145 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2146 }
5e891bf8
EH		 2147 *ebx = (L2_LINE_SIZE - 1) | \
2148 ((L2_PARTITIONS - 1) << 12) | \
2149 ((L2_ASSOCIATIVITY - 1) << 22);
2150 *ecx = L2_SETS - 1;
2151 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2152 break;
2153 default: /* end of info */
2154 *eax = 0;
2155 *ebx = 0;
2156 *ecx = 0;
2157 *edx = 0;
2158 break;
76c2975a
PB		 2159 }
2160 }
2161
2162 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2163 if ((*eax & 31) && cs->nr_cores > 1) {
2164 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2165 }
2166 break;
2167 case 5:
2168 /* mwait info: needed for Core compatibility */
2169 *eax = 0; /* Smallest monitor-line size in bytes */
2170 *ebx = 0; /* Largest monitor-line size in bytes */
2171 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2172 *edx = 0;
2173 break;
2174 case 6:
2175 /* Thermal and Power Leaf */
2176 *eax = 0;
2177 *ebx = 0;
2178 *ecx = 0;
2179 *edx = 0;
2180 break;
f7911686 2181 case 7:
13526728
EH		 2182 /* Structured Extended Feature Flags Enumeration Leaf */
2183 if (count == 0) {
2184 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2185 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2186 *ecx = 0; /* Reserved */
2187 *edx = 0; /* Reserved */
f7911686
YW		 2188 } else {
2189 *eax = 0;
2190 *ebx = 0;
2191 *ecx = 0;
2192 *edx = 0;
2193 }
2194 break;
c6dc6f63
AP		 2195 case 9:
2196 /* Direct Cache Access Information Leaf */
2197 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2198 *ebx = 0;
2199 *ecx = 0;
2200 *edx = 0;
2201 break;
2202 case 0xA:
2203 /* Architectural Performance Monitoring Leaf */
9337e3b6 2204 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2205 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2206
2207 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2208 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2209 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2210 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2211 } else {
2212 *eax = 0;
2213 *ebx = 0;
2214 *ecx = 0;
2215 *edx = 0;
2216 }
c6dc6f63 2217 break;
2560f19f
PB		 2218 case 0xD: {
2219 KVMState *s = cs->kvm_state;
2220 uint64_t kvm_mask;
2221 int i;
2222
51e49430 2223 /* Processor Extended State */
2560f19f
PB		 2224 *eax = 0;
2225 *ebx = 0;
2226 *ecx = 0;
2227 *edx = 0;
2228 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2229 break;
2230 }
2560f19f
PB		 2231 kvm_mask =
2232 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2233 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2234
2560f19f
PB		 2235 if (count == 0) {
2236 *ecx = 0x240;
2237 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2238 const ExtSaveArea *esa = &ext_save_areas[i];
2239 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2240 (kvm_mask & (1 << i)) != 0) {
2241 if (i < 32) {
2242 *eax |= 1 << i;
2243 } else {
2244 *edx |= 1 << (i - 32);
2245 }
2246 *ecx = MAX(*ecx, esa->offset + esa->size);
2247 }
2248 }
2249 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2250 *ebx = *ecx;
2251 } else if (count == 1) {
2252 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2253 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2254 const ExtSaveArea *esa = &ext_save_areas[count];
2255 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2256 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2257 *eax = esa->size;
2258 *ebx = esa->offset;
2560f19f 2259 }
51e49430
SY		 2260 }
2261 break;
2560f19f 2262 }
c6dc6f63
AP		 2263 case 0x80000000:
2264 *eax = env->cpuid_xlevel;
2265 *ebx = env->cpuid_vendor1;
2266 *edx = env->cpuid_vendor2;
2267 *ecx = env->cpuid_vendor3;
2268 break;
2269 case 0x80000001:
2270 *eax = env->cpuid_version;
2271 *ebx = 0;
0514ef2f
EH		 2272 *ecx = env->features[FEAT_8000_0001_ECX];
2273 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2274
2275 /* The Linux kernel checks for the CMPLegacy bit and
2276 * discards multiple thread information if it is set.
2277 * So dont set it here for Intel to make Linux guests happy.
2278 */
ce3960eb 2279 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2280 uint32_t tebx, tecx, tedx;
2281 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2282 if (tebx != CPUID_VENDOR_INTEL_1 ||
2283 tedx != CPUID_VENDOR_INTEL_2 ||
2284 tecx != CPUID_VENDOR_INTEL_3) {
2285 *ecx |= 1 << 1; /* CmpLegacy bit */
2286 }
2287 }
c6dc6f63
AP		 2288 break;
2289 case 0x80000002:
2290 case 0x80000003:
2291 case 0x80000004:
2292 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2293 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2294 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2295 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2296 break;
2297 case 0x80000005:
2298 /* cache info (L1 cache) */
787aaf57
BC		 2299 if (cpu->cache_info_passthrough) {
2300 host_cpuid(index, 0, eax, ebx, ecx, edx);
2301 break;
2302 }
5e891bf8
EH		 2303 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2304 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2305 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2306 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2307 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2308 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2309 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2310 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2311 break;
2312 case 0x80000006:
2313 /* cache info (L2 cache) */
787aaf57
BC		 2314 if (cpu->cache_info_passthrough) {
2315 host_cpuid(index, 0, eax, ebx, ecx, edx);
2316 break;
2317 }
5e891bf8
EH		 2318 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2319 (L2_DTLB_2M_ENTRIES << 16) | \
2320 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2321 (L2_ITLB_2M_ENTRIES);
2322 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2323 (L2_DTLB_4K_ENTRIES << 16) | \
2324 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2325 (L2_ITLB_4K_ENTRIES);
2326 *ecx = (L2_SIZE_KB_AMD << 16) | \
2327 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2328 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2329 *edx = ((L3_SIZE_KB/512) << 18) | \
2330 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2331 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2332 break;
2333 case 0x80000008:
2334 /* virtual & phys address size in low 2 bytes. */
2335/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2336 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2337 /* 64 bit processor */
2338/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2339 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2340 } else {
0514ef2f 2341 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2342 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2343 } else {
c6dc6f63 2344 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2345 }
c6dc6f63
AP		 2346 }
2347 *ebx = 0;
2348 *ecx = 0;
2349 *edx = 0;
ce3960eb
AF		 2350 if (cs->nr_cores * cs->nr_threads > 1) {
2351 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2352 }
2353 break;
2354 case 0x8000000A:
0514ef2f 2355 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2356 *eax = 0x00000001; /* SVM Revision */
2357 *ebx = 0x00000010; /* nr of ASIDs */
2358 *ecx = 0;
0514ef2f 2359 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2360 } else {
2361 *eax = 0;
2362 *ebx = 0;
2363 *ecx = 0;
2364 *edx = 0;
2365 }
c6dc6f63 2366 break;
b3baa152
BW		 2367 case 0xC0000000:
2368 *eax = env->cpuid_xlevel2;
2369 *ebx = 0;
2370 *ecx = 0;
2371 *edx = 0;
2372 break;
2373 case 0xC0000001:
2374 /* Support for VIA CPU's CPUID instruction */
2375 *eax = env->cpuid_version;
2376 *ebx = 0;
2377 *ecx = 0;
0514ef2f 2378 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2379 break;
2380 case 0xC0000002:
2381 case 0xC0000003:
2382 case 0xC0000004:
2383 /* Reserved for the future, and now filled with zero */
2384 *eax = 0;
2385 *ebx = 0;
2386 *ecx = 0;
2387 *edx = 0;
2388 break;
c6dc6f63
AP		 2389 default:
2390 /* reserved values: zero */
2391 *eax = 0;
2392 *ebx = 0;
2393 *ecx = 0;
2394 *edx = 0;
2395 break;
2396 }
2397}
5fd2087a
AF		 2398
2399/* CPUClass::reset() */
2400static void x86_cpu_reset(CPUState *s)
2401{
2402 X86CPU *cpu = X86_CPU(s);
2403 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2404 CPUX86State *env = &cpu->env;
c1958aea
AF		 2405 int i;
2406
5fd2087a
AF		 2407 xcc->parent_reset(s);
2408
43175fa9 2409 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2410
00c8cb0a 2411 tlb_flush(s, 1);
c1958aea
AF		 2412
2413 env->old_exception = -1;
2414
2415 /* init to reset state */
2416
2417#ifdef CONFIG_SOFTMMU
2418 env->hflags |= HF_SOFTMMU_MASK;
2419#endif
2420 env->hflags2 |= HF2_GIF_MASK;
2421
2422 cpu_x86_update_cr0(env, 0x60000010);
2423 env->a20_mask = ~0x0;
2424 env->smbase = 0x30000;
2425
2426 env->idt.limit = 0xffff;
2427 env->gdt.limit = 0xffff;
2428 env->ldt.limit = 0xffff;
2429 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2430 env->tr.limit = 0xffff;
2431 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2432
2433 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2434 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2435 DESC_R_MASK | DESC_A_MASK);
2436 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2437 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2438 DESC_A_MASK);
2439 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2440 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2441 DESC_A_MASK);
2442 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2443 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2444 DESC_A_MASK);
2445 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2446 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2447 DESC_A_MASK);
2448 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2449 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450 DESC_A_MASK);
2451
2452 env->eip = 0xfff0;
2453 env->regs[R_EDX] = env->cpuid_version;
2454
2455 env->eflags = 0x2;
2456
2457 /* FPU init */
2458 for (i = 0; i < 8; i++) {
2459 env->fptags[i] = 1;
2460 }
2461 env->fpuc = 0x37f;
2462
2463 env->mxcsr = 0x1f80;
c74f41bb 2464 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2465
2466 env->pat = 0x0007040600070406ULL;
2467 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2468
2469 memset(env->dr, 0, sizeof(env->dr));
2470 env->dr[6] = DR6_FIXED_1;
2471 env->dr[7] = DR7_FIXED_1;
b3310ab3 2472 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2473 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2474
05e7e819 2475 env->xcr0 = 1;
0522604b 2476
dd673288
IM		 2477#if !defined(CONFIG_USER_ONLY)
2478 /* We hard-wire the BSP to the first CPU. */
55e5c285 2479 if (s->cpu_index == 0) {
02e51483 2480 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2481 }
2482
259186a7 2483 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2484
2485 if (kvm_enabled()) {
2486 kvm_arch_reset_vcpu(cpu);
2487 }
dd673288 2488#endif
5fd2087a
AF		 2489}
2490
dd673288
IM		 2491#ifndef CONFIG_USER_ONLY
2492bool cpu_is_bsp(X86CPU *cpu)
2493{
02e51483 2494 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2495}
65dee380
IM		 2496
2497/* TODO: remove me, when reset over QOM tree is implemented */
2498static void x86_cpu_machine_reset_cb(void *opaque)
2499{
2500 X86CPU *cpu = opaque;
2501 cpu_reset(CPU(cpu));
2502}
dd673288
IM		 2503#endif
2504
de024815
AF		 2505static void mce_init(X86CPU *cpu)
2506{
2507 CPUX86State *cenv = &cpu->env;
2508 unsigned int bank;
2509
2510 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2511 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2512 (CPUID_MCE | CPUID_MCA)) {
2513 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2514 cenv->mcg_ctl = ~(uint64_t)0;
2515 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2516 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2517 }
2518 }
2519}
2520
bdeec802 2521#ifndef CONFIG_USER_ONLY
d3c64d6a 2522static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2523{
bdeec802 2524 CPUX86State *env = &cpu->env;
53a89e26 2525 DeviceState *dev = DEVICE(cpu);
449994eb 2526 APICCommonState *apic;
bdeec802
IM		 2527 const char *apic_type = "apic";
2528
2529 if (kvm_irqchip_in_kernel()) {
2530 apic_type = "kvm-apic";
2531 } else if (xen_enabled()) {
2532 apic_type = "xen-apic";
2533 }
2534
02e51483
CF		 2535 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2536 if (cpu->apic_state == NULL) {
bdeec802
IM		 2537 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2538 return;
2539 }
2540
2541 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2542 OBJECT(cpu->apic_state), NULL);
2543 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2544 /* TODO: convert to link<> */
02e51483 2545 apic = APIC_COMMON(cpu->apic_state);
60671e58 2546 apic->cpu = cpu;
d3c64d6a
IM		 2547}
2548
2549static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2550{
02e51483 2551 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2552 return;
2553 }
bdeec802 2554
02e51483 2555 if (qdev_init(cpu->apic_state)) {
bdeec802 2556 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2557 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2558 return;
2559 }
bdeec802 2560}
d3c64d6a
IM		 2561#else
2562static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2563{
2564}
bdeec802
IM		 2565#endif
2566
2b6f294c 2567static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2568{
14a10fc3 2569 CPUState *cs = CPU(dev);
2b6f294c
AF		 2570 X86CPU *cpu = X86_CPU(dev);
2571 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2572 CPUX86State *env = &cpu->env;
2b6f294c 2573 Error *local_err = NULL;
b34d12d1 2574
0514ef2f 2575 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2576 env->cpuid_level = 7;
2577 }
7a059953 2578
9b15cd9e
IM		 2579 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2580 * CPUID[1].EDX.
2581 */
2582 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2583 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2584 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2585 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2586 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2587 & CPUID_EXT2_AMD_ALIASES);
2588 }
2589
4586f157 2590 if (!kvm_enabled()) {
0514ef2f
EH		 2591 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2592 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
d0a70f46 2593 env->features[FEAT_7_0_EBX] &= TCG_7_0_EBX_FEATURES;
a42d9938 2594 env->features[FEAT_8000_0001_EDX] &= TCG_EXT2_FEATURES;
0514ef2f
EH		 2595 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2596 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
84a6c6cd
EH		 2597 env->features[FEAT_KVM] &= TCG_KVM_FEATURES;
2598 env->features[FEAT_C000_0001_EDX] &= TCG_EXT4_FEATURES;
4586f157 2599 } else {
27418adf 2600 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2601 error_setg(&local_err,
2602 "Host's CPU doesn't support requested features");
2603 goto out;
5ec01c2e 2604 }
4586f157
IM		 2605 }
2606
65dee380
IM		 2607#ifndef CONFIG_USER_ONLY
2608 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2609
0514ef2f 2610 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2611 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2612 if (local_err != NULL) {
4dc1f449 2613 goto out;
bdeec802
IM		 2614 }
2615 }
65dee380
IM		 2616#endif
2617
7a059953 2618 mce_init(cpu);
14a10fc3 2619 qemu_init_vcpu(cs);
d3c64d6a
IM		 2620
2621 x86_cpu_apic_realize(cpu, &local_err);
2622 if (local_err != NULL) {
2623 goto out;
2624 }
14a10fc3 2625 cpu_reset(cs);
2b6f294c 2626
4dc1f449
IM		 2627 xcc->parent_realize(dev, &local_err);
2628out:
2629 if (local_err != NULL) {
2630 error_propagate(errp, local_err);
2631 return;
2632 }
7a059953
AF		 2633}
2634
8932cfdf
EH		 2635/* Enables contiguous-apic-ID mode, for compatibility */
2636static bool compat_apic_id_mode;
2637
2638void enable_compat_apic_id_mode(void)
2639{
2640 compat_apic_id_mode = true;
2641}
2642
cb41bad3
EH		 2643/* Calculates initial APIC ID for a specific CPU index
2644 *
2645 * Currently we need to be able to calculate the APIC ID from the CPU index
2646 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2647 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2648 * all CPUs up to max_cpus.
2649 */
2650uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2651{
8932cfdf
EH		 2652 uint32_t correct_id;
2653 static bool warned;
2654
2655 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2656 if (compat_apic_id_mode) {
2657 if (cpu_index != correct_id && !warned) {
2658 error_report("APIC IDs set in compatibility mode, "
2659 "CPU topology won't match the configuration");
2660 warned = true;
2661 }
2662 return cpu_index;
2663 } else {
2664 return correct_id;
2665 }
cb41bad3
EH		 2666}
2667
de024815
AF		 2668static void x86_cpu_initfn(Object *obj)
2669{
55e5c285 2670 CPUState *cs = CPU(obj);
de024815 2671 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2672 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2673 CPUX86State *env = &cpu->env;
d65e9815 2674 static int inited;
de024815 2675
c05efcb1 2676 cs->env_ptr = env;
de024815 2677 cpu_exec_init(env);
71ad61d3
AF		 2678
2679 object_property_add(obj, "family", "int",
95b8519d 2680 x86_cpuid_version_get_family,
71ad61d3 2681 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2682 object_property_add(obj, "model", "int",
67e30c83 2683 x86_cpuid_version_get_model,
c5291a4f 2684 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2685 object_property_add(obj, "stepping", "int",
35112e41 2686 x86_cpuid_version_get_stepping,
036e2222 2687 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2688 object_property_add(obj, "level", "int",
2689 x86_cpuid_get_level,
2690 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2691 object_property_add(obj, "xlevel", "int",
2692 x86_cpuid_get_xlevel,
2693 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2694 object_property_add_str(obj, "vendor",
2695 x86_cpuid_get_vendor,
2696 x86_cpuid_set_vendor, NULL);
938d4c25 2697 object_property_add_str(obj, "model-id",
63e886eb 2698 x86_cpuid_get_model_id,
938d4c25 2699 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2700 object_property_add(obj, "tsc-frequency", "int",
2701 x86_cpuid_get_tsc_freq,
2702 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2703 object_property_add(obj, "apic-id", "int",
2704 x86_cpuid_get_apic_id,
2705 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2706 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2707 x86_cpu_get_feature_words,
7e5292b5
EH		 2708 NULL, NULL, (void *)env->features, NULL);
2709 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2710 x86_cpu_get_feature_words,
2711 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2712
92067bf4 2713 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2714 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2715
d940ee9b
EH		 2716 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2717
d65e9815
IM		 2718 /* init various static tables used in TCG mode */
2719 if (tcg_enabled() && !inited) {
2720 inited = 1;
2721 optimize_flags_init();
2722#ifndef CONFIG_USER_ONLY
2723 cpu_set_debug_excp_handler(breakpoint_handler);
2724#endif
2725 }
de024815
AF		 2726}
2727
997395d3
IM		 2728static int64_t x86_cpu_get_arch_id(CPUState *cs)
2729{
2730 X86CPU *cpu = X86_CPU(cs);
2731 CPUX86State *env = &cpu->env;
2732
2733 return env->cpuid_apic_id;
2734}
2735
444d5590
AF		 2736static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2737{
2738 X86CPU *cpu = X86_CPU(cs);
2739
2740 return cpu->env.cr[0] & CR0_PG_MASK;
2741}
2742
f45748f1
AF		 2743static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2744{
2745 X86CPU *cpu = X86_CPU(cs);
2746
2747 cpu->env.eip = value;
2748}
2749
bdf7ae5b
AF		 2750static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2751{
2752 X86CPU *cpu = X86_CPU(cs);
2753
2754 cpu->env.eip = tb->pc - tb->cs_base;
2755}
2756
8c2e1b00
AF		 2757static bool x86_cpu_has_work(CPUState *cs)
2758{
2759 X86CPU *cpu = X86_CPU(cs);
2760 CPUX86State *env = &cpu->env;
2761
2762 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2763 CPU_INTERRUPT_POLL)) &&
2764 (env->eflags & IF_MASK)) ||
2765 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2766 CPU_INTERRUPT_INIT |
2767 CPU_INTERRUPT_SIPI |
2768 CPU_INTERRUPT_MCE));
2769}
2770
9337e3b6
EH		 2771static Property x86_cpu_properties[] = {
2772 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2773 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2774 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2775 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2776 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2777 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2778 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2779 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2780 DEFINE_PROP_END_OF_LIST()
2781};
2782
5fd2087a
AF		 2783static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2784{
2785 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2786 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2787 DeviceClass *dc = DEVICE_CLASS(oc);
2788
2789 xcc->parent_realize = dc->realize;
2790 dc->realize = x86_cpu_realizefn;
62fc403f 2791 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2792 dc->props = x86_cpu_properties;
5fd2087a
AF		 2793
2794 xcc->parent_reset = cc->reset;
2795 cc->reset = x86_cpu_reset;
91b1df8c 2796 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2797
500050d1 2798 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2799 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2800 cc->has_work = x86_cpu_has_work;
97a8ea5a 2801 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2802 cc->dump_state = x86_cpu_dump_state;
f45748f1 2803 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2804 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2805 cc->gdb_read_register = x86_cpu_gdb_read_register;
2806 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2807 cc->get_arch_id = x86_cpu_get_arch_id;
2808 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2809#ifdef CONFIG_USER_ONLY
2810 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2811#else
a23bbfda 2812 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2813 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2814 cc->write_elf64_note = x86_cpu_write_elf64_note;
2815 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2816 cc->write_elf32_note = x86_cpu_write_elf32_note;
2817 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2818 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2819#endif
a0e372f0 2820 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2821}
2822
2823static const TypeInfo x86_cpu_type_info = {
2824 .name = TYPE_X86_CPU,
2825 .parent = TYPE_CPU,
2826 .instance_size = sizeof(X86CPU),
de024815 2827 .instance_init = x86_cpu_initfn,
d940ee9b 2828 .abstract = true,
5fd2087a
AF		 2829 .class_size = sizeof(X86CPUClass),
2830 .class_init = x86_cpu_common_class_init,
2831};
2832
2833static void x86_cpu_register_types(void)
2834{
d940ee9b
EH		 2835 int i;
2836
5fd2087a 2837 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2838 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2839 x86_register_cpudef_type(&builtin_x86_defs[i]);
2840 }
2841#ifdef CONFIG_KVM
2842 type_register_static(&host_x86_cpu_type_info);
2843#endif
5fd2087a
AF		 2844}
2845
2846type_init(x86_cpu_register_types)
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