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Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
b60503ba | 16 | #include <linux/blkdev.h> |
a4aea562 | 17 | #include <linux/blk-mq.h> |
dca51e78 | 18 | #include <linux/blk-mq-pci.h> |
ff5350a8 | 19 | #include <linux/dmi.h> |
b60503ba MW |
20 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
b60503ba MW |
23 | #include <linux/mm.h> |
24 | #include <linux/module.h> | |
77bf25ea | 25 | #include <linux/mutex.h> |
d0877473 | 26 | #include <linux/once.h> |
b60503ba | 27 | #include <linux/pci.h> |
e1e5e564 | 28 | #include <linux/t10-pi.h> |
b60503ba | 29 | #include <linux/types.h> |
2f8e2c87 | 30 | #include <linux/io-64-nonatomic-lo-hi.h> |
a98e58e5 | 31 | #include <linux/sed-opal.h> |
797a796a | 32 | |
f11bb3e2 CH |
33 | #include "nvme.h" |
34 | ||
b60503ba MW |
35 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
36 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 37 | |
a7a7cbe3 | 38 | #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) |
9d43cf64 | 39 | |
58ffacb5 MW |
40 | static int use_threaded_interrupts; |
41 | module_param(use_threaded_interrupts, int, 0); | |
42 | ||
8ffaadf7 JD |
43 | static bool use_cmb_sqes = true; |
44 | module_param(use_cmb_sqes, bool, 0644); | |
45 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
46 | ||
87ad72a5 CH |
47 | static unsigned int max_host_mem_size_mb = 128; |
48 | module_param(max_host_mem_size_mb, uint, 0444); | |
49 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
50 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 51 | |
a7a7cbe3 CK |
52 | static unsigned int sgl_threshold = SZ_32K; |
53 | module_param(sgl_threshold, uint, 0644); | |
54 | MODULE_PARM_DESC(sgl_threshold, | |
55 | "Use SGLs when average request segment size is larger or equal to " | |
56 | "this size. Use 0 to disable SGLs."); | |
57 | ||
b27c1e68 | 58 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
59 | static const struct kernel_param_ops io_queue_depth_ops = { | |
60 | .set = io_queue_depth_set, | |
61 | .get = param_get_int, | |
62 | }; | |
63 | ||
64 | static int io_queue_depth = 1024; | |
65 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); | |
66 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); | |
67 | ||
1c63dc66 CH |
68 | struct nvme_dev; |
69 | struct nvme_queue; | |
b3fffdef | 70 | |
a0fa9647 | 71 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 72 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 73 | |
1c63dc66 CH |
74 | /* |
75 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
76 | */ | |
77 | struct nvme_dev { | |
1c63dc66 CH |
78 | struct nvme_queue **queues; |
79 | struct blk_mq_tag_set tagset; | |
80 | struct blk_mq_tag_set admin_tagset; | |
81 | u32 __iomem *dbs; | |
82 | struct device *dev; | |
83 | struct dma_pool *prp_page_pool; | |
84 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
85 | unsigned online_queues; |
86 | unsigned max_qid; | |
87 | int q_depth; | |
88 | u32 db_stride; | |
1c63dc66 | 89 | void __iomem *bar; |
97f6ef64 | 90 | unsigned long bar_mapped_size; |
5c8809e6 | 91 | struct work_struct remove_work; |
77bf25ea | 92 | struct mutex shutdown_lock; |
1c63dc66 | 93 | bool subsystem; |
1c63dc66 | 94 | void __iomem *cmb; |
8969f1f8 | 95 | pci_bus_addr_t cmb_bus_addr; |
1c63dc66 CH |
96 | u64 cmb_size; |
97 | u32 cmbsz; | |
202021c1 | 98 | u32 cmbloc; |
1c63dc66 | 99 | struct nvme_ctrl ctrl; |
db3cbfff | 100 | struct completion ioq_wait; |
87ad72a5 CH |
101 | |
102 | /* shadow doorbell buffer support: */ | |
f9f38e33 HK |
103 | u32 *dbbuf_dbs; |
104 | dma_addr_t dbbuf_dbs_dma_addr; | |
105 | u32 *dbbuf_eis; | |
106 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
107 | |
108 | /* host memory buffer support: */ | |
109 | u64 host_mem_size; | |
110 | u32 nr_host_mem_descs; | |
4033f35d | 111 | dma_addr_t host_mem_descs_dma; |
87ad72a5 CH |
112 | struct nvme_host_mem_buf_desc *host_mem_descs; |
113 | void **host_mem_desc_bufs; | |
4d115420 | 114 | }; |
1fa6aead | 115 | |
b27c1e68 | 116 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
117 | { | |
118 | int n = 0, ret; | |
119 | ||
120 | ret = kstrtoint(val, 10, &n); | |
121 | if (ret != 0 || n < 2) | |
122 | return -EINVAL; | |
123 | ||
124 | return param_set_int(val, kp); | |
125 | } | |
126 | ||
f9f38e33 HK |
127 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
128 | { | |
129 | return qid * 2 * stride; | |
130 | } | |
131 | ||
132 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
133 | { | |
134 | return (qid * 2 + 1) * stride; | |
135 | } | |
136 | ||
1c63dc66 CH |
137 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
138 | { | |
139 | return container_of(ctrl, struct nvme_dev, ctrl); | |
140 | } | |
141 | ||
b60503ba MW |
142 | /* |
143 | * An NVM Express queue. Each device has at least two (one for admin | |
144 | * commands and one for I/O commands). | |
145 | */ | |
146 | struct nvme_queue { | |
147 | struct device *q_dmadev; | |
091b6092 | 148 | struct nvme_dev *dev; |
b60503ba MW |
149 | spinlock_t q_lock; |
150 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 151 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 152 | volatile struct nvme_completion *cqes; |
42483228 | 153 | struct blk_mq_tags **tags; |
b60503ba MW |
154 | dma_addr_t sq_dma_addr; |
155 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
156 | u32 __iomem *q_db; |
157 | u16 q_depth; | |
6222d172 | 158 | s16 cq_vector; |
b60503ba MW |
159 | u16 sq_tail; |
160 | u16 cq_head; | |
c30341dc | 161 | u16 qid; |
e9539f47 MW |
162 | u8 cq_phase; |
163 | u8 cqe_seen; | |
f9f38e33 HK |
164 | u32 *dbbuf_sq_db; |
165 | u32 *dbbuf_cq_db; | |
166 | u32 *dbbuf_sq_ei; | |
167 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
168 | }; |
169 | ||
71bd150c CH |
170 | /* |
171 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
172 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 173 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
174 | * allocated to store the PRP list. |
175 | */ | |
176 | struct nvme_iod { | |
d49187e9 | 177 | struct nvme_request req; |
f4800d6d | 178 | struct nvme_queue *nvmeq; |
a7a7cbe3 | 179 | bool use_sgl; |
f4800d6d | 180 | int aborted; |
71bd150c | 181 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
182 | int nents; /* Used in scatterlist */ |
183 | int length; /* Of data, in bytes */ | |
184 | dma_addr_t first_dma; | |
bf684057 | 185 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
186 | struct scatterlist *sg; |
187 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
188 | }; |
189 | ||
190 | /* | |
191 | * Check we didin't inadvertently grow the command struct | |
192 | */ | |
193 | static inline void _nvme_check_size(void) | |
194 | { | |
195 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
196 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
197 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
198 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
199 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 200 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 201 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba | 202 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
0add5e8e JT |
203 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); |
204 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); | |
b60503ba | 205 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); |
6ecec745 | 206 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
207 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
208 | } | |
209 | ||
210 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
211 | { | |
212 | return ((num_possible_cpus() + 1) * 8 * stride); | |
213 | } | |
214 | ||
215 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
216 | { | |
217 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
218 | ||
219 | if (dev->dbbuf_dbs) | |
220 | return 0; | |
221 | ||
222 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
223 | &dev->dbbuf_dbs_dma_addr, | |
224 | GFP_KERNEL); | |
225 | if (!dev->dbbuf_dbs) | |
226 | return -ENOMEM; | |
227 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
228 | &dev->dbbuf_eis_dma_addr, | |
229 | GFP_KERNEL); | |
230 | if (!dev->dbbuf_eis) { | |
231 | dma_free_coherent(dev->dev, mem_size, | |
232 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
233 | dev->dbbuf_dbs = NULL; | |
234 | return -ENOMEM; | |
235 | } | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
240 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
241 | { | |
242 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
243 | ||
244 | if (dev->dbbuf_dbs) { | |
245 | dma_free_coherent(dev->dev, mem_size, | |
246 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
247 | dev->dbbuf_dbs = NULL; | |
248 | } | |
249 | if (dev->dbbuf_eis) { | |
250 | dma_free_coherent(dev->dev, mem_size, | |
251 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
252 | dev->dbbuf_eis = NULL; | |
253 | } | |
254 | } | |
255 | ||
256 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
257 | struct nvme_queue *nvmeq, int qid) | |
258 | { | |
259 | if (!dev->dbbuf_dbs || !qid) | |
260 | return; | |
261 | ||
262 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
263 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
264 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
265 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
266 | } | |
267 | ||
268 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
269 | { | |
270 | struct nvme_command c; | |
271 | ||
272 | if (!dev->dbbuf_dbs) | |
273 | return; | |
274 | ||
275 | memset(&c, 0, sizeof(c)); | |
276 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
277 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
278 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
279 | ||
280 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 281 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
282 | /* Free memory and continue on */ |
283 | nvme_dbbuf_dma_free(dev); | |
284 | } | |
285 | } | |
286 | ||
287 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
288 | { | |
289 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
290 | } | |
291 | ||
292 | /* Update dbbuf and return true if an MMIO is required */ | |
293 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
294 | volatile u32 *dbbuf_ei) | |
295 | { | |
296 | if (dbbuf_db) { | |
297 | u16 old_value; | |
298 | ||
299 | /* | |
300 | * Ensure that the queue is written before updating | |
301 | * the doorbell in memory | |
302 | */ | |
303 | wmb(); | |
304 | ||
305 | old_value = *dbbuf_db; | |
306 | *dbbuf_db = value; | |
307 | ||
3041e55f MW |
308 | /* |
309 | * Ensure that the doorbell is updated before reading the event | |
310 | * index from memory. The controller needs to provide similar | |
311 | * ordering to ensure the envent index is updated before reading | |
312 | * the doorbell. | |
313 | */ | |
314 | mb(); | |
315 | ||
f9f38e33 HK |
316 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) |
317 | return false; | |
318 | } | |
319 | ||
320 | return true; | |
b60503ba MW |
321 | } |
322 | ||
ac3dd5bd JA |
323 | /* |
324 | * Max size of iod being embedded in the request payload | |
325 | */ | |
326 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 327 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
328 | |
329 | /* | |
330 | * Will slightly overestimate the number of pages needed. This is OK | |
331 | * as it only leads to a small amount of wasted memory for the lifetime of | |
332 | * the I/O. | |
333 | */ | |
334 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
335 | { | |
5fd4ce1b CH |
336 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
337 | dev->ctrl.page_size); | |
ac3dd5bd JA |
338 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
339 | } | |
340 | ||
a7a7cbe3 CK |
341 | /* |
342 | * Calculates the number of pages needed for the SGL segments. For example a 4k | |
343 | * page can accommodate 256 SGL descriptors. | |
344 | */ | |
345 | static int nvme_pci_npages_sgl(unsigned int num_seg) | |
ac3dd5bd | 346 | { |
a7a7cbe3 | 347 | return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); |
f4800d6d | 348 | } |
ac3dd5bd | 349 | |
a7a7cbe3 CK |
350 | static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, |
351 | unsigned int size, unsigned int nseg, bool use_sgl) | |
f4800d6d | 352 | { |
a7a7cbe3 CK |
353 | size_t alloc_size; |
354 | ||
355 | if (use_sgl) | |
356 | alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); | |
357 | else | |
358 | alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); | |
359 | ||
360 | return alloc_size + sizeof(struct scatterlist) * nseg; | |
f4800d6d | 361 | } |
ac3dd5bd | 362 | |
a7a7cbe3 | 363 | static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) |
f4800d6d | 364 | { |
a7a7cbe3 CK |
365 | unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, |
366 | NVME_INT_BYTES(dev), NVME_INT_PAGES, | |
367 | use_sgl); | |
368 | ||
369 | return sizeof(struct nvme_iod) + alloc_size; | |
ac3dd5bd JA |
370 | } |
371 | ||
a4aea562 MB |
372 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
373 | unsigned int hctx_idx) | |
e85248e5 | 374 | { |
a4aea562 MB |
375 | struct nvme_dev *dev = data; |
376 | struct nvme_queue *nvmeq = dev->queues[0]; | |
377 | ||
42483228 KB |
378 | WARN_ON(hctx_idx != 0); |
379 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
380 | WARN_ON(nvmeq->tags); | |
381 | ||
a4aea562 | 382 | hctx->driver_data = nvmeq; |
42483228 | 383 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 384 | return 0; |
e85248e5 MW |
385 | } |
386 | ||
4af0e21c KB |
387 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
388 | { | |
389 | struct nvme_queue *nvmeq = hctx->driver_data; | |
390 | ||
391 | nvmeq->tags = NULL; | |
392 | } | |
393 | ||
a4aea562 MB |
394 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
395 | unsigned int hctx_idx) | |
b60503ba | 396 | { |
a4aea562 | 397 | struct nvme_dev *dev = data; |
42483228 | 398 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 399 | |
42483228 KB |
400 | if (!nvmeq->tags) |
401 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 402 | |
42483228 | 403 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
404 | hctx->driver_data = nvmeq; |
405 | return 0; | |
b60503ba MW |
406 | } |
407 | ||
d6296d39 CH |
408 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
409 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 410 | { |
d6296d39 | 411 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 412 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a CH |
413 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
414 | struct nvme_queue *nvmeq = dev->queues[queue_idx]; | |
a4aea562 MB |
415 | |
416 | BUG_ON(!nvmeq); | |
f4800d6d | 417 | iod->nvmeq = nvmeq; |
a4aea562 MB |
418 | return 0; |
419 | } | |
420 | ||
dca51e78 CH |
421 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
422 | { | |
423 | struct nvme_dev *dev = set->driver_data; | |
424 | ||
425 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
426 | } | |
427 | ||
b60503ba | 428 | /** |
adf68f21 | 429 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
430 | * @nvmeq: The queue to use |
431 | * @cmd: The command to send | |
432 | * | |
433 | * Safe to use from interrupt context | |
434 | */ | |
e3f879bf SB |
435 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
436 | struct nvme_command *cmd) | |
b60503ba | 437 | { |
a4aea562 MB |
438 | u16 tail = nvmeq->sq_tail; |
439 | ||
8ffaadf7 JD |
440 | if (nvmeq->sq_cmds_io) |
441 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
442 | else | |
443 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
444 | ||
b60503ba MW |
445 | if (++tail == nvmeq->q_depth) |
446 | tail = 0; | |
f9f38e33 HK |
447 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
448 | nvmeq->dbbuf_sq_ei)) | |
449 | writel(tail, nvmeq->q_db); | |
b60503ba | 450 | nvmeq->sq_tail = tail; |
b60503ba MW |
451 | } |
452 | ||
a7a7cbe3 | 453 | static void **nvme_pci_iod_list(struct request *req) |
b60503ba | 454 | { |
f4800d6d | 455 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a7a7cbe3 | 456 | return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
457 | } |
458 | ||
955b1b5a MI |
459 | static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) |
460 | { | |
461 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
20469a37 | 462 | int nseg = blk_rq_nr_phys_segments(req); |
955b1b5a MI |
463 | unsigned int avg_seg_size; |
464 | ||
20469a37 KB |
465 | if (nseg == 0) |
466 | return false; | |
467 | ||
468 | avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); | |
955b1b5a MI |
469 | |
470 | if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) | |
471 | return false; | |
472 | if (!iod->nvmeq->qid) | |
473 | return false; | |
474 | if (!sgl_threshold || avg_seg_size < sgl_threshold) | |
475 | return false; | |
476 | return true; | |
477 | } | |
478 | ||
fc17b653 | 479 | static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 480 | { |
f4800d6d | 481 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 482 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 483 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 484 | |
955b1b5a MI |
485 | iod->use_sgl = nvme_pci_use_sgls(dev, rq); |
486 | ||
f4800d6d | 487 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
a7a7cbe3 CK |
488 | size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, |
489 | iod->use_sgl); | |
490 | ||
491 | iod->sg = kmalloc(alloc_size, GFP_ATOMIC); | |
f4800d6d | 492 | if (!iod->sg) |
fc17b653 | 493 | return BLK_STS_RESOURCE; |
f4800d6d CH |
494 | } else { |
495 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
496 | } |
497 | ||
f4800d6d CH |
498 | iod->aborted = 0; |
499 | iod->npages = -1; | |
500 | iod->nents = 0; | |
501 | iod->length = size; | |
f80ec966 | 502 | |
fc17b653 | 503 | return BLK_STS_OK; |
ac3dd5bd JA |
504 | } |
505 | ||
f4800d6d | 506 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 507 | { |
f4800d6d | 508 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a7a7cbe3 CK |
509 | const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; |
510 | dma_addr_t dma_addr = iod->first_dma, next_dma_addr; | |
511 | ||
eca18b23 | 512 | int i; |
eca18b23 MW |
513 | |
514 | if (iod->npages == 0) | |
a7a7cbe3 CK |
515 | dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], |
516 | dma_addr); | |
517 | ||
eca18b23 | 518 | for (i = 0; i < iod->npages; i++) { |
a7a7cbe3 CK |
519 | void *addr = nvme_pci_iod_list(req)[i]; |
520 | ||
521 | if (iod->use_sgl) { | |
522 | struct nvme_sgl_desc *sg_list = addr; | |
523 | ||
524 | next_dma_addr = | |
525 | le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); | |
526 | } else { | |
527 | __le64 *prp_list = addr; | |
528 | ||
529 | next_dma_addr = le64_to_cpu(prp_list[last_prp]); | |
530 | } | |
531 | ||
532 | dma_pool_free(dev->prp_page_pool, addr, dma_addr); | |
533 | dma_addr = next_dma_addr; | |
eca18b23 | 534 | } |
ac3dd5bd | 535 | |
f4800d6d CH |
536 | if (iod->sg != iod->inline_sg) |
537 | kfree(iod->sg); | |
b4ff9c8d KB |
538 | } |
539 | ||
52b68d7e | 540 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
541 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
542 | { | |
543 | if (be32_to_cpu(pi->ref_tag) == v) | |
544 | pi->ref_tag = cpu_to_be32(p); | |
545 | } | |
546 | ||
547 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
548 | { | |
549 | if (be32_to_cpu(pi->ref_tag) == p) | |
550 | pi->ref_tag = cpu_to_be32(v); | |
551 | } | |
552 | ||
553 | /** | |
554 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
555 | * | |
556 | * The virtual start sector is the one that was originally submitted by the | |
557 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
558 | * start sector may be different. Remap protection information to match the | |
559 | * physical LBA on writes, and back to the original seed on reads. | |
560 | * | |
561 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
562 | */ | |
563 | static void nvme_dif_remap(struct request *req, | |
564 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
565 | { | |
566 | struct nvme_ns *ns = req->rq_disk->private_data; | |
567 | struct bio_integrity_payload *bip; | |
568 | struct t10_pi_tuple *pi; | |
569 | void *p, *pmap; | |
570 | u32 i, nlb, ts, phys, virt; | |
571 | ||
572 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
573 | return; | |
574 | ||
575 | bip = bio_integrity(req->bio); | |
576 | if (!bip) | |
577 | return; | |
578 | ||
579 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
580 | |
581 | p = pmap; | |
582 | virt = bip_get_seed(bip); | |
583 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
584 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 585 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
586 | |
587 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
588 | pi = (struct t10_pi_tuple *)p; | |
589 | dif_swap(phys, virt, pi); | |
590 | p += ts; | |
591 | } | |
592 | kunmap_atomic(pmap); | |
593 | } | |
52b68d7e KB |
594 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
595 | static void nvme_dif_remap(struct request *req, | |
596 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
597 | { | |
598 | } | |
599 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
600 | { | |
601 | } | |
602 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
603 | { | |
604 | } | |
52b68d7e KB |
605 | #endif |
606 | ||
d0877473 KB |
607 | static void nvme_print_sgl(struct scatterlist *sgl, int nents) |
608 | { | |
609 | int i; | |
610 | struct scatterlist *sg; | |
611 | ||
612 | for_each_sg(sgl, sg, nents, i) { | |
613 | dma_addr_t phys = sg_phys(sg); | |
614 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
615 | "dma_address:%pad dma_length:%d\n", | |
616 | i, &phys, sg->offset, sg->length, &sg_dma_address(sg), | |
617 | sg_dma_len(sg)); | |
618 | } | |
619 | } | |
620 | ||
a7a7cbe3 CK |
621 | static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, |
622 | struct request *req, struct nvme_rw_command *cmnd) | |
ff22b54f | 623 | { |
f4800d6d | 624 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 625 | struct dma_pool *pool; |
b131c61d | 626 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 627 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
628 | int dma_len = sg_dma_len(sg); |
629 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 630 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 631 | int offset = dma_addr & (page_size - 1); |
e025344c | 632 | __le64 *prp_list; |
a7a7cbe3 | 633 | void **list = nvme_pci_iod_list(req); |
e025344c | 634 | dma_addr_t prp_dma; |
eca18b23 | 635 | int nprps, i; |
ff22b54f | 636 | |
1d090624 | 637 | length -= (page_size - offset); |
5228b328 JS |
638 | if (length <= 0) { |
639 | iod->first_dma = 0; | |
a7a7cbe3 | 640 | goto done; |
5228b328 | 641 | } |
ff22b54f | 642 | |
1d090624 | 643 | dma_len -= (page_size - offset); |
ff22b54f | 644 | if (dma_len) { |
1d090624 | 645 | dma_addr += (page_size - offset); |
ff22b54f MW |
646 | } else { |
647 | sg = sg_next(sg); | |
648 | dma_addr = sg_dma_address(sg); | |
649 | dma_len = sg_dma_len(sg); | |
650 | } | |
651 | ||
1d090624 | 652 | if (length <= page_size) { |
edd10d33 | 653 | iod->first_dma = dma_addr; |
a7a7cbe3 | 654 | goto done; |
e025344c SMM |
655 | } |
656 | ||
1d090624 | 657 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
658 | if (nprps <= (256 / 8)) { |
659 | pool = dev->prp_small_pool; | |
eca18b23 | 660 | iod->npages = 0; |
99802a7a MW |
661 | } else { |
662 | pool = dev->prp_page_pool; | |
eca18b23 | 663 | iod->npages = 1; |
99802a7a MW |
664 | } |
665 | ||
69d2b571 | 666 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 667 | if (!prp_list) { |
edd10d33 | 668 | iod->first_dma = dma_addr; |
eca18b23 | 669 | iod->npages = -1; |
86eea289 | 670 | return BLK_STS_RESOURCE; |
b77954cb | 671 | } |
eca18b23 MW |
672 | list[0] = prp_list; |
673 | iod->first_dma = prp_dma; | |
e025344c SMM |
674 | i = 0; |
675 | for (;;) { | |
1d090624 | 676 | if (i == page_size >> 3) { |
e025344c | 677 | __le64 *old_prp_list = prp_list; |
69d2b571 | 678 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 679 | if (!prp_list) |
86eea289 | 680 | return BLK_STS_RESOURCE; |
eca18b23 | 681 | list[iod->npages++] = prp_list; |
7523d834 MW |
682 | prp_list[0] = old_prp_list[i - 1]; |
683 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
684 | i = 1; | |
e025344c SMM |
685 | } |
686 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
687 | dma_len -= page_size; |
688 | dma_addr += page_size; | |
689 | length -= page_size; | |
e025344c SMM |
690 | if (length <= 0) |
691 | break; | |
692 | if (dma_len > 0) | |
693 | continue; | |
86eea289 KB |
694 | if (unlikely(dma_len < 0)) |
695 | goto bad_sgl; | |
e025344c SMM |
696 | sg = sg_next(sg); |
697 | dma_addr = sg_dma_address(sg); | |
698 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
699 | } |
700 | ||
a7a7cbe3 CK |
701 | done: |
702 | cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
703 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); | |
704 | ||
86eea289 KB |
705 | return BLK_STS_OK; |
706 | ||
707 | bad_sgl: | |
d0877473 KB |
708 | WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), |
709 | "Invalid SGL for payload:%d nents:%d\n", | |
710 | blk_rq_payload_bytes(req), iod->nents); | |
86eea289 | 711 | return BLK_STS_IOERR; |
ff22b54f MW |
712 | } |
713 | ||
a7a7cbe3 CK |
714 | static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, |
715 | struct scatterlist *sg) | |
716 | { | |
717 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
718 | sge->length = cpu_to_le32(sg_dma_len(sg)); | |
719 | sge->type = NVME_SGL_FMT_DATA_DESC << 4; | |
720 | } | |
721 | ||
722 | static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, | |
723 | dma_addr_t dma_addr, int entries) | |
724 | { | |
725 | sge->addr = cpu_to_le64(dma_addr); | |
726 | if (entries < SGES_PER_PAGE) { | |
727 | sge->length = cpu_to_le32(entries * sizeof(*sge)); | |
728 | sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; | |
729 | } else { | |
730 | sge->length = cpu_to_le32(PAGE_SIZE); | |
731 | sge->type = NVME_SGL_FMT_SEG_DESC << 4; | |
732 | } | |
733 | } | |
734 | ||
735 | static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, | |
b0f2853b | 736 | struct request *req, struct nvme_rw_command *cmd, int entries) |
a7a7cbe3 CK |
737 | { |
738 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 CK |
739 | struct dma_pool *pool; |
740 | struct nvme_sgl_desc *sg_list; | |
741 | struct scatterlist *sg = iod->sg; | |
a7a7cbe3 | 742 | dma_addr_t sgl_dma; |
b0f2853b | 743 | int i = 0; |
a7a7cbe3 | 744 | |
a7a7cbe3 CK |
745 | /* setting the transfer type as SGL */ |
746 | cmd->flags = NVME_CMD_SGL_METABUF; | |
747 | ||
b0f2853b | 748 | if (entries == 1) { |
a7a7cbe3 CK |
749 | nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); |
750 | return BLK_STS_OK; | |
751 | } | |
752 | ||
753 | if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { | |
754 | pool = dev->prp_small_pool; | |
755 | iod->npages = 0; | |
756 | } else { | |
757 | pool = dev->prp_page_pool; | |
758 | iod->npages = 1; | |
759 | } | |
760 | ||
761 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
762 | if (!sg_list) { | |
763 | iod->npages = -1; | |
764 | return BLK_STS_RESOURCE; | |
765 | } | |
766 | ||
767 | nvme_pci_iod_list(req)[0] = sg_list; | |
768 | iod->first_dma = sgl_dma; | |
769 | ||
770 | nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); | |
771 | ||
772 | do { | |
773 | if (i == SGES_PER_PAGE) { | |
774 | struct nvme_sgl_desc *old_sg_desc = sg_list; | |
775 | struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; | |
776 | ||
777 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
778 | if (!sg_list) | |
779 | return BLK_STS_RESOURCE; | |
780 | ||
781 | i = 0; | |
782 | nvme_pci_iod_list(req)[iod->npages++] = sg_list; | |
783 | sg_list[i++] = *link; | |
784 | nvme_pci_sgl_set_seg(link, sgl_dma, entries); | |
785 | } | |
786 | ||
787 | nvme_pci_sgl_set_data(&sg_list[i++], sg); | |
a7a7cbe3 | 788 | sg = sg_next(sg); |
b0f2853b | 789 | } while (--entries > 0); |
a7a7cbe3 | 790 | |
a7a7cbe3 CK |
791 | return BLK_STS_OK; |
792 | } | |
793 | ||
fc17b653 | 794 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 795 | struct nvme_command *cmnd) |
d29ec824 | 796 | { |
f4800d6d | 797 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
798 | struct request_queue *q = req->q; |
799 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
800 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
fc17b653 | 801 | blk_status_t ret = BLK_STS_IOERR; |
b0f2853b | 802 | int nr_mapped; |
d29ec824 | 803 | |
f9d03f96 | 804 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
805 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
806 | if (!iod->nents) | |
807 | goto out; | |
d29ec824 | 808 | |
fc17b653 | 809 | ret = BLK_STS_RESOURCE; |
b0f2853b CH |
810 | nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
811 | DMA_ATTR_NO_WARN); | |
812 | if (!nr_mapped) | |
ba1ca37e | 813 | goto out; |
d29ec824 | 814 | |
955b1b5a | 815 | if (iod->use_sgl) |
b0f2853b | 816 | ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); |
a7a7cbe3 CK |
817 | else |
818 | ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); | |
819 | ||
86eea289 | 820 | if (ret != BLK_STS_OK) |
ba1ca37e | 821 | goto out_unmap; |
0e5e4f0e | 822 | |
fc17b653 | 823 | ret = BLK_STS_IOERR; |
ba1ca37e CH |
824 | if (blk_integrity_rq(req)) { |
825 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
826 | goto out_unmap; | |
0e5e4f0e | 827 | |
bf684057 CH |
828 | sg_init_table(&iod->meta_sg, 1); |
829 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 830 | goto out_unmap; |
0e5e4f0e | 831 | |
b5d8af5b | 832 | if (req_op(req) == REQ_OP_WRITE) |
ba1ca37e | 833 | nvme_dif_remap(req, nvme_dif_prep); |
0e5e4f0e | 834 | |
bf684057 | 835 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 836 | goto out_unmap; |
d29ec824 | 837 | } |
00df5cb4 | 838 | |
ba1ca37e | 839 | if (blk_integrity_rq(req)) |
bf684057 | 840 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
fc17b653 | 841 | return BLK_STS_OK; |
00df5cb4 | 842 | |
ba1ca37e CH |
843 | out_unmap: |
844 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
845 | out: | |
846 | return ret; | |
00df5cb4 MW |
847 | } |
848 | ||
f4800d6d | 849 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 850 | { |
f4800d6d | 851 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
852 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
853 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
854 | ||
855 | if (iod->nents) { | |
856 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
857 | if (blk_integrity_rq(req)) { | |
b5d8af5b | 858 | if (req_op(req) == REQ_OP_READ) |
d4f6c3ab | 859 | nvme_dif_remap(req, nvme_dif_complete); |
bf684057 | 860 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 861 | } |
e19b127f | 862 | } |
e1e5e564 | 863 | |
f9d03f96 | 864 | nvme_cleanup_cmd(req); |
f4800d6d | 865 | nvme_free_iod(dev, req); |
d4f6c3ab | 866 | } |
b60503ba | 867 | |
d29ec824 CH |
868 | /* |
869 | * NOTE: ns is NULL when called on the admin queue. | |
870 | */ | |
fc17b653 | 871 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 872 | const struct blk_mq_queue_data *bd) |
edd10d33 | 873 | { |
a4aea562 MB |
874 | struct nvme_ns *ns = hctx->queue->queuedata; |
875 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 876 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 877 | struct request *req = bd->rq; |
ba1ca37e | 878 | struct nvme_command cmnd; |
ebe6d874 | 879 | blk_status_t ret; |
e1e5e564 | 880 | |
f9d03f96 | 881 | ret = nvme_setup_cmd(ns, req, &cmnd); |
fc17b653 | 882 | if (ret) |
f4800d6d | 883 | return ret; |
a4aea562 | 884 | |
b131c61d | 885 | ret = nvme_init_iod(req, dev); |
fc17b653 | 886 | if (ret) |
f9d03f96 | 887 | goto out_free_cmd; |
a4aea562 | 888 | |
fc17b653 | 889 | if (blk_rq_nr_phys_segments(req)) { |
b131c61d | 890 | ret = nvme_map_data(dev, req, &cmnd); |
fc17b653 CH |
891 | if (ret) |
892 | goto out_cleanup_iod; | |
893 | } | |
a4aea562 | 894 | |
aae239e1 | 895 | blk_mq_start_request(req); |
a4aea562 | 896 | |
ba1ca37e | 897 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 898 | if (unlikely(nvmeq->cq_vector < 0)) { |
fc17b653 | 899 | ret = BLK_STS_IOERR; |
ae1fba20 | 900 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 901 | goto out_cleanup_iod; |
ae1fba20 | 902 | } |
ba1ca37e | 903 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
904 | nvme_process_cq(nvmeq); |
905 | spin_unlock_irq(&nvmeq->q_lock); | |
fc17b653 | 906 | return BLK_STS_OK; |
f9d03f96 | 907 | out_cleanup_iod: |
f4800d6d | 908 | nvme_free_iod(dev, req); |
f9d03f96 CH |
909 | out_free_cmd: |
910 | nvme_cleanup_cmd(req); | |
ba1ca37e | 911 | return ret; |
b60503ba | 912 | } |
e1e5e564 | 913 | |
77f02a7a | 914 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 915 | { |
f4800d6d | 916 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 | 917 | |
77f02a7a CH |
918 | nvme_unmap_data(iod->nvmeq->dev, req); |
919 | nvme_complete_rq(req); | |
b60503ba MW |
920 | } |
921 | ||
d783e0bd MR |
922 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
923 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
924 | u16 phase) | |
925 | { | |
926 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
927 | } | |
928 | ||
eb281c82 | 929 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 930 | { |
eb281c82 | 931 | u16 head = nvmeq->cq_head; |
adf68f21 | 932 | |
eb281c82 SG |
933 | if (likely(nvmeq->cq_vector >= 0)) { |
934 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, | |
935 | nvmeq->dbbuf_cq_ei)) | |
936 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
937 | } | |
938 | } | |
aae239e1 | 939 | |
83a12fb7 SG |
940 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, |
941 | struct nvme_completion *cqe) | |
942 | { | |
943 | struct request *req; | |
adf68f21 | 944 | |
83a12fb7 SG |
945 | if (unlikely(cqe->command_id >= nvmeq->q_depth)) { |
946 | dev_warn(nvmeq->dev->ctrl.device, | |
947 | "invalid id %d completed on queue %d\n", | |
948 | cqe->command_id, le16_to_cpu(cqe->sq_id)); | |
949 | return; | |
b60503ba MW |
950 | } |
951 | ||
83a12fb7 SG |
952 | /* |
953 | * AEN requests are special as they don't time out and can | |
954 | * survive any kind of queue freeze and often don't respond to | |
955 | * aborts. We don't even bother to allocate a struct request | |
956 | * for them but rather special case them here. | |
957 | */ | |
958 | if (unlikely(nvmeq->qid == 0 && | |
38dabe21 | 959 | cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { |
83a12fb7 SG |
960 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
961 | cqe->status, &cqe->result); | |
a0fa9647 | 962 | return; |
83a12fb7 | 963 | } |
b60503ba | 964 | |
e9d8a0fd | 965 | nvmeq->cqe_seen = 1; |
83a12fb7 SG |
966 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); |
967 | nvme_end_request(req, cqe->status, cqe->result); | |
968 | } | |
b60503ba | 969 | |
920d13a8 SG |
970 | static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, |
971 | struct nvme_completion *cqe) | |
b60503ba | 972 | { |
920d13a8 SG |
973 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
974 | *cqe = nvmeq->cqes[nvmeq->cq_head]; | |
adf68f21 | 975 | |
fdcd1de9 | 976 | if (nvmeq->cq_head == nvmeq->q_depth - 1) { |
920d13a8 SG |
977 | nvmeq->cq_head = 0; |
978 | nvmeq->cq_phase = !nvmeq->cq_phase; | |
fdcd1de9 HY |
979 | } else { |
980 | nvmeq->cq_head++; | |
b60503ba | 981 | } |
920d13a8 | 982 | return true; |
b60503ba | 983 | } |
920d13a8 | 984 | return false; |
a0fa9647 JA |
985 | } |
986 | ||
987 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
988 | { | |
920d13a8 SG |
989 | struct nvme_completion cqe; |
990 | int consumed = 0; | |
b60503ba | 991 | |
920d13a8 SG |
992 | while (nvme_read_cqe(nvmeq, &cqe)) { |
993 | nvme_handle_cqe(nvmeq, &cqe); | |
994 | consumed++; | |
920d13a8 | 995 | } |
eb281c82 | 996 | |
e9d8a0fd | 997 | if (consumed) |
920d13a8 | 998 | nvme_ring_cq_doorbell(nvmeq); |
b60503ba MW |
999 | } |
1000 | ||
1001 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
1002 | { |
1003 | irqreturn_t result; | |
1004 | struct nvme_queue *nvmeq = data; | |
1005 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
1006 | nvme_process_cq(nvmeq); |
1007 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
1008 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
1009 | spin_unlock(&nvmeq->q_lock); |
1010 | return result; | |
1011 | } | |
1012 | ||
1013 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
1014 | { | |
1015 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
1016 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
1017 | return IRQ_WAKE_THREAD; | |
1018 | return IRQ_NONE; | |
58ffacb5 MW |
1019 | } |
1020 | ||
7776db1c | 1021 | static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) |
a0fa9647 | 1022 | { |
442e19b7 SG |
1023 | struct nvme_completion cqe; |
1024 | int found = 0, consumed = 0; | |
a0fa9647 | 1025 | |
442e19b7 SG |
1026 | if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
1027 | return 0; | |
a0fa9647 | 1028 | |
442e19b7 SG |
1029 | spin_lock_irq(&nvmeq->q_lock); |
1030 | while (nvme_read_cqe(nvmeq, &cqe)) { | |
1031 | nvme_handle_cqe(nvmeq, &cqe); | |
1032 | consumed++; | |
1033 | ||
1034 | if (tag == cqe.command_id) { | |
1035 | found = 1; | |
1036 | break; | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | if (consumed) | |
1041 | nvme_ring_cq_doorbell(nvmeq); | |
1042 | spin_unlock_irq(&nvmeq->q_lock); | |
1043 | ||
1044 | return found; | |
a0fa9647 JA |
1045 | } |
1046 | ||
7776db1c KB |
1047 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
1048 | { | |
1049 | struct nvme_queue *nvmeq = hctx->driver_data; | |
1050 | ||
1051 | return __nvme_poll(nvmeq, tag); | |
1052 | } | |
1053 | ||
ad22c355 | 1054 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) |
b60503ba | 1055 | { |
f866fc42 | 1056 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 1057 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 1058 | struct nvme_command c; |
b60503ba | 1059 | |
a4aea562 MB |
1060 | memset(&c, 0, sizeof(c)); |
1061 | c.common.opcode = nvme_admin_async_event; | |
ad22c355 | 1062 | c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; |
3c0cf138 | 1063 | |
9396dec9 | 1064 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 1065 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 1066 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
1067 | } |
1068 | ||
b60503ba | 1069 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 1070 | { |
b60503ba MW |
1071 | struct nvme_command c; |
1072 | ||
1073 | memset(&c, 0, sizeof(c)); | |
1074 | c.delete_queue.opcode = opcode; | |
1075 | c.delete_queue.qid = cpu_to_le16(id); | |
1076 | ||
1c63dc66 | 1077 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1078 | } |
1079 | ||
b60503ba MW |
1080 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
1081 | struct nvme_queue *nvmeq) | |
1082 | { | |
5750cb1c | 1083 | struct nvme_ctrl *ctrl = &dev->ctrl; |
b60503ba MW |
1084 | struct nvme_command c; |
1085 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1086 | ||
5750cb1c JA |
1087 | /* |
1088 | * Some drives have a bug that auto-enables WRRU if MEDIUM isn't | |
1089 | * set. Since URGENT priority is zeroes, it makes all queues | |
1090 | * URGENT. | |
1091 | */ | |
1092 | if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) | |
1093 | flags |= NVME_SQ_PRIO_MEDIUM; | |
1094 | ||
d29ec824 | 1095 | /* |
16772ae6 | 1096 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1097 | * is attached to the request. |
1098 | */ | |
b60503ba MW |
1099 | memset(&c, 0, sizeof(c)); |
1100 | c.create_cq.opcode = nvme_admin_create_cq; | |
1101 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1102 | c.create_cq.cqid = cpu_to_le16(qid); | |
1103 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1104 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1105 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1106 | ||
1c63dc66 | 1107 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1108 | } |
1109 | ||
1110 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1111 | struct nvme_queue *nvmeq) | |
1112 | { | |
b60503ba | 1113 | struct nvme_command c; |
81c1cd98 | 1114 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 1115 | |
d29ec824 | 1116 | /* |
16772ae6 | 1117 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1118 | * is attached to the request. |
1119 | */ | |
b60503ba MW |
1120 | memset(&c, 0, sizeof(c)); |
1121 | c.create_sq.opcode = nvme_admin_create_sq; | |
1122 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1123 | c.create_sq.sqid = cpu_to_le16(qid); | |
1124 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1125 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1126 | c.create_sq.cqid = cpu_to_le16(qid); | |
1127 | ||
1c63dc66 | 1128 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1129 | } |
1130 | ||
1131 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1132 | { | |
1133 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1134 | } | |
1135 | ||
1136 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1137 | { | |
1138 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1139 | } | |
1140 | ||
2a842aca | 1141 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 1142 | { |
f4800d6d CH |
1143 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1144 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 1145 | |
27fa9bc5 CH |
1146 | dev_warn(nvmeq->dev->ctrl.device, |
1147 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 1148 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 1149 | blk_mq_free_request(req); |
bc5fc7e4 MW |
1150 | } |
1151 | ||
b2a0eb1a KB |
1152 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1153 | { | |
1154 | ||
1155 | /* If true, indicates loss of adapter communication, possibly by a | |
1156 | * NVMe Subsystem reset. | |
1157 | */ | |
1158 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1159 | ||
1160 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
1161 | if (dev->ctrl.state == NVME_CTRL_RESETTING) | |
1162 | return false; | |
1163 | ||
1164 | /* We shouldn't reset unless the controller is on fatal error state | |
1165 | * _or_ if we lost the communication with it. | |
1166 | */ | |
1167 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1168 | return false; | |
1169 | ||
b2a0eb1a KB |
1170 | return true; |
1171 | } | |
1172 | ||
1173 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1174 | { | |
1175 | /* Read a config register to help see what died. */ | |
1176 | u16 pci_status; | |
1177 | int result; | |
1178 | ||
1179 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1180 | &pci_status); | |
1181 | if (result == PCIBIOS_SUCCESSFUL) | |
1182 | dev_warn(dev->ctrl.device, | |
1183 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1184 | csts, pci_status); | |
1185 | else | |
1186 | dev_warn(dev->ctrl.device, | |
1187 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1188 | csts, result); | |
1189 | } | |
1190 | ||
31c7c7d2 | 1191 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 1192 | { |
f4800d6d CH |
1193 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1194 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 1195 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1196 | struct request *abort_req; |
a4aea562 | 1197 | struct nvme_command cmd; |
b2a0eb1a KB |
1198 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1199 | ||
963e0db6 WX |
1200 | /* If PCI error recovery process is happening, we cannot reset or |
1201 | * the recovery mechanism will surely fail. | |
1202 | */ | |
1203 | mb(); | |
1204 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1205 | return BLK_EH_RESET_TIMER; | |
1206 | ||
b2a0eb1a KB |
1207 | /* |
1208 | * Reset immediately if the controller is failed | |
1209 | */ | |
1210 | if (nvme_should_reset(dev, csts)) { | |
1211 | nvme_warn_reset(dev, csts); | |
1212 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1213 | nvme_reset_ctrl(&dev->ctrl); |
b2a0eb1a KB |
1214 | return BLK_EH_HANDLED; |
1215 | } | |
c30341dc | 1216 | |
7776db1c KB |
1217 | /* |
1218 | * Did we miss an interrupt? | |
1219 | */ | |
1220 | if (__nvme_poll(nvmeq, req->tag)) { | |
1221 | dev_warn(dev->ctrl.device, | |
1222 | "I/O %d QID %d timeout, completion polled\n", | |
1223 | req->tag, nvmeq->qid); | |
1224 | return BLK_EH_HANDLED; | |
1225 | } | |
1226 | ||
31c7c7d2 | 1227 | /* |
fd634f41 CH |
1228 | * Shutdown immediately if controller times out while starting. The |
1229 | * reset work will see the pci device disabled when it gets the forced | |
1230 | * cancellation error. All outstanding requests are completed on | |
1231 | * shutdown, so we return BLK_EH_HANDLED. | |
1232 | */ | |
bb8d261e | 1233 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 1234 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
1235 | "I/O %d QID %d timeout, disable controller\n", |
1236 | req->tag, nvmeq->qid); | |
a5cdb68c | 1237 | nvme_dev_disable(dev, false); |
27fa9bc5 | 1238 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 1239 | return BLK_EH_HANDLED; |
c30341dc KB |
1240 | } |
1241 | ||
fd634f41 CH |
1242 | /* |
1243 | * Shutdown the controller immediately and schedule a reset if the | |
1244 | * command was already aborted once before and still hasn't been | |
1245 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1246 | */ |
f4800d6d | 1247 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1248 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1249 | "I/O %d QID %d timeout, reset controller\n", |
1250 | req->tag, nvmeq->qid); | |
a5cdb68c | 1251 | nvme_dev_disable(dev, false); |
d86c4d8e | 1252 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1253 | |
e1569a16 KB |
1254 | /* |
1255 | * Mark the request as handled, since the inline shutdown | |
1256 | * forces all outstanding requests to complete. | |
1257 | */ | |
27fa9bc5 | 1258 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 1259 | return BLK_EH_HANDLED; |
c30341dc | 1260 | } |
c30341dc | 1261 | |
e7a2a87d | 1262 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1263 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1264 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1265 | } |
7bf7d778 | 1266 | iod->aborted = 1; |
a4aea562 | 1267 | |
c30341dc KB |
1268 | memset(&cmd, 0, sizeof(cmd)); |
1269 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1270 | cmd.abort.cid = req->tag; |
c30341dc | 1271 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1272 | |
1b3c47c1 SG |
1273 | dev_warn(nvmeq->dev->ctrl.device, |
1274 | "I/O %d QID %d timeout, aborting\n", | |
1275 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1276 | |
1277 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1278 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1279 | if (IS_ERR(abort_req)) { |
1280 | atomic_inc(&dev->ctrl.abort_limit); | |
1281 | return BLK_EH_RESET_TIMER; | |
1282 | } | |
1283 | ||
1284 | abort_req->timeout = ADMIN_TIMEOUT; | |
1285 | abort_req->end_io_data = NULL; | |
1286 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1287 | |
31c7c7d2 CH |
1288 | /* |
1289 | * The aborted req will be completed on receiving the abort req. | |
1290 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1291 | * as the device then is in a faulty state. | |
1292 | */ | |
1293 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1294 | } |
1295 | ||
a4aea562 MB |
1296 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1297 | { | |
9e866774 MW |
1298 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1299 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1300 | if (nvmeq->sq_cmds) |
1301 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1302 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1303 | kfree(nvmeq); | |
1304 | } | |
1305 | ||
a1a5ef99 | 1306 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1307 | { |
1308 | int i; | |
1309 | ||
d858e5f0 | 1310 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1311 | struct nvme_queue *nvmeq = dev->queues[i]; |
d858e5f0 | 1312 | dev->ctrl.queue_count--; |
a4aea562 | 1313 | dev->queues[i] = NULL; |
f435c282 | 1314 | nvme_free_queue(nvmeq); |
121c7ad4 | 1315 | } |
22404274 KB |
1316 | } |
1317 | ||
4d115420 KB |
1318 | /** |
1319 | * nvme_suspend_queue - put queue into suspended state | |
1320 | * @nvmeq - queue to suspend | |
4d115420 KB |
1321 | */ |
1322 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1323 | { |
2b25d981 | 1324 | int vector; |
b60503ba | 1325 | |
a09115b2 | 1326 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1327 | if (nvmeq->cq_vector == -1) { |
1328 | spin_unlock_irq(&nvmeq->q_lock); | |
1329 | return 1; | |
1330 | } | |
0ff199cb | 1331 | vector = nvmeq->cq_vector; |
42f61420 | 1332 | nvmeq->dev->online_queues--; |
2b25d981 | 1333 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1334 | spin_unlock_irq(&nvmeq->q_lock); |
1335 | ||
1c63dc66 | 1336 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
c81545f9 | 1337 | blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1338 | |
0ff199cb | 1339 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); |
b60503ba | 1340 | |
4d115420 KB |
1341 | return 0; |
1342 | } | |
b60503ba | 1343 | |
a5cdb68c | 1344 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1345 | { |
a5cdb68c | 1346 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1347 | |
1348 | if (!nvmeq) | |
1349 | return; | |
1350 | if (nvme_suspend_queue(nvmeq)) | |
1351 | return; | |
1352 | ||
a5cdb68c KB |
1353 | if (shutdown) |
1354 | nvme_shutdown_ctrl(&dev->ctrl); | |
1355 | else | |
20d0dfe6 | 1356 | nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
07836e65 KB |
1357 | |
1358 | spin_lock_irq(&nvmeq->q_lock); | |
1359 | nvme_process_cq(nvmeq); | |
1360 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1361 | } |
1362 | ||
8ffaadf7 JD |
1363 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1364 | int entry_size) | |
1365 | { | |
1366 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1367 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1368 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1369 | |
1370 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1371 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1372 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1373 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1374 | |
1375 | /* | |
1376 | * Ensure the reduced q_depth is above some threshold where it | |
1377 | * would be better to map queues in system memory with the | |
1378 | * original depth | |
1379 | */ | |
1380 | if (q_depth < 64) | |
1381 | return -ENOMEM; | |
1382 | } | |
1383 | ||
1384 | return q_depth; | |
1385 | } | |
1386 | ||
1387 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1388 | int qid, int depth) | |
1389 | { | |
57fff717 KB |
1390 | |
1391 | /* CMB SQEs will be mapped before creation */ | |
1392 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) | |
1393 | return 0; | |
1394 | ||
1395 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1396 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1397 | if (!nvmeq->sq_cmds) | |
1398 | return -ENOMEM; | |
8ffaadf7 JD |
1399 | |
1400 | return 0; | |
1401 | } | |
1402 | ||
b60503ba | 1403 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1404 | int depth, int node) |
b60503ba | 1405 | { |
d3af3ecd SL |
1406 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1407 | node); | |
b60503ba MW |
1408 | if (!nvmeq) |
1409 | return NULL; | |
1410 | ||
e75ec752 | 1411 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1412 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1413 | if (!nvmeq->cqes) |
1414 | goto free_nvmeq; | |
b60503ba | 1415 | |
8ffaadf7 | 1416 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1417 | goto free_cqdma; |
1418 | ||
e75ec752 | 1419 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1420 | nvmeq->dev = dev; |
b60503ba MW |
1421 | spin_lock_init(&nvmeq->q_lock); |
1422 | nvmeq->cq_head = 0; | |
82123460 | 1423 | nvmeq->cq_phase = 1; |
b80d5ccc | 1424 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1425 | nvmeq->q_depth = depth; |
c30341dc | 1426 | nvmeq->qid = qid; |
758dd7fd | 1427 | nvmeq->cq_vector = -1; |
a4aea562 | 1428 | dev->queues[qid] = nvmeq; |
d858e5f0 | 1429 | dev->ctrl.queue_count++; |
36a7e993 | 1430 | |
b60503ba MW |
1431 | return nvmeq; |
1432 | ||
1433 | free_cqdma: | |
e75ec752 | 1434 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1435 | nvmeq->cq_dma_addr); |
1436 | free_nvmeq: | |
1437 | kfree(nvmeq); | |
1438 | return NULL; | |
1439 | } | |
1440 | ||
dca51e78 | 1441 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1442 | { |
0ff199cb CH |
1443 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1444 | int nr = nvmeq->dev->ctrl.instance; | |
1445 | ||
1446 | if (use_threaded_interrupts) { | |
1447 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1448 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1449 | } else { | |
1450 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1451 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1452 | } | |
3001082c MW |
1453 | } |
1454 | ||
22404274 | 1455 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1456 | { |
22404274 | 1457 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1458 | |
7be50e93 | 1459 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1460 | nvmeq->sq_tail = 0; |
1461 | nvmeq->cq_head = 0; | |
1462 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1463 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1464 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1465 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1466 | dev->online_queues++; |
7be50e93 | 1467 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1468 | } |
1469 | ||
1470 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1471 | { | |
1472 | struct nvme_dev *dev = nvmeq->dev; | |
1473 | int result; | |
3f85d50b | 1474 | |
57fff717 KB |
1475 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { |
1476 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), | |
1477 | dev->ctrl.page_size); | |
1478 | nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; | |
1479 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1480 | } | |
1481 | ||
2b25d981 | 1482 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1483 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1484 | if (result < 0) | |
8c410b9f | 1485 | goto release_vector; |
b60503ba MW |
1486 | |
1487 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1488 | if (result < 0) | |
1489 | goto release_cq; | |
1490 | ||
161b8be2 | 1491 | nvme_init_queue(nvmeq, qid); |
dca51e78 | 1492 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1493 | if (result < 0) |
1494 | goto release_sq; | |
1495 | ||
22404274 | 1496 | return result; |
b60503ba MW |
1497 | |
1498 | release_sq: | |
8c410b9f | 1499 | dev->online_queues--; |
b60503ba MW |
1500 | adapter_delete_sq(dev, qid); |
1501 | release_cq: | |
1502 | adapter_delete_cq(dev, qid); | |
8c410b9f JW |
1503 | release_vector: |
1504 | nvmeq->cq_vector = -1; | |
22404274 | 1505 | return result; |
b60503ba MW |
1506 | } |
1507 | ||
f363b089 | 1508 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1509 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1510 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1511 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1512 | .exit_hctx = nvme_admin_exit_hctx, |
0350815a | 1513 | .init_request = nvme_init_request, |
a4aea562 MB |
1514 | .timeout = nvme_timeout, |
1515 | }; | |
1516 | ||
f363b089 | 1517 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1518 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1519 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1520 | .init_hctx = nvme_init_hctx, |
1521 | .init_request = nvme_init_request, | |
dca51e78 | 1522 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1523 | .timeout = nvme_timeout, |
a0fa9647 | 1524 | .poll = nvme_poll, |
a4aea562 MB |
1525 | }; |
1526 | ||
ea191d2f KB |
1527 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1528 | { | |
1c63dc66 | 1529 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1530 | /* |
1531 | * If the controller was reset during removal, it's possible | |
1532 | * user requests may be waiting on a stopped queue. Start the | |
1533 | * queue to flush these to completion. | |
1534 | */ | |
c81545f9 | 1535 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
1c63dc66 | 1536 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1537 | blk_mq_free_tag_set(&dev->admin_tagset); |
1538 | } | |
1539 | } | |
1540 | ||
a4aea562 MB |
1541 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1542 | { | |
1c63dc66 | 1543 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1544 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1545 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c | 1546 | |
38dabe21 | 1547 | dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; |
a4aea562 | 1548 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1549 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
a7a7cbe3 | 1550 | dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); |
d3484991 | 1551 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1552 | dev->admin_tagset.driver_data = dev; |
1553 | ||
1554 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1555 | return -ENOMEM; | |
34b6c231 | 1556 | dev->ctrl.admin_tagset = &dev->admin_tagset; |
a4aea562 | 1557 | |
1c63dc66 CH |
1558 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1559 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1560 | blk_mq_free_tag_set(&dev->admin_tagset); |
1561 | return -ENOMEM; | |
1562 | } | |
1c63dc66 | 1563 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1564 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1565 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1566 | return -ENODEV; |
1567 | } | |
0fb59cbc | 1568 | } else |
c81545f9 | 1569 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1570 | |
1571 | return 0; | |
1572 | } | |
1573 | ||
97f6ef64 XY |
1574 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1575 | { | |
1576 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1577 | } | |
1578 | ||
1579 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1580 | { | |
1581 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1582 | ||
1583 | if (size <= dev->bar_mapped_size) | |
1584 | return 0; | |
1585 | if (size > pci_resource_len(pdev, 0)) | |
1586 | return -ENOMEM; | |
1587 | if (dev->bar) | |
1588 | iounmap(dev->bar); | |
1589 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1590 | if (!dev->bar) { | |
1591 | dev->bar_mapped_size = 0; | |
1592 | return -ENOMEM; | |
1593 | } | |
1594 | dev->bar_mapped_size = size; | |
1595 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1596 | ||
1597 | return 0; | |
1598 | } | |
1599 | ||
01ad0990 | 1600 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1601 | { |
ba47e386 | 1602 | int result; |
b60503ba MW |
1603 | u32 aqa; |
1604 | struct nvme_queue *nvmeq; | |
1605 | ||
97f6ef64 XY |
1606 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1607 | if (result < 0) | |
1608 | return result; | |
1609 | ||
8ef2074d | 1610 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1611 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1612 | |
7a67cbea CH |
1613 | if (dev->subsystem && |
1614 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1615 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1616 | |
20d0dfe6 | 1617 | result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
ba47e386 MW |
1618 | if (result < 0) |
1619 | return result; | |
b60503ba | 1620 | |
a4aea562 | 1621 | nvmeq = dev->queues[0]; |
cd638946 | 1622 | if (!nvmeq) { |
d3af3ecd SL |
1623 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1624 | dev_to_node(dev->dev)); | |
cd638946 KB |
1625 | if (!nvmeq) |
1626 | return -ENOMEM; | |
cd638946 | 1627 | } |
b60503ba MW |
1628 | |
1629 | aqa = nvmeq->q_depth - 1; | |
1630 | aqa |= aqa << 16; | |
1631 | ||
7a67cbea CH |
1632 | writel(aqa, dev->bar + NVME_REG_AQA); |
1633 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1634 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1635 | |
20d0dfe6 | 1636 | result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); |
025c557a | 1637 | if (result) |
d4875622 | 1638 | return result; |
a4aea562 | 1639 | |
2b25d981 | 1640 | nvmeq->cq_vector = 0; |
161b8be2 | 1641 | nvme_init_queue(nvmeq, 0); |
dca51e78 | 1642 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1643 | if (result) { |
1644 | nvmeq->cq_vector = -1; | |
d4875622 | 1645 | return result; |
758dd7fd | 1646 | } |
025c557a | 1647 | |
b60503ba MW |
1648 | return result; |
1649 | } | |
1650 | ||
749941f2 | 1651 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1652 | { |
949928c1 | 1653 | unsigned i, max; |
749941f2 | 1654 | int ret = 0; |
42f61420 | 1655 | |
d858e5f0 | 1656 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1657 | /* vector == qid - 1, match nvme_create_queue */ |
1658 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1659 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1660 | ret = -ENOMEM; |
42f61420 | 1661 | break; |
749941f2 CH |
1662 | } |
1663 | } | |
42f61420 | 1664 | |
d858e5f0 | 1665 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
949928c1 | 1666 | for (i = dev->online_queues; i <= max; i++) { |
749941f2 | 1667 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1668 | if (ret) |
42f61420 | 1669 | break; |
27e8166c | 1670 | } |
749941f2 CH |
1671 | |
1672 | /* | |
1673 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1674 | * than the desired aount of queues, and even a controller without | |
1675 | * I/O queues an still be used to issue admin commands. This might | |
1676 | * be useful to upgrade a buggy firmware for example. | |
1677 | */ | |
1678 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1679 | } |
1680 | ||
202021c1 SB |
1681 | static ssize_t nvme_cmb_show(struct device *dev, |
1682 | struct device_attribute *attr, | |
1683 | char *buf) | |
1684 | { | |
1685 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1686 | ||
c965809c | 1687 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1688 | ndev->cmbloc, ndev->cmbsz); |
1689 | } | |
1690 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1691 | ||
8ffaadf7 JD |
1692 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1693 | { | |
1694 | u64 szu, size, offset; | |
8ffaadf7 JD |
1695 | resource_size_t bar_size; |
1696 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1697 | void __iomem *cmb; | |
8969f1f8 | 1698 | int bar; |
8ffaadf7 | 1699 | |
7a67cbea | 1700 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1701 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1702 | return NULL; | |
202021c1 | 1703 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1704 | |
202021c1 SB |
1705 | if (!use_cmb_sqes) |
1706 | return NULL; | |
8ffaadf7 JD |
1707 | |
1708 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1709 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 | 1710 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
8969f1f8 CH |
1711 | bar = NVME_CMB_BIR(dev->cmbloc); |
1712 | bar_size = pci_resource_len(pdev, bar); | |
8ffaadf7 JD |
1713 | |
1714 | if (offset > bar_size) | |
1715 | return NULL; | |
1716 | ||
1717 | /* | |
1718 | * Controllers may support a CMB size larger than their BAR, | |
1719 | * for example, due to being behind a bridge. Reduce the CMB to | |
1720 | * the reported size of the BAR | |
1721 | */ | |
1722 | if (size > bar_size - offset) | |
1723 | size = bar_size - offset; | |
1724 | ||
8969f1f8 | 1725 | cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); |
8ffaadf7 JD |
1726 | if (!cmb) |
1727 | return NULL; | |
1728 | ||
8969f1f8 | 1729 | dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; |
8ffaadf7 JD |
1730 | dev->cmb_size = size; |
1731 | return cmb; | |
1732 | } | |
1733 | ||
1734 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1735 | { | |
1736 | if (dev->cmb) { | |
1737 | iounmap(dev->cmb); | |
1738 | dev->cmb = NULL; | |
1c78f773 MG |
1739 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, |
1740 | &dev_attr_cmb.attr, NULL); | |
1741 | dev->cmbsz = 0; | |
8ffaadf7 JD |
1742 | } |
1743 | } | |
1744 | ||
87ad72a5 CH |
1745 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1746 | { | |
4033f35d | 1747 | u64 dma_addr = dev->host_mem_descs_dma; |
87ad72a5 | 1748 | struct nvme_command c; |
87ad72a5 CH |
1749 | int ret; |
1750 | ||
87ad72a5 CH |
1751 | memset(&c, 0, sizeof(c)); |
1752 | c.features.opcode = nvme_admin_set_features; | |
1753 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1754 | c.features.dword11 = cpu_to_le32(bits); | |
1755 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> | |
1756 | ilog2(dev->ctrl.page_size)); | |
1757 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); | |
1758 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1759 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1760 | ||
1761 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1762 | if (ret) { | |
1763 | dev_warn(dev->ctrl.device, | |
1764 | "failed to set host mem (err %d, flags %#x).\n", | |
1765 | ret, bits); | |
1766 | } | |
87ad72a5 CH |
1767 | return ret; |
1768 | } | |
1769 | ||
1770 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1771 | { | |
1772 | int i; | |
1773 | ||
1774 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1775 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
1776 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; | |
1777 | ||
1778 | dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], | |
1779 | le64_to_cpu(desc->addr)); | |
1780 | } | |
1781 | ||
1782 | kfree(dev->host_mem_desc_bufs); | |
1783 | dev->host_mem_desc_bufs = NULL; | |
4033f35d CH |
1784 | dma_free_coherent(dev->dev, |
1785 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), | |
1786 | dev->host_mem_descs, dev->host_mem_descs_dma); | |
87ad72a5 | 1787 | dev->host_mem_descs = NULL; |
7e5dd57e | 1788 | dev->nr_host_mem_descs = 0; |
87ad72a5 CH |
1789 | } |
1790 | ||
92dc6895 CH |
1791 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
1792 | u32 chunk_size) | |
9d713c2b | 1793 | { |
87ad72a5 | 1794 | struct nvme_host_mem_buf_desc *descs; |
92dc6895 | 1795 | u32 max_entries, len; |
4033f35d | 1796 | dma_addr_t descs_dma; |
2ee0e4ed | 1797 | int i = 0; |
87ad72a5 | 1798 | void **bufs; |
2ee0e4ed | 1799 | u64 size = 0, tmp; |
87ad72a5 | 1800 | |
87ad72a5 CH |
1801 | tmp = (preferred + chunk_size - 1); |
1802 | do_div(tmp, chunk_size); | |
1803 | max_entries = tmp; | |
044a9df1 CH |
1804 | |
1805 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) | |
1806 | max_entries = dev->ctrl.hmmaxd; | |
1807 | ||
4033f35d CH |
1808 | descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), |
1809 | &descs_dma, GFP_KERNEL); | |
87ad72a5 CH |
1810 | if (!descs) |
1811 | goto out; | |
1812 | ||
1813 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1814 | if (!bufs) | |
1815 | goto out_free_descs; | |
1816 | ||
244a8fe4 | 1817 | for (size = 0; size < preferred && i < max_entries; size += len) { |
87ad72a5 CH |
1818 | dma_addr_t dma_addr; |
1819 | ||
50cdb7c6 | 1820 | len = min_t(u64, chunk_size, preferred - size); |
87ad72a5 CH |
1821 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
1822 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1823 | if (!bufs[i]) | |
1824 | break; | |
1825 | ||
1826 | descs[i].addr = cpu_to_le64(dma_addr); | |
1827 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); | |
1828 | i++; | |
1829 | } | |
1830 | ||
92dc6895 | 1831 | if (!size) |
87ad72a5 | 1832 | goto out_free_bufs; |
87ad72a5 | 1833 | |
87ad72a5 CH |
1834 | dev->nr_host_mem_descs = i; |
1835 | dev->host_mem_size = size; | |
1836 | dev->host_mem_descs = descs; | |
4033f35d | 1837 | dev->host_mem_descs_dma = descs_dma; |
87ad72a5 CH |
1838 | dev->host_mem_desc_bufs = bufs; |
1839 | return 0; | |
1840 | ||
1841 | out_free_bufs: | |
1842 | while (--i >= 0) { | |
1843 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; | |
1844 | ||
1845 | dma_free_coherent(dev->dev, size, bufs[i], | |
1846 | le64_to_cpu(descs[i].addr)); | |
1847 | } | |
1848 | ||
1849 | kfree(bufs); | |
1850 | out_free_descs: | |
4033f35d CH |
1851 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
1852 | descs_dma); | |
87ad72a5 | 1853 | out: |
87ad72a5 CH |
1854 | dev->host_mem_descs = NULL; |
1855 | return -ENOMEM; | |
1856 | } | |
1857 | ||
92dc6895 CH |
1858 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
1859 | { | |
1860 | u32 chunk_size; | |
1861 | ||
1862 | /* start big and work our way down */ | |
30f92d62 | 1863 | for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
044a9df1 | 1864 | chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); |
92dc6895 CH |
1865 | chunk_size /= 2) { |
1866 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { | |
1867 | if (!min || dev->host_mem_size >= min) | |
1868 | return 0; | |
1869 | nvme_free_host_mem(dev); | |
1870 | } | |
1871 | } | |
1872 | ||
1873 | return -ENOMEM; | |
1874 | } | |
1875 | ||
9620cfba | 1876 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
87ad72a5 CH |
1877 | { |
1878 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
1879 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
1880 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
1881 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
9620cfba | 1882 | int ret = 0; |
87ad72a5 CH |
1883 | |
1884 | preferred = min(preferred, max); | |
1885 | if (min > max) { | |
1886 | dev_warn(dev->ctrl.device, | |
1887 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
1888 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
1889 | nvme_free_host_mem(dev); | |
9620cfba | 1890 | return 0; |
87ad72a5 CH |
1891 | } |
1892 | ||
1893 | /* | |
1894 | * If we already have a buffer allocated check if we can reuse it. | |
1895 | */ | |
1896 | if (dev->host_mem_descs) { | |
1897 | if (dev->host_mem_size >= min) | |
1898 | enable_bits |= NVME_HOST_MEM_RETURN; | |
1899 | else | |
1900 | nvme_free_host_mem(dev); | |
1901 | } | |
1902 | ||
1903 | if (!dev->host_mem_descs) { | |
92dc6895 CH |
1904 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
1905 | dev_warn(dev->ctrl.device, | |
1906 | "failed to allocate host memory buffer.\n"); | |
9620cfba | 1907 | return 0; /* controller must work without HMB */ |
92dc6895 CH |
1908 | } |
1909 | ||
1910 | dev_info(dev->ctrl.device, | |
1911 | "allocated %lld MiB host memory buffer.\n", | |
1912 | dev->host_mem_size >> ilog2(SZ_1M)); | |
87ad72a5 CH |
1913 | } |
1914 | ||
9620cfba CH |
1915 | ret = nvme_set_host_mem(dev, enable_bits); |
1916 | if (ret) | |
87ad72a5 | 1917 | nvme_free_host_mem(dev); |
9620cfba | 1918 | return ret; |
9d713c2b KB |
1919 | } |
1920 | ||
8d85fce7 | 1921 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1922 | { |
a4aea562 | 1923 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1924 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
97f6ef64 XY |
1925 | int result, nr_io_queues; |
1926 | unsigned long size; | |
b60503ba | 1927 | |
77aa379d | 1928 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1929 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1930 | if (result < 0) | |
1b23484b | 1931 | return result; |
9a0be7ab | 1932 | |
f5fa90dc | 1933 | if (nr_io_queues == 0) |
a5229050 | 1934 | return 0; |
b60503ba | 1935 | |
8ffaadf7 JD |
1936 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1937 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1938 | sizeof(struct nvme_command)); | |
1939 | if (result > 0) | |
1940 | dev->q_depth = result; | |
1941 | else | |
1942 | nvme_release_cmb(dev); | |
1943 | } | |
1944 | ||
97f6ef64 XY |
1945 | do { |
1946 | size = db_bar_size(dev, nr_io_queues); | |
1947 | result = nvme_remap_bar(dev, size); | |
1948 | if (!result) | |
1949 | break; | |
1950 | if (!--nr_io_queues) | |
1951 | return -ENOMEM; | |
1952 | } while (1); | |
1953 | adminq->q_db = dev->dbs; | |
f1938f6e | 1954 | |
9d713c2b | 1955 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 1956 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 1957 | |
e32efbfc JA |
1958 | /* |
1959 | * If we enable msix early due to not intx, disable it again before | |
1960 | * setting up the full range we need. | |
1961 | */ | |
dca51e78 CH |
1962 | pci_free_irq_vectors(pdev); |
1963 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1964 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1965 | if (nr_io_queues <= 0) | |
1966 | return -EIO; | |
1967 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1968 | |
063a8096 MW |
1969 | /* |
1970 | * Should investigate if there's a performance win from allocating | |
1971 | * more queues than interrupt vectors; it might allow the submission | |
1972 | * path to scale better, even if the receive path is limited by the | |
1973 | * number of interrupts. | |
1974 | */ | |
063a8096 | 1975 | |
dca51e78 | 1976 | result = queue_request_irq(adminq); |
758dd7fd JD |
1977 | if (result) { |
1978 | adminq->cq_vector = -1; | |
d4875622 | 1979 | return result; |
758dd7fd | 1980 | } |
749941f2 | 1981 | return nvme_create_io_queues(dev); |
b60503ba MW |
1982 | } |
1983 | ||
2a842aca | 1984 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 1985 | { |
db3cbfff | 1986 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1987 | |
db3cbfff KB |
1988 | blk_mq_free_request(req); |
1989 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1990 | } |
1991 | ||
2a842aca | 1992 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 1993 | { |
db3cbfff | 1994 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1995 | |
db3cbfff KB |
1996 | if (!error) { |
1997 | unsigned long flags; | |
1998 | ||
2e39e0f6 ML |
1999 | /* |
2000 | * We might be called with the AQ q_lock held | |
2001 | * and the I/O queue q_lock should always | |
2002 | * nest inside the AQ one. | |
2003 | */ | |
2004 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
2005 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
2006 | nvme_process_cq(nvmeq); |
2007 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 2008 | } |
db3cbfff KB |
2009 | |
2010 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
2011 | } |
2012 | ||
db3cbfff | 2013 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 2014 | { |
db3cbfff KB |
2015 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
2016 | struct request *req; | |
2017 | struct nvme_command cmd; | |
bda4e0fb | 2018 | |
db3cbfff KB |
2019 | memset(&cmd, 0, sizeof(cmd)); |
2020 | cmd.delete_queue.opcode = opcode; | |
2021 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 2022 | |
eb71f435 | 2023 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
2024 | if (IS_ERR(req)) |
2025 | return PTR_ERR(req); | |
bda4e0fb | 2026 | |
db3cbfff KB |
2027 | req->timeout = ADMIN_TIMEOUT; |
2028 | req->end_io_data = nvmeq; | |
2029 | ||
2030 | blk_execute_rq_nowait(q, NULL, req, false, | |
2031 | opcode == nvme_admin_delete_cq ? | |
2032 | nvme_del_cq_end : nvme_del_queue_end); | |
2033 | return 0; | |
bda4e0fb KB |
2034 | } |
2035 | ||
70659060 | 2036 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 2037 | { |
70659060 | 2038 | int pass; |
db3cbfff KB |
2039 | unsigned long timeout; |
2040 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 2041 | |
db3cbfff | 2042 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 2043 | int sent = 0, i = queues; |
db3cbfff KB |
2044 | |
2045 | reinit_completion(&dev->ioq_wait); | |
2046 | retry: | |
2047 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
2048 | for (; i > 0; i--, sent++) |
2049 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 2050 | break; |
c21377f8 | 2051 | |
db3cbfff KB |
2052 | while (sent--) { |
2053 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
2054 | if (timeout == 0) | |
2055 | return; | |
2056 | if (i) | |
2057 | goto retry; | |
2058 | } | |
2059 | opcode = nvme_admin_delete_cq; | |
2060 | } | |
a5768aa8 KB |
2061 | } |
2062 | ||
422ef0c7 MW |
2063 | /* |
2064 | * Return: error value if an error occurred setting up the queues or calling | |
2065 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2066 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2067 | * failures should be reported. | |
2068 | */ | |
8d85fce7 | 2069 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2070 | { |
5bae7f73 | 2071 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
2072 | dev->tagset.ops = &nvme_mq_ops; |
2073 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2074 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
2075 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
2076 | dev->tagset.queue_depth = | |
a4aea562 | 2077 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
a7a7cbe3 CK |
2078 | dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); |
2079 | if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { | |
2080 | dev->tagset.cmd_size = max(dev->tagset.cmd_size, | |
2081 | nvme_pci_cmd_size(dev, true)); | |
2082 | } | |
ffe7704d KB |
2083 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
2084 | dev->tagset.driver_data = dev; | |
b60503ba | 2085 | |
ffe7704d KB |
2086 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
2087 | return 0; | |
5bae7f73 | 2088 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
2089 | |
2090 | nvme_dbbuf_set(dev); | |
949928c1 KB |
2091 | } else { |
2092 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
2093 | ||
2094 | /* Free previously allocated queues that are no longer usable */ | |
2095 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 2096 | } |
949928c1 | 2097 | |
e1e5e564 | 2098 | return 0; |
b60503ba MW |
2099 | } |
2100 | ||
b00a726a | 2101 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 2102 | { |
b00a726a | 2103 | int result = -ENOMEM; |
e75ec752 | 2104 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
2105 | |
2106 | if (pci_enable_device_mem(pdev)) | |
2107 | return result; | |
2108 | ||
0877cb0d | 2109 | pci_set_master(pdev); |
0877cb0d | 2110 | |
e75ec752 CH |
2111 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
2112 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 2113 | goto disable; |
0877cb0d | 2114 | |
7a67cbea | 2115 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 2116 | result = -ENODEV; |
b00a726a | 2117 | goto disable; |
0e53d180 | 2118 | } |
e32efbfc JA |
2119 | |
2120 | /* | |
a5229050 KB |
2121 | * Some devices and/or platforms don't advertise or work with INTx |
2122 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
2123 | * adjust this later. | |
e32efbfc | 2124 | */ |
dca51e78 CH |
2125 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
2126 | if (result < 0) | |
2127 | return result; | |
e32efbfc | 2128 | |
20d0dfe6 | 2129 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 2130 | |
20d0dfe6 | 2131 | dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 2132 | io_queue_depth); |
20d0dfe6 | 2133 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 2134 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
2135 | |
2136 | /* | |
2137 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
2138 | * some MacBook7,1 to avoid controller resets and data loss. | |
2139 | */ | |
2140 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
2141 | dev->q_depth = 2; | |
9bdcfb10 CH |
2142 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
2143 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 2144 | dev->q_depth); |
d554b5e1 MP |
2145 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
2146 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 2147 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
2148 | dev->q_depth = 64; |
2149 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
2150 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
2151 | } |
2152 | ||
202021c1 SB |
2153 | /* |
2154 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1c78f773 MG |
2155 | * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group |
2156 | * has no name we can pass NULL as final argument to | |
2157 | * sysfs_add_file_to_group. | |
202021c1 SB |
2158 | */ |
2159 | ||
8ef2074d | 2160 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 2161 | dev->cmb = nvme_map_cmb(dev); |
1c78f773 | 2162 | if (dev->cmb) { |
202021c1 SB |
2163 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, |
2164 | &dev_attr_cmb.attr, NULL)) | |
9bdcfb10 | 2165 | dev_warn(dev->ctrl.device, |
202021c1 SB |
2166 | "failed to add sysfs attribute for CMB\n"); |
2167 | } | |
2168 | } | |
2169 | ||
a0a3408e KB |
2170 | pci_enable_pcie_error_reporting(pdev); |
2171 | pci_save_state(pdev); | |
0877cb0d KB |
2172 | return 0; |
2173 | ||
2174 | disable: | |
0877cb0d KB |
2175 | pci_disable_device(pdev); |
2176 | return result; | |
2177 | } | |
2178 | ||
2179 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
2180 | { |
2181 | if (dev->bar) | |
2182 | iounmap(dev->bar); | |
a1f447b3 | 2183 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
2184 | } |
2185 | ||
2186 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 2187 | { |
e75ec752 CH |
2188 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2189 | ||
f63572df | 2190 | nvme_release_cmb(dev); |
dca51e78 | 2191 | pci_free_irq_vectors(pdev); |
0877cb0d | 2192 | |
a0a3408e KB |
2193 | if (pci_is_enabled(pdev)) { |
2194 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 2195 | pci_disable_device(pdev); |
4d115420 | 2196 | } |
4d115420 KB |
2197 | } |
2198 | ||
a5cdb68c | 2199 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2200 | { |
70659060 | 2201 | int i, queues; |
302ad8cc KB |
2202 | bool dead = true; |
2203 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 2204 | |
77bf25ea | 2205 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
2206 | if (pci_is_enabled(pdev)) { |
2207 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
2208 | ||
ebef7368 KB |
2209 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
2210 | dev->ctrl.state == NVME_CTRL_RESETTING) | |
302ad8cc KB |
2211 | nvme_start_freeze(&dev->ctrl); |
2212 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
2213 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2214 | } |
c21377f8 | 2215 | |
302ad8cc KB |
2216 | /* |
2217 | * Give the controller a chance to complete all entered requests if | |
2218 | * doing a safe shutdown. | |
2219 | */ | |
87ad72a5 CH |
2220 | if (!dead) { |
2221 | if (shutdown) | |
2222 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
2223 | ||
2224 | /* | |
2225 | * If the controller is still alive tell it to stop using the | |
2226 | * host memory buffer. In theory the shutdown / reset should | |
2227 | * make sure that it doesn't access the host memoery anymore, | |
2228 | * but I'd rather be safe than sorry.. | |
2229 | */ | |
2230 | if (dev->host_mem_descs) | |
2231 | nvme_set_host_mem(dev, 0); | |
2232 | ||
2233 | } | |
302ad8cc KB |
2234 | nvme_stop_queues(&dev->ctrl); |
2235 | ||
70659060 | 2236 | queues = dev->online_queues - 1; |
d858e5f0 | 2237 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) |
c21377f8 GKB |
2238 | nvme_suspend_queue(dev->queues[i]); |
2239 | ||
302ad8cc | 2240 | if (dead) { |
82469c59 GKB |
2241 | /* A device might become IO incapable very soon during |
2242 | * probe, before the admin queue is configured. Thus, | |
2243 | * queue_count can be 0 here. | |
2244 | */ | |
d858e5f0 | 2245 | if (dev->ctrl.queue_count) |
82469c59 | 2246 | nvme_suspend_queue(dev->queues[0]); |
4d115420 | 2247 | } else { |
70659060 | 2248 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 2249 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2250 | } |
b00a726a | 2251 | nvme_pci_disable(dev); |
07836e65 | 2252 | |
e1958e65 ML |
2253 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
2254 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
2255 | |
2256 | /* | |
2257 | * The driver will not be starting up queues again if shutting down so | |
2258 | * must flush all entered requests to their failed completion to avoid | |
2259 | * deadlocking blk-mq hot-cpu notifier. | |
2260 | */ | |
2261 | if (shutdown) | |
2262 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 2263 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2264 | } |
2265 | ||
091b6092 MW |
2266 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2267 | { | |
e75ec752 | 2268 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2269 | PAGE_SIZE, PAGE_SIZE, 0); |
2270 | if (!dev->prp_page_pool) | |
2271 | return -ENOMEM; | |
2272 | ||
99802a7a | 2273 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2274 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2275 | 256, 256, 0); |
2276 | if (!dev->prp_small_pool) { | |
2277 | dma_pool_destroy(dev->prp_page_pool); | |
2278 | return -ENOMEM; | |
2279 | } | |
091b6092 MW |
2280 | return 0; |
2281 | } | |
2282 | ||
2283 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2284 | { | |
2285 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2286 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2287 | } |
2288 | ||
1673f1f0 | 2289 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2290 | { |
1673f1f0 | 2291 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2292 | |
f9f38e33 | 2293 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 2294 | put_device(dev->dev); |
4af0e21c KB |
2295 | if (dev->tagset.tags) |
2296 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2297 | if (dev->ctrl.admin_q) |
2298 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 2299 | kfree(dev->queues); |
e286bcfc | 2300 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
2301 | kfree(dev); |
2302 | } | |
2303 | ||
f58944e2 KB |
2304 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
2305 | { | |
237045fc | 2306 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 | 2307 | |
d22524a4 | 2308 | nvme_get_ctrl(&dev->ctrl); |
69d9a99c | 2309 | nvme_dev_disable(dev, false); |
03e0f3a6 | 2310 | if (!queue_work(nvme_wq, &dev->remove_work)) |
f58944e2 KB |
2311 | nvme_put_ctrl(&dev->ctrl); |
2312 | } | |
2313 | ||
fd634f41 | 2314 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2315 | { |
d86c4d8e CH |
2316 | struct nvme_dev *dev = |
2317 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2318 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 2319 | int result = -ENODEV; |
5e82e952 | 2320 | |
82b057ca | 2321 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 2322 | goto out; |
5e82e952 | 2323 | |
fd634f41 CH |
2324 | /* |
2325 | * If we're called to reset a live controller first shut it down before | |
2326 | * moving on. | |
2327 | */ | |
b00a726a | 2328 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2329 | nvme_dev_disable(dev, false); |
5e82e952 | 2330 | |
b00a726a | 2331 | result = nvme_pci_enable(dev); |
f0b50732 | 2332 | if (result) |
3cf519b5 | 2333 | goto out; |
f0b50732 | 2334 | |
01ad0990 | 2335 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2336 | if (result) |
f58944e2 | 2337 | goto out; |
f0b50732 | 2338 | |
0fb59cbc KB |
2339 | result = nvme_alloc_admin_tags(dev); |
2340 | if (result) | |
f58944e2 | 2341 | goto out; |
b9afca3e | 2342 | |
ce4541f4 CH |
2343 | result = nvme_init_identify(&dev->ctrl); |
2344 | if (result) | |
f58944e2 | 2345 | goto out; |
ce4541f4 | 2346 | |
e286bcfc SB |
2347 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2348 | if (!dev->ctrl.opal_dev) | |
2349 | dev->ctrl.opal_dev = | |
2350 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2351 | else if (was_suspend) | |
2352 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2353 | } else { | |
2354 | free_opal_dev(dev->ctrl.opal_dev); | |
2355 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2356 | } |
a98e58e5 | 2357 | |
f9f38e33 HK |
2358 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2359 | result = nvme_dbbuf_dma_alloc(dev); | |
2360 | if (result) | |
2361 | dev_warn(dev->dev, | |
2362 | "unable to allocate dma for dbbuf\n"); | |
2363 | } | |
2364 | ||
9620cfba CH |
2365 | if (dev->ctrl.hmpre) { |
2366 | result = nvme_setup_host_mem(dev); | |
2367 | if (result < 0) | |
2368 | goto out; | |
2369 | } | |
87ad72a5 | 2370 | |
f0b50732 | 2371 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2372 | if (result) |
f58944e2 | 2373 | goto out; |
f0b50732 | 2374 | |
2659e57b CH |
2375 | /* |
2376 | * Keep the controller around but remove all namespaces if we don't have | |
2377 | * any working I/O queue. | |
2378 | */ | |
3cf519b5 | 2379 | if (dev->online_queues < 2) { |
1b3c47c1 | 2380 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2381 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2382 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 2383 | } else { |
25646264 | 2384 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2385 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 2386 | nvme_dev_add(dev); |
302ad8cc | 2387 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2388 | } |
2389 | ||
bb8d261e CH |
2390 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2391 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
2392 | goto out; | |
2393 | } | |
92911a55 | 2394 | |
d09f2b45 | 2395 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2396 | return; |
f0b50732 | 2397 | |
3cf519b5 | 2398 | out: |
f58944e2 | 2399 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
2400 | } |
2401 | ||
5c8809e6 | 2402 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2403 | { |
5c8809e6 | 2404 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2405 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 2406 | |
69d9a99c | 2407 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 2408 | if (pci_get_drvdata(pdev)) |
921920ab | 2409 | device_release_driver(&pdev->dev); |
1673f1f0 | 2410 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2411 | } |
2412 | ||
1c63dc66 | 2413 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2414 | { |
1c63dc66 | 2415 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2416 | return 0; |
9ca97374 TH |
2417 | } |
2418 | ||
5fd4ce1b | 2419 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2420 | { |
5fd4ce1b CH |
2421 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2422 | return 0; | |
2423 | } | |
4cc06521 | 2424 | |
7fd8930f CH |
2425 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2426 | { | |
2427 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2428 | return 0; | |
4cc06521 KB |
2429 | } |
2430 | ||
1c63dc66 | 2431 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2432 | .name = "pcie", |
e439bb12 | 2433 | .module = THIS_MODULE, |
c81bfba9 | 2434 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 2435 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2436 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2437 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2438 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2439 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2440 | }; |
4cc06521 | 2441 | |
b00a726a KB |
2442 | static int nvme_dev_map(struct nvme_dev *dev) |
2443 | { | |
b00a726a KB |
2444 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2445 | ||
a1f447b3 | 2446 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2447 | return -ENODEV; |
2448 | ||
97f6ef64 | 2449 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2450 | goto release; |
2451 | ||
9fa196e7 | 2452 | return 0; |
b00a726a | 2453 | release: |
9fa196e7 MG |
2454 | pci_release_mem_regions(pdev); |
2455 | return -ENODEV; | |
b00a726a KB |
2456 | } |
2457 | ||
8427bbc2 | 2458 | static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) |
ff5350a8 AL |
2459 | { |
2460 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2461 | /* | |
2462 | * Several Samsung devices seem to drop off the PCIe bus | |
2463 | * randomly when APST is on and uses the deepest sleep state. | |
2464 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2465 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2466 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2467 | * laptops. | |
2468 | */ | |
2469 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2470 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2471 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2472 | return NVME_QUIRK_NO_DEEPEST_PS; | |
8427bbc2 KHF |
2473 | } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { |
2474 | /* | |
2475 | * Samsung SSD 960 EVO drops off the PCIe bus after system | |
8ec9bf9c JJ |
2476 | * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as |
2477 | * within few minutes after bootup on a Coffee Lake board - | |
2478 | * ASUS PRIME Z370-A | |
8427bbc2 KHF |
2479 | */ |
2480 | if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && | |
8ec9bf9c JJ |
2481 | (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || |
2482 | dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) | |
8427bbc2 | 2483 | return NVME_QUIRK_NO_APST; |
ff5350a8 AL |
2484 | } |
2485 | ||
2486 | return 0; | |
2487 | } | |
2488 | ||
8d85fce7 | 2489 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2490 | { |
a4aea562 | 2491 | int node, result = -ENOMEM; |
b60503ba | 2492 | struct nvme_dev *dev; |
ff5350a8 | 2493 | unsigned long quirks = id->driver_data; |
b60503ba | 2494 | |
a4aea562 MB |
2495 | node = dev_to_node(&pdev->dev); |
2496 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2497 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2498 | |
2499 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2500 | if (!dev) |
2501 | return -ENOMEM; | |
a4aea562 MB |
2502 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2503 | GFP_KERNEL, node); | |
b60503ba MW |
2504 | if (!dev->queues) |
2505 | goto free; | |
2506 | ||
e75ec752 | 2507 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2508 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2509 | |
b00a726a KB |
2510 | result = nvme_dev_map(dev); |
2511 | if (result) | |
b00c9b7a | 2512 | goto put_pci; |
b00a726a | 2513 | |
d86c4d8e | 2514 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2515 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2516 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2517 | init_completion(&dev->ioq_wait); |
b60503ba | 2518 | |
091b6092 MW |
2519 | result = nvme_setup_prp_pools(dev); |
2520 | if (result) | |
b00c9b7a | 2521 | goto unmap; |
4cc06521 | 2522 | |
8427bbc2 | 2523 | quirks |= check_vendor_combination_bug(pdev); |
ff5350a8 | 2524 | |
f3ca80fc | 2525 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
ff5350a8 | 2526 | quirks); |
4cc06521 | 2527 | if (result) |
2e1d8448 | 2528 | goto release_pools; |
740216fc | 2529 | |
82b057ca | 2530 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); |
1b3c47c1 SG |
2531 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2532 | ||
d86c4d8e | 2533 | queue_work(nvme_wq, &dev->ctrl.reset_work); |
b60503ba MW |
2534 | return 0; |
2535 | ||
0877cb0d | 2536 | release_pools: |
091b6092 | 2537 | nvme_release_prp_pools(dev); |
b00c9b7a CJ |
2538 | unmap: |
2539 | nvme_dev_unmap(dev); | |
a96d4f5c | 2540 | put_pci: |
e75ec752 | 2541 | put_device(dev->dev); |
b60503ba MW |
2542 | free: |
2543 | kfree(dev->queues); | |
b60503ba MW |
2544 | kfree(dev); |
2545 | return result; | |
2546 | } | |
2547 | ||
775755ed | 2548 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 2549 | { |
a6739479 | 2550 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f263fbb8 | 2551 | nvme_dev_disable(dev, false); |
775755ed | 2552 | } |
f0d54a54 | 2553 | |
775755ed CH |
2554 | static void nvme_reset_done(struct pci_dev *pdev) |
2555 | { | |
f263fbb8 LT |
2556 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
2557 | nvme_reset_ctrl(&dev->ctrl); | |
f0d54a54 KB |
2558 | } |
2559 | ||
09ece142 KB |
2560 | static void nvme_shutdown(struct pci_dev *pdev) |
2561 | { | |
2562 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2563 | nvme_dev_disable(dev, true); |
09ece142 KB |
2564 | } |
2565 | ||
f58944e2 KB |
2566 | /* |
2567 | * The driver's remove may be called on a device in a partially initialized | |
2568 | * state. This function must not have any dependencies on the device state in | |
2569 | * order to proceed. | |
2570 | */ | |
8d85fce7 | 2571 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2572 | { |
2573 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2574 | |
bb8d261e CH |
2575 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2576 | ||
d86c4d8e | 2577 | cancel_work_sync(&dev->ctrl.reset_work); |
9a6b9458 | 2578 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2579 | |
6db28eda | 2580 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2581 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2582 | nvme_dev_disable(dev, false); |
2583 | } | |
0ff9d4e1 | 2584 | |
d86c4d8e | 2585 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
2586 | nvme_stop_ctrl(&dev->ctrl); |
2587 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 2588 | nvme_dev_disable(dev, true); |
87ad72a5 | 2589 | nvme_free_host_mem(dev); |
a4aea562 | 2590 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2591 | nvme_free_queues(dev, 0); |
d09f2b45 | 2592 | nvme_uninit_ctrl(&dev->ctrl); |
9a6b9458 | 2593 | nvme_release_prp_pools(dev); |
b00a726a | 2594 | nvme_dev_unmap(dev); |
1673f1f0 | 2595 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2596 | } |
2597 | ||
13880f5b KB |
2598 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2599 | { | |
2600 | int ret = 0; | |
2601 | ||
2602 | if (numvfs == 0) { | |
2603 | if (pci_vfs_assigned(pdev)) { | |
2604 | dev_warn(&pdev->dev, | |
2605 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2606 | return -EPERM; | |
2607 | } | |
2608 | pci_disable_sriov(pdev); | |
2609 | return 0; | |
2610 | } | |
2611 | ||
2612 | ret = pci_enable_sriov(pdev, numvfs); | |
2613 | return ret ? ret : numvfs; | |
2614 | } | |
2615 | ||
671a6018 | 2616 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2617 | static int nvme_suspend(struct device *dev) |
2618 | { | |
2619 | struct pci_dev *pdev = to_pci_dev(dev); | |
2620 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2621 | ||
a1894ef1 | 2622 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2623 | return 0; |
2624 | } | |
2625 | ||
2626 | static int nvme_resume(struct device *dev) | |
2627 | { | |
2628 | struct pci_dev *pdev = to_pci_dev(dev); | |
2629 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2630 | |
d86c4d8e | 2631 | nvme_reset_ctrl(&ndev->ctrl); |
9a6b9458 | 2632 | return 0; |
cd638946 | 2633 | } |
671a6018 | 2634 | #endif |
cd638946 KB |
2635 | |
2636 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2637 | |
a0a3408e KB |
2638 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2639 | pci_channel_state_t state) | |
2640 | { | |
2641 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2642 | ||
2643 | /* | |
2644 | * A frozen channel requires a reset. When detected, this method will | |
2645 | * shutdown the controller to quiesce. The controller will be restarted | |
2646 | * after the slot reset through driver's slot_reset callback. | |
2647 | */ | |
a0a3408e KB |
2648 | switch (state) { |
2649 | case pci_channel_io_normal: | |
2650 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2651 | case pci_channel_io_frozen: | |
d011fb31 KB |
2652 | dev_warn(dev->ctrl.device, |
2653 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2654 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2655 | return PCI_ERS_RESULT_NEED_RESET; |
2656 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2657 | dev_warn(dev->ctrl.device, |
2658 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2659 | return PCI_ERS_RESULT_DISCONNECT; |
2660 | } | |
2661 | return PCI_ERS_RESULT_NEED_RESET; | |
2662 | } | |
2663 | ||
2664 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2665 | { | |
2666 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2667 | ||
1b3c47c1 | 2668 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2669 | pci_restore_state(pdev); |
d86c4d8e | 2670 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
2671 | return PCI_ERS_RESULT_RECOVERED; |
2672 | } | |
2673 | ||
2674 | static void nvme_error_resume(struct pci_dev *pdev) | |
2675 | { | |
baf41196 KB |
2676 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
2677 | ||
2678 | flush_work(&dev->ctrl.reset_work); | |
a0a3408e KB |
2679 | pci_cleanup_aer_uncorrect_error_status(pdev); |
2680 | } | |
2681 | ||
1d352035 | 2682 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2683 | .error_detected = nvme_error_detected, |
b60503ba MW |
2684 | .slot_reset = nvme_slot_reset, |
2685 | .resume = nvme_error_resume, | |
775755ed CH |
2686 | .reset_prepare = nvme_reset_prepare, |
2687 | .reset_done = nvme_reset_done, | |
b60503ba MW |
2688 | }; |
2689 | ||
6eb0d698 | 2690 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2691 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2692 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2693 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2694 | { PCI_VDEVICE(INTEL, 0x0a53), |
2695 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2696 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2697 | { PCI_VDEVICE(INTEL, 0x0a54), |
2698 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2699 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
f99cb7af DWF |
2700 | { PCI_VDEVICE(INTEL, 0x0a55), |
2701 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2702 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 | 2703 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
5750cb1c JA |
2704 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | |
2705 | NVME_QUIRK_MEDIUM_PRIO_SQ }, | |
a676e05d | 2706 | { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ |
af9e76ef | 2707 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, |
540c801c KB |
2708 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2709 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2710 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2711 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
8c97eecc JL |
2712 | { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ |
2713 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2714 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2715 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
2716 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
2717 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
2718 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
2719 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
608cc4b1 CH |
2720 | { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ |
2721 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
2722 | { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ | |
2723 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
705e8934 WX |
2724 | { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ |
2725 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
b60503ba | 2726 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2727 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2728 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2729 | { 0, } |
2730 | }; | |
2731 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2732 | ||
2733 | static struct pci_driver nvme_driver = { | |
2734 | .name = "nvme", | |
2735 | .id_table = nvme_id_table, | |
2736 | .probe = nvme_probe, | |
8d85fce7 | 2737 | .remove = nvme_remove, |
09ece142 | 2738 | .shutdown = nvme_shutdown, |
cd638946 KB |
2739 | .driver = { |
2740 | .pm = &nvme_dev_pm_ops, | |
2741 | }, | |
13880f5b | 2742 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2743 | .err_handler = &nvme_err_handler, |
2744 | }; | |
2745 | ||
2746 | static int __init nvme_init(void) | |
2747 | { | |
9a6327d2 | 2748 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
2749 | } |
2750 | ||
2751 | static void __exit nvme_exit(void) | |
2752 | { | |
2753 | pci_unregister_driver(&nvme_driver); | |
03e0f3a6 | 2754 | flush_workqueue(nvme_wq); |
21bd78bc | 2755 | _nvme_check_size(); |
b60503ba MW |
2756 | } |
2757 | ||
2758 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2759 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2760 | MODULE_VERSION("1.0"); |
b60503ba MW |
2761 | module_init(nvme_init); |
2762 | module_exit(nvme_exit); |