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KVM: VMX: Check the posted interrupt capability
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
01e439be
YZ		 87static bool __read_mostly enable_apicv;
88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
801d3424
NHE		 90/*
91 * If nested=1, nested virtualization is supported, i.e., guests may use
92 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
93 * use VMX instructions.
94 */
476bc001 95static bool __read_mostly nested = 0;
801d3424
NHE		 96module_param(nested, bool, S_IRUGO);
97
5037878e
GN		 98#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
99#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
83287ea4
AK		 130extern const ulong vmx_return;
131
8bf00a52 132#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 133#define VMCS02_POOL_SIZE 1
61d2ef2c 134
a2fa3e9f
GH		 135struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139};
140
d462b819
NHE		 141/*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151};
152
26bb0981
AK		 153struct shared_msr_entry {
154 unsigned index;
155 u64 data;
d5696725 156 u64 mask;
26bb0981
AK		 157};
158
a9d30f33
NHE		 159/*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
22bd0358 172typedef u64 natural_width;
a9d30f33
NHE		 173struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
22bd0358 179
27d6c865
NHE		 180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
22bd0358
NHE		 183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
0238ea91
JK		 302 u32 vmx_preemption_timer_value;
303 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 304 u16 virtual_processor_id;
305 u16 guest_es_selector;
306 u16 guest_cs_selector;
307 u16 guest_ss_selector;
308 u16 guest_ds_selector;
309 u16 guest_fs_selector;
310 u16 guest_gs_selector;
311 u16 guest_ldtr_selector;
312 u16 guest_tr_selector;
313 u16 host_es_selector;
314 u16 host_cs_selector;
315 u16 host_ss_selector;
316 u16 host_ds_selector;
317 u16 host_fs_selector;
318 u16 host_gs_selector;
319 u16 host_tr_selector;
a9d30f33
NHE		 320};
321
322/*
323 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
324 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
325 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 */
327#define VMCS12_REVISION 0x11e57ed0
328
329/*
330 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
331 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
332 * current implementation, 4K are reserved to avoid future complications.
333 */
334#define VMCS12_SIZE 0x1000
335
ff2f6fe9
NHE		 336/* Used to remember the last vmcs02 used for some recently used vmcs12s */
337struct vmcs02_list {
338 struct list_head list;
339 gpa_t vmptr;
340 struct loaded_vmcs vmcs02;
341};
342
ec378aee
NHE		 343/*
344 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
345 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 */
347struct nested_vmx {
348 /* Has the level1 guest done vmxon? */
349 bool vmxon;
a9d30f33
NHE		 350
351 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 gpa_t current_vmptr;
353 /* The host-usable pointer to the above */
354 struct page *current_vmcs12_page;
355 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 356
357 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
358 struct list_head vmcs02_pool;
359 int vmcs02_num;
fe3ef05c 360 u64 vmcs01_tsc_offset;
644d711a
NHE		 361 /* L2 must run next, and mustn't decide to exit to L1. */
362 bool nested_run_pending;
fe3ef05c
NHE		 363 /*
364 * Guest pages referred to in vmcs02 with host-physical pointers, so
365 * we must keep them pinned while L2 runs.
366 */
367 struct page *apic_access_page;
ec378aee
NHE		 368};
369
01e439be
YZ		 370#define POSTED_INTR_ON 0
371/* Posted-Interrupt Descriptor */
372struct pi_desc {
373 u32 pir[8]; /* Posted interrupt requested */
374 u32 control; /* bit 0 of control is outstanding notification bit */
375 u32 rsvd[7];
376} __aligned(64);
377
a2fa3e9f 378struct vcpu_vmx {
fb3f0f51 379 struct kvm_vcpu vcpu;
313dbd49 380 unsigned long host_rsp;
29bd8a78 381 u8 fail;
69c73028 382 u8 cpl;
9d58b931 383 bool nmi_known_unmasked;
51aa01d1 384 u32 exit_intr_info;
1155f76a 385 u32 idt_vectoring_info;
6de12732 386 ulong rflags;
26bb0981 387 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 388 int nmsrs;
389 int save_nmsrs;
a547c6db 390 unsigned long host_idt_base;
a2fa3e9f 391#ifdef CONFIG_X86_64
44ea2b17
AK		 392 u64 msr_host_kernel_gs_base;
393 u64 msr_guest_kernel_gs_base;
a2fa3e9f 394#endif
d462b819
NHE		 395 /*
396 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
397 * non-nested (L1) guest, it always points to vmcs01. For a nested
398 * guest (L2), it points to a different VMCS.
399 */
400 struct loaded_vmcs vmcs01;
401 struct loaded_vmcs *loaded_vmcs;
402 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 403 struct msr_autoload {
404 unsigned nr;
405 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
406 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
407 } msr_autoload;
a2fa3e9f
GH		 408 struct {
409 int loaded;
410 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 411#ifdef CONFIG_X86_64
412 u16 ds_sel, es_sel;
413#endif
152d3f2f
LV		 414 int gs_ldt_reload_needed;
415 int fs_reload_needed;
d77c26fc 416 } host_state;
9c8cba37 417 struct {
7ffd92c5 418 int vm86_active;
78ac8b47 419 ulong save_rflags;
f5f7b2fe
AK		 420 struct kvm_segment segs[8];
421 } rmode;
422 struct {
423 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 424 struct kvm_save_segment {
425 u16 selector;
426 unsigned long base;
427 u32 limit;
428 u32 ar;
f5f7b2fe 429 } seg[8];
2fb92db1 430 } segment_cache;
2384d2b3 431 int vpid;
04fa4d32 432 bool emulation_required;
3b86cd99
JK		 433
434 /* Support for vnmi-less CPUs */
435 int soft_vnmi_blocked;
436 ktime_t entry_time;
437 s64 vnmi_blocked_time;
a0861c02 438 u32 exit_reason;
4e47c7a6
SY		 439
440 bool rdtscp_enabled;
ec378aee 441
01e439be
YZ		 442 /* Posted interrupt descriptor */
443 struct pi_desc pi_desc;
444
ec378aee
NHE		 445 /* Support for a guest hypervisor (nested VMX) */
446 struct nested_vmx nested;
a2fa3e9f
GH		 447};
448
2fb92db1
AK		 449enum segment_cache_field {
450 SEG_FIELD_SEL = 0,
451 SEG_FIELD_BASE = 1,
452 SEG_FIELD_LIMIT = 2,
453 SEG_FIELD_AR = 3,
454
455 SEG_FIELD_NR = 4
456};
457
a2fa3e9f
GH		 458static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
459{
fb3f0f51 460 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 461}
462
22bd0358
NHE		 463#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
464#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
465#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
466 [number##_HIGH] = VMCS12_OFFSET(name)+4
467
772e0318 468static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 469 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
470 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
471 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
472 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
473 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
474 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
475 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
476 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
477 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
478 FIELD(HOST_ES_SELECTOR, host_es_selector),
479 FIELD(HOST_CS_SELECTOR, host_cs_selector),
480 FIELD(HOST_SS_SELECTOR, host_ss_selector),
481 FIELD(HOST_DS_SELECTOR, host_ds_selector),
482 FIELD(HOST_FS_SELECTOR, host_fs_selector),
483 FIELD(HOST_GS_SELECTOR, host_gs_selector),
484 FIELD(HOST_TR_SELECTOR, host_tr_selector),
485 FIELD64(IO_BITMAP_A, io_bitmap_a),
486 FIELD64(IO_BITMAP_B, io_bitmap_b),
487 FIELD64(MSR_BITMAP, msr_bitmap),
488 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
489 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
490 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
491 FIELD64(TSC_OFFSET, tsc_offset),
492 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
493 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
494 FIELD64(EPT_POINTER, ept_pointer),
495 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
496 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
497 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
498 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
499 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
500 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
501 FIELD64(GUEST_PDPTR0, guest_pdptr0),
502 FIELD64(GUEST_PDPTR1, guest_pdptr1),
503 FIELD64(GUEST_PDPTR2, guest_pdptr2),
504 FIELD64(GUEST_PDPTR3, guest_pdptr3),
505 FIELD64(HOST_IA32_PAT, host_ia32_pat),
506 FIELD64(HOST_IA32_EFER, host_ia32_efer),
507 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
508 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
509 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
510 FIELD(EXCEPTION_BITMAP, exception_bitmap),
511 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
512 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
513 FIELD(CR3_TARGET_COUNT, cr3_target_count),
514 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
515 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
516 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
517 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
518 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
519 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
520 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
521 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
522 FIELD(TPR_THRESHOLD, tpr_threshold),
523 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
524 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
525 FIELD(VM_EXIT_REASON, vm_exit_reason),
526 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
527 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
528 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
529 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
530 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
531 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
532 FIELD(GUEST_ES_LIMIT, guest_es_limit),
533 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
534 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
535 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
536 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
537 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
538 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
539 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
540 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
541 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
542 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
543 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
544 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
545 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
546 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
547 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
548 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
549 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
550 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
551 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
552 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
553 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 554 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 555 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
556 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
557 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
558 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
559 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
560 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
561 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
562 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
563 FIELD(EXIT_QUALIFICATION, exit_qualification),
564 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
565 FIELD(GUEST_CR0, guest_cr0),
566 FIELD(GUEST_CR3, guest_cr3),
567 FIELD(GUEST_CR4, guest_cr4),
568 FIELD(GUEST_ES_BASE, guest_es_base),
569 FIELD(GUEST_CS_BASE, guest_cs_base),
570 FIELD(GUEST_SS_BASE, guest_ss_base),
571 FIELD(GUEST_DS_BASE, guest_ds_base),
572 FIELD(GUEST_FS_BASE, guest_fs_base),
573 FIELD(GUEST_GS_BASE, guest_gs_base),
574 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
575 FIELD(GUEST_TR_BASE, guest_tr_base),
576 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
577 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
578 FIELD(GUEST_DR7, guest_dr7),
579 FIELD(GUEST_RSP, guest_rsp),
580 FIELD(GUEST_RIP, guest_rip),
581 FIELD(GUEST_RFLAGS, guest_rflags),
582 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
583 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
584 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
585 FIELD(HOST_CR0, host_cr0),
586 FIELD(HOST_CR3, host_cr3),
587 FIELD(HOST_CR4, host_cr4),
588 FIELD(HOST_FS_BASE, host_fs_base),
589 FIELD(HOST_GS_BASE, host_gs_base),
590 FIELD(HOST_TR_BASE, host_tr_base),
591 FIELD(HOST_GDTR_BASE, host_gdtr_base),
592 FIELD(HOST_IDTR_BASE, host_idtr_base),
593 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
594 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
595 FIELD(HOST_RSP, host_rsp),
596 FIELD(HOST_RIP, host_rip),
597};
598static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
599
600static inline short vmcs_field_to_offset(unsigned long field)
601{
602 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
603 return -1;
604 return vmcs_field_to_offset_table[field];
605}
606
a9d30f33
NHE		 607static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
608{
609 return to_vmx(vcpu)->nested.current_vmcs12;
610}
611
612static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
613{
614 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 615 if (is_error_page(page))
a9d30f33 616 return NULL;
32cad84f 617
a9d30f33
NHE		 618 return page;
619}
620
621static void nested_release_page(struct page *page)
622{
623 kvm_release_page_dirty(page);
624}
625
626static void nested_release_page_clean(struct page *page)
627{
628 kvm_release_page_clean(page);
629}
630
4e1096d2 631static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 632static void kvm_cpu_vmxon(u64 addr);
633static void kvm_cpu_vmxoff(void);
aff48baa 634static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 635static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 636static void vmx_set_segment(struct kvm_vcpu *vcpu,
637 struct kvm_segment *var, int seg);
638static void vmx_get_segment(struct kvm_vcpu *vcpu,
639 struct kvm_segment *var, int seg);
d99e4152
GN		 640static bool guest_state_valid(struct kvm_vcpu *vcpu);
641static u32 vmx_segment_access_rights(struct kvm_segment *var);
75880a01 642
6aa8b732
AK		 643static DEFINE_PER_CPU(struct vmcs *, vmxarea);
644static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 645/*
646 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
647 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
648 */
649static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 650static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 651
3e7c73e9
AK		 652static unsigned long *vmx_io_bitmap_a;
653static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 654static unsigned long *vmx_msr_bitmap_legacy;
655static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 656static unsigned long *vmx_msr_bitmap_legacy_x2apic;
657static unsigned long *vmx_msr_bitmap_longmode_x2apic;
fdef3ad1 658
110312c8 659static bool cpu_has_load_ia32_efer;
8bf00a52 660static bool cpu_has_load_perf_global_ctrl;
110312c8 661
2384d2b3
SY		 662static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
663static DEFINE_SPINLOCK(vmx_vpid_lock);
664
1c3d14fe 665static struct vmcs_config {
6aa8b732
AK		 666 int size;
667 int order;
668 u32 revision_id;
1c3d14fe
YS		 669 u32 pin_based_exec_ctrl;
670 u32 cpu_based_exec_ctrl;
f78e0e2e 671 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 672 u32 vmexit_ctrl;
673 u32 vmentry_ctrl;
674} vmcs_config;
6aa8b732 675
efff9e53 676static struct vmx_capability {
d56f546d
SY		 677 u32 ept;
678 u32 vpid;
679} vmx_capability;
680
6aa8b732
AK		 681#define VMX_SEGMENT_FIELD(seg) \
682 [VCPU_SREG_##seg] = { \
683 .selector = GUEST_##seg##_SELECTOR, \
684 .base = GUEST_##seg##_BASE, \
685 .limit = GUEST_##seg##_LIMIT, \
686 .ar_bytes = GUEST_##seg##_AR_BYTES, \
687 }
688
772e0318 689static const struct kvm_vmx_segment_field {
6aa8b732
AK		 690 unsigned selector;
691 unsigned base;
692 unsigned limit;
693 unsigned ar_bytes;
694} kvm_vmx_segment_fields[] = {
695 VMX_SEGMENT_FIELD(CS),
696 VMX_SEGMENT_FIELD(DS),
697 VMX_SEGMENT_FIELD(ES),
698 VMX_SEGMENT_FIELD(FS),
699 VMX_SEGMENT_FIELD(GS),
700 VMX_SEGMENT_FIELD(SS),
701 VMX_SEGMENT_FIELD(TR),
702 VMX_SEGMENT_FIELD(LDTR),
703};
704
26bb0981
AK		 705static u64 host_efer;
706
6de4f3ad
AK		 707static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
708
4d56c8a7 709/*
8c06585d 710 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 711 * away by decrementing the array size.
712 */
6aa8b732 713static const u32 vmx_msr_index[] = {
05b3e0c2 714#ifdef CONFIG_X86_64
44ea2b17 715 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 716#endif
8c06585d 717 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 718};
9d8f549d 719#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 720
31299944 721static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 722{
723 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
724 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 725 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 726}
727
31299944 728static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 729{
730 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
731 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 732 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 733}
734
31299944 735static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 736{
737 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
738 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 739 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 740}
741
31299944 742static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 743{
744 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
745 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
746}
747
31299944 748static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 749{
750 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
751 INTR_INFO_VALID_MASK)) ==
752 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
753}
754
31299944 755static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 756{
04547156 757 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 758}
759
31299944 760static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 761{
04547156 762 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 763}
764
31299944 765static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 766{
04547156 767 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 768}
769
31299944 770static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 771{
04547156
SY		 772 return vmcs_config.cpu_based_exec_ctrl &
773 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 774}
775
774ead3a 776static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 777{
04547156
SY		 778 return vmcs_config.cpu_based_2nd_exec_ctrl &
779 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
780}
781
8d14695f
YZ		 782static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
783{
784 return vmcs_config.cpu_based_2nd_exec_ctrl &
785 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
786}
787
83d4c286
YZ		 788static inline bool cpu_has_vmx_apic_register_virt(void)
789{
790 return vmcs_config.cpu_based_2nd_exec_ctrl &
791 SECONDARY_EXEC_APIC_REGISTER_VIRT;
792}
793
c7c9c56c
YZ		 794static inline bool cpu_has_vmx_virtual_intr_delivery(void)
795{
796 return vmcs_config.cpu_based_2nd_exec_ctrl &
797 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
798}
799
01e439be
YZ		 800static inline bool cpu_has_vmx_posted_intr(void)
801{
802 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
803}
804
805static inline bool cpu_has_vmx_apicv(void)
806{
807 return cpu_has_vmx_apic_register_virt() &&
808 cpu_has_vmx_virtual_intr_delivery() &&
809 cpu_has_vmx_posted_intr();
810}
811
04547156
SY		 812static inline bool cpu_has_vmx_flexpriority(void)
813{
814 return cpu_has_vmx_tpr_shadow() &&
815 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 816}
817
e799794e
MT		 818static inline bool cpu_has_vmx_ept_execute_only(void)
819{
31299944 820 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 821}
822
823static inline bool cpu_has_vmx_eptp_uncacheable(void)
824{
31299944 825 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 826}
827
828static inline bool cpu_has_vmx_eptp_writeback(void)
829{
31299944 830 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 831}
832
833static inline bool cpu_has_vmx_ept_2m_page(void)
834{
31299944 835 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 836}
837
878403b7
SY		 838static inline bool cpu_has_vmx_ept_1g_page(void)
839{
31299944 840 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 841}
842
4bc9b982
SY		 843static inline bool cpu_has_vmx_ept_4levels(void)
844{
845 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
846}
847
83c3a331
XH		 848static inline bool cpu_has_vmx_ept_ad_bits(void)
849{
850 return vmx_capability.ept & VMX_EPT_AD_BIT;
851}
852
31299944 853static inline bool cpu_has_vmx_invept_context(void)
d56f546d 854{
31299944 855 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 856}
857
31299944 858static inline bool cpu_has_vmx_invept_global(void)
d56f546d 859{
31299944 860 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 861}
862
518c8aee
GJ		 863static inline bool cpu_has_vmx_invvpid_single(void)
864{
865 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
866}
867
b9d762fa
GJ		 868static inline bool cpu_has_vmx_invvpid_global(void)
869{
870 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
871}
872
31299944 873static inline bool cpu_has_vmx_ept(void)
d56f546d 874{
04547156
SY		 875 return vmcs_config.cpu_based_2nd_exec_ctrl &
876 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 877}
878
31299944 879static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 880{
881 return vmcs_config.cpu_based_2nd_exec_ctrl &
882 SECONDARY_EXEC_UNRESTRICTED_GUEST;
883}
884
31299944 885static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 886{
887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
889}
890
31299944 891static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 892{
6d3e435e 893 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 894}
895
31299944 896static inline bool cpu_has_vmx_vpid(void)
2384d2b3 897{
04547156
SY		 898 return vmcs_config.cpu_based_2nd_exec_ctrl &
899 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 900}
901
31299944 902static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 903{
904 return vmcs_config.cpu_based_2nd_exec_ctrl &
905 SECONDARY_EXEC_RDTSCP;
906}
907
ad756a16
MJ		 908static inline bool cpu_has_vmx_invpcid(void)
909{
910 return vmcs_config.cpu_based_2nd_exec_ctrl &
911 SECONDARY_EXEC_ENABLE_INVPCID;
912}
913
31299944 914static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 915{
916 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
917}
918
f5f48ee1
SY		 919static inline bool cpu_has_vmx_wbinvd_exit(void)
920{
921 return vmcs_config.cpu_based_2nd_exec_ctrl &
922 SECONDARY_EXEC_WBINVD_EXITING;
923}
924
04547156
SY		 925static inline bool report_flexpriority(void)
926{
927 return flexpriority_enabled;
928}
929
fe3ef05c
NHE		 930static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
931{
932 return vmcs12->cpu_based_vm_exec_control & bit;
933}
934
935static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
936{
937 return (vmcs12->cpu_based_vm_exec_control &
938 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
939 (vmcs12->secondary_vm_exec_control & bit);
940}
941
644d711a
NHE		 942static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
943 struct kvm_vcpu *vcpu)
944{
945 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
946}
947
948static inline bool is_exception(u32 intr_info)
949{
950 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
951 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
952}
953
954static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 955static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
956 struct vmcs12 *vmcs12,
957 u32 reason, unsigned long qualification);
958
8b9cf98c 959static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 960{
961 int i;
962
a2fa3e9f 963 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 964 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 965 return i;
966 return -1;
967}
968
2384d2b3
SY		 969static inline void __invvpid(int ext, u16 vpid, gva_t gva)
970{
971 struct {
972 u64 vpid : 16;
973 u64 rsvd : 48;
974 u64 gva;
975 } operand = { vpid, 0, gva };
976
4ecac3fd 977 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 978 /* CF==1 or ZF==1 --> rc = -1 */
979 "; ja 1f ; ud2 ; 1:"
980 : : "a"(&operand), "c"(ext) : "cc", "memory");
981}
982
1439442c
SY		 983static inline void __invept(int ext, u64 eptp, gpa_t gpa)
984{
985 struct {
986 u64 eptp, gpa;
987 } operand = {eptp, gpa};
988
4ecac3fd 989 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 990 /* CF==1 or ZF==1 --> rc = -1 */
991 "; ja 1f ; ud2 ; 1:\n"
992 : : "a" (&operand), "c" (ext) : "cc", "memory");
993}
994
26bb0981 995static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 996{
997 int i;
998
8b9cf98c 999 i = __find_msr_index(vmx, msr);
a75beee6 1000 if (i >= 0)
a2fa3e9f 1001 return &vmx->guest_msrs[i];
8b6d44c7 1002 return NULL;
7725f0ba
AK		 1003}
1004
6aa8b732
AK		 1005static void vmcs_clear(struct vmcs *vmcs)
1006{
1007 u64 phys_addr = __pa(vmcs);
1008 u8 error;
1009
4ecac3fd 1010 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1011 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1012 : "cc", "memory");
1013 if (error)
1014 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1015 vmcs, phys_addr);
1016}
1017
d462b819
NHE		 1018static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1019{
1020 vmcs_clear(loaded_vmcs->vmcs);
1021 loaded_vmcs->cpu = -1;
1022 loaded_vmcs->launched = 0;
1023}
1024
7725b894
DX		 1025static void vmcs_load(struct vmcs *vmcs)
1026{
1027 u64 phys_addr = __pa(vmcs);
1028 u8 error;
1029
1030 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1031 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1032 : "cc", "memory");
1033 if (error)
2844d849 1034 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1035 vmcs, phys_addr);
1036}
1037
8f536b76
ZY		 1038#ifdef CONFIG_KEXEC
1039/*
1040 * This bitmap is used to indicate whether the vmclear
1041 * operation is enabled on all cpus. All disabled by
1042 * default.
1043 */
1044static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1045
1046static inline void crash_enable_local_vmclear(int cpu)
1047{
1048 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1049}
1050
1051static inline void crash_disable_local_vmclear(int cpu)
1052{
1053 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1054}
1055
1056static inline int crash_local_vmclear_enabled(int cpu)
1057{
1058 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1059}
1060
1061static void crash_vmclear_local_loaded_vmcss(void)
1062{
1063 int cpu = raw_smp_processor_id();
1064 struct loaded_vmcs *v;
1065
1066 if (!crash_local_vmclear_enabled(cpu))
1067 return;
1068
1069 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1070 loaded_vmcss_on_cpu_link)
1071 vmcs_clear(v->vmcs);
1072}
1073#else
1074static inline void crash_enable_local_vmclear(int cpu) { }
1075static inline void crash_disable_local_vmclear(int cpu) { }
1076#endif /* CONFIG_KEXEC */
1077
d462b819 1078static void __loaded_vmcs_clear(void *arg)
6aa8b732 1079{
d462b819 1080 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1081 int cpu = raw_smp_processor_id();
6aa8b732 1082
d462b819
NHE		 1083 if (loaded_vmcs->cpu != cpu)
1084 return; /* vcpu migration can race with cpu offline */
1085 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1086 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1087 crash_disable_local_vmclear(cpu);
d462b819 1088 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1089
1090 /*
1091 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1092 * is before setting loaded_vmcs->vcpu to -1 which is done in
1093 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1094 * then adds the vmcs into percpu list before it is deleted.
1095 */
1096 smp_wmb();
1097
d462b819 1098 loaded_vmcs_init(loaded_vmcs);
8f536b76 1099 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1100}
1101
d462b819 1102static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1103{
e6c7d321
XG		 1104 int cpu = loaded_vmcs->cpu;
1105
1106 if (cpu != -1)
1107 smp_call_function_single(cpu,
1108 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1109}
1110
1760dd49 1111static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1112{
1113 if (vmx->vpid == 0)
1114 return;
1115
518c8aee
GJ		 1116 if (cpu_has_vmx_invvpid_single())
1117 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1118}
1119
b9d762fa
GJ		 1120static inline void vpid_sync_vcpu_global(void)
1121{
1122 if (cpu_has_vmx_invvpid_global())
1123 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1124}
1125
1126static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1127{
1128 if (cpu_has_vmx_invvpid_single())
1760dd49 1129 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1130 else
1131 vpid_sync_vcpu_global();
1132}
1133
1439442c
SY		 1134static inline void ept_sync_global(void)
1135{
1136 if (cpu_has_vmx_invept_global())
1137 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1138}
1139
1140static inline void ept_sync_context(u64 eptp)
1141{
089d034e 1142 if (enable_ept) {
1439442c
SY		 1143 if (cpu_has_vmx_invept_context())
1144 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1145 else
1146 ept_sync_global();
1147 }
1148}
1149
96304217 1150static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1151{
5e520e62 1152 unsigned long value;
6aa8b732 1153
5e520e62
AK		 1154 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1155 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1156 return value;
1157}
1158
96304217 1159static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1160{
1161 return vmcs_readl(field);
1162}
1163
96304217 1164static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1165{
1166 return vmcs_readl(field);
1167}
1168
96304217 1169static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1170{
05b3e0c2 1171#ifdef CONFIG_X86_64
6aa8b732
AK		 1172 return vmcs_readl(field);
1173#else
1174 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1175#endif
1176}
1177
e52de1b8
AK		 1178static noinline void vmwrite_error(unsigned long field, unsigned long value)
1179{
1180 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1181 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1182 dump_stack();
1183}
1184
6aa8b732
AK		 1185static void vmcs_writel(unsigned long field, unsigned long value)
1186{
1187 u8 error;
1188
4ecac3fd 1189 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1190 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1191 if (unlikely(error))
1192 vmwrite_error(field, value);
6aa8b732
AK		 1193}
1194
1195static void vmcs_write16(unsigned long field, u16 value)
1196{
1197 vmcs_writel(field, value);
1198}
1199
1200static void vmcs_write32(unsigned long field, u32 value)
1201{
1202 vmcs_writel(field, value);
1203}
1204
1205static void vmcs_write64(unsigned long field, u64 value)
1206{
6aa8b732 1207 vmcs_writel(field, value);
7682f2d0 1208#ifndef CONFIG_X86_64
6aa8b732
AK		 1209 asm volatile ("");
1210 vmcs_writel(field+1, value >> 32);
1211#endif
1212}
1213
2ab455cc
AL		 1214static void vmcs_clear_bits(unsigned long field, u32 mask)
1215{
1216 vmcs_writel(field, vmcs_readl(field) & ~mask);
1217}
1218
1219static void vmcs_set_bits(unsigned long field, u32 mask)
1220{
1221 vmcs_writel(field, vmcs_readl(field) | mask);
1222}
1223
2fb92db1
AK		 1224static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1225{
1226 vmx->segment_cache.bitmask = 0;
1227}
1228
1229static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1230 unsigned field)
1231{
1232 bool ret;
1233 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1234
1235 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1236 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1237 vmx->segment_cache.bitmask = 0;
1238 }
1239 ret = vmx->segment_cache.bitmask & mask;
1240 vmx->segment_cache.bitmask |= mask;
1241 return ret;
1242}
1243
1244static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1245{
1246 u16 *p = &vmx->segment_cache.seg[seg].selector;
1247
1248 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1249 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1250 return *p;
1251}
1252
1253static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1254{
1255 ulong *p = &vmx->segment_cache.seg[seg].base;
1256
1257 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1258 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1259 return *p;
1260}
1261
1262static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1263{
1264 u32 *p = &vmx->segment_cache.seg[seg].limit;
1265
1266 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1267 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1268 return *p;
1269}
1270
1271static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1272{
1273 u32 *p = &vmx->segment_cache.seg[seg].ar;
1274
1275 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1276 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1277 return *p;
1278}
1279
abd3f2d6
AK		 1280static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1281{
1282 u32 eb;
1283
fd7373cc
JK		 1284 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1285 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1286 if ((vcpu->guest_debug &
1287 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1288 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1289 eb |= 1u << BP_VECTOR;
7ffd92c5 1290 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1291 eb = ~0;
089d034e 1292 if (enable_ept)
1439442c 1293 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1294 if (vcpu->fpu_active)
1295 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1296
1297 /* When we are running a nested L2 guest and L1 specified for it a
1298 * certain exception bitmap, we must trap the same exceptions and pass
1299 * them to L1. When running L2, we will only handle the exceptions
1300 * specified above if L1 did not want them.
1301 */
1302 if (is_guest_mode(vcpu))
1303 eb |= get_vmcs12(vcpu)->exception_bitmap;
1304
abd3f2d6
AK		 1305 vmcs_write32(EXCEPTION_BITMAP, eb);
1306}
1307
8bf00a52
GN		 1308static void clear_atomic_switch_msr_special(unsigned long entry,
1309 unsigned long exit)
1310{
1311 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1312 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1313}
1314
61d2ef2c
AK		 1315static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1316{
1317 unsigned i;
1318 struct msr_autoload *m = &vmx->msr_autoload;
1319
8bf00a52
GN		 1320 switch (msr) {
1321 case MSR_EFER:
1322 if (cpu_has_load_ia32_efer) {
1323 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1324 VM_EXIT_LOAD_IA32_EFER);
1325 return;
1326 }
1327 break;
1328 case MSR_CORE_PERF_GLOBAL_CTRL:
1329 if (cpu_has_load_perf_global_ctrl) {
1330 clear_atomic_switch_msr_special(
1331 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1332 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1333 return;
1334 }
1335 break;
110312c8
AK		 1336 }
1337
61d2ef2c
AK		 1338 for (i = 0; i < m->nr; ++i)
1339 if (m->guest[i].index == msr)
1340 break;
1341
1342 if (i == m->nr)
1343 return;
1344 --m->nr;
1345 m->guest[i] = m->guest[m->nr];
1346 m->host[i] = m->host[m->nr];
1347 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1348 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1349}
1350
8bf00a52
GN		 1351static void add_atomic_switch_msr_special(unsigned long entry,
1352 unsigned long exit, unsigned long guest_val_vmcs,
1353 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1354{
1355 vmcs_write64(guest_val_vmcs, guest_val);
1356 vmcs_write64(host_val_vmcs, host_val);
1357 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1358 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1359}
1360
61d2ef2c
AK		 1361static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1362 u64 guest_val, u64 host_val)
1363{
1364 unsigned i;
1365 struct msr_autoload *m = &vmx->msr_autoload;
1366
8bf00a52
GN		 1367 switch (msr) {
1368 case MSR_EFER:
1369 if (cpu_has_load_ia32_efer) {
1370 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1371 VM_EXIT_LOAD_IA32_EFER,
1372 GUEST_IA32_EFER,
1373 HOST_IA32_EFER,
1374 guest_val, host_val);
1375 return;
1376 }
1377 break;
1378 case MSR_CORE_PERF_GLOBAL_CTRL:
1379 if (cpu_has_load_perf_global_ctrl) {
1380 add_atomic_switch_msr_special(
1381 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1382 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1383 GUEST_IA32_PERF_GLOBAL_CTRL,
1384 HOST_IA32_PERF_GLOBAL_CTRL,
1385 guest_val, host_val);
1386 return;
1387 }
1388 break;
110312c8
AK		 1389 }
1390
61d2ef2c
AK		 1391 for (i = 0; i < m->nr; ++i)
1392 if (m->guest[i].index == msr)
1393 break;
1394
e7fc6f93
GN		 1395 if (i == NR_AUTOLOAD_MSRS) {
1396 printk_once(KERN_WARNING"Not enough mst switch entries. "
1397 "Can't add msr %x\n", msr);
1398 return;
1399 } else if (i == m->nr) {
61d2ef2c
AK		 1400 ++m->nr;
1401 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1402 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1403 }
1404
1405 m->guest[i].index = msr;
1406 m->guest[i].value = guest_val;
1407 m->host[i].index = msr;
1408 m->host[i].value = host_val;
1409}
1410
33ed6329
AK		 1411static void reload_tss(void)
1412{
33ed6329
AK		 1413 /*
1414 * VT restores TR but not its size. Useless.
1415 */
d359192f 1416 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1417 struct desc_struct *descs;
33ed6329 1418
d359192f 1419 descs = (void *)gdt->address;
33ed6329
AK		 1420 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1421 load_TR_desc();
33ed6329
AK		 1422}
1423
92c0d900 1424static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1425{
3a34a881 1426 u64 guest_efer;
51c6cf66
AK		 1427 u64 ignore_bits;
1428
f6801dff 1429 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1430
51c6cf66 1431 /*
0fa06071 1432 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1433 * outside long mode
1434 */
1435 ignore_bits = EFER_NX | EFER_SCE;
1436#ifdef CONFIG_X86_64
1437 ignore_bits |= EFER_LMA | EFER_LME;
1438 /* SCE is meaningful only in long mode on Intel */
1439 if (guest_efer & EFER_LMA)
1440 ignore_bits &= ~(u64)EFER_SCE;
1441#endif
51c6cf66
AK		 1442 guest_efer &= ~ignore_bits;
1443 guest_efer |= host_efer & ignore_bits;
26bb0981 1444 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1445 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1446
1447 clear_atomic_switch_msr(vmx, MSR_EFER);
1448 /* On ept, can't emulate nx, and must switch nx atomically */
1449 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1450 guest_efer = vmx->vcpu.arch.efer;
1451 if (!(guest_efer & EFER_LMA))
1452 guest_efer &= ~EFER_LME;
1453 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1454 return false;
1455 }
1456
26bb0981 1457 return true;
51c6cf66
AK		 1458}
1459
2d49ec72
GN		 1460static unsigned long segment_base(u16 selector)
1461{
d359192f 1462 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1463 struct desc_struct *d;
1464 unsigned long table_base;
1465 unsigned long v;
1466
1467 if (!(selector & ~3))
1468 return 0;
1469
d359192f 1470 table_base = gdt->address;
2d49ec72
GN		 1471
1472 if (selector & 4) { /* from ldt */
1473 u16 ldt_selector = kvm_read_ldt();
1474
1475 if (!(ldt_selector & ~3))
1476 return 0;
1477
1478 table_base = segment_base(ldt_selector);
1479 }
1480 d = (struct desc_struct *)(table_base + (selector & ~7));
1481 v = get_desc_base(d);
1482#ifdef CONFIG_X86_64
1483 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1484 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1485#endif
1486 return v;
1487}
1488
1489static inline unsigned long kvm_read_tr_base(void)
1490{
1491 u16 tr;
1492 asm("str %0" : "=g"(tr));
1493 return segment_base(tr);
1494}
1495
04d2cc77 1496static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1497{
04d2cc77 1498 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1499 int i;
04d2cc77 1500
a2fa3e9f 1501 if (vmx->host_state.loaded)
33ed6329
AK		 1502 return;
1503
a2fa3e9f 1504 vmx->host_state.loaded = 1;
33ed6329
AK		 1505 /*
1506 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1507 * allow segment selectors with cpl > 0 or ti == 1.
1508 */
d6e88aec 1509 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1510 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1511 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1512 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1513 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1514 vmx->host_state.fs_reload_needed = 0;
1515 } else {
33ed6329 1516 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1517 vmx->host_state.fs_reload_needed = 1;
33ed6329 1518 }
9581d442 1519 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1520 if (!(vmx->host_state.gs_sel & 7))
1521 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1522 else {
1523 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1524 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1525 }
1526
b2da15ac
AK		 1527#ifdef CONFIG_X86_64
1528 savesegment(ds, vmx->host_state.ds_sel);
1529 savesegment(es, vmx->host_state.es_sel);
1530#endif
1531
33ed6329
AK		 1532#ifdef CONFIG_X86_64
1533 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1534 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1535#else
a2fa3e9f
GH		 1536 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1537 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1538#endif
707c0874
AK		 1539
1540#ifdef CONFIG_X86_64
c8770e7b
AK		 1541 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1542 if (is_long_mode(&vmx->vcpu))
44ea2b17 1543 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1544#endif
26bb0981
AK		 1545 for (i = 0; i < vmx->save_nmsrs; ++i)
1546 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1547 vmx->guest_msrs[i].data,
1548 vmx->guest_msrs[i].mask);
33ed6329
AK		 1549}
1550
a9b21b62 1551static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1552{
a2fa3e9f 1553 if (!vmx->host_state.loaded)
33ed6329
AK		 1554 return;
1555
e1beb1d3 1556 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1557 vmx->host_state.loaded = 0;
c8770e7b
AK		 1558#ifdef CONFIG_X86_64
1559 if (is_long_mode(&vmx->vcpu))
1560 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1561#endif
152d3f2f 1562 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1563 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1564#ifdef CONFIG_X86_64
9581d442 1565 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1566#else
1567 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1568#endif
33ed6329 1569 }
0a77fe4c
AK		 1570 if (vmx->host_state.fs_reload_needed)
1571 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1572#ifdef CONFIG_X86_64
1573 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1574 loadsegment(ds, vmx->host_state.ds_sel);
1575 loadsegment(es, vmx->host_state.es_sel);
1576 }
b2da15ac 1577#endif
152d3f2f 1578 reload_tss();
44ea2b17 1579#ifdef CONFIG_X86_64
c8770e7b 1580 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1581#endif
b1a74bf8
SS		 1582 /*
1583 * If the FPU is not active (through the host task or
1584 * the guest vcpu), then restore the cr0.TS bit.
1585 */
1586 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1587 stts();
3444d7da 1588 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1589}
1590
a9b21b62
AK		 1591static void vmx_load_host_state(struct vcpu_vmx *vmx)
1592{
1593 preempt_disable();
1594 __vmx_load_host_state(vmx);
1595 preempt_enable();
1596}
1597
6aa8b732
AK		 1598/*
1599 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1600 * vcpu mutex is already taken.
1601 */
15ad7146 1602static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1603{
a2fa3e9f 1604 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1605 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1606
4610c9cc
DX		 1607 if (!vmm_exclusive)
1608 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1609 else if (vmx->loaded_vmcs->cpu != cpu)
1610 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1611
d462b819
NHE		 1612 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1613 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1614 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1615 }
1616
d462b819 1617 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1618 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1619 unsigned long sysenter_esp;
1620
a8eeb04a 1621 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1622 local_irq_disable();
8f536b76 1623 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1624
1625 /*
1626 * Read loaded_vmcs->cpu should be before fetching
1627 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1628 * See the comments in __loaded_vmcs_clear().
1629 */
1630 smp_rmb();
1631
d462b819
NHE		 1632 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1633 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1634 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1635 local_irq_enable();
1636
6aa8b732
AK		 1637 /*
1638 * Linux uses per-cpu TSS and GDT, so set these when switching
1639 * processors.
1640 */
d6e88aec 1641 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1642 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1643
1644 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1645 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1646 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1647 }
6aa8b732
AK		 1648}
1649
1650static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1651{
a9b21b62 1652 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1653 if (!vmm_exclusive) {
d462b819
NHE		 1654 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1655 vcpu->cpu = -1;
4610c9cc
DX		 1656 kvm_cpu_vmxoff();
1657 }
6aa8b732
AK		 1658}
1659
5fd86fcf
AK		 1660static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1661{
81231c69
AK		 1662 ulong cr0;
1663
5fd86fcf
AK		 1664 if (vcpu->fpu_active)
1665 return;
1666 vcpu->fpu_active = 1;
81231c69
AK		 1667 cr0 = vmcs_readl(GUEST_CR0);
1668 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1669 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1670 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1671 update_exception_bitmap(vcpu);
edcafe3c 1672 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1673 if (is_guest_mode(vcpu))
1674 vcpu->arch.cr0_guest_owned_bits &=
1675 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1676 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1677}
1678
edcafe3c
AK		 1679static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1680
fe3ef05c
NHE		 1681/*
1682 * Return the cr0 value that a nested guest would read. This is a combination
1683 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1684 * its hypervisor (cr0_read_shadow).
1685 */
1686static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1687{
1688 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1689 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1690}
1691static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1692{
1693 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1694 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1695}
1696
5fd86fcf
AK		 1697static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1698{
36cf24e0
NHE		 1699 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1700 * set this *before* calling this function.
1701 */
edcafe3c 1702 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1703 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1704 update_exception_bitmap(vcpu);
edcafe3c
AK		 1705 vcpu->arch.cr0_guest_owned_bits = 0;
1706 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1707 if (is_guest_mode(vcpu)) {
1708 /*
1709 * L1's specified read shadow might not contain the TS bit,
1710 * so now that we turned on shadowing of this bit, we need to
1711 * set this bit of the shadow. Like in nested_vmx_run we need
1712 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1713 * up-to-date here because we just decached cr0.TS (and we'll
1714 * only update vmcs12->guest_cr0 on nested exit).
1715 */
1716 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1717 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1718 (vcpu->arch.cr0 & X86_CR0_TS);
1719 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1720 } else
1721 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1722}
1723
6aa8b732
AK		 1724static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1725{
78ac8b47 1726 unsigned long rflags, save_rflags;
345dcaa8 1727
6de12732
AK		 1728 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1729 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1730 rflags = vmcs_readl(GUEST_RFLAGS);
1731 if (to_vmx(vcpu)->rmode.vm86_active) {
1732 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1733 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1734 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1735 }
1736 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1737 }
6de12732 1738 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1739}
1740
1741static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1742{
6de12732
AK		 1743 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1744 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1745 if (to_vmx(vcpu)->rmode.vm86_active) {
1746 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1747 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1748 }
6aa8b732
AK		 1749 vmcs_writel(GUEST_RFLAGS, rflags);
1750}
1751
2809f5d2
GC		 1752static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1753{
1754 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1755 int ret = 0;
1756
1757 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1758 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1759 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1760 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1761
1762 return ret & mask;
1763}
1764
1765static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1766{
1767 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1768 u32 interruptibility = interruptibility_old;
1769
1770 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1771
48005f64 1772 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1773 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1774 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1775 interruptibility |= GUEST_INTR_STATE_STI;
1776
1777 if ((interruptibility != interruptibility_old))
1778 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1779}
1780
6aa8b732
AK		 1781static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1782{
1783 unsigned long rip;
6aa8b732 1784
5fdbf976 1785 rip = kvm_rip_read(vcpu);
6aa8b732 1786 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1787 kvm_rip_write(vcpu, rip);
6aa8b732 1788
2809f5d2
GC		 1789 /* skipping an emulated instruction also counts */
1790 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1791}
1792
0b6ac343
NHE		 1793/*
1794 * KVM wants to inject page-faults which it got to the guest. This function
1795 * checks whether in a nested guest, we need to inject them to L1 or L2.
1796 * This function assumes it is called with the exit reason in vmcs02 being
1797 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1798 * is running).
1799 */
1800static int nested_pf_handled(struct kvm_vcpu *vcpu)
1801{
1802 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1803
1804 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1805 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1806 return 0;
1807
1808 nested_vmx_vmexit(vcpu);
1809 return 1;
1810}
1811
298101da 1812static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1813 bool has_error_code, u32 error_code,
1814 bool reinject)
298101da 1815{
77ab6db0 1816 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1817 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1818
0b6ac343
NHE		 1819 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1820 nested_pf_handled(vcpu))
1821 return;
1822
8ab2d2e2 1823 if (has_error_code) {
77ab6db0 1824 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1825 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1826 }
77ab6db0 1827
7ffd92c5 1828 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1829 int inc_eip = 0;
1830 if (kvm_exception_is_soft(nr))
1831 inc_eip = vcpu->arch.event_exit_inst_len;
1832 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1833 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1834 return;
1835 }
1836
66fd3f7f
GN		 1837 if (kvm_exception_is_soft(nr)) {
1838 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1839 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1840 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1841 } else
1842 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1843
1844 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1845}
1846
4e47c7a6
SY		 1847static bool vmx_rdtscp_supported(void)
1848{
1849 return cpu_has_vmx_rdtscp();
1850}
1851
ad756a16
MJ		 1852static bool vmx_invpcid_supported(void)
1853{
1854 return cpu_has_vmx_invpcid() && enable_ept;
1855}
1856
a75beee6
ED		 1857/*
1858 * Swap MSR entry in host/guest MSR entry array.
1859 */
8b9cf98c 1860static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1861{
26bb0981 1862 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1863
1864 tmp = vmx->guest_msrs[to];
1865 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1866 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1867}
1868
8d14695f
YZ		 1869static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1870{
1871 unsigned long *msr_bitmap;
1872
1873 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1874 if (is_long_mode(vcpu))
1875 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1876 else
1877 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1878 } else {
1879 if (is_long_mode(vcpu))
1880 msr_bitmap = vmx_msr_bitmap_longmode;
1881 else
1882 msr_bitmap = vmx_msr_bitmap_legacy;
1883 }
1884
1885 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1886}
1887
e38aea3e
AK		 1888/*
1889 * Set up the vmcs to automatically save and restore system
1890 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1891 * mode, as fiddling with msrs is very expensive.
1892 */
8b9cf98c 1893static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1894{
26bb0981 1895 int save_nmsrs, index;
e38aea3e 1896
a75beee6
ED		 1897 save_nmsrs = 0;
1898#ifdef CONFIG_X86_64
8b9cf98c 1899 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1900 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1901 if (index >= 0)
8b9cf98c
RR		 1902 move_msr_up(vmx, index, save_nmsrs++);
1903 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1904 if (index >= 0)
8b9cf98c
RR		 1905 move_msr_up(vmx, index, save_nmsrs++);
1906 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1907 if (index >= 0)
8b9cf98c 1908 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1909 index = __find_msr_index(vmx, MSR_TSC_AUX);
1910 if (index >= 0 && vmx->rdtscp_enabled)
1911 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1912 /*
8c06585d 1913 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1914 * if efer.sce is enabled.
1915 */
8c06585d 1916 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1917 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1918 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1919 }
1920#endif
92c0d900
AK		 1921 index = __find_msr_index(vmx, MSR_EFER);
1922 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1923 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1924
26bb0981 1925 vmx->save_nmsrs = save_nmsrs;
5897297b 1926
8d14695f
YZ		 1927 if (cpu_has_vmx_msr_bitmap())
1928 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1929}
1930
6aa8b732
AK		 1931/*
1932 * reads and returns guest's timestamp counter "register"
1933 * guest_tsc = host_tsc + tsc_offset -- 21.3
1934 */
1935static u64 guest_read_tsc(void)
1936{
1937 u64 host_tsc, tsc_offset;
1938
1939 rdtscll(host_tsc);
1940 tsc_offset = vmcs_read64(TSC_OFFSET);
1941 return host_tsc + tsc_offset;
1942}
1943
d5c1785d
NHE		 1944/*
1945 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1946 * counter, even if a nested guest (L2) is currently running.
1947 */
886b470c 1948u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1949{
886b470c 1950 u64 tsc_offset;
d5c1785d 1951
d5c1785d
NHE		 1952 tsc_offset = is_guest_mode(vcpu) ?
1953 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1954 vmcs_read64(TSC_OFFSET);
1955 return host_tsc + tsc_offset;
1956}
1957
4051b188 1958/*
cc578287
ZA		 1959 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1960 * software catchup for faster rates on slower CPUs.
4051b188 1961 */
cc578287 1962static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1963{
cc578287
ZA		 1964 if (!scale)
1965 return;
1966
1967 if (user_tsc_khz > tsc_khz) {
1968 vcpu->arch.tsc_catchup = 1;
1969 vcpu->arch.tsc_always_catchup = 1;
1970 } else
1971 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1972}
1973
ba904635
WA		 1974static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1975{
1976 return vmcs_read64(TSC_OFFSET);
1977}
1978
6aa8b732 1979/*
99e3e30a 1980 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1981 */
99e3e30a 1982static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1983{
27fc51b2 1984 if (is_guest_mode(vcpu)) {
7991825b 1985 /*
27fc51b2
NHE		 1986 * We're here if L1 chose not to trap WRMSR to TSC. According
1987 * to the spec, this should set L1's TSC; The offset that L1
1988 * set for L2 remains unchanged, and still needs to be added
1989 * to the newly set TSC to get L2's TSC.
7991825b 1990 */
27fc51b2
NHE		 1991 struct vmcs12 *vmcs12;
1992 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1993 /* recalculate vmcs02.TSC_OFFSET: */
1994 vmcs12 = get_vmcs12(vcpu);
1995 vmcs_write64(TSC_OFFSET, offset +
1996 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1997 vmcs12->tsc_offset : 0));
1998 } else {
1999 vmcs_write64(TSC_OFFSET, offset);
2000 }
6aa8b732
AK		 2001}
2002
f1e2b260 2003static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2004{
2005 u64 offset = vmcs_read64(TSC_OFFSET);
2006 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2007 if (is_guest_mode(vcpu)) {
2008 /* Even when running L2, the adjustment needs to apply to L1 */
2009 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2010 }
e48672fa
ZA		 2011}
2012
857e4099
JR		 2013static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2014{
2015 return target_tsc - native_read_tsc();
2016}
2017
801d3424
NHE		 2018static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2019{
2020 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2021 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2022}
2023
2024/*
2025 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2026 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2027 * all guests if the "nested" module option is off, and can also be disabled
2028 * for a single guest by disabling its VMX cpuid bit.
2029 */
2030static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2031{
2032 return nested && guest_cpuid_has_vmx(vcpu);
2033}
2034
b87a51ae
NHE		 2035/*
2036 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2037 * returned for the various VMX controls MSRs when nested VMX is enabled.
2038 * The same values should also be used to verify that vmcs12 control fields are
2039 * valid during nested entry from L1 to L2.
2040 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2041 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2042 * bit in the high half is on if the corresponding bit in the control field
2043 * may be on. See also vmx_control_verify().
2044 * TODO: allow these variables to be modified (downgraded) by module options
2045 * or other means.
2046 */
2047static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2048static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2049static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2050static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2051static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2052static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2053static __init void nested_vmx_setup_ctls_msrs(void)
2054{
2055 /*
2056 * Note that as a general rule, the high half of the MSRs (bits in
2057 * the control fields which may be 1) should be initialized by the
2058 * intersection of the underlying hardware's MSR (i.e., features which
2059 * can be supported) and the list of features we want to expose -
2060 * because they are known to be properly supported in our code.
2061 * Also, usually, the low half of the MSRs (bits which must be 1) can
2062 * be set to 0, meaning that L1 may turn off any of these bits. The
2063 * reason is that if one of these bits is necessary, it will appear
2064 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2065 * fields of vmcs01 and vmcs02, will turn these bits off - and
2066 * nested_vmx_exit_handled() will not pass related exits to L1.
2067 * These rules have exceptions below.
2068 */
2069
2070 /* pin-based controls */
eabeaacc
JK		 2071 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2072 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2073 /*
2074 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2075 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2076 */
eabeaacc
JK		 2077 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2078 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2079 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2080 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2081 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2082
33fb20c3
JK		 2083 /*
2084 * Exit controls
2085 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2086 * 17 must be 1.
2087 */
2088 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2089 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2090#ifdef CONFIG_X86_64
2091 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2092#else
2093 nested_vmx_exit_ctls_high = 0;
2094#endif
33fb20c3 2095 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2096
2097 /* entry controls */
2098 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2099 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2100 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2101 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2102 nested_vmx_entry_ctls_high &=
2103 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2104 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2105
2106 /* cpu-based controls */
2107 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2108 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2109 nested_vmx_procbased_ctls_low = 0;
2110 nested_vmx_procbased_ctls_high &=
2111 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2112 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2113 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2114 CPU_BASED_CR3_STORE_EXITING |
2115#ifdef CONFIG_X86_64
2116 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2117#endif
2118 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2119 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2120 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2121 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2122 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2123 /*
2124 * We can allow some features even when not supported by the
2125 * hardware. For example, L1 can specify an MSR bitmap - and we
2126 * can use it to avoid exits to L1 - even when L0 runs L2
2127 * without MSR bitmaps.
2128 */
2129 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2130
2131 /* secondary cpu-based controls */
2132 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2133 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2134 nested_vmx_secondary_ctls_low = 0;
2135 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2136 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2137 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2138
2139 /* miscellaneous data */
2140 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2141 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2142 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2143 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2144}
2145
2146static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2147{
2148 /*
2149 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2150 */
2151 return ((control & high) | low) == control;
2152}
2153
2154static inline u64 vmx_control_msr(u32 low, u32 high)
2155{
2156 return low | ((u64)high << 32);
2157}
2158
2159/*
2160 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2161 * also let it use VMX-specific MSRs.
2162 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2163 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2164 * like all other MSRs).
2165 */
2166static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2167{
2168 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2169 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2170 /*
2171 * According to the spec, processors which do not support VMX
2172 * should throw a #GP(0) when VMX capability MSRs are read.
2173 */
2174 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2175 return 1;
2176 }
2177
2178 switch (msr_index) {
2179 case MSR_IA32_FEATURE_CONTROL:
2180 *pdata = 0;
2181 break;
2182 case MSR_IA32_VMX_BASIC:
2183 /*
2184 * This MSR reports some information about VMX support. We
2185 * should return information about the VMX we emulate for the
2186 * guest, and the VMCS structure we give it - not about the
2187 * VMX support of the underlying hardware.
2188 */
2189 *pdata = VMCS12_REVISION |
2190 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2191 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2192 break;
2193 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2194 case MSR_IA32_VMX_PINBASED_CTLS:
2195 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2196 nested_vmx_pinbased_ctls_high);
2197 break;
2198 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2199 case MSR_IA32_VMX_PROCBASED_CTLS:
2200 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2201 nested_vmx_procbased_ctls_high);
2202 break;
2203 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2204 case MSR_IA32_VMX_EXIT_CTLS:
2205 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2206 nested_vmx_exit_ctls_high);
2207 break;
2208 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2209 case MSR_IA32_VMX_ENTRY_CTLS:
2210 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2211 nested_vmx_entry_ctls_high);
2212 break;
2213 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2214 *pdata = vmx_control_msr(nested_vmx_misc_low,
2215 nested_vmx_misc_high);
b87a51ae
NHE		 2216 break;
2217 /*
2218 * These MSRs specify bits which the guest must keep fixed (on or off)
2219 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2220 * We picked the standard core2 setting.
2221 */
2222#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2223#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2224 case MSR_IA32_VMX_CR0_FIXED0:
2225 *pdata = VMXON_CR0_ALWAYSON;
2226 break;
2227 case MSR_IA32_VMX_CR0_FIXED1:
2228 *pdata = -1ULL;
2229 break;
2230 case MSR_IA32_VMX_CR4_FIXED0:
2231 *pdata = VMXON_CR4_ALWAYSON;
2232 break;
2233 case MSR_IA32_VMX_CR4_FIXED1:
2234 *pdata = -1ULL;
2235 break;
2236 case MSR_IA32_VMX_VMCS_ENUM:
2237 *pdata = 0x1f;
2238 break;
2239 case MSR_IA32_VMX_PROCBASED_CTLS2:
2240 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2241 nested_vmx_secondary_ctls_high);
2242 break;
2243 case MSR_IA32_VMX_EPT_VPID_CAP:
2244 /* Currently, no nested ept or nested vpid */
2245 *pdata = 0;
2246 break;
2247 default:
2248 return 0;
2249 }
2250
2251 return 1;
2252}
2253
2254static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2255{
2256 if (!nested_vmx_allowed(vcpu))
2257 return 0;
2258
2259 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2260 /* TODO: the right thing. */
2261 return 1;
2262 /*
2263 * No need to treat VMX capability MSRs specially: If we don't handle
2264 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2265 */
2266 return 0;
2267}
2268
6aa8b732
AK		 2269/*
2270 * Reads an msr value (of 'msr_index') into 'pdata'.
2271 * Returns 0 on success, non-0 otherwise.
2272 * Assumes vcpu_load() was already called.
2273 */
2274static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2275{
2276 u64 data;
26bb0981 2277 struct shared_msr_entry *msr;
6aa8b732
AK		 2278
2279 if (!pdata) {
2280 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2281 return -EINVAL;
2282 }
2283
2284 switch (msr_index) {
05b3e0c2 2285#ifdef CONFIG_X86_64
6aa8b732
AK		 2286 case MSR_FS_BASE:
2287 data = vmcs_readl(GUEST_FS_BASE);
2288 break;
2289 case MSR_GS_BASE:
2290 data = vmcs_readl(GUEST_GS_BASE);
2291 break;
44ea2b17
AK		 2292 case MSR_KERNEL_GS_BASE:
2293 vmx_load_host_state(to_vmx(vcpu));
2294 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2295 break;
26bb0981 2296#endif
6aa8b732 2297 case MSR_EFER:
3bab1f5d 2298 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2299 case MSR_IA32_TSC:
6aa8b732
AK		 2300 data = guest_read_tsc();
2301 break;
2302 case MSR_IA32_SYSENTER_CS:
2303 data = vmcs_read32(GUEST_SYSENTER_CS);
2304 break;
2305 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2306 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2307 break;
2308 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2309 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2310 break;
4e47c7a6
SY		 2311 case MSR_TSC_AUX:
2312 if (!to_vmx(vcpu)->rdtscp_enabled)
2313 return 1;
2314 /* Otherwise falls through */
6aa8b732 2315 default:
b87a51ae
NHE		 2316 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2317 return 0;
8b9cf98c 2318 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2319 if (msr) {
2320 data = msr->data;
2321 break;
6aa8b732 2322 }
3bab1f5d 2323 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2324 }
2325
2326 *pdata = data;
2327 return 0;
2328}
2329
2330/*
2331 * Writes msr value into into the appropriate "register".
2332 * Returns 0 on success, non-0 otherwise.
2333 * Assumes vcpu_load() was already called.
2334 */
8fe8ab46 2335static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2336{
a2fa3e9f 2337 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2338 struct shared_msr_entry *msr;
2cc51560 2339 int ret = 0;
8fe8ab46
WA		 2340 u32 msr_index = msr_info->index;
2341 u64 data = msr_info->data;
2cc51560 2342
6aa8b732 2343 switch (msr_index) {
3bab1f5d 2344 case MSR_EFER:
8fe8ab46 2345 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2346 break;
16175a79 2347#ifdef CONFIG_X86_64
6aa8b732 2348 case MSR_FS_BASE:
2fb92db1 2349 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2350 vmcs_writel(GUEST_FS_BASE, data);
2351 break;
2352 case MSR_GS_BASE:
2fb92db1 2353 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2354 vmcs_writel(GUEST_GS_BASE, data);
2355 break;
44ea2b17
AK		 2356 case MSR_KERNEL_GS_BASE:
2357 vmx_load_host_state(vmx);
2358 vmx->msr_guest_kernel_gs_base = data;
2359 break;
6aa8b732
AK		 2360#endif
2361 case MSR_IA32_SYSENTER_CS:
2362 vmcs_write32(GUEST_SYSENTER_CS, data);
2363 break;
2364 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2365 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2366 break;
2367 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2368 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2369 break;
af24a4e4 2370 case MSR_IA32_TSC:
8fe8ab46 2371 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2372 break;
468d472f
SY		 2373 case MSR_IA32_CR_PAT:
2374 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2375 vmcs_write64(GUEST_IA32_PAT, data);
2376 vcpu->arch.pat = data;
2377 break;
2378 }
8fe8ab46 2379 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2380 break;
ba904635
WA		 2381 case MSR_IA32_TSC_ADJUST:
2382 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2383 break;
2384 case MSR_TSC_AUX:
2385 if (!vmx->rdtscp_enabled)
2386 return 1;
2387 /* Check reserved bit, higher 32 bits should be zero */
2388 if ((data >> 32) != 0)
2389 return 1;
2390 /* Otherwise falls through */
6aa8b732 2391 default:
b87a51ae
NHE		 2392 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2393 break;
8b9cf98c 2394 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2395 if (msr) {
2396 msr->data = data;
2225fd56
AK		 2397 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2398 preempt_disable();
9ee73970
AK		 2399 kvm_set_shared_msr(msr->index, msr->data,
2400 msr->mask);
2225fd56
AK		 2401 preempt_enable();
2402 }
3bab1f5d 2403 break;
6aa8b732 2404 }
8fe8ab46 2405 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2406 }
2407
2cc51560 2408 return ret;
6aa8b732
AK		 2409}
2410
5fdbf976 2411static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2412{
5fdbf976
MT		 2413 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2414 switch (reg) {
2415 case VCPU_REGS_RSP:
2416 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2417 break;
2418 case VCPU_REGS_RIP:
2419 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2420 break;
6de4f3ad
AK		 2421 case VCPU_EXREG_PDPTR:
2422 if (enable_ept)
2423 ept_save_pdptrs(vcpu);
2424 break;
5fdbf976
MT		 2425 default:
2426 break;
2427 }
6aa8b732
AK		 2428}
2429
6aa8b732
AK		 2430static __init int cpu_has_kvm_support(void)
2431{
6210e37b 2432 return cpu_has_vmx();
6aa8b732
AK		 2433}
2434
2435static __init int vmx_disabled_by_bios(void)
2436{
2437 u64 msr;
2438
2439 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2440 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2441 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2442 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2443 && tboot_enabled())
2444 return 1;
23f3e991 2445 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2446 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2447 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2448 && !tboot_enabled()) {
2449 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2450 "activate TXT before enabling KVM\n");
cafd6659 2451 return 1;
f9335afe 2452 }
23f3e991
JC		 2453 /* launched w/o TXT and VMX disabled */
2454 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2455 && !tboot_enabled())
2456 return 1;
cafd6659
SW		 2457 }
2458
2459 return 0;
6aa8b732
AK		 2460}
2461
7725b894
DX		 2462static void kvm_cpu_vmxon(u64 addr)
2463{
2464 asm volatile (ASM_VMX_VMXON_RAX
2465 : : "a"(&addr), "m"(addr)
2466 : "memory", "cc");
2467}
2468
10474ae8 2469static int hardware_enable(void *garbage)
6aa8b732
AK		 2470{
2471 int cpu = raw_smp_processor_id();
2472 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2473 u64 old, test_bits;
6aa8b732 2474
10474ae8
AG		 2475 if (read_cr4() & X86_CR4_VMXE)
2476 return -EBUSY;
2477
d462b819 2478 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2479
2480 /*
2481 * Now we can enable the vmclear operation in kdump
2482 * since the loaded_vmcss_on_cpu list on this cpu
2483 * has been initialized.
2484 *
2485 * Though the cpu is not in VMX operation now, there
2486 * is no problem to enable the vmclear operation
2487 * for the loaded_vmcss_on_cpu list is empty!
2488 */
2489 crash_enable_local_vmclear(cpu);
2490
6aa8b732 2491 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2492
2493 test_bits = FEATURE_CONTROL_LOCKED;
2494 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2495 if (tboot_enabled())
2496 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2497
2498 if ((old & test_bits) != test_bits) {
6aa8b732 2499 /* enable and lock */
cafd6659
SW		 2500 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2501 }
66aee91a 2502 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2503
4610c9cc
DX		 2504 if (vmm_exclusive) {
2505 kvm_cpu_vmxon(phys_addr);
2506 ept_sync_global();
2507 }
10474ae8 2508
3444d7da
AK		 2509 store_gdt(&__get_cpu_var(host_gdt));
2510
10474ae8 2511 return 0;
6aa8b732
AK		 2512}
2513
d462b819 2514static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2515{
2516 int cpu = raw_smp_processor_id();
d462b819 2517 struct loaded_vmcs *v, *n;
543e4243 2518
d462b819
NHE		 2519 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2520 loaded_vmcss_on_cpu_link)
2521 __loaded_vmcs_clear(v);
543e4243
AK		 2522}
2523
710ff4a8
EH		 2524
2525/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2526 * tricks.
2527 */
2528static void kvm_cpu_vmxoff(void)
6aa8b732 2529{
4ecac3fd 2530 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2531}
2532
710ff4a8
EH		 2533static void hardware_disable(void *garbage)
2534{
4610c9cc 2535 if (vmm_exclusive) {
d462b819 2536 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2537 kvm_cpu_vmxoff();
2538 }
7725b894 2539 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2540}
2541
1c3d14fe 2542static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2543 u32 msr, u32 *result)
1c3d14fe
YS		 2544{
2545 u32 vmx_msr_low, vmx_msr_high;
2546 u32 ctl = ctl_min | ctl_opt;
2547
2548 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2549
2550 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2551 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2552
2553 /* Ensure minimum (required) set of control bits are supported. */
2554 if (ctl_min & ~ctl)
002c7f7c 2555 return -EIO;
1c3d14fe
YS		 2556
2557 *result = ctl;
2558 return 0;
2559}
2560
110312c8
AK		 2561static __init bool allow_1_setting(u32 msr, u32 ctl)
2562{
2563 u32 vmx_msr_low, vmx_msr_high;
2564
2565 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2566 return vmx_msr_high & ctl;
2567}
2568
002c7f7c 2569static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2570{
2571 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2572 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2573 u32 _pin_based_exec_control = 0;
2574 u32 _cpu_based_exec_control = 0;
f78e0e2e 2575 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2576 u32 _vmexit_control = 0;
2577 u32 _vmentry_control = 0;
2578
10166744 2579 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2580#ifdef CONFIG_X86_64
2581 CPU_BASED_CR8_LOAD_EXITING |
2582 CPU_BASED_CR8_STORE_EXITING |
2583#endif
d56f546d
SY		 2584 CPU_BASED_CR3_LOAD_EXITING |
2585 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2586 CPU_BASED_USE_IO_BITMAPS |
2587 CPU_BASED_MOV_DR_EXITING |
a7052897 2588 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2589 CPU_BASED_MWAIT_EXITING |
2590 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2591 CPU_BASED_INVLPG_EXITING |
2592 CPU_BASED_RDPMC_EXITING;
443381a8 2593
f78e0e2e 2594 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2595 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2596 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2597 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2598 &_cpu_based_exec_control) < 0)
002c7f7c 2599 return -EIO;
6e5d865c
YS		 2600#ifdef CONFIG_X86_64
2601 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2602 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2603 ~CPU_BASED_CR8_STORE_EXITING;
2604#endif
f78e0e2e 2605 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2606 min2 = 0;
2607 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2608 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2609 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2610 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2611 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2612 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2613 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2614 SECONDARY_EXEC_RDTSCP |
83d4c286 2615 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c
YZ		 2616 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2617 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
d56f546d
SY		 2618 if (adjust_vmx_controls(min2, opt2,
2619 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2620 &_cpu_based_2nd_exec_control) < 0)
2621 return -EIO;
2622 }
2623#ifndef CONFIG_X86_64
2624 if (!(_cpu_based_2nd_exec_control &
2625 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2626 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2627#endif
83d4c286
YZ		 2628
2629 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2630 _cpu_based_2nd_exec_control &= ~(
8d14695f 2631 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2632 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2633 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2634
d56f546d 2635 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2636 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2637 enabled */
5fff7d27
GN		 2638 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2639 CPU_BASED_CR3_STORE_EXITING |
2640 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2641 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2642 vmx_capability.ept, vmx_capability.vpid);
2643 }
1c3d14fe
YS		 2644
2645 min = 0;
2646#ifdef CONFIG_X86_64
2647 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2648#endif
a547c6db
YZ		 2649 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2650 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2651 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2652 &_vmexit_control) < 0)
002c7f7c 2653 return -EIO;
1c3d14fe 2654
01e439be
YZ		 2655 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2656 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2657 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2658 &_pin_based_exec_control) < 0)
2659 return -EIO;
2660
2661 if (!(_cpu_based_2nd_exec_control &
2662 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2663 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2664 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2665
468d472f
SY		 2666 min = 0;
2667 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2668 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2669 &_vmentry_control) < 0)
002c7f7c 2670 return -EIO;
6aa8b732 2671
c68876fd 2672 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2673
2674 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2675 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2676 return -EIO;
1c3d14fe
YS		 2677
2678#ifdef CONFIG_X86_64
2679 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2680 if (vmx_msr_high & (1u<<16))
002c7f7c 2681 return -EIO;
1c3d14fe
YS		 2682#endif
2683
2684 /* Require Write-Back (WB) memory type for VMCS accesses. */
2685 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2686 return -EIO;
1c3d14fe 2687
002c7f7c
YS		 2688 vmcs_conf->size = vmx_msr_high & 0x1fff;
2689 vmcs_conf->order = get_order(vmcs_config.size);
2690 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2691
002c7f7c
YS		 2692 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2693 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2694 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2695 vmcs_conf->vmexit_ctrl = _vmexit_control;
2696 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2697
110312c8
AK		 2698 cpu_has_load_ia32_efer =
2699 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2700 VM_ENTRY_LOAD_IA32_EFER)
2701 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2702 VM_EXIT_LOAD_IA32_EFER);
2703
8bf00a52
GN		 2704 cpu_has_load_perf_global_ctrl =
2705 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2706 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2707 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2708 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2709
2710 /*
2711 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2712 * but due to arrata below it can't be used. Workaround is to use
2713 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2714 *
2715 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2716 *
2717 * AAK155 (model 26)
2718 * AAP115 (model 30)
2719 * AAT100 (model 37)
2720 * BC86,AAY89,BD102 (model 44)
2721 * BA97 (model 46)
2722 *
2723 */
2724 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2725 switch (boot_cpu_data.x86_model) {
2726 case 26:
2727 case 30:
2728 case 37:
2729 case 44:
2730 case 46:
2731 cpu_has_load_perf_global_ctrl = false;
2732 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2733 "does not work properly. Using workaround\n");
2734 break;
2735 default:
2736 break;
2737 }
2738 }
2739
1c3d14fe 2740 return 0;
c68876fd 2741}
6aa8b732
AK		 2742
2743static struct vmcs *alloc_vmcs_cpu(int cpu)
2744{
2745 int node = cpu_to_node(cpu);
2746 struct page *pages;
2747 struct vmcs *vmcs;
2748
6484eb3e 2749 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2750 if (!pages)
2751 return NULL;
2752 vmcs = page_address(pages);
1c3d14fe
YS		 2753 memset(vmcs, 0, vmcs_config.size);
2754 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2755 return vmcs;
2756}
2757
2758static struct vmcs *alloc_vmcs(void)
2759{
d3b2c338 2760 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2761}
2762
2763static void free_vmcs(struct vmcs *vmcs)
2764{
1c3d14fe 2765 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2766}
2767
d462b819
NHE		 2768/*
2769 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2770 */
2771static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2772{
2773 if (!loaded_vmcs->vmcs)
2774 return;
2775 loaded_vmcs_clear(loaded_vmcs);
2776 free_vmcs(loaded_vmcs->vmcs);
2777 loaded_vmcs->vmcs = NULL;
2778}
2779
39959588 2780static void free_kvm_area(void)
6aa8b732
AK		 2781{
2782 int cpu;
2783
3230bb47 2784 for_each_possible_cpu(cpu) {
6aa8b732 2785 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2786 per_cpu(vmxarea, cpu) = NULL;
2787 }
6aa8b732
AK		 2788}
2789
6aa8b732
AK		 2790static __init int alloc_kvm_area(void)
2791{
2792 int cpu;
2793
3230bb47 2794 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2795 struct vmcs *vmcs;
2796
2797 vmcs = alloc_vmcs_cpu(cpu);
2798 if (!vmcs) {
2799 free_kvm_area();
2800 return -ENOMEM;
2801 }
2802
2803 per_cpu(vmxarea, cpu) = vmcs;
2804 }
2805 return 0;
2806}
2807
2808static __init int hardware_setup(void)
2809{
002c7f7c
YS		 2810 if (setup_vmcs_config(&vmcs_config) < 0)
2811 return -EIO;
50a37eb4
JR		 2812
2813 if (boot_cpu_has(X86_FEATURE_NX))
2814 kvm_enable_efer_bits(EFER_NX);
2815
93ba03c2
SY		 2816 if (!cpu_has_vmx_vpid())
2817 enable_vpid = 0;
2818
4bc9b982
SY		 2819 if (!cpu_has_vmx_ept() ||
2820 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2821 enable_ept = 0;
3a624e29 2822 enable_unrestricted_guest = 0;
83c3a331 2823 enable_ept_ad_bits = 0;
3a624e29
NK		 2824 }
2825
83c3a331
XH		 2826 if (!cpu_has_vmx_ept_ad_bits())
2827 enable_ept_ad_bits = 0;
2828
3a624e29
NK		 2829 if (!cpu_has_vmx_unrestricted_guest())
2830 enable_unrestricted_guest = 0;
93ba03c2
SY		 2831
2832 if (!cpu_has_vmx_flexpriority())
2833 flexpriority_enabled = 0;
2834
95ba8273
GN		 2835 if (!cpu_has_vmx_tpr_shadow())
2836 kvm_x86_ops->update_cr8_intercept = NULL;
2837
54dee993
MT		 2838 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2839 kvm_disable_largepages();
2840
4b8d54f9
ZE		 2841 if (!cpu_has_vmx_ple())
2842 ple_gap = 0;
2843
01e439be
YZ		 2844 if (!cpu_has_vmx_apicv())
2845 enable_apicv = 0;
c7c9c56c 2846
01e439be 2847 if (enable_apicv)
c7c9c56c
YZ		 2848 kvm_x86_ops->update_cr8_intercept = NULL;
2849 else
2850 kvm_x86_ops->hwapic_irr_update = NULL;
83d4c286 2851
b87a51ae
NHE		 2852 if (nested)
2853 nested_vmx_setup_ctls_msrs();
2854
6aa8b732
AK		 2855 return alloc_kvm_area();
2856}
2857
2858static __exit void hardware_unsetup(void)
2859{
2860 free_kvm_area();
2861}
2862
14168786
GN		 2863static bool emulation_required(struct kvm_vcpu *vcpu)
2864{
2865 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2866}
2867
91b0aa2c 2868static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2869 struct kvm_segment *save)
6aa8b732 2870{
d99e4152
GN		 2871 if (!emulate_invalid_guest_state) {
2872 /*
2873 * CS and SS RPL should be equal during guest entry according
2874 * to VMX spec, but in reality it is not always so. Since vcpu
2875 * is in the middle of the transition from real mode to
2876 * protected mode it is safe to assume that RPL 0 is a good
2877 * default value.
2878 */
2879 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2880 save->selector &= ~SELECTOR_RPL_MASK;
2881 save->dpl = save->selector & SELECTOR_RPL_MASK;
2882 save->s = 1;
6aa8b732 2883 }
d99e4152 2884 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2885}
2886
2887static void enter_pmode(struct kvm_vcpu *vcpu)
2888{
2889 unsigned long flags;
a89a8fb9 2890 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2891
d99e4152
GN		 2892 /*
2893 * Update real mode segment cache. It may be not up-to-date if sement
2894 * register was written while vcpu was in a guest mode.
2895 */
2896 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2897 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2898 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2899 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2900 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2901 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2902
7ffd92c5 2903 vmx->rmode.vm86_active = 0;
6aa8b732 2904
2fb92db1
AK		 2905 vmx_segment_cache_clear(vmx);
2906
f5f7b2fe 2907 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2908
2909 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2910 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2911 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2912 vmcs_writel(GUEST_RFLAGS, flags);
2913
66aee91a
RR		 2914 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2915 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2916
2917 update_exception_bitmap(vcpu);
2918
91b0aa2c
GN		 2919 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2920 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2921 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2922 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2923 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2924 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 2925
2926 /* CPL is always 0 when CPU enters protected mode */
2927 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2928 vmx->cpl = 0;
6aa8b732
AK		 2929}
2930
f5f7b2fe 2931static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2932{
772e0318 2933 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2934 struct kvm_segment var = *save;
2935
2936 var.dpl = 0x3;
2937 if (seg == VCPU_SREG_CS)
2938 var.type = 0x3;
2939
2940 if (!emulate_invalid_guest_state) {
2941 var.selector = var.base >> 4;
2942 var.base = var.base & 0xffff0;
2943 var.limit = 0xffff;
2944 var.g = 0;
2945 var.db = 0;
2946 var.present = 1;
2947 var.s = 1;
2948 var.l = 0;
2949 var.unusable = 0;
2950 var.type = 0x3;
2951 var.avl = 0;
2952 if (save->base & 0xf)
2953 printk_once(KERN_WARNING "kvm: segment base is not "
2954 "paragraph aligned when entering "
2955 "protected mode (seg=%d)", seg);
2956 }
6aa8b732 2957
d99e4152
GN		 2958 vmcs_write16(sf->selector, var.selector);
2959 vmcs_write32(sf->base, var.base);
2960 vmcs_write32(sf->limit, var.limit);
2961 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2962}
2963
2964static void enter_rmode(struct kvm_vcpu *vcpu)
2965{
2966 unsigned long flags;
a89a8fb9 2967 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2968
f5f7b2fe
AK		 2969 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2970 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2971 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2972 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2973 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2974 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2975 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2976
7ffd92c5 2977 vmx->rmode.vm86_active = 1;
6aa8b732 2978
776e58ea
GN		 2979 /*
2980 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2981 * vcpu. Warn the user that an update is overdue.
776e58ea 2982 */
4918c6ca 2983 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 2984 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2985 "called before entering vcpu\n");
776e58ea 2986
2fb92db1
AK		 2987 vmx_segment_cache_clear(vmx);
2988
4918c6ca 2989 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 2990 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2991 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2992
2993 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2994 vmx->rmode.save_rflags = flags;
6aa8b732 2995
053de044 2996 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2997
2998 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2999 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3000 update_exception_bitmap(vcpu);
3001
d99e4152
GN		 3002 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3003 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3004 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3005 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3006 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3007 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3008
8668a3c4 3009 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3010}
3011
401d10de
AS		 3012static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3013{
3014 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3015 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3016
3017 if (!msr)
3018 return;
401d10de 3019
44ea2b17
AK		 3020 /*
3021 * Force kernel_gs_base reloading before EFER changes, as control
3022 * of this msr depends on is_long_mode().
3023 */
3024 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3025 vcpu->arch.efer = efer;
401d10de
AS		 3026 if (efer & EFER_LMA) {
3027 vmcs_write32(VM_ENTRY_CONTROLS,
3028 vmcs_read32(VM_ENTRY_CONTROLS) |
3029 VM_ENTRY_IA32E_MODE);
3030 msr->data = efer;
3031 } else {
3032 vmcs_write32(VM_ENTRY_CONTROLS,
3033 vmcs_read32(VM_ENTRY_CONTROLS) &
3034 ~VM_ENTRY_IA32E_MODE);
3035
3036 msr->data = efer & ~EFER_LME;
3037 }
3038 setup_msrs(vmx);
3039}
3040
05b3e0c2 3041#ifdef CONFIG_X86_64
6aa8b732
AK		 3042
3043static void enter_lmode(struct kvm_vcpu *vcpu)
3044{
3045 u32 guest_tr_ar;
3046
2fb92db1
AK		 3047 vmx_segment_cache_clear(to_vmx(vcpu));
3048
6aa8b732
AK		 3049 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3050 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3051 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3052 __func__);
6aa8b732
AK		 3053 vmcs_write32(GUEST_TR_AR_BYTES,
3054 (guest_tr_ar & ~AR_TYPE_MASK)
3055 | AR_TYPE_BUSY_64_TSS);
3056 }
da38f438 3057 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3058}
3059
3060static void exit_lmode(struct kvm_vcpu *vcpu)
3061{
6aa8b732
AK		 3062 vmcs_write32(VM_ENTRY_CONTROLS,
3063 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3064 & ~VM_ENTRY_IA32E_MODE);
da38f438 3065 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3066}
3067
3068#endif
3069
2384d2b3
SY		 3070static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3071{
b9d762fa 3072 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3073 if (enable_ept) {
3074 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3075 return;
4e1096d2 3076 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3077 }
2384d2b3
SY		 3078}
3079
e8467fda
AK		 3080static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3081{
3082 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3083
3084 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3085 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3086}
3087
aff48baa
AK		 3088static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3089{
3090 if (enable_ept && is_paging(vcpu))
3091 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3092 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3093}
3094
25c4c276 3095static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3096{
fc78f519
AK		 3097 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3098
3099 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3100 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3101}
3102
1439442c
SY		 3103static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3104{
6de4f3ad
AK		 3105 if (!test_bit(VCPU_EXREG_PDPTR,
3106 (unsigned long *)&vcpu->arch.regs_dirty))
3107 return;
3108
1439442c 3109 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3110 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3111 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3112 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3113 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3114 }
3115}
3116
8f5d549f
AK		 3117static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3118{
3119 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3120 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3121 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3122 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3123 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3124 }
6de4f3ad
AK		 3125
3126 __set_bit(VCPU_EXREG_PDPTR,
3127 (unsigned long *)&vcpu->arch.regs_avail);
3128 __set_bit(VCPU_EXREG_PDPTR,
3129 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3130}
3131
5e1746d6 3132static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3133
3134static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3135 unsigned long cr0,
3136 struct kvm_vcpu *vcpu)
3137{
5233dd51
MT		 3138 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3139 vmx_decache_cr3(vcpu);
1439442c
SY		 3140 if (!(cr0 & X86_CR0_PG)) {
3141 /* From paging/starting to nonpaging */
3142 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3143 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3144 (CPU_BASED_CR3_LOAD_EXITING |
3145 CPU_BASED_CR3_STORE_EXITING));
3146 vcpu->arch.cr0 = cr0;
fc78f519 3147 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3148 } else if (!is_paging(vcpu)) {
3149 /* From nonpaging to paging */
3150 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3151 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3152 ~(CPU_BASED_CR3_LOAD_EXITING |
3153 CPU_BASED_CR3_STORE_EXITING));
3154 vcpu->arch.cr0 = cr0;
fc78f519 3155 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3156 }
95eb84a7
SY		 3157
3158 if (!(cr0 & X86_CR0_WP))
3159 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3160}
3161
6aa8b732
AK		 3162static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3163{
7ffd92c5 3164 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3165 unsigned long hw_cr0;
3166
5037878e 3167 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3168 if (enable_unrestricted_guest)
5037878e 3169 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3170 else {
5037878e 3171 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3172
218e763f
GN		 3173 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3174 enter_pmode(vcpu);
6aa8b732 3175
218e763f
GN		 3176 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3177 enter_rmode(vcpu);
3178 }
6aa8b732 3179
05b3e0c2 3180#ifdef CONFIG_X86_64
f6801dff 3181 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3182 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3183 enter_lmode(vcpu);
707d92fa 3184 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3185 exit_lmode(vcpu);
3186 }
3187#endif
3188
089d034e 3189 if (enable_ept)
1439442c
SY		 3190 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3191
02daab21 3192 if (!vcpu->fpu_active)
81231c69 3193 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3194
6aa8b732 3195 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3196 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3197 vcpu->arch.cr0 = cr0;
14168786
GN		 3198
3199 /* depends on vcpu->arch.cr0 to be set to a new value */
3200 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3201}
3202
1439442c
SY		 3203static u64 construct_eptp(unsigned long root_hpa)
3204{
3205 u64 eptp;
3206
3207 /* TODO write the value reading from MSR */
3208 eptp = VMX_EPT_DEFAULT_MT |
3209 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3210 if (enable_ept_ad_bits)
3211 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3212 eptp |= (root_hpa & PAGE_MASK);
3213
3214 return eptp;
3215}
3216
6aa8b732
AK		 3217static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3218{
1439442c
SY		 3219 unsigned long guest_cr3;
3220 u64 eptp;
3221
3222 guest_cr3 = cr3;
089d034e 3223 if (enable_ept) {
1439442c
SY		 3224 eptp = construct_eptp(cr3);
3225 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3226 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3227 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3228 ept_load_pdptrs(vcpu);
1439442c
SY		 3229 }
3230
2384d2b3 3231 vmx_flush_tlb(vcpu);
1439442c 3232 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3233}
3234
5e1746d6 3235static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3236{
7ffd92c5 3237 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3238 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3239
5e1746d6
NHE		 3240 if (cr4 & X86_CR4_VMXE) {
3241 /*
3242 * To use VMXON (and later other VMX instructions), a guest
3243 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3244 * So basically the check on whether to allow nested VMX
3245 * is here.
3246 */
3247 if (!nested_vmx_allowed(vcpu))
3248 return 1;
1a0d74e6
JK		 3249 }
3250 if (to_vmx(vcpu)->nested.vmxon &&
3251 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3252 return 1;
3253
ad312c7c 3254 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3255 if (enable_ept) {
3256 if (!is_paging(vcpu)) {
3257 hw_cr4 &= ~X86_CR4_PAE;
3258 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3259 /*
3260 * SMEP is disabled if CPU is in non-paging mode in
3261 * hardware. However KVM always uses paging mode to
3262 * emulate guest non-paging mode with TDP.
3263 * To emulate this behavior, SMEP needs to be manually
3264 * disabled when guest switches to non-paging mode.
3265 */
3266 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3267 } else if (!(cr4 & X86_CR4_PAE)) {
3268 hw_cr4 &= ~X86_CR4_PAE;
3269 }
3270 }
1439442c
SY		 3271
3272 vmcs_writel(CR4_READ_SHADOW, cr4);
3273 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3274 return 0;
6aa8b732
AK		 3275}
3276
6aa8b732
AK		 3277static void vmx_get_segment(struct kvm_vcpu *vcpu,
3278 struct kvm_segment *var, int seg)
3279{
a9179499 3280 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3281 u32 ar;
3282
c6ad1153 3283 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3284 *var = vmx->rmode.segs[seg];
a9179499 3285 if (seg == VCPU_SREG_TR
2fb92db1 3286 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3287 return;
1390a28b
AK		 3288 var->base = vmx_read_guest_seg_base(vmx, seg);
3289 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3290 return;
a9179499 3291 }
2fb92db1
AK		 3292 var->base = vmx_read_guest_seg_base(vmx, seg);
3293 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3294 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3295 ar = vmx_read_guest_seg_ar(vmx, seg);
6aa8b732
AK		 3296 var->type = ar & 15;
3297 var->s = (ar >> 4) & 1;
3298 var->dpl = (ar >> 5) & 3;
3299 var->present = (ar >> 7) & 1;
3300 var->avl = (ar >> 12) & 1;
3301 var->l = (ar >> 13) & 1;
3302 var->db = (ar >> 14) & 1;
3303 var->g = (ar >> 15) & 1;
3304 var->unusable = (ar >> 16) & 1;
3305}
3306
a9179499
AK		 3307static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3308{
a9179499
AK		 3309 struct kvm_segment s;
3310
3311 if (to_vmx(vcpu)->rmode.vm86_active) {
3312 vmx_get_segment(vcpu, &s, seg);
3313 return s.base;
3314 }
2fb92db1 3315 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3316}
3317
b09408d0 3318static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3319{
b09408d0
MT		 3320 struct vcpu_vmx *vmx = to_vmx(vcpu);
3321
3eeb3288 3322 if (!is_protmode(vcpu))
2e4d2653
IE		 3323 return 0;
3324
f4c63e5d
AK		 3325 if (!is_long_mode(vcpu)
3326 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3327 return 3;
3328
69c73028
AK		 3329 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3330 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3331 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3332 }
d881e6f6
AK		 3333
3334 return vmx->cpl;
69c73028
AK		 3335}
3336
3337
653e3108 3338static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3339{
6aa8b732
AK		 3340 u32 ar;
3341
f0495f9b 3342 if (var->unusable || !var->present)
6aa8b732
AK		 3343 ar = 1 << 16;
3344 else {
3345 ar = var->type & 15;
3346 ar |= (var->s & 1) << 4;
3347 ar |= (var->dpl & 3) << 5;
3348 ar |= (var->present & 1) << 7;
3349 ar |= (var->avl & 1) << 12;
3350 ar |= (var->l & 1) << 13;
3351 ar |= (var->db & 1) << 14;
3352 ar |= (var->g & 1) << 15;
3353 }
653e3108
AK		 3354
3355 return ar;
3356}
3357
3358static void vmx_set_segment(struct kvm_vcpu *vcpu,
3359 struct kvm_segment *var, int seg)
3360{
7ffd92c5 3361 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3362 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3363
2fb92db1 3364 vmx_segment_cache_clear(vmx);
2f143240
GN		 3365 if (seg == VCPU_SREG_CS)
3366 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3367
1ecd50a9
GN		 3368 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3369 vmx->rmode.segs[seg] = *var;
3370 if (seg == VCPU_SREG_TR)
3371 vmcs_write16(sf->selector, var->selector);
3372 else if (var->s)
3373 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3374 goto out;
653e3108 3375 }
1ecd50a9 3376
653e3108
AK		 3377 vmcs_writel(sf->base, var->base);
3378 vmcs_write32(sf->limit, var->limit);
3379 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3380
3381 /*
3382 * Fix the "Accessed" bit in AR field of segment registers for older
3383 * qemu binaries.
3384 * IA32 arch specifies that at the time of processor reset the
3385 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3386 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3387 * state vmexit when "unrestricted guest" mode is turned on.
3388 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3389 * tree. Newer qemu binaries with that qemu fix would not need this
3390 * kvm hack.
3391 */
3392 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3393 var->type |= 0x1; /* Accessed */
3a624e29 3394
f924d66d 3395 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3396
3397out:
14168786 3398 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3399}
3400
6aa8b732
AK		 3401static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3402{
2fb92db1 3403 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3404
3405 *db = (ar >> 14) & 1;
3406 *l = (ar >> 13) & 1;
3407}
3408
89a27f4d 3409static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3410{
89a27f4d
GN		 3411 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3412 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3413}
3414
89a27f4d 3415static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3416{
89a27f4d
GN		 3417 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3418 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3419}
3420
89a27f4d 3421static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3422{
89a27f4d
GN		 3423 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3424 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3425}
3426
89a27f4d 3427static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3428{
89a27f4d
GN		 3429 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3430 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3431}
3432
648dfaa7
MG		 3433static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3434{
3435 struct kvm_segment var;
3436 u32 ar;
3437
3438 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3439 var.dpl = 0x3;
0647f4aa
GN		 3440 if (seg == VCPU_SREG_CS)
3441 var.type = 0x3;
648dfaa7
MG		 3442 ar = vmx_segment_access_rights(&var);
3443
3444 if (var.base != (var.selector << 4))
3445 return false;
89efbed0 3446 if (var.limit != 0xffff)
648dfaa7 3447 return false;
07f42f5f 3448 if (ar != 0xf3)
648dfaa7
MG		 3449 return false;
3450
3451 return true;
3452}
3453
3454static bool code_segment_valid(struct kvm_vcpu *vcpu)
3455{
3456 struct kvm_segment cs;
3457 unsigned int cs_rpl;
3458
3459 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3460 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3461
1872a3f4
AK		 3462 if (cs.unusable)
3463 return false;
648dfaa7
MG		 3464 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3465 return false;
3466 if (!cs.s)
3467 return false;
1872a3f4 3468 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3469 if (cs.dpl > cs_rpl)
3470 return false;
1872a3f4 3471 } else {
648dfaa7
MG		 3472 if (cs.dpl != cs_rpl)
3473 return false;
3474 }
3475 if (!cs.present)
3476 return false;
3477
3478 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3479 return true;
3480}
3481
3482static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3483{
3484 struct kvm_segment ss;
3485 unsigned int ss_rpl;
3486
3487 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3488 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3489
1872a3f4
AK		 3490 if (ss.unusable)
3491 return true;
3492 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3493 return false;
3494 if (!ss.s)
3495 return false;
3496 if (ss.dpl != ss_rpl) /* DPL != RPL */
3497 return false;
3498 if (!ss.present)
3499 return false;
3500
3501 return true;
3502}
3503
3504static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3505{
3506 struct kvm_segment var;
3507 unsigned int rpl;
3508
3509 vmx_get_segment(vcpu, &var, seg);
3510 rpl = var.selector & SELECTOR_RPL_MASK;
3511
1872a3f4
AK		 3512 if (var.unusable)
3513 return true;
648dfaa7
MG		 3514 if (!var.s)
3515 return false;
3516 if (!var.present)
3517 return false;
3518 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3519 if (var.dpl < rpl) /* DPL < RPL */
3520 return false;
3521 }
3522
3523 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3524 * rights flags
3525 */
3526 return true;
3527}
3528
3529static bool tr_valid(struct kvm_vcpu *vcpu)
3530{
3531 struct kvm_segment tr;
3532
3533 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3534
1872a3f4
AK		 3535 if (tr.unusable)
3536 return false;
648dfaa7
MG		 3537 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3538 return false;
1872a3f4 3539 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3540 return false;
3541 if (!tr.present)
3542 return false;
3543
3544 return true;
3545}
3546
3547static bool ldtr_valid(struct kvm_vcpu *vcpu)
3548{
3549 struct kvm_segment ldtr;
3550
3551 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3552
1872a3f4
AK		 3553 if (ldtr.unusable)
3554 return true;
648dfaa7
MG		 3555 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3556 return false;
3557 if (ldtr.type != 2)
3558 return false;
3559 if (!ldtr.present)
3560 return false;
3561
3562 return true;
3563}
3564
3565static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3566{
3567 struct kvm_segment cs, ss;
3568
3569 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3570 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3571
3572 return ((cs.selector & SELECTOR_RPL_MASK) ==
3573 (ss.selector & SELECTOR_RPL_MASK));
3574}
3575
3576/*
3577 * Check if guest state is valid. Returns true if valid, false if
3578 * not.
3579 * We assume that registers are always usable
3580 */
3581static bool guest_state_valid(struct kvm_vcpu *vcpu)
3582{
c5e97c80
GN		 3583 if (enable_unrestricted_guest)
3584 return true;
3585
648dfaa7 3586 /* real mode guest state checks */
3eeb3288 3587 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3588 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3589 return false;
3590 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3591 return false;
3592 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3593 return false;
3594 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3595 return false;
3596 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3597 return false;
3598 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3599 return false;
3600 } else {
3601 /* protected mode guest state checks */
3602 if (!cs_ss_rpl_check(vcpu))
3603 return false;
3604 if (!code_segment_valid(vcpu))
3605 return false;
3606 if (!stack_segment_valid(vcpu))
3607 return false;
3608 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3609 return false;
3610 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3611 return false;
3612 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3613 return false;
3614 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3615 return false;
3616 if (!tr_valid(vcpu))
3617 return false;
3618 if (!ldtr_valid(vcpu))
3619 return false;
3620 }
3621 /* TODO:
3622 * - Add checks on RIP
3623 * - Add checks on RFLAGS
3624 */
3625
3626 return true;
3627}
3628
d77c26fc 3629static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3630{
40dcaa9f 3631 gfn_t fn;
195aefde 3632 u16 data = 0;
40dcaa9f 3633 int r, idx, ret = 0;
6aa8b732 3634
40dcaa9f 3635 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3636 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3637 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3638 if (r < 0)
10589a46 3639 goto out;
195aefde 3640 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3641 r = kvm_write_guest_page(kvm, fn++, &data,
3642 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3643 if (r < 0)
10589a46 3644 goto out;
195aefde
IE		 3645 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3646 if (r < 0)
10589a46 3647 goto out;
195aefde
IE		 3648 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3649 if (r < 0)
10589a46 3650 goto out;
195aefde 3651 data = ~0;
10589a46
MT		 3652 r = kvm_write_guest_page(kvm, fn, &data,
3653 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3654 sizeof(u8));
195aefde 3655 if (r < 0)
10589a46
MT		 3656 goto out;
3657
3658 ret = 1;
3659out:
40dcaa9f 3660 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3661 return ret;
6aa8b732
AK		 3662}
3663
b7ebfb05
SY		 3664static int init_rmode_identity_map(struct kvm *kvm)
3665{
40dcaa9f 3666 int i, idx, r, ret;
b7ebfb05
SY		 3667 pfn_t identity_map_pfn;
3668 u32 tmp;
3669
089d034e 3670 if (!enable_ept)
b7ebfb05
SY		 3671 return 1;
3672 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3673 printk(KERN_ERR "EPT: identity-mapping pagetable "
3674 "haven't been allocated!\n");
3675 return 0;
3676 }
3677 if (likely(kvm->arch.ept_identity_pagetable_done))
3678 return 1;
3679 ret = 0;
b927a3ce 3680 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3681 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3682 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3683 if (r < 0)
3684 goto out;
3685 /* Set up identity-mapping pagetable for EPT in real mode */
3686 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3687 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3688 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3689 r = kvm_write_guest_page(kvm, identity_map_pfn,
3690 &tmp, i * sizeof(tmp), sizeof(tmp));
3691 if (r < 0)
3692 goto out;
3693 }
3694 kvm->arch.ept_identity_pagetable_done = true;
3695 ret = 1;
3696out:
40dcaa9f 3697 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3698 return ret;
3699}
3700
6aa8b732
AK		 3701static void seg_setup(int seg)
3702{
772e0318 3703 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3704 unsigned int ar;
6aa8b732
AK		 3705
3706 vmcs_write16(sf->selector, 0);
3707 vmcs_writel(sf->base, 0);
3708 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3709 ar = 0x93;
3710 if (seg == VCPU_SREG_CS)
3711 ar |= 0x08; /* code segment */
3a624e29
NK		 3712
3713 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3714}
3715
f78e0e2e
SY		 3716static int alloc_apic_access_page(struct kvm *kvm)
3717{
4484141a 3718 struct page *page;
f78e0e2e
SY		 3719 struct kvm_userspace_memory_region kvm_userspace_mem;
3720 int r = 0;
3721
79fac95e 3722 mutex_lock(&kvm->slots_lock);
bfc6d222 3723 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3724 goto out;
3725 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3726 kvm_userspace_mem.flags = 0;
3727 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3728 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3729 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3730 if (r)
3731 goto out;
72dc67a6 3732
4484141a
XG		 3733 page = gfn_to_page(kvm, 0xfee00);
3734 if (is_error_page(page)) {
3735 r = -EFAULT;
3736 goto out;
3737 }
3738
3739 kvm->arch.apic_access_page = page;
f78e0e2e 3740out:
79fac95e 3741 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3742 return r;
3743}
3744
b7ebfb05
SY		 3745static int alloc_identity_pagetable(struct kvm *kvm)
3746{
4484141a 3747 struct page *page;
b7ebfb05
SY		 3748 struct kvm_userspace_memory_region kvm_userspace_mem;
3749 int r = 0;
3750
79fac95e 3751 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3752 if (kvm->arch.ept_identity_pagetable)
3753 goto out;
3754 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3755 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3756 kvm_userspace_mem.guest_phys_addr =
3757 kvm->arch.ept_identity_map_addr;
b7ebfb05 3758 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3759 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3760 if (r)
3761 goto out;
3762
4484141a
XG		 3763 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3764 if (is_error_page(page)) {
3765 r = -EFAULT;
3766 goto out;
3767 }
3768
3769 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3770out:
79fac95e 3771 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3772 return r;
3773}
3774
2384d2b3
SY		 3775static void allocate_vpid(struct vcpu_vmx *vmx)
3776{
3777 int vpid;
3778
3779 vmx->vpid = 0;
919818ab 3780 if (!enable_vpid)
2384d2b3
SY		 3781 return;
3782 spin_lock(&vmx_vpid_lock);
3783 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3784 if (vpid < VMX_NR_VPIDS) {
3785 vmx->vpid = vpid;
3786 __set_bit(vpid, vmx_vpid_bitmap);
3787 }
3788 spin_unlock(&vmx_vpid_lock);
3789}
3790
cdbecfc3
LJ		 3791static void free_vpid(struct vcpu_vmx *vmx)
3792{
3793 if (!enable_vpid)
3794 return;
3795 spin_lock(&vmx_vpid_lock);
3796 if (vmx->vpid != 0)
3797 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3798 spin_unlock(&vmx_vpid_lock);
3799}
3800
8d14695f
YZ		 3801#define MSR_TYPE_R 1
3802#define MSR_TYPE_W 2
3803static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3804 u32 msr, int type)
25c5f225 3805{
3e7c73e9 3806 int f = sizeof(unsigned long);
25c5f225
SY		 3807
3808 if (!cpu_has_vmx_msr_bitmap())
3809 return;
3810
3811 /*
3812 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3813 * have the write-low and read-high bitmap offsets the wrong way round.
3814 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3815 */
25c5f225 3816 if (msr <= 0x1fff) {
8d14695f
YZ		 3817 if (type & MSR_TYPE_R)
3818 /* read-low */
3819 __clear_bit(msr, msr_bitmap + 0x000 / f);
3820
3821 if (type & MSR_TYPE_W)
3822 /* write-low */
3823 __clear_bit(msr, msr_bitmap + 0x800 / f);
3824
25c5f225
SY		 3825 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3826 msr &= 0x1fff;
8d14695f
YZ		 3827 if (type & MSR_TYPE_R)
3828 /* read-high */
3829 __clear_bit(msr, msr_bitmap + 0x400 / f);
3830
3831 if (type & MSR_TYPE_W)
3832 /* write-high */
3833 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3834
3835 }
3836}
3837
3838static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3839 u32 msr, int type)
3840{
3841 int f = sizeof(unsigned long);
3842
3843 if (!cpu_has_vmx_msr_bitmap())
3844 return;
3845
3846 /*
3847 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3848 * have the write-low and read-high bitmap offsets the wrong way round.
3849 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3850 */
3851 if (msr <= 0x1fff) {
3852 if (type & MSR_TYPE_R)
3853 /* read-low */
3854 __set_bit(msr, msr_bitmap + 0x000 / f);
3855
3856 if (type & MSR_TYPE_W)
3857 /* write-low */
3858 __set_bit(msr, msr_bitmap + 0x800 / f);
3859
3860 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3861 msr &= 0x1fff;
3862 if (type & MSR_TYPE_R)
3863 /* read-high */
3864 __set_bit(msr, msr_bitmap + 0x400 / f);
3865
3866 if (type & MSR_TYPE_W)
3867 /* write-high */
3868 __set_bit(msr, msr_bitmap + 0xc00 / f);
3869
25c5f225 3870 }
25c5f225
SY		 3871}
3872
5897297b
AK		 3873static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3874{
3875 if (!longmode_only)
8d14695f
YZ		 3876 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3877 msr, MSR_TYPE_R | MSR_TYPE_W);
3878 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3879 msr, MSR_TYPE_R | MSR_TYPE_W);
3880}
3881
3882static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3883{
3884 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3885 msr, MSR_TYPE_R);
3886 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3887 msr, MSR_TYPE_R);
3888}
3889
3890static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3891{
3892 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3893 msr, MSR_TYPE_R);
3894 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3895 msr, MSR_TYPE_R);
3896}
3897
3898static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3899{
3900 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3901 msr, MSR_TYPE_W);
3902 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3903 msr, MSR_TYPE_W);
5897297b
AK		 3904}
3905
01e439be
YZ		 3906static int vmx_vm_has_apicv(struct kvm *kvm)
3907{
3908 return enable_apicv && irqchip_in_kernel(kvm);
3909}
3910
a3a8ff8e
NHE		 3911/*
3912 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3913 * will not change in the lifetime of the guest.
3914 * Note that host-state that does change is set elsewhere. E.g., host-state
3915 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3916 */
a547c6db 3917static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3918{
3919 u32 low32, high32;
3920 unsigned long tmpl;
3921 struct desc_ptr dt;
3922
b1a74bf8 3923 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3924 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3925 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3926
3927 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3928#ifdef CONFIG_X86_64
3929 /*
3930 * Load null selectors, so we can avoid reloading them in
3931 * __vmx_load_host_state(), in case userspace uses the null selectors
3932 * too (the expected case).
3933 */
3934 vmcs_write16(HOST_DS_SELECTOR, 0);
3935 vmcs_write16(HOST_ES_SELECTOR, 0);
3936#else
a3a8ff8e
NHE		 3937 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3938 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3939#endif
a3a8ff8e
NHE		 3940 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3941 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3942
3943 native_store_idt(&dt);
3944 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 3945 vmx->host_idt_base = dt.address;
a3a8ff8e 3946
83287ea4 3947 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3948
3949 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3950 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3951 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3952 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3953
3954 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3955 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3956 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3957 }
3958}
3959
bf8179a0
NHE		 3960static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3961{
3962 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3963 if (enable_ept)
3964 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3965 if (is_guest_mode(&vmx->vcpu))
3966 vmx->vcpu.arch.cr4_guest_owned_bits &=
3967 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3968 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3969}
3970
01e439be
YZ		 3971static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3972{
3973 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3974
3975 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3976 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
3977 return pin_based_exec_ctrl;
3978}
3979
bf8179a0
NHE		 3980static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3981{
3982 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3983 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3984 exec_control &= ~CPU_BASED_TPR_SHADOW;
3985#ifdef CONFIG_X86_64
3986 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3987 CPU_BASED_CR8_LOAD_EXITING;
3988#endif
3989 }
3990 if (!enable_ept)
3991 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3992 CPU_BASED_CR3_LOAD_EXITING |
3993 CPU_BASED_INVLPG_EXITING;
3994 return exec_control;
3995}
3996
3997static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3998{
3999 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4000 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4001 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4002 if (vmx->vpid == 0)
4003 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4004 if (!enable_ept) {
4005 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4006 enable_unrestricted_guest = 0;
ad756a16
MJ		 4007 /* Enable INVPCID for non-ept guests may cause performance regression. */
4008 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4009 }
4010 if (!enable_unrestricted_guest)
4011 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4012 if (!ple_gap)
4013 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4014 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4015 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4016 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4017 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
bf8179a0
NHE		 4018 return exec_control;
4019}
4020
ce88decf
XG		 4021static void ept_set_mmio_spte_mask(void)
4022{
4023 /*
4024 * EPT Misconfigurations can be generated if the value of bits 2:0
4025 * of an EPT paging-structure entry is 110b (write/execute).
4026 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4027 * spte.
4028 */
4029 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
4030}
4031
6aa8b732
AK		 4032/*
4033 * Sets up the vmcs for emulated real mode.
4034 */
8b9cf98c 4035static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4036{
2e4ce7f5 4037#ifdef CONFIG_X86_64
6aa8b732 4038 unsigned long a;
2e4ce7f5 4039#endif
6aa8b732 4040 int i;
6aa8b732 4041
6aa8b732 4042 /* I/O */
3e7c73e9
AK		 4043 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4044 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4045
25c5f225 4046 if (cpu_has_vmx_msr_bitmap())
5897297b 4047 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4048
6aa8b732
AK		 4049 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4050
6aa8b732 4051 /* Control */
01e439be 4052 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4053
bf8179a0 4054 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4055
83ff3b9d 4056 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4057 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4058 vmx_secondary_exec_control(vmx));
83ff3b9d 4059 }
f78e0e2e 4060
01e439be 4061 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4062 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4063 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4064 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4065 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4066
4067 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4068
4069 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4070 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4071 }
4072
4b8d54f9
ZE		 4073 if (ple_gap) {
4074 vmcs_write32(PLE_GAP, ple_gap);
4075 vmcs_write32(PLE_WINDOW, ple_window);
4076 }
4077
c3707958
XG		 4078 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4079 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4080 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4081
9581d442
AK		 4082 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4083 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4084 vmx_set_constant_host_state(vmx);
05b3e0c2 4085#ifdef CONFIG_X86_64
6aa8b732
AK		 4086 rdmsrl(MSR_FS_BASE, a);
4087 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4088 rdmsrl(MSR_GS_BASE, a);
4089 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4090#else
4091 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4092 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4093#endif
4094
2cc51560
ED		 4095 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4096 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4097 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4098 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4099 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4100
468d472f 4101 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4102 u32 msr_low, msr_high;
4103 u64 host_pat;
468d472f
SY		 4104 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4105 host_pat = msr_low | ((u64) msr_high << 32);
4106 /* Write the default value follow host pat */
4107 vmcs_write64(GUEST_IA32_PAT, host_pat);
4108 /* Keep arch.pat sync with GUEST_IA32_PAT */
4109 vmx->vcpu.arch.pat = host_pat;
4110 }
4111
6aa8b732
AK		 4112 for (i = 0; i < NR_VMX_MSR; ++i) {
4113 u32 index = vmx_msr_index[i];
4114 u32 data_low, data_high;
a2fa3e9f 4115 int j = vmx->nmsrs;
6aa8b732
AK		 4116
4117 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4118 continue;
432bd6cb
AK		 4119 if (wrmsr_safe(index, data_low, data_high) < 0)
4120 continue;
26bb0981
AK		 4121 vmx->guest_msrs[j].index = i;
4122 vmx->guest_msrs[j].data = 0;
d5696725 4123 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4124 ++vmx->nmsrs;
6aa8b732 4125 }
6aa8b732 4126
1c3d14fe 4127 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4128
4129 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4130 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4131
e00c8cf2 4132 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4133 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4134
4135 return 0;
4136}
4137
57f252f2 4138static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4139{
4140 struct vcpu_vmx *vmx = to_vmx(vcpu);
4141 u64 msr;
e00c8cf2 4142
7ffd92c5 4143 vmx->rmode.vm86_active = 0;
e00c8cf2 4144
3b86cd99
JK		 4145 vmx->soft_vnmi_blocked = 0;
4146
ad312c7c 4147 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4148 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4149 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4150 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4151 msr |= MSR_IA32_APICBASE_BSP;
4152 kvm_set_apic_base(&vmx->vcpu, msr);
4153
2fb92db1
AK		 4154 vmx_segment_cache_clear(vmx);
4155
5706be0d 4156 seg_setup(VCPU_SREG_CS);
66450a21 4157 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4158 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4159
4160 seg_setup(VCPU_SREG_DS);
4161 seg_setup(VCPU_SREG_ES);
4162 seg_setup(VCPU_SREG_FS);
4163 seg_setup(VCPU_SREG_GS);
4164 seg_setup(VCPU_SREG_SS);
4165
4166 vmcs_write16(GUEST_TR_SELECTOR, 0);
4167 vmcs_writel(GUEST_TR_BASE, 0);
4168 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4169 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4170
4171 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4172 vmcs_writel(GUEST_LDTR_BASE, 0);
4173 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4174 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4175
4176 vmcs_write32(GUEST_SYSENTER_CS, 0);
4177 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4178 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4179
4180 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4181 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4182
e00c8cf2
AK		 4183 vmcs_writel(GUEST_GDTR_BASE, 0);
4184 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4185
4186 vmcs_writel(GUEST_IDTR_BASE, 0);
4187 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4188
443381a8 4189 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4190 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4191 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4192
e00c8cf2
AK		 4193 /* Special registers */
4194 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4195
4196 setup_msrs(vmx);
4197
6aa8b732
AK		 4198 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4199
f78e0e2e
SY		 4200 if (cpu_has_vmx_tpr_shadow()) {
4201 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4202 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4203 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4204 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4205 vmcs_write32(TPR_THRESHOLD, 0);
4206 }
4207
4208 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4209 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4210 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4211
01e439be
YZ		 4212 if (vmx_vm_has_apicv(vcpu->kvm))
4213 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4214
2384d2b3
SY		 4215 if (vmx->vpid != 0)
4216 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4217
fa40052c 4218 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4219 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4220 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4221 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4222 vmx_fpu_activate(&vmx->vcpu);
4223 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4224
b9d762fa 4225 vpid_sync_context(vmx);
6aa8b732
AK		 4226}
4227
b6f1250e
NHE		 4228/*
4229 * In nested virtualization, check if L1 asked to exit on external interrupts.
4230 * For most existing hypervisors, this will always return true.
4231 */
4232static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4233{
4234 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4235 PIN_BASED_EXT_INTR_MASK;
4236}
4237
3b86cd99
JK		 4238static void enable_irq_window(struct kvm_vcpu *vcpu)
4239{
4240 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4241 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4242 /*
4243 * We get here if vmx_interrupt_allowed() said we can't
4244 * inject to L1 now because L2 must run. Ask L2 to exit
4245 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4246 */
d6185f20 4247 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4248 return;
d6185f20 4249 }
3b86cd99
JK		 4250
4251 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4252 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4253 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4254}
4255
4256static void enable_nmi_window(struct kvm_vcpu *vcpu)
4257{
4258 u32 cpu_based_vm_exec_control;
4259
4260 if (!cpu_has_virtual_nmis()) {
4261 enable_irq_window(vcpu);
4262 return;
4263 }
4264
30bd0c4c
AK		 4265 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4266 enable_irq_window(vcpu);
4267 return;
4268 }
3b86cd99
JK		 4269 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4270 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4271 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4272}
4273
66fd3f7f 4274static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4275{
9c8cba37 4276 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4277 uint32_t intr;
4278 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4279
229456fc 4280 trace_kvm_inj_virq(irq);
2714d1d3 4281
fa89a817 4282 ++vcpu->stat.irq_injections;
7ffd92c5 4283 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4284 int inc_eip = 0;
4285 if (vcpu->arch.interrupt.soft)
4286 inc_eip = vcpu->arch.event_exit_inst_len;
4287 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4288 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4289 return;
4290 }
66fd3f7f
GN		 4291 intr = irq | INTR_INFO_VALID_MASK;
4292 if (vcpu->arch.interrupt.soft) {
4293 intr |= INTR_TYPE_SOFT_INTR;
4294 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4295 vmx->vcpu.arch.event_exit_inst_len);
4296 } else
4297 intr |= INTR_TYPE_EXT_INTR;
4298 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4299}
4300
f08864b4
SY		 4301static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4302{
66a5a347
JK		 4303 struct vcpu_vmx *vmx = to_vmx(vcpu);
4304
0b6ac343
NHE		 4305 if (is_guest_mode(vcpu))
4306 return;
4307
3b86cd99
JK		 4308 if (!cpu_has_virtual_nmis()) {
4309 /*
4310 * Tracking the NMI-blocked state in software is built upon
4311 * finding the next open IRQ window. This, in turn, depends on
4312 * well-behaving guests: They have to keep IRQs disabled at
4313 * least as long as the NMI handler runs. Otherwise we may
4314 * cause NMI nesting, maybe breaking the guest. But as this is
4315 * highly unlikely, we can live with the residual risk.
4316 */
4317 vmx->soft_vnmi_blocked = 1;
4318 vmx->vnmi_blocked_time = 0;
4319 }
4320
487b391d 4321 ++vcpu->stat.nmi_injections;
9d58b931 4322 vmx->nmi_known_unmasked = false;
7ffd92c5 4323 if (vmx->rmode.vm86_active) {
71f9833b 4324 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4325 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4326 return;
4327 }
f08864b4
SY		 4328 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4329 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4330}
4331
c4282df9 4332static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4333{
3b86cd99 4334 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4335 return 0;
33f089ca 4336
c4282df9 4337 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4338 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4339 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4340}
4341
3cfc3092
JK		 4342static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4343{
4344 if (!cpu_has_virtual_nmis())
4345 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4346 if (to_vmx(vcpu)->nmi_known_unmasked)
4347 return false;
c332c83a 4348 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4349}
4350
4351static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4352{
4353 struct vcpu_vmx *vmx = to_vmx(vcpu);
4354
4355 if (!cpu_has_virtual_nmis()) {
4356 if (vmx->soft_vnmi_blocked != masked) {
4357 vmx->soft_vnmi_blocked = masked;
4358 vmx->vnmi_blocked_time = 0;
4359 }
4360 } else {
9d58b931 4361 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4362 if (masked)
4363 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4364 GUEST_INTR_STATE_NMI);
4365 else
4366 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4367 GUEST_INTR_STATE_NMI);
4368 }
4369}
4370
78646121
GN		 4371static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4372{
e8457c67 4373 if (is_guest_mode(vcpu)) {
51cfe38e 4374 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4375
4376 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4377 return 0;
e8457c67
JK		 4378 if (nested_exit_on_intr(vcpu)) {
4379 nested_vmx_vmexit(vcpu);
4380 vmcs12->vm_exit_reason =
4381 EXIT_REASON_EXTERNAL_INTERRUPT;
4382 vmcs12->vm_exit_intr_info = 0;
4383 /*
4384 * fall through to normal code, but now in L1, not L2
4385 */
4386 }
b6f1250e
NHE		 4387 }
4388
c4282df9
GN		 4389 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4390 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4391 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4392}
4393
cbc94022
IE		 4394static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4395{
4396 int ret;
4397 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4398 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4399 .guest_phys_addr = addr,
4400 .memory_size = PAGE_SIZE * 3,
4401 .flags = 0,
4402 };
4403
47ae31e2 4404 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4405 if (ret)
4406 return ret;
bfc6d222 4407 kvm->arch.tss_addr = addr;
93ea5388
GN		 4408 if (!init_rmode_tss(kvm))
4409 return -ENOMEM;
4410
cbc94022
IE		 4411 return 0;
4412}
4413
0ca1b4f4 4414static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4415{
77ab6db0 4416 switch (vec) {
77ab6db0 4417 case BP_VECTOR:
c573cd22
JK		 4418 /*
4419 * Update instruction length as we may reinject the exception
4420 * from user space while in guest debugging mode.
4421 */
4422 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4423 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4424 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4425 return false;
4426 /* fall through */
4427 case DB_VECTOR:
4428 if (vcpu->guest_debug &
4429 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4430 return false;
d0bfb940
JK		 4431 /* fall through */
4432 case DE_VECTOR:
77ab6db0
JK		 4433 case OF_VECTOR:
4434 case BR_VECTOR:
4435 case UD_VECTOR:
4436 case DF_VECTOR:
4437 case SS_VECTOR:
4438 case GP_VECTOR:
4439 case MF_VECTOR:
0ca1b4f4
GN		 4440 return true;
4441 break;
77ab6db0 4442 }
0ca1b4f4
GN		 4443 return false;
4444}
4445
4446static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4447 int vec, u32 err_code)
4448{
4449 /*
4450 * Instruction with address size override prefix opcode 0x67
4451 * Cause the #SS fault with 0 error code in VM86 mode.
4452 */
4453 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4454 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4455 if (vcpu->arch.halt_request) {
4456 vcpu->arch.halt_request = 0;
4457 return kvm_emulate_halt(vcpu);
4458 }
4459 return 1;
4460 }
4461 return 0;
4462 }
4463
4464 /*
4465 * Forward all other exceptions that are valid in real mode.
4466 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4467 * the required debugging infrastructure rework.
4468 */
4469 kvm_queue_exception(vcpu, vec);
4470 return 1;
6aa8b732
AK		 4471}
4472
a0861c02
AK		 4473/*
4474 * Trigger machine check on the host. We assume all the MSRs are already set up
4475 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4476 * We pass a fake environment to the machine check handler because we want
4477 * the guest to be always treated like user space, no matter what context
4478 * it used internally.
4479 */
4480static void kvm_machine_check(void)
4481{
4482#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4483 struct pt_regs regs = {
4484 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4485 .flags = X86_EFLAGS_IF,
4486 };
4487
4488 do_machine_check(&regs, 0);
4489#endif
4490}
4491
851ba692 4492static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4493{
4494 /* already handled by vcpu_run */
4495 return 1;
4496}
4497
851ba692 4498static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4499{
1155f76a 4500 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4501 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4502 u32 intr_info, ex_no, error_code;
42dbaa5a 4503 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4504 u32 vect_info;
4505 enum emulation_result er;
4506
1155f76a 4507 vect_info = vmx->idt_vectoring_info;
88786475 4508 intr_info = vmx->exit_intr_info;
6aa8b732 4509
a0861c02 4510 if (is_machine_check(intr_info))
851ba692 4511 return handle_machine_check(vcpu);
a0861c02 4512
e4a41889 4513 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4514 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4515
4516 if (is_no_device(intr_info)) {
5fd86fcf 4517 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4518 return 1;
4519 }
4520
7aa81cc0 4521 if (is_invalid_opcode(intr_info)) {
51d8b661 4522 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4523 if (er != EMULATE_DONE)
7ee5d940 4524 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4525 return 1;
4526 }
4527
6aa8b732 4528 error_code = 0;
2e11384c 4529 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4530 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4531
4532 /*
4533 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4534 * MMIO, it is better to report an internal error.
4535 * See the comments in vmx_handle_exit.
4536 */
4537 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4538 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4539 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4540 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4541 vcpu->run->internal.ndata = 2;
4542 vcpu->run->internal.data[0] = vect_info;
4543 vcpu->run->internal.data[1] = intr_info;
4544 return 0;
4545 }
4546
6aa8b732 4547 if (is_page_fault(intr_info)) {
1439442c 4548 /* EPT won't cause page fault directly */
cf3ace79 4549 BUG_ON(enable_ept);
6aa8b732 4550 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4551 trace_kvm_page_fault(cr2, error_code);
4552
3298b75c 4553 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4554 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4555 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4556 }
4557
d0bfb940 4558 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4559
4560 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4561 return handle_rmode_exception(vcpu, ex_no, error_code);
4562
42dbaa5a
JK		 4563 switch (ex_no) {
4564 case DB_VECTOR:
4565 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4566 if (!(vcpu->guest_debug &
4567 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4568 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4569 kvm_queue_exception(vcpu, DB_VECTOR);
4570 return 1;
4571 }
4572 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4573 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4574 /* fall through */
4575 case BP_VECTOR:
c573cd22
JK		 4576 /*
4577 * Update instruction length as we may reinject #BP from
4578 * user space while in guest debugging mode. Reading it for
4579 * #DB as well causes no harm, it is not used in that case.
4580 */
4581 vmx->vcpu.arch.event_exit_inst_len =
4582 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4583 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4584 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4585 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4586 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4587 break;
4588 default:
d0bfb940
JK		 4589 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4590 kvm_run->ex.exception = ex_no;
4591 kvm_run->ex.error_code = error_code;
42dbaa5a 4592 break;
6aa8b732 4593 }
6aa8b732
AK		 4594 return 0;
4595}
4596
851ba692 4597static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4598{
1165f5fe 4599 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4600 return 1;
4601}
4602
851ba692 4603static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4604{
851ba692 4605 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4606 return 0;
4607}
6aa8b732 4608
851ba692 4609static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4610{
bfdaab09 4611 unsigned long exit_qualification;
34c33d16 4612 int size, in, string;
039576c0 4613 unsigned port;
6aa8b732 4614
bfdaab09 4615 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4616 string = (exit_qualification & 16) != 0;
cf8f70bf 4617 in = (exit_qualification & 8) != 0;
e70669ab 4618
cf8f70bf 4619 ++vcpu->stat.io_exits;
e70669ab 4620
cf8f70bf 4621 if (string || in)
51d8b661 4622 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4623
cf8f70bf
GN		 4624 port = exit_qualification >> 16;
4625 size = (exit_qualification & 7) + 1;
e93f36bc 4626 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4627
4628 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4629}
4630
102d8325
IM		 4631static void
4632vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4633{
4634 /*
4635 * Patch in the VMCALL instruction:
4636 */
4637 hypercall[0] = 0x0f;
4638 hypercall[1] = 0x01;
4639 hypercall[2] = 0xc1;
102d8325
IM		 4640}
4641
0fa06071 4642/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4643static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4644{
eeadf9e7 4645 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4646 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4647 unsigned long orig_val = val;
4648
eeadf9e7
NHE		 4649 /*
4650 * We get here when L2 changed cr0 in a way that did not change
4651 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4652 * but did change L0 shadowed bits. So we first calculate the
4653 * effective cr0 value that L1 would like to write into the
4654 * hardware. It consists of the L2-owned bits from the new
4655 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4656 */
1a0d74e6
JK		 4657 val = (val & ~vmcs12->cr0_guest_host_mask) |
4658 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4659
4660 /* TODO: will have to take unrestricted guest mode into
4661 * account */
4662 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4663 return 1;
1a0d74e6
JK		 4664
4665 if (kvm_set_cr0(vcpu, val))
4666 return 1;
4667 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4668 return 0;
1a0d74e6
JK		 4669 } else {
4670 if (to_vmx(vcpu)->nested.vmxon &&
4671 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4672 return 1;
eeadf9e7 4673 return kvm_set_cr0(vcpu, val);
1a0d74e6 4674 }
eeadf9e7
NHE		 4675}
4676
4677static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4678{
4679 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4680 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4681 unsigned long orig_val = val;
4682
4683 /* analogously to handle_set_cr0 */
4684 val = (val & ~vmcs12->cr4_guest_host_mask) |
4685 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4686 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4687 return 1;
1a0d74e6 4688 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4689 return 0;
4690 } else
4691 return kvm_set_cr4(vcpu, val);
4692}
4693
4694/* called to set cr0 as approriate for clts instruction exit. */
4695static void handle_clts(struct kvm_vcpu *vcpu)
4696{
4697 if (is_guest_mode(vcpu)) {
4698 /*
4699 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4700 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4701 * just pretend it's off (also in arch.cr0 for fpu_activate).
4702 */
4703 vmcs_writel(CR0_READ_SHADOW,
4704 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4705 vcpu->arch.cr0 &= ~X86_CR0_TS;
4706 } else
4707 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4708}
4709
851ba692 4710static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4711{
229456fc 4712 unsigned long exit_qualification, val;
6aa8b732
AK		 4713 int cr;
4714 int reg;
49a9b07e 4715 int err;
6aa8b732 4716
bfdaab09 4717 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4718 cr = exit_qualification & 15;
4719 reg = (exit_qualification >> 8) & 15;
4720 switch ((exit_qualification >> 4) & 3) {
4721 case 0: /* mov to cr */
229456fc
MT		 4722 val = kvm_register_read(vcpu, reg);
4723 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4724 switch (cr) {
4725 case 0:
eeadf9e7 4726 err = handle_set_cr0(vcpu, val);
db8fcefa 4727 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4728 return 1;
4729 case 3:
2390218b 4730 err = kvm_set_cr3(vcpu, val);
db8fcefa 4731 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4732 return 1;
4733 case 4:
eeadf9e7 4734 err = handle_set_cr4(vcpu, val);
db8fcefa 4735 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4736 return 1;
0a5fff19
GN		 4737 case 8: {
4738 u8 cr8_prev = kvm_get_cr8(vcpu);
4739 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4740 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4741 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4742 if (irqchip_in_kernel(vcpu->kvm))
4743 return 1;
4744 if (cr8_prev <= cr8)
4745 return 1;
851ba692 4746 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4747 return 0;
4748 }
4b8073e4 4749 }
6aa8b732 4750 break;
25c4c276 4751 case 2: /* clts */
eeadf9e7 4752 handle_clts(vcpu);
4d4ec087 4753 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4754 skip_emulated_instruction(vcpu);
6b52d186 4755 vmx_fpu_activate(vcpu);
25c4c276 4756 return 1;
6aa8b732
AK		 4757 case 1: /*mov from cr*/
4758 switch (cr) {
4759 case 3:
9f8fe504
AK		 4760 val = kvm_read_cr3(vcpu);
4761 kvm_register_write(vcpu, reg, val);
4762 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4763 skip_emulated_instruction(vcpu);
4764 return 1;
4765 case 8:
229456fc
MT		 4766 val = kvm_get_cr8(vcpu);
4767 kvm_register_write(vcpu, reg, val);
4768 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4769 skip_emulated_instruction(vcpu);
4770 return 1;
4771 }
4772 break;
4773 case 3: /* lmsw */
a1f83a74 4774 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4775 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4776 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4777
4778 skip_emulated_instruction(vcpu);
4779 return 1;
4780 default:
4781 break;
4782 }
851ba692 4783 vcpu->run->exit_reason = 0;
a737f256 4784 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4785 (int)(exit_qualification >> 4) & 3, cr);
4786 return 0;
4787}
4788
851ba692 4789static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4790{
bfdaab09 4791 unsigned long exit_qualification;
6aa8b732
AK		 4792 int dr, reg;
4793
f2483415 4794 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4795 if (!kvm_require_cpl(vcpu, 0))
4796 return 1;
42dbaa5a
JK		 4797 dr = vmcs_readl(GUEST_DR7);
4798 if (dr & DR7_GD) {
4799 /*
4800 * As the vm-exit takes precedence over the debug trap, we
4801 * need to emulate the latter, either for the host or the
4802 * guest debugging itself.
4803 */
4804 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4805 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4806 vcpu->run->debug.arch.dr7 = dr;
4807 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4808 vmcs_readl(GUEST_CS_BASE) +
4809 vmcs_readl(GUEST_RIP);
851ba692
AK		 4810 vcpu->run->debug.arch.exception = DB_VECTOR;
4811 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4812 return 0;
4813 } else {
4814 vcpu->arch.dr7 &= ~DR7_GD;
4815 vcpu->arch.dr6 |= DR6_BD;
4816 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4817 kvm_queue_exception(vcpu, DB_VECTOR);
4818 return 1;
4819 }
4820 }
4821
bfdaab09 4822 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4823 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4824 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4825 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4826 unsigned long val;
4827 if (!kvm_get_dr(vcpu, dr, &val))
4828 kvm_register_write(vcpu, reg, val);
4829 } else
4830 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4831 skip_emulated_instruction(vcpu);
4832 return 1;
4833}
4834
020df079
GN		 4835static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4836{
4837 vmcs_writel(GUEST_DR7, val);
4838}
4839
851ba692 4840static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4841{
06465c5a
AK		 4842 kvm_emulate_cpuid(vcpu);
4843 return 1;
6aa8b732
AK		 4844}
4845
851ba692 4846static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4847{
ad312c7c 4848 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4849 u64 data;
4850
4851 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4852 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4853 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4854 return 1;
4855 }
4856
229456fc 4857 trace_kvm_msr_read(ecx, data);
2714d1d3 4858
6aa8b732 4859 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4860 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4861 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4862 skip_emulated_instruction(vcpu);
4863 return 1;
4864}
4865
851ba692 4866static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4867{
8fe8ab46 4868 struct msr_data msr;
ad312c7c
ZX		 4869 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4870 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4871 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4872
8fe8ab46
WA		 4873 msr.data = data;
4874 msr.index = ecx;
4875 msr.host_initiated = false;
4876 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4877 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4878 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4879 return 1;
4880 }
4881
59200273 4882 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4883 skip_emulated_instruction(vcpu);
4884 return 1;
4885}
4886
851ba692 4887static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4888{
3842d135 4889 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4890 return 1;
4891}
4892
851ba692 4893static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4894{
85f455f7
ED		 4895 u32 cpu_based_vm_exec_control;
4896
4897 /* clear pending irq */
4898 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4899 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4900 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4901
3842d135
AK		 4902 kvm_make_request(KVM_REQ_EVENT, vcpu);
4903
a26bf12a 4904 ++vcpu->stat.irq_window_exits;
2714d1d3 4905
c1150d8c
DL		 4906 /*
4907 * If the user space waits to inject interrupts, exit as soon as
4908 * possible
4909 */
8061823a 4910 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4911 vcpu->run->request_interrupt_window &&
8061823a 4912 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4913 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4914 return 0;
4915 }
6aa8b732
AK		 4916 return 1;
4917}
4918
851ba692 4919static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4920{
4921 skip_emulated_instruction(vcpu);
d3bef15f 4922 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4923}
4924
851ba692 4925static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4926{
510043da 4927 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4928 kvm_emulate_hypercall(vcpu);
4929 return 1;
c21415e8
IM		 4930}
4931
ec25d5e6
GN		 4932static int handle_invd(struct kvm_vcpu *vcpu)
4933{
51d8b661 4934 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4935}
4936
851ba692 4937static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4938{
f9c617f6 4939 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4940
4941 kvm_mmu_invlpg(vcpu, exit_qualification);
4942 skip_emulated_instruction(vcpu);
4943 return 1;
4944}
4945
fee84b07
AK		 4946static int handle_rdpmc(struct kvm_vcpu *vcpu)
4947{
4948 int err;
4949
4950 err = kvm_rdpmc(vcpu);
4951 kvm_complete_insn_gp(vcpu, err);
4952
4953 return 1;
4954}
4955
851ba692 4956static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4957{
4958 skip_emulated_instruction(vcpu);
f5f48ee1 4959 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4960 return 1;
4961}
4962
2acf923e
DC		 4963static int handle_xsetbv(struct kvm_vcpu *vcpu)
4964{
4965 u64 new_bv = kvm_read_edx_eax(vcpu);
4966 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4967
4968 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4969 skip_emulated_instruction(vcpu);
4970 return 1;
4971}
4972
851ba692 4973static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4974{
58fbbf26
KT		 4975 if (likely(fasteoi)) {
4976 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4977 int access_type, offset;
4978
4979 access_type = exit_qualification & APIC_ACCESS_TYPE;
4980 offset = exit_qualification & APIC_ACCESS_OFFSET;
4981 /*
4982 * Sane guest uses MOV to write EOI, with written value
4983 * not cared. So make a short-circuit here by avoiding
4984 * heavy instruction emulation.
4985 */
4986 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4987 (offset == APIC_EOI)) {
4988 kvm_lapic_set_eoi(vcpu);
4989 skip_emulated_instruction(vcpu);
4990 return 1;
4991 }
4992 }
51d8b661 4993 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4994}
4995
c7c9c56c
YZ		 4996static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4997{
4998 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4999 int vector = exit_qualification & 0xff;
5000
5001 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5002 kvm_apic_set_eoi_accelerated(vcpu, vector);
5003 return 1;
5004}
5005
83d4c286
YZ		 5006static int handle_apic_write(struct kvm_vcpu *vcpu)
5007{
5008 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5009 u32 offset = exit_qualification & 0xfff;
5010
5011 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5012 kvm_apic_write_nodecode(vcpu, offset);
5013 return 1;
5014}
5015
851ba692 5016static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5017{
60637aac 5018 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5019 unsigned long exit_qualification;
e269fb21
JK		 5020 bool has_error_code = false;
5021 u32 error_code = 0;
37817f29 5022 u16 tss_selector;
7f3d35fd 5023 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5024
5025 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5026 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5027 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5028
5029 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5030
5031 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5032 if (reason == TASK_SWITCH_GATE && idt_v) {
5033 switch (type) {
5034 case INTR_TYPE_NMI_INTR:
5035 vcpu->arch.nmi_injected = false;
654f06fc 5036 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5037 break;
5038 case INTR_TYPE_EXT_INTR:
66fd3f7f 5039 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5040 kvm_clear_interrupt_queue(vcpu);
5041 break;
5042 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5043 if (vmx->idt_vectoring_info &
5044 VECTORING_INFO_DELIVER_CODE_MASK) {
5045 has_error_code = true;
5046 error_code =
5047 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5048 }
5049 /* fall through */
64a7ec06
GN		 5050 case INTR_TYPE_SOFT_EXCEPTION:
5051 kvm_clear_exception_queue(vcpu);
5052 break;
5053 default:
5054 break;
5055 }
60637aac 5056 }
37817f29
IE		 5057 tss_selector = exit_qualification;
5058
64a7ec06
GN		 5059 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5060 type != INTR_TYPE_EXT_INTR &&
5061 type != INTR_TYPE_NMI_INTR))
5062 skip_emulated_instruction(vcpu);
5063
7f3d35fd
KW		 5064 if (kvm_task_switch(vcpu, tss_selector,
5065 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5066 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5067 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5068 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5069 vcpu->run->internal.ndata = 0;
42dbaa5a 5070 return 0;
acb54517 5071 }
42dbaa5a
JK		 5072
5073 /* clear all local breakpoint enable flags */
5074 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5075
5076 /*
5077 * TODO: What about debug traps on tss switch?
5078 * Are we supposed to inject them and update dr6?
5079 */
5080
5081 return 1;
37817f29
IE		 5082}
5083
851ba692 5084static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5085{
f9c617f6 5086 unsigned long exit_qualification;
1439442c 5087 gpa_t gpa;
4f5982a5 5088 u32 error_code;
1439442c 5089 int gla_validity;
1439442c 5090
f9c617f6 5091 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5092
1439442c
SY		 5093 gla_validity = (exit_qualification >> 7) & 0x3;
5094 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5095 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5096 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5097 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5098 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5099 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5100 (long unsigned int)exit_qualification);
851ba692
AK		 5101 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5102 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5103 return 0;
1439442c
SY		 5104 }
5105
5106 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5107 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5108
5109 /* It is a write fault? */
5110 error_code = exit_qualification & (1U << 1);
5111 /* ept page table is present? */
5112 error_code |= (exit_qualification >> 3) & 0x1;
5113
5114 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5115}
5116
68f89400
MT		 5117static u64 ept_rsvd_mask(u64 spte, int level)
5118{
5119 int i;
5120 u64 mask = 0;
5121
5122 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5123 mask |= (1ULL << i);
5124
5125 if (level > 2)
5126 /* bits 7:3 reserved */
5127 mask |= 0xf8;
5128 else if (level == 2) {
5129 if (spte & (1ULL << 7))
5130 /* 2MB ref, bits 20:12 reserved */
5131 mask |= 0x1ff000;
5132 else
5133 /* bits 6:3 reserved */
5134 mask |= 0x78;
5135 }
5136
5137 return mask;
5138}
5139
5140static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5141 int level)
5142{
5143 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5144
5145 /* 010b (write-only) */
5146 WARN_ON((spte & 0x7) == 0x2);
5147
5148 /* 110b (write/execute) */
5149 WARN_ON((spte & 0x7) == 0x6);
5150
5151 /* 100b (execute-only) and value not supported by logical processor */
5152 if (!cpu_has_vmx_ept_execute_only())
5153 WARN_ON((spte & 0x7) == 0x4);
5154
5155 /* not 000b */
5156 if ((spte & 0x7)) {
5157 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5158
5159 if (rsvd_bits != 0) {
5160 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5161 __func__, rsvd_bits);
5162 WARN_ON(1);
5163 }
5164
5165 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5166 u64 ept_mem_type = (spte & 0x38) >> 3;
5167
5168 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5169 ept_mem_type == 7) {
5170 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5171 __func__, ept_mem_type);
5172 WARN_ON(1);
5173 }
5174 }
5175 }
5176}
5177
851ba692 5178static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5179{
5180 u64 sptes[4];
ce88decf 5181 int nr_sptes, i, ret;
68f89400
MT		 5182 gpa_t gpa;
5183
5184 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5185
ce88decf
XG		 5186 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5187 if (likely(ret == 1))
5188 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5189 EMULATE_DONE;
5190 if (unlikely(!ret))
5191 return 1;
5192
5193 /* It is the real ept misconfig */
68f89400
MT		 5194 printk(KERN_ERR "EPT: Misconfiguration.\n");
5195 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5196
5197 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5198
5199 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5200 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5201
851ba692
AK		 5202 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5203 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5204
5205 return 0;
5206}
5207
851ba692 5208static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5209{
5210 u32 cpu_based_vm_exec_control;
5211
5212 /* clear pending NMI */
5213 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5214 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5215 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5216 ++vcpu->stat.nmi_window_exits;
3842d135 5217 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5218
5219 return 1;
5220}
5221
80ced186 5222static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5223{
8b3079a5
AK		 5224 struct vcpu_vmx *vmx = to_vmx(vcpu);
5225 enum emulation_result err = EMULATE_DONE;
80ced186 5226 int ret = 1;
49e9d557
AK		 5227 u32 cpu_exec_ctrl;
5228 bool intr_window_requested;
b8405c18 5229 unsigned count = 130;
49e9d557
AK		 5230
5231 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5232 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5233
b8405c18 5234 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5235 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5236 return handle_interrupt_window(&vmx->vcpu);
5237
de87dcdd
AK		 5238 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5239 return 1;
5240
991eebf9 5241 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5242
80ced186
MG		 5243 if (err == EMULATE_DO_MMIO) {
5244 ret = 0;
5245 goto out;
5246 }
1d5a4d9b 5247
de5f70e0
AK		 5248 if (err != EMULATE_DONE) {
5249 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5250 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5251 vcpu->run->internal.ndata = 0;
6d77dbfc 5252 return 0;
de5f70e0 5253 }
ea953ef0
MG		 5254
5255 if (signal_pending(current))
80ced186 5256 goto out;
ea953ef0
MG		 5257 if (need_resched())
5258 schedule();
5259 }
5260
14168786 5261 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5262out:
5263 return ret;
ea953ef0
MG		 5264}
5265
4b8d54f9
ZE		 5266/*
5267 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5268 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5269 */
9fb41ba8 5270static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5271{
5272 skip_emulated_instruction(vcpu);
5273 kvm_vcpu_on_spin(vcpu);
5274
5275 return 1;
5276}
5277
59708670
SY		 5278static int handle_invalid_op(struct kvm_vcpu *vcpu)
5279{
5280 kvm_queue_exception(vcpu, UD_VECTOR);
5281 return 1;
5282}
5283
ff2f6fe9
NHE		 5284/*
5285 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5286 * We could reuse a single VMCS for all the L2 guests, but we also want the
5287 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5288 * allows keeping them loaded on the processor, and in the future will allow
5289 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5290 * every entry if they never change.
5291 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5292 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5293 *
5294 * The following functions allocate and free a vmcs02 in this pool.
5295 */
5296
5297/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5298static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5299{
5300 struct vmcs02_list *item;
5301 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5302 if (item->vmptr == vmx->nested.current_vmptr) {
5303 list_move(&item->list, &vmx->nested.vmcs02_pool);
5304 return &item->vmcs02;
5305 }
5306
5307 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5308 /* Recycle the least recently used VMCS. */
5309 item = list_entry(vmx->nested.vmcs02_pool.prev,
5310 struct vmcs02_list, list);
5311 item->vmptr = vmx->nested.current_vmptr;
5312 list_move(&item->list, &vmx->nested.vmcs02_pool);
5313 return &item->vmcs02;
5314 }
5315
5316 /* Create a new VMCS */
0fa24ce3 5317 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5318 if (!item)
5319 return NULL;
5320 item->vmcs02.vmcs = alloc_vmcs();
5321 if (!item->vmcs02.vmcs) {
5322 kfree(item);
5323 return NULL;
5324 }
5325 loaded_vmcs_init(&item->vmcs02);
5326 item->vmptr = vmx->nested.current_vmptr;
5327 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5328 vmx->nested.vmcs02_num++;
5329 return &item->vmcs02;
5330}
5331
5332/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5333static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5334{
5335 struct vmcs02_list *item;
5336 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5337 if (item->vmptr == vmptr) {
5338 free_loaded_vmcs(&item->vmcs02);
5339 list_del(&item->list);
5340 kfree(item);
5341 vmx->nested.vmcs02_num--;
5342 return;
5343 }
5344}
5345
5346/*
5347 * Free all VMCSs saved for this vcpu, except the one pointed by
5348 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5349 * currently used, if running L2), and vmcs01 when running L2.
5350 */
5351static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5352{
5353 struct vmcs02_list *item, *n;
5354 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5355 if (vmx->loaded_vmcs != &item->vmcs02)
5356 free_loaded_vmcs(&item->vmcs02);
5357 list_del(&item->list);
5358 kfree(item);
5359 }
5360 vmx->nested.vmcs02_num = 0;
5361
5362 if (vmx->loaded_vmcs != &vmx->vmcs01)
5363 free_loaded_vmcs(&vmx->vmcs01);
5364}
5365
ec378aee
NHE		 5366/*
5367 * Emulate the VMXON instruction.
5368 * Currently, we just remember that VMX is active, and do not save or even
5369 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5370 * do not currently need to store anything in that guest-allocated memory
5371 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5372 * argument is different from the VMXON pointer (which the spec says they do).
5373 */
5374static int handle_vmon(struct kvm_vcpu *vcpu)
5375{
5376 struct kvm_segment cs;
5377 struct vcpu_vmx *vmx = to_vmx(vcpu);
5378
5379 /* The Intel VMX Instruction Reference lists a bunch of bits that
5380 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5381 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5382 * Otherwise, we should fail with #UD. We test these now:
5383 */
5384 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5385 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5386 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5387 kvm_queue_exception(vcpu, UD_VECTOR);
5388 return 1;
5389 }
5390
5391 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5392 if (is_long_mode(vcpu) && !cs.l) {
5393 kvm_queue_exception(vcpu, UD_VECTOR);
5394 return 1;
5395 }
5396
5397 if (vmx_get_cpl(vcpu)) {
5398 kvm_inject_gp(vcpu, 0);
5399 return 1;
5400 }
5401
ff2f6fe9
NHE		 5402 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5403 vmx->nested.vmcs02_num = 0;
5404
ec378aee
NHE		 5405 vmx->nested.vmxon = true;
5406
5407 skip_emulated_instruction(vcpu);
5408 return 1;
5409}
5410
5411/*
5412 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5413 * for running VMX instructions (except VMXON, whose prerequisites are
5414 * slightly different). It also specifies what exception to inject otherwise.
5415 */
5416static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5417{
5418 struct kvm_segment cs;
5419 struct vcpu_vmx *vmx = to_vmx(vcpu);
5420
5421 if (!vmx->nested.vmxon) {
5422 kvm_queue_exception(vcpu, UD_VECTOR);
5423 return 0;
5424 }
5425
5426 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5427 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5428 (is_long_mode(vcpu) && !cs.l)) {
5429 kvm_queue_exception(vcpu, UD_VECTOR);
5430 return 0;
5431 }
5432
5433 if (vmx_get_cpl(vcpu)) {
5434 kvm_inject_gp(vcpu, 0);
5435 return 0;
5436 }
5437
5438 return 1;
5439}
5440
5441/*
5442 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5443 * just stops using VMX.
5444 */
5445static void free_nested(struct vcpu_vmx *vmx)
5446{
5447 if (!vmx->nested.vmxon)
5448 return;
5449 vmx->nested.vmxon = false;
a9d30f33
NHE		 5450 if (vmx->nested.current_vmptr != -1ull) {
5451 kunmap(vmx->nested.current_vmcs12_page);
5452 nested_release_page(vmx->nested.current_vmcs12_page);
5453 vmx->nested.current_vmptr = -1ull;
5454 vmx->nested.current_vmcs12 = NULL;
5455 }
fe3ef05c
NHE		 5456 /* Unpin physical memory we referred to in current vmcs02 */
5457 if (vmx->nested.apic_access_page) {
5458 nested_release_page(vmx->nested.apic_access_page);
5459 vmx->nested.apic_access_page = 0;
5460 }
ff2f6fe9
NHE		 5461
5462 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5463}
5464
5465/* Emulate the VMXOFF instruction */
5466static int handle_vmoff(struct kvm_vcpu *vcpu)
5467{
5468 if (!nested_vmx_check_permission(vcpu))
5469 return 1;
5470 free_nested(to_vmx(vcpu));
5471 skip_emulated_instruction(vcpu);
5472 return 1;
5473}
5474
064aea77
NHE		 5475/*
5476 * Decode the memory-address operand of a vmx instruction, as recorded on an
5477 * exit caused by such an instruction (run by a guest hypervisor).
5478 * On success, returns 0. When the operand is invalid, returns 1 and throws
5479 * #UD or #GP.
5480 */
5481static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5482 unsigned long exit_qualification,
5483 u32 vmx_instruction_info, gva_t *ret)
5484{
5485 /*
5486 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5487 * Execution", on an exit, vmx_instruction_info holds most of the
5488 * addressing components of the operand. Only the displacement part
5489 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5490 * For how an actual address is calculated from all these components,
5491 * refer to Vol. 1, "Operand Addressing".
5492 */
5493 int scaling = vmx_instruction_info & 3;
5494 int addr_size = (vmx_instruction_info >> 7) & 7;
5495 bool is_reg = vmx_instruction_info & (1u << 10);
5496 int seg_reg = (vmx_instruction_info >> 15) & 7;
5497 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5498 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5499 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5500 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5501
5502 if (is_reg) {
5503 kvm_queue_exception(vcpu, UD_VECTOR);
5504 return 1;
5505 }
5506
5507 /* Addr = segment_base + offset */
5508 /* offset = base + [index * scale] + displacement */
5509 *ret = vmx_get_segment_base(vcpu, seg_reg);
5510 if (base_is_valid)
5511 *ret += kvm_register_read(vcpu, base_reg);
5512 if (index_is_valid)
5513 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5514 *ret += exit_qualification; /* holds the displacement */
5515
5516 if (addr_size == 1) /* 32 bit */
5517 *ret &= 0xffffffff;
5518
5519 /*
5520 * TODO: throw #GP (and return 1) in various cases that the VM*
5521 * instructions require it - e.g., offset beyond segment limit,
5522 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5523 * address, and so on. Currently these are not checked.
5524 */
5525 return 0;
5526}
5527
0140caea
NHE		 5528/*
5529 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5530 * set the success or error code of an emulated VMX instruction, as specified
5531 * by Vol 2B, VMX Instruction Reference, "Conventions".
5532 */
5533static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5534{
5535 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5536 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5537 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5538}
5539
5540static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5541{
5542 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5543 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5544 X86_EFLAGS_SF | X86_EFLAGS_OF))
5545 | X86_EFLAGS_CF);
5546}
5547
5548static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5549 u32 vm_instruction_error)
5550{
5551 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5552 /*
5553 * failValid writes the error number to the current VMCS, which
5554 * can't be done there isn't a current VMCS.
5555 */
5556 nested_vmx_failInvalid(vcpu);
5557 return;
5558 }
5559 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5560 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5561 X86_EFLAGS_SF | X86_EFLAGS_OF))
5562 | X86_EFLAGS_ZF);
5563 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5564}
5565
27d6c865
NHE		 5566/* Emulate the VMCLEAR instruction */
5567static int handle_vmclear(struct kvm_vcpu *vcpu)
5568{
5569 struct vcpu_vmx *vmx = to_vmx(vcpu);
5570 gva_t gva;
5571 gpa_t vmptr;
5572 struct vmcs12 *vmcs12;
5573 struct page *page;
5574 struct x86_exception e;
5575
5576 if (!nested_vmx_check_permission(vcpu))
5577 return 1;
5578
5579 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5580 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5581 return 1;
5582
5583 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5584 sizeof(vmptr), &e)) {
5585 kvm_inject_page_fault(vcpu, &e);
5586 return 1;
5587 }
5588
5589 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5590 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5591 skip_emulated_instruction(vcpu);
5592 return 1;
5593 }
5594
5595 if (vmptr == vmx->nested.current_vmptr) {
5596 kunmap(vmx->nested.current_vmcs12_page);
5597 nested_release_page(vmx->nested.current_vmcs12_page);
5598 vmx->nested.current_vmptr = -1ull;
5599 vmx->nested.current_vmcs12 = NULL;
5600 }
5601
5602 page = nested_get_page(vcpu, vmptr);
5603 if (page == NULL) {
5604 /*
5605 * For accurate processor emulation, VMCLEAR beyond available
5606 * physical memory should do nothing at all. However, it is
5607 * possible that a nested vmx bug, not a guest hypervisor bug,
5608 * resulted in this case, so let's shut down before doing any
5609 * more damage:
5610 */
5611 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5612 return 1;
5613 }
5614 vmcs12 = kmap(page);
5615 vmcs12->launch_state = 0;
5616 kunmap(page);
5617 nested_release_page(page);
5618
5619 nested_free_vmcs02(vmx, vmptr);
5620
5621 skip_emulated_instruction(vcpu);
5622 nested_vmx_succeed(vcpu);
5623 return 1;
5624}
5625
cd232ad0
NHE		 5626static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5627
5628/* Emulate the VMLAUNCH instruction */
5629static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5630{
5631 return nested_vmx_run(vcpu, true);
5632}
5633
5634/* Emulate the VMRESUME instruction */
5635static int handle_vmresume(struct kvm_vcpu *vcpu)
5636{
5637
5638 return nested_vmx_run(vcpu, false);
5639}
5640
49f705c5
NHE		 5641enum vmcs_field_type {
5642 VMCS_FIELD_TYPE_U16 = 0,
5643 VMCS_FIELD_TYPE_U64 = 1,
5644 VMCS_FIELD_TYPE_U32 = 2,
5645 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5646};
5647
5648static inline int vmcs_field_type(unsigned long field)
5649{
5650 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5651 return VMCS_FIELD_TYPE_U32;
5652 return (field >> 13) & 0x3 ;
5653}
5654
5655static inline int vmcs_field_readonly(unsigned long field)
5656{
5657 return (((field >> 10) & 0x3) == 1);
5658}
5659
5660/*
5661 * Read a vmcs12 field. Since these can have varying lengths and we return
5662 * one type, we chose the biggest type (u64) and zero-extend the return value
5663 * to that size. Note that the caller, handle_vmread, might need to use only
5664 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5665 * 64-bit fields are to be returned).
5666 */
5667static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5668 unsigned long field, u64 *ret)
5669{
5670 short offset = vmcs_field_to_offset(field);
5671 char *p;
5672
5673 if (offset < 0)
5674 return 0;
5675
5676 p = ((char *)(get_vmcs12(vcpu))) + offset;
5677
5678 switch (vmcs_field_type(field)) {
5679 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5680 *ret = *((natural_width *)p);
5681 return 1;
5682 case VMCS_FIELD_TYPE_U16:
5683 *ret = *((u16 *)p);
5684 return 1;
5685 case VMCS_FIELD_TYPE_U32:
5686 *ret = *((u32 *)p);
5687 return 1;
5688 case VMCS_FIELD_TYPE_U64:
5689 *ret = *((u64 *)p);
5690 return 1;
5691 default:
5692 return 0; /* can never happen. */
5693 }
5694}
5695
5696/*
5697 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5698 * used before) all generate the same failure when it is missing.
5699 */
5700static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5701{
5702 struct vcpu_vmx *vmx = to_vmx(vcpu);
5703 if (vmx->nested.current_vmptr == -1ull) {
5704 nested_vmx_failInvalid(vcpu);
5705 skip_emulated_instruction(vcpu);
5706 return 0;
5707 }
5708 return 1;
5709}
5710
5711static int handle_vmread(struct kvm_vcpu *vcpu)
5712{
5713 unsigned long field;
5714 u64 field_value;
5715 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5716 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5717 gva_t gva = 0;
5718
5719 if (!nested_vmx_check_permission(vcpu) ||
5720 !nested_vmx_check_vmcs12(vcpu))
5721 return 1;
5722
5723 /* Decode instruction info and find the field to read */
5724 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5725 /* Read the field, zero-extended to a u64 field_value */
5726 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5727 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5728 skip_emulated_instruction(vcpu);
5729 return 1;
5730 }
5731 /*
5732 * Now copy part of this value to register or memory, as requested.
5733 * Note that the number of bits actually copied is 32 or 64 depending
5734 * on the guest's mode (32 or 64 bit), not on the given field's length.
5735 */
5736 if (vmx_instruction_info & (1u << 10)) {
5737 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5738 field_value);
5739 } else {
5740 if (get_vmx_mem_address(vcpu, exit_qualification,
5741 vmx_instruction_info, &gva))
5742 return 1;
5743 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5744 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5745 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5746 }
5747
5748 nested_vmx_succeed(vcpu);
5749 skip_emulated_instruction(vcpu);
5750 return 1;
5751}
5752
5753
5754static int handle_vmwrite(struct kvm_vcpu *vcpu)
5755{
5756 unsigned long field;
5757 gva_t gva;
5758 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5759 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5760 char *p;
5761 short offset;
5762 /* The value to write might be 32 or 64 bits, depending on L1's long
5763 * mode, and eventually we need to write that into a field of several
5764 * possible lengths. The code below first zero-extends the value to 64
5765 * bit (field_value), and then copies only the approriate number of
5766 * bits into the vmcs12 field.
5767 */
5768 u64 field_value = 0;
5769 struct x86_exception e;
5770
5771 if (!nested_vmx_check_permission(vcpu) ||
5772 !nested_vmx_check_vmcs12(vcpu))
5773 return 1;
5774
5775 if (vmx_instruction_info & (1u << 10))
5776 field_value = kvm_register_read(vcpu,
5777 (((vmx_instruction_info) >> 3) & 0xf));
5778 else {
5779 if (get_vmx_mem_address(vcpu, exit_qualification,
5780 vmx_instruction_info, &gva))
5781 return 1;
5782 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5783 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5784 kvm_inject_page_fault(vcpu, &e);
5785 return 1;
5786 }
5787 }
5788
5789
5790 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5791 if (vmcs_field_readonly(field)) {
5792 nested_vmx_failValid(vcpu,
5793 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5794 skip_emulated_instruction(vcpu);
5795 return 1;
5796 }
5797
5798 offset = vmcs_field_to_offset(field);
5799 if (offset < 0) {
5800 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5801 skip_emulated_instruction(vcpu);
5802 return 1;
5803 }
5804 p = ((char *) get_vmcs12(vcpu)) + offset;
5805
5806 switch (vmcs_field_type(field)) {
5807 case VMCS_FIELD_TYPE_U16:
5808 *(u16 *)p = field_value;
5809 break;
5810 case VMCS_FIELD_TYPE_U32:
5811 *(u32 *)p = field_value;
5812 break;
5813 case VMCS_FIELD_TYPE_U64:
5814 *(u64 *)p = field_value;
5815 break;
5816 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5817 *(natural_width *)p = field_value;
5818 break;
5819 default:
5820 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5821 skip_emulated_instruction(vcpu);
5822 return 1;
5823 }
5824
5825 nested_vmx_succeed(vcpu);
5826 skip_emulated_instruction(vcpu);
5827 return 1;
5828}
5829
63846663
NHE		 5830/* Emulate the VMPTRLD instruction */
5831static int handle_vmptrld(struct kvm_vcpu *vcpu)
5832{
5833 struct vcpu_vmx *vmx = to_vmx(vcpu);
5834 gva_t gva;
5835 gpa_t vmptr;
5836 struct x86_exception e;
5837
5838 if (!nested_vmx_check_permission(vcpu))
5839 return 1;
5840
5841 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5842 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5843 return 1;
5844
5845 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5846 sizeof(vmptr), &e)) {
5847 kvm_inject_page_fault(vcpu, &e);
5848 return 1;
5849 }
5850
5851 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5852 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5853 skip_emulated_instruction(vcpu);
5854 return 1;
5855 }
5856
5857 if (vmx->nested.current_vmptr != vmptr) {
5858 struct vmcs12 *new_vmcs12;
5859 struct page *page;
5860 page = nested_get_page(vcpu, vmptr);
5861 if (page == NULL) {
5862 nested_vmx_failInvalid(vcpu);
5863 skip_emulated_instruction(vcpu);
5864 return 1;
5865 }
5866 new_vmcs12 = kmap(page);
5867 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5868 kunmap(page);
5869 nested_release_page_clean(page);
5870 nested_vmx_failValid(vcpu,
5871 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5872 skip_emulated_instruction(vcpu);
5873 return 1;
5874 }
5875 if (vmx->nested.current_vmptr != -1ull) {
5876 kunmap(vmx->nested.current_vmcs12_page);
5877 nested_release_page(vmx->nested.current_vmcs12_page);
5878 }
5879
5880 vmx->nested.current_vmptr = vmptr;
5881 vmx->nested.current_vmcs12 = new_vmcs12;
5882 vmx->nested.current_vmcs12_page = page;
5883 }
5884
5885 nested_vmx_succeed(vcpu);
5886 skip_emulated_instruction(vcpu);
5887 return 1;
5888}
5889
6a4d7550
NHE		 5890/* Emulate the VMPTRST instruction */
5891static int handle_vmptrst(struct kvm_vcpu *vcpu)
5892{
5893 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5894 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5895 gva_t vmcs_gva;
5896 struct x86_exception e;
5897
5898 if (!nested_vmx_check_permission(vcpu))
5899 return 1;
5900
5901 if (get_vmx_mem_address(vcpu, exit_qualification,
5902 vmx_instruction_info, &vmcs_gva))
5903 return 1;
5904 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5905 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5906 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5907 sizeof(u64), &e)) {
5908 kvm_inject_page_fault(vcpu, &e);
5909 return 1;
5910 }
5911 nested_vmx_succeed(vcpu);
5912 skip_emulated_instruction(vcpu);
5913 return 1;
5914}
5915
6aa8b732
AK		 5916/*
5917 * The exit handlers return 1 if the exit was handled fully and guest execution
5918 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5919 * to be done to userspace and return 0.
5920 */
772e0318 5921static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5922 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5923 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5924 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5925 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5926 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5927 [EXIT_REASON_CR_ACCESS] = handle_cr,
5928 [EXIT_REASON_DR_ACCESS] = handle_dr,
5929 [EXIT_REASON_CPUID] = handle_cpuid,
5930 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5931 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5932 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5933 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5934 [EXIT_REASON_INVD] = handle_invd,
a7052897 5935 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5936 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5937 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5938 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5939 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5940 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5941 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5942 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5943 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5944 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5945 [EXIT_REASON_VMOFF] = handle_vmoff,
5946 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5947 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5948 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 5949 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 5950 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 5951 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5952 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5953 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5954 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5955 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5956 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5957 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5958 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5959 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5960};
5961
5962static const int kvm_vmx_max_exit_handlers =
50a3485c 5963 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5964
908a7bdd
JK		 5965static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5966 struct vmcs12 *vmcs12)
5967{
5968 unsigned long exit_qualification;
5969 gpa_t bitmap, last_bitmap;
5970 unsigned int port;
5971 int size;
5972 u8 b;
5973
5974 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5975 return 1;
5976
5977 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5978 return 0;
5979
5980 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5981
5982 port = exit_qualification >> 16;
5983 size = (exit_qualification & 7) + 1;
5984
5985 last_bitmap = (gpa_t)-1;
5986 b = -1;
5987
5988 while (size > 0) {
5989 if (port < 0x8000)
5990 bitmap = vmcs12->io_bitmap_a;
5991 else if (port < 0x10000)
5992 bitmap = vmcs12->io_bitmap_b;
5993 else
5994 return 1;
5995 bitmap += (port & 0x7fff) / 8;
5996
5997 if (last_bitmap != bitmap)
5998 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5999 return 1;
6000 if (b & (1 << (port & 7)))
6001 return 1;
6002
6003 port++;
6004 size--;
6005 last_bitmap = bitmap;
6006 }
6007
6008 return 0;
6009}
6010
644d711a
NHE		 6011/*
6012 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6013 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6014 * disinterest in the current event (read or write a specific MSR) by using an
6015 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6016 */
6017static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6018 struct vmcs12 *vmcs12, u32 exit_reason)
6019{
6020 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6021 gpa_t bitmap;
6022
cbd29cb6 6023 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6024 return 1;
6025
6026 /*
6027 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6028 * for the four combinations of read/write and low/high MSR numbers.
6029 * First we need to figure out which of the four to use:
6030 */
6031 bitmap = vmcs12->msr_bitmap;
6032 if (exit_reason == EXIT_REASON_MSR_WRITE)
6033 bitmap += 2048;
6034 if (msr_index >= 0xc0000000) {
6035 msr_index -= 0xc0000000;
6036 bitmap += 1024;
6037 }
6038
6039 /* Then read the msr_index'th bit from this bitmap: */
6040 if (msr_index < 1024*8) {
6041 unsigned char b;
bd31a7f5
JK		 6042 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6043 return 1;
644d711a
NHE		 6044 return 1 & (b >> (msr_index & 7));
6045 } else
6046 return 1; /* let L1 handle the wrong parameter */
6047}
6048
6049/*
6050 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6051 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6052 * intercept (via guest_host_mask etc.) the current event.
6053 */
6054static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6055 struct vmcs12 *vmcs12)
6056{
6057 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6058 int cr = exit_qualification & 15;
6059 int reg = (exit_qualification >> 8) & 15;
6060 unsigned long val = kvm_register_read(vcpu, reg);
6061
6062 switch ((exit_qualification >> 4) & 3) {
6063 case 0: /* mov to cr */
6064 switch (cr) {
6065 case 0:
6066 if (vmcs12->cr0_guest_host_mask &
6067 (val ^ vmcs12->cr0_read_shadow))
6068 return 1;
6069 break;
6070 case 3:
6071 if ((vmcs12->cr3_target_count >= 1 &&
6072 vmcs12->cr3_target_value0 == val) ||
6073 (vmcs12->cr3_target_count >= 2 &&
6074 vmcs12->cr3_target_value1 == val) ||
6075 (vmcs12->cr3_target_count >= 3 &&
6076 vmcs12->cr3_target_value2 == val) ||
6077 (vmcs12->cr3_target_count >= 4 &&
6078 vmcs12->cr3_target_value3 == val))
6079 return 0;
6080 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6081 return 1;
6082 break;
6083 case 4:
6084 if (vmcs12->cr4_guest_host_mask &
6085 (vmcs12->cr4_read_shadow ^ val))
6086 return 1;
6087 break;
6088 case 8:
6089 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6090 return 1;
6091 break;
6092 }
6093 break;
6094 case 2: /* clts */
6095 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6096 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6097 return 1;
6098 break;
6099 case 1: /* mov from cr */
6100 switch (cr) {
6101 case 3:
6102 if (vmcs12->cpu_based_vm_exec_control &
6103 CPU_BASED_CR3_STORE_EXITING)
6104 return 1;
6105 break;
6106 case 8:
6107 if (vmcs12->cpu_based_vm_exec_control &
6108 CPU_BASED_CR8_STORE_EXITING)
6109 return 1;
6110 break;
6111 }
6112 break;
6113 case 3: /* lmsw */
6114 /*
6115 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6116 * cr0. Other attempted changes are ignored, with no exit.
6117 */
6118 if (vmcs12->cr0_guest_host_mask & 0xe &
6119 (val ^ vmcs12->cr0_read_shadow))
6120 return 1;
6121 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6122 !(vmcs12->cr0_read_shadow & 0x1) &&
6123 (val & 0x1))
6124 return 1;
6125 break;
6126 }
6127 return 0;
6128}
6129
6130/*
6131 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6132 * should handle it ourselves in L0 (and then continue L2). Only call this
6133 * when in is_guest_mode (L2).
6134 */
6135static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6136{
644d711a
NHE		 6137 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6138 struct vcpu_vmx *vmx = to_vmx(vcpu);
6139 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6140 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6141
6142 if (vmx->nested.nested_run_pending)
6143 return 0;
6144
6145 if (unlikely(vmx->fail)) {
bd80158a
JK		 6146 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6147 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6148 return 1;
6149 }
6150
6151 switch (exit_reason) {
6152 case EXIT_REASON_EXCEPTION_NMI:
6153 if (!is_exception(intr_info))
6154 return 0;
6155 else if (is_page_fault(intr_info))
6156 return enable_ept;
6157 return vmcs12->exception_bitmap &
6158 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6159 case EXIT_REASON_EXTERNAL_INTERRUPT:
6160 return 0;
6161 case EXIT_REASON_TRIPLE_FAULT:
6162 return 1;
6163 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6164 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6165 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6166 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6167 case EXIT_REASON_TASK_SWITCH:
6168 return 1;
6169 case EXIT_REASON_CPUID:
6170 return 1;
6171 case EXIT_REASON_HLT:
6172 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6173 case EXIT_REASON_INVD:
6174 return 1;
6175 case EXIT_REASON_INVLPG:
6176 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6177 case EXIT_REASON_RDPMC:
6178 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6179 case EXIT_REASON_RDTSC:
6180 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6181 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6182 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6183 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6184 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6185 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6186 /*
6187 * VMX instructions trap unconditionally. This allows L1 to
6188 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6189 */
6190 return 1;
6191 case EXIT_REASON_CR_ACCESS:
6192 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6193 case EXIT_REASON_DR_ACCESS:
6194 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6195 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6196 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6197 case EXIT_REASON_MSR_READ:
6198 case EXIT_REASON_MSR_WRITE:
6199 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6200 case EXIT_REASON_INVALID_STATE:
6201 return 1;
6202 case EXIT_REASON_MWAIT_INSTRUCTION:
6203 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6204 case EXIT_REASON_MONITOR_INSTRUCTION:
6205 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6206 case EXIT_REASON_PAUSE_INSTRUCTION:
6207 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6208 nested_cpu_has2(vmcs12,
6209 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6210 case EXIT_REASON_MCE_DURING_VMENTRY:
6211 return 0;
6212 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6213 return 1;
6214 case EXIT_REASON_APIC_ACCESS:
6215 return nested_cpu_has2(vmcs12,
6216 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6217 case EXIT_REASON_EPT_VIOLATION:
6218 case EXIT_REASON_EPT_MISCONFIG:
6219 return 0;
0238ea91
JK		 6220 case EXIT_REASON_PREEMPTION_TIMER:
6221 return vmcs12->pin_based_vm_exec_control &
6222 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6223 case EXIT_REASON_WBINVD:
6224 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6225 case EXIT_REASON_XSETBV:
6226 return 1;
6227 default:
6228 return 1;
6229 }
6230}
6231
586f9607
AK		 6232static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6233{
6234 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6235 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6236}
6237
6aa8b732
AK		 6238/*
6239 * The guest has exited. See if we can fix it or if we need userspace
6240 * assistance.
6241 */
851ba692 6242static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6243{
29bd8a78 6244 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6245 u32 exit_reason = vmx->exit_reason;
1155f76a 6246 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6247
80ced186 6248 /* If guest state is invalid, start emulating */
14168786 6249 if (vmx->emulation_required)
80ced186 6250 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6251
b6f1250e
NHE		 6252 /*
6253 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6254 * we did not inject a still-pending event to L1 now because of
6255 * nested_run_pending, we need to re-enable this bit.
6256 */
6257 if (vmx->nested.nested_run_pending)
6258 kvm_make_request(KVM_REQ_EVENT, vcpu);
6259
509c75ea
NHE		 6260 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6261 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6262 vmx->nested.nested_run_pending = 1;
6263 else
6264 vmx->nested.nested_run_pending = 0;
6265
6266 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6267 nested_vmx_vmexit(vcpu);
6268 return 1;
6269 }
6270
5120702e
MG		 6271 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6272 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6273 vcpu->run->fail_entry.hardware_entry_failure_reason
6274 = exit_reason;
6275 return 0;
6276 }
6277
29bd8a78 6278 if (unlikely(vmx->fail)) {
851ba692
AK		 6279 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6280 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6281 = vmcs_read32(VM_INSTRUCTION_ERROR);
6282 return 0;
6283 }
6aa8b732 6284
b9bf6882
XG		 6285 /*
6286 * Note:
6287 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6288 * delivery event since it indicates guest is accessing MMIO.
6289 * The vm-exit can be triggered again after return to guest that
6290 * will cause infinite loop.
6291 */
d77c26fc 6292 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6293 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6294 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6295 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6296 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6297 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6298 vcpu->run->internal.ndata = 2;
6299 vcpu->run->internal.data[0] = vectoring_info;
6300 vcpu->run->internal.data[1] = exit_reason;
6301 return 0;
6302 }
3b86cd99 6303
644d711a
NHE		 6304 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6305 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6306 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6307 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6308 vmx->soft_vnmi_blocked = 0;
3b86cd99 6309 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6310 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6311 /*
6312 * This CPU don't support us in finding the end of an
6313 * NMI-blocked window if the guest runs with IRQs
6314 * disabled. So we pull the trigger after 1 s of
6315 * futile waiting, but inform the user about this.
6316 */
6317 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6318 "state on VCPU %d after 1 s timeout\n",
6319 __func__, vcpu->vcpu_id);
6320 vmx->soft_vnmi_blocked = 0;
3b86cd99 6321 }
3b86cd99
JK		 6322 }
6323
6aa8b732
AK		 6324 if (exit_reason < kvm_vmx_max_exit_handlers
6325 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6326 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6327 else {
851ba692
AK		 6328 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6329 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6330 }
6331 return 0;
6332}
6333
95ba8273 6334static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6335{
95ba8273 6336 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6337 vmcs_write32(TPR_THRESHOLD, 0);
6338 return;
6339 }
6340
95ba8273 6341 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6342}
6343
8d14695f
YZ		 6344static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6345{
6346 u32 sec_exec_control;
6347
6348 /*
6349 * There is not point to enable virtualize x2apic without enable
6350 * apicv
6351 */
c7c9c56c
YZ		 6352 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6353 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6354 return;
6355
6356 if (!vm_need_tpr_shadow(vcpu->kvm))
6357 return;
6358
6359 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6360
6361 if (set) {
6362 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6363 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6364 } else {
6365 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6366 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6367 }
6368 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6369
6370 vmx_set_msr_bitmap(vcpu);
6371}
6372
c7c9c56c
YZ		 6373static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6374{
6375 u16 status;
6376 u8 old;
6377
6378 if (!vmx_vm_has_apicv(kvm))
6379 return;
6380
6381 if (isr == -1)
6382 isr = 0;
6383
6384 status = vmcs_read16(GUEST_INTR_STATUS);
6385 old = status >> 8;
6386 if (isr != old) {
6387 status &= 0xff;
6388 status |= isr << 8;
6389 vmcs_write16(GUEST_INTR_STATUS, status);
6390 }
6391}
6392
6393static void vmx_set_rvi(int vector)
6394{
6395 u16 status;
6396 u8 old;
6397
6398 status = vmcs_read16(GUEST_INTR_STATUS);
6399 old = (u8)status & 0xff;
6400 if ((u8)vector != old) {
6401 status &= ~0xff;
6402 status |= (u8)vector;
6403 vmcs_write16(GUEST_INTR_STATUS, status);
6404 }
6405}
6406
6407static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6408{
6409 if (max_irr == -1)
6410 return;
6411
6412 vmx_set_rvi(max_irr);
6413}
6414
6415static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6416{
6417 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6418 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6419 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6420 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6421}
6422
51aa01d1 6423static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6424{
00eba012
AK		 6425 u32 exit_intr_info;
6426
6427 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6428 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6429 return;
6430
c5ca8e57 6431 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6432 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6433
6434 /* Handle machine checks before interrupts are enabled */
00eba012 6435 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6436 kvm_machine_check();
6437
20f65983 6438 /* We need to handle NMIs before interrupts are enabled */
00eba012 6439 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6440 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6441 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6442 asm("int $2");
ff9d07a0
ZY		 6443 kvm_after_handle_nmi(&vmx->vcpu);
6444 }
51aa01d1 6445}
20f65983 6446
a547c6db
YZ		 6447static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6448{
6449 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6450
6451 /*
6452 * If external interrupt exists, IF bit is set in rflags/eflags on the
6453 * interrupt stack frame, and interrupt will be enabled on a return
6454 * from interrupt handler.
6455 */
6456 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6457 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6458 unsigned int vector;
6459 unsigned long entry;
6460 gate_desc *desc;
6461 struct vcpu_vmx *vmx = to_vmx(vcpu);
6462#ifdef CONFIG_X86_64
6463 unsigned long tmp;
6464#endif
6465
6466 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6467 desc = (gate_desc *)vmx->host_idt_base + vector;
6468 entry = gate_offset(*desc);
6469 asm volatile(
6470#ifdef CONFIG_X86_64
6471 "mov %%" _ASM_SP ", %[sp]\n\t"
6472 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6473 "push $%c[ss]\n\t"
6474 "push %[sp]\n\t"
6475#endif
6476 "pushf\n\t"
6477 "orl $0x200, (%%" _ASM_SP ")\n\t"
6478 __ASM_SIZE(push) " $%c[cs]\n\t"
6479 "call *%[entry]\n\t"
6480 :
6481#ifdef CONFIG_X86_64
6482 [sp]"=&r"(tmp)
6483#endif
6484 :
6485 [entry]"r"(entry),
6486 [ss]"i"(__KERNEL_DS),
6487 [cs]"i"(__KERNEL_CS)
6488 );
6489 } else
6490 local_irq_enable();
6491}
6492
51aa01d1
AK		 6493static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6494{
c5ca8e57 6495 u32 exit_intr_info;
51aa01d1
AK		 6496 bool unblock_nmi;
6497 u8 vector;
6498 bool idtv_info_valid;
6499
6500 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6501
cf393f75 6502 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6503 if (vmx->nmi_known_unmasked)
6504 return;
c5ca8e57
AK		 6505 /*
6506 * Can't use vmx->exit_intr_info since we're not sure what
6507 * the exit reason is.
6508 */
6509 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6510 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6511 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6512 /*
7b4a25cb 6513 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6514 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6515 * a guest IRET fault.
7b4a25cb
GN		 6516 * SDM 3: 23.2.2 (September 2008)
6517 * Bit 12 is undefined in any of the following cases:
6518 * If the VM exit sets the valid bit in the IDT-vectoring
6519 * information field.
6520 * If the VM exit is due to a double fault.
cf393f75 6521 */
7b4a25cb
GN		 6522 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6523 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6524 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6525 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6526 else
6527 vmx->nmi_known_unmasked =
6528 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6529 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6530 } else if (unlikely(vmx->soft_vnmi_blocked))
6531 vmx->vnmi_blocked_time +=
6532 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6533}
6534
3ab66e8a 6535static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6536 u32 idt_vectoring_info,
6537 int instr_len_field,
6538 int error_code_field)
51aa01d1 6539{
51aa01d1
AK		 6540 u8 vector;
6541 int type;
6542 bool idtv_info_valid;
6543
6544 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6545
3ab66e8a
JK		 6546 vcpu->arch.nmi_injected = false;
6547 kvm_clear_exception_queue(vcpu);
6548 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6549
6550 if (!idtv_info_valid)
6551 return;
6552
3ab66e8a 6553 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6554
668f612f
AK		 6555 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6556 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6557
64a7ec06 6558 switch (type) {
37b96e98 6559 case INTR_TYPE_NMI_INTR:
3ab66e8a 6560 vcpu->arch.nmi_injected = true;
668f612f 6561 /*
7b4a25cb 6562 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6563 * Clear bit "block by NMI" before VM entry if a NMI
6564 * delivery faulted.
668f612f 6565 */
3ab66e8a 6566 vmx_set_nmi_mask(vcpu, false);
37b96e98 6567 break;
37b96e98 6568 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6569 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6570 /* fall through */
6571 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6572 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6573 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6574 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6575 } else
3ab66e8a 6576 kvm_queue_exception(vcpu, vector);
37b96e98 6577 break;
66fd3f7f 6578 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6579 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6580 /* fall through */
37b96e98 6581 case INTR_TYPE_EXT_INTR:
3ab66e8a 6582 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6583 break;
6584 default:
6585 break;
f7d9238f 6586 }
cf393f75
AK		 6587}
6588
83422e17
AK		 6589static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6590{
3ab66e8a 6591 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6592 VM_EXIT_INSTRUCTION_LEN,
6593 IDT_VECTORING_ERROR_CODE);
6594}
6595
b463a6f7
AK		 6596static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6597{
3ab66e8a 6598 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6599 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6600 VM_ENTRY_INSTRUCTION_LEN,
6601 VM_ENTRY_EXCEPTION_ERROR_CODE);
6602
6603 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6604}
6605
d7cd9796
GN		 6606static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6607{
6608 int i, nr_msrs;
6609 struct perf_guest_switch_msr *msrs;
6610
6611 msrs = perf_guest_get_msrs(&nr_msrs);
6612
6613 if (!msrs)
6614 return;
6615
6616 for (i = 0; i < nr_msrs; i++)
6617 if (msrs[i].host == msrs[i].guest)
6618 clear_atomic_switch_msr(vmx, msrs[i].msr);
6619 else
6620 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6621 msrs[i].host);
6622}
6623
a3b5ba49 6624static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6625{
a2fa3e9f 6626 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6627 unsigned long debugctlmsr;
104f226b
AK		 6628
6629 /* Record the guest's net vcpu time for enforced NMI injections. */
6630 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6631 vmx->entry_time = ktime_get();
6632
6633 /* Don't enter VMX if guest state is invalid, let the exit handler
6634 start emulation until we arrive back to a valid state */
14168786 6635 if (vmx->emulation_required)
104f226b
AK		 6636 return;
6637
6638 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6639 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6640 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6641 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6642
6643 /* When single-stepping over STI and MOV SS, we must clear the
6644 * corresponding interruptibility bits in the guest state. Otherwise
6645 * vmentry fails as it then expects bit 14 (BS) in pending debug
6646 * exceptions being set, but that's not correct for the guest debugging
6647 * case. */
6648 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6649 vmx_set_interrupt_shadow(vcpu, 0);
6650
d7cd9796 6651 atomic_switch_perf_msrs(vmx);
2a7921b7 6652 debugctlmsr = get_debugctlmsr();
d7cd9796 6653
d462b819 6654 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6655 asm(
6aa8b732 6656 /* Store host registers */
b188c81f
AK		 6657 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6658 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6659 "push %%" _ASM_CX " \n\t"
6660 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6661 "je 1f \n\t"
b188c81f 6662 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6663 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6664 "1: \n\t"
d3edefc0 6665 /* Reload cr2 if changed */
b188c81f
AK		 6666 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6667 "mov %%cr2, %%" _ASM_DX " \n\t"
6668 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6669 "je 2f \n\t"
b188c81f 6670 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6671 "2: \n\t"
6aa8b732 6672 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6673 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6674 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6675 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6676 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6677 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6678 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6679 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6680 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6681#ifdef CONFIG_X86_64
e08aa78a
AK		 6682 "mov %c[r8](%0), %%r8 \n\t"
6683 "mov %c[r9](%0), %%r9 \n\t"
6684 "mov %c[r10](%0), %%r10 \n\t"
6685 "mov %c[r11](%0), %%r11 \n\t"
6686 "mov %c[r12](%0), %%r12 \n\t"
6687 "mov %c[r13](%0), %%r13 \n\t"
6688 "mov %c[r14](%0), %%r14 \n\t"
6689 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6690#endif
b188c81f 6691 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6692
6aa8b732 6693 /* Enter guest mode */
83287ea4 6694 "jne 1f \n\t"
4ecac3fd 6695 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6696 "jmp 2f \n\t"
6697 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6698 "2: "
6aa8b732 6699 /* Save guest registers, load host registers, keep flags */
b188c81f 6700 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6701 "pop %0 \n\t"
b188c81f
AK		 6702 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6703 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6704 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6705 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6706 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6707 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6708 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6709#ifdef CONFIG_X86_64
e08aa78a
AK		 6710 "mov %%r8, %c[r8](%0) \n\t"
6711 "mov %%r9, %c[r9](%0) \n\t"
6712 "mov %%r10, %c[r10](%0) \n\t"
6713 "mov %%r11, %c[r11](%0) \n\t"
6714 "mov %%r12, %c[r12](%0) \n\t"
6715 "mov %%r13, %c[r13](%0) \n\t"
6716 "mov %%r14, %c[r14](%0) \n\t"
6717 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6718#endif
b188c81f
AK		 6719 "mov %%cr2, %%" _ASM_AX " \n\t"
6720 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6721
b188c81f 6722 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6723 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6724 ".pushsection .rodata \n\t"
6725 ".global vmx_return \n\t"
6726 "vmx_return: " _ASM_PTR " 2b \n\t"
6727 ".popsection"
e08aa78a 6728 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6729 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6730 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6731 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6732 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6733 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6734 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6735 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6736 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6737 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6738 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6739#ifdef CONFIG_X86_64
ad312c7c
ZX		 6740 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6741 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6742 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6743 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6744 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6745 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6746 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6747 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6748#endif
40712fae
AK		 6749 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6750 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6751 : "cc", "memory"
6752#ifdef CONFIG_X86_64
b188c81f 6753 , "rax", "rbx", "rdi", "rsi"
c2036300 6754 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6755#else
6756 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6757#endif
6758 );
6aa8b732 6759
2a7921b7
GN		 6760 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6761 if (debugctlmsr)
6762 update_debugctlmsr(debugctlmsr);
6763
aa67f609
AK		 6764#ifndef CONFIG_X86_64
6765 /*
6766 * The sysexit path does not restore ds/es, so we must set them to
6767 * a reasonable value ourselves.
6768 *
6769 * We can't defer this to vmx_load_host_state() since that function
6770 * may be executed in interrupt context, which saves and restore segments
6771 * around it, nullifying its effect.
6772 */
6773 loadsegment(ds, __USER_DS);
6774 loadsegment(es, __USER_DS);
6775#endif
6776
6de4f3ad 6777 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6778 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6779 | (1 << VCPU_EXREG_CPL)
aff48baa 6780 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6781 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6782 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6783 vcpu->arch.regs_dirty = 0;
6784
1155f76a
AK		 6785 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6786
d462b819 6787 vmx->loaded_vmcs->launched = 1;
1b6269db 6788
51aa01d1 6789 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6790 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6791
6792 vmx_complete_atomic_exit(vmx);
6793 vmx_recover_nmi_blocking(vmx);
cf393f75 6794 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6795}
6796
6aa8b732
AK		 6797static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6798{
fb3f0f51
RR		 6799 struct vcpu_vmx *vmx = to_vmx(vcpu);
6800
cdbecfc3 6801 free_vpid(vmx);
ec378aee 6802 free_nested(vmx);
d462b819 6803 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6804 kfree(vmx->guest_msrs);
6805 kvm_vcpu_uninit(vcpu);
a4770347 6806 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6807}
6808
fb3f0f51 6809static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6810{
fb3f0f51 6811 int err;
c16f862d 6812 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6813 int cpu;
6aa8b732 6814
a2fa3e9f 6815 if (!vmx)
fb3f0f51
RR		 6816 return ERR_PTR(-ENOMEM);
6817
2384d2b3
SY		 6818 allocate_vpid(vmx);
6819
fb3f0f51
RR		 6820 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6821 if (err)
6822 goto free_vcpu;
965b58a5 6823
a2fa3e9f 6824 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6825 err = -ENOMEM;
fb3f0f51 6826 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6827 goto uninit_vcpu;
6828 }
965b58a5 6829
d462b819
NHE		 6830 vmx->loaded_vmcs = &vmx->vmcs01;
6831 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6832 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6833 goto free_msrs;
d462b819
NHE		 6834 if (!vmm_exclusive)
6835 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6836 loaded_vmcs_init(vmx->loaded_vmcs);
6837 if (!vmm_exclusive)
6838 kvm_cpu_vmxoff();
a2fa3e9f 6839
15ad7146
AK		 6840 cpu = get_cpu();
6841 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6842 vmx->vcpu.cpu = cpu;
8b9cf98c 6843 err = vmx_vcpu_setup(vmx);
fb3f0f51 6844 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6845 put_cpu();
fb3f0f51
RR		 6846 if (err)
6847 goto free_vmcs;
a63cb560 6848 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 6849 err = alloc_apic_access_page(kvm);
6850 if (err)
5e4a0b3c 6851 goto free_vmcs;
a63cb560 6852 }
fb3f0f51 6853
b927a3ce
SY		 6854 if (enable_ept) {
6855 if (!kvm->arch.ept_identity_map_addr)
6856 kvm->arch.ept_identity_map_addr =
6857 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6858 err = -ENOMEM;
b7ebfb05
SY		 6859 if (alloc_identity_pagetable(kvm) != 0)
6860 goto free_vmcs;
93ea5388
GN		 6861 if (!init_rmode_identity_map(kvm))
6862 goto free_vmcs;
b927a3ce 6863 }
b7ebfb05 6864
a9d30f33
NHE		 6865 vmx->nested.current_vmptr = -1ull;
6866 vmx->nested.current_vmcs12 = NULL;
6867
fb3f0f51
RR		 6868 return &vmx->vcpu;
6869
6870free_vmcs:
5f3fbc34 6871 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6872free_msrs:
fb3f0f51
RR		 6873 kfree(vmx->guest_msrs);
6874uninit_vcpu:
6875 kvm_vcpu_uninit(&vmx->vcpu);
6876free_vcpu:
cdbecfc3 6877 free_vpid(vmx);
a4770347 6878 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6879 return ERR_PTR(err);
6aa8b732
AK		 6880}
6881
002c7f7c
YS		 6882static void __init vmx_check_processor_compat(void *rtn)
6883{
6884 struct vmcs_config vmcs_conf;
6885
6886 *(int *)rtn = 0;
6887 if (setup_vmcs_config(&vmcs_conf) < 0)
6888 *(int *)rtn = -EIO;
6889 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6890 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6891 smp_processor_id());
6892 *(int *)rtn = -EIO;
6893 }
6894}
6895
67253af5
SY		 6896static int get_ept_level(void)
6897{
6898 return VMX_EPT_DEFAULT_GAW + 1;
6899}
6900
4b12f0de 6901static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6902{
4b12f0de
SY		 6903 u64 ret;
6904
522c68c4
SY		 6905 /* For VT-d and EPT combination
6906 * 1. MMIO: always map as UC
6907 * 2. EPT with VT-d:
6908 * a. VT-d without snooping control feature: can't guarantee the
6909 * result, try to trust guest.
6910 * b. VT-d with snooping control feature: snooping control feature of
6911 * VT-d engine can guarantee the cache correctness. Just set it
6912 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6913 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6914 * consistent with host MTRR
6915 */
4b12f0de
SY		 6916 if (is_mmio)
6917 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6918 else if (vcpu->kvm->arch.iommu_domain &&
6919 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6920 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6921 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6922 else
522c68c4 6923 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6924 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6925
6926 return ret;
64d4d521
SY		 6927}
6928
17cc3935 6929static int vmx_get_lpage_level(void)
344f414f 6930{
878403b7
SY		 6931 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6932 return PT_DIRECTORY_LEVEL;
6933 else
6934 /* For shadow and EPT supported 1GB page */
6935 return PT_PDPE_LEVEL;
344f414f
JR		 6936}
6937
0e851880
SY		 6938static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6939{
4e47c7a6
SY		 6940 struct kvm_cpuid_entry2 *best;
6941 struct vcpu_vmx *vmx = to_vmx(vcpu);
6942 u32 exec_control;
6943
6944 vmx->rdtscp_enabled = false;
6945 if (vmx_rdtscp_supported()) {
6946 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6947 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6948 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6949 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6950 vmx->rdtscp_enabled = true;
6951 else {
6952 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6953 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6954 exec_control);
6955 }
6956 }
6957 }
ad756a16 6958
ad756a16
MJ		 6959 /* Exposing INVPCID only when PCID is exposed */
6960 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6961 if (vmx_invpcid_supported() &&
4f977045 6962 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6963 guest_cpuid_has_pcid(vcpu)) {
29282fde 6964 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6965 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6966 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6967 exec_control);
6968 } else {
29282fde
TI		 6969 if (cpu_has_secondary_exec_ctrls()) {
6970 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6971 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6972 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6973 exec_control);
6974 }
ad756a16 6975 if (best)
4f977045 6976 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6977 }
0e851880
SY		 6978}
6979
d4330ef2
JR		 6980static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6981{
7b8050f5
NHE		 6982 if (func == 1 && nested)
6983 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6984}
6985
fe3ef05c
NHE		 6986/*
6987 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6988 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6989 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6990 * guest in a way that will both be appropriate to L1's requests, and our
6991 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6992 * function also has additional necessary side-effects, like setting various
6993 * vcpu->arch fields.
6994 */
6995static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6996{
6997 struct vcpu_vmx *vmx = to_vmx(vcpu);
6998 u32 exec_control;
6999
7000 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7001 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7002 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7003 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7004 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7005 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7006 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7007 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7008 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7009 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7010 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7011 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7012 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7013 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7014 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7015 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7016 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7017 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7018 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7019 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7020 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7021 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7022 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7023 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7024 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7025 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7026 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7027 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7028 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7029 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7030 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7031 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7032 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7033 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7034 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7035 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7036
7037 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7038 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7039 vmcs12->vm_entry_intr_info_field);
7040 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7041 vmcs12->vm_entry_exception_error_code);
7042 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7043 vmcs12->vm_entry_instruction_len);
7044 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7045 vmcs12->guest_interruptibility_info);
7046 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
7047 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7048 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7049 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7050 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7051 vmcs12->guest_pending_dbg_exceptions);
7052 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7053 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7054
7055 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7056
7057 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7058 (vmcs_config.pin_based_exec_ctrl |
7059 vmcs12->pin_based_vm_exec_control));
7060
0238ea91
JK		 7061 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7062 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7063 vmcs12->vmx_preemption_timer_value);
7064
fe3ef05c
NHE		 7065 /*
7066 * Whether page-faults are trapped is determined by a combination of
7067 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7068 * If enable_ept, L0 doesn't care about page faults and we should
7069 * set all of these to L1's desires. However, if !enable_ept, L0 does
7070 * care about (at least some) page faults, and because it is not easy
7071 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7072 * to exit on each and every L2 page fault. This is done by setting
7073 * MASK=MATCH=0 and (see below) EB.PF=1.
7074 * Note that below we don't need special code to set EB.PF beyond the
7075 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7076 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7077 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7078 *
7079 * A problem with this approach (when !enable_ept) is that L1 may be
7080 * injected with more page faults than it asked for. This could have
7081 * caused problems, but in practice existing hypervisors don't care.
7082 * To fix this, we will need to emulate the PFEC checking (on the L1
7083 * page tables), using walk_addr(), when injecting PFs to L1.
7084 */
7085 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7086 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7087 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7088 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7089
7090 if (cpu_has_secondary_exec_ctrls()) {
7091 u32 exec_control = vmx_secondary_exec_control(vmx);
7092 if (!vmx->rdtscp_enabled)
7093 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7094 /* Take the following fields only from vmcs12 */
7095 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7096 if (nested_cpu_has(vmcs12,
7097 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7098 exec_control |= vmcs12->secondary_vm_exec_control;
7099
7100 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7101 /*
7102 * Translate L1 physical address to host physical
7103 * address for vmcs02. Keep the page pinned, so this
7104 * physical address remains valid. We keep a reference
7105 * to it so we can release it later.
7106 */
7107 if (vmx->nested.apic_access_page) /* shouldn't happen */
7108 nested_release_page(vmx->nested.apic_access_page);
7109 vmx->nested.apic_access_page =
7110 nested_get_page(vcpu, vmcs12->apic_access_addr);
7111 /*
7112 * If translation failed, no matter: This feature asks
7113 * to exit when accessing the given address, and if it
7114 * can never be accessed, this feature won't do
7115 * anything anyway.
7116 */
7117 if (!vmx->nested.apic_access_page)
7118 exec_control &=
7119 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7120 else
7121 vmcs_write64(APIC_ACCESS_ADDR,
7122 page_to_phys(vmx->nested.apic_access_page));
7123 }
7124
7125 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7126 }
7127
7128
7129 /*
7130 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7131 * Some constant fields are set here by vmx_set_constant_host_state().
7132 * Other fields are different per CPU, and will be set later when
7133 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7134 */
a547c6db 7135 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7136
7137 /*
7138 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7139 * entry, but only if the current (host) sp changed from the value
7140 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7141 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7142 * here we just force the write to happen on entry.
7143 */
7144 vmx->host_rsp = 0;
7145
7146 exec_control = vmx_exec_control(vmx); /* L0's desires */
7147 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7148 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7149 exec_control &= ~CPU_BASED_TPR_SHADOW;
7150 exec_control |= vmcs12->cpu_based_vm_exec_control;
7151 /*
7152 * Merging of IO and MSR bitmaps not currently supported.
7153 * Rather, exit every time.
7154 */
7155 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7156 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7157 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7158
7159 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7160
7161 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7162 * bitwise-or of what L1 wants to trap for L2, and what we want to
7163 * trap. Note that CR0.TS also needs updating - we do this later.
7164 */
7165 update_exception_bitmap(vcpu);
7166 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7167 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7168
7169 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7170 vmcs_write32(VM_EXIT_CONTROLS,
7171 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7172 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7173 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7174
7175 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7176 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7177 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7178 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7179
7180
7181 set_cr4_guest_host_mask(vmx);
7182
27fc51b2
NHE		 7183 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7184 vmcs_write64(TSC_OFFSET,
7185 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7186 else
7187 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7188
7189 if (enable_vpid) {
7190 /*
7191 * Trivially support vpid by letting L2s share their parent
7192 * L1's vpid. TODO: move to a more elaborate solution, giving
7193 * each L2 its own vpid and exposing the vpid feature to L1.
7194 */
7195 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7196 vmx_flush_tlb(vcpu);
7197 }
7198
7199 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7200 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7201 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7202 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7203 else
7204 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7205 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7206 vmx_set_efer(vcpu, vcpu->arch.efer);
7207
7208 /*
7209 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7210 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7211 * The CR0_READ_SHADOW is what L2 should have expected to read given
7212 * the specifications by L1; It's not enough to take
7213 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7214 * have more bits than L1 expected.
7215 */
7216 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7217 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7218
7219 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7220 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7221
7222 /* shadow page tables on either EPT or shadow page tables */
7223 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7224 kvm_mmu_reset_context(vcpu);
7225
7226 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7227 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7228}
7229
cd232ad0
NHE		 7230/*
7231 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7232 * for running an L2 nested guest.
7233 */
7234static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7235{
7236 struct vmcs12 *vmcs12;
7237 struct vcpu_vmx *vmx = to_vmx(vcpu);
7238 int cpu;
7239 struct loaded_vmcs *vmcs02;
7240
7241 if (!nested_vmx_check_permission(vcpu) ||
7242 !nested_vmx_check_vmcs12(vcpu))
7243 return 1;
7244
7245 skip_emulated_instruction(vcpu);
7246 vmcs12 = get_vmcs12(vcpu);
7247
7c177938
NHE		 7248 /*
7249 * The nested entry process starts with enforcing various prerequisites
7250 * on vmcs12 as required by the Intel SDM, and act appropriately when
7251 * they fail: As the SDM explains, some conditions should cause the
7252 * instruction to fail, while others will cause the instruction to seem
7253 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7254 * To speed up the normal (success) code path, we should avoid checking
7255 * for misconfigurations which will anyway be caught by the processor
7256 * when using the merged vmcs02.
7257 */
7258 if (vmcs12->launch_state == launch) {
7259 nested_vmx_failValid(vcpu,
7260 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7261 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7262 return 1;
7263 }
7264
7265 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7266 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7267 /*TODO: Also verify bits beyond physical address width are 0*/
7268 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7269 return 1;
7270 }
7271
7272 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7273 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7274 /*TODO: Also verify bits beyond physical address width are 0*/
7275 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7276 return 1;
7277 }
7278
7279 if (vmcs12->vm_entry_msr_load_count > 0 ||
7280 vmcs12->vm_exit_msr_load_count > 0 ||
7281 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7282 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7283 __func__);
7c177938
NHE		 7284 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7285 return 1;
7286 }
7287
7288 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7289 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7290 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7291 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7292 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7293 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7294 !vmx_control_verify(vmcs12->vm_exit_controls,
7295 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7296 !vmx_control_verify(vmcs12->vm_entry_controls,
7297 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7298 {
7299 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7300 return 1;
7301 }
7302
7303 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7304 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7305 nested_vmx_failValid(vcpu,
7306 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7307 return 1;
7308 }
7309
7310 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7311 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7312 nested_vmx_entry_failure(vcpu, vmcs12,
7313 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7314 return 1;
7315 }
7316 if (vmcs12->vmcs_link_pointer != -1ull) {
7317 nested_vmx_entry_failure(vcpu, vmcs12,
7318 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7319 return 1;
7320 }
7321
7322 /*
7323 * We're finally done with prerequisite checking, and can start with
7324 * the nested entry.
7325 */
7326
cd232ad0
NHE		 7327 vmcs02 = nested_get_current_vmcs02(vmx);
7328 if (!vmcs02)
7329 return -ENOMEM;
7330
7331 enter_guest_mode(vcpu);
7332
7333 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7334
7335 cpu = get_cpu();
7336 vmx->loaded_vmcs = vmcs02;
7337 vmx_vcpu_put(vcpu);
7338 vmx_vcpu_load(vcpu, cpu);
7339 vcpu->cpu = cpu;
7340 put_cpu();
7341
36c3cc42
JK		 7342 vmx_segment_cache_clear(vmx);
7343
cd232ad0
NHE		 7344 vmcs12->launch_state = 1;
7345
7346 prepare_vmcs02(vcpu, vmcs12);
7347
7348 /*
7349 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7350 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7351 * returned as far as L1 is concerned. It will only return (and set
7352 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7353 */
7354 return 1;
7355}
7356
4704d0be
NHE		 7357/*
7358 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7359 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7360 * This function returns the new value we should put in vmcs12.guest_cr0.
7361 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7362 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7363 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7364 * didn't trap the bit, because if L1 did, so would L0).
7365 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7366 * been modified by L2, and L1 knows it. So just leave the old value of
7367 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7368 * isn't relevant, because if L0 traps this bit it can set it to anything.
7369 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7370 * changed these bits, and therefore they need to be updated, but L0
7371 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7372 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7373 */
7374static inline unsigned long
7375vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7376{
7377 return
7378 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7379 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7380 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7381 vcpu->arch.cr0_guest_owned_bits));
7382}
7383
7384static inline unsigned long
7385vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7386{
7387 return
7388 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7389 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7390 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7391 vcpu->arch.cr4_guest_owned_bits));
7392}
7393
5f3d5799
JK		 7394static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7395 struct vmcs12 *vmcs12)
7396{
7397 u32 idt_vectoring;
7398 unsigned int nr;
7399
7400 if (vcpu->arch.exception.pending) {
7401 nr = vcpu->arch.exception.nr;
7402 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7403
7404 if (kvm_exception_is_soft(nr)) {
7405 vmcs12->vm_exit_instruction_len =
7406 vcpu->arch.event_exit_inst_len;
7407 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7408 } else
7409 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7410
7411 if (vcpu->arch.exception.has_error_code) {
7412 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7413 vmcs12->idt_vectoring_error_code =
7414 vcpu->arch.exception.error_code;
7415 }
7416
7417 vmcs12->idt_vectoring_info_field = idt_vectoring;
7418 } else if (vcpu->arch.nmi_pending) {
7419 vmcs12->idt_vectoring_info_field =
7420 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7421 } else if (vcpu->arch.interrupt.pending) {
7422 nr = vcpu->arch.interrupt.nr;
7423 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7424
7425 if (vcpu->arch.interrupt.soft) {
7426 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7427 vmcs12->vm_entry_instruction_len =
7428 vcpu->arch.event_exit_inst_len;
7429 } else
7430 idt_vectoring |= INTR_TYPE_EXT_INTR;
7431
7432 vmcs12->idt_vectoring_info_field = idt_vectoring;
7433 }
7434}
7435
4704d0be
NHE		 7436/*
7437 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7438 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7439 * and this function updates it to reflect the changes to the guest state while
7440 * L2 was running (and perhaps made some exits which were handled directly by L0
7441 * without going back to L1), and to reflect the exit reason.
7442 * Note that we do not have to copy here all VMCS fields, just those that
7443 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7444 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7445 * which already writes to vmcs12 directly.
7446 */
733568f9 7447static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7448{
7449 /* update guest state fields: */
7450 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7451 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7452
7453 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7454 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7455 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7456 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7457
7458 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7459 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7460 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7461 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7462 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7463 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7464 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7465 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7466 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7467 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7468 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7469 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7470 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7471 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7472 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7473 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7474 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7475 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7476 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7477 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7478 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7479 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7480 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7481 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7482 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7483 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7484 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7485 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7486 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7487 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7488 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7489 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7490 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7491 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7492 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7493 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7494
7495 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7496 vmcs12->guest_interruptibility_info =
7497 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7498 vmcs12->guest_pending_dbg_exceptions =
7499 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7500
c18911a2
JK		 7501 vmcs12->vm_entry_controls =
7502 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7503 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7504
4704d0be
NHE		 7505 /* TODO: These cannot have changed unless we have MSR bitmaps and
7506 * the relevant bit asks not to trap the change */
7507 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7508 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7509 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7510 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7511 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7512 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7513
7514 /* update exit information fields: */
7515
957c897e 7516 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7517 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7518
7519 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7520 if ((vmcs12->vm_exit_intr_info &
7521 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7522 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7523 vmcs12->vm_exit_intr_error_code =
7524 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7525 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7526 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7527 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7528
5f3d5799
JK		 7529 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7530 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7531 * instead of reading the real value. */
4704d0be 7532 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7533
7534 /*
7535 * Transfer the event that L0 or L1 may wanted to inject into
7536 * L2 to IDT_VECTORING_INFO_FIELD.
7537 */
7538 vmcs12_save_pending_event(vcpu, vmcs12);
7539 }
7540
7541 /*
7542 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7543 * preserved above and would only end up incorrectly in L1.
7544 */
7545 vcpu->arch.nmi_injected = false;
7546 kvm_clear_exception_queue(vcpu);
7547 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7548}
7549
7550/*
7551 * A part of what we need to when the nested L2 guest exits and we want to
7552 * run its L1 parent, is to reset L1's guest state to the host state specified
7553 * in vmcs12.
7554 * This function is to be called not only on normal nested exit, but also on
7555 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7556 * Failures During or After Loading Guest State").
7557 * This function should be called when the active VMCS is L1's (vmcs01).
7558 */
733568f9
JK		 7559static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7560 struct vmcs12 *vmcs12)
4704d0be
NHE		 7561{
7562 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7563 vcpu->arch.efer = vmcs12->host_ia32_efer;
7564 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7565 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7566 else
7567 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7568 vmx_set_efer(vcpu, vcpu->arch.efer);
7569
7570 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7571 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
c4627c72 7572 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
4704d0be
NHE		 7573 /*
7574 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7575 * actually changed, because it depends on the current state of
7576 * fpu_active (which may have changed).
7577 * Note that vmx_set_cr0 refers to efer set above.
7578 */
7579 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7580 /*
7581 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7582 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7583 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7584 */
7585 update_exception_bitmap(vcpu);
7586 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7587 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7588
7589 /*
7590 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7591 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7592 */
7593 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7594 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7595
7596 /* shadow page tables on either EPT or shadow page tables */
7597 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7598 kvm_mmu_reset_context(vcpu);
7599
7600 if (enable_vpid) {
7601 /*
7602 * Trivially support vpid by letting L2s share their parent
7603 * L1's vpid. TODO: move to a more elaborate solution, giving
7604 * each L2 its own vpid and exposing the vpid feature to L1.
7605 */
7606 vmx_flush_tlb(vcpu);
7607 }
7608
7609
7610 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7611 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7612 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7613 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7614 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7615 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7616 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7617 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7618 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7619 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7620 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7621 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7622 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7623 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7624 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7625
7626 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7627 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7628 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7629 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7630 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 7631
7632 kvm_set_dr(vcpu, 7, 0x400);
7633 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 7634}
7635
7636/*
7637 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7638 * and modify vmcs12 to make it see what it would expect to see there if
7639 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7640 */
7641static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7642{
7643 struct vcpu_vmx *vmx = to_vmx(vcpu);
7644 int cpu;
7645 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7646
5f3d5799
JK		 7647 /* trying to cancel vmlaunch/vmresume is a bug */
7648 WARN_ON_ONCE(vmx->nested.nested_run_pending);
7649
4704d0be
NHE		 7650 leave_guest_mode(vcpu);
7651 prepare_vmcs12(vcpu, vmcs12);
7652
7653 cpu = get_cpu();
7654 vmx->loaded_vmcs = &vmx->vmcs01;
7655 vmx_vcpu_put(vcpu);
7656 vmx_vcpu_load(vcpu, cpu);
7657 vcpu->cpu = cpu;
7658 put_cpu();
7659
36c3cc42
JK		 7660 vmx_segment_cache_clear(vmx);
7661
4704d0be
NHE		 7662 /* if no vmcs02 cache requested, remove the one we used */
7663 if (VMCS02_POOL_SIZE == 0)
7664 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7665
7666 load_vmcs12_host_state(vcpu, vmcs12);
7667
27fc51b2 7668 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7669 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7670
7671 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7672 vmx->host_rsp = 0;
7673
7674 /* Unpin physical memory we referred to in vmcs02 */
7675 if (vmx->nested.apic_access_page) {
7676 nested_release_page(vmx->nested.apic_access_page);
7677 vmx->nested.apic_access_page = 0;
7678 }
7679
7680 /*
7681 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7682 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7683 * success or failure flag accordingly.
7684 */
7685 if (unlikely(vmx->fail)) {
7686 vmx->fail = 0;
7687 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7688 } else
7689 nested_vmx_succeed(vcpu);
7690}
7691
7c177938
NHE		 7692/*
7693 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7694 * 23.7 "VM-entry failures during or after loading guest state" (this also
7695 * lists the acceptable exit-reason and exit-qualification parameters).
7696 * It should only be called before L2 actually succeeded to run, and when
7697 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7698 */
7699static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7700 struct vmcs12 *vmcs12,
7701 u32 reason, unsigned long qualification)
7702{
7703 load_vmcs12_host_state(vcpu, vmcs12);
7704 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7705 vmcs12->exit_qualification = qualification;
7706 nested_vmx_succeed(vcpu);
7707}
7708
8a76d7f2
JR		 7709static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7710 struct x86_instruction_info *info,
7711 enum x86_intercept_stage stage)
7712{
7713 return X86EMUL_CONTINUE;
7714}
7715
cbdd1bea 7716static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7717 .cpu_has_kvm_support = cpu_has_kvm_support,
7718 .disabled_by_bios = vmx_disabled_by_bios,
7719 .hardware_setup = hardware_setup,
7720 .hardware_unsetup = hardware_unsetup,
002c7f7c 7721 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7722 .hardware_enable = hardware_enable,
7723 .hardware_disable = hardware_disable,
04547156 7724 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7725
7726 .vcpu_create = vmx_create_vcpu,
7727 .vcpu_free = vmx_free_vcpu,
04d2cc77 7728 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7729
04d2cc77 7730 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7731 .vcpu_load = vmx_vcpu_load,
7732 .vcpu_put = vmx_vcpu_put,
7733
c8639010 7734 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7735 .get_msr = vmx_get_msr,
7736 .set_msr = vmx_set_msr,
7737 .get_segment_base = vmx_get_segment_base,
7738 .get_segment = vmx_get_segment,
7739 .set_segment = vmx_set_segment,
2e4d2653 7740 .get_cpl = vmx_get_cpl,
6aa8b732 7741 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7742 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7743 .decache_cr3 = vmx_decache_cr3,
25c4c276 7744 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7745 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7746 .set_cr3 = vmx_set_cr3,
7747 .set_cr4 = vmx_set_cr4,
6aa8b732 7748 .set_efer = vmx_set_efer,
6aa8b732
AK		 7749 .get_idt = vmx_get_idt,
7750 .set_idt = vmx_set_idt,
7751 .get_gdt = vmx_get_gdt,
7752 .set_gdt = vmx_set_gdt,
020df079 7753 .set_dr7 = vmx_set_dr7,
5fdbf976 7754 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7755 .get_rflags = vmx_get_rflags,
7756 .set_rflags = vmx_set_rflags,
ebcbab4c 7757 .fpu_activate = vmx_fpu_activate,
02daab21 7758 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7759
7760 .tlb_flush = vmx_flush_tlb,
6aa8b732 7761
6aa8b732 7762 .run = vmx_vcpu_run,
6062d012 7763 .handle_exit = vmx_handle_exit,
6aa8b732 7764 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7765 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7766 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7767 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7768 .set_irq = vmx_inject_irq,
95ba8273 7769 .set_nmi = vmx_inject_nmi,
298101da 7770 .queue_exception = vmx_queue_exception,
b463a6f7 7771 .cancel_injection = vmx_cancel_injection,
78646121 7772 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7773 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7774 .get_nmi_mask = vmx_get_nmi_mask,
7775 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7776 .enable_nmi_window = enable_nmi_window,
7777 .enable_irq_window = enable_irq_window,
7778 .update_cr8_intercept = update_cr8_intercept,
8d14695f 7779 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 7780 .vm_has_apicv = vmx_vm_has_apicv,
7781 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7782 .hwapic_irr_update = vmx_hwapic_irr_update,
7783 .hwapic_isr_update = vmx_hwapic_isr_update,
95ba8273 7784
cbc94022 7785 .set_tss_addr = vmx_set_tss_addr,
67253af5 7786 .get_tdp_level = get_ept_level,
4b12f0de 7787 .get_mt_mask = vmx_get_mt_mask,
229456fc 7788
586f9607 7789 .get_exit_info = vmx_get_exit_info,
586f9607 7790
17cc3935 7791 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7792
7793 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7794
7795 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7796 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7797
7798 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7799
7800 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7801
4051b188 7802 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7803 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7804 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7805 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7806 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7807 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7808
7809 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7810
7811 .check_intercept = vmx_check_intercept,
a547c6db 7812 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 7813};
7814
7815static int __init vmx_init(void)
7816{
8d14695f 7817 int r, i, msr;
26bb0981
AK		 7818
7819 rdmsrl_safe(MSR_EFER, &host_efer);
7820
7821 for (i = 0; i < NR_VMX_MSR; ++i)
7822 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7823
3e7c73e9 7824 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7825 if (!vmx_io_bitmap_a)
7826 return -ENOMEM;
7827
2106a548
GC		 7828 r = -ENOMEM;
7829
3e7c73e9 7830 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7831 if (!vmx_io_bitmap_b)
fdef3ad1 7832 goto out;
fdef3ad1 7833
5897297b 7834 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7835 if (!vmx_msr_bitmap_legacy)
25c5f225 7836 goto out1;
2106a548 7837
8d14695f
YZ		 7838 vmx_msr_bitmap_legacy_x2apic =
7839 (unsigned long *)__get_free_page(GFP_KERNEL);
7840 if (!vmx_msr_bitmap_legacy_x2apic)
7841 goto out2;
25c5f225 7842
5897297b 7843 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7844 if (!vmx_msr_bitmap_longmode)
8d14695f 7845 goto out3;
2106a548 7846
8d14695f
YZ		 7847 vmx_msr_bitmap_longmode_x2apic =
7848 (unsigned long *)__get_free_page(GFP_KERNEL);
7849 if (!vmx_msr_bitmap_longmode_x2apic)
7850 goto out4;
5897297b 7851
fdef3ad1
HQ		 7852 /*
7853 * Allow direct access to the PC debug port (it is often used for I/O
7854 * delays, but the vmexits simply slow things down).
7855 */
3e7c73e9
AK		 7856 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7857 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7858
3e7c73e9 7859 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7860
5897297b
AK		 7861 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7862 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7863
2384d2b3
SY		 7864 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7865
0ee75bea
AK		 7866 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7867 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7868 if (r)
458f212e 7869 goto out5;
25c5f225 7870
8f536b76
ZY		 7871#ifdef CONFIG_KEXEC
7872 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7873 crash_vmclear_local_loaded_vmcss);
7874#endif
7875
5897297b
AK		 7876 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7877 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7878 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7879 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7880 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7881 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 7882 memcpy(vmx_msr_bitmap_legacy_x2apic,
7883 vmx_msr_bitmap_legacy, PAGE_SIZE);
7884 memcpy(vmx_msr_bitmap_longmode_x2apic,
7885 vmx_msr_bitmap_longmode, PAGE_SIZE);
7886
01e439be 7887 if (enable_apicv) {
8d14695f
YZ		 7888 for (msr = 0x800; msr <= 0x8ff; msr++)
7889 vmx_disable_intercept_msr_read_x2apic(msr);
7890
7891 /* According SDM, in x2apic mode, the whole id reg is used.
7892 * But in KVM, it only use the highest eight bits. Need to
7893 * intercept it */
7894 vmx_enable_intercept_msr_read_x2apic(0x802);
7895 /* TMCCT */
7896 vmx_enable_intercept_msr_read_x2apic(0x839);
7897 /* TPR */
7898 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 7899 /* EOI */
7900 vmx_disable_intercept_msr_write_x2apic(0x80b);
7901 /* SELF-IPI */
7902 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 7903 }
fdef3ad1 7904
089d034e 7905 if (enable_ept) {
3f6d8c8a
XH		 7906 kvm_mmu_set_mask_ptes(0ull,
7907 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7908 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7909 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7910 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7911 kvm_enable_tdp();
7912 } else
7913 kvm_disable_tdp();
1439442c 7914
fdef3ad1
HQ		 7915 return 0;
7916
458f212e
YZ		 7917out5:
7918 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 7919out4:
5897297b 7920 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 7921out3:
7922 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 7923out2:
5897297b 7924 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7925out1:
3e7c73e9 7926 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7927out:
3e7c73e9 7928 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7929 return r;
6aa8b732
AK		 7930}
7931
7932static void __exit vmx_exit(void)
7933{
8d14695f
YZ		 7934 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7935 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 7936 free_page((unsigned long)vmx_msr_bitmap_legacy);
7937 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7938 free_page((unsigned long)vmx_io_bitmap_b);
7939 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7940
8f536b76
ZY		 7941#ifdef CONFIG_KEXEC
7942 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7943 synchronize_rcu();
7944#endif
7945
cb498ea2 7946 kvm_exit();
6aa8b732
AK		 7947}
7948
7949module_init(vmx_init)
7950module_exit(vmx_exit)
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