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x86/kexec: VMCLEAR VMCSs loaded on all cpus if necessary
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
a27685c3 77static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
83287ea4
AK		 130extern const ulong vmx_return;
131
8bf00a52 132#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 133#define VMCS02_POOL_SIZE 1
61d2ef2c 134
a2fa3e9f
GH		 135struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139};
140
d462b819
NHE		 141/*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151};
152
26bb0981
AK		 153struct shared_msr_entry {
154 unsigned index;
155 u64 data;
d5696725 156 u64 mask;
26bb0981
AK		 157};
158
a9d30f33
NHE		 159/*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
22bd0358 172typedef u64 natural_width;
a9d30f33
NHE		 173struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
22bd0358 179
27d6c865
NHE		 180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
22bd0358
NHE		 183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
302 u32 padding32[8]; /* room for future expansion */
303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
a9d30f33
NHE		 319};
320
321/*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326#define VMCS12_REVISION 0x11e57ed0
327
328/*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333#define VMCS12_SIZE 0x1000
334
ff2f6fe9
NHE		 335/* Used to remember the last vmcs02 used for some recently used vmcs12s */
336struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340};
341
ec378aee
NHE		 342/*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
a9d30f33
NHE		 349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
fe3ef05c 359 u64 vmcs01_tsc_offset;
644d711a
NHE		 360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
fe3ef05c
NHE		 362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
ec378aee
NHE		 367};
368
a2fa3e9f 369struct vcpu_vmx {
fb3f0f51 370 struct kvm_vcpu vcpu;
313dbd49 371 unsigned long host_rsp;
29bd8a78 372 u8 fail;
69c73028 373 u8 cpl;
9d58b931 374 bool nmi_known_unmasked;
51aa01d1 375 u32 exit_intr_info;
1155f76a 376 u32 idt_vectoring_info;
6de12732 377 ulong rflags;
26bb0981 378 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 379 int nmsrs;
380 int save_nmsrs;
a2fa3e9f 381#ifdef CONFIG_X86_64
44ea2b17
AK		 382 u64 msr_host_kernel_gs_base;
383 u64 msr_guest_kernel_gs_base;
a2fa3e9f 384#endif
d462b819
NHE		 385 /*
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
389 */
390 struct loaded_vmcs vmcs01;
391 struct loaded_vmcs *loaded_vmcs;
392 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 393 struct msr_autoload {
394 unsigned nr;
395 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
396 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
397 } msr_autoload;
a2fa3e9f
GH		 398 struct {
399 int loaded;
400 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 401#ifdef CONFIG_X86_64
402 u16 ds_sel, es_sel;
403#endif
152d3f2f
LV		 404 int gs_ldt_reload_needed;
405 int fs_reload_needed;
d77c26fc 406 } host_state;
9c8cba37 407 struct {
7ffd92c5 408 int vm86_active;
78ac8b47 409 ulong save_rflags;
f5f7b2fe
AK		 410 struct kvm_segment segs[8];
411 } rmode;
412 struct {
413 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 414 struct kvm_save_segment {
415 u16 selector;
416 unsigned long base;
417 u32 limit;
418 u32 ar;
f5f7b2fe 419 } seg[8];
2fb92db1 420 } segment_cache;
2384d2b3 421 int vpid;
04fa4d32 422 bool emulation_required;
3b86cd99
JK		 423
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked;
426 ktime_t entry_time;
427 s64 vnmi_blocked_time;
a0861c02 428 u32 exit_reason;
4e47c7a6
SY		 429
430 bool rdtscp_enabled;
ec378aee
NHE		 431
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested;
a2fa3e9f
GH		 434};
435
2fb92db1
AK		 436enum segment_cache_field {
437 SEG_FIELD_SEL = 0,
438 SEG_FIELD_BASE = 1,
439 SEG_FIELD_LIMIT = 2,
440 SEG_FIELD_AR = 3,
441
442 SEG_FIELD_NR = 4
443};
444
a2fa3e9f
GH		 445static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446{
fb3f0f51 447 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 448}
449
22bd0358
NHE		 450#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
454
772e0318 455static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 456 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
457 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
458 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
459 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
460 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
461 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
462 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
463 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
464 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
465 FIELD(HOST_ES_SELECTOR, host_es_selector),
466 FIELD(HOST_CS_SELECTOR, host_cs_selector),
467 FIELD(HOST_SS_SELECTOR, host_ss_selector),
468 FIELD(HOST_DS_SELECTOR, host_ds_selector),
469 FIELD(HOST_FS_SELECTOR, host_fs_selector),
470 FIELD(HOST_GS_SELECTOR, host_gs_selector),
471 FIELD(HOST_TR_SELECTOR, host_tr_selector),
472 FIELD64(IO_BITMAP_A, io_bitmap_a),
473 FIELD64(IO_BITMAP_B, io_bitmap_b),
474 FIELD64(MSR_BITMAP, msr_bitmap),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
478 FIELD64(TSC_OFFSET, tsc_offset),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
480 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
481 FIELD64(EPT_POINTER, ept_pointer),
482 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
483 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
484 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
485 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
486 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
488 FIELD64(GUEST_PDPTR0, guest_pdptr0),
489 FIELD64(GUEST_PDPTR1, guest_pdptr1),
490 FIELD64(GUEST_PDPTR2, guest_pdptr2),
491 FIELD64(GUEST_PDPTR3, guest_pdptr3),
492 FIELD64(HOST_IA32_PAT, host_ia32_pat),
493 FIELD64(HOST_IA32_EFER, host_ia32_efer),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
497 FIELD(EXCEPTION_BITMAP, exception_bitmap),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
500 FIELD(CR3_TARGET_COUNT, cr3_target_count),
501 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
502 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
504 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
509 FIELD(TPR_THRESHOLD, tpr_threshold),
510 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
511 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
512 FIELD(VM_EXIT_REASON, vm_exit_reason),
513 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
514 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
515 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
516 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
517 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
518 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
519 FIELD(GUEST_ES_LIMIT, guest_es_limit),
520 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
521 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
522 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
523 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
524 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
525 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
526 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
527 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
528 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
529 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
530 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
531 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
532 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
533 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
534 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
535 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
536 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
538 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
539 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
540 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
541 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
542 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
543 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
544 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
545 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
546 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
547 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
548 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
549 FIELD(EXIT_QUALIFICATION, exit_qualification),
550 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
551 FIELD(GUEST_CR0, guest_cr0),
552 FIELD(GUEST_CR3, guest_cr3),
553 FIELD(GUEST_CR4, guest_cr4),
554 FIELD(GUEST_ES_BASE, guest_es_base),
555 FIELD(GUEST_CS_BASE, guest_cs_base),
556 FIELD(GUEST_SS_BASE, guest_ss_base),
557 FIELD(GUEST_DS_BASE, guest_ds_base),
558 FIELD(GUEST_FS_BASE, guest_fs_base),
559 FIELD(GUEST_GS_BASE, guest_gs_base),
560 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
561 FIELD(GUEST_TR_BASE, guest_tr_base),
562 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
563 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
564 FIELD(GUEST_DR7, guest_dr7),
565 FIELD(GUEST_RSP, guest_rsp),
566 FIELD(GUEST_RIP, guest_rip),
567 FIELD(GUEST_RFLAGS, guest_rflags),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
569 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
570 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
571 FIELD(HOST_CR0, host_cr0),
572 FIELD(HOST_CR3, host_cr3),
573 FIELD(HOST_CR4, host_cr4),
574 FIELD(HOST_FS_BASE, host_fs_base),
575 FIELD(HOST_GS_BASE, host_gs_base),
576 FIELD(HOST_TR_BASE, host_tr_base),
577 FIELD(HOST_GDTR_BASE, host_gdtr_base),
578 FIELD(HOST_IDTR_BASE, host_idtr_base),
579 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
580 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
581 FIELD(HOST_RSP, host_rsp),
582 FIELD(HOST_RIP, host_rip),
583};
584static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585
586static inline short vmcs_field_to_offset(unsigned long field)
587{
588 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return -1;
590 return vmcs_field_to_offset_table[field];
591}
592
a9d30f33
NHE		 593static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594{
595 return to_vmx(vcpu)->nested.current_vmcs12;
596}
597
598static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599{
600 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 601 if (is_error_page(page))
a9d30f33 602 return NULL;
32cad84f 603
a9d30f33
NHE		 604 return page;
605}
606
607static void nested_release_page(struct page *page)
608{
609 kvm_release_page_dirty(page);
610}
611
612static void nested_release_page_clean(struct page *page)
613{
614 kvm_release_page_clean(page);
615}
616
4e1096d2 617static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 618static void kvm_cpu_vmxon(u64 addr);
619static void kvm_cpu_vmxoff(void);
aff48baa 620static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 621static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 622static void vmx_set_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
624static void vmx_get_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
75880a01 626
6aa8b732
AK		 627static DEFINE_PER_CPU(struct vmcs *, vmxarea);
628static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 629/*
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 */
633static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 634static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 635
3e7c73e9
AK		 636static unsigned long *vmx_io_bitmap_a;
637static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 638static unsigned long *vmx_msr_bitmap_legacy;
639static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 640
110312c8 641static bool cpu_has_load_ia32_efer;
8bf00a52 642static bool cpu_has_load_perf_global_ctrl;
110312c8 643
2384d2b3
SY		 644static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
645static DEFINE_SPINLOCK(vmx_vpid_lock);
646
1c3d14fe 647static struct vmcs_config {
6aa8b732
AK		 648 int size;
649 int order;
650 u32 revision_id;
1c3d14fe
YS		 651 u32 pin_based_exec_ctrl;
652 u32 cpu_based_exec_ctrl;
f78e0e2e 653 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 654 u32 vmexit_ctrl;
655 u32 vmentry_ctrl;
656} vmcs_config;
6aa8b732 657
efff9e53 658static struct vmx_capability {
d56f546d
SY		 659 u32 ept;
660 u32 vpid;
661} vmx_capability;
662
6aa8b732
AK		 663#define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
669 }
670
772e0318 671static const struct kvm_vmx_segment_field {
6aa8b732
AK		 672 unsigned selector;
673 unsigned base;
674 unsigned limit;
675 unsigned ar_bytes;
676} kvm_vmx_segment_fields[] = {
677 VMX_SEGMENT_FIELD(CS),
678 VMX_SEGMENT_FIELD(DS),
679 VMX_SEGMENT_FIELD(ES),
680 VMX_SEGMENT_FIELD(FS),
681 VMX_SEGMENT_FIELD(GS),
682 VMX_SEGMENT_FIELD(SS),
683 VMX_SEGMENT_FIELD(TR),
684 VMX_SEGMENT_FIELD(LDTR),
685};
686
26bb0981
AK		 687static u64 host_efer;
688
6de4f3ad
AK		 689static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
690
4d56c8a7 691/*
8c06585d 692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 693 * away by decrementing the array size.
694 */
6aa8b732 695static const u32 vmx_msr_index[] = {
05b3e0c2 696#ifdef CONFIG_X86_64
44ea2b17 697 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 698#endif
8c06585d 699 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 700};
9d8f549d 701#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 702
31299944 703static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 704{
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
706 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 707 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 708}
709
31299944 710static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 711{
712 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
713 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 714 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 715}
716
31299944 717static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 718{
719 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
720 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 721 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 722}
723
31299944 724static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 725{
726 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
727 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
728}
729
31299944 730static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 731{
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
733 INTR_INFO_VALID_MASK)) ==
734 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
735}
736
31299944 737static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 738{
04547156 739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 740}
741
31299944 742static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 743{
04547156 744 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 745}
746
31299944 747static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 748{
04547156 749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 750}
751
31299944 752static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 753{
04547156
SY		 754 return vmcs_config.cpu_based_exec_ctrl &
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 756}
757
774ead3a 758static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 759{
04547156
SY		 760 return vmcs_config.cpu_based_2nd_exec_ctrl &
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
762}
763
764static inline bool cpu_has_vmx_flexpriority(void)
765{
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 768}
769
e799794e
MT		 770static inline bool cpu_has_vmx_ept_execute_only(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 773}
774
775static inline bool cpu_has_vmx_eptp_uncacheable(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 778}
779
780static inline bool cpu_has_vmx_eptp_writeback(void)
781{
31299944 782 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 783}
784
785static inline bool cpu_has_vmx_ept_2m_page(void)
786{
31299944 787 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 788}
789
878403b7
SY		 790static inline bool cpu_has_vmx_ept_1g_page(void)
791{
31299944 792 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 793}
794
4bc9b982
SY		 795static inline bool cpu_has_vmx_ept_4levels(void)
796{
797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
798}
799
83c3a331
XH		 800static inline bool cpu_has_vmx_ept_ad_bits(void)
801{
802 return vmx_capability.ept & VMX_EPT_AD_BIT;
803}
804
31299944 805static inline bool cpu_has_vmx_invept_context(void)
d56f546d 806{
31299944 807 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 808}
809
31299944 810static inline bool cpu_has_vmx_invept_global(void)
d56f546d 811{
31299944 812 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 813}
814
518c8aee
GJ		 815static inline bool cpu_has_vmx_invvpid_single(void)
816{
817 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
818}
819
b9d762fa
GJ		 820static inline bool cpu_has_vmx_invvpid_global(void)
821{
822 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
823}
824
31299944 825static inline bool cpu_has_vmx_ept(void)
d56f546d 826{
04547156
SY		 827 return vmcs_config.cpu_based_2nd_exec_ctrl &
828 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 829}
830
31299944 831static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 832{
833 return vmcs_config.cpu_based_2nd_exec_ctrl &
834 SECONDARY_EXEC_UNRESTRICTED_GUEST;
835}
836
31299944 837static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 838{
839 return vmcs_config.cpu_based_2nd_exec_ctrl &
840 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
841}
842
31299944 843static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 844{
6d3e435e 845 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 846}
847
31299944 848static inline bool cpu_has_vmx_vpid(void)
2384d2b3 849{
04547156
SY		 850 return vmcs_config.cpu_based_2nd_exec_ctrl &
851 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 852}
853
31299944 854static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 855{
856 return vmcs_config.cpu_based_2nd_exec_ctrl &
857 SECONDARY_EXEC_RDTSCP;
858}
859
ad756a16
MJ		 860static inline bool cpu_has_vmx_invpcid(void)
861{
862 return vmcs_config.cpu_based_2nd_exec_ctrl &
863 SECONDARY_EXEC_ENABLE_INVPCID;
864}
865
31299944 866static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 867{
868 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
869}
870
f5f48ee1
SY		 871static inline bool cpu_has_vmx_wbinvd_exit(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_WBINVD_EXITING;
875}
876
04547156
SY		 877static inline bool report_flexpriority(void)
878{
879 return flexpriority_enabled;
880}
881
fe3ef05c
NHE		 882static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
883{
884 return vmcs12->cpu_based_vm_exec_control & bit;
885}
886
887static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
888{
889 return (vmcs12->cpu_based_vm_exec_control &
890 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
891 (vmcs12->secondary_vm_exec_control & bit);
892}
893
644d711a
NHE		 894static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
895 struct kvm_vcpu *vcpu)
896{
897 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
898}
899
900static inline bool is_exception(u32 intr_info)
901{
902 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
903 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
904}
905
906static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 907static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
908 struct vmcs12 *vmcs12,
909 u32 reason, unsigned long qualification);
910
8b9cf98c 911static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 912{
913 int i;
914
a2fa3e9f 915 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 916 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 917 return i;
918 return -1;
919}
920
2384d2b3
SY		 921static inline void __invvpid(int ext, u16 vpid, gva_t gva)
922{
923 struct {
924 u64 vpid : 16;
925 u64 rsvd : 48;
926 u64 gva;
927 } operand = { vpid, 0, gva };
928
4ecac3fd 929 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 930 /* CF==1 or ZF==1 --> rc = -1 */
931 "; ja 1f ; ud2 ; 1:"
932 : : "a"(&operand), "c"(ext) : "cc", "memory");
933}
934
1439442c
SY		 935static inline void __invept(int ext, u64 eptp, gpa_t gpa)
936{
937 struct {
938 u64 eptp, gpa;
939 } operand = {eptp, gpa};
940
4ecac3fd 941 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 942 /* CF==1 or ZF==1 --> rc = -1 */
943 "; ja 1f ; ud2 ; 1:\n"
944 : : "a" (&operand), "c" (ext) : "cc", "memory");
945}
946
26bb0981 947static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 948{
949 int i;
950
8b9cf98c 951 i = __find_msr_index(vmx, msr);
a75beee6 952 if (i >= 0)
a2fa3e9f 953 return &vmx->guest_msrs[i];
8b6d44c7 954 return NULL;
7725f0ba
AK		 955}
956
6aa8b732
AK		 957static void vmcs_clear(struct vmcs *vmcs)
958{
959 u64 phys_addr = __pa(vmcs);
960 u8 error;
961
4ecac3fd 962 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 963 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 964 : "cc", "memory");
965 if (error)
966 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
967 vmcs, phys_addr);
968}
969
d462b819
NHE		 970static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
971{
972 vmcs_clear(loaded_vmcs->vmcs);
973 loaded_vmcs->cpu = -1;
974 loaded_vmcs->launched = 0;
975}
976
7725b894
DX		 977static void vmcs_load(struct vmcs *vmcs)
978{
979 u64 phys_addr = __pa(vmcs);
980 u8 error;
981
982 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 983 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 984 : "cc", "memory");
985 if (error)
2844d849 986 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 987 vmcs, phys_addr);
988}
989
d462b819 990static void __loaded_vmcs_clear(void *arg)
6aa8b732 991{
d462b819 992 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 993 int cpu = raw_smp_processor_id();
6aa8b732 994
d462b819
NHE		 995 if (loaded_vmcs->cpu != cpu)
996 return; /* vcpu migration can race with cpu offline */
997 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 998 per_cpu(current_vmcs, cpu) = NULL;
d462b819 999 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1000
1001 /*
1002 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1003 * is before setting loaded_vmcs->vcpu to -1 which is done in
1004 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1005 * then adds the vmcs into percpu list before it is deleted.
1006 */
1007 smp_wmb();
1008
d462b819 1009 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 1010}
1011
d462b819 1012static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1013{
e6c7d321
XG		 1014 int cpu = loaded_vmcs->cpu;
1015
1016 if (cpu != -1)
1017 smp_call_function_single(cpu,
1018 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1019}
1020
1760dd49 1021static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1022{
1023 if (vmx->vpid == 0)
1024 return;
1025
518c8aee
GJ		 1026 if (cpu_has_vmx_invvpid_single())
1027 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1028}
1029
b9d762fa
GJ		 1030static inline void vpid_sync_vcpu_global(void)
1031{
1032 if (cpu_has_vmx_invvpid_global())
1033 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1034}
1035
1036static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1037{
1038 if (cpu_has_vmx_invvpid_single())
1760dd49 1039 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1040 else
1041 vpid_sync_vcpu_global();
1042}
1043
1439442c
SY		 1044static inline void ept_sync_global(void)
1045{
1046 if (cpu_has_vmx_invept_global())
1047 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1048}
1049
1050static inline void ept_sync_context(u64 eptp)
1051{
089d034e 1052 if (enable_ept) {
1439442c
SY		 1053 if (cpu_has_vmx_invept_context())
1054 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1055 else
1056 ept_sync_global();
1057 }
1058}
1059
96304217 1060static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1061{
5e520e62 1062 unsigned long value;
6aa8b732 1063
5e520e62
AK		 1064 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1065 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1066 return value;
1067}
1068
96304217 1069static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1070{
1071 return vmcs_readl(field);
1072}
1073
96304217 1074static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1075{
1076 return vmcs_readl(field);
1077}
1078
96304217 1079static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1080{
05b3e0c2 1081#ifdef CONFIG_X86_64
6aa8b732
AK		 1082 return vmcs_readl(field);
1083#else
1084 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1085#endif
1086}
1087
e52de1b8
AK		 1088static noinline void vmwrite_error(unsigned long field, unsigned long value)
1089{
1090 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1091 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1092 dump_stack();
1093}
1094
6aa8b732
AK		 1095static void vmcs_writel(unsigned long field, unsigned long value)
1096{
1097 u8 error;
1098
4ecac3fd 1099 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1100 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1101 if (unlikely(error))
1102 vmwrite_error(field, value);
6aa8b732
AK		 1103}
1104
1105static void vmcs_write16(unsigned long field, u16 value)
1106{
1107 vmcs_writel(field, value);
1108}
1109
1110static void vmcs_write32(unsigned long field, u32 value)
1111{
1112 vmcs_writel(field, value);
1113}
1114
1115static void vmcs_write64(unsigned long field, u64 value)
1116{
6aa8b732 1117 vmcs_writel(field, value);
7682f2d0 1118#ifndef CONFIG_X86_64
6aa8b732
AK		 1119 asm volatile ("");
1120 vmcs_writel(field+1, value >> 32);
1121#endif
1122}
1123
2ab455cc
AL		 1124static void vmcs_clear_bits(unsigned long field, u32 mask)
1125{
1126 vmcs_writel(field, vmcs_readl(field) & ~mask);
1127}
1128
1129static void vmcs_set_bits(unsigned long field, u32 mask)
1130{
1131 vmcs_writel(field, vmcs_readl(field) | mask);
1132}
1133
2fb92db1
AK		 1134static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1135{
1136 vmx->segment_cache.bitmask = 0;
1137}
1138
1139static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1140 unsigned field)
1141{
1142 bool ret;
1143 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1144
1145 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1146 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1147 vmx->segment_cache.bitmask = 0;
1148 }
1149 ret = vmx->segment_cache.bitmask & mask;
1150 vmx->segment_cache.bitmask |= mask;
1151 return ret;
1152}
1153
1154static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1155{
1156 u16 *p = &vmx->segment_cache.seg[seg].selector;
1157
1158 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1159 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1160 return *p;
1161}
1162
1163static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1164{
1165 ulong *p = &vmx->segment_cache.seg[seg].base;
1166
1167 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1168 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1169 return *p;
1170}
1171
1172static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1173{
1174 u32 *p = &vmx->segment_cache.seg[seg].limit;
1175
1176 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1177 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1178 return *p;
1179}
1180
1181static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1182{
1183 u32 *p = &vmx->segment_cache.seg[seg].ar;
1184
1185 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1186 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1187 return *p;
1188}
1189
abd3f2d6
AK		 1190static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1191{
1192 u32 eb;
1193
fd7373cc
JK		 1194 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1195 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1196 if ((vcpu->guest_debug &
1197 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1198 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1199 eb |= 1u << BP_VECTOR;
7ffd92c5 1200 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1201 eb = ~0;
089d034e 1202 if (enable_ept)
1439442c 1203 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1204 if (vcpu->fpu_active)
1205 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1206
1207 /* When we are running a nested L2 guest and L1 specified for it a
1208 * certain exception bitmap, we must trap the same exceptions and pass
1209 * them to L1. When running L2, we will only handle the exceptions
1210 * specified above if L1 did not want them.
1211 */
1212 if (is_guest_mode(vcpu))
1213 eb |= get_vmcs12(vcpu)->exception_bitmap;
1214
abd3f2d6
AK		 1215 vmcs_write32(EXCEPTION_BITMAP, eb);
1216}
1217
8bf00a52
GN		 1218static void clear_atomic_switch_msr_special(unsigned long entry,
1219 unsigned long exit)
1220{
1221 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1222 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1223}
1224
61d2ef2c
AK		 1225static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1226{
1227 unsigned i;
1228 struct msr_autoload *m = &vmx->msr_autoload;
1229
8bf00a52
GN		 1230 switch (msr) {
1231 case MSR_EFER:
1232 if (cpu_has_load_ia32_efer) {
1233 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1234 VM_EXIT_LOAD_IA32_EFER);
1235 return;
1236 }
1237 break;
1238 case MSR_CORE_PERF_GLOBAL_CTRL:
1239 if (cpu_has_load_perf_global_ctrl) {
1240 clear_atomic_switch_msr_special(
1241 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1242 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1243 return;
1244 }
1245 break;
110312c8
AK		 1246 }
1247
61d2ef2c
AK		 1248 for (i = 0; i < m->nr; ++i)
1249 if (m->guest[i].index == msr)
1250 break;
1251
1252 if (i == m->nr)
1253 return;
1254 --m->nr;
1255 m->guest[i] = m->guest[m->nr];
1256 m->host[i] = m->host[m->nr];
1257 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1258 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1259}
1260
8bf00a52
GN		 1261static void add_atomic_switch_msr_special(unsigned long entry,
1262 unsigned long exit, unsigned long guest_val_vmcs,
1263 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1264{
1265 vmcs_write64(guest_val_vmcs, guest_val);
1266 vmcs_write64(host_val_vmcs, host_val);
1267 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1268 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1269}
1270
61d2ef2c
AK		 1271static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1272 u64 guest_val, u64 host_val)
1273{
1274 unsigned i;
1275 struct msr_autoload *m = &vmx->msr_autoload;
1276
8bf00a52
GN		 1277 switch (msr) {
1278 case MSR_EFER:
1279 if (cpu_has_load_ia32_efer) {
1280 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1281 VM_EXIT_LOAD_IA32_EFER,
1282 GUEST_IA32_EFER,
1283 HOST_IA32_EFER,
1284 guest_val, host_val);
1285 return;
1286 }
1287 break;
1288 case MSR_CORE_PERF_GLOBAL_CTRL:
1289 if (cpu_has_load_perf_global_ctrl) {
1290 add_atomic_switch_msr_special(
1291 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1292 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1293 GUEST_IA32_PERF_GLOBAL_CTRL,
1294 HOST_IA32_PERF_GLOBAL_CTRL,
1295 guest_val, host_val);
1296 return;
1297 }
1298 break;
110312c8
AK		 1299 }
1300
61d2ef2c
AK		 1301 for (i = 0; i < m->nr; ++i)
1302 if (m->guest[i].index == msr)
1303 break;
1304
e7fc6f93
GN		 1305 if (i == NR_AUTOLOAD_MSRS) {
1306 printk_once(KERN_WARNING"Not enough mst switch entries. "
1307 "Can't add msr %x\n", msr);
1308 return;
1309 } else if (i == m->nr) {
61d2ef2c
AK		 1310 ++m->nr;
1311 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1312 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1313 }
1314
1315 m->guest[i].index = msr;
1316 m->guest[i].value = guest_val;
1317 m->host[i].index = msr;
1318 m->host[i].value = host_val;
1319}
1320
33ed6329
AK		 1321static void reload_tss(void)
1322{
33ed6329
AK		 1323 /*
1324 * VT restores TR but not its size. Useless.
1325 */
d359192f 1326 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1327 struct desc_struct *descs;
33ed6329 1328
d359192f 1329 descs = (void *)gdt->address;
33ed6329
AK		 1330 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1331 load_TR_desc();
33ed6329
AK		 1332}
1333
92c0d900 1334static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1335{
3a34a881 1336 u64 guest_efer;
51c6cf66
AK		 1337 u64 ignore_bits;
1338
f6801dff 1339 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1340
51c6cf66 1341 /*
0fa06071 1342 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1343 * outside long mode
1344 */
1345 ignore_bits = EFER_NX | EFER_SCE;
1346#ifdef CONFIG_X86_64
1347 ignore_bits |= EFER_LMA | EFER_LME;
1348 /* SCE is meaningful only in long mode on Intel */
1349 if (guest_efer & EFER_LMA)
1350 ignore_bits &= ~(u64)EFER_SCE;
1351#endif
51c6cf66
AK		 1352 guest_efer &= ~ignore_bits;
1353 guest_efer |= host_efer & ignore_bits;
26bb0981 1354 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1355 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1356
1357 clear_atomic_switch_msr(vmx, MSR_EFER);
1358 /* On ept, can't emulate nx, and must switch nx atomically */
1359 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1360 guest_efer = vmx->vcpu.arch.efer;
1361 if (!(guest_efer & EFER_LMA))
1362 guest_efer &= ~EFER_LME;
1363 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1364 return false;
1365 }
1366
26bb0981 1367 return true;
51c6cf66
AK		 1368}
1369
2d49ec72
GN		 1370static unsigned long segment_base(u16 selector)
1371{
d359192f 1372 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1373 struct desc_struct *d;
1374 unsigned long table_base;
1375 unsigned long v;
1376
1377 if (!(selector & ~3))
1378 return 0;
1379
d359192f 1380 table_base = gdt->address;
2d49ec72
GN		 1381
1382 if (selector & 4) { /* from ldt */
1383 u16 ldt_selector = kvm_read_ldt();
1384
1385 if (!(ldt_selector & ~3))
1386 return 0;
1387
1388 table_base = segment_base(ldt_selector);
1389 }
1390 d = (struct desc_struct *)(table_base + (selector & ~7));
1391 v = get_desc_base(d);
1392#ifdef CONFIG_X86_64
1393 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1394 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1395#endif
1396 return v;
1397}
1398
1399static inline unsigned long kvm_read_tr_base(void)
1400{
1401 u16 tr;
1402 asm("str %0" : "=g"(tr));
1403 return segment_base(tr);
1404}
1405
04d2cc77 1406static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1407{
04d2cc77 1408 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1409 int i;
04d2cc77 1410
a2fa3e9f 1411 if (vmx->host_state.loaded)
33ed6329
AK		 1412 return;
1413
a2fa3e9f 1414 vmx->host_state.loaded = 1;
33ed6329
AK		 1415 /*
1416 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1417 * allow segment selectors with cpl > 0 or ti == 1.
1418 */
d6e88aec 1419 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1420 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1421 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1422 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1423 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1424 vmx->host_state.fs_reload_needed = 0;
1425 } else {
33ed6329 1426 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1427 vmx->host_state.fs_reload_needed = 1;
33ed6329 1428 }
9581d442 1429 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1430 if (!(vmx->host_state.gs_sel & 7))
1431 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1432 else {
1433 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1434 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1435 }
1436
b2da15ac
AK		 1437#ifdef CONFIG_X86_64
1438 savesegment(ds, vmx->host_state.ds_sel);
1439 savesegment(es, vmx->host_state.es_sel);
1440#endif
1441
33ed6329
AK		 1442#ifdef CONFIG_X86_64
1443 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1444 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1445#else
a2fa3e9f
GH		 1446 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1447 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1448#endif
707c0874
AK		 1449
1450#ifdef CONFIG_X86_64
c8770e7b
AK		 1451 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1452 if (is_long_mode(&vmx->vcpu))
44ea2b17 1453 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1454#endif
26bb0981
AK		 1455 for (i = 0; i < vmx->save_nmsrs; ++i)
1456 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1457 vmx->guest_msrs[i].data,
1458 vmx->guest_msrs[i].mask);
33ed6329
AK		 1459}
1460
a9b21b62 1461static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1462{
a2fa3e9f 1463 if (!vmx->host_state.loaded)
33ed6329
AK		 1464 return;
1465
e1beb1d3 1466 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1467 vmx->host_state.loaded = 0;
c8770e7b
AK		 1468#ifdef CONFIG_X86_64
1469 if (is_long_mode(&vmx->vcpu))
1470 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1471#endif
152d3f2f 1472 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1473 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1474#ifdef CONFIG_X86_64
9581d442 1475 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1476#else
1477 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1478#endif
33ed6329 1479 }
0a77fe4c
AK		 1480 if (vmx->host_state.fs_reload_needed)
1481 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1482#ifdef CONFIG_X86_64
1483 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1484 loadsegment(ds, vmx->host_state.ds_sel);
1485 loadsegment(es, vmx->host_state.es_sel);
1486 }
b2da15ac 1487#endif
152d3f2f 1488 reload_tss();
44ea2b17 1489#ifdef CONFIG_X86_64
c8770e7b 1490 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1491#endif
b1a74bf8
SS		 1492 /*
1493 * If the FPU is not active (through the host task or
1494 * the guest vcpu), then restore the cr0.TS bit.
1495 */
1496 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1497 stts();
3444d7da 1498 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1499}
1500
a9b21b62
AK		 1501static void vmx_load_host_state(struct vcpu_vmx *vmx)
1502{
1503 preempt_disable();
1504 __vmx_load_host_state(vmx);
1505 preempt_enable();
1506}
1507
6aa8b732
AK		 1508/*
1509 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1510 * vcpu mutex is already taken.
1511 */
15ad7146 1512static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1513{
a2fa3e9f 1514 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1515 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1516
4610c9cc
DX		 1517 if (!vmm_exclusive)
1518 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1519 else if (vmx->loaded_vmcs->cpu != cpu)
1520 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1521
d462b819
NHE		 1522 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1523 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1524 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1525 }
1526
d462b819 1527 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1528 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1529 unsigned long sysenter_esp;
1530
a8eeb04a 1531 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1532 local_irq_disable();
5a560f8b
XG		 1533
1534 /*
1535 * Read loaded_vmcs->cpu should be before fetching
1536 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1537 * See the comments in __loaded_vmcs_clear().
1538 */
1539 smp_rmb();
1540
d462b819
NHE		 1541 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1542 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1543 local_irq_enable();
1544
6aa8b732
AK		 1545 /*
1546 * Linux uses per-cpu TSS and GDT, so set these when switching
1547 * processors.
1548 */
d6e88aec 1549 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1550 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1551
1552 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1553 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1554 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1555 }
6aa8b732
AK		 1556}
1557
1558static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1559{
a9b21b62 1560 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1561 if (!vmm_exclusive) {
d462b819
NHE		 1562 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1563 vcpu->cpu = -1;
4610c9cc
DX		 1564 kvm_cpu_vmxoff();
1565 }
6aa8b732
AK		 1566}
1567
5fd86fcf
AK		 1568static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1569{
81231c69
AK		 1570 ulong cr0;
1571
5fd86fcf
AK		 1572 if (vcpu->fpu_active)
1573 return;
1574 vcpu->fpu_active = 1;
81231c69
AK		 1575 cr0 = vmcs_readl(GUEST_CR0);
1576 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1577 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1578 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1579 update_exception_bitmap(vcpu);
edcafe3c 1580 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1581 if (is_guest_mode(vcpu))
1582 vcpu->arch.cr0_guest_owned_bits &=
1583 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1584 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1585}
1586
edcafe3c
AK		 1587static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1588
fe3ef05c
NHE		 1589/*
1590 * Return the cr0 value that a nested guest would read. This is a combination
1591 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1592 * its hypervisor (cr0_read_shadow).
1593 */
1594static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1595{
1596 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1597 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1598}
1599static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1600{
1601 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1602 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1603}
1604
5fd86fcf
AK		 1605static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1606{
36cf24e0
NHE		 1607 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1608 * set this *before* calling this function.
1609 */
edcafe3c 1610 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1611 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1612 update_exception_bitmap(vcpu);
edcafe3c
AK		 1613 vcpu->arch.cr0_guest_owned_bits = 0;
1614 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1615 if (is_guest_mode(vcpu)) {
1616 /*
1617 * L1's specified read shadow might not contain the TS bit,
1618 * so now that we turned on shadowing of this bit, we need to
1619 * set this bit of the shadow. Like in nested_vmx_run we need
1620 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1621 * up-to-date here because we just decached cr0.TS (and we'll
1622 * only update vmcs12->guest_cr0 on nested exit).
1623 */
1624 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1625 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1626 (vcpu->arch.cr0 & X86_CR0_TS);
1627 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1628 } else
1629 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1630}
1631
6aa8b732
AK		 1632static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1633{
78ac8b47 1634 unsigned long rflags, save_rflags;
345dcaa8 1635
6de12732
AK		 1636 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1637 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1638 rflags = vmcs_readl(GUEST_RFLAGS);
1639 if (to_vmx(vcpu)->rmode.vm86_active) {
1640 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1641 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1642 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1643 }
1644 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1645 }
6de12732 1646 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1647}
1648
1649static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1650{
6de12732 1651 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1652 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1653 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1654 if (to_vmx(vcpu)->rmode.vm86_active) {
1655 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1656 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1657 }
6aa8b732
AK		 1658 vmcs_writel(GUEST_RFLAGS, rflags);
1659}
1660
2809f5d2
GC		 1661static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1662{
1663 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1664 int ret = 0;
1665
1666 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1667 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1668 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1669 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1670
1671 return ret & mask;
1672}
1673
1674static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1675{
1676 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1677 u32 interruptibility = interruptibility_old;
1678
1679 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1680
48005f64 1681 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1682 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1683 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1684 interruptibility |= GUEST_INTR_STATE_STI;
1685
1686 if ((interruptibility != interruptibility_old))
1687 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1688}
1689
6aa8b732
AK		 1690static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1691{
1692 unsigned long rip;
6aa8b732 1693
5fdbf976 1694 rip = kvm_rip_read(vcpu);
6aa8b732 1695 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1696 kvm_rip_write(vcpu, rip);
6aa8b732 1697
2809f5d2
GC		 1698 /* skipping an emulated instruction also counts */
1699 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1700}
1701
0b6ac343
NHE		 1702/*
1703 * KVM wants to inject page-faults which it got to the guest. This function
1704 * checks whether in a nested guest, we need to inject them to L1 or L2.
1705 * This function assumes it is called with the exit reason in vmcs02 being
1706 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1707 * is running).
1708 */
1709static int nested_pf_handled(struct kvm_vcpu *vcpu)
1710{
1711 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1712
1713 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1714 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1715 return 0;
1716
1717 nested_vmx_vmexit(vcpu);
1718 return 1;
1719}
1720
298101da 1721static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1722 bool has_error_code, u32 error_code,
1723 bool reinject)
298101da 1724{
77ab6db0 1725 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1726 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1727
0b6ac343
NHE		 1728 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1729 nested_pf_handled(vcpu))
1730 return;
1731
8ab2d2e2 1732 if (has_error_code) {
77ab6db0 1733 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1734 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1735 }
77ab6db0 1736
7ffd92c5 1737 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1738 int inc_eip = 0;
1739 if (kvm_exception_is_soft(nr))
1740 inc_eip = vcpu->arch.event_exit_inst_len;
1741 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1742 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1743 return;
1744 }
1745
66fd3f7f
GN		 1746 if (kvm_exception_is_soft(nr)) {
1747 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1748 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1749 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1750 } else
1751 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1752
1753 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1754}
1755
4e47c7a6
SY		 1756static bool vmx_rdtscp_supported(void)
1757{
1758 return cpu_has_vmx_rdtscp();
1759}
1760
ad756a16
MJ		 1761static bool vmx_invpcid_supported(void)
1762{
1763 return cpu_has_vmx_invpcid() && enable_ept;
1764}
1765
a75beee6
ED		 1766/*
1767 * Swap MSR entry in host/guest MSR entry array.
1768 */
8b9cf98c 1769static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1770{
26bb0981 1771 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1772
1773 tmp = vmx->guest_msrs[to];
1774 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1775 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1776}
1777
e38aea3e
AK		 1778/*
1779 * Set up the vmcs to automatically save and restore system
1780 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1781 * mode, as fiddling with msrs is very expensive.
1782 */
8b9cf98c 1783static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1784{
26bb0981 1785 int save_nmsrs, index;
5897297b 1786 unsigned long *msr_bitmap;
e38aea3e 1787
a75beee6
ED		 1788 save_nmsrs = 0;
1789#ifdef CONFIG_X86_64
8b9cf98c 1790 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1791 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1792 if (index >= 0)
8b9cf98c
RR		 1793 move_msr_up(vmx, index, save_nmsrs++);
1794 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1795 if (index >= 0)
8b9cf98c
RR		 1796 move_msr_up(vmx, index, save_nmsrs++);
1797 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1798 if (index >= 0)
8b9cf98c 1799 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1800 index = __find_msr_index(vmx, MSR_TSC_AUX);
1801 if (index >= 0 && vmx->rdtscp_enabled)
1802 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1803 /*
8c06585d 1804 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1805 * if efer.sce is enabled.
1806 */
8c06585d 1807 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1808 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1809 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1810 }
1811#endif
92c0d900
AK		 1812 index = __find_msr_index(vmx, MSR_EFER);
1813 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1814 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1815
26bb0981 1816 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1817
1818 if (cpu_has_vmx_msr_bitmap()) {
1819 if (is_long_mode(&vmx->vcpu))
1820 msr_bitmap = vmx_msr_bitmap_longmode;
1821 else
1822 msr_bitmap = vmx_msr_bitmap_legacy;
1823
1824 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1825 }
e38aea3e
AK		 1826}
1827
6aa8b732
AK		 1828/*
1829 * reads and returns guest's timestamp counter "register"
1830 * guest_tsc = host_tsc + tsc_offset -- 21.3
1831 */
1832static u64 guest_read_tsc(void)
1833{
1834 u64 host_tsc, tsc_offset;
1835
1836 rdtscll(host_tsc);
1837 tsc_offset = vmcs_read64(TSC_OFFSET);
1838 return host_tsc + tsc_offset;
1839}
1840
d5c1785d
NHE		 1841/*
1842 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1843 * counter, even if a nested guest (L2) is currently running.
1844 */
886b470c 1845u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1846{
886b470c 1847 u64 tsc_offset;
d5c1785d 1848
d5c1785d
NHE		 1849 tsc_offset = is_guest_mode(vcpu) ?
1850 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1851 vmcs_read64(TSC_OFFSET);
1852 return host_tsc + tsc_offset;
1853}
1854
4051b188 1855/*
cc578287
ZA		 1856 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1857 * software catchup for faster rates on slower CPUs.
4051b188 1858 */
cc578287 1859static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1860{
cc578287
ZA		 1861 if (!scale)
1862 return;
1863
1864 if (user_tsc_khz > tsc_khz) {
1865 vcpu->arch.tsc_catchup = 1;
1866 vcpu->arch.tsc_always_catchup = 1;
1867 } else
1868 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1869}
1870
ba904635
WA		 1871static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1872{
1873 return vmcs_read64(TSC_OFFSET);
1874}
1875
6aa8b732 1876/*
99e3e30a 1877 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1878 */
99e3e30a 1879static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1880{
27fc51b2 1881 if (is_guest_mode(vcpu)) {
7991825b 1882 /*
27fc51b2
NHE		 1883 * We're here if L1 chose not to trap WRMSR to TSC. According
1884 * to the spec, this should set L1's TSC; The offset that L1
1885 * set for L2 remains unchanged, and still needs to be added
1886 * to the newly set TSC to get L2's TSC.
7991825b 1887 */
27fc51b2
NHE		 1888 struct vmcs12 *vmcs12;
1889 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1890 /* recalculate vmcs02.TSC_OFFSET: */
1891 vmcs12 = get_vmcs12(vcpu);
1892 vmcs_write64(TSC_OFFSET, offset +
1893 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1894 vmcs12->tsc_offset : 0));
1895 } else {
1896 vmcs_write64(TSC_OFFSET, offset);
1897 }
6aa8b732
AK		 1898}
1899
f1e2b260 1900static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1901{
1902 u64 offset = vmcs_read64(TSC_OFFSET);
1903 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1904 if (is_guest_mode(vcpu)) {
1905 /* Even when running L2, the adjustment needs to apply to L1 */
1906 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1907 }
e48672fa
ZA		 1908}
1909
857e4099
JR		 1910static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1911{
1912 return target_tsc - native_read_tsc();
1913}
1914
801d3424
NHE		 1915static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1916{
1917 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1918 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1919}
1920
1921/*
1922 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1923 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1924 * all guests if the "nested" module option is off, and can also be disabled
1925 * for a single guest by disabling its VMX cpuid bit.
1926 */
1927static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1928{
1929 return nested && guest_cpuid_has_vmx(vcpu);
1930}
1931
b87a51ae
NHE		 1932/*
1933 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1934 * returned for the various VMX controls MSRs when nested VMX is enabled.
1935 * The same values should also be used to verify that vmcs12 control fields are
1936 * valid during nested entry from L1 to L2.
1937 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1938 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1939 * bit in the high half is on if the corresponding bit in the control field
1940 * may be on. See also vmx_control_verify().
1941 * TODO: allow these variables to be modified (downgraded) by module options
1942 * or other means.
1943 */
1944static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1945static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1946static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1947static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1948static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1949static __init void nested_vmx_setup_ctls_msrs(void)
1950{
1951 /*
1952 * Note that as a general rule, the high half of the MSRs (bits in
1953 * the control fields which may be 1) should be initialized by the
1954 * intersection of the underlying hardware's MSR (i.e., features which
1955 * can be supported) and the list of features we want to expose -
1956 * because they are known to be properly supported in our code.
1957 * Also, usually, the low half of the MSRs (bits which must be 1) can
1958 * be set to 0, meaning that L1 may turn off any of these bits. The
1959 * reason is that if one of these bits is necessary, it will appear
1960 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1961 * fields of vmcs01 and vmcs02, will turn these bits off - and
1962 * nested_vmx_exit_handled() will not pass related exits to L1.
1963 * These rules have exceptions below.
1964 */
1965
1966 /* pin-based controls */
1967 /*
1968 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1969 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1970 */
1971 nested_vmx_pinbased_ctls_low = 0x16 ;
1972 nested_vmx_pinbased_ctls_high = 0x16 |
1973 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1974 PIN_BASED_VIRTUAL_NMIS;
1975
1976 /* exit controls */
1977 nested_vmx_exit_ctls_low = 0;
b6f1250e 1978 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1979#ifdef CONFIG_X86_64
1980 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1981#else
1982 nested_vmx_exit_ctls_high = 0;
1983#endif
1984
1985 /* entry controls */
1986 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1987 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1988 nested_vmx_entry_ctls_low = 0;
1989 nested_vmx_entry_ctls_high &=
1990 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1991
1992 /* cpu-based controls */
1993 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1994 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1995 nested_vmx_procbased_ctls_low = 0;
1996 nested_vmx_procbased_ctls_high &=
1997 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1998 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1999 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2000 CPU_BASED_CR3_STORE_EXITING |
2001#ifdef CONFIG_X86_64
2002 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2003#endif
2004 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2005 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2006 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2007 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2008 /*
2009 * We can allow some features even when not supported by the
2010 * hardware. For example, L1 can specify an MSR bitmap - and we
2011 * can use it to avoid exits to L1 - even when L0 runs L2
2012 * without MSR bitmaps.
2013 */
2014 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2015
2016 /* secondary cpu-based controls */
2017 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2018 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2019 nested_vmx_secondary_ctls_low = 0;
2020 nested_vmx_secondary_ctls_high &=
2021 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2022}
2023
2024static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2025{
2026 /*
2027 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2028 */
2029 return ((control & high) | low) == control;
2030}
2031
2032static inline u64 vmx_control_msr(u32 low, u32 high)
2033{
2034 return low | ((u64)high << 32);
2035}
2036
2037/*
2038 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2039 * also let it use VMX-specific MSRs.
2040 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2041 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2042 * like all other MSRs).
2043 */
2044static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2045{
2046 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2047 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2048 /*
2049 * According to the spec, processors which do not support VMX
2050 * should throw a #GP(0) when VMX capability MSRs are read.
2051 */
2052 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2053 return 1;
2054 }
2055
2056 switch (msr_index) {
2057 case MSR_IA32_FEATURE_CONTROL:
2058 *pdata = 0;
2059 break;
2060 case MSR_IA32_VMX_BASIC:
2061 /*
2062 * This MSR reports some information about VMX support. We
2063 * should return information about the VMX we emulate for the
2064 * guest, and the VMCS structure we give it - not about the
2065 * VMX support of the underlying hardware.
2066 */
2067 *pdata = VMCS12_REVISION |
2068 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2069 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2070 break;
2071 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2072 case MSR_IA32_VMX_PINBASED_CTLS:
2073 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2074 nested_vmx_pinbased_ctls_high);
2075 break;
2076 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2077 case MSR_IA32_VMX_PROCBASED_CTLS:
2078 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2079 nested_vmx_procbased_ctls_high);
2080 break;
2081 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2082 case MSR_IA32_VMX_EXIT_CTLS:
2083 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2084 nested_vmx_exit_ctls_high);
2085 break;
2086 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2087 case MSR_IA32_VMX_ENTRY_CTLS:
2088 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2089 nested_vmx_entry_ctls_high);
2090 break;
2091 case MSR_IA32_VMX_MISC:
2092 *pdata = 0;
2093 break;
2094 /*
2095 * These MSRs specify bits which the guest must keep fixed (on or off)
2096 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2097 * We picked the standard core2 setting.
2098 */
2099#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2100#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2101 case MSR_IA32_VMX_CR0_FIXED0:
2102 *pdata = VMXON_CR0_ALWAYSON;
2103 break;
2104 case MSR_IA32_VMX_CR0_FIXED1:
2105 *pdata = -1ULL;
2106 break;
2107 case MSR_IA32_VMX_CR4_FIXED0:
2108 *pdata = VMXON_CR4_ALWAYSON;
2109 break;
2110 case MSR_IA32_VMX_CR4_FIXED1:
2111 *pdata = -1ULL;
2112 break;
2113 case MSR_IA32_VMX_VMCS_ENUM:
2114 *pdata = 0x1f;
2115 break;
2116 case MSR_IA32_VMX_PROCBASED_CTLS2:
2117 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2118 nested_vmx_secondary_ctls_high);
2119 break;
2120 case MSR_IA32_VMX_EPT_VPID_CAP:
2121 /* Currently, no nested ept or nested vpid */
2122 *pdata = 0;
2123 break;
2124 default:
2125 return 0;
2126 }
2127
2128 return 1;
2129}
2130
2131static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2132{
2133 if (!nested_vmx_allowed(vcpu))
2134 return 0;
2135
2136 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2137 /* TODO: the right thing. */
2138 return 1;
2139 /*
2140 * No need to treat VMX capability MSRs specially: If we don't handle
2141 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2142 */
2143 return 0;
2144}
2145
6aa8b732
AK		 2146/*
2147 * Reads an msr value (of 'msr_index') into 'pdata'.
2148 * Returns 0 on success, non-0 otherwise.
2149 * Assumes vcpu_load() was already called.
2150 */
2151static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2152{
2153 u64 data;
26bb0981 2154 struct shared_msr_entry *msr;
6aa8b732
AK		 2155
2156 if (!pdata) {
2157 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2158 return -EINVAL;
2159 }
2160
2161 switch (msr_index) {
05b3e0c2 2162#ifdef CONFIG_X86_64
6aa8b732
AK		 2163 case MSR_FS_BASE:
2164 data = vmcs_readl(GUEST_FS_BASE);
2165 break;
2166 case MSR_GS_BASE:
2167 data = vmcs_readl(GUEST_GS_BASE);
2168 break;
44ea2b17
AK		 2169 case MSR_KERNEL_GS_BASE:
2170 vmx_load_host_state(to_vmx(vcpu));
2171 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2172 break;
26bb0981 2173#endif
6aa8b732 2174 case MSR_EFER:
3bab1f5d 2175 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2176 case MSR_IA32_TSC:
6aa8b732
AK		 2177 data = guest_read_tsc();
2178 break;
2179 case MSR_IA32_SYSENTER_CS:
2180 data = vmcs_read32(GUEST_SYSENTER_CS);
2181 break;
2182 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2183 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2184 break;
2185 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2186 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2187 break;
4e47c7a6
SY		 2188 case MSR_TSC_AUX:
2189 if (!to_vmx(vcpu)->rdtscp_enabled)
2190 return 1;
2191 /* Otherwise falls through */
6aa8b732 2192 default:
b87a51ae
NHE		 2193 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2194 return 0;
8b9cf98c 2195 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2196 if (msr) {
2197 data = msr->data;
2198 break;
6aa8b732 2199 }
3bab1f5d 2200 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2201 }
2202
2203 *pdata = data;
2204 return 0;
2205}
2206
2207/*
2208 * Writes msr value into into the appropriate "register".
2209 * Returns 0 on success, non-0 otherwise.
2210 * Assumes vcpu_load() was already called.
2211 */
8fe8ab46 2212static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2213{
a2fa3e9f 2214 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2215 struct shared_msr_entry *msr;
2cc51560 2216 int ret = 0;
8fe8ab46
WA		 2217 u32 msr_index = msr_info->index;
2218 u64 data = msr_info->data;
2cc51560 2219
6aa8b732 2220 switch (msr_index) {
3bab1f5d 2221 case MSR_EFER:
8fe8ab46 2222 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2223 break;
16175a79 2224#ifdef CONFIG_X86_64
6aa8b732 2225 case MSR_FS_BASE:
2fb92db1 2226 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2227 vmcs_writel(GUEST_FS_BASE, data);
2228 break;
2229 case MSR_GS_BASE:
2fb92db1 2230 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2231 vmcs_writel(GUEST_GS_BASE, data);
2232 break;
44ea2b17
AK		 2233 case MSR_KERNEL_GS_BASE:
2234 vmx_load_host_state(vmx);
2235 vmx->msr_guest_kernel_gs_base = data;
2236 break;
6aa8b732
AK		 2237#endif
2238 case MSR_IA32_SYSENTER_CS:
2239 vmcs_write32(GUEST_SYSENTER_CS, data);
2240 break;
2241 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2242 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2243 break;
2244 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2245 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2246 break;
af24a4e4 2247 case MSR_IA32_TSC:
8fe8ab46 2248 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2249 break;
468d472f
SY		 2250 case MSR_IA32_CR_PAT:
2251 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2252 vmcs_write64(GUEST_IA32_PAT, data);
2253 vcpu->arch.pat = data;
2254 break;
2255 }
8fe8ab46 2256 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2257 break;
ba904635
WA		 2258 case MSR_IA32_TSC_ADJUST:
2259 ret = kvm_set_msr_common(vcpu, msr_info);
2260 break;
4e47c7a6
SY		 2261 case MSR_TSC_AUX:
2262 if (!vmx->rdtscp_enabled)
2263 return 1;
2264 /* Check reserved bit, higher 32 bits should be zero */
2265 if ((data >> 32) != 0)
2266 return 1;
2267 /* Otherwise falls through */
6aa8b732 2268 default:
b87a51ae
NHE		 2269 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2270 break;
8b9cf98c 2271 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2272 if (msr) {
2273 msr->data = data;
2225fd56
AK		 2274 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2275 preempt_disable();
9ee73970
AK		 2276 kvm_set_shared_msr(msr->index, msr->data,
2277 msr->mask);
2225fd56
AK		 2278 preempt_enable();
2279 }
3bab1f5d 2280 break;
6aa8b732 2281 }
8fe8ab46 2282 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2283 }
2284
2cc51560 2285 return ret;
6aa8b732
AK		 2286}
2287
5fdbf976 2288static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2289{
5fdbf976
MT		 2290 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2291 switch (reg) {
2292 case VCPU_REGS_RSP:
2293 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2294 break;
2295 case VCPU_REGS_RIP:
2296 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2297 break;
6de4f3ad
AK		 2298 case VCPU_EXREG_PDPTR:
2299 if (enable_ept)
2300 ept_save_pdptrs(vcpu);
2301 break;
5fdbf976
MT		 2302 default:
2303 break;
2304 }
6aa8b732
AK		 2305}
2306
6aa8b732
AK		 2307static __init int cpu_has_kvm_support(void)
2308{
6210e37b 2309 return cpu_has_vmx();
6aa8b732
AK		 2310}
2311
2312static __init int vmx_disabled_by_bios(void)
2313{
2314 u64 msr;
2315
2316 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2317 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2318 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2319 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2320 && tboot_enabled())
2321 return 1;
23f3e991 2322 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2323 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2324 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2325 && !tboot_enabled()) {
2326 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2327 "activate TXT before enabling KVM\n");
cafd6659 2328 return 1;
f9335afe 2329 }
23f3e991
JC		 2330 /* launched w/o TXT and VMX disabled */
2331 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2332 && !tboot_enabled())
2333 return 1;
cafd6659
SW		 2334 }
2335
2336 return 0;
6aa8b732
AK		 2337}
2338
7725b894
DX		 2339static void kvm_cpu_vmxon(u64 addr)
2340{
2341 asm volatile (ASM_VMX_VMXON_RAX
2342 : : "a"(&addr), "m"(addr)
2343 : "memory", "cc");
2344}
2345
10474ae8 2346static int hardware_enable(void *garbage)
6aa8b732
AK		 2347{
2348 int cpu = raw_smp_processor_id();
2349 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2350 u64 old, test_bits;
6aa8b732 2351
10474ae8
AG		 2352 if (read_cr4() & X86_CR4_VMXE)
2353 return -EBUSY;
2354
d462b819 2355 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2356 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2357
2358 test_bits = FEATURE_CONTROL_LOCKED;
2359 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2360 if (tboot_enabled())
2361 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2362
2363 if ((old & test_bits) != test_bits) {
6aa8b732 2364 /* enable and lock */
cafd6659
SW		 2365 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2366 }
66aee91a 2367 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2368
4610c9cc
DX		 2369 if (vmm_exclusive) {
2370 kvm_cpu_vmxon(phys_addr);
2371 ept_sync_global();
2372 }
10474ae8 2373
3444d7da
AK		 2374 store_gdt(&__get_cpu_var(host_gdt));
2375
10474ae8 2376 return 0;
6aa8b732
AK		 2377}
2378
d462b819 2379static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2380{
2381 int cpu = raw_smp_processor_id();
d462b819 2382 struct loaded_vmcs *v, *n;
543e4243 2383
d462b819
NHE		 2384 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2385 loaded_vmcss_on_cpu_link)
2386 __loaded_vmcs_clear(v);
543e4243
AK		 2387}
2388
710ff4a8
EH		 2389
2390/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2391 * tricks.
2392 */
2393static void kvm_cpu_vmxoff(void)
6aa8b732 2394{
4ecac3fd 2395 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2396}
2397
710ff4a8
EH		 2398static void hardware_disable(void *garbage)
2399{
4610c9cc 2400 if (vmm_exclusive) {
d462b819 2401 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2402 kvm_cpu_vmxoff();
2403 }
7725b894 2404 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2405}
2406
1c3d14fe 2407static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2408 u32 msr, u32 *result)
1c3d14fe
YS		 2409{
2410 u32 vmx_msr_low, vmx_msr_high;
2411 u32 ctl = ctl_min | ctl_opt;
2412
2413 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2414
2415 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2416 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2417
2418 /* Ensure minimum (required) set of control bits are supported. */
2419 if (ctl_min & ~ctl)
002c7f7c 2420 return -EIO;
1c3d14fe
YS		 2421
2422 *result = ctl;
2423 return 0;
2424}
2425
110312c8
AK		 2426static __init bool allow_1_setting(u32 msr, u32 ctl)
2427{
2428 u32 vmx_msr_low, vmx_msr_high;
2429
2430 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2431 return vmx_msr_high & ctl;
2432}
2433
002c7f7c 2434static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2435{
2436 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2437 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2438 u32 _pin_based_exec_control = 0;
2439 u32 _cpu_based_exec_control = 0;
f78e0e2e 2440 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2441 u32 _vmexit_control = 0;
2442 u32 _vmentry_control = 0;
2443
2444 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2445 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2446 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2447 &_pin_based_exec_control) < 0)
002c7f7c 2448 return -EIO;
1c3d14fe 2449
10166744 2450 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2451#ifdef CONFIG_X86_64
2452 CPU_BASED_CR8_LOAD_EXITING |
2453 CPU_BASED_CR8_STORE_EXITING |
2454#endif
d56f546d
SY		 2455 CPU_BASED_CR3_LOAD_EXITING |
2456 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2457 CPU_BASED_USE_IO_BITMAPS |
2458 CPU_BASED_MOV_DR_EXITING |
a7052897 2459 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2460 CPU_BASED_MWAIT_EXITING |
2461 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2462 CPU_BASED_INVLPG_EXITING |
2463 CPU_BASED_RDPMC_EXITING;
443381a8 2464
f78e0e2e 2465 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2466 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2467 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2469 &_cpu_based_exec_control) < 0)
002c7f7c 2470 return -EIO;
6e5d865c
YS		 2471#ifdef CONFIG_X86_64
2472 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2473 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2474 ~CPU_BASED_CR8_STORE_EXITING;
2475#endif
f78e0e2e 2476 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2477 min2 = 0;
2478 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2479 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2480 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2481 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2482 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2483 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2484 SECONDARY_EXEC_RDTSCP |
2485 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2486 if (adjust_vmx_controls(min2, opt2,
2487 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2488 &_cpu_based_2nd_exec_control) < 0)
2489 return -EIO;
2490 }
2491#ifndef CONFIG_X86_64
2492 if (!(_cpu_based_2nd_exec_control &
2493 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2494 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2495#endif
d56f546d 2496 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2497 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2498 enabled */
5fff7d27
GN		 2499 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2500 CPU_BASED_CR3_STORE_EXITING |
2501 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2502 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2503 vmx_capability.ept, vmx_capability.vpid);
2504 }
1c3d14fe
YS		 2505
2506 min = 0;
2507#ifdef CONFIG_X86_64
2508 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2509#endif
468d472f 2510 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2511 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2512 &_vmexit_control) < 0)
002c7f7c 2513 return -EIO;
1c3d14fe 2514
468d472f
SY		 2515 min = 0;
2516 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2517 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2518 &_vmentry_control) < 0)
002c7f7c 2519 return -EIO;
6aa8b732 2520
c68876fd 2521 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2522
2523 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2524 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2525 return -EIO;
1c3d14fe
YS		 2526
2527#ifdef CONFIG_X86_64
2528 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2529 if (vmx_msr_high & (1u<<16))
002c7f7c 2530 return -EIO;
1c3d14fe
YS		 2531#endif
2532
2533 /* Require Write-Back (WB) memory type for VMCS accesses. */
2534 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2535 return -EIO;
1c3d14fe 2536
002c7f7c
YS		 2537 vmcs_conf->size = vmx_msr_high & 0x1fff;
2538 vmcs_conf->order = get_order(vmcs_config.size);
2539 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2540
002c7f7c
YS		 2541 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2542 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2543 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2544 vmcs_conf->vmexit_ctrl = _vmexit_control;
2545 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2546
110312c8
AK		 2547 cpu_has_load_ia32_efer =
2548 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2549 VM_ENTRY_LOAD_IA32_EFER)
2550 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2551 VM_EXIT_LOAD_IA32_EFER);
2552
8bf00a52
GN		 2553 cpu_has_load_perf_global_ctrl =
2554 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2555 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2556 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2557 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2558
2559 /*
2560 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2561 * but due to arrata below it can't be used. Workaround is to use
2562 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2563 *
2564 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2565 *
2566 * AAK155 (model 26)
2567 * AAP115 (model 30)
2568 * AAT100 (model 37)
2569 * BC86,AAY89,BD102 (model 44)
2570 * BA97 (model 46)
2571 *
2572 */
2573 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2574 switch (boot_cpu_data.x86_model) {
2575 case 26:
2576 case 30:
2577 case 37:
2578 case 44:
2579 case 46:
2580 cpu_has_load_perf_global_ctrl = false;
2581 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2582 "does not work properly. Using workaround\n");
2583 break;
2584 default:
2585 break;
2586 }
2587 }
2588
1c3d14fe 2589 return 0;
c68876fd 2590}
6aa8b732
AK		 2591
2592static struct vmcs *alloc_vmcs_cpu(int cpu)
2593{
2594 int node = cpu_to_node(cpu);
2595 struct page *pages;
2596 struct vmcs *vmcs;
2597
6484eb3e 2598 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2599 if (!pages)
2600 return NULL;
2601 vmcs = page_address(pages);
1c3d14fe
YS		 2602 memset(vmcs, 0, vmcs_config.size);
2603 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2604 return vmcs;
2605}
2606
2607static struct vmcs *alloc_vmcs(void)
2608{
d3b2c338 2609 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2610}
2611
2612static void free_vmcs(struct vmcs *vmcs)
2613{
1c3d14fe 2614 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2615}
2616
d462b819
NHE		 2617/*
2618 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2619 */
2620static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2621{
2622 if (!loaded_vmcs->vmcs)
2623 return;
2624 loaded_vmcs_clear(loaded_vmcs);
2625 free_vmcs(loaded_vmcs->vmcs);
2626 loaded_vmcs->vmcs = NULL;
2627}
2628
39959588 2629static void free_kvm_area(void)
6aa8b732
AK		 2630{
2631 int cpu;
2632
3230bb47 2633 for_each_possible_cpu(cpu) {
6aa8b732 2634 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2635 per_cpu(vmxarea, cpu) = NULL;
2636 }
6aa8b732
AK		 2637}
2638
6aa8b732
AK		 2639static __init int alloc_kvm_area(void)
2640{
2641 int cpu;
2642
3230bb47 2643 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2644 struct vmcs *vmcs;
2645
2646 vmcs = alloc_vmcs_cpu(cpu);
2647 if (!vmcs) {
2648 free_kvm_area();
2649 return -ENOMEM;
2650 }
2651
2652 per_cpu(vmxarea, cpu) = vmcs;
2653 }
2654 return 0;
2655}
2656
2657static __init int hardware_setup(void)
2658{
002c7f7c
YS		 2659 if (setup_vmcs_config(&vmcs_config) < 0)
2660 return -EIO;
50a37eb4
JR		 2661
2662 if (boot_cpu_has(X86_FEATURE_NX))
2663 kvm_enable_efer_bits(EFER_NX);
2664
93ba03c2
SY		 2665 if (!cpu_has_vmx_vpid())
2666 enable_vpid = 0;
2667
4bc9b982
SY		 2668 if (!cpu_has_vmx_ept() ||
2669 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2670 enable_ept = 0;
3a624e29 2671 enable_unrestricted_guest = 0;
83c3a331 2672 enable_ept_ad_bits = 0;
3a624e29
NK		 2673 }
2674
83c3a331
XH		 2675 if (!cpu_has_vmx_ept_ad_bits())
2676 enable_ept_ad_bits = 0;
2677
3a624e29
NK		 2678 if (!cpu_has_vmx_unrestricted_guest())
2679 enable_unrestricted_guest = 0;
93ba03c2
SY		 2680
2681 if (!cpu_has_vmx_flexpriority())
2682 flexpriority_enabled = 0;
2683
95ba8273
GN		 2684 if (!cpu_has_vmx_tpr_shadow())
2685 kvm_x86_ops->update_cr8_intercept = NULL;
2686
54dee993
MT		 2687 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2688 kvm_disable_largepages();
2689
4b8d54f9
ZE		 2690 if (!cpu_has_vmx_ple())
2691 ple_gap = 0;
2692
b87a51ae
NHE		 2693 if (nested)
2694 nested_vmx_setup_ctls_msrs();
2695
6aa8b732
AK		 2696 return alloc_kvm_area();
2697}
2698
2699static __exit void hardware_unsetup(void)
2700{
2701 free_kvm_area();
2702}
2703
f5f7b2fe 2704static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
6aa8b732 2705{
772e0318 2706 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
c865c43d 2707 struct kvm_segment tmp = *save;
6aa8b732 2708
c865c43d
AK		 2709 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2710 tmp.base = vmcs_readl(sf->base);
2711 tmp.selector = vmcs_read16(sf->selector);
2712 tmp.s = 1;
6aa8b732 2713 }
c865c43d 2714 vmx_set_segment(vcpu, &tmp, seg);
6aa8b732
AK		 2715}
2716
2717static void enter_pmode(struct kvm_vcpu *vcpu)
2718{
2719 unsigned long flags;
a89a8fb9 2720 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2721
a89a8fb9 2722 vmx->emulation_required = 1;
7ffd92c5 2723 vmx->rmode.vm86_active = 0;
6aa8b732 2724
2fb92db1
AK		 2725 vmx_segment_cache_clear(vmx);
2726
f5f7b2fe 2727 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2728
2729 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2730 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2731 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2732 vmcs_writel(GUEST_RFLAGS, flags);
2733
66aee91a
RR		 2734 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2735 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2736
2737 update_exception_bitmap(vcpu);
2738
a89a8fb9
MG		 2739 if (emulate_invalid_guest_state)
2740 return;
2741
f5f7b2fe
AK		 2742 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2743 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2744 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2745 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732 2746
2fb92db1
AK		 2747 vmx_segment_cache_clear(vmx);
2748
6aa8b732
AK		 2749 vmcs_write16(GUEST_SS_SELECTOR, 0);
2750 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2751
2752 vmcs_write16(GUEST_CS_SELECTOR,
2753 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2754 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2755}
2756
d77c26fc 2757static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2758{
bfc6d222 2759 if (!kvm->arch.tss_addr) {
bc6678a3 2760 struct kvm_memslots *slots;
28a37544 2761 struct kvm_memory_slot *slot;
bc6678a3
MT		 2762 gfn_t base_gfn;
2763
90d83dc3 2764 slots = kvm_memslots(kvm);
28a37544
XG		 2765 slot = id_to_memslot(slots, 0);
2766 base_gfn = slot->base_gfn + slot->npages - 3;
2767
cbc94022
IE		 2768 return base_gfn << PAGE_SHIFT;
2769 }
bfc6d222 2770 return kvm->arch.tss_addr;
6aa8b732
AK		 2771}
2772
f5f7b2fe 2773static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2774{
772e0318 2775 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
6aa8b732 2776
15b00f32 2777 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2778 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2779 vmcs_write32(sf->limit, 0xffff);
2780 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2781 if (save->base & 0xf)
2782 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2783 " aligned when entering protected mode (seg=%d)",
2784 seg);
6aa8b732
AK		 2785}
2786
2787static void enter_rmode(struct kvm_vcpu *vcpu)
2788{
2789 unsigned long flags;
a89a8fb9 2790 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2791 struct kvm_segment var;
6aa8b732 2792
3a624e29
NK		 2793 if (enable_unrestricted_guest)
2794 return;
2795
f5f7b2fe
AK		 2796 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2797 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2798 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2799 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2800 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2801
a89a8fb9 2802 vmx->emulation_required = 1;
7ffd92c5 2803 vmx->rmode.vm86_active = 1;
6aa8b732 2804
baa7e81e 2805
776e58ea
GN		 2806 /*
2807 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2808 * vcpu. Call it here with phys address pointing 16M below 4G.
2809 */
2810 if (!vcpu->kvm->arch.tss_addr) {
2811 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2812 "called before entering vcpu\n");
2813 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2814 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2815 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2816 }
2817
2fb92db1
AK		 2818 vmx_segment_cache_clear(vmx);
2819
6aa8b732 2820 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2821 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2822 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2823
2824 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2825 vmx->rmode.save_rflags = flags;
6aa8b732 2826
053de044 2827 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2828
2829 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2830 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2831 update_exception_bitmap(vcpu);
2832
a89a8fb9
MG		 2833 if (emulate_invalid_guest_state)
2834 goto continue_rmode;
2835
b246dd5d
OW		 2836 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2837 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2838
2839 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2840 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2841
2842 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2843 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2844
2845 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2846 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2847
b246dd5d
OW		 2848 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2849 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2850
b246dd5d
OW		 2851 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2852 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2853
a89a8fb9 2854continue_rmode:
8668a3c4 2855 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2856}
2857
401d10de
AS		 2858static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2859{
2860 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2861 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2862
2863 if (!msr)
2864 return;
401d10de 2865
44ea2b17
AK		 2866 /*
2867 * Force kernel_gs_base reloading before EFER changes, as control
2868 * of this msr depends on is_long_mode().
2869 */
2870 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2871 vcpu->arch.efer = efer;
401d10de
AS		 2872 if (efer & EFER_LMA) {
2873 vmcs_write32(VM_ENTRY_CONTROLS,
2874 vmcs_read32(VM_ENTRY_CONTROLS) |
2875 VM_ENTRY_IA32E_MODE);
2876 msr->data = efer;
2877 } else {
2878 vmcs_write32(VM_ENTRY_CONTROLS,
2879 vmcs_read32(VM_ENTRY_CONTROLS) &
2880 ~VM_ENTRY_IA32E_MODE);
2881
2882 msr->data = efer & ~EFER_LME;
2883 }
2884 setup_msrs(vmx);
2885}
2886
05b3e0c2 2887#ifdef CONFIG_X86_64
6aa8b732
AK		 2888
2889static void enter_lmode(struct kvm_vcpu *vcpu)
2890{
2891 u32 guest_tr_ar;
2892
2fb92db1
AK		 2893 vmx_segment_cache_clear(to_vmx(vcpu));
2894
6aa8b732
AK		 2895 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2896 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2897 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2898 __func__);
6aa8b732
AK		 2899 vmcs_write32(GUEST_TR_AR_BYTES,
2900 (guest_tr_ar & ~AR_TYPE_MASK)
2901 | AR_TYPE_BUSY_64_TSS);
2902 }
da38f438 2903 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2904}
2905
2906static void exit_lmode(struct kvm_vcpu *vcpu)
2907{
6aa8b732
AK		 2908 vmcs_write32(VM_ENTRY_CONTROLS,
2909 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2910 & ~VM_ENTRY_IA32E_MODE);
da38f438 2911 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2912}
2913
2914#endif
2915
2384d2b3
SY		 2916static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2917{
b9d762fa 2918 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2919 if (enable_ept) {
2920 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2921 return;
4e1096d2 2922 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2923 }
2384d2b3
SY		 2924}
2925
e8467fda
AK		 2926static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2927{
2928 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2929
2930 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2931 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2932}
2933
aff48baa
AK		 2934static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2935{
2936 if (enable_ept && is_paging(vcpu))
2937 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2938 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2939}
2940
25c4c276 2941static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2942{
fc78f519
AK		 2943 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2944
2945 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2946 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2947}
2948
1439442c
SY		 2949static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2950{
6de4f3ad
AK		 2951 if (!test_bit(VCPU_EXREG_PDPTR,
2952 (unsigned long *)&vcpu->arch.regs_dirty))
2953 return;
2954
1439442c 2955 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2956 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2957 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2958 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2959 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2960 }
2961}
2962
8f5d549f
AK		 2963static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2964{
2965 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2966 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2967 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2968 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2969 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2970 }
6de4f3ad
AK		 2971
2972 __set_bit(VCPU_EXREG_PDPTR,
2973 (unsigned long *)&vcpu->arch.regs_avail);
2974 __set_bit(VCPU_EXREG_PDPTR,
2975 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2976}
2977
5e1746d6 2978static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2979
2980static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2981 unsigned long cr0,
2982 struct kvm_vcpu *vcpu)
2983{
5233dd51
MT		 2984 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2985 vmx_decache_cr3(vcpu);
1439442c
SY		 2986 if (!(cr0 & X86_CR0_PG)) {
2987 /* From paging/starting to nonpaging */
2988 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2989 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2990 (CPU_BASED_CR3_LOAD_EXITING |
2991 CPU_BASED_CR3_STORE_EXITING));
2992 vcpu->arch.cr0 = cr0;
fc78f519 2993 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2994 } else if (!is_paging(vcpu)) {
2995 /* From nonpaging to paging */
2996 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2997 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2998 ~(CPU_BASED_CR3_LOAD_EXITING |
2999 CPU_BASED_CR3_STORE_EXITING));
3000 vcpu->arch.cr0 = cr0;
fc78f519 3001 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3002 }
95eb84a7
SY		 3003
3004 if (!(cr0 & X86_CR0_WP))
3005 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3006}
3007
6aa8b732
AK		 3008static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3009{
7ffd92c5 3010 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3011 unsigned long hw_cr0;
3012
3013 if (enable_unrestricted_guest)
3014 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3015 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3016 else
3017 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3018
7ffd92c5 3019 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3020 enter_pmode(vcpu);
3021
7ffd92c5 3022 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3023 enter_rmode(vcpu);
3024
05b3e0c2 3025#ifdef CONFIG_X86_64
f6801dff 3026 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3027 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3028 enter_lmode(vcpu);
707d92fa 3029 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3030 exit_lmode(vcpu);
3031 }
3032#endif
3033
089d034e 3034 if (enable_ept)
1439442c
SY		 3035 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3036
02daab21 3037 if (!vcpu->fpu_active)
81231c69 3038 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3039
6aa8b732 3040 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3041 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3042 vcpu->arch.cr0 = cr0;
69c73028 3043 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3044}
3045
1439442c
SY		 3046static u64 construct_eptp(unsigned long root_hpa)
3047{
3048 u64 eptp;
3049
3050 /* TODO write the value reading from MSR */
3051 eptp = VMX_EPT_DEFAULT_MT |
3052 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3053 if (enable_ept_ad_bits)
3054 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3055 eptp |= (root_hpa & PAGE_MASK);
3056
3057 return eptp;
3058}
3059
6aa8b732
AK		 3060static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3061{
1439442c
SY		 3062 unsigned long guest_cr3;
3063 u64 eptp;
3064
3065 guest_cr3 = cr3;
089d034e 3066 if (enable_ept) {
1439442c
SY		 3067 eptp = construct_eptp(cr3);
3068 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3069 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3070 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3071 ept_load_pdptrs(vcpu);
1439442c
SY		 3072 }
3073
2384d2b3 3074 vmx_flush_tlb(vcpu);
1439442c 3075 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3076}
3077
5e1746d6 3078static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3079{
7ffd92c5 3080 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3081 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3082
5e1746d6
NHE		 3083 if (cr4 & X86_CR4_VMXE) {
3084 /*
3085 * To use VMXON (and later other VMX instructions), a guest
3086 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3087 * So basically the check on whether to allow nested VMX
3088 * is here.
3089 */
3090 if (!nested_vmx_allowed(vcpu))
3091 return 1;
3092 } else if (to_vmx(vcpu)->nested.vmxon)
3093 return 1;
3094
ad312c7c 3095 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3096 if (enable_ept) {
3097 if (!is_paging(vcpu)) {
3098 hw_cr4 &= ~X86_CR4_PAE;
3099 hw_cr4 |= X86_CR4_PSE;
3100 } else if (!(cr4 & X86_CR4_PAE)) {
3101 hw_cr4 &= ~X86_CR4_PAE;
3102 }
3103 }
1439442c
SY		 3104
3105 vmcs_writel(CR4_READ_SHADOW, cr4);
3106 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3107 return 0;
6aa8b732
AK		 3108}
3109
6aa8b732
AK		 3110static void vmx_get_segment(struct kvm_vcpu *vcpu,
3111 struct kvm_segment *var, int seg)
3112{
a9179499 3113 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3114 u32 ar;
3115
a9179499
AK		 3116 if (vmx->rmode.vm86_active
3117 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3118 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
72636420 3119 || seg == VCPU_SREG_GS)) {
f5f7b2fe 3120 *var = vmx->rmode.segs[seg];
a9179499 3121 if (seg == VCPU_SREG_TR
2fb92db1 3122 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3123 return;
1390a28b
AK		 3124 var->base = vmx_read_guest_seg_base(vmx, seg);
3125 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3126 return;
a9179499 3127 }
2fb92db1
AK		 3128 var->base = vmx_read_guest_seg_base(vmx, seg);
3129 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3130 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3131 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3132 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3133 ar = 0;
3134 var->type = ar & 15;
3135 var->s = (ar >> 4) & 1;
3136 var->dpl = (ar >> 5) & 3;
3137 var->present = (ar >> 7) & 1;
3138 var->avl = (ar >> 12) & 1;
3139 var->l = (ar >> 13) & 1;
3140 var->db = (ar >> 14) & 1;
3141 var->g = (ar >> 15) & 1;
3142 var->unusable = (ar >> 16) & 1;
3143}
3144
a9179499
AK		 3145static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3146{
a9179499
AK		 3147 struct kvm_segment s;
3148
3149 if (to_vmx(vcpu)->rmode.vm86_active) {
3150 vmx_get_segment(vcpu, &s, seg);
3151 return s.base;
3152 }
2fb92db1 3153 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3154}
3155
69c73028 3156static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3157{
3eeb3288 3158 if (!is_protmode(vcpu))
2e4d2653
IE		 3159 return 0;
3160
f4c63e5d
AK		 3161 if (!is_long_mode(vcpu)
3162 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3163 return 3;
3164
2fb92db1 3165 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3166}
3167
69c73028
AK		 3168static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3169{
d881e6f6
AK		 3170 struct vcpu_vmx *vmx = to_vmx(vcpu);
3171
3172 /*
3173 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3174 * fail; use the cache instead.
3175 */
3176 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3177 return vmx->cpl;
3178 }
3179
69c73028
AK		 3180 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3181 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3182 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3183 }
d881e6f6
AK		 3184
3185 return vmx->cpl;
69c73028
AK		 3186}
3187
3188
653e3108 3189static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3190{
6aa8b732
AK		 3191 u32 ar;
3192
f0495f9b 3193 if (var->unusable || !var->present)
6aa8b732
AK		 3194 ar = 1 << 16;
3195 else {
3196 ar = var->type & 15;
3197 ar |= (var->s & 1) << 4;
3198 ar |= (var->dpl & 3) << 5;
3199 ar |= (var->present & 1) << 7;
3200 ar |= (var->avl & 1) << 12;
3201 ar |= (var->l & 1) << 13;
3202 ar |= (var->db & 1) << 14;
3203 ar |= (var->g & 1) << 15;
3204 }
653e3108
AK		 3205
3206 return ar;
3207}
3208
3209static void vmx_set_segment(struct kvm_vcpu *vcpu,
3210 struct kvm_segment *var, int seg)
3211{
7ffd92c5 3212 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3213 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108
AK		 3214 u32 ar;
3215
2fb92db1
AK		 3216 vmx_segment_cache_clear(vmx);
3217
7ffd92c5 3218 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3219 vmcs_write16(sf->selector, var->selector);
f5f7b2fe 3220 vmx->rmode.segs[VCPU_SREG_TR] = *var;
653e3108
AK		 3221 return;
3222 }
3223 vmcs_writel(sf->base, var->base);
3224 vmcs_write32(sf->limit, var->limit);
3225 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3226 if (vmx->rmode.vm86_active && var->s) {
ce566803 3227 vmx->rmode.segs[seg] = *var;
653e3108
AK		 3228 /*
3229 * Hack real-mode segments into vm86 compatibility.
3230 */
3231 if (var->base == 0xffff0000 && var->selector == 0xf000)
3232 vmcs_writel(sf->base, 0xf0000);
3233 ar = 0xf3;
3234 } else
3235 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3236
3237 /*
3238 * Fix the "Accessed" bit in AR field of segment registers for older
3239 * qemu binaries.
3240 * IA32 arch specifies that at the time of processor reset the
3241 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3242 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3243 * state vmexit when "unrestricted guest" mode is turned on.
3244 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3245 * tree. Newer qemu binaries with that qemu fix would not need this
3246 * kvm hack.
3247 */
3248 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3249 ar |= 0x1; /* Accessed */
3250
6aa8b732 3251 vmcs_write32(sf->ar_bytes, ar);
69c73028 3252 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3253
3254 /*
3255 * Fix segments for real mode guest in hosts that don't have
3256 * "unrestricted_mode" or it was disabled.
3257 * This is done to allow migration of the guests from hosts with
3258 * unrestricted guest like Westmere to older host that don't have
3259 * unrestricted guest like Nehelem.
3260 */
3261 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3262 switch (seg) {
3263 case VCPU_SREG_CS:
3264 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3265 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3266 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3267 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3268 vmcs_write16(GUEST_CS_SELECTOR,
3269 vmcs_readl(GUEST_CS_BASE) >> 4);
3270 break;
3271 case VCPU_SREG_ES:
b246dd5d 3272 case VCPU_SREG_DS:
b246dd5d 3273 case VCPU_SREG_GS:
b246dd5d 3274 case VCPU_SREG_FS:
f5f7b2fe 3275 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
b246dd5d
OW		 3276 break;
3277 case VCPU_SREG_SS:
3278 vmcs_write16(GUEST_SS_SELECTOR,
3279 vmcs_readl(GUEST_SS_BASE) >> 4);
3280 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3281 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3282 break;
3283 }
3284 }
6aa8b732
AK		 3285}
3286
6aa8b732
AK		 3287static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3288{
2fb92db1 3289 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3290
3291 *db = (ar >> 14) & 1;
3292 *l = (ar >> 13) & 1;
3293}
3294
89a27f4d 3295static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3296{
89a27f4d
GN		 3297 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3298 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3299}
3300
89a27f4d 3301static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3302{
89a27f4d
GN		 3303 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3304 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3305}
3306
89a27f4d 3307static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3308{
89a27f4d
GN		 3309 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3310 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3311}
3312
89a27f4d 3313static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3314{
89a27f4d
GN		 3315 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3316 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3317}
3318
648dfaa7
MG		 3319static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3320{
3321 struct kvm_segment var;
3322 u32 ar;
3323
3324 vmx_get_segment(vcpu, &var, seg);
3325 ar = vmx_segment_access_rights(&var);
3326
3327 if (var.base != (var.selector << 4))
3328 return false;
e2a610d7 3329 if (var.limit < 0xffff)
648dfaa7 3330 return false;
a81aba14 3331 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
648dfaa7
MG		 3332 return false;
3333
3334 return true;
3335}
3336
3337static bool code_segment_valid(struct kvm_vcpu *vcpu)
3338{
3339 struct kvm_segment cs;
3340 unsigned int cs_rpl;
3341
3342 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3343 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3344
1872a3f4
AK		 3345 if (cs.unusable)
3346 return false;
648dfaa7
MG		 3347 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3348 return false;
3349 if (!cs.s)
3350 return false;
1872a3f4 3351 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3352 if (cs.dpl > cs_rpl)
3353 return false;
1872a3f4 3354 } else {
648dfaa7
MG		 3355 if (cs.dpl != cs_rpl)
3356 return false;
3357 }
3358 if (!cs.present)
3359 return false;
3360
3361 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3362 return true;
3363}
3364
3365static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3366{
3367 struct kvm_segment ss;
3368 unsigned int ss_rpl;
3369
3370 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3371 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3372
1872a3f4
AK		 3373 if (ss.unusable)
3374 return true;
3375 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3376 return false;
3377 if (!ss.s)
3378 return false;
3379 if (ss.dpl != ss_rpl) /* DPL != RPL */
3380 return false;
3381 if (!ss.present)
3382 return false;
3383
3384 return true;
3385}
3386
3387static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3388{
3389 struct kvm_segment var;
3390 unsigned int rpl;
3391
3392 vmx_get_segment(vcpu, &var, seg);
3393 rpl = var.selector & SELECTOR_RPL_MASK;
3394
1872a3f4
AK		 3395 if (var.unusable)
3396 return true;
648dfaa7
MG		 3397 if (!var.s)
3398 return false;
3399 if (!var.present)
3400 return false;
3401 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3402 if (var.dpl < rpl) /* DPL < RPL */
3403 return false;
3404 }
3405
3406 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3407 * rights flags
3408 */
3409 return true;
3410}
3411
3412static bool tr_valid(struct kvm_vcpu *vcpu)
3413{
3414 struct kvm_segment tr;
3415
3416 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3417
1872a3f4
AK		 3418 if (tr.unusable)
3419 return false;
648dfaa7
MG		 3420 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3421 return false;
1872a3f4 3422 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3423 return false;
3424 if (!tr.present)
3425 return false;
3426
3427 return true;
3428}
3429
3430static bool ldtr_valid(struct kvm_vcpu *vcpu)
3431{
3432 struct kvm_segment ldtr;
3433
3434 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3435
1872a3f4
AK		 3436 if (ldtr.unusable)
3437 return true;
648dfaa7
MG		 3438 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3439 return false;
3440 if (ldtr.type != 2)
3441 return false;
3442 if (!ldtr.present)
3443 return false;
3444
3445 return true;
3446}
3447
3448static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3449{
3450 struct kvm_segment cs, ss;
3451
3452 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3453 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3454
3455 return ((cs.selector & SELECTOR_RPL_MASK) ==
3456 (ss.selector & SELECTOR_RPL_MASK));
3457}
3458
3459/*
3460 * Check if guest state is valid. Returns true if valid, false if
3461 * not.
3462 * We assume that registers are always usable
3463 */
3464static bool guest_state_valid(struct kvm_vcpu *vcpu)
3465{
3466 /* real mode guest state checks */
3eeb3288 3467 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3468 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3469 return false;
3470 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3471 return false;
3472 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3473 return false;
3474 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3475 return false;
3476 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3477 return false;
3478 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3479 return false;
3480 } else {
3481 /* protected mode guest state checks */
3482 if (!cs_ss_rpl_check(vcpu))
3483 return false;
3484 if (!code_segment_valid(vcpu))
3485 return false;
3486 if (!stack_segment_valid(vcpu))
3487 return false;
3488 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3489 return false;
3490 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3491 return false;
3492 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3493 return false;
3494 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3495 return false;
3496 if (!tr_valid(vcpu))
3497 return false;
3498 if (!ldtr_valid(vcpu))
3499 return false;
3500 }
3501 /* TODO:
3502 * - Add checks on RIP
3503 * - Add checks on RFLAGS
3504 */
3505
3506 return true;
3507}
3508
d77c26fc 3509static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3510{
40dcaa9f 3511 gfn_t fn;
195aefde 3512 u16 data = 0;
40dcaa9f 3513 int r, idx, ret = 0;
6aa8b732 3514
40dcaa9f
XG		 3515 idx = srcu_read_lock(&kvm->srcu);
3516 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3517 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3518 if (r < 0)
10589a46 3519 goto out;
195aefde 3520 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3521 r = kvm_write_guest_page(kvm, fn++, &data,
3522 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3523 if (r < 0)
10589a46 3524 goto out;
195aefde
IE		 3525 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3526 if (r < 0)
10589a46 3527 goto out;
195aefde
IE		 3528 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3529 if (r < 0)
10589a46 3530 goto out;
195aefde 3531 data = ~0;
10589a46
MT		 3532 r = kvm_write_guest_page(kvm, fn, &data,
3533 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3534 sizeof(u8));
195aefde 3535 if (r < 0)
10589a46
MT		 3536 goto out;
3537
3538 ret = 1;
3539out:
40dcaa9f 3540 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3541 return ret;
6aa8b732
AK		 3542}
3543
b7ebfb05
SY		 3544static int init_rmode_identity_map(struct kvm *kvm)
3545{
40dcaa9f 3546 int i, idx, r, ret;
b7ebfb05
SY		 3547 pfn_t identity_map_pfn;
3548 u32 tmp;
3549
089d034e 3550 if (!enable_ept)
b7ebfb05
SY		 3551 return 1;
3552 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3553 printk(KERN_ERR "EPT: identity-mapping pagetable "
3554 "haven't been allocated!\n");
3555 return 0;
3556 }
3557 if (likely(kvm->arch.ept_identity_pagetable_done))
3558 return 1;
3559 ret = 0;
b927a3ce 3560 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3561 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3562 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3563 if (r < 0)
3564 goto out;
3565 /* Set up identity-mapping pagetable for EPT in real mode */
3566 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3567 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3568 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3569 r = kvm_write_guest_page(kvm, identity_map_pfn,
3570 &tmp, i * sizeof(tmp), sizeof(tmp));
3571 if (r < 0)
3572 goto out;
3573 }
3574 kvm->arch.ept_identity_pagetable_done = true;
3575 ret = 1;
3576out:
40dcaa9f 3577 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3578 return ret;
3579}
3580
6aa8b732
AK		 3581static void seg_setup(int seg)
3582{
772e0318 3583 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3584 unsigned int ar;
6aa8b732
AK		 3585
3586 vmcs_write16(sf->selector, 0);
3587 vmcs_writel(sf->base, 0);
3588 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3589 if (enable_unrestricted_guest) {
3590 ar = 0x93;
3591 if (seg == VCPU_SREG_CS)
3592 ar |= 0x08; /* code segment */
3593 } else
3594 ar = 0xf3;
3595
3596 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3597}
3598
f78e0e2e
SY		 3599static int alloc_apic_access_page(struct kvm *kvm)
3600{
4484141a 3601 struct page *page;
f78e0e2e
SY		 3602 struct kvm_userspace_memory_region kvm_userspace_mem;
3603 int r = 0;
3604
79fac95e 3605 mutex_lock(&kvm->slots_lock);
bfc6d222 3606 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3607 goto out;
3608 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3609 kvm_userspace_mem.flags = 0;
3610 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3611 kvm_userspace_mem.memory_size = PAGE_SIZE;
3612 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3613 if (r)
3614 goto out;
72dc67a6 3615
4484141a
XG		 3616 page = gfn_to_page(kvm, 0xfee00);
3617 if (is_error_page(page)) {
3618 r = -EFAULT;
3619 goto out;
3620 }
3621
3622 kvm->arch.apic_access_page = page;
f78e0e2e 3623out:
79fac95e 3624 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3625 return r;
3626}
3627
b7ebfb05
SY		 3628static int alloc_identity_pagetable(struct kvm *kvm)
3629{
4484141a 3630 struct page *page;
b7ebfb05
SY		 3631 struct kvm_userspace_memory_region kvm_userspace_mem;
3632 int r = 0;
3633
79fac95e 3634 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3635 if (kvm->arch.ept_identity_pagetable)
3636 goto out;
3637 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3638 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3639 kvm_userspace_mem.guest_phys_addr =
3640 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3641 kvm_userspace_mem.memory_size = PAGE_SIZE;
3642 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3643 if (r)
3644 goto out;
3645
4484141a
XG		 3646 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3647 if (is_error_page(page)) {
3648 r = -EFAULT;
3649 goto out;
3650 }
3651
3652 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3653out:
79fac95e 3654 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3655 return r;
3656}
3657
2384d2b3
SY		 3658static void allocate_vpid(struct vcpu_vmx *vmx)
3659{
3660 int vpid;
3661
3662 vmx->vpid = 0;
919818ab 3663 if (!enable_vpid)
2384d2b3
SY		 3664 return;
3665 spin_lock(&vmx_vpid_lock);
3666 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3667 if (vpid < VMX_NR_VPIDS) {
3668 vmx->vpid = vpid;
3669 __set_bit(vpid, vmx_vpid_bitmap);
3670 }
3671 spin_unlock(&vmx_vpid_lock);
3672}
3673
cdbecfc3
LJ		 3674static void free_vpid(struct vcpu_vmx *vmx)
3675{
3676 if (!enable_vpid)
3677 return;
3678 spin_lock(&vmx_vpid_lock);
3679 if (vmx->vpid != 0)
3680 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3681 spin_unlock(&vmx_vpid_lock);
3682}
3683
5897297b 3684static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3685{
3e7c73e9 3686 int f = sizeof(unsigned long);
25c5f225
SY		 3687
3688 if (!cpu_has_vmx_msr_bitmap())
3689 return;
3690
3691 /*
3692 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3693 * have the write-low and read-high bitmap offsets the wrong way round.
3694 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3695 */
25c5f225 3696 if (msr <= 0x1fff) {
3e7c73e9
AK		 3697 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3698 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3699 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3700 msr &= 0x1fff;
3e7c73e9
AK		 3701 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3702 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3703 }
25c5f225
SY		 3704}
3705
5897297b
AK		 3706static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3707{
3708 if (!longmode_only)
3709 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3710 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3711}
3712
a3a8ff8e
NHE		 3713/*
3714 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3715 * will not change in the lifetime of the guest.
3716 * Note that host-state that does change is set elsewhere. E.g., host-state
3717 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3718 */
3719static void vmx_set_constant_host_state(void)
3720{
3721 u32 low32, high32;
3722 unsigned long tmpl;
3723 struct desc_ptr dt;
3724
b1a74bf8 3725 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3726 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3727 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3728
3729 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3730#ifdef CONFIG_X86_64
3731 /*
3732 * Load null selectors, so we can avoid reloading them in
3733 * __vmx_load_host_state(), in case userspace uses the null selectors
3734 * too (the expected case).
3735 */
3736 vmcs_write16(HOST_DS_SELECTOR, 0);
3737 vmcs_write16(HOST_ES_SELECTOR, 0);
3738#else
a3a8ff8e
NHE		 3739 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3740 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3741#endif
a3a8ff8e
NHE		 3742 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3743 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3744
3745 native_store_idt(&dt);
3746 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3747
83287ea4 3748 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3749
3750 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3751 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3752 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3753 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3754
3755 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3756 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3757 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3758 }
3759}
3760
bf8179a0
NHE		 3761static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3762{
3763 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3764 if (enable_ept)
3765 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3766 if (is_guest_mode(&vmx->vcpu))
3767 vmx->vcpu.arch.cr4_guest_owned_bits &=
3768 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3769 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3770}
3771
3772static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3773{
3774 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3775 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3776 exec_control &= ~CPU_BASED_TPR_SHADOW;
3777#ifdef CONFIG_X86_64
3778 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3779 CPU_BASED_CR8_LOAD_EXITING;
3780#endif
3781 }
3782 if (!enable_ept)
3783 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3784 CPU_BASED_CR3_LOAD_EXITING |
3785 CPU_BASED_INVLPG_EXITING;
3786 return exec_control;
3787}
3788
3789static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3790{
3791 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3792 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3793 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3794 if (vmx->vpid == 0)
3795 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3796 if (!enable_ept) {
3797 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3798 enable_unrestricted_guest = 0;
ad756a16
MJ		 3799 /* Enable INVPCID for non-ept guests may cause performance regression. */
3800 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3801 }
3802 if (!enable_unrestricted_guest)
3803 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3804 if (!ple_gap)
3805 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3806 return exec_control;
3807}
3808
ce88decf
XG		 3809static void ept_set_mmio_spte_mask(void)
3810{
3811 /*
3812 * EPT Misconfigurations can be generated if the value of bits 2:0
3813 * of an EPT paging-structure entry is 110b (write/execute).
3814 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3815 * spte.
3816 */
3817 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3818}
3819
6aa8b732
AK		 3820/*
3821 * Sets up the vmcs for emulated real mode.
3822 */
8b9cf98c 3823static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3824{
2e4ce7f5 3825#ifdef CONFIG_X86_64
6aa8b732 3826 unsigned long a;
2e4ce7f5 3827#endif
6aa8b732 3828 int i;
6aa8b732 3829
6aa8b732 3830 /* I/O */
3e7c73e9
AK		 3831 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3832 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3833
25c5f225 3834 if (cpu_has_vmx_msr_bitmap())
5897297b 3835 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3836
6aa8b732
AK		 3837 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3838
6aa8b732 3839 /* Control */
1c3d14fe
YS		 3840 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3841 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3842
bf8179a0 3843 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3844
83ff3b9d 3845 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3846 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3847 vmx_secondary_exec_control(vmx));
83ff3b9d 3848 }
f78e0e2e 3849
4b8d54f9
ZE		 3850 if (ple_gap) {
3851 vmcs_write32(PLE_GAP, ple_gap);
3852 vmcs_write32(PLE_WINDOW, ple_window);
3853 }
3854
c3707958
XG		 3855 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3856 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3857 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3858
9581d442
AK		 3859 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3860 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3861 vmx_set_constant_host_state();
05b3e0c2 3862#ifdef CONFIG_X86_64
6aa8b732
AK		 3863 rdmsrl(MSR_FS_BASE, a);
3864 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3865 rdmsrl(MSR_GS_BASE, a);
3866 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3867#else
3868 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3869 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3870#endif
3871
2cc51560
ED		 3872 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3873 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3874 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3875 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3876 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3877
468d472f 3878 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3879 u32 msr_low, msr_high;
3880 u64 host_pat;
468d472f
SY		 3881 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3882 host_pat = msr_low | ((u64) msr_high << 32);
3883 /* Write the default value follow host pat */
3884 vmcs_write64(GUEST_IA32_PAT, host_pat);
3885 /* Keep arch.pat sync with GUEST_IA32_PAT */
3886 vmx->vcpu.arch.pat = host_pat;
3887 }
3888
6aa8b732
AK		 3889 for (i = 0; i < NR_VMX_MSR; ++i) {
3890 u32 index = vmx_msr_index[i];
3891 u32 data_low, data_high;
a2fa3e9f 3892 int j = vmx->nmsrs;
6aa8b732
AK		 3893
3894 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3895 continue;
432bd6cb
AK		 3896 if (wrmsr_safe(index, data_low, data_high) < 0)
3897 continue;
26bb0981
AK		 3898 vmx->guest_msrs[j].index = i;
3899 vmx->guest_msrs[j].data = 0;
d5696725 3900 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3901 ++vmx->nmsrs;
6aa8b732 3902 }
6aa8b732 3903
1c3d14fe 3904 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3905
3906 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3907 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3908
e00c8cf2 3909 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3910 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3911
3912 return 0;
3913}
3914
3915static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3916{
3917 struct vcpu_vmx *vmx = to_vmx(vcpu);
3918 u64 msr;
4b9d3a04 3919 int ret;
e00c8cf2 3920
7ffd92c5 3921 vmx->rmode.vm86_active = 0;
e00c8cf2 3922
3b86cd99
JK		 3923 vmx->soft_vnmi_blocked = 0;
3924
ad312c7c 3925 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3926 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3927 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3928 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3929 msr |= MSR_IA32_APICBASE_BSP;
3930 kvm_set_apic_base(&vmx->vcpu, msr);
3931
2fb92db1
AK		 3932 vmx_segment_cache_clear(vmx);
3933
5706be0d 3934 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3935 /*
3936 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3937 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3938 */
c5af89b6 3939 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3940 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3941 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3942 } else {
ad312c7c
ZX		 3943 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3944 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3945 }
e00c8cf2
AK		 3946
3947 seg_setup(VCPU_SREG_DS);
3948 seg_setup(VCPU_SREG_ES);
3949 seg_setup(VCPU_SREG_FS);
3950 seg_setup(VCPU_SREG_GS);
3951 seg_setup(VCPU_SREG_SS);
3952
3953 vmcs_write16(GUEST_TR_SELECTOR, 0);
3954 vmcs_writel(GUEST_TR_BASE, 0);
3955 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3956 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3957
3958 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3959 vmcs_writel(GUEST_LDTR_BASE, 0);
3960 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3961 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3962
3963 vmcs_write32(GUEST_SYSENTER_CS, 0);
3964 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3965 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3966
3967 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3968 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3969 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3970 else
5fdbf976 3971 kvm_rip_write(vcpu, 0);
e00c8cf2 3972
e00c8cf2
AK		 3973 vmcs_writel(GUEST_GDTR_BASE, 0);
3974 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3975
3976 vmcs_writel(GUEST_IDTR_BASE, 0);
3977 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3978
443381a8 3979 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3980 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3981 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3982
e00c8cf2
AK		 3983 /* Special registers */
3984 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3985
3986 setup_msrs(vmx);
3987
6aa8b732
AK		 3988 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3989
f78e0e2e
SY		 3990 if (cpu_has_vmx_tpr_shadow()) {
3991 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3992 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3993 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3994 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3995 vmcs_write32(TPR_THRESHOLD, 0);
3996 }
3997
3998 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3999 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4000 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4001
2384d2b3
SY		 4002 if (vmx->vpid != 0)
4003 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4004
fa40052c 4005 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4006 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4007 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4008 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4009 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4010 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4011 vmx_fpu_activate(&vmx->vcpu);
4012 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4013
b9d762fa 4014 vpid_sync_context(vmx);
2384d2b3 4015
3200f405 4016 ret = 0;
6aa8b732 4017
a89a8fb9
MG		 4018 /* HACK: Don't enable emulation on guest boot/reset */
4019 vmx->emulation_required = 0;
4020
6aa8b732
AK		 4021 return ret;
4022}
4023
b6f1250e
NHE		 4024/*
4025 * In nested virtualization, check if L1 asked to exit on external interrupts.
4026 * For most existing hypervisors, this will always return true.
4027 */
4028static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4029{
4030 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4031 PIN_BASED_EXT_INTR_MASK;
4032}
4033
3b86cd99
JK		 4034static void enable_irq_window(struct kvm_vcpu *vcpu)
4035{
4036 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4037 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4038 /*
4039 * We get here if vmx_interrupt_allowed() said we can't
4040 * inject to L1 now because L2 must run. Ask L2 to exit
4041 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4042 */
d6185f20 4043 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4044 return;
d6185f20 4045 }
3b86cd99
JK		 4046
4047 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4048 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4049 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4050}
4051
4052static void enable_nmi_window(struct kvm_vcpu *vcpu)
4053{
4054 u32 cpu_based_vm_exec_control;
4055
4056 if (!cpu_has_virtual_nmis()) {
4057 enable_irq_window(vcpu);
4058 return;
4059 }
4060
30bd0c4c
AK		 4061 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4062 enable_irq_window(vcpu);
4063 return;
4064 }
3b86cd99
JK		 4065 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4066 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4067 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4068}
4069
66fd3f7f 4070static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4071{
9c8cba37 4072 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4073 uint32_t intr;
4074 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4075
229456fc 4076 trace_kvm_inj_virq(irq);
2714d1d3 4077
fa89a817 4078 ++vcpu->stat.irq_injections;
7ffd92c5 4079 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4080 int inc_eip = 0;
4081 if (vcpu->arch.interrupt.soft)
4082 inc_eip = vcpu->arch.event_exit_inst_len;
4083 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4084 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4085 return;
4086 }
66fd3f7f
GN		 4087 intr = irq | INTR_INFO_VALID_MASK;
4088 if (vcpu->arch.interrupt.soft) {
4089 intr |= INTR_TYPE_SOFT_INTR;
4090 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4091 vmx->vcpu.arch.event_exit_inst_len);
4092 } else
4093 intr |= INTR_TYPE_EXT_INTR;
4094 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4095}
4096
f08864b4
SY		 4097static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4098{
66a5a347
JK		 4099 struct vcpu_vmx *vmx = to_vmx(vcpu);
4100
0b6ac343
NHE		 4101 if (is_guest_mode(vcpu))
4102 return;
4103
3b86cd99
JK		 4104 if (!cpu_has_virtual_nmis()) {
4105 /*
4106 * Tracking the NMI-blocked state in software is built upon
4107 * finding the next open IRQ window. This, in turn, depends on
4108 * well-behaving guests: They have to keep IRQs disabled at
4109 * least as long as the NMI handler runs. Otherwise we may
4110 * cause NMI nesting, maybe breaking the guest. But as this is
4111 * highly unlikely, we can live with the residual risk.
4112 */
4113 vmx->soft_vnmi_blocked = 1;
4114 vmx->vnmi_blocked_time = 0;
4115 }
4116
487b391d 4117 ++vcpu->stat.nmi_injections;
9d58b931 4118 vmx->nmi_known_unmasked = false;
7ffd92c5 4119 if (vmx->rmode.vm86_active) {
71f9833b 4120 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4121 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4122 return;
4123 }
f08864b4
SY		 4124 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4125 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4126}
4127
c4282df9 4128static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4129{
3b86cd99 4130 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4131 return 0;
33f089ca 4132
c4282df9 4133 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4134 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4135 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4136}
4137
3cfc3092
JK		 4138static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4139{
4140 if (!cpu_has_virtual_nmis())
4141 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4142 if (to_vmx(vcpu)->nmi_known_unmasked)
4143 return false;
c332c83a 4144 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4145}
4146
4147static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4148{
4149 struct vcpu_vmx *vmx = to_vmx(vcpu);
4150
4151 if (!cpu_has_virtual_nmis()) {
4152 if (vmx->soft_vnmi_blocked != masked) {
4153 vmx->soft_vnmi_blocked = masked;
4154 vmx->vnmi_blocked_time = 0;
4155 }
4156 } else {
9d58b931 4157 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4158 if (masked)
4159 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4160 GUEST_INTR_STATE_NMI);
4161 else
4162 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4163 GUEST_INTR_STATE_NMI);
4164 }
4165}
4166
78646121
GN		 4167static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4168{
b6f1250e 4169 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4170 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4171 if (to_vmx(vcpu)->nested.nested_run_pending ||
4172 (vmcs12->idt_vectoring_info_field &
4173 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4174 return 0;
4175 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4176 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4177 vmcs12->vm_exit_intr_info = 0;
4178 /* fall through to normal code, but now in L1, not L2 */
4179 }
4180
c4282df9
GN		 4181 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4182 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4183 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4184}
4185
cbc94022
IE		 4186static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4187{
4188 int ret;
4189 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4190 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4191 .guest_phys_addr = addr,
4192 .memory_size = PAGE_SIZE * 3,
4193 .flags = 0,
4194 };
4195
4196 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4197 if (ret)
4198 return ret;
bfc6d222 4199 kvm->arch.tss_addr = addr;
93ea5388
GN		 4200 if (!init_rmode_tss(kvm))
4201 return -ENOMEM;
4202
cbc94022
IE		 4203 return 0;
4204}
4205
6aa8b732
AK		 4206static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4207 int vec, u32 err_code)
4208{
b3f37707
NK		 4209 /*
4210 * Instruction with address size override prefix opcode 0x67
4211 * Cause the #SS fault with 0 error code in VM86 mode.
4212 */
4213 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4214 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4215 return 1;
77ab6db0
JK		 4216 /*
4217 * Forward all other exceptions that are valid in real mode.
4218 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4219 * the required debugging infrastructure rework.
4220 */
4221 switch (vec) {
77ab6db0 4222 case DB_VECTOR:
d0bfb940
JK		 4223 if (vcpu->guest_debug &
4224 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4225 return 0;
4226 kvm_queue_exception(vcpu, vec);
4227 return 1;
77ab6db0 4228 case BP_VECTOR:
c573cd22
JK		 4229 /*
4230 * Update instruction length as we may reinject the exception
4231 * from user space while in guest debugging mode.
4232 */
4233 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4234 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4235 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4236 return 0;
4237 /* fall through */
4238 case DE_VECTOR:
77ab6db0
JK		 4239 case OF_VECTOR:
4240 case BR_VECTOR:
4241 case UD_VECTOR:
4242 case DF_VECTOR:
4243 case SS_VECTOR:
4244 case GP_VECTOR:
4245 case MF_VECTOR:
4246 kvm_queue_exception(vcpu, vec);
4247 return 1;
4248 }
6aa8b732
AK		 4249 return 0;
4250}
4251
a0861c02
AK		 4252/*
4253 * Trigger machine check on the host. We assume all the MSRs are already set up
4254 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4255 * We pass a fake environment to the machine check handler because we want
4256 * the guest to be always treated like user space, no matter what context
4257 * it used internally.
4258 */
4259static void kvm_machine_check(void)
4260{
4261#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4262 struct pt_regs regs = {
4263 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4264 .flags = X86_EFLAGS_IF,
4265 };
4266
4267 do_machine_check(&regs, 0);
4268#endif
4269}
4270
851ba692 4271static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4272{
4273 /* already handled by vcpu_run */
4274 return 1;
4275}
4276
851ba692 4277static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4278{
1155f76a 4279 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4280 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4281 u32 intr_info, ex_no, error_code;
42dbaa5a 4282 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4283 u32 vect_info;
4284 enum emulation_result er;
4285
1155f76a 4286 vect_info = vmx->idt_vectoring_info;
88786475 4287 intr_info = vmx->exit_intr_info;
6aa8b732 4288
a0861c02 4289 if (is_machine_check(intr_info))
851ba692 4290 return handle_machine_check(vcpu);
a0861c02 4291
e4a41889 4292 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4293 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4294
4295 if (is_no_device(intr_info)) {
5fd86fcf 4296 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4297 return 1;
4298 }
4299
7aa81cc0 4300 if (is_invalid_opcode(intr_info)) {
51d8b661 4301 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4302 if (er != EMULATE_DONE)
7ee5d940 4303 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4304 return 1;
4305 }
4306
6aa8b732 4307 error_code = 0;
2e11384c 4308 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4309 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4310
4311 /*
4312 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4313 * MMIO, it is better to report an internal error.
4314 * See the comments in vmx_handle_exit.
4315 */
4316 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4317 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4318 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4319 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4320 vcpu->run->internal.ndata = 2;
4321 vcpu->run->internal.data[0] = vect_info;
4322 vcpu->run->internal.data[1] = intr_info;
4323 return 0;
4324 }
4325
6aa8b732 4326 if (is_page_fault(intr_info)) {
1439442c 4327 /* EPT won't cause page fault directly */
cf3ace79 4328 BUG_ON(enable_ept);
6aa8b732 4329 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4330 trace_kvm_page_fault(cr2, error_code);
4331
3298b75c 4332 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4333 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4334 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4335 }
4336
7ffd92c5 4337 if (vmx->rmode.vm86_active &&
6aa8b732 4338 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4339 error_code)) {
ad312c7c
ZX		 4340 if (vcpu->arch.halt_request) {
4341 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4342 return kvm_emulate_halt(vcpu);
4343 }
6aa8b732 4344 return 1;
72d6e5a0 4345 }
6aa8b732 4346
d0bfb940 4347 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4348 switch (ex_no) {
4349 case DB_VECTOR:
4350 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4351 if (!(vcpu->guest_debug &
4352 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4353 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4354 kvm_queue_exception(vcpu, DB_VECTOR);
4355 return 1;
4356 }
4357 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4358 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4359 /* fall through */
4360 case BP_VECTOR:
c573cd22
JK		 4361 /*
4362 * Update instruction length as we may reinject #BP from
4363 * user space while in guest debugging mode. Reading it for
4364 * #DB as well causes no harm, it is not used in that case.
4365 */
4366 vmx->vcpu.arch.event_exit_inst_len =
4367 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4368 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4369 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4370 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4371 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4372 break;
4373 default:
d0bfb940
JK		 4374 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4375 kvm_run->ex.exception = ex_no;
4376 kvm_run->ex.error_code = error_code;
42dbaa5a 4377 break;
6aa8b732 4378 }
6aa8b732
AK		 4379 return 0;
4380}
4381
851ba692 4382static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4383{
1165f5fe 4384 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4385 return 1;
4386}
4387
851ba692 4388static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4389{
851ba692 4390 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4391 return 0;
4392}
6aa8b732 4393
851ba692 4394static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4395{
bfdaab09 4396 unsigned long exit_qualification;
34c33d16 4397 int size, in, string;
039576c0 4398 unsigned port;
6aa8b732 4399
bfdaab09 4400 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4401 string = (exit_qualification & 16) != 0;
cf8f70bf 4402 in = (exit_qualification & 8) != 0;
e70669ab 4403
cf8f70bf 4404 ++vcpu->stat.io_exits;
e70669ab 4405
cf8f70bf 4406 if (string || in)
51d8b661 4407 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4408
cf8f70bf
GN		 4409 port = exit_qualification >> 16;
4410 size = (exit_qualification & 7) + 1;
e93f36bc 4411 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4412
4413 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4414}
4415
102d8325
IM		 4416static void
4417vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4418{
4419 /*
4420 * Patch in the VMCALL instruction:
4421 */
4422 hypercall[0] = 0x0f;
4423 hypercall[1] = 0x01;
4424 hypercall[2] = 0xc1;
102d8325
IM		 4425}
4426
0fa06071 4427/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4428static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4429{
4430 if (to_vmx(vcpu)->nested.vmxon &&
4431 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4432 return 1;
4433
4434 if (is_guest_mode(vcpu)) {
4435 /*
4436 * We get here when L2 changed cr0 in a way that did not change
4437 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4438 * but did change L0 shadowed bits. This can currently happen
4439 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4440 * loading) while pretending to allow the guest to change it.
4441 */
4442 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4443 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4444 return 1;
4445 vmcs_writel(CR0_READ_SHADOW, val);
4446 return 0;
4447 } else
4448 return kvm_set_cr0(vcpu, val);
4449}
4450
4451static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4452{
4453 if (is_guest_mode(vcpu)) {
4454 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4455 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4456 return 1;
4457 vmcs_writel(CR4_READ_SHADOW, val);
4458 return 0;
4459 } else
4460 return kvm_set_cr4(vcpu, val);
4461}
4462
4463/* called to set cr0 as approriate for clts instruction exit. */
4464static void handle_clts(struct kvm_vcpu *vcpu)
4465{
4466 if (is_guest_mode(vcpu)) {
4467 /*
4468 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4469 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4470 * just pretend it's off (also in arch.cr0 for fpu_activate).
4471 */
4472 vmcs_writel(CR0_READ_SHADOW,
4473 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4474 vcpu->arch.cr0 &= ~X86_CR0_TS;
4475 } else
4476 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4477}
4478
851ba692 4479static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4480{
229456fc 4481 unsigned long exit_qualification, val;
6aa8b732
AK		 4482 int cr;
4483 int reg;
49a9b07e 4484 int err;
6aa8b732 4485
bfdaab09 4486 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4487 cr = exit_qualification & 15;
4488 reg = (exit_qualification >> 8) & 15;
4489 switch ((exit_qualification >> 4) & 3) {
4490 case 0: /* mov to cr */
229456fc
MT		 4491 val = kvm_register_read(vcpu, reg);
4492 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4493 switch (cr) {
4494 case 0:
eeadf9e7 4495 err = handle_set_cr0(vcpu, val);
db8fcefa 4496 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4497 return 1;
4498 case 3:
2390218b 4499 err = kvm_set_cr3(vcpu, val);
db8fcefa 4500 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4501 return 1;
4502 case 4:
eeadf9e7 4503 err = handle_set_cr4(vcpu, val);
db8fcefa 4504 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4505 return 1;
0a5fff19
GN		 4506 case 8: {
4507 u8 cr8_prev = kvm_get_cr8(vcpu);
4508 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4509 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4510 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4511 if (irqchip_in_kernel(vcpu->kvm))
4512 return 1;
4513 if (cr8_prev <= cr8)
4514 return 1;
851ba692 4515 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4516 return 0;
4517 }
4b8073e4 4518 }
6aa8b732 4519 break;
25c4c276 4520 case 2: /* clts */
eeadf9e7 4521 handle_clts(vcpu);
4d4ec087 4522 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4523 skip_emulated_instruction(vcpu);
6b52d186 4524 vmx_fpu_activate(vcpu);
25c4c276 4525 return 1;
6aa8b732
AK		 4526 case 1: /*mov from cr*/
4527 switch (cr) {
4528 case 3:
9f8fe504
AK		 4529 val = kvm_read_cr3(vcpu);
4530 kvm_register_write(vcpu, reg, val);
4531 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4532 skip_emulated_instruction(vcpu);
4533 return 1;
4534 case 8:
229456fc
MT		 4535 val = kvm_get_cr8(vcpu);
4536 kvm_register_write(vcpu, reg, val);
4537 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4538 skip_emulated_instruction(vcpu);
4539 return 1;
4540 }
4541 break;
4542 case 3: /* lmsw */
a1f83a74 4543 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4544 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4545 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4546
4547 skip_emulated_instruction(vcpu);
4548 return 1;
4549 default:
4550 break;
4551 }
851ba692 4552 vcpu->run->exit_reason = 0;
a737f256 4553 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4554 (int)(exit_qualification >> 4) & 3, cr);
4555 return 0;
4556}
4557
851ba692 4558static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4559{
bfdaab09 4560 unsigned long exit_qualification;
6aa8b732
AK		 4561 int dr, reg;
4562
f2483415 4563 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4564 if (!kvm_require_cpl(vcpu, 0))
4565 return 1;
42dbaa5a
JK		 4566 dr = vmcs_readl(GUEST_DR7);
4567 if (dr & DR7_GD) {
4568 /*
4569 * As the vm-exit takes precedence over the debug trap, we
4570 * need to emulate the latter, either for the host or the
4571 * guest debugging itself.
4572 */
4573 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4574 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4575 vcpu->run->debug.arch.dr7 = dr;
4576 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4577 vmcs_readl(GUEST_CS_BASE) +
4578 vmcs_readl(GUEST_RIP);
851ba692
AK		 4579 vcpu->run->debug.arch.exception = DB_VECTOR;
4580 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4581 return 0;
4582 } else {
4583 vcpu->arch.dr7 &= ~DR7_GD;
4584 vcpu->arch.dr6 |= DR6_BD;
4585 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4586 kvm_queue_exception(vcpu, DB_VECTOR);
4587 return 1;
4588 }
4589 }
4590
bfdaab09 4591 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4592 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4593 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4594 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4595 unsigned long val;
4596 if (!kvm_get_dr(vcpu, dr, &val))
4597 kvm_register_write(vcpu, reg, val);
4598 } else
4599 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4600 skip_emulated_instruction(vcpu);
4601 return 1;
4602}
4603
020df079
GN		 4604static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4605{
4606 vmcs_writel(GUEST_DR7, val);
4607}
4608
851ba692 4609static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4610{
06465c5a
AK		 4611 kvm_emulate_cpuid(vcpu);
4612 return 1;
6aa8b732
AK		 4613}
4614
851ba692 4615static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4616{
ad312c7c 4617 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4618 u64 data;
4619
4620 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4621 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4622 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4623 return 1;
4624 }
4625
229456fc 4626 trace_kvm_msr_read(ecx, data);
2714d1d3 4627
6aa8b732 4628 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4629 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4630 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4631 skip_emulated_instruction(vcpu);
4632 return 1;
4633}
4634
851ba692 4635static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4636{
8fe8ab46 4637 struct msr_data msr;
ad312c7c
ZX		 4638 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4639 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4640 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4641
8fe8ab46
WA		 4642 msr.data = data;
4643 msr.index = ecx;
4644 msr.host_initiated = false;
4645 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4646 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4647 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4648 return 1;
4649 }
4650
59200273 4651 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4652 skip_emulated_instruction(vcpu);
4653 return 1;
4654}
4655
851ba692 4656static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4657{
3842d135 4658 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4659 return 1;
4660}
4661
851ba692 4662static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4663{
85f455f7
ED		 4664 u32 cpu_based_vm_exec_control;
4665
4666 /* clear pending irq */
4667 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4668 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4669 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4670
3842d135
AK		 4671 kvm_make_request(KVM_REQ_EVENT, vcpu);
4672
a26bf12a 4673 ++vcpu->stat.irq_window_exits;
2714d1d3 4674
c1150d8c
DL		 4675 /*
4676 * If the user space waits to inject interrupts, exit as soon as
4677 * possible
4678 */
8061823a 4679 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4680 vcpu->run->request_interrupt_window &&
8061823a 4681 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4682 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4683 return 0;
4684 }
6aa8b732
AK		 4685 return 1;
4686}
4687
851ba692 4688static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4689{
4690 skip_emulated_instruction(vcpu);
d3bef15f 4691 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4692}
4693
851ba692 4694static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4695{
510043da 4696 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4697 kvm_emulate_hypercall(vcpu);
4698 return 1;
c21415e8
IM		 4699}
4700
ec25d5e6
GN		 4701static int handle_invd(struct kvm_vcpu *vcpu)
4702{
51d8b661 4703 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4704}
4705
851ba692 4706static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4707{
f9c617f6 4708 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4709
4710 kvm_mmu_invlpg(vcpu, exit_qualification);
4711 skip_emulated_instruction(vcpu);
4712 return 1;
4713}
4714
fee84b07
AK		 4715static int handle_rdpmc(struct kvm_vcpu *vcpu)
4716{
4717 int err;
4718
4719 err = kvm_rdpmc(vcpu);
4720 kvm_complete_insn_gp(vcpu, err);
4721
4722 return 1;
4723}
4724
851ba692 4725static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4726{
4727 skip_emulated_instruction(vcpu);
f5f48ee1 4728 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4729 return 1;
4730}
4731
2acf923e
DC		 4732static int handle_xsetbv(struct kvm_vcpu *vcpu)
4733{
4734 u64 new_bv = kvm_read_edx_eax(vcpu);
4735 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4736
4737 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4738 skip_emulated_instruction(vcpu);
4739 return 1;
4740}
4741
851ba692 4742static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4743{
58fbbf26
KT		 4744 if (likely(fasteoi)) {
4745 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4746 int access_type, offset;
4747
4748 access_type = exit_qualification & APIC_ACCESS_TYPE;
4749 offset = exit_qualification & APIC_ACCESS_OFFSET;
4750 /*
4751 * Sane guest uses MOV to write EOI, with written value
4752 * not cared. So make a short-circuit here by avoiding
4753 * heavy instruction emulation.
4754 */
4755 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4756 (offset == APIC_EOI)) {
4757 kvm_lapic_set_eoi(vcpu);
4758 skip_emulated_instruction(vcpu);
4759 return 1;
4760 }
4761 }
51d8b661 4762 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4763}
4764
851ba692 4765static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4766{
60637aac 4767 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4768 unsigned long exit_qualification;
e269fb21
JK		 4769 bool has_error_code = false;
4770 u32 error_code = 0;
37817f29 4771 u16 tss_selector;
7f3d35fd 4772 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4773
4774 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4775 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4776 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4777
4778 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4779
4780 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4781 if (reason == TASK_SWITCH_GATE && idt_v) {
4782 switch (type) {
4783 case INTR_TYPE_NMI_INTR:
4784 vcpu->arch.nmi_injected = false;
654f06fc 4785 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4786 break;
4787 case INTR_TYPE_EXT_INTR:
66fd3f7f 4788 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4789 kvm_clear_interrupt_queue(vcpu);
4790 break;
4791 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4792 if (vmx->idt_vectoring_info &
4793 VECTORING_INFO_DELIVER_CODE_MASK) {
4794 has_error_code = true;
4795 error_code =
4796 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4797 }
4798 /* fall through */
64a7ec06
GN		 4799 case INTR_TYPE_SOFT_EXCEPTION:
4800 kvm_clear_exception_queue(vcpu);
4801 break;
4802 default:
4803 break;
4804 }
60637aac 4805 }
37817f29
IE		 4806 tss_selector = exit_qualification;
4807
64a7ec06
GN		 4808 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4809 type != INTR_TYPE_EXT_INTR &&
4810 type != INTR_TYPE_NMI_INTR))
4811 skip_emulated_instruction(vcpu);
4812
7f3d35fd
KW		 4813 if (kvm_task_switch(vcpu, tss_selector,
4814 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4815 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4816 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4817 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4818 vcpu->run->internal.ndata = 0;
42dbaa5a 4819 return 0;
acb54517 4820 }
42dbaa5a
JK		 4821
4822 /* clear all local breakpoint enable flags */
4823 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4824
4825 /*
4826 * TODO: What about debug traps on tss switch?
4827 * Are we supposed to inject them and update dr6?
4828 */
4829
4830 return 1;
37817f29
IE		 4831}
4832
851ba692 4833static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4834{
f9c617f6 4835 unsigned long exit_qualification;
1439442c 4836 gpa_t gpa;
4f5982a5 4837 u32 error_code;
1439442c 4838 int gla_validity;
1439442c 4839
f9c617f6 4840 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 4841
1439442c
SY		 4842 gla_validity = (exit_qualification >> 7) & 0x3;
4843 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4844 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4845 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4846 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4847 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4848 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4849 (long unsigned int)exit_qualification);
851ba692
AK		 4850 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4851 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4852 return 0;
1439442c
SY		 4853 }
4854
4855 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4856 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4857
4858 /* It is a write fault? */
4859 error_code = exit_qualification & (1U << 1);
4860 /* ept page table is present? */
4861 error_code |= (exit_qualification >> 3) & 0x1;
4862
4863 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4864}
4865
68f89400
MT		 4866static u64 ept_rsvd_mask(u64 spte, int level)
4867{
4868 int i;
4869 u64 mask = 0;
4870
4871 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4872 mask |= (1ULL << i);
4873
4874 if (level > 2)
4875 /* bits 7:3 reserved */
4876 mask |= 0xf8;
4877 else if (level == 2) {
4878 if (spte & (1ULL << 7))
4879 /* 2MB ref, bits 20:12 reserved */
4880 mask |= 0x1ff000;
4881 else
4882 /* bits 6:3 reserved */
4883 mask |= 0x78;
4884 }
4885
4886 return mask;
4887}
4888
4889static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4890 int level)
4891{
4892 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4893
4894 /* 010b (write-only) */
4895 WARN_ON((spte & 0x7) == 0x2);
4896
4897 /* 110b (write/execute) */
4898 WARN_ON((spte & 0x7) == 0x6);
4899
4900 /* 100b (execute-only) and value not supported by logical processor */
4901 if (!cpu_has_vmx_ept_execute_only())
4902 WARN_ON((spte & 0x7) == 0x4);
4903
4904 /* not 000b */
4905 if ((spte & 0x7)) {
4906 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4907
4908 if (rsvd_bits != 0) {
4909 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4910 __func__, rsvd_bits);
4911 WARN_ON(1);
4912 }
4913
4914 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4915 u64 ept_mem_type = (spte & 0x38) >> 3;
4916
4917 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4918 ept_mem_type == 7) {
4919 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4920 __func__, ept_mem_type);
4921 WARN_ON(1);
4922 }
4923 }
4924 }
4925}
4926
851ba692 4927static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4928{
4929 u64 sptes[4];
ce88decf 4930 int nr_sptes, i, ret;
68f89400
MT		 4931 gpa_t gpa;
4932
4933 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4934
ce88decf
XG		 4935 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4936 if (likely(ret == 1))
4937 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4938 EMULATE_DONE;
4939 if (unlikely(!ret))
4940 return 1;
4941
4942 /* It is the real ept misconfig */
68f89400
MT		 4943 printk(KERN_ERR "EPT: Misconfiguration.\n");
4944 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4945
4946 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4947
4948 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4949 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4950
851ba692
AK		 4951 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4952 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4953
4954 return 0;
4955}
4956
851ba692 4957static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4958{
4959 u32 cpu_based_vm_exec_control;
4960
4961 /* clear pending NMI */
4962 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4963 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4964 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4965 ++vcpu->stat.nmi_window_exits;
3842d135 4966 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4967
4968 return 1;
4969}
4970
80ced186 4971static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4972{
8b3079a5
AK		 4973 struct vcpu_vmx *vmx = to_vmx(vcpu);
4974 enum emulation_result err = EMULATE_DONE;
80ced186 4975 int ret = 1;
49e9d557
AK		 4976 u32 cpu_exec_ctrl;
4977 bool intr_window_requested;
b8405c18 4978 unsigned count = 130;
49e9d557
AK		 4979
4980 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4981 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 4982
b8405c18 4983 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 4984 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 4985 return handle_interrupt_window(&vmx->vcpu);
4986
de87dcdd
AK		 4987 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
4988 return 1;
4989
51d8b661 4990 err = emulate_instruction(vcpu, 0);
ea953ef0 4991
80ced186
MG		 4992 if (err == EMULATE_DO_MMIO) {
4993 ret = 0;
4994 goto out;
4995 }
1d5a4d9b 4996
de5f70e0
AK		 4997 if (err != EMULATE_DONE) {
4998 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4999 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5000 vcpu->run->internal.ndata = 0;
6d77dbfc 5001 return 0;
de5f70e0 5002 }
ea953ef0
MG		 5003
5004 if (signal_pending(current))
80ced186 5005 goto out;
ea953ef0
MG		 5006 if (need_resched())
5007 schedule();
5008 }
5009
7c068e45 5010 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5011out:
5012 return ret;
ea953ef0
MG		 5013}
5014
4b8d54f9
ZE		 5015/*
5016 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5017 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5018 */
9fb41ba8 5019static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5020{
5021 skip_emulated_instruction(vcpu);
5022 kvm_vcpu_on_spin(vcpu);
5023
5024 return 1;
5025}
5026
59708670
SY		 5027static int handle_invalid_op(struct kvm_vcpu *vcpu)
5028{
5029 kvm_queue_exception(vcpu, UD_VECTOR);
5030 return 1;
5031}
5032
ff2f6fe9
NHE		 5033/*
5034 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5035 * We could reuse a single VMCS for all the L2 guests, but we also want the
5036 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5037 * allows keeping them loaded on the processor, and in the future will allow
5038 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5039 * every entry if they never change.
5040 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5041 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5042 *
5043 * The following functions allocate and free a vmcs02 in this pool.
5044 */
5045
5046/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5047static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5048{
5049 struct vmcs02_list *item;
5050 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5051 if (item->vmptr == vmx->nested.current_vmptr) {
5052 list_move(&item->list, &vmx->nested.vmcs02_pool);
5053 return &item->vmcs02;
5054 }
5055
5056 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5057 /* Recycle the least recently used VMCS. */
5058 item = list_entry(vmx->nested.vmcs02_pool.prev,
5059 struct vmcs02_list, list);
5060 item->vmptr = vmx->nested.current_vmptr;
5061 list_move(&item->list, &vmx->nested.vmcs02_pool);
5062 return &item->vmcs02;
5063 }
5064
5065 /* Create a new VMCS */
5066 item = (struct vmcs02_list *)
5067 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5068 if (!item)
5069 return NULL;
5070 item->vmcs02.vmcs = alloc_vmcs();
5071 if (!item->vmcs02.vmcs) {
5072 kfree(item);
5073 return NULL;
5074 }
5075 loaded_vmcs_init(&item->vmcs02);
5076 item->vmptr = vmx->nested.current_vmptr;
5077 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5078 vmx->nested.vmcs02_num++;
5079 return &item->vmcs02;
5080}
5081
5082/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5083static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5084{
5085 struct vmcs02_list *item;
5086 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5087 if (item->vmptr == vmptr) {
5088 free_loaded_vmcs(&item->vmcs02);
5089 list_del(&item->list);
5090 kfree(item);
5091 vmx->nested.vmcs02_num--;
5092 return;
5093 }
5094}
5095
5096/*
5097 * Free all VMCSs saved for this vcpu, except the one pointed by
5098 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5099 * currently used, if running L2), and vmcs01 when running L2.
5100 */
5101static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5102{
5103 struct vmcs02_list *item, *n;
5104 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5105 if (vmx->loaded_vmcs != &item->vmcs02)
5106 free_loaded_vmcs(&item->vmcs02);
5107 list_del(&item->list);
5108 kfree(item);
5109 }
5110 vmx->nested.vmcs02_num = 0;
5111
5112 if (vmx->loaded_vmcs != &vmx->vmcs01)
5113 free_loaded_vmcs(&vmx->vmcs01);
5114}
5115
ec378aee
NHE		 5116/*
5117 * Emulate the VMXON instruction.
5118 * Currently, we just remember that VMX is active, and do not save or even
5119 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5120 * do not currently need to store anything in that guest-allocated memory
5121 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5122 * argument is different from the VMXON pointer (which the spec says they do).
5123 */
5124static int handle_vmon(struct kvm_vcpu *vcpu)
5125{
5126 struct kvm_segment cs;
5127 struct vcpu_vmx *vmx = to_vmx(vcpu);
5128
5129 /* The Intel VMX Instruction Reference lists a bunch of bits that
5130 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5131 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5132 * Otherwise, we should fail with #UD. We test these now:
5133 */
5134 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5135 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5136 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5137 kvm_queue_exception(vcpu, UD_VECTOR);
5138 return 1;
5139 }
5140
5141 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5142 if (is_long_mode(vcpu) && !cs.l) {
5143 kvm_queue_exception(vcpu, UD_VECTOR);
5144 return 1;
5145 }
5146
5147 if (vmx_get_cpl(vcpu)) {
5148 kvm_inject_gp(vcpu, 0);
5149 return 1;
5150 }
5151
ff2f6fe9
NHE		 5152 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5153 vmx->nested.vmcs02_num = 0;
5154
ec378aee
NHE		 5155 vmx->nested.vmxon = true;
5156
5157 skip_emulated_instruction(vcpu);
5158 return 1;
5159}
5160
5161/*
5162 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5163 * for running VMX instructions (except VMXON, whose prerequisites are
5164 * slightly different). It also specifies what exception to inject otherwise.
5165 */
5166static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5167{
5168 struct kvm_segment cs;
5169 struct vcpu_vmx *vmx = to_vmx(vcpu);
5170
5171 if (!vmx->nested.vmxon) {
5172 kvm_queue_exception(vcpu, UD_VECTOR);
5173 return 0;
5174 }
5175
5176 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5177 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5178 (is_long_mode(vcpu) && !cs.l)) {
5179 kvm_queue_exception(vcpu, UD_VECTOR);
5180 return 0;
5181 }
5182
5183 if (vmx_get_cpl(vcpu)) {
5184 kvm_inject_gp(vcpu, 0);
5185 return 0;
5186 }
5187
5188 return 1;
5189}
5190
5191/*
5192 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5193 * just stops using VMX.
5194 */
5195static void free_nested(struct vcpu_vmx *vmx)
5196{
5197 if (!vmx->nested.vmxon)
5198 return;
5199 vmx->nested.vmxon = false;
a9d30f33
NHE		 5200 if (vmx->nested.current_vmptr != -1ull) {
5201 kunmap(vmx->nested.current_vmcs12_page);
5202 nested_release_page(vmx->nested.current_vmcs12_page);
5203 vmx->nested.current_vmptr = -1ull;
5204 vmx->nested.current_vmcs12 = NULL;
5205 }
fe3ef05c
NHE		 5206 /* Unpin physical memory we referred to in current vmcs02 */
5207 if (vmx->nested.apic_access_page) {
5208 nested_release_page(vmx->nested.apic_access_page);
5209 vmx->nested.apic_access_page = 0;
5210 }
ff2f6fe9
NHE		 5211
5212 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5213}
5214
5215/* Emulate the VMXOFF instruction */
5216static int handle_vmoff(struct kvm_vcpu *vcpu)
5217{
5218 if (!nested_vmx_check_permission(vcpu))
5219 return 1;
5220 free_nested(to_vmx(vcpu));
5221 skip_emulated_instruction(vcpu);
5222 return 1;
5223}
5224
064aea77
NHE		 5225/*
5226 * Decode the memory-address operand of a vmx instruction, as recorded on an
5227 * exit caused by such an instruction (run by a guest hypervisor).
5228 * On success, returns 0. When the operand is invalid, returns 1 and throws
5229 * #UD or #GP.
5230 */
5231static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5232 unsigned long exit_qualification,
5233 u32 vmx_instruction_info, gva_t *ret)
5234{
5235 /*
5236 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5237 * Execution", on an exit, vmx_instruction_info holds most of the
5238 * addressing components of the operand. Only the displacement part
5239 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5240 * For how an actual address is calculated from all these components,
5241 * refer to Vol. 1, "Operand Addressing".
5242 */
5243 int scaling = vmx_instruction_info & 3;
5244 int addr_size = (vmx_instruction_info >> 7) & 7;
5245 bool is_reg = vmx_instruction_info & (1u << 10);
5246 int seg_reg = (vmx_instruction_info >> 15) & 7;
5247 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5248 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5249 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5250 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5251
5252 if (is_reg) {
5253 kvm_queue_exception(vcpu, UD_VECTOR);
5254 return 1;
5255 }
5256
5257 /* Addr = segment_base + offset */
5258 /* offset = base + [index * scale] + displacement */
5259 *ret = vmx_get_segment_base(vcpu, seg_reg);
5260 if (base_is_valid)
5261 *ret += kvm_register_read(vcpu, base_reg);
5262 if (index_is_valid)
5263 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5264 *ret += exit_qualification; /* holds the displacement */
5265
5266 if (addr_size == 1) /* 32 bit */
5267 *ret &= 0xffffffff;
5268
5269 /*
5270 * TODO: throw #GP (and return 1) in various cases that the VM*
5271 * instructions require it - e.g., offset beyond segment limit,
5272 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5273 * address, and so on. Currently these are not checked.
5274 */
5275 return 0;
5276}
5277
0140caea
NHE		 5278/*
5279 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5280 * set the success or error code of an emulated VMX instruction, as specified
5281 * by Vol 2B, VMX Instruction Reference, "Conventions".
5282 */
5283static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5284{
5285 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5286 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5287 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5288}
5289
5290static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5291{
5292 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5293 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5294 X86_EFLAGS_SF | X86_EFLAGS_OF))
5295 | X86_EFLAGS_CF);
5296}
5297
5298static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5299 u32 vm_instruction_error)
5300{
5301 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5302 /*
5303 * failValid writes the error number to the current VMCS, which
5304 * can't be done there isn't a current VMCS.
5305 */
5306 nested_vmx_failInvalid(vcpu);
5307 return;
5308 }
5309 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5310 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5311 X86_EFLAGS_SF | X86_EFLAGS_OF))
5312 | X86_EFLAGS_ZF);
5313 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5314}
5315
27d6c865
NHE		 5316/* Emulate the VMCLEAR instruction */
5317static int handle_vmclear(struct kvm_vcpu *vcpu)
5318{
5319 struct vcpu_vmx *vmx = to_vmx(vcpu);
5320 gva_t gva;
5321 gpa_t vmptr;
5322 struct vmcs12 *vmcs12;
5323 struct page *page;
5324 struct x86_exception e;
5325
5326 if (!nested_vmx_check_permission(vcpu))
5327 return 1;
5328
5329 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5330 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5331 return 1;
5332
5333 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5334 sizeof(vmptr), &e)) {
5335 kvm_inject_page_fault(vcpu, &e);
5336 return 1;
5337 }
5338
5339 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5340 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5341 skip_emulated_instruction(vcpu);
5342 return 1;
5343 }
5344
5345 if (vmptr == vmx->nested.current_vmptr) {
5346 kunmap(vmx->nested.current_vmcs12_page);
5347 nested_release_page(vmx->nested.current_vmcs12_page);
5348 vmx->nested.current_vmptr = -1ull;
5349 vmx->nested.current_vmcs12 = NULL;
5350 }
5351
5352 page = nested_get_page(vcpu, vmptr);
5353 if (page == NULL) {
5354 /*
5355 * For accurate processor emulation, VMCLEAR beyond available
5356 * physical memory should do nothing at all. However, it is
5357 * possible that a nested vmx bug, not a guest hypervisor bug,
5358 * resulted in this case, so let's shut down before doing any
5359 * more damage:
5360 */
5361 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5362 return 1;
5363 }
5364 vmcs12 = kmap(page);
5365 vmcs12->launch_state = 0;
5366 kunmap(page);
5367 nested_release_page(page);
5368
5369 nested_free_vmcs02(vmx, vmptr);
5370
5371 skip_emulated_instruction(vcpu);
5372 nested_vmx_succeed(vcpu);
5373 return 1;
5374}
5375
cd232ad0
NHE		 5376static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5377
5378/* Emulate the VMLAUNCH instruction */
5379static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5380{
5381 return nested_vmx_run(vcpu, true);
5382}
5383
5384/* Emulate the VMRESUME instruction */
5385static int handle_vmresume(struct kvm_vcpu *vcpu)
5386{
5387
5388 return nested_vmx_run(vcpu, false);
5389}
5390
49f705c5
NHE		 5391enum vmcs_field_type {
5392 VMCS_FIELD_TYPE_U16 = 0,
5393 VMCS_FIELD_TYPE_U64 = 1,
5394 VMCS_FIELD_TYPE_U32 = 2,
5395 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5396};
5397
5398static inline int vmcs_field_type(unsigned long field)
5399{
5400 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5401 return VMCS_FIELD_TYPE_U32;
5402 return (field >> 13) & 0x3 ;
5403}
5404
5405static inline int vmcs_field_readonly(unsigned long field)
5406{
5407 return (((field >> 10) & 0x3) == 1);
5408}
5409
5410/*
5411 * Read a vmcs12 field. Since these can have varying lengths and we return
5412 * one type, we chose the biggest type (u64) and zero-extend the return value
5413 * to that size. Note that the caller, handle_vmread, might need to use only
5414 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5415 * 64-bit fields are to be returned).
5416 */
5417static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5418 unsigned long field, u64 *ret)
5419{
5420 short offset = vmcs_field_to_offset(field);
5421 char *p;
5422
5423 if (offset < 0)
5424 return 0;
5425
5426 p = ((char *)(get_vmcs12(vcpu))) + offset;
5427
5428 switch (vmcs_field_type(field)) {
5429 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5430 *ret = *((natural_width *)p);
5431 return 1;
5432 case VMCS_FIELD_TYPE_U16:
5433 *ret = *((u16 *)p);
5434 return 1;
5435 case VMCS_FIELD_TYPE_U32:
5436 *ret = *((u32 *)p);
5437 return 1;
5438 case VMCS_FIELD_TYPE_U64:
5439 *ret = *((u64 *)p);
5440 return 1;
5441 default:
5442 return 0; /* can never happen. */
5443 }
5444}
5445
5446/*
5447 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5448 * used before) all generate the same failure when it is missing.
5449 */
5450static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5451{
5452 struct vcpu_vmx *vmx = to_vmx(vcpu);
5453 if (vmx->nested.current_vmptr == -1ull) {
5454 nested_vmx_failInvalid(vcpu);
5455 skip_emulated_instruction(vcpu);
5456 return 0;
5457 }
5458 return 1;
5459}
5460
5461static int handle_vmread(struct kvm_vcpu *vcpu)
5462{
5463 unsigned long field;
5464 u64 field_value;
5465 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5466 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5467 gva_t gva = 0;
5468
5469 if (!nested_vmx_check_permission(vcpu) ||
5470 !nested_vmx_check_vmcs12(vcpu))
5471 return 1;
5472
5473 /* Decode instruction info and find the field to read */
5474 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5475 /* Read the field, zero-extended to a u64 field_value */
5476 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5477 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5478 skip_emulated_instruction(vcpu);
5479 return 1;
5480 }
5481 /*
5482 * Now copy part of this value to register or memory, as requested.
5483 * Note that the number of bits actually copied is 32 or 64 depending
5484 * on the guest's mode (32 or 64 bit), not on the given field's length.
5485 */
5486 if (vmx_instruction_info & (1u << 10)) {
5487 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5488 field_value);
5489 } else {
5490 if (get_vmx_mem_address(vcpu, exit_qualification,
5491 vmx_instruction_info, &gva))
5492 return 1;
5493 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5494 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5495 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5496 }
5497
5498 nested_vmx_succeed(vcpu);
5499 skip_emulated_instruction(vcpu);
5500 return 1;
5501}
5502
5503
5504static int handle_vmwrite(struct kvm_vcpu *vcpu)
5505{
5506 unsigned long field;
5507 gva_t gva;
5508 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5509 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5510 char *p;
5511 short offset;
5512 /* The value to write might be 32 or 64 bits, depending on L1's long
5513 * mode, and eventually we need to write that into a field of several
5514 * possible lengths. The code below first zero-extends the value to 64
5515 * bit (field_value), and then copies only the approriate number of
5516 * bits into the vmcs12 field.
5517 */
5518 u64 field_value = 0;
5519 struct x86_exception e;
5520
5521 if (!nested_vmx_check_permission(vcpu) ||
5522 !nested_vmx_check_vmcs12(vcpu))
5523 return 1;
5524
5525 if (vmx_instruction_info & (1u << 10))
5526 field_value = kvm_register_read(vcpu,
5527 (((vmx_instruction_info) >> 3) & 0xf));
5528 else {
5529 if (get_vmx_mem_address(vcpu, exit_qualification,
5530 vmx_instruction_info, &gva))
5531 return 1;
5532 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5533 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5534 kvm_inject_page_fault(vcpu, &e);
5535 return 1;
5536 }
5537 }
5538
5539
5540 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5541 if (vmcs_field_readonly(field)) {
5542 nested_vmx_failValid(vcpu,
5543 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5544 skip_emulated_instruction(vcpu);
5545 return 1;
5546 }
5547
5548 offset = vmcs_field_to_offset(field);
5549 if (offset < 0) {
5550 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5551 skip_emulated_instruction(vcpu);
5552 return 1;
5553 }
5554 p = ((char *) get_vmcs12(vcpu)) + offset;
5555
5556 switch (vmcs_field_type(field)) {
5557 case VMCS_FIELD_TYPE_U16:
5558 *(u16 *)p = field_value;
5559 break;
5560 case VMCS_FIELD_TYPE_U32:
5561 *(u32 *)p = field_value;
5562 break;
5563 case VMCS_FIELD_TYPE_U64:
5564 *(u64 *)p = field_value;
5565 break;
5566 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5567 *(natural_width *)p = field_value;
5568 break;
5569 default:
5570 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5571 skip_emulated_instruction(vcpu);
5572 return 1;
5573 }
5574
5575 nested_vmx_succeed(vcpu);
5576 skip_emulated_instruction(vcpu);
5577 return 1;
5578}
5579
63846663
NHE		 5580/* Emulate the VMPTRLD instruction */
5581static int handle_vmptrld(struct kvm_vcpu *vcpu)
5582{
5583 struct vcpu_vmx *vmx = to_vmx(vcpu);
5584 gva_t gva;
5585 gpa_t vmptr;
5586 struct x86_exception e;
5587
5588 if (!nested_vmx_check_permission(vcpu))
5589 return 1;
5590
5591 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5592 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5593 return 1;
5594
5595 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5596 sizeof(vmptr), &e)) {
5597 kvm_inject_page_fault(vcpu, &e);
5598 return 1;
5599 }
5600
5601 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5602 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5603 skip_emulated_instruction(vcpu);
5604 return 1;
5605 }
5606
5607 if (vmx->nested.current_vmptr != vmptr) {
5608 struct vmcs12 *new_vmcs12;
5609 struct page *page;
5610 page = nested_get_page(vcpu, vmptr);
5611 if (page == NULL) {
5612 nested_vmx_failInvalid(vcpu);
5613 skip_emulated_instruction(vcpu);
5614 return 1;
5615 }
5616 new_vmcs12 = kmap(page);
5617 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5618 kunmap(page);
5619 nested_release_page_clean(page);
5620 nested_vmx_failValid(vcpu,
5621 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5622 skip_emulated_instruction(vcpu);
5623 return 1;
5624 }
5625 if (vmx->nested.current_vmptr != -1ull) {
5626 kunmap(vmx->nested.current_vmcs12_page);
5627 nested_release_page(vmx->nested.current_vmcs12_page);
5628 }
5629
5630 vmx->nested.current_vmptr = vmptr;
5631 vmx->nested.current_vmcs12 = new_vmcs12;
5632 vmx->nested.current_vmcs12_page = page;
5633 }
5634
5635 nested_vmx_succeed(vcpu);
5636 skip_emulated_instruction(vcpu);
5637 return 1;
5638}
5639
6a4d7550
NHE		 5640/* Emulate the VMPTRST instruction */
5641static int handle_vmptrst(struct kvm_vcpu *vcpu)
5642{
5643 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5644 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5645 gva_t vmcs_gva;
5646 struct x86_exception e;
5647
5648 if (!nested_vmx_check_permission(vcpu))
5649 return 1;
5650
5651 if (get_vmx_mem_address(vcpu, exit_qualification,
5652 vmx_instruction_info, &vmcs_gva))
5653 return 1;
5654 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5655 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5656 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5657 sizeof(u64), &e)) {
5658 kvm_inject_page_fault(vcpu, &e);
5659 return 1;
5660 }
5661 nested_vmx_succeed(vcpu);
5662 skip_emulated_instruction(vcpu);
5663 return 1;
5664}
5665
6aa8b732
AK		 5666/*
5667 * The exit handlers return 1 if the exit was handled fully and guest execution
5668 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5669 * to be done to userspace and return 0.
5670 */
772e0318 5671static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5672 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5673 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5674 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5675 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5676 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5677 [EXIT_REASON_CR_ACCESS] = handle_cr,
5678 [EXIT_REASON_DR_ACCESS] = handle_dr,
5679 [EXIT_REASON_CPUID] = handle_cpuid,
5680 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5681 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5682 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5683 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5684 [EXIT_REASON_INVD] = handle_invd,
a7052897 5685 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5686 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5687 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5688 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5689 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5690 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5691 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5692 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5693 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5694 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5695 [EXIT_REASON_VMOFF] = handle_vmoff,
5696 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5697 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5698 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5699 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5700 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5701 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5702 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5703 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5704 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5705 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5706 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5707 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5708};
5709
5710static const int kvm_vmx_max_exit_handlers =
50a3485c 5711 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5712
644d711a
NHE		 5713/*
5714 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5715 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5716 * disinterest in the current event (read or write a specific MSR) by using an
5717 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5718 */
5719static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5720 struct vmcs12 *vmcs12, u32 exit_reason)
5721{
5722 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5723 gpa_t bitmap;
5724
5725 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5726 return 1;
5727
5728 /*
5729 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5730 * for the four combinations of read/write and low/high MSR numbers.
5731 * First we need to figure out which of the four to use:
5732 */
5733 bitmap = vmcs12->msr_bitmap;
5734 if (exit_reason == EXIT_REASON_MSR_WRITE)
5735 bitmap += 2048;
5736 if (msr_index >= 0xc0000000) {
5737 msr_index -= 0xc0000000;
5738 bitmap += 1024;
5739 }
5740
5741 /* Then read the msr_index'th bit from this bitmap: */
5742 if (msr_index < 1024*8) {
5743 unsigned char b;
5744 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5745 return 1 & (b >> (msr_index & 7));
5746 } else
5747 return 1; /* let L1 handle the wrong parameter */
5748}
5749
5750/*
5751 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5752 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5753 * intercept (via guest_host_mask etc.) the current event.
5754 */
5755static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5756 struct vmcs12 *vmcs12)
5757{
5758 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5759 int cr = exit_qualification & 15;
5760 int reg = (exit_qualification >> 8) & 15;
5761 unsigned long val = kvm_register_read(vcpu, reg);
5762
5763 switch ((exit_qualification >> 4) & 3) {
5764 case 0: /* mov to cr */
5765 switch (cr) {
5766 case 0:
5767 if (vmcs12->cr0_guest_host_mask &
5768 (val ^ vmcs12->cr0_read_shadow))
5769 return 1;
5770 break;
5771 case 3:
5772 if ((vmcs12->cr3_target_count >= 1 &&
5773 vmcs12->cr3_target_value0 == val) ||
5774 (vmcs12->cr3_target_count >= 2 &&
5775 vmcs12->cr3_target_value1 == val) ||
5776 (vmcs12->cr3_target_count >= 3 &&
5777 vmcs12->cr3_target_value2 == val) ||
5778 (vmcs12->cr3_target_count >= 4 &&
5779 vmcs12->cr3_target_value3 == val))
5780 return 0;
5781 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5782 return 1;
5783 break;
5784 case 4:
5785 if (vmcs12->cr4_guest_host_mask &
5786 (vmcs12->cr4_read_shadow ^ val))
5787 return 1;
5788 break;
5789 case 8:
5790 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5791 return 1;
5792 break;
5793 }
5794 break;
5795 case 2: /* clts */
5796 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5797 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5798 return 1;
5799 break;
5800 case 1: /* mov from cr */
5801 switch (cr) {
5802 case 3:
5803 if (vmcs12->cpu_based_vm_exec_control &
5804 CPU_BASED_CR3_STORE_EXITING)
5805 return 1;
5806 break;
5807 case 8:
5808 if (vmcs12->cpu_based_vm_exec_control &
5809 CPU_BASED_CR8_STORE_EXITING)
5810 return 1;
5811 break;
5812 }
5813 break;
5814 case 3: /* lmsw */
5815 /*
5816 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5817 * cr0. Other attempted changes are ignored, with no exit.
5818 */
5819 if (vmcs12->cr0_guest_host_mask & 0xe &
5820 (val ^ vmcs12->cr0_read_shadow))
5821 return 1;
5822 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5823 !(vmcs12->cr0_read_shadow & 0x1) &&
5824 (val & 0x1))
5825 return 1;
5826 break;
5827 }
5828 return 0;
5829}
5830
5831/*
5832 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5833 * should handle it ourselves in L0 (and then continue L2). Only call this
5834 * when in is_guest_mode (L2).
5835 */
5836static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5837{
5838 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5839 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5840 struct vcpu_vmx *vmx = to_vmx(vcpu);
5841 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5842
5843 if (vmx->nested.nested_run_pending)
5844 return 0;
5845
5846 if (unlikely(vmx->fail)) {
bd80158a
JK		 5847 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5848 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5849 return 1;
5850 }
5851
5852 switch (exit_reason) {
5853 case EXIT_REASON_EXCEPTION_NMI:
5854 if (!is_exception(intr_info))
5855 return 0;
5856 else if (is_page_fault(intr_info))
5857 return enable_ept;
5858 return vmcs12->exception_bitmap &
5859 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5860 case EXIT_REASON_EXTERNAL_INTERRUPT:
5861 return 0;
5862 case EXIT_REASON_TRIPLE_FAULT:
5863 return 1;
5864 case EXIT_REASON_PENDING_INTERRUPT:
5865 case EXIT_REASON_NMI_WINDOW:
5866 /*
5867 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5868 * (aka Interrupt Window Exiting) only when L1 turned it on,
5869 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5870 * Same for NMI Window Exiting.
5871 */
5872 return 1;
5873 case EXIT_REASON_TASK_SWITCH:
5874 return 1;
5875 case EXIT_REASON_CPUID:
5876 return 1;
5877 case EXIT_REASON_HLT:
5878 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5879 case EXIT_REASON_INVD:
5880 return 1;
5881 case EXIT_REASON_INVLPG:
5882 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5883 case EXIT_REASON_RDPMC:
5884 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5885 case EXIT_REASON_RDTSC:
5886 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5887 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5888 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5889 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5890 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5891 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5892 /*
5893 * VMX instructions trap unconditionally. This allows L1 to
5894 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5895 */
5896 return 1;
5897 case EXIT_REASON_CR_ACCESS:
5898 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5899 case EXIT_REASON_DR_ACCESS:
5900 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5901 case EXIT_REASON_IO_INSTRUCTION:
5902 /* TODO: support IO bitmaps */
5903 return 1;
5904 case EXIT_REASON_MSR_READ:
5905 case EXIT_REASON_MSR_WRITE:
5906 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5907 case EXIT_REASON_INVALID_STATE:
5908 return 1;
5909 case EXIT_REASON_MWAIT_INSTRUCTION:
5910 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5911 case EXIT_REASON_MONITOR_INSTRUCTION:
5912 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5913 case EXIT_REASON_PAUSE_INSTRUCTION:
5914 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5915 nested_cpu_has2(vmcs12,
5916 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5917 case EXIT_REASON_MCE_DURING_VMENTRY:
5918 return 0;
5919 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5920 return 1;
5921 case EXIT_REASON_APIC_ACCESS:
5922 return nested_cpu_has2(vmcs12,
5923 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5924 case EXIT_REASON_EPT_VIOLATION:
5925 case EXIT_REASON_EPT_MISCONFIG:
5926 return 0;
5927 case EXIT_REASON_WBINVD:
5928 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5929 case EXIT_REASON_XSETBV:
5930 return 1;
5931 default:
5932 return 1;
5933 }
5934}
5935
586f9607
AK		 5936static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5937{
5938 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5939 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5940}
5941
6aa8b732
AK		 5942/*
5943 * The guest has exited. See if we can fix it or if we need userspace
5944 * assistance.
5945 */
851ba692 5946static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5947{
29bd8a78 5948 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5949 u32 exit_reason = vmx->exit_reason;
1155f76a 5950 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5951
80ced186
MG		 5952 /* If guest state is invalid, start emulating */
5953 if (vmx->emulation_required && emulate_invalid_guest_state)
5954 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5955
b6f1250e
NHE		 5956 /*
5957 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5958 * we did not inject a still-pending event to L1 now because of
5959 * nested_run_pending, we need to re-enable this bit.
5960 */
5961 if (vmx->nested.nested_run_pending)
5962 kvm_make_request(KVM_REQ_EVENT, vcpu);
5963
509c75ea
NHE		 5964 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5965 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5966 vmx->nested.nested_run_pending = 1;
5967 else
5968 vmx->nested.nested_run_pending = 0;
5969
5970 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5971 nested_vmx_vmexit(vcpu);
5972 return 1;
5973 }
5974
5120702e
MG		 5975 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5976 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5977 vcpu->run->fail_entry.hardware_entry_failure_reason
5978 = exit_reason;
5979 return 0;
5980 }
5981
29bd8a78 5982 if (unlikely(vmx->fail)) {
851ba692
AK		 5983 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5984 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5985 = vmcs_read32(VM_INSTRUCTION_ERROR);
5986 return 0;
5987 }
6aa8b732 5988
b9bf6882
XG		 5989 /*
5990 * Note:
5991 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5992 * delivery event since it indicates guest is accessing MMIO.
5993 * The vm-exit can be triggered again after return to guest that
5994 * will cause infinite loop.
5995 */
d77c26fc 5996 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5997 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 5998 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 5999 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6000 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6001 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6002 vcpu->run->internal.ndata = 2;
6003 vcpu->run->internal.data[0] = vectoring_info;
6004 vcpu->run->internal.data[1] = exit_reason;
6005 return 0;
6006 }
3b86cd99 6007
644d711a
NHE		 6008 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6009 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6010 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6011 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6012 vmx->soft_vnmi_blocked = 0;
3b86cd99 6013 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6014 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6015 /*
6016 * This CPU don't support us in finding the end of an
6017 * NMI-blocked window if the guest runs with IRQs
6018 * disabled. So we pull the trigger after 1 s of
6019 * futile waiting, but inform the user about this.
6020 */
6021 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6022 "state on VCPU %d after 1 s timeout\n",
6023 __func__, vcpu->vcpu_id);
6024 vmx->soft_vnmi_blocked = 0;
3b86cd99 6025 }
3b86cd99
JK		 6026 }
6027
6aa8b732
AK		 6028 if (exit_reason < kvm_vmx_max_exit_handlers
6029 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6030 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6031 else {
851ba692
AK		 6032 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6033 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6034 }
6035 return 0;
6036}
6037
95ba8273 6038static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6039{
95ba8273 6040 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6041 vmcs_write32(TPR_THRESHOLD, 0);
6042 return;
6043 }
6044
95ba8273 6045 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6046}
6047
51aa01d1 6048static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6049{
00eba012
AK		 6050 u32 exit_intr_info;
6051
6052 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6053 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6054 return;
6055
c5ca8e57 6056 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6057 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6058
6059 /* Handle machine checks before interrupts are enabled */
00eba012 6060 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6061 kvm_machine_check();
6062
20f65983 6063 /* We need to handle NMIs before interrupts are enabled */
00eba012 6064 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6065 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6066 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6067 asm("int $2");
ff9d07a0
ZY		 6068 kvm_after_handle_nmi(&vmx->vcpu);
6069 }
51aa01d1 6070}
20f65983 6071
51aa01d1
AK		 6072static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6073{
c5ca8e57 6074 u32 exit_intr_info;
51aa01d1
AK		 6075 bool unblock_nmi;
6076 u8 vector;
6077 bool idtv_info_valid;
6078
6079 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6080
cf393f75 6081 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6082 if (vmx->nmi_known_unmasked)
6083 return;
c5ca8e57
AK		 6084 /*
6085 * Can't use vmx->exit_intr_info since we're not sure what
6086 * the exit reason is.
6087 */
6088 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6089 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6090 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6091 /*
7b4a25cb 6092 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6093 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6094 * a guest IRET fault.
7b4a25cb
GN		 6095 * SDM 3: 23.2.2 (September 2008)
6096 * Bit 12 is undefined in any of the following cases:
6097 * If the VM exit sets the valid bit in the IDT-vectoring
6098 * information field.
6099 * If the VM exit is due to a double fault.
cf393f75 6100 */
7b4a25cb
GN		 6101 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6102 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6103 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6104 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6105 else
6106 vmx->nmi_known_unmasked =
6107 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6108 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6109 } else if (unlikely(vmx->soft_vnmi_blocked))
6110 vmx->vnmi_blocked_time +=
6111 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6112}
6113
83422e17
AK		 6114static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6115 u32 idt_vectoring_info,
6116 int instr_len_field,
6117 int error_code_field)
51aa01d1 6118{
51aa01d1
AK		 6119 u8 vector;
6120 int type;
6121 bool idtv_info_valid;
6122
6123 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6124
37b96e98
GN		 6125 vmx->vcpu.arch.nmi_injected = false;
6126 kvm_clear_exception_queue(&vmx->vcpu);
6127 kvm_clear_interrupt_queue(&vmx->vcpu);
6128
6129 if (!idtv_info_valid)
6130 return;
6131
3842d135
AK		 6132 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6133
668f612f
AK		 6134 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6135 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6136
64a7ec06 6137 switch (type) {
37b96e98
GN		 6138 case INTR_TYPE_NMI_INTR:
6139 vmx->vcpu.arch.nmi_injected = true;
668f612f 6140 /*
7b4a25cb 6141 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6142 * Clear bit "block by NMI" before VM entry if a NMI
6143 * delivery faulted.
668f612f 6144 */
654f06fc 6145 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6146 break;
37b96e98 6147 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6148 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6149 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6150 /* fall through */
6151 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6152 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6153 u32 err = vmcs_read32(error_code_field);
37b96e98 6154 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6155 } else
6156 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6157 break;
66fd3f7f
GN		 6158 case INTR_TYPE_SOFT_INTR:
6159 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6160 vmcs_read32(instr_len_field);
66fd3f7f 6161 /* fall through */
37b96e98 6162 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6163 kvm_queue_interrupt(&vmx->vcpu, vector,
6164 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6165 break;
6166 default:
6167 break;
f7d9238f 6168 }
cf393f75
AK		 6169}
6170
83422e17
AK		 6171static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6172{
66c78ae4
NHE		 6173 if (is_guest_mode(&vmx->vcpu))
6174 return;
83422e17
AK		 6175 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6176 VM_EXIT_INSTRUCTION_LEN,
6177 IDT_VECTORING_ERROR_CODE);
6178}
6179
b463a6f7
AK		 6180static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6181{
66c78ae4
NHE		 6182 if (is_guest_mode(vcpu))
6183 return;
b463a6f7
AK		 6184 __vmx_complete_interrupts(to_vmx(vcpu),
6185 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6186 VM_ENTRY_INSTRUCTION_LEN,
6187 VM_ENTRY_EXCEPTION_ERROR_CODE);
6188
6189 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6190}
6191
d7cd9796
GN		 6192static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6193{
6194 int i, nr_msrs;
6195 struct perf_guest_switch_msr *msrs;
6196
6197 msrs = perf_guest_get_msrs(&nr_msrs);
6198
6199 if (!msrs)
6200 return;
6201
6202 for (i = 0; i < nr_msrs; i++)
6203 if (msrs[i].host == msrs[i].guest)
6204 clear_atomic_switch_msr(vmx, msrs[i].msr);
6205 else
6206 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6207 msrs[i].host);
6208}
6209
a3b5ba49 6210static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6211{
a2fa3e9f 6212 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6213 unsigned long debugctlmsr;
104f226b 6214
66c78ae4
NHE		 6215 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6216 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6217 if (vmcs12->idt_vectoring_info_field &
6218 VECTORING_INFO_VALID_MASK) {
6219 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6220 vmcs12->idt_vectoring_info_field);
6221 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6222 vmcs12->vm_exit_instruction_len);
6223 if (vmcs12->idt_vectoring_info_field &
6224 VECTORING_INFO_DELIVER_CODE_MASK)
6225 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6226 vmcs12->idt_vectoring_error_code);
6227 }
6228 }
6229
104f226b
AK		 6230 /* Record the guest's net vcpu time for enforced NMI injections. */
6231 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6232 vmx->entry_time = ktime_get();
6233
6234 /* Don't enter VMX if guest state is invalid, let the exit handler
6235 start emulation until we arrive back to a valid state */
6236 if (vmx->emulation_required && emulate_invalid_guest_state)
6237 return;
6238
6239 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6240 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6241 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6242 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6243
6244 /* When single-stepping over STI and MOV SS, we must clear the
6245 * corresponding interruptibility bits in the guest state. Otherwise
6246 * vmentry fails as it then expects bit 14 (BS) in pending debug
6247 * exceptions being set, but that's not correct for the guest debugging
6248 * case. */
6249 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6250 vmx_set_interrupt_shadow(vcpu, 0);
6251
d7cd9796 6252 atomic_switch_perf_msrs(vmx);
2a7921b7 6253 debugctlmsr = get_debugctlmsr();
d7cd9796 6254
d462b819 6255 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6256 asm(
6aa8b732 6257 /* Store host registers */
b188c81f
AK		 6258 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6259 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6260 "push %%" _ASM_CX " \n\t"
6261 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6262 "je 1f \n\t"
b188c81f 6263 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6264 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6265 "1: \n\t"
d3edefc0 6266 /* Reload cr2 if changed */
b188c81f
AK		 6267 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6268 "mov %%cr2, %%" _ASM_DX " \n\t"
6269 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6270 "je 2f \n\t"
b188c81f 6271 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6272 "2: \n\t"
6aa8b732 6273 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6274 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6275 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6276 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6277 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6278 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6279 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6280 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6281 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6282#ifdef CONFIG_X86_64
e08aa78a
AK		 6283 "mov %c[r8](%0), %%r8 \n\t"
6284 "mov %c[r9](%0), %%r9 \n\t"
6285 "mov %c[r10](%0), %%r10 \n\t"
6286 "mov %c[r11](%0), %%r11 \n\t"
6287 "mov %c[r12](%0), %%r12 \n\t"
6288 "mov %c[r13](%0), %%r13 \n\t"
6289 "mov %c[r14](%0), %%r14 \n\t"
6290 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6291#endif
b188c81f 6292 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6293
6aa8b732 6294 /* Enter guest mode */
83287ea4 6295 "jne 1f \n\t"
4ecac3fd 6296 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6297 "jmp 2f \n\t"
6298 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6299 "2: "
6aa8b732 6300 /* Save guest registers, load host registers, keep flags */
b188c81f 6301 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6302 "pop %0 \n\t"
b188c81f
AK		 6303 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6304 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6305 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6306 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6307 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6308 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6309 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6310#ifdef CONFIG_X86_64
e08aa78a
AK		 6311 "mov %%r8, %c[r8](%0) \n\t"
6312 "mov %%r9, %c[r9](%0) \n\t"
6313 "mov %%r10, %c[r10](%0) \n\t"
6314 "mov %%r11, %c[r11](%0) \n\t"
6315 "mov %%r12, %c[r12](%0) \n\t"
6316 "mov %%r13, %c[r13](%0) \n\t"
6317 "mov %%r14, %c[r14](%0) \n\t"
6318 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6319#endif
b188c81f
AK		 6320 "mov %%cr2, %%" _ASM_AX " \n\t"
6321 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6322
b188c81f 6323 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6324 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6325 ".pushsection .rodata \n\t"
6326 ".global vmx_return \n\t"
6327 "vmx_return: " _ASM_PTR " 2b \n\t"
6328 ".popsection"
e08aa78a 6329 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6330 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6331 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6332 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6333 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6334 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6335 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6336 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6337 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6338 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6339 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6340#ifdef CONFIG_X86_64
ad312c7c
ZX		 6341 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6342 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6343 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6344 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6345 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6346 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6347 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6348 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6349#endif
40712fae
AK		 6350 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6351 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6352 : "cc", "memory"
6353#ifdef CONFIG_X86_64
b188c81f 6354 , "rax", "rbx", "rdi", "rsi"
c2036300 6355 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6356#else
6357 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6358#endif
6359 );
6aa8b732 6360
2a7921b7
GN		 6361 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6362 if (debugctlmsr)
6363 update_debugctlmsr(debugctlmsr);
6364
aa67f609
AK		 6365#ifndef CONFIG_X86_64
6366 /*
6367 * The sysexit path does not restore ds/es, so we must set them to
6368 * a reasonable value ourselves.
6369 *
6370 * We can't defer this to vmx_load_host_state() since that function
6371 * may be executed in interrupt context, which saves and restore segments
6372 * around it, nullifying its effect.
6373 */
6374 loadsegment(ds, __USER_DS);
6375 loadsegment(es, __USER_DS);
6376#endif
6377
6de4f3ad 6378 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6379 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6380 | (1 << VCPU_EXREG_CPL)
aff48baa 6381 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6382 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6383 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6384 vcpu->arch.regs_dirty = 0;
6385
1155f76a
AK		 6386 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6387
66c78ae4
NHE		 6388 if (is_guest_mode(vcpu)) {
6389 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6390 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6391 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6392 vmcs12->idt_vectoring_error_code =
6393 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6394 vmcs12->vm_exit_instruction_len =
6395 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6396 }
6397 }
6398
d462b819 6399 vmx->loaded_vmcs->launched = 1;
1b6269db 6400
51aa01d1 6401 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6402 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6403
6404 vmx_complete_atomic_exit(vmx);
6405 vmx_recover_nmi_blocking(vmx);
cf393f75 6406 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6407}
6408
6aa8b732
AK		 6409static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6410{
fb3f0f51
RR		 6411 struct vcpu_vmx *vmx = to_vmx(vcpu);
6412
cdbecfc3 6413 free_vpid(vmx);
ec378aee 6414 free_nested(vmx);
d462b819 6415 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6416 kfree(vmx->guest_msrs);
6417 kvm_vcpu_uninit(vcpu);
a4770347 6418 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6419}
6420
fb3f0f51 6421static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6422{
fb3f0f51 6423 int err;
c16f862d 6424 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6425 int cpu;
6aa8b732 6426
a2fa3e9f 6427 if (!vmx)
fb3f0f51
RR		 6428 return ERR_PTR(-ENOMEM);
6429
2384d2b3
SY		 6430 allocate_vpid(vmx);
6431
fb3f0f51
RR		 6432 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6433 if (err)
6434 goto free_vcpu;
965b58a5 6435
a2fa3e9f 6436 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6437 err = -ENOMEM;
fb3f0f51 6438 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6439 goto uninit_vcpu;
6440 }
965b58a5 6441
d462b819
NHE		 6442 vmx->loaded_vmcs = &vmx->vmcs01;
6443 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6444 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6445 goto free_msrs;
d462b819
NHE		 6446 if (!vmm_exclusive)
6447 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6448 loaded_vmcs_init(vmx->loaded_vmcs);
6449 if (!vmm_exclusive)
6450 kvm_cpu_vmxoff();
a2fa3e9f 6451
15ad7146
AK		 6452 cpu = get_cpu();
6453 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6454 vmx->vcpu.cpu = cpu;
8b9cf98c 6455 err = vmx_vcpu_setup(vmx);
fb3f0f51 6456 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6457 put_cpu();
fb3f0f51
RR		 6458 if (err)
6459 goto free_vmcs;
5e4a0b3c 6460 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6461 err = alloc_apic_access_page(kvm);
6462 if (err)
5e4a0b3c 6463 goto free_vmcs;
fb3f0f51 6464
b927a3ce
SY		 6465 if (enable_ept) {
6466 if (!kvm->arch.ept_identity_map_addr)
6467 kvm->arch.ept_identity_map_addr =
6468 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6469 err = -ENOMEM;
b7ebfb05
SY		 6470 if (alloc_identity_pagetable(kvm) != 0)
6471 goto free_vmcs;
93ea5388
GN		 6472 if (!init_rmode_identity_map(kvm))
6473 goto free_vmcs;
b927a3ce 6474 }
b7ebfb05 6475
a9d30f33
NHE		 6476 vmx->nested.current_vmptr = -1ull;
6477 vmx->nested.current_vmcs12 = NULL;
6478
fb3f0f51
RR		 6479 return &vmx->vcpu;
6480
6481free_vmcs:
5f3fbc34 6482 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6483free_msrs:
fb3f0f51
RR		 6484 kfree(vmx->guest_msrs);
6485uninit_vcpu:
6486 kvm_vcpu_uninit(&vmx->vcpu);
6487free_vcpu:
cdbecfc3 6488 free_vpid(vmx);
a4770347 6489 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6490 return ERR_PTR(err);
6aa8b732
AK		 6491}
6492
002c7f7c
YS		 6493static void __init vmx_check_processor_compat(void *rtn)
6494{
6495 struct vmcs_config vmcs_conf;
6496
6497 *(int *)rtn = 0;
6498 if (setup_vmcs_config(&vmcs_conf) < 0)
6499 *(int *)rtn = -EIO;
6500 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6501 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6502 smp_processor_id());
6503 *(int *)rtn = -EIO;
6504 }
6505}
6506
67253af5
SY		 6507static int get_ept_level(void)
6508{
6509 return VMX_EPT_DEFAULT_GAW + 1;
6510}
6511
4b12f0de 6512static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6513{
4b12f0de
SY		 6514 u64 ret;
6515
522c68c4
SY		 6516 /* For VT-d and EPT combination
6517 * 1. MMIO: always map as UC
6518 * 2. EPT with VT-d:
6519 * a. VT-d without snooping control feature: can't guarantee the
6520 * result, try to trust guest.
6521 * b. VT-d with snooping control feature: snooping control feature of
6522 * VT-d engine can guarantee the cache correctness. Just set it
6523 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6524 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6525 * consistent with host MTRR
6526 */
4b12f0de
SY		 6527 if (is_mmio)
6528 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6529 else if (vcpu->kvm->arch.iommu_domain &&
6530 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6531 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6532 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6533 else
522c68c4 6534 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6535 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6536
6537 return ret;
64d4d521
SY		 6538}
6539
17cc3935 6540static int vmx_get_lpage_level(void)
344f414f 6541{
878403b7
SY		 6542 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6543 return PT_DIRECTORY_LEVEL;
6544 else
6545 /* For shadow and EPT supported 1GB page */
6546 return PT_PDPE_LEVEL;
344f414f
JR		 6547}
6548
0e851880
SY		 6549static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6550{
4e47c7a6
SY		 6551 struct kvm_cpuid_entry2 *best;
6552 struct vcpu_vmx *vmx = to_vmx(vcpu);
6553 u32 exec_control;
6554
6555 vmx->rdtscp_enabled = false;
6556 if (vmx_rdtscp_supported()) {
6557 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6558 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6559 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6560 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6561 vmx->rdtscp_enabled = true;
6562 else {
6563 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6564 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6565 exec_control);
6566 }
6567 }
6568 }
ad756a16
MJ		 6569
6570 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6571 /* Exposing INVPCID only when PCID is exposed */
6572 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6573 if (vmx_invpcid_supported() &&
4f977045 6574 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16
MJ		 6575 guest_cpuid_has_pcid(vcpu)) {
6576 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6577 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6578 exec_control);
6579 } else {
6580 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6581 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6582 exec_control);
6583 if (best)
4f977045 6584 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6585 }
0e851880
SY		 6586}
6587
d4330ef2
JR		 6588static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6589{
7b8050f5
NHE		 6590 if (func == 1 && nested)
6591 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6592}
6593
fe3ef05c
NHE		 6594/*
6595 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6596 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6597 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6598 * guest in a way that will both be appropriate to L1's requests, and our
6599 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6600 * function also has additional necessary side-effects, like setting various
6601 * vcpu->arch fields.
6602 */
6603static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6604{
6605 struct vcpu_vmx *vmx = to_vmx(vcpu);
6606 u32 exec_control;
6607
6608 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6609 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6610 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6611 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6612 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6613 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6614 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6615 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6616 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6617 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6618 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6619 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6620 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6621 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6622 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6623 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6624 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6625 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6626 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6627 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6628 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6629 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6630 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6631 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6632 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6633 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6634 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6635 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6636 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6637 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6638 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6639 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6640 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6641 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6642 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6643 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6644
6645 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6646 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6647 vmcs12->vm_entry_intr_info_field);
6648 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6649 vmcs12->vm_entry_exception_error_code);
6650 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6651 vmcs12->vm_entry_instruction_len);
6652 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6653 vmcs12->guest_interruptibility_info);
6654 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6655 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6656 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6657 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6658 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6659 vmcs12->guest_pending_dbg_exceptions);
6660 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6661 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6662
6663 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6664
6665 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6666 (vmcs_config.pin_based_exec_ctrl |
6667 vmcs12->pin_based_vm_exec_control));
6668
6669 /*
6670 * Whether page-faults are trapped is determined by a combination of
6671 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6672 * If enable_ept, L0 doesn't care about page faults and we should
6673 * set all of these to L1's desires. However, if !enable_ept, L0 does
6674 * care about (at least some) page faults, and because it is not easy
6675 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6676 * to exit on each and every L2 page fault. This is done by setting
6677 * MASK=MATCH=0 and (see below) EB.PF=1.
6678 * Note that below we don't need special code to set EB.PF beyond the
6679 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6680 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6681 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6682 *
6683 * A problem with this approach (when !enable_ept) is that L1 may be
6684 * injected with more page faults than it asked for. This could have
6685 * caused problems, but in practice existing hypervisors don't care.
6686 * To fix this, we will need to emulate the PFEC checking (on the L1
6687 * page tables), using walk_addr(), when injecting PFs to L1.
6688 */
6689 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6690 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6691 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6692 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6693
6694 if (cpu_has_secondary_exec_ctrls()) {
6695 u32 exec_control = vmx_secondary_exec_control(vmx);
6696 if (!vmx->rdtscp_enabled)
6697 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6698 /* Take the following fields only from vmcs12 */
6699 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6700 if (nested_cpu_has(vmcs12,
6701 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6702 exec_control |= vmcs12->secondary_vm_exec_control;
6703
6704 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6705 /*
6706 * Translate L1 physical address to host physical
6707 * address for vmcs02. Keep the page pinned, so this
6708 * physical address remains valid. We keep a reference
6709 * to it so we can release it later.
6710 */
6711 if (vmx->nested.apic_access_page) /* shouldn't happen */
6712 nested_release_page(vmx->nested.apic_access_page);
6713 vmx->nested.apic_access_page =
6714 nested_get_page(vcpu, vmcs12->apic_access_addr);
6715 /*
6716 * If translation failed, no matter: This feature asks
6717 * to exit when accessing the given address, and if it
6718 * can never be accessed, this feature won't do
6719 * anything anyway.
6720 */
6721 if (!vmx->nested.apic_access_page)
6722 exec_control &=
6723 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6724 else
6725 vmcs_write64(APIC_ACCESS_ADDR,
6726 page_to_phys(vmx->nested.apic_access_page));
6727 }
6728
6729 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6730 }
6731
6732
6733 /*
6734 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6735 * Some constant fields are set here by vmx_set_constant_host_state().
6736 * Other fields are different per CPU, and will be set later when
6737 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6738 */
6739 vmx_set_constant_host_state();
6740
6741 /*
6742 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6743 * entry, but only if the current (host) sp changed from the value
6744 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6745 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6746 * here we just force the write to happen on entry.
6747 */
6748 vmx->host_rsp = 0;
6749
6750 exec_control = vmx_exec_control(vmx); /* L0's desires */
6751 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6752 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6753 exec_control &= ~CPU_BASED_TPR_SHADOW;
6754 exec_control |= vmcs12->cpu_based_vm_exec_control;
6755 /*
6756 * Merging of IO and MSR bitmaps not currently supported.
6757 * Rather, exit every time.
6758 */
6759 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6760 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6761 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6762
6763 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6764
6765 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6766 * bitwise-or of what L1 wants to trap for L2, and what we want to
6767 * trap. Note that CR0.TS also needs updating - we do this later.
6768 */
6769 update_exception_bitmap(vcpu);
6770 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6771 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6772
6773 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6774 vmcs_write32(VM_EXIT_CONTROLS,
6775 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6776 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6777 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6778
6779 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6780 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6781 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6782 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6783
6784
6785 set_cr4_guest_host_mask(vmx);
6786
27fc51b2
NHE		 6787 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6788 vmcs_write64(TSC_OFFSET,
6789 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6790 else
6791 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6792
6793 if (enable_vpid) {
6794 /*
6795 * Trivially support vpid by letting L2s share their parent
6796 * L1's vpid. TODO: move to a more elaborate solution, giving
6797 * each L2 its own vpid and exposing the vpid feature to L1.
6798 */
6799 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6800 vmx_flush_tlb(vcpu);
6801 }
6802
6803 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6804 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6805 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6806 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6807 else
6808 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6809 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6810 vmx_set_efer(vcpu, vcpu->arch.efer);
6811
6812 /*
6813 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6814 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6815 * The CR0_READ_SHADOW is what L2 should have expected to read given
6816 * the specifications by L1; It's not enough to take
6817 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6818 * have more bits than L1 expected.
6819 */
6820 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6821 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6822
6823 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6824 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6825
6826 /* shadow page tables on either EPT or shadow page tables */
6827 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6828 kvm_mmu_reset_context(vcpu);
6829
6830 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6831 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6832}
6833
cd232ad0
NHE		 6834/*
6835 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6836 * for running an L2 nested guest.
6837 */
6838static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6839{
6840 struct vmcs12 *vmcs12;
6841 struct vcpu_vmx *vmx = to_vmx(vcpu);
6842 int cpu;
6843 struct loaded_vmcs *vmcs02;
6844
6845 if (!nested_vmx_check_permission(vcpu) ||
6846 !nested_vmx_check_vmcs12(vcpu))
6847 return 1;
6848
6849 skip_emulated_instruction(vcpu);
6850 vmcs12 = get_vmcs12(vcpu);
6851
7c177938
NHE		 6852 /*
6853 * The nested entry process starts with enforcing various prerequisites
6854 * on vmcs12 as required by the Intel SDM, and act appropriately when
6855 * they fail: As the SDM explains, some conditions should cause the
6856 * instruction to fail, while others will cause the instruction to seem
6857 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6858 * To speed up the normal (success) code path, we should avoid checking
6859 * for misconfigurations which will anyway be caught by the processor
6860 * when using the merged vmcs02.
6861 */
6862 if (vmcs12->launch_state == launch) {
6863 nested_vmx_failValid(vcpu,
6864 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6865 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6866 return 1;
6867 }
6868
6869 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6870 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6871 /*TODO: Also verify bits beyond physical address width are 0*/
6872 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6873 return 1;
6874 }
6875
6876 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6877 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6878 /*TODO: Also verify bits beyond physical address width are 0*/
6879 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6880 return 1;
6881 }
6882
6883 if (vmcs12->vm_entry_msr_load_count > 0 ||
6884 vmcs12->vm_exit_msr_load_count > 0 ||
6885 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6886 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6887 __func__);
7c177938
NHE		 6888 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6889 return 1;
6890 }
6891
6892 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6893 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6894 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6895 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6896 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6897 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6898 !vmx_control_verify(vmcs12->vm_exit_controls,
6899 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6900 !vmx_control_verify(vmcs12->vm_entry_controls,
6901 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6902 {
6903 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6904 return 1;
6905 }
6906
6907 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6908 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6909 nested_vmx_failValid(vcpu,
6910 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6911 return 1;
6912 }
6913
6914 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6915 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6916 nested_vmx_entry_failure(vcpu, vmcs12,
6917 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6918 return 1;
6919 }
6920 if (vmcs12->vmcs_link_pointer != -1ull) {
6921 nested_vmx_entry_failure(vcpu, vmcs12,
6922 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6923 return 1;
6924 }
6925
6926 /*
6927 * We're finally done with prerequisite checking, and can start with
6928 * the nested entry.
6929 */
6930
cd232ad0
NHE		 6931 vmcs02 = nested_get_current_vmcs02(vmx);
6932 if (!vmcs02)
6933 return -ENOMEM;
6934
6935 enter_guest_mode(vcpu);
6936
6937 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6938
6939 cpu = get_cpu();
6940 vmx->loaded_vmcs = vmcs02;
6941 vmx_vcpu_put(vcpu);
6942 vmx_vcpu_load(vcpu, cpu);
6943 vcpu->cpu = cpu;
6944 put_cpu();
6945
6946 vmcs12->launch_state = 1;
6947
6948 prepare_vmcs02(vcpu, vmcs12);
6949
6950 /*
6951 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6952 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6953 * returned as far as L1 is concerned. It will only return (and set
6954 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6955 */
6956 return 1;
6957}
6958
4704d0be
NHE		 6959/*
6960 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6961 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6962 * This function returns the new value we should put in vmcs12.guest_cr0.
6963 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6964 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6965 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6966 * didn't trap the bit, because if L1 did, so would L0).
6967 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6968 * been modified by L2, and L1 knows it. So just leave the old value of
6969 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6970 * isn't relevant, because if L0 traps this bit it can set it to anything.
6971 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6972 * changed these bits, and therefore they need to be updated, but L0
6973 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6974 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6975 */
6976static inline unsigned long
6977vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6978{
6979 return
6980 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6981 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6982 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6983 vcpu->arch.cr0_guest_owned_bits));
6984}
6985
6986static inline unsigned long
6987vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6988{
6989 return
6990 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6991 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6992 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6993 vcpu->arch.cr4_guest_owned_bits));
6994}
6995
6996/*
6997 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6998 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6999 * and this function updates it to reflect the changes to the guest state while
7000 * L2 was running (and perhaps made some exits which were handled directly by L0
7001 * without going back to L1), and to reflect the exit reason.
7002 * Note that we do not have to copy here all VMCS fields, just those that
7003 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7004 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7005 * which already writes to vmcs12 directly.
7006 */
7007void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7008{
7009 /* update guest state fields: */
7010 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7011 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7012
7013 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7014 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7015 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7016 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7017
7018 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7019 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7020 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7021 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7022 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7023 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7024 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7025 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7026 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7027 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7028 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7029 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7030 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7031 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7032 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7033 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7034 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7035 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7036 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7037 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7038 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7039 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7040 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7041 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7042 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7043 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7044 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7045 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7046 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7047 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7048 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7049 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7050 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7051 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7052 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7053 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7054
7055 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7056 vmcs12->guest_interruptibility_info =
7057 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7058 vmcs12->guest_pending_dbg_exceptions =
7059 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7060
7061 /* TODO: These cannot have changed unless we have MSR bitmaps and
7062 * the relevant bit asks not to trap the change */
7063 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7064 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7065 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7066 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7067 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7068 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7069
7070 /* update exit information fields: */
7071
7072 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7073 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7074
7075 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7076 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7077 vmcs12->idt_vectoring_info_field =
7078 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7079 vmcs12->idt_vectoring_error_code =
7080 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7081 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7082 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7083
7084 /* clear vm-entry fields which are to be cleared on exit */
7085 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7086 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7087}
7088
7089/*
7090 * A part of what we need to when the nested L2 guest exits and we want to
7091 * run its L1 parent, is to reset L1's guest state to the host state specified
7092 * in vmcs12.
7093 * This function is to be called not only on normal nested exit, but also on
7094 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7095 * Failures During or After Loading Guest State").
7096 * This function should be called when the active VMCS is L1's (vmcs01).
7097 */
7098void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7099{
7100 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7101 vcpu->arch.efer = vmcs12->host_ia32_efer;
7102 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7103 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7104 else
7105 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7106 vmx_set_efer(vcpu, vcpu->arch.efer);
7107
7108 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7109 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7110 /*
7111 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7112 * actually changed, because it depends on the current state of
7113 * fpu_active (which may have changed).
7114 * Note that vmx_set_cr0 refers to efer set above.
7115 */
7116 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7117 /*
7118 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7119 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7120 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7121 */
7122 update_exception_bitmap(vcpu);
7123 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7124 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7125
7126 /*
7127 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7128 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7129 */
7130 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7131 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7132
7133 /* shadow page tables on either EPT or shadow page tables */
7134 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7135 kvm_mmu_reset_context(vcpu);
7136
7137 if (enable_vpid) {
7138 /*
7139 * Trivially support vpid by letting L2s share their parent
7140 * L1's vpid. TODO: move to a more elaborate solution, giving
7141 * each L2 its own vpid and exposing the vpid feature to L1.
7142 */
7143 vmx_flush_tlb(vcpu);
7144 }
7145
7146
7147 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7148 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7149 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7150 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7151 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7152 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7153 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7154 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7155 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7156 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7157 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7158 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7159 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7160 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7161 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7162
7163 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7164 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7165 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7166 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7167 vmcs12->host_ia32_perf_global_ctrl);
7168}
7169
7170/*
7171 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7172 * and modify vmcs12 to make it see what it would expect to see there if
7173 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7174 */
7175static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7176{
7177 struct vcpu_vmx *vmx = to_vmx(vcpu);
7178 int cpu;
7179 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7180
7181 leave_guest_mode(vcpu);
7182 prepare_vmcs12(vcpu, vmcs12);
7183
7184 cpu = get_cpu();
7185 vmx->loaded_vmcs = &vmx->vmcs01;
7186 vmx_vcpu_put(vcpu);
7187 vmx_vcpu_load(vcpu, cpu);
7188 vcpu->cpu = cpu;
7189 put_cpu();
7190
7191 /* if no vmcs02 cache requested, remove the one we used */
7192 if (VMCS02_POOL_SIZE == 0)
7193 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7194
7195 load_vmcs12_host_state(vcpu, vmcs12);
7196
27fc51b2 7197 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7198 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7199
7200 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7201 vmx->host_rsp = 0;
7202
7203 /* Unpin physical memory we referred to in vmcs02 */
7204 if (vmx->nested.apic_access_page) {
7205 nested_release_page(vmx->nested.apic_access_page);
7206 vmx->nested.apic_access_page = 0;
7207 }
7208
7209 /*
7210 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7211 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7212 * success or failure flag accordingly.
7213 */
7214 if (unlikely(vmx->fail)) {
7215 vmx->fail = 0;
7216 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7217 } else
7218 nested_vmx_succeed(vcpu);
7219}
7220
7c177938
NHE		 7221/*
7222 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7223 * 23.7 "VM-entry failures during or after loading guest state" (this also
7224 * lists the acceptable exit-reason and exit-qualification parameters).
7225 * It should only be called before L2 actually succeeded to run, and when
7226 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7227 */
7228static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7229 struct vmcs12 *vmcs12,
7230 u32 reason, unsigned long qualification)
7231{
7232 load_vmcs12_host_state(vcpu, vmcs12);
7233 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7234 vmcs12->exit_qualification = qualification;
7235 nested_vmx_succeed(vcpu);
7236}
7237
8a76d7f2
JR		 7238static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7239 struct x86_instruction_info *info,
7240 enum x86_intercept_stage stage)
7241{
7242 return X86EMUL_CONTINUE;
7243}
7244
cbdd1bea 7245static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7246 .cpu_has_kvm_support = cpu_has_kvm_support,
7247 .disabled_by_bios = vmx_disabled_by_bios,
7248 .hardware_setup = hardware_setup,
7249 .hardware_unsetup = hardware_unsetup,
002c7f7c 7250 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7251 .hardware_enable = hardware_enable,
7252 .hardware_disable = hardware_disable,
04547156 7253 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7254
7255 .vcpu_create = vmx_create_vcpu,
7256 .vcpu_free = vmx_free_vcpu,
04d2cc77 7257 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7258
04d2cc77 7259 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7260 .vcpu_load = vmx_vcpu_load,
7261 .vcpu_put = vmx_vcpu_put,
7262
c8639010 7263 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7264 .get_msr = vmx_get_msr,
7265 .set_msr = vmx_set_msr,
7266 .get_segment_base = vmx_get_segment_base,
7267 .get_segment = vmx_get_segment,
7268 .set_segment = vmx_set_segment,
2e4d2653 7269 .get_cpl = vmx_get_cpl,
6aa8b732 7270 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7271 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7272 .decache_cr3 = vmx_decache_cr3,
25c4c276 7273 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7274 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7275 .set_cr3 = vmx_set_cr3,
7276 .set_cr4 = vmx_set_cr4,
6aa8b732 7277 .set_efer = vmx_set_efer,
6aa8b732
AK		 7278 .get_idt = vmx_get_idt,
7279 .set_idt = vmx_set_idt,
7280 .get_gdt = vmx_get_gdt,
7281 .set_gdt = vmx_set_gdt,
020df079 7282 .set_dr7 = vmx_set_dr7,
5fdbf976 7283 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7284 .get_rflags = vmx_get_rflags,
7285 .set_rflags = vmx_set_rflags,
ebcbab4c 7286 .fpu_activate = vmx_fpu_activate,
02daab21 7287 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7288
7289 .tlb_flush = vmx_flush_tlb,
6aa8b732 7290
6aa8b732 7291 .run = vmx_vcpu_run,
6062d012 7292 .handle_exit = vmx_handle_exit,
6aa8b732 7293 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7294 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7295 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7296 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7297 .set_irq = vmx_inject_irq,
95ba8273 7298 .set_nmi = vmx_inject_nmi,
298101da 7299 .queue_exception = vmx_queue_exception,
b463a6f7 7300 .cancel_injection = vmx_cancel_injection,
78646121 7301 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7302 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7303 .get_nmi_mask = vmx_get_nmi_mask,
7304 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7305 .enable_nmi_window = enable_nmi_window,
7306 .enable_irq_window = enable_irq_window,
7307 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7308
cbc94022 7309 .set_tss_addr = vmx_set_tss_addr,
67253af5 7310 .get_tdp_level = get_ept_level,
4b12f0de 7311 .get_mt_mask = vmx_get_mt_mask,
229456fc 7312
586f9607 7313 .get_exit_info = vmx_get_exit_info,
586f9607 7314
17cc3935 7315 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7316
7317 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7318
7319 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7320 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7321
7322 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7323
7324 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7325
4051b188 7326 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7327 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7328 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7329 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7330 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7331 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7332
7333 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7334
7335 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7336};
7337
7338static int __init vmx_init(void)
7339{
26bb0981
AK		 7340 int r, i;
7341
7342 rdmsrl_safe(MSR_EFER, &host_efer);
7343
7344 for (i = 0; i < NR_VMX_MSR; ++i)
7345 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7346
3e7c73e9 7347 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7348 if (!vmx_io_bitmap_a)
7349 return -ENOMEM;
7350
2106a548
GC		 7351 r = -ENOMEM;
7352
3e7c73e9 7353 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7354 if (!vmx_io_bitmap_b)
fdef3ad1 7355 goto out;
fdef3ad1 7356
5897297b 7357 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7358 if (!vmx_msr_bitmap_legacy)
25c5f225 7359 goto out1;
2106a548 7360
25c5f225 7361
5897297b 7362 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7363 if (!vmx_msr_bitmap_longmode)
5897297b 7364 goto out2;
2106a548 7365
5897297b 7366
fdef3ad1
HQ		 7367 /*
7368 * Allow direct access to the PC debug port (it is often used for I/O
7369 * delays, but the vmexits simply slow things down).
7370 */
3e7c73e9
AK		 7371 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7372 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7373
3e7c73e9 7374 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7375
5897297b
AK		 7376 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7377 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7378
2384d2b3
SY		 7379 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7380
0ee75bea
AK		 7381 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7382 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7383 if (r)
5897297b 7384 goto out3;
25c5f225 7385
5897297b
AK		 7386 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7387 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7388 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7389 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7390 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7391 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7392
089d034e 7393 if (enable_ept) {
3f6d8c8a
XH		 7394 kvm_mmu_set_mask_ptes(0ull,
7395 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7396 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7397 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7398 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7399 kvm_enable_tdp();
7400 } else
7401 kvm_disable_tdp();
1439442c 7402
fdef3ad1
HQ		 7403 return 0;
7404
5897297b
AK		 7405out3:
7406 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7407out2:
5897297b 7408 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7409out1:
3e7c73e9 7410 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7411out:
3e7c73e9 7412 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7413 return r;
6aa8b732
AK		 7414}
7415
7416static void __exit vmx_exit(void)
7417{
5897297b
AK		 7418 free_page((unsigned long)vmx_msr_bitmap_legacy);
7419 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7420 free_page((unsigned long)vmx_io_bitmap_b);
7421 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7422
cb498ea2 7423 kvm_exit();
6aa8b732
AK		 7424}
7425
7426module_init(vmx_init)
7427module_exit(vmx_exit)
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