]> git.proxmox.com Git - mirror_qemu.git/blame - target-i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-i386: Loop-based feature word filtering in TCG mode
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
621626ce
EH		 266#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
267#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
268 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
269#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
270 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
271 CPUID_PSE36 | CPUID_FXSR)
272#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
273#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
274 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
275 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
276 CPUID_PAE | CPUID_SEP | CPUID_APIC)
277
278#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
279 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
280 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
281 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
282 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
283 /* partly implemented:
284 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
285 /* missing:
286 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
287#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
288 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
289 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
290 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
291 /* missing:
292 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
293 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
294 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
295 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
296 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
297 CPUID_EXT_RDRAND */
298
299#ifdef TARGET_X86_64
300#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
301#else
302#define TCG_EXT2_X86_64_FEATURES 0
303#endif
304
305#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
306 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
307 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
308 TCG_EXT2_X86_64_FEATURES)
309#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
310 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
311#define TCG_EXT4_FEATURES 0
312#define TCG_SVM_FEATURES 0
313#define TCG_KVM_FEATURES 0
314#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
315 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
316 /* missing:
317 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
318 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
319 CPUID_7_0_EBX_RDSEED */
320
321
5ef57876
EH		 322typedef struct FeatureWordInfo {
323 const char **feat_names;
04d104b6
EH		 324 uint32_t cpuid_eax; /* Input EAX for CPUID */
325 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
326 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
327 int cpuid_reg; /* output register (R_* constant) */
37ce3522 328 uint32_t tcg_features; /* Feature flags supported by TCG */
5ef57876
EH		 329} FeatureWordInfo;
330
331static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 332 [FEAT_1_EDX] = {
333 .feat_names = feature_name,
334 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 335 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 336 },
337 [FEAT_1_ECX] = {
338 .feat_names = ext_feature_name,
339 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 340 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 341 },
342 [FEAT_8000_0001_EDX] = {
343 .feat_names = ext2_feature_name,
344 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 345 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 346 },
347 [FEAT_8000_0001_ECX] = {
348 .feat_names = ext3_feature_name,
349 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 350 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 351 },
89e49c8b
EH		 352 [FEAT_C000_0001_EDX] = {
353 .feat_names = ext4_feature_name,
354 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 355 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 356 },
bffd67b0
EH		 357 [FEAT_KVM] = {
358 .feat_names = kvm_feature_name,
359 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 360 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 361 },
362 [FEAT_SVM] = {
363 .feat_names = svm_feature_name,
364 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 365 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 366 },
367 [FEAT_7_0_EBX] = {
368 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 369 .cpuid_eax = 7,
370 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
371 .cpuid_reg = R_EBX,
37ce3522 372 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 373 },
5ef57876
EH		 374};
375
8e8aba50
EH		 376typedef struct X86RegisterInfo32 {
377 /* Name of register */
378 const char *name;
379 /* QAPI enum value register */
380 X86CPURegister32 qapi_enum;
381} X86RegisterInfo32;
382
383#define REGISTER(reg) \
5d371f41 384 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 385static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 386 REGISTER(EAX),
387 REGISTER(ECX),
388 REGISTER(EDX),
389 REGISTER(EBX),
390 REGISTER(ESP),
391 REGISTER(EBP),
392 REGISTER(ESI),
393 REGISTER(EDI),
394};
395#undef REGISTER
396
2560f19f
PB		 397typedef struct ExtSaveArea {
398 uint32_t feature, bits;
399 uint32_t offset, size;
400} ExtSaveArea;
401
402static const ExtSaveArea ext_save_areas[] = {
403 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 404 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 405 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
406 .offset = 0x3c0, .size = 0x40 },
407 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 408 .offset = 0x400, .size = 0x40 },
2560f19f 409};
8e8aba50 410
8b4beddc
EH		 411const char *get_register_name_32(unsigned int reg)
412{
31ccdde2 413 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 414 return NULL;
415 }
8e8aba50 416 return x86_reg_info_32[reg].name;
8b4beddc
EH		 417}
418
c6dc6f63
AP		 419/* collects per-function cpuid data
420 */
421typedef struct model_features_t {
422 uint32_t *guest_feat;
423 uint32_t *host_feat;
bffd67b0 424 FeatureWord feat_word;
8b4beddc 425} model_features_t;
c6dc6f63 426
5fcca9ff
EH		 427/* KVM-specific features that are automatically added to all CPU models
428 * when KVM is enabled.
429 */
430static uint32_t kvm_default_features[FEATURE_WORDS] = {
431 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 432 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 433 (1 << KVM_FEATURE_CLOCKSOURCE2) |
434 (1 << KVM_FEATURE_ASYNC_PF) |
435 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 436 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 437 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 438 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 439};
dc59944b 440
136a7e9a
EH		 441/* Features that are not added by default to any CPU model when KVM is enabled.
442 */
443static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
444 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
445};
446
8fb4f821 447void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 448{
8fb4f821 449 kvm_default_features[w] &= ~features;
dc59944b
MT		 450}
451
bb44e0d1
JK		 452void host_cpuid(uint32_t function, uint32_t count,
453 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 454{
a1fd24af
AL		 455 uint32_t vec[4];
456
457#ifdef __x86_64__
458 asm volatile("cpuid"
459 : "=a"(vec[0]), "=b"(vec[1]),
460 "=c"(vec[2]), "=d"(vec[3])
461 : "0"(function), "c"(count) : "cc");
c1f41226 462#elif defined(__i386__)
a1fd24af
AL		 463 asm volatile("pusha \n\t"
464 "cpuid \n\t"
465 "mov %%eax, 0(%2) \n\t"
466 "mov %%ebx, 4(%2) \n\t"
467 "mov %%ecx, 8(%2) \n\t"
468 "mov %%edx, 12(%2) \n\t"
469 "popa"
470 : : "a"(function), "c"(count), "S"(vec)
471 : "memory", "cc");
c1f41226
EH		 472#else
473 abort();
a1fd24af
AL		 474#endif
475
bdde476a 476 if (eax)
a1fd24af 477 *eax = vec[0];
bdde476a 478 if (ebx)
a1fd24af 479 *ebx = vec[1];
bdde476a 480 if (ecx)
a1fd24af 481 *ecx = vec[2];
bdde476a 482 if (edx)
a1fd24af 483 *edx = vec[3];
bdde476a 484}
c6dc6f63
AP		 485
486#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
487
488/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
489 * a substring. ex if !NULL points to the first char after a substring,
490 * otherwise the string is assumed to sized by a terminating nul.
491 * Return lexical ordering of *s1:*s2.
492 */
493static int sstrcmp(const char *s1, const char *e1, const char *s2,
494 const char *e2)
495{
496 for (;;) {
497 if (!*s1 || !*s2 || *s1 != *s2)
498 return (*s1 - *s2);
499 ++s1, ++s2;
500 if (s1 == e1 && s2 == e2)
501 return (0);
502 else if (s1 == e1)
503 return (*s2);
504 else if (s2 == e2)
505 return (*s1);
506 }
507}
508
509/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
510 * '|' delimited (possibly empty) strings in which case search for a match
511 * within the alternatives proceeds left to right. Return 0 for success,
512 * non-zero otherwise.
513 */
514static int altcmp(const char *s, const char *e, const char *altstr)
515{
516 const char *p, *q;
517
518 for (q = p = altstr; ; ) {
519 while (*p && *p != '|')
520 ++p;
521 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
522 return (0);
523 if (!*p)
524 return (1);
525 else
526 q = ++p;
527 }
528}
529
530/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 531 * *pval and return true, otherwise return false
c6dc6f63 532 */
e41e0fc6
JK		 533static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
534 const char **featureset)
c6dc6f63
AP		 535{
536 uint32_t mask;
537 const char **ppc;
e41e0fc6 538 bool found = false;
c6dc6f63 539
e41e0fc6 540 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 541 if (*ppc && !altcmp(s, e, *ppc)) {
542 *pval |= mask;
e41e0fc6 543 found = true;
c6dc6f63 544 }
e41e0fc6
JK		 545 }
546 return found;
c6dc6f63
AP		 547}
548
5ef57876
EH		 549static void add_flagname_to_bitmaps(const char *flagname,
550 FeatureWordArray words)
c6dc6f63 551{
5ef57876
EH		 552 FeatureWord w;
553 for (w = 0; w < FEATURE_WORDS; w++) {
554 FeatureWordInfo *wi = &feature_word_info[w];
555 if (wi->feat_names &&
556 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
557 break;
558 }
559 }
560 if (w == FEATURE_WORDS) {
561 fprintf(stderr, "CPU feature %s not found\n", flagname);
562 }
c6dc6f63
AP		 563}
564
d940ee9b
EH		 565/* CPU class name definitions: */
566
567#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
568#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
569
570/* Return type name for a given CPU model name
571 * Caller is responsible for freeing the returned string.
572 */
573static char *x86_cpu_type_name(const char *model_name)
574{
575 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
576}
577
500050d1
AF		 578static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
579{
d940ee9b
EH		 580 ObjectClass *oc;
581 char *typename;
582
500050d1
AF		 583 if (cpu_model == NULL) {
584 return NULL;
585 }
586
d940ee9b
EH		 587 typename = x86_cpu_type_name(cpu_model);
588 oc = object_class_by_name(typename);
589 g_free(typename);
590 return oc;
500050d1
AF		 591}
592
d940ee9b 593struct X86CPUDefinition {
c6dc6f63
AP		 594 const char *name;
595 uint32_t level;
90e4b0c3
EH		 596 uint32_t xlevel;
597 uint32_t xlevel2;
99b88a17
IM		 598 /* vendor is zero-terminated, 12 character ASCII string */
599 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 600 int family;
601 int model;
602 int stepping;
0514ef2f 603 FeatureWordArray features;
c6dc6f63 604 char model_id[48];
787aaf57 605 bool cache_info_passthrough;
d940ee9b 606};
c6dc6f63 607
9576de75 608static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 609 {
610 .name = "qemu64",
611 .level = 4,
99b88a17 612 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 613 .family = 6,
f8e6a11a 614 .model = 6,
c6dc6f63 615 .stepping = 3,
0514ef2f 616 .features[FEAT_1_EDX] =
27861ecc 617 PPRO_FEATURES |
c6dc6f63 618 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 619 CPUID_PSE36,
0514ef2f 620 .features[FEAT_1_ECX] =
27861ecc 621 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 622 .features[FEAT_8000_0001_EDX] =
27861ecc 623 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 624 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 625 .features[FEAT_8000_0001_ECX] =
27861ecc 626 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 627 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
628 .xlevel = 0x8000000A,
c6dc6f63
AP		 629 },
630 {
631 .name = "phenom",
632 .level = 5,
99b88a17 633 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 634 .family = 16,
635 .model = 2,
636 .stepping = 3,
0514ef2f 637 .features[FEAT_1_EDX] =
27861ecc 638 PPRO_FEATURES |
c6dc6f63 639 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 640 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 641 .features[FEAT_1_ECX] =
27861ecc 642 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 643 CPUID_EXT_POPCNT,
0514ef2f 644 .features[FEAT_8000_0001_EDX] =
27861ecc 645 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 646 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
647 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 648 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 649 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
650 CPUID_EXT3_CR8LEG,
651 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
652 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 653 .features[FEAT_8000_0001_ECX] =
27861ecc 654 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 655 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 656 .features[FEAT_SVM] =
27861ecc 657 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 658 .xlevel = 0x8000001A,
659 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
660 },
661 {
662 .name = "core2duo",
663 .level = 10,
99b88a17 664 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 665 .family = 6,
666 .model = 15,
667 .stepping = 11,
0514ef2f 668 .features[FEAT_1_EDX] =
27861ecc 669 PPRO_FEATURES |
c6dc6f63 670 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 671 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
672 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 673 .features[FEAT_1_ECX] =
27861ecc 674 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 675 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
676 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 677 .features[FEAT_8000_0001_EDX] =
27861ecc 678 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 679 .features[FEAT_8000_0001_ECX] =
27861ecc 680 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 681 .xlevel = 0x80000008,
682 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
683 },
684 {
685 .name = "kvm64",
686 .level = 5,
99b88a17 687 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 688 .family = 15,
689 .model = 6,
690 .stepping = 1,
691 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 692 .features[FEAT_1_EDX] =
27861ecc 693 PPRO_FEATURES |
c6dc6f63
AP		 694 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
695 CPUID_PSE36,
696 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 697 .features[FEAT_1_ECX] =
27861ecc 698 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 699 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 700 .features[FEAT_8000_0001_EDX] =
27861ecc 701 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 702 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
703 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
704 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
705 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
706 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 707 .features[FEAT_8000_0001_ECX] =
27861ecc 708 0,
c6dc6f63
AP		 709 .xlevel = 0x80000008,
710 .model_id = "Common KVM processor"
711 },
c6dc6f63
AP		 712 {
713 .name = "qemu32",
714 .level = 4,
99b88a17 715 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 716 .family = 6,
f8e6a11a 717 .model = 6,
c6dc6f63 718 .stepping = 3,
0514ef2f 719 .features[FEAT_1_EDX] =
27861ecc 720 PPRO_FEATURES,
0514ef2f 721 .features[FEAT_1_ECX] =
27861ecc 722 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 723 .xlevel = 0x80000004,
c6dc6f63 724 },
eafaf1e5
AP		 725 {
726 .name = "kvm32",
727 .level = 5,
99b88a17 728 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 729 .family = 15,
730 .model = 6,
731 .stepping = 1,
0514ef2f 732 .features[FEAT_1_EDX] =
27861ecc 733 PPRO_FEATURES |
eafaf1e5 734 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 735 .features[FEAT_1_ECX] =
27861ecc 736 CPUID_EXT_SSE3,
0514ef2f 737 .features[FEAT_8000_0001_EDX] =
27861ecc 738 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 739 .features[FEAT_8000_0001_ECX] =
27861ecc 740 0,
eafaf1e5
AP		 741 .xlevel = 0x80000008,
742 .model_id = "Common 32-bit KVM processor"
743 },
c6dc6f63
AP		 744 {
745 .name = "coreduo",
746 .level = 10,
99b88a17 747 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 748 .family = 6,
749 .model = 14,
750 .stepping = 8,
0514ef2f 751 .features[FEAT_1_EDX] =
27861ecc 752 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 753 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
754 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 755 .features[FEAT_1_ECX] =
27861ecc 756 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 757 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 758 .features[FEAT_8000_0001_EDX] =
27861ecc 759 CPUID_EXT2_NX,
c6dc6f63
AP		 760 .xlevel = 0x80000008,
761 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
762 },
763 {
764 .name = "486",
58012d66 765 .level = 1,
99b88a17 766 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 767 .family = 4,
b2a856d9 768 .model = 8,
c6dc6f63 769 .stepping = 0,
0514ef2f 770 .features[FEAT_1_EDX] =
27861ecc 771 I486_FEATURES,
c6dc6f63
AP		 772 .xlevel = 0,
773 },
774 {
775 .name = "pentium",
776 .level = 1,
99b88a17 777 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 778 .family = 5,
779 .model = 4,
780 .stepping = 3,
0514ef2f 781 .features[FEAT_1_EDX] =
27861ecc 782 PENTIUM_FEATURES,
c6dc6f63
AP		 783 .xlevel = 0,
784 },
785 {
786 .name = "pentium2",
787 .level = 2,
99b88a17 788 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 789 .family = 6,
790 .model = 5,
791 .stepping = 2,
0514ef2f 792 .features[FEAT_1_EDX] =
27861ecc 793 PENTIUM2_FEATURES,
c6dc6f63
AP		 794 .xlevel = 0,
795 },
796 {
797 .name = "pentium3",
798 .level = 2,
99b88a17 799 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 800 .family = 6,
801 .model = 7,
802 .stepping = 3,
0514ef2f 803 .features[FEAT_1_EDX] =
27861ecc 804 PENTIUM3_FEATURES,
c6dc6f63
AP		 805 .xlevel = 0,
806 },
807 {
808 .name = "athlon",
809 .level = 2,
99b88a17 810 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 811 .family = 6,
812 .model = 2,
813 .stepping = 3,
0514ef2f 814 .features[FEAT_1_EDX] =
27861ecc 815 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 816 CPUID_MCA,
0514ef2f 817 .features[FEAT_8000_0001_EDX] =
27861ecc 818 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 819 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 820 .xlevel = 0x80000008,
c6dc6f63
AP		 821 },
822 {
823 .name = "n270",
824 /* original is on level 10 */
825 .level = 5,
99b88a17 826 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 827 .family = 6,
828 .model = 28,
829 .stepping = 2,
0514ef2f 830 .features[FEAT_1_EDX] =
27861ecc 831 PPRO_FEATURES |
8560efed
AJ		 832 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
833 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 834 /* Some CPUs got no CPUID_SEP */
0514ef2f 835 .features[FEAT_1_ECX] =
27861ecc 836 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 837 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
838 CPUID_EXT_MOVBE,
0514ef2f 839 .features[FEAT_8000_0001_EDX] =
27861ecc 840 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 841 CPUID_EXT2_NX,
0514ef2f 842 .features[FEAT_8000_0001_ECX] =
27861ecc 843 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 844 .xlevel = 0x8000000A,
845 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
846 },
3eca4642
EH		 847 {
848 .name = "Conroe",
6b11322e 849 .level = 4,
99b88a17 850 .vendor = CPUID_VENDOR_INTEL,
3eca4642 851 .family = 6,
ffce9ebb 852 .model = 15,
3eca4642 853 .stepping = 3,
0514ef2f 854 .features[FEAT_1_EDX] =
27861ecc 855 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 856 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
857 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
858 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
859 CPUID_DE | CPUID_FP87,
0514ef2f 860 .features[FEAT_1_ECX] =
27861ecc 861 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 862 .features[FEAT_8000_0001_EDX] =
27861ecc 863 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 864 .features[FEAT_8000_0001_ECX] =
27861ecc 865 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 866 .xlevel = 0x8000000A,
867 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
868 },
869 {
870 .name = "Penryn",
6b11322e 871 .level = 4,
99b88a17 872 .vendor = CPUID_VENDOR_INTEL,
3eca4642 873 .family = 6,
ffce9ebb 874 .model = 23,
3eca4642 875 .stepping = 3,
0514ef2f 876 .features[FEAT_1_EDX] =
27861ecc 877 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 878 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
879 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
880 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
881 CPUID_DE | CPUID_FP87,
0514ef2f 882 .features[FEAT_1_ECX] =
27861ecc 883 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 884 CPUID_EXT_SSE3,
0514ef2f 885 .features[FEAT_8000_0001_EDX] =
27861ecc 886 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 887 .features[FEAT_8000_0001_ECX] =
27861ecc 888 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 889 .xlevel = 0x8000000A,
890 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
891 },
892 {
893 .name = "Nehalem",
6b11322e 894 .level = 4,
99b88a17 895 .vendor = CPUID_VENDOR_INTEL,
3eca4642 896 .family = 6,
ffce9ebb 897 .model = 26,
3eca4642 898 .stepping = 3,
0514ef2f 899 .features[FEAT_1_EDX] =
27861ecc 900 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 901 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
902 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
903 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
904 CPUID_DE | CPUID_FP87,
0514ef2f 905 .features[FEAT_1_ECX] =
27861ecc 906 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 907 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 908 .features[FEAT_8000_0001_EDX] =
27861ecc 909 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 910 .features[FEAT_8000_0001_ECX] =
27861ecc 911 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 912 .xlevel = 0x8000000A,
913 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
914 },
915 {
916 .name = "Westmere",
917 .level = 11,
99b88a17 918 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 919 .family = 6,
920 .model = 44,
921 .stepping = 1,
0514ef2f 922 .features[FEAT_1_EDX] =
27861ecc 923 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
927 CPUID_DE | CPUID_FP87,
0514ef2f 928 .features[FEAT_1_ECX] =
27861ecc 929 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 930 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 931 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 932 .features[FEAT_8000_0001_EDX] =
27861ecc 933 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 934 .features[FEAT_8000_0001_ECX] =
27861ecc 935 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 936 .xlevel = 0x8000000A,
937 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
938 },
939 {
940 .name = "SandyBridge",
941 .level = 0xd,
99b88a17 942 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 943 .family = 6,
944 .model = 42,
945 .stepping = 1,
0514ef2f 946 .features[FEAT_1_EDX] =
27861ecc 947 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 948 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
949 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
950 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
951 CPUID_DE | CPUID_FP87,
0514ef2f 952 .features[FEAT_1_ECX] =
27861ecc 953 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 954 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
955 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
956 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
957 CPUID_EXT_SSE3,
0514ef2f 958 .features[FEAT_8000_0001_EDX] =
27861ecc 959 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 960 CPUID_EXT2_SYSCALL,
0514ef2f 961 .features[FEAT_8000_0001_ECX] =
27861ecc 962 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 963 .xlevel = 0x8000000A,
964 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
965 },
37507094
EH		 966 {
967 .name = "Haswell",
968 .level = 0xd,
99b88a17 969 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 970 .family = 6,
971 .model = 60,
972 .stepping = 1,
0514ef2f 973 .features[FEAT_1_EDX] =
27861ecc 974 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 975 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 976 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 977 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
978 CPUID_DE | CPUID_FP87,
0514ef2f 979 .features[FEAT_1_ECX] =
27861ecc 980 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 981 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
982 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
983 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
984 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
985 CPUID_EXT_PCID,
0514ef2f 986 .features[FEAT_8000_0001_EDX] =
27861ecc 987 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 988 CPUID_EXT2_SYSCALL,
0514ef2f 989 .features[FEAT_8000_0001_ECX] =
27861ecc 990 CPUID_EXT3_LAHF_LM,
0514ef2f 991 .features[FEAT_7_0_EBX] =
27861ecc 992 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 993 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
994 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
995 CPUID_7_0_EBX_RTM,
996 .xlevel = 0x8000000A,
997 .model_id = "Intel Core Processor (Haswell)",
998 },
3eca4642
EH		 999 {
1000 .name = "Opteron_G1",
1001 .level = 5,
99b88a17 1002 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1003 .family = 15,
1004 .model = 6,
1005 .stepping = 1,
0514ef2f 1006 .features[FEAT_1_EDX] =
27861ecc 1007 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1008 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1009 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1010 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1011 CPUID_DE | CPUID_FP87,
0514ef2f 1012 .features[FEAT_1_ECX] =
27861ecc 1013 CPUID_EXT_SSE3,
0514ef2f 1014 .features[FEAT_8000_0001_EDX] =
27861ecc 1015 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 1016 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1017 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1018 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1019 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1020 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1021 .xlevel = 0x80000008,
1022 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1023 },
1024 {
1025 .name = "Opteron_G2",
1026 .level = 5,
99b88a17 1027 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1028 .family = 15,
1029 .model = 6,
1030 .stepping = 1,
0514ef2f 1031 .features[FEAT_1_EDX] =
27861ecc 1032 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1033 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1034 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1035 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1036 CPUID_DE | CPUID_FP87,
0514ef2f 1037 .features[FEAT_1_ECX] =
27861ecc 1038 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1039 .features[FEAT_8000_0001_EDX] =
27861ecc 1040 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1041 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1042 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1043 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1044 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1045 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1046 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1047 .features[FEAT_8000_0001_ECX] =
27861ecc 1048 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1049 .xlevel = 0x80000008,
1050 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1051 },
1052 {
1053 .name = "Opteron_G3",
1054 .level = 5,
99b88a17 1055 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1056 .family = 15,
1057 .model = 6,
1058 .stepping = 1,
0514ef2f 1059 .features[FEAT_1_EDX] =
27861ecc 1060 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1061 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1062 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1063 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1064 CPUID_DE | CPUID_FP87,
0514ef2f 1065 .features[FEAT_1_ECX] =
27861ecc 1066 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1067 CPUID_EXT_SSE3,
0514ef2f 1068 .features[FEAT_8000_0001_EDX] =
27861ecc 1069 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1070 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1071 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1072 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1073 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1074 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1075 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1076 .features[FEAT_8000_0001_ECX] =
27861ecc 1077 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1078 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1079 .xlevel = 0x80000008,
1080 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1081 },
1082 {
1083 .name = "Opteron_G4",
1084 .level = 0xd,
99b88a17 1085 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1086 .family = 21,
1087 .model = 1,
1088 .stepping = 2,
0514ef2f 1089 .features[FEAT_1_EDX] =
27861ecc 1090 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1091 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1092 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1093 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1094 CPUID_DE | CPUID_FP87,
0514ef2f 1095 .features[FEAT_1_ECX] =
27861ecc 1096 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1097 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1098 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1099 CPUID_EXT_SSE3,
0514ef2f 1100 .features[FEAT_8000_0001_EDX] =
27861ecc 1101 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1102 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1103 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1104 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1105 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1106 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1107 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1108 .features[FEAT_8000_0001_ECX] =
27861ecc 1109 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1110 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1111 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1112 CPUID_EXT3_LAHF_LM,
1113 .xlevel = 0x8000001A,
1114 .model_id = "AMD Opteron 62xx class CPU",
1115 },
021941b9
AP		 1116 {
1117 .name = "Opteron_G5",
1118 .level = 0xd,
99b88a17 1119 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1120 .family = 21,
1121 .model = 2,
1122 .stepping = 0,
0514ef2f 1123 .features[FEAT_1_EDX] =
27861ecc 1124 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1125 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1126 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1127 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1128 CPUID_DE | CPUID_FP87,
0514ef2f 1129 .features[FEAT_1_ECX] =
27861ecc 1130 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1131 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1132 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1133 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1134 .features[FEAT_8000_0001_EDX] =
27861ecc 1135 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1136 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1137 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1138 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1139 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1140 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1141 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1142 .features[FEAT_8000_0001_ECX] =
27861ecc 1143 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1144 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1145 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1146 CPUID_EXT3_LAHF_LM,
1147 .xlevel = 0x8000001A,
1148 .model_id = "AMD Opteron 63xx class CPU",
1149 },
c6dc6f63
AP		 1150};
1151
0668af54
EH		 1152/**
1153 * x86_cpu_compat_set_features:
1154 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1155 * @w: Identifies the feature word to be changed.
1156 * @feat_add: Feature bits to be added to feature word
1157 * @feat_remove: Feature bits to be removed from feature word
1158 *
1159 * Change CPU model feature bits for compatibility.
1160 *
1161 * This function may be used by machine-type compatibility functions
1162 * to enable or disable feature bits on specific CPU models.
1163 */
1164void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1165 uint32_t feat_add, uint32_t feat_remove)
1166{
9576de75 1167 X86CPUDefinition *def;
0668af54
EH		 1168 int i;
1169 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1170 def = &builtin_x86_defs[i];
1171 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1172 def->features[w] |= feat_add;
1173 def->features[w] &= ~feat_remove;
1174 }
1175 }
1176}
1177
d940ee9b
EH		 1178#ifdef CONFIG_KVM
1179
c6dc6f63
AP		 1180static int cpu_x86_fill_model_id(char *str)
1181{
1182 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1183 int i;
1184
1185 for (i = 0; i < 3; i++) {
1186 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1187 memcpy(str + i * 16 + 0, &eax, 4);
1188 memcpy(str + i * 16 + 4, &ebx, 4);
1189 memcpy(str + i * 16 + 8, &ecx, 4);
1190 memcpy(str + i * 16 + 12, &edx, 4);
1191 }
1192 return 0;
1193}
1194
d940ee9b
EH		 1195static X86CPUDefinition host_cpudef;
1196
1197/* class_init for the "host" CPU model
6e746f30 1198 *
d940ee9b 1199 * This function may be called before KVM is initialized.
6e746f30 1200 */
d940ee9b 1201static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1202{
d940ee9b 1203 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1204 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1205
d940ee9b 1206 xcc->kvm_required = true;
6e746f30 1207
c6dc6f63 1208 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1209 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1210
1211 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1212 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1213 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1214 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1215
d940ee9b 1216 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1217
d940ee9b
EH		 1218 xcc->cpu_def = &host_cpudef;
1219 host_cpudef.cache_info_passthrough = true;
1220
1221 /* level, xlevel, xlevel2, and the feature words are initialized on
1222 * instance_init, because they require KVM to be initialized.
1223 */
1224}
1225
1226static void host_x86_cpu_initfn(Object *obj)
1227{
1228 X86CPU *cpu = X86_CPU(obj);
1229 CPUX86State *env = &cpu->env;
1230 KVMState *s = kvm_state;
1231 FeatureWord w;
1232
1233 assert(kvm_enabled());
1234
1235 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1236 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1237 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1238
2bc65d2b
EH		 1239 for (w = 0; w < FEATURE_WORDS; w++) {
1240 FeatureWordInfo *wi = &feature_word_info[w];
d940ee9b 1241 env->features[w] =
2bc65d2b
EH		 1242 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1243 wi->cpuid_reg);
1244 }
d940ee9b 1245 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1246}
1247
d940ee9b
EH		 1248static const TypeInfo host_x86_cpu_type_info = {
1249 .name = X86_CPU_TYPE_NAME("host"),
1250 .parent = TYPE_X86_CPU,
1251 .instance_init = host_x86_cpu_initfn,
1252 .class_init = host_x86_cpu_class_init,
1253};
1254
1255#endif
1256
8459e396 1257static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1258{
8459e396 1259 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1260 int i;
1261
857aee33 1262 for (i = 0; i < 32; ++i) {
c6dc6f63 1263 if (1 << i & mask) {
bffd67b0 1264 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc
EH		 1265 assert(reg);
1266 fprintf(stderr, "warning: host doesn't support requested feature: "
1267 "CPUID.%02XH:%s%s%s [bit %d]\n",
bffd67b0
EH		 1268 f->cpuid_eax, reg,
1269 f->feat_names[i] ? "." : "",
1270 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1271 }
857aee33 1272 }
c6dc6f63
AP		 1273}
1274
95b8519d
AF		 1275static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1276 const char *name, Error **errp)
1277{
1278 X86CPU *cpu = X86_CPU(obj);
1279 CPUX86State *env = &cpu->env;
1280 int64_t value;
1281
1282 value = (env->cpuid_version >> 8) & 0xf;
1283 if (value == 0xf) {
1284 value += (env->cpuid_version >> 20) & 0xff;
1285 }
1286 visit_type_int(v, &value, name, errp);
1287}
1288
71ad61d3
AF		 1289static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1290 const char *name, Error **errp)
ed5e1ec3 1291{
71ad61d3
AF		 1292 X86CPU *cpu = X86_CPU(obj);
1293 CPUX86State *env = &cpu->env;
1294 const int64_t min = 0;
1295 const int64_t max = 0xff + 0xf;
65cd9064 1296 Error *local_err = NULL;
71ad61d3
AF		 1297 int64_t value;
1298
65cd9064
MA		 1299 visit_type_int(v, &value, name, &local_err);
1300 if (local_err) {
1301 error_propagate(errp, local_err);
71ad61d3
AF		 1302 return;
1303 }
1304 if (value < min || value > max) {
1305 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1306 name ? name : "null", value, min, max);
1307 return;
1308 }
1309
ed5e1ec3 1310 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1311 if (value > 0x0f) {
1312 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1313 } else {
71ad61d3 1314 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1315 }
1316}
1317
67e30c83
AF		 1318static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1319 const char *name, Error **errp)
1320{
1321 X86CPU *cpu = X86_CPU(obj);
1322 CPUX86State *env = &cpu->env;
1323 int64_t value;
1324
1325 value = (env->cpuid_version >> 4) & 0xf;
1326 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1327 visit_type_int(v, &value, name, errp);
1328}
1329
c5291a4f
AF		 1330static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1331 const char *name, Error **errp)
b0704cbd 1332{
c5291a4f
AF		 1333 X86CPU *cpu = X86_CPU(obj);
1334 CPUX86State *env = &cpu->env;
1335 const int64_t min = 0;
1336 const int64_t max = 0xff;
65cd9064 1337 Error *local_err = NULL;
c5291a4f
AF		 1338 int64_t value;
1339
65cd9064
MA		 1340 visit_type_int(v, &value, name, &local_err);
1341 if (local_err) {
1342 error_propagate(errp, local_err);
c5291a4f
AF		 1343 return;
1344 }
1345 if (value < min || value > max) {
1346 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1347 name ? name : "null", value, min, max);
1348 return;
1349 }
1350
b0704cbd 1351 env->cpuid_version &= ~0xf00f0;
c5291a4f 1352 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1353}
1354
35112e41
AF		 1355static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1356 void *opaque, const char *name,
1357 Error **errp)
1358{
1359 X86CPU *cpu = X86_CPU(obj);
1360 CPUX86State *env = &cpu->env;
1361 int64_t value;
1362
1363 value = env->cpuid_version & 0xf;
1364 visit_type_int(v, &value, name, errp);
1365}
1366
036e2222
AF		 1367static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1368 void *opaque, const char *name,
1369 Error **errp)
38c3dc46 1370{
036e2222
AF		 1371 X86CPU *cpu = X86_CPU(obj);
1372 CPUX86State *env = &cpu->env;
1373 const int64_t min = 0;
1374 const int64_t max = 0xf;
65cd9064 1375 Error *local_err = NULL;
036e2222
AF		 1376 int64_t value;
1377
65cd9064
MA		 1378 visit_type_int(v, &value, name, &local_err);
1379 if (local_err) {
1380 error_propagate(errp, local_err);
036e2222
AF		 1381 return;
1382 }
1383 if (value < min || value > max) {
1384 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1385 name ? name : "null", value, min, max);
1386 return;
1387 }
1388
38c3dc46 1389 env->cpuid_version &= ~0xf;
036e2222 1390 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1391}
1392
8e1898bf
AF		 1393static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1394 const char *name, Error **errp)
1395{
1396 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1397
fa029887 1398 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1399}
1400
1401static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1402 const char *name, Error **errp)
1403{
1404 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1405
fa029887 1406 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1407}
1408
16b93aa8
AF		 1409static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1410 const char *name, Error **errp)
1411{
1412 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1413
fa029887 1414 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1415}
1416
1417static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1418 const char *name, Error **errp)
1419{
1420 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1421
fa029887 1422 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1423}
1424
d480e1af
AF		 1425static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1426{
1427 X86CPU *cpu = X86_CPU(obj);
1428 CPUX86State *env = &cpu->env;
1429 char *value;
d480e1af 1430
9df694ee 1431 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1432 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1433 env->cpuid_vendor3);
d480e1af
AF		 1434 return value;
1435}
1436
1437static void x86_cpuid_set_vendor(Object *obj, const char *value,
1438 Error **errp)
1439{
1440 X86CPU *cpu = X86_CPU(obj);
1441 CPUX86State *env = &cpu->env;
1442 int i;
1443
9df694ee 1444 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1445 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1446 "vendor", value);
1447 return;
1448 }
1449
1450 env->cpuid_vendor1 = 0;
1451 env->cpuid_vendor2 = 0;
1452 env->cpuid_vendor3 = 0;
1453 for (i = 0; i < 4; i++) {
1454 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1455 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1456 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1457 }
d480e1af
AF		 1458}
1459
63e886eb
AF		 1460static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1461{
1462 X86CPU *cpu = X86_CPU(obj);
1463 CPUX86State *env = &cpu->env;
1464 char *value;
1465 int i;
1466
1467 value = g_malloc(48 + 1);
1468 for (i = 0; i < 48; i++) {
1469 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1470 }
1471 value[48] = '\0';
1472 return value;
1473}
1474
938d4c25
AF		 1475static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1476 Error **errp)
dcce6675 1477{
938d4c25
AF		 1478 X86CPU *cpu = X86_CPU(obj);
1479 CPUX86State *env = &cpu->env;
dcce6675
AF		 1480 int c, len, i;
1481
1482 if (model_id == NULL) {
1483 model_id = "";
1484 }
1485 len = strlen(model_id);
d0a6acf4 1486 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1487 for (i = 0; i < 48; i++) {
1488 if (i >= len) {
1489 c = '\0';
1490 } else {
1491 c = (uint8_t)model_id[i];
1492 }
1493 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1494 }
1495}
1496
89e48965
AF		 1497static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1498 const char *name, Error **errp)
1499{
1500 X86CPU *cpu = X86_CPU(obj);
1501 int64_t value;
1502
1503 value = cpu->env.tsc_khz * 1000;
1504 visit_type_int(v, &value, name, errp);
1505}
1506
1507static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1508 const char *name, Error **errp)
1509{
1510 X86CPU *cpu = X86_CPU(obj);
1511 const int64_t min = 0;
2e84849a 1512 const int64_t max = INT64_MAX;
65cd9064 1513 Error *local_err = NULL;
89e48965
AF		 1514 int64_t value;
1515
65cd9064
MA		 1516 visit_type_int(v, &value, name, &local_err);
1517 if (local_err) {
1518 error_propagate(errp, local_err);
89e48965
AF		 1519 return;
1520 }
1521 if (value < min || value > max) {
1522 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1523 name ? name : "null", value, min, max);
1524 return;
1525 }
1526
1527 cpu->env.tsc_khz = value / 1000;
1528}
1529
31050930
IM		 1530static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1531 const char *name, Error **errp)
1532{
1533 X86CPU *cpu = X86_CPU(obj);
1534 int64_t value = cpu->env.cpuid_apic_id;
1535
1536 visit_type_int(v, &value, name, errp);
1537}
1538
1539static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1540 const char *name, Error **errp)
1541{
1542 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1543 DeviceState *dev = DEVICE(obj);
31050930
IM		 1544 const int64_t min = 0;
1545 const int64_t max = UINT32_MAX;
1546 Error *error = NULL;
1547 int64_t value;
1548
8d6d4980
IM		 1549 if (dev->realized) {
1550 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1551 "it was realized", name, object_get_typename(obj));
1552 return;
1553 }
1554
31050930
IM		 1555 visit_type_int(v, &value, name, &error);
1556 if (error) {
1557 error_propagate(errp, error);
1558 return;
1559 }
1560 if (value < min || value > max) {
1561 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1562 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1563 object_get_typename(obj), name, value, min, max);
1564 return;
1565 }
1566
1567 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1568 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1569 return;
1570 }
1571 cpu->env.cpuid_apic_id = value;
1572}
1573
7e5292b5 1574/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1575static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1576 const char *name, Error **errp)
1577{
7e5292b5 1578 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1579 FeatureWord w;
1580 Error *err = NULL;
1581 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1582 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1583 X86CPUFeatureWordInfoList *list = NULL;
1584
1585 for (w = 0; w < FEATURE_WORDS; w++) {
1586 FeatureWordInfo *wi = &feature_word_info[w];
1587 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1588 qwi->cpuid_input_eax = wi->cpuid_eax;
1589 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1590 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1591 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1592 qwi->features = array[w];
8e8aba50
EH		 1593
1594 /* List will be in reverse order, but order shouldn't matter */
1595 list_entries[w].next = list;
1596 list_entries[w].value = &word_infos[w];
1597 list = &list_entries[w];
1598 }
1599
1600 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1601 error_propagate(errp, err);
1602}
1603
c8f0f88e
IM		 1604static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1605 const char *name, Error **errp)
1606{
1607 X86CPU *cpu = X86_CPU(obj);
1608 int64_t value = cpu->hyperv_spinlock_attempts;
1609
1610 visit_type_int(v, &value, name, errp);
1611}
1612
1613static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1614 const char *name, Error **errp)
1615{
1616 const int64_t min = 0xFFF;
1617 const int64_t max = UINT_MAX;
1618 X86CPU *cpu = X86_CPU(obj);
1619 Error *err = NULL;
1620 int64_t value;
1621
1622 visit_type_int(v, &value, name, &err);
1623 if (err) {
1624 error_propagate(errp, err);
1625 return;
1626 }
1627
1628 if (value < min || value > max) {
1629 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1630 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1631 object_get_typename(obj), name ? name : "null",
1632 value, min, max);
1633 return;
1634 }
1635 cpu->hyperv_spinlock_attempts = value;
1636}
1637
1638static PropertyInfo qdev_prop_spinlocks = {
1639 .name = "int",
1640 .get = x86_get_hv_spinlocks,
1641 .set = x86_set_hv_spinlocks,
1642};
1643
72ac2e87
IM		 1644/* Convert all '_' in a feature string option name to '-', to make feature
1645 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1646 */
1647static inline void feat2prop(char *s)
1648{
1649 while ((s = strchr(s, '_'))) {
1650 *s = '-';
1651 }
1652}
1653
8f961357
EH		 1654/* Parse "+feature,-feature,feature=foo" CPU feature string
1655 */
94a444b2
AF		 1656static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1657 Error **errp)
8f961357 1658{
94a444b2 1659 X86CPU *cpu = X86_CPU(cs);
8f961357 1660 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1661 FeatureWord w;
8f961357 1662 /* Features to be added */
077c68c3 1663 FeatureWordArray plus_features = { 0 };
8f961357 1664 /* Features to be removed */
5ef57876 1665 FeatureWordArray minus_features = { 0 };
8f961357 1666 uint32_t numvalue;
a91987c2 1667 CPUX86State *env = &cpu->env;
94a444b2 1668 Error *local_err = NULL;
8f961357 1669
8f961357 1670 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1671
1672 while (featurestr) {
1673 char *val;
1674 if (featurestr[0] == '+') {
5ef57876 1675 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1676 } else if (featurestr[0] == '-') {
5ef57876 1677 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1678 } else if ((val = strchr(featurestr, '='))) {
1679 *val = 0; val++;
72ac2e87 1680 feat2prop(featurestr);
d024d209 1681 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1682 char *err;
a91987c2
IM		 1683 char num[32];
1684
c6dc6f63
AP		 1685 numvalue = strtoul(val, &err, 0);
1686 if (!*val || *err) {
6b1dd54b
PB		 1687 error_setg(errp, "bad numerical value %s", val);
1688 return;
c6dc6f63
AP		 1689 }
1690 if (numvalue < 0x80000000) {
94a444b2
AF		 1691 error_report("xlevel value shall always be >= 0x80000000"
1692 ", fixup will be removed in future versions");
2f7a21c4 1693 numvalue += 0x80000000;
c6dc6f63 1694 }
a91987c2 1695 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1696 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1697 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1698 int64_t tsc_freq;
1699 char *err;
a91987c2 1700 char num[32];
b862d1fe
JR		 1701
1702 tsc_freq = strtosz_suffix_unit(val, &err,
1703 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1704 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1705 error_setg(errp, "bad numerical value %s", val);
1706 return;
b862d1fe 1707 }
a91987c2 1708 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1709 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1710 &local_err);
72ac2e87 1711 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1712 char *err;
92067bf4 1713 const int min = 0xFFF;
c8f0f88e 1714 char num[32];
28f52cc0
VR		 1715 numvalue = strtoul(val, &err, 0);
1716 if (!*val || *err) {
6b1dd54b
PB		 1717 error_setg(errp, "bad numerical value %s", val);
1718 return;
28f52cc0 1719 }
92067bf4 1720 if (numvalue < min) {
94a444b2
AF		 1721 error_report("hv-spinlocks value shall always be >= 0x%x"
1722 ", fixup will be removed in future versions",
92067bf4
IM		 1723 min);
1724 numvalue = min;
1725 }
c8f0f88e 1726 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1727 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1728 } else {
94a444b2 1729 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1730 }
c6dc6f63 1731 } else {
258f5abe 1732 feat2prop(featurestr);
94a444b2 1733 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1734 }
94a444b2
AF		 1735 if (local_err) {
1736 error_propagate(errp, local_err);
6b1dd54b 1737 return;
c6dc6f63
AP		 1738 }
1739 featurestr = strtok(NULL, ",");
1740 }
e1c224b4
EH		 1741
1742 for (w = 0; w < FEATURE_WORDS; w++) {
1743 env->features[w] |= plus_features[w];
1744 env->features[w] &= ~minus_features[w];
1745 }
c6dc6f63
AP		 1746}
1747
1748/* generate a composite string into buf of all cpuid names in featureset
1749 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1750 * if flags, suppress names undefined in featureset.
1751 */
1752static void listflags(char *buf, int bufsize, uint32_t fbits,
1753 const char **featureset, uint32_t flags)
1754{
1755 const char **p = &featureset[31];
1756 char *q, *b, bit;
1757 int nc;
1758
1759 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1760 *buf = '\0';
1761 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1762 if (fbits & 1 << bit && (*p || !flags)) {
1763 if (*p)
1764 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1765 else
1766 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1767 if (bufsize <= nc) {
1768 if (b) {
1769 memcpy(b, "...", sizeof("..."));
1770 }
1771 return;
1772 }
1773 q += nc;
1774 bufsize -= nc;
1775 }
1776}
1777
e916cbf8
PM		 1778/* generate CPU information. */
1779void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1780{
9576de75 1781 X86CPUDefinition *def;
c6dc6f63 1782 char buf[256];
7fc9b714 1783 int i;
c6dc6f63 1784
7fc9b714
AF		 1785 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1786 def = &builtin_x86_defs[i];
c04321b3 1787 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1788 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1789 }
21ad7789
JK		 1790#ifdef CONFIG_KVM
1791 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1792 "KVM processor with all supported host features "
1793 "(only available in KVM mode)");
1794#endif
1795
6cdf8854 1796 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1797 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1798 FeatureWordInfo *fw = &feature_word_info[i];
1799
1800 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1801 (*cpu_fprintf)(f, " %s\n", buf);
1802 }
c6dc6f63
AP		 1803}
1804
76b64a7a 1805CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1806{
1807 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1808 X86CPUDefinition *def;
7fc9b714 1809 int i;
e3966126 1810
7fc9b714 1811 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1812 CpuDefinitionInfoList *entry;
1813 CpuDefinitionInfo *info;
1814
7fc9b714 1815 def = &builtin_x86_defs[i];
e3966126
AL		 1816 info = g_malloc0(sizeof(*info));
1817 info->name = g_strdup(def->name);
1818
1819 entry = g_malloc0(sizeof(*entry));
1820 entry->value = info;
1821 entry->next = cpu_list;
1822 cpu_list = entry;
1823 }
1824
1825 return cpu_list;
1826}
1827
27418adf
EH		 1828static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w)
1829{
1830 FeatureWordInfo *wi = &feature_word_info[w];
1831
1832 assert(kvm_enabled());
1833 return kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1834 wi->cpuid_ecx,
1835 wi->cpuid_reg);
1836}
1837
51f63aed
EH		 1838/*
1839 * Filters CPU feature words based on host availability of each feature.
1840 *
1841 * This function may be called only if KVM is enabled.
1842 *
1843 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1844 */
27418adf 1845static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 1846{
1847 CPUX86State *env = &cpu->env;
bd87d2a2 1848 FeatureWord w;
51f63aed
EH		 1849 int rv = 0;
1850
bd87d2a2 1851 for (w = 0; w < FEATURE_WORDS; w++) {
27418adf 1852 uint32_t host_feat = x86_cpu_get_supported_feature_word(w);
034acf4a
EH		 1853 uint32_t requested_features = env->features[w];
1854 env->features[w] &= host_feat;
1855 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 1856 if (cpu->filtered_features[w]) {
1857 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 1858 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 1859 }
1860 rv = 1;
1861 }
bd87d2a2 1862 }
51f63aed
EH		 1863
1864 return rv;
bc74b7db 1865}
bc74b7db 1866
d940ee9b 1867/* Load data from X86CPUDefinition
c080e30e 1868 */
d940ee9b 1869static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1870{
61dcd775 1871 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1872 const char *vendor;
1873 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 1874 FeatureWord w;
c6dc6f63 1875
2d64255b
AF		 1876 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1877 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1878 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1879 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 1880 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 1881 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1882 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 1883 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 1884 for (w = 0; w < FEATURE_WORDS; w++) {
1885 env->features[w] = def->features[w];
1886 }
82beb536 1887
9576de75 1888 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1889 if (kvm_enabled()) {
5fcca9ff
EH		 1890 FeatureWord w;
1891 for (w = 0; w < FEATURE_WORDS; w++) {
1892 env->features[w] |= kvm_default_features[w];
136a7e9a 1893 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 1894 }
82beb536 1895 }
5fcca9ff 1896
82beb536 1897 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1898
1899 /* sysenter isn't supported in compatibility mode on AMD,
1900 * syscall isn't supported in compatibility mode on Intel.
1901 * Normally we advertise the actual CPU vendor, but you can
1902 * override this using the 'vendor' property if you want to use
1903 * KVM's sysenter/syscall emulation in compatibility mode and
1904 * when doing cross vendor migration
1905 */
74f54bc4 1906 vendor = def->vendor;
7c08db30
EH		 1907 if (kvm_enabled()) {
1908 uint32_t ebx = 0, ecx = 0, edx = 0;
1909 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1910 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1911 vendor = host_vendor;
1912 }
1913
1914 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1915
c6dc6f63
AP		 1916}
1917
62fc403f
IM		 1918X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1919 Error **errp)
5c3c6a68 1920{
2d64255b 1921 X86CPU *cpu = NULL;
d940ee9b 1922 X86CPUClass *xcc;
500050d1 1923 ObjectClass *oc;
2d64255b
AF		 1924 gchar **model_pieces;
1925 char *name, *features;
5c3c6a68
AF		 1926 Error *error = NULL;
1927
2d64255b
AF		 1928 model_pieces = g_strsplit(cpu_model, ",", 2);
1929 if (!model_pieces[0]) {
1930 error_setg(&error, "Invalid/empty CPU model name");
1931 goto out;
1932 }
1933 name = model_pieces[0];
1934 features = model_pieces[1];
1935
500050d1
AF		 1936 oc = x86_cpu_class_by_name(name);
1937 if (oc == NULL) {
1938 error_setg(&error, "Unable to find CPU definition: %s", name);
1939 goto out;
1940 }
d940ee9b
EH		 1941 xcc = X86_CPU_CLASS(oc);
1942
1943 if (xcc->kvm_required && !kvm_enabled()) {
1944 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 1945 goto out;
1946 }
1947
d940ee9b
EH		 1948 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1949
62fc403f
IM		 1950#ifndef CONFIG_USER_ONLY
1951 if (icc_bridge == NULL) {
1952 error_setg(&error, "Invalid icc-bridge value");
1953 goto out;
1954 }
1955 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1956 object_unref(OBJECT(cpu));
1957#endif
5c3c6a68 1958
94a444b2 1959 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 1960 if (error) {
1961 goto out;
5c3c6a68
AF		 1962 }
1963
7f833247 1964out:
cd7b87ff
AF		 1965 if (error != NULL) {
1966 error_propagate(errp, error);
500050d1
AF		 1967 if (cpu) {
1968 object_unref(OBJECT(cpu));
1969 cpu = NULL;
1970 }
cd7b87ff 1971 }
7f833247
IM		 1972 g_strfreev(model_pieces);
1973 return cpu;
1974}
1975
1976X86CPU *cpu_x86_init(const char *cpu_model)
1977{
1978 Error *error = NULL;
1979 X86CPU *cpu;
1980
62fc403f 1981 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 1982 if (error) {
2d64255b
AF		 1983 goto out;
1984 }
1985
7f833247
IM		 1986 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1987
2d64255b 1988out:
2d64255b 1989 if (error) {
4a44d85e 1990 error_report("%s", error_get_pretty(error));
5c3c6a68 1991 error_free(error);
2d64255b
AF		 1992 if (cpu != NULL) {
1993 object_unref(OBJECT(cpu));
1994 cpu = NULL;
1995 }
5c3c6a68
AF		 1996 }
1997 return cpu;
1998}
1999
d940ee9b
EH		 2000static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2001{
2002 X86CPUDefinition *cpudef = data;
2003 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2004
2005 xcc->cpu_def = cpudef;
2006}
2007
2008static void x86_register_cpudef_type(X86CPUDefinition *def)
2009{
2010 char *typename = x86_cpu_type_name(def->name);
2011 TypeInfo ti = {
2012 .name = typename,
2013 .parent = TYPE_X86_CPU,
2014 .class_init = x86_cpu_cpudef_class_init,
2015 .class_data = def,
2016 };
2017
2018 type_register(&ti);
2019 g_free(typename);
2020}
2021
c6dc6f63 2022#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2023
0e26b7b8
BS		 2024void cpu_clear_apic_feature(CPUX86State *env)
2025{
0514ef2f 2026 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2027}
2028
c6dc6f63
AP		 2029#endif /* !CONFIG_USER_ONLY */
2030
c04321b3 2031/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2032 */
2033void x86_cpudef_setup(void)
2034{
93bfef4c
CV		 2035 int i, j;
2036 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2037
2038 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2039 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2040
2041 /* Look for specific "cpudef" models that */
09faecf2 2042 /* have the QEMU version in .model_id */
93bfef4c 2043 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2044 if (strcmp(model_with_versions[j], def->name) == 0) {
2045 pstrcpy(def->model_id, sizeof(def->model_id),
2046 "QEMU Virtual CPU version ");
2047 pstrcat(def->model_id, sizeof(def->model_id),
2048 qemu_get_version());
93bfef4c
CV		 2049 break;
2050 }
2051 }
c6dc6f63 2052 }
c6dc6f63
AP		 2053}
2054
c6dc6f63
AP		 2055static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2056 uint32_t *ecx, uint32_t *edx)
2057{
2058 *ebx = env->cpuid_vendor1;
2059 *edx = env->cpuid_vendor2;
2060 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2061}
2062
2063void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2064 uint32_t *eax, uint32_t *ebx,
2065 uint32_t *ecx, uint32_t *edx)
2066{
a60f24b5
AF		 2067 X86CPU *cpu = x86_env_get_cpu(env);
2068 CPUState *cs = CPU(cpu);
2069
c6dc6f63
AP		 2070 /* test if maximum index reached */
2071 if (index & 0x80000000) {
b3baa152
BW		 2072 if (index > env->cpuid_xlevel) {
2073 if (env->cpuid_xlevel2 > 0) {
2074 /* Handle the Centaur's CPUID instruction. */
2075 if (index > env->cpuid_xlevel2) {
2076 index = env->cpuid_xlevel2;
2077 } else if (index < 0xC0000000) {
2078 index = env->cpuid_xlevel;
2079 }
2080 } else {
57f26ae7
EH		 2081 /* Intel documentation states that invalid EAX input will
2082 * return the same information as EAX=cpuid_level
2083 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2084 */
2085 index = env->cpuid_level;
b3baa152
BW		 2086 }
2087 }
c6dc6f63
AP		 2088 } else {
2089 if (index > env->cpuid_level)
2090 index = env->cpuid_level;
2091 }
2092
2093 switch(index) {
2094 case 0:
2095 *eax = env->cpuid_level;
2096 get_cpuid_vendor(env, ebx, ecx, edx);
2097 break;
2098 case 1:
2099 *eax = env->cpuid_version;
2100 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2101 *ecx = env->features[FEAT_1_ECX];
2102 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2103 if (cs->nr_cores * cs->nr_threads > 1) {
2104 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2105 *edx |= 1 << 28; /* HTT bit */
2106 }
2107 break;
2108 case 2:
2109 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2110 if (cpu->cache_info_passthrough) {
2111 host_cpuid(index, 0, eax, ebx, ecx, edx);
2112 break;
2113 }
5e891bf8 2114 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2115 *ebx = 0;
2116 *ecx = 0;
5e891bf8
EH		 2117 *edx = (L1D_DESCRIPTOR << 16) | \
2118 (L1I_DESCRIPTOR << 8) | \
2119 (L2_DESCRIPTOR);
c6dc6f63
AP		 2120 break;
2121 case 4:
2122 /* cache info: needed for Core compatibility */
787aaf57
BC		 2123 if (cpu->cache_info_passthrough) {
2124 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2125 *eax &= ~0xFC000000;
c6dc6f63 2126 } else {
2f7a21c4 2127 *eax = 0;
76c2975a 2128 switch (count) {
c6dc6f63 2129 case 0: /* L1 dcache info */
5e891bf8
EH		 2130 *eax |= CPUID_4_TYPE_DCACHE | \
2131 CPUID_4_LEVEL(1) | \
2132 CPUID_4_SELF_INIT_LEVEL;
2133 *ebx = (L1D_LINE_SIZE - 1) | \
2134 ((L1D_PARTITIONS - 1) << 12) | \
2135 ((L1D_ASSOCIATIVITY - 1) << 22);
2136 *ecx = L1D_SETS - 1;
2137 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2138 break;
2139 case 1: /* L1 icache info */
5e891bf8
EH		 2140 *eax |= CPUID_4_TYPE_ICACHE | \
2141 CPUID_4_LEVEL(1) | \
2142 CPUID_4_SELF_INIT_LEVEL;
2143 *ebx = (L1I_LINE_SIZE - 1) | \
2144 ((L1I_PARTITIONS - 1) << 12) | \
2145 ((L1I_ASSOCIATIVITY - 1) << 22);
2146 *ecx = L1I_SETS - 1;
2147 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2148 break;
2149 case 2: /* L2 cache info */
5e891bf8
EH		 2150 *eax |= CPUID_4_TYPE_UNIFIED | \
2151 CPUID_4_LEVEL(2) | \
2152 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2153 if (cs->nr_threads > 1) {
2154 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2155 }
5e891bf8
EH		 2156 *ebx = (L2_LINE_SIZE - 1) | \
2157 ((L2_PARTITIONS - 1) << 12) | \
2158 ((L2_ASSOCIATIVITY - 1) << 22);
2159 *ecx = L2_SETS - 1;
2160 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2161 break;
2162 default: /* end of info */
2163 *eax = 0;
2164 *ebx = 0;
2165 *ecx = 0;
2166 *edx = 0;
2167 break;
76c2975a
PB		 2168 }
2169 }
2170
2171 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2172 if ((*eax & 31) && cs->nr_cores > 1) {
2173 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2174 }
2175 break;
2176 case 5:
2177 /* mwait info: needed for Core compatibility */
2178 *eax = 0; /* Smallest monitor-line size in bytes */
2179 *ebx = 0; /* Largest monitor-line size in bytes */
2180 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2181 *edx = 0;
2182 break;
2183 case 6:
2184 /* Thermal and Power Leaf */
2185 *eax = 0;
2186 *ebx = 0;
2187 *ecx = 0;
2188 *edx = 0;
2189 break;
f7911686 2190 case 7:
13526728
EH		 2191 /* Structured Extended Feature Flags Enumeration Leaf */
2192 if (count == 0) {
2193 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2194 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2195 *ecx = 0; /* Reserved */
2196 *edx = 0; /* Reserved */
f7911686
YW		 2197 } else {
2198 *eax = 0;
2199 *ebx = 0;
2200 *ecx = 0;
2201 *edx = 0;
2202 }
2203 break;
c6dc6f63
AP		 2204 case 9:
2205 /* Direct Cache Access Information Leaf */
2206 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2207 *ebx = 0;
2208 *ecx = 0;
2209 *edx = 0;
2210 break;
2211 case 0xA:
2212 /* Architectural Performance Monitoring Leaf */
9337e3b6 2213 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2214 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2215
2216 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2217 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2218 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2219 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2220 } else {
2221 *eax = 0;
2222 *ebx = 0;
2223 *ecx = 0;
2224 *edx = 0;
2225 }
c6dc6f63 2226 break;
2560f19f
PB		 2227 case 0xD: {
2228 KVMState *s = cs->kvm_state;
2229 uint64_t kvm_mask;
2230 int i;
2231
51e49430 2232 /* Processor Extended State */
2560f19f
PB		 2233 *eax = 0;
2234 *ebx = 0;
2235 *ecx = 0;
2236 *edx = 0;
2237 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2238 break;
2239 }
2560f19f
PB		 2240 kvm_mask =
2241 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2242 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2243
2560f19f
PB		 2244 if (count == 0) {
2245 *ecx = 0x240;
2246 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2247 const ExtSaveArea *esa = &ext_save_areas[i];
2248 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2249 (kvm_mask & (1 << i)) != 0) {
2250 if (i < 32) {
2251 *eax |= 1 << i;
2252 } else {
2253 *edx |= 1 << (i - 32);
2254 }
2255 *ecx = MAX(*ecx, esa->offset + esa->size);
2256 }
2257 }
2258 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2259 *ebx = *ecx;
2260 } else if (count == 1) {
2261 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2262 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2263 const ExtSaveArea *esa = &ext_save_areas[count];
2264 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2265 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2266 *eax = esa->size;
2267 *ebx = esa->offset;
2560f19f 2268 }
51e49430
SY		 2269 }
2270 break;
2560f19f 2271 }
c6dc6f63
AP		 2272 case 0x80000000:
2273 *eax = env->cpuid_xlevel;
2274 *ebx = env->cpuid_vendor1;
2275 *edx = env->cpuid_vendor2;
2276 *ecx = env->cpuid_vendor3;
2277 break;
2278 case 0x80000001:
2279 *eax = env->cpuid_version;
2280 *ebx = 0;
0514ef2f
EH		 2281 *ecx = env->features[FEAT_8000_0001_ECX];
2282 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2283
2284 /* The Linux kernel checks for the CMPLegacy bit and
2285 * discards multiple thread information if it is set.
2286 * So dont set it here for Intel to make Linux guests happy.
2287 */
ce3960eb 2288 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2289 uint32_t tebx, tecx, tedx;
2290 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2291 if (tebx != CPUID_VENDOR_INTEL_1 ||
2292 tedx != CPUID_VENDOR_INTEL_2 ||
2293 tecx != CPUID_VENDOR_INTEL_3) {
2294 *ecx |= 1 << 1; /* CmpLegacy bit */
2295 }
2296 }
c6dc6f63
AP		 2297 break;
2298 case 0x80000002:
2299 case 0x80000003:
2300 case 0x80000004:
2301 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2302 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2303 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2304 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2305 break;
2306 case 0x80000005:
2307 /* cache info (L1 cache) */
787aaf57
BC		 2308 if (cpu->cache_info_passthrough) {
2309 host_cpuid(index, 0, eax, ebx, ecx, edx);
2310 break;
2311 }
5e891bf8
EH		 2312 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2313 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2314 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2315 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2316 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2317 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2318 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2319 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2320 break;
2321 case 0x80000006:
2322 /* cache info (L2 cache) */
787aaf57
BC		 2323 if (cpu->cache_info_passthrough) {
2324 host_cpuid(index, 0, eax, ebx, ecx, edx);
2325 break;
2326 }
5e891bf8
EH		 2327 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2328 (L2_DTLB_2M_ENTRIES << 16) | \
2329 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2330 (L2_ITLB_2M_ENTRIES);
2331 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2332 (L2_DTLB_4K_ENTRIES << 16) | \
2333 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2334 (L2_ITLB_4K_ENTRIES);
2335 *ecx = (L2_SIZE_KB_AMD << 16) | \
2336 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2337 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2338 *edx = ((L3_SIZE_KB/512) << 18) | \
2339 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2340 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2341 break;
2342 case 0x80000008:
2343 /* virtual & phys address size in low 2 bytes. */
2344/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2345 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2346 /* 64 bit processor */
2347/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2348 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2349 } else {
0514ef2f 2350 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2351 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2352 } else {
c6dc6f63 2353 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2354 }
c6dc6f63
AP		 2355 }
2356 *ebx = 0;
2357 *ecx = 0;
2358 *edx = 0;
ce3960eb
AF		 2359 if (cs->nr_cores * cs->nr_threads > 1) {
2360 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2361 }
2362 break;
2363 case 0x8000000A:
0514ef2f 2364 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2365 *eax = 0x00000001; /* SVM Revision */
2366 *ebx = 0x00000010; /* nr of ASIDs */
2367 *ecx = 0;
0514ef2f 2368 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2369 } else {
2370 *eax = 0;
2371 *ebx = 0;
2372 *ecx = 0;
2373 *edx = 0;
2374 }
c6dc6f63 2375 break;
b3baa152
BW		 2376 case 0xC0000000:
2377 *eax = env->cpuid_xlevel2;
2378 *ebx = 0;
2379 *ecx = 0;
2380 *edx = 0;
2381 break;
2382 case 0xC0000001:
2383 /* Support for VIA CPU's CPUID instruction */
2384 *eax = env->cpuid_version;
2385 *ebx = 0;
2386 *ecx = 0;
0514ef2f 2387 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2388 break;
2389 case 0xC0000002:
2390 case 0xC0000003:
2391 case 0xC0000004:
2392 /* Reserved for the future, and now filled with zero */
2393 *eax = 0;
2394 *ebx = 0;
2395 *ecx = 0;
2396 *edx = 0;
2397 break;
c6dc6f63
AP		 2398 default:
2399 /* reserved values: zero */
2400 *eax = 0;
2401 *ebx = 0;
2402 *ecx = 0;
2403 *edx = 0;
2404 break;
2405 }
2406}
5fd2087a
AF		 2407
2408/* CPUClass::reset() */
2409static void x86_cpu_reset(CPUState *s)
2410{
2411 X86CPU *cpu = X86_CPU(s);
2412 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2413 CPUX86State *env = &cpu->env;
c1958aea
AF		 2414 int i;
2415
5fd2087a
AF		 2416 xcc->parent_reset(s);
2417
43175fa9 2418 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2419
00c8cb0a 2420 tlb_flush(s, 1);
c1958aea
AF		 2421
2422 env->old_exception = -1;
2423
2424 /* init to reset state */
2425
2426#ifdef CONFIG_SOFTMMU
2427 env->hflags |= HF_SOFTMMU_MASK;
2428#endif
2429 env->hflags2 |= HF2_GIF_MASK;
2430
2431 cpu_x86_update_cr0(env, 0x60000010);
2432 env->a20_mask = ~0x0;
2433 env->smbase = 0x30000;
2434
2435 env->idt.limit = 0xffff;
2436 env->gdt.limit = 0xffff;
2437 env->ldt.limit = 0xffff;
2438 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2439 env->tr.limit = 0xffff;
2440 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2441
2442 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2443 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2444 DESC_R_MASK | DESC_A_MASK);
2445 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2446 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2447 DESC_A_MASK);
2448 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2449 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450 DESC_A_MASK);
2451 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2452 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453 DESC_A_MASK);
2454 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2455 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456 DESC_A_MASK);
2457 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2458 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2459 DESC_A_MASK);
2460
2461 env->eip = 0xfff0;
2462 env->regs[R_EDX] = env->cpuid_version;
2463
2464 env->eflags = 0x2;
2465
2466 /* FPU init */
2467 for (i = 0; i < 8; i++) {
2468 env->fptags[i] = 1;
2469 }
2470 env->fpuc = 0x37f;
2471
2472 env->mxcsr = 0x1f80;
c74f41bb 2473 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2474
2475 env->pat = 0x0007040600070406ULL;
2476 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2477
2478 memset(env->dr, 0, sizeof(env->dr));
2479 env->dr[6] = DR6_FIXED_1;
2480 env->dr[7] = DR7_FIXED_1;
b3310ab3 2481 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2482 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2483
05e7e819 2484 env->xcr0 = 1;
0522604b 2485
dd673288
IM		 2486#if !defined(CONFIG_USER_ONLY)
2487 /* We hard-wire the BSP to the first CPU. */
55e5c285 2488 if (s->cpu_index == 0) {
02e51483 2489 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2490 }
2491
259186a7 2492 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2493
2494 if (kvm_enabled()) {
2495 kvm_arch_reset_vcpu(cpu);
2496 }
dd673288 2497#endif
5fd2087a
AF		 2498}
2499
dd673288
IM		 2500#ifndef CONFIG_USER_ONLY
2501bool cpu_is_bsp(X86CPU *cpu)
2502{
02e51483 2503 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2504}
65dee380
IM		 2505
2506/* TODO: remove me, when reset over QOM tree is implemented */
2507static void x86_cpu_machine_reset_cb(void *opaque)
2508{
2509 X86CPU *cpu = opaque;
2510 cpu_reset(CPU(cpu));
2511}
dd673288
IM		 2512#endif
2513
de024815
AF		 2514static void mce_init(X86CPU *cpu)
2515{
2516 CPUX86State *cenv = &cpu->env;
2517 unsigned int bank;
2518
2519 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2520 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2521 (CPUID_MCE | CPUID_MCA)) {
2522 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2523 cenv->mcg_ctl = ~(uint64_t)0;
2524 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2525 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2526 }
2527 }
2528}
2529
bdeec802 2530#ifndef CONFIG_USER_ONLY
d3c64d6a 2531static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2532{
bdeec802 2533 CPUX86State *env = &cpu->env;
53a89e26 2534 DeviceState *dev = DEVICE(cpu);
449994eb 2535 APICCommonState *apic;
bdeec802
IM		 2536 const char *apic_type = "apic";
2537
2538 if (kvm_irqchip_in_kernel()) {
2539 apic_type = "kvm-apic";
2540 } else if (xen_enabled()) {
2541 apic_type = "xen-apic";
2542 }
2543
02e51483
CF		 2544 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2545 if (cpu->apic_state == NULL) {
bdeec802
IM		 2546 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2547 return;
2548 }
2549
2550 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2551 OBJECT(cpu->apic_state), NULL);
2552 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2553 /* TODO: convert to link<> */
02e51483 2554 apic = APIC_COMMON(cpu->apic_state);
60671e58 2555 apic->cpu = cpu;
d3c64d6a
IM		 2556}
2557
2558static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2559{
02e51483 2560 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2561 return;
2562 }
bdeec802 2563
02e51483 2564 if (qdev_init(cpu->apic_state)) {
bdeec802 2565 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2566 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2567 return;
2568 }
bdeec802 2569}
d3c64d6a
IM		 2570#else
2571static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2572{
2573}
bdeec802
IM		 2574#endif
2575
2b6f294c 2576static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2577{
14a10fc3 2578 CPUState *cs = CPU(dev);
2b6f294c
AF		 2579 X86CPU *cpu = X86_CPU(dev);
2580 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2581 CPUX86State *env = &cpu->env;
2b6f294c 2582 Error *local_err = NULL;
b34d12d1 2583
0514ef2f 2584 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2585 env->cpuid_level = 7;
2586 }
7a059953 2587
9b15cd9e
IM		 2588 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2589 * CPUID[1].EDX.
2590 */
2591 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2592 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2593 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2594 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2595 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2596 & CPUID_EXT2_AMD_ALIASES);
2597 }
2598
4586f157 2599 if (!kvm_enabled()) {
37ce3522
EH		 2600 FeatureWord w;
2601 for (w = 0; w < FEATURE_WORDS; w++) {
2602 env->features[w] &= feature_word_info[w].tcg_features;
2603 }
4586f157 2604 } else {
27418adf 2605 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
4dc1f449
IM		 2606 error_setg(&local_err,
2607 "Host's CPU doesn't support requested features");
2608 goto out;
5ec01c2e 2609 }
4586f157
IM		 2610 }
2611
65dee380
IM		 2612#ifndef CONFIG_USER_ONLY
2613 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2614
0514ef2f 2615 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2616 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2617 if (local_err != NULL) {
4dc1f449 2618 goto out;
bdeec802
IM		 2619 }
2620 }
65dee380
IM		 2621#endif
2622
7a059953 2623 mce_init(cpu);
14a10fc3 2624 qemu_init_vcpu(cs);
d3c64d6a
IM		 2625
2626 x86_cpu_apic_realize(cpu, &local_err);
2627 if (local_err != NULL) {
2628 goto out;
2629 }
14a10fc3 2630 cpu_reset(cs);
2b6f294c 2631
4dc1f449
IM		 2632 xcc->parent_realize(dev, &local_err);
2633out:
2634 if (local_err != NULL) {
2635 error_propagate(errp, local_err);
2636 return;
2637 }
7a059953
AF		 2638}
2639
8932cfdf
EH		 2640/* Enables contiguous-apic-ID mode, for compatibility */
2641static bool compat_apic_id_mode;
2642
2643void enable_compat_apic_id_mode(void)
2644{
2645 compat_apic_id_mode = true;
2646}
2647
cb41bad3
EH		 2648/* Calculates initial APIC ID for a specific CPU index
2649 *
2650 * Currently we need to be able to calculate the APIC ID from the CPU index
2651 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2652 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2653 * all CPUs up to max_cpus.
2654 */
2655uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2656{
8932cfdf
EH		 2657 uint32_t correct_id;
2658 static bool warned;
2659
2660 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2661 if (compat_apic_id_mode) {
2662 if (cpu_index != correct_id && !warned) {
2663 error_report("APIC IDs set in compatibility mode, "
2664 "CPU topology won't match the configuration");
2665 warned = true;
2666 }
2667 return cpu_index;
2668 } else {
2669 return correct_id;
2670 }
cb41bad3
EH		 2671}
2672
de024815
AF		 2673static void x86_cpu_initfn(Object *obj)
2674{
55e5c285 2675 CPUState *cs = CPU(obj);
de024815 2676 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2677 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2678 CPUX86State *env = &cpu->env;
d65e9815 2679 static int inited;
de024815 2680
c05efcb1 2681 cs->env_ptr = env;
de024815 2682 cpu_exec_init(env);
71ad61d3
AF		 2683
2684 object_property_add(obj, "family", "int",
95b8519d 2685 x86_cpuid_version_get_family,
71ad61d3 2686 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2687 object_property_add(obj, "model", "int",
67e30c83 2688 x86_cpuid_version_get_model,
c5291a4f 2689 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2690 object_property_add(obj, "stepping", "int",
35112e41 2691 x86_cpuid_version_get_stepping,
036e2222 2692 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2693 object_property_add(obj, "level", "int",
2694 x86_cpuid_get_level,
2695 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2696 object_property_add(obj, "xlevel", "int",
2697 x86_cpuid_get_xlevel,
2698 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2699 object_property_add_str(obj, "vendor",
2700 x86_cpuid_get_vendor,
2701 x86_cpuid_set_vendor, NULL);
938d4c25 2702 object_property_add_str(obj, "model-id",
63e886eb 2703 x86_cpuid_get_model_id,
938d4c25 2704 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2705 object_property_add(obj, "tsc-frequency", "int",
2706 x86_cpuid_get_tsc_freq,
2707 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2708 object_property_add(obj, "apic-id", "int",
2709 x86_cpuid_get_apic_id,
2710 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2711 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2712 x86_cpu_get_feature_words,
7e5292b5
EH		 2713 NULL, NULL, (void *)env->features, NULL);
2714 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2715 x86_cpu_get_feature_words,
2716 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2717
92067bf4 2718 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2719 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2720
d940ee9b
EH		 2721 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2722
d65e9815
IM		 2723 /* init various static tables used in TCG mode */
2724 if (tcg_enabled() && !inited) {
2725 inited = 1;
2726 optimize_flags_init();
2727#ifndef CONFIG_USER_ONLY
2728 cpu_set_debug_excp_handler(breakpoint_handler);
2729#endif
2730 }
de024815
AF		 2731}
2732
997395d3
IM		 2733static int64_t x86_cpu_get_arch_id(CPUState *cs)
2734{
2735 X86CPU *cpu = X86_CPU(cs);
2736 CPUX86State *env = &cpu->env;
2737
2738 return env->cpuid_apic_id;
2739}
2740
444d5590
AF		 2741static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2742{
2743 X86CPU *cpu = X86_CPU(cs);
2744
2745 return cpu->env.cr[0] & CR0_PG_MASK;
2746}
2747
f45748f1
AF		 2748static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2749{
2750 X86CPU *cpu = X86_CPU(cs);
2751
2752 cpu->env.eip = value;
2753}
2754
bdf7ae5b
AF		 2755static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2756{
2757 X86CPU *cpu = X86_CPU(cs);
2758
2759 cpu->env.eip = tb->pc - tb->cs_base;
2760}
2761
8c2e1b00
AF		 2762static bool x86_cpu_has_work(CPUState *cs)
2763{
2764 X86CPU *cpu = X86_CPU(cs);
2765 CPUX86State *env = &cpu->env;
2766
2767 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2768 CPU_INTERRUPT_POLL)) &&
2769 (env->eflags & IF_MASK)) ||
2770 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2771 CPU_INTERRUPT_INIT |
2772 CPU_INTERRUPT_SIPI |
2773 CPU_INTERRUPT_MCE));
2774}
2775
9337e3b6
EH		 2776static Property x86_cpu_properties[] = {
2777 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2778 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2779 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2780 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2781 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2782 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2783 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2784 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2785 DEFINE_PROP_END_OF_LIST()
2786};
2787
5fd2087a
AF		 2788static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2789{
2790 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2791 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2792 DeviceClass *dc = DEVICE_CLASS(oc);
2793
2794 xcc->parent_realize = dc->realize;
2795 dc->realize = x86_cpu_realizefn;
62fc403f 2796 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2797 dc->props = x86_cpu_properties;
5fd2087a
AF		 2798
2799 xcc->parent_reset = cc->reset;
2800 cc->reset = x86_cpu_reset;
91b1df8c 2801 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2802
500050d1 2803 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2804 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2805 cc->has_work = x86_cpu_has_work;
97a8ea5a 2806 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2807 cc->dump_state = x86_cpu_dump_state;
f45748f1 2808 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2809 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2810 cc->gdb_read_register = x86_cpu_gdb_read_register;
2811 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2812 cc->get_arch_id = x86_cpu_get_arch_id;
2813 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2814#ifdef CONFIG_USER_ONLY
2815 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2816#else
a23bbfda 2817 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2818 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2819 cc->write_elf64_note = x86_cpu_write_elf64_note;
2820 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2821 cc->write_elf32_note = x86_cpu_write_elf32_note;
2822 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2823 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2824#endif
a0e372f0 2825 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2826}
2827
2828static const TypeInfo x86_cpu_type_info = {
2829 .name = TYPE_X86_CPU,
2830 .parent = TYPE_CPU,
2831 .instance_size = sizeof(X86CPU),
de024815 2832 .instance_init = x86_cpu_initfn,
d940ee9b 2833 .abstract = true,
5fd2087a
AF		 2834 .class_size = sizeof(X86CPUClass),
2835 .class_init = x86_cpu_common_class_init,
2836};
2837
2838static void x86_cpu_register_types(void)
2839{
d940ee9b
EH		 2840 int i;
2841
5fd2087a 2842 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2843 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2844 x86_register_cpudef_type(&builtin_x86_defs[i]);
2845 }
2846#ifdef CONFIG_KVM
2847 type_register_static(&host_x86_cpu_type_info);
2848#endif
5fd2087a
AF		 2849}
2850
2851type_init(x86_cpu_register_types)
QEMU mirror