]> git.proxmox.com Git - mirror_qemu.git/blame - target-i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-i386: Add "migratable" property to "host" CPU model
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
621626ce
EH		 266#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
267#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
268 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
269#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
270 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
271 CPUID_PSE36 | CPUID_FXSR)
272#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
273#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
274 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
275 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
276 CPUID_PAE | CPUID_SEP | CPUID_APIC)
277
278#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
279 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
280 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
281 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
282 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
283 /* partly implemented:
284 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
285 /* missing:
286 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
287#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
288 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
289 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
290 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
291 /* missing:
292 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
293 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
294 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
295 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
296 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
297 CPUID_EXT_RDRAND */
298
299#ifdef TARGET_X86_64
300#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
301#else
302#define TCG_EXT2_X86_64_FEATURES 0
303#endif
304
305#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
306 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
307 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
308 TCG_EXT2_X86_64_FEATURES)
309#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
310 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
311#define TCG_EXT4_FEATURES 0
312#define TCG_SVM_FEATURES 0
313#define TCG_KVM_FEATURES 0
314#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
315 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
316 /* missing:
317 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
318 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
319 CPUID_7_0_EBX_RDSEED */
320
321
5ef57876
EH		 322typedef struct FeatureWordInfo {
323 const char **feat_names;
04d104b6
EH		 324 uint32_t cpuid_eax; /* Input EAX for CPUID */
325 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
326 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
327 int cpuid_reg; /* output register (R_* constant) */
37ce3522 328 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 329 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 330} FeatureWordInfo;
331
332static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 333 [FEAT_1_EDX] = {
334 .feat_names = feature_name,
335 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 336 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 337 },
338 [FEAT_1_ECX] = {
339 .feat_names = ext_feature_name,
340 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 341 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 342 },
343 [FEAT_8000_0001_EDX] = {
344 .feat_names = ext2_feature_name,
345 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 346 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 347 },
348 [FEAT_8000_0001_ECX] = {
349 .feat_names = ext3_feature_name,
350 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 351 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 352 },
89e49c8b
EH		 353 [FEAT_C000_0001_EDX] = {
354 .feat_names = ext4_feature_name,
355 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 356 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 357 },
bffd67b0
EH		 358 [FEAT_KVM] = {
359 .feat_names = kvm_feature_name,
360 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 361 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 362 },
363 [FEAT_SVM] = {
364 .feat_names = svm_feature_name,
365 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 366 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 367 },
368 [FEAT_7_0_EBX] = {
369 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 370 .cpuid_eax = 7,
371 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
372 .cpuid_reg = R_EBX,
37ce3522 373 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 374 },
5ef57876
EH		 375};
376
8e8aba50
EH		 377typedef struct X86RegisterInfo32 {
378 /* Name of register */
379 const char *name;
380 /* QAPI enum value register */
381 X86CPURegister32 qapi_enum;
382} X86RegisterInfo32;
383
384#define REGISTER(reg) \
5d371f41 385 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 386static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 387 REGISTER(EAX),
388 REGISTER(ECX),
389 REGISTER(EDX),
390 REGISTER(EBX),
391 REGISTER(ESP),
392 REGISTER(EBP),
393 REGISTER(ESI),
394 REGISTER(EDI),
395};
396#undef REGISTER
397
2560f19f
PB		 398typedef struct ExtSaveArea {
399 uint32_t feature, bits;
400 uint32_t offset, size;
401} ExtSaveArea;
402
403static const ExtSaveArea ext_save_areas[] = {
404 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 405 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 406 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
407 .offset = 0x3c0, .size = 0x40 },
408 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 409 .offset = 0x400, .size = 0x40 },
2560f19f 410};
8e8aba50 411
8b4beddc
EH		 412const char *get_register_name_32(unsigned int reg)
413{
31ccdde2 414 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 415 return NULL;
416 }
8e8aba50 417 return x86_reg_info_32[reg].name;
8b4beddc
EH		 418}
419
c6dc6f63
AP		 420/* collects per-function cpuid data
421 */
422typedef struct model_features_t {
423 uint32_t *guest_feat;
424 uint32_t *host_feat;
bffd67b0 425 FeatureWord feat_word;
8b4beddc 426} model_features_t;
c6dc6f63 427
5fcca9ff
EH		 428/* KVM-specific features that are automatically added to all CPU models
429 * when KVM is enabled.
430 */
431static uint32_t kvm_default_features[FEATURE_WORDS] = {
432 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 433 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 434 (1 << KVM_FEATURE_CLOCKSOURCE2) |
435 (1 << KVM_FEATURE_ASYNC_PF) |
436 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 437 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 438 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 439 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 440};
dc59944b 441
136a7e9a
EH		 442/* Features that are not added by default to any CPU model when KVM is enabled.
443 */
444static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
445 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
446};
447
8fb4f821 448void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 449{
8fb4f821 450 kvm_default_features[w] &= ~features;
dc59944b
MT		 451}
452
84f1b92f
EH		 453/*
454 * Returns the set of feature flags that are supported and migratable by
455 * QEMU, for a given FeatureWord.
456 */
457static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
458{
459 FeatureWordInfo *wi = &feature_word_info[w];
460 uint32_t r = 0;
461 int i;
462
463 for (i = 0; i < 32; i++) {
464 uint32_t f = 1U << i;
465 /* If the feature name is unknown, it is not supported by QEMU yet */
466 if (!wi->feat_names[i]) {
467 continue;
468 }
469 /* Skip features known to QEMU, but explicitly marked as unmigratable */
470 if (wi->unmigratable_flags & f) {
471 continue;
472 }
473 r |= f;
474 }
475 return r;
476}
477
bb44e0d1
JK		 478void host_cpuid(uint32_t function, uint32_t count,
479 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 480{
a1fd24af
AL		 481 uint32_t vec[4];
482
483#ifdef __x86_64__
484 asm volatile("cpuid"
485 : "=a"(vec[0]), "=b"(vec[1]),
486 "=c"(vec[2]), "=d"(vec[3])
487 : "0"(function), "c"(count) : "cc");
c1f41226 488#elif defined(__i386__)
a1fd24af
AL		 489 asm volatile("pusha \n\t"
490 "cpuid \n\t"
491 "mov %%eax, 0(%2) \n\t"
492 "mov %%ebx, 4(%2) \n\t"
493 "mov %%ecx, 8(%2) \n\t"
494 "mov %%edx, 12(%2) \n\t"
495 "popa"
496 : : "a"(function), "c"(count), "S"(vec)
497 : "memory", "cc");
c1f41226
EH		 498#else
499 abort();
a1fd24af
AL		 500#endif
501
bdde476a 502 if (eax)
a1fd24af 503 *eax = vec[0];
bdde476a 504 if (ebx)
a1fd24af 505 *ebx = vec[1];
bdde476a 506 if (ecx)
a1fd24af 507 *ecx = vec[2];
bdde476a 508 if (edx)
a1fd24af 509 *edx = vec[3];
bdde476a 510}
c6dc6f63
AP		 511
512#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
513
514/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
515 * a substring. ex if !NULL points to the first char after a substring,
516 * otherwise the string is assumed to sized by a terminating nul.
517 * Return lexical ordering of *s1:*s2.
518 */
519static int sstrcmp(const char *s1, const char *e1, const char *s2,
520 const char *e2)
521{
522 for (;;) {
523 if (!*s1 || !*s2 || *s1 != *s2)
524 return (*s1 - *s2);
525 ++s1, ++s2;
526 if (s1 == e1 && s2 == e2)
527 return (0);
528 else if (s1 == e1)
529 return (*s2);
530 else if (s2 == e2)
531 return (*s1);
532 }
533}
534
535/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
536 * '|' delimited (possibly empty) strings in which case search for a match
537 * within the alternatives proceeds left to right. Return 0 for success,
538 * non-zero otherwise.
539 */
540static int altcmp(const char *s, const char *e, const char *altstr)
541{
542 const char *p, *q;
543
544 for (q = p = altstr; ; ) {
545 while (*p && *p != '|')
546 ++p;
547 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
548 return (0);
549 if (!*p)
550 return (1);
551 else
552 q = ++p;
553 }
554}
555
556/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 557 * *pval and return true, otherwise return false
c6dc6f63 558 */
e41e0fc6
JK		 559static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
560 const char **featureset)
c6dc6f63
AP		 561{
562 uint32_t mask;
563 const char **ppc;
e41e0fc6 564 bool found = false;
c6dc6f63 565
e41e0fc6 566 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 567 if (*ppc && !altcmp(s, e, *ppc)) {
568 *pval |= mask;
e41e0fc6 569 found = true;
c6dc6f63 570 }
e41e0fc6
JK		 571 }
572 return found;
c6dc6f63
AP		 573}
574
5ef57876
EH		 575static void add_flagname_to_bitmaps(const char *flagname,
576 FeatureWordArray words)
c6dc6f63 577{
5ef57876
EH		 578 FeatureWord w;
579 for (w = 0; w < FEATURE_WORDS; w++) {
580 FeatureWordInfo *wi = &feature_word_info[w];
581 if (wi->feat_names &&
582 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
583 break;
584 }
585 }
586 if (w == FEATURE_WORDS) {
587 fprintf(stderr, "CPU feature %s not found\n", flagname);
588 }
c6dc6f63
AP		 589}
590
d940ee9b
EH		 591/* CPU class name definitions: */
592
593#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
594#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
595
596/* Return type name for a given CPU model name
597 * Caller is responsible for freeing the returned string.
598 */
599static char *x86_cpu_type_name(const char *model_name)
600{
601 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
602}
603
500050d1
AF		 604static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
605{
d940ee9b
EH		 606 ObjectClass *oc;
607 char *typename;
608
500050d1
AF		 609 if (cpu_model == NULL) {
610 return NULL;
611 }
612
d940ee9b
EH		 613 typename = x86_cpu_type_name(cpu_model);
614 oc = object_class_by_name(typename);
615 g_free(typename);
616 return oc;
500050d1
AF		 617}
618
d940ee9b 619struct X86CPUDefinition {
c6dc6f63
AP		 620 const char *name;
621 uint32_t level;
90e4b0c3
EH		 622 uint32_t xlevel;
623 uint32_t xlevel2;
99b88a17
IM		 624 /* vendor is zero-terminated, 12 character ASCII string */
625 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 626 int family;
627 int model;
628 int stepping;
0514ef2f 629 FeatureWordArray features;
c6dc6f63 630 char model_id[48];
787aaf57 631 bool cache_info_passthrough;
d940ee9b 632};
c6dc6f63 633
9576de75 634static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 635 {
636 .name = "qemu64",
637 .level = 4,
99b88a17 638 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 639 .family = 6,
f8e6a11a 640 .model = 6,
c6dc6f63 641 .stepping = 3,
0514ef2f 642 .features[FEAT_1_EDX] =
27861ecc 643 PPRO_FEATURES |
c6dc6f63 644 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 645 CPUID_PSE36,
0514ef2f 646 .features[FEAT_1_ECX] =
27861ecc 647 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 648 .features[FEAT_8000_0001_EDX] =
27861ecc 649 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 650 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 651 .features[FEAT_8000_0001_ECX] =
27861ecc 652 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 653 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
654 .xlevel = 0x8000000A,
c6dc6f63
AP		 655 },
656 {
657 .name = "phenom",
658 .level = 5,
99b88a17 659 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 660 .family = 16,
661 .model = 2,
662 .stepping = 3,
0514ef2f 663 .features[FEAT_1_EDX] =
27861ecc 664 PPRO_FEATURES |
c6dc6f63 665 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 666 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 667 .features[FEAT_1_ECX] =
27861ecc 668 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 669 CPUID_EXT_POPCNT,
0514ef2f 670 .features[FEAT_8000_0001_EDX] =
27861ecc 671 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 672 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
673 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 674 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 675 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
676 CPUID_EXT3_CR8LEG,
677 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
678 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 679 .features[FEAT_8000_0001_ECX] =
27861ecc 680 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 681 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 682 .features[FEAT_SVM] =
27861ecc 683 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 684 .xlevel = 0x8000001A,
685 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
686 },
687 {
688 .name = "core2duo",
689 .level = 10,
99b88a17 690 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 691 .family = 6,
692 .model = 15,
693 .stepping = 11,
0514ef2f 694 .features[FEAT_1_EDX] =
27861ecc 695 PPRO_FEATURES |
c6dc6f63 696 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 697 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
698 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 699 .features[FEAT_1_ECX] =
27861ecc 700 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 701 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
702 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 703 .features[FEAT_8000_0001_EDX] =
27861ecc 704 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 705 .features[FEAT_8000_0001_ECX] =
27861ecc 706 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 707 .xlevel = 0x80000008,
708 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
709 },
710 {
711 .name = "kvm64",
712 .level = 5,
99b88a17 713 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 714 .family = 15,
715 .model = 6,
716 .stepping = 1,
717 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 718 .features[FEAT_1_EDX] =
27861ecc 719 PPRO_FEATURES |
c6dc6f63
AP		 720 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
721 CPUID_PSE36,
722 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 723 .features[FEAT_1_ECX] =
27861ecc 724 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 725 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 726 .features[FEAT_8000_0001_EDX] =
27861ecc 727 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 728 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
729 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
730 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
731 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
732 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 733 .features[FEAT_8000_0001_ECX] =
27861ecc 734 0,
c6dc6f63
AP		 735 .xlevel = 0x80000008,
736 .model_id = "Common KVM processor"
737 },
c6dc6f63
AP		 738 {
739 .name = "qemu32",
740 .level = 4,
99b88a17 741 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 742 .family = 6,
f8e6a11a 743 .model = 6,
c6dc6f63 744 .stepping = 3,
0514ef2f 745 .features[FEAT_1_EDX] =
27861ecc 746 PPRO_FEATURES,
0514ef2f 747 .features[FEAT_1_ECX] =
27861ecc 748 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 749 .xlevel = 0x80000004,
c6dc6f63 750 },
eafaf1e5
AP		 751 {
752 .name = "kvm32",
753 .level = 5,
99b88a17 754 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 755 .family = 15,
756 .model = 6,
757 .stepping = 1,
0514ef2f 758 .features[FEAT_1_EDX] =
27861ecc 759 PPRO_FEATURES |
eafaf1e5 760 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 761 .features[FEAT_1_ECX] =
27861ecc 762 CPUID_EXT_SSE3,
0514ef2f 763 .features[FEAT_8000_0001_EDX] =
27861ecc 764 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 765 .features[FEAT_8000_0001_ECX] =
27861ecc 766 0,
eafaf1e5
AP		 767 .xlevel = 0x80000008,
768 .model_id = "Common 32-bit KVM processor"
769 },
c6dc6f63
AP		 770 {
771 .name = "coreduo",
772 .level = 10,
99b88a17 773 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 774 .family = 6,
775 .model = 14,
776 .stepping = 8,
0514ef2f 777 .features[FEAT_1_EDX] =
27861ecc 778 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
780 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 781 .features[FEAT_1_ECX] =
27861ecc 782 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 783 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 784 .features[FEAT_8000_0001_EDX] =
27861ecc 785 CPUID_EXT2_NX,
c6dc6f63
AP		 786 .xlevel = 0x80000008,
787 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
788 },
789 {
790 .name = "486",
58012d66 791 .level = 1,
99b88a17 792 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 793 .family = 4,
b2a856d9 794 .model = 8,
c6dc6f63 795 .stepping = 0,
0514ef2f 796 .features[FEAT_1_EDX] =
27861ecc 797 I486_FEATURES,
c6dc6f63
AP		 798 .xlevel = 0,
799 },
800 {
801 .name = "pentium",
802 .level = 1,
99b88a17 803 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 804 .family = 5,
805 .model = 4,
806 .stepping = 3,
0514ef2f 807 .features[FEAT_1_EDX] =
27861ecc 808 PENTIUM_FEATURES,
c6dc6f63
AP		 809 .xlevel = 0,
810 },
811 {
812 .name = "pentium2",
813 .level = 2,
99b88a17 814 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 815 .family = 6,
816 .model = 5,
817 .stepping = 2,
0514ef2f 818 .features[FEAT_1_EDX] =
27861ecc 819 PENTIUM2_FEATURES,
c6dc6f63
AP		 820 .xlevel = 0,
821 },
822 {
823 .name = "pentium3",
824 .level = 2,
99b88a17 825 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 826 .family = 6,
827 .model = 7,
828 .stepping = 3,
0514ef2f 829 .features[FEAT_1_EDX] =
27861ecc 830 PENTIUM3_FEATURES,
c6dc6f63
AP		 831 .xlevel = 0,
832 },
833 {
834 .name = "athlon",
835 .level = 2,
99b88a17 836 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 837 .family = 6,
838 .model = 2,
839 .stepping = 3,
0514ef2f 840 .features[FEAT_1_EDX] =
27861ecc 841 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 842 CPUID_MCA,
0514ef2f 843 .features[FEAT_8000_0001_EDX] =
27861ecc 844 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 845 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 846 .xlevel = 0x80000008,
c6dc6f63
AP		 847 },
848 {
849 .name = "n270",
850 /* original is on level 10 */
851 .level = 5,
99b88a17 852 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 853 .family = 6,
854 .model = 28,
855 .stepping = 2,
0514ef2f 856 .features[FEAT_1_EDX] =
27861ecc 857 PPRO_FEATURES |
8560efed
AJ		 858 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
859 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 860 /* Some CPUs got no CPUID_SEP */
0514ef2f 861 .features[FEAT_1_ECX] =
27861ecc 862 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 863 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
864 CPUID_EXT_MOVBE,
0514ef2f 865 .features[FEAT_8000_0001_EDX] =
27861ecc 866 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 867 CPUID_EXT2_NX,
0514ef2f 868 .features[FEAT_8000_0001_ECX] =
27861ecc 869 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 870 .xlevel = 0x8000000A,
871 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
872 },
3eca4642
EH		 873 {
874 .name = "Conroe",
6b11322e 875 .level = 4,
99b88a17 876 .vendor = CPUID_VENDOR_INTEL,
3eca4642 877 .family = 6,
ffce9ebb 878 .model = 15,
3eca4642 879 .stepping = 3,
0514ef2f 880 .features[FEAT_1_EDX] =
27861ecc 881 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 882 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
883 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
884 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
885 CPUID_DE | CPUID_FP87,
0514ef2f 886 .features[FEAT_1_ECX] =
27861ecc 887 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 888 .features[FEAT_8000_0001_EDX] =
27861ecc 889 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 890 .features[FEAT_8000_0001_ECX] =
27861ecc 891 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 892 .xlevel = 0x8000000A,
893 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
894 },
895 {
896 .name = "Penryn",
6b11322e 897 .level = 4,
99b88a17 898 .vendor = CPUID_VENDOR_INTEL,
3eca4642 899 .family = 6,
ffce9ebb 900 .model = 23,
3eca4642 901 .stepping = 3,
0514ef2f 902 .features[FEAT_1_EDX] =
27861ecc 903 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 904 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
905 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
906 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
907 CPUID_DE | CPUID_FP87,
0514ef2f 908 .features[FEAT_1_ECX] =
27861ecc 909 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3eca4642 910 CPUID_EXT_SSE3,
0514ef2f 911 .features[FEAT_8000_0001_EDX] =
27861ecc 912 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 913 .features[FEAT_8000_0001_ECX] =
27861ecc 914 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 915 .xlevel = 0x8000000A,
916 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
917 },
918 {
919 .name = "Nehalem",
6b11322e 920 .level = 4,
99b88a17 921 .vendor = CPUID_VENDOR_INTEL,
3eca4642 922 .family = 6,
ffce9ebb 923 .model = 26,
3eca4642 924 .stepping = 3,
0514ef2f 925 .features[FEAT_1_EDX] =
27861ecc 926 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 927 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
928 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
929 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
930 CPUID_DE | CPUID_FP87,
0514ef2f 931 .features[FEAT_1_ECX] =
27861ecc 932 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3eca4642 933 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 934 .features[FEAT_8000_0001_EDX] =
27861ecc 935 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 936 .features[FEAT_8000_0001_ECX] =
27861ecc 937 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 938 .xlevel = 0x8000000A,
939 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
940 },
941 {
942 .name = "Westmere",
943 .level = 11,
99b88a17 944 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 945 .family = 6,
946 .model = 44,
947 .stepping = 1,
0514ef2f 948 .features[FEAT_1_EDX] =
27861ecc 949 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 950 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
951 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
952 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
953 CPUID_DE | CPUID_FP87,
0514ef2f 954 .features[FEAT_1_ECX] =
27861ecc 955 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3eca4642 956 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
41cb383f 957 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 958 .features[FEAT_8000_0001_EDX] =
27861ecc 959 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 960 .features[FEAT_8000_0001_ECX] =
27861ecc 961 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 962 .xlevel = 0x8000000A,
963 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
964 },
965 {
966 .name = "SandyBridge",
967 .level = 0xd,
99b88a17 968 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 969 .family = 6,
970 .model = 42,
971 .stepping = 1,
0514ef2f 972 .features[FEAT_1_EDX] =
27861ecc 973 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 974 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
975 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
976 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
977 CPUID_DE | CPUID_FP87,
0514ef2f 978 .features[FEAT_1_ECX] =
27861ecc 979 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 980 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
981 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
982 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
983 CPUID_EXT_SSE3,
0514ef2f 984 .features[FEAT_8000_0001_EDX] =
27861ecc 985 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3eca4642 986 CPUID_EXT2_SYSCALL,
0514ef2f 987 .features[FEAT_8000_0001_ECX] =
27861ecc 988 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 989 .xlevel = 0x8000000A,
990 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
991 },
37507094
EH		 992 {
993 .name = "Haswell",
994 .level = 0xd,
99b88a17 995 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 996 .family = 6,
997 .model = 60,
998 .stepping = 1,
0514ef2f 999 .features[FEAT_1_EDX] =
27861ecc 1000 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
37507094 1001 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
80ae4160 1002 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
37507094
EH		 1003 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1004 CPUID_DE | CPUID_FP87,
0514ef2f 1005 .features[FEAT_1_ECX] =
27861ecc 1006 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
37507094
EH		 1007 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1008 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1009 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1010 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1011 CPUID_EXT_PCID,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
80ae4160 1014 CPUID_EXT2_SYSCALL,
0514ef2f 1015 .features[FEAT_8000_0001_ECX] =
27861ecc 1016 CPUID_EXT3_LAHF_LM,
0514ef2f 1017 .features[FEAT_7_0_EBX] =
27861ecc 1018 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 1019 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1020 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1021 CPUID_7_0_EBX_RTM,
1022 .xlevel = 0x8000000A,
1023 .model_id = "Intel Core Processor (Haswell)",
1024 },
3eca4642
EH		 1025 {
1026 .name = "Opteron_G1",
1027 .level = 5,
99b88a17 1028 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1029 .family = 15,
1030 .model = 6,
1031 .stepping = 1,
0514ef2f 1032 .features[FEAT_1_EDX] =
27861ecc 1033 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1034 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1035 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1036 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1037 CPUID_DE | CPUID_FP87,
0514ef2f 1038 .features[FEAT_1_ECX] =
27861ecc 1039 CPUID_EXT_SSE3,
0514ef2f 1040 .features[FEAT_8000_0001_EDX] =
27861ecc 1041 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
3eca4642
EH		 1042 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1043 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1044 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1045 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1046 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1047 .xlevel = 0x80000008,
1048 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1049 },
1050 {
1051 .name = "Opteron_G2",
1052 .level = 5,
99b88a17 1053 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1054 .family = 15,
1055 .model = 6,
1056 .stepping = 1,
0514ef2f 1057 .features[FEAT_1_EDX] =
27861ecc 1058 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1062 CPUID_DE | CPUID_FP87,
0514ef2f 1063 .features[FEAT_1_ECX] =
27861ecc 1064 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1065 .features[FEAT_8000_0001_EDX] =
27861ecc 1066 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1067 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1068 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1069 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1070 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1071 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1072 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1073 .features[FEAT_8000_0001_ECX] =
27861ecc 1074 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1075 .xlevel = 0x80000008,
1076 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1077 },
1078 {
1079 .name = "Opteron_G3",
1080 .level = 5,
99b88a17 1081 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1082 .family = 15,
1083 .model = 6,
1084 .stepping = 1,
0514ef2f 1085 .features[FEAT_1_EDX] =
27861ecc 1086 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1087 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1088 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1089 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1090 CPUID_DE | CPUID_FP87,
0514ef2f 1091 .features[FEAT_1_ECX] =
27861ecc 1092 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3eca4642 1093 CPUID_EXT_SSE3,
0514ef2f 1094 .features[FEAT_8000_0001_EDX] =
27861ecc 1095 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
3eca4642
EH		 1096 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1097 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1098 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1099 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1100 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1101 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1102 .features[FEAT_8000_0001_ECX] =
27861ecc 1103 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3eca4642
EH		 1104 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1105 .xlevel = 0x80000008,
1106 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1107 },
1108 {
1109 .name = "Opteron_G4",
1110 .level = 0xd,
99b88a17 1111 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1112 .family = 21,
1113 .model = 1,
1114 .stepping = 2,
0514ef2f 1115 .features[FEAT_1_EDX] =
27861ecc 1116 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3eca4642
EH		 1117 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1118 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1119 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1120 CPUID_DE | CPUID_FP87,
0514ef2f 1121 .features[FEAT_1_ECX] =
27861ecc 1122 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3eca4642
EH		 1123 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1124 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1125 CPUID_EXT_SSE3,
0514ef2f 1126 .features[FEAT_8000_0001_EDX] =
27861ecc 1127 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
3eca4642
EH		 1128 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1129 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1130 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1131 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1132 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1133 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1134 .features[FEAT_8000_0001_ECX] =
27861ecc 1135 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3eca4642
EH		 1136 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1137 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1138 CPUID_EXT3_LAHF_LM,
1139 .xlevel = 0x8000001A,
1140 .model_id = "AMD Opteron 62xx class CPU",
1141 },
021941b9
AP		 1142 {
1143 .name = "Opteron_G5",
1144 .level = 0xd,
99b88a17 1145 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1146 .family = 21,
1147 .model = 2,
1148 .stepping = 0,
0514ef2f 1149 .features[FEAT_1_EDX] =
27861ecc 1150 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
021941b9
AP		 1151 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1152 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1153 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1154 CPUID_DE | CPUID_FP87,
0514ef2f 1155 .features[FEAT_1_ECX] =
27861ecc 1156 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
021941b9
AP		 1157 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1158 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1159 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1160 .features[FEAT_8000_0001_EDX] =
27861ecc 1161 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
021941b9
AP		 1162 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1163 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1164 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1165 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1166 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1167 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1168 .features[FEAT_8000_0001_ECX] =
27861ecc 1169 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
021941b9
AP		 1170 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1171 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1172 CPUID_EXT3_LAHF_LM,
1173 .xlevel = 0x8000001A,
1174 .model_id = "AMD Opteron 63xx class CPU",
1175 },
c6dc6f63
AP		 1176};
1177
0668af54
EH		 1178/**
1179 * x86_cpu_compat_set_features:
1180 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1181 * @w: Identifies the feature word to be changed.
1182 * @feat_add: Feature bits to be added to feature word
1183 * @feat_remove: Feature bits to be removed from feature word
1184 *
1185 * Change CPU model feature bits for compatibility.
1186 *
1187 * This function may be used by machine-type compatibility functions
1188 * to enable or disable feature bits on specific CPU models.
1189 */
1190void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1191 uint32_t feat_add, uint32_t feat_remove)
1192{
9576de75 1193 X86CPUDefinition *def;
0668af54
EH		 1194 int i;
1195 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1196 def = &builtin_x86_defs[i];
1197 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1198 def->features[w] |= feat_add;
1199 def->features[w] &= ~feat_remove;
1200 }
1201 }
1202}
1203
d940ee9b
EH		 1204#ifdef CONFIG_KVM
1205
c6dc6f63
AP		 1206static int cpu_x86_fill_model_id(char *str)
1207{
1208 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1209 int i;
1210
1211 for (i = 0; i < 3; i++) {
1212 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1213 memcpy(str + i * 16 + 0, &eax, 4);
1214 memcpy(str + i * 16 + 4, &ebx, 4);
1215 memcpy(str + i * 16 + 8, &ecx, 4);
1216 memcpy(str + i * 16 + 12, &edx, 4);
1217 }
1218 return 0;
1219}
1220
d940ee9b
EH		 1221static X86CPUDefinition host_cpudef;
1222
84f1b92f
EH		 1223static Property host_x86_cpu_properties[] = {
1224 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, false),
1225 DEFINE_PROP_END_OF_LIST()
1226};
1227
d940ee9b 1228/* class_init for the "host" CPU model
6e746f30 1229 *
d940ee9b 1230 * This function may be called before KVM is initialized.
6e746f30 1231 */
d940ee9b 1232static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1233{
84f1b92f 1234 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1235 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1236 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1237
d940ee9b 1238 xcc->kvm_required = true;
6e746f30 1239
c6dc6f63 1240 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1241 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1242
1243 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1244 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1245 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1246 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1247
d940ee9b 1248 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1249
d940ee9b
EH		 1250 xcc->cpu_def = &host_cpudef;
1251 host_cpudef.cache_info_passthrough = true;
1252
1253 /* level, xlevel, xlevel2, and the feature words are initialized on
1254 * instance_init, because they require KVM to be initialized.
1255 */
84f1b92f
EH		 1256
1257 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1258}
1259
84f1b92f
EH		 1260static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1261 bool migratable_only);
1262
d940ee9b
EH		 1263static void host_x86_cpu_initfn(Object *obj)
1264{
1265 X86CPU *cpu = X86_CPU(obj);
1266 CPUX86State *env = &cpu->env;
1267 KVMState *s = kvm_state;
1268 FeatureWord w;
1269
1270 assert(kvm_enabled());
1271
1272 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1273 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1274 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1275
2bc65d2b 1276 for (w = 0; w < FEATURE_WORDS; w++) {
d940ee9b 1277 env->features[w] =
84f1b92f 1278 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2bc65d2b 1279 }
d940ee9b 1280 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1281}
1282
d940ee9b
EH		 1283static const TypeInfo host_x86_cpu_type_info = {
1284 .name = X86_CPU_TYPE_NAME("host"),
1285 .parent = TYPE_X86_CPU,
1286 .instance_init = host_x86_cpu_initfn,
1287 .class_init = host_x86_cpu_class_init,
1288};
1289
1290#endif
1291
8459e396 1292static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1293{
8459e396 1294 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1295 int i;
1296
857aee33 1297 for (i = 0; i < 32; ++i) {
c6dc6f63 1298 if (1 << i & mask) {
bffd67b0 1299 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1300 assert(reg);
fefb41bf 1301 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1302 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1303 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1304 f->cpuid_eax, reg,
1305 f->feat_names[i] ? "." : "",
1306 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1307 }
857aee33 1308 }
c6dc6f63
AP		 1309}
1310
95b8519d
AF		 1311static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1312 const char *name, Error **errp)
1313{
1314 X86CPU *cpu = X86_CPU(obj);
1315 CPUX86State *env = &cpu->env;
1316 int64_t value;
1317
1318 value = (env->cpuid_version >> 8) & 0xf;
1319 if (value == 0xf) {
1320 value += (env->cpuid_version >> 20) & 0xff;
1321 }
1322 visit_type_int(v, &value, name, errp);
1323}
1324
71ad61d3
AF		 1325static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1326 const char *name, Error **errp)
ed5e1ec3 1327{
71ad61d3
AF		 1328 X86CPU *cpu = X86_CPU(obj);
1329 CPUX86State *env = &cpu->env;
1330 const int64_t min = 0;
1331 const int64_t max = 0xff + 0xf;
65cd9064 1332 Error *local_err = NULL;
71ad61d3
AF		 1333 int64_t value;
1334
65cd9064
MA		 1335 visit_type_int(v, &value, name, &local_err);
1336 if (local_err) {
1337 error_propagate(errp, local_err);
71ad61d3
AF		 1338 return;
1339 }
1340 if (value < min || value > max) {
1341 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1342 name ? name : "null", value, min, max);
1343 return;
1344 }
1345
ed5e1ec3 1346 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1347 if (value > 0x0f) {
1348 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1349 } else {
71ad61d3 1350 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1351 }
1352}
1353
67e30c83
AF		 1354static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1355 const char *name, Error **errp)
1356{
1357 X86CPU *cpu = X86_CPU(obj);
1358 CPUX86State *env = &cpu->env;
1359 int64_t value;
1360
1361 value = (env->cpuid_version >> 4) & 0xf;
1362 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1363 visit_type_int(v, &value, name, errp);
1364}
1365
c5291a4f
AF		 1366static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1367 const char *name, Error **errp)
b0704cbd 1368{
c5291a4f
AF		 1369 X86CPU *cpu = X86_CPU(obj);
1370 CPUX86State *env = &cpu->env;
1371 const int64_t min = 0;
1372 const int64_t max = 0xff;
65cd9064 1373 Error *local_err = NULL;
c5291a4f
AF		 1374 int64_t value;
1375
65cd9064
MA		 1376 visit_type_int(v, &value, name, &local_err);
1377 if (local_err) {
1378 error_propagate(errp, local_err);
c5291a4f
AF		 1379 return;
1380 }
1381 if (value < min || value > max) {
1382 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1383 name ? name : "null", value, min, max);
1384 return;
1385 }
1386
b0704cbd 1387 env->cpuid_version &= ~0xf00f0;
c5291a4f 1388 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1389}
1390
35112e41
AF		 1391static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1392 void *opaque, const char *name,
1393 Error **errp)
1394{
1395 X86CPU *cpu = X86_CPU(obj);
1396 CPUX86State *env = &cpu->env;
1397 int64_t value;
1398
1399 value = env->cpuid_version & 0xf;
1400 visit_type_int(v, &value, name, errp);
1401}
1402
036e2222
AF		 1403static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1404 void *opaque, const char *name,
1405 Error **errp)
38c3dc46 1406{
036e2222
AF		 1407 X86CPU *cpu = X86_CPU(obj);
1408 CPUX86State *env = &cpu->env;
1409 const int64_t min = 0;
1410 const int64_t max = 0xf;
65cd9064 1411 Error *local_err = NULL;
036e2222
AF		 1412 int64_t value;
1413
65cd9064
MA		 1414 visit_type_int(v, &value, name, &local_err);
1415 if (local_err) {
1416 error_propagate(errp, local_err);
036e2222
AF		 1417 return;
1418 }
1419 if (value < min || value > max) {
1420 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1421 name ? name : "null", value, min, max);
1422 return;
1423 }
1424
38c3dc46 1425 env->cpuid_version &= ~0xf;
036e2222 1426 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1427}
1428
8e1898bf
AF		 1429static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1430 const char *name, Error **errp)
1431{
1432 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1433
fa029887 1434 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1435}
1436
1437static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1438 const char *name, Error **errp)
1439{
1440 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1441
fa029887 1442 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1443}
1444
16b93aa8
AF		 1445static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1446 const char *name, Error **errp)
1447{
1448 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1449
fa029887 1450 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1451}
1452
1453static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1454 const char *name, Error **errp)
1455{
1456 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1457
fa029887 1458 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1459}
1460
d480e1af
AF		 1461static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1462{
1463 X86CPU *cpu = X86_CPU(obj);
1464 CPUX86State *env = &cpu->env;
1465 char *value;
d480e1af 1466
9df694ee 1467 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1468 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1469 env->cpuid_vendor3);
d480e1af
AF		 1470 return value;
1471}
1472
1473static void x86_cpuid_set_vendor(Object *obj, const char *value,
1474 Error **errp)
1475{
1476 X86CPU *cpu = X86_CPU(obj);
1477 CPUX86State *env = &cpu->env;
1478 int i;
1479
9df694ee 1480 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1481 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1482 "vendor", value);
1483 return;
1484 }
1485
1486 env->cpuid_vendor1 = 0;
1487 env->cpuid_vendor2 = 0;
1488 env->cpuid_vendor3 = 0;
1489 for (i = 0; i < 4; i++) {
1490 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1491 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1492 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1493 }
d480e1af
AF		 1494}
1495
63e886eb
AF		 1496static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1497{
1498 X86CPU *cpu = X86_CPU(obj);
1499 CPUX86State *env = &cpu->env;
1500 char *value;
1501 int i;
1502
1503 value = g_malloc(48 + 1);
1504 for (i = 0; i < 48; i++) {
1505 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1506 }
1507 value[48] = '\0';
1508 return value;
1509}
1510
938d4c25
AF		 1511static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1512 Error **errp)
dcce6675 1513{
938d4c25
AF		 1514 X86CPU *cpu = X86_CPU(obj);
1515 CPUX86State *env = &cpu->env;
dcce6675
AF		 1516 int c, len, i;
1517
1518 if (model_id == NULL) {
1519 model_id = "";
1520 }
1521 len = strlen(model_id);
d0a6acf4 1522 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1523 for (i = 0; i < 48; i++) {
1524 if (i >= len) {
1525 c = '\0';
1526 } else {
1527 c = (uint8_t)model_id[i];
1528 }
1529 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1530 }
1531}
1532
89e48965
AF		 1533static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1534 const char *name, Error **errp)
1535{
1536 X86CPU *cpu = X86_CPU(obj);
1537 int64_t value;
1538
1539 value = cpu->env.tsc_khz * 1000;
1540 visit_type_int(v, &value, name, errp);
1541}
1542
1543static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1544 const char *name, Error **errp)
1545{
1546 X86CPU *cpu = X86_CPU(obj);
1547 const int64_t min = 0;
2e84849a 1548 const int64_t max = INT64_MAX;
65cd9064 1549 Error *local_err = NULL;
89e48965
AF		 1550 int64_t value;
1551
65cd9064
MA		 1552 visit_type_int(v, &value, name, &local_err);
1553 if (local_err) {
1554 error_propagate(errp, local_err);
89e48965
AF		 1555 return;
1556 }
1557 if (value < min || value > max) {
1558 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1559 name ? name : "null", value, min, max);
1560 return;
1561 }
1562
1563 cpu->env.tsc_khz = value / 1000;
1564}
1565
31050930
IM		 1566static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1567 const char *name, Error **errp)
1568{
1569 X86CPU *cpu = X86_CPU(obj);
1570 int64_t value = cpu->env.cpuid_apic_id;
1571
1572 visit_type_int(v, &value, name, errp);
1573}
1574
1575static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1576 const char *name, Error **errp)
1577{
1578 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1579 DeviceState *dev = DEVICE(obj);
31050930
IM		 1580 const int64_t min = 0;
1581 const int64_t max = UINT32_MAX;
1582 Error *error = NULL;
1583 int64_t value;
1584
8d6d4980
IM		 1585 if (dev->realized) {
1586 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1587 "it was realized", name, object_get_typename(obj));
1588 return;
1589 }
1590
31050930
IM		 1591 visit_type_int(v, &value, name, &error);
1592 if (error) {
1593 error_propagate(errp, error);
1594 return;
1595 }
1596 if (value < min || value > max) {
1597 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1598 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1599 object_get_typename(obj), name, value, min, max);
1600 return;
1601 }
1602
1603 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1604 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1605 return;
1606 }
1607 cpu->env.cpuid_apic_id = value;
1608}
1609
7e5292b5 1610/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1611static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1612 const char *name, Error **errp)
1613{
7e5292b5 1614 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1615 FeatureWord w;
1616 Error *err = NULL;
1617 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1618 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1619 X86CPUFeatureWordInfoList *list = NULL;
1620
1621 for (w = 0; w < FEATURE_WORDS; w++) {
1622 FeatureWordInfo *wi = &feature_word_info[w];
1623 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1624 qwi->cpuid_input_eax = wi->cpuid_eax;
1625 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1626 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1627 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1628 qwi->features = array[w];
8e8aba50
EH		 1629
1630 /* List will be in reverse order, but order shouldn't matter */
1631 list_entries[w].next = list;
1632 list_entries[w].value = &word_infos[w];
1633 list = &list_entries[w];
1634 }
1635
1636 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1637 error_propagate(errp, err);
1638}
1639
c8f0f88e
IM		 1640static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1641 const char *name, Error **errp)
1642{
1643 X86CPU *cpu = X86_CPU(obj);
1644 int64_t value = cpu->hyperv_spinlock_attempts;
1645
1646 visit_type_int(v, &value, name, errp);
1647}
1648
1649static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1650 const char *name, Error **errp)
1651{
1652 const int64_t min = 0xFFF;
1653 const int64_t max = UINT_MAX;
1654 X86CPU *cpu = X86_CPU(obj);
1655 Error *err = NULL;
1656 int64_t value;
1657
1658 visit_type_int(v, &value, name, &err);
1659 if (err) {
1660 error_propagate(errp, err);
1661 return;
1662 }
1663
1664 if (value < min || value > max) {
1665 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1666 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1667 object_get_typename(obj), name ? name : "null",
1668 value, min, max);
1669 return;
1670 }
1671 cpu->hyperv_spinlock_attempts = value;
1672}
1673
1674static PropertyInfo qdev_prop_spinlocks = {
1675 .name = "int",
1676 .get = x86_get_hv_spinlocks,
1677 .set = x86_set_hv_spinlocks,
1678};
1679
72ac2e87
IM		 1680/* Convert all '_' in a feature string option name to '-', to make feature
1681 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1682 */
1683static inline void feat2prop(char *s)
1684{
1685 while ((s = strchr(s, '_'))) {
1686 *s = '-';
1687 }
1688}
1689
8f961357
EH		 1690/* Parse "+feature,-feature,feature=foo" CPU feature string
1691 */
94a444b2
AF		 1692static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1693 Error **errp)
8f961357 1694{
94a444b2 1695 X86CPU *cpu = X86_CPU(cs);
8f961357 1696 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1697 FeatureWord w;
8f961357 1698 /* Features to be added */
077c68c3 1699 FeatureWordArray plus_features = { 0 };
8f961357 1700 /* Features to be removed */
5ef57876 1701 FeatureWordArray minus_features = { 0 };
8f961357 1702 uint32_t numvalue;
a91987c2 1703 CPUX86State *env = &cpu->env;
94a444b2 1704 Error *local_err = NULL;
8f961357 1705
8f961357 1706 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1707
1708 while (featurestr) {
1709 char *val;
1710 if (featurestr[0] == '+') {
5ef57876 1711 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1712 } else if (featurestr[0] == '-') {
5ef57876 1713 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1714 } else if ((val = strchr(featurestr, '='))) {
1715 *val = 0; val++;
72ac2e87 1716 feat2prop(featurestr);
d024d209 1717 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1718 char *err;
a91987c2
IM		 1719 char num[32];
1720
c6dc6f63
AP		 1721 numvalue = strtoul(val, &err, 0);
1722 if (!*val || *err) {
6b1dd54b
PB		 1723 error_setg(errp, "bad numerical value %s", val);
1724 return;
c6dc6f63
AP		 1725 }
1726 if (numvalue < 0x80000000) {
94a444b2
AF		 1727 error_report("xlevel value shall always be >= 0x80000000"
1728 ", fixup will be removed in future versions");
2f7a21c4 1729 numvalue += 0x80000000;
c6dc6f63 1730 }
a91987c2 1731 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1732 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1733 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1734 int64_t tsc_freq;
1735 char *err;
a91987c2 1736 char num[32];
b862d1fe
JR		 1737
1738 tsc_freq = strtosz_suffix_unit(val, &err,
1739 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1740 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1741 error_setg(errp, "bad numerical value %s", val);
1742 return;
b862d1fe 1743 }
a91987c2 1744 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1745 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1746 &local_err);
72ac2e87 1747 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1748 char *err;
92067bf4 1749 const int min = 0xFFF;
c8f0f88e 1750 char num[32];
28f52cc0
VR		 1751 numvalue = strtoul(val, &err, 0);
1752 if (!*val || *err) {
6b1dd54b
PB		 1753 error_setg(errp, "bad numerical value %s", val);
1754 return;
28f52cc0 1755 }
92067bf4 1756 if (numvalue < min) {
94a444b2
AF		 1757 error_report("hv-spinlocks value shall always be >= 0x%x"
1758 ", fixup will be removed in future versions",
92067bf4
IM		 1759 min);
1760 numvalue = min;
1761 }
c8f0f88e 1762 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1763 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1764 } else {
94a444b2 1765 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1766 }
c6dc6f63 1767 } else {
258f5abe 1768 feat2prop(featurestr);
94a444b2 1769 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1770 }
94a444b2
AF		 1771 if (local_err) {
1772 error_propagate(errp, local_err);
6b1dd54b 1773 return;
c6dc6f63
AP		 1774 }
1775 featurestr = strtok(NULL, ",");
1776 }
e1c224b4
EH		 1777
1778 for (w = 0; w < FEATURE_WORDS; w++) {
1779 env->features[w] |= plus_features[w];
1780 env->features[w] &= ~minus_features[w];
1781 }
c6dc6f63
AP		 1782}
1783
1784/* generate a composite string into buf of all cpuid names in featureset
1785 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1786 * if flags, suppress names undefined in featureset.
1787 */
1788static void listflags(char *buf, int bufsize, uint32_t fbits,
1789 const char **featureset, uint32_t flags)
1790{
1791 const char **p = &featureset[31];
1792 char *q, *b, bit;
1793 int nc;
1794
1795 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1796 *buf = '\0';
1797 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1798 if (fbits & 1 << bit && (*p || !flags)) {
1799 if (*p)
1800 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1801 else
1802 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1803 if (bufsize <= nc) {
1804 if (b) {
1805 memcpy(b, "...", sizeof("..."));
1806 }
1807 return;
1808 }
1809 q += nc;
1810 bufsize -= nc;
1811 }
1812}
1813
e916cbf8
PM		 1814/* generate CPU information. */
1815void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1816{
9576de75 1817 X86CPUDefinition *def;
c6dc6f63 1818 char buf[256];
7fc9b714 1819 int i;
c6dc6f63 1820
7fc9b714
AF		 1821 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1822 def = &builtin_x86_defs[i];
c04321b3 1823 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1824 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1825 }
21ad7789
JK		 1826#ifdef CONFIG_KVM
1827 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1828 "KVM processor with all supported host features "
1829 "(only available in KVM mode)");
1830#endif
1831
6cdf8854 1832 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1833 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1834 FeatureWordInfo *fw = &feature_word_info[i];
1835
1836 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1837 (*cpu_fprintf)(f, " %s\n", buf);
1838 }
c6dc6f63
AP		 1839}
1840
76b64a7a 1841CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1842{
1843 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1844 X86CPUDefinition *def;
7fc9b714 1845 int i;
e3966126 1846
7fc9b714 1847 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1848 CpuDefinitionInfoList *entry;
1849 CpuDefinitionInfo *info;
1850
7fc9b714 1851 def = &builtin_x86_defs[i];
e3966126
AL		 1852 info = g_malloc0(sizeof(*info));
1853 info->name = g_strdup(def->name);
1854
1855 entry = g_malloc0(sizeof(*entry));
1856 entry->value = info;
1857 entry->next = cpu_list;
1858 cpu_list = entry;
1859 }
1860
1861 return cpu_list;
1862}
1863
84f1b92f
EH		 1864static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1865 bool migratable_only)
27418adf
EH		 1866{
1867 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 1868 uint32_t r;
27418adf 1869
fefb41bf 1870 if (kvm_enabled()) {
84f1b92f
EH		 1871 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1872 wi->cpuid_ecx,
1873 wi->cpuid_reg);
fefb41bf 1874 } else if (tcg_enabled()) {
84f1b92f 1875 r = wi->tcg_features;
fefb41bf
EH		 1876 } else {
1877 return ~0;
1878 }
84f1b92f
EH		 1879 if (migratable_only) {
1880 r &= x86_cpu_get_migratable_flags(w);
1881 }
1882 return r;
27418adf
EH		 1883}
1884
51f63aed
EH		 1885/*
1886 * Filters CPU feature words based on host availability of each feature.
1887 *
51f63aed
EH		 1888 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1889 */
27418adf 1890static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 1891{
1892 CPUX86State *env = &cpu->env;
bd87d2a2 1893 FeatureWord w;
51f63aed
EH		 1894 int rv = 0;
1895
bd87d2a2 1896 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 1897 uint32_t host_feat =
1898 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 1899 uint32_t requested_features = env->features[w];
1900 env->features[w] &= host_feat;
1901 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 1902 if (cpu->filtered_features[w]) {
1903 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 1904 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 1905 }
1906 rv = 1;
1907 }
bd87d2a2 1908 }
51f63aed
EH		 1909
1910 return rv;
bc74b7db 1911}
bc74b7db 1912
d940ee9b 1913/* Load data from X86CPUDefinition
c080e30e 1914 */
d940ee9b 1915static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1916{
61dcd775 1917 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1918 const char *vendor;
1919 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 1920 FeatureWord w;
c6dc6f63 1921
2d64255b
AF		 1922 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1923 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1924 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1925 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 1926 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 1927 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1928 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 1929 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 1930 for (w = 0; w < FEATURE_WORDS; w++) {
1931 env->features[w] = def->features[w];
1932 }
82beb536 1933
9576de75 1934 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1935 if (kvm_enabled()) {
5fcca9ff
EH		 1936 FeatureWord w;
1937 for (w = 0; w < FEATURE_WORDS; w++) {
1938 env->features[w] |= kvm_default_features[w];
136a7e9a 1939 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 1940 }
82beb536 1941 }
5fcca9ff 1942
82beb536 1943 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1944
1945 /* sysenter isn't supported in compatibility mode on AMD,
1946 * syscall isn't supported in compatibility mode on Intel.
1947 * Normally we advertise the actual CPU vendor, but you can
1948 * override this using the 'vendor' property if you want to use
1949 * KVM's sysenter/syscall emulation in compatibility mode and
1950 * when doing cross vendor migration
1951 */
74f54bc4 1952 vendor = def->vendor;
7c08db30
EH		 1953 if (kvm_enabled()) {
1954 uint32_t ebx = 0, ecx = 0, edx = 0;
1955 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1956 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1957 vendor = host_vendor;
1958 }
1959
1960 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1961
c6dc6f63
AP		 1962}
1963
62fc403f
IM		 1964X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1965 Error **errp)
5c3c6a68 1966{
2d64255b 1967 X86CPU *cpu = NULL;
d940ee9b 1968 X86CPUClass *xcc;
500050d1 1969 ObjectClass *oc;
2d64255b
AF		 1970 gchar **model_pieces;
1971 char *name, *features;
5c3c6a68
AF		 1972 Error *error = NULL;
1973
2d64255b
AF		 1974 model_pieces = g_strsplit(cpu_model, ",", 2);
1975 if (!model_pieces[0]) {
1976 error_setg(&error, "Invalid/empty CPU model name");
1977 goto out;
1978 }
1979 name = model_pieces[0];
1980 features = model_pieces[1];
1981
500050d1
AF		 1982 oc = x86_cpu_class_by_name(name);
1983 if (oc == NULL) {
1984 error_setg(&error, "Unable to find CPU definition: %s", name);
1985 goto out;
1986 }
d940ee9b
EH		 1987 xcc = X86_CPU_CLASS(oc);
1988
1989 if (xcc->kvm_required && !kvm_enabled()) {
1990 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 1991 goto out;
1992 }
1993
d940ee9b
EH		 1994 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1995
62fc403f
IM		 1996#ifndef CONFIG_USER_ONLY
1997 if (icc_bridge == NULL) {
1998 error_setg(&error, "Invalid icc-bridge value");
1999 goto out;
2000 }
2001 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2002 object_unref(OBJECT(cpu));
2003#endif
5c3c6a68 2004
94a444b2 2005 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2006 if (error) {
2007 goto out;
5c3c6a68
AF		 2008 }
2009
7f833247 2010out:
cd7b87ff
AF		 2011 if (error != NULL) {
2012 error_propagate(errp, error);
500050d1
AF		 2013 if (cpu) {
2014 object_unref(OBJECT(cpu));
2015 cpu = NULL;
2016 }
cd7b87ff 2017 }
7f833247
IM		 2018 g_strfreev(model_pieces);
2019 return cpu;
2020}
2021
2022X86CPU *cpu_x86_init(const char *cpu_model)
2023{
2024 Error *error = NULL;
2025 X86CPU *cpu;
2026
62fc403f 2027 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 2028 if (error) {
2d64255b
AF		 2029 goto out;
2030 }
2031
7f833247
IM		 2032 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2033
2d64255b 2034out:
2d64255b 2035 if (error) {
4a44d85e 2036 error_report("%s", error_get_pretty(error));
5c3c6a68 2037 error_free(error);
2d64255b
AF		 2038 if (cpu != NULL) {
2039 object_unref(OBJECT(cpu));
2040 cpu = NULL;
2041 }
5c3c6a68
AF		 2042 }
2043 return cpu;
2044}
2045
d940ee9b
EH		 2046static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2047{
2048 X86CPUDefinition *cpudef = data;
2049 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2050
2051 xcc->cpu_def = cpudef;
2052}
2053
2054static void x86_register_cpudef_type(X86CPUDefinition *def)
2055{
2056 char *typename = x86_cpu_type_name(def->name);
2057 TypeInfo ti = {
2058 .name = typename,
2059 .parent = TYPE_X86_CPU,
2060 .class_init = x86_cpu_cpudef_class_init,
2061 .class_data = def,
2062 };
2063
2064 type_register(&ti);
2065 g_free(typename);
2066}
2067
c6dc6f63 2068#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2069
0e26b7b8
BS		 2070void cpu_clear_apic_feature(CPUX86State *env)
2071{
0514ef2f 2072 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2073}
2074
c6dc6f63
AP		 2075#endif /* !CONFIG_USER_ONLY */
2076
c04321b3 2077/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2078 */
2079void x86_cpudef_setup(void)
2080{
93bfef4c
CV		 2081 int i, j;
2082 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2083
2084 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2085 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2086
2087 /* Look for specific "cpudef" models that */
09faecf2 2088 /* have the QEMU version in .model_id */
93bfef4c 2089 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2090 if (strcmp(model_with_versions[j], def->name) == 0) {
2091 pstrcpy(def->model_id, sizeof(def->model_id),
2092 "QEMU Virtual CPU version ");
2093 pstrcat(def->model_id, sizeof(def->model_id),
2094 qemu_get_version());
93bfef4c
CV		 2095 break;
2096 }
2097 }
c6dc6f63 2098 }
c6dc6f63
AP		 2099}
2100
c6dc6f63
AP		 2101static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2102 uint32_t *ecx, uint32_t *edx)
2103{
2104 *ebx = env->cpuid_vendor1;
2105 *edx = env->cpuid_vendor2;
2106 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2107}
2108
2109void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2110 uint32_t *eax, uint32_t *ebx,
2111 uint32_t *ecx, uint32_t *edx)
2112{
a60f24b5
AF		 2113 X86CPU *cpu = x86_env_get_cpu(env);
2114 CPUState *cs = CPU(cpu);
2115
c6dc6f63
AP		 2116 /* test if maximum index reached */
2117 if (index & 0x80000000) {
b3baa152
BW		 2118 if (index > env->cpuid_xlevel) {
2119 if (env->cpuid_xlevel2 > 0) {
2120 /* Handle the Centaur's CPUID instruction. */
2121 if (index > env->cpuid_xlevel2) {
2122 index = env->cpuid_xlevel2;
2123 } else if (index < 0xC0000000) {
2124 index = env->cpuid_xlevel;
2125 }
2126 } else {
57f26ae7
EH		 2127 /* Intel documentation states that invalid EAX input will
2128 * return the same information as EAX=cpuid_level
2129 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2130 */
2131 index = env->cpuid_level;
b3baa152
BW		 2132 }
2133 }
c6dc6f63
AP		 2134 } else {
2135 if (index > env->cpuid_level)
2136 index = env->cpuid_level;
2137 }
2138
2139 switch(index) {
2140 case 0:
2141 *eax = env->cpuid_level;
2142 get_cpuid_vendor(env, ebx, ecx, edx);
2143 break;
2144 case 1:
2145 *eax = env->cpuid_version;
2146 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2147 *ecx = env->features[FEAT_1_ECX];
2148 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2149 if (cs->nr_cores * cs->nr_threads > 1) {
2150 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2151 *edx |= 1 << 28; /* HTT bit */
2152 }
2153 break;
2154 case 2:
2155 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2156 if (cpu->cache_info_passthrough) {
2157 host_cpuid(index, 0, eax, ebx, ecx, edx);
2158 break;
2159 }
5e891bf8 2160 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2161 *ebx = 0;
2162 *ecx = 0;
5e891bf8
EH		 2163 *edx = (L1D_DESCRIPTOR << 16) | \
2164 (L1I_DESCRIPTOR << 8) | \
2165 (L2_DESCRIPTOR);
c6dc6f63
AP		 2166 break;
2167 case 4:
2168 /* cache info: needed for Core compatibility */
787aaf57
BC		 2169 if (cpu->cache_info_passthrough) {
2170 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2171 *eax &= ~0xFC000000;
c6dc6f63 2172 } else {
2f7a21c4 2173 *eax = 0;
76c2975a 2174 switch (count) {
c6dc6f63 2175 case 0: /* L1 dcache info */
5e891bf8
EH		 2176 *eax |= CPUID_4_TYPE_DCACHE | \
2177 CPUID_4_LEVEL(1) | \
2178 CPUID_4_SELF_INIT_LEVEL;
2179 *ebx = (L1D_LINE_SIZE - 1) | \
2180 ((L1D_PARTITIONS - 1) << 12) | \
2181 ((L1D_ASSOCIATIVITY - 1) << 22);
2182 *ecx = L1D_SETS - 1;
2183 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2184 break;
2185 case 1: /* L1 icache info */
5e891bf8
EH		 2186 *eax |= CPUID_4_TYPE_ICACHE | \
2187 CPUID_4_LEVEL(1) | \
2188 CPUID_4_SELF_INIT_LEVEL;
2189 *ebx = (L1I_LINE_SIZE - 1) | \
2190 ((L1I_PARTITIONS - 1) << 12) | \
2191 ((L1I_ASSOCIATIVITY - 1) << 22);
2192 *ecx = L1I_SETS - 1;
2193 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2194 break;
2195 case 2: /* L2 cache info */
5e891bf8
EH		 2196 *eax |= CPUID_4_TYPE_UNIFIED | \
2197 CPUID_4_LEVEL(2) | \
2198 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2199 if (cs->nr_threads > 1) {
2200 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2201 }
5e891bf8
EH		 2202 *ebx = (L2_LINE_SIZE - 1) | \
2203 ((L2_PARTITIONS - 1) << 12) | \
2204 ((L2_ASSOCIATIVITY - 1) << 22);
2205 *ecx = L2_SETS - 1;
2206 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2207 break;
2208 default: /* end of info */
2209 *eax = 0;
2210 *ebx = 0;
2211 *ecx = 0;
2212 *edx = 0;
2213 break;
76c2975a
PB		 2214 }
2215 }
2216
2217 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2218 if ((*eax & 31) && cs->nr_cores > 1) {
2219 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2220 }
2221 break;
2222 case 5:
2223 /* mwait info: needed for Core compatibility */
2224 *eax = 0; /* Smallest monitor-line size in bytes */
2225 *ebx = 0; /* Largest monitor-line size in bytes */
2226 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2227 *edx = 0;
2228 break;
2229 case 6:
2230 /* Thermal and Power Leaf */
2231 *eax = 0;
2232 *ebx = 0;
2233 *ecx = 0;
2234 *edx = 0;
2235 break;
f7911686 2236 case 7:
13526728
EH		 2237 /* Structured Extended Feature Flags Enumeration Leaf */
2238 if (count == 0) {
2239 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2240 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2241 *ecx = 0; /* Reserved */
2242 *edx = 0; /* Reserved */
f7911686
YW		 2243 } else {
2244 *eax = 0;
2245 *ebx = 0;
2246 *ecx = 0;
2247 *edx = 0;
2248 }
2249 break;
c6dc6f63
AP		 2250 case 9:
2251 /* Direct Cache Access Information Leaf */
2252 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2253 *ebx = 0;
2254 *ecx = 0;
2255 *edx = 0;
2256 break;
2257 case 0xA:
2258 /* Architectural Performance Monitoring Leaf */
9337e3b6 2259 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2260 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2261
2262 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2263 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2264 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2265 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2266 } else {
2267 *eax = 0;
2268 *ebx = 0;
2269 *ecx = 0;
2270 *edx = 0;
2271 }
c6dc6f63 2272 break;
2560f19f
PB		 2273 case 0xD: {
2274 KVMState *s = cs->kvm_state;
2275 uint64_t kvm_mask;
2276 int i;
2277
51e49430 2278 /* Processor Extended State */
2560f19f
PB		 2279 *eax = 0;
2280 *ebx = 0;
2281 *ecx = 0;
2282 *edx = 0;
2283 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2284 break;
2285 }
2560f19f
PB		 2286 kvm_mask =
2287 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2288 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2289
2560f19f
PB		 2290 if (count == 0) {
2291 *ecx = 0x240;
2292 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2293 const ExtSaveArea *esa = &ext_save_areas[i];
2294 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2295 (kvm_mask & (1 << i)) != 0) {
2296 if (i < 32) {
2297 *eax |= 1 << i;
2298 } else {
2299 *edx |= 1 << (i - 32);
2300 }
2301 *ecx = MAX(*ecx, esa->offset + esa->size);
2302 }
2303 }
2304 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2305 *ebx = *ecx;
2306 } else if (count == 1) {
2307 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2308 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2309 const ExtSaveArea *esa = &ext_save_areas[count];
2310 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2311 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2312 *eax = esa->size;
2313 *ebx = esa->offset;
2560f19f 2314 }
51e49430
SY		 2315 }
2316 break;
2560f19f 2317 }
c6dc6f63
AP		 2318 case 0x80000000:
2319 *eax = env->cpuid_xlevel;
2320 *ebx = env->cpuid_vendor1;
2321 *edx = env->cpuid_vendor2;
2322 *ecx = env->cpuid_vendor3;
2323 break;
2324 case 0x80000001:
2325 *eax = env->cpuid_version;
2326 *ebx = 0;
0514ef2f
EH		 2327 *ecx = env->features[FEAT_8000_0001_ECX];
2328 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2329
2330 /* The Linux kernel checks for the CMPLegacy bit and
2331 * discards multiple thread information if it is set.
2332 * So dont set it here for Intel to make Linux guests happy.
2333 */
ce3960eb 2334 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2335 uint32_t tebx, tecx, tedx;
2336 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2337 if (tebx != CPUID_VENDOR_INTEL_1 ||
2338 tedx != CPUID_VENDOR_INTEL_2 ||
2339 tecx != CPUID_VENDOR_INTEL_3) {
2340 *ecx |= 1 << 1; /* CmpLegacy bit */
2341 }
2342 }
c6dc6f63
AP		 2343 break;
2344 case 0x80000002:
2345 case 0x80000003:
2346 case 0x80000004:
2347 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2348 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2349 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2350 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2351 break;
2352 case 0x80000005:
2353 /* cache info (L1 cache) */
787aaf57
BC		 2354 if (cpu->cache_info_passthrough) {
2355 host_cpuid(index, 0, eax, ebx, ecx, edx);
2356 break;
2357 }
5e891bf8
EH		 2358 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2359 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2360 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2361 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2362 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2363 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2364 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2365 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2366 break;
2367 case 0x80000006:
2368 /* cache info (L2 cache) */
787aaf57
BC		 2369 if (cpu->cache_info_passthrough) {
2370 host_cpuid(index, 0, eax, ebx, ecx, edx);
2371 break;
2372 }
5e891bf8
EH		 2373 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2374 (L2_DTLB_2M_ENTRIES << 16) | \
2375 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2376 (L2_ITLB_2M_ENTRIES);
2377 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2378 (L2_DTLB_4K_ENTRIES << 16) | \
2379 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2380 (L2_ITLB_4K_ENTRIES);
2381 *ecx = (L2_SIZE_KB_AMD << 16) | \
2382 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2383 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2384 *edx = ((L3_SIZE_KB/512) << 18) | \
2385 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2386 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63
AP		 2387 break;
2388 case 0x80000008:
2389 /* virtual & phys address size in low 2 bytes. */
2390/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2391 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2392 /* 64 bit processor */
2393/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2394 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2395 } else {
0514ef2f 2396 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2397 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2398 } else {
c6dc6f63 2399 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2400 }
c6dc6f63
AP		 2401 }
2402 *ebx = 0;
2403 *ecx = 0;
2404 *edx = 0;
ce3960eb
AF		 2405 if (cs->nr_cores * cs->nr_threads > 1) {
2406 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2407 }
2408 break;
2409 case 0x8000000A:
0514ef2f 2410 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2411 *eax = 0x00000001; /* SVM Revision */
2412 *ebx = 0x00000010; /* nr of ASIDs */
2413 *ecx = 0;
0514ef2f 2414 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2415 } else {
2416 *eax = 0;
2417 *ebx = 0;
2418 *ecx = 0;
2419 *edx = 0;
2420 }
c6dc6f63 2421 break;
b3baa152
BW		 2422 case 0xC0000000:
2423 *eax = env->cpuid_xlevel2;
2424 *ebx = 0;
2425 *ecx = 0;
2426 *edx = 0;
2427 break;
2428 case 0xC0000001:
2429 /* Support for VIA CPU's CPUID instruction */
2430 *eax = env->cpuid_version;
2431 *ebx = 0;
2432 *ecx = 0;
0514ef2f 2433 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2434 break;
2435 case 0xC0000002:
2436 case 0xC0000003:
2437 case 0xC0000004:
2438 /* Reserved for the future, and now filled with zero */
2439 *eax = 0;
2440 *ebx = 0;
2441 *ecx = 0;
2442 *edx = 0;
2443 break;
c6dc6f63
AP		 2444 default:
2445 /* reserved values: zero */
2446 *eax = 0;
2447 *ebx = 0;
2448 *ecx = 0;
2449 *edx = 0;
2450 break;
2451 }
2452}
5fd2087a
AF		 2453
2454/* CPUClass::reset() */
2455static void x86_cpu_reset(CPUState *s)
2456{
2457 X86CPU *cpu = X86_CPU(s);
2458 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2459 CPUX86State *env = &cpu->env;
c1958aea
AF		 2460 int i;
2461
5fd2087a
AF		 2462 xcc->parent_reset(s);
2463
43175fa9 2464 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2465
00c8cb0a 2466 tlb_flush(s, 1);
c1958aea
AF		 2467
2468 env->old_exception = -1;
2469
2470 /* init to reset state */
2471
2472#ifdef CONFIG_SOFTMMU
2473 env->hflags |= HF_SOFTMMU_MASK;
2474#endif
2475 env->hflags2 |= HF2_GIF_MASK;
2476
2477 cpu_x86_update_cr0(env, 0x60000010);
2478 env->a20_mask = ~0x0;
2479 env->smbase = 0x30000;
2480
2481 env->idt.limit = 0xffff;
2482 env->gdt.limit = 0xffff;
2483 env->ldt.limit = 0xffff;
2484 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2485 env->tr.limit = 0xffff;
2486 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2487
2488 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2489 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2490 DESC_R_MASK | DESC_A_MASK);
2491 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2492 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2493 DESC_A_MASK);
2494 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2495 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2496 DESC_A_MASK);
2497 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2498 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2499 DESC_A_MASK);
2500 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2501 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2502 DESC_A_MASK);
2503 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2504 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2505 DESC_A_MASK);
2506
2507 env->eip = 0xfff0;
2508 env->regs[R_EDX] = env->cpuid_version;
2509
2510 env->eflags = 0x2;
2511
2512 /* FPU init */
2513 for (i = 0; i < 8; i++) {
2514 env->fptags[i] = 1;
2515 }
2516 env->fpuc = 0x37f;
2517
2518 env->mxcsr = 0x1f80;
c74f41bb 2519 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2520
2521 env->pat = 0x0007040600070406ULL;
2522 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2523
2524 memset(env->dr, 0, sizeof(env->dr));
2525 env->dr[6] = DR6_FIXED_1;
2526 env->dr[7] = DR7_FIXED_1;
b3310ab3 2527 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2528 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2529
05e7e819 2530 env->xcr0 = 1;
0522604b 2531
dd673288
IM		 2532#if !defined(CONFIG_USER_ONLY)
2533 /* We hard-wire the BSP to the first CPU. */
55e5c285 2534 if (s->cpu_index == 0) {
02e51483 2535 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2536 }
2537
259186a7 2538 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2539
2540 if (kvm_enabled()) {
2541 kvm_arch_reset_vcpu(cpu);
2542 }
dd673288 2543#endif
5fd2087a
AF		 2544}
2545
dd673288
IM		 2546#ifndef CONFIG_USER_ONLY
2547bool cpu_is_bsp(X86CPU *cpu)
2548{
02e51483 2549 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2550}
65dee380
IM		 2551
2552/* TODO: remove me, when reset over QOM tree is implemented */
2553static void x86_cpu_machine_reset_cb(void *opaque)
2554{
2555 X86CPU *cpu = opaque;
2556 cpu_reset(CPU(cpu));
2557}
dd673288
IM		 2558#endif
2559
de024815
AF		 2560static void mce_init(X86CPU *cpu)
2561{
2562 CPUX86State *cenv = &cpu->env;
2563 unsigned int bank;
2564
2565 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2566 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2567 (CPUID_MCE | CPUID_MCA)) {
2568 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2569 cenv->mcg_ctl = ~(uint64_t)0;
2570 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2571 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2572 }
2573 }
2574}
2575
bdeec802 2576#ifndef CONFIG_USER_ONLY
d3c64d6a 2577static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2578{
bdeec802 2579 CPUX86State *env = &cpu->env;
53a89e26 2580 DeviceState *dev = DEVICE(cpu);
449994eb 2581 APICCommonState *apic;
bdeec802
IM		 2582 const char *apic_type = "apic";
2583
2584 if (kvm_irqchip_in_kernel()) {
2585 apic_type = "kvm-apic";
2586 } else if (xen_enabled()) {
2587 apic_type = "xen-apic";
2588 }
2589
02e51483
CF		 2590 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2591 if (cpu->apic_state == NULL) {
bdeec802
IM		 2592 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2593 return;
2594 }
2595
2596 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2597 OBJECT(cpu->apic_state), NULL);
2598 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2599 /* TODO: convert to link<> */
02e51483 2600 apic = APIC_COMMON(cpu->apic_state);
60671e58 2601 apic->cpu = cpu;
d3c64d6a
IM		 2602}
2603
2604static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2605{
02e51483 2606 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2607 return;
2608 }
bdeec802 2609
02e51483 2610 if (qdev_init(cpu->apic_state)) {
bdeec802 2611 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2612 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2613 return;
2614 }
bdeec802 2615}
d3c64d6a
IM		 2616#else
2617static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2618{
2619}
bdeec802
IM		 2620#endif
2621
2b6f294c 2622static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2623{
14a10fc3 2624 CPUState *cs = CPU(dev);
2b6f294c
AF		 2625 X86CPU *cpu = X86_CPU(dev);
2626 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2627 CPUX86State *env = &cpu->env;
2b6f294c 2628 Error *local_err = NULL;
b34d12d1 2629
0514ef2f 2630 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2631 env->cpuid_level = 7;
2632 }
7a059953 2633
9b15cd9e
IM		 2634 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2635 * CPUID[1].EDX.
2636 */
2637 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2638 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2639 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2640 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2641 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2642 & CPUID_EXT2_AMD_ALIASES);
2643 }
2644
fefb41bf
EH		 2645
2646 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2647 error_setg(&local_err,
2648 kvm_enabled() ?
2649 "Host doesn't support requested features" :
2650 "TCG doesn't support requested features");
2651 goto out;
4586f157
IM		 2652 }
2653
65dee380
IM		 2654#ifndef CONFIG_USER_ONLY
2655 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2656
0514ef2f 2657 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2658 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2659 if (local_err != NULL) {
4dc1f449 2660 goto out;
bdeec802
IM		 2661 }
2662 }
65dee380
IM		 2663#endif
2664
7a059953 2665 mce_init(cpu);
14a10fc3 2666 qemu_init_vcpu(cs);
d3c64d6a
IM		 2667
2668 x86_cpu_apic_realize(cpu, &local_err);
2669 if (local_err != NULL) {
2670 goto out;
2671 }
14a10fc3 2672 cpu_reset(cs);
2b6f294c 2673
4dc1f449
IM		 2674 xcc->parent_realize(dev, &local_err);
2675out:
2676 if (local_err != NULL) {
2677 error_propagate(errp, local_err);
2678 return;
2679 }
7a059953
AF		 2680}
2681
8932cfdf
EH		 2682/* Enables contiguous-apic-ID mode, for compatibility */
2683static bool compat_apic_id_mode;
2684
2685void enable_compat_apic_id_mode(void)
2686{
2687 compat_apic_id_mode = true;
2688}
2689
cb41bad3
EH		 2690/* Calculates initial APIC ID for a specific CPU index
2691 *
2692 * Currently we need to be able to calculate the APIC ID from the CPU index
2693 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2694 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2695 * all CPUs up to max_cpus.
2696 */
2697uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2698{
8932cfdf
EH		 2699 uint32_t correct_id;
2700 static bool warned;
2701
2702 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2703 if (compat_apic_id_mode) {
2704 if (cpu_index != correct_id && !warned) {
2705 error_report("APIC IDs set in compatibility mode, "
2706 "CPU topology won't match the configuration");
2707 warned = true;
2708 }
2709 return cpu_index;
2710 } else {
2711 return correct_id;
2712 }
cb41bad3
EH		 2713}
2714
de024815
AF		 2715static void x86_cpu_initfn(Object *obj)
2716{
55e5c285 2717 CPUState *cs = CPU(obj);
de024815 2718 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2719 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2720 CPUX86State *env = &cpu->env;
d65e9815 2721 static int inited;
de024815 2722
c05efcb1 2723 cs->env_ptr = env;
de024815 2724 cpu_exec_init(env);
71ad61d3
AF		 2725
2726 object_property_add(obj, "family", "int",
95b8519d 2727 x86_cpuid_version_get_family,
71ad61d3 2728 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2729 object_property_add(obj, "model", "int",
67e30c83 2730 x86_cpuid_version_get_model,
c5291a4f 2731 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2732 object_property_add(obj, "stepping", "int",
35112e41 2733 x86_cpuid_version_get_stepping,
036e2222 2734 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2735 object_property_add(obj, "level", "int",
2736 x86_cpuid_get_level,
2737 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2738 object_property_add(obj, "xlevel", "int",
2739 x86_cpuid_get_xlevel,
2740 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2741 object_property_add_str(obj, "vendor",
2742 x86_cpuid_get_vendor,
2743 x86_cpuid_set_vendor, NULL);
938d4c25 2744 object_property_add_str(obj, "model-id",
63e886eb 2745 x86_cpuid_get_model_id,
938d4c25 2746 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2747 object_property_add(obj, "tsc-frequency", "int",
2748 x86_cpuid_get_tsc_freq,
2749 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2750 object_property_add(obj, "apic-id", "int",
2751 x86_cpuid_get_apic_id,
2752 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2753 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2754 x86_cpu_get_feature_words,
7e5292b5
EH		 2755 NULL, NULL, (void *)env->features, NULL);
2756 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2757 x86_cpu_get_feature_words,
2758 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2759
92067bf4 2760 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2761 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2762
d940ee9b
EH		 2763 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2764
d65e9815
IM		 2765 /* init various static tables used in TCG mode */
2766 if (tcg_enabled() && !inited) {
2767 inited = 1;
2768 optimize_flags_init();
2769#ifndef CONFIG_USER_ONLY
2770 cpu_set_debug_excp_handler(breakpoint_handler);
2771#endif
2772 }
de024815
AF		 2773}
2774
997395d3
IM		 2775static int64_t x86_cpu_get_arch_id(CPUState *cs)
2776{
2777 X86CPU *cpu = X86_CPU(cs);
2778 CPUX86State *env = &cpu->env;
2779
2780 return env->cpuid_apic_id;
2781}
2782
444d5590
AF		 2783static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2784{
2785 X86CPU *cpu = X86_CPU(cs);
2786
2787 return cpu->env.cr[0] & CR0_PG_MASK;
2788}
2789
f45748f1
AF		 2790static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2791{
2792 X86CPU *cpu = X86_CPU(cs);
2793
2794 cpu->env.eip = value;
2795}
2796
bdf7ae5b
AF		 2797static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2798{
2799 X86CPU *cpu = X86_CPU(cs);
2800
2801 cpu->env.eip = tb->pc - tb->cs_base;
2802}
2803
8c2e1b00
AF		 2804static bool x86_cpu_has_work(CPUState *cs)
2805{
2806 X86CPU *cpu = X86_CPU(cs);
2807 CPUX86State *env = &cpu->env;
2808
2809 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2810 CPU_INTERRUPT_POLL)) &&
2811 (env->eflags & IF_MASK)) ||
2812 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2813 CPU_INTERRUPT_INIT |
2814 CPU_INTERRUPT_SIPI |
2815 CPU_INTERRUPT_MCE));
2816}
2817
9337e3b6
EH		 2818static Property x86_cpu_properties[] = {
2819 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2820 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2821 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2822 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2823 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2824 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2825 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2826 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2827 DEFINE_PROP_END_OF_LIST()
2828};
2829
5fd2087a
AF		 2830static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2831{
2832 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2833 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2834 DeviceClass *dc = DEVICE_CLASS(oc);
2835
2836 xcc->parent_realize = dc->realize;
2837 dc->realize = x86_cpu_realizefn;
62fc403f 2838 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2839 dc->props = x86_cpu_properties;
5fd2087a
AF		 2840
2841 xcc->parent_reset = cc->reset;
2842 cc->reset = x86_cpu_reset;
91b1df8c 2843 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2844
500050d1 2845 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2846 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2847 cc->has_work = x86_cpu_has_work;
97a8ea5a 2848 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2849 cc->dump_state = x86_cpu_dump_state;
f45748f1 2850 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2851 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2852 cc->gdb_read_register = x86_cpu_gdb_read_register;
2853 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2854 cc->get_arch_id = x86_cpu_get_arch_id;
2855 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2856#ifdef CONFIG_USER_ONLY
2857 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2858#else
a23bbfda 2859 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2860 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2861 cc->write_elf64_note = x86_cpu_write_elf64_note;
2862 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2863 cc->write_elf32_note = x86_cpu_write_elf32_note;
2864 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2865 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2866#endif
a0e372f0 2867 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2868}
2869
2870static const TypeInfo x86_cpu_type_info = {
2871 .name = TYPE_X86_CPU,
2872 .parent = TYPE_CPU,
2873 .instance_size = sizeof(X86CPU),
de024815 2874 .instance_init = x86_cpu_initfn,
d940ee9b 2875 .abstract = true,
5fd2087a
AF		 2876 .class_size = sizeof(X86CPUClass),
2877 .class_init = x86_cpu_common_class_init,
2878};
2879
2880static void x86_cpu_register_types(void)
2881{
d940ee9b
EH		 2882 int i;
2883
5fd2087a 2884 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2885 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2886 x86_register_cpudef_type(&builtin_x86_defs[i]);
2887 }
2888#ifdef CONFIG_KVM
2889 type_register_static(&host_x86_cpu_type_info);
2890#endif
5fd2087a
AF		 2891}
2892
2893type_init(x86_cpu_register_types)
QEMU mirror