]> git.proxmox.com Git - mirror_qemu.git/blame - target-i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-i386: Fix indentation of CPU model definitions
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
811a8ae0
EH		 260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
c8acc380 262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
a9321a4d
PA		 263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
303752a9
MT		 266static const char *cpuid_apm_edx_feature_name[] = {
267 NULL, NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 "invtsc", NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275};
276
621626ce
EH		 277#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
278#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
279 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
280#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
281 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
282 CPUID_PSE36 | CPUID_FXSR)
283#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
284#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
285 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
286 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
287 CPUID_PAE | CPUID_SEP | CPUID_APIC)
288
289#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
290 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
291 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
292 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
293 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
294 /* partly implemented:
295 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
296 /* missing:
297 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
298#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
299 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
300 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
301 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
302 /* missing:
303 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
304 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
305 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
306 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
307 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
308 CPUID_EXT_RDRAND */
309
310#ifdef TARGET_X86_64
311#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
312#else
313#define TCG_EXT2_X86_64_FEATURES 0
314#endif
315
316#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
317 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
318 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
319 TCG_EXT2_X86_64_FEATURES)
320#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
321 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
322#define TCG_EXT4_FEATURES 0
323#define TCG_SVM_FEATURES 0
324#define TCG_KVM_FEATURES 0
325#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
326 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
327 /* missing:
328 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
329 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
330 CPUID_7_0_EBX_RDSEED */
303752a9 331#define TCG_APM_FEATURES 0
621626ce
EH		 332
333
5ef57876
EH		 334typedef struct FeatureWordInfo {
335 const char **feat_names;
04d104b6
EH		 336 uint32_t cpuid_eax; /* Input EAX for CPUID */
337 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
338 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
339 int cpuid_reg; /* output register (R_* constant) */
37ce3522 340 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 341 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 342} FeatureWordInfo;
343
344static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 345 [FEAT_1_EDX] = {
346 .feat_names = feature_name,
347 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 348 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 349 },
350 [FEAT_1_ECX] = {
351 .feat_names = ext_feature_name,
352 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 353 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 354 },
355 [FEAT_8000_0001_EDX] = {
356 .feat_names = ext2_feature_name,
357 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 358 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 359 },
360 [FEAT_8000_0001_ECX] = {
361 .feat_names = ext3_feature_name,
362 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 363 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 364 },
89e49c8b
EH		 365 [FEAT_C000_0001_EDX] = {
366 .feat_names = ext4_feature_name,
367 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 368 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 369 },
bffd67b0
EH		 370 [FEAT_KVM] = {
371 .feat_names = kvm_feature_name,
372 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 373 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 374 },
375 [FEAT_SVM] = {
376 .feat_names = svm_feature_name,
377 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 378 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 379 },
380 [FEAT_7_0_EBX] = {
381 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 382 .cpuid_eax = 7,
383 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
384 .cpuid_reg = R_EBX,
37ce3522 385 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 386 },
303752a9
MT		 387 [FEAT_8000_0007_EDX] = {
388 .feat_names = cpuid_apm_edx_feature_name,
389 .cpuid_eax = 0x80000007,
390 .cpuid_reg = R_EDX,
391 .tcg_features = TCG_APM_FEATURES,
392 .unmigratable_flags = CPUID_APM_INVTSC,
393 },
5ef57876
EH		 394};
395
8e8aba50
EH		 396typedef struct X86RegisterInfo32 {
397 /* Name of register */
398 const char *name;
399 /* QAPI enum value register */
400 X86CPURegister32 qapi_enum;
401} X86RegisterInfo32;
402
403#define REGISTER(reg) \
5d371f41 404 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 405static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 406 REGISTER(EAX),
407 REGISTER(ECX),
408 REGISTER(EDX),
409 REGISTER(EBX),
410 REGISTER(ESP),
411 REGISTER(EBP),
412 REGISTER(ESI),
413 REGISTER(EDI),
414};
415#undef REGISTER
416
2560f19f
PB		 417typedef struct ExtSaveArea {
418 uint32_t feature, bits;
419 uint32_t offset, size;
420} ExtSaveArea;
421
422static const ExtSaveArea ext_save_areas[] = {
423 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 424 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 425 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
426 .offset = 0x3c0, .size = 0x40 },
427 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 428 .offset = 0x400, .size = 0x40 },
2560f19f 429};
8e8aba50 430
8b4beddc
EH		 431const char *get_register_name_32(unsigned int reg)
432{
31ccdde2 433 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 434 return NULL;
435 }
8e8aba50 436 return x86_reg_info_32[reg].name;
8b4beddc
EH		 437}
438
c6dc6f63
AP		 439/* collects per-function cpuid data
440 */
441typedef struct model_features_t {
442 uint32_t *guest_feat;
443 uint32_t *host_feat;
bffd67b0 444 FeatureWord feat_word;
8b4beddc 445} model_features_t;
c6dc6f63 446
5fcca9ff
EH		 447/* KVM-specific features that are automatically added to all CPU models
448 * when KVM is enabled.
449 */
450static uint32_t kvm_default_features[FEATURE_WORDS] = {
451 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 452 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 453 (1 << KVM_FEATURE_CLOCKSOURCE2) |
454 (1 << KVM_FEATURE_ASYNC_PF) |
455 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 456 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 457 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 458 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 459};
dc59944b 460
136a7e9a
EH		 461/* Features that are not added by default to any CPU model when KVM is enabled.
462 */
463static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
464 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
465};
466
8fb4f821 467void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
dc59944b 468{
8fb4f821 469 kvm_default_features[w] &= ~features;
dc59944b
MT		 470}
471
84f1b92f
EH		 472/*
473 * Returns the set of feature flags that are supported and migratable by
474 * QEMU, for a given FeatureWord.
475 */
476static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
477{
478 FeatureWordInfo *wi = &feature_word_info[w];
479 uint32_t r = 0;
480 int i;
481
482 for (i = 0; i < 32; i++) {
483 uint32_t f = 1U << i;
484 /* If the feature name is unknown, it is not supported by QEMU yet */
485 if (!wi->feat_names[i]) {
486 continue;
487 }
488 /* Skip features known to QEMU, but explicitly marked as unmigratable */
489 if (wi->unmigratable_flags & f) {
490 continue;
491 }
492 r |= f;
493 }
494 return r;
495}
496
bb44e0d1
JK		 497void host_cpuid(uint32_t function, uint32_t count,
498 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 499{
a1fd24af
AL		 500 uint32_t vec[4];
501
502#ifdef __x86_64__
503 asm volatile("cpuid"
504 : "=a"(vec[0]), "=b"(vec[1]),
505 "=c"(vec[2]), "=d"(vec[3])
506 : "0"(function), "c"(count) : "cc");
c1f41226 507#elif defined(__i386__)
a1fd24af
AL		 508 asm volatile("pusha \n\t"
509 "cpuid \n\t"
510 "mov %%eax, 0(%2) \n\t"
511 "mov %%ebx, 4(%2) \n\t"
512 "mov %%ecx, 8(%2) \n\t"
513 "mov %%edx, 12(%2) \n\t"
514 "popa"
515 : : "a"(function), "c"(count), "S"(vec)
516 : "memory", "cc");
c1f41226
EH		 517#else
518 abort();
a1fd24af
AL		 519#endif
520
bdde476a 521 if (eax)
a1fd24af 522 *eax = vec[0];
bdde476a 523 if (ebx)
a1fd24af 524 *ebx = vec[1];
bdde476a 525 if (ecx)
a1fd24af 526 *ecx = vec[2];
bdde476a 527 if (edx)
a1fd24af 528 *edx = vec[3];
bdde476a 529}
c6dc6f63
AP		 530
531#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
532
533/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
534 * a substring. ex if !NULL points to the first char after a substring,
535 * otherwise the string is assumed to sized by a terminating nul.
536 * Return lexical ordering of *s1:*s2.
537 */
538static int sstrcmp(const char *s1, const char *e1, const char *s2,
539 const char *e2)
540{
541 for (;;) {
542 if (!*s1 || !*s2 || *s1 != *s2)
543 return (*s1 - *s2);
544 ++s1, ++s2;
545 if (s1 == e1 && s2 == e2)
546 return (0);
547 else if (s1 == e1)
548 return (*s2);
549 else if (s2 == e2)
550 return (*s1);
551 }
552}
553
554/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
555 * '|' delimited (possibly empty) strings in which case search for a match
556 * within the alternatives proceeds left to right. Return 0 for success,
557 * non-zero otherwise.
558 */
559static int altcmp(const char *s, const char *e, const char *altstr)
560{
561 const char *p, *q;
562
563 for (q = p = altstr; ; ) {
564 while (*p && *p != '|')
565 ++p;
566 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
567 return (0);
568 if (!*p)
569 return (1);
570 else
571 q = ++p;
572 }
573}
574
575/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 576 * *pval and return true, otherwise return false
c6dc6f63 577 */
e41e0fc6
JK		 578static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
579 const char **featureset)
c6dc6f63
AP		 580{
581 uint32_t mask;
582 const char **ppc;
e41e0fc6 583 bool found = false;
c6dc6f63 584
e41e0fc6 585 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 586 if (*ppc && !altcmp(s, e, *ppc)) {
587 *pval |= mask;
e41e0fc6 588 found = true;
c6dc6f63 589 }
e41e0fc6
JK		 590 }
591 return found;
c6dc6f63
AP		 592}
593
5ef57876
EH		 594static void add_flagname_to_bitmaps(const char *flagname,
595 FeatureWordArray words)
c6dc6f63 596{
5ef57876
EH		 597 FeatureWord w;
598 for (w = 0; w < FEATURE_WORDS; w++) {
599 FeatureWordInfo *wi = &feature_word_info[w];
600 if (wi->feat_names &&
601 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
602 break;
603 }
604 }
605 if (w == FEATURE_WORDS) {
606 fprintf(stderr, "CPU feature %s not found\n", flagname);
607 }
c6dc6f63
AP		 608}
609
d940ee9b
EH		 610/* CPU class name definitions: */
611
612#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
613#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
614
615/* Return type name for a given CPU model name
616 * Caller is responsible for freeing the returned string.
617 */
618static char *x86_cpu_type_name(const char *model_name)
619{
620 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
621}
622
500050d1
AF		 623static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
624{
d940ee9b
EH		 625 ObjectClass *oc;
626 char *typename;
627
500050d1
AF		 628 if (cpu_model == NULL) {
629 return NULL;
630 }
631
d940ee9b
EH		 632 typename = x86_cpu_type_name(cpu_model);
633 oc = object_class_by_name(typename);
634 g_free(typename);
635 return oc;
500050d1
AF		 636}
637
d940ee9b 638struct X86CPUDefinition {
c6dc6f63
AP		 639 const char *name;
640 uint32_t level;
90e4b0c3
EH		 641 uint32_t xlevel;
642 uint32_t xlevel2;
99b88a17
IM		 643 /* vendor is zero-terminated, 12 character ASCII string */
644 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 645 int family;
646 int model;
647 int stepping;
0514ef2f 648 FeatureWordArray features;
c6dc6f63 649 char model_id[48];
787aaf57 650 bool cache_info_passthrough;
d940ee9b 651};
c6dc6f63 652
9576de75 653static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 654 {
655 .name = "qemu64",
656 .level = 4,
99b88a17 657 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 658 .family = 6,
f8e6a11a 659 .model = 6,
c6dc6f63 660 .stepping = 3,
0514ef2f 661 .features[FEAT_1_EDX] =
27861ecc 662 PPRO_FEATURES |
c6dc6f63 663 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 664 CPUID_PSE36,
0514ef2f 665 .features[FEAT_1_ECX] =
27861ecc 666 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 667 .features[FEAT_8000_0001_EDX] =
27861ecc 668 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 669 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 670 .features[FEAT_8000_0001_ECX] =
27861ecc 671 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 672 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
673 .xlevel = 0x8000000A,
c6dc6f63
AP		 674 },
675 {
676 .name = "phenom",
677 .level = 5,
99b88a17 678 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 679 .family = 16,
680 .model = 2,
681 .stepping = 3,
0514ef2f 682 .features[FEAT_1_EDX] =
27861ecc 683 PPRO_FEATURES |
c6dc6f63 684 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 685 CPUID_PSE36 | CPUID_VME | CPUID_HT,
0514ef2f 686 .features[FEAT_1_ECX] =
27861ecc 687 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 688 CPUID_EXT_POPCNT,
0514ef2f 689 .features[FEAT_8000_0001_EDX] =
27861ecc 690 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 691 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
692 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 693 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 694 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
695 CPUID_EXT3_CR8LEG,
696 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
697 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 698 .features[FEAT_8000_0001_ECX] =
27861ecc 699 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 700 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
0514ef2f 701 .features[FEAT_SVM] =
27861ecc 702 CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 703 .xlevel = 0x8000001A,
704 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
705 },
706 {
707 .name = "core2duo",
708 .level = 10,
99b88a17 709 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 710 .family = 6,
711 .model = 15,
712 .stepping = 11,
0514ef2f 713 .features[FEAT_1_EDX] =
27861ecc 714 PPRO_FEATURES |
c6dc6f63 715 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 716 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
717 CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 718 .features[FEAT_1_ECX] =
27861ecc 719 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
8560efed
AJ		 720 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
721 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 722 .features[FEAT_8000_0001_EDX] =
27861ecc 723 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 724 .features[FEAT_8000_0001_ECX] =
27861ecc 725 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 726 .xlevel = 0x80000008,
727 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
728 },
729 {
730 .name = "kvm64",
731 .level = 5,
99b88a17 732 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 733 .family = 15,
734 .model = 6,
735 .stepping = 1,
736 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 737 .features[FEAT_1_EDX] =
27861ecc 738 PPRO_FEATURES |
c6dc6f63
AP		 739 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
740 CPUID_PSE36,
741 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 742 .features[FEAT_1_ECX] =
27861ecc 743 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 744 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 745 .features[FEAT_8000_0001_EDX] =
27861ecc 746 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 747 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
748 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
749 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
750 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
751 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 752 .features[FEAT_8000_0001_ECX] =
27861ecc 753 0,
c6dc6f63
AP		 754 .xlevel = 0x80000008,
755 .model_id = "Common KVM processor"
756 },
c6dc6f63
AP		 757 {
758 .name = "qemu32",
759 .level = 4,
99b88a17 760 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 761 .family = 6,
f8e6a11a 762 .model = 6,
c6dc6f63 763 .stepping = 3,
0514ef2f 764 .features[FEAT_1_EDX] =
27861ecc 765 PPRO_FEATURES,
0514ef2f 766 .features[FEAT_1_ECX] =
27861ecc 767 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 768 .xlevel = 0x80000004,
c6dc6f63 769 },
eafaf1e5
AP		 770 {
771 .name = "kvm32",
772 .level = 5,
99b88a17 773 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 774 .family = 15,
775 .model = 6,
776 .stepping = 1,
0514ef2f 777 .features[FEAT_1_EDX] =
27861ecc 778 PPRO_FEATURES |
eafaf1e5 779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 780 .features[FEAT_1_ECX] =
27861ecc 781 CPUID_EXT_SSE3,
0514ef2f 782 .features[FEAT_8000_0001_EDX] =
27861ecc 783 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 784 .features[FEAT_8000_0001_ECX] =
27861ecc 785 0,
eafaf1e5
AP		 786 .xlevel = 0x80000008,
787 .model_id = "Common 32-bit KVM processor"
788 },
c6dc6f63
AP		 789 {
790 .name = "coreduo",
791 .level = 10,
99b88a17 792 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 793 .family = 6,
794 .model = 14,
795 .stepping = 8,
0514ef2f 796 .features[FEAT_1_EDX] =
27861ecc 797 PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 798 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
799 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
0514ef2f 800 .features[FEAT_1_ECX] =
27861ecc 801 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
8560efed 802 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
0514ef2f 803 .features[FEAT_8000_0001_EDX] =
27861ecc 804 CPUID_EXT2_NX,
c6dc6f63
AP		 805 .xlevel = 0x80000008,
806 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
807 },
808 {
809 .name = "486",
58012d66 810 .level = 1,
99b88a17 811 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 812 .family = 4,
b2a856d9 813 .model = 8,
c6dc6f63 814 .stepping = 0,
0514ef2f 815 .features[FEAT_1_EDX] =
27861ecc 816 I486_FEATURES,
c6dc6f63
AP		 817 .xlevel = 0,
818 },
819 {
820 .name = "pentium",
821 .level = 1,
99b88a17 822 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 823 .family = 5,
824 .model = 4,
825 .stepping = 3,
0514ef2f 826 .features[FEAT_1_EDX] =
27861ecc 827 PENTIUM_FEATURES,
c6dc6f63
AP		 828 .xlevel = 0,
829 },
830 {
831 .name = "pentium2",
832 .level = 2,
99b88a17 833 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 834 .family = 6,
835 .model = 5,
836 .stepping = 2,
0514ef2f 837 .features[FEAT_1_EDX] =
27861ecc 838 PENTIUM2_FEATURES,
c6dc6f63
AP		 839 .xlevel = 0,
840 },
841 {
842 .name = "pentium3",
843 .level = 2,
99b88a17 844 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 845 .family = 6,
846 .model = 7,
847 .stepping = 3,
0514ef2f 848 .features[FEAT_1_EDX] =
27861ecc 849 PENTIUM3_FEATURES,
c6dc6f63
AP		 850 .xlevel = 0,
851 },
852 {
853 .name = "athlon",
854 .level = 2,
99b88a17 855 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 856 .family = 6,
857 .model = 2,
858 .stepping = 3,
0514ef2f 859 .features[FEAT_1_EDX] =
27861ecc 860 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 861 CPUID_MCA,
0514ef2f 862 .features[FEAT_8000_0001_EDX] =
27861ecc 863 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 864 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 865 .xlevel = 0x80000008,
c6dc6f63
AP		 866 },
867 {
868 .name = "n270",
869 /* original is on level 10 */
870 .level = 5,
99b88a17 871 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 872 .family = 6,
873 .model = 28,
874 .stepping = 2,
0514ef2f 875 .features[FEAT_1_EDX] =
27861ecc 876 PPRO_FEATURES |
8560efed
AJ		 877 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
878 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 879 /* Some CPUs got no CPUID_SEP */
0514ef2f 880 .features[FEAT_1_ECX] =
27861ecc 881 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236
BP		 882 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
883 CPUID_EXT_MOVBE,
0514ef2f 884 .features[FEAT_8000_0001_EDX] =
27861ecc 885 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 886 CPUID_EXT2_NX,
0514ef2f 887 .features[FEAT_8000_0001_ECX] =
27861ecc 888 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 889 .xlevel = 0x8000000A,
890 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
891 },
3eca4642
EH		 892 {
893 .name = "Conroe",
6b11322e 894 .level = 4,
99b88a17 895 .vendor = CPUID_VENDOR_INTEL,
3eca4642 896 .family = 6,
ffce9ebb 897 .model = 15,
3eca4642 898 .stepping = 3,
0514ef2f 899 .features[FEAT_1_EDX] =
27861ecc 900 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 901 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
902 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
903 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
904 CPUID_DE | CPUID_FP87,
0514ef2f 905 .features[FEAT_1_ECX] =
27861ecc 906 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 907 .features[FEAT_8000_0001_EDX] =
27861ecc 908 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 909 .features[FEAT_8000_0001_ECX] =
27861ecc 910 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 911 .xlevel = 0x8000000A,
912 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
913 },
914 {
915 .name = "Penryn",
6b11322e 916 .level = 4,
99b88a17 917 .vendor = CPUID_VENDOR_INTEL,
3eca4642 918 .family = 6,
ffce9ebb 919 .model = 23,
3eca4642 920 .stepping = 3,
0514ef2f 921 .features[FEAT_1_EDX] =
27861ecc 922 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 923 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
924 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
925 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
926 CPUID_DE | CPUID_FP87,
0514ef2f 927 .features[FEAT_1_ECX] =
27861ecc 928 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 929 CPUID_EXT_SSE3,
0514ef2f 930 .features[FEAT_8000_0001_EDX] =
27861ecc 931 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 932 .features[FEAT_8000_0001_ECX] =
27861ecc 933 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 934 .xlevel = 0x8000000A,
935 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
936 },
937 {
938 .name = "Nehalem",
6b11322e 939 .level = 4,
99b88a17 940 .vendor = CPUID_VENDOR_INTEL,
3eca4642 941 .family = 6,
ffce9ebb 942 .model = 26,
3eca4642 943 .stepping = 3,
0514ef2f 944 .features[FEAT_1_EDX] =
27861ecc 945 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 946 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
947 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
948 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
949 CPUID_DE | CPUID_FP87,
0514ef2f 950 .features[FEAT_1_ECX] =
27861ecc 951 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 952 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 953 .features[FEAT_8000_0001_EDX] =
27861ecc 954 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 955 .features[FEAT_8000_0001_ECX] =
27861ecc 956 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 957 .xlevel = 0x8000000A,
958 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
959 },
960 {
961 .name = "Westmere",
962 .level = 11,
99b88a17 963 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 964 .family = 6,
965 .model = 44,
966 .stepping = 1,
0514ef2f 967 .features[FEAT_1_EDX] =
27861ecc 968 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 969 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
970 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
971 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
972 CPUID_DE | CPUID_FP87,
0514ef2f 973 .features[FEAT_1_ECX] =
27861ecc 974 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 975 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
976 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 977 .features[FEAT_8000_0001_EDX] =
27861ecc 978 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 979 .features[FEAT_8000_0001_ECX] =
27861ecc 980 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 981 .xlevel = 0x8000000A,
982 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
983 },
984 {
985 .name = "SandyBridge",
986 .level = 0xd,
99b88a17 987 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 988 .family = 6,
989 .model = 42,
990 .stepping = 1,
0514ef2f 991 .features[FEAT_1_EDX] =
27861ecc 992 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 993 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
994 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
995 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
996 CPUID_DE | CPUID_FP87,
0514ef2f 997 .features[FEAT_1_ECX] =
27861ecc 998 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 999 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1000 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1001 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1002 CPUID_EXT_SSE3,
0514ef2f 1003 .features[FEAT_8000_0001_EDX] =
27861ecc 1004 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1005 CPUID_EXT2_SYSCALL,
0514ef2f 1006 .features[FEAT_8000_0001_ECX] =
27861ecc 1007 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1008 .xlevel = 0x8000000A,
1009 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1010 },
37507094
EH		 1011 {
1012 .name = "Haswell",
1013 .level = 0xd,
99b88a17 1014 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1015 .family = 6,
1016 .model = 60,
1017 .stepping = 1,
0514ef2f 1018 .features[FEAT_1_EDX] =
27861ecc 1019 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1020 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1021 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1022 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1023 CPUID_DE | CPUID_FP87,
0514ef2f 1024 .features[FEAT_1_ECX] =
27861ecc 1025 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1026 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1027 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1028 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1029 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1030 CPUID_EXT_PCID,
0514ef2f 1031 .features[FEAT_8000_0001_EDX] =
27861ecc 1032 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1033 CPUID_EXT2_SYSCALL,
0514ef2f 1034 .features[FEAT_8000_0001_ECX] =
27861ecc 1035 CPUID_EXT3_LAHF_LM,
0514ef2f 1036 .features[FEAT_7_0_EBX] =
27861ecc 1037 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 1038 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1039 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1040 CPUID_7_0_EBX_RTM,
1041 .xlevel = 0x8000000A,
1042 .model_id = "Intel Core Processor (Haswell)",
1043 },
3eca4642
EH		 1044 {
1045 .name = "Opteron_G1",
1046 .level = 5,
99b88a17 1047 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1048 .family = 15,
1049 .model = 6,
1050 .stepping = 1,
0514ef2f 1051 .features[FEAT_1_EDX] =
27861ecc 1052 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1053 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1054 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1055 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1056 CPUID_DE | CPUID_FP87,
0514ef2f 1057 .features[FEAT_1_ECX] =
27861ecc 1058 CPUID_EXT_SSE3,
0514ef2f 1059 .features[FEAT_8000_0001_EDX] =
27861ecc 1060 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1061 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1062 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1063 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1064 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1065 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1066 .xlevel = 0x80000008,
1067 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1068 },
1069 {
1070 .name = "Opteron_G2",
1071 .level = 5,
99b88a17 1072 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1073 .family = 15,
1074 .model = 6,
1075 .stepping = 1,
0514ef2f 1076 .features[FEAT_1_EDX] =
27861ecc 1077 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1078 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1079 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1080 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1081 CPUID_DE | CPUID_FP87,
0514ef2f 1082 .features[FEAT_1_ECX] =
27861ecc 1083 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1084 .features[FEAT_8000_0001_EDX] =
27861ecc 1085 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1086 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1087 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1088 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1089 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1090 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1091 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1092 .features[FEAT_8000_0001_ECX] =
27861ecc 1093 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1094 .xlevel = 0x80000008,
1095 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1096 },
1097 {
1098 .name = "Opteron_G3",
1099 .level = 5,
99b88a17 1100 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1101 .family = 15,
1102 .model = 6,
1103 .stepping = 1,
0514ef2f 1104 .features[FEAT_1_EDX] =
27861ecc 1105 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1106 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1107 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1108 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1109 CPUID_DE | CPUID_FP87,
0514ef2f 1110 .features[FEAT_1_ECX] =
27861ecc 1111 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1112 CPUID_EXT_SSE3,
0514ef2f 1113 .features[FEAT_8000_0001_EDX] =
27861ecc 1114 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1115 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1116 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1117 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1118 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1119 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1120 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1121 .features[FEAT_8000_0001_ECX] =
27861ecc 1122 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1123 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1124 .xlevel = 0x80000008,
1125 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1126 },
1127 {
1128 .name = "Opteron_G4",
1129 .level = 0xd,
99b88a17 1130 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1131 .family = 21,
1132 .model = 1,
1133 .stepping = 2,
0514ef2f 1134 .features[FEAT_1_EDX] =
27861ecc 1135 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1136 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1137 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1138 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1139 CPUID_DE | CPUID_FP87,
0514ef2f 1140 .features[FEAT_1_ECX] =
27861ecc 1141 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1142 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1143 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1144 CPUID_EXT_SSE3,
0514ef2f 1145 .features[FEAT_8000_0001_EDX] =
27861ecc 1146 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1147 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1148 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1149 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1150 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1151 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1152 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1153 .features[FEAT_8000_0001_ECX] =
27861ecc 1154 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1155 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1156 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1157 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1158 .xlevel = 0x8000001A,
1159 .model_id = "AMD Opteron 62xx class CPU",
1160 },
021941b9
AP		 1161 {
1162 .name = "Opteron_G5",
1163 .level = 0xd,
99b88a17 1164 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1165 .family = 21,
1166 .model = 2,
1167 .stepping = 0,
0514ef2f 1168 .features[FEAT_1_EDX] =
27861ecc 1169 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1170 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1171 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1172 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1173 CPUID_DE | CPUID_FP87,
0514ef2f 1174 .features[FEAT_1_ECX] =
27861ecc 1175 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1176 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1177 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1178 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1179 .features[FEAT_8000_0001_EDX] =
27861ecc 1180 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1181 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1182 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1183 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1184 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1185 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1186 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1187 .features[FEAT_8000_0001_ECX] =
27861ecc 1188 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1189 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1190 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1191 CPUID_EXT3_LAHF_LM,
021941b9
AP		 1192 .xlevel = 0x8000001A,
1193 .model_id = "AMD Opteron 63xx class CPU",
1194 },
c6dc6f63
AP		 1195};
1196
0668af54
EH		 1197/**
1198 * x86_cpu_compat_set_features:
1199 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1200 * @w: Identifies the feature word to be changed.
1201 * @feat_add: Feature bits to be added to feature word
1202 * @feat_remove: Feature bits to be removed from feature word
1203 *
1204 * Change CPU model feature bits for compatibility.
1205 *
1206 * This function may be used by machine-type compatibility functions
1207 * to enable or disable feature bits on specific CPU models.
1208 */
1209void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1210 uint32_t feat_add, uint32_t feat_remove)
1211{
9576de75 1212 X86CPUDefinition *def;
0668af54
EH		 1213 int i;
1214 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1215 def = &builtin_x86_defs[i];
1216 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1217 def->features[w] |= feat_add;
1218 def->features[w] &= ~feat_remove;
1219 }
1220 }
1221}
1222
d940ee9b
EH		 1223#ifdef CONFIG_KVM
1224
c6dc6f63
AP		 1225static int cpu_x86_fill_model_id(char *str)
1226{
1227 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1228 int i;
1229
1230 for (i = 0; i < 3; i++) {
1231 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1232 memcpy(str + i * 16 + 0, &eax, 4);
1233 memcpy(str + i * 16 + 4, &ebx, 4);
1234 memcpy(str + i * 16 + 8, &ecx, 4);
1235 memcpy(str + i * 16 + 12, &edx, 4);
1236 }
1237 return 0;
1238}
1239
d940ee9b
EH		 1240static X86CPUDefinition host_cpudef;
1241
84f1b92f 1242static Property host_x86_cpu_properties[] = {
120eee7d 1243 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1244 DEFINE_PROP_END_OF_LIST()
1245};
1246
d940ee9b 1247/* class_init for the "host" CPU model
6e746f30 1248 *
d940ee9b 1249 * This function may be called before KVM is initialized.
6e746f30 1250 */
d940ee9b 1251static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1252{
84f1b92f 1253 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1254 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1255 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1256
d940ee9b 1257 xcc->kvm_required = true;
6e746f30 1258
c6dc6f63 1259 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1260 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1261
1262 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1263 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1264 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1265 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1266
d940ee9b 1267 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1268
d940ee9b
EH		 1269 xcc->cpu_def = &host_cpudef;
1270 host_cpudef.cache_info_passthrough = true;
1271
1272 /* level, xlevel, xlevel2, and the feature words are initialized on
1273 * instance_init, because they require KVM to be initialized.
1274 */
84f1b92f
EH		 1275
1276 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1277}
1278
84f1b92f
EH		 1279static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1280 bool migratable_only);
1281
d940ee9b
EH		 1282static void host_x86_cpu_initfn(Object *obj)
1283{
1284 X86CPU *cpu = X86_CPU(obj);
1285 CPUX86State *env = &cpu->env;
1286 KVMState *s = kvm_state;
1287 FeatureWord w;
1288
1289 assert(kvm_enabled());
1290
1291 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1292 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1293 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1294
2bc65d2b 1295 for (w = 0; w < FEATURE_WORDS; w++) {
d940ee9b 1296 env->features[w] =
84f1b92f 1297 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2bc65d2b 1298 }
d940ee9b 1299 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1300}
1301
d940ee9b
EH		 1302static const TypeInfo host_x86_cpu_type_info = {
1303 .name = X86_CPU_TYPE_NAME("host"),
1304 .parent = TYPE_X86_CPU,
1305 .instance_init = host_x86_cpu_initfn,
1306 .class_init = host_x86_cpu_class_init,
1307};
1308
1309#endif
1310
8459e396 1311static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1312{
8459e396 1313 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1314 int i;
1315
857aee33 1316 for (i = 0; i < 32; ++i) {
c6dc6f63 1317 if (1 << i & mask) {
bffd67b0 1318 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1319 assert(reg);
fefb41bf 1320 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1321 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1322 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1323 f->cpuid_eax, reg,
1324 f->feat_names[i] ? "." : "",
1325 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1326 }
857aee33 1327 }
c6dc6f63
AP		 1328}
1329
95b8519d
AF		 1330static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1331 const char *name, Error **errp)
1332{
1333 X86CPU *cpu = X86_CPU(obj);
1334 CPUX86State *env = &cpu->env;
1335 int64_t value;
1336
1337 value = (env->cpuid_version >> 8) & 0xf;
1338 if (value == 0xf) {
1339 value += (env->cpuid_version >> 20) & 0xff;
1340 }
1341 visit_type_int(v, &value, name, errp);
1342}
1343
71ad61d3
AF		 1344static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1345 const char *name, Error **errp)
ed5e1ec3 1346{
71ad61d3
AF		 1347 X86CPU *cpu = X86_CPU(obj);
1348 CPUX86State *env = &cpu->env;
1349 const int64_t min = 0;
1350 const int64_t max = 0xff + 0xf;
65cd9064 1351 Error *local_err = NULL;
71ad61d3
AF		 1352 int64_t value;
1353
65cd9064
MA		 1354 visit_type_int(v, &value, name, &local_err);
1355 if (local_err) {
1356 error_propagate(errp, local_err);
71ad61d3
AF		 1357 return;
1358 }
1359 if (value < min || value > max) {
1360 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1361 name ? name : "null", value, min, max);
1362 return;
1363 }
1364
ed5e1ec3 1365 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1366 if (value > 0x0f) {
1367 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1368 } else {
71ad61d3 1369 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1370 }
1371}
1372
67e30c83
AF		 1373static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1374 const char *name, Error **errp)
1375{
1376 X86CPU *cpu = X86_CPU(obj);
1377 CPUX86State *env = &cpu->env;
1378 int64_t value;
1379
1380 value = (env->cpuid_version >> 4) & 0xf;
1381 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1382 visit_type_int(v, &value, name, errp);
1383}
1384
c5291a4f
AF		 1385static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1386 const char *name, Error **errp)
b0704cbd 1387{
c5291a4f
AF		 1388 X86CPU *cpu = X86_CPU(obj);
1389 CPUX86State *env = &cpu->env;
1390 const int64_t min = 0;
1391 const int64_t max = 0xff;
65cd9064 1392 Error *local_err = NULL;
c5291a4f
AF		 1393 int64_t value;
1394
65cd9064
MA		 1395 visit_type_int(v, &value, name, &local_err);
1396 if (local_err) {
1397 error_propagate(errp, local_err);
c5291a4f
AF		 1398 return;
1399 }
1400 if (value < min || value > max) {
1401 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1402 name ? name : "null", value, min, max);
1403 return;
1404 }
1405
b0704cbd 1406 env->cpuid_version &= ~0xf00f0;
c5291a4f 1407 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1408}
1409
35112e41
AF		 1410static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1411 void *opaque, const char *name,
1412 Error **errp)
1413{
1414 X86CPU *cpu = X86_CPU(obj);
1415 CPUX86State *env = &cpu->env;
1416 int64_t value;
1417
1418 value = env->cpuid_version & 0xf;
1419 visit_type_int(v, &value, name, errp);
1420}
1421
036e2222
AF		 1422static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1423 void *opaque, const char *name,
1424 Error **errp)
38c3dc46 1425{
036e2222
AF		 1426 X86CPU *cpu = X86_CPU(obj);
1427 CPUX86State *env = &cpu->env;
1428 const int64_t min = 0;
1429 const int64_t max = 0xf;
65cd9064 1430 Error *local_err = NULL;
036e2222
AF		 1431 int64_t value;
1432
65cd9064
MA		 1433 visit_type_int(v, &value, name, &local_err);
1434 if (local_err) {
1435 error_propagate(errp, local_err);
036e2222
AF		 1436 return;
1437 }
1438 if (value < min || value > max) {
1439 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1440 name ? name : "null", value, min, max);
1441 return;
1442 }
1443
38c3dc46 1444 env->cpuid_version &= ~0xf;
036e2222 1445 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1446}
1447
8e1898bf
AF		 1448static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1449 const char *name, Error **errp)
1450{
1451 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1452
fa029887 1453 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1454}
1455
1456static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1457 const char *name, Error **errp)
1458{
1459 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1460
fa029887 1461 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1462}
1463
16b93aa8
AF		 1464static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1465 const char *name, Error **errp)
1466{
1467 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1468
fa029887 1469 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1470}
1471
1472static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1473 const char *name, Error **errp)
1474{
1475 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1476
fa029887 1477 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1478}
1479
d480e1af
AF		 1480static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1481{
1482 X86CPU *cpu = X86_CPU(obj);
1483 CPUX86State *env = &cpu->env;
1484 char *value;
d480e1af 1485
9df694ee 1486 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1487 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1488 env->cpuid_vendor3);
d480e1af
AF		 1489 return value;
1490}
1491
1492static void x86_cpuid_set_vendor(Object *obj, const char *value,
1493 Error **errp)
1494{
1495 X86CPU *cpu = X86_CPU(obj);
1496 CPUX86State *env = &cpu->env;
1497 int i;
1498
9df694ee 1499 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1500 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1501 "vendor", value);
1502 return;
1503 }
1504
1505 env->cpuid_vendor1 = 0;
1506 env->cpuid_vendor2 = 0;
1507 env->cpuid_vendor3 = 0;
1508 for (i = 0; i < 4; i++) {
1509 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1510 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1511 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1512 }
d480e1af
AF		 1513}
1514
63e886eb
AF		 1515static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1516{
1517 X86CPU *cpu = X86_CPU(obj);
1518 CPUX86State *env = &cpu->env;
1519 char *value;
1520 int i;
1521
1522 value = g_malloc(48 + 1);
1523 for (i = 0; i < 48; i++) {
1524 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1525 }
1526 value[48] = '\0';
1527 return value;
1528}
1529
938d4c25
AF		 1530static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1531 Error **errp)
dcce6675 1532{
938d4c25
AF		 1533 X86CPU *cpu = X86_CPU(obj);
1534 CPUX86State *env = &cpu->env;
dcce6675
AF		 1535 int c, len, i;
1536
1537 if (model_id == NULL) {
1538 model_id = "";
1539 }
1540 len = strlen(model_id);
d0a6acf4 1541 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1542 for (i = 0; i < 48; i++) {
1543 if (i >= len) {
1544 c = '\0';
1545 } else {
1546 c = (uint8_t)model_id[i];
1547 }
1548 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1549 }
1550}
1551
89e48965
AF		 1552static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1553 const char *name, Error **errp)
1554{
1555 X86CPU *cpu = X86_CPU(obj);
1556 int64_t value;
1557
1558 value = cpu->env.tsc_khz * 1000;
1559 visit_type_int(v, &value, name, errp);
1560}
1561
1562static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1563 const char *name, Error **errp)
1564{
1565 X86CPU *cpu = X86_CPU(obj);
1566 const int64_t min = 0;
2e84849a 1567 const int64_t max = INT64_MAX;
65cd9064 1568 Error *local_err = NULL;
89e48965
AF		 1569 int64_t value;
1570
65cd9064
MA		 1571 visit_type_int(v, &value, name, &local_err);
1572 if (local_err) {
1573 error_propagate(errp, local_err);
89e48965
AF		 1574 return;
1575 }
1576 if (value < min || value > max) {
1577 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1578 name ? name : "null", value, min, max);
1579 return;
1580 }
1581
1582 cpu->env.tsc_khz = value / 1000;
1583}
1584
31050930
IM		 1585static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1586 const char *name, Error **errp)
1587{
1588 X86CPU *cpu = X86_CPU(obj);
1589 int64_t value = cpu->env.cpuid_apic_id;
1590
1591 visit_type_int(v, &value, name, errp);
1592}
1593
1594static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1595 const char *name, Error **errp)
1596{
1597 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1598 DeviceState *dev = DEVICE(obj);
31050930
IM		 1599 const int64_t min = 0;
1600 const int64_t max = UINT32_MAX;
1601 Error *error = NULL;
1602 int64_t value;
1603
8d6d4980
IM		 1604 if (dev->realized) {
1605 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1606 "it was realized", name, object_get_typename(obj));
1607 return;
1608 }
1609
31050930
IM		 1610 visit_type_int(v, &value, name, &error);
1611 if (error) {
1612 error_propagate(errp, error);
1613 return;
1614 }
1615 if (value < min || value > max) {
1616 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1617 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1618 object_get_typename(obj), name, value, min, max);
1619 return;
1620 }
1621
1622 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1623 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1624 return;
1625 }
1626 cpu->env.cpuid_apic_id = value;
1627}
1628
7e5292b5 1629/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1630static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1631 const char *name, Error **errp)
1632{
7e5292b5 1633 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1634 FeatureWord w;
1635 Error *err = NULL;
1636 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1637 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1638 X86CPUFeatureWordInfoList *list = NULL;
1639
1640 for (w = 0; w < FEATURE_WORDS; w++) {
1641 FeatureWordInfo *wi = &feature_word_info[w];
1642 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1643 qwi->cpuid_input_eax = wi->cpuid_eax;
1644 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1645 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1646 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1647 qwi->features = array[w];
8e8aba50
EH		 1648
1649 /* List will be in reverse order, but order shouldn't matter */
1650 list_entries[w].next = list;
1651 list_entries[w].value = &word_infos[w];
1652 list = &list_entries[w];
1653 }
1654
1655 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1656 error_propagate(errp, err);
1657}
1658
c8f0f88e
IM		 1659static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1660 const char *name, Error **errp)
1661{
1662 X86CPU *cpu = X86_CPU(obj);
1663 int64_t value = cpu->hyperv_spinlock_attempts;
1664
1665 visit_type_int(v, &value, name, errp);
1666}
1667
1668static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1669 const char *name, Error **errp)
1670{
1671 const int64_t min = 0xFFF;
1672 const int64_t max = UINT_MAX;
1673 X86CPU *cpu = X86_CPU(obj);
1674 Error *err = NULL;
1675 int64_t value;
1676
1677 visit_type_int(v, &value, name, &err);
1678 if (err) {
1679 error_propagate(errp, err);
1680 return;
1681 }
1682
1683 if (value < min || value > max) {
1684 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1685 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1686 object_get_typename(obj), name ? name : "null",
1687 value, min, max);
1688 return;
1689 }
1690 cpu->hyperv_spinlock_attempts = value;
1691}
1692
1693static PropertyInfo qdev_prop_spinlocks = {
1694 .name = "int",
1695 .get = x86_get_hv_spinlocks,
1696 .set = x86_set_hv_spinlocks,
1697};
1698
72ac2e87
IM		 1699/* Convert all '_' in a feature string option name to '-', to make feature
1700 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1701 */
1702static inline void feat2prop(char *s)
1703{
1704 while ((s = strchr(s, '_'))) {
1705 *s = '-';
1706 }
1707}
1708
8f961357
EH		 1709/* Parse "+feature,-feature,feature=foo" CPU feature string
1710 */
94a444b2
AF		 1711static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1712 Error **errp)
8f961357 1713{
94a444b2 1714 X86CPU *cpu = X86_CPU(cs);
8f961357 1715 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1716 FeatureWord w;
8f961357 1717 /* Features to be added */
077c68c3 1718 FeatureWordArray plus_features = { 0 };
8f961357 1719 /* Features to be removed */
5ef57876 1720 FeatureWordArray minus_features = { 0 };
8f961357 1721 uint32_t numvalue;
a91987c2 1722 CPUX86State *env = &cpu->env;
94a444b2 1723 Error *local_err = NULL;
8f961357 1724
8f961357 1725 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1726
1727 while (featurestr) {
1728 char *val;
1729 if (featurestr[0] == '+') {
5ef57876 1730 add_flagname_to_bitmaps(featurestr + 1, plus_features);
c6dc6f63 1731 } else if (featurestr[0] == '-') {
5ef57876 1732 add_flagname_to_bitmaps(featurestr + 1, minus_features);
c6dc6f63
AP		 1733 } else if ((val = strchr(featurestr, '='))) {
1734 *val = 0; val++;
72ac2e87 1735 feat2prop(featurestr);
d024d209 1736 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1737 char *err;
a91987c2
IM		 1738 char num[32];
1739
c6dc6f63
AP		 1740 numvalue = strtoul(val, &err, 0);
1741 if (!*val || *err) {
6b1dd54b
PB		 1742 error_setg(errp, "bad numerical value %s", val);
1743 return;
c6dc6f63
AP		 1744 }
1745 if (numvalue < 0x80000000) {
94a444b2
AF		 1746 error_report("xlevel value shall always be >= 0x80000000"
1747 ", fixup will be removed in future versions");
2f7a21c4 1748 numvalue += 0x80000000;
c6dc6f63 1749 }
a91987c2 1750 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1751 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1752 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1753 int64_t tsc_freq;
1754 char *err;
a91987c2 1755 char num[32];
b862d1fe
JR		 1756
1757 tsc_freq = strtosz_suffix_unit(val, &err,
1758 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1759 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1760 error_setg(errp, "bad numerical value %s", val);
1761 return;
b862d1fe 1762 }
a91987c2 1763 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1764 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1765 &local_err);
72ac2e87 1766 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1767 char *err;
92067bf4 1768 const int min = 0xFFF;
c8f0f88e 1769 char num[32];
28f52cc0
VR		 1770 numvalue = strtoul(val, &err, 0);
1771 if (!*val || *err) {
6b1dd54b
PB		 1772 error_setg(errp, "bad numerical value %s", val);
1773 return;
28f52cc0 1774 }
92067bf4 1775 if (numvalue < min) {
94a444b2
AF		 1776 error_report("hv-spinlocks value shall always be >= 0x%x"
1777 ", fixup will be removed in future versions",
92067bf4
IM		 1778 min);
1779 numvalue = min;
1780 }
c8f0f88e 1781 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1782 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1783 } else {
94a444b2 1784 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1785 }
c6dc6f63 1786 } else {
258f5abe 1787 feat2prop(featurestr);
94a444b2 1788 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1789 }
94a444b2
AF		 1790 if (local_err) {
1791 error_propagate(errp, local_err);
6b1dd54b 1792 return;
c6dc6f63
AP		 1793 }
1794 featurestr = strtok(NULL, ",");
1795 }
e1c224b4
EH		 1796
1797 for (w = 0; w < FEATURE_WORDS; w++) {
1798 env->features[w] |= plus_features[w];
1799 env->features[w] &= ~minus_features[w];
1800 }
c6dc6f63
AP		 1801}
1802
1803/* generate a composite string into buf of all cpuid names in featureset
1804 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1805 * if flags, suppress names undefined in featureset.
1806 */
1807static void listflags(char *buf, int bufsize, uint32_t fbits,
1808 const char **featureset, uint32_t flags)
1809{
1810 const char **p = &featureset[31];
1811 char *q, *b, bit;
1812 int nc;
1813
1814 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1815 *buf = '\0';
1816 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1817 if (fbits & 1 << bit && (*p || !flags)) {
1818 if (*p)
1819 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1820 else
1821 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1822 if (bufsize <= nc) {
1823 if (b) {
1824 memcpy(b, "...", sizeof("..."));
1825 }
1826 return;
1827 }
1828 q += nc;
1829 bufsize -= nc;
1830 }
1831}
1832
e916cbf8
PM		 1833/* generate CPU information. */
1834void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1835{
9576de75 1836 X86CPUDefinition *def;
c6dc6f63 1837 char buf[256];
7fc9b714 1838 int i;
c6dc6f63 1839
7fc9b714
AF		 1840 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1841 def = &builtin_x86_defs[i];
c04321b3 1842 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1843 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1844 }
21ad7789
JK		 1845#ifdef CONFIG_KVM
1846 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1847 "KVM processor with all supported host features "
1848 "(only available in KVM mode)");
1849#endif
1850
6cdf8854 1851 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1852 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1853 FeatureWordInfo *fw = &feature_word_info[i];
1854
1855 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1856 (*cpu_fprintf)(f, " %s\n", buf);
1857 }
c6dc6f63
AP		 1858}
1859
76b64a7a 1860CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1861{
1862 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1863 X86CPUDefinition *def;
7fc9b714 1864 int i;
e3966126 1865
7fc9b714 1866 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1867 CpuDefinitionInfoList *entry;
1868 CpuDefinitionInfo *info;
1869
7fc9b714 1870 def = &builtin_x86_defs[i];
e3966126
AL		 1871 info = g_malloc0(sizeof(*info));
1872 info->name = g_strdup(def->name);
1873
1874 entry = g_malloc0(sizeof(*entry));
1875 entry->value = info;
1876 entry->next = cpu_list;
1877 cpu_list = entry;
1878 }
1879
1880 return cpu_list;
1881}
1882
84f1b92f
EH		 1883static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1884 bool migratable_only)
27418adf
EH		 1885{
1886 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 1887 uint32_t r;
27418adf 1888
fefb41bf 1889 if (kvm_enabled()) {
84f1b92f
EH		 1890 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1891 wi->cpuid_ecx,
1892 wi->cpuid_reg);
fefb41bf 1893 } else if (tcg_enabled()) {
84f1b92f 1894 r = wi->tcg_features;
fefb41bf
EH		 1895 } else {
1896 return ~0;
1897 }
84f1b92f
EH		 1898 if (migratable_only) {
1899 r &= x86_cpu_get_migratable_flags(w);
1900 }
1901 return r;
27418adf
EH		 1902}
1903
51f63aed
EH		 1904/*
1905 * Filters CPU feature words based on host availability of each feature.
1906 *
51f63aed
EH		 1907 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1908 */
27418adf 1909static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 1910{
1911 CPUX86State *env = &cpu->env;
bd87d2a2 1912 FeatureWord w;
51f63aed
EH		 1913 int rv = 0;
1914
bd87d2a2 1915 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 1916 uint32_t host_feat =
1917 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 1918 uint32_t requested_features = env->features[w];
1919 env->features[w] &= host_feat;
1920 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 1921 if (cpu->filtered_features[w]) {
1922 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 1923 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 1924 }
1925 rv = 1;
1926 }
bd87d2a2 1927 }
51f63aed
EH		 1928
1929 return rv;
bc74b7db 1930}
bc74b7db 1931
d940ee9b 1932/* Load data from X86CPUDefinition
c080e30e 1933 */
d940ee9b 1934static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1935{
61dcd775 1936 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1937 const char *vendor;
1938 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 1939 FeatureWord w;
c6dc6f63 1940
2d64255b
AF		 1941 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1942 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1943 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1944 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 1945 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 1946 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1947 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 1948 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 1949 for (w = 0; w < FEATURE_WORDS; w++) {
1950 env->features[w] = def->features[w];
1951 }
82beb536 1952
9576de75 1953 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 1954 if (kvm_enabled()) {
5fcca9ff
EH		 1955 FeatureWord w;
1956 for (w = 0; w < FEATURE_WORDS; w++) {
1957 env->features[w] |= kvm_default_features[w];
136a7e9a 1958 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 1959 }
82beb536 1960 }
5fcca9ff 1961
82beb536 1962 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 1963
1964 /* sysenter isn't supported in compatibility mode on AMD,
1965 * syscall isn't supported in compatibility mode on Intel.
1966 * Normally we advertise the actual CPU vendor, but you can
1967 * override this using the 'vendor' property if you want to use
1968 * KVM's sysenter/syscall emulation in compatibility mode and
1969 * when doing cross vendor migration
1970 */
74f54bc4 1971 vendor = def->vendor;
7c08db30
EH		 1972 if (kvm_enabled()) {
1973 uint32_t ebx = 0, ecx = 0, edx = 0;
1974 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1975 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1976 vendor = host_vendor;
1977 }
1978
1979 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1980
c6dc6f63
AP		 1981}
1982
62fc403f
IM		 1983X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1984 Error **errp)
5c3c6a68 1985{
2d64255b 1986 X86CPU *cpu = NULL;
d940ee9b 1987 X86CPUClass *xcc;
500050d1 1988 ObjectClass *oc;
2d64255b
AF		 1989 gchar **model_pieces;
1990 char *name, *features;
5c3c6a68
AF		 1991 Error *error = NULL;
1992
2d64255b
AF		 1993 model_pieces = g_strsplit(cpu_model, ",", 2);
1994 if (!model_pieces[0]) {
1995 error_setg(&error, "Invalid/empty CPU model name");
1996 goto out;
1997 }
1998 name = model_pieces[0];
1999 features = model_pieces[1];
2000
500050d1
AF		 2001 oc = x86_cpu_class_by_name(name);
2002 if (oc == NULL) {
2003 error_setg(&error, "Unable to find CPU definition: %s", name);
2004 goto out;
2005 }
d940ee9b
EH		 2006 xcc = X86_CPU_CLASS(oc);
2007
2008 if (xcc->kvm_required && !kvm_enabled()) {
2009 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2010 goto out;
2011 }
2012
d940ee9b
EH		 2013 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2014
62fc403f
IM		 2015#ifndef CONFIG_USER_ONLY
2016 if (icc_bridge == NULL) {
2017 error_setg(&error, "Invalid icc-bridge value");
2018 goto out;
2019 }
2020 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2021 object_unref(OBJECT(cpu));
2022#endif
5c3c6a68 2023
94a444b2 2024 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2025 if (error) {
2026 goto out;
5c3c6a68
AF		 2027 }
2028
7f833247 2029out:
cd7b87ff
AF		 2030 if (error != NULL) {
2031 error_propagate(errp, error);
500050d1
AF		 2032 if (cpu) {
2033 object_unref(OBJECT(cpu));
2034 cpu = NULL;
2035 }
cd7b87ff 2036 }
7f833247
IM		 2037 g_strfreev(model_pieces);
2038 return cpu;
2039}
2040
2041X86CPU *cpu_x86_init(const char *cpu_model)
2042{
2043 Error *error = NULL;
2044 X86CPU *cpu;
2045
62fc403f 2046 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 2047 if (error) {
2d64255b
AF		 2048 goto out;
2049 }
2050
7f833247
IM		 2051 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2052
2d64255b 2053out:
2d64255b 2054 if (error) {
4a44d85e 2055 error_report("%s", error_get_pretty(error));
5c3c6a68 2056 error_free(error);
2d64255b
AF		 2057 if (cpu != NULL) {
2058 object_unref(OBJECT(cpu));
2059 cpu = NULL;
2060 }
5c3c6a68
AF		 2061 }
2062 return cpu;
2063}
2064
d940ee9b
EH		 2065static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2066{
2067 X86CPUDefinition *cpudef = data;
2068 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2069
2070 xcc->cpu_def = cpudef;
2071}
2072
2073static void x86_register_cpudef_type(X86CPUDefinition *def)
2074{
2075 char *typename = x86_cpu_type_name(def->name);
2076 TypeInfo ti = {
2077 .name = typename,
2078 .parent = TYPE_X86_CPU,
2079 .class_init = x86_cpu_cpudef_class_init,
2080 .class_data = def,
2081 };
2082
2083 type_register(&ti);
2084 g_free(typename);
2085}
2086
c6dc6f63 2087#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2088
0e26b7b8
BS		 2089void cpu_clear_apic_feature(CPUX86State *env)
2090{
0514ef2f 2091 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2092}
2093
c6dc6f63
AP		 2094#endif /* !CONFIG_USER_ONLY */
2095
c04321b3 2096/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2097 */
2098void x86_cpudef_setup(void)
2099{
93bfef4c
CV		 2100 int i, j;
2101 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2102
2103 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2104 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2105
2106 /* Look for specific "cpudef" models that */
09faecf2 2107 /* have the QEMU version in .model_id */
93bfef4c 2108 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2109 if (strcmp(model_with_versions[j], def->name) == 0) {
2110 pstrcpy(def->model_id, sizeof(def->model_id),
2111 "QEMU Virtual CPU version ");
2112 pstrcat(def->model_id, sizeof(def->model_id),
2113 qemu_get_version());
93bfef4c
CV		 2114 break;
2115 }
2116 }
c6dc6f63 2117 }
c6dc6f63
AP		 2118}
2119
c6dc6f63
AP		 2120static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2121 uint32_t *ecx, uint32_t *edx)
2122{
2123 *ebx = env->cpuid_vendor1;
2124 *edx = env->cpuid_vendor2;
2125 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2126}
2127
2128void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2129 uint32_t *eax, uint32_t *ebx,
2130 uint32_t *ecx, uint32_t *edx)
2131{
a60f24b5
AF		 2132 X86CPU *cpu = x86_env_get_cpu(env);
2133 CPUState *cs = CPU(cpu);
2134
c6dc6f63
AP		 2135 /* test if maximum index reached */
2136 if (index & 0x80000000) {
b3baa152
BW		 2137 if (index > env->cpuid_xlevel) {
2138 if (env->cpuid_xlevel2 > 0) {
2139 /* Handle the Centaur's CPUID instruction. */
2140 if (index > env->cpuid_xlevel2) {
2141 index = env->cpuid_xlevel2;
2142 } else if (index < 0xC0000000) {
2143 index = env->cpuid_xlevel;
2144 }
2145 } else {
57f26ae7
EH		 2146 /* Intel documentation states that invalid EAX input will
2147 * return the same information as EAX=cpuid_level
2148 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2149 */
2150 index = env->cpuid_level;
b3baa152
BW		 2151 }
2152 }
c6dc6f63
AP		 2153 } else {
2154 if (index > env->cpuid_level)
2155 index = env->cpuid_level;
2156 }
2157
2158 switch(index) {
2159 case 0:
2160 *eax = env->cpuid_level;
2161 get_cpuid_vendor(env, ebx, ecx, edx);
2162 break;
2163 case 1:
2164 *eax = env->cpuid_version;
2165 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2166 *ecx = env->features[FEAT_1_ECX];
2167 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2168 if (cs->nr_cores * cs->nr_threads > 1) {
2169 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2170 *edx |= 1 << 28; /* HTT bit */
2171 }
2172 break;
2173 case 2:
2174 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2175 if (cpu->cache_info_passthrough) {
2176 host_cpuid(index, 0, eax, ebx, ecx, edx);
2177 break;
2178 }
5e891bf8 2179 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2180 *ebx = 0;
2181 *ecx = 0;
5e891bf8
EH		 2182 *edx = (L1D_DESCRIPTOR << 16) | \
2183 (L1I_DESCRIPTOR << 8) | \
2184 (L2_DESCRIPTOR);
c6dc6f63
AP		 2185 break;
2186 case 4:
2187 /* cache info: needed for Core compatibility */
787aaf57
BC		 2188 if (cpu->cache_info_passthrough) {
2189 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2190 *eax &= ~0xFC000000;
c6dc6f63 2191 } else {
2f7a21c4 2192 *eax = 0;
76c2975a 2193 switch (count) {
c6dc6f63 2194 case 0: /* L1 dcache info */
5e891bf8
EH		 2195 *eax |= CPUID_4_TYPE_DCACHE | \
2196 CPUID_4_LEVEL(1) | \
2197 CPUID_4_SELF_INIT_LEVEL;
2198 *ebx = (L1D_LINE_SIZE - 1) | \
2199 ((L1D_PARTITIONS - 1) << 12) | \
2200 ((L1D_ASSOCIATIVITY - 1) << 22);
2201 *ecx = L1D_SETS - 1;
2202 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2203 break;
2204 case 1: /* L1 icache info */
5e891bf8
EH		 2205 *eax |= CPUID_4_TYPE_ICACHE | \
2206 CPUID_4_LEVEL(1) | \
2207 CPUID_4_SELF_INIT_LEVEL;
2208 *ebx = (L1I_LINE_SIZE - 1) | \
2209 ((L1I_PARTITIONS - 1) << 12) | \
2210 ((L1I_ASSOCIATIVITY - 1) << 22);
2211 *ecx = L1I_SETS - 1;
2212 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2213 break;
2214 case 2: /* L2 cache info */
5e891bf8
EH		 2215 *eax |= CPUID_4_TYPE_UNIFIED | \
2216 CPUID_4_LEVEL(2) | \
2217 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2218 if (cs->nr_threads > 1) {
2219 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2220 }
5e891bf8
EH		 2221 *ebx = (L2_LINE_SIZE - 1) | \
2222 ((L2_PARTITIONS - 1) << 12) | \
2223 ((L2_ASSOCIATIVITY - 1) << 22);
2224 *ecx = L2_SETS - 1;
2225 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2226 break;
2227 default: /* end of info */
2228 *eax = 0;
2229 *ebx = 0;
2230 *ecx = 0;
2231 *edx = 0;
2232 break;
76c2975a
PB		 2233 }
2234 }
2235
2236 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2237 if ((*eax & 31) && cs->nr_cores > 1) {
2238 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2239 }
2240 break;
2241 case 5:
2242 /* mwait info: needed for Core compatibility */
2243 *eax = 0; /* Smallest monitor-line size in bytes */
2244 *ebx = 0; /* Largest monitor-line size in bytes */
2245 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2246 *edx = 0;
2247 break;
2248 case 6:
2249 /* Thermal and Power Leaf */
2250 *eax = 0;
2251 *ebx = 0;
2252 *ecx = 0;
2253 *edx = 0;
2254 break;
f7911686 2255 case 7:
13526728
EH		 2256 /* Structured Extended Feature Flags Enumeration Leaf */
2257 if (count == 0) {
2258 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2259 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2260 *ecx = 0; /* Reserved */
2261 *edx = 0; /* Reserved */
f7911686
YW		 2262 } else {
2263 *eax = 0;
2264 *ebx = 0;
2265 *ecx = 0;
2266 *edx = 0;
2267 }
2268 break;
c6dc6f63
AP		 2269 case 9:
2270 /* Direct Cache Access Information Leaf */
2271 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2272 *ebx = 0;
2273 *ecx = 0;
2274 *edx = 0;
2275 break;
2276 case 0xA:
2277 /* Architectural Performance Monitoring Leaf */
9337e3b6 2278 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2279 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2280
2281 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2282 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2283 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2284 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2285 } else {
2286 *eax = 0;
2287 *ebx = 0;
2288 *ecx = 0;
2289 *edx = 0;
2290 }
c6dc6f63 2291 break;
2560f19f
PB		 2292 case 0xD: {
2293 KVMState *s = cs->kvm_state;
2294 uint64_t kvm_mask;
2295 int i;
2296
51e49430 2297 /* Processor Extended State */
2560f19f
PB		 2298 *eax = 0;
2299 *ebx = 0;
2300 *ecx = 0;
2301 *edx = 0;
2302 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2303 break;
2304 }
2560f19f
PB		 2305 kvm_mask =
2306 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2307 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2308
2560f19f
PB		 2309 if (count == 0) {
2310 *ecx = 0x240;
2311 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2312 const ExtSaveArea *esa = &ext_save_areas[i];
2313 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2314 (kvm_mask & (1 << i)) != 0) {
2315 if (i < 32) {
2316 *eax |= 1 << i;
2317 } else {
2318 *edx |= 1 << (i - 32);
2319 }
2320 *ecx = MAX(*ecx, esa->offset + esa->size);
2321 }
2322 }
2323 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2324 *ebx = *ecx;
2325 } else if (count == 1) {
2326 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2327 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2328 const ExtSaveArea *esa = &ext_save_areas[count];
2329 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2330 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2331 *eax = esa->size;
2332 *ebx = esa->offset;
2560f19f 2333 }
51e49430
SY		 2334 }
2335 break;
2560f19f 2336 }
c6dc6f63
AP		 2337 case 0x80000000:
2338 *eax = env->cpuid_xlevel;
2339 *ebx = env->cpuid_vendor1;
2340 *edx = env->cpuid_vendor2;
2341 *ecx = env->cpuid_vendor3;
2342 break;
2343 case 0x80000001:
2344 *eax = env->cpuid_version;
2345 *ebx = 0;
0514ef2f
EH		 2346 *ecx = env->features[FEAT_8000_0001_ECX];
2347 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2348
2349 /* The Linux kernel checks for the CMPLegacy bit and
2350 * discards multiple thread information if it is set.
2351 * So dont set it here for Intel to make Linux guests happy.
2352 */
ce3960eb 2353 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2354 uint32_t tebx, tecx, tedx;
2355 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2356 if (tebx != CPUID_VENDOR_INTEL_1 ||
2357 tedx != CPUID_VENDOR_INTEL_2 ||
2358 tecx != CPUID_VENDOR_INTEL_3) {
2359 *ecx |= 1 << 1; /* CmpLegacy bit */
2360 }
2361 }
c6dc6f63
AP		 2362 break;
2363 case 0x80000002:
2364 case 0x80000003:
2365 case 0x80000004:
2366 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2367 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2368 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2369 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2370 break;
2371 case 0x80000005:
2372 /* cache info (L1 cache) */
787aaf57
BC		 2373 if (cpu->cache_info_passthrough) {
2374 host_cpuid(index, 0, eax, ebx, ecx, edx);
2375 break;
2376 }
5e891bf8
EH		 2377 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2378 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2379 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2380 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2381 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2382 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2383 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2384 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2385 break;
2386 case 0x80000006:
2387 /* cache info (L2 cache) */
787aaf57
BC		 2388 if (cpu->cache_info_passthrough) {
2389 host_cpuid(index, 0, eax, ebx, ecx, edx);
2390 break;
2391 }
5e891bf8
EH		 2392 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2393 (L2_DTLB_2M_ENTRIES << 16) | \
2394 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2395 (L2_ITLB_2M_ENTRIES);
2396 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2397 (L2_DTLB_4K_ENTRIES << 16) | \
2398 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2399 (L2_ITLB_4K_ENTRIES);
2400 *ecx = (L2_SIZE_KB_AMD << 16) | \
2401 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2402 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2403 *edx = ((L3_SIZE_KB/512) << 18) | \
2404 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2405 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2406 break;
303752a9
MT		 2407 case 0x80000007:
2408 *eax = 0;
2409 *ebx = 0;
2410 *ecx = 0;
2411 *edx = env->features[FEAT_8000_0007_EDX];
2412 break;
c6dc6f63
AP		 2413 case 0x80000008:
2414 /* virtual & phys address size in low 2 bytes. */
2415/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2416 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2417 /* 64 bit processor */
2418/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2419 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2420 } else {
0514ef2f 2421 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2422 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2423 } else {
c6dc6f63 2424 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2425 }
c6dc6f63
AP		 2426 }
2427 *ebx = 0;
2428 *ecx = 0;
2429 *edx = 0;
ce3960eb
AF		 2430 if (cs->nr_cores * cs->nr_threads > 1) {
2431 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2432 }
2433 break;
2434 case 0x8000000A:
0514ef2f 2435 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2436 *eax = 0x00000001; /* SVM Revision */
2437 *ebx = 0x00000010; /* nr of ASIDs */
2438 *ecx = 0;
0514ef2f 2439 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2440 } else {
2441 *eax = 0;
2442 *ebx = 0;
2443 *ecx = 0;
2444 *edx = 0;
2445 }
c6dc6f63 2446 break;
b3baa152
BW		 2447 case 0xC0000000:
2448 *eax = env->cpuid_xlevel2;
2449 *ebx = 0;
2450 *ecx = 0;
2451 *edx = 0;
2452 break;
2453 case 0xC0000001:
2454 /* Support for VIA CPU's CPUID instruction */
2455 *eax = env->cpuid_version;
2456 *ebx = 0;
2457 *ecx = 0;
0514ef2f 2458 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2459 break;
2460 case 0xC0000002:
2461 case 0xC0000003:
2462 case 0xC0000004:
2463 /* Reserved for the future, and now filled with zero */
2464 *eax = 0;
2465 *ebx = 0;
2466 *ecx = 0;
2467 *edx = 0;
2468 break;
c6dc6f63
AP		 2469 default:
2470 /* reserved values: zero */
2471 *eax = 0;
2472 *ebx = 0;
2473 *ecx = 0;
2474 *edx = 0;
2475 break;
2476 }
2477}
5fd2087a
AF		 2478
2479/* CPUClass::reset() */
2480static void x86_cpu_reset(CPUState *s)
2481{
2482 X86CPU *cpu = X86_CPU(s);
2483 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2484 CPUX86State *env = &cpu->env;
c1958aea
AF		 2485 int i;
2486
5fd2087a
AF		 2487 xcc->parent_reset(s);
2488
43175fa9 2489 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2490
00c8cb0a 2491 tlb_flush(s, 1);
c1958aea
AF		 2492
2493 env->old_exception = -1;
2494
2495 /* init to reset state */
2496
2497#ifdef CONFIG_SOFTMMU
2498 env->hflags |= HF_SOFTMMU_MASK;
2499#endif
2500 env->hflags2 |= HF2_GIF_MASK;
2501
2502 cpu_x86_update_cr0(env, 0x60000010);
2503 env->a20_mask = ~0x0;
2504 env->smbase = 0x30000;
2505
2506 env->idt.limit = 0xffff;
2507 env->gdt.limit = 0xffff;
2508 env->ldt.limit = 0xffff;
2509 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2510 env->tr.limit = 0xffff;
2511 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2512
2513 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2514 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2515 DESC_R_MASK | DESC_A_MASK);
2516 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2517 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2518 DESC_A_MASK);
2519 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2520 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2521 DESC_A_MASK);
2522 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2523 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2524 DESC_A_MASK);
2525 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2526 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2527 DESC_A_MASK);
2528 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2529 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2530 DESC_A_MASK);
2531
2532 env->eip = 0xfff0;
2533 env->regs[R_EDX] = env->cpuid_version;
2534
2535 env->eflags = 0x2;
2536
2537 /* FPU init */
2538 for (i = 0; i < 8; i++) {
2539 env->fptags[i] = 1;
2540 }
2541 env->fpuc = 0x37f;
2542
2543 env->mxcsr = 0x1f80;
c74f41bb 2544 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2545
2546 env->pat = 0x0007040600070406ULL;
2547 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2548
2549 memset(env->dr, 0, sizeof(env->dr));
2550 env->dr[6] = DR6_FIXED_1;
2551 env->dr[7] = DR7_FIXED_1;
b3310ab3 2552 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2553 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2554
05e7e819 2555 env->xcr0 = 1;
0522604b 2556
dd673288
IM		 2557#if !defined(CONFIG_USER_ONLY)
2558 /* We hard-wire the BSP to the first CPU. */
55e5c285 2559 if (s->cpu_index == 0) {
02e51483 2560 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2561 }
2562
259186a7 2563 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2564
2565 if (kvm_enabled()) {
2566 kvm_arch_reset_vcpu(cpu);
2567 }
dd673288 2568#endif
5fd2087a
AF		 2569}
2570
dd673288
IM		 2571#ifndef CONFIG_USER_ONLY
2572bool cpu_is_bsp(X86CPU *cpu)
2573{
02e51483 2574 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2575}
65dee380
IM		 2576
2577/* TODO: remove me, when reset over QOM tree is implemented */
2578static void x86_cpu_machine_reset_cb(void *opaque)
2579{
2580 X86CPU *cpu = opaque;
2581 cpu_reset(CPU(cpu));
2582}
dd673288
IM		 2583#endif
2584
de024815
AF		 2585static void mce_init(X86CPU *cpu)
2586{
2587 CPUX86State *cenv = &cpu->env;
2588 unsigned int bank;
2589
2590 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2591 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2592 (CPUID_MCE | CPUID_MCA)) {
2593 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2594 cenv->mcg_ctl = ~(uint64_t)0;
2595 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2596 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2597 }
2598 }
2599}
2600
bdeec802 2601#ifndef CONFIG_USER_ONLY
d3c64d6a 2602static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2603{
bdeec802 2604 CPUX86State *env = &cpu->env;
53a89e26 2605 DeviceState *dev = DEVICE(cpu);
449994eb 2606 APICCommonState *apic;
bdeec802
IM		 2607 const char *apic_type = "apic";
2608
2609 if (kvm_irqchip_in_kernel()) {
2610 apic_type = "kvm-apic";
2611 } else if (xen_enabled()) {
2612 apic_type = "xen-apic";
2613 }
2614
02e51483
CF		 2615 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2616 if (cpu->apic_state == NULL) {
bdeec802
IM		 2617 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2618 return;
2619 }
2620
2621 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2622 OBJECT(cpu->apic_state), NULL);
2623 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2624 /* TODO: convert to link<> */
02e51483 2625 apic = APIC_COMMON(cpu->apic_state);
60671e58 2626 apic->cpu = cpu;
d3c64d6a
IM		 2627}
2628
2629static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2630{
02e51483 2631 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2632 return;
2633 }
bdeec802 2634
02e51483 2635 if (qdev_init(cpu->apic_state)) {
bdeec802 2636 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2637 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2638 return;
2639 }
bdeec802 2640}
d3c64d6a
IM		 2641#else
2642static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2643{
2644}
bdeec802
IM		 2645#endif
2646
2b6f294c 2647static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2648{
14a10fc3 2649 CPUState *cs = CPU(dev);
2b6f294c
AF		 2650 X86CPU *cpu = X86_CPU(dev);
2651 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2652 CPUX86State *env = &cpu->env;
2b6f294c 2653 Error *local_err = NULL;
b34d12d1 2654
0514ef2f 2655 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2656 env->cpuid_level = 7;
2657 }
7a059953 2658
9b15cd9e
IM		 2659 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2660 * CPUID[1].EDX.
2661 */
2662 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2663 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2664 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
0514ef2f
EH		 2665 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2666 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2667 & CPUID_EXT2_AMD_ALIASES);
2668 }
2669
fefb41bf
EH		 2670
2671 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2672 error_setg(&local_err,
2673 kvm_enabled() ?
2674 "Host doesn't support requested features" :
2675 "TCG doesn't support requested features");
2676 goto out;
4586f157
IM		 2677 }
2678
65dee380
IM		 2679#ifndef CONFIG_USER_ONLY
2680 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2681
0514ef2f 2682 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2683 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2684 if (local_err != NULL) {
4dc1f449 2685 goto out;
bdeec802
IM		 2686 }
2687 }
65dee380
IM		 2688#endif
2689
7a059953 2690 mce_init(cpu);
14a10fc3 2691 qemu_init_vcpu(cs);
d3c64d6a
IM		 2692
2693 x86_cpu_apic_realize(cpu, &local_err);
2694 if (local_err != NULL) {
2695 goto out;
2696 }
14a10fc3 2697 cpu_reset(cs);
2b6f294c 2698
4dc1f449
IM		 2699 xcc->parent_realize(dev, &local_err);
2700out:
2701 if (local_err != NULL) {
2702 error_propagate(errp, local_err);
2703 return;
2704 }
7a059953
AF		 2705}
2706
8932cfdf
EH		 2707/* Enables contiguous-apic-ID mode, for compatibility */
2708static bool compat_apic_id_mode;
2709
2710void enable_compat_apic_id_mode(void)
2711{
2712 compat_apic_id_mode = true;
2713}
2714
cb41bad3
EH		 2715/* Calculates initial APIC ID for a specific CPU index
2716 *
2717 * Currently we need to be able to calculate the APIC ID from the CPU index
2718 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2719 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2720 * all CPUs up to max_cpus.
2721 */
2722uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2723{
8932cfdf
EH		 2724 uint32_t correct_id;
2725 static bool warned;
2726
2727 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2728 if (compat_apic_id_mode) {
2729 if (cpu_index != correct_id && !warned) {
2730 error_report("APIC IDs set in compatibility mode, "
2731 "CPU topology won't match the configuration");
2732 warned = true;
2733 }
2734 return cpu_index;
2735 } else {
2736 return correct_id;
2737 }
cb41bad3
EH		 2738}
2739
de024815
AF		 2740static void x86_cpu_initfn(Object *obj)
2741{
55e5c285 2742 CPUState *cs = CPU(obj);
de024815 2743 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2744 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2745 CPUX86State *env = &cpu->env;
d65e9815 2746 static int inited;
de024815 2747
c05efcb1 2748 cs->env_ptr = env;
de024815 2749 cpu_exec_init(env);
71ad61d3
AF		 2750
2751 object_property_add(obj, "family", "int",
95b8519d 2752 x86_cpuid_version_get_family,
71ad61d3 2753 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2754 object_property_add(obj, "model", "int",
67e30c83 2755 x86_cpuid_version_get_model,
c5291a4f 2756 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2757 object_property_add(obj, "stepping", "int",
35112e41 2758 x86_cpuid_version_get_stepping,
036e2222 2759 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2760 object_property_add(obj, "level", "int",
2761 x86_cpuid_get_level,
2762 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2763 object_property_add(obj, "xlevel", "int",
2764 x86_cpuid_get_xlevel,
2765 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2766 object_property_add_str(obj, "vendor",
2767 x86_cpuid_get_vendor,
2768 x86_cpuid_set_vendor, NULL);
938d4c25 2769 object_property_add_str(obj, "model-id",
63e886eb 2770 x86_cpuid_get_model_id,
938d4c25 2771 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2772 object_property_add(obj, "tsc-frequency", "int",
2773 x86_cpuid_get_tsc_freq,
2774 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2775 object_property_add(obj, "apic-id", "int",
2776 x86_cpuid_get_apic_id,
2777 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2778 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2779 x86_cpu_get_feature_words,
7e5292b5
EH		 2780 NULL, NULL, (void *)env->features, NULL);
2781 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2782 x86_cpu_get_feature_words,
2783 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2784
92067bf4 2785 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2786 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2787
d940ee9b
EH		 2788 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2789
d65e9815
IM		 2790 /* init various static tables used in TCG mode */
2791 if (tcg_enabled() && !inited) {
2792 inited = 1;
2793 optimize_flags_init();
2794#ifndef CONFIG_USER_ONLY
2795 cpu_set_debug_excp_handler(breakpoint_handler);
2796#endif
2797 }
de024815
AF		 2798}
2799
997395d3
IM		 2800static int64_t x86_cpu_get_arch_id(CPUState *cs)
2801{
2802 X86CPU *cpu = X86_CPU(cs);
2803 CPUX86State *env = &cpu->env;
2804
2805 return env->cpuid_apic_id;
2806}
2807
444d5590
AF		 2808static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2809{
2810 X86CPU *cpu = X86_CPU(cs);
2811
2812 return cpu->env.cr[0] & CR0_PG_MASK;
2813}
2814
f45748f1
AF		 2815static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2816{
2817 X86CPU *cpu = X86_CPU(cs);
2818
2819 cpu->env.eip = value;
2820}
2821
bdf7ae5b
AF		 2822static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2823{
2824 X86CPU *cpu = X86_CPU(cs);
2825
2826 cpu->env.eip = tb->pc - tb->cs_base;
2827}
2828
8c2e1b00
AF		 2829static bool x86_cpu_has_work(CPUState *cs)
2830{
2831 X86CPU *cpu = X86_CPU(cs);
2832 CPUX86State *env = &cpu->env;
2833
2834 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2835 CPU_INTERRUPT_POLL)) &&
2836 (env->eflags & IF_MASK)) ||
2837 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2838 CPU_INTERRUPT_INIT |
2839 CPU_INTERRUPT_SIPI |
2840 CPU_INTERRUPT_MCE));
2841}
2842
9337e3b6
EH		 2843static Property x86_cpu_properties[] = {
2844 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2845 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2846 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2847 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2848 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2849 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2850 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2851 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2852 DEFINE_PROP_END_OF_LIST()
2853};
2854
5fd2087a
AF		 2855static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2856{
2857 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2858 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2859 DeviceClass *dc = DEVICE_CLASS(oc);
2860
2861 xcc->parent_realize = dc->realize;
2862 dc->realize = x86_cpu_realizefn;
62fc403f 2863 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2864 dc->props = x86_cpu_properties;
5fd2087a
AF		 2865
2866 xcc->parent_reset = cc->reset;
2867 cc->reset = x86_cpu_reset;
91b1df8c 2868 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2869
500050d1 2870 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2871 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2872 cc->has_work = x86_cpu_has_work;
97a8ea5a 2873 cc->do_interrupt = x86_cpu_do_interrupt;
878096ee 2874 cc->dump_state = x86_cpu_dump_state;
f45748f1 2875 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2876 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2877 cc->gdb_read_register = x86_cpu_gdb_read_register;
2878 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2879 cc->get_arch_id = x86_cpu_get_arch_id;
2880 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2881#ifdef CONFIG_USER_ONLY
2882 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2883#else
a23bbfda 2884 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2885 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2886 cc->write_elf64_note = x86_cpu_write_elf64_note;
2887 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2888 cc->write_elf32_note = x86_cpu_write_elf32_note;
2889 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2890 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2891#endif
a0e372f0 2892 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
5fd2087a
AF		 2893}
2894
2895static const TypeInfo x86_cpu_type_info = {
2896 .name = TYPE_X86_CPU,
2897 .parent = TYPE_CPU,
2898 .instance_size = sizeof(X86CPU),
de024815 2899 .instance_init = x86_cpu_initfn,
d940ee9b 2900 .abstract = true,
5fd2087a
AF		 2901 .class_size = sizeof(X86CPUClass),
2902 .class_init = x86_cpu_common_class_init,
2903};
2904
2905static void x86_cpu_register_types(void)
2906{
d940ee9b
EH		 2907 int i;
2908
5fd2087a 2909 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2910 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2911 x86_register_cpudef_type(&builtin_x86_defs[i]);
2912 }
2913#ifdef CONFIG_KVM
2914 type_register_static(&host_x86_cpu_type_info);
2915#endif
5fd2087a
AF		 2916}
2917
2918type_init(x86_cpu_register_types)
QEMU mirror