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nEPT: MMU context for nested EPT
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
4e1096d2 715static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 716static void kvm_cpu_vmxon(u64 addr);
717static void kvm_cpu_vmxoff(void);
aff48baa 718static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
644d711a
NHE		 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1044 struct kvm_vcpu *vcpu)
1045{
1046 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1047}
1048
155a97a3
NHE		 1049static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1050{
1051 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1052}
1053
644d711a
NHE		 1054static inline bool is_exception(u32 intr_info)
1055{
1056 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1057 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1058}
1059
1060static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1061static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1062 struct vmcs12 *vmcs12,
1063 u32 reason, unsigned long qualification);
1064
8b9cf98c 1065static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1066{
1067 int i;
1068
a2fa3e9f 1069 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1070 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1071 return i;
1072 return -1;
1073}
1074
2384d2b3
SY		 1075static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1076{
1077 struct {
1078 u64 vpid : 16;
1079 u64 rsvd : 48;
1080 u64 gva;
1081 } operand = { vpid, 0, gva };
1082
4ecac3fd 1083 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1084 /* CF==1 or ZF==1 --> rc = -1 */
1085 "; ja 1f ; ud2 ; 1:"
1086 : : "a"(&operand), "c"(ext) : "cc", "memory");
1087}
1088
1439442c
SY		 1089static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1090{
1091 struct {
1092 u64 eptp, gpa;
1093 } operand = {eptp, gpa};
1094
4ecac3fd 1095 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1096 /* CF==1 or ZF==1 --> rc = -1 */
1097 "; ja 1f ; ud2 ; 1:\n"
1098 : : "a" (&operand), "c" (ext) : "cc", "memory");
1099}
1100
26bb0981 1101static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1102{
1103 int i;
1104
8b9cf98c 1105 i = __find_msr_index(vmx, msr);
a75beee6 1106 if (i >= 0)
a2fa3e9f 1107 return &vmx->guest_msrs[i];
8b6d44c7 1108 return NULL;
7725f0ba
AK		 1109}
1110
6aa8b732
AK		 1111static void vmcs_clear(struct vmcs *vmcs)
1112{
1113 u64 phys_addr = __pa(vmcs);
1114 u8 error;
1115
4ecac3fd 1116 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1117 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1118 : "cc", "memory");
1119 if (error)
1120 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1121 vmcs, phys_addr);
1122}
1123
d462b819
NHE		 1124static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1125{
1126 vmcs_clear(loaded_vmcs->vmcs);
1127 loaded_vmcs->cpu = -1;
1128 loaded_vmcs->launched = 0;
1129}
1130
7725b894
DX		 1131static void vmcs_load(struct vmcs *vmcs)
1132{
1133 u64 phys_addr = __pa(vmcs);
1134 u8 error;
1135
1136 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1137 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1138 : "cc", "memory");
1139 if (error)
2844d849 1140 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1141 vmcs, phys_addr);
1142}
1143
8f536b76
ZY		 1144#ifdef CONFIG_KEXEC
1145/*
1146 * This bitmap is used to indicate whether the vmclear
1147 * operation is enabled on all cpus. All disabled by
1148 * default.
1149 */
1150static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1151
1152static inline void crash_enable_local_vmclear(int cpu)
1153{
1154 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1155}
1156
1157static inline void crash_disable_local_vmclear(int cpu)
1158{
1159 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1160}
1161
1162static inline int crash_local_vmclear_enabled(int cpu)
1163{
1164 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1165}
1166
1167static void crash_vmclear_local_loaded_vmcss(void)
1168{
1169 int cpu = raw_smp_processor_id();
1170 struct loaded_vmcs *v;
1171
1172 if (!crash_local_vmclear_enabled(cpu))
1173 return;
1174
1175 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1176 loaded_vmcss_on_cpu_link)
1177 vmcs_clear(v->vmcs);
1178}
1179#else
1180static inline void crash_enable_local_vmclear(int cpu) { }
1181static inline void crash_disable_local_vmclear(int cpu) { }
1182#endif /* CONFIG_KEXEC */
1183
d462b819 1184static void __loaded_vmcs_clear(void *arg)
6aa8b732 1185{
d462b819 1186 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1187 int cpu = raw_smp_processor_id();
6aa8b732 1188
d462b819
NHE		 1189 if (loaded_vmcs->cpu != cpu)
1190 return; /* vcpu migration can race with cpu offline */
1191 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1192 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1193 crash_disable_local_vmclear(cpu);
d462b819 1194 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1195
1196 /*
1197 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1198 * is before setting loaded_vmcs->vcpu to -1 which is done in
1199 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1200 * then adds the vmcs into percpu list before it is deleted.
1201 */
1202 smp_wmb();
1203
d462b819 1204 loaded_vmcs_init(loaded_vmcs);
8f536b76 1205 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1206}
1207
d462b819 1208static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1209{
e6c7d321
XG		 1210 int cpu = loaded_vmcs->cpu;
1211
1212 if (cpu != -1)
1213 smp_call_function_single(cpu,
1214 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1215}
1216
1760dd49 1217static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1218{
1219 if (vmx->vpid == 0)
1220 return;
1221
518c8aee
GJ		 1222 if (cpu_has_vmx_invvpid_single())
1223 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1224}
1225
b9d762fa
GJ		 1226static inline void vpid_sync_vcpu_global(void)
1227{
1228 if (cpu_has_vmx_invvpid_global())
1229 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1230}
1231
1232static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1233{
1234 if (cpu_has_vmx_invvpid_single())
1760dd49 1235 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1236 else
1237 vpid_sync_vcpu_global();
1238}
1239
1439442c
SY		 1240static inline void ept_sync_global(void)
1241{
1242 if (cpu_has_vmx_invept_global())
1243 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1244}
1245
1246static inline void ept_sync_context(u64 eptp)
1247{
089d034e 1248 if (enable_ept) {
1439442c
SY		 1249 if (cpu_has_vmx_invept_context())
1250 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1251 else
1252 ept_sync_global();
1253 }
1254}
1255
96304217 1256static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1257{
5e520e62 1258 unsigned long value;
6aa8b732 1259
5e520e62
AK		 1260 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1261 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1262 return value;
1263}
1264
96304217 1265static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1266{
1267 return vmcs_readl(field);
1268}
1269
96304217 1270static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1271{
1272 return vmcs_readl(field);
1273}
1274
96304217 1275static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1276{
05b3e0c2 1277#ifdef CONFIG_X86_64
6aa8b732
AK		 1278 return vmcs_readl(field);
1279#else
1280 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1281#endif
1282}
1283
e52de1b8
AK		 1284static noinline void vmwrite_error(unsigned long field, unsigned long value)
1285{
1286 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1287 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1288 dump_stack();
1289}
1290
6aa8b732
AK		 1291static void vmcs_writel(unsigned long field, unsigned long value)
1292{
1293 u8 error;
1294
4ecac3fd 1295 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1296 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1297 if (unlikely(error))
1298 vmwrite_error(field, value);
6aa8b732
AK		 1299}
1300
1301static void vmcs_write16(unsigned long field, u16 value)
1302{
1303 vmcs_writel(field, value);
1304}
1305
1306static void vmcs_write32(unsigned long field, u32 value)
1307{
1308 vmcs_writel(field, value);
1309}
1310
1311static void vmcs_write64(unsigned long field, u64 value)
1312{
6aa8b732 1313 vmcs_writel(field, value);
7682f2d0 1314#ifndef CONFIG_X86_64
6aa8b732
AK		 1315 asm volatile ("");
1316 vmcs_writel(field+1, value >> 32);
1317#endif
1318}
1319
2ab455cc
AL		 1320static void vmcs_clear_bits(unsigned long field, u32 mask)
1321{
1322 vmcs_writel(field, vmcs_readl(field) & ~mask);
1323}
1324
1325static void vmcs_set_bits(unsigned long field, u32 mask)
1326{
1327 vmcs_writel(field, vmcs_readl(field) | mask);
1328}
1329
2fb92db1
AK		 1330static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1331{
1332 vmx->segment_cache.bitmask = 0;
1333}
1334
1335static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1336 unsigned field)
1337{
1338 bool ret;
1339 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1340
1341 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1342 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1343 vmx->segment_cache.bitmask = 0;
1344 }
1345 ret = vmx->segment_cache.bitmask & mask;
1346 vmx->segment_cache.bitmask |= mask;
1347 return ret;
1348}
1349
1350static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1351{
1352 u16 *p = &vmx->segment_cache.seg[seg].selector;
1353
1354 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1355 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1356 return *p;
1357}
1358
1359static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1360{
1361 ulong *p = &vmx->segment_cache.seg[seg].base;
1362
1363 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1364 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1365 return *p;
1366}
1367
1368static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1369{
1370 u32 *p = &vmx->segment_cache.seg[seg].limit;
1371
1372 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1373 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1374 return *p;
1375}
1376
1377static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1378{
1379 u32 *p = &vmx->segment_cache.seg[seg].ar;
1380
1381 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1382 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1383 return *p;
1384}
1385
abd3f2d6
AK		 1386static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1387{
1388 u32 eb;
1389
fd7373cc
JK		 1390 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1391 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1392 if ((vcpu->guest_debug &
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1394 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1395 eb |= 1u << BP_VECTOR;
7ffd92c5 1396 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1397 eb = ~0;
089d034e 1398 if (enable_ept)
1439442c 1399 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1400 if (vcpu->fpu_active)
1401 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1402
1403 /* When we are running a nested L2 guest and L1 specified for it a
1404 * certain exception bitmap, we must trap the same exceptions and pass
1405 * them to L1. When running L2, we will only handle the exceptions
1406 * specified above if L1 did not want them.
1407 */
1408 if (is_guest_mode(vcpu))
1409 eb |= get_vmcs12(vcpu)->exception_bitmap;
1410
abd3f2d6
AK		 1411 vmcs_write32(EXCEPTION_BITMAP, eb);
1412}
1413
8bf00a52
GN		 1414static void clear_atomic_switch_msr_special(unsigned long entry,
1415 unsigned long exit)
1416{
1417 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1418 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1419}
1420
61d2ef2c
AK		 1421static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1422{
1423 unsigned i;
1424 struct msr_autoload *m = &vmx->msr_autoload;
1425
8bf00a52
GN		 1426 switch (msr) {
1427 case MSR_EFER:
1428 if (cpu_has_load_ia32_efer) {
1429 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1430 VM_EXIT_LOAD_IA32_EFER);
1431 return;
1432 }
1433 break;
1434 case MSR_CORE_PERF_GLOBAL_CTRL:
1435 if (cpu_has_load_perf_global_ctrl) {
1436 clear_atomic_switch_msr_special(
1437 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1438 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1439 return;
1440 }
1441 break;
110312c8
AK		 1442 }
1443
61d2ef2c
AK		 1444 for (i = 0; i < m->nr; ++i)
1445 if (m->guest[i].index == msr)
1446 break;
1447
1448 if (i == m->nr)
1449 return;
1450 --m->nr;
1451 m->guest[i] = m->guest[m->nr];
1452 m->host[i] = m->host[m->nr];
1453 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1454 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1455}
1456
8bf00a52
GN		 1457static void add_atomic_switch_msr_special(unsigned long entry,
1458 unsigned long exit, unsigned long guest_val_vmcs,
1459 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1460{
1461 vmcs_write64(guest_val_vmcs, guest_val);
1462 vmcs_write64(host_val_vmcs, host_val);
1463 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1464 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1465}
1466
61d2ef2c
AK		 1467static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1468 u64 guest_val, u64 host_val)
1469{
1470 unsigned i;
1471 struct msr_autoload *m = &vmx->msr_autoload;
1472
8bf00a52
GN		 1473 switch (msr) {
1474 case MSR_EFER:
1475 if (cpu_has_load_ia32_efer) {
1476 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1477 VM_EXIT_LOAD_IA32_EFER,
1478 GUEST_IA32_EFER,
1479 HOST_IA32_EFER,
1480 guest_val, host_val);
1481 return;
1482 }
1483 break;
1484 case MSR_CORE_PERF_GLOBAL_CTRL:
1485 if (cpu_has_load_perf_global_ctrl) {
1486 add_atomic_switch_msr_special(
1487 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1489 GUEST_IA32_PERF_GLOBAL_CTRL,
1490 HOST_IA32_PERF_GLOBAL_CTRL,
1491 guest_val, host_val);
1492 return;
1493 }
1494 break;
110312c8
AK		 1495 }
1496
61d2ef2c
AK		 1497 for (i = 0; i < m->nr; ++i)
1498 if (m->guest[i].index == msr)
1499 break;
1500
e7fc6f93
GN		 1501 if (i == NR_AUTOLOAD_MSRS) {
1502 printk_once(KERN_WARNING"Not enough mst switch entries. "
1503 "Can't add msr %x\n", msr);
1504 return;
1505 } else if (i == m->nr) {
61d2ef2c
AK		 1506 ++m->nr;
1507 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1508 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1509 }
1510
1511 m->guest[i].index = msr;
1512 m->guest[i].value = guest_val;
1513 m->host[i].index = msr;
1514 m->host[i].value = host_val;
1515}
1516
33ed6329
AK		 1517static void reload_tss(void)
1518{
33ed6329
AK		 1519 /*
1520 * VT restores TR but not its size. Useless.
1521 */
d359192f 1522 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1523 struct desc_struct *descs;
33ed6329 1524
d359192f 1525 descs = (void *)gdt->address;
33ed6329
AK		 1526 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1527 load_TR_desc();
33ed6329
AK		 1528}
1529
92c0d900 1530static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1531{
3a34a881 1532 u64 guest_efer;
51c6cf66
AK		 1533 u64 ignore_bits;
1534
f6801dff 1535 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1536
51c6cf66 1537 /*
0fa06071 1538 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1539 * outside long mode
1540 */
1541 ignore_bits = EFER_NX | EFER_SCE;
1542#ifdef CONFIG_X86_64
1543 ignore_bits |= EFER_LMA | EFER_LME;
1544 /* SCE is meaningful only in long mode on Intel */
1545 if (guest_efer & EFER_LMA)
1546 ignore_bits &= ~(u64)EFER_SCE;
1547#endif
51c6cf66
AK		 1548 guest_efer &= ~ignore_bits;
1549 guest_efer |= host_efer & ignore_bits;
26bb0981 1550 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1551 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1552
1553 clear_atomic_switch_msr(vmx, MSR_EFER);
1554 /* On ept, can't emulate nx, and must switch nx atomically */
1555 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1556 guest_efer = vmx->vcpu.arch.efer;
1557 if (!(guest_efer & EFER_LMA))
1558 guest_efer &= ~EFER_LME;
1559 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1560 return false;
1561 }
1562
26bb0981 1563 return true;
51c6cf66
AK		 1564}
1565
2d49ec72
GN		 1566static unsigned long segment_base(u16 selector)
1567{
d359192f 1568 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1569 struct desc_struct *d;
1570 unsigned long table_base;
1571 unsigned long v;
1572
1573 if (!(selector & ~3))
1574 return 0;
1575
d359192f 1576 table_base = gdt->address;
2d49ec72
GN		 1577
1578 if (selector & 4) { /* from ldt */
1579 u16 ldt_selector = kvm_read_ldt();
1580
1581 if (!(ldt_selector & ~3))
1582 return 0;
1583
1584 table_base = segment_base(ldt_selector);
1585 }
1586 d = (struct desc_struct *)(table_base + (selector & ~7));
1587 v = get_desc_base(d);
1588#ifdef CONFIG_X86_64
1589 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1590 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1591#endif
1592 return v;
1593}
1594
1595static inline unsigned long kvm_read_tr_base(void)
1596{
1597 u16 tr;
1598 asm("str %0" : "=g"(tr));
1599 return segment_base(tr);
1600}
1601
04d2cc77 1602static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1603{
04d2cc77 1604 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1605 int i;
04d2cc77 1606
a2fa3e9f 1607 if (vmx->host_state.loaded)
33ed6329
AK		 1608 return;
1609
a2fa3e9f 1610 vmx->host_state.loaded = 1;
33ed6329
AK		 1611 /*
1612 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1613 * allow segment selectors with cpl > 0 or ti == 1.
1614 */
d6e88aec 1615 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1616 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1617 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1618 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1619 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1620 vmx->host_state.fs_reload_needed = 0;
1621 } else {
33ed6329 1622 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1623 vmx->host_state.fs_reload_needed = 1;
33ed6329 1624 }
9581d442 1625 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1626 if (!(vmx->host_state.gs_sel & 7))
1627 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1628 else {
1629 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1630 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1631 }
1632
b2da15ac
AK		 1633#ifdef CONFIG_X86_64
1634 savesegment(ds, vmx->host_state.ds_sel);
1635 savesegment(es, vmx->host_state.es_sel);
1636#endif
1637
33ed6329
AK		 1638#ifdef CONFIG_X86_64
1639 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1640 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1641#else
a2fa3e9f
GH		 1642 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1643 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1644#endif
707c0874
AK		 1645
1646#ifdef CONFIG_X86_64
c8770e7b
AK		 1647 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1648 if (is_long_mode(&vmx->vcpu))
44ea2b17 1649 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1650#endif
26bb0981
AK		 1651 for (i = 0; i < vmx->save_nmsrs; ++i)
1652 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1653 vmx->guest_msrs[i].data,
1654 vmx->guest_msrs[i].mask);
33ed6329
AK		 1655}
1656
a9b21b62 1657static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1658{
a2fa3e9f 1659 if (!vmx->host_state.loaded)
33ed6329
AK		 1660 return;
1661
e1beb1d3 1662 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1663 vmx->host_state.loaded = 0;
c8770e7b
AK		 1664#ifdef CONFIG_X86_64
1665 if (is_long_mode(&vmx->vcpu))
1666 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1667#endif
152d3f2f 1668 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1669 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1670#ifdef CONFIG_X86_64
9581d442 1671 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1672#else
1673 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1674#endif
33ed6329 1675 }
0a77fe4c
AK		 1676 if (vmx->host_state.fs_reload_needed)
1677 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1678#ifdef CONFIG_X86_64
1679 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1680 loadsegment(ds, vmx->host_state.ds_sel);
1681 loadsegment(es, vmx->host_state.es_sel);
1682 }
b2da15ac 1683#endif
152d3f2f 1684 reload_tss();
44ea2b17 1685#ifdef CONFIG_X86_64
c8770e7b 1686 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1687#endif
b1a74bf8
SS		 1688 /*
1689 * If the FPU is not active (through the host task or
1690 * the guest vcpu), then restore the cr0.TS bit.
1691 */
1692 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1693 stts();
3444d7da 1694 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1695}
1696
a9b21b62
AK		 1697static void vmx_load_host_state(struct vcpu_vmx *vmx)
1698{
1699 preempt_disable();
1700 __vmx_load_host_state(vmx);
1701 preempt_enable();
1702}
1703
6aa8b732
AK		 1704/*
1705 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1706 * vcpu mutex is already taken.
1707 */
15ad7146 1708static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1709{
a2fa3e9f 1710 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1711 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1712
4610c9cc
DX		 1713 if (!vmm_exclusive)
1714 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1715 else if (vmx->loaded_vmcs->cpu != cpu)
1716 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1717
d462b819
NHE		 1718 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1719 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1720 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1721 }
1722
d462b819 1723 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1724 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1725 unsigned long sysenter_esp;
1726
a8eeb04a 1727 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1728 local_irq_disable();
8f536b76 1729 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1730
1731 /*
1732 * Read loaded_vmcs->cpu should be before fetching
1733 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1734 * See the comments in __loaded_vmcs_clear().
1735 */
1736 smp_rmb();
1737
d462b819
NHE		 1738 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1739 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1740 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1741 local_irq_enable();
1742
6aa8b732
AK		 1743 /*
1744 * Linux uses per-cpu TSS and GDT, so set these when switching
1745 * processors.
1746 */
d6e88aec 1747 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1748 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1749
1750 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1751 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1752 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1753 }
6aa8b732
AK		 1754}
1755
1756static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1757{
a9b21b62 1758 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1759 if (!vmm_exclusive) {
d462b819
NHE		 1760 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1761 vcpu->cpu = -1;
4610c9cc
DX		 1762 kvm_cpu_vmxoff();
1763 }
6aa8b732
AK		 1764}
1765
5fd86fcf
AK		 1766static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1767{
81231c69
AK		 1768 ulong cr0;
1769
5fd86fcf
AK		 1770 if (vcpu->fpu_active)
1771 return;
1772 vcpu->fpu_active = 1;
81231c69
AK		 1773 cr0 = vmcs_readl(GUEST_CR0);
1774 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1775 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1776 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1777 update_exception_bitmap(vcpu);
edcafe3c 1778 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1779 if (is_guest_mode(vcpu))
1780 vcpu->arch.cr0_guest_owned_bits &=
1781 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1782 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1783}
1784
edcafe3c
AK		 1785static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1786
fe3ef05c
NHE		 1787/*
1788 * Return the cr0 value that a nested guest would read. This is a combination
1789 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1790 * its hypervisor (cr0_read_shadow).
1791 */
1792static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1793{
1794 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1795 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1796}
1797static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1798{
1799 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1800 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1801}
1802
5fd86fcf
AK		 1803static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1804{
36cf24e0
NHE		 1805 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1806 * set this *before* calling this function.
1807 */
edcafe3c 1808 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1809 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1810 update_exception_bitmap(vcpu);
edcafe3c
AK		 1811 vcpu->arch.cr0_guest_owned_bits = 0;
1812 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1813 if (is_guest_mode(vcpu)) {
1814 /*
1815 * L1's specified read shadow might not contain the TS bit,
1816 * so now that we turned on shadowing of this bit, we need to
1817 * set this bit of the shadow. Like in nested_vmx_run we need
1818 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1819 * up-to-date here because we just decached cr0.TS (and we'll
1820 * only update vmcs12->guest_cr0 on nested exit).
1821 */
1822 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1823 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1824 (vcpu->arch.cr0 & X86_CR0_TS);
1825 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1826 } else
1827 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1828}
1829
6aa8b732
AK		 1830static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1831{
78ac8b47 1832 unsigned long rflags, save_rflags;
345dcaa8 1833
6de12732
AK		 1834 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1835 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1836 rflags = vmcs_readl(GUEST_RFLAGS);
1837 if (to_vmx(vcpu)->rmode.vm86_active) {
1838 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1839 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1840 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1841 }
1842 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1843 }
6de12732 1844 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1845}
1846
1847static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1848{
6de12732
AK		 1849 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1850 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1851 if (to_vmx(vcpu)->rmode.vm86_active) {
1852 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1853 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1854 }
6aa8b732
AK		 1855 vmcs_writel(GUEST_RFLAGS, rflags);
1856}
1857
2809f5d2
GC		 1858static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1859{
1860 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1861 int ret = 0;
1862
1863 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1864 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1865 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1866 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1867
1868 return ret & mask;
1869}
1870
1871static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1872{
1873 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1874 u32 interruptibility = interruptibility_old;
1875
1876 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1877
48005f64 1878 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1879 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1880 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1881 interruptibility |= GUEST_INTR_STATE_STI;
1882
1883 if ((interruptibility != interruptibility_old))
1884 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1885}
1886
6aa8b732
AK		 1887static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1888{
1889 unsigned long rip;
6aa8b732 1890
5fdbf976 1891 rip = kvm_rip_read(vcpu);
6aa8b732 1892 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1893 kvm_rip_write(vcpu, rip);
6aa8b732 1894
2809f5d2
GC		 1895 /* skipping an emulated instruction also counts */
1896 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1897}
1898
0b6ac343
NHE		 1899/*
1900 * KVM wants to inject page-faults which it got to the guest. This function
1901 * checks whether in a nested guest, we need to inject them to L1 or L2.
1902 * This function assumes it is called with the exit reason in vmcs02 being
1903 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1904 * is running).
1905 */
1906static int nested_pf_handled(struct kvm_vcpu *vcpu)
1907{
1908 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1909
1910 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1911 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1912 return 0;
1913
1914 nested_vmx_vmexit(vcpu);
1915 return 1;
1916}
1917
298101da 1918static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1919 bool has_error_code, u32 error_code,
1920 bool reinject)
298101da 1921{
77ab6db0 1922 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1923 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1924
0b6ac343 1925 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1926 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1927 return;
1928
8ab2d2e2 1929 if (has_error_code) {
77ab6db0 1930 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1931 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1932 }
77ab6db0 1933
7ffd92c5 1934 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1935 int inc_eip = 0;
1936 if (kvm_exception_is_soft(nr))
1937 inc_eip = vcpu->arch.event_exit_inst_len;
1938 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1939 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1940 return;
1941 }
1942
66fd3f7f
GN		 1943 if (kvm_exception_is_soft(nr)) {
1944 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1945 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1946 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1947 } else
1948 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1949
1950 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1951}
1952
4e47c7a6
SY		 1953static bool vmx_rdtscp_supported(void)
1954{
1955 return cpu_has_vmx_rdtscp();
1956}
1957
ad756a16
MJ		 1958static bool vmx_invpcid_supported(void)
1959{
1960 return cpu_has_vmx_invpcid() && enable_ept;
1961}
1962
a75beee6
ED		 1963/*
1964 * Swap MSR entry in host/guest MSR entry array.
1965 */
8b9cf98c 1966static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1967{
26bb0981 1968 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1969
1970 tmp = vmx->guest_msrs[to];
1971 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1972 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1973}
1974
8d14695f
YZ		 1975static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1976{
1977 unsigned long *msr_bitmap;
1978
1979 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1980 if (is_long_mode(vcpu))
1981 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1982 else
1983 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1984 } else {
1985 if (is_long_mode(vcpu))
1986 msr_bitmap = vmx_msr_bitmap_longmode;
1987 else
1988 msr_bitmap = vmx_msr_bitmap_legacy;
1989 }
1990
1991 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1992}
1993
e38aea3e
AK		 1994/*
1995 * Set up the vmcs to automatically save and restore system
1996 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1997 * mode, as fiddling with msrs is very expensive.
1998 */
8b9cf98c 1999static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2000{
26bb0981 2001 int save_nmsrs, index;
e38aea3e 2002
a75beee6
ED		 2003 save_nmsrs = 0;
2004#ifdef CONFIG_X86_64
8b9cf98c 2005 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2006 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2007 if (index >= 0)
8b9cf98c
RR		 2008 move_msr_up(vmx, index, save_nmsrs++);
2009 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2010 if (index >= 0)
8b9cf98c
RR		 2011 move_msr_up(vmx, index, save_nmsrs++);
2012 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2013 if (index >= 0)
8b9cf98c 2014 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2015 index = __find_msr_index(vmx, MSR_TSC_AUX);
2016 if (index >= 0 && vmx->rdtscp_enabled)
2017 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2018 /*
8c06585d 2019 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2020 * if efer.sce is enabled.
2021 */
8c06585d 2022 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2023 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2024 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2025 }
2026#endif
92c0d900
AK		 2027 index = __find_msr_index(vmx, MSR_EFER);
2028 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2029 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2030
26bb0981 2031 vmx->save_nmsrs = save_nmsrs;
5897297b 2032
8d14695f
YZ		 2033 if (cpu_has_vmx_msr_bitmap())
2034 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2035}
2036
6aa8b732
AK		 2037/*
2038 * reads and returns guest's timestamp counter "register"
2039 * guest_tsc = host_tsc + tsc_offset -- 21.3
2040 */
2041static u64 guest_read_tsc(void)
2042{
2043 u64 host_tsc, tsc_offset;
2044
2045 rdtscll(host_tsc);
2046 tsc_offset = vmcs_read64(TSC_OFFSET);
2047 return host_tsc + tsc_offset;
2048}
2049
d5c1785d
NHE		 2050/*
2051 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2052 * counter, even if a nested guest (L2) is currently running.
2053 */
886b470c 2054u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2055{
886b470c 2056 u64 tsc_offset;
d5c1785d 2057
d5c1785d
NHE		 2058 tsc_offset = is_guest_mode(vcpu) ?
2059 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2060 vmcs_read64(TSC_OFFSET);
2061 return host_tsc + tsc_offset;
2062}
2063
4051b188 2064/*
cc578287
ZA		 2065 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2066 * software catchup for faster rates on slower CPUs.
4051b188 2067 */
cc578287 2068static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2069{
cc578287
ZA		 2070 if (!scale)
2071 return;
2072
2073 if (user_tsc_khz > tsc_khz) {
2074 vcpu->arch.tsc_catchup = 1;
2075 vcpu->arch.tsc_always_catchup = 1;
2076 } else
2077 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2078}
2079
ba904635
WA		 2080static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2081{
2082 return vmcs_read64(TSC_OFFSET);
2083}
2084
6aa8b732 2085/*
99e3e30a 2086 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2087 */
99e3e30a 2088static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2089{
27fc51b2 2090 if (is_guest_mode(vcpu)) {
7991825b 2091 /*
27fc51b2
NHE		 2092 * We're here if L1 chose not to trap WRMSR to TSC. According
2093 * to the spec, this should set L1's TSC; The offset that L1
2094 * set for L2 remains unchanged, and still needs to be added
2095 * to the newly set TSC to get L2's TSC.
7991825b 2096 */
27fc51b2
NHE		 2097 struct vmcs12 *vmcs12;
2098 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2099 /* recalculate vmcs02.TSC_OFFSET: */
2100 vmcs12 = get_vmcs12(vcpu);
2101 vmcs_write64(TSC_OFFSET, offset +
2102 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2103 vmcs12->tsc_offset : 0));
2104 } else {
489223ed
YY		 2105 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2106 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2107 vmcs_write64(TSC_OFFSET, offset);
2108 }
6aa8b732
AK		 2109}
2110
f1e2b260 2111static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2112{
2113 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2114
e48672fa 2115 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2116 if (is_guest_mode(vcpu)) {
2117 /* Even when running L2, the adjustment needs to apply to L1 */
2118 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2119 } else
2120 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2121 offset + adjustment);
e48672fa
ZA		 2122}
2123
857e4099
JR		 2124static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2125{
2126 return target_tsc - native_read_tsc();
2127}
2128
801d3424
NHE		 2129static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2130{
2131 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2132 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2133}
2134
2135/*
2136 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2137 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2138 * all guests if the "nested" module option is off, and can also be disabled
2139 * for a single guest by disabling its VMX cpuid bit.
2140 */
2141static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2142{
2143 return nested && guest_cpuid_has_vmx(vcpu);
2144}
2145
b87a51ae
NHE		 2146/*
2147 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2148 * returned for the various VMX controls MSRs when nested VMX is enabled.
2149 * The same values should also be used to verify that vmcs12 control fields are
2150 * valid during nested entry from L1 to L2.
2151 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2152 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2153 * bit in the high half is on if the corresponding bit in the control field
2154 * may be on. See also vmx_control_verify().
2155 * TODO: allow these variables to be modified (downgraded) by module options
2156 * or other means.
2157 */
2158static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2159static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2160static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2161static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2162static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2163static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2164static __init void nested_vmx_setup_ctls_msrs(void)
2165{
2166 /*
2167 * Note that as a general rule, the high half of the MSRs (bits in
2168 * the control fields which may be 1) should be initialized by the
2169 * intersection of the underlying hardware's MSR (i.e., features which
2170 * can be supported) and the list of features we want to expose -
2171 * because they are known to be properly supported in our code.
2172 * Also, usually, the low half of the MSRs (bits which must be 1) can
2173 * be set to 0, meaning that L1 may turn off any of these bits. The
2174 * reason is that if one of these bits is necessary, it will appear
2175 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2176 * fields of vmcs01 and vmcs02, will turn these bits off - and
2177 * nested_vmx_exit_handled() will not pass related exits to L1.
2178 * These rules have exceptions below.
2179 */
2180
2181 /* pin-based controls */
eabeaacc
JK		 2182 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2183 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2184 /*
2185 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2186 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2187 */
eabeaacc
JK		 2188 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2190 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2191 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2192 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2193
33fb20c3
JK		 2194 /*
2195 * Exit controls
2196 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2197 * 17 must be 1.
2198 */
2199 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2200 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2201#ifdef CONFIG_X86_64
2202 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2203#else
2204 nested_vmx_exit_ctls_high = 0;
2205#endif
8049d651
NHE		 2206 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2207 VM_EXIT_LOAD_IA32_EFER);
b87a51ae
NHE		 2208
2209 /* entry controls */
2210 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2211 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2212 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2213 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2214 nested_vmx_entry_ctls_high &=
2215 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
8049d651
NHE		 2216 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2217 VM_ENTRY_LOAD_IA32_EFER);
b87a51ae
NHE		 2218 /* cpu-based controls */
2219 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2220 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2221 nested_vmx_procbased_ctls_low = 0;
2222 nested_vmx_procbased_ctls_high &=
2223 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2224 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2225 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2226 CPU_BASED_CR3_STORE_EXITING |
2227#ifdef CONFIG_X86_64
2228 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2229#endif
2230 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2231 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2232 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2233 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2234 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2235 /*
2236 * We can allow some features even when not supported by the
2237 * hardware. For example, L1 can specify an MSR bitmap - and we
2238 * can use it to avoid exits to L1 - even when L0 runs L2
2239 * without MSR bitmaps.
2240 */
2241 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2242
2243 /* secondary cpu-based controls */
2244 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2245 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2246 nested_vmx_secondary_ctls_low = 0;
2247 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2248 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2249 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2250
2251 /* miscellaneous data */
2252 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2253 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2254 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2255 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2256}
2257
2258static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2259{
2260 /*
2261 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2262 */
2263 return ((control & high) | low) == control;
2264}
2265
2266static inline u64 vmx_control_msr(u32 low, u32 high)
2267{
2268 return low | ((u64)high << 32);
2269}
2270
2271/*
2272 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2273 * also let it use VMX-specific MSRs.
2274 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2275 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2276 * like all other MSRs).
2277 */
2278static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2279{
2280 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2281 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2282 /*
2283 * According to the spec, processors which do not support VMX
2284 * should throw a #GP(0) when VMX capability MSRs are read.
2285 */
2286 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2287 return 1;
2288 }
2289
2290 switch (msr_index) {
2291 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2292 if (nested_vmx_allowed(vcpu)) {
2293 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2294 break;
2295 }
2296 return 0;
b87a51ae
NHE		 2297 case MSR_IA32_VMX_BASIC:
2298 /*
2299 * This MSR reports some information about VMX support. We
2300 * should return information about the VMX we emulate for the
2301 * guest, and the VMCS structure we give it - not about the
2302 * VMX support of the underlying hardware.
2303 */
2304 *pdata = VMCS12_REVISION |
2305 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2306 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2307 break;
2308 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2309 case MSR_IA32_VMX_PINBASED_CTLS:
2310 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2311 nested_vmx_pinbased_ctls_high);
2312 break;
2313 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2314 case MSR_IA32_VMX_PROCBASED_CTLS:
2315 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2316 nested_vmx_procbased_ctls_high);
2317 break;
2318 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2319 case MSR_IA32_VMX_EXIT_CTLS:
2320 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2321 nested_vmx_exit_ctls_high);
2322 break;
2323 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2324 case MSR_IA32_VMX_ENTRY_CTLS:
2325 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2326 nested_vmx_entry_ctls_high);
2327 break;
2328 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2329 *pdata = vmx_control_msr(nested_vmx_misc_low,
2330 nested_vmx_misc_high);
b87a51ae
NHE		 2331 break;
2332 /*
2333 * These MSRs specify bits which the guest must keep fixed (on or off)
2334 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2335 * We picked the standard core2 setting.
2336 */
2337#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2338#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2339 case MSR_IA32_VMX_CR0_FIXED0:
2340 *pdata = VMXON_CR0_ALWAYSON;
2341 break;
2342 case MSR_IA32_VMX_CR0_FIXED1:
2343 *pdata = -1ULL;
2344 break;
2345 case MSR_IA32_VMX_CR4_FIXED0:
2346 *pdata = VMXON_CR4_ALWAYSON;
2347 break;
2348 case MSR_IA32_VMX_CR4_FIXED1:
2349 *pdata = -1ULL;
2350 break;
2351 case MSR_IA32_VMX_VMCS_ENUM:
2352 *pdata = 0x1f;
2353 break;
2354 case MSR_IA32_VMX_PROCBASED_CTLS2:
2355 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2356 nested_vmx_secondary_ctls_high);
2357 break;
2358 case MSR_IA32_VMX_EPT_VPID_CAP:
2359 /* Currently, no nested ept or nested vpid */
2360 *pdata = 0;
2361 break;
2362 default:
2363 return 0;
2364 }
2365
2366 return 1;
2367}
2368
b3897a49 2369static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2370{
b3897a49
NHE		 2371 u32 msr_index = msr_info->index;
2372 u64 data = msr_info->data;
2373 bool host_initialized = msr_info->host_initiated;
2374
b87a51ae
NHE		 2375 if (!nested_vmx_allowed(vcpu))
2376 return 0;
2377
b3897a49
NHE		 2378 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2379 if (!host_initialized &&
2380 to_vmx(vcpu)->nested.msr_ia32_feature_control
2381 & FEATURE_CONTROL_LOCKED)
2382 return 0;
2383 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2384 return 1;
b3897a49
NHE		 2385 }
2386
b87a51ae
NHE		 2387 /*
2388 * No need to treat VMX capability MSRs specially: If we don't handle
2389 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2390 */
2391 return 0;
2392}
2393
6aa8b732
AK		 2394/*
2395 * Reads an msr value (of 'msr_index') into 'pdata'.
2396 * Returns 0 on success, non-0 otherwise.
2397 * Assumes vcpu_load() was already called.
2398 */
2399static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2400{
2401 u64 data;
26bb0981 2402 struct shared_msr_entry *msr;
6aa8b732
AK		 2403
2404 if (!pdata) {
2405 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2406 return -EINVAL;
2407 }
2408
2409 switch (msr_index) {
05b3e0c2 2410#ifdef CONFIG_X86_64
6aa8b732
AK		 2411 case MSR_FS_BASE:
2412 data = vmcs_readl(GUEST_FS_BASE);
2413 break;
2414 case MSR_GS_BASE:
2415 data = vmcs_readl(GUEST_GS_BASE);
2416 break;
44ea2b17
AK		 2417 case MSR_KERNEL_GS_BASE:
2418 vmx_load_host_state(to_vmx(vcpu));
2419 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2420 break;
26bb0981 2421#endif
6aa8b732 2422 case MSR_EFER:
3bab1f5d 2423 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2424 case MSR_IA32_TSC:
6aa8b732
AK		 2425 data = guest_read_tsc();
2426 break;
2427 case MSR_IA32_SYSENTER_CS:
2428 data = vmcs_read32(GUEST_SYSENTER_CS);
2429 break;
2430 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2431 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2432 break;
2433 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2434 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2435 break;
4e47c7a6
SY		 2436 case MSR_TSC_AUX:
2437 if (!to_vmx(vcpu)->rdtscp_enabled)
2438 return 1;
2439 /* Otherwise falls through */
6aa8b732 2440 default:
b87a51ae
NHE		 2441 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2442 return 0;
8b9cf98c 2443 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2444 if (msr) {
2445 data = msr->data;
2446 break;
6aa8b732 2447 }
3bab1f5d 2448 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2449 }
2450
2451 *pdata = data;
2452 return 0;
2453}
2454
2455/*
2456 * Writes msr value into into the appropriate "register".
2457 * Returns 0 on success, non-0 otherwise.
2458 * Assumes vcpu_load() was already called.
2459 */
8fe8ab46 2460static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2461{
a2fa3e9f 2462 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2463 struct shared_msr_entry *msr;
2cc51560 2464 int ret = 0;
8fe8ab46
WA		 2465 u32 msr_index = msr_info->index;
2466 u64 data = msr_info->data;
2cc51560 2467
6aa8b732 2468 switch (msr_index) {
3bab1f5d 2469 case MSR_EFER:
8fe8ab46 2470 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2471 break;
16175a79 2472#ifdef CONFIG_X86_64
6aa8b732 2473 case MSR_FS_BASE:
2fb92db1 2474 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2475 vmcs_writel(GUEST_FS_BASE, data);
2476 break;
2477 case MSR_GS_BASE:
2fb92db1 2478 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2479 vmcs_writel(GUEST_GS_BASE, data);
2480 break;
44ea2b17
AK		 2481 case MSR_KERNEL_GS_BASE:
2482 vmx_load_host_state(vmx);
2483 vmx->msr_guest_kernel_gs_base = data;
2484 break;
6aa8b732
AK		 2485#endif
2486 case MSR_IA32_SYSENTER_CS:
2487 vmcs_write32(GUEST_SYSENTER_CS, data);
2488 break;
2489 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2490 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2491 break;
2492 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2493 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2494 break;
af24a4e4 2495 case MSR_IA32_TSC:
8fe8ab46 2496 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2497 break;
468d472f
SY		 2498 case MSR_IA32_CR_PAT:
2499 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2500 vmcs_write64(GUEST_IA32_PAT, data);
2501 vcpu->arch.pat = data;
2502 break;
2503 }
8fe8ab46 2504 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2505 break;
ba904635
WA		 2506 case MSR_IA32_TSC_ADJUST:
2507 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2508 break;
2509 case MSR_TSC_AUX:
2510 if (!vmx->rdtscp_enabled)
2511 return 1;
2512 /* Check reserved bit, higher 32 bits should be zero */
2513 if ((data >> 32) != 0)
2514 return 1;
2515 /* Otherwise falls through */
6aa8b732 2516 default:
b3897a49 2517 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2518 break;
8b9cf98c 2519 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2520 if (msr) {
2521 msr->data = data;
2225fd56
AK		 2522 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2523 preempt_disable();
9ee73970
AK		 2524 kvm_set_shared_msr(msr->index, msr->data,
2525 msr->mask);
2225fd56
AK		 2526 preempt_enable();
2527 }
3bab1f5d 2528 break;
6aa8b732 2529 }
8fe8ab46 2530 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2531 }
2532
2cc51560 2533 return ret;
6aa8b732
AK		 2534}
2535
5fdbf976 2536static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2537{
5fdbf976
MT		 2538 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2539 switch (reg) {
2540 case VCPU_REGS_RSP:
2541 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2542 break;
2543 case VCPU_REGS_RIP:
2544 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2545 break;
6de4f3ad
AK		 2546 case VCPU_EXREG_PDPTR:
2547 if (enable_ept)
2548 ept_save_pdptrs(vcpu);
2549 break;
5fdbf976
MT		 2550 default:
2551 break;
2552 }
6aa8b732
AK		 2553}
2554
6aa8b732
AK		 2555static __init int cpu_has_kvm_support(void)
2556{
6210e37b 2557 return cpu_has_vmx();
6aa8b732
AK		 2558}
2559
2560static __init int vmx_disabled_by_bios(void)
2561{
2562 u64 msr;
2563
2564 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2565 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2566 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2567 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2568 && tboot_enabled())
2569 return 1;
23f3e991 2570 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2571 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2572 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2573 && !tboot_enabled()) {
2574 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2575 "activate TXT before enabling KVM\n");
cafd6659 2576 return 1;
f9335afe 2577 }
23f3e991
JC		 2578 /* launched w/o TXT and VMX disabled */
2579 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2580 && !tboot_enabled())
2581 return 1;
cafd6659
SW		 2582 }
2583
2584 return 0;
6aa8b732
AK		 2585}
2586
7725b894
DX		 2587static void kvm_cpu_vmxon(u64 addr)
2588{
2589 asm volatile (ASM_VMX_VMXON_RAX
2590 : : "a"(&addr), "m"(addr)
2591 : "memory", "cc");
2592}
2593
10474ae8 2594static int hardware_enable(void *garbage)
6aa8b732
AK		 2595{
2596 int cpu = raw_smp_processor_id();
2597 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2598 u64 old, test_bits;
6aa8b732 2599
10474ae8
AG		 2600 if (read_cr4() & X86_CR4_VMXE)
2601 return -EBUSY;
2602
d462b819 2603 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2604
2605 /*
2606 * Now we can enable the vmclear operation in kdump
2607 * since the loaded_vmcss_on_cpu list on this cpu
2608 * has been initialized.
2609 *
2610 * Though the cpu is not in VMX operation now, there
2611 * is no problem to enable the vmclear operation
2612 * for the loaded_vmcss_on_cpu list is empty!
2613 */
2614 crash_enable_local_vmclear(cpu);
2615
6aa8b732 2616 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2617
2618 test_bits = FEATURE_CONTROL_LOCKED;
2619 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2620 if (tboot_enabled())
2621 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2622
2623 if ((old & test_bits) != test_bits) {
6aa8b732 2624 /* enable and lock */
cafd6659
SW		 2625 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2626 }
66aee91a 2627 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2628
4610c9cc
DX		 2629 if (vmm_exclusive) {
2630 kvm_cpu_vmxon(phys_addr);
2631 ept_sync_global();
2632 }
10474ae8 2633
357d1226 2634 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2635
10474ae8 2636 return 0;
6aa8b732
AK		 2637}
2638
d462b819 2639static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2640{
2641 int cpu = raw_smp_processor_id();
d462b819 2642 struct loaded_vmcs *v, *n;
543e4243 2643
d462b819
NHE		 2644 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2645 loaded_vmcss_on_cpu_link)
2646 __loaded_vmcs_clear(v);
543e4243
AK		 2647}
2648
710ff4a8
EH		 2649
2650/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2651 * tricks.
2652 */
2653static void kvm_cpu_vmxoff(void)
6aa8b732 2654{
4ecac3fd 2655 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2656}
2657
710ff4a8
EH		 2658static void hardware_disable(void *garbage)
2659{
4610c9cc 2660 if (vmm_exclusive) {
d462b819 2661 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2662 kvm_cpu_vmxoff();
2663 }
7725b894 2664 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2665}
2666
1c3d14fe 2667static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2668 u32 msr, u32 *result)
1c3d14fe
YS		 2669{
2670 u32 vmx_msr_low, vmx_msr_high;
2671 u32 ctl = ctl_min | ctl_opt;
2672
2673 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2674
2675 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2676 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2677
2678 /* Ensure minimum (required) set of control bits are supported. */
2679 if (ctl_min & ~ctl)
002c7f7c 2680 return -EIO;
1c3d14fe
YS		 2681
2682 *result = ctl;
2683 return 0;
2684}
2685
110312c8
AK		 2686static __init bool allow_1_setting(u32 msr, u32 ctl)
2687{
2688 u32 vmx_msr_low, vmx_msr_high;
2689
2690 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2691 return vmx_msr_high & ctl;
2692}
2693
002c7f7c 2694static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2695{
2696 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2697 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2698 u32 _pin_based_exec_control = 0;
2699 u32 _cpu_based_exec_control = 0;
f78e0e2e 2700 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2701 u32 _vmexit_control = 0;
2702 u32 _vmentry_control = 0;
2703
10166744 2704 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2705#ifdef CONFIG_X86_64
2706 CPU_BASED_CR8_LOAD_EXITING |
2707 CPU_BASED_CR8_STORE_EXITING |
2708#endif
d56f546d
SY		 2709 CPU_BASED_CR3_LOAD_EXITING |
2710 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2711 CPU_BASED_USE_IO_BITMAPS |
2712 CPU_BASED_MOV_DR_EXITING |
a7052897 2713 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2714 CPU_BASED_MWAIT_EXITING |
2715 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2716 CPU_BASED_INVLPG_EXITING |
2717 CPU_BASED_RDPMC_EXITING;
443381a8 2718
f78e0e2e 2719 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2720 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2721 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2722 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2723 &_cpu_based_exec_control) < 0)
002c7f7c 2724 return -EIO;
6e5d865c
YS		 2725#ifdef CONFIG_X86_64
2726 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2727 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2728 ~CPU_BASED_CR8_STORE_EXITING;
2729#endif
f78e0e2e 2730 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2731 min2 = 0;
2732 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2733 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2734 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2735 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2736 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2737 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2738 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2739 SECONDARY_EXEC_RDTSCP |
83d4c286 2740 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2741 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2742 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2743 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2744 if (adjust_vmx_controls(min2, opt2,
2745 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2746 &_cpu_based_2nd_exec_control) < 0)
2747 return -EIO;
2748 }
2749#ifndef CONFIG_X86_64
2750 if (!(_cpu_based_2nd_exec_control &
2751 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2752 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2753#endif
83d4c286
YZ		 2754
2755 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2756 _cpu_based_2nd_exec_control &= ~(
8d14695f 2757 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2758 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2759 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2760
d56f546d 2761 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2762 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2763 enabled */
5fff7d27
GN		 2764 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2765 CPU_BASED_CR3_STORE_EXITING |
2766 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2767 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2768 vmx_capability.ept, vmx_capability.vpid);
2769 }
1c3d14fe
YS		 2770
2771 min = 0;
2772#ifdef CONFIG_X86_64
2773 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2774#endif
a547c6db
YZ		 2775 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2776 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2777 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2778 &_vmexit_control) < 0)
002c7f7c 2779 return -EIO;
1c3d14fe 2780
01e439be
YZ		 2781 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2782 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2783 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2784 &_pin_based_exec_control) < 0)
2785 return -EIO;
2786
2787 if (!(_cpu_based_2nd_exec_control &
2788 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2789 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2790 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2791
468d472f
SY		 2792 min = 0;
2793 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2794 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2795 &_vmentry_control) < 0)
002c7f7c 2796 return -EIO;
6aa8b732 2797
c68876fd 2798 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2799
2800 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2801 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2802 return -EIO;
1c3d14fe
YS		 2803
2804#ifdef CONFIG_X86_64
2805 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2806 if (vmx_msr_high & (1u<<16))
002c7f7c 2807 return -EIO;
1c3d14fe
YS		 2808#endif
2809
2810 /* Require Write-Back (WB) memory type for VMCS accesses. */
2811 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2812 return -EIO;
1c3d14fe 2813
002c7f7c
YS		 2814 vmcs_conf->size = vmx_msr_high & 0x1fff;
2815 vmcs_conf->order = get_order(vmcs_config.size);
2816 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2817
002c7f7c
YS		 2818 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2819 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2820 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2821 vmcs_conf->vmexit_ctrl = _vmexit_control;
2822 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2823
110312c8
AK		 2824 cpu_has_load_ia32_efer =
2825 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2826 VM_ENTRY_LOAD_IA32_EFER)
2827 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2828 VM_EXIT_LOAD_IA32_EFER);
2829
8bf00a52
GN		 2830 cpu_has_load_perf_global_ctrl =
2831 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2832 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2833 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2834 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2835
2836 /*
2837 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2838 * but due to arrata below it can't be used. Workaround is to use
2839 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2840 *
2841 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2842 *
2843 * AAK155 (model 26)
2844 * AAP115 (model 30)
2845 * AAT100 (model 37)
2846 * BC86,AAY89,BD102 (model 44)
2847 * BA97 (model 46)
2848 *
2849 */
2850 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2851 switch (boot_cpu_data.x86_model) {
2852 case 26:
2853 case 30:
2854 case 37:
2855 case 44:
2856 case 46:
2857 cpu_has_load_perf_global_ctrl = false;
2858 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2859 "does not work properly. Using workaround\n");
2860 break;
2861 default:
2862 break;
2863 }
2864 }
2865
1c3d14fe 2866 return 0;
c68876fd 2867}
6aa8b732
AK		 2868
2869static struct vmcs *alloc_vmcs_cpu(int cpu)
2870{
2871 int node = cpu_to_node(cpu);
2872 struct page *pages;
2873 struct vmcs *vmcs;
2874
6484eb3e 2875 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2876 if (!pages)
2877 return NULL;
2878 vmcs = page_address(pages);
1c3d14fe
YS		 2879 memset(vmcs, 0, vmcs_config.size);
2880 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2881 return vmcs;
2882}
2883
2884static struct vmcs *alloc_vmcs(void)
2885{
d3b2c338 2886 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2887}
2888
2889static void free_vmcs(struct vmcs *vmcs)
2890{
1c3d14fe 2891 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2892}
2893
d462b819
NHE		 2894/*
2895 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2896 */
2897static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2898{
2899 if (!loaded_vmcs->vmcs)
2900 return;
2901 loaded_vmcs_clear(loaded_vmcs);
2902 free_vmcs(loaded_vmcs->vmcs);
2903 loaded_vmcs->vmcs = NULL;
2904}
2905
39959588 2906static void free_kvm_area(void)
6aa8b732
AK		 2907{
2908 int cpu;
2909
3230bb47 2910 for_each_possible_cpu(cpu) {
6aa8b732 2911 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2912 per_cpu(vmxarea, cpu) = NULL;
2913 }
6aa8b732
AK		 2914}
2915
6aa8b732
AK		 2916static __init int alloc_kvm_area(void)
2917{
2918 int cpu;
2919
3230bb47 2920 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2921 struct vmcs *vmcs;
2922
2923 vmcs = alloc_vmcs_cpu(cpu);
2924 if (!vmcs) {
2925 free_kvm_area();
2926 return -ENOMEM;
2927 }
2928
2929 per_cpu(vmxarea, cpu) = vmcs;
2930 }
2931 return 0;
2932}
2933
2934static __init int hardware_setup(void)
2935{
002c7f7c
YS		 2936 if (setup_vmcs_config(&vmcs_config) < 0)
2937 return -EIO;
50a37eb4
JR		 2938
2939 if (boot_cpu_has(X86_FEATURE_NX))
2940 kvm_enable_efer_bits(EFER_NX);
2941
93ba03c2
SY		 2942 if (!cpu_has_vmx_vpid())
2943 enable_vpid = 0;
abc4fc58
AG		 2944 if (!cpu_has_vmx_shadow_vmcs())
2945 enable_shadow_vmcs = 0;
93ba03c2 2946
4bc9b982
SY		 2947 if (!cpu_has_vmx_ept() ||
2948 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2949 enable_ept = 0;
3a624e29 2950 enable_unrestricted_guest = 0;
83c3a331 2951 enable_ept_ad_bits = 0;
3a624e29
NK		 2952 }
2953
83c3a331
XH		 2954 if (!cpu_has_vmx_ept_ad_bits())
2955 enable_ept_ad_bits = 0;
2956
3a624e29
NK		 2957 if (!cpu_has_vmx_unrestricted_guest())
2958 enable_unrestricted_guest = 0;
93ba03c2
SY		 2959
2960 if (!cpu_has_vmx_flexpriority())
2961 flexpriority_enabled = 0;
2962
95ba8273
GN		 2963 if (!cpu_has_vmx_tpr_shadow())
2964 kvm_x86_ops->update_cr8_intercept = NULL;
2965
54dee993
MT		 2966 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2967 kvm_disable_largepages();
2968
4b8d54f9
ZE		 2969 if (!cpu_has_vmx_ple())
2970 ple_gap = 0;
2971
01e439be
YZ		 2972 if (!cpu_has_vmx_apicv())
2973 enable_apicv = 0;
c7c9c56c 2974
01e439be 2975 if (enable_apicv)
c7c9c56c 2976 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2977 else {
c7c9c56c 2978 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2979 kvm_x86_ops->deliver_posted_interrupt = NULL;
2980 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2981 }
83d4c286 2982
b87a51ae
NHE		 2983 if (nested)
2984 nested_vmx_setup_ctls_msrs();
2985
6aa8b732
AK		 2986 return alloc_kvm_area();
2987}
2988
2989static __exit void hardware_unsetup(void)
2990{
2991 free_kvm_area();
2992}
2993
14168786
GN		 2994static bool emulation_required(struct kvm_vcpu *vcpu)
2995{
2996 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2997}
2998
91b0aa2c 2999static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3000 struct kvm_segment *save)
6aa8b732 3001{
d99e4152
GN		 3002 if (!emulate_invalid_guest_state) {
3003 /*
3004 * CS and SS RPL should be equal during guest entry according
3005 * to VMX spec, but in reality it is not always so. Since vcpu
3006 * is in the middle of the transition from real mode to
3007 * protected mode it is safe to assume that RPL 0 is a good
3008 * default value.
3009 */
3010 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3011 save->selector &= ~SELECTOR_RPL_MASK;
3012 save->dpl = save->selector & SELECTOR_RPL_MASK;
3013 save->s = 1;
6aa8b732 3014 }
d99e4152 3015 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3016}
3017
3018static void enter_pmode(struct kvm_vcpu *vcpu)
3019{
3020 unsigned long flags;
a89a8fb9 3021 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3022
d99e4152
GN		 3023 /*
3024 * Update real mode segment cache. It may be not up-to-date if sement
3025 * register was written while vcpu was in a guest mode.
3026 */
3027 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3028 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3029 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3030 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3031 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3032 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3033
7ffd92c5 3034 vmx->rmode.vm86_active = 0;
6aa8b732 3035
2fb92db1
AK		 3036 vmx_segment_cache_clear(vmx);
3037
f5f7b2fe 3038 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3039
3040 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3041 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3042 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3043 vmcs_writel(GUEST_RFLAGS, flags);
3044
66aee91a
RR		 3045 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3046 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3047
3048 update_exception_bitmap(vcpu);
3049
91b0aa2c
GN		 3050 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3051 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3052 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3053 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3054 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3055 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3056
3057 /* CPL is always 0 when CPU enters protected mode */
3058 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3059 vmx->cpl = 0;
6aa8b732
AK		 3060}
3061
f5f7b2fe 3062static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3063{
772e0318 3064 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3065 struct kvm_segment var = *save;
3066
3067 var.dpl = 0x3;
3068 if (seg == VCPU_SREG_CS)
3069 var.type = 0x3;
3070
3071 if (!emulate_invalid_guest_state) {
3072 var.selector = var.base >> 4;
3073 var.base = var.base & 0xffff0;
3074 var.limit = 0xffff;
3075 var.g = 0;
3076 var.db = 0;
3077 var.present = 1;
3078 var.s = 1;
3079 var.l = 0;
3080 var.unusable = 0;
3081 var.type = 0x3;
3082 var.avl = 0;
3083 if (save->base & 0xf)
3084 printk_once(KERN_WARNING "kvm: segment base is not "
3085 "paragraph aligned when entering "
3086 "protected mode (seg=%d)", seg);
3087 }
6aa8b732 3088
d99e4152
GN		 3089 vmcs_write16(sf->selector, var.selector);
3090 vmcs_write32(sf->base, var.base);
3091 vmcs_write32(sf->limit, var.limit);
3092 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3093}
3094
3095static void enter_rmode(struct kvm_vcpu *vcpu)
3096{
3097 unsigned long flags;
a89a8fb9 3098 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3099
f5f7b2fe
AK		 3100 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3101 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3102 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3103 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3104 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3105 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3106 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3107
7ffd92c5 3108 vmx->rmode.vm86_active = 1;
6aa8b732 3109
776e58ea
GN		 3110 /*
3111 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3112 * vcpu. Warn the user that an update is overdue.
776e58ea 3113 */
4918c6ca 3114 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3115 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3116 "called before entering vcpu\n");
776e58ea 3117
2fb92db1
AK		 3118 vmx_segment_cache_clear(vmx);
3119
4918c6ca 3120 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3121 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3122 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3123
3124 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3125 vmx->rmode.save_rflags = flags;
6aa8b732 3126
053de044 3127 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3128
3129 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3130 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3131 update_exception_bitmap(vcpu);
3132
d99e4152
GN		 3133 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3134 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3135 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3136 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3137 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3138 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3139
8668a3c4 3140 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3141}
3142
401d10de
AS		 3143static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3144{
3145 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3146 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3147
3148 if (!msr)
3149 return;
401d10de 3150
44ea2b17
AK		 3151 /*
3152 * Force kernel_gs_base reloading before EFER changes, as control
3153 * of this msr depends on is_long_mode().
3154 */
3155 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3156 vcpu->arch.efer = efer;
401d10de
AS		 3157 if (efer & EFER_LMA) {
3158 vmcs_write32(VM_ENTRY_CONTROLS,
3159 vmcs_read32(VM_ENTRY_CONTROLS) |
3160 VM_ENTRY_IA32E_MODE);
3161 msr->data = efer;
3162 } else {
3163 vmcs_write32(VM_ENTRY_CONTROLS,
3164 vmcs_read32(VM_ENTRY_CONTROLS) &
3165 ~VM_ENTRY_IA32E_MODE);
3166
3167 msr->data = efer & ~EFER_LME;
3168 }
3169 setup_msrs(vmx);
3170}
3171
05b3e0c2 3172#ifdef CONFIG_X86_64
6aa8b732
AK		 3173
3174static void enter_lmode(struct kvm_vcpu *vcpu)
3175{
3176 u32 guest_tr_ar;
3177
2fb92db1
AK		 3178 vmx_segment_cache_clear(to_vmx(vcpu));
3179
6aa8b732
AK		 3180 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3181 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3182 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3183 __func__);
6aa8b732
AK		 3184 vmcs_write32(GUEST_TR_AR_BYTES,
3185 (guest_tr_ar & ~AR_TYPE_MASK)
3186 | AR_TYPE_BUSY_64_TSS);
3187 }
da38f438 3188 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3189}
3190
3191static void exit_lmode(struct kvm_vcpu *vcpu)
3192{
6aa8b732
AK		 3193 vmcs_write32(VM_ENTRY_CONTROLS,
3194 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3195 & ~VM_ENTRY_IA32E_MODE);
da38f438 3196 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3197}
3198
3199#endif
3200
2384d2b3
SY		 3201static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3202{
b9d762fa 3203 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3204 if (enable_ept) {
3205 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3206 return;
4e1096d2 3207 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3208 }
2384d2b3
SY		 3209}
3210
e8467fda
AK		 3211static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3212{
3213 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3214
3215 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3216 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3217}
3218
aff48baa
AK		 3219static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3220{
3221 if (enable_ept && is_paging(vcpu))
3222 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3223 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3224}
3225
25c4c276 3226static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3227{
fc78f519
AK		 3228 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3229
3230 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3231 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3232}
3233
1439442c
SY		 3234static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3235{
6de4f3ad
AK		 3236 if (!test_bit(VCPU_EXREG_PDPTR,
3237 (unsigned long *)&vcpu->arch.regs_dirty))
3238 return;
3239
1439442c 3240 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3241 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3242 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3243 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3244 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3245 }
3246}
3247
8f5d549f
AK		 3248static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3249{
3250 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3251 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3252 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3253 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3254 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3255 }
6de4f3ad
AK		 3256
3257 __set_bit(VCPU_EXREG_PDPTR,
3258 (unsigned long *)&vcpu->arch.regs_avail);
3259 __set_bit(VCPU_EXREG_PDPTR,
3260 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3261}
3262
5e1746d6 3263static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3264
3265static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3266 unsigned long cr0,
3267 struct kvm_vcpu *vcpu)
3268{
5233dd51
MT		 3269 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3270 vmx_decache_cr3(vcpu);
1439442c
SY		 3271 if (!(cr0 & X86_CR0_PG)) {
3272 /* From paging/starting to nonpaging */
3273 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3274 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3275 (CPU_BASED_CR3_LOAD_EXITING |
3276 CPU_BASED_CR3_STORE_EXITING));
3277 vcpu->arch.cr0 = cr0;
fc78f519 3278 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3279 } else if (!is_paging(vcpu)) {
3280 /* From nonpaging to paging */
3281 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3282 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3283 ~(CPU_BASED_CR3_LOAD_EXITING |
3284 CPU_BASED_CR3_STORE_EXITING));
3285 vcpu->arch.cr0 = cr0;
fc78f519 3286 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3287 }
95eb84a7
SY		 3288
3289 if (!(cr0 & X86_CR0_WP))
3290 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3291}
3292
6aa8b732
AK		 3293static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3294{
7ffd92c5 3295 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3296 unsigned long hw_cr0;
3297
5037878e 3298 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3299 if (enable_unrestricted_guest)
5037878e 3300 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3301 else {
5037878e 3302 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3303
218e763f
GN		 3304 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3305 enter_pmode(vcpu);
6aa8b732 3306
218e763f
GN		 3307 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3308 enter_rmode(vcpu);
3309 }
6aa8b732 3310
05b3e0c2 3311#ifdef CONFIG_X86_64
f6801dff 3312 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3313 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3314 enter_lmode(vcpu);
707d92fa 3315 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3316 exit_lmode(vcpu);
3317 }
3318#endif
3319
089d034e 3320 if (enable_ept)
1439442c
SY		 3321 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3322
02daab21 3323 if (!vcpu->fpu_active)
81231c69 3324 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3325
6aa8b732 3326 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3327 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3328 vcpu->arch.cr0 = cr0;
14168786
GN		 3329
3330 /* depends on vcpu->arch.cr0 to be set to a new value */
3331 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3332}
3333
1439442c
SY		 3334static u64 construct_eptp(unsigned long root_hpa)
3335{
3336 u64 eptp;
3337
3338 /* TODO write the value reading from MSR */
3339 eptp = VMX_EPT_DEFAULT_MT |
3340 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3341 if (enable_ept_ad_bits)
3342 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3343 eptp |= (root_hpa & PAGE_MASK);
3344
3345 return eptp;
3346}
3347
6aa8b732
AK		 3348static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3349{
1439442c
SY		 3350 unsigned long guest_cr3;
3351 u64 eptp;
3352
3353 guest_cr3 = cr3;
089d034e 3354 if (enable_ept) {
1439442c
SY		 3355 eptp = construct_eptp(cr3);
3356 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3357 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3358 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3359 ept_load_pdptrs(vcpu);
1439442c
SY		 3360 }
3361
2384d2b3 3362 vmx_flush_tlb(vcpu);
1439442c 3363 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3364}
3365
5e1746d6 3366static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3367{
7ffd92c5 3368 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3369 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3370
5e1746d6
NHE		 3371 if (cr4 & X86_CR4_VMXE) {
3372 /*
3373 * To use VMXON (and later other VMX instructions), a guest
3374 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3375 * So basically the check on whether to allow nested VMX
3376 * is here.
3377 */
3378 if (!nested_vmx_allowed(vcpu))
3379 return 1;
1a0d74e6
JK		 3380 }
3381 if (to_vmx(vcpu)->nested.vmxon &&
3382 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3383 return 1;
3384
ad312c7c 3385 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3386 if (enable_ept) {
3387 if (!is_paging(vcpu)) {
3388 hw_cr4 &= ~X86_CR4_PAE;
3389 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3390 /*
3391 * SMEP is disabled if CPU is in non-paging mode in
3392 * hardware. However KVM always uses paging mode to
3393 * emulate guest non-paging mode with TDP.
3394 * To emulate this behavior, SMEP needs to be manually
3395 * disabled when guest switches to non-paging mode.
3396 */
3397 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3398 } else if (!(cr4 & X86_CR4_PAE)) {
3399 hw_cr4 &= ~X86_CR4_PAE;
3400 }
3401 }
1439442c
SY		 3402
3403 vmcs_writel(CR4_READ_SHADOW, cr4);
3404 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3405 return 0;
6aa8b732
AK		 3406}
3407
6aa8b732
AK		 3408static void vmx_get_segment(struct kvm_vcpu *vcpu,
3409 struct kvm_segment *var, int seg)
3410{
a9179499 3411 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3412 u32 ar;
3413
c6ad1153 3414 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3415 *var = vmx->rmode.segs[seg];
a9179499 3416 if (seg == VCPU_SREG_TR
2fb92db1 3417 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3418 return;
1390a28b
AK		 3419 var->base = vmx_read_guest_seg_base(vmx, seg);
3420 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3421 return;
a9179499 3422 }
2fb92db1
AK		 3423 var->base = vmx_read_guest_seg_base(vmx, seg);
3424 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3425 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3426 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3427 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3428 var->type = ar & 15;
3429 var->s = (ar >> 4) & 1;
3430 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3431 /*
3432 * Some userspaces do not preserve unusable property. Since usable
3433 * segment has to be present according to VMX spec we can use present
3434 * property to amend userspace bug by making unusable segment always
3435 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3436 * segment as unusable.
3437 */
3438 var->present = !var->unusable;
6aa8b732
AK		 3439 var->avl = (ar >> 12) & 1;
3440 var->l = (ar >> 13) & 1;
3441 var->db = (ar >> 14) & 1;
3442 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3443}
3444
a9179499
AK		 3445static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3446{
a9179499
AK		 3447 struct kvm_segment s;
3448
3449 if (to_vmx(vcpu)->rmode.vm86_active) {
3450 vmx_get_segment(vcpu, &s, seg);
3451 return s.base;
3452 }
2fb92db1 3453 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3454}
3455
b09408d0 3456static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3457{
b09408d0
MT		 3458 struct vcpu_vmx *vmx = to_vmx(vcpu);
3459
3eeb3288 3460 if (!is_protmode(vcpu))
2e4d2653
IE		 3461 return 0;
3462
f4c63e5d
AK		 3463 if (!is_long_mode(vcpu)
3464 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3465 return 3;
3466
69c73028
AK		 3467 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3468 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3469 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3470 }
d881e6f6
AK		 3471
3472 return vmx->cpl;
69c73028
AK		 3473}
3474
3475
653e3108 3476static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3477{
6aa8b732
AK		 3478 u32 ar;
3479
f0495f9b 3480 if (var->unusable || !var->present)
6aa8b732
AK		 3481 ar = 1 << 16;
3482 else {
3483 ar = var->type & 15;
3484 ar |= (var->s & 1) << 4;
3485 ar |= (var->dpl & 3) << 5;
3486 ar |= (var->present & 1) << 7;
3487 ar |= (var->avl & 1) << 12;
3488 ar |= (var->l & 1) << 13;
3489 ar |= (var->db & 1) << 14;
3490 ar |= (var->g & 1) << 15;
3491 }
653e3108
AK		 3492
3493 return ar;
3494}
3495
3496static void vmx_set_segment(struct kvm_vcpu *vcpu,
3497 struct kvm_segment *var, int seg)
3498{
7ffd92c5 3499 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3500 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3501
2fb92db1 3502 vmx_segment_cache_clear(vmx);
2f143240
GN		 3503 if (seg == VCPU_SREG_CS)
3504 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3505
1ecd50a9
GN		 3506 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3507 vmx->rmode.segs[seg] = *var;
3508 if (seg == VCPU_SREG_TR)
3509 vmcs_write16(sf->selector, var->selector);
3510 else if (var->s)
3511 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3512 goto out;
653e3108 3513 }
1ecd50a9 3514
653e3108
AK		 3515 vmcs_writel(sf->base, var->base);
3516 vmcs_write32(sf->limit, var->limit);
3517 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3518
3519 /*
3520 * Fix the "Accessed" bit in AR field of segment registers for older
3521 * qemu binaries.
3522 * IA32 arch specifies that at the time of processor reset the
3523 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3524 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3525 * state vmexit when "unrestricted guest" mode is turned on.
3526 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3527 * tree. Newer qemu binaries with that qemu fix would not need this
3528 * kvm hack.
3529 */
3530 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3531 var->type |= 0x1; /* Accessed */
3a624e29 3532
f924d66d 3533 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3534
3535out:
14168786 3536 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3537}
3538
6aa8b732
AK		 3539static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3540{
2fb92db1 3541 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3542
3543 *db = (ar >> 14) & 1;
3544 *l = (ar >> 13) & 1;
3545}
3546
89a27f4d 3547static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3548{
89a27f4d
GN		 3549 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3550 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3551}
3552
89a27f4d 3553static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3554{
89a27f4d
GN		 3555 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3556 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3557}
3558
89a27f4d 3559static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3560{
89a27f4d
GN		 3561 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3562 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3563}
3564
89a27f4d 3565static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3566{
89a27f4d
GN		 3567 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3568 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3569}
3570
648dfaa7
MG		 3571static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3572{
3573 struct kvm_segment var;
3574 u32 ar;
3575
3576 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3577 var.dpl = 0x3;
0647f4aa
GN		 3578 if (seg == VCPU_SREG_CS)
3579 var.type = 0x3;
648dfaa7
MG		 3580 ar = vmx_segment_access_rights(&var);
3581
3582 if (var.base != (var.selector << 4))
3583 return false;
89efbed0 3584 if (var.limit != 0xffff)
648dfaa7 3585 return false;
07f42f5f 3586 if (ar != 0xf3)
648dfaa7
MG		 3587 return false;
3588
3589 return true;
3590}
3591
3592static bool code_segment_valid(struct kvm_vcpu *vcpu)
3593{
3594 struct kvm_segment cs;
3595 unsigned int cs_rpl;
3596
3597 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3598 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3599
1872a3f4
AK		 3600 if (cs.unusable)
3601 return false;
648dfaa7
MG		 3602 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3603 return false;
3604 if (!cs.s)
3605 return false;
1872a3f4 3606 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3607 if (cs.dpl > cs_rpl)
3608 return false;
1872a3f4 3609 } else {
648dfaa7
MG		 3610 if (cs.dpl != cs_rpl)
3611 return false;
3612 }
3613 if (!cs.present)
3614 return false;
3615
3616 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3617 return true;
3618}
3619
3620static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3621{
3622 struct kvm_segment ss;
3623 unsigned int ss_rpl;
3624
3625 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3626 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3627
1872a3f4
AK		 3628 if (ss.unusable)
3629 return true;
3630 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3631 return false;
3632 if (!ss.s)
3633 return false;
3634 if (ss.dpl != ss_rpl) /* DPL != RPL */
3635 return false;
3636 if (!ss.present)
3637 return false;
3638
3639 return true;
3640}
3641
3642static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3643{
3644 struct kvm_segment var;
3645 unsigned int rpl;
3646
3647 vmx_get_segment(vcpu, &var, seg);
3648 rpl = var.selector & SELECTOR_RPL_MASK;
3649
1872a3f4
AK		 3650 if (var.unusable)
3651 return true;
648dfaa7
MG		 3652 if (!var.s)
3653 return false;
3654 if (!var.present)
3655 return false;
3656 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3657 if (var.dpl < rpl) /* DPL < RPL */
3658 return false;
3659 }
3660
3661 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3662 * rights flags
3663 */
3664 return true;
3665}
3666
3667static bool tr_valid(struct kvm_vcpu *vcpu)
3668{
3669 struct kvm_segment tr;
3670
3671 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3672
1872a3f4
AK		 3673 if (tr.unusable)
3674 return false;
648dfaa7
MG		 3675 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3676 return false;
1872a3f4 3677 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3678 return false;
3679 if (!tr.present)
3680 return false;
3681
3682 return true;
3683}
3684
3685static bool ldtr_valid(struct kvm_vcpu *vcpu)
3686{
3687 struct kvm_segment ldtr;
3688
3689 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3690
1872a3f4
AK		 3691 if (ldtr.unusable)
3692 return true;
648dfaa7
MG		 3693 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3694 return false;
3695 if (ldtr.type != 2)
3696 return false;
3697 if (!ldtr.present)
3698 return false;
3699
3700 return true;
3701}
3702
3703static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3704{
3705 struct kvm_segment cs, ss;
3706
3707 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3708 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3709
3710 return ((cs.selector & SELECTOR_RPL_MASK) ==
3711 (ss.selector & SELECTOR_RPL_MASK));
3712}
3713
3714/*
3715 * Check if guest state is valid. Returns true if valid, false if
3716 * not.
3717 * We assume that registers are always usable
3718 */
3719static bool guest_state_valid(struct kvm_vcpu *vcpu)
3720{
c5e97c80
GN		 3721 if (enable_unrestricted_guest)
3722 return true;
3723
648dfaa7 3724 /* real mode guest state checks */
f13882d8 3725 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3726 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3727 return false;
3728 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3729 return false;
3730 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3731 return false;
3732 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3733 return false;
3734 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3735 return false;
3736 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3737 return false;
3738 } else {
3739 /* protected mode guest state checks */
3740 if (!cs_ss_rpl_check(vcpu))
3741 return false;
3742 if (!code_segment_valid(vcpu))
3743 return false;
3744 if (!stack_segment_valid(vcpu))
3745 return false;
3746 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3747 return false;
3748 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3749 return false;
3750 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3751 return false;
3752 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3753 return false;
3754 if (!tr_valid(vcpu))
3755 return false;
3756 if (!ldtr_valid(vcpu))
3757 return false;
3758 }
3759 /* TODO:
3760 * - Add checks on RIP
3761 * - Add checks on RFLAGS
3762 */
3763
3764 return true;
3765}
3766
d77c26fc 3767static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3768{
40dcaa9f 3769 gfn_t fn;
195aefde 3770 u16 data = 0;
40dcaa9f 3771 int r, idx, ret = 0;
6aa8b732 3772
40dcaa9f 3773 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3774 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3775 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3776 if (r < 0)
10589a46 3777 goto out;
195aefde 3778 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3779 r = kvm_write_guest_page(kvm, fn++, &data,
3780 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3781 if (r < 0)
10589a46 3782 goto out;
195aefde
IE		 3783 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3784 if (r < 0)
10589a46 3785 goto out;
195aefde
IE		 3786 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3787 if (r < 0)
10589a46 3788 goto out;
195aefde 3789 data = ~0;
10589a46
MT		 3790 r = kvm_write_guest_page(kvm, fn, &data,
3791 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3792 sizeof(u8));
195aefde 3793 if (r < 0)
10589a46
MT		 3794 goto out;
3795
3796 ret = 1;
3797out:
40dcaa9f 3798 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3799 return ret;
6aa8b732
AK		 3800}
3801
b7ebfb05
SY		 3802static int init_rmode_identity_map(struct kvm *kvm)
3803{
40dcaa9f 3804 int i, idx, r, ret;
b7ebfb05
SY		 3805 pfn_t identity_map_pfn;
3806 u32 tmp;
3807
089d034e 3808 if (!enable_ept)
b7ebfb05
SY		 3809 return 1;
3810 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3811 printk(KERN_ERR "EPT: identity-mapping pagetable "
3812 "haven't been allocated!\n");
3813 return 0;
3814 }
3815 if (likely(kvm->arch.ept_identity_pagetable_done))
3816 return 1;
3817 ret = 0;
b927a3ce 3818 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3819 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3820 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3821 if (r < 0)
3822 goto out;
3823 /* Set up identity-mapping pagetable for EPT in real mode */
3824 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3825 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3826 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3827 r = kvm_write_guest_page(kvm, identity_map_pfn,
3828 &tmp, i * sizeof(tmp), sizeof(tmp));
3829 if (r < 0)
3830 goto out;
3831 }
3832 kvm->arch.ept_identity_pagetable_done = true;
3833 ret = 1;
3834out:
40dcaa9f 3835 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3836 return ret;
3837}
3838
6aa8b732
AK		 3839static void seg_setup(int seg)
3840{
772e0318 3841 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3842 unsigned int ar;
6aa8b732
AK		 3843
3844 vmcs_write16(sf->selector, 0);
3845 vmcs_writel(sf->base, 0);
3846 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3847 ar = 0x93;
3848 if (seg == VCPU_SREG_CS)
3849 ar |= 0x08; /* code segment */
3a624e29
NK		 3850
3851 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3852}
3853
f78e0e2e
SY		 3854static int alloc_apic_access_page(struct kvm *kvm)
3855{
4484141a 3856 struct page *page;
f78e0e2e
SY		 3857 struct kvm_userspace_memory_region kvm_userspace_mem;
3858 int r = 0;
3859
79fac95e 3860 mutex_lock(&kvm->slots_lock);
bfc6d222 3861 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3862 goto out;
3863 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3864 kvm_userspace_mem.flags = 0;
3865 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3866 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3867 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3868 if (r)
3869 goto out;
72dc67a6 3870
4484141a
XG		 3871 page = gfn_to_page(kvm, 0xfee00);
3872 if (is_error_page(page)) {
3873 r = -EFAULT;
3874 goto out;
3875 }
3876
3877 kvm->arch.apic_access_page = page;
f78e0e2e 3878out:
79fac95e 3879 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3880 return r;
3881}
3882
b7ebfb05
SY		 3883static int alloc_identity_pagetable(struct kvm *kvm)
3884{
4484141a 3885 struct page *page;
b7ebfb05
SY		 3886 struct kvm_userspace_memory_region kvm_userspace_mem;
3887 int r = 0;
3888
79fac95e 3889 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3890 if (kvm->arch.ept_identity_pagetable)
3891 goto out;
3892 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3893 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3894 kvm_userspace_mem.guest_phys_addr =
3895 kvm->arch.ept_identity_map_addr;
b7ebfb05 3896 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3897 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3898 if (r)
3899 goto out;
3900
4484141a
XG		 3901 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3902 if (is_error_page(page)) {
3903 r = -EFAULT;
3904 goto out;
3905 }
3906
3907 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3908out:
79fac95e 3909 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3910 return r;
3911}
3912
2384d2b3
SY		 3913static void allocate_vpid(struct vcpu_vmx *vmx)
3914{
3915 int vpid;
3916
3917 vmx->vpid = 0;
919818ab 3918 if (!enable_vpid)
2384d2b3
SY		 3919 return;
3920 spin_lock(&vmx_vpid_lock);
3921 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3922 if (vpid < VMX_NR_VPIDS) {
3923 vmx->vpid = vpid;
3924 __set_bit(vpid, vmx_vpid_bitmap);
3925 }
3926 spin_unlock(&vmx_vpid_lock);
3927}
3928
cdbecfc3
LJ		 3929static void free_vpid(struct vcpu_vmx *vmx)
3930{
3931 if (!enable_vpid)
3932 return;
3933 spin_lock(&vmx_vpid_lock);
3934 if (vmx->vpid != 0)
3935 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3936 spin_unlock(&vmx_vpid_lock);
3937}
3938
8d14695f
YZ		 3939#define MSR_TYPE_R 1
3940#define MSR_TYPE_W 2
3941static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3942 u32 msr, int type)
25c5f225 3943{
3e7c73e9 3944 int f = sizeof(unsigned long);
25c5f225
SY		 3945
3946 if (!cpu_has_vmx_msr_bitmap())
3947 return;
3948
3949 /*
3950 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3951 * have the write-low and read-high bitmap offsets the wrong way round.
3952 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3953 */
25c5f225 3954 if (msr <= 0x1fff) {
8d14695f
YZ		 3955 if (type & MSR_TYPE_R)
3956 /* read-low */
3957 __clear_bit(msr, msr_bitmap + 0x000 / f);
3958
3959 if (type & MSR_TYPE_W)
3960 /* write-low */
3961 __clear_bit(msr, msr_bitmap + 0x800 / f);
3962
25c5f225
SY		 3963 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3964 msr &= 0x1fff;
8d14695f
YZ		 3965 if (type & MSR_TYPE_R)
3966 /* read-high */
3967 __clear_bit(msr, msr_bitmap + 0x400 / f);
3968
3969 if (type & MSR_TYPE_W)
3970 /* write-high */
3971 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3972
3973 }
3974}
3975
3976static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3977 u32 msr, int type)
3978{
3979 int f = sizeof(unsigned long);
3980
3981 if (!cpu_has_vmx_msr_bitmap())
3982 return;
3983
3984 /*
3985 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3986 * have the write-low and read-high bitmap offsets the wrong way round.
3987 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3988 */
3989 if (msr <= 0x1fff) {
3990 if (type & MSR_TYPE_R)
3991 /* read-low */
3992 __set_bit(msr, msr_bitmap + 0x000 / f);
3993
3994 if (type & MSR_TYPE_W)
3995 /* write-low */
3996 __set_bit(msr, msr_bitmap + 0x800 / f);
3997
3998 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3999 msr &= 0x1fff;
4000 if (type & MSR_TYPE_R)
4001 /* read-high */
4002 __set_bit(msr, msr_bitmap + 0x400 / f);
4003
4004 if (type & MSR_TYPE_W)
4005 /* write-high */
4006 __set_bit(msr, msr_bitmap + 0xc00 / f);
4007
25c5f225 4008 }
25c5f225
SY		 4009}
4010
5897297b
AK		 4011static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4012{
4013 if (!longmode_only)
8d14695f
YZ		 4014 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4015 msr, MSR_TYPE_R | MSR_TYPE_W);
4016 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4017 msr, MSR_TYPE_R | MSR_TYPE_W);
4018}
4019
4020static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4021{
4022 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4023 msr, MSR_TYPE_R);
4024 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4025 msr, MSR_TYPE_R);
4026}
4027
4028static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4029{
4030 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4031 msr, MSR_TYPE_R);
4032 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4033 msr, MSR_TYPE_R);
4034}
4035
4036static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4037{
4038 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4039 msr, MSR_TYPE_W);
4040 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4041 msr, MSR_TYPE_W);
5897297b
AK		 4042}
4043
01e439be
YZ		 4044static int vmx_vm_has_apicv(struct kvm *kvm)
4045{
4046 return enable_apicv && irqchip_in_kernel(kvm);
4047}
4048
a20ed54d
YZ		 4049/*
4050 * Send interrupt to vcpu via posted interrupt way.
4051 * 1. If target vcpu is running(non-root mode), send posted interrupt
4052 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4053 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4054 * interrupt from PIR in next vmentry.
4055 */
4056static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4057{
4058 struct vcpu_vmx *vmx = to_vmx(vcpu);
4059 int r;
4060
4061 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4062 return;
4063
4064 r = pi_test_and_set_on(&vmx->pi_desc);
4065 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4066#ifdef CONFIG_SMP
a20ed54d
YZ		 4067 if (!r && (vcpu->mode == IN_GUEST_MODE))
4068 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4069 POSTED_INTR_VECTOR);
4070 else
6ffbbbba 4071#endif
a20ed54d
YZ		 4072 kvm_vcpu_kick(vcpu);
4073}
4074
4075static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4076{
4077 struct vcpu_vmx *vmx = to_vmx(vcpu);
4078
4079 if (!pi_test_and_clear_on(&vmx->pi_desc))
4080 return;
4081
4082 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4083}
4084
4085static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4086{
4087 return;
4088}
4089
a3a8ff8e
NHE		 4090/*
4091 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4092 * will not change in the lifetime of the guest.
4093 * Note that host-state that does change is set elsewhere. E.g., host-state
4094 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4095 */
a547c6db 4096static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4097{
4098 u32 low32, high32;
4099 unsigned long tmpl;
4100 struct desc_ptr dt;
4101
b1a74bf8 4102 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4103 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4104 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4105
4106 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4107#ifdef CONFIG_X86_64
4108 /*
4109 * Load null selectors, so we can avoid reloading them in
4110 * __vmx_load_host_state(), in case userspace uses the null selectors
4111 * too (the expected case).
4112 */
4113 vmcs_write16(HOST_DS_SELECTOR, 0);
4114 vmcs_write16(HOST_ES_SELECTOR, 0);
4115#else
a3a8ff8e
NHE		 4116 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4117 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4118#endif
a3a8ff8e
NHE		 4119 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4120 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4121
4122 native_store_idt(&dt);
4123 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4124 vmx->host_idt_base = dt.address;
a3a8ff8e 4125
83287ea4 4126 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4127
4128 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4129 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4130 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4131 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4132
4133 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4134 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4135 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4136 }
4137}
4138
bf8179a0
NHE		 4139static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4140{
4141 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4142 if (enable_ept)
4143 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4144 if (is_guest_mode(&vmx->vcpu))
4145 vmx->vcpu.arch.cr4_guest_owned_bits &=
4146 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4147 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4148}
4149
01e439be
YZ		 4150static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4151{
4152 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4153
4154 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4155 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4156 return pin_based_exec_ctrl;
4157}
4158
bf8179a0
NHE		 4159static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4160{
4161 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4162 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4163 exec_control &= ~CPU_BASED_TPR_SHADOW;
4164#ifdef CONFIG_X86_64
4165 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4166 CPU_BASED_CR8_LOAD_EXITING;
4167#endif
4168 }
4169 if (!enable_ept)
4170 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4171 CPU_BASED_CR3_LOAD_EXITING |
4172 CPU_BASED_INVLPG_EXITING;
4173 return exec_control;
4174}
4175
4176static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4177{
4178 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4179 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4180 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4181 if (vmx->vpid == 0)
4182 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4183 if (!enable_ept) {
4184 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4185 enable_unrestricted_guest = 0;
ad756a16
MJ		 4186 /* Enable INVPCID for non-ept guests may cause performance regression. */
4187 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4188 }
4189 if (!enable_unrestricted_guest)
4190 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4191 if (!ple_gap)
4192 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4193 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4194 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4195 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4196 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4197 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4198 (handle_vmptrld).
4199 We can NOT enable shadow_vmcs here because we don't have yet
4200 a current VMCS12
4201 */
4202 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4203 return exec_control;
4204}
4205
ce88decf
XG		 4206static void ept_set_mmio_spte_mask(void)
4207{
4208 /*
4209 * EPT Misconfigurations can be generated if the value of bits 2:0
4210 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4211 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4212 * spte.
4213 */
885032b9 4214 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4215}
4216
6aa8b732
AK		 4217/*
4218 * Sets up the vmcs for emulated real mode.
4219 */
8b9cf98c 4220static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4221{
2e4ce7f5 4222#ifdef CONFIG_X86_64
6aa8b732 4223 unsigned long a;
2e4ce7f5 4224#endif
6aa8b732 4225 int i;
6aa8b732 4226
6aa8b732 4227 /* I/O */
3e7c73e9
AK		 4228 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4229 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4230
4607c2d7
AG		 4231 if (enable_shadow_vmcs) {
4232 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4233 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4234 }
25c5f225 4235 if (cpu_has_vmx_msr_bitmap())
5897297b 4236 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4237
6aa8b732
AK		 4238 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4239
6aa8b732 4240 /* Control */
01e439be 4241 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4242
bf8179a0 4243 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4244
83ff3b9d 4245 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4246 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4247 vmx_secondary_exec_control(vmx));
83ff3b9d 4248 }
f78e0e2e 4249
01e439be 4250 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4251 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4252 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4253 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4254 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4255
4256 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4257
4258 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4259 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4260 }
4261
4b8d54f9
ZE		 4262 if (ple_gap) {
4263 vmcs_write32(PLE_GAP, ple_gap);
4264 vmcs_write32(PLE_WINDOW, ple_window);
4265 }
4266
c3707958
XG		 4267 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4268 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4269 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4270
9581d442
AK		 4271 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4272 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4273 vmx_set_constant_host_state(vmx);
05b3e0c2 4274#ifdef CONFIG_X86_64
6aa8b732
AK		 4275 rdmsrl(MSR_FS_BASE, a);
4276 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4277 rdmsrl(MSR_GS_BASE, a);
4278 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4279#else
4280 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4281 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4282#endif
4283
2cc51560
ED		 4284 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4285 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4286 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4287 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4288 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4289
468d472f 4290 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4291 u32 msr_low, msr_high;
4292 u64 host_pat;
468d472f
SY		 4293 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4294 host_pat = msr_low | ((u64) msr_high << 32);
4295 /* Write the default value follow host pat */
4296 vmcs_write64(GUEST_IA32_PAT, host_pat);
4297 /* Keep arch.pat sync with GUEST_IA32_PAT */
4298 vmx->vcpu.arch.pat = host_pat;
4299 }
4300
6aa8b732
AK		 4301 for (i = 0; i < NR_VMX_MSR; ++i) {
4302 u32 index = vmx_msr_index[i];
4303 u32 data_low, data_high;
a2fa3e9f 4304 int j = vmx->nmsrs;
6aa8b732
AK		 4305
4306 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4307 continue;
432bd6cb
AK		 4308 if (wrmsr_safe(index, data_low, data_high) < 0)
4309 continue;
26bb0981
AK		 4310 vmx->guest_msrs[j].index = i;
4311 vmx->guest_msrs[j].data = 0;
d5696725 4312 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4313 ++vmx->nmsrs;
6aa8b732 4314 }
6aa8b732 4315
1c3d14fe 4316 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4317
4318 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4319 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4320
e00c8cf2 4321 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4322 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4323
4324 return 0;
4325}
4326
57f252f2 4327static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4328{
4329 struct vcpu_vmx *vmx = to_vmx(vcpu);
4330 u64 msr;
e00c8cf2 4331
7ffd92c5 4332 vmx->rmode.vm86_active = 0;
e00c8cf2 4333
3b86cd99
JK		 4334 vmx->soft_vnmi_blocked = 0;
4335
ad312c7c 4336 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4337 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4338 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4339 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4340 msr |= MSR_IA32_APICBASE_BSP;
4341 kvm_set_apic_base(&vmx->vcpu, msr);
4342
2fb92db1
AK		 4343 vmx_segment_cache_clear(vmx);
4344
5706be0d 4345 seg_setup(VCPU_SREG_CS);
66450a21 4346 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4347 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4348
4349 seg_setup(VCPU_SREG_DS);
4350 seg_setup(VCPU_SREG_ES);
4351 seg_setup(VCPU_SREG_FS);
4352 seg_setup(VCPU_SREG_GS);
4353 seg_setup(VCPU_SREG_SS);
4354
4355 vmcs_write16(GUEST_TR_SELECTOR, 0);
4356 vmcs_writel(GUEST_TR_BASE, 0);
4357 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4358 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4359
4360 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4361 vmcs_writel(GUEST_LDTR_BASE, 0);
4362 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4363 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4364
4365 vmcs_write32(GUEST_SYSENTER_CS, 0);
4366 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4367 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4368
4369 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4370 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4371
e00c8cf2
AK		 4372 vmcs_writel(GUEST_GDTR_BASE, 0);
4373 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4374
4375 vmcs_writel(GUEST_IDTR_BASE, 0);
4376 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4377
443381a8 4378 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4379 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4380 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4381
e00c8cf2
AK		 4382 /* Special registers */
4383 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4384
4385 setup_msrs(vmx);
4386
6aa8b732
AK		 4387 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4388
f78e0e2e
SY		 4389 if (cpu_has_vmx_tpr_shadow()) {
4390 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4391 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4392 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4393 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4394 vmcs_write32(TPR_THRESHOLD, 0);
4395 }
4396
4397 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4398 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4399 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4400
01e439be
YZ		 4401 if (vmx_vm_has_apicv(vcpu->kvm))
4402 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4403
2384d2b3
SY		 4404 if (vmx->vpid != 0)
4405 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4406
fa40052c 4407 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4408 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4409 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4410 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4411 vmx_fpu_activate(&vmx->vcpu);
4412 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4413
b9d762fa 4414 vpid_sync_context(vmx);
6aa8b732
AK		 4415}
4416
b6f1250e
NHE		 4417/*
4418 * In nested virtualization, check if L1 asked to exit on external interrupts.
4419 * For most existing hypervisors, this will always return true.
4420 */
4421static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4422{
4423 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4424 PIN_BASED_EXT_INTR_MASK;
4425}
4426
ea8ceb83
JK		 4427static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4428{
4429 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4430 PIN_BASED_NMI_EXITING;
4431}
4432
730dca42 4433static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4434{
4435 u32 cpu_based_vm_exec_control;
730dca42
JK		 4436
4437 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4438 /*
4439 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4440 * inject to L1 now because L2 must run. The caller will have
4441 * to make L2 exit right after entry, so we can inject to L1
4442 * more promptly.
b6f1250e 4443 */
730dca42 4444 return -EBUSY;
3b86cd99
JK		 4445
4446 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4447 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4448 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4449 return 0;
3b86cd99
JK		 4450}
4451
03b28f81 4452static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4453{
4454 u32 cpu_based_vm_exec_control;
4455
03b28f81
JK		 4456 if (!cpu_has_virtual_nmis())
4457 return enable_irq_window(vcpu);
4458
4459 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4460 return enable_irq_window(vcpu);
3b86cd99
JK		 4461
4462 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4463 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4464 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4465 return 0;
3b86cd99
JK		 4466}
4467
66fd3f7f 4468static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4469{
9c8cba37 4470 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4471 uint32_t intr;
4472 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4473
229456fc 4474 trace_kvm_inj_virq(irq);
2714d1d3 4475
fa89a817 4476 ++vcpu->stat.irq_injections;
7ffd92c5 4477 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4478 int inc_eip = 0;
4479 if (vcpu->arch.interrupt.soft)
4480 inc_eip = vcpu->arch.event_exit_inst_len;
4481 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4482 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4483 return;
4484 }
66fd3f7f
GN		 4485 intr = irq | INTR_INFO_VALID_MASK;
4486 if (vcpu->arch.interrupt.soft) {
4487 intr |= INTR_TYPE_SOFT_INTR;
4488 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4489 vmx->vcpu.arch.event_exit_inst_len);
4490 } else
4491 intr |= INTR_TYPE_EXT_INTR;
4492 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4493}
4494
f08864b4
SY		 4495static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4496{
66a5a347
JK		 4497 struct vcpu_vmx *vmx = to_vmx(vcpu);
4498
0b6ac343
NHE		 4499 if (is_guest_mode(vcpu))
4500 return;
4501
3b86cd99
JK		 4502 if (!cpu_has_virtual_nmis()) {
4503 /*
4504 * Tracking the NMI-blocked state in software is built upon
4505 * finding the next open IRQ window. This, in turn, depends on
4506 * well-behaving guests: They have to keep IRQs disabled at
4507 * least as long as the NMI handler runs. Otherwise we may
4508 * cause NMI nesting, maybe breaking the guest. But as this is
4509 * highly unlikely, we can live with the residual risk.
4510 */
4511 vmx->soft_vnmi_blocked = 1;
4512 vmx->vnmi_blocked_time = 0;
4513 }
4514
487b391d 4515 ++vcpu->stat.nmi_injections;
9d58b931 4516 vmx->nmi_known_unmasked = false;
7ffd92c5 4517 if (vmx->rmode.vm86_active) {
71f9833b 4518 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4519 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4520 return;
4521 }
f08864b4
SY		 4522 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4523 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4524}
4525
3cfc3092
JK		 4526static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4527{
4528 if (!cpu_has_virtual_nmis())
4529 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4530 if (to_vmx(vcpu)->nmi_known_unmasked)
4531 return false;
c332c83a 4532 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4533}
4534
4535static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4536{
4537 struct vcpu_vmx *vmx = to_vmx(vcpu);
4538
4539 if (!cpu_has_virtual_nmis()) {
4540 if (vmx->soft_vnmi_blocked != masked) {
4541 vmx->soft_vnmi_blocked = masked;
4542 vmx->vnmi_blocked_time = 0;
4543 }
4544 } else {
9d58b931 4545 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4546 if (masked)
4547 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4548 GUEST_INTR_STATE_NMI);
4549 else
4550 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4551 GUEST_INTR_STATE_NMI);
4552 }
4553}
4554
2505dc9f
JK		 4555static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4556{
ea8ceb83
JK		 4557 if (is_guest_mode(vcpu)) {
4558 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4559
4560 if (to_vmx(vcpu)->nested.nested_run_pending)
4561 return 0;
4562 if (nested_exit_on_nmi(vcpu)) {
4563 nested_vmx_vmexit(vcpu);
4564 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4565 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4566 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4567 /*
4568 * The NMI-triggered VM exit counts as injection:
4569 * clear this one and block further NMIs.
4570 */
4571 vcpu->arch.nmi_pending = 0;
4572 vmx_set_nmi_mask(vcpu, true);
4573 return 0;
4574 }
4575 }
4576
2505dc9f
JK		 4577 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4578 return 0;
4579
4580 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4581 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4582 | GUEST_INTR_STATE_NMI));
4583}
4584
78646121
GN		 4585static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4586{
e8457c67 4587 if (is_guest_mode(vcpu)) {
51cfe38e 4588 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4589
4590 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4591 return 0;
e8457c67
JK		 4592 if (nested_exit_on_intr(vcpu)) {
4593 nested_vmx_vmexit(vcpu);
4594 vmcs12->vm_exit_reason =
4595 EXIT_REASON_EXTERNAL_INTERRUPT;
4596 vmcs12->vm_exit_intr_info = 0;
4597 /*
4598 * fall through to normal code, but now in L1, not L2
4599 */
4600 }
b6f1250e
NHE		 4601 }
4602
c4282df9
GN		 4603 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4604 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4605 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4606}
4607
cbc94022
IE		 4608static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4609{
4610 int ret;
4611 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4612 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4613 .guest_phys_addr = addr,
4614 .memory_size = PAGE_SIZE * 3,
4615 .flags = 0,
4616 };
4617
47ae31e2 4618 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4619 if (ret)
4620 return ret;
bfc6d222 4621 kvm->arch.tss_addr = addr;
93ea5388
GN		 4622 if (!init_rmode_tss(kvm))
4623 return -ENOMEM;
4624
cbc94022
IE		 4625 return 0;
4626}
4627
0ca1b4f4 4628static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4629{
77ab6db0 4630 switch (vec) {
77ab6db0 4631 case BP_VECTOR:
c573cd22
JK		 4632 /*
4633 * Update instruction length as we may reinject the exception
4634 * from user space while in guest debugging mode.
4635 */
4636 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4637 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4638 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4639 return false;
4640 /* fall through */
4641 case DB_VECTOR:
4642 if (vcpu->guest_debug &
4643 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4644 return false;
d0bfb940
JK		 4645 /* fall through */
4646 case DE_VECTOR:
77ab6db0
JK		 4647 case OF_VECTOR:
4648 case BR_VECTOR:
4649 case UD_VECTOR:
4650 case DF_VECTOR:
4651 case SS_VECTOR:
4652 case GP_VECTOR:
4653 case MF_VECTOR:
0ca1b4f4
GN		 4654 return true;
4655 break;
77ab6db0 4656 }
0ca1b4f4
GN		 4657 return false;
4658}
4659
4660static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4661 int vec, u32 err_code)
4662{
4663 /*
4664 * Instruction with address size override prefix opcode 0x67
4665 * Cause the #SS fault with 0 error code in VM86 mode.
4666 */
4667 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4668 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4669 if (vcpu->arch.halt_request) {
4670 vcpu->arch.halt_request = 0;
4671 return kvm_emulate_halt(vcpu);
4672 }
4673 return 1;
4674 }
4675 return 0;
4676 }
4677
4678 /*
4679 * Forward all other exceptions that are valid in real mode.
4680 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4681 * the required debugging infrastructure rework.
4682 */
4683 kvm_queue_exception(vcpu, vec);
4684 return 1;
6aa8b732
AK		 4685}
4686
a0861c02
AK		 4687/*
4688 * Trigger machine check on the host. We assume all the MSRs are already set up
4689 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4690 * We pass a fake environment to the machine check handler because we want
4691 * the guest to be always treated like user space, no matter what context
4692 * it used internally.
4693 */
4694static void kvm_machine_check(void)
4695{
4696#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4697 struct pt_regs regs = {
4698 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4699 .flags = X86_EFLAGS_IF,
4700 };
4701
4702 do_machine_check(&regs, 0);
4703#endif
4704}
4705
851ba692 4706static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4707{
4708 /* already handled by vcpu_run */
4709 return 1;
4710}
4711
851ba692 4712static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4713{
1155f76a 4714 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4715 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4716 u32 intr_info, ex_no, error_code;
42dbaa5a 4717 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4718 u32 vect_info;
4719 enum emulation_result er;
4720
1155f76a 4721 vect_info = vmx->idt_vectoring_info;
88786475 4722 intr_info = vmx->exit_intr_info;
6aa8b732 4723
a0861c02 4724 if (is_machine_check(intr_info))
851ba692 4725 return handle_machine_check(vcpu);
a0861c02 4726
e4a41889 4727 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4728 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4729
4730 if (is_no_device(intr_info)) {
5fd86fcf 4731 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4732 return 1;
4733 }
4734
7aa81cc0 4735 if (is_invalid_opcode(intr_info)) {
51d8b661 4736 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4737 if (er != EMULATE_DONE)
7ee5d940 4738 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4739 return 1;
4740 }
4741
6aa8b732 4742 error_code = 0;
2e11384c 4743 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4744 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4745
4746 /*
4747 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4748 * MMIO, it is better to report an internal error.
4749 * See the comments in vmx_handle_exit.
4750 */
4751 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4752 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4753 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4754 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4755 vcpu->run->internal.ndata = 2;
4756 vcpu->run->internal.data[0] = vect_info;
4757 vcpu->run->internal.data[1] = intr_info;
4758 return 0;
4759 }
4760
6aa8b732 4761 if (is_page_fault(intr_info)) {
1439442c 4762 /* EPT won't cause page fault directly */
cf3ace79 4763 BUG_ON(enable_ept);
6aa8b732 4764 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4765 trace_kvm_page_fault(cr2, error_code);
4766
3298b75c 4767 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4768 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4769 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4770 }
4771
d0bfb940 4772 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4773
4774 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4775 return handle_rmode_exception(vcpu, ex_no, error_code);
4776
42dbaa5a
JK		 4777 switch (ex_no) {
4778 case DB_VECTOR:
4779 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4780 if (!(vcpu->guest_debug &
4781 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4782 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4783 kvm_queue_exception(vcpu, DB_VECTOR);
4784 return 1;
4785 }
4786 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4787 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4788 /* fall through */
4789 case BP_VECTOR:
c573cd22
JK		 4790 /*
4791 * Update instruction length as we may reinject #BP from
4792 * user space while in guest debugging mode. Reading it for
4793 * #DB as well causes no harm, it is not used in that case.
4794 */
4795 vmx->vcpu.arch.event_exit_inst_len =
4796 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4797 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4798 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4799 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4800 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4801 break;
4802 default:
d0bfb940
JK		 4803 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4804 kvm_run->ex.exception = ex_no;
4805 kvm_run->ex.error_code = error_code;
42dbaa5a 4806 break;
6aa8b732 4807 }
6aa8b732
AK		 4808 return 0;
4809}
4810
851ba692 4811static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4812{
1165f5fe 4813 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4814 return 1;
4815}
4816
851ba692 4817static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4818{
851ba692 4819 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4820 return 0;
4821}
6aa8b732 4822
851ba692 4823static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4824{
bfdaab09 4825 unsigned long exit_qualification;
34c33d16 4826 int size, in, string;
039576c0 4827 unsigned port;
6aa8b732 4828
bfdaab09 4829 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4830 string = (exit_qualification & 16) != 0;
cf8f70bf 4831 in = (exit_qualification & 8) != 0;
e70669ab 4832
cf8f70bf 4833 ++vcpu->stat.io_exits;
e70669ab 4834
cf8f70bf 4835 if (string || in)
51d8b661 4836 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4837
cf8f70bf
GN		 4838 port = exit_qualification >> 16;
4839 size = (exit_qualification & 7) + 1;
e93f36bc 4840 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4841
4842 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4843}
4844
102d8325
IM		 4845static void
4846vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4847{
4848 /*
4849 * Patch in the VMCALL instruction:
4850 */
4851 hypercall[0] = 0x0f;
4852 hypercall[1] = 0x01;
4853 hypercall[2] = 0xc1;
102d8325
IM		 4854}
4855
0fa06071 4856/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4857static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4858{
eeadf9e7 4859 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4860 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4861 unsigned long orig_val = val;
4862
eeadf9e7
NHE		 4863 /*
4864 * We get here when L2 changed cr0 in a way that did not change
4865 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4866 * but did change L0 shadowed bits. So we first calculate the
4867 * effective cr0 value that L1 would like to write into the
4868 * hardware. It consists of the L2-owned bits from the new
4869 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4870 */
1a0d74e6
JK		 4871 val = (val & ~vmcs12->cr0_guest_host_mask) |
4872 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4873
4874 /* TODO: will have to take unrestricted guest mode into
4875 * account */
4876 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4877 return 1;
1a0d74e6
JK		 4878
4879 if (kvm_set_cr0(vcpu, val))
4880 return 1;
4881 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4882 return 0;
1a0d74e6
JK		 4883 } else {
4884 if (to_vmx(vcpu)->nested.vmxon &&
4885 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4886 return 1;
eeadf9e7 4887 return kvm_set_cr0(vcpu, val);
1a0d74e6 4888 }
eeadf9e7
NHE		 4889}
4890
4891static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4892{
4893 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4894 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4895 unsigned long orig_val = val;
4896
4897 /* analogously to handle_set_cr0 */
4898 val = (val & ~vmcs12->cr4_guest_host_mask) |
4899 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4900 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4901 return 1;
1a0d74e6 4902 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4903 return 0;
4904 } else
4905 return kvm_set_cr4(vcpu, val);
4906}
4907
4908/* called to set cr0 as approriate for clts instruction exit. */
4909static void handle_clts(struct kvm_vcpu *vcpu)
4910{
4911 if (is_guest_mode(vcpu)) {
4912 /*
4913 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4914 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4915 * just pretend it's off (also in arch.cr0 for fpu_activate).
4916 */
4917 vmcs_writel(CR0_READ_SHADOW,
4918 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4919 vcpu->arch.cr0 &= ~X86_CR0_TS;
4920 } else
4921 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4922}
4923
851ba692 4924static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4925{
229456fc 4926 unsigned long exit_qualification, val;
6aa8b732
AK		 4927 int cr;
4928 int reg;
49a9b07e 4929 int err;
6aa8b732 4930
bfdaab09 4931 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4932 cr = exit_qualification & 15;
4933 reg = (exit_qualification >> 8) & 15;
4934 switch ((exit_qualification >> 4) & 3) {
4935 case 0: /* mov to cr */
229456fc
MT		 4936 val = kvm_register_read(vcpu, reg);
4937 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4938 switch (cr) {
4939 case 0:
eeadf9e7 4940 err = handle_set_cr0(vcpu, val);
db8fcefa 4941 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4942 return 1;
4943 case 3:
2390218b 4944 err = kvm_set_cr3(vcpu, val);
db8fcefa 4945 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4946 return 1;
4947 case 4:
eeadf9e7 4948 err = handle_set_cr4(vcpu, val);
db8fcefa 4949 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4950 return 1;
0a5fff19
GN		 4951 case 8: {
4952 u8 cr8_prev = kvm_get_cr8(vcpu);
4953 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4954 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4955 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4956 if (irqchip_in_kernel(vcpu->kvm))
4957 return 1;
4958 if (cr8_prev <= cr8)
4959 return 1;
851ba692 4960 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4961 return 0;
4962 }
4b8073e4 4963 }
6aa8b732 4964 break;
25c4c276 4965 case 2: /* clts */
eeadf9e7 4966 handle_clts(vcpu);
4d4ec087 4967 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4968 skip_emulated_instruction(vcpu);
6b52d186 4969 vmx_fpu_activate(vcpu);
25c4c276 4970 return 1;
6aa8b732
AK		 4971 case 1: /*mov from cr*/
4972 switch (cr) {
4973 case 3:
9f8fe504
AK		 4974 val = kvm_read_cr3(vcpu);
4975 kvm_register_write(vcpu, reg, val);
4976 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4977 skip_emulated_instruction(vcpu);
4978 return 1;
4979 case 8:
229456fc
MT		 4980 val = kvm_get_cr8(vcpu);
4981 kvm_register_write(vcpu, reg, val);
4982 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4983 skip_emulated_instruction(vcpu);
4984 return 1;
4985 }
4986 break;
4987 case 3: /* lmsw */
a1f83a74 4988 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4989 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4990 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4991
4992 skip_emulated_instruction(vcpu);
4993 return 1;
4994 default:
4995 break;
4996 }
851ba692 4997 vcpu->run->exit_reason = 0;
a737f256 4998 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4999 (int)(exit_qualification >> 4) & 3, cr);
5000 return 0;
5001}
5002
851ba692 5003static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5004{
bfdaab09 5005 unsigned long exit_qualification;
6aa8b732
AK		 5006 int dr, reg;
5007
f2483415 5008 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5009 if (!kvm_require_cpl(vcpu, 0))
5010 return 1;
42dbaa5a
JK		 5011 dr = vmcs_readl(GUEST_DR7);
5012 if (dr & DR7_GD) {
5013 /*
5014 * As the vm-exit takes precedence over the debug trap, we
5015 * need to emulate the latter, either for the host or the
5016 * guest debugging itself.
5017 */
5018 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5019 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5020 vcpu->run->debug.arch.dr7 = dr;
5021 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5022 vmcs_readl(GUEST_CS_BASE) +
5023 vmcs_readl(GUEST_RIP);
851ba692
AK		 5024 vcpu->run->debug.arch.exception = DB_VECTOR;
5025 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5026 return 0;
5027 } else {
5028 vcpu->arch.dr7 &= ~DR7_GD;
5029 vcpu->arch.dr6 |= DR6_BD;
5030 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5031 kvm_queue_exception(vcpu, DB_VECTOR);
5032 return 1;
5033 }
5034 }
5035
bfdaab09 5036 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5037 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5038 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5039 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5040 unsigned long val;
5041 if (!kvm_get_dr(vcpu, dr, &val))
5042 kvm_register_write(vcpu, reg, val);
5043 } else
5044 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5045 skip_emulated_instruction(vcpu);
5046 return 1;
5047}
5048
020df079
GN		 5049static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5050{
5051 vmcs_writel(GUEST_DR7, val);
5052}
5053
851ba692 5054static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5055{
06465c5a
AK		 5056 kvm_emulate_cpuid(vcpu);
5057 return 1;
6aa8b732
AK		 5058}
5059
851ba692 5060static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5061{
ad312c7c 5062 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5063 u64 data;
5064
5065 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5066 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5067 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5068 return 1;
5069 }
5070
229456fc 5071 trace_kvm_msr_read(ecx, data);
2714d1d3 5072
6aa8b732 5073 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5074 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5075 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5076 skip_emulated_instruction(vcpu);
5077 return 1;
5078}
5079
851ba692 5080static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5081{
8fe8ab46 5082 struct msr_data msr;
ad312c7c
ZX		 5083 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5084 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5085 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5086
8fe8ab46
WA		 5087 msr.data = data;
5088 msr.index = ecx;
5089 msr.host_initiated = false;
5090 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5091 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5092 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5093 return 1;
5094 }
5095
59200273 5096 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5097 skip_emulated_instruction(vcpu);
5098 return 1;
5099}
5100
851ba692 5101static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5102{
3842d135 5103 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5104 return 1;
5105}
5106
851ba692 5107static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5108{
85f455f7
ED		 5109 u32 cpu_based_vm_exec_control;
5110
5111 /* clear pending irq */
5112 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5113 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5114 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5115
3842d135
AK		 5116 kvm_make_request(KVM_REQ_EVENT, vcpu);
5117
a26bf12a 5118 ++vcpu->stat.irq_window_exits;
2714d1d3 5119
c1150d8c
DL		 5120 /*
5121 * If the user space waits to inject interrupts, exit as soon as
5122 * possible
5123 */
8061823a 5124 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5125 vcpu->run->request_interrupt_window &&
8061823a 5126 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5127 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5128 return 0;
5129 }
6aa8b732
AK		 5130 return 1;
5131}
5132
851ba692 5133static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5134{
5135 skip_emulated_instruction(vcpu);
d3bef15f 5136 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5137}
5138
851ba692 5139static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5140{
510043da 5141 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5142 kvm_emulate_hypercall(vcpu);
5143 return 1;
c21415e8
IM		 5144}
5145
ec25d5e6
GN		 5146static int handle_invd(struct kvm_vcpu *vcpu)
5147{
51d8b661 5148 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5149}
5150
851ba692 5151static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5152{
f9c617f6 5153 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5154
5155 kvm_mmu_invlpg(vcpu, exit_qualification);
5156 skip_emulated_instruction(vcpu);
5157 return 1;
5158}
5159
fee84b07
AK		 5160static int handle_rdpmc(struct kvm_vcpu *vcpu)
5161{
5162 int err;
5163
5164 err = kvm_rdpmc(vcpu);
5165 kvm_complete_insn_gp(vcpu, err);
5166
5167 return 1;
5168}
5169
851ba692 5170static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5171{
5172 skip_emulated_instruction(vcpu);
f5f48ee1 5173 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5174 return 1;
5175}
5176
2acf923e
DC		 5177static int handle_xsetbv(struct kvm_vcpu *vcpu)
5178{
5179 u64 new_bv = kvm_read_edx_eax(vcpu);
5180 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5181
5182 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5183 skip_emulated_instruction(vcpu);
5184 return 1;
5185}
5186
851ba692 5187static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5188{
58fbbf26
KT		 5189 if (likely(fasteoi)) {
5190 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5191 int access_type, offset;
5192
5193 access_type = exit_qualification & APIC_ACCESS_TYPE;
5194 offset = exit_qualification & APIC_ACCESS_OFFSET;
5195 /*
5196 * Sane guest uses MOV to write EOI, with written value
5197 * not cared. So make a short-circuit here by avoiding
5198 * heavy instruction emulation.
5199 */
5200 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5201 (offset == APIC_EOI)) {
5202 kvm_lapic_set_eoi(vcpu);
5203 skip_emulated_instruction(vcpu);
5204 return 1;
5205 }
5206 }
51d8b661 5207 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5208}
5209
c7c9c56c
YZ		 5210static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5211{
5212 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5213 int vector = exit_qualification & 0xff;
5214
5215 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5216 kvm_apic_set_eoi_accelerated(vcpu, vector);
5217 return 1;
5218}
5219
83d4c286
YZ		 5220static int handle_apic_write(struct kvm_vcpu *vcpu)
5221{
5222 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5223 u32 offset = exit_qualification & 0xfff;
5224
5225 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5226 kvm_apic_write_nodecode(vcpu, offset);
5227 return 1;
5228}
5229
851ba692 5230static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5231{
60637aac 5232 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5233 unsigned long exit_qualification;
e269fb21
JK		 5234 bool has_error_code = false;
5235 u32 error_code = 0;
37817f29 5236 u16 tss_selector;
7f3d35fd 5237 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5238
5239 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5240 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5241 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5242
5243 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5244
5245 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5246 if (reason == TASK_SWITCH_GATE && idt_v) {
5247 switch (type) {
5248 case INTR_TYPE_NMI_INTR:
5249 vcpu->arch.nmi_injected = false;
654f06fc 5250 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5251 break;
5252 case INTR_TYPE_EXT_INTR:
66fd3f7f 5253 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5254 kvm_clear_interrupt_queue(vcpu);
5255 break;
5256 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5257 if (vmx->idt_vectoring_info &
5258 VECTORING_INFO_DELIVER_CODE_MASK) {
5259 has_error_code = true;
5260 error_code =
5261 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5262 }
5263 /* fall through */
64a7ec06
GN		 5264 case INTR_TYPE_SOFT_EXCEPTION:
5265 kvm_clear_exception_queue(vcpu);
5266 break;
5267 default:
5268 break;
5269 }
60637aac 5270 }
37817f29
IE		 5271 tss_selector = exit_qualification;
5272
64a7ec06
GN		 5273 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5274 type != INTR_TYPE_EXT_INTR &&
5275 type != INTR_TYPE_NMI_INTR))
5276 skip_emulated_instruction(vcpu);
5277
7f3d35fd
KW		 5278 if (kvm_task_switch(vcpu, tss_selector,
5279 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5280 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5281 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5282 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5283 vcpu->run->internal.ndata = 0;
42dbaa5a 5284 return 0;
acb54517 5285 }
42dbaa5a
JK		 5286
5287 /* clear all local breakpoint enable flags */
5288 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5289
5290 /*
5291 * TODO: What about debug traps on tss switch?
5292 * Are we supposed to inject them and update dr6?
5293 */
5294
5295 return 1;
37817f29
IE		 5296}
5297
851ba692 5298static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5299{
f9c617f6 5300 unsigned long exit_qualification;
1439442c 5301 gpa_t gpa;
4f5982a5 5302 u32 error_code;
1439442c 5303 int gla_validity;
1439442c 5304
f9c617f6 5305 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5306
1439442c
SY		 5307 gla_validity = (exit_qualification >> 7) & 0x3;
5308 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5309 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5310 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5311 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5312 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5313 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5314 (long unsigned int)exit_qualification);
851ba692
AK		 5315 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5316 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5317 return 0;
1439442c
SY		 5318 }
5319
5320 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5321 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5322
5323 /* It is a write fault? */
5324 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5325 /* It is a fetch fault? */
5326 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5327 /* ept page table is present? */
5328 error_code |= (exit_qualification >> 3) & 0x1;
5329
25d92081
YZ		 5330 vcpu->arch.exit_qualification = exit_qualification;
5331
4f5982a5 5332 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5333}
5334
68f89400
MT		 5335static u64 ept_rsvd_mask(u64 spte, int level)
5336{
5337 int i;
5338 u64 mask = 0;
5339
5340 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5341 mask |= (1ULL << i);
5342
5343 if (level > 2)
5344 /* bits 7:3 reserved */
5345 mask |= 0xf8;
5346 else if (level == 2) {
5347 if (spte & (1ULL << 7))
5348 /* 2MB ref, bits 20:12 reserved */
5349 mask |= 0x1ff000;
5350 else
5351 /* bits 6:3 reserved */
5352 mask |= 0x78;
5353 }
5354
5355 return mask;
5356}
5357
5358static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5359 int level)
5360{
5361 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5362
5363 /* 010b (write-only) */
5364 WARN_ON((spte & 0x7) == 0x2);
5365
5366 /* 110b (write/execute) */
5367 WARN_ON((spte & 0x7) == 0x6);
5368
5369 /* 100b (execute-only) and value not supported by logical processor */
5370 if (!cpu_has_vmx_ept_execute_only())
5371 WARN_ON((spte & 0x7) == 0x4);
5372
5373 /* not 000b */
5374 if ((spte & 0x7)) {
5375 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5376
5377 if (rsvd_bits != 0) {
5378 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5379 __func__, rsvd_bits);
5380 WARN_ON(1);
5381 }
5382
5383 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5384 u64 ept_mem_type = (spte & 0x38) >> 3;
5385
5386 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5387 ept_mem_type == 7) {
5388 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5389 __func__, ept_mem_type);
5390 WARN_ON(1);
5391 }
5392 }
5393 }
5394}
5395
851ba692 5396static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5397{
5398 u64 sptes[4];
ce88decf 5399 int nr_sptes, i, ret;
68f89400
MT		 5400 gpa_t gpa;
5401
5402 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5403
ce88decf 5404 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5405 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5406 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5407 EMULATE_DONE;
f8f55942
XG		 5408
5409 if (unlikely(ret == RET_MMIO_PF_INVALID))
5410 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5411
b37fbea6 5412 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5413 return 1;
5414
5415 /* It is the real ept misconfig */
68f89400
MT		 5416 printk(KERN_ERR "EPT: Misconfiguration.\n");
5417 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5418
5419 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5420
5421 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5422 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5423
851ba692
AK		 5424 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5425 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5426
5427 return 0;
5428}
5429
851ba692 5430static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5431{
5432 u32 cpu_based_vm_exec_control;
5433
5434 /* clear pending NMI */
5435 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5436 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5437 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5438 ++vcpu->stat.nmi_window_exits;
3842d135 5439 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5440
5441 return 1;
5442}
5443
80ced186 5444static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5445{
8b3079a5
AK		 5446 struct vcpu_vmx *vmx = to_vmx(vcpu);
5447 enum emulation_result err = EMULATE_DONE;
80ced186 5448 int ret = 1;
49e9d557
AK		 5449 u32 cpu_exec_ctrl;
5450 bool intr_window_requested;
b8405c18 5451 unsigned count = 130;
49e9d557
AK		 5452
5453 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5454 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5455
b8405c18 5456 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5457 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5458 return handle_interrupt_window(&vmx->vcpu);
5459
de87dcdd
AK		 5460 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5461 return 1;
5462
991eebf9 5463 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5464
ac0a48c3 5465 if (err == EMULATE_USER_EXIT) {
80ced186
MG		 5466 ret = 0;
5467 goto out;
5468 }
1d5a4d9b 5469
de5f70e0
AK		 5470 if (err != EMULATE_DONE) {
5471 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5472 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5473 vcpu->run->internal.ndata = 0;
6d77dbfc 5474 return 0;
de5f70e0 5475 }
ea953ef0 5476
8d76c49e
GN		 5477 if (vcpu->arch.halt_request) {
5478 vcpu->arch.halt_request = 0;
5479 ret = kvm_emulate_halt(vcpu);
5480 goto out;
5481 }
5482
ea953ef0 5483 if (signal_pending(current))
80ced186 5484 goto out;
ea953ef0
MG		 5485 if (need_resched())
5486 schedule();
5487 }
5488
14168786 5489 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5490out:
5491 return ret;
ea953ef0
MG		 5492}
5493
4b8d54f9
ZE		 5494/*
5495 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5496 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5497 */
9fb41ba8 5498static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5499{
5500 skip_emulated_instruction(vcpu);
5501 kvm_vcpu_on_spin(vcpu);
5502
5503 return 1;
5504}
5505
59708670
SY		 5506static int handle_invalid_op(struct kvm_vcpu *vcpu)
5507{
5508 kvm_queue_exception(vcpu, UD_VECTOR);
5509 return 1;
5510}
5511
ff2f6fe9
NHE		 5512/*
5513 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5514 * We could reuse a single VMCS for all the L2 guests, but we also want the
5515 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5516 * allows keeping them loaded on the processor, and in the future will allow
5517 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5518 * every entry if they never change.
5519 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5520 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5521 *
5522 * The following functions allocate and free a vmcs02 in this pool.
5523 */
5524
5525/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5526static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5527{
5528 struct vmcs02_list *item;
5529 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5530 if (item->vmptr == vmx->nested.current_vmptr) {
5531 list_move(&item->list, &vmx->nested.vmcs02_pool);
5532 return &item->vmcs02;
5533 }
5534
5535 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5536 /* Recycle the least recently used VMCS. */
5537 item = list_entry(vmx->nested.vmcs02_pool.prev,
5538 struct vmcs02_list, list);
5539 item->vmptr = vmx->nested.current_vmptr;
5540 list_move(&item->list, &vmx->nested.vmcs02_pool);
5541 return &item->vmcs02;
5542 }
5543
5544 /* Create a new VMCS */
0fa24ce3 5545 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5546 if (!item)
5547 return NULL;
5548 item->vmcs02.vmcs = alloc_vmcs();
5549 if (!item->vmcs02.vmcs) {
5550 kfree(item);
5551 return NULL;
5552 }
5553 loaded_vmcs_init(&item->vmcs02);
5554 item->vmptr = vmx->nested.current_vmptr;
5555 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5556 vmx->nested.vmcs02_num++;
5557 return &item->vmcs02;
5558}
5559
5560/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5561static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5562{
5563 struct vmcs02_list *item;
5564 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5565 if (item->vmptr == vmptr) {
5566 free_loaded_vmcs(&item->vmcs02);
5567 list_del(&item->list);
5568 kfree(item);
5569 vmx->nested.vmcs02_num--;
5570 return;
5571 }
5572}
5573
5574/*
5575 * Free all VMCSs saved for this vcpu, except the one pointed by
5576 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5577 * currently used, if running L2), and vmcs01 when running L2.
5578 */
5579static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5580{
5581 struct vmcs02_list *item, *n;
5582 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5583 if (vmx->loaded_vmcs != &item->vmcs02)
5584 free_loaded_vmcs(&item->vmcs02);
5585 list_del(&item->list);
5586 kfree(item);
5587 }
5588 vmx->nested.vmcs02_num = 0;
5589
5590 if (vmx->loaded_vmcs != &vmx->vmcs01)
5591 free_loaded_vmcs(&vmx->vmcs01);
5592}
5593
0658fbaa
ACL		 5594/*
5595 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5596 * set the success or error code of an emulated VMX instruction, as specified
5597 * by Vol 2B, VMX Instruction Reference, "Conventions".
5598 */
5599static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5600{
5601 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5602 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5603 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5604}
5605
5606static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5607{
5608 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5609 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5610 X86_EFLAGS_SF | X86_EFLAGS_OF))
5611 | X86_EFLAGS_CF);
5612}
5613
145c28dd 5614static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5615 u32 vm_instruction_error)
5616{
5617 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5618 /*
5619 * failValid writes the error number to the current VMCS, which
5620 * can't be done there isn't a current VMCS.
5621 */
5622 nested_vmx_failInvalid(vcpu);
5623 return;
5624 }
5625 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5626 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5627 X86_EFLAGS_SF | X86_EFLAGS_OF))
5628 | X86_EFLAGS_ZF);
5629 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5630 /*
5631 * We don't need to force a shadow sync because
5632 * VM_INSTRUCTION_ERROR is not shadowed
5633 */
5634}
145c28dd 5635
ec378aee
NHE		 5636/*
5637 * Emulate the VMXON instruction.
5638 * Currently, we just remember that VMX is active, and do not save or even
5639 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5640 * do not currently need to store anything in that guest-allocated memory
5641 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5642 * argument is different from the VMXON pointer (which the spec says they do).
5643 */
5644static int handle_vmon(struct kvm_vcpu *vcpu)
5645{
5646 struct kvm_segment cs;
5647 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5648 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5649 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5650 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5651
5652 /* The Intel VMX Instruction Reference lists a bunch of bits that
5653 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5654 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5655 * Otherwise, we should fail with #UD. We test these now:
5656 */
5657 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5658 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5659 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5660 kvm_queue_exception(vcpu, UD_VECTOR);
5661 return 1;
5662 }
5663
5664 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5665 if (is_long_mode(vcpu) && !cs.l) {
5666 kvm_queue_exception(vcpu, UD_VECTOR);
5667 return 1;
5668 }
5669
5670 if (vmx_get_cpl(vcpu)) {
5671 kvm_inject_gp(vcpu, 0);
5672 return 1;
5673 }
145c28dd
AG		 5674 if (vmx->nested.vmxon) {
5675 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5676 skip_emulated_instruction(vcpu);
5677 return 1;
5678 }
b3897a49
NHE		 5679
5680 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5681 != VMXON_NEEDED_FEATURES) {
5682 kvm_inject_gp(vcpu, 0);
5683 return 1;
5684 }
5685
8de48833
AG		 5686 if (enable_shadow_vmcs) {
5687 shadow_vmcs = alloc_vmcs();
5688 if (!shadow_vmcs)
5689 return -ENOMEM;
5690 /* mark vmcs as shadow */
5691 shadow_vmcs->revision_id |= (1u << 31);
5692 /* init shadow vmcs */
5693 vmcs_clear(shadow_vmcs);
5694 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5695 }
ec378aee 5696
ff2f6fe9
NHE		 5697 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5698 vmx->nested.vmcs02_num = 0;
5699
ec378aee
NHE		 5700 vmx->nested.vmxon = true;
5701
5702 skip_emulated_instruction(vcpu);
a25eb114 5703 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5704 return 1;
5705}
5706
5707/*
5708 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5709 * for running VMX instructions (except VMXON, whose prerequisites are
5710 * slightly different). It also specifies what exception to inject otherwise.
5711 */
5712static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5713{
5714 struct kvm_segment cs;
5715 struct vcpu_vmx *vmx = to_vmx(vcpu);
5716
5717 if (!vmx->nested.vmxon) {
5718 kvm_queue_exception(vcpu, UD_VECTOR);
5719 return 0;
5720 }
5721
5722 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5723 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5724 (is_long_mode(vcpu) && !cs.l)) {
5725 kvm_queue_exception(vcpu, UD_VECTOR);
5726 return 0;
5727 }
5728
5729 if (vmx_get_cpl(vcpu)) {
5730 kvm_inject_gp(vcpu, 0);
5731 return 0;
5732 }
5733
5734 return 1;
5735}
5736
e7953d7f
AG		 5737static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5738{
8a1b9dd0 5739 u32 exec_control;
012f83cb
AG		 5740 if (enable_shadow_vmcs) {
5741 if (vmx->nested.current_vmcs12 != NULL) {
5742 /* copy to memory all shadowed fields in case
5743 they were modified */
5744 copy_shadow_to_vmcs12(vmx);
5745 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5746 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5747 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5748 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5749 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5750 }
5751 }
e7953d7f
AG		 5752 kunmap(vmx->nested.current_vmcs12_page);
5753 nested_release_page(vmx->nested.current_vmcs12_page);
5754}
5755
ec378aee
NHE		 5756/*
5757 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5758 * just stops using VMX.
5759 */
5760static void free_nested(struct vcpu_vmx *vmx)
5761{
5762 if (!vmx->nested.vmxon)
5763 return;
5764 vmx->nested.vmxon = false;
a9d30f33 5765 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5766 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5767 vmx->nested.current_vmptr = -1ull;
5768 vmx->nested.current_vmcs12 = NULL;
5769 }
e7953d7f
AG		 5770 if (enable_shadow_vmcs)
5771 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5772 /* Unpin physical memory we referred to in current vmcs02 */
5773 if (vmx->nested.apic_access_page) {
5774 nested_release_page(vmx->nested.apic_access_page);
5775 vmx->nested.apic_access_page = 0;
5776 }
ff2f6fe9
NHE		 5777
5778 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5779}
5780
5781/* Emulate the VMXOFF instruction */
5782static int handle_vmoff(struct kvm_vcpu *vcpu)
5783{
5784 if (!nested_vmx_check_permission(vcpu))
5785 return 1;
5786 free_nested(to_vmx(vcpu));
5787 skip_emulated_instruction(vcpu);
a25eb114 5788 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5789 return 1;
5790}
5791
064aea77
NHE		 5792/*
5793 * Decode the memory-address operand of a vmx instruction, as recorded on an
5794 * exit caused by such an instruction (run by a guest hypervisor).
5795 * On success, returns 0. When the operand is invalid, returns 1 and throws
5796 * #UD or #GP.
5797 */
5798static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5799 unsigned long exit_qualification,
5800 u32 vmx_instruction_info, gva_t *ret)
5801{
5802 /*
5803 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5804 * Execution", on an exit, vmx_instruction_info holds most of the
5805 * addressing components of the operand. Only the displacement part
5806 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5807 * For how an actual address is calculated from all these components,
5808 * refer to Vol. 1, "Operand Addressing".
5809 */
5810 int scaling = vmx_instruction_info & 3;
5811 int addr_size = (vmx_instruction_info >> 7) & 7;
5812 bool is_reg = vmx_instruction_info & (1u << 10);
5813 int seg_reg = (vmx_instruction_info >> 15) & 7;
5814 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5815 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5816 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5817 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5818
5819 if (is_reg) {
5820 kvm_queue_exception(vcpu, UD_VECTOR);
5821 return 1;
5822 }
5823
5824 /* Addr = segment_base + offset */
5825 /* offset = base + [index * scale] + displacement */
5826 *ret = vmx_get_segment_base(vcpu, seg_reg);
5827 if (base_is_valid)
5828 *ret += kvm_register_read(vcpu, base_reg);
5829 if (index_is_valid)
5830 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5831 *ret += exit_qualification; /* holds the displacement */
5832
5833 if (addr_size == 1) /* 32 bit */
5834 *ret &= 0xffffffff;
5835
5836 /*
5837 * TODO: throw #GP (and return 1) in various cases that the VM*
5838 * instructions require it - e.g., offset beyond segment limit,
5839 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5840 * address, and so on. Currently these are not checked.
5841 */
5842 return 0;
5843}
5844
27d6c865
NHE		 5845/* Emulate the VMCLEAR instruction */
5846static int handle_vmclear(struct kvm_vcpu *vcpu)
5847{
5848 struct vcpu_vmx *vmx = to_vmx(vcpu);
5849 gva_t gva;
5850 gpa_t vmptr;
5851 struct vmcs12 *vmcs12;
5852 struct page *page;
5853 struct x86_exception e;
5854
5855 if (!nested_vmx_check_permission(vcpu))
5856 return 1;
5857
5858 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5859 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5860 return 1;
5861
5862 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5863 sizeof(vmptr), &e)) {
5864 kvm_inject_page_fault(vcpu, &e);
5865 return 1;
5866 }
5867
5868 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5869 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5870 skip_emulated_instruction(vcpu);
5871 return 1;
5872 }
5873
5874 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5875 nested_release_vmcs12(vmx);
27d6c865
NHE		 5876 vmx->nested.current_vmptr = -1ull;
5877 vmx->nested.current_vmcs12 = NULL;
5878 }
5879
5880 page = nested_get_page(vcpu, vmptr);
5881 if (page == NULL) {
5882 /*
5883 * For accurate processor emulation, VMCLEAR beyond available
5884 * physical memory should do nothing at all. However, it is
5885 * possible that a nested vmx bug, not a guest hypervisor bug,
5886 * resulted in this case, so let's shut down before doing any
5887 * more damage:
5888 */
5889 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5890 return 1;
5891 }
5892 vmcs12 = kmap(page);
5893 vmcs12->launch_state = 0;
5894 kunmap(page);
5895 nested_release_page(page);
5896
5897 nested_free_vmcs02(vmx, vmptr);
5898
5899 skip_emulated_instruction(vcpu);
5900 nested_vmx_succeed(vcpu);
5901 return 1;
5902}
5903
cd232ad0
NHE		 5904static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5905
5906/* Emulate the VMLAUNCH instruction */
5907static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5908{
5909 return nested_vmx_run(vcpu, true);
5910}
5911
5912/* Emulate the VMRESUME instruction */
5913static int handle_vmresume(struct kvm_vcpu *vcpu)
5914{
5915
5916 return nested_vmx_run(vcpu, false);
5917}
5918
49f705c5
NHE		 5919enum vmcs_field_type {
5920 VMCS_FIELD_TYPE_U16 = 0,
5921 VMCS_FIELD_TYPE_U64 = 1,
5922 VMCS_FIELD_TYPE_U32 = 2,
5923 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5924};
5925
5926static inline int vmcs_field_type(unsigned long field)
5927{
5928 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5929 return VMCS_FIELD_TYPE_U32;
5930 return (field >> 13) & 0x3 ;
5931}
5932
5933static inline int vmcs_field_readonly(unsigned long field)
5934{
5935 return (((field >> 10) & 0x3) == 1);
5936}
5937
5938/*
5939 * Read a vmcs12 field. Since these can have varying lengths and we return
5940 * one type, we chose the biggest type (u64) and zero-extend the return value
5941 * to that size. Note that the caller, handle_vmread, might need to use only
5942 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5943 * 64-bit fields are to be returned).
5944 */
5945static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5946 unsigned long field, u64 *ret)
5947{
5948 short offset = vmcs_field_to_offset(field);
5949 char *p;
5950
5951 if (offset < 0)
5952 return 0;
5953
5954 p = ((char *)(get_vmcs12(vcpu))) + offset;
5955
5956 switch (vmcs_field_type(field)) {
5957 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5958 *ret = *((natural_width *)p);
5959 return 1;
5960 case VMCS_FIELD_TYPE_U16:
5961 *ret = *((u16 *)p);
5962 return 1;
5963 case VMCS_FIELD_TYPE_U32:
5964 *ret = *((u32 *)p);
5965 return 1;
5966 case VMCS_FIELD_TYPE_U64:
5967 *ret = *((u64 *)p);
5968 return 1;
5969 default:
5970 return 0; /* can never happen. */
5971 }
5972}
5973
20b97fea
AG		 5974
5975static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5976 unsigned long field, u64 field_value){
5977 short offset = vmcs_field_to_offset(field);
5978 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5979 if (offset < 0)
5980 return false;
5981
5982 switch (vmcs_field_type(field)) {
5983 case VMCS_FIELD_TYPE_U16:
5984 *(u16 *)p = field_value;
5985 return true;
5986 case VMCS_FIELD_TYPE_U32:
5987 *(u32 *)p = field_value;
5988 return true;
5989 case VMCS_FIELD_TYPE_U64:
5990 *(u64 *)p = field_value;
5991 return true;
5992 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5993 *(natural_width *)p = field_value;
5994 return true;
5995 default:
5996 return false; /* can never happen. */
5997 }
5998
5999}
6000
16f5b903
AG		 6001static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6002{
6003 int i;
6004 unsigned long field;
6005 u64 field_value;
6006 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6007 const unsigned long *fields = shadow_read_write_fields;
6008 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6009
6010 vmcs_load(shadow_vmcs);
6011
6012 for (i = 0; i < num_fields; i++) {
6013 field = fields[i];
6014 switch (vmcs_field_type(field)) {
6015 case VMCS_FIELD_TYPE_U16:
6016 field_value = vmcs_read16(field);
6017 break;
6018 case VMCS_FIELD_TYPE_U32:
6019 field_value = vmcs_read32(field);
6020 break;
6021 case VMCS_FIELD_TYPE_U64:
6022 field_value = vmcs_read64(field);
6023 break;
6024 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6025 field_value = vmcs_readl(field);
6026 break;
6027 }
6028 vmcs12_write_any(&vmx->vcpu, field, field_value);
6029 }
6030
6031 vmcs_clear(shadow_vmcs);
6032 vmcs_load(vmx->loaded_vmcs->vmcs);
6033}
6034
c3114420
AG		 6035static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6036{
c2bae893
MK		 6037 const unsigned long *fields[] = {
6038 shadow_read_write_fields,
6039 shadow_read_only_fields
c3114420 6040 };
c2bae893 6041 const int max_fields[] = {
c3114420
AG		 6042 max_shadow_read_write_fields,
6043 max_shadow_read_only_fields
6044 };
6045 int i, q;
6046 unsigned long field;
6047 u64 field_value = 0;
6048 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6049
6050 vmcs_load(shadow_vmcs);
6051
c2bae893 6052 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6053 for (i = 0; i < max_fields[q]; i++) {
6054 field = fields[q][i];
6055 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6056
6057 switch (vmcs_field_type(field)) {
6058 case VMCS_FIELD_TYPE_U16:
6059 vmcs_write16(field, (u16)field_value);
6060 break;
6061 case VMCS_FIELD_TYPE_U32:
6062 vmcs_write32(field, (u32)field_value);
6063 break;
6064 case VMCS_FIELD_TYPE_U64:
6065 vmcs_write64(field, (u64)field_value);
6066 break;
6067 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6068 vmcs_writel(field, (long)field_value);
6069 break;
6070 }
6071 }
6072 }
6073
6074 vmcs_clear(shadow_vmcs);
6075 vmcs_load(vmx->loaded_vmcs->vmcs);
6076}
6077
49f705c5
NHE		 6078/*
6079 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6080 * used before) all generate the same failure when it is missing.
6081 */
6082static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6083{
6084 struct vcpu_vmx *vmx = to_vmx(vcpu);
6085 if (vmx->nested.current_vmptr == -1ull) {
6086 nested_vmx_failInvalid(vcpu);
6087 skip_emulated_instruction(vcpu);
6088 return 0;
6089 }
6090 return 1;
6091}
6092
6093static int handle_vmread(struct kvm_vcpu *vcpu)
6094{
6095 unsigned long field;
6096 u64 field_value;
6097 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6098 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6099 gva_t gva = 0;
6100
6101 if (!nested_vmx_check_permission(vcpu) ||
6102 !nested_vmx_check_vmcs12(vcpu))
6103 return 1;
6104
6105 /* Decode instruction info and find the field to read */
6106 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6107 /* Read the field, zero-extended to a u64 field_value */
6108 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6109 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6110 skip_emulated_instruction(vcpu);
6111 return 1;
6112 }
6113 /*
6114 * Now copy part of this value to register or memory, as requested.
6115 * Note that the number of bits actually copied is 32 or 64 depending
6116 * on the guest's mode (32 or 64 bit), not on the given field's length.
6117 */
6118 if (vmx_instruction_info & (1u << 10)) {
6119 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6120 field_value);
6121 } else {
6122 if (get_vmx_mem_address(vcpu, exit_qualification,
6123 vmx_instruction_info, &gva))
6124 return 1;
6125 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6126 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6127 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6128 }
6129
6130 nested_vmx_succeed(vcpu);
6131 skip_emulated_instruction(vcpu);
6132 return 1;
6133}
6134
6135
6136static int handle_vmwrite(struct kvm_vcpu *vcpu)
6137{
6138 unsigned long field;
6139 gva_t gva;
6140 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6141 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6142 /* The value to write might be 32 or 64 bits, depending on L1's long
6143 * mode, and eventually we need to write that into a field of several
6144 * possible lengths. The code below first zero-extends the value to 64
6145 * bit (field_value), and then copies only the approriate number of
6146 * bits into the vmcs12 field.
6147 */
6148 u64 field_value = 0;
6149 struct x86_exception e;
6150
6151 if (!nested_vmx_check_permission(vcpu) ||
6152 !nested_vmx_check_vmcs12(vcpu))
6153 return 1;
6154
6155 if (vmx_instruction_info & (1u << 10))
6156 field_value = kvm_register_read(vcpu,
6157 (((vmx_instruction_info) >> 3) & 0xf));
6158 else {
6159 if (get_vmx_mem_address(vcpu, exit_qualification,
6160 vmx_instruction_info, &gva))
6161 return 1;
6162 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6163 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6164 kvm_inject_page_fault(vcpu, &e);
6165 return 1;
6166 }
6167 }
6168
6169
6170 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6171 if (vmcs_field_readonly(field)) {
6172 nested_vmx_failValid(vcpu,
6173 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6174 skip_emulated_instruction(vcpu);
6175 return 1;
6176 }
6177
20b97fea 6178 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6179 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6180 skip_emulated_instruction(vcpu);
6181 return 1;
6182 }
6183
6184 nested_vmx_succeed(vcpu);
6185 skip_emulated_instruction(vcpu);
6186 return 1;
6187}
6188
63846663
NHE		 6189/* Emulate the VMPTRLD instruction */
6190static int handle_vmptrld(struct kvm_vcpu *vcpu)
6191{
6192 struct vcpu_vmx *vmx = to_vmx(vcpu);
6193 gva_t gva;
6194 gpa_t vmptr;
6195 struct x86_exception e;
8a1b9dd0 6196 u32 exec_control;
63846663
NHE		 6197
6198 if (!nested_vmx_check_permission(vcpu))
6199 return 1;
6200
6201 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6202 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6203 return 1;
6204
6205 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6206 sizeof(vmptr), &e)) {
6207 kvm_inject_page_fault(vcpu, &e);
6208 return 1;
6209 }
6210
6211 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6212 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6213 skip_emulated_instruction(vcpu);
6214 return 1;
6215 }
6216
6217 if (vmx->nested.current_vmptr != vmptr) {
6218 struct vmcs12 *new_vmcs12;
6219 struct page *page;
6220 page = nested_get_page(vcpu, vmptr);
6221 if (page == NULL) {
6222 nested_vmx_failInvalid(vcpu);
6223 skip_emulated_instruction(vcpu);
6224 return 1;
6225 }
6226 new_vmcs12 = kmap(page);
6227 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6228 kunmap(page);
6229 nested_release_page_clean(page);
6230 nested_vmx_failValid(vcpu,
6231 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6232 skip_emulated_instruction(vcpu);
6233 return 1;
6234 }
e7953d7f
AG		 6235 if (vmx->nested.current_vmptr != -1ull)
6236 nested_release_vmcs12(vmx);
63846663
NHE		 6237
6238 vmx->nested.current_vmptr = vmptr;
6239 vmx->nested.current_vmcs12 = new_vmcs12;
6240 vmx->nested.current_vmcs12_page = page;
012f83cb 6241 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6242 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6243 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6244 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6245 vmcs_write64(VMCS_LINK_POINTER,
6246 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6247 vmx->nested.sync_shadow_vmcs = true;
6248 }
63846663
NHE		 6249 }
6250
6251 nested_vmx_succeed(vcpu);
6252 skip_emulated_instruction(vcpu);
6253 return 1;
6254}
6255
6a4d7550
NHE		 6256/* Emulate the VMPTRST instruction */
6257static int handle_vmptrst(struct kvm_vcpu *vcpu)
6258{
6259 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6260 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6261 gva_t vmcs_gva;
6262 struct x86_exception e;
6263
6264 if (!nested_vmx_check_permission(vcpu))
6265 return 1;
6266
6267 if (get_vmx_mem_address(vcpu, exit_qualification,
6268 vmx_instruction_info, &vmcs_gva))
6269 return 1;
6270 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6271 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6272 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6273 sizeof(u64), &e)) {
6274 kvm_inject_page_fault(vcpu, &e);
6275 return 1;
6276 }
6277 nested_vmx_succeed(vcpu);
6278 skip_emulated_instruction(vcpu);
6279 return 1;
6280}
6281
6aa8b732
AK		 6282/*
6283 * The exit handlers return 1 if the exit was handled fully and guest execution
6284 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6285 * to be done to userspace and return 0.
6286 */
772e0318 6287static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6288 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6289 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6290 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6291 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6292 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6293 [EXIT_REASON_CR_ACCESS] = handle_cr,
6294 [EXIT_REASON_DR_ACCESS] = handle_dr,
6295 [EXIT_REASON_CPUID] = handle_cpuid,
6296 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6297 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6298 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6299 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6300 [EXIT_REASON_INVD] = handle_invd,
a7052897 6301 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6302 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6303 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6304 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6305 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6306 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6307 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6308 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6309 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6310 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6311 [EXIT_REASON_VMOFF] = handle_vmoff,
6312 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6313 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6314 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6315 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6316 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6317 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6318 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6319 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6320 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6321 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6322 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6323 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6324 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6325 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 6326};
6327
6328static const int kvm_vmx_max_exit_handlers =
50a3485c 6329 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6330
908a7bdd
JK		 6331static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6332 struct vmcs12 *vmcs12)
6333{
6334 unsigned long exit_qualification;
6335 gpa_t bitmap, last_bitmap;
6336 unsigned int port;
6337 int size;
6338 u8 b;
6339
6340 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6341 return 1;
6342
6343 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6344 return 0;
6345
6346 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6347
6348 port = exit_qualification >> 16;
6349 size = (exit_qualification & 7) + 1;
6350
6351 last_bitmap = (gpa_t)-1;
6352 b = -1;
6353
6354 while (size > 0) {
6355 if (port < 0x8000)
6356 bitmap = vmcs12->io_bitmap_a;
6357 else if (port < 0x10000)
6358 bitmap = vmcs12->io_bitmap_b;
6359 else
6360 return 1;
6361 bitmap += (port & 0x7fff) / 8;
6362
6363 if (last_bitmap != bitmap)
6364 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6365 return 1;
6366 if (b & (1 << (port & 7)))
6367 return 1;
6368
6369 port++;
6370 size--;
6371 last_bitmap = bitmap;
6372 }
6373
6374 return 0;
6375}
6376
644d711a
NHE		 6377/*
6378 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6379 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6380 * disinterest in the current event (read or write a specific MSR) by using an
6381 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6382 */
6383static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6384 struct vmcs12 *vmcs12, u32 exit_reason)
6385{
6386 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6387 gpa_t bitmap;
6388
cbd29cb6 6389 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6390 return 1;
6391
6392 /*
6393 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6394 * for the four combinations of read/write and low/high MSR numbers.
6395 * First we need to figure out which of the four to use:
6396 */
6397 bitmap = vmcs12->msr_bitmap;
6398 if (exit_reason == EXIT_REASON_MSR_WRITE)
6399 bitmap += 2048;
6400 if (msr_index >= 0xc0000000) {
6401 msr_index -= 0xc0000000;
6402 bitmap += 1024;
6403 }
6404
6405 /* Then read the msr_index'th bit from this bitmap: */
6406 if (msr_index < 1024*8) {
6407 unsigned char b;
bd31a7f5
JK		 6408 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6409 return 1;
644d711a
NHE		 6410 return 1 & (b >> (msr_index & 7));
6411 } else
6412 return 1; /* let L1 handle the wrong parameter */
6413}
6414
6415/*
6416 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6417 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6418 * intercept (via guest_host_mask etc.) the current event.
6419 */
6420static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6421 struct vmcs12 *vmcs12)
6422{
6423 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6424 int cr = exit_qualification & 15;
6425 int reg = (exit_qualification >> 8) & 15;
6426 unsigned long val = kvm_register_read(vcpu, reg);
6427
6428 switch ((exit_qualification >> 4) & 3) {
6429 case 0: /* mov to cr */
6430 switch (cr) {
6431 case 0:
6432 if (vmcs12->cr0_guest_host_mask &
6433 (val ^ vmcs12->cr0_read_shadow))
6434 return 1;
6435 break;
6436 case 3:
6437 if ((vmcs12->cr3_target_count >= 1 &&
6438 vmcs12->cr3_target_value0 == val) ||
6439 (vmcs12->cr3_target_count >= 2 &&
6440 vmcs12->cr3_target_value1 == val) ||
6441 (vmcs12->cr3_target_count >= 3 &&
6442 vmcs12->cr3_target_value2 == val) ||
6443 (vmcs12->cr3_target_count >= 4 &&
6444 vmcs12->cr3_target_value3 == val))
6445 return 0;
6446 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6447 return 1;
6448 break;
6449 case 4:
6450 if (vmcs12->cr4_guest_host_mask &
6451 (vmcs12->cr4_read_shadow ^ val))
6452 return 1;
6453 break;
6454 case 8:
6455 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6456 return 1;
6457 break;
6458 }
6459 break;
6460 case 2: /* clts */
6461 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6462 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6463 return 1;
6464 break;
6465 case 1: /* mov from cr */
6466 switch (cr) {
6467 case 3:
6468 if (vmcs12->cpu_based_vm_exec_control &
6469 CPU_BASED_CR3_STORE_EXITING)
6470 return 1;
6471 break;
6472 case 8:
6473 if (vmcs12->cpu_based_vm_exec_control &
6474 CPU_BASED_CR8_STORE_EXITING)
6475 return 1;
6476 break;
6477 }
6478 break;
6479 case 3: /* lmsw */
6480 /*
6481 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6482 * cr0. Other attempted changes are ignored, with no exit.
6483 */
6484 if (vmcs12->cr0_guest_host_mask & 0xe &
6485 (val ^ vmcs12->cr0_read_shadow))
6486 return 1;
6487 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6488 !(vmcs12->cr0_read_shadow & 0x1) &&
6489 (val & 0x1))
6490 return 1;
6491 break;
6492 }
6493 return 0;
6494}
6495
6496/*
6497 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6498 * should handle it ourselves in L0 (and then continue L2). Only call this
6499 * when in is_guest_mode (L2).
6500 */
6501static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6502{
644d711a
NHE		 6503 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6504 struct vcpu_vmx *vmx = to_vmx(vcpu);
6505 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6506 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6507
6508 if (vmx->nested.nested_run_pending)
6509 return 0;
6510
6511 if (unlikely(vmx->fail)) {
bd80158a
JK		 6512 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6513 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6514 return 1;
6515 }
6516
6517 switch (exit_reason) {
6518 case EXIT_REASON_EXCEPTION_NMI:
6519 if (!is_exception(intr_info))
6520 return 0;
6521 else if (is_page_fault(intr_info))
6522 return enable_ept;
6523 return vmcs12->exception_bitmap &
6524 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6525 case EXIT_REASON_EXTERNAL_INTERRUPT:
6526 return 0;
6527 case EXIT_REASON_TRIPLE_FAULT:
6528 return 1;
6529 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6530 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6531 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6532 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6533 case EXIT_REASON_TASK_SWITCH:
6534 return 1;
6535 case EXIT_REASON_CPUID:
6536 return 1;
6537 case EXIT_REASON_HLT:
6538 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6539 case EXIT_REASON_INVD:
6540 return 1;
6541 case EXIT_REASON_INVLPG:
6542 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6543 case EXIT_REASON_RDPMC:
6544 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6545 case EXIT_REASON_RDTSC:
6546 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6547 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6548 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6549 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6550 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6551 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6552 /*
6553 * VMX instructions trap unconditionally. This allows L1 to
6554 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6555 */
6556 return 1;
6557 case EXIT_REASON_CR_ACCESS:
6558 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6559 case EXIT_REASON_DR_ACCESS:
6560 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6561 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6562 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6563 case EXIT_REASON_MSR_READ:
6564 case EXIT_REASON_MSR_WRITE:
6565 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6566 case EXIT_REASON_INVALID_STATE:
6567 return 1;
6568 case EXIT_REASON_MWAIT_INSTRUCTION:
6569 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6570 case EXIT_REASON_MONITOR_INSTRUCTION:
6571 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6572 case EXIT_REASON_PAUSE_INSTRUCTION:
6573 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6574 nested_cpu_has2(vmcs12,
6575 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6576 case EXIT_REASON_MCE_DURING_VMENTRY:
6577 return 0;
6578 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6579 return 1;
6580 case EXIT_REASON_APIC_ACCESS:
6581 return nested_cpu_has2(vmcs12,
6582 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6583 case EXIT_REASON_EPT_VIOLATION:
6584 case EXIT_REASON_EPT_MISCONFIG:
6585 return 0;
0238ea91
JK		 6586 case EXIT_REASON_PREEMPTION_TIMER:
6587 return vmcs12->pin_based_vm_exec_control &
6588 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6589 case EXIT_REASON_WBINVD:
6590 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6591 case EXIT_REASON_XSETBV:
6592 return 1;
6593 default:
6594 return 1;
6595 }
6596}
6597
586f9607
AK		 6598static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6599{
6600 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6601 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6602}
6603
6aa8b732
AK		 6604/*
6605 * The guest has exited. See if we can fix it or if we need userspace
6606 * assistance.
6607 */
851ba692 6608static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6609{
29bd8a78 6610 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6611 u32 exit_reason = vmx->exit_reason;
1155f76a 6612 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6613
80ced186 6614 /* If guest state is invalid, start emulating */
14168786 6615 if (vmx->emulation_required)
80ced186 6616 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6617
b6f1250e
NHE		 6618 /*
6619 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6620 * we did not inject a still-pending event to L1 now because of
6621 * nested_run_pending, we need to re-enable this bit.
6622 */
6623 if (vmx->nested.nested_run_pending)
6624 kvm_make_request(KVM_REQ_EVENT, vcpu);
6625
509c75ea
NHE		 6626 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6627 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6628 vmx->nested.nested_run_pending = 1;
6629 else
6630 vmx->nested.nested_run_pending = 0;
6631
6632 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6633 nested_vmx_vmexit(vcpu);
6634 return 1;
6635 }
6636
5120702e
MG		 6637 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6638 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6639 vcpu->run->fail_entry.hardware_entry_failure_reason
6640 = exit_reason;
6641 return 0;
6642 }
6643
29bd8a78 6644 if (unlikely(vmx->fail)) {
851ba692
AK		 6645 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6646 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6647 = vmcs_read32(VM_INSTRUCTION_ERROR);
6648 return 0;
6649 }
6aa8b732 6650
b9bf6882
XG		 6651 /*
6652 * Note:
6653 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6654 * delivery event since it indicates guest is accessing MMIO.
6655 * The vm-exit can be triggered again after return to guest that
6656 * will cause infinite loop.
6657 */
d77c26fc 6658 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6659 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6660 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6661 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6662 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6663 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6664 vcpu->run->internal.ndata = 2;
6665 vcpu->run->internal.data[0] = vectoring_info;
6666 vcpu->run->internal.data[1] = exit_reason;
6667 return 0;
6668 }
3b86cd99 6669
644d711a
NHE		 6670 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6671 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6672 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6673 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6674 vmx->soft_vnmi_blocked = 0;
3b86cd99 6675 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6676 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6677 /*
6678 * This CPU don't support us in finding the end of an
6679 * NMI-blocked window if the guest runs with IRQs
6680 * disabled. So we pull the trigger after 1 s of
6681 * futile waiting, but inform the user about this.
6682 */
6683 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6684 "state on VCPU %d after 1 s timeout\n",
6685 __func__, vcpu->vcpu_id);
6686 vmx->soft_vnmi_blocked = 0;
3b86cd99 6687 }
3b86cd99
JK		 6688 }
6689
6aa8b732
AK		 6690 if (exit_reason < kvm_vmx_max_exit_handlers
6691 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6692 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6693 else {
851ba692
AK		 6694 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6695 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6696 }
6697 return 0;
6698}
6699
95ba8273 6700static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6701{
95ba8273 6702 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6703 vmcs_write32(TPR_THRESHOLD, 0);
6704 return;
6705 }
6706
95ba8273 6707 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6708}
6709
8d14695f
YZ		 6710static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6711{
6712 u32 sec_exec_control;
6713
6714 /*
6715 * There is not point to enable virtualize x2apic without enable
6716 * apicv
6717 */
c7c9c56c
YZ		 6718 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6719 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6720 return;
6721
6722 if (!vm_need_tpr_shadow(vcpu->kvm))
6723 return;
6724
6725 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6726
6727 if (set) {
6728 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6729 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6730 } else {
6731 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6732 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6733 }
6734 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6735
6736 vmx_set_msr_bitmap(vcpu);
6737}
6738
c7c9c56c
YZ		 6739static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6740{
6741 u16 status;
6742 u8 old;
6743
6744 if (!vmx_vm_has_apicv(kvm))
6745 return;
6746
6747 if (isr == -1)
6748 isr = 0;
6749
6750 status = vmcs_read16(GUEST_INTR_STATUS);
6751 old = status >> 8;
6752 if (isr != old) {
6753 status &= 0xff;
6754 status |= isr << 8;
6755 vmcs_write16(GUEST_INTR_STATUS, status);
6756 }
6757}
6758
6759static void vmx_set_rvi(int vector)
6760{
6761 u16 status;
6762 u8 old;
6763
6764 status = vmcs_read16(GUEST_INTR_STATUS);
6765 old = (u8)status & 0xff;
6766 if ((u8)vector != old) {
6767 status &= ~0xff;
6768 status |= (u8)vector;
6769 vmcs_write16(GUEST_INTR_STATUS, status);
6770 }
6771}
6772
6773static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6774{
6775 if (max_irr == -1)
6776 return;
6777
6778 vmx_set_rvi(max_irr);
6779}
6780
6781static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6782{
3d81bc7e
YZ		 6783 if (!vmx_vm_has_apicv(vcpu->kvm))
6784 return;
6785
c7c9c56c
YZ		 6786 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6787 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6788 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6789 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6790}
6791
51aa01d1 6792static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6793{
00eba012
AK		 6794 u32 exit_intr_info;
6795
6796 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6797 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6798 return;
6799
c5ca8e57 6800 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6801 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6802
6803 /* Handle machine checks before interrupts are enabled */
00eba012 6804 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6805 kvm_machine_check();
6806
20f65983 6807 /* We need to handle NMIs before interrupts are enabled */
00eba012 6808 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6809 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6810 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6811 asm("int $2");
ff9d07a0
ZY		 6812 kvm_after_handle_nmi(&vmx->vcpu);
6813 }
51aa01d1 6814}
20f65983 6815
a547c6db
YZ		 6816static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6817{
6818 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6819
6820 /*
6821 * If external interrupt exists, IF bit is set in rflags/eflags on the
6822 * interrupt stack frame, and interrupt will be enabled on a return
6823 * from interrupt handler.
6824 */
6825 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6826 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6827 unsigned int vector;
6828 unsigned long entry;
6829 gate_desc *desc;
6830 struct vcpu_vmx *vmx = to_vmx(vcpu);
6831#ifdef CONFIG_X86_64
6832 unsigned long tmp;
6833#endif
6834
6835 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6836 desc = (gate_desc *)vmx->host_idt_base + vector;
6837 entry = gate_offset(*desc);
6838 asm volatile(
6839#ifdef CONFIG_X86_64
6840 "mov %%" _ASM_SP ", %[sp]\n\t"
6841 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6842 "push $%c[ss]\n\t"
6843 "push %[sp]\n\t"
6844#endif
6845 "pushf\n\t"
6846 "orl $0x200, (%%" _ASM_SP ")\n\t"
6847 __ASM_SIZE(push) " $%c[cs]\n\t"
6848 "call *%[entry]\n\t"
6849 :
6850#ifdef CONFIG_X86_64
6851 [sp]"=&r"(tmp)
6852#endif
6853 :
6854 [entry]"r"(entry),
6855 [ss]"i"(__KERNEL_DS),
6856 [cs]"i"(__KERNEL_CS)
6857 );
6858 } else
6859 local_irq_enable();
6860}
6861
51aa01d1
AK		 6862static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6863{
c5ca8e57 6864 u32 exit_intr_info;
51aa01d1
AK		 6865 bool unblock_nmi;
6866 u8 vector;
6867 bool idtv_info_valid;
6868
6869 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6870
cf393f75 6871 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6872 if (vmx->nmi_known_unmasked)
6873 return;
c5ca8e57
AK		 6874 /*
6875 * Can't use vmx->exit_intr_info since we're not sure what
6876 * the exit reason is.
6877 */
6878 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6879 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6880 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6881 /*
7b4a25cb 6882 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6883 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6884 * a guest IRET fault.
7b4a25cb
GN		 6885 * SDM 3: 23.2.2 (September 2008)
6886 * Bit 12 is undefined in any of the following cases:
6887 * If the VM exit sets the valid bit in the IDT-vectoring
6888 * information field.
6889 * If the VM exit is due to a double fault.
cf393f75 6890 */
7b4a25cb
GN		 6891 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6892 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6893 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6894 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6895 else
6896 vmx->nmi_known_unmasked =
6897 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6898 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6899 } else if (unlikely(vmx->soft_vnmi_blocked))
6900 vmx->vnmi_blocked_time +=
6901 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6902}
6903
3ab66e8a 6904static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6905 u32 idt_vectoring_info,
6906 int instr_len_field,
6907 int error_code_field)
51aa01d1 6908{
51aa01d1
AK		 6909 u8 vector;
6910 int type;
6911 bool idtv_info_valid;
6912
6913 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6914
3ab66e8a
JK		 6915 vcpu->arch.nmi_injected = false;
6916 kvm_clear_exception_queue(vcpu);
6917 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6918
6919 if (!idtv_info_valid)
6920 return;
6921
3ab66e8a 6922 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6923
668f612f
AK		 6924 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6925 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6926
64a7ec06 6927 switch (type) {
37b96e98 6928 case INTR_TYPE_NMI_INTR:
3ab66e8a 6929 vcpu->arch.nmi_injected = true;
668f612f 6930 /*
7b4a25cb 6931 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6932 * Clear bit "block by NMI" before VM entry if a NMI
6933 * delivery faulted.
668f612f 6934 */
3ab66e8a 6935 vmx_set_nmi_mask(vcpu, false);
37b96e98 6936 break;
37b96e98 6937 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6938 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6939 /* fall through */
6940 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6941 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6942 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6943 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6944 } else
3ab66e8a 6945 kvm_queue_exception(vcpu, vector);
37b96e98 6946 break;
66fd3f7f 6947 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6948 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6949 /* fall through */
37b96e98 6950 case INTR_TYPE_EXT_INTR:
3ab66e8a 6951 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6952 break;
6953 default:
6954 break;
f7d9238f 6955 }
cf393f75
AK		 6956}
6957
83422e17
AK		 6958static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6959{
3ab66e8a 6960 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6961 VM_EXIT_INSTRUCTION_LEN,
6962 IDT_VECTORING_ERROR_CODE);
6963}
6964
b463a6f7
AK		 6965static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6966{
3ab66e8a 6967 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6968 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6969 VM_ENTRY_INSTRUCTION_LEN,
6970 VM_ENTRY_EXCEPTION_ERROR_CODE);
6971
6972 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6973}
6974
d7cd9796
GN		 6975static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6976{
6977 int i, nr_msrs;
6978 struct perf_guest_switch_msr *msrs;
6979
6980 msrs = perf_guest_get_msrs(&nr_msrs);
6981
6982 if (!msrs)
6983 return;
6984
6985 for (i = 0; i < nr_msrs; i++)
6986 if (msrs[i].host == msrs[i].guest)
6987 clear_atomic_switch_msr(vmx, msrs[i].msr);
6988 else
6989 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6990 msrs[i].host);
6991}
6992
a3b5ba49 6993static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6994{
a2fa3e9f 6995 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6996 unsigned long debugctlmsr;
104f226b
AK		 6997
6998 /* Record the guest's net vcpu time for enforced NMI injections. */
6999 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7000 vmx->entry_time = ktime_get();
7001
7002 /* Don't enter VMX if guest state is invalid, let the exit handler
7003 start emulation until we arrive back to a valid state */
14168786 7004 if (vmx->emulation_required)
104f226b
AK		 7005 return;
7006
012f83cb
AG		 7007 if (vmx->nested.sync_shadow_vmcs) {
7008 copy_vmcs12_to_shadow(vmx);
7009 vmx->nested.sync_shadow_vmcs = false;
7010 }
7011
104f226b
AK		 7012 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7013 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7014 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7015 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7016
7017 /* When single-stepping over STI and MOV SS, we must clear the
7018 * corresponding interruptibility bits in the guest state. Otherwise
7019 * vmentry fails as it then expects bit 14 (BS) in pending debug
7020 * exceptions being set, but that's not correct for the guest debugging
7021 * case. */
7022 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7023 vmx_set_interrupt_shadow(vcpu, 0);
7024
d7cd9796 7025 atomic_switch_perf_msrs(vmx);
2a7921b7 7026 debugctlmsr = get_debugctlmsr();
d7cd9796 7027
d462b819 7028 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7029 asm(
6aa8b732 7030 /* Store host registers */
b188c81f
AK		 7031 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7032 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7033 "push %%" _ASM_CX " \n\t"
7034 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7035 "je 1f \n\t"
b188c81f 7036 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7037 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7038 "1: \n\t"
d3edefc0 7039 /* Reload cr2 if changed */
b188c81f
AK		 7040 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7041 "mov %%cr2, %%" _ASM_DX " \n\t"
7042 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7043 "je 2f \n\t"
b188c81f 7044 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7045 "2: \n\t"
6aa8b732 7046 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7047 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7048 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7049 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7050 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7051 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7052 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7053 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7054 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7055#ifdef CONFIG_X86_64
e08aa78a
AK		 7056 "mov %c[r8](%0), %%r8 \n\t"
7057 "mov %c[r9](%0), %%r9 \n\t"
7058 "mov %c[r10](%0), %%r10 \n\t"
7059 "mov %c[r11](%0), %%r11 \n\t"
7060 "mov %c[r12](%0), %%r12 \n\t"
7061 "mov %c[r13](%0), %%r13 \n\t"
7062 "mov %c[r14](%0), %%r14 \n\t"
7063 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7064#endif
b188c81f 7065 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7066
6aa8b732 7067 /* Enter guest mode */
83287ea4 7068 "jne 1f \n\t"
4ecac3fd 7069 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7070 "jmp 2f \n\t"
7071 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7072 "2: "
6aa8b732 7073 /* Save guest registers, load host registers, keep flags */
b188c81f 7074 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7075 "pop %0 \n\t"
b188c81f
AK		 7076 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7077 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7078 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7079 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7080 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7081 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7082 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7083#ifdef CONFIG_X86_64
e08aa78a
AK		 7084 "mov %%r8, %c[r8](%0) \n\t"
7085 "mov %%r9, %c[r9](%0) \n\t"
7086 "mov %%r10, %c[r10](%0) \n\t"
7087 "mov %%r11, %c[r11](%0) \n\t"
7088 "mov %%r12, %c[r12](%0) \n\t"
7089 "mov %%r13, %c[r13](%0) \n\t"
7090 "mov %%r14, %c[r14](%0) \n\t"
7091 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7092#endif
b188c81f
AK		 7093 "mov %%cr2, %%" _ASM_AX " \n\t"
7094 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7095
b188c81f 7096 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7097 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7098 ".pushsection .rodata \n\t"
7099 ".global vmx_return \n\t"
7100 "vmx_return: " _ASM_PTR " 2b \n\t"
7101 ".popsection"
e08aa78a 7102 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7103 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7104 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7105 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7106 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7107 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7108 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7109 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7110 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7111 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7112 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7113#ifdef CONFIG_X86_64
ad312c7c
ZX		 7114 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7115 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7116 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7117 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7118 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7119 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7120 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7121 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7122#endif
40712fae
AK		 7123 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7124 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7125 : "cc", "memory"
7126#ifdef CONFIG_X86_64
b188c81f 7127 , "rax", "rbx", "rdi", "rsi"
c2036300 7128 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7129#else
7130 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7131#endif
7132 );
6aa8b732 7133
2a7921b7
GN		 7134 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7135 if (debugctlmsr)
7136 update_debugctlmsr(debugctlmsr);
7137
aa67f609
AK		 7138#ifndef CONFIG_X86_64
7139 /*
7140 * The sysexit path does not restore ds/es, so we must set them to
7141 * a reasonable value ourselves.
7142 *
7143 * We can't defer this to vmx_load_host_state() since that function
7144 * may be executed in interrupt context, which saves and restore segments
7145 * around it, nullifying its effect.
7146 */
7147 loadsegment(ds, __USER_DS);
7148 loadsegment(es, __USER_DS);
7149#endif
7150
6de4f3ad 7151 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7152 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7153 | (1 << VCPU_EXREG_CPL)
aff48baa 7154 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7155 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7156 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7157 vcpu->arch.regs_dirty = 0;
7158
1155f76a
AK		 7159 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7160
d462b819 7161 vmx->loaded_vmcs->launched = 1;
1b6269db 7162
51aa01d1 7163 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7164 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7165
7166 vmx_complete_atomic_exit(vmx);
7167 vmx_recover_nmi_blocking(vmx);
cf393f75 7168 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7169}
7170
6aa8b732
AK		 7171static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7172{
fb3f0f51
RR		 7173 struct vcpu_vmx *vmx = to_vmx(vcpu);
7174
cdbecfc3 7175 free_vpid(vmx);
ec378aee 7176 free_nested(vmx);
d462b819 7177 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7178 kfree(vmx->guest_msrs);
7179 kvm_vcpu_uninit(vcpu);
a4770347 7180 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7181}
7182
fb3f0f51 7183static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7184{
fb3f0f51 7185 int err;
c16f862d 7186 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7187 int cpu;
6aa8b732 7188
a2fa3e9f 7189 if (!vmx)
fb3f0f51
RR		 7190 return ERR_PTR(-ENOMEM);
7191
2384d2b3
SY		 7192 allocate_vpid(vmx);
7193
fb3f0f51
RR		 7194 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7195 if (err)
7196 goto free_vcpu;
965b58a5 7197
a2fa3e9f 7198 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7199 err = -ENOMEM;
fb3f0f51 7200 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7201 goto uninit_vcpu;
7202 }
965b58a5 7203
d462b819
NHE		 7204 vmx->loaded_vmcs = &vmx->vmcs01;
7205 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7206 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7207 goto free_msrs;
d462b819
NHE		 7208 if (!vmm_exclusive)
7209 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7210 loaded_vmcs_init(vmx->loaded_vmcs);
7211 if (!vmm_exclusive)
7212 kvm_cpu_vmxoff();
a2fa3e9f 7213
15ad7146
AK		 7214 cpu = get_cpu();
7215 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7216 vmx->vcpu.cpu = cpu;
8b9cf98c 7217 err = vmx_vcpu_setup(vmx);
fb3f0f51 7218 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7219 put_cpu();
fb3f0f51
RR		 7220 if (err)
7221 goto free_vmcs;
a63cb560 7222 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7223 err = alloc_apic_access_page(kvm);
7224 if (err)
5e4a0b3c 7225 goto free_vmcs;
a63cb560 7226 }
fb3f0f51 7227
b927a3ce
SY		 7228 if (enable_ept) {
7229 if (!kvm->arch.ept_identity_map_addr)
7230 kvm->arch.ept_identity_map_addr =
7231 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7232 err = -ENOMEM;
b7ebfb05
SY		 7233 if (alloc_identity_pagetable(kvm) != 0)
7234 goto free_vmcs;
93ea5388
GN		 7235 if (!init_rmode_identity_map(kvm))
7236 goto free_vmcs;
b927a3ce 7237 }
b7ebfb05 7238
a9d30f33
NHE		 7239 vmx->nested.current_vmptr = -1ull;
7240 vmx->nested.current_vmcs12 = NULL;
7241
fb3f0f51
RR		 7242 return &vmx->vcpu;
7243
7244free_vmcs:
5f3fbc34 7245 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7246free_msrs:
fb3f0f51
RR		 7247 kfree(vmx->guest_msrs);
7248uninit_vcpu:
7249 kvm_vcpu_uninit(&vmx->vcpu);
7250free_vcpu:
cdbecfc3 7251 free_vpid(vmx);
a4770347 7252 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7253 return ERR_PTR(err);
6aa8b732
AK		 7254}
7255
002c7f7c
YS		 7256static void __init vmx_check_processor_compat(void *rtn)
7257{
7258 struct vmcs_config vmcs_conf;
7259
7260 *(int *)rtn = 0;
7261 if (setup_vmcs_config(&vmcs_conf) < 0)
7262 *(int *)rtn = -EIO;
7263 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7264 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7265 smp_processor_id());
7266 *(int *)rtn = -EIO;
7267 }
7268}
7269
67253af5
SY		 7270static int get_ept_level(void)
7271{
7272 return VMX_EPT_DEFAULT_GAW + 1;
7273}
7274
4b12f0de 7275static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7276{
4b12f0de
SY		 7277 u64 ret;
7278
522c68c4
SY		 7279 /* For VT-d and EPT combination
7280 * 1. MMIO: always map as UC
7281 * 2. EPT with VT-d:
7282 * a. VT-d without snooping control feature: can't guarantee the
7283 * result, try to trust guest.
7284 * b. VT-d with snooping control feature: snooping control feature of
7285 * VT-d engine can guarantee the cache correctness. Just set it
7286 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7287 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7288 * consistent with host MTRR
7289 */
4b12f0de
SY		 7290 if (is_mmio)
7291 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7292 else if (vcpu->kvm->arch.iommu_domain &&
7293 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7294 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7295 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7296 else
522c68c4 7297 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7298 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7299
7300 return ret;
64d4d521
SY		 7301}
7302
17cc3935 7303static int vmx_get_lpage_level(void)
344f414f 7304{
878403b7
SY		 7305 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7306 return PT_DIRECTORY_LEVEL;
7307 else
7308 /* For shadow and EPT supported 1GB page */
7309 return PT_PDPE_LEVEL;
344f414f
JR		 7310}
7311
0e851880
SY		 7312static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7313{
4e47c7a6
SY		 7314 struct kvm_cpuid_entry2 *best;
7315 struct vcpu_vmx *vmx = to_vmx(vcpu);
7316 u32 exec_control;
7317
7318 vmx->rdtscp_enabled = false;
7319 if (vmx_rdtscp_supported()) {
7320 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7321 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7322 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7323 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7324 vmx->rdtscp_enabled = true;
7325 else {
7326 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7327 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7328 exec_control);
7329 }
7330 }
7331 }
ad756a16 7332
ad756a16
MJ		 7333 /* Exposing INVPCID only when PCID is exposed */
7334 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7335 if (vmx_invpcid_supported() &&
4f977045 7336 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7337 guest_cpuid_has_pcid(vcpu)) {
29282fde 7338 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7339 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7340 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7341 exec_control);
7342 } else {
29282fde
TI		 7343 if (cpu_has_secondary_exec_ctrls()) {
7344 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7345 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7346 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7347 exec_control);
7348 }
ad756a16 7349 if (best)
4f977045 7350 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7351 }
0e851880
SY		 7352}
7353
d4330ef2
JR		 7354static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7355{
7b8050f5
NHE		 7356 if (func == 1 && nested)
7357 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7358}
7359
25d92081
YZ		 7360static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7361 struct x86_exception *fault)
7362{
7363 struct vmcs12 *vmcs12;
7364 nested_vmx_vmexit(vcpu);
7365 vmcs12 = get_vmcs12(vcpu);
7366
7367 if (fault->error_code & PFERR_RSVD_MASK)
7368 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7369 else
7370 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7371 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7372 vmcs12->guest_physical_address = fault->address;
7373}
7374
155a97a3
NHE		 7375/* Callbacks for nested_ept_init_mmu_context: */
7376
7377static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7378{
7379 /* return the page table to be shadowed - in our case, EPT12 */
7380 return get_vmcs12(vcpu)->ept_pointer;
7381}
7382
7383static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7384{
7385 int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7386 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7387
7388 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7389 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7390 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7391
7392 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7393
7394 return r;
7395}
7396
7397static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7398{
7399 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7400}
7401
fe3ef05c
NHE		 7402/*
7403 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7404 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7405 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7406 * guest in a way that will both be appropriate to L1's requests, and our
7407 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7408 * function also has additional necessary side-effects, like setting various
7409 * vcpu->arch fields.
7410 */
7411static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7412{
7413 struct vcpu_vmx *vmx = to_vmx(vcpu);
7414 u32 exec_control;
7415
7416 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7417 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7418 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7419 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7420 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7421 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7422 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7423 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7424 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7425 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7426 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7427 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7428 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7429 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7430 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7431 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7432 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7433 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7434 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7435 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7436 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7437 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7438 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7439 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7440 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7441 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7442 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7443 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7444 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7445 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7446 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7447 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7448 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7449 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7450 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7451 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7452
7453 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7454 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7455 vmcs12->vm_entry_intr_info_field);
7456 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7457 vmcs12->vm_entry_exception_error_code);
7458 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7459 vmcs12->vm_entry_instruction_len);
7460 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7461 vmcs12->guest_interruptibility_info);
fe3ef05c 7462 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7463 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7464 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7465 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7466 vmcs12->guest_pending_dbg_exceptions);
7467 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7468 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7469
7470 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7471
7472 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7473 (vmcs_config.pin_based_exec_ctrl |
7474 vmcs12->pin_based_vm_exec_control));
7475
0238ea91
JK		 7476 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7477 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7478 vmcs12->vmx_preemption_timer_value);
7479
fe3ef05c
NHE		 7480 /*
7481 * Whether page-faults are trapped is determined by a combination of
7482 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7483 * If enable_ept, L0 doesn't care about page faults and we should
7484 * set all of these to L1's desires. However, if !enable_ept, L0 does
7485 * care about (at least some) page faults, and because it is not easy
7486 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7487 * to exit on each and every L2 page fault. This is done by setting
7488 * MASK=MATCH=0 and (see below) EB.PF=1.
7489 * Note that below we don't need special code to set EB.PF beyond the
7490 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7491 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7492 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7493 *
7494 * A problem with this approach (when !enable_ept) is that L1 may be
7495 * injected with more page faults than it asked for. This could have
7496 * caused problems, but in practice existing hypervisors don't care.
7497 * To fix this, we will need to emulate the PFEC checking (on the L1
7498 * page tables), using walk_addr(), when injecting PFs to L1.
7499 */
7500 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7501 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7502 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7503 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7504
7505 if (cpu_has_secondary_exec_ctrls()) {
7506 u32 exec_control = vmx_secondary_exec_control(vmx);
7507 if (!vmx->rdtscp_enabled)
7508 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7509 /* Take the following fields only from vmcs12 */
7510 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7511 if (nested_cpu_has(vmcs12,
7512 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7513 exec_control |= vmcs12->secondary_vm_exec_control;
7514
7515 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7516 /*
7517 * Translate L1 physical address to host physical
7518 * address for vmcs02. Keep the page pinned, so this
7519 * physical address remains valid. We keep a reference
7520 * to it so we can release it later.
7521 */
7522 if (vmx->nested.apic_access_page) /* shouldn't happen */
7523 nested_release_page(vmx->nested.apic_access_page);
7524 vmx->nested.apic_access_page =
7525 nested_get_page(vcpu, vmcs12->apic_access_addr);
7526 /*
7527 * If translation failed, no matter: This feature asks
7528 * to exit when accessing the given address, and if it
7529 * can never be accessed, this feature won't do
7530 * anything anyway.
7531 */
7532 if (!vmx->nested.apic_access_page)
7533 exec_control &=
7534 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7535 else
7536 vmcs_write64(APIC_ACCESS_ADDR,
7537 page_to_phys(vmx->nested.apic_access_page));
7538 }
7539
7540 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7541 }
7542
7543
7544 /*
7545 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7546 * Some constant fields are set here by vmx_set_constant_host_state().
7547 * Other fields are different per CPU, and will be set later when
7548 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7549 */
a547c6db 7550 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7551
7552 /*
7553 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7554 * entry, but only if the current (host) sp changed from the value
7555 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7556 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7557 * here we just force the write to happen on entry.
7558 */
7559 vmx->host_rsp = 0;
7560
7561 exec_control = vmx_exec_control(vmx); /* L0's desires */
7562 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7563 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7564 exec_control &= ~CPU_BASED_TPR_SHADOW;
7565 exec_control |= vmcs12->cpu_based_vm_exec_control;
7566 /*
7567 * Merging of IO and MSR bitmaps not currently supported.
7568 * Rather, exit every time.
7569 */
7570 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7571 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7572 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7573
7574 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7575
7576 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7577 * bitwise-or of what L1 wants to trap for L2, and what we want to
7578 * trap. Note that CR0.TS also needs updating - we do this later.
7579 */
7580 update_exception_bitmap(vcpu);
7581 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7582 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7583
8049d651
NHE		 7584 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7585 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7586 * bits are further modified by vmx_set_efer() below.
7587 */
7588 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7589
7590 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7591 * emulated by vmx_set_efer(), below.
7592 */
7593 vmcs_write32(VM_ENTRY_CONTROLS,
7594 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7595 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7596 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7597
7598 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7599 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7600 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7601 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7602
7603
7604 set_cr4_guest_host_mask(vmx);
7605
27fc51b2
NHE		 7606 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7607 vmcs_write64(TSC_OFFSET,
7608 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7609 else
7610 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7611
7612 if (enable_vpid) {
7613 /*
7614 * Trivially support vpid by letting L2s share their parent
7615 * L1's vpid. TODO: move to a more elaborate solution, giving
7616 * each L2 its own vpid and exposing the vpid feature to L1.
7617 */
7618 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7619 vmx_flush_tlb(vcpu);
7620 }
7621
155a97a3
NHE		 7622 if (nested_cpu_has_ept(vmcs12)) {
7623 kvm_mmu_unload(vcpu);
7624 nested_ept_init_mmu_context(vcpu);
7625 }
7626
fe3ef05c
NHE		 7627 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7628 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7629 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7630 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7631 else
7632 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7633 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7634 vmx_set_efer(vcpu, vcpu->arch.efer);
7635
7636 /*
7637 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7638 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7639 * The CR0_READ_SHADOW is what L2 should have expected to read given
7640 * the specifications by L1; It's not enough to take
7641 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7642 * have more bits than L1 expected.
7643 */
7644 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7645 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7646
7647 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7648 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7649
7650 /* shadow page tables on either EPT or shadow page tables */
7651 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7652 kvm_mmu_reset_context(vcpu);
7653
3633cfc3
NHE		 7654 /*
7655 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7656 */
7657 if (enable_ept) {
7658 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7659 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7660 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7661 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7662 }
7663
fe3ef05c
NHE		 7664 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7665 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7666}
7667
cd232ad0
NHE		 7668/*
7669 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7670 * for running an L2 nested guest.
7671 */
7672static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7673{
7674 struct vmcs12 *vmcs12;
7675 struct vcpu_vmx *vmx = to_vmx(vcpu);
7676 int cpu;
7677 struct loaded_vmcs *vmcs02;
384bb783 7678 bool ia32e;
cd232ad0
NHE		 7679
7680 if (!nested_vmx_check_permission(vcpu) ||
7681 !nested_vmx_check_vmcs12(vcpu))
7682 return 1;
7683
7684 skip_emulated_instruction(vcpu);
7685 vmcs12 = get_vmcs12(vcpu);
7686
012f83cb
AG		 7687 if (enable_shadow_vmcs)
7688 copy_shadow_to_vmcs12(vmx);
7689
7c177938
NHE		 7690 /*
7691 * The nested entry process starts with enforcing various prerequisites
7692 * on vmcs12 as required by the Intel SDM, and act appropriately when
7693 * they fail: As the SDM explains, some conditions should cause the
7694 * instruction to fail, while others will cause the instruction to seem
7695 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7696 * To speed up the normal (success) code path, we should avoid checking
7697 * for misconfigurations which will anyway be caught by the processor
7698 * when using the merged vmcs02.
7699 */
7700 if (vmcs12->launch_state == launch) {
7701 nested_vmx_failValid(vcpu,
7702 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7703 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7704 return 1;
7705 }
7706
26539bd0
PB		 7707 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7708 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7709 return 1;
7710 }
7711
7c177938
NHE		 7712 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7713 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7714 /*TODO: Also verify bits beyond physical address width are 0*/
7715 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7716 return 1;
7717 }
7718
7719 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7720 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7721 /*TODO: Also verify bits beyond physical address width are 0*/
7722 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7723 return 1;
7724 }
7725
7726 if (vmcs12->vm_entry_msr_load_count > 0 ||
7727 vmcs12->vm_exit_msr_load_count > 0 ||
7728 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7729 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7730 __func__);
7c177938
NHE		 7731 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7732 return 1;
7733 }
7734
7735 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7736 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7737 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7738 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7739 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7740 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7741 !vmx_control_verify(vmcs12->vm_exit_controls,
7742 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7743 !vmx_control_verify(vmcs12->vm_entry_controls,
7744 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7745 {
7746 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7747 return 1;
7748 }
7749
7750 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7751 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7752 nested_vmx_failValid(vcpu,
7753 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7754 return 1;
7755 }
7756
7757 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7758 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7759 nested_vmx_entry_failure(vcpu, vmcs12,
7760 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7761 return 1;
7762 }
7763 if (vmcs12->vmcs_link_pointer != -1ull) {
7764 nested_vmx_entry_failure(vcpu, vmcs12,
7765 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7766 return 1;
7767 }
7768
384bb783 7769 /*
cb0c8cda 7770 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7771 * are performed on the field for the IA32_EFER MSR:
7772 * - Bits reserved in the IA32_EFER MSR must be 0.
7773 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7774 * the IA-32e mode guest VM-exit control. It must also be identical
7775 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7776 * CR0.PG) is 1.
7777 */
7778 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7779 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7780 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7781 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7782 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7783 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7784 nested_vmx_entry_failure(vcpu, vmcs12,
7785 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7786 return 1;
7787 }
7788 }
7789
7790 /*
7791 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7792 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7793 * the values of the LMA and LME bits in the field must each be that of
7794 * the host address-space size VM-exit control.
7795 */
7796 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7797 ia32e = (vmcs12->vm_exit_controls &
7798 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7799 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7800 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7801 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7802 nested_vmx_entry_failure(vcpu, vmcs12,
7803 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7804 return 1;
7805 }
7806 }
7807
7c177938
NHE		 7808 /*
7809 * We're finally done with prerequisite checking, and can start with
7810 * the nested entry.
7811 */
7812
cd232ad0
NHE		 7813 vmcs02 = nested_get_current_vmcs02(vmx);
7814 if (!vmcs02)
7815 return -ENOMEM;
7816
7817 enter_guest_mode(vcpu);
7818
7819 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7820
7821 cpu = get_cpu();
7822 vmx->loaded_vmcs = vmcs02;
7823 vmx_vcpu_put(vcpu);
7824 vmx_vcpu_load(vcpu, cpu);
7825 vcpu->cpu = cpu;
7826 put_cpu();
7827
36c3cc42
JK		 7828 vmx_segment_cache_clear(vmx);
7829
cd232ad0
NHE		 7830 vmcs12->launch_state = 1;
7831
7832 prepare_vmcs02(vcpu, vmcs12);
7833
7834 /*
7835 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7836 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7837 * returned as far as L1 is concerned. It will only return (and set
7838 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7839 */
7840 return 1;
7841}
7842
4704d0be
NHE		 7843/*
7844 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7845 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7846 * This function returns the new value we should put in vmcs12.guest_cr0.
7847 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7848 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7849 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7850 * didn't trap the bit, because if L1 did, so would L0).
7851 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7852 * been modified by L2, and L1 knows it. So just leave the old value of
7853 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7854 * isn't relevant, because if L0 traps this bit it can set it to anything.
7855 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7856 * changed these bits, and therefore they need to be updated, but L0
7857 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7858 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7859 */
7860static inline unsigned long
7861vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7862{
7863 return
7864 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7865 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7866 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7867 vcpu->arch.cr0_guest_owned_bits));
7868}
7869
7870static inline unsigned long
7871vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7872{
7873 return
7874 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7875 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7876 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7877 vcpu->arch.cr4_guest_owned_bits));
7878}
7879
5f3d5799
JK		 7880static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7881 struct vmcs12 *vmcs12)
7882{
7883 u32 idt_vectoring;
7884 unsigned int nr;
7885
7886 if (vcpu->arch.exception.pending) {
7887 nr = vcpu->arch.exception.nr;
7888 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7889
7890 if (kvm_exception_is_soft(nr)) {
7891 vmcs12->vm_exit_instruction_len =
7892 vcpu->arch.event_exit_inst_len;
7893 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7894 } else
7895 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7896
7897 if (vcpu->arch.exception.has_error_code) {
7898 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7899 vmcs12->idt_vectoring_error_code =
7900 vcpu->arch.exception.error_code;
7901 }
7902
7903 vmcs12->idt_vectoring_info_field = idt_vectoring;
7904 } else if (vcpu->arch.nmi_pending) {
7905 vmcs12->idt_vectoring_info_field =
7906 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7907 } else if (vcpu->arch.interrupt.pending) {
7908 nr = vcpu->arch.interrupt.nr;
7909 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7910
7911 if (vcpu->arch.interrupt.soft) {
7912 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7913 vmcs12->vm_entry_instruction_len =
7914 vcpu->arch.event_exit_inst_len;
7915 } else
7916 idt_vectoring |= INTR_TYPE_EXT_INTR;
7917
7918 vmcs12->idt_vectoring_info_field = idt_vectoring;
7919 }
7920}
7921
4704d0be
NHE		 7922/*
7923 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7924 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7925 * and this function updates it to reflect the changes to the guest state while
7926 * L2 was running (and perhaps made some exits which were handled directly by L0
7927 * without going back to L1), and to reflect the exit reason.
7928 * Note that we do not have to copy here all VMCS fields, just those that
7929 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7930 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7931 * which already writes to vmcs12 directly.
7932 */
733568f9 7933static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7934{
7935 /* update guest state fields: */
7936 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7937 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7938
7939 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7940 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7941 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7942 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7943
7944 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7945 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7946 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7947 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7948 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7949 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7950 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7951 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7952 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7953 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7954 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7955 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7956 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7957 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7958 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7959 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7960 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7961 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7962 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7963 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7964 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7965 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7966 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7967 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7968 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7969 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7970 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7971 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7972 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7973 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7974 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7975 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7976 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7977 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7978 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7979 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7980
4704d0be
NHE		 7981 vmcs12->guest_interruptibility_info =
7982 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7983 vmcs12->guest_pending_dbg_exceptions =
7984 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7985
3633cfc3
NHE		 7986 /*
7987 * In some cases (usually, nested EPT), L2 is allowed to change its
7988 * own CR3 without exiting. If it has changed it, we must keep it.
7989 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
7990 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
7991 *
7992 * Additionally, restore L2's PDPTR to vmcs12.
7993 */
7994 if (enable_ept) {
7995 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
7996 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
7997 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
7998 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
7999 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8000 }
8001
c18911a2
JK		 8002 vmcs12->vm_entry_controls =
8003 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8004 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8005
4704d0be
NHE		 8006 /* TODO: These cannot have changed unless we have MSR bitmaps and
8007 * the relevant bit asks not to trap the change */
8008 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8009 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 8010 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8011 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8012 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8013 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8014
8015 /* update exit information fields: */
8016
957c897e 8017 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8018 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8019
8020 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8021 if ((vmcs12->vm_exit_intr_info &
8022 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8023 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8024 vmcs12->vm_exit_intr_error_code =
8025 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8026 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8027 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8028 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8029
5f3d5799
JK		 8030 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8031 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8032 * instead of reading the real value. */
4704d0be 8033 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8034
8035 /*
8036 * Transfer the event that L0 or L1 may wanted to inject into
8037 * L2 to IDT_VECTORING_INFO_FIELD.
8038 */
8039 vmcs12_save_pending_event(vcpu, vmcs12);
8040 }
8041
8042 /*
8043 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8044 * preserved above and would only end up incorrectly in L1.
8045 */
8046 vcpu->arch.nmi_injected = false;
8047 kvm_clear_exception_queue(vcpu);
8048 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8049}
8050
8051/*
8052 * A part of what we need to when the nested L2 guest exits and we want to
8053 * run its L1 parent, is to reset L1's guest state to the host state specified
8054 * in vmcs12.
8055 * This function is to be called not only on normal nested exit, but also on
8056 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8057 * Failures During or After Loading Guest State").
8058 * This function should be called when the active VMCS is L1's (vmcs01).
8059 */
733568f9
JK		 8060static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8061 struct vmcs12 *vmcs12)
4704d0be 8062{
21feb4eb
ACL		 8063 struct kvm_segment seg;
8064
4704d0be
NHE		 8065 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8066 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8067 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8068 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8069 else
8070 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8071 vmx_set_efer(vcpu, vcpu->arch.efer);
8072
8073 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8074 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8075 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8076 /*
8077 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8078 * actually changed, because it depends on the current state of
8079 * fpu_active (which may have changed).
8080 * Note that vmx_set_cr0 refers to efer set above.
8081 */
8082 kvm_set_cr0(vcpu, vmcs12->host_cr0);
8083 /*
8084 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8085 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8086 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8087 */
8088 update_exception_bitmap(vcpu);
8089 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8090 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8091
8092 /*
8093 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8094 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8095 */
8096 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8097 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8098
155a97a3
NHE		 8099 if (nested_cpu_has_ept(vmcs12))
8100 nested_ept_uninit_mmu_context(vcpu);
8101
4704d0be
NHE		 8102 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8103 kvm_mmu_reset_context(vcpu);
8104
8105 if (enable_vpid) {
8106 /*
8107 * Trivially support vpid by letting L2s share their parent
8108 * L1's vpid. TODO: move to a more elaborate solution, giving
8109 * each L2 its own vpid and exposing the vpid feature to L1.
8110 */
8111 vmx_flush_tlb(vcpu);
8112 }
8113
8114
8115 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8116 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8117 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8118 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8119 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be
NHE		 8120
8121 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8122 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8123 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8124 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8125 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8126
21feb4eb
ACL		 8127 /* Set L1 segment info according to Intel SDM
8128 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8129 seg = (struct kvm_segment) {
8130 .base = 0,
8131 .limit = 0xFFFFFFFF,
8132 .selector = vmcs12->host_cs_selector,
8133 .type = 11,
8134 .present = 1,
8135 .s = 1,
8136 .g = 1
8137 };
8138 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8139 seg.l = 1;
8140 else
8141 seg.db = 1;
8142 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8143 seg = (struct kvm_segment) {
8144 .base = 0,
8145 .limit = 0xFFFFFFFF,
8146 .type = 3,
8147 .present = 1,
8148 .s = 1,
8149 .db = 1,
8150 .g = 1
8151 };
8152 seg.selector = vmcs12->host_ds_selector;
8153 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8154 seg.selector = vmcs12->host_es_selector;
8155 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8156 seg.selector = vmcs12->host_ss_selector;
8157 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8158 seg.selector = vmcs12->host_fs_selector;
8159 seg.base = vmcs12->host_fs_base;
8160 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8161 seg.selector = vmcs12->host_gs_selector;
8162 seg.base = vmcs12->host_gs_base;
8163 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8164 seg = (struct kvm_segment) {
205befd9 8165 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8166 .limit = 0x67,
8167 .selector = vmcs12->host_tr_selector,
8168 .type = 11,
8169 .present = 1
8170 };
8171 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8172
503cd0c5
JK		 8173 kvm_set_dr(vcpu, 7, 0x400);
8174 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8175}
8176
8177/*
8178 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8179 * and modify vmcs12 to make it see what it would expect to see there if
8180 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8181 */
8182static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8183{
8184 struct vcpu_vmx *vmx = to_vmx(vcpu);
8185 int cpu;
8186 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8187
5f3d5799
JK		 8188 /* trying to cancel vmlaunch/vmresume is a bug */
8189 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8190
4704d0be
NHE		 8191 leave_guest_mode(vcpu);
8192 prepare_vmcs12(vcpu, vmcs12);
8193
8194 cpu = get_cpu();
8195 vmx->loaded_vmcs = &vmx->vmcs01;
8196 vmx_vcpu_put(vcpu);
8197 vmx_vcpu_load(vcpu, cpu);
8198 vcpu->cpu = cpu;
8199 put_cpu();
8200
36c3cc42
JK		 8201 vmx_segment_cache_clear(vmx);
8202
4704d0be
NHE		 8203 /* if no vmcs02 cache requested, remove the one we used */
8204 if (VMCS02_POOL_SIZE == 0)
8205 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8206
8207 load_vmcs12_host_state(vcpu, vmcs12);
8208
27fc51b2 8209 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8210 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8211
8212 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8213 vmx->host_rsp = 0;
8214
8215 /* Unpin physical memory we referred to in vmcs02 */
8216 if (vmx->nested.apic_access_page) {
8217 nested_release_page(vmx->nested.apic_access_page);
8218 vmx->nested.apic_access_page = 0;
8219 }
8220
8221 /*
8222 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8223 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8224 * success or failure flag accordingly.
8225 */
8226 if (unlikely(vmx->fail)) {
8227 vmx->fail = 0;
8228 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8229 } else
8230 nested_vmx_succeed(vcpu);
012f83cb
AG		 8231 if (enable_shadow_vmcs)
8232 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8233}
8234
7c177938
NHE		 8235/*
8236 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8237 * 23.7 "VM-entry failures during or after loading guest state" (this also
8238 * lists the acceptable exit-reason and exit-qualification parameters).
8239 * It should only be called before L2 actually succeeded to run, and when
8240 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8241 */
8242static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8243 struct vmcs12 *vmcs12,
8244 u32 reason, unsigned long qualification)
8245{
8246 load_vmcs12_host_state(vcpu, vmcs12);
8247 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8248 vmcs12->exit_qualification = qualification;
8249 nested_vmx_succeed(vcpu);
012f83cb
AG		 8250 if (enable_shadow_vmcs)
8251 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8252}
8253
8a76d7f2
JR		 8254static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8255 struct x86_instruction_info *info,
8256 enum x86_intercept_stage stage)
8257{
8258 return X86EMUL_CONTINUE;
8259}
8260
cbdd1bea 8261static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8262 .cpu_has_kvm_support = cpu_has_kvm_support,
8263 .disabled_by_bios = vmx_disabled_by_bios,
8264 .hardware_setup = hardware_setup,
8265 .hardware_unsetup = hardware_unsetup,
002c7f7c 8266 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8267 .hardware_enable = hardware_enable,
8268 .hardware_disable = hardware_disable,
04547156 8269 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8270
8271 .vcpu_create = vmx_create_vcpu,
8272 .vcpu_free = vmx_free_vcpu,
04d2cc77 8273 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8274
04d2cc77 8275 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8276 .vcpu_load = vmx_vcpu_load,
8277 .vcpu_put = vmx_vcpu_put,
8278
c8639010 8279 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8280 .get_msr = vmx_get_msr,
8281 .set_msr = vmx_set_msr,
8282 .get_segment_base = vmx_get_segment_base,
8283 .get_segment = vmx_get_segment,
8284 .set_segment = vmx_set_segment,
2e4d2653 8285 .get_cpl = vmx_get_cpl,
6aa8b732 8286 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8287 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8288 .decache_cr3 = vmx_decache_cr3,
25c4c276 8289 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8290 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8291 .set_cr3 = vmx_set_cr3,
8292 .set_cr4 = vmx_set_cr4,
6aa8b732 8293 .set_efer = vmx_set_efer,
6aa8b732
AK		 8294 .get_idt = vmx_get_idt,
8295 .set_idt = vmx_set_idt,
8296 .get_gdt = vmx_get_gdt,
8297 .set_gdt = vmx_set_gdt,
020df079 8298 .set_dr7 = vmx_set_dr7,
5fdbf976 8299 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8300 .get_rflags = vmx_get_rflags,
8301 .set_rflags = vmx_set_rflags,
ebcbab4c 8302 .fpu_activate = vmx_fpu_activate,
02daab21 8303 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8304
8305 .tlb_flush = vmx_flush_tlb,
6aa8b732 8306
6aa8b732 8307 .run = vmx_vcpu_run,
6062d012 8308 .handle_exit = vmx_handle_exit,
6aa8b732 8309 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8310 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8311 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8312 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8313 .set_irq = vmx_inject_irq,
95ba8273 8314 .set_nmi = vmx_inject_nmi,
298101da 8315 .queue_exception = vmx_queue_exception,
b463a6f7 8316 .cancel_injection = vmx_cancel_injection,
78646121 8317 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8318 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8319 .get_nmi_mask = vmx_get_nmi_mask,
8320 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8321 .enable_nmi_window = enable_nmi_window,
8322 .enable_irq_window = enable_irq_window,
8323 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8324 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8325 .vm_has_apicv = vmx_vm_has_apicv,
8326 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8327 .hwapic_irr_update = vmx_hwapic_irr_update,
8328 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8329 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8330 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8331
cbc94022 8332 .set_tss_addr = vmx_set_tss_addr,
67253af5 8333 .get_tdp_level = get_ept_level,
4b12f0de 8334 .get_mt_mask = vmx_get_mt_mask,
229456fc 8335
586f9607 8336 .get_exit_info = vmx_get_exit_info,
586f9607 8337
17cc3935 8338 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8339
8340 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8341
8342 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8343 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8344
8345 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8346
8347 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8348
4051b188 8349 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8350 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8351 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8352 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8353 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8354 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8355
8356 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8357
8358 .check_intercept = vmx_check_intercept,
a547c6db 8359 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8360};
8361
8362static int __init vmx_init(void)
8363{
8d14695f 8364 int r, i, msr;
26bb0981
AK		 8365
8366 rdmsrl_safe(MSR_EFER, &host_efer);
8367
8368 for (i = 0; i < NR_VMX_MSR; ++i)
8369 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8370
3e7c73e9 8371 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8372 if (!vmx_io_bitmap_a)
8373 return -ENOMEM;
8374
2106a548
GC		 8375 r = -ENOMEM;
8376
3e7c73e9 8377 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8378 if (!vmx_io_bitmap_b)
fdef3ad1 8379 goto out;
fdef3ad1 8380
5897297b 8381 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8382 if (!vmx_msr_bitmap_legacy)
25c5f225 8383 goto out1;
2106a548 8384
8d14695f
YZ		 8385 vmx_msr_bitmap_legacy_x2apic =
8386 (unsigned long *)__get_free_page(GFP_KERNEL);
8387 if (!vmx_msr_bitmap_legacy_x2apic)
8388 goto out2;
25c5f225 8389
5897297b 8390 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8391 if (!vmx_msr_bitmap_longmode)
8d14695f 8392 goto out3;
2106a548 8393
8d14695f
YZ		 8394 vmx_msr_bitmap_longmode_x2apic =
8395 (unsigned long *)__get_free_page(GFP_KERNEL);
8396 if (!vmx_msr_bitmap_longmode_x2apic)
8397 goto out4;
4607c2d7
AG		 8398 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8399 if (!vmx_vmread_bitmap)
8400 goto out5;
8401
8402 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8403 if (!vmx_vmwrite_bitmap)
8404 goto out6;
8405
8406 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8407 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8408 /* shadowed read/write fields */
8409 for (i = 0; i < max_shadow_read_write_fields; i++) {
8410 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8411 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8412 }
8413 /* shadowed read only fields */
8414 for (i = 0; i < max_shadow_read_only_fields; i++)
8415 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8416
fdef3ad1
HQ		 8417 /*
8418 * Allow direct access to the PC debug port (it is often used for I/O
8419 * delays, but the vmexits simply slow things down).
8420 */
3e7c73e9
AK		 8421 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8422 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8423
3e7c73e9 8424 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8425
5897297b
AK		 8426 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8427 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8428
2384d2b3
SY		 8429 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8430
0ee75bea
AK		 8431 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8432 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8433 if (r)
4607c2d7 8434 goto out7;
25c5f225 8435
8f536b76
ZY		 8436#ifdef CONFIG_KEXEC
8437 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8438 crash_vmclear_local_loaded_vmcss);
8439#endif
8440
5897297b
AK		 8441 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8442 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8443 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8444 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8445 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8446 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8447 memcpy(vmx_msr_bitmap_legacy_x2apic,
8448 vmx_msr_bitmap_legacy, PAGE_SIZE);
8449 memcpy(vmx_msr_bitmap_longmode_x2apic,
8450 vmx_msr_bitmap_longmode, PAGE_SIZE);
8451
01e439be 8452 if (enable_apicv) {
8d14695f
YZ		 8453 for (msr = 0x800; msr <= 0x8ff; msr++)
8454 vmx_disable_intercept_msr_read_x2apic(msr);
8455
8456 /* According SDM, in x2apic mode, the whole id reg is used.
8457 * But in KVM, it only use the highest eight bits. Need to
8458 * intercept it */
8459 vmx_enable_intercept_msr_read_x2apic(0x802);
8460 /* TMCCT */
8461 vmx_enable_intercept_msr_read_x2apic(0x839);
8462 /* TPR */
8463 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8464 /* EOI */
8465 vmx_disable_intercept_msr_write_x2apic(0x80b);
8466 /* SELF-IPI */
8467 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8468 }
fdef3ad1 8469
089d034e 8470 if (enable_ept) {
3f6d8c8a
XH		 8471 kvm_mmu_set_mask_ptes(0ull,
8472 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8473 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8474 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8475 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8476 kvm_enable_tdp();
8477 } else
8478 kvm_disable_tdp();
1439442c 8479
fdef3ad1
HQ		 8480 return 0;
8481
4607c2d7
AG		 8482out7:
8483 free_page((unsigned long)vmx_vmwrite_bitmap);
8484out6:
8485 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8486out5:
8487 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8488out4:
5897297b 8489 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8490out3:
8491 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8492out2:
5897297b 8493 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8494out1:
3e7c73e9 8495 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8496out:
3e7c73e9 8497 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8498 return r;
6aa8b732
AK		 8499}
8500
8501static void __exit vmx_exit(void)
8502{
8d14695f
YZ		 8503 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8504 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8505 free_page((unsigned long)vmx_msr_bitmap_legacy);
8506 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8507 free_page((unsigned long)vmx_io_bitmap_b);
8508 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8509 free_page((unsigned long)vmx_vmwrite_bitmap);
8510 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8511
8f536b76
ZY		 8512#ifdef CONFIG_KEXEC
8513 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8514 synchronize_rcu();
8515#endif
8516
cb498ea2 8517 kvm_exit();
6aa8b732
AK		 8518}
8519
8520module_init(vmx_init)
8521module_exit(vmx_exit)
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