]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nEPT: correctly check if remote tlb flush is needed for shadowed EPT tables
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
4e1096d2 715static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 716static void kvm_cpu_vmxon(u64 addr);
717static void kvm_cpu_vmxoff(void);
aff48baa 718static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
644d711a
NHE		 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1044 struct kvm_vcpu *vcpu)
1045{
1046 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1047}
1048
1049static inline bool is_exception(u32 intr_info)
1050{
1051 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1052 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1053}
1054
1055static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1056static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1057 struct vmcs12 *vmcs12,
1058 u32 reason, unsigned long qualification);
1059
8b9cf98c 1060static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1061{
1062 int i;
1063
a2fa3e9f 1064 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1065 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1066 return i;
1067 return -1;
1068}
1069
2384d2b3
SY		 1070static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1071{
1072 struct {
1073 u64 vpid : 16;
1074 u64 rsvd : 48;
1075 u64 gva;
1076 } operand = { vpid, 0, gva };
1077
4ecac3fd 1078 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1079 /* CF==1 or ZF==1 --> rc = -1 */
1080 "; ja 1f ; ud2 ; 1:"
1081 : : "a"(&operand), "c"(ext) : "cc", "memory");
1082}
1083
1439442c
SY		 1084static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1085{
1086 struct {
1087 u64 eptp, gpa;
1088 } operand = {eptp, gpa};
1089
4ecac3fd 1090 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1091 /* CF==1 or ZF==1 --> rc = -1 */
1092 "; ja 1f ; ud2 ; 1:\n"
1093 : : "a" (&operand), "c" (ext) : "cc", "memory");
1094}
1095
26bb0981 1096static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1097{
1098 int i;
1099
8b9cf98c 1100 i = __find_msr_index(vmx, msr);
a75beee6 1101 if (i >= 0)
a2fa3e9f 1102 return &vmx->guest_msrs[i];
8b6d44c7 1103 return NULL;
7725f0ba
AK		 1104}
1105
6aa8b732
AK		 1106static void vmcs_clear(struct vmcs *vmcs)
1107{
1108 u64 phys_addr = __pa(vmcs);
1109 u8 error;
1110
4ecac3fd 1111 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1112 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1113 : "cc", "memory");
1114 if (error)
1115 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1116 vmcs, phys_addr);
1117}
1118
d462b819
NHE		 1119static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1120{
1121 vmcs_clear(loaded_vmcs->vmcs);
1122 loaded_vmcs->cpu = -1;
1123 loaded_vmcs->launched = 0;
1124}
1125
7725b894
DX		 1126static void vmcs_load(struct vmcs *vmcs)
1127{
1128 u64 phys_addr = __pa(vmcs);
1129 u8 error;
1130
1131 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1132 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1133 : "cc", "memory");
1134 if (error)
2844d849 1135 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1136 vmcs, phys_addr);
1137}
1138
8f536b76
ZY		 1139#ifdef CONFIG_KEXEC
1140/*
1141 * This bitmap is used to indicate whether the vmclear
1142 * operation is enabled on all cpus. All disabled by
1143 * default.
1144 */
1145static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1146
1147static inline void crash_enable_local_vmclear(int cpu)
1148{
1149 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1150}
1151
1152static inline void crash_disable_local_vmclear(int cpu)
1153{
1154 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1155}
1156
1157static inline int crash_local_vmclear_enabled(int cpu)
1158{
1159 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1160}
1161
1162static void crash_vmclear_local_loaded_vmcss(void)
1163{
1164 int cpu = raw_smp_processor_id();
1165 struct loaded_vmcs *v;
1166
1167 if (!crash_local_vmclear_enabled(cpu))
1168 return;
1169
1170 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1171 loaded_vmcss_on_cpu_link)
1172 vmcs_clear(v->vmcs);
1173}
1174#else
1175static inline void crash_enable_local_vmclear(int cpu) { }
1176static inline void crash_disable_local_vmclear(int cpu) { }
1177#endif /* CONFIG_KEXEC */
1178
d462b819 1179static void __loaded_vmcs_clear(void *arg)
6aa8b732 1180{
d462b819 1181 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1182 int cpu = raw_smp_processor_id();
6aa8b732 1183
d462b819
NHE		 1184 if (loaded_vmcs->cpu != cpu)
1185 return; /* vcpu migration can race with cpu offline */
1186 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1187 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1188 crash_disable_local_vmclear(cpu);
d462b819 1189 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1190
1191 /*
1192 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1193 * is before setting loaded_vmcs->vcpu to -1 which is done in
1194 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1195 * then adds the vmcs into percpu list before it is deleted.
1196 */
1197 smp_wmb();
1198
d462b819 1199 loaded_vmcs_init(loaded_vmcs);
8f536b76 1200 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1201}
1202
d462b819 1203static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1204{
e6c7d321
XG		 1205 int cpu = loaded_vmcs->cpu;
1206
1207 if (cpu != -1)
1208 smp_call_function_single(cpu,
1209 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1210}
1211
1760dd49 1212static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1213{
1214 if (vmx->vpid == 0)
1215 return;
1216
518c8aee
GJ		 1217 if (cpu_has_vmx_invvpid_single())
1218 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1219}
1220
b9d762fa
GJ		 1221static inline void vpid_sync_vcpu_global(void)
1222{
1223 if (cpu_has_vmx_invvpid_global())
1224 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1225}
1226
1227static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1228{
1229 if (cpu_has_vmx_invvpid_single())
1760dd49 1230 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1231 else
1232 vpid_sync_vcpu_global();
1233}
1234
1439442c
SY		 1235static inline void ept_sync_global(void)
1236{
1237 if (cpu_has_vmx_invept_global())
1238 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1239}
1240
1241static inline void ept_sync_context(u64 eptp)
1242{
089d034e 1243 if (enable_ept) {
1439442c
SY		 1244 if (cpu_has_vmx_invept_context())
1245 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1246 else
1247 ept_sync_global();
1248 }
1249}
1250
96304217 1251static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1252{
5e520e62 1253 unsigned long value;
6aa8b732 1254
5e520e62
AK		 1255 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1256 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1257 return value;
1258}
1259
96304217 1260static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1261{
1262 return vmcs_readl(field);
1263}
1264
96304217 1265static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1266{
1267 return vmcs_readl(field);
1268}
1269
96304217 1270static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1271{
05b3e0c2 1272#ifdef CONFIG_X86_64
6aa8b732
AK		 1273 return vmcs_readl(field);
1274#else
1275 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1276#endif
1277}
1278
e52de1b8
AK		 1279static noinline void vmwrite_error(unsigned long field, unsigned long value)
1280{
1281 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1282 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1283 dump_stack();
1284}
1285
6aa8b732
AK		 1286static void vmcs_writel(unsigned long field, unsigned long value)
1287{
1288 u8 error;
1289
4ecac3fd 1290 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1291 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1292 if (unlikely(error))
1293 vmwrite_error(field, value);
6aa8b732
AK		 1294}
1295
1296static void vmcs_write16(unsigned long field, u16 value)
1297{
1298 vmcs_writel(field, value);
1299}
1300
1301static void vmcs_write32(unsigned long field, u32 value)
1302{
1303 vmcs_writel(field, value);
1304}
1305
1306static void vmcs_write64(unsigned long field, u64 value)
1307{
6aa8b732 1308 vmcs_writel(field, value);
7682f2d0 1309#ifndef CONFIG_X86_64
6aa8b732
AK		 1310 asm volatile ("");
1311 vmcs_writel(field+1, value >> 32);
1312#endif
1313}
1314
2ab455cc
AL		 1315static void vmcs_clear_bits(unsigned long field, u32 mask)
1316{
1317 vmcs_writel(field, vmcs_readl(field) & ~mask);
1318}
1319
1320static void vmcs_set_bits(unsigned long field, u32 mask)
1321{
1322 vmcs_writel(field, vmcs_readl(field) | mask);
1323}
1324
2fb92db1
AK		 1325static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1326{
1327 vmx->segment_cache.bitmask = 0;
1328}
1329
1330static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1331 unsigned field)
1332{
1333 bool ret;
1334 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1335
1336 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1337 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1338 vmx->segment_cache.bitmask = 0;
1339 }
1340 ret = vmx->segment_cache.bitmask & mask;
1341 vmx->segment_cache.bitmask |= mask;
1342 return ret;
1343}
1344
1345static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1346{
1347 u16 *p = &vmx->segment_cache.seg[seg].selector;
1348
1349 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1350 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1351 return *p;
1352}
1353
1354static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1355{
1356 ulong *p = &vmx->segment_cache.seg[seg].base;
1357
1358 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1359 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1360 return *p;
1361}
1362
1363static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1364{
1365 u32 *p = &vmx->segment_cache.seg[seg].limit;
1366
1367 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1368 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1369 return *p;
1370}
1371
1372static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1373{
1374 u32 *p = &vmx->segment_cache.seg[seg].ar;
1375
1376 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1377 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1378 return *p;
1379}
1380
abd3f2d6
AK		 1381static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1382{
1383 u32 eb;
1384
fd7373cc
JK		 1385 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1386 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1387 if ((vcpu->guest_debug &
1388 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1389 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1390 eb |= 1u << BP_VECTOR;
7ffd92c5 1391 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1392 eb = ~0;
089d034e 1393 if (enable_ept)
1439442c 1394 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1395 if (vcpu->fpu_active)
1396 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1397
1398 /* When we are running a nested L2 guest and L1 specified for it a
1399 * certain exception bitmap, we must trap the same exceptions and pass
1400 * them to L1. When running L2, we will only handle the exceptions
1401 * specified above if L1 did not want them.
1402 */
1403 if (is_guest_mode(vcpu))
1404 eb |= get_vmcs12(vcpu)->exception_bitmap;
1405
abd3f2d6
AK		 1406 vmcs_write32(EXCEPTION_BITMAP, eb);
1407}
1408
8bf00a52
GN		 1409static void clear_atomic_switch_msr_special(unsigned long entry,
1410 unsigned long exit)
1411{
1412 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1413 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1414}
1415
61d2ef2c
AK		 1416static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1417{
1418 unsigned i;
1419 struct msr_autoload *m = &vmx->msr_autoload;
1420
8bf00a52
GN		 1421 switch (msr) {
1422 case MSR_EFER:
1423 if (cpu_has_load_ia32_efer) {
1424 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1425 VM_EXIT_LOAD_IA32_EFER);
1426 return;
1427 }
1428 break;
1429 case MSR_CORE_PERF_GLOBAL_CTRL:
1430 if (cpu_has_load_perf_global_ctrl) {
1431 clear_atomic_switch_msr_special(
1432 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1433 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1434 return;
1435 }
1436 break;
110312c8
AK		 1437 }
1438
61d2ef2c
AK		 1439 for (i = 0; i < m->nr; ++i)
1440 if (m->guest[i].index == msr)
1441 break;
1442
1443 if (i == m->nr)
1444 return;
1445 --m->nr;
1446 m->guest[i] = m->guest[m->nr];
1447 m->host[i] = m->host[m->nr];
1448 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1449 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1450}
1451
8bf00a52
GN		 1452static void add_atomic_switch_msr_special(unsigned long entry,
1453 unsigned long exit, unsigned long guest_val_vmcs,
1454 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1455{
1456 vmcs_write64(guest_val_vmcs, guest_val);
1457 vmcs_write64(host_val_vmcs, host_val);
1458 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1459 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1460}
1461
61d2ef2c
AK		 1462static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1463 u64 guest_val, u64 host_val)
1464{
1465 unsigned i;
1466 struct msr_autoload *m = &vmx->msr_autoload;
1467
8bf00a52
GN		 1468 switch (msr) {
1469 case MSR_EFER:
1470 if (cpu_has_load_ia32_efer) {
1471 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1472 VM_EXIT_LOAD_IA32_EFER,
1473 GUEST_IA32_EFER,
1474 HOST_IA32_EFER,
1475 guest_val, host_val);
1476 return;
1477 }
1478 break;
1479 case MSR_CORE_PERF_GLOBAL_CTRL:
1480 if (cpu_has_load_perf_global_ctrl) {
1481 add_atomic_switch_msr_special(
1482 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1483 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1484 GUEST_IA32_PERF_GLOBAL_CTRL,
1485 HOST_IA32_PERF_GLOBAL_CTRL,
1486 guest_val, host_val);
1487 return;
1488 }
1489 break;
110312c8
AK		 1490 }
1491
61d2ef2c
AK		 1492 for (i = 0; i < m->nr; ++i)
1493 if (m->guest[i].index == msr)
1494 break;
1495
e7fc6f93
GN		 1496 if (i == NR_AUTOLOAD_MSRS) {
1497 printk_once(KERN_WARNING"Not enough mst switch entries. "
1498 "Can't add msr %x\n", msr);
1499 return;
1500 } else if (i == m->nr) {
61d2ef2c
AK		 1501 ++m->nr;
1502 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1503 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1504 }
1505
1506 m->guest[i].index = msr;
1507 m->guest[i].value = guest_val;
1508 m->host[i].index = msr;
1509 m->host[i].value = host_val;
1510}
1511
33ed6329
AK		 1512static void reload_tss(void)
1513{
33ed6329
AK		 1514 /*
1515 * VT restores TR but not its size. Useless.
1516 */
d359192f 1517 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1518 struct desc_struct *descs;
33ed6329 1519
d359192f 1520 descs = (void *)gdt->address;
33ed6329
AK		 1521 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1522 load_TR_desc();
33ed6329
AK		 1523}
1524
92c0d900 1525static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1526{
3a34a881 1527 u64 guest_efer;
51c6cf66
AK		 1528 u64 ignore_bits;
1529
f6801dff 1530 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1531
51c6cf66 1532 /*
0fa06071 1533 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1534 * outside long mode
1535 */
1536 ignore_bits = EFER_NX | EFER_SCE;
1537#ifdef CONFIG_X86_64
1538 ignore_bits |= EFER_LMA | EFER_LME;
1539 /* SCE is meaningful only in long mode on Intel */
1540 if (guest_efer & EFER_LMA)
1541 ignore_bits &= ~(u64)EFER_SCE;
1542#endif
51c6cf66
AK		 1543 guest_efer &= ~ignore_bits;
1544 guest_efer |= host_efer & ignore_bits;
26bb0981 1545 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1546 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1547
1548 clear_atomic_switch_msr(vmx, MSR_EFER);
1549 /* On ept, can't emulate nx, and must switch nx atomically */
1550 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1551 guest_efer = vmx->vcpu.arch.efer;
1552 if (!(guest_efer & EFER_LMA))
1553 guest_efer &= ~EFER_LME;
1554 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1555 return false;
1556 }
1557
26bb0981 1558 return true;
51c6cf66
AK		 1559}
1560
2d49ec72
GN		 1561static unsigned long segment_base(u16 selector)
1562{
d359192f 1563 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1564 struct desc_struct *d;
1565 unsigned long table_base;
1566 unsigned long v;
1567
1568 if (!(selector & ~3))
1569 return 0;
1570
d359192f 1571 table_base = gdt->address;
2d49ec72
GN		 1572
1573 if (selector & 4) { /* from ldt */
1574 u16 ldt_selector = kvm_read_ldt();
1575
1576 if (!(ldt_selector & ~3))
1577 return 0;
1578
1579 table_base = segment_base(ldt_selector);
1580 }
1581 d = (struct desc_struct *)(table_base + (selector & ~7));
1582 v = get_desc_base(d);
1583#ifdef CONFIG_X86_64
1584 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1585 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1586#endif
1587 return v;
1588}
1589
1590static inline unsigned long kvm_read_tr_base(void)
1591{
1592 u16 tr;
1593 asm("str %0" : "=g"(tr));
1594 return segment_base(tr);
1595}
1596
04d2cc77 1597static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1598{
04d2cc77 1599 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1600 int i;
04d2cc77 1601
a2fa3e9f 1602 if (vmx->host_state.loaded)
33ed6329
AK		 1603 return;
1604
a2fa3e9f 1605 vmx->host_state.loaded = 1;
33ed6329
AK		 1606 /*
1607 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1608 * allow segment selectors with cpl > 0 or ti == 1.
1609 */
d6e88aec 1610 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1611 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1612 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1613 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1614 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1615 vmx->host_state.fs_reload_needed = 0;
1616 } else {
33ed6329 1617 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1618 vmx->host_state.fs_reload_needed = 1;
33ed6329 1619 }
9581d442 1620 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1621 if (!(vmx->host_state.gs_sel & 7))
1622 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1623 else {
1624 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1625 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1626 }
1627
b2da15ac
AK		 1628#ifdef CONFIG_X86_64
1629 savesegment(ds, vmx->host_state.ds_sel);
1630 savesegment(es, vmx->host_state.es_sel);
1631#endif
1632
33ed6329
AK		 1633#ifdef CONFIG_X86_64
1634 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1635 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1636#else
a2fa3e9f
GH		 1637 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1638 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1639#endif
707c0874
AK		 1640
1641#ifdef CONFIG_X86_64
c8770e7b
AK		 1642 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1643 if (is_long_mode(&vmx->vcpu))
44ea2b17 1644 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1645#endif
26bb0981
AK		 1646 for (i = 0; i < vmx->save_nmsrs; ++i)
1647 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1648 vmx->guest_msrs[i].data,
1649 vmx->guest_msrs[i].mask);
33ed6329
AK		 1650}
1651
a9b21b62 1652static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1653{
a2fa3e9f 1654 if (!vmx->host_state.loaded)
33ed6329
AK		 1655 return;
1656
e1beb1d3 1657 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1658 vmx->host_state.loaded = 0;
c8770e7b
AK		 1659#ifdef CONFIG_X86_64
1660 if (is_long_mode(&vmx->vcpu))
1661 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1662#endif
152d3f2f 1663 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1664 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1665#ifdef CONFIG_X86_64
9581d442 1666 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1667#else
1668 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1669#endif
33ed6329 1670 }
0a77fe4c
AK		 1671 if (vmx->host_state.fs_reload_needed)
1672 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1673#ifdef CONFIG_X86_64
1674 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1675 loadsegment(ds, vmx->host_state.ds_sel);
1676 loadsegment(es, vmx->host_state.es_sel);
1677 }
b2da15ac 1678#endif
152d3f2f 1679 reload_tss();
44ea2b17 1680#ifdef CONFIG_X86_64
c8770e7b 1681 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1682#endif
b1a74bf8
SS		 1683 /*
1684 * If the FPU is not active (through the host task or
1685 * the guest vcpu), then restore the cr0.TS bit.
1686 */
1687 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1688 stts();
3444d7da 1689 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1690}
1691
a9b21b62
AK		 1692static void vmx_load_host_state(struct vcpu_vmx *vmx)
1693{
1694 preempt_disable();
1695 __vmx_load_host_state(vmx);
1696 preempt_enable();
1697}
1698
6aa8b732
AK		 1699/*
1700 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1701 * vcpu mutex is already taken.
1702 */
15ad7146 1703static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1704{
a2fa3e9f 1705 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1706 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1707
4610c9cc
DX		 1708 if (!vmm_exclusive)
1709 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1710 else if (vmx->loaded_vmcs->cpu != cpu)
1711 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1712
d462b819
NHE		 1713 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1714 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1715 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1716 }
1717
d462b819 1718 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1719 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1720 unsigned long sysenter_esp;
1721
a8eeb04a 1722 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1723 local_irq_disable();
8f536b76 1724 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1725
1726 /*
1727 * Read loaded_vmcs->cpu should be before fetching
1728 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1729 * See the comments in __loaded_vmcs_clear().
1730 */
1731 smp_rmb();
1732
d462b819
NHE		 1733 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1734 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1735 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1736 local_irq_enable();
1737
6aa8b732
AK		 1738 /*
1739 * Linux uses per-cpu TSS and GDT, so set these when switching
1740 * processors.
1741 */
d6e88aec 1742 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1743 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1744
1745 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1746 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1747 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1748 }
6aa8b732
AK		 1749}
1750
1751static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1752{
a9b21b62 1753 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1754 if (!vmm_exclusive) {
d462b819
NHE		 1755 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1756 vcpu->cpu = -1;
4610c9cc
DX		 1757 kvm_cpu_vmxoff();
1758 }
6aa8b732
AK		 1759}
1760
5fd86fcf
AK		 1761static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1762{
81231c69
AK		 1763 ulong cr0;
1764
5fd86fcf
AK		 1765 if (vcpu->fpu_active)
1766 return;
1767 vcpu->fpu_active = 1;
81231c69
AK		 1768 cr0 = vmcs_readl(GUEST_CR0);
1769 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1770 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1771 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1772 update_exception_bitmap(vcpu);
edcafe3c 1773 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1774 if (is_guest_mode(vcpu))
1775 vcpu->arch.cr0_guest_owned_bits &=
1776 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1777 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1778}
1779
edcafe3c
AK		 1780static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1781
fe3ef05c
NHE		 1782/*
1783 * Return the cr0 value that a nested guest would read. This is a combination
1784 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1785 * its hypervisor (cr0_read_shadow).
1786 */
1787static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1788{
1789 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1790 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1791}
1792static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1793{
1794 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1795 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1796}
1797
5fd86fcf
AK		 1798static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1799{
36cf24e0
NHE		 1800 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1801 * set this *before* calling this function.
1802 */
edcafe3c 1803 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1804 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1805 update_exception_bitmap(vcpu);
edcafe3c
AK		 1806 vcpu->arch.cr0_guest_owned_bits = 0;
1807 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1808 if (is_guest_mode(vcpu)) {
1809 /*
1810 * L1's specified read shadow might not contain the TS bit,
1811 * so now that we turned on shadowing of this bit, we need to
1812 * set this bit of the shadow. Like in nested_vmx_run we need
1813 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1814 * up-to-date here because we just decached cr0.TS (and we'll
1815 * only update vmcs12->guest_cr0 on nested exit).
1816 */
1817 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1818 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1819 (vcpu->arch.cr0 & X86_CR0_TS);
1820 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1821 } else
1822 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1823}
1824
6aa8b732
AK		 1825static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1826{
78ac8b47 1827 unsigned long rflags, save_rflags;
345dcaa8 1828
6de12732
AK		 1829 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1830 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1831 rflags = vmcs_readl(GUEST_RFLAGS);
1832 if (to_vmx(vcpu)->rmode.vm86_active) {
1833 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1834 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1835 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1836 }
1837 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1838 }
6de12732 1839 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1840}
1841
1842static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1843{
6de12732
AK		 1844 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1845 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1846 if (to_vmx(vcpu)->rmode.vm86_active) {
1847 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1848 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1849 }
6aa8b732
AK		 1850 vmcs_writel(GUEST_RFLAGS, rflags);
1851}
1852
2809f5d2
GC		 1853static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1854{
1855 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1856 int ret = 0;
1857
1858 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1859 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1860 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1861 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1862
1863 return ret & mask;
1864}
1865
1866static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1867{
1868 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1869 u32 interruptibility = interruptibility_old;
1870
1871 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1872
48005f64 1873 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1874 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1875 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1876 interruptibility |= GUEST_INTR_STATE_STI;
1877
1878 if ((interruptibility != interruptibility_old))
1879 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1880}
1881
6aa8b732
AK		 1882static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1883{
1884 unsigned long rip;
6aa8b732 1885
5fdbf976 1886 rip = kvm_rip_read(vcpu);
6aa8b732 1887 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1888 kvm_rip_write(vcpu, rip);
6aa8b732 1889
2809f5d2
GC		 1890 /* skipping an emulated instruction also counts */
1891 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1892}
1893
0b6ac343
NHE		 1894/*
1895 * KVM wants to inject page-faults which it got to the guest. This function
1896 * checks whether in a nested guest, we need to inject them to L1 or L2.
1897 * This function assumes it is called with the exit reason in vmcs02 being
1898 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1899 * is running).
1900 */
1901static int nested_pf_handled(struct kvm_vcpu *vcpu)
1902{
1903 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1904
1905 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1906 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1907 return 0;
1908
1909 nested_vmx_vmexit(vcpu);
1910 return 1;
1911}
1912
298101da 1913static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1914 bool has_error_code, u32 error_code,
1915 bool reinject)
298101da 1916{
77ab6db0 1917 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1918 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1919
0b6ac343 1920 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1921 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1922 return;
1923
8ab2d2e2 1924 if (has_error_code) {
77ab6db0 1925 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1926 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927 }
77ab6db0 1928
7ffd92c5 1929 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1930 int inc_eip = 0;
1931 if (kvm_exception_is_soft(nr))
1932 inc_eip = vcpu->arch.event_exit_inst_len;
1933 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1934 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1935 return;
1936 }
1937
66fd3f7f
GN		 1938 if (kvm_exception_is_soft(nr)) {
1939 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1941 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942 } else
1943 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1946}
1947
4e47c7a6
SY		 1948static bool vmx_rdtscp_supported(void)
1949{
1950 return cpu_has_vmx_rdtscp();
1951}
1952
ad756a16
MJ		 1953static bool vmx_invpcid_supported(void)
1954{
1955 return cpu_has_vmx_invpcid() && enable_ept;
1956}
1957
a75beee6
ED		 1958/*
1959 * Swap MSR entry in host/guest MSR entry array.
1960 */
8b9cf98c 1961static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1962{
26bb0981 1963 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1964
1965 tmp = vmx->guest_msrs[to];
1966 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1968}
1969
8d14695f
YZ		 1970static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971{
1972 unsigned long *msr_bitmap;
1973
1974 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975 if (is_long_mode(vcpu))
1976 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977 else
1978 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979 } else {
1980 if (is_long_mode(vcpu))
1981 msr_bitmap = vmx_msr_bitmap_longmode;
1982 else
1983 msr_bitmap = vmx_msr_bitmap_legacy;
1984 }
1985
1986 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987}
1988
e38aea3e
AK		 1989/*
1990 * Set up the vmcs to automatically save and restore system
1991 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1992 * mode, as fiddling with msrs is very expensive.
1993 */
8b9cf98c 1994static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1995{
26bb0981 1996 int save_nmsrs, index;
e38aea3e 1997
a75beee6
ED		 1998 save_nmsrs = 0;
1999#ifdef CONFIG_X86_64
8b9cf98c 2000 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2001 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2002 if (index >= 0)
8b9cf98c
RR		 2003 move_msr_up(vmx, index, save_nmsrs++);
2004 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2005 if (index >= 0)
8b9cf98c
RR		 2006 move_msr_up(vmx, index, save_nmsrs++);
2007 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2008 if (index >= 0)
8b9cf98c 2009 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2010 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011 if (index >= 0 && vmx->rdtscp_enabled)
2012 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2013 /*
8c06585d 2014 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2015 * if efer.sce is enabled.
2016 */
8c06585d 2017 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2018 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2019 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2020 }
2021#endif
92c0d900
AK		 2022 index = __find_msr_index(vmx, MSR_EFER);
2023 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2024 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2025
26bb0981 2026 vmx->save_nmsrs = save_nmsrs;
5897297b 2027
8d14695f
YZ		 2028 if (cpu_has_vmx_msr_bitmap())
2029 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2030}
2031
6aa8b732
AK		 2032/*
2033 * reads and returns guest's timestamp counter "register"
2034 * guest_tsc = host_tsc + tsc_offset -- 21.3
2035 */
2036static u64 guest_read_tsc(void)
2037{
2038 u64 host_tsc, tsc_offset;
2039
2040 rdtscll(host_tsc);
2041 tsc_offset = vmcs_read64(TSC_OFFSET);
2042 return host_tsc + tsc_offset;
2043}
2044
d5c1785d
NHE		 2045/*
2046 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047 * counter, even if a nested guest (L2) is currently running.
2048 */
886b470c 2049u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2050{
886b470c 2051 u64 tsc_offset;
d5c1785d 2052
d5c1785d
NHE		 2053 tsc_offset = is_guest_mode(vcpu) ?
2054 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055 vmcs_read64(TSC_OFFSET);
2056 return host_tsc + tsc_offset;
2057}
2058
4051b188 2059/*
cc578287
ZA		 2060 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2061 * software catchup for faster rates on slower CPUs.
4051b188 2062 */
cc578287 2063static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2064{
cc578287
ZA		 2065 if (!scale)
2066 return;
2067
2068 if (user_tsc_khz > tsc_khz) {
2069 vcpu->arch.tsc_catchup = 1;
2070 vcpu->arch.tsc_always_catchup = 1;
2071 } else
2072 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2073}
2074
ba904635
WA		 2075static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076{
2077 return vmcs_read64(TSC_OFFSET);
2078}
2079
6aa8b732 2080/*
99e3e30a 2081 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2082 */
99e3e30a 2083static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2084{
27fc51b2 2085 if (is_guest_mode(vcpu)) {
7991825b 2086 /*
27fc51b2
NHE		 2087 * We're here if L1 chose not to trap WRMSR to TSC. According
2088 * to the spec, this should set L1's TSC; The offset that L1
2089 * set for L2 remains unchanged, and still needs to be added
2090 * to the newly set TSC to get L2's TSC.
7991825b 2091 */
27fc51b2
NHE		 2092 struct vmcs12 *vmcs12;
2093 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094 /* recalculate vmcs02.TSC_OFFSET: */
2095 vmcs12 = get_vmcs12(vcpu);
2096 vmcs_write64(TSC_OFFSET, offset +
2097 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098 vmcs12->tsc_offset : 0));
2099 } else {
489223ed
YY		 2100 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2102 vmcs_write64(TSC_OFFSET, offset);
2103 }
6aa8b732
AK		 2104}
2105
f1e2b260 2106static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2107{
2108 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2109
e48672fa 2110 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2111 if (is_guest_mode(vcpu)) {
2112 /* Even when running L2, the adjustment needs to apply to L1 */
2113 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2114 } else
2115 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116 offset + adjustment);
e48672fa
ZA		 2117}
2118
857e4099
JR		 2119static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120{
2121 return target_tsc - native_read_tsc();
2122}
2123
801d3424
NHE		 2124static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125{
2126 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128}
2129
2130/*
2131 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133 * all guests if the "nested" module option is off, and can also be disabled
2134 * for a single guest by disabling its VMX cpuid bit.
2135 */
2136static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137{
2138 return nested && guest_cpuid_has_vmx(vcpu);
2139}
2140
b87a51ae
NHE		 2141/*
2142 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143 * returned for the various VMX controls MSRs when nested VMX is enabled.
2144 * The same values should also be used to verify that vmcs12 control fields are
2145 * valid during nested entry from L1 to L2.
2146 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148 * bit in the high half is on if the corresponding bit in the control field
2149 * may be on. See also vmx_control_verify().
2150 * TODO: allow these variables to be modified (downgraded) by module options
2151 * or other means.
2152 */
2153static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2158static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2159static __init void nested_vmx_setup_ctls_msrs(void)
2160{
2161 /*
2162 * Note that as a general rule, the high half of the MSRs (bits in
2163 * the control fields which may be 1) should be initialized by the
2164 * intersection of the underlying hardware's MSR (i.e., features which
2165 * can be supported) and the list of features we want to expose -
2166 * because they are known to be properly supported in our code.
2167 * Also, usually, the low half of the MSRs (bits which must be 1) can
2168 * be set to 0, meaning that L1 may turn off any of these bits. The
2169 * reason is that if one of these bits is necessary, it will appear
2170 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2171 * fields of vmcs01 and vmcs02, will turn these bits off - and
2172 * nested_vmx_exit_handled() will not pass related exits to L1.
2173 * These rules have exceptions below.
2174 */
2175
2176 /* pin-based controls */
eabeaacc
JK		 2177 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2178 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2179 /*
2180 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2181 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2182 */
eabeaacc
JK		 2183 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2184 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2185 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2186 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2187 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2188
33fb20c3
JK		 2189 /*
2190 * Exit controls
2191 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2192 * 17 must be 1.
2193 */
2194 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2195 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2196#ifdef CONFIG_X86_64
2197 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2198#else
2199 nested_vmx_exit_ctls_high = 0;
2200#endif
8049d651
NHE		 2201 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2202 VM_EXIT_LOAD_IA32_EFER);
b87a51ae
NHE		 2203
2204 /* entry controls */
2205 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2206 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2207 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2208 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2209 nested_vmx_entry_ctls_high &=
2210 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
8049d651
NHE		 2211 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2212 VM_ENTRY_LOAD_IA32_EFER);
b87a51ae
NHE		 2213 /* cpu-based controls */
2214 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2215 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2216 nested_vmx_procbased_ctls_low = 0;
2217 nested_vmx_procbased_ctls_high &=
2218 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2219 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2220 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2221 CPU_BASED_CR3_STORE_EXITING |
2222#ifdef CONFIG_X86_64
2223 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2224#endif
2225 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2226 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2227 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2228 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2229 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2230 /*
2231 * We can allow some features even when not supported by the
2232 * hardware. For example, L1 can specify an MSR bitmap - and we
2233 * can use it to avoid exits to L1 - even when L0 runs L2
2234 * without MSR bitmaps.
2235 */
2236 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2237
2238 /* secondary cpu-based controls */
2239 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2240 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2241 nested_vmx_secondary_ctls_low = 0;
2242 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2243 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2244 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2245
2246 /* miscellaneous data */
2247 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2248 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2249 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2250 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2251}
2252
2253static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2254{
2255 /*
2256 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2257 */
2258 return ((control & high) | low) == control;
2259}
2260
2261static inline u64 vmx_control_msr(u32 low, u32 high)
2262{
2263 return low | ((u64)high << 32);
2264}
2265
2266/*
2267 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2268 * also let it use VMX-specific MSRs.
2269 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2270 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2271 * like all other MSRs).
2272 */
2273static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2274{
2275 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2276 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2277 /*
2278 * According to the spec, processors which do not support VMX
2279 * should throw a #GP(0) when VMX capability MSRs are read.
2280 */
2281 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2282 return 1;
2283 }
2284
2285 switch (msr_index) {
2286 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2287 if (nested_vmx_allowed(vcpu)) {
2288 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2289 break;
2290 }
2291 return 0;
b87a51ae
NHE		 2292 case MSR_IA32_VMX_BASIC:
2293 /*
2294 * This MSR reports some information about VMX support. We
2295 * should return information about the VMX we emulate for the
2296 * guest, and the VMCS structure we give it - not about the
2297 * VMX support of the underlying hardware.
2298 */
2299 *pdata = VMCS12_REVISION |
2300 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2301 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2302 break;
2303 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2304 case MSR_IA32_VMX_PINBASED_CTLS:
2305 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2306 nested_vmx_pinbased_ctls_high);
2307 break;
2308 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2309 case MSR_IA32_VMX_PROCBASED_CTLS:
2310 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2311 nested_vmx_procbased_ctls_high);
2312 break;
2313 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2314 case MSR_IA32_VMX_EXIT_CTLS:
2315 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2316 nested_vmx_exit_ctls_high);
2317 break;
2318 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2319 case MSR_IA32_VMX_ENTRY_CTLS:
2320 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2321 nested_vmx_entry_ctls_high);
2322 break;
2323 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2324 *pdata = vmx_control_msr(nested_vmx_misc_low,
2325 nested_vmx_misc_high);
b87a51ae
NHE		 2326 break;
2327 /*
2328 * These MSRs specify bits which the guest must keep fixed (on or off)
2329 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2330 * We picked the standard core2 setting.
2331 */
2332#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2333#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2334 case MSR_IA32_VMX_CR0_FIXED0:
2335 *pdata = VMXON_CR0_ALWAYSON;
2336 break;
2337 case MSR_IA32_VMX_CR0_FIXED1:
2338 *pdata = -1ULL;
2339 break;
2340 case MSR_IA32_VMX_CR4_FIXED0:
2341 *pdata = VMXON_CR4_ALWAYSON;
2342 break;
2343 case MSR_IA32_VMX_CR4_FIXED1:
2344 *pdata = -1ULL;
2345 break;
2346 case MSR_IA32_VMX_VMCS_ENUM:
2347 *pdata = 0x1f;
2348 break;
2349 case MSR_IA32_VMX_PROCBASED_CTLS2:
2350 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2351 nested_vmx_secondary_ctls_high);
2352 break;
2353 case MSR_IA32_VMX_EPT_VPID_CAP:
2354 /* Currently, no nested ept or nested vpid */
2355 *pdata = 0;
2356 break;
2357 default:
2358 return 0;
2359 }
2360
2361 return 1;
2362}
2363
b3897a49 2364static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2365{
b3897a49
NHE		 2366 u32 msr_index = msr_info->index;
2367 u64 data = msr_info->data;
2368 bool host_initialized = msr_info->host_initiated;
2369
b87a51ae
NHE		 2370 if (!nested_vmx_allowed(vcpu))
2371 return 0;
2372
b3897a49
NHE		 2373 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2374 if (!host_initialized &&
2375 to_vmx(vcpu)->nested.msr_ia32_feature_control
2376 & FEATURE_CONTROL_LOCKED)
2377 return 0;
2378 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2379 return 1;
b3897a49
NHE		 2380 }
2381
b87a51ae
NHE		 2382 /*
2383 * No need to treat VMX capability MSRs specially: If we don't handle
2384 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2385 */
2386 return 0;
2387}
2388
6aa8b732
AK		 2389/*
2390 * Reads an msr value (of 'msr_index') into 'pdata'.
2391 * Returns 0 on success, non-0 otherwise.
2392 * Assumes vcpu_load() was already called.
2393 */
2394static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2395{
2396 u64 data;
26bb0981 2397 struct shared_msr_entry *msr;
6aa8b732
AK		 2398
2399 if (!pdata) {
2400 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2401 return -EINVAL;
2402 }
2403
2404 switch (msr_index) {
05b3e0c2 2405#ifdef CONFIG_X86_64
6aa8b732
AK		 2406 case MSR_FS_BASE:
2407 data = vmcs_readl(GUEST_FS_BASE);
2408 break;
2409 case MSR_GS_BASE:
2410 data = vmcs_readl(GUEST_GS_BASE);
2411 break;
44ea2b17
AK		 2412 case MSR_KERNEL_GS_BASE:
2413 vmx_load_host_state(to_vmx(vcpu));
2414 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2415 break;
26bb0981 2416#endif
6aa8b732 2417 case MSR_EFER:
3bab1f5d 2418 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2419 case MSR_IA32_TSC:
6aa8b732
AK		 2420 data = guest_read_tsc();
2421 break;
2422 case MSR_IA32_SYSENTER_CS:
2423 data = vmcs_read32(GUEST_SYSENTER_CS);
2424 break;
2425 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2426 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2427 break;
2428 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2429 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2430 break;
4e47c7a6
SY		 2431 case MSR_TSC_AUX:
2432 if (!to_vmx(vcpu)->rdtscp_enabled)
2433 return 1;
2434 /* Otherwise falls through */
6aa8b732 2435 default:
b87a51ae
NHE		 2436 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2437 return 0;
8b9cf98c 2438 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2439 if (msr) {
2440 data = msr->data;
2441 break;
6aa8b732 2442 }
3bab1f5d 2443 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2444 }
2445
2446 *pdata = data;
2447 return 0;
2448}
2449
2450/*
2451 * Writes msr value into into the appropriate "register".
2452 * Returns 0 on success, non-0 otherwise.
2453 * Assumes vcpu_load() was already called.
2454 */
8fe8ab46 2455static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2456{
a2fa3e9f 2457 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2458 struct shared_msr_entry *msr;
2cc51560 2459 int ret = 0;
8fe8ab46
WA		 2460 u32 msr_index = msr_info->index;
2461 u64 data = msr_info->data;
2cc51560 2462
6aa8b732 2463 switch (msr_index) {
3bab1f5d 2464 case MSR_EFER:
8fe8ab46 2465 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2466 break;
16175a79 2467#ifdef CONFIG_X86_64
6aa8b732 2468 case MSR_FS_BASE:
2fb92db1 2469 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2470 vmcs_writel(GUEST_FS_BASE, data);
2471 break;
2472 case MSR_GS_BASE:
2fb92db1 2473 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2474 vmcs_writel(GUEST_GS_BASE, data);
2475 break;
44ea2b17
AK		 2476 case MSR_KERNEL_GS_BASE:
2477 vmx_load_host_state(vmx);
2478 vmx->msr_guest_kernel_gs_base = data;
2479 break;
6aa8b732
AK		 2480#endif
2481 case MSR_IA32_SYSENTER_CS:
2482 vmcs_write32(GUEST_SYSENTER_CS, data);
2483 break;
2484 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2485 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2486 break;
2487 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2488 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2489 break;
af24a4e4 2490 case MSR_IA32_TSC:
8fe8ab46 2491 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2492 break;
468d472f
SY		 2493 case MSR_IA32_CR_PAT:
2494 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2495 vmcs_write64(GUEST_IA32_PAT, data);
2496 vcpu->arch.pat = data;
2497 break;
2498 }
8fe8ab46 2499 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2500 break;
ba904635
WA		 2501 case MSR_IA32_TSC_ADJUST:
2502 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2503 break;
2504 case MSR_TSC_AUX:
2505 if (!vmx->rdtscp_enabled)
2506 return 1;
2507 /* Check reserved bit, higher 32 bits should be zero */
2508 if ((data >> 32) != 0)
2509 return 1;
2510 /* Otherwise falls through */
6aa8b732 2511 default:
b3897a49 2512 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2513 break;
8b9cf98c 2514 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2515 if (msr) {
2516 msr->data = data;
2225fd56
AK		 2517 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2518 preempt_disable();
9ee73970
AK		 2519 kvm_set_shared_msr(msr->index, msr->data,
2520 msr->mask);
2225fd56
AK		 2521 preempt_enable();
2522 }
3bab1f5d 2523 break;
6aa8b732 2524 }
8fe8ab46 2525 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2526 }
2527
2cc51560 2528 return ret;
6aa8b732
AK		 2529}
2530
5fdbf976 2531static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2532{
5fdbf976
MT		 2533 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2534 switch (reg) {
2535 case VCPU_REGS_RSP:
2536 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2537 break;
2538 case VCPU_REGS_RIP:
2539 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2540 break;
6de4f3ad
AK		 2541 case VCPU_EXREG_PDPTR:
2542 if (enable_ept)
2543 ept_save_pdptrs(vcpu);
2544 break;
5fdbf976
MT		 2545 default:
2546 break;
2547 }
6aa8b732
AK		 2548}
2549
6aa8b732
AK		 2550static __init int cpu_has_kvm_support(void)
2551{
6210e37b 2552 return cpu_has_vmx();
6aa8b732
AK		 2553}
2554
2555static __init int vmx_disabled_by_bios(void)
2556{
2557 u64 msr;
2558
2559 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2560 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2561 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2562 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2563 && tboot_enabled())
2564 return 1;
23f3e991 2565 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2566 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2567 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2568 && !tboot_enabled()) {
2569 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2570 "activate TXT before enabling KVM\n");
cafd6659 2571 return 1;
f9335afe 2572 }
23f3e991
JC		 2573 /* launched w/o TXT and VMX disabled */
2574 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2575 && !tboot_enabled())
2576 return 1;
cafd6659
SW		 2577 }
2578
2579 return 0;
6aa8b732
AK		 2580}
2581
7725b894
DX		 2582static void kvm_cpu_vmxon(u64 addr)
2583{
2584 asm volatile (ASM_VMX_VMXON_RAX
2585 : : "a"(&addr), "m"(addr)
2586 : "memory", "cc");
2587}
2588
10474ae8 2589static int hardware_enable(void *garbage)
6aa8b732
AK		 2590{
2591 int cpu = raw_smp_processor_id();
2592 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2593 u64 old, test_bits;
6aa8b732 2594
10474ae8
AG		 2595 if (read_cr4() & X86_CR4_VMXE)
2596 return -EBUSY;
2597
d462b819 2598 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2599
2600 /*
2601 * Now we can enable the vmclear operation in kdump
2602 * since the loaded_vmcss_on_cpu list on this cpu
2603 * has been initialized.
2604 *
2605 * Though the cpu is not in VMX operation now, there
2606 * is no problem to enable the vmclear operation
2607 * for the loaded_vmcss_on_cpu list is empty!
2608 */
2609 crash_enable_local_vmclear(cpu);
2610
6aa8b732 2611 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2612
2613 test_bits = FEATURE_CONTROL_LOCKED;
2614 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2615 if (tboot_enabled())
2616 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2617
2618 if ((old & test_bits) != test_bits) {
6aa8b732 2619 /* enable and lock */
cafd6659
SW		 2620 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2621 }
66aee91a 2622 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2623
4610c9cc
DX		 2624 if (vmm_exclusive) {
2625 kvm_cpu_vmxon(phys_addr);
2626 ept_sync_global();
2627 }
10474ae8 2628
357d1226 2629 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2630
10474ae8 2631 return 0;
6aa8b732
AK		 2632}
2633
d462b819 2634static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2635{
2636 int cpu = raw_smp_processor_id();
d462b819 2637 struct loaded_vmcs *v, *n;
543e4243 2638
d462b819
NHE		 2639 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2640 loaded_vmcss_on_cpu_link)
2641 __loaded_vmcs_clear(v);
543e4243
AK		 2642}
2643
710ff4a8
EH		 2644
2645/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2646 * tricks.
2647 */
2648static void kvm_cpu_vmxoff(void)
6aa8b732 2649{
4ecac3fd 2650 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2651}
2652
710ff4a8
EH		 2653static void hardware_disable(void *garbage)
2654{
4610c9cc 2655 if (vmm_exclusive) {
d462b819 2656 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2657 kvm_cpu_vmxoff();
2658 }
7725b894 2659 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2660}
2661
1c3d14fe 2662static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2663 u32 msr, u32 *result)
1c3d14fe
YS		 2664{
2665 u32 vmx_msr_low, vmx_msr_high;
2666 u32 ctl = ctl_min | ctl_opt;
2667
2668 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2669
2670 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2671 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2672
2673 /* Ensure minimum (required) set of control bits are supported. */
2674 if (ctl_min & ~ctl)
002c7f7c 2675 return -EIO;
1c3d14fe
YS		 2676
2677 *result = ctl;
2678 return 0;
2679}
2680
110312c8
AK		 2681static __init bool allow_1_setting(u32 msr, u32 ctl)
2682{
2683 u32 vmx_msr_low, vmx_msr_high;
2684
2685 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2686 return vmx_msr_high & ctl;
2687}
2688
002c7f7c 2689static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2690{
2691 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2692 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2693 u32 _pin_based_exec_control = 0;
2694 u32 _cpu_based_exec_control = 0;
f78e0e2e 2695 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2696 u32 _vmexit_control = 0;
2697 u32 _vmentry_control = 0;
2698
10166744 2699 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2700#ifdef CONFIG_X86_64
2701 CPU_BASED_CR8_LOAD_EXITING |
2702 CPU_BASED_CR8_STORE_EXITING |
2703#endif
d56f546d
SY		 2704 CPU_BASED_CR3_LOAD_EXITING |
2705 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2706 CPU_BASED_USE_IO_BITMAPS |
2707 CPU_BASED_MOV_DR_EXITING |
a7052897 2708 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2709 CPU_BASED_MWAIT_EXITING |
2710 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2711 CPU_BASED_INVLPG_EXITING |
2712 CPU_BASED_RDPMC_EXITING;
443381a8 2713
f78e0e2e 2714 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2715 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2716 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2717 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2718 &_cpu_based_exec_control) < 0)
002c7f7c 2719 return -EIO;
6e5d865c
YS		 2720#ifdef CONFIG_X86_64
2721 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2722 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2723 ~CPU_BASED_CR8_STORE_EXITING;
2724#endif
f78e0e2e 2725 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2726 min2 = 0;
2727 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2728 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2729 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2730 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2731 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2732 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2733 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2734 SECONDARY_EXEC_RDTSCP |
83d4c286 2735 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2736 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2737 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2738 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2739 if (adjust_vmx_controls(min2, opt2,
2740 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2741 &_cpu_based_2nd_exec_control) < 0)
2742 return -EIO;
2743 }
2744#ifndef CONFIG_X86_64
2745 if (!(_cpu_based_2nd_exec_control &
2746 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2747 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2748#endif
83d4c286
YZ		 2749
2750 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2751 _cpu_based_2nd_exec_control &= ~(
8d14695f 2752 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2753 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2754 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2755
d56f546d 2756 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2757 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2758 enabled */
5fff7d27
GN		 2759 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2760 CPU_BASED_CR3_STORE_EXITING |
2761 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2762 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2763 vmx_capability.ept, vmx_capability.vpid);
2764 }
1c3d14fe
YS		 2765
2766 min = 0;
2767#ifdef CONFIG_X86_64
2768 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2769#endif
a547c6db
YZ		 2770 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2771 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2772 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2773 &_vmexit_control) < 0)
002c7f7c 2774 return -EIO;
1c3d14fe 2775
01e439be
YZ		 2776 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2777 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2778 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2779 &_pin_based_exec_control) < 0)
2780 return -EIO;
2781
2782 if (!(_cpu_based_2nd_exec_control &
2783 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2784 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2785 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2786
468d472f
SY		 2787 min = 0;
2788 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2789 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2790 &_vmentry_control) < 0)
002c7f7c 2791 return -EIO;
6aa8b732 2792
c68876fd 2793 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2794
2795 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2796 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2797 return -EIO;
1c3d14fe
YS		 2798
2799#ifdef CONFIG_X86_64
2800 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2801 if (vmx_msr_high & (1u<<16))
002c7f7c 2802 return -EIO;
1c3d14fe
YS		 2803#endif
2804
2805 /* Require Write-Back (WB) memory type for VMCS accesses. */
2806 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2807 return -EIO;
1c3d14fe 2808
002c7f7c
YS		 2809 vmcs_conf->size = vmx_msr_high & 0x1fff;
2810 vmcs_conf->order = get_order(vmcs_config.size);
2811 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2812
002c7f7c
YS		 2813 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2814 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2815 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2816 vmcs_conf->vmexit_ctrl = _vmexit_control;
2817 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2818
110312c8
AK		 2819 cpu_has_load_ia32_efer =
2820 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2821 VM_ENTRY_LOAD_IA32_EFER)
2822 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2823 VM_EXIT_LOAD_IA32_EFER);
2824
8bf00a52
GN		 2825 cpu_has_load_perf_global_ctrl =
2826 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2827 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2828 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2829 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2830
2831 /*
2832 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2833 * but due to arrata below it can't be used. Workaround is to use
2834 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2835 *
2836 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2837 *
2838 * AAK155 (model 26)
2839 * AAP115 (model 30)
2840 * AAT100 (model 37)
2841 * BC86,AAY89,BD102 (model 44)
2842 * BA97 (model 46)
2843 *
2844 */
2845 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2846 switch (boot_cpu_data.x86_model) {
2847 case 26:
2848 case 30:
2849 case 37:
2850 case 44:
2851 case 46:
2852 cpu_has_load_perf_global_ctrl = false;
2853 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2854 "does not work properly. Using workaround\n");
2855 break;
2856 default:
2857 break;
2858 }
2859 }
2860
1c3d14fe 2861 return 0;
c68876fd 2862}
6aa8b732
AK		 2863
2864static struct vmcs *alloc_vmcs_cpu(int cpu)
2865{
2866 int node = cpu_to_node(cpu);
2867 struct page *pages;
2868 struct vmcs *vmcs;
2869
6484eb3e 2870 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2871 if (!pages)
2872 return NULL;
2873 vmcs = page_address(pages);
1c3d14fe
YS		 2874 memset(vmcs, 0, vmcs_config.size);
2875 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2876 return vmcs;
2877}
2878
2879static struct vmcs *alloc_vmcs(void)
2880{
d3b2c338 2881 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2882}
2883
2884static void free_vmcs(struct vmcs *vmcs)
2885{
1c3d14fe 2886 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2887}
2888
d462b819
NHE		 2889/*
2890 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2891 */
2892static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2893{
2894 if (!loaded_vmcs->vmcs)
2895 return;
2896 loaded_vmcs_clear(loaded_vmcs);
2897 free_vmcs(loaded_vmcs->vmcs);
2898 loaded_vmcs->vmcs = NULL;
2899}
2900
39959588 2901static void free_kvm_area(void)
6aa8b732
AK		 2902{
2903 int cpu;
2904
3230bb47 2905 for_each_possible_cpu(cpu) {
6aa8b732 2906 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2907 per_cpu(vmxarea, cpu) = NULL;
2908 }
6aa8b732
AK		 2909}
2910
6aa8b732
AK		 2911static __init int alloc_kvm_area(void)
2912{
2913 int cpu;
2914
3230bb47 2915 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2916 struct vmcs *vmcs;
2917
2918 vmcs = alloc_vmcs_cpu(cpu);
2919 if (!vmcs) {
2920 free_kvm_area();
2921 return -ENOMEM;
2922 }
2923
2924 per_cpu(vmxarea, cpu) = vmcs;
2925 }
2926 return 0;
2927}
2928
2929static __init int hardware_setup(void)
2930{
002c7f7c
YS		 2931 if (setup_vmcs_config(&vmcs_config) < 0)
2932 return -EIO;
50a37eb4
JR		 2933
2934 if (boot_cpu_has(X86_FEATURE_NX))
2935 kvm_enable_efer_bits(EFER_NX);
2936
93ba03c2
SY		 2937 if (!cpu_has_vmx_vpid())
2938 enable_vpid = 0;
abc4fc58
AG		 2939 if (!cpu_has_vmx_shadow_vmcs())
2940 enable_shadow_vmcs = 0;
93ba03c2 2941
4bc9b982
SY		 2942 if (!cpu_has_vmx_ept() ||
2943 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2944 enable_ept = 0;
3a624e29 2945 enable_unrestricted_guest = 0;
83c3a331 2946 enable_ept_ad_bits = 0;
3a624e29
NK		 2947 }
2948
83c3a331
XH		 2949 if (!cpu_has_vmx_ept_ad_bits())
2950 enable_ept_ad_bits = 0;
2951
3a624e29
NK		 2952 if (!cpu_has_vmx_unrestricted_guest())
2953 enable_unrestricted_guest = 0;
93ba03c2
SY		 2954
2955 if (!cpu_has_vmx_flexpriority())
2956 flexpriority_enabled = 0;
2957
95ba8273
GN		 2958 if (!cpu_has_vmx_tpr_shadow())
2959 kvm_x86_ops->update_cr8_intercept = NULL;
2960
54dee993
MT		 2961 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2962 kvm_disable_largepages();
2963
4b8d54f9
ZE		 2964 if (!cpu_has_vmx_ple())
2965 ple_gap = 0;
2966
01e439be
YZ		 2967 if (!cpu_has_vmx_apicv())
2968 enable_apicv = 0;
c7c9c56c 2969
01e439be 2970 if (enable_apicv)
c7c9c56c 2971 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2972 else {
c7c9c56c 2973 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2974 kvm_x86_ops->deliver_posted_interrupt = NULL;
2975 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2976 }
83d4c286 2977
b87a51ae
NHE		 2978 if (nested)
2979 nested_vmx_setup_ctls_msrs();
2980
6aa8b732
AK		 2981 return alloc_kvm_area();
2982}
2983
2984static __exit void hardware_unsetup(void)
2985{
2986 free_kvm_area();
2987}
2988
14168786
GN		 2989static bool emulation_required(struct kvm_vcpu *vcpu)
2990{
2991 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2992}
2993
91b0aa2c 2994static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2995 struct kvm_segment *save)
6aa8b732 2996{
d99e4152
GN		 2997 if (!emulate_invalid_guest_state) {
2998 /*
2999 * CS and SS RPL should be equal during guest entry according
3000 * to VMX spec, but in reality it is not always so. Since vcpu
3001 * is in the middle of the transition from real mode to
3002 * protected mode it is safe to assume that RPL 0 is a good
3003 * default value.
3004 */
3005 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3006 save->selector &= ~SELECTOR_RPL_MASK;
3007 save->dpl = save->selector & SELECTOR_RPL_MASK;
3008 save->s = 1;
6aa8b732 3009 }
d99e4152 3010 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3011}
3012
3013static void enter_pmode(struct kvm_vcpu *vcpu)
3014{
3015 unsigned long flags;
a89a8fb9 3016 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3017
d99e4152
GN		 3018 /*
3019 * Update real mode segment cache. It may be not up-to-date if sement
3020 * register was written while vcpu was in a guest mode.
3021 */
3022 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3023 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3024 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3025 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3026 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3027 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3028
7ffd92c5 3029 vmx->rmode.vm86_active = 0;
6aa8b732 3030
2fb92db1
AK		 3031 vmx_segment_cache_clear(vmx);
3032
f5f7b2fe 3033 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3034
3035 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3036 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3037 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3038 vmcs_writel(GUEST_RFLAGS, flags);
3039
66aee91a
RR		 3040 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3041 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3042
3043 update_exception_bitmap(vcpu);
3044
91b0aa2c
GN		 3045 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3046 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3047 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3048 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3049 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3050 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3051
3052 /* CPL is always 0 when CPU enters protected mode */
3053 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3054 vmx->cpl = 0;
6aa8b732
AK		 3055}
3056
f5f7b2fe 3057static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3058{
772e0318 3059 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3060 struct kvm_segment var = *save;
3061
3062 var.dpl = 0x3;
3063 if (seg == VCPU_SREG_CS)
3064 var.type = 0x3;
3065
3066 if (!emulate_invalid_guest_state) {
3067 var.selector = var.base >> 4;
3068 var.base = var.base & 0xffff0;
3069 var.limit = 0xffff;
3070 var.g = 0;
3071 var.db = 0;
3072 var.present = 1;
3073 var.s = 1;
3074 var.l = 0;
3075 var.unusable = 0;
3076 var.type = 0x3;
3077 var.avl = 0;
3078 if (save->base & 0xf)
3079 printk_once(KERN_WARNING "kvm: segment base is not "
3080 "paragraph aligned when entering "
3081 "protected mode (seg=%d)", seg);
3082 }
6aa8b732 3083
d99e4152
GN		 3084 vmcs_write16(sf->selector, var.selector);
3085 vmcs_write32(sf->base, var.base);
3086 vmcs_write32(sf->limit, var.limit);
3087 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3088}
3089
3090static void enter_rmode(struct kvm_vcpu *vcpu)
3091{
3092 unsigned long flags;
a89a8fb9 3093 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3094
f5f7b2fe
AK		 3095 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3096 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3097 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3098 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3099 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3100 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3101 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3102
7ffd92c5 3103 vmx->rmode.vm86_active = 1;
6aa8b732 3104
776e58ea
GN		 3105 /*
3106 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3107 * vcpu. Warn the user that an update is overdue.
776e58ea 3108 */
4918c6ca 3109 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3110 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3111 "called before entering vcpu\n");
776e58ea 3112
2fb92db1
AK		 3113 vmx_segment_cache_clear(vmx);
3114
4918c6ca 3115 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3116 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3117 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3118
3119 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3120 vmx->rmode.save_rflags = flags;
6aa8b732 3121
053de044 3122 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3123
3124 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3125 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3126 update_exception_bitmap(vcpu);
3127
d99e4152
GN		 3128 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3129 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3130 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3131 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3132 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3133 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3134
8668a3c4 3135 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3136}
3137
401d10de
AS		 3138static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3139{
3140 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3141 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3142
3143 if (!msr)
3144 return;
401d10de 3145
44ea2b17
AK		 3146 /*
3147 * Force kernel_gs_base reloading before EFER changes, as control
3148 * of this msr depends on is_long_mode().
3149 */
3150 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3151 vcpu->arch.efer = efer;
401d10de
AS		 3152 if (efer & EFER_LMA) {
3153 vmcs_write32(VM_ENTRY_CONTROLS,
3154 vmcs_read32(VM_ENTRY_CONTROLS) |
3155 VM_ENTRY_IA32E_MODE);
3156 msr->data = efer;
3157 } else {
3158 vmcs_write32(VM_ENTRY_CONTROLS,
3159 vmcs_read32(VM_ENTRY_CONTROLS) &
3160 ~VM_ENTRY_IA32E_MODE);
3161
3162 msr->data = efer & ~EFER_LME;
3163 }
3164 setup_msrs(vmx);
3165}
3166
05b3e0c2 3167#ifdef CONFIG_X86_64
6aa8b732
AK		 3168
3169static void enter_lmode(struct kvm_vcpu *vcpu)
3170{
3171 u32 guest_tr_ar;
3172
2fb92db1
AK		 3173 vmx_segment_cache_clear(to_vmx(vcpu));
3174
6aa8b732
AK		 3175 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3176 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3177 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3178 __func__);
6aa8b732
AK		 3179 vmcs_write32(GUEST_TR_AR_BYTES,
3180 (guest_tr_ar & ~AR_TYPE_MASK)
3181 | AR_TYPE_BUSY_64_TSS);
3182 }
da38f438 3183 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3184}
3185
3186static void exit_lmode(struct kvm_vcpu *vcpu)
3187{
6aa8b732
AK		 3188 vmcs_write32(VM_ENTRY_CONTROLS,
3189 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3190 & ~VM_ENTRY_IA32E_MODE);
da38f438 3191 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3192}
3193
3194#endif
3195
2384d2b3
SY		 3196static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3197{
b9d762fa 3198 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3199 if (enable_ept) {
3200 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3201 return;
4e1096d2 3202 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3203 }
2384d2b3
SY		 3204}
3205
e8467fda
AK		 3206static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3207{
3208 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3209
3210 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3211 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3212}
3213
aff48baa
AK		 3214static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3215{
3216 if (enable_ept && is_paging(vcpu))
3217 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3218 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3219}
3220
25c4c276 3221static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3222{
fc78f519
AK		 3223 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3224
3225 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3226 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3227}
3228
1439442c
SY		 3229static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3230{
6de4f3ad
AK		 3231 if (!test_bit(VCPU_EXREG_PDPTR,
3232 (unsigned long *)&vcpu->arch.regs_dirty))
3233 return;
3234
1439442c 3235 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3236 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3237 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3238 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3239 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3240 }
3241}
3242
8f5d549f
AK		 3243static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3244{
3245 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3246 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3247 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3248 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3249 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3250 }
6de4f3ad
AK		 3251
3252 __set_bit(VCPU_EXREG_PDPTR,
3253 (unsigned long *)&vcpu->arch.regs_avail);
3254 __set_bit(VCPU_EXREG_PDPTR,
3255 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3256}
3257
5e1746d6 3258static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3259
3260static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3261 unsigned long cr0,
3262 struct kvm_vcpu *vcpu)
3263{
5233dd51
MT		 3264 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3265 vmx_decache_cr3(vcpu);
1439442c
SY		 3266 if (!(cr0 & X86_CR0_PG)) {
3267 /* From paging/starting to nonpaging */
3268 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3269 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3270 (CPU_BASED_CR3_LOAD_EXITING |
3271 CPU_BASED_CR3_STORE_EXITING));
3272 vcpu->arch.cr0 = cr0;
fc78f519 3273 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3274 } else if (!is_paging(vcpu)) {
3275 /* From nonpaging to paging */
3276 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3277 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3278 ~(CPU_BASED_CR3_LOAD_EXITING |
3279 CPU_BASED_CR3_STORE_EXITING));
3280 vcpu->arch.cr0 = cr0;
fc78f519 3281 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3282 }
95eb84a7
SY		 3283
3284 if (!(cr0 & X86_CR0_WP))
3285 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3286}
3287
6aa8b732
AK		 3288static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3289{
7ffd92c5 3290 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3291 unsigned long hw_cr0;
3292
5037878e 3293 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3294 if (enable_unrestricted_guest)
5037878e 3295 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3296 else {
5037878e 3297 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3298
218e763f
GN		 3299 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3300 enter_pmode(vcpu);
6aa8b732 3301
218e763f
GN		 3302 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3303 enter_rmode(vcpu);
3304 }
6aa8b732 3305
05b3e0c2 3306#ifdef CONFIG_X86_64
f6801dff 3307 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3308 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3309 enter_lmode(vcpu);
707d92fa 3310 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3311 exit_lmode(vcpu);
3312 }
3313#endif
3314
089d034e 3315 if (enable_ept)
1439442c
SY		 3316 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3317
02daab21 3318 if (!vcpu->fpu_active)
81231c69 3319 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3320
6aa8b732 3321 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3322 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3323 vcpu->arch.cr0 = cr0;
14168786
GN		 3324
3325 /* depends on vcpu->arch.cr0 to be set to a new value */
3326 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3327}
3328
1439442c
SY		 3329static u64 construct_eptp(unsigned long root_hpa)
3330{
3331 u64 eptp;
3332
3333 /* TODO write the value reading from MSR */
3334 eptp = VMX_EPT_DEFAULT_MT |
3335 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3336 if (enable_ept_ad_bits)
3337 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3338 eptp |= (root_hpa & PAGE_MASK);
3339
3340 return eptp;
3341}
3342
6aa8b732
AK		 3343static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3344{
1439442c
SY		 3345 unsigned long guest_cr3;
3346 u64 eptp;
3347
3348 guest_cr3 = cr3;
089d034e 3349 if (enable_ept) {
1439442c
SY		 3350 eptp = construct_eptp(cr3);
3351 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3352 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3353 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3354 ept_load_pdptrs(vcpu);
1439442c
SY		 3355 }
3356
2384d2b3 3357 vmx_flush_tlb(vcpu);
1439442c 3358 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3359}
3360
5e1746d6 3361static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3362{
7ffd92c5 3363 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3364 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3365
5e1746d6
NHE		 3366 if (cr4 & X86_CR4_VMXE) {
3367 /*
3368 * To use VMXON (and later other VMX instructions), a guest
3369 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3370 * So basically the check on whether to allow nested VMX
3371 * is here.
3372 */
3373 if (!nested_vmx_allowed(vcpu))
3374 return 1;
1a0d74e6
JK		 3375 }
3376 if (to_vmx(vcpu)->nested.vmxon &&
3377 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3378 return 1;
3379
ad312c7c 3380 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3381 if (enable_ept) {
3382 if (!is_paging(vcpu)) {
3383 hw_cr4 &= ~X86_CR4_PAE;
3384 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3385 /*
3386 * SMEP is disabled if CPU is in non-paging mode in
3387 * hardware. However KVM always uses paging mode to
3388 * emulate guest non-paging mode with TDP.
3389 * To emulate this behavior, SMEP needs to be manually
3390 * disabled when guest switches to non-paging mode.
3391 */
3392 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3393 } else if (!(cr4 & X86_CR4_PAE)) {
3394 hw_cr4 &= ~X86_CR4_PAE;
3395 }
3396 }
1439442c
SY		 3397
3398 vmcs_writel(CR4_READ_SHADOW, cr4);
3399 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3400 return 0;
6aa8b732
AK		 3401}
3402
6aa8b732
AK		 3403static void vmx_get_segment(struct kvm_vcpu *vcpu,
3404 struct kvm_segment *var, int seg)
3405{
a9179499 3406 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3407 u32 ar;
3408
c6ad1153 3409 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3410 *var = vmx->rmode.segs[seg];
a9179499 3411 if (seg == VCPU_SREG_TR
2fb92db1 3412 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3413 return;
1390a28b
AK		 3414 var->base = vmx_read_guest_seg_base(vmx, seg);
3415 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3416 return;
a9179499 3417 }
2fb92db1
AK		 3418 var->base = vmx_read_guest_seg_base(vmx, seg);
3419 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3420 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3421 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3422 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3423 var->type = ar & 15;
3424 var->s = (ar >> 4) & 1;
3425 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3426 /*
3427 * Some userspaces do not preserve unusable property. Since usable
3428 * segment has to be present according to VMX spec we can use present
3429 * property to amend userspace bug by making unusable segment always
3430 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3431 * segment as unusable.
3432 */
3433 var->present = !var->unusable;
6aa8b732
AK		 3434 var->avl = (ar >> 12) & 1;
3435 var->l = (ar >> 13) & 1;
3436 var->db = (ar >> 14) & 1;
3437 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3438}
3439
a9179499
AK		 3440static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3441{
a9179499
AK		 3442 struct kvm_segment s;
3443
3444 if (to_vmx(vcpu)->rmode.vm86_active) {
3445 vmx_get_segment(vcpu, &s, seg);
3446 return s.base;
3447 }
2fb92db1 3448 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3449}
3450
b09408d0 3451static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3452{
b09408d0
MT		 3453 struct vcpu_vmx *vmx = to_vmx(vcpu);
3454
3eeb3288 3455 if (!is_protmode(vcpu))
2e4d2653
IE		 3456 return 0;
3457
f4c63e5d
AK		 3458 if (!is_long_mode(vcpu)
3459 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3460 return 3;
3461
69c73028
AK		 3462 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3463 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3464 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3465 }
d881e6f6
AK		 3466
3467 return vmx->cpl;
69c73028
AK		 3468}
3469
3470
653e3108 3471static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3472{
6aa8b732
AK		 3473 u32 ar;
3474
f0495f9b 3475 if (var->unusable || !var->present)
6aa8b732
AK		 3476 ar = 1 << 16;
3477 else {
3478 ar = var->type & 15;
3479 ar |= (var->s & 1) << 4;
3480 ar |= (var->dpl & 3) << 5;
3481 ar |= (var->present & 1) << 7;
3482 ar |= (var->avl & 1) << 12;
3483 ar |= (var->l & 1) << 13;
3484 ar |= (var->db & 1) << 14;
3485 ar |= (var->g & 1) << 15;
3486 }
653e3108
AK		 3487
3488 return ar;
3489}
3490
3491static void vmx_set_segment(struct kvm_vcpu *vcpu,
3492 struct kvm_segment *var, int seg)
3493{
7ffd92c5 3494 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3495 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3496
2fb92db1 3497 vmx_segment_cache_clear(vmx);
2f143240
GN		 3498 if (seg == VCPU_SREG_CS)
3499 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3500
1ecd50a9
GN		 3501 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3502 vmx->rmode.segs[seg] = *var;
3503 if (seg == VCPU_SREG_TR)
3504 vmcs_write16(sf->selector, var->selector);
3505 else if (var->s)
3506 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3507 goto out;
653e3108 3508 }
1ecd50a9 3509
653e3108
AK		 3510 vmcs_writel(sf->base, var->base);
3511 vmcs_write32(sf->limit, var->limit);
3512 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3513
3514 /*
3515 * Fix the "Accessed" bit in AR field of segment registers for older
3516 * qemu binaries.
3517 * IA32 arch specifies that at the time of processor reset the
3518 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3519 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3520 * state vmexit when "unrestricted guest" mode is turned on.
3521 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3522 * tree. Newer qemu binaries with that qemu fix would not need this
3523 * kvm hack.
3524 */
3525 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3526 var->type |= 0x1; /* Accessed */
3a624e29 3527
f924d66d 3528 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3529
3530out:
14168786 3531 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3532}
3533
6aa8b732
AK		 3534static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3535{
2fb92db1 3536 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3537
3538 *db = (ar >> 14) & 1;
3539 *l = (ar >> 13) & 1;
3540}
3541
89a27f4d 3542static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3543{
89a27f4d
GN		 3544 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3545 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3546}
3547
89a27f4d 3548static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3549{
89a27f4d
GN		 3550 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3551 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3552}
3553
89a27f4d 3554static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3555{
89a27f4d
GN		 3556 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3557 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3558}
3559
89a27f4d 3560static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3561{
89a27f4d
GN		 3562 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3563 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3564}
3565
648dfaa7
MG		 3566static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3567{
3568 struct kvm_segment var;
3569 u32 ar;
3570
3571 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3572 var.dpl = 0x3;
0647f4aa
GN		 3573 if (seg == VCPU_SREG_CS)
3574 var.type = 0x3;
648dfaa7
MG		 3575 ar = vmx_segment_access_rights(&var);
3576
3577 if (var.base != (var.selector << 4))
3578 return false;
89efbed0 3579 if (var.limit != 0xffff)
648dfaa7 3580 return false;
07f42f5f 3581 if (ar != 0xf3)
648dfaa7
MG		 3582 return false;
3583
3584 return true;
3585}
3586
3587static bool code_segment_valid(struct kvm_vcpu *vcpu)
3588{
3589 struct kvm_segment cs;
3590 unsigned int cs_rpl;
3591
3592 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3593 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3594
1872a3f4
AK		 3595 if (cs.unusable)
3596 return false;
648dfaa7
MG		 3597 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3598 return false;
3599 if (!cs.s)
3600 return false;
1872a3f4 3601 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3602 if (cs.dpl > cs_rpl)
3603 return false;
1872a3f4 3604 } else {
648dfaa7
MG		 3605 if (cs.dpl != cs_rpl)
3606 return false;
3607 }
3608 if (!cs.present)
3609 return false;
3610
3611 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3612 return true;
3613}
3614
3615static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3616{
3617 struct kvm_segment ss;
3618 unsigned int ss_rpl;
3619
3620 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3621 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3622
1872a3f4
AK		 3623 if (ss.unusable)
3624 return true;
3625 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3626 return false;
3627 if (!ss.s)
3628 return false;
3629 if (ss.dpl != ss_rpl) /* DPL != RPL */
3630 return false;
3631 if (!ss.present)
3632 return false;
3633
3634 return true;
3635}
3636
3637static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3638{
3639 struct kvm_segment var;
3640 unsigned int rpl;
3641
3642 vmx_get_segment(vcpu, &var, seg);
3643 rpl = var.selector & SELECTOR_RPL_MASK;
3644
1872a3f4
AK		 3645 if (var.unusable)
3646 return true;
648dfaa7
MG		 3647 if (!var.s)
3648 return false;
3649 if (!var.present)
3650 return false;
3651 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3652 if (var.dpl < rpl) /* DPL < RPL */
3653 return false;
3654 }
3655
3656 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3657 * rights flags
3658 */
3659 return true;
3660}
3661
3662static bool tr_valid(struct kvm_vcpu *vcpu)
3663{
3664 struct kvm_segment tr;
3665
3666 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3667
1872a3f4
AK		 3668 if (tr.unusable)
3669 return false;
648dfaa7
MG		 3670 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3671 return false;
1872a3f4 3672 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3673 return false;
3674 if (!tr.present)
3675 return false;
3676
3677 return true;
3678}
3679
3680static bool ldtr_valid(struct kvm_vcpu *vcpu)
3681{
3682 struct kvm_segment ldtr;
3683
3684 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3685
1872a3f4
AK		 3686 if (ldtr.unusable)
3687 return true;
648dfaa7
MG		 3688 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3689 return false;
3690 if (ldtr.type != 2)
3691 return false;
3692 if (!ldtr.present)
3693 return false;
3694
3695 return true;
3696}
3697
3698static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3699{
3700 struct kvm_segment cs, ss;
3701
3702 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3703 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3704
3705 return ((cs.selector & SELECTOR_RPL_MASK) ==
3706 (ss.selector & SELECTOR_RPL_MASK));
3707}
3708
3709/*
3710 * Check if guest state is valid. Returns true if valid, false if
3711 * not.
3712 * We assume that registers are always usable
3713 */
3714static bool guest_state_valid(struct kvm_vcpu *vcpu)
3715{
c5e97c80
GN		 3716 if (enable_unrestricted_guest)
3717 return true;
3718
648dfaa7 3719 /* real mode guest state checks */
f13882d8 3720 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3721 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3722 return false;
3723 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3724 return false;
3725 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3726 return false;
3727 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3728 return false;
3729 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3730 return false;
3731 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3732 return false;
3733 } else {
3734 /* protected mode guest state checks */
3735 if (!cs_ss_rpl_check(vcpu))
3736 return false;
3737 if (!code_segment_valid(vcpu))
3738 return false;
3739 if (!stack_segment_valid(vcpu))
3740 return false;
3741 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3742 return false;
3743 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3744 return false;
3745 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3746 return false;
3747 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3748 return false;
3749 if (!tr_valid(vcpu))
3750 return false;
3751 if (!ldtr_valid(vcpu))
3752 return false;
3753 }
3754 /* TODO:
3755 * - Add checks on RIP
3756 * - Add checks on RFLAGS
3757 */
3758
3759 return true;
3760}
3761
d77c26fc 3762static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3763{
40dcaa9f 3764 gfn_t fn;
195aefde 3765 u16 data = 0;
40dcaa9f 3766 int r, idx, ret = 0;
6aa8b732 3767
40dcaa9f 3768 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3769 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3770 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3771 if (r < 0)
10589a46 3772 goto out;
195aefde 3773 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3774 r = kvm_write_guest_page(kvm, fn++, &data,
3775 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3776 if (r < 0)
10589a46 3777 goto out;
195aefde
IE		 3778 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3779 if (r < 0)
10589a46 3780 goto out;
195aefde
IE		 3781 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3782 if (r < 0)
10589a46 3783 goto out;
195aefde 3784 data = ~0;
10589a46
MT		 3785 r = kvm_write_guest_page(kvm, fn, &data,
3786 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3787 sizeof(u8));
195aefde 3788 if (r < 0)
10589a46
MT		 3789 goto out;
3790
3791 ret = 1;
3792out:
40dcaa9f 3793 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3794 return ret;
6aa8b732
AK		 3795}
3796
b7ebfb05
SY		 3797static int init_rmode_identity_map(struct kvm *kvm)
3798{
40dcaa9f 3799 int i, idx, r, ret;
b7ebfb05
SY		 3800 pfn_t identity_map_pfn;
3801 u32 tmp;
3802
089d034e 3803 if (!enable_ept)
b7ebfb05
SY		 3804 return 1;
3805 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3806 printk(KERN_ERR "EPT: identity-mapping pagetable "
3807 "haven't been allocated!\n");
3808 return 0;
3809 }
3810 if (likely(kvm->arch.ept_identity_pagetable_done))
3811 return 1;
3812 ret = 0;
b927a3ce 3813 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3814 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3815 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3816 if (r < 0)
3817 goto out;
3818 /* Set up identity-mapping pagetable for EPT in real mode */
3819 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3820 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3821 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3822 r = kvm_write_guest_page(kvm, identity_map_pfn,
3823 &tmp, i * sizeof(tmp), sizeof(tmp));
3824 if (r < 0)
3825 goto out;
3826 }
3827 kvm->arch.ept_identity_pagetable_done = true;
3828 ret = 1;
3829out:
40dcaa9f 3830 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3831 return ret;
3832}
3833
6aa8b732
AK		 3834static void seg_setup(int seg)
3835{
772e0318 3836 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3837 unsigned int ar;
6aa8b732
AK		 3838
3839 vmcs_write16(sf->selector, 0);
3840 vmcs_writel(sf->base, 0);
3841 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3842 ar = 0x93;
3843 if (seg == VCPU_SREG_CS)
3844 ar |= 0x08; /* code segment */
3a624e29
NK		 3845
3846 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3847}
3848
f78e0e2e
SY		 3849static int alloc_apic_access_page(struct kvm *kvm)
3850{
4484141a 3851 struct page *page;
f78e0e2e
SY		 3852 struct kvm_userspace_memory_region kvm_userspace_mem;
3853 int r = 0;
3854
79fac95e 3855 mutex_lock(&kvm->slots_lock);
bfc6d222 3856 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3857 goto out;
3858 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3859 kvm_userspace_mem.flags = 0;
3860 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3861 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3862 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3863 if (r)
3864 goto out;
72dc67a6 3865
4484141a
XG		 3866 page = gfn_to_page(kvm, 0xfee00);
3867 if (is_error_page(page)) {
3868 r = -EFAULT;
3869 goto out;
3870 }
3871
3872 kvm->arch.apic_access_page = page;
f78e0e2e 3873out:
79fac95e 3874 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3875 return r;
3876}
3877
b7ebfb05
SY		 3878static int alloc_identity_pagetable(struct kvm *kvm)
3879{
4484141a 3880 struct page *page;
b7ebfb05
SY		 3881 struct kvm_userspace_memory_region kvm_userspace_mem;
3882 int r = 0;
3883
79fac95e 3884 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3885 if (kvm->arch.ept_identity_pagetable)
3886 goto out;
3887 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3888 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3889 kvm_userspace_mem.guest_phys_addr =
3890 kvm->arch.ept_identity_map_addr;
b7ebfb05 3891 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3892 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3893 if (r)
3894 goto out;
3895
4484141a
XG		 3896 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3897 if (is_error_page(page)) {
3898 r = -EFAULT;
3899 goto out;
3900 }
3901
3902 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3903out:
79fac95e 3904 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3905 return r;
3906}
3907
2384d2b3
SY		 3908static void allocate_vpid(struct vcpu_vmx *vmx)
3909{
3910 int vpid;
3911
3912 vmx->vpid = 0;
919818ab 3913 if (!enable_vpid)
2384d2b3
SY		 3914 return;
3915 spin_lock(&vmx_vpid_lock);
3916 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3917 if (vpid < VMX_NR_VPIDS) {
3918 vmx->vpid = vpid;
3919 __set_bit(vpid, vmx_vpid_bitmap);
3920 }
3921 spin_unlock(&vmx_vpid_lock);
3922}
3923
cdbecfc3
LJ		 3924static void free_vpid(struct vcpu_vmx *vmx)
3925{
3926 if (!enable_vpid)
3927 return;
3928 spin_lock(&vmx_vpid_lock);
3929 if (vmx->vpid != 0)
3930 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3931 spin_unlock(&vmx_vpid_lock);
3932}
3933
8d14695f
YZ		 3934#define MSR_TYPE_R 1
3935#define MSR_TYPE_W 2
3936static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3937 u32 msr, int type)
25c5f225 3938{
3e7c73e9 3939 int f = sizeof(unsigned long);
25c5f225
SY		 3940
3941 if (!cpu_has_vmx_msr_bitmap())
3942 return;
3943
3944 /*
3945 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3946 * have the write-low and read-high bitmap offsets the wrong way round.
3947 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3948 */
25c5f225 3949 if (msr <= 0x1fff) {
8d14695f
YZ		 3950 if (type & MSR_TYPE_R)
3951 /* read-low */
3952 __clear_bit(msr, msr_bitmap + 0x000 / f);
3953
3954 if (type & MSR_TYPE_W)
3955 /* write-low */
3956 __clear_bit(msr, msr_bitmap + 0x800 / f);
3957
25c5f225
SY		 3958 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3959 msr &= 0x1fff;
8d14695f
YZ		 3960 if (type & MSR_TYPE_R)
3961 /* read-high */
3962 __clear_bit(msr, msr_bitmap + 0x400 / f);
3963
3964 if (type & MSR_TYPE_W)
3965 /* write-high */
3966 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3967
3968 }
3969}
3970
3971static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3972 u32 msr, int type)
3973{
3974 int f = sizeof(unsigned long);
3975
3976 if (!cpu_has_vmx_msr_bitmap())
3977 return;
3978
3979 /*
3980 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3981 * have the write-low and read-high bitmap offsets the wrong way round.
3982 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3983 */
3984 if (msr <= 0x1fff) {
3985 if (type & MSR_TYPE_R)
3986 /* read-low */
3987 __set_bit(msr, msr_bitmap + 0x000 / f);
3988
3989 if (type & MSR_TYPE_W)
3990 /* write-low */
3991 __set_bit(msr, msr_bitmap + 0x800 / f);
3992
3993 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3994 msr &= 0x1fff;
3995 if (type & MSR_TYPE_R)
3996 /* read-high */
3997 __set_bit(msr, msr_bitmap + 0x400 / f);
3998
3999 if (type & MSR_TYPE_W)
4000 /* write-high */
4001 __set_bit(msr, msr_bitmap + 0xc00 / f);
4002
25c5f225 4003 }
25c5f225
SY		 4004}
4005
5897297b
AK		 4006static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4007{
4008 if (!longmode_only)
8d14695f
YZ		 4009 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4010 msr, MSR_TYPE_R | MSR_TYPE_W);
4011 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4012 msr, MSR_TYPE_R | MSR_TYPE_W);
4013}
4014
4015static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4016{
4017 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4018 msr, MSR_TYPE_R);
4019 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4020 msr, MSR_TYPE_R);
4021}
4022
4023static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4024{
4025 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4026 msr, MSR_TYPE_R);
4027 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4028 msr, MSR_TYPE_R);
4029}
4030
4031static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4032{
4033 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4034 msr, MSR_TYPE_W);
4035 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4036 msr, MSR_TYPE_W);
5897297b
AK		 4037}
4038
01e439be
YZ		 4039static int vmx_vm_has_apicv(struct kvm *kvm)
4040{
4041 return enable_apicv && irqchip_in_kernel(kvm);
4042}
4043
a20ed54d
YZ		 4044/*
4045 * Send interrupt to vcpu via posted interrupt way.
4046 * 1. If target vcpu is running(non-root mode), send posted interrupt
4047 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4048 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4049 * interrupt from PIR in next vmentry.
4050 */
4051static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4052{
4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
4054 int r;
4055
4056 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4057 return;
4058
4059 r = pi_test_and_set_on(&vmx->pi_desc);
4060 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4061#ifdef CONFIG_SMP
a20ed54d
YZ		 4062 if (!r && (vcpu->mode == IN_GUEST_MODE))
4063 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4064 POSTED_INTR_VECTOR);
4065 else
6ffbbbba 4066#endif
a20ed54d
YZ		 4067 kvm_vcpu_kick(vcpu);
4068}
4069
4070static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4071{
4072 struct vcpu_vmx *vmx = to_vmx(vcpu);
4073
4074 if (!pi_test_and_clear_on(&vmx->pi_desc))
4075 return;
4076
4077 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4078}
4079
4080static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4081{
4082 return;
4083}
4084
a3a8ff8e
NHE		 4085/*
4086 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4087 * will not change in the lifetime of the guest.
4088 * Note that host-state that does change is set elsewhere. E.g., host-state
4089 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4090 */
a547c6db 4091static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4092{
4093 u32 low32, high32;
4094 unsigned long tmpl;
4095 struct desc_ptr dt;
4096
b1a74bf8 4097 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4098 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4099 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4100
4101 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4102#ifdef CONFIG_X86_64
4103 /*
4104 * Load null selectors, so we can avoid reloading them in
4105 * __vmx_load_host_state(), in case userspace uses the null selectors
4106 * too (the expected case).
4107 */
4108 vmcs_write16(HOST_DS_SELECTOR, 0);
4109 vmcs_write16(HOST_ES_SELECTOR, 0);
4110#else
a3a8ff8e
NHE		 4111 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4112 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4113#endif
a3a8ff8e
NHE		 4114 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4115 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4116
4117 native_store_idt(&dt);
4118 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4119 vmx->host_idt_base = dt.address;
a3a8ff8e 4120
83287ea4 4121 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4122
4123 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4124 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4125 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4126 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4127
4128 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4129 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4130 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4131 }
4132}
4133
bf8179a0
NHE		 4134static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4135{
4136 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4137 if (enable_ept)
4138 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4139 if (is_guest_mode(&vmx->vcpu))
4140 vmx->vcpu.arch.cr4_guest_owned_bits &=
4141 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4142 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4143}
4144
01e439be
YZ		 4145static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4146{
4147 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4148
4149 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4150 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4151 return pin_based_exec_ctrl;
4152}
4153
bf8179a0
NHE		 4154static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4155{
4156 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4157 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4158 exec_control &= ~CPU_BASED_TPR_SHADOW;
4159#ifdef CONFIG_X86_64
4160 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4161 CPU_BASED_CR8_LOAD_EXITING;
4162#endif
4163 }
4164 if (!enable_ept)
4165 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4166 CPU_BASED_CR3_LOAD_EXITING |
4167 CPU_BASED_INVLPG_EXITING;
4168 return exec_control;
4169}
4170
4171static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4172{
4173 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4174 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4175 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4176 if (vmx->vpid == 0)
4177 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4178 if (!enable_ept) {
4179 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4180 enable_unrestricted_guest = 0;
ad756a16
MJ		 4181 /* Enable INVPCID for non-ept guests may cause performance regression. */
4182 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4183 }
4184 if (!enable_unrestricted_guest)
4185 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4186 if (!ple_gap)
4187 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4188 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4189 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4190 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4191 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4192 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4193 (handle_vmptrld).
4194 We can NOT enable shadow_vmcs here because we don't have yet
4195 a current VMCS12
4196 */
4197 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4198 return exec_control;
4199}
4200
ce88decf
XG		 4201static void ept_set_mmio_spte_mask(void)
4202{
4203 /*
4204 * EPT Misconfigurations can be generated if the value of bits 2:0
4205 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4206 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4207 * spte.
4208 */
885032b9 4209 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4210}
4211
6aa8b732
AK		 4212/*
4213 * Sets up the vmcs for emulated real mode.
4214 */
8b9cf98c 4215static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4216{
2e4ce7f5 4217#ifdef CONFIG_X86_64
6aa8b732 4218 unsigned long a;
2e4ce7f5 4219#endif
6aa8b732 4220 int i;
6aa8b732 4221
6aa8b732 4222 /* I/O */
3e7c73e9
AK		 4223 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4224 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4225
4607c2d7
AG		 4226 if (enable_shadow_vmcs) {
4227 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4228 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4229 }
25c5f225 4230 if (cpu_has_vmx_msr_bitmap())
5897297b 4231 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4232
6aa8b732
AK		 4233 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4234
6aa8b732 4235 /* Control */
01e439be 4236 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4237
bf8179a0 4238 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4239
83ff3b9d 4240 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4241 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4242 vmx_secondary_exec_control(vmx));
83ff3b9d 4243 }
f78e0e2e 4244
01e439be 4245 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4246 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4247 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4248 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4249 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4250
4251 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4252
4253 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4254 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4255 }
4256
4b8d54f9
ZE		 4257 if (ple_gap) {
4258 vmcs_write32(PLE_GAP, ple_gap);
4259 vmcs_write32(PLE_WINDOW, ple_window);
4260 }
4261
c3707958
XG		 4262 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4263 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4264 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4265
9581d442
AK		 4266 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4267 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4268 vmx_set_constant_host_state(vmx);
05b3e0c2 4269#ifdef CONFIG_X86_64
6aa8b732
AK		 4270 rdmsrl(MSR_FS_BASE, a);
4271 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4272 rdmsrl(MSR_GS_BASE, a);
4273 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4274#else
4275 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4276 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4277#endif
4278
2cc51560
ED		 4279 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4280 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4281 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4282 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4283 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4284
468d472f 4285 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4286 u32 msr_low, msr_high;
4287 u64 host_pat;
468d472f
SY		 4288 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4289 host_pat = msr_low | ((u64) msr_high << 32);
4290 /* Write the default value follow host pat */
4291 vmcs_write64(GUEST_IA32_PAT, host_pat);
4292 /* Keep arch.pat sync with GUEST_IA32_PAT */
4293 vmx->vcpu.arch.pat = host_pat;
4294 }
4295
6aa8b732
AK		 4296 for (i = 0; i < NR_VMX_MSR; ++i) {
4297 u32 index = vmx_msr_index[i];
4298 u32 data_low, data_high;
a2fa3e9f 4299 int j = vmx->nmsrs;
6aa8b732
AK		 4300
4301 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4302 continue;
432bd6cb
AK		 4303 if (wrmsr_safe(index, data_low, data_high) < 0)
4304 continue;
26bb0981
AK		 4305 vmx->guest_msrs[j].index = i;
4306 vmx->guest_msrs[j].data = 0;
d5696725 4307 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4308 ++vmx->nmsrs;
6aa8b732 4309 }
6aa8b732 4310
1c3d14fe 4311 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4312
4313 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4314 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4315
e00c8cf2 4316 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4317 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4318
4319 return 0;
4320}
4321
57f252f2 4322static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4323{
4324 struct vcpu_vmx *vmx = to_vmx(vcpu);
4325 u64 msr;
e00c8cf2 4326
7ffd92c5 4327 vmx->rmode.vm86_active = 0;
e00c8cf2 4328
3b86cd99
JK		 4329 vmx->soft_vnmi_blocked = 0;
4330
ad312c7c 4331 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4332 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4333 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4334 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4335 msr |= MSR_IA32_APICBASE_BSP;
4336 kvm_set_apic_base(&vmx->vcpu, msr);
4337
2fb92db1
AK		 4338 vmx_segment_cache_clear(vmx);
4339
5706be0d 4340 seg_setup(VCPU_SREG_CS);
66450a21 4341 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4342 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4343
4344 seg_setup(VCPU_SREG_DS);
4345 seg_setup(VCPU_SREG_ES);
4346 seg_setup(VCPU_SREG_FS);
4347 seg_setup(VCPU_SREG_GS);
4348 seg_setup(VCPU_SREG_SS);
4349
4350 vmcs_write16(GUEST_TR_SELECTOR, 0);
4351 vmcs_writel(GUEST_TR_BASE, 0);
4352 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4353 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4354
4355 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4356 vmcs_writel(GUEST_LDTR_BASE, 0);
4357 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4358 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4359
4360 vmcs_write32(GUEST_SYSENTER_CS, 0);
4361 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4362 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4363
4364 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4365 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4366
e00c8cf2
AK		 4367 vmcs_writel(GUEST_GDTR_BASE, 0);
4368 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4369
4370 vmcs_writel(GUEST_IDTR_BASE, 0);
4371 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4372
443381a8 4373 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4374 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4375 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4376
e00c8cf2
AK		 4377 /* Special registers */
4378 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4379
4380 setup_msrs(vmx);
4381
6aa8b732
AK		 4382 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4383
f78e0e2e
SY		 4384 if (cpu_has_vmx_tpr_shadow()) {
4385 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4386 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4387 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4388 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4389 vmcs_write32(TPR_THRESHOLD, 0);
4390 }
4391
4392 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4393 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4394 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4395
01e439be
YZ		 4396 if (vmx_vm_has_apicv(vcpu->kvm))
4397 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4398
2384d2b3
SY		 4399 if (vmx->vpid != 0)
4400 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4401
fa40052c 4402 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4403 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4404 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4405 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4406 vmx_fpu_activate(&vmx->vcpu);
4407 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4408
b9d762fa 4409 vpid_sync_context(vmx);
6aa8b732
AK		 4410}
4411
b6f1250e
NHE		 4412/*
4413 * In nested virtualization, check if L1 asked to exit on external interrupts.
4414 * For most existing hypervisors, this will always return true.
4415 */
4416static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4417{
4418 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4419 PIN_BASED_EXT_INTR_MASK;
4420}
4421
ea8ceb83
JK		 4422static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4423{
4424 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4425 PIN_BASED_NMI_EXITING;
4426}
4427
730dca42 4428static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4429{
4430 u32 cpu_based_vm_exec_control;
730dca42
JK		 4431
4432 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4433 /*
4434 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4435 * inject to L1 now because L2 must run. The caller will have
4436 * to make L2 exit right after entry, so we can inject to L1
4437 * more promptly.
b6f1250e 4438 */
730dca42 4439 return -EBUSY;
3b86cd99
JK		 4440
4441 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4442 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4443 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4444 return 0;
3b86cd99
JK		 4445}
4446
03b28f81 4447static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4448{
4449 u32 cpu_based_vm_exec_control;
4450
03b28f81
JK		 4451 if (!cpu_has_virtual_nmis())
4452 return enable_irq_window(vcpu);
4453
4454 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4455 return enable_irq_window(vcpu);
3b86cd99
JK		 4456
4457 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4458 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4459 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4460 return 0;
3b86cd99
JK		 4461}
4462
66fd3f7f 4463static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4464{
9c8cba37 4465 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4466 uint32_t intr;
4467 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4468
229456fc 4469 trace_kvm_inj_virq(irq);
2714d1d3 4470
fa89a817 4471 ++vcpu->stat.irq_injections;
7ffd92c5 4472 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4473 int inc_eip = 0;
4474 if (vcpu->arch.interrupt.soft)
4475 inc_eip = vcpu->arch.event_exit_inst_len;
4476 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4477 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4478 return;
4479 }
66fd3f7f
GN		 4480 intr = irq | INTR_INFO_VALID_MASK;
4481 if (vcpu->arch.interrupt.soft) {
4482 intr |= INTR_TYPE_SOFT_INTR;
4483 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4484 vmx->vcpu.arch.event_exit_inst_len);
4485 } else
4486 intr |= INTR_TYPE_EXT_INTR;
4487 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4488}
4489
f08864b4
SY		 4490static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4491{
66a5a347
JK		 4492 struct vcpu_vmx *vmx = to_vmx(vcpu);
4493
0b6ac343
NHE		 4494 if (is_guest_mode(vcpu))
4495 return;
4496
3b86cd99
JK		 4497 if (!cpu_has_virtual_nmis()) {
4498 /*
4499 * Tracking the NMI-blocked state in software is built upon
4500 * finding the next open IRQ window. This, in turn, depends on
4501 * well-behaving guests: They have to keep IRQs disabled at
4502 * least as long as the NMI handler runs. Otherwise we may
4503 * cause NMI nesting, maybe breaking the guest. But as this is
4504 * highly unlikely, we can live with the residual risk.
4505 */
4506 vmx->soft_vnmi_blocked = 1;
4507 vmx->vnmi_blocked_time = 0;
4508 }
4509
487b391d 4510 ++vcpu->stat.nmi_injections;
9d58b931 4511 vmx->nmi_known_unmasked = false;
7ffd92c5 4512 if (vmx->rmode.vm86_active) {
71f9833b 4513 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4514 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4515 return;
4516 }
f08864b4
SY		 4517 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4518 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4519}
4520
3cfc3092
JK		 4521static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4522{
4523 if (!cpu_has_virtual_nmis())
4524 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4525 if (to_vmx(vcpu)->nmi_known_unmasked)
4526 return false;
c332c83a 4527 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4528}
4529
4530static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4531{
4532 struct vcpu_vmx *vmx = to_vmx(vcpu);
4533
4534 if (!cpu_has_virtual_nmis()) {
4535 if (vmx->soft_vnmi_blocked != masked) {
4536 vmx->soft_vnmi_blocked = masked;
4537 vmx->vnmi_blocked_time = 0;
4538 }
4539 } else {
9d58b931 4540 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4541 if (masked)
4542 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4543 GUEST_INTR_STATE_NMI);
4544 else
4545 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4546 GUEST_INTR_STATE_NMI);
4547 }
4548}
4549
2505dc9f
JK		 4550static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4551{
ea8ceb83
JK		 4552 if (is_guest_mode(vcpu)) {
4553 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4554
4555 if (to_vmx(vcpu)->nested.nested_run_pending)
4556 return 0;
4557 if (nested_exit_on_nmi(vcpu)) {
4558 nested_vmx_vmexit(vcpu);
4559 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4560 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4561 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4562 /*
4563 * The NMI-triggered VM exit counts as injection:
4564 * clear this one and block further NMIs.
4565 */
4566 vcpu->arch.nmi_pending = 0;
4567 vmx_set_nmi_mask(vcpu, true);
4568 return 0;
4569 }
4570 }
4571
2505dc9f
JK		 4572 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4573 return 0;
4574
4575 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4576 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4577 | GUEST_INTR_STATE_NMI));
4578}
4579
78646121
GN		 4580static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4581{
e8457c67 4582 if (is_guest_mode(vcpu)) {
51cfe38e 4583 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4584
4585 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4586 return 0;
e8457c67
JK		 4587 if (nested_exit_on_intr(vcpu)) {
4588 nested_vmx_vmexit(vcpu);
4589 vmcs12->vm_exit_reason =
4590 EXIT_REASON_EXTERNAL_INTERRUPT;
4591 vmcs12->vm_exit_intr_info = 0;
4592 /*
4593 * fall through to normal code, but now in L1, not L2
4594 */
4595 }
b6f1250e
NHE		 4596 }
4597
c4282df9
GN		 4598 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4599 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4600 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4601}
4602
cbc94022
IE		 4603static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4604{
4605 int ret;
4606 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4607 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4608 .guest_phys_addr = addr,
4609 .memory_size = PAGE_SIZE * 3,
4610 .flags = 0,
4611 };
4612
47ae31e2 4613 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4614 if (ret)
4615 return ret;
bfc6d222 4616 kvm->arch.tss_addr = addr;
93ea5388
GN		 4617 if (!init_rmode_tss(kvm))
4618 return -ENOMEM;
4619
cbc94022
IE		 4620 return 0;
4621}
4622
0ca1b4f4 4623static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4624{
77ab6db0 4625 switch (vec) {
77ab6db0 4626 case BP_VECTOR:
c573cd22
JK		 4627 /*
4628 * Update instruction length as we may reinject the exception
4629 * from user space while in guest debugging mode.
4630 */
4631 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4632 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4633 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4634 return false;
4635 /* fall through */
4636 case DB_VECTOR:
4637 if (vcpu->guest_debug &
4638 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4639 return false;
d0bfb940
JK		 4640 /* fall through */
4641 case DE_VECTOR:
77ab6db0
JK		 4642 case OF_VECTOR:
4643 case BR_VECTOR:
4644 case UD_VECTOR:
4645 case DF_VECTOR:
4646 case SS_VECTOR:
4647 case GP_VECTOR:
4648 case MF_VECTOR:
0ca1b4f4
GN		 4649 return true;
4650 break;
77ab6db0 4651 }
0ca1b4f4
GN		 4652 return false;
4653}
4654
4655static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4656 int vec, u32 err_code)
4657{
4658 /*
4659 * Instruction with address size override prefix opcode 0x67
4660 * Cause the #SS fault with 0 error code in VM86 mode.
4661 */
4662 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4663 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4664 if (vcpu->arch.halt_request) {
4665 vcpu->arch.halt_request = 0;
4666 return kvm_emulate_halt(vcpu);
4667 }
4668 return 1;
4669 }
4670 return 0;
4671 }
4672
4673 /*
4674 * Forward all other exceptions that are valid in real mode.
4675 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4676 * the required debugging infrastructure rework.
4677 */
4678 kvm_queue_exception(vcpu, vec);
4679 return 1;
6aa8b732
AK		 4680}
4681
a0861c02
AK		 4682/*
4683 * Trigger machine check on the host. We assume all the MSRs are already set up
4684 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4685 * We pass a fake environment to the machine check handler because we want
4686 * the guest to be always treated like user space, no matter what context
4687 * it used internally.
4688 */
4689static void kvm_machine_check(void)
4690{
4691#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4692 struct pt_regs regs = {
4693 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4694 .flags = X86_EFLAGS_IF,
4695 };
4696
4697 do_machine_check(&regs, 0);
4698#endif
4699}
4700
851ba692 4701static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4702{
4703 /* already handled by vcpu_run */
4704 return 1;
4705}
4706
851ba692 4707static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4708{
1155f76a 4709 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4710 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4711 u32 intr_info, ex_no, error_code;
42dbaa5a 4712 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4713 u32 vect_info;
4714 enum emulation_result er;
4715
1155f76a 4716 vect_info = vmx->idt_vectoring_info;
88786475 4717 intr_info = vmx->exit_intr_info;
6aa8b732 4718
a0861c02 4719 if (is_machine_check(intr_info))
851ba692 4720 return handle_machine_check(vcpu);
a0861c02 4721
e4a41889 4722 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4723 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4724
4725 if (is_no_device(intr_info)) {
5fd86fcf 4726 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4727 return 1;
4728 }
4729
7aa81cc0 4730 if (is_invalid_opcode(intr_info)) {
51d8b661 4731 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4732 if (er != EMULATE_DONE)
7ee5d940 4733 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4734 return 1;
4735 }
4736
6aa8b732 4737 error_code = 0;
2e11384c 4738 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4739 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4740
4741 /*
4742 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4743 * MMIO, it is better to report an internal error.
4744 * See the comments in vmx_handle_exit.
4745 */
4746 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4747 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4748 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4749 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4750 vcpu->run->internal.ndata = 2;
4751 vcpu->run->internal.data[0] = vect_info;
4752 vcpu->run->internal.data[1] = intr_info;
4753 return 0;
4754 }
4755
6aa8b732 4756 if (is_page_fault(intr_info)) {
1439442c 4757 /* EPT won't cause page fault directly */
cf3ace79 4758 BUG_ON(enable_ept);
6aa8b732 4759 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4760 trace_kvm_page_fault(cr2, error_code);
4761
3298b75c 4762 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4763 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4764 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4765 }
4766
d0bfb940 4767 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4768
4769 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4770 return handle_rmode_exception(vcpu, ex_no, error_code);
4771
42dbaa5a
JK		 4772 switch (ex_no) {
4773 case DB_VECTOR:
4774 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4775 if (!(vcpu->guest_debug &
4776 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4777 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4778 kvm_queue_exception(vcpu, DB_VECTOR);
4779 return 1;
4780 }
4781 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4782 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4783 /* fall through */
4784 case BP_VECTOR:
c573cd22
JK		 4785 /*
4786 * Update instruction length as we may reinject #BP from
4787 * user space while in guest debugging mode. Reading it for
4788 * #DB as well causes no harm, it is not used in that case.
4789 */
4790 vmx->vcpu.arch.event_exit_inst_len =
4791 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4792 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4793 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4794 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4795 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4796 break;
4797 default:
d0bfb940
JK		 4798 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4799 kvm_run->ex.exception = ex_no;
4800 kvm_run->ex.error_code = error_code;
42dbaa5a 4801 break;
6aa8b732 4802 }
6aa8b732
AK		 4803 return 0;
4804}
4805
851ba692 4806static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4807{
1165f5fe 4808 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4809 return 1;
4810}
4811
851ba692 4812static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4813{
851ba692 4814 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4815 return 0;
4816}
6aa8b732 4817
851ba692 4818static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4819{
bfdaab09 4820 unsigned long exit_qualification;
34c33d16 4821 int size, in, string;
039576c0 4822 unsigned port;
6aa8b732 4823
bfdaab09 4824 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4825 string = (exit_qualification & 16) != 0;
cf8f70bf 4826 in = (exit_qualification & 8) != 0;
e70669ab 4827
cf8f70bf 4828 ++vcpu->stat.io_exits;
e70669ab 4829
cf8f70bf 4830 if (string || in)
51d8b661 4831 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4832
cf8f70bf
GN		 4833 port = exit_qualification >> 16;
4834 size = (exit_qualification & 7) + 1;
e93f36bc 4835 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4836
4837 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4838}
4839
102d8325
IM		 4840static void
4841vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4842{
4843 /*
4844 * Patch in the VMCALL instruction:
4845 */
4846 hypercall[0] = 0x0f;
4847 hypercall[1] = 0x01;
4848 hypercall[2] = 0xc1;
102d8325
IM		 4849}
4850
0fa06071 4851/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4852static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4853{
eeadf9e7 4854 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4855 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4856 unsigned long orig_val = val;
4857
eeadf9e7
NHE		 4858 /*
4859 * We get here when L2 changed cr0 in a way that did not change
4860 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4861 * but did change L0 shadowed bits. So we first calculate the
4862 * effective cr0 value that L1 would like to write into the
4863 * hardware. It consists of the L2-owned bits from the new
4864 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4865 */
1a0d74e6
JK		 4866 val = (val & ~vmcs12->cr0_guest_host_mask) |
4867 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4868
4869 /* TODO: will have to take unrestricted guest mode into
4870 * account */
4871 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4872 return 1;
1a0d74e6
JK		 4873
4874 if (kvm_set_cr0(vcpu, val))
4875 return 1;
4876 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4877 return 0;
1a0d74e6
JK		 4878 } else {
4879 if (to_vmx(vcpu)->nested.vmxon &&
4880 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4881 return 1;
eeadf9e7 4882 return kvm_set_cr0(vcpu, val);
1a0d74e6 4883 }
eeadf9e7
NHE		 4884}
4885
4886static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4887{
4888 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4889 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4890 unsigned long orig_val = val;
4891
4892 /* analogously to handle_set_cr0 */
4893 val = (val & ~vmcs12->cr4_guest_host_mask) |
4894 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4895 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4896 return 1;
1a0d74e6 4897 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4898 return 0;
4899 } else
4900 return kvm_set_cr4(vcpu, val);
4901}
4902
4903/* called to set cr0 as approriate for clts instruction exit. */
4904static void handle_clts(struct kvm_vcpu *vcpu)
4905{
4906 if (is_guest_mode(vcpu)) {
4907 /*
4908 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4909 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4910 * just pretend it's off (also in arch.cr0 for fpu_activate).
4911 */
4912 vmcs_writel(CR0_READ_SHADOW,
4913 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4914 vcpu->arch.cr0 &= ~X86_CR0_TS;
4915 } else
4916 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4917}
4918
851ba692 4919static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4920{
229456fc 4921 unsigned long exit_qualification, val;
6aa8b732
AK		 4922 int cr;
4923 int reg;
49a9b07e 4924 int err;
6aa8b732 4925
bfdaab09 4926 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4927 cr = exit_qualification & 15;
4928 reg = (exit_qualification >> 8) & 15;
4929 switch ((exit_qualification >> 4) & 3) {
4930 case 0: /* mov to cr */
229456fc
MT		 4931 val = kvm_register_read(vcpu, reg);
4932 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4933 switch (cr) {
4934 case 0:
eeadf9e7 4935 err = handle_set_cr0(vcpu, val);
db8fcefa 4936 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4937 return 1;
4938 case 3:
2390218b 4939 err = kvm_set_cr3(vcpu, val);
db8fcefa 4940 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4941 return 1;
4942 case 4:
eeadf9e7 4943 err = handle_set_cr4(vcpu, val);
db8fcefa 4944 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4945 return 1;
0a5fff19
GN		 4946 case 8: {
4947 u8 cr8_prev = kvm_get_cr8(vcpu);
4948 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4949 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4950 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4951 if (irqchip_in_kernel(vcpu->kvm))
4952 return 1;
4953 if (cr8_prev <= cr8)
4954 return 1;
851ba692 4955 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4956 return 0;
4957 }
4b8073e4 4958 }
6aa8b732 4959 break;
25c4c276 4960 case 2: /* clts */
eeadf9e7 4961 handle_clts(vcpu);
4d4ec087 4962 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4963 skip_emulated_instruction(vcpu);
6b52d186 4964 vmx_fpu_activate(vcpu);
25c4c276 4965 return 1;
6aa8b732
AK		 4966 case 1: /*mov from cr*/
4967 switch (cr) {
4968 case 3:
9f8fe504
AK		 4969 val = kvm_read_cr3(vcpu);
4970 kvm_register_write(vcpu, reg, val);
4971 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4972 skip_emulated_instruction(vcpu);
4973 return 1;
4974 case 8:
229456fc
MT		 4975 val = kvm_get_cr8(vcpu);
4976 kvm_register_write(vcpu, reg, val);
4977 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4978 skip_emulated_instruction(vcpu);
4979 return 1;
4980 }
4981 break;
4982 case 3: /* lmsw */
a1f83a74 4983 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4984 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4985 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4986
4987 skip_emulated_instruction(vcpu);
4988 return 1;
4989 default:
4990 break;
4991 }
851ba692 4992 vcpu->run->exit_reason = 0;
a737f256 4993 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4994 (int)(exit_qualification >> 4) & 3, cr);
4995 return 0;
4996}
4997
851ba692 4998static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4999{
bfdaab09 5000 unsigned long exit_qualification;
6aa8b732
AK		 5001 int dr, reg;
5002
f2483415 5003 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5004 if (!kvm_require_cpl(vcpu, 0))
5005 return 1;
42dbaa5a
JK		 5006 dr = vmcs_readl(GUEST_DR7);
5007 if (dr & DR7_GD) {
5008 /*
5009 * As the vm-exit takes precedence over the debug trap, we
5010 * need to emulate the latter, either for the host or the
5011 * guest debugging itself.
5012 */
5013 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5014 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5015 vcpu->run->debug.arch.dr7 = dr;
5016 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5017 vmcs_readl(GUEST_CS_BASE) +
5018 vmcs_readl(GUEST_RIP);
851ba692
AK		 5019 vcpu->run->debug.arch.exception = DB_VECTOR;
5020 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5021 return 0;
5022 } else {
5023 vcpu->arch.dr7 &= ~DR7_GD;
5024 vcpu->arch.dr6 |= DR6_BD;
5025 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5026 kvm_queue_exception(vcpu, DB_VECTOR);
5027 return 1;
5028 }
5029 }
5030
bfdaab09 5031 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5032 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5033 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5034 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5035 unsigned long val;
5036 if (!kvm_get_dr(vcpu, dr, &val))
5037 kvm_register_write(vcpu, reg, val);
5038 } else
5039 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5040 skip_emulated_instruction(vcpu);
5041 return 1;
5042}
5043
020df079
GN		 5044static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5045{
5046 vmcs_writel(GUEST_DR7, val);
5047}
5048
851ba692 5049static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5050{
06465c5a
AK		 5051 kvm_emulate_cpuid(vcpu);
5052 return 1;
6aa8b732
AK		 5053}
5054
851ba692 5055static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5056{
ad312c7c 5057 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5058 u64 data;
5059
5060 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5061 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5062 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5063 return 1;
5064 }
5065
229456fc 5066 trace_kvm_msr_read(ecx, data);
2714d1d3 5067
6aa8b732 5068 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5069 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5070 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5071 skip_emulated_instruction(vcpu);
5072 return 1;
5073}
5074
851ba692 5075static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5076{
8fe8ab46 5077 struct msr_data msr;
ad312c7c
ZX		 5078 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5079 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5080 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5081
8fe8ab46
WA		 5082 msr.data = data;
5083 msr.index = ecx;
5084 msr.host_initiated = false;
5085 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5086 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5087 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5088 return 1;
5089 }
5090
59200273 5091 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5092 skip_emulated_instruction(vcpu);
5093 return 1;
5094}
5095
851ba692 5096static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5097{
3842d135 5098 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5099 return 1;
5100}
5101
851ba692 5102static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5103{
85f455f7
ED		 5104 u32 cpu_based_vm_exec_control;
5105
5106 /* clear pending irq */
5107 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5108 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5109 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5110
3842d135
AK		 5111 kvm_make_request(KVM_REQ_EVENT, vcpu);
5112
a26bf12a 5113 ++vcpu->stat.irq_window_exits;
2714d1d3 5114
c1150d8c
DL		 5115 /*
5116 * If the user space waits to inject interrupts, exit as soon as
5117 * possible
5118 */
8061823a 5119 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5120 vcpu->run->request_interrupt_window &&
8061823a 5121 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5122 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5123 return 0;
5124 }
6aa8b732
AK		 5125 return 1;
5126}
5127
851ba692 5128static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5129{
5130 skip_emulated_instruction(vcpu);
d3bef15f 5131 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5132}
5133
851ba692 5134static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5135{
510043da 5136 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5137 kvm_emulate_hypercall(vcpu);
5138 return 1;
c21415e8
IM		 5139}
5140
ec25d5e6
GN		 5141static int handle_invd(struct kvm_vcpu *vcpu)
5142{
51d8b661 5143 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5144}
5145
851ba692 5146static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5147{
f9c617f6 5148 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5149
5150 kvm_mmu_invlpg(vcpu, exit_qualification);
5151 skip_emulated_instruction(vcpu);
5152 return 1;
5153}
5154
fee84b07
AK		 5155static int handle_rdpmc(struct kvm_vcpu *vcpu)
5156{
5157 int err;
5158
5159 err = kvm_rdpmc(vcpu);
5160 kvm_complete_insn_gp(vcpu, err);
5161
5162 return 1;
5163}
5164
851ba692 5165static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5166{
5167 skip_emulated_instruction(vcpu);
f5f48ee1 5168 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5169 return 1;
5170}
5171
2acf923e
DC		 5172static int handle_xsetbv(struct kvm_vcpu *vcpu)
5173{
5174 u64 new_bv = kvm_read_edx_eax(vcpu);
5175 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5176
5177 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5178 skip_emulated_instruction(vcpu);
5179 return 1;
5180}
5181
851ba692 5182static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5183{
58fbbf26
KT		 5184 if (likely(fasteoi)) {
5185 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5186 int access_type, offset;
5187
5188 access_type = exit_qualification & APIC_ACCESS_TYPE;
5189 offset = exit_qualification & APIC_ACCESS_OFFSET;
5190 /*
5191 * Sane guest uses MOV to write EOI, with written value
5192 * not cared. So make a short-circuit here by avoiding
5193 * heavy instruction emulation.
5194 */
5195 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5196 (offset == APIC_EOI)) {
5197 kvm_lapic_set_eoi(vcpu);
5198 skip_emulated_instruction(vcpu);
5199 return 1;
5200 }
5201 }
51d8b661 5202 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5203}
5204
c7c9c56c
YZ		 5205static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5206{
5207 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5208 int vector = exit_qualification & 0xff;
5209
5210 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5211 kvm_apic_set_eoi_accelerated(vcpu, vector);
5212 return 1;
5213}
5214
83d4c286
YZ		 5215static int handle_apic_write(struct kvm_vcpu *vcpu)
5216{
5217 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5218 u32 offset = exit_qualification & 0xfff;
5219
5220 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5221 kvm_apic_write_nodecode(vcpu, offset);
5222 return 1;
5223}
5224
851ba692 5225static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5226{
60637aac 5227 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5228 unsigned long exit_qualification;
e269fb21
JK		 5229 bool has_error_code = false;
5230 u32 error_code = 0;
37817f29 5231 u16 tss_selector;
7f3d35fd 5232 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5233
5234 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5235 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5236 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5237
5238 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5239
5240 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5241 if (reason == TASK_SWITCH_GATE && idt_v) {
5242 switch (type) {
5243 case INTR_TYPE_NMI_INTR:
5244 vcpu->arch.nmi_injected = false;
654f06fc 5245 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5246 break;
5247 case INTR_TYPE_EXT_INTR:
66fd3f7f 5248 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5249 kvm_clear_interrupt_queue(vcpu);
5250 break;
5251 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5252 if (vmx->idt_vectoring_info &
5253 VECTORING_INFO_DELIVER_CODE_MASK) {
5254 has_error_code = true;
5255 error_code =
5256 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5257 }
5258 /* fall through */
64a7ec06
GN		 5259 case INTR_TYPE_SOFT_EXCEPTION:
5260 kvm_clear_exception_queue(vcpu);
5261 break;
5262 default:
5263 break;
5264 }
60637aac 5265 }
37817f29
IE		 5266 tss_selector = exit_qualification;
5267
64a7ec06
GN		 5268 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5269 type != INTR_TYPE_EXT_INTR &&
5270 type != INTR_TYPE_NMI_INTR))
5271 skip_emulated_instruction(vcpu);
5272
7f3d35fd
KW		 5273 if (kvm_task_switch(vcpu, tss_selector,
5274 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5275 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5276 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5277 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5278 vcpu->run->internal.ndata = 0;
42dbaa5a 5279 return 0;
acb54517 5280 }
42dbaa5a
JK		 5281
5282 /* clear all local breakpoint enable flags */
5283 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5284
5285 /*
5286 * TODO: What about debug traps on tss switch?
5287 * Are we supposed to inject them and update dr6?
5288 */
5289
5290 return 1;
37817f29
IE		 5291}
5292
851ba692 5293static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5294{
f9c617f6 5295 unsigned long exit_qualification;
1439442c 5296 gpa_t gpa;
4f5982a5 5297 u32 error_code;
1439442c 5298 int gla_validity;
1439442c 5299
f9c617f6 5300 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5301
1439442c
SY		 5302 gla_validity = (exit_qualification >> 7) & 0x3;
5303 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5304 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5305 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5306 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5307 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5308 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5309 (long unsigned int)exit_qualification);
851ba692
AK		 5310 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5311 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5312 return 0;
1439442c
SY		 5313 }
5314
5315 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5316 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5317
5318 /* It is a write fault? */
5319 error_code = exit_qualification & (1U << 1);
5320 /* ept page table is present? */
5321 error_code |= (exit_qualification >> 3) & 0x1;
5322
5323 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5324}
5325
68f89400
MT		 5326static u64 ept_rsvd_mask(u64 spte, int level)
5327{
5328 int i;
5329 u64 mask = 0;
5330
5331 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5332 mask |= (1ULL << i);
5333
5334 if (level > 2)
5335 /* bits 7:3 reserved */
5336 mask |= 0xf8;
5337 else if (level == 2) {
5338 if (spte & (1ULL << 7))
5339 /* 2MB ref, bits 20:12 reserved */
5340 mask |= 0x1ff000;
5341 else
5342 /* bits 6:3 reserved */
5343 mask |= 0x78;
5344 }
5345
5346 return mask;
5347}
5348
5349static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5350 int level)
5351{
5352 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5353
5354 /* 010b (write-only) */
5355 WARN_ON((spte & 0x7) == 0x2);
5356
5357 /* 110b (write/execute) */
5358 WARN_ON((spte & 0x7) == 0x6);
5359
5360 /* 100b (execute-only) and value not supported by logical processor */
5361 if (!cpu_has_vmx_ept_execute_only())
5362 WARN_ON((spte & 0x7) == 0x4);
5363
5364 /* not 000b */
5365 if ((spte & 0x7)) {
5366 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5367
5368 if (rsvd_bits != 0) {
5369 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5370 __func__, rsvd_bits);
5371 WARN_ON(1);
5372 }
5373
5374 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5375 u64 ept_mem_type = (spte & 0x38) >> 3;
5376
5377 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5378 ept_mem_type == 7) {
5379 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5380 __func__, ept_mem_type);
5381 WARN_ON(1);
5382 }
5383 }
5384 }
5385}
5386
851ba692 5387static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5388{
5389 u64 sptes[4];
ce88decf 5390 int nr_sptes, i, ret;
68f89400
MT		 5391 gpa_t gpa;
5392
5393 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5394
ce88decf 5395 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5396 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5397 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5398 EMULATE_DONE;
f8f55942
XG		 5399
5400 if (unlikely(ret == RET_MMIO_PF_INVALID))
5401 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5402
b37fbea6 5403 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5404 return 1;
5405
5406 /* It is the real ept misconfig */
68f89400
MT		 5407 printk(KERN_ERR "EPT: Misconfiguration.\n");
5408 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5409
5410 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5411
5412 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5413 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5414
851ba692
AK		 5415 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5416 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5417
5418 return 0;
5419}
5420
851ba692 5421static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5422{
5423 u32 cpu_based_vm_exec_control;
5424
5425 /* clear pending NMI */
5426 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5427 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5428 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5429 ++vcpu->stat.nmi_window_exits;
3842d135 5430 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5431
5432 return 1;
5433}
5434
80ced186 5435static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5436{
8b3079a5
AK		 5437 struct vcpu_vmx *vmx = to_vmx(vcpu);
5438 enum emulation_result err = EMULATE_DONE;
80ced186 5439 int ret = 1;
49e9d557
AK		 5440 u32 cpu_exec_ctrl;
5441 bool intr_window_requested;
b8405c18 5442 unsigned count = 130;
49e9d557
AK		 5443
5444 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5445 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5446
b8405c18 5447 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5448 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5449 return handle_interrupt_window(&vmx->vcpu);
5450
de87dcdd
AK		 5451 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5452 return 1;
5453
991eebf9 5454 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5455
ac0a48c3 5456 if (err == EMULATE_USER_EXIT) {
80ced186
MG		 5457 ret = 0;
5458 goto out;
5459 }
1d5a4d9b 5460
de5f70e0
AK		 5461 if (err != EMULATE_DONE) {
5462 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5463 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5464 vcpu->run->internal.ndata = 0;
6d77dbfc 5465 return 0;
de5f70e0 5466 }
ea953ef0 5467
8d76c49e
GN		 5468 if (vcpu->arch.halt_request) {
5469 vcpu->arch.halt_request = 0;
5470 ret = kvm_emulate_halt(vcpu);
5471 goto out;
5472 }
5473
ea953ef0 5474 if (signal_pending(current))
80ced186 5475 goto out;
ea953ef0
MG		 5476 if (need_resched())
5477 schedule();
5478 }
5479
14168786 5480 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5481out:
5482 return ret;
ea953ef0
MG		 5483}
5484
4b8d54f9
ZE		 5485/*
5486 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5487 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5488 */
9fb41ba8 5489static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5490{
5491 skip_emulated_instruction(vcpu);
5492 kvm_vcpu_on_spin(vcpu);
5493
5494 return 1;
5495}
5496
59708670
SY		 5497static int handle_invalid_op(struct kvm_vcpu *vcpu)
5498{
5499 kvm_queue_exception(vcpu, UD_VECTOR);
5500 return 1;
5501}
5502
ff2f6fe9
NHE		 5503/*
5504 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5505 * We could reuse a single VMCS for all the L2 guests, but we also want the
5506 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5507 * allows keeping them loaded on the processor, and in the future will allow
5508 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5509 * every entry if they never change.
5510 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5511 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5512 *
5513 * The following functions allocate and free a vmcs02 in this pool.
5514 */
5515
5516/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5517static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5518{
5519 struct vmcs02_list *item;
5520 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5521 if (item->vmptr == vmx->nested.current_vmptr) {
5522 list_move(&item->list, &vmx->nested.vmcs02_pool);
5523 return &item->vmcs02;
5524 }
5525
5526 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5527 /* Recycle the least recently used VMCS. */
5528 item = list_entry(vmx->nested.vmcs02_pool.prev,
5529 struct vmcs02_list, list);
5530 item->vmptr = vmx->nested.current_vmptr;
5531 list_move(&item->list, &vmx->nested.vmcs02_pool);
5532 return &item->vmcs02;
5533 }
5534
5535 /* Create a new VMCS */
0fa24ce3 5536 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5537 if (!item)
5538 return NULL;
5539 item->vmcs02.vmcs = alloc_vmcs();
5540 if (!item->vmcs02.vmcs) {
5541 kfree(item);
5542 return NULL;
5543 }
5544 loaded_vmcs_init(&item->vmcs02);
5545 item->vmptr = vmx->nested.current_vmptr;
5546 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5547 vmx->nested.vmcs02_num++;
5548 return &item->vmcs02;
5549}
5550
5551/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5552static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5553{
5554 struct vmcs02_list *item;
5555 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5556 if (item->vmptr == vmptr) {
5557 free_loaded_vmcs(&item->vmcs02);
5558 list_del(&item->list);
5559 kfree(item);
5560 vmx->nested.vmcs02_num--;
5561 return;
5562 }
5563}
5564
5565/*
5566 * Free all VMCSs saved for this vcpu, except the one pointed by
5567 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5568 * currently used, if running L2), and vmcs01 when running L2.
5569 */
5570static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5571{
5572 struct vmcs02_list *item, *n;
5573 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5574 if (vmx->loaded_vmcs != &item->vmcs02)
5575 free_loaded_vmcs(&item->vmcs02);
5576 list_del(&item->list);
5577 kfree(item);
5578 }
5579 vmx->nested.vmcs02_num = 0;
5580
5581 if (vmx->loaded_vmcs != &vmx->vmcs01)
5582 free_loaded_vmcs(&vmx->vmcs01);
5583}
5584
0658fbaa
ACL		 5585/*
5586 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5587 * set the success or error code of an emulated VMX instruction, as specified
5588 * by Vol 2B, VMX Instruction Reference, "Conventions".
5589 */
5590static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5591{
5592 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5593 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5594 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5595}
5596
5597static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5598{
5599 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5600 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5601 X86_EFLAGS_SF | X86_EFLAGS_OF))
5602 | X86_EFLAGS_CF);
5603}
5604
145c28dd 5605static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5606 u32 vm_instruction_error)
5607{
5608 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5609 /*
5610 * failValid writes the error number to the current VMCS, which
5611 * can't be done there isn't a current VMCS.
5612 */
5613 nested_vmx_failInvalid(vcpu);
5614 return;
5615 }
5616 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5617 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5618 X86_EFLAGS_SF | X86_EFLAGS_OF))
5619 | X86_EFLAGS_ZF);
5620 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5621 /*
5622 * We don't need to force a shadow sync because
5623 * VM_INSTRUCTION_ERROR is not shadowed
5624 */
5625}
145c28dd 5626
ec378aee
NHE		 5627/*
5628 * Emulate the VMXON instruction.
5629 * Currently, we just remember that VMX is active, and do not save or even
5630 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5631 * do not currently need to store anything in that guest-allocated memory
5632 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5633 * argument is different from the VMXON pointer (which the spec says they do).
5634 */
5635static int handle_vmon(struct kvm_vcpu *vcpu)
5636{
5637 struct kvm_segment cs;
5638 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5639 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5640 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5641 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5642
5643 /* The Intel VMX Instruction Reference lists a bunch of bits that
5644 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5645 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5646 * Otherwise, we should fail with #UD. We test these now:
5647 */
5648 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5649 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5650 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5651 kvm_queue_exception(vcpu, UD_VECTOR);
5652 return 1;
5653 }
5654
5655 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5656 if (is_long_mode(vcpu) && !cs.l) {
5657 kvm_queue_exception(vcpu, UD_VECTOR);
5658 return 1;
5659 }
5660
5661 if (vmx_get_cpl(vcpu)) {
5662 kvm_inject_gp(vcpu, 0);
5663 return 1;
5664 }
145c28dd
AG		 5665 if (vmx->nested.vmxon) {
5666 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5667 skip_emulated_instruction(vcpu);
5668 return 1;
5669 }
b3897a49
NHE		 5670
5671 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5672 != VMXON_NEEDED_FEATURES) {
5673 kvm_inject_gp(vcpu, 0);
5674 return 1;
5675 }
5676
8de48833
AG		 5677 if (enable_shadow_vmcs) {
5678 shadow_vmcs = alloc_vmcs();
5679 if (!shadow_vmcs)
5680 return -ENOMEM;
5681 /* mark vmcs as shadow */
5682 shadow_vmcs->revision_id |= (1u << 31);
5683 /* init shadow vmcs */
5684 vmcs_clear(shadow_vmcs);
5685 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5686 }
ec378aee 5687
ff2f6fe9
NHE		 5688 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5689 vmx->nested.vmcs02_num = 0;
5690
ec378aee
NHE		 5691 vmx->nested.vmxon = true;
5692
5693 skip_emulated_instruction(vcpu);
a25eb114 5694 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5695 return 1;
5696}
5697
5698/*
5699 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5700 * for running VMX instructions (except VMXON, whose prerequisites are
5701 * slightly different). It also specifies what exception to inject otherwise.
5702 */
5703static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5704{
5705 struct kvm_segment cs;
5706 struct vcpu_vmx *vmx = to_vmx(vcpu);
5707
5708 if (!vmx->nested.vmxon) {
5709 kvm_queue_exception(vcpu, UD_VECTOR);
5710 return 0;
5711 }
5712
5713 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5714 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5715 (is_long_mode(vcpu) && !cs.l)) {
5716 kvm_queue_exception(vcpu, UD_VECTOR);
5717 return 0;
5718 }
5719
5720 if (vmx_get_cpl(vcpu)) {
5721 kvm_inject_gp(vcpu, 0);
5722 return 0;
5723 }
5724
5725 return 1;
5726}
5727
e7953d7f
AG		 5728static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5729{
8a1b9dd0 5730 u32 exec_control;
012f83cb
AG		 5731 if (enable_shadow_vmcs) {
5732 if (vmx->nested.current_vmcs12 != NULL) {
5733 /* copy to memory all shadowed fields in case
5734 they were modified */
5735 copy_shadow_to_vmcs12(vmx);
5736 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5737 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5738 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5739 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5740 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5741 }
5742 }
e7953d7f
AG		 5743 kunmap(vmx->nested.current_vmcs12_page);
5744 nested_release_page(vmx->nested.current_vmcs12_page);
5745}
5746
ec378aee
NHE		 5747/*
5748 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5749 * just stops using VMX.
5750 */
5751static void free_nested(struct vcpu_vmx *vmx)
5752{
5753 if (!vmx->nested.vmxon)
5754 return;
5755 vmx->nested.vmxon = false;
a9d30f33 5756 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5757 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5758 vmx->nested.current_vmptr = -1ull;
5759 vmx->nested.current_vmcs12 = NULL;
5760 }
e7953d7f
AG		 5761 if (enable_shadow_vmcs)
5762 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5763 /* Unpin physical memory we referred to in current vmcs02 */
5764 if (vmx->nested.apic_access_page) {
5765 nested_release_page(vmx->nested.apic_access_page);
5766 vmx->nested.apic_access_page = 0;
5767 }
ff2f6fe9
NHE		 5768
5769 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5770}
5771
5772/* Emulate the VMXOFF instruction */
5773static int handle_vmoff(struct kvm_vcpu *vcpu)
5774{
5775 if (!nested_vmx_check_permission(vcpu))
5776 return 1;
5777 free_nested(to_vmx(vcpu));
5778 skip_emulated_instruction(vcpu);
a25eb114 5779 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5780 return 1;
5781}
5782
064aea77
NHE		 5783/*
5784 * Decode the memory-address operand of a vmx instruction, as recorded on an
5785 * exit caused by such an instruction (run by a guest hypervisor).
5786 * On success, returns 0. When the operand is invalid, returns 1 and throws
5787 * #UD or #GP.
5788 */
5789static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5790 unsigned long exit_qualification,
5791 u32 vmx_instruction_info, gva_t *ret)
5792{
5793 /*
5794 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5795 * Execution", on an exit, vmx_instruction_info holds most of the
5796 * addressing components of the operand. Only the displacement part
5797 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5798 * For how an actual address is calculated from all these components,
5799 * refer to Vol. 1, "Operand Addressing".
5800 */
5801 int scaling = vmx_instruction_info & 3;
5802 int addr_size = (vmx_instruction_info >> 7) & 7;
5803 bool is_reg = vmx_instruction_info & (1u << 10);
5804 int seg_reg = (vmx_instruction_info >> 15) & 7;
5805 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5806 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5807 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5808 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5809
5810 if (is_reg) {
5811 kvm_queue_exception(vcpu, UD_VECTOR);
5812 return 1;
5813 }
5814
5815 /* Addr = segment_base + offset */
5816 /* offset = base + [index * scale] + displacement */
5817 *ret = vmx_get_segment_base(vcpu, seg_reg);
5818 if (base_is_valid)
5819 *ret += kvm_register_read(vcpu, base_reg);
5820 if (index_is_valid)
5821 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5822 *ret += exit_qualification; /* holds the displacement */
5823
5824 if (addr_size == 1) /* 32 bit */
5825 *ret &= 0xffffffff;
5826
5827 /*
5828 * TODO: throw #GP (and return 1) in various cases that the VM*
5829 * instructions require it - e.g., offset beyond segment limit,
5830 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5831 * address, and so on. Currently these are not checked.
5832 */
5833 return 0;
5834}
5835
27d6c865
NHE		 5836/* Emulate the VMCLEAR instruction */
5837static int handle_vmclear(struct kvm_vcpu *vcpu)
5838{
5839 struct vcpu_vmx *vmx = to_vmx(vcpu);
5840 gva_t gva;
5841 gpa_t vmptr;
5842 struct vmcs12 *vmcs12;
5843 struct page *page;
5844 struct x86_exception e;
5845
5846 if (!nested_vmx_check_permission(vcpu))
5847 return 1;
5848
5849 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5850 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5851 return 1;
5852
5853 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5854 sizeof(vmptr), &e)) {
5855 kvm_inject_page_fault(vcpu, &e);
5856 return 1;
5857 }
5858
5859 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5860 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5861 skip_emulated_instruction(vcpu);
5862 return 1;
5863 }
5864
5865 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5866 nested_release_vmcs12(vmx);
27d6c865
NHE		 5867 vmx->nested.current_vmptr = -1ull;
5868 vmx->nested.current_vmcs12 = NULL;
5869 }
5870
5871 page = nested_get_page(vcpu, vmptr);
5872 if (page == NULL) {
5873 /*
5874 * For accurate processor emulation, VMCLEAR beyond available
5875 * physical memory should do nothing at all. However, it is
5876 * possible that a nested vmx bug, not a guest hypervisor bug,
5877 * resulted in this case, so let's shut down before doing any
5878 * more damage:
5879 */
5880 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5881 return 1;
5882 }
5883 vmcs12 = kmap(page);
5884 vmcs12->launch_state = 0;
5885 kunmap(page);
5886 nested_release_page(page);
5887
5888 nested_free_vmcs02(vmx, vmptr);
5889
5890 skip_emulated_instruction(vcpu);
5891 nested_vmx_succeed(vcpu);
5892 return 1;
5893}
5894
cd232ad0
NHE		 5895static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5896
5897/* Emulate the VMLAUNCH instruction */
5898static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5899{
5900 return nested_vmx_run(vcpu, true);
5901}
5902
5903/* Emulate the VMRESUME instruction */
5904static int handle_vmresume(struct kvm_vcpu *vcpu)
5905{
5906
5907 return nested_vmx_run(vcpu, false);
5908}
5909
49f705c5
NHE		 5910enum vmcs_field_type {
5911 VMCS_FIELD_TYPE_U16 = 0,
5912 VMCS_FIELD_TYPE_U64 = 1,
5913 VMCS_FIELD_TYPE_U32 = 2,
5914 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5915};
5916
5917static inline int vmcs_field_type(unsigned long field)
5918{
5919 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5920 return VMCS_FIELD_TYPE_U32;
5921 return (field >> 13) & 0x3 ;
5922}
5923
5924static inline int vmcs_field_readonly(unsigned long field)
5925{
5926 return (((field >> 10) & 0x3) == 1);
5927}
5928
5929/*
5930 * Read a vmcs12 field. Since these can have varying lengths and we return
5931 * one type, we chose the biggest type (u64) and zero-extend the return value
5932 * to that size. Note that the caller, handle_vmread, might need to use only
5933 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5934 * 64-bit fields are to be returned).
5935 */
5936static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5937 unsigned long field, u64 *ret)
5938{
5939 short offset = vmcs_field_to_offset(field);
5940 char *p;
5941
5942 if (offset < 0)
5943 return 0;
5944
5945 p = ((char *)(get_vmcs12(vcpu))) + offset;
5946
5947 switch (vmcs_field_type(field)) {
5948 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5949 *ret = *((natural_width *)p);
5950 return 1;
5951 case VMCS_FIELD_TYPE_U16:
5952 *ret = *((u16 *)p);
5953 return 1;
5954 case VMCS_FIELD_TYPE_U32:
5955 *ret = *((u32 *)p);
5956 return 1;
5957 case VMCS_FIELD_TYPE_U64:
5958 *ret = *((u64 *)p);
5959 return 1;
5960 default:
5961 return 0; /* can never happen. */
5962 }
5963}
5964
20b97fea
AG		 5965
5966static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5967 unsigned long field, u64 field_value){
5968 short offset = vmcs_field_to_offset(field);
5969 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5970 if (offset < 0)
5971 return false;
5972
5973 switch (vmcs_field_type(field)) {
5974 case VMCS_FIELD_TYPE_U16:
5975 *(u16 *)p = field_value;
5976 return true;
5977 case VMCS_FIELD_TYPE_U32:
5978 *(u32 *)p = field_value;
5979 return true;
5980 case VMCS_FIELD_TYPE_U64:
5981 *(u64 *)p = field_value;
5982 return true;
5983 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5984 *(natural_width *)p = field_value;
5985 return true;
5986 default:
5987 return false; /* can never happen. */
5988 }
5989
5990}
5991
16f5b903
AG		 5992static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5993{
5994 int i;
5995 unsigned long field;
5996 u64 field_value;
5997 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 5998 const unsigned long *fields = shadow_read_write_fields;
5999 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6000
6001 vmcs_load(shadow_vmcs);
6002
6003 for (i = 0; i < num_fields; i++) {
6004 field = fields[i];
6005 switch (vmcs_field_type(field)) {
6006 case VMCS_FIELD_TYPE_U16:
6007 field_value = vmcs_read16(field);
6008 break;
6009 case VMCS_FIELD_TYPE_U32:
6010 field_value = vmcs_read32(field);
6011 break;
6012 case VMCS_FIELD_TYPE_U64:
6013 field_value = vmcs_read64(field);
6014 break;
6015 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6016 field_value = vmcs_readl(field);
6017 break;
6018 }
6019 vmcs12_write_any(&vmx->vcpu, field, field_value);
6020 }
6021
6022 vmcs_clear(shadow_vmcs);
6023 vmcs_load(vmx->loaded_vmcs->vmcs);
6024}
6025
c3114420
AG		 6026static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6027{
c2bae893
MK		 6028 const unsigned long *fields[] = {
6029 shadow_read_write_fields,
6030 shadow_read_only_fields
c3114420 6031 };
c2bae893 6032 const int max_fields[] = {
c3114420
AG		 6033 max_shadow_read_write_fields,
6034 max_shadow_read_only_fields
6035 };
6036 int i, q;
6037 unsigned long field;
6038 u64 field_value = 0;
6039 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6040
6041 vmcs_load(shadow_vmcs);
6042
c2bae893 6043 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6044 for (i = 0; i < max_fields[q]; i++) {
6045 field = fields[q][i];
6046 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6047
6048 switch (vmcs_field_type(field)) {
6049 case VMCS_FIELD_TYPE_U16:
6050 vmcs_write16(field, (u16)field_value);
6051 break;
6052 case VMCS_FIELD_TYPE_U32:
6053 vmcs_write32(field, (u32)field_value);
6054 break;
6055 case VMCS_FIELD_TYPE_U64:
6056 vmcs_write64(field, (u64)field_value);
6057 break;
6058 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6059 vmcs_writel(field, (long)field_value);
6060 break;
6061 }
6062 }
6063 }
6064
6065 vmcs_clear(shadow_vmcs);
6066 vmcs_load(vmx->loaded_vmcs->vmcs);
6067}
6068
49f705c5
NHE		 6069/*
6070 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6071 * used before) all generate the same failure when it is missing.
6072 */
6073static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6074{
6075 struct vcpu_vmx *vmx = to_vmx(vcpu);
6076 if (vmx->nested.current_vmptr == -1ull) {
6077 nested_vmx_failInvalid(vcpu);
6078 skip_emulated_instruction(vcpu);
6079 return 0;
6080 }
6081 return 1;
6082}
6083
6084static int handle_vmread(struct kvm_vcpu *vcpu)
6085{
6086 unsigned long field;
6087 u64 field_value;
6088 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6089 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6090 gva_t gva = 0;
6091
6092 if (!nested_vmx_check_permission(vcpu) ||
6093 !nested_vmx_check_vmcs12(vcpu))
6094 return 1;
6095
6096 /* Decode instruction info and find the field to read */
6097 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6098 /* Read the field, zero-extended to a u64 field_value */
6099 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6100 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6101 skip_emulated_instruction(vcpu);
6102 return 1;
6103 }
6104 /*
6105 * Now copy part of this value to register or memory, as requested.
6106 * Note that the number of bits actually copied is 32 or 64 depending
6107 * on the guest's mode (32 or 64 bit), not on the given field's length.
6108 */
6109 if (vmx_instruction_info & (1u << 10)) {
6110 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6111 field_value);
6112 } else {
6113 if (get_vmx_mem_address(vcpu, exit_qualification,
6114 vmx_instruction_info, &gva))
6115 return 1;
6116 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6117 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6118 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6119 }
6120
6121 nested_vmx_succeed(vcpu);
6122 skip_emulated_instruction(vcpu);
6123 return 1;
6124}
6125
6126
6127static int handle_vmwrite(struct kvm_vcpu *vcpu)
6128{
6129 unsigned long field;
6130 gva_t gva;
6131 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6132 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6133 /* The value to write might be 32 or 64 bits, depending on L1's long
6134 * mode, and eventually we need to write that into a field of several
6135 * possible lengths. The code below first zero-extends the value to 64
6136 * bit (field_value), and then copies only the approriate number of
6137 * bits into the vmcs12 field.
6138 */
6139 u64 field_value = 0;
6140 struct x86_exception e;
6141
6142 if (!nested_vmx_check_permission(vcpu) ||
6143 !nested_vmx_check_vmcs12(vcpu))
6144 return 1;
6145
6146 if (vmx_instruction_info & (1u << 10))
6147 field_value = kvm_register_read(vcpu,
6148 (((vmx_instruction_info) >> 3) & 0xf));
6149 else {
6150 if (get_vmx_mem_address(vcpu, exit_qualification,
6151 vmx_instruction_info, &gva))
6152 return 1;
6153 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6154 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6155 kvm_inject_page_fault(vcpu, &e);
6156 return 1;
6157 }
6158 }
6159
6160
6161 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6162 if (vmcs_field_readonly(field)) {
6163 nested_vmx_failValid(vcpu,
6164 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6165 skip_emulated_instruction(vcpu);
6166 return 1;
6167 }
6168
20b97fea 6169 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6170 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6171 skip_emulated_instruction(vcpu);
6172 return 1;
6173 }
6174
6175 nested_vmx_succeed(vcpu);
6176 skip_emulated_instruction(vcpu);
6177 return 1;
6178}
6179
63846663
NHE		 6180/* Emulate the VMPTRLD instruction */
6181static int handle_vmptrld(struct kvm_vcpu *vcpu)
6182{
6183 struct vcpu_vmx *vmx = to_vmx(vcpu);
6184 gva_t gva;
6185 gpa_t vmptr;
6186 struct x86_exception e;
8a1b9dd0 6187 u32 exec_control;
63846663
NHE		 6188
6189 if (!nested_vmx_check_permission(vcpu))
6190 return 1;
6191
6192 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6193 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6194 return 1;
6195
6196 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6197 sizeof(vmptr), &e)) {
6198 kvm_inject_page_fault(vcpu, &e);
6199 return 1;
6200 }
6201
6202 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6203 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6204 skip_emulated_instruction(vcpu);
6205 return 1;
6206 }
6207
6208 if (vmx->nested.current_vmptr != vmptr) {
6209 struct vmcs12 *new_vmcs12;
6210 struct page *page;
6211 page = nested_get_page(vcpu, vmptr);
6212 if (page == NULL) {
6213 nested_vmx_failInvalid(vcpu);
6214 skip_emulated_instruction(vcpu);
6215 return 1;
6216 }
6217 new_vmcs12 = kmap(page);
6218 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6219 kunmap(page);
6220 nested_release_page_clean(page);
6221 nested_vmx_failValid(vcpu,
6222 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6223 skip_emulated_instruction(vcpu);
6224 return 1;
6225 }
e7953d7f
AG		 6226 if (vmx->nested.current_vmptr != -1ull)
6227 nested_release_vmcs12(vmx);
63846663
NHE		 6228
6229 vmx->nested.current_vmptr = vmptr;
6230 vmx->nested.current_vmcs12 = new_vmcs12;
6231 vmx->nested.current_vmcs12_page = page;
012f83cb 6232 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6233 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6234 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6235 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6236 vmcs_write64(VMCS_LINK_POINTER,
6237 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6238 vmx->nested.sync_shadow_vmcs = true;
6239 }
63846663
NHE		 6240 }
6241
6242 nested_vmx_succeed(vcpu);
6243 skip_emulated_instruction(vcpu);
6244 return 1;
6245}
6246
6a4d7550
NHE		 6247/* Emulate the VMPTRST instruction */
6248static int handle_vmptrst(struct kvm_vcpu *vcpu)
6249{
6250 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6251 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6252 gva_t vmcs_gva;
6253 struct x86_exception e;
6254
6255 if (!nested_vmx_check_permission(vcpu))
6256 return 1;
6257
6258 if (get_vmx_mem_address(vcpu, exit_qualification,
6259 vmx_instruction_info, &vmcs_gva))
6260 return 1;
6261 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6262 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6263 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6264 sizeof(u64), &e)) {
6265 kvm_inject_page_fault(vcpu, &e);
6266 return 1;
6267 }
6268 nested_vmx_succeed(vcpu);
6269 skip_emulated_instruction(vcpu);
6270 return 1;
6271}
6272
6aa8b732
AK		 6273/*
6274 * The exit handlers return 1 if the exit was handled fully and guest execution
6275 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6276 * to be done to userspace and return 0.
6277 */
772e0318 6278static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6279 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6280 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6281 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6282 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6283 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6284 [EXIT_REASON_CR_ACCESS] = handle_cr,
6285 [EXIT_REASON_DR_ACCESS] = handle_dr,
6286 [EXIT_REASON_CPUID] = handle_cpuid,
6287 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6288 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6289 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6290 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6291 [EXIT_REASON_INVD] = handle_invd,
a7052897 6292 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6293 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6294 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6295 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6296 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6297 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6298 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6299 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6300 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6301 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6302 [EXIT_REASON_VMOFF] = handle_vmoff,
6303 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6304 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6305 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6306 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6307 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6308 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6309 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6310 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6311 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6312 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6313 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6314 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6315 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6316 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 6317};
6318
6319static const int kvm_vmx_max_exit_handlers =
50a3485c 6320 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6321
908a7bdd
JK		 6322static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6323 struct vmcs12 *vmcs12)
6324{
6325 unsigned long exit_qualification;
6326 gpa_t bitmap, last_bitmap;
6327 unsigned int port;
6328 int size;
6329 u8 b;
6330
6331 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6332 return 1;
6333
6334 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6335 return 0;
6336
6337 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6338
6339 port = exit_qualification >> 16;
6340 size = (exit_qualification & 7) + 1;
6341
6342 last_bitmap = (gpa_t)-1;
6343 b = -1;
6344
6345 while (size > 0) {
6346 if (port < 0x8000)
6347 bitmap = vmcs12->io_bitmap_a;
6348 else if (port < 0x10000)
6349 bitmap = vmcs12->io_bitmap_b;
6350 else
6351 return 1;
6352 bitmap += (port & 0x7fff) / 8;
6353
6354 if (last_bitmap != bitmap)
6355 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6356 return 1;
6357 if (b & (1 << (port & 7)))
6358 return 1;
6359
6360 port++;
6361 size--;
6362 last_bitmap = bitmap;
6363 }
6364
6365 return 0;
6366}
6367
644d711a
NHE		 6368/*
6369 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6370 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6371 * disinterest in the current event (read or write a specific MSR) by using an
6372 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6373 */
6374static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6375 struct vmcs12 *vmcs12, u32 exit_reason)
6376{
6377 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6378 gpa_t bitmap;
6379
cbd29cb6 6380 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6381 return 1;
6382
6383 /*
6384 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6385 * for the four combinations of read/write and low/high MSR numbers.
6386 * First we need to figure out which of the four to use:
6387 */
6388 bitmap = vmcs12->msr_bitmap;
6389 if (exit_reason == EXIT_REASON_MSR_WRITE)
6390 bitmap += 2048;
6391 if (msr_index >= 0xc0000000) {
6392 msr_index -= 0xc0000000;
6393 bitmap += 1024;
6394 }
6395
6396 /* Then read the msr_index'th bit from this bitmap: */
6397 if (msr_index < 1024*8) {
6398 unsigned char b;
bd31a7f5
JK		 6399 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6400 return 1;
644d711a
NHE		 6401 return 1 & (b >> (msr_index & 7));
6402 } else
6403 return 1; /* let L1 handle the wrong parameter */
6404}
6405
6406/*
6407 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6408 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6409 * intercept (via guest_host_mask etc.) the current event.
6410 */
6411static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6412 struct vmcs12 *vmcs12)
6413{
6414 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6415 int cr = exit_qualification & 15;
6416 int reg = (exit_qualification >> 8) & 15;
6417 unsigned long val = kvm_register_read(vcpu, reg);
6418
6419 switch ((exit_qualification >> 4) & 3) {
6420 case 0: /* mov to cr */
6421 switch (cr) {
6422 case 0:
6423 if (vmcs12->cr0_guest_host_mask &
6424 (val ^ vmcs12->cr0_read_shadow))
6425 return 1;
6426 break;
6427 case 3:
6428 if ((vmcs12->cr3_target_count >= 1 &&
6429 vmcs12->cr3_target_value0 == val) ||
6430 (vmcs12->cr3_target_count >= 2 &&
6431 vmcs12->cr3_target_value1 == val) ||
6432 (vmcs12->cr3_target_count >= 3 &&
6433 vmcs12->cr3_target_value2 == val) ||
6434 (vmcs12->cr3_target_count >= 4 &&
6435 vmcs12->cr3_target_value3 == val))
6436 return 0;
6437 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6438 return 1;
6439 break;
6440 case 4:
6441 if (vmcs12->cr4_guest_host_mask &
6442 (vmcs12->cr4_read_shadow ^ val))
6443 return 1;
6444 break;
6445 case 8:
6446 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6447 return 1;
6448 break;
6449 }
6450 break;
6451 case 2: /* clts */
6452 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6453 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6454 return 1;
6455 break;
6456 case 1: /* mov from cr */
6457 switch (cr) {
6458 case 3:
6459 if (vmcs12->cpu_based_vm_exec_control &
6460 CPU_BASED_CR3_STORE_EXITING)
6461 return 1;
6462 break;
6463 case 8:
6464 if (vmcs12->cpu_based_vm_exec_control &
6465 CPU_BASED_CR8_STORE_EXITING)
6466 return 1;
6467 break;
6468 }
6469 break;
6470 case 3: /* lmsw */
6471 /*
6472 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6473 * cr0. Other attempted changes are ignored, with no exit.
6474 */
6475 if (vmcs12->cr0_guest_host_mask & 0xe &
6476 (val ^ vmcs12->cr0_read_shadow))
6477 return 1;
6478 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6479 !(vmcs12->cr0_read_shadow & 0x1) &&
6480 (val & 0x1))
6481 return 1;
6482 break;
6483 }
6484 return 0;
6485}
6486
6487/*
6488 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6489 * should handle it ourselves in L0 (and then continue L2). Only call this
6490 * when in is_guest_mode (L2).
6491 */
6492static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6493{
644d711a
NHE		 6494 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6495 struct vcpu_vmx *vmx = to_vmx(vcpu);
6496 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6497 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6498
6499 if (vmx->nested.nested_run_pending)
6500 return 0;
6501
6502 if (unlikely(vmx->fail)) {
bd80158a
JK		 6503 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6504 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6505 return 1;
6506 }
6507
6508 switch (exit_reason) {
6509 case EXIT_REASON_EXCEPTION_NMI:
6510 if (!is_exception(intr_info))
6511 return 0;
6512 else if (is_page_fault(intr_info))
6513 return enable_ept;
6514 return vmcs12->exception_bitmap &
6515 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6516 case EXIT_REASON_EXTERNAL_INTERRUPT:
6517 return 0;
6518 case EXIT_REASON_TRIPLE_FAULT:
6519 return 1;
6520 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6521 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6522 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6523 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6524 case EXIT_REASON_TASK_SWITCH:
6525 return 1;
6526 case EXIT_REASON_CPUID:
6527 return 1;
6528 case EXIT_REASON_HLT:
6529 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6530 case EXIT_REASON_INVD:
6531 return 1;
6532 case EXIT_REASON_INVLPG:
6533 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6534 case EXIT_REASON_RDPMC:
6535 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6536 case EXIT_REASON_RDTSC:
6537 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6538 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6539 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6540 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6541 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6542 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6543 /*
6544 * VMX instructions trap unconditionally. This allows L1 to
6545 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6546 */
6547 return 1;
6548 case EXIT_REASON_CR_ACCESS:
6549 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6550 case EXIT_REASON_DR_ACCESS:
6551 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6552 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6553 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6554 case EXIT_REASON_MSR_READ:
6555 case EXIT_REASON_MSR_WRITE:
6556 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6557 case EXIT_REASON_INVALID_STATE:
6558 return 1;
6559 case EXIT_REASON_MWAIT_INSTRUCTION:
6560 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6561 case EXIT_REASON_MONITOR_INSTRUCTION:
6562 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6563 case EXIT_REASON_PAUSE_INSTRUCTION:
6564 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6565 nested_cpu_has2(vmcs12,
6566 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6567 case EXIT_REASON_MCE_DURING_VMENTRY:
6568 return 0;
6569 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6570 return 1;
6571 case EXIT_REASON_APIC_ACCESS:
6572 return nested_cpu_has2(vmcs12,
6573 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6574 case EXIT_REASON_EPT_VIOLATION:
6575 case EXIT_REASON_EPT_MISCONFIG:
6576 return 0;
0238ea91
JK		 6577 case EXIT_REASON_PREEMPTION_TIMER:
6578 return vmcs12->pin_based_vm_exec_control &
6579 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6580 case EXIT_REASON_WBINVD:
6581 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6582 case EXIT_REASON_XSETBV:
6583 return 1;
6584 default:
6585 return 1;
6586 }
6587}
6588
586f9607
AK		 6589static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6590{
6591 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6592 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6593}
6594
6aa8b732
AK		 6595/*
6596 * The guest has exited. See if we can fix it or if we need userspace
6597 * assistance.
6598 */
851ba692 6599static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6600{
29bd8a78 6601 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6602 u32 exit_reason = vmx->exit_reason;
1155f76a 6603 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6604
80ced186 6605 /* If guest state is invalid, start emulating */
14168786 6606 if (vmx->emulation_required)
80ced186 6607 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6608
b6f1250e
NHE		 6609 /*
6610 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6611 * we did not inject a still-pending event to L1 now because of
6612 * nested_run_pending, we need to re-enable this bit.
6613 */
6614 if (vmx->nested.nested_run_pending)
6615 kvm_make_request(KVM_REQ_EVENT, vcpu);
6616
509c75ea
NHE		 6617 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6618 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6619 vmx->nested.nested_run_pending = 1;
6620 else
6621 vmx->nested.nested_run_pending = 0;
6622
6623 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6624 nested_vmx_vmexit(vcpu);
6625 return 1;
6626 }
6627
5120702e
MG		 6628 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6629 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6630 vcpu->run->fail_entry.hardware_entry_failure_reason
6631 = exit_reason;
6632 return 0;
6633 }
6634
29bd8a78 6635 if (unlikely(vmx->fail)) {
851ba692
AK		 6636 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6637 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6638 = vmcs_read32(VM_INSTRUCTION_ERROR);
6639 return 0;
6640 }
6aa8b732 6641
b9bf6882
XG		 6642 /*
6643 * Note:
6644 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6645 * delivery event since it indicates guest is accessing MMIO.
6646 * The vm-exit can be triggered again after return to guest that
6647 * will cause infinite loop.
6648 */
d77c26fc 6649 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6650 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6651 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6652 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6653 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6654 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6655 vcpu->run->internal.ndata = 2;
6656 vcpu->run->internal.data[0] = vectoring_info;
6657 vcpu->run->internal.data[1] = exit_reason;
6658 return 0;
6659 }
3b86cd99 6660
644d711a
NHE		 6661 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6662 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6663 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6664 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6665 vmx->soft_vnmi_blocked = 0;
3b86cd99 6666 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6667 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6668 /*
6669 * This CPU don't support us in finding the end of an
6670 * NMI-blocked window if the guest runs with IRQs
6671 * disabled. So we pull the trigger after 1 s of
6672 * futile waiting, but inform the user about this.
6673 */
6674 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6675 "state on VCPU %d after 1 s timeout\n",
6676 __func__, vcpu->vcpu_id);
6677 vmx->soft_vnmi_blocked = 0;
3b86cd99 6678 }
3b86cd99
JK		 6679 }
6680
6aa8b732
AK		 6681 if (exit_reason < kvm_vmx_max_exit_handlers
6682 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6683 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6684 else {
851ba692
AK		 6685 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6686 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6687 }
6688 return 0;
6689}
6690
95ba8273 6691static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6692{
95ba8273 6693 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6694 vmcs_write32(TPR_THRESHOLD, 0);
6695 return;
6696 }
6697
95ba8273 6698 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6699}
6700
8d14695f
YZ		 6701static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6702{
6703 u32 sec_exec_control;
6704
6705 /*
6706 * There is not point to enable virtualize x2apic without enable
6707 * apicv
6708 */
c7c9c56c
YZ		 6709 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6710 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6711 return;
6712
6713 if (!vm_need_tpr_shadow(vcpu->kvm))
6714 return;
6715
6716 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6717
6718 if (set) {
6719 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6720 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6721 } else {
6722 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6723 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6724 }
6725 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6726
6727 vmx_set_msr_bitmap(vcpu);
6728}
6729
c7c9c56c
YZ		 6730static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6731{
6732 u16 status;
6733 u8 old;
6734
6735 if (!vmx_vm_has_apicv(kvm))
6736 return;
6737
6738 if (isr == -1)
6739 isr = 0;
6740
6741 status = vmcs_read16(GUEST_INTR_STATUS);
6742 old = status >> 8;
6743 if (isr != old) {
6744 status &= 0xff;
6745 status |= isr << 8;
6746 vmcs_write16(GUEST_INTR_STATUS, status);
6747 }
6748}
6749
6750static void vmx_set_rvi(int vector)
6751{
6752 u16 status;
6753 u8 old;
6754
6755 status = vmcs_read16(GUEST_INTR_STATUS);
6756 old = (u8)status & 0xff;
6757 if ((u8)vector != old) {
6758 status &= ~0xff;
6759 status |= (u8)vector;
6760 vmcs_write16(GUEST_INTR_STATUS, status);
6761 }
6762}
6763
6764static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6765{
6766 if (max_irr == -1)
6767 return;
6768
6769 vmx_set_rvi(max_irr);
6770}
6771
6772static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6773{
3d81bc7e
YZ		 6774 if (!vmx_vm_has_apicv(vcpu->kvm))
6775 return;
6776
c7c9c56c
YZ		 6777 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6778 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6779 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6780 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6781}
6782
51aa01d1 6783static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6784{
00eba012
AK		 6785 u32 exit_intr_info;
6786
6787 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6788 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6789 return;
6790
c5ca8e57 6791 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6792 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6793
6794 /* Handle machine checks before interrupts are enabled */
00eba012 6795 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6796 kvm_machine_check();
6797
20f65983 6798 /* We need to handle NMIs before interrupts are enabled */
00eba012 6799 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6800 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6801 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6802 asm("int $2");
ff9d07a0
ZY		 6803 kvm_after_handle_nmi(&vmx->vcpu);
6804 }
51aa01d1 6805}
20f65983 6806
a547c6db
YZ		 6807static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6808{
6809 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6810
6811 /*
6812 * If external interrupt exists, IF bit is set in rflags/eflags on the
6813 * interrupt stack frame, and interrupt will be enabled on a return
6814 * from interrupt handler.
6815 */
6816 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6817 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6818 unsigned int vector;
6819 unsigned long entry;
6820 gate_desc *desc;
6821 struct vcpu_vmx *vmx = to_vmx(vcpu);
6822#ifdef CONFIG_X86_64
6823 unsigned long tmp;
6824#endif
6825
6826 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6827 desc = (gate_desc *)vmx->host_idt_base + vector;
6828 entry = gate_offset(*desc);
6829 asm volatile(
6830#ifdef CONFIG_X86_64
6831 "mov %%" _ASM_SP ", %[sp]\n\t"
6832 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6833 "push $%c[ss]\n\t"
6834 "push %[sp]\n\t"
6835#endif
6836 "pushf\n\t"
6837 "orl $0x200, (%%" _ASM_SP ")\n\t"
6838 __ASM_SIZE(push) " $%c[cs]\n\t"
6839 "call *%[entry]\n\t"
6840 :
6841#ifdef CONFIG_X86_64
6842 [sp]"=&r"(tmp)
6843#endif
6844 :
6845 [entry]"r"(entry),
6846 [ss]"i"(__KERNEL_DS),
6847 [cs]"i"(__KERNEL_CS)
6848 );
6849 } else
6850 local_irq_enable();
6851}
6852
51aa01d1
AK		 6853static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6854{
c5ca8e57 6855 u32 exit_intr_info;
51aa01d1
AK		 6856 bool unblock_nmi;
6857 u8 vector;
6858 bool idtv_info_valid;
6859
6860 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6861
cf393f75 6862 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6863 if (vmx->nmi_known_unmasked)
6864 return;
c5ca8e57
AK		 6865 /*
6866 * Can't use vmx->exit_intr_info since we're not sure what
6867 * the exit reason is.
6868 */
6869 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6870 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6871 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6872 /*
7b4a25cb 6873 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6874 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6875 * a guest IRET fault.
7b4a25cb
GN		 6876 * SDM 3: 23.2.2 (September 2008)
6877 * Bit 12 is undefined in any of the following cases:
6878 * If the VM exit sets the valid bit in the IDT-vectoring
6879 * information field.
6880 * If the VM exit is due to a double fault.
cf393f75 6881 */
7b4a25cb
GN		 6882 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6883 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6884 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6885 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6886 else
6887 vmx->nmi_known_unmasked =
6888 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6889 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6890 } else if (unlikely(vmx->soft_vnmi_blocked))
6891 vmx->vnmi_blocked_time +=
6892 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6893}
6894
3ab66e8a 6895static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6896 u32 idt_vectoring_info,
6897 int instr_len_field,
6898 int error_code_field)
51aa01d1 6899{
51aa01d1
AK		 6900 u8 vector;
6901 int type;
6902 bool idtv_info_valid;
6903
6904 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6905
3ab66e8a
JK		 6906 vcpu->arch.nmi_injected = false;
6907 kvm_clear_exception_queue(vcpu);
6908 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6909
6910 if (!idtv_info_valid)
6911 return;
6912
3ab66e8a 6913 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6914
668f612f
AK		 6915 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6916 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6917
64a7ec06 6918 switch (type) {
37b96e98 6919 case INTR_TYPE_NMI_INTR:
3ab66e8a 6920 vcpu->arch.nmi_injected = true;
668f612f 6921 /*
7b4a25cb 6922 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6923 * Clear bit "block by NMI" before VM entry if a NMI
6924 * delivery faulted.
668f612f 6925 */
3ab66e8a 6926 vmx_set_nmi_mask(vcpu, false);
37b96e98 6927 break;
37b96e98 6928 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6929 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6930 /* fall through */
6931 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6932 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6933 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6934 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6935 } else
3ab66e8a 6936 kvm_queue_exception(vcpu, vector);
37b96e98 6937 break;
66fd3f7f 6938 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6939 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6940 /* fall through */
37b96e98 6941 case INTR_TYPE_EXT_INTR:
3ab66e8a 6942 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6943 break;
6944 default:
6945 break;
f7d9238f 6946 }
cf393f75
AK		 6947}
6948
83422e17
AK		 6949static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6950{
3ab66e8a 6951 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6952 VM_EXIT_INSTRUCTION_LEN,
6953 IDT_VECTORING_ERROR_CODE);
6954}
6955
b463a6f7
AK		 6956static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6957{
3ab66e8a 6958 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6959 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6960 VM_ENTRY_INSTRUCTION_LEN,
6961 VM_ENTRY_EXCEPTION_ERROR_CODE);
6962
6963 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6964}
6965
d7cd9796
GN		 6966static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6967{
6968 int i, nr_msrs;
6969 struct perf_guest_switch_msr *msrs;
6970
6971 msrs = perf_guest_get_msrs(&nr_msrs);
6972
6973 if (!msrs)
6974 return;
6975
6976 for (i = 0; i < nr_msrs; i++)
6977 if (msrs[i].host == msrs[i].guest)
6978 clear_atomic_switch_msr(vmx, msrs[i].msr);
6979 else
6980 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6981 msrs[i].host);
6982}
6983
a3b5ba49 6984static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6985{
a2fa3e9f 6986 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6987 unsigned long debugctlmsr;
104f226b
AK		 6988
6989 /* Record the guest's net vcpu time for enforced NMI injections. */
6990 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6991 vmx->entry_time = ktime_get();
6992
6993 /* Don't enter VMX if guest state is invalid, let the exit handler
6994 start emulation until we arrive back to a valid state */
14168786 6995 if (vmx->emulation_required)
104f226b
AK		 6996 return;
6997
012f83cb
AG		 6998 if (vmx->nested.sync_shadow_vmcs) {
6999 copy_vmcs12_to_shadow(vmx);
7000 vmx->nested.sync_shadow_vmcs = false;
7001 }
7002
104f226b
AK		 7003 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7004 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7005 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7006 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7007
7008 /* When single-stepping over STI and MOV SS, we must clear the
7009 * corresponding interruptibility bits in the guest state. Otherwise
7010 * vmentry fails as it then expects bit 14 (BS) in pending debug
7011 * exceptions being set, but that's not correct for the guest debugging
7012 * case. */
7013 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7014 vmx_set_interrupt_shadow(vcpu, 0);
7015
d7cd9796 7016 atomic_switch_perf_msrs(vmx);
2a7921b7 7017 debugctlmsr = get_debugctlmsr();
d7cd9796 7018
d462b819 7019 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7020 asm(
6aa8b732 7021 /* Store host registers */
b188c81f
AK		 7022 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7023 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7024 "push %%" _ASM_CX " \n\t"
7025 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7026 "je 1f \n\t"
b188c81f 7027 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7028 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7029 "1: \n\t"
d3edefc0 7030 /* Reload cr2 if changed */
b188c81f
AK		 7031 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7032 "mov %%cr2, %%" _ASM_DX " \n\t"
7033 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7034 "je 2f \n\t"
b188c81f 7035 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7036 "2: \n\t"
6aa8b732 7037 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7038 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7039 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7040 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7041 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7042 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7043 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7044 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7045 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7046#ifdef CONFIG_X86_64
e08aa78a
AK		 7047 "mov %c[r8](%0), %%r8 \n\t"
7048 "mov %c[r9](%0), %%r9 \n\t"
7049 "mov %c[r10](%0), %%r10 \n\t"
7050 "mov %c[r11](%0), %%r11 \n\t"
7051 "mov %c[r12](%0), %%r12 \n\t"
7052 "mov %c[r13](%0), %%r13 \n\t"
7053 "mov %c[r14](%0), %%r14 \n\t"
7054 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7055#endif
b188c81f 7056 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7057
6aa8b732 7058 /* Enter guest mode */
83287ea4 7059 "jne 1f \n\t"
4ecac3fd 7060 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7061 "jmp 2f \n\t"
7062 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7063 "2: "
6aa8b732 7064 /* Save guest registers, load host registers, keep flags */
b188c81f 7065 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7066 "pop %0 \n\t"
b188c81f
AK		 7067 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7068 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7069 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7070 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7071 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7072 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7073 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7074#ifdef CONFIG_X86_64
e08aa78a
AK		 7075 "mov %%r8, %c[r8](%0) \n\t"
7076 "mov %%r9, %c[r9](%0) \n\t"
7077 "mov %%r10, %c[r10](%0) \n\t"
7078 "mov %%r11, %c[r11](%0) \n\t"
7079 "mov %%r12, %c[r12](%0) \n\t"
7080 "mov %%r13, %c[r13](%0) \n\t"
7081 "mov %%r14, %c[r14](%0) \n\t"
7082 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7083#endif
b188c81f
AK		 7084 "mov %%cr2, %%" _ASM_AX " \n\t"
7085 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7086
b188c81f 7087 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7088 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7089 ".pushsection .rodata \n\t"
7090 ".global vmx_return \n\t"
7091 "vmx_return: " _ASM_PTR " 2b \n\t"
7092 ".popsection"
e08aa78a 7093 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7094 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7095 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7096 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7097 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7098 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7099 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7100 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7101 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7102 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7103 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7104#ifdef CONFIG_X86_64
ad312c7c
ZX		 7105 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7106 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7107 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7108 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7109 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7110 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7111 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7112 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7113#endif
40712fae
AK		 7114 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7115 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7116 : "cc", "memory"
7117#ifdef CONFIG_X86_64
b188c81f 7118 , "rax", "rbx", "rdi", "rsi"
c2036300 7119 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7120#else
7121 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7122#endif
7123 );
6aa8b732 7124
2a7921b7
GN		 7125 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7126 if (debugctlmsr)
7127 update_debugctlmsr(debugctlmsr);
7128
aa67f609
AK		 7129#ifndef CONFIG_X86_64
7130 /*
7131 * The sysexit path does not restore ds/es, so we must set them to
7132 * a reasonable value ourselves.
7133 *
7134 * We can't defer this to vmx_load_host_state() since that function
7135 * may be executed in interrupt context, which saves and restore segments
7136 * around it, nullifying its effect.
7137 */
7138 loadsegment(ds, __USER_DS);
7139 loadsegment(es, __USER_DS);
7140#endif
7141
6de4f3ad 7142 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7143 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7144 | (1 << VCPU_EXREG_CPL)
aff48baa 7145 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7146 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7147 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7148 vcpu->arch.regs_dirty = 0;
7149
1155f76a
AK		 7150 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7151
d462b819 7152 vmx->loaded_vmcs->launched = 1;
1b6269db 7153
51aa01d1 7154 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7155 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7156
7157 vmx_complete_atomic_exit(vmx);
7158 vmx_recover_nmi_blocking(vmx);
cf393f75 7159 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7160}
7161
6aa8b732
AK		 7162static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7163{
fb3f0f51
RR		 7164 struct vcpu_vmx *vmx = to_vmx(vcpu);
7165
cdbecfc3 7166 free_vpid(vmx);
ec378aee 7167 free_nested(vmx);
d462b819 7168 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7169 kfree(vmx->guest_msrs);
7170 kvm_vcpu_uninit(vcpu);
a4770347 7171 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7172}
7173
fb3f0f51 7174static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7175{
fb3f0f51 7176 int err;
c16f862d 7177 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7178 int cpu;
6aa8b732 7179
a2fa3e9f 7180 if (!vmx)
fb3f0f51
RR		 7181 return ERR_PTR(-ENOMEM);
7182
2384d2b3
SY		 7183 allocate_vpid(vmx);
7184
fb3f0f51
RR		 7185 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7186 if (err)
7187 goto free_vcpu;
965b58a5 7188
a2fa3e9f 7189 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7190 err = -ENOMEM;
fb3f0f51 7191 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7192 goto uninit_vcpu;
7193 }
965b58a5 7194
d462b819
NHE		 7195 vmx->loaded_vmcs = &vmx->vmcs01;
7196 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7197 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7198 goto free_msrs;
d462b819
NHE		 7199 if (!vmm_exclusive)
7200 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7201 loaded_vmcs_init(vmx->loaded_vmcs);
7202 if (!vmm_exclusive)
7203 kvm_cpu_vmxoff();
a2fa3e9f 7204
15ad7146
AK		 7205 cpu = get_cpu();
7206 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7207 vmx->vcpu.cpu = cpu;
8b9cf98c 7208 err = vmx_vcpu_setup(vmx);
fb3f0f51 7209 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7210 put_cpu();
fb3f0f51
RR		 7211 if (err)
7212 goto free_vmcs;
a63cb560 7213 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7214 err = alloc_apic_access_page(kvm);
7215 if (err)
5e4a0b3c 7216 goto free_vmcs;
a63cb560 7217 }
fb3f0f51 7218
b927a3ce
SY		 7219 if (enable_ept) {
7220 if (!kvm->arch.ept_identity_map_addr)
7221 kvm->arch.ept_identity_map_addr =
7222 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7223 err = -ENOMEM;
b7ebfb05
SY		 7224 if (alloc_identity_pagetable(kvm) != 0)
7225 goto free_vmcs;
93ea5388
GN		 7226 if (!init_rmode_identity_map(kvm))
7227 goto free_vmcs;
b927a3ce 7228 }
b7ebfb05 7229
a9d30f33
NHE		 7230 vmx->nested.current_vmptr = -1ull;
7231 vmx->nested.current_vmcs12 = NULL;
7232
fb3f0f51
RR		 7233 return &vmx->vcpu;
7234
7235free_vmcs:
5f3fbc34 7236 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7237free_msrs:
fb3f0f51
RR		 7238 kfree(vmx->guest_msrs);
7239uninit_vcpu:
7240 kvm_vcpu_uninit(&vmx->vcpu);
7241free_vcpu:
cdbecfc3 7242 free_vpid(vmx);
a4770347 7243 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7244 return ERR_PTR(err);
6aa8b732
AK		 7245}
7246
002c7f7c
YS		 7247static void __init vmx_check_processor_compat(void *rtn)
7248{
7249 struct vmcs_config vmcs_conf;
7250
7251 *(int *)rtn = 0;
7252 if (setup_vmcs_config(&vmcs_conf) < 0)
7253 *(int *)rtn = -EIO;
7254 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7255 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7256 smp_processor_id());
7257 *(int *)rtn = -EIO;
7258 }
7259}
7260
67253af5
SY		 7261static int get_ept_level(void)
7262{
7263 return VMX_EPT_DEFAULT_GAW + 1;
7264}
7265
4b12f0de 7266static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7267{
4b12f0de
SY		 7268 u64 ret;
7269
522c68c4
SY		 7270 /* For VT-d and EPT combination
7271 * 1. MMIO: always map as UC
7272 * 2. EPT with VT-d:
7273 * a. VT-d without snooping control feature: can't guarantee the
7274 * result, try to trust guest.
7275 * b. VT-d with snooping control feature: snooping control feature of
7276 * VT-d engine can guarantee the cache correctness. Just set it
7277 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7278 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7279 * consistent with host MTRR
7280 */
4b12f0de
SY		 7281 if (is_mmio)
7282 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7283 else if (vcpu->kvm->arch.iommu_domain &&
7284 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7285 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7286 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7287 else
522c68c4 7288 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7289 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7290
7291 return ret;
64d4d521
SY		 7292}
7293
17cc3935 7294static int vmx_get_lpage_level(void)
344f414f 7295{
878403b7
SY		 7296 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7297 return PT_DIRECTORY_LEVEL;
7298 else
7299 /* For shadow and EPT supported 1GB page */
7300 return PT_PDPE_LEVEL;
344f414f
JR		 7301}
7302
0e851880
SY		 7303static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7304{
4e47c7a6
SY		 7305 struct kvm_cpuid_entry2 *best;
7306 struct vcpu_vmx *vmx = to_vmx(vcpu);
7307 u32 exec_control;
7308
7309 vmx->rdtscp_enabled = false;
7310 if (vmx_rdtscp_supported()) {
7311 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7312 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7313 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7314 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7315 vmx->rdtscp_enabled = true;
7316 else {
7317 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7318 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7319 exec_control);
7320 }
7321 }
7322 }
ad756a16 7323
ad756a16
MJ		 7324 /* Exposing INVPCID only when PCID is exposed */
7325 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7326 if (vmx_invpcid_supported() &&
4f977045 7327 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7328 guest_cpuid_has_pcid(vcpu)) {
29282fde 7329 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7330 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7331 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7332 exec_control);
7333 } else {
29282fde
TI		 7334 if (cpu_has_secondary_exec_ctrls()) {
7335 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7336 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7337 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7338 exec_control);
7339 }
ad756a16 7340 if (best)
4f977045 7341 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7342 }
0e851880
SY		 7343}
7344
d4330ef2
JR		 7345static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7346{
7b8050f5
NHE		 7347 if (func == 1 && nested)
7348 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7349}
7350
fe3ef05c
NHE		 7351/*
7352 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7353 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7354 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7355 * guest in a way that will both be appropriate to L1's requests, and our
7356 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7357 * function also has additional necessary side-effects, like setting various
7358 * vcpu->arch fields.
7359 */
7360static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7361{
7362 struct vcpu_vmx *vmx = to_vmx(vcpu);
7363 u32 exec_control;
7364
7365 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7366 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7367 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7368 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7369 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7370 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7371 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7372 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7373 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7374 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7375 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7376 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7377 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7378 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7379 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7380 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7381 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7382 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7383 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7384 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7385 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7386 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7387 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7388 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7389 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7390 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7391 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7392 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7393 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7394 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7395 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7396 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7397 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7398 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7399 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7400 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7401
7402 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7403 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7404 vmcs12->vm_entry_intr_info_field);
7405 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7406 vmcs12->vm_entry_exception_error_code);
7407 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7408 vmcs12->vm_entry_instruction_len);
7409 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7410 vmcs12->guest_interruptibility_info);
fe3ef05c 7411 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7412 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7413 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7414 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7415 vmcs12->guest_pending_dbg_exceptions);
7416 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7417 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7418
7419 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7420
7421 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7422 (vmcs_config.pin_based_exec_ctrl |
7423 vmcs12->pin_based_vm_exec_control));
7424
0238ea91
JK		 7425 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7426 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7427 vmcs12->vmx_preemption_timer_value);
7428
fe3ef05c
NHE		 7429 /*
7430 * Whether page-faults are trapped is determined by a combination of
7431 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7432 * If enable_ept, L0 doesn't care about page faults and we should
7433 * set all of these to L1's desires. However, if !enable_ept, L0 does
7434 * care about (at least some) page faults, and because it is not easy
7435 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7436 * to exit on each and every L2 page fault. This is done by setting
7437 * MASK=MATCH=0 and (see below) EB.PF=1.
7438 * Note that below we don't need special code to set EB.PF beyond the
7439 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7440 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7441 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7442 *
7443 * A problem with this approach (when !enable_ept) is that L1 may be
7444 * injected with more page faults than it asked for. This could have
7445 * caused problems, but in practice existing hypervisors don't care.
7446 * To fix this, we will need to emulate the PFEC checking (on the L1
7447 * page tables), using walk_addr(), when injecting PFs to L1.
7448 */
7449 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7450 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7451 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7452 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7453
7454 if (cpu_has_secondary_exec_ctrls()) {
7455 u32 exec_control = vmx_secondary_exec_control(vmx);
7456 if (!vmx->rdtscp_enabled)
7457 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7458 /* Take the following fields only from vmcs12 */
7459 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7460 if (nested_cpu_has(vmcs12,
7461 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7462 exec_control |= vmcs12->secondary_vm_exec_control;
7463
7464 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7465 /*
7466 * Translate L1 physical address to host physical
7467 * address for vmcs02. Keep the page pinned, so this
7468 * physical address remains valid. We keep a reference
7469 * to it so we can release it later.
7470 */
7471 if (vmx->nested.apic_access_page) /* shouldn't happen */
7472 nested_release_page(vmx->nested.apic_access_page);
7473 vmx->nested.apic_access_page =
7474 nested_get_page(vcpu, vmcs12->apic_access_addr);
7475 /*
7476 * If translation failed, no matter: This feature asks
7477 * to exit when accessing the given address, and if it
7478 * can never be accessed, this feature won't do
7479 * anything anyway.
7480 */
7481 if (!vmx->nested.apic_access_page)
7482 exec_control &=
7483 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7484 else
7485 vmcs_write64(APIC_ACCESS_ADDR,
7486 page_to_phys(vmx->nested.apic_access_page));
7487 }
7488
7489 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7490 }
7491
7492
7493 /*
7494 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7495 * Some constant fields are set here by vmx_set_constant_host_state().
7496 * Other fields are different per CPU, and will be set later when
7497 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7498 */
a547c6db 7499 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7500
7501 /*
7502 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7503 * entry, but only if the current (host) sp changed from the value
7504 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7505 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7506 * here we just force the write to happen on entry.
7507 */
7508 vmx->host_rsp = 0;
7509
7510 exec_control = vmx_exec_control(vmx); /* L0's desires */
7511 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7512 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7513 exec_control &= ~CPU_BASED_TPR_SHADOW;
7514 exec_control |= vmcs12->cpu_based_vm_exec_control;
7515 /*
7516 * Merging of IO and MSR bitmaps not currently supported.
7517 * Rather, exit every time.
7518 */
7519 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7520 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7521 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7522
7523 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7524
7525 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7526 * bitwise-or of what L1 wants to trap for L2, and what we want to
7527 * trap. Note that CR0.TS also needs updating - we do this later.
7528 */
7529 update_exception_bitmap(vcpu);
7530 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7531 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7532
8049d651
NHE		 7533 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7534 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7535 * bits are further modified by vmx_set_efer() below.
7536 */
7537 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7538
7539 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7540 * emulated by vmx_set_efer(), below.
7541 */
7542 vmcs_write32(VM_ENTRY_CONTROLS,
7543 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7544 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7545 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7546
7547 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7548 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7549 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7550 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7551
7552
7553 set_cr4_guest_host_mask(vmx);
7554
27fc51b2
NHE		 7555 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7556 vmcs_write64(TSC_OFFSET,
7557 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7558 else
7559 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7560
7561 if (enable_vpid) {
7562 /*
7563 * Trivially support vpid by letting L2s share their parent
7564 * L1's vpid. TODO: move to a more elaborate solution, giving
7565 * each L2 its own vpid and exposing the vpid feature to L1.
7566 */
7567 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7568 vmx_flush_tlb(vcpu);
7569 }
7570
7571 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7572 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7573 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7574 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7575 else
7576 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7577 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7578 vmx_set_efer(vcpu, vcpu->arch.efer);
7579
7580 /*
7581 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7582 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7583 * The CR0_READ_SHADOW is what L2 should have expected to read given
7584 * the specifications by L1; It's not enough to take
7585 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7586 * have more bits than L1 expected.
7587 */
7588 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7589 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7590
7591 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7592 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7593
7594 /* shadow page tables on either EPT or shadow page tables */
7595 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7596 kvm_mmu_reset_context(vcpu);
7597
3633cfc3
NHE		 7598 /*
7599 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7600 */
7601 if (enable_ept) {
7602 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7603 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7604 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7605 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7606 }
7607
fe3ef05c
NHE		 7608 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7609 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7610}
7611
cd232ad0
NHE		 7612/*
7613 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7614 * for running an L2 nested guest.
7615 */
7616static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7617{
7618 struct vmcs12 *vmcs12;
7619 struct vcpu_vmx *vmx = to_vmx(vcpu);
7620 int cpu;
7621 struct loaded_vmcs *vmcs02;
384bb783 7622 bool ia32e;
cd232ad0
NHE		 7623
7624 if (!nested_vmx_check_permission(vcpu) ||
7625 !nested_vmx_check_vmcs12(vcpu))
7626 return 1;
7627
7628 skip_emulated_instruction(vcpu);
7629 vmcs12 = get_vmcs12(vcpu);
7630
012f83cb
AG		 7631 if (enable_shadow_vmcs)
7632 copy_shadow_to_vmcs12(vmx);
7633
7c177938
NHE		 7634 /*
7635 * The nested entry process starts with enforcing various prerequisites
7636 * on vmcs12 as required by the Intel SDM, and act appropriately when
7637 * they fail: As the SDM explains, some conditions should cause the
7638 * instruction to fail, while others will cause the instruction to seem
7639 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7640 * To speed up the normal (success) code path, we should avoid checking
7641 * for misconfigurations which will anyway be caught by the processor
7642 * when using the merged vmcs02.
7643 */
7644 if (vmcs12->launch_state == launch) {
7645 nested_vmx_failValid(vcpu,
7646 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7647 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7648 return 1;
7649 }
7650
26539bd0
PB		 7651 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7652 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7653 return 1;
7654 }
7655
7c177938
NHE		 7656 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7657 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7658 /*TODO: Also verify bits beyond physical address width are 0*/
7659 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7660 return 1;
7661 }
7662
7663 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7664 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7665 /*TODO: Also verify bits beyond physical address width are 0*/
7666 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7667 return 1;
7668 }
7669
7670 if (vmcs12->vm_entry_msr_load_count > 0 ||
7671 vmcs12->vm_exit_msr_load_count > 0 ||
7672 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7673 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7674 __func__);
7c177938
NHE		 7675 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7676 return 1;
7677 }
7678
7679 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7680 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7681 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7682 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7683 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7684 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7685 !vmx_control_verify(vmcs12->vm_exit_controls,
7686 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7687 !vmx_control_verify(vmcs12->vm_entry_controls,
7688 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7689 {
7690 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7691 return 1;
7692 }
7693
7694 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7695 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7696 nested_vmx_failValid(vcpu,
7697 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7698 return 1;
7699 }
7700
7701 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7702 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7703 nested_vmx_entry_failure(vcpu, vmcs12,
7704 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7705 return 1;
7706 }
7707 if (vmcs12->vmcs_link_pointer != -1ull) {
7708 nested_vmx_entry_failure(vcpu, vmcs12,
7709 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7710 return 1;
7711 }
7712
384bb783 7713 /*
cb0c8cda 7714 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7715 * are performed on the field for the IA32_EFER MSR:
7716 * - Bits reserved in the IA32_EFER MSR must be 0.
7717 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7718 * the IA-32e mode guest VM-exit control. It must also be identical
7719 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7720 * CR0.PG) is 1.
7721 */
7722 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7723 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7724 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7725 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7726 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7727 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7728 nested_vmx_entry_failure(vcpu, vmcs12,
7729 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7730 return 1;
7731 }
7732 }
7733
7734 /*
7735 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7736 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7737 * the values of the LMA and LME bits in the field must each be that of
7738 * the host address-space size VM-exit control.
7739 */
7740 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7741 ia32e = (vmcs12->vm_exit_controls &
7742 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7743 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7744 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7745 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7746 nested_vmx_entry_failure(vcpu, vmcs12,
7747 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7748 return 1;
7749 }
7750 }
7751
7c177938
NHE		 7752 /*
7753 * We're finally done with prerequisite checking, and can start with
7754 * the nested entry.
7755 */
7756
cd232ad0
NHE		 7757 vmcs02 = nested_get_current_vmcs02(vmx);
7758 if (!vmcs02)
7759 return -ENOMEM;
7760
7761 enter_guest_mode(vcpu);
7762
7763 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7764
7765 cpu = get_cpu();
7766 vmx->loaded_vmcs = vmcs02;
7767 vmx_vcpu_put(vcpu);
7768 vmx_vcpu_load(vcpu, cpu);
7769 vcpu->cpu = cpu;
7770 put_cpu();
7771
36c3cc42
JK		 7772 vmx_segment_cache_clear(vmx);
7773
cd232ad0
NHE		 7774 vmcs12->launch_state = 1;
7775
7776 prepare_vmcs02(vcpu, vmcs12);
7777
7778 /*
7779 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7780 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7781 * returned as far as L1 is concerned. It will only return (and set
7782 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7783 */
7784 return 1;
7785}
7786
4704d0be
NHE		 7787/*
7788 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7789 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7790 * This function returns the new value we should put in vmcs12.guest_cr0.
7791 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7792 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7793 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7794 * didn't trap the bit, because if L1 did, so would L0).
7795 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7796 * been modified by L2, and L1 knows it. So just leave the old value of
7797 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7798 * isn't relevant, because if L0 traps this bit it can set it to anything.
7799 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7800 * changed these bits, and therefore they need to be updated, but L0
7801 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7802 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7803 */
7804static inline unsigned long
7805vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7806{
7807 return
7808 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7809 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7810 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7811 vcpu->arch.cr0_guest_owned_bits));
7812}
7813
7814static inline unsigned long
7815vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7816{
7817 return
7818 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7819 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7820 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7821 vcpu->arch.cr4_guest_owned_bits));
7822}
7823
5f3d5799
JK		 7824static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7825 struct vmcs12 *vmcs12)
7826{
7827 u32 idt_vectoring;
7828 unsigned int nr;
7829
7830 if (vcpu->arch.exception.pending) {
7831 nr = vcpu->arch.exception.nr;
7832 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7833
7834 if (kvm_exception_is_soft(nr)) {
7835 vmcs12->vm_exit_instruction_len =
7836 vcpu->arch.event_exit_inst_len;
7837 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7838 } else
7839 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7840
7841 if (vcpu->arch.exception.has_error_code) {
7842 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7843 vmcs12->idt_vectoring_error_code =
7844 vcpu->arch.exception.error_code;
7845 }
7846
7847 vmcs12->idt_vectoring_info_field = idt_vectoring;
7848 } else if (vcpu->arch.nmi_pending) {
7849 vmcs12->idt_vectoring_info_field =
7850 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7851 } else if (vcpu->arch.interrupt.pending) {
7852 nr = vcpu->arch.interrupt.nr;
7853 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7854
7855 if (vcpu->arch.interrupt.soft) {
7856 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7857 vmcs12->vm_entry_instruction_len =
7858 vcpu->arch.event_exit_inst_len;
7859 } else
7860 idt_vectoring |= INTR_TYPE_EXT_INTR;
7861
7862 vmcs12->idt_vectoring_info_field = idt_vectoring;
7863 }
7864}
7865
4704d0be
NHE		 7866/*
7867 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7868 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7869 * and this function updates it to reflect the changes to the guest state while
7870 * L2 was running (and perhaps made some exits which were handled directly by L0
7871 * without going back to L1), and to reflect the exit reason.
7872 * Note that we do not have to copy here all VMCS fields, just those that
7873 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7874 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7875 * which already writes to vmcs12 directly.
7876 */
733568f9 7877static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7878{
7879 /* update guest state fields: */
7880 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7881 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7882
7883 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7884 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7885 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7886 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7887
7888 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7889 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7890 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7891 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7892 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7893 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7894 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7895 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7896 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7897 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7898 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7899 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7900 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7901 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7902 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7903 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7904 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7905 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7906 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7907 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7908 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7909 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7910 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7911 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7912 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7913 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7914 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7915 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7916 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7917 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7918 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7919 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7920 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7921 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7922 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7923 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7924
4704d0be
NHE		 7925 vmcs12->guest_interruptibility_info =
7926 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7927 vmcs12->guest_pending_dbg_exceptions =
7928 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7929
3633cfc3
NHE		 7930 /*
7931 * In some cases (usually, nested EPT), L2 is allowed to change its
7932 * own CR3 without exiting. If it has changed it, we must keep it.
7933 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
7934 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
7935 *
7936 * Additionally, restore L2's PDPTR to vmcs12.
7937 */
7938 if (enable_ept) {
7939 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
7940 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
7941 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
7942 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
7943 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
7944 }
7945
c18911a2
JK		 7946 vmcs12->vm_entry_controls =
7947 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7948 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7949
4704d0be
NHE		 7950 /* TODO: These cannot have changed unless we have MSR bitmaps and
7951 * the relevant bit asks not to trap the change */
7952 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7953 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7954 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7955 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7956 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7957 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7958
7959 /* update exit information fields: */
7960
957c897e 7961 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7962 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7963
7964 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7965 if ((vmcs12->vm_exit_intr_info &
7966 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7967 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7968 vmcs12->vm_exit_intr_error_code =
7969 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7970 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7971 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7972 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7973
5f3d5799
JK		 7974 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7975 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7976 * instead of reading the real value. */
4704d0be 7977 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7978
7979 /*
7980 * Transfer the event that L0 or L1 may wanted to inject into
7981 * L2 to IDT_VECTORING_INFO_FIELD.
7982 */
7983 vmcs12_save_pending_event(vcpu, vmcs12);
7984 }
7985
7986 /*
7987 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7988 * preserved above and would only end up incorrectly in L1.
7989 */
7990 vcpu->arch.nmi_injected = false;
7991 kvm_clear_exception_queue(vcpu);
7992 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7993}
7994
7995/*
7996 * A part of what we need to when the nested L2 guest exits and we want to
7997 * run its L1 parent, is to reset L1's guest state to the host state specified
7998 * in vmcs12.
7999 * This function is to be called not only on normal nested exit, but also on
8000 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8001 * Failures During or After Loading Guest State").
8002 * This function should be called when the active VMCS is L1's (vmcs01).
8003 */
733568f9
JK		 8004static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8005 struct vmcs12 *vmcs12)
4704d0be 8006{
21feb4eb
ACL		 8007 struct kvm_segment seg;
8008
4704d0be
NHE		 8009 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8010 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8011 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8012 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8013 else
8014 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8015 vmx_set_efer(vcpu, vcpu->arch.efer);
8016
8017 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8018 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8019 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8020 /*
8021 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8022 * actually changed, because it depends on the current state of
8023 * fpu_active (which may have changed).
8024 * Note that vmx_set_cr0 refers to efer set above.
8025 */
8026 kvm_set_cr0(vcpu, vmcs12->host_cr0);
8027 /*
8028 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8029 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8030 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8031 */
8032 update_exception_bitmap(vcpu);
8033 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8034 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8035
8036 /*
8037 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8038 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8039 */
8040 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8041 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8042
8043 /* shadow page tables on either EPT or shadow page tables */
8044 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8045 kvm_mmu_reset_context(vcpu);
8046
8047 if (enable_vpid) {
8048 /*
8049 * Trivially support vpid by letting L2s share their parent
8050 * L1's vpid. TODO: move to a more elaborate solution, giving
8051 * each L2 its own vpid and exposing the vpid feature to L1.
8052 */
8053 vmx_flush_tlb(vcpu);
8054 }
8055
8056
8057 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8058 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8059 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8060 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8061 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be
NHE		 8062
8063 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8064 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8065 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8066 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8067 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8068
21feb4eb
ACL		 8069 /* Set L1 segment info according to Intel SDM
8070 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8071 seg = (struct kvm_segment) {
8072 .base = 0,
8073 .limit = 0xFFFFFFFF,
8074 .selector = vmcs12->host_cs_selector,
8075 .type = 11,
8076 .present = 1,
8077 .s = 1,
8078 .g = 1
8079 };
8080 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8081 seg.l = 1;
8082 else
8083 seg.db = 1;
8084 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8085 seg = (struct kvm_segment) {
8086 .base = 0,
8087 .limit = 0xFFFFFFFF,
8088 .type = 3,
8089 .present = 1,
8090 .s = 1,
8091 .db = 1,
8092 .g = 1
8093 };
8094 seg.selector = vmcs12->host_ds_selector;
8095 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8096 seg.selector = vmcs12->host_es_selector;
8097 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8098 seg.selector = vmcs12->host_ss_selector;
8099 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8100 seg.selector = vmcs12->host_fs_selector;
8101 seg.base = vmcs12->host_fs_base;
8102 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8103 seg.selector = vmcs12->host_gs_selector;
8104 seg.base = vmcs12->host_gs_base;
8105 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8106 seg = (struct kvm_segment) {
205befd9 8107 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8108 .limit = 0x67,
8109 .selector = vmcs12->host_tr_selector,
8110 .type = 11,
8111 .present = 1
8112 };
8113 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8114
503cd0c5
JK		 8115 kvm_set_dr(vcpu, 7, 0x400);
8116 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8117}
8118
8119/*
8120 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8121 * and modify vmcs12 to make it see what it would expect to see there if
8122 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8123 */
8124static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8125{
8126 struct vcpu_vmx *vmx = to_vmx(vcpu);
8127 int cpu;
8128 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8129
5f3d5799
JK		 8130 /* trying to cancel vmlaunch/vmresume is a bug */
8131 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8132
4704d0be
NHE		 8133 leave_guest_mode(vcpu);
8134 prepare_vmcs12(vcpu, vmcs12);
8135
8136 cpu = get_cpu();
8137 vmx->loaded_vmcs = &vmx->vmcs01;
8138 vmx_vcpu_put(vcpu);
8139 vmx_vcpu_load(vcpu, cpu);
8140 vcpu->cpu = cpu;
8141 put_cpu();
8142
36c3cc42
JK		 8143 vmx_segment_cache_clear(vmx);
8144
4704d0be
NHE		 8145 /* if no vmcs02 cache requested, remove the one we used */
8146 if (VMCS02_POOL_SIZE == 0)
8147 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8148
8149 load_vmcs12_host_state(vcpu, vmcs12);
8150
27fc51b2 8151 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8152 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8153
8154 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8155 vmx->host_rsp = 0;
8156
8157 /* Unpin physical memory we referred to in vmcs02 */
8158 if (vmx->nested.apic_access_page) {
8159 nested_release_page(vmx->nested.apic_access_page);
8160 vmx->nested.apic_access_page = 0;
8161 }
8162
8163 /*
8164 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8165 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8166 * success or failure flag accordingly.
8167 */
8168 if (unlikely(vmx->fail)) {
8169 vmx->fail = 0;
8170 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8171 } else
8172 nested_vmx_succeed(vcpu);
012f83cb
AG		 8173 if (enable_shadow_vmcs)
8174 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8175}
8176
7c177938
NHE		 8177/*
8178 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8179 * 23.7 "VM-entry failures during or after loading guest state" (this also
8180 * lists the acceptable exit-reason and exit-qualification parameters).
8181 * It should only be called before L2 actually succeeded to run, and when
8182 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8183 */
8184static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8185 struct vmcs12 *vmcs12,
8186 u32 reason, unsigned long qualification)
8187{
8188 load_vmcs12_host_state(vcpu, vmcs12);
8189 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8190 vmcs12->exit_qualification = qualification;
8191 nested_vmx_succeed(vcpu);
012f83cb
AG		 8192 if (enable_shadow_vmcs)
8193 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8194}
8195
8a76d7f2
JR		 8196static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8197 struct x86_instruction_info *info,
8198 enum x86_intercept_stage stage)
8199{
8200 return X86EMUL_CONTINUE;
8201}
8202
cbdd1bea 8203static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8204 .cpu_has_kvm_support = cpu_has_kvm_support,
8205 .disabled_by_bios = vmx_disabled_by_bios,
8206 .hardware_setup = hardware_setup,
8207 .hardware_unsetup = hardware_unsetup,
002c7f7c 8208 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8209 .hardware_enable = hardware_enable,
8210 .hardware_disable = hardware_disable,
04547156 8211 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8212
8213 .vcpu_create = vmx_create_vcpu,
8214 .vcpu_free = vmx_free_vcpu,
04d2cc77 8215 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8216
04d2cc77 8217 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8218 .vcpu_load = vmx_vcpu_load,
8219 .vcpu_put = vmx_vcpu_put,
8220
c8639010 8221 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8222 .get_msr = vmx_get_msr,
8223 .set_msr = vmx_set_msr,
8224 .get_segment_base = vmx_get_segment_base,
8225 .get_segment = vmx_get_segment,
8226 .set_segment = vmx_set_segment,
2e4d2653 8227 .get_cpl = vmx_get_cpl,
6aa8b732 8228 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8229 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8230 .decache_cr3 = vmx_decache_cr3,
25c4c276 8231 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8232 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8233 .set_cr3 = vmx_set_cr3,
8234 .set_cr4 = vmx_set_cr4,
6aa8b732 8235 .set_efer = vmx_set_efer,
6aa8b732
AK		 8236 .get_idt = vmx_get_idt,
8237 .set_idt = vmx_set_idt,
8238 .get_gdt = vmx_get_gdt,
8239 .set_gdt = vmx_set_gdt,
020df079 8240 .set_dr7 = vmx_set_dr7,
5fdbf976 8241 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8242 .get_rflags = vmx_get_rflags,
8243 .set_rflags = vmx_set_rflags,
ebcbab4c 8244 .fpu_activate = vmx_fpu_activate,
02daab21 8245 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8246
8247 .tlb_flush = vmx_flush_tlb,
6aa8b732 8248
6aa8b732 8249 .run = vmx_vcpu_run,
6062d012 8250 .handle_exit = vmx_handle_exit,
6aa8b732 8251 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8252 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8253 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8254 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8255 .set_irq = vmx_inject_irq,
95ba8273 8256 .set_nmi = vmx_inject_nmi,
298101da 8257 .queue_exception = vmx_queue_exception,
b463a6f7 8258 .cancel_injection = vmx_cancel_injection,
78646121 8259 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8260 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8261 .get_nmi_mask = vmx_get_nmi_mask,
8262 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8263 .enable_nmi_window = enable_nmi_window,
8264 .enable_irq_window = enable_irq_window,
8265 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8266 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8267 .vm_has_apicv = vmx_vm_has_apicv,
8268 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8269 .hwapic_irr_update = vmx_hwapic_irr_update,
8270 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8271 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8272 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8273
cbc94022 8274 .set_tss_addr = vmx_set_tss_addr,
67253af5 8275 .get_tdp_level = get_ept_level,
4b12f0de 8276 .get_mt_mask = vmx_get_mt_mask,
229456fc 8277
586f9607 8278 .get_exit_info = vmx_get_exit_info,
586f9607 8279
17cc3935 8280 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8281
8282 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8283
8284 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8285 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8286
8287 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8288
8289 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8290
4051b188 8291 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8292 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8293 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8294 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8295 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8296 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8297
8298 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8299
8300 .check_intercept = vmx_check_intercept,
a547c6db 8301 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8302};
8303
8304static int __init vmx_init(void)
8305{
8d14695f 8306 int r, i, msr;
26bb0981
AK		 8307
8308 rdmsrl_safe(MSR_EFER, &host_efer);
8309
8310 for (i = 0; i < NR_VMX_MSR; ++i)
8311 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8312
3e7c73e9 8313 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8314 if (!vmx_io_bitmap_a)
8315 return -ENOMEM;
8316
2106a548
GC		 8317 r = -ENOMEM;
8318
3e7c73e9 8319 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8320 if (!vmx_io_bitmap_b)
fdef3ad1 8321 goto out;
fdef3ad1 8322
5897297b 8323 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8324 if (!vmx_msr_bitmap_legacy)
25c5f225 8325 goto out1;
2106a548 8326
8d14695f
YZ		 8327 vmx_msr_bitmap_legacy_x2apic =
8328 (unsigned long *)__get_free_page(GFP_KERNEL);
8329 if (!vmx_msr_bitmap_legacy_x2apic)
8330 goto out2;
25c5f225 8331
5897297b 8332 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8333 if (!vmx_msr_bitmap_longmode)
8d14695f 8334 goto out3;
2106a548 8335
8d14695f
YZ		 8336 vmx_msr_bitmap_longmode_x2apic =
8337 (unsigned long *)__get_free_page(GFP_KERNEL);
8338 if (!vmx_msr_bitmap_longmode_x2apic)
8339 goto out4;
4607c2d7
AG		 8340 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8341 if (!vmx_vmread_bitmap)
8342 goto out5;
8343
8344 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8345 if (!vmx_vmwrite_bitmap)
8346 goto out6;
8347
8348 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8349 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8350 /* shadowed read/write fields */
8351 for (i = 0; i < max_shadow_read_write_fields; i++) {
8352 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8353 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8354 }
8355 /* shadowed read only fields */
8356 for (i = 0; i < max_shadow_read_only_fields; i++)
8357 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8358
fdef3ad1
HQ		 8359 /*
8360 * Allow direct access to the PC debug port (it is often used for I/O
8361 * delays, but the vmexits simply slow things down).
8362 */
3e7c73e9
AK		 8363 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8364 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8365
3e7c73e9 8366 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8367
5897297b
AK		 8368 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8369 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8370
2384d2b3
SY		 8371 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8372
0ee75bea
AK		 8373 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8374 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8375 if (r)
4607c2d7 8376 goto out7;
25c5f225 8377
8f536b76
ZY		 8378#ifdef CONFIG_KEXEC
8379 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8380 crash_vmclear_local_loaded_vmcss);
8381#endif
8382
5897297b
AK		 8383 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8384 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8385 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8386 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8387 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8388 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8389 memcpy(vmx_msr_bitmap_legacy_x2apic,
8390 vmx_msr_bitmap_legacy, PAGE_SIZE);
8391 memcpy(vmx_msr_bitmap_longmode_x2apic,
8392 vmx_msr_bitmap_longmode, PAGE_SIZE);
8393
01e439be 8394 if (enable_apicv) {
8d14695f
YZ		 8395 for (msr = 0x800; msr <= 0x8ff; msr++)
8396 vmx_disable_intercept_msr_read_x2apic(msr);
8397
8398 /* According SDM, in x2apic mode, the whole id reg is used.
8399 * But in KVM, it only use the highest eight bits. Need to
8400 * intercept it */
8401 vmx_enable_intercept_msr_read_x2apic(0x802);
8402 /* TMCCT */
8403 vmx_enable_intercept_msr_read_x2apic(0x839);
8404 /* TPR */
8405 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8406 /* EOI */
8407 vmx_disable_intercept_msr_write_x2apic(0x80b);
8408 /* SELF-IPI */
8409 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8410 }
fdef3ad1 8411
089d034e 8412 if (enable_ept) {
3f6d8c8a
XH		 8413 kvm_mmu_set_mask_ptes(0ull,
8414 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8415 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8416 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8417 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8418 kvm_enable_tdp();
8419 } else
8420 kvm_disable_tdp();
1439442c 8421
fdef3ad1
HQ		 8422 return 0;
8423
4607c2d7
AG		 8424out7:
8425 free_page((unsigned long)vmx_vmwrite_bitmap);
8426out6:
8427 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8428out5:
8429 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8430out4:
5897297b 8431 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8432out3:
8433 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8434out2:
5897297b 8435 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8436out1:
3e7c73e9 8437 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8438out:
3e7c73e9 8439 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8440 return r;
6aa8b732
AK		 8441}
8442
8443static void __exit vmx_exit(void)
8444{
8d14695f
YZ		 8445 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8446 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8447 free_page((unsigned long)vmx_msr_bitmap_legacy);
8448 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8449 free_page((unsigned long)vmx_io_bitmap_b);
8450 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8451 free_page((unsigned long)vmx_vmwrite_bitmap);
8452 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8453
8f536b76
ZY		 8454#ifdef CONFIG_KEXEC
8455 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8456 synchronize_rcu();
8457#endif
8458
cb498ea2 8459 kvm_exit();
6aa8b732
AK		 8460}
8461
8462module_init(vmx_init)
8463module_exit(vmx_exit)
Ubuntu Artful kernel mirror