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target-i386: Remove unsupported bits from all CPU models
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 260 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 262 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 264};
265
303752a9
MT		 266static const char *cpuid_apm_edx_feature_name[] = {
267 NULL, NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 "invtsc", NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275};
276
621626ce
EH		 277#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
278#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
279 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
280#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
281 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
282 CPUID_PSE36 | CPUID_FXSR)
283#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
284#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
285 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
286 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
287 CPUID_PAE | CPUID_SEP | CPUID_APIC)
288
289#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
290 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
291 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
292 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
293 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
294 /* partly implemented:
295 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
296 /* missing:
297 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
298#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
299 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
300 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
301 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
302 /* missing:
303 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
304 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
305 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
306 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
307 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
308 CPUID_EXT_RDRAND */
309
310#ifdef TARGET_X86_64
311#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
312#else
313#define TCG_EXT2_X86_64_FEATURES 0
314#endif
315
316#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
317 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
318 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
319 TCG_EXT2_X86_64_FEATURES)
320#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
321 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
322#define TCG_EXT4_FEATURES 0
323#define TCG_SVM_FEATURES 0
324#define TCG_KVM_FEATURES 0
325#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
326 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
327 /* missing:
328 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
329 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
330 CPUID_7_0_EBX_RDSEED */
303752a9 331#define TCG_APM_FEATURES 0
621626ce
EH		 332
333
5ef57876
EH		 334typedef struct FeatureWordInfo {
335 const char **feat_names;
04d104b6
EH		 336 uint32_t cpuid_eax; /* Input EAX for CPUID */
337 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
338 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
339 int cpuid_reg; /* output register (R_* constant) */
37ce3522 340 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 341 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 342} FeatureWordInfo;
343
344static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 345 [FEAT_1_EDX] = {
346 .feat_names = feature_name,
347 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 348 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 349 },
350 [FEAT_1_ECX] = {
351 .feat_names = ext_feature_name,
352 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 353 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 354 },
355 [FEAT_8000_0001_EDX] = {
356 .feat_names = ext2_feature_name,
357 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 358 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 359 },
360 [FEAT_8000_0001_ECX] = {
361 .feat_names = ext3_feature_name,
362 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 363 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 364 },
89e49c8b
EH		 365 [FEAT_C000_0001_EDX] = {
366 .feat_names = ext4_feature_name,
367 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 368 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 369 },
bffd67b0
EH		 370 [FEAT_KVM] = {
371 .feat_names = kvm_feature_name,
372 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 373 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 374 },
375 [FEAT_SVM] = {
376 .feat_names = svm_feature_name,
377 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 378 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 379 },
380 [FEAT_7_0_EBX] = {
381 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 382 .cpuid_eax = 7,
383 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
384 .cpuid_reg = R_EBX,
37ce3522 385 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 386 },
303752a9
MT		 387 [FEAT_8000_0007_EDX] = {
388 .feat_names = cpuid_apm_edx_feature_name,
389 .cpuid_eax = 0x80000007,
390 .cpuid_reg = R_EDX,
391 .tcg_features = TCG_APM_FEATURES,
392 .unmigratable_flags = CPUID_APM_INVTSC,
393 },
5ef57876
EH		 394};
395
8e8aba50
EH		 396typedef struct X86RegisterInfo32 {
397 /* Name of register */
398 const char *name;
399 /* QAPI enum value register */
400 X86CPURegister32 qapi_enum;
401} X86RegisterInfo32;
402
403#define REGISTER(reg) \
5d371f41 404 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 405static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 406 REGISTER(EAX),
407 REGISTER(ECX),
408 REGISTER(EDX),
409 REGISTER(EBX),
410 REGISTER(ESP),
411 REGISTER(EBP),
412 REGISTER(ESI),
413 REGISTER(EDI),
414};
415#undef REGISTER
416
2560f19f
PB		 417typedef struct ExtSaveArea {
418 uint32_t feature, bits;
419 uint32_t offset, size;
420} ExtSaveArea;
421
422static const ExtSaveArea ext_save_areas[] = {
423 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 424 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 425 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
426 .offset = 0x3c0, .size = 0x40 },
427 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 428 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 429 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
430 .offset = 0x440, .size = 0x40 },
431 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
432 .offset = 0x480, .size = 0x200 },
433 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
434 .offset = 0x680, .size = 0x400 },
2560f19f 435};
8e8aba50 436
8b4beddc
EH		 437const char *get_register_name_32(unsigned int reg)
438{
31ccdde2 439 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 440 return NULL;
441 }
8e8aba50 442 return x86_reg_info_32[reg].name;
8b4beddc
EH		 443}
444
5fcca9ff
EH		 445/* KVM-specific features that are automatically added to all CPU models
446 * when KVM is enabled.
447 */
448static uint32_t kvm_default_features[FEATURE_WORDS] = {
449 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 450 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 451 (1 << KVM_FEATURE_CLOCKSOURCE2) |
452 (1 << KVM_FEATURE_ASYNC_PF) |
453 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 454 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 455 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 456 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 457};
dc59944b 458
136a7e9a
EH		 459/* Features that are not added by default to any CPU model when KVM is enabled.
460 */
461static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 462 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a
EH		 463 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
464};
465
1cadaa94 466void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 467{
8fb4f821 468 kvm_default_features[w] &= ~features;
dc59944b
MT		 469}
470
84f1b92f
EH		 471/*
472 * Returns the set of feature flags that are supported and migratable by
473 * QEMU, for a given FeatureWord.
474 */
475static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
476{
477 FeatureWordInfo *wi = &feature_word_info[w];
478 uint32_t r = 0;
479 int i;
480
481 for (i = 0; i < 32; i++) {
482 uint32_t f = 1U << i;
483 /* If the feature name is unknown, it is not supported by QEMU yet */
484 if (!wi->feat_names[i]) {
485 continue;
486 }
487 /* Skip features known to QEMU, but explicitly marked as unmigratable */
488 if (wi->unmigratable_flags & f) {
489 continue;
490 }
491 r |= f;
492 }
493 return r;
494}
495
bb44e0d1
JK		 496void host_cpuid(uint32_t function, uint32_t count,
497 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 498{
a1fd24af
AL		 499 uint32_t vec[4];
500
501#ifdef __x86_64__
502 asm volatile("cpuid"
503 : "=a"(vec[0]), "=b"(vec[1]),
504 "=c"(vec[2]), "=d"(vec[3])
505 : "0"(function), "c"(count) : "cc");
c1f41226 506#elif defined(__i386__)
a1fd24af
AL		 507 asm volatile("pusha \n\t"
508 "cpuid \n\t"
509 "mov %%eax, 0(%2) \n\t"
510 "mov %%ebx, 4(%2) \n\t"
511 "mov %%ecx, 8(%2) \n\t"
512 "mov %%edx, 12(%2) \n\t"
513 "popa"
514 : : "a"(function), "c"(count), "S"(vec)
515 : "memory", "cc");
c1f41226
EH		 516#else
517 abort();
a1fd24af
AL		 518#endif
519
bdde476a 520 if (eax)
a1fd24af 521 *eax = vec[0];
bdde476a 522 if (ebx)
a1fd24af 523 *ebx = vec[1];
bdde476a 524 if (ecx)
a1fd24af 525 *ecx = vec[2];
bdde476a 526 if (edx)
a1fd24af 527 *edx = vec[3];
bdde476a 528}
c6dc6f63
AP		 529
530#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
531
532/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
533 * a substring. ex if !NULL points to the first char after a substring,
534 * otherwise the string is assumed to sized by a terminating nul.
535 * Return lexical ordering of *s1:*s2.
536 */
537static int sstrcmp(const char *s1, const char *e1, const char *s2,
538 const char *e2)
539{
540 for (;;) {
541 if (!*s1 || !*s2 || *s1 != *s2)
542 return (*s1 - *s2);
543 ++s1, ++s2;
544 if (s1 == e1 && s2 == e2)
545 return (0);
546 else if (s1 == e1)
547 return (*s2);
548 else if (s2 == e2)
549 return (*s1);
550 }
551}
552
553/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
554 * '|' delimited (possibly empty) strings in which case search for a match
555 * within the alternatives proceeds left to right. Return 0 for success,
556 * non-zero otherwise.
557 */
558static int altcmp(const char *s, const char *e, const char *altstr)
559{
560 const char *p, *q;
561
562 for (q = p = altstr; ; ) {
563 while (*p && *p != '|')
564 ++p;
565 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
566 return (0);
567 if (!*p)
568 return (1);
569 else
570 q = ++p;
571 }
572}
573
574/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 575 * *pval and return true, otherwise return false
c6dc6f63 576 */
e41e0fc6
JK		 577static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
578 const char **featureset)
c6dc6f63
AP		 579{
580 uint32_t mask;
581 const char **ppc;
e41e0fc6 582 bool found = false;
c6dc6f63 583
e41e0fc6 584 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 585 if (*ppc && !altcmp(s, e, *ppc)) {
586 *pval |= mask;
e41e0fc6 587 found = true;
c6dc6f63 588 }
e41e0fc6
JK		 589 }
590 return found;
c6dc6f63
AP		 591}
592
5ef57876 593static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 594 FeatureWordArray words,
595 Error **errp)
c6dc6f63 596{
5ef57876
EH		 597 FeatureWord w;
598 for (w = 0; w < FEATURE_WORDS; w++) {
599 FeatureWordInfo *wi = &feature_word_info[w];
600 if (wi->feat_names &&
601 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
602 break;
603 }
604 }
605 if (w == FEATURE_WORDS) {
c00c94ab 606 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 607 }
c6dc6f63
AP		 608}
609
d940ee9b
EH		 610/* CPU class name definitions: */
611
612#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
613#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
614
615/* Return type name for a given CPU model name
616 * Caller is responsible for freeing the returned string.
617 */
618static char *x86_cpu_type_name(const char *model_name)
619{
620 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
621}
622
500050d1
AF		 623static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
624{
d940ee9b
EH		 625 ObjectClass *oc;
626 char *typename;
627
500050d1
AF		 628 if (cpu_model == NULL) {
629 return NULL;
630 }
631
d940ee9b
EH		 632 typename = x86_cpu_type_name(cpu_model);
633 oc = object_class_by_name(typename);
634 g_free(typename);
635 return oc;
500050d1
AF		 636}
637
d940ee9b 638struct X86CPUDefinition {
c6dc6f63
AP		 639 const char *name;
640 uint32_t level;
90e4b0c3
EH		 641 uint32_t xlevel;
642 uint32_t xlevel2;
99b88a17
IM		 643 /* vendor is zero-terminated, 12 character ASCII string */
644 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 645 int family;
646 int model;
647 int stepping;
0514ef2f 648 FeatureWordArray features;
c6dc6f63 649 char model_id[48];
787aaf57 650 bool cache_info_passthrough;
d940ee9b 651};
c6dc6f63 652
9576de75 653static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 654 {
655 .name = "qemu64",
656 .level = 4,
99b88a17 657 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 658 .family = 6,
f8e6a11a 659 .model = 6,
c6dc6f63 660 .stepping = 3,
0514ef2f 661 .features[FEAT_1_EDX] =
27861ecc 662 PPRO_FEATURES |
c6dc6f63 663 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 664 CPUID_PSE36,
0514ef2f 665 .features[FEAT_1_ECX] =
27861ecc 666 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 667 .features[FEAT_8000_0001_EDX] =
27861ecc 668 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 669 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 670 .features[FEAT_8000_0001_ECX] =
27861ecc 671 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 672 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
673 .xlevel = 0x8000000A,
c6dc6f63
AP		 674 },
675 {
676 .name = "phenom",
677 .level = 5,
99b88a17 678 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 679 .family = 16,
680 .model = 2,
681 .stepping = 3,
b9fc20bc 682 /* Missing: CPUID_HT */
0514ef2f 683 .features[FEAT_1_EDX] =
27861ecc 684 PPRO_FEATURES |
c6dc6f63 685 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 686 CPUID_PSE36 | CPUID_VME,
0514ef2f 687 .features[FEAT_1_ECX] =
27861ecc 688 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 689 CPUID_EXT_POPCNT,
0514ef2f 690 .features[FEAT_8000_0001_EDX] =
27861ecc 691 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 692 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
693 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 694 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 695 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
696 CPUID_EXT3_CR8LEG,
697 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
698 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 699 .features[FEAT_8000_0001_ECX] =
27861ecc 700 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 701 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 702 /* Missing: CPUID_SVM_LBRV */
0514ef2f 703 .features[FEAT_SVM] =
b9fc20bc 704 CPUID_SVM_NPT,
c6dc6f63
AP		 705 .xlevel = 0x8000001A,
706 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
707 },
708 {
709 .name = "core2duo",
710 .level = 10,
99b88a17 711 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 712 .family = 6,
713 .model = 15,
714 .stepping = 11,
b9fc20bc 715 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 716 .features[FEAT_1_EDX] =
27861ecc 717 PPRO_FEATURES |
c6dc6f63 718 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 719 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
720 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
721 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
0514ef2f 722 .features[FEAT_1_ECX] =
27861ecc 723 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
b9fc20bc 724 CPUID_EXT_VMX | CPUID_EXT_CX16,
0514ef2f 725 .features[FEAT_8000_0001_EDX] =
27861ecc 726 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 727 .features[FEAT_8000_0001_ECX] =
27861ecc 728 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 729 .xlevel = 0x80000008,
730 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
731 },
732 {
733 .name = "kvm64",
734 .level = 5,
99b88a17 735 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 736 .family = 15,
737 .model = 6,
738 .stepping = 1,
739 /* Missing: CPUID_VME, CPUID_HT */
0514ef2f 740 .features[FEAT_1_EDX] =
27861ecc 741 PPRO_FEATURES |
c6dc6f63
AP		 742 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
743 CPUID_PSE36,
744 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 745 .features[FEAT_1_ECX] =
27861ecc 746 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 747 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 748 .features[FEAT_8000_0001_EDX] =
27861ecc 749 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 750 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
751 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
752 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
753 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
754 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 755 .features[FEAT_8000_0001_ECX] =
27861ecc 756 0,
c6dc6f63
AP		 757 .xlevel = 0x80000008,
758 .model_id = "Common KVM processor"
759 },
c6dc6f63
AP		 760 {
761 .name = "qemu32",
762 .level = 4,
99b88a17 763 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 764 .family = 6,
f8e6a11a 765 .model = 6,
c6dc6f63 766 .stepping = 3,
0514ef2f 767 .features[FEAT_1_EDX] =
27861ecc 768 PPRO_FEATURES,
0514ef2f 769 .features[FEAT_1_ECX] =
27861ecc 770 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 771 .xlevel = 0x80000004,
c6dc6f63 772 },
eafaf1e5
AP		 773 {
774 .name = "kvm32",
775 .level = 5,
99b88a17 776 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 777 .family = 15,
778 .model = 6,
779 .stepping = 1,
0514ef2f 780 .features[FEAT_1_EDX] =
27861ecc 781 PPRO_FEATURES |
eafaf1e5 782 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 783 .features[FEAT_1_ECX] =
27861ecc 784 CPUID_EXT_SSE3,
0514ef2f 785 .features[FEAT_8000_0001_EDX] =
27861ecc 786 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 787 .features[FEAT_8000_0001_ECX] =
27861ecc 788 0,
eafaf1e5
AP		 789 .xlevel = 0x80000008,
790 .model_id = "Common 32-bit KVM processor"
791 },
c6dc6f63
AP		 792 {
793 .name = "coreduo",
794 .level = 10,
99b88a17 795 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 796 .family = 6,
797 .model = 14,
798 .stepping = 8,
b9fc20bc 799 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 800 .features[FEAT_1_EDX] =
27861ecc 801 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 802 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
803 CPUID_SS,
804 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
805 * CPUID_EXT_PDCM */
0514ef2f 806 .features[FEAT_1_ECX] =
b9fc20bc 807 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX,
0514ef2f 808 .features[FEAT_8000_0001_EDX] =
27861ecc 809 CPUID_EXT2_NX,
c6dc6f63
AP		 810 .xlevel = 0x80000008,
811 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
812 },
813 {
814 .name = "486",
58012d66 815 .level = 1,
99b88a17 816 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 817 .family = 4,
b2a856d9 818 .model = 8,
c6dc6f63 819 .stepping = 0,
0514ef2f 820 .features[FEAT_1_EDX] =
27861ecc 821 I486_FEATURES,
c6dc6f63
AP		 822 .xlevel = 0,
823 },
824 {
825 .name = "pentium",
826 .level = 1,
99b88a17 827 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 828 .family = 5,
829 .model = 4,
830 .stepping = 3,
0514ef2f 831 .features[FEAT_1_EDX] =
27861ecc 832 PENTIUM_FEATURES,
c6dc6f63
AP		 833 .xlevel = 0,
834 },
835 {
836 .name = "pentium2",
837 .level = 2,
99b88a17 838 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 839 .family = 6,
840 .model = 5,
841 .stepping = 2,
0514ef2f 842 .features[FEAT_1_EDX] =
27861ecc 843 PENTIUM2_FEATURES,
c6dc6f63
AP		 844 .xlevel = 0,
845 },
846 {
847 .name = "pentium3",
848 .level = 2,
99b88a17 849 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 850 .family = 6,
851 .model = 7,
852 .stepping = 3,
0514ef2f 853 .features[FEAT_1_EDX] =
27861ecc 854 PENTIUM3_FEATURES,
c6dc6f63
AP		 855 .xlevel = 0,
856 },
857 {
858 .name = "athlon",
859 .level = 2,
99b88a17 860 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 861 .family = 6,
862 .model = 2,
863 .stepping = 3,
0514ef2f 864 .features[FEAT_1_EDX] =
27861ecc 865 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 866 CPUID_MCA,
0514ef2f 867 .features[FEAT_8000_0001_EDX] =
27861ecc 868 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 869 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 870 .xlevel = 0x80000008,
c6dc6f63
AP		 871 },
872 {
873 .name = "n270",
874 /* original is on level 10 */
875 .level = 5,
99b88a17 876 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 877 .family = 6,
878 .model = 28,
879 .stepping = 2,
b9fc20bc 880 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 881 .features[FEAT_1_EDX] =
27861ecc 882 PPRO_FEATURES |
b9fc20bc
EH		 883 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
884 CPUID_ACPI | CPUID_SS,
c6dc6f63 885 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 886 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
887 * CPUID_EXT_XTPR */
0514ef2f 888 .features[FEAT_1_ECX] =
27861ecc 889 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 890 CPUID_EXT_MOVBE,
0514ef2f 891 .features[FEAT_8000_0001_EDX] =
27861ecc 892 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 893 CPUID_EXT2_NX,
0514ef2f 894 .features[FEAT_8000_0001_ECX] =
27861ecc 895 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 896 .xlevel = 0x8000000A,
897 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
898 },
3eca4642
EH		 899 {
900 .name = "Conroe",
6b11322e 901 .level = 4,
99b88a17 902 .vendor = CPUID_VENDOR_INTEL,
3eca4642 903 .family = 6,
ffce9ebb 904 .model = 15,
3eca4642 905 .stepping = 3,
0514ef2f 906 .features[FEAT_1_EDX] =
27861ecc 907 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 908 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
909 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
910 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
911 CPUID_DE | CPUID_FP87,
0514ef2f 912 .features[FEAT_1_ECX] =
27861ecc 913 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 914 .features[FEAT_8000_0001_EDX] =
27861ecc 915 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 916 .features[FEAT_8000_0001_ECX] =
27861ecc 917 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 918 .xlevel = 0x8000000A,
919 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
920 },
921 {
922 .name = "Penryn",
6b11322e 923 .level = 4,
99b88a17 924 .vendor = CPUID_VENDOR_INTEL,
3eca4642 925 .family = 6,
ffce9ebb 926 .model = 23,
3eca4642 927 .stepping = 3,
0514ef2f 928 .features[FEAT_1_EDX] =
27861ecc 929 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 930 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
931 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
932 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
933 CPUID_DE | CPUID_FP87,
0514ef2f 934 .features[FEAT_1_ECX] =
27861ecc 935 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 936 CPUID_EXT_SSE3,
0514ef2f 937 .features[FEAT_8000_0001_EDX] =
27861ecc 938 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 939 .features[FEAT_8000_0001_ECX] =
27861ecc 940 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 941 .xlevel = 0x8000000A,
942 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
943 },
944 {
945 .name = "Nehalem",
6b11322e 946 .level = 4,
99b88a17 947 .vendor = CPUID_VENDOR_INTEL,
3eca4642 948 .family = 6,
ffce9ebb 949 .model = 26,
3eca4642 950 .stepping = 3,
0514ef2f 951 .features[FEAT_1_EDX] =
27861ecc 952 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 953 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
954 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
955 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
956 CPUID_DE | CPUID_FP87,
0514ef2f 957 .features[FEAT_1_ECX] =
27861ecc 958 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 959 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 960 .features[FEAT_8000_0001_EDX] =
27861ecc 961 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 962 .features[FEAT_8000_0001_ECX] =
27861ecc 963 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 964 .xlevel = 0x8000000A,
965 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
966 },
967 {
968 .name = "Westmere",
969 .level = 11,
99b88a17 970 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 971 .family = 6,
972 .model = 44,
973 .stepping = 1,
0514ef2f 974 .features[FEAT_1_EDX] =
27861ecc 975 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 976 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
977 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
978 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
979 CPUID_DE | CPUID_FP87,
0514ef2f 980 .features[FEAT_1_ECX] =
27861ecc 981 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 982 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
983 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 984 .features[FEAT_8000_0001_EDX] =
27861ecc 985 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 986 .features[FEAT_8000_0001_ECX] =
27861ecc 987 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 988 .xlevel = 0x8000000A,
989 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
990 },
991 {
992 .name = "SandyBridge",
993 .level = 0xd,
99b88a17 994 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 995 .family = 6,
996 .model = 42,
997 .stepping = 1,
0514ef2f 998 .features[FEAT_1_EDX] =
27861ecc 999 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1000 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1001 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1002 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1003 CPUID_DE | CPUID_FP87,
0514ef2f 1004 .features[FEAT_1_ECX] =
27861ecc 1005 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1006 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1007 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1008 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1009 CPUID_EXT_SSE3,
0514ef2f 1010 .features[FEAT_8000_0001_EDX] =
27861ecc 1011 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1012 CPUID_EXT2_SYSCALL,
0514ef2f 1013 .features[FEAT_8000_0001_ECX] =
27861ecc 1014 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1015 .xlevel = 0x8000000A,
1016 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1017 },
37507094
EH		 1018 {
1019 .name = "Haswell",
1020 .level = 0xd,
99b88a17 1021 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1022 .family = 6,
1023 .model = 60,
1024 .stepping = 1,
0514ef2f 1025 .features[FEAT_1_EDX] =
27861ecc 1026 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1027 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1028 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1029 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1030 CPUID_DE | CPUID_FP87,
0514ef2f 1031 .features[FEAT_1_ECX] =
27861ecc 1032 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1033 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1034 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1035 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1036 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1037 CPUID_EXT_PCID,
0514ef2f 1038 .features[FEAT_8000_0001_EDX] =
27861ecc 1039 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1040 CPUID_EXT2_SYSCALL,
0514ef2f 1041 .features[FEAT_8000_0001_ECX] =
27861ecc 1042 CPUID_EXT3_LAHF_LM,
0514ef2f 1043 .features[FEAT_7_0_EBX] =
27861ecc 1044 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 1045 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1046 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1047 CPUID_7_0_EBX_RTM,
1048 .xlevel = 0x8000000A,
1049 .model_id = "Intel Core Processor (Haswell)",
1050 },
ece01354
EH		 1051 {
1052 .name = "Broadwell",
1053 .level = 0xd,
1054 .vendor = CPUID_VENDOR_INTEL,
1055 .family = 6,
1056 .model = 61,
1057 .stepping = 2,
1058 .features[FEAT_1_EDX] =
1059 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1060 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1061 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1062 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1063 CPUID_DE | CPUID_FP87,
1064 .features[FEAT_1_ECX] =
1065 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1066 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1067 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1068 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1069 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1070 CPUID_EXT_PCID,
1071 .features[FEAT_8000_0001_EDX] =
1072 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1073 CPUID_EXT2_SYSCALL,
1074 .features[FEAT_8000_0001_ECX] =
1075 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1076 .features[FEAT_7_0_EBX] =
1077 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1078 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1079 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1080 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1081 CPUID_7_0_EBX_SMAP,
1082 .xlevel = 0x8000000A,
1083 .model_id = "Intel Core Processor (Broadwell)",
1084 },
3eca4642
EH		 1085 {
1086 .name = "Opteron_G1",
1087 .level = 5,
99b88a17 1088 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1089 .family = 15,
1090 .model = 6,
1091 .stepping = 1,
0514ef2f 1092 .features[FEAT_1_EDX] =
27861ecc 1093 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1094 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1095 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1096 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1097 CPUID_DE | CPUID_FP87,
0514ef2f 1098 .features[FEAT_1_ECX] =
27861ecc 1099 CPUID_EXT_SSE3,
0514ef2f 1100 .features[FEAT_8000_0001_EDX] =
27861ecc 1101 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1102 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1103 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1104 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1105 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1106 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1107 .xlevel = 0x80000008,
1108 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1109 },
1110 {
1111 .name = "Opteron_G2",
1112 .level = 5,
99b88a17 1113 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1114 .family = 15,
1115 .model = 6,
1116 .stepping = 1,
0514ef2f 1117 .features[FEAT_1_EDX] =
27861ecc 1118 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1119 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1120 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1121 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1122 CPUID_DE | CPUID_FP87,
0514ef2f 1123 .features[FEAT_1_ECX] =
27861ecc 1124 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1125 .features[FEAT_8000_0001_EDX] =
27861ecc 1126 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1127 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1128 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1129 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1130 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1131 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1132 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1133 .features[FEAT_8000_0001_ECX] =
27861ecc 1134 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1135 .xlevel = 0x80000008,
1136 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1137 },
1138 {
1139 .name = "Opteron_G3",
1140 .level = 5,
99b88a17 1141 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1142 .family = 15,
1143 .model = 6,
1144 .stepping = 1,
0514ef2f 1145 .features[FEAT_1_EDX] =
27861ecc 1146 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1147 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1148 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1149 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1150 CPUID_DE | CPUID_FP87,
0514ef2f 1151 .features[FEAT_1_ECX] =
27861ecc 1152 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1153 CPUID_EXT_SSE3,
0514ef2f 1154 .features[FEAT_8000_0001_EDX] =
27861ecc 1155 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1156 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1157 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1158 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1159 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1160 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1161 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1162 .features[FEAT_8000_0001_ECX] =
27861ecc 1163 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1164 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1165 .xlevel = 0x80000008,
1166 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1167 },
1168 {
1169 .name = "Opteron_G4",
1170 .level = 0xd,
99b88a17 1171 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1172 .family = 21,
1173 .model = 1,
1174 .stepping = 2,
0514ef2f 1175 .features[FEAT_1_EDX] =
27861ecc 1176 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1180 CPUID_DE | CPUID_FP87,
0514ef2f 1181 .features[FEAT_1_ECX] =
27861ecc 1182 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1183 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1184 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1185 CPUID_EXT_SSE3,
0514ef2f 1186 .features[FEAT_8000_0001_EDX] =
27861ecc 1187 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1188 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1189 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1190 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1191 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1192 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1193 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1194 .features[FEAT_8000_0001_ECX] =
27861ecc 1195 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1196 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1197 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1198 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1199 .xlevel = 0x8000001A,
1200 .model_id = "AMD Opteron 62xx class CPU",
1201 },
021941b9
AP		 1202 {
1203 .name = "Opteron_G5",
1204 .level = 0xd,
99b88a17 1205 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1206 .family = 21,
1207 .model = 2,
1208 .stepping = 0,
0514ef2f 1209 .features[FEAT_1_EDX] =
27861ecc 1210 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1211 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1212 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1213 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1214 CPUID_DE | CPUID_FP87,
0514ef2f 1215 .features[FEAT_1_ECX] =
27861ecc 1216 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1217 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1218 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1219 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1220 .features[FEAT_8000_0001_EDX] =
27861ecc 1221 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1222 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1223 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1224 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1225 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1226 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1227 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1228 .features[FEAT_8000_0001_ECX] =
27861ecc 1229 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1230 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1231 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1232 CPUID_EXT3_LAHF_LM,
021941b9
AP		 1233 .xlevel = 0x8000001A,
1234 .model_id = "AMD Opteron 63xx class CPU",
1235 },
c6dc6f63
AP		 1236};
1237
0668af54
EH		 1238/**
1239 * x86_cpu_compat_set_features:
1240 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1241 * @w: Identifies the feature word to be changed.
1242 * @feat_add: Feature bits to be added to feature word
1243 * @feat_remove: Feature bits to be removed from feature word
1244 *
1245 * Change CPU model feature bits for compatibility.
1246 *
1247 * This function may be used by machine-type compatibility functions
1248 * to enable or disable feature bits on specific CPU models.
1249 */
1250void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1251 uint32_t feat_add, uint32_t feat_remove)
1252{
9576de75 1253 X86CPUDefinition *def;
0668af54
EH		 1254 int i;
1255 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1256 def = &builtin_x86_defs[i];
1257 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1258 def->features[w] |= feat_add;
1259 def->features[w] &= ~feat_remove;
1260 }
1261 }
1262}
1263
4d1b279b
EH		 1264static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1265 bool migratable_only);
1266
d940ee9b
EH		 1267#ifdef CONFIG_KVM
1268
c6dc6f63
AP		 1269static int cpu_x86_fill_model_id(char *str)
1270{
1271 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1272 int i;
1273
1274 for (i = 0; i < 3; i++) {
1275 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1276 memcpy(str + i * 16 + 0, &eax, 4);
1277 memcpy(str + i * 16 + 4, &ebx, 4);
1278 memcpy(str + i * 16 + 8, &ecx, 4);
1279 memcpy(str + i * 16 + 12, &edx, 4);
1280 }
1281 return 0;
1282}
1283
d940ee9b
EH		 1284static X86CPUDefinition host_cpudef;
1285
84f1b92f 1286static Property host_x86_cpu_properties[] = {
120eee7d 1287 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1288 DEFINE_PROP_END_OF_LIST()
1289};
1290
d940ee9b 1291/* class_init for the "host" CPU model
6e746f30 1292 *
d940ee9b 1293 * This function may be called before KVM is initialized.
6e746f30 1294 */
d940ee9b 1295static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1296{
84f1b92f 1297 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1298 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1299 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1300
d940ee9b 1301 xcc->kvm_required = true;
6e746f30 1302
c6dc6f63 1303 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1304 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1305
1306 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1307 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1308 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1309 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1310
d940ee9b 1311 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1312
d940ee9b
EH		 1313 xcc->cpu_def = &host_cpudef;
1314 host_cpudef.cache_info_passthrough = true;
1315
1316 /* level, xlevel, xlevel2, and the feature words are initialized on
1317 * instance_init, because they require KVM to be initialized.
1318 */
84f1b92f
EH		 1319
1320 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1321}
1322
1323static void host_x86_cpu_initfn(Object *obj)
1324{
1325 X86CPU *cpu = X86_CPU(obj);
1326 CPUX86State *env = &cpu->env;
1327 KVMState *s = kvm_state;
d940ee9b
EH		 1328
1329 assert(kvm_enabled());
1330
4d1b279b
EH		 1331 /* We can't fill the features array here because we don't know yet if
1332 * "migratable" is true or false.
1333 */
1334 cpu->host_features = true;
1335
d940ee9b
EH		 1336 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1337 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1338 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1339
d940ee9b 1340 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1341}
1342
d940ee9b
EH		 1343static const TypeInfo host_x86_cpu_type_info = {
1344 .name = X86_CPU_TYPE_NAME("host"),
1345 .parent = TYPE_X86_CPU,
1346 .instance_init = host_x86_cpu_initfn,
1347 .class_init = host_x86_cpu_class_init,
1348};
1349
1350#endif
1351
8459e396 1352static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1353{
8459e396 1354 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1355 int i;
1356
857aee33 1357 for (i = 0; i < 32; ++i) {
c6dc6f63 1358 if (1 << i & mask) {
bffd67b0 1359 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1360 assert(reg);
fefb41bf 1361 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1362 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1363 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1364 f->cpuid_eax, reg,
1365 f->feat_names[i] ? "." : "",
1366 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1367 }
857aee33 1368 }
c6dc6f63
AP		 1369}
1370
95b8519d
AF		 1371static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1372 const char *name, Error **errp)
1373{
1374 X86CPU *cpu = X86_CPU(obj);
1375 CPUX86State *env = &cpu->env;
1376 int64_t value;
1377
1378 value = (env->cpuid_version >> 8) & 0xf;
1379 if (value == 0xf) {
1380 value += (env->cpuid_version >> 20) & 0xff;
1381 }
1382 visit_type_int(v, &value, name, errp);
1383}
1384
71ad61d3
AF		 1385static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1386 const char *name, Error **errp)
ed5e1ec3 1387{
71ad61d3
AF		 1388 X86CPU *cpu = X86_CPU(obj);
1389 CPUX86State *env = &cpu->env;
1390 const int64_t min = 0;
1391 const int64_t max = 0xff + 0xf;
65cd9064 1392 Error *local_err = NULL;
71ad61d3
AF		 1393 int64_t value;
1394
65cd9064
MA		 1395 visit_type_int(v, &value, name, &local_err);
1396 if (local_err) {
1397 error_propagate(errp, local_err);
71ad61d3
AF		 1398 return;
1399 }
1400 if (value < min || value > max) {
1401 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1402 name ? name : "null", value, min, max);
1403 return;
1404 }
1405
ed5e1ec3 1406 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1407 if (value > 0x0f) {
1408 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1409 } else {
71ad61d3 1410 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1411 }
1412}
1413
67e30c83
AF		 1414static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1415 const char *name, Error **errp)
1416{
1417 X86CPU *cpu = X86_CPU(obj);
1418 CPUX86State *env = &cpu->env;
1419 int64_t value;
1420
1421 value = (env->cpuid_version >> 4) & 0xf;
1422 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1423 visit_type_int(v, &value, name, errp);
1424}
1425
c5291a4f
AF		 1426static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1427 const char *name, Error **errp)
b0704cbd 1428{
c5291a4f
AF		 1429 X86CPU *cpu = X86_CPU(obj);
1430 CPUX86State *env = &cpu->env;
1431 const int64_t min = 0;
1432 const int64_t max = 0xff;
65cd9064 1433 Error *local_err = NULL;
c5291a4f
AF		 1434 int64_t value;
1435
65cd9064
MA		 1436 visit_type_int(v, &value, name, &local_err);
1437 if (local_err) {
1438 error_propagate(errp, local_err);
c5291a4f
AF		 1439 return;
1440 }
1441 if (value < min || value > max) {
1442 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1443 name ? name : "null", value, min, max);
1444 return;
1445 }
1446
b0704cbd 1447 env->cpuid_version &= ~0xf00f0;
c5291a4f 1448 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1449}
1450
35112e41
AF		 1451static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1452 void *opaque, const char *name,
1453 Error **errp)
1454{
1455 X86CPU *cpu = X86_CPU(obj);
1456 CPUX86State *env = &cpu->env;
1457 int64_t value;
1458
1459 value = env->cpuid_version & 0xf;
1460 visit_type_int(v, &value, name, errp);
1461}
1462
036e2222
AF		 1463static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1464 void *opaque, const char *name,
1465 Error **errp)
38c3dc46 1466{
036e2222
AF		 1467 X86CPU *cpu = X86_CPU(obj);
1468 CPUX86State *env = &cpu->env;
1469 const int64_t min = 0;
1470 const int64_t max = 0xf;
65cd9064 1471 Error *local_err = NULL;
036e2222
AF		 1472 int64_t value;
1473
65cd9064
MA		 1474 visit_type_int(v, &value, name, &local_err);
1475 if (local_err) {
1476 error_propagate(errp, local_err);
036e2222
AF		 1477 return;
1478 }
1479 if (value < min || value > max) {
1480 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1481 name ? name : "null", value, min, max);
1482 return;
1483 }
1484
38c3dc46 1485 env->cpuid_version &= ~0xf;
036e2222 1486 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1487}
1488
8e1898bf
AF		 1489static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1490 const char *name, Error **errp)
1491{
1492 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1493
fa029887 1494 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1495}
1496
1497static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1498 const char *name, Error **errp)
1499{
1500 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1501
fa029887 1502 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1503}
1504
16b93aa8
AF		 1505static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1506 const char *name, Error **errp)
1507{
1508 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1509
fa029887 1510 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1511}
1512
1513static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1514 const char *name, Error **errp)
1515{
1516 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1517
fa029887 1518 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1519}
1520
d480e1af
AF		 1521static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1522{
1523 X86CPU *cpu = X86_CPU(obj);
1524 CPUX86State *env = &cpu->env;
1525 char *value;
d480e1af 1526
9df694ee 1527 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1528 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1529 env->cpuid_vendor3);
d480e1af
AF		 1530 return value;
1531}
1532
1533static void x86_cpuid_set_vendor(Object *obj, const char *value,
1534 Error **errp)
1535{
1536 X86CPU *cpu = X86_CPU(obj);
1537 CPUX86State *env = &cpu->env;
1538 int i;
1539
9df694ee 1540 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1541 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1542 "vendor", value);
1543 return;
1544 }
1545
1546 env->cpuid_vendor1 = 0;
1547 env->cpuid_vendor2 = 0;
1548 env->cpuid_vendor3 = 0;
1549 for (i = 0; i < 4; i++) {
1550 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1551 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1552 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1553 }
d480e1af
AF		 1554}
1555
63e886eb
AF		 1556static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1557{
1558 X86CPU *cpu = X86_CPU(obj);
1559 CPUX86State *env = &cpu->env;
1560 char *value;
1561 int i;
1562
1563 value = g_malloc(48 + 1);
1564 for (i = 0; i < 48; i++) {
1565 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1566 }
1567 value[48] = '\0';
1568 return value;
1569}
1570
938d4c25
AF		 1571static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1572 Error **errp)
dcce6675 1573{
938d4c25
AF		 1574 X86CPU *cpu = X86_CPU(obj);
1575 CPUX86State *env = &cpu->env;
dcce6675
AF		 1576 int c, len, i;
1577
1578 if (model_id == NULL) {
1579 model_id = "";
1580 }
1581 len = strlen(model_id);
d0a6acf4 1582 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1583 for (i = 0; i < 48; i++) {
1584 if (i >= len) {
1585 c = '\0';
1586 } else {
1587 c = (uint8_t)model_id[i];
1588 }
1589 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1590 }
1591}
1592
89e48965
AF		 1593static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1594 const char *name, Error **errp)
1595{
1596 X86CPU *cpu = X86_CPU(obj);
1597 int64_t value;
1598
1599 value = cpu->env.tsc_khz * 1000;
1600 visit_type_int(v, &value, name, errp);
1601}
1602
1603static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1604 const char *name, Error **errp)
1605{
1606 X86CPU *cpu = X86_CPU(obj);
1607 const int64_t min = 0;
2e84849a 1608 const int64_t max = INT64_MAX;
65cd9064 1609 Error *local_err = NULL;
89e48965
AF		 1610 int64_t value;
1611
65cd9064
MA		 1612 visit_type_int(v, &value, name, &local_err);
1613 if (local_err) {
1614 error_propagate(errp, local_err);
89e48965
AF		 1615 return;
1616 }
1617 if (value < min || value > max) {
1618 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1619 name ? name : "null", value, min, max);
1620 return;
1621 }
1622
1623 cpu->env.tsc_khz = value / 1000;
1624}
1625
31050930
IM		 1626static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1627 const char *name, Error **errp)
1628{
1629 X86CPU *cpu = X86_CPU(obj);
1630 int64_t value = cpu->env.cpuid_apic_id;
1631
1632 visit_type_int(v, &value, name, errp);
1633}
1634
1635static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1636 const char *name, Error **errp)
1637{
1638 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1639 DeviceState *dev = DEVICE(obj);
31050930
IM		 1640 const int64_t min = 0;
1641 const int64_t max = UINT32_MAX;
1642 Error *error = NULL;
1643 int64_t value;
1644
8d6d4980
IM		 1645 if (dev->realized) {
1646 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1647 "it was realized", name, object_get_typename(obj));
1648 return;
1649 }
1650
31050930
IM		 1651 visit_type_int(v, &value, name, &error);
1652 if (error) {
1653 error_propagate(errp, error);
1654 return;
1655 }
1656 if (value < min || value > max) {
1657 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1658 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1659 object_get_typename(obj), name, value, min, max);
1660 return;
1661 }
1662
1663 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1664 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1665 return;
1666 }
1667 cpu->env.cpuid_apic_id = value;
1668}
1669
7e5292b5 1670/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1671static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1672 const char *name, Error **errp)
1673{
7e5292b5 1674 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1675 FeatureWord w;
1676 Error *err = NULL;
1677 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1678 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1679 X86CPUFeatureWordInfoList *list = NULL;
1680
1681 for (w = 0; w < FEATURE_WORDS; w++) {
1682 FeatureWordInfo *wi = &feature_word_info[w];
1683 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1684 qwi->cpuid_input_eax = wi->cpuid_eax;
1685 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1686 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1687 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1688 qwi->features = array[w];
8e8aba50
EH		 1689
1690 /* List will be in reverse order, but order shouldn't matter */
1691 list_entries[w].next = list;
1692 list_entries[w].value = &word_infos[w];
1693 list = &list_entries[w];
1694 }
1695
1696 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1697 error_propagate(errp, err);
1698}
1699
c8f0f88e
IM		 1700static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1701 const char *name, Error **errp)
1702{
1703 X86CPU *cpu = X86_CPU(obj);
1704 int64_t value = cpu->hyperv_spinlock_attempts;
1705
1706 visit_type_int(v, &value, name, errp);
1707}
1708
1709static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1710 const char *name, Error **errp)
1711{
1712 const int64_t min = 0xFFF;
1713 const int64_t max = UINT_MAX;
1714 X86CPU *cpu = X86_CPU(obj);
1715 Error *err = NULL;
1716 int64_t value;
1717
1718 visit_type_int(v, &value, name, &err);
1719 if (err) {
1720 error_propagate(errp, err);
1721 return;
1722 }
1723
1724 if (value < min || value > max) {
1725 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1726 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1727 object_get_typename(obj), name ? name : "null",
1728 value, min, max);
c8f0f88e
IM		 1729 return;
1730 }
1731 cpu->hyperv_spinlock_attempts = value;
1732}
1733
1734static PropertyInfo qdev_prop_spinlocks = {
1735 .name = "int",
1736 .get = x86_get_hv_spinlocks,
1737 .set = x86_set_hv_spinlocks,
1738};
1739
72ac2e87
IM		 1740/* Convert all '_' in a feature string option name to '-', to make feature
1741 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1742 */
1743static inline void feat2prop(char *s)
1744{
1745 while ((s = strchr(s, '_'))) {
1746 *s = '-';
1747 }
1748}
1749
8f961357
EH		 1750/* Parse "+feature,-feature,feature=foo" CPU feature string
1751 */
94a444b2
AF		 1752static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1753 Error **errp)
8f961357 1754{
94a444b2 1755 X86CPU *cpu = X86_CPU(cs);
8f961357 1756 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1757 FeatureWord w;
8f961357 1758 /* Features to be added */
077c68c3 1759 FeatureWordArray plus_features = { 0 };
8f961357 1760 /* Features to be removed */
5ef57876 1761 FeatureWordArray minus_features = { 0 };
8f961357 1762 uint32_t numvalue;
a91987c2 1763 CPUX86State *env = &cpu->env;
94a444b2 1764 Error *local_err = NULL;
8f961357 1765
8f961357 1766 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1767
1768 while (featurestr) {
1769 char *val;
1770 if (featurestr[0] == '+') {
c00c94ab 1771 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1772 } else if (featurestr[0] == '-') {
c00c94ab 1773 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1774 } else if ((val = strchr(featurestr, '='))) {
1775 *val = 0; val++;
72ac2e87 1776 feat2prop(featurestr);
d024d209 1777 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1778 char *err;
a91987c2
IM		 1779 char num[32];
1780
c6dc6f63
AP		 1781 numvalue = strtoul(val, &err, 0);
1782 if (!*val || *err) {
6b1dd54b
PB		 1783 error_setg(errp, "bad numerical value %s", val);
1784 return;
c6dc6f63
AP		 1785 }
1786 if (numvalue < 0x80000000) {
94a444b2
AF		 1787 error_report("xlevel value shall always be >= 0x80000000"
1788 ", fixup will be removed in future versions");
2f7a21c4 1789 numvalue += 0x80000000;
c6dc6f63 1790 }
a91987c2 1791 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1792 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1793 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1794 int64_t tsc_freq;
1795 char *err;
a91987c2 1796 char num[32];
b862d1fe
JR		 1797
1798 tsc_freq = strtosz_suffix_unit(val, &err,
1799 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1800 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1801 error_setg(errp, "bad numerical value %s", val);
1802 return;
b862d1fe 1803 }
a91987c2 1804 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1805 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1806 &local_err);
72ac2e87 1807 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1808 char *err;
92067bf4 1809 const int min = 0xFFF;
c8f0f88e 1810 char num[32];
28f52cc0
VR		 1811 numvalue = strtoul(val, &err, 0);
1812 if (!*val || *err) {
6b1dd54b
PB		 1813 error_setg(errp, "bad numerical value %s", val);
1814 return;
28f52cc0 1815 }
92067bf4 1816 if (numvalue < min) {
94a444b2 1817 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1818 ", fixup will be removed in future versions",
1819 min);
92067bf4
IM		 1820 numvalue = min;
1821 }
c8f0f88e 1822 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1823 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1824 } else {
94a444b2 1825 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1826 }
c6dc6f63 1827 } else {
258f5abe 1828 feat2prop(featurestr);
94a444b2 1829 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1830 }
94a444b2
AF		 1831 if (local_err) {
1832 error_propagate(errp, local_err);
6b1dd54b 1833 return;
c6dc6f63
AP		 1834 }
1835 featurestr = strtok(NULL, ",");
1836 }
e1c224b4 1837
4d1b279b
EH		 1838 if (cpu->host_features) {
1839 for (w = 0; w < FEATURE_WORDS; w++) {
1840 env->features[w] =
1841 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1842 }
1843 }
1844
e1c224b4
EH		 1845 for (w = 0; w < FEATURE_WORDS; w++) {
1846 env->features[w] |= plus_features[w];
1847 env->features[w] &= ~minus_features[w];
1848 }
c6dc6f63
AP		 1849}
1850
1851/* generate a composite string into buf of all cpuid names in featureset
1852 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1853 * if flags, suppress names undefined in featureset.
1854 */
1855static void listflags(char *buf, int bufsize, uint32_t fbits,
1856 const char **featureset, uint32_t flags)
1857{
1858 const char **p = &featureset[31];
1859 char *q, *b, bit;
1860 int nc;
1861
1862 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1863 *buf = '\0';
1864 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1865 if (fbits & 1 << bit && (*p || !flags)) {
1866 if (*p)
1867 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1868 else
1869 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1870 if (bufsize <= nc) {
1871 if (b) {
1872 memcpy(b, "...", sizeof("..."));
1873 }
1874 return;
1875 }
1876 q += nc;
1877 bufsize -= nc;
1878 }
1879}
1880
e916cbf8
PM		 1881/* generate CPU information. */
1882void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1883{
9576de75 1884 X86CPUDefinition *def;
c6dc6f63 1885 char buf[256];
7fc9b714 1886 int i;
c6dc6f63 1887
7fc9b714
AF		 1888 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1889 def = &builtin_x86_defs[i];
c04321b3 1890 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1891 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1892 }
21ad7789
JK		 1893#ifdef CONFIG_KVM
1894 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1895 "KVM processor with all supported host features "
1896 "(only available in KVM mode)");
1897#endif
1898
6cdf8854 1899 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1900 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1901 FeatureWordInfo *fw = &feature_word_info[i];
1902
1903 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1904 (*cpu_fprintf)(f, " %s\n", buf);
1905 }
c6dc6f63
AP		 1906}
1907
76b64a7a 1908CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1909{
1910 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1911 X86CPUDefinition *def;
7fc9b714 1912 int i;
e3966126 1913
7fc9b714 1914 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1915 CpuDefinitionInfoList *entry;
1916 CpuDefinitionInfo *info;
1917
7fc9b714 1918 def = &builtin_x86_defs[i];
e3966126
AL		 1919 info = g_malloc0(sizeof(*info));
1920 info->name = g_strdup(def->name);
1921
1922 entry = g_malloc0(sizeof(*entry));
1923 entry->value = info;
1924 entry->next = cpu_list;
1925 cpu_list = entry;
1926 }
1927
1928 return cpu_list;
1929}
1930
84f1b92f
EH		 1931static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1932 bool migratable_only)
27418adf
EH		 1933{
1934 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 1935 uint32_t r;
27418adf 1936
fefb41bf 1937 if (kvm_enabled()) {
84f1b92f
EH		 1938 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1939 wi->cpuid_ecx,
1940 wi->cpuid_reg);
fefb41bf 1941 } else if (tcg_enabled()) {
84f1b92f 1942 r = wi->tcg_features;
fefb41bf
EH		 1943 } else {
1944 return ~0;
1945 }
84f1b92f
EH		 1946 if (migratable_only) {
1947 r &= x86_cpu_get_migratable_flags(w);
1948 }
1949 return r;
27418adf
EH		 1950}
1951
51f63aed
EH		 1952/*
1953 * Filters CPU feature words based on host availability of each feature.
1954 *
51f63aed
EH		 1955 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1956 */
27418adf 1957static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 1958{
1959 CPUX86State *env = &cpu->env;
bd87d2a2 1960 FeatureWord w;
51f63aed
EH		 1961 int rv = 0;
1962
bd87d2a2 1963 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 1964 uint32_t host_feat =
1965 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 1966 uint32_t requested_features = env->features[w];
1967 env->features[w] &= host_feat;
1968 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 1969 if (cpu->filtered_features[w]) {
1970 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 1971 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 1972 }
1973 rv = 1;
1974 }
bd87d2a2 1975 }
51f63aed
EH		 1976
1977 return rv;
bc74b7db 1978}
bc74b7db 1979
d940ee9b 1980/* Load data from X86CPUDefinition
c080e30e 1981 */
d940ee9b 1982static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 1983{
61dcd775 1984 CPUX86State *env = &cpu->env;
74f54bc4
EH		 1985 const char *vendor;
1986 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 1987 FeatureWord w;
c6dc6f63 1988
2d64255b
AF		 1989 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1990 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1991 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1992 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 1993 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 1994 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 1995 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 1996 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 1997 for (w = 0; w < FEATURE_WORDS; w++) {
1998 env->features[w] = def->features[w];
1999 }
82beb536 2000
9576de75 2001 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2002 if (kvm_enabled()) {
5fcca9ff
EH		 2003 FeatureWord w;
2004 for (w = 0; w < FEATURE_WORDS; w++) {
2005 env->features[w] |= kvm_default_features[w];
136a7e9a 2006 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2007 }
82beb536 2008 }
5fcca9ff 2009
82beb536 2010 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2011
2012 /* sysenter isn't supported in compatibility mode on AMD,
2013 * syscall isn't supported in compatibility mode on Intel.
2014 * Normally we advertise the actual CPU vendor, but you can
2015 * override this using the 'vendor' property if you want to use
2016 * KVM's sysenter/syscall emulation in compatibility mode and
2017 * when doing cross vendor migration
2018 */
74f54bc4 2019 vendor = def->vendor;
7c08db30
EH		 2020 if (kvm_enabled()) {
2021 uint32_t ebx = 0, ecx = 0, edx = 0;
2022 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2023 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2024 vendor = host_vendor;
2025 }
2026
2027 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2028
c6dc6f63
AP		 2029}
2030
62fc403f
IM		 2031X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
2032 Error **errp)
5c3c6a68 2033{
2d64255b 2034 X86CPU *cpu = NULL;
d940ee9b 2035 X86CPUClass *xcc;
500050d1 2036 ObjectClass *oc;
2d64255b
AF		 2037 gchar **model_pieces;
2038 char *name, *features;
5c3c6a68
AF		 2039 Error *error = NULL;
2040
2d64255b
AF		 2041 model_pieces = g_strsplit(cpu_model, ",", 2);
2042 if (!model_pieces[0]) {
2043 error_setg(&error, "Invalid/empty CPU model name");
2044 goto out;
2045 }
2046 name = model_pieces[0];
2047 features = model_pieces[1];
2048
500050d1
AF		 2049 oc = x86_cpu_class_by_name(name);
2050 if (oc == NULL) {
2051 error_setg(&error, "Unable to find CPU definition: %s", name);
2052 goto out;
2053 }
d940ee9b
EH		 2054 xcc = X86_CPU_CLASS(oc);
2055
2056 if (xcc->kvm_required && !kvm_enabled()) {
2057 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2058 goto out;
2059 }
2060
d940ee9b
EH		 2061 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2062
62fc403f
IM		 2063#ifndef CONFIG_USER_ONLY
2064 if (icc_bridge == NULL) {
2065 error_setg(&error, "Invalid icc-bridge value");
2066 goto out;
2067 }
2068 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2069 object_unref(OBJECT(cpu));
2070#endif
5c3c6a68 2071
94a444b2 2072 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2073 if (error) {
2074 goto out;
5c3c6a68
AF		 2075 }
2076
7f833247 2077out:
cd7b87ff
AF		 2078 if (error != NULL) {
2079 error_propagate(errp, error);
500050d1
AF		 2080 if (cpu) {
2081 object_unref(OBJECT(cpu));
2082 cpu = NULL;
2083 }
cd7b87ff 2084 }
7f833247
IM		 2085 g_strfreev(model_pieces);
2086 return cpu;
2087}
2088
2089X86CPU *cpu_x86_init(const char *cpu_model)
2090{
2091 Error *error = NULL;
2092 X86CPU *cpu;
2093
62fc403f 2094 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 2095 if (error) {
2d64255b
AF		 2096 goto out;
2097 }
2098
7f833247
IM		 2099 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2100
2d64255b 2101out:
2d64255b 2102 if (error) {
4a44d85e 2103 error_report("%s", error_get_pretty(error));
5c3c6a68 2104 error_free(error);
2d64255b
AF		 2105 if (cpu != NULL) {
2106 object_unref(OBJECT(cpu));
2107 cpu = NULL;
2108 }
5c3c6a68
AF		 2109 }
2110 return cpu;
2111}
2112
d940ee9b
EH		 2113static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2114{
2115 X86CPUDefinition *cpudef = data;
2116 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2117
2118 xcc->cpu_def = cpudef;
2119}
2120
2121static void x86_register_cpudef_type(X86CPUDefinition *def)
2122{
2123 char *typename = x86_cpu_type_name(def->name);
2124 TypeInfo ti = {
2125 .name = typename,
2126 .parent = TYPE_X86_CPU,
2127 .class_init = x86_cpu_cpudef_class_init,
2128 .class_data = def,
2129 };
2130
2131 type_register(&ti);
2132 g_free(typename);
2133}
2134
c6dc6f63 2135#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2136
0e26b7b8
BS		 2137void cpu_clear_apic_feature(CPUX86State *env)
2138{
0514ef2f 2139 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2140}
2141
c6dc6f63
AP		 2142#endif /* !CONFIG_USER_ONLY */
2143
c04321b3 2144/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2145 */
2146void x86_cpudef_setup(void)
2147{
93bfef4c
CV		 2148 int i, j;
2149 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2150
2151 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2152 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2153
2154 /* Look for specific "cpudef" models that */
09faecf2 2155 /* have the QEMU version in .model_id */
93bfef4c 2156 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2157 if (strcmp(model_with_versions[j], def->name) == 0) {
2158 pstrcpy(def->model_id, sizeof(def->model_id),
2159 "QEMU Virtual CPU version ");
2160 pstrcat(def->model_id, sizeof(def->model_id),
2161 qemu_get_version());
93bfef4c
CV		 2162 break;
2163 }
2164 }
c6dc6f63 2165 }
c6dc6f63
AP		 2166}
2167
c6dc6f63
AP		 2168static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2169 uint32_t *ecx, uint32_t *edx)
2170{
2171 *ebx = env->cpuid_vendor1;
2172 *edx = env->cpuid_vendor2;
2173 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2174}
2175
2176void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2177 uint32_t *eax, uint32_t *ebx,
2178 uint32_t *ecx, uint32_t *edx)
2179{
a60f24b5
AF		 2180 X86CPU *cpu = x86_env_get_cpu(env);
2181 CPUState *cs = CPU(cpu);
2182
c6dc6f63
AP		 2183 /* test if maximum index reached */
2184 if (index & 0x80000000) {
b3baa152
BW		 2185 if (index > env->cpuid_xlevel) {
2186 if (env->cpuid_xlevel2 > 0) {
2187 /* Handle the Centaur's CPUID instruction. */
2188 if (index > env->cpuid_xlevel2) {
2189 index = env->cpuid_xlevel2;
2190 } else if (index < 0xC0000000) {
2191 index = env->cpuid_xlevel;
2192 }
2193 } else {
57f26ae7
EH		 2194 /* Intel documentation states that invalid EAX input will
2195 * return the same information as EAX=cpuid_level
2196 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2197 */
2198 index = env->cpuid_level;
b3baa152
BW		 2199 }
2200 }
c6dc6f63
AP		 2201 } else {
2202 if (index > env->cpuid_level)
2203 index = env->cpuid_level;
2204 }
2205
2206 switch(index) {
2207 case 0:
2208 *eax = env->cpuid_level;
2209 get_cpuid_vendor(env, ebx, ecx, edx);
2210 break;
2211 case 1:
2212 *eax = env->cpuid_version;
2213 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2214 *ecx = env->features[FEAT_1_ECX];
2215 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2216 if (cs->nr_cores * cs->nr_threads > 1) {
2217 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2218 *edx |= 1 << 28; /* HTT bit */
2219 }
2220 break;
2221 case 2:
2222 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2223 if (cpu->cache_info_passthrough) {
2224 host_cpuid(index, 0, eax, ebx, ecx, edx);
2225 break;
2226 }
5e891bf8 2227 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2228 *ebx = 0;
2229 *ecx = 0;
5e891bf8
EH		 2230 *edx = (L1D_DESCRIPTOR << 16) | \
2231 (L1I_DESCRIPTOR << 8) | \
2232 (L2_DESCRIPTOR);
c6dc6f63
AP		 2233 break;
2234 case 4:
2235 /* cache info: needed for Core compatibility */
787aaf57
BC		 2236 if (cpu->cache_info_passthrough) {
2237 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2238 *eax &= ~0xFC000000;
c6dc6f63 2239 } else {
2f7a21c4 2240 *eax = 0;
76c2975a 2241 switch (count) {
c6dc6f63 2242 case 0: /* L1 dcache info */
5e891bf8
EH		 2243 *eax |= CPUID_4_TYPE_DCACHE | \
2244 CPUID_4_LEVEL(1) | \
2245 CPUID_4_SELF_INIT_LEVEL;
2246 *ebx = (L1D_LINE_SIZE - 1) | \
2247 ((L1D_PARTITIONS - 1) << 12) | \
2248 ((L1D_ASSOCIATIVITY - 1) << 22);
2249 *ecx = L1D_SETS - 1;
2250 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2251 break;
2252 case 1: /* L1 icache info */
5e891bf8
EH		 2253 *eax |= CPUID_4_TYPE_ICACHE | \
2254 CPUID_4_LEVEL(1) | \
2255 CPUID_4_SELF_INIT_LEVEL;
2256 *ebx = (L1I_LINE_SIZE - 1) | \
2257 ((L1I_PARTITIONS - 1) << 12) | \
2258 ((L1I_ASSOCIATIVITY - 1) << 22);
2259 *ecx = L1I_SETS - 1;
2260 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2261 break;
2262 case 2: /* L2 cache info */
5e891bf8
EH		 2263 *eax |= CPUID_4_TYPE_UNIFIED | \
2264 CPUID_4_LEVEL(2) | \
2265 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2266 if (cs->nr_threads > 1) {
2267 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2268 }
5e891bf8
EH		 2269 *ebx = (L2_LINE_SIZE - 1) | \
2270 ((L2_PARTITIONS - 1) << 12) | \
2271 ((L2_ASSOCIATIVITY - 1) << 22);
2272 *ecx = L2_SETS - 1;
2273 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2274 break;
2275 default: /* end of info */
2276 *eax = 0;
2277 *ebx = 0;
2278 *ecx = 0;
2279 *edx = 0;
2280 break;
76c2975a
PB		 2281 }
2282 }
2283
2284 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2285 if ((*eax & 31) && cs->nr_cores > 1) {
2286 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2287 }
2288 break;
2289 case 5:
2290 /* mwait info: needed for Core compatibility */
2291 *eax = 0; /* Smallest monitor-line size in bytes */
2292 *ebx = 0; /* Largest monitor-line size in bytes */
2293 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2294 *edx = 0;
2295 break;
2296 case 6:
2297 /* Thermal and Power Leaf */
2298 *eax = 0;
2299 *ebx = 0;
2300 *ecx = 0;
2301 *edx = 0;
2302 break;
f7911686 2303 case 7:
13526728
EH		 2304 /* Structured Extended Feature Flags Enumeration Leaf */
2305 if (count == 0) {
2306 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2307 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2308 *ecx = 0; /* Reserved */
2309 *edx = 0; /* Reserved */
f7911686
YW		 2310 } else {
2311 *eax = 0;
2312 *ebx = 0;
2313 *ecx = 0;
2314 *edx = 0;
2315 }
2316 break;
c6dc6f63
AP		 2317 case 9:
2318 /* Direct Cache Access Information Leaf */
2319 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2320 *ebx = 0;
2321 *ecx = 0;
2322 *edx = 0;
2323 break;
2324 case 0xA:
2325 /* Architectural Performance Monitoring Leaf */
9337e3b6 2326 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2327 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2328
2329 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2330 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2331 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2332 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2333 } else {
2334 *eax = 0;
2335 *ebx = 0;
2336 *ecx = 0;
2337 *edx = 0;
2338 }
c6dc6f63 2339 break;
2560f19f
PB		 2340 case 0xD: {
2341 KVMState *s = cs->kvm_state;
2342 uint64_t kvm_mask;
2343 int i;
2344
51e49430 2345 /* Processor Extended State */
2560f19f
PB		 2346 *eax = 0;
2347 *ebx = 0;
2348 *ecx = 0;
2349 *edx = 0;
2350 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2351 break;
2352 }
2560f19f
PB		 2353 kvm_mask =
2354 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2355 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2356
2560f19f
PB		 2357 if (count == 0) {
2358 *ecx = 0x240;
2359 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2360 const ExtSaveArea *esa = &ext_save_areas[i];
2361 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2362 (kvm_mask & (1 << i)) != 0) {
2363 if (i < 32) {
2364 *eax |= 1 << i;
2365 } else {
2366 *edx |= 1 << (i - 32);
2367 }
2368 *ecx = MAX(*ecx, esa->offset + esa->size);
2369 }
2370 }
2371 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2372 *ebx = *ecx;
2373 } else if (count == 1) {
2374 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2375 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2376 const ExtSaveArea *esa = &ext_save_areas[count];
2377 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2378 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2379 *eax = esa->size;
2380 *ebx = esa->offset;
2560f19f 2381 }
51e49430
SY		 2382 }
2383 break;
2560f19f 2384 }
c6dc6f63
AP		 2385 case 0x80000000:
2386 *eax = env->cpuid_xlevel;
2387 *ebx = env->cpuid_vendor1;
2388 *edx = env->cpuid_vendor2;
2389 *ecx = env->cpuid_vendor3;
2390 break;
2391 case 0x80000001:
2392 *eax = env->cpuid_version;
2393 *ebx = 0;
0514ef2f
EH		 2394 *ecx = env->features[FEAT_8000_0001_ECX];
2395 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2396
2397 /* The Linux kernel checks for the CMPLegacy bit and
2398 * discards multiple thread information if it is set.
2399 * So dont set it here for Intel to make Linux guests happy.
2400 */
ce3960eb 2401 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2402 uint32_t tebx, tecx, tedx;
2403 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2404 if (tebx != CPUID_VENDOR_INTEL_1 ||
2405 tedx != CPUID_VENDOR_INTEL_2 ||
2406 tecx != CPUID_VENDOR_INTEL_3) {
2407 *ecx |= 1 << 1; /* CmpLegacy bit */
2408 }
2409 }
c6dc6f63
AP		 2410 break;
2411 case 0x80000002:
2412 case 0x80000003:
2413 case 0x80000004:
2414 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2415 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2416 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2417 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2418 break;
2419 case 0x80000005:
2420 /* cache info (L1 cache) */
787aaf57
BC		 2421 if (cpu->cache_info_passthrough) {
2422 host_cpuid(index, 0, eax, ebx, ecx, edx);
2423 break;
2424 }
5e891bf8
EH		 2425 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2426 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2427 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2428 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2429 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2430 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2431 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2432 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2433 break;
2434 case 0x80000006:
2435 /* cache info (L2 cache) */
787aaf57
BC		 2436 if (cpu->cache_info_passthrough) {
2437 host_cpuid(index, 0, eax, ebx, ecx, edx);
2438 break;
2439 }
5e891bf8
EH		 2440 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2441 (L2_DTLB_2M_ENTRIES << 16) | \
2442 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2443 (L2_ITLB_2M_ENTRIES);
2444 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2445 (L2_DTLB_4K_ENTRIES << 16) | \
2446 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2447 (L2_ITLB_4K_ENTRIES);
2448 *ecx = (L2_SIZE_KB_AMD << 16) | \
2449 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2450 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2451 *edx = ((L3_SIZE_KB/512) << 18) | \
2452 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2453 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2454 break;
303752a9
MT		 2455 case 0x80000007:
2456 *eax = 0;
2457 *ebx = 0;
2458 *ecx = 0;
2459 *edx = env->features[FEAT_8000_0007_EDX];
2460 break;
c6dc6f63
AP		 2461 case 0x80000008:
2462 /* virtual & phys address size in low 2 bytes. */
2463/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2464 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2465 /* 64 bit processor */
2466/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2467 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2468 } else {
0514ef2f 2469 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2470 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2471 } else {
c6dc6f63 2472 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2473 }
c6dc6f63
AP		 2474 }
2475 *ebx = 0;
2476 *ecx = 0;
2477 *edx = 0;
ce3960eb
AF		 2478 if (cs->nr_cores * cs->nr_threads > 1) {
2479 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2480 }
2481 break;
2482 case 0x8000000A:
0514ef2f 2483 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2484 *eax = 0x00000001; /* SVM Revision */
2485 *ebx = 0x00000010; /* nr of ASIDs */
2486 *ecx = 0;
0514ef2f 2487 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2488 } else {
2489 *eax = 0;
2490 *ebx = 0;
2491 *ecx = 0;
2492 *edx = 0;
2493 }
c6dc6f63 2494 break;
b3baa152
BW		 2495 case 0xC0000000:
2496 *eax = env->cpuid_xlevel2;
2497 *ebx = 0;
2498 *ecx = 0;
2499 *edx = 0;
2500 break;
2501 case 0xC0000001:
2502 /* Support for VIA CPU's CPUID instruction */
2503 *eax = env->cpuid_version;
2504 *ebx = 0;
2505 *ecx = 0;
0514ef2f 2506 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2507 break;
2508 case 0xC0000002:
2509 case 0xC0000003:
2510 case 0xC0000004:
2511 /* Reserved for the future, and now filled with zero */
2512 *eax = 0;
2513 *ebx = 0;
2514 *ecx = 0;
2515 *edx = 0;
2516 break;
c6dc6f63
AP		 2517 default:
2518 /* reserved values: zero */
2519 *eax = 0;
2520 *ebx = 0;
2521 *ecx = 0;
2522 *edx = 0;
2523 break;
2524 }
2525}
5fd2087a
AF		 2526
2527/* CPUClass::reset() */
2528static void x86_cpu_reset(CPUState *s)
2529{
2530 X86CPU *cpu = X86_CPU(s);
2531 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2532 CPUX86State *env = &cpu->env;
c1958aea
AF		 2533 int i;
2534
5fd2087a
AF		 2535 xcc->parent_reset(s);
2536
43175fa9 2537 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2538
00c8cb0a 2539 tlb_flush(s, 1);
c1958aea
AF		 2540
2541 env->old_exception = -1;
2542
2543 /* init to reset state */
2544
2545#ifdef CONFIG_SOFTMMU
2546 env->hflags |= HF_SOFTMMU_MASK;
2547#endif
2548 env->hflags2 |= HF2_GIF_MASK;
2549
2550 cpu_x86_update_cr0(env, 0x60000010);
2551 env->a20_mask = ~0x0;
2552 env->smbase = 0x30000;
2553
2554 env->idt.limit = 0xffff;
2555 env->gdt.limit = 0xffff;
2556 env->ldt.limit = 0xffff;
2557 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2558 env->tr.limit = 0xffff;
2559 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2560
2561 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2562 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2563 DESC_R_MASK | DESC_A_MASK);
2564 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2565 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2566 DESC_A_MASK);
2567 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2568 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2569 DESC_A_MASK);
2570 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2571 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2572 DESC_A_MASK);
2573 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2574 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2575 DESC_A_MASK);
2576 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2577 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2578 DESC_A_MASK);
2579
2580 env->eip = 0xfff0;
2581 env->regs[R_EDX] = env->cpuid_version;
2582
2583 env->eflags = 0x2;
2584
2585 /* FPU init */
2586 for (i = 0; i < 8; i++) {
2587 env->fptags[i] = 1;
2588 }
5bde1407 2589 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2590
2591 env->mxcsr = 0x1f80;
c74f41bb 2592 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2593
2594 env->pat = 0x0007040600070406ULL;
2595 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2596
2597 memset(env->dr, 0, sizeof(env->dr));
2598 env->dr[6] = DR6_FIXED_1;
2599 env->dr[7] = DR7_FIXED_1;
b3310ab3 2600 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2601 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2602
05e7e819 2603 env->xcr0 = 1;
0522604b 2604
9db2efd9
AW		 2605 /*
2606 * SDM 11.11.5 requires:
2607 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2608 * - IA32_MTRR_PHYSMASKn.V = 0
2609 * All other bits are undefined. For simplification, zero it all.
2610 */
2611 env->mtrr_deftype = 0;
2612 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2613 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2614
dd673288
IM		 2615#if !defined(CONFIG_USER_ONLY)
2616 /* We hard-wire the BSP to the first CPU. */
55e5c285 2617 if (s->cpu_index == 0) {
02e51483 2618 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2619 }
2620
259186a7 2621 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2622
2623 if (kvm_enabled()) {
2624 kvm_arch_reset_vcpu(cpu);
2625 }
dd673288 2626#endif
5fd2087a
AF		 2627}
2628
dd673288
IM		 2629#ifndef CONFIG_USER_ONLY
2630bool cpu_is_bsp(X86CPU *cpu)
2631{
02e51483 2632 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2633}
65dee380
IM		 2634
2635/* TODO: remove me, when reset over QOM tree is implemented */
2636static void x86_cpu_machine_reset_cb(void *opaque)
2637{
2638 X86CPU *cpu = opaque;
2639 cpu_reset(CPU(cpu));
2640}
dd673288
IM		 2641#endif
2642
de024815
AF		 2643static void mce_init(X86CPU *cpu)
2644{
2645 CPUX86State *cenv = &cpu->env;
2646 unsigned int bank;
2647
2648 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2649 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2650 (CPUID_MCE | CPUID_MCA)) {
2651 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2652 cenv->mcg_ctl = ~(uint64_t)0;
2653 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2654 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2655 }
2656 }
2657}
2658
bdeec802 2659#ifndef CONFIG_USER_ONLY
d3c64d6a 2660static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2661{
bdeec802 2662 CPUX86State *env = &cpu->env;
53a89e26 2663 DeviceState *dev = DEVICE(cpu);
449994eb 2664 APICCommonState *apic;
bdeec802
IM		 2665 const char *apic_type = "apic";
2666
2667 if (kvm_irqchip_in_kernel()) {
2668 apic_type = "kvm-apic";
2669 } else if (xen_enabled()) {
2670 apic_type = "xen-apic";
2671 }
2672
02e51483
CF		 2673 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2674 if (cpu->apic_state == NULL) {
bdeec802
IM		 2675 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2676 return;
2677 }
2678
2679 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2680 OBJECT(cpu->apic_state), NULL);
2681 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2682 /* TODO: convert to link<> */
02e51483 2683 apic = APIC_COMMON(cpu->apic_state);
60671e58 2684 apic->cpu = cpu;
d3c64d6a
IM		 2685}
2686
2687static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2688{
02e51483 2689 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2690 return;
2691 }
bdeec802 2692
02e51483 2693 if (qdev_init(cpu->apic_state)) {
bdeec802 2694 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2695 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2696 return;
2697 }
bdeec802 2698}
d3c64d6a
IM		 2699#else
2700static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2701{
2702}
bdeec802
IM		 2703#endif
2704
e48638fd
WH		 2705
2706#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2707 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2708 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2709#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2710 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2711 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2712static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2713{
14a10fc3 2714 CPUState *cs = CPU(dev);
2b6f294c
AF		 2715 X86CPU *cpu = X86_CPU(dev);
2716 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2717 CPUX86State *env = &cpu->env;
2b6f294c 2718 Error *local_err = NULL;
e48638fd 2719 static bool ht_warned;
b34d12d1 2720
0514ef2f 2721 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2722 env->cpuid_level = 7;
2723 }
7a059953 2724
9b15cd9e
IM		 2725 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2726 * CPUID[1].EDX.
2727 */
e48638fd 2728 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2729 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2730 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2731 & CPUID_EXT2_AMD_ALIASES);
2732 }
2733
fefb41bf
EH		 2734
2735 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2736 error_setg(&local_err,
2737 kvm_enabled() ?
2738 "Host doesn't support requested features" :
2739 "TCG doesn't support requested features");
2740 goto out;
4586f157
IM		 2741 }
2742
65dee380
IM		 2743#ifndef CONFIG_USER_ONLY
2744 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2745
0514ef2f 2746 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2747 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2748 if (local_err != NULL) {
4dc1f449 2749 goto out;
bdeec802
IM		 2750 }
2751 }
65dee380
IM		 2752#endif
2753
7a059953 2754 mce_init(cpu);
14a10fc3 2755 qemu_init_vcpu(cs);
d3c64d6a 2756
e48638fd
WH		 2757 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2758 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2759 * based on inputs (sockets,cores,threads), it is still better to gives
2760 * users a warning.
2761 *
2762 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2763 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2764 */
2765 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2766 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2767 " -smp options properly.");
2768 ht_warned = true;
2769 }
2770
d3c64d6a
IM		 2771 x86_cpu_apic_realize(cpu, &local_err);
2772 if (local_err != NULL) {
2773 goto out;
2774 }
14a10fc3 2775 cpu_reset(cs);
2b6f294c 2776
4dc1f449
IM		 2777 xcc->parent_realize(dev, &local_err);
2778out:
2779 if (local_err != NULL) {
2780 error_propagate(errp, local_err);
2781 return;
2782 }
7a059953
AF		 2783}
2784
8932cfdf
EH		 2785/* Enables contiguous-apic-ID mode, for compatibility */
2786static bool compat_apic_id_mode;
2787
2788void enable_compat_apic_id_mode(void)
2789{
2790 compat_apic_id_mode = true;
2791}
2792
cb41bad3
EH		 2793/* Calculates initial APIC ID for a specific CPU index
2794 *
2795 * Currently we need to be able to calculate the APIC ID from the CPU index
2796 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2797 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2798 * all CPUs up to max_cpus.
2799 */
2800uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2801{
8932cfdf
EH		 2802 uint32_t correct_id;
2803 static bool warned;
2804
2805 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2806 if (compat_apic_id_mode) {
2807 if (cpu_index != correct_id && !warned) {
2808 error_report("APIC IDs set in compatibility mode, "
2809 "CPU topology won't match the configuration");
2810 warned = true;
2811 }
2812 return cpu_index;
2813 } else {
2814 return correct_id;
2815 }
cb41bad3
EH		 2816}
2817
de024815
AF		 2818static void x86_cpu_initfn(Object *obj)
2819{
55e5c285 2820 CPUState *cs = CPU(obj);
de024815 2821 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2822 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2823 CPUX86State *env = &cpu->env;
d65e9815 2824 static int inited;
de024815 2825
c05efcb1 2826 cs->env_ptr = env;
de024815 2827 cpu_exec_init(env);
71ad61d3
AF		 2828
2829 object_property_add(obj, "family", "int",
95b8519d 2830 x86_cpuid_version_get_family,
71ad61d3 2831 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2832 object_property_add(obj, "model", "int",
67e30c83 2833 x86_cpuid_version_get_model,
c5291a4f 2834 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2835 object_property_add(obj, "stepping", "int",
35112e41 2836 x86_cpuid_version_get_stepping,
036e2222 2837 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2838 object_property_add(obj, "level", "int",
2839 x86_cpuid_get_level,
2840 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2841 object_property_add(obj, "xlevel", "int",
2842 x86_cpuid_get_xlevel,
2843 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2844 object_property_add_str(obj, "vendor",
2845 x86_cpuid_get_vendor,
2846 x86_cpuid_set_vendor, NULL);
938d4c25 2847 object_property_add_str(obj, "model-id",
63e886eb 2848 x86_cpuid_get_model_id,
938d4c25 2849 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2850 object_property_add(obj, "tsc-frequency", "int",
2851 x86_cpuid_get_tsc_freq,
2852 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2853 object_property_add(obj, "apic-id", "int",
2854 x86_cpuid_get_apic_id,
2855 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2856 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2857 x86_cpu_get_feature_words,
7e5292b5
EH		 2858 NULL, NULL, (void *)env->features, NULL);
2859 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2860 x86_cpu_get_feature_words,
2861 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2862
92067bf4 2863 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2864 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2865
d940ee9b
EH		 2866 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2867
d65e9815
IM		 2868 /* init various static tables used in TCG mode */
2869 if (tcg_enabled() && !inited) {
2870 inited = 1;
2871 optimize_flags_init();
d65e9815 2872 }
de024815
AF		 2873}
2874
997395d3
IM		 2875static int64_t x86_cpu_get_arch_id(CPUState *cs)
2876{
2877 X86CPU *cpu = X86_CPU(cs);
2878 CPUX86State *env = &cpu->env;
2879
2880 return env->cpuid_apic_id;
2881}
2882
444d5590
AF		 2883static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2884{
2885 X86CPU *cpu = X86_CPU(cs);
2886
2887 return cpu->env.cr[0] & CR0_PG_MASK;
2888}
2889
f45748f1
AF		 2890static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2891{
2892 X86CPU *cpu = X86_CPU(cs);
2893
2894 cpu->env.eip = value;
2895}
2896
bdf7ae5b
AF		 2897static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2898{
2899 X86CPU *cpu = X86_CPU(cs);
2900
2901 cpu->env.eip = tb->pc - tb->cs_base;
2902}
2903
8c2e1b00
AF		 2904static bool x86_cpu_has_work(CPUState *cs)
2905{
2906 X86CPU *cpu = X86_CPU(cs);
2907 CPUX86State *env = &cpu->env;
2908
2909 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2910 CPU_INTERRUPT_POLL)) &&
2911 (env->eflags & IF_MASK)) ||
2912 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2913 CPU_INTERRUPT_INIT |
2914 CPU_INTERRUPT_SIPI |
2915 CPU_INTERRUPT_MCE));
2916}
2917
9337e3b6
EH		 2918static Property x86_cpu_properties[] = {
2919 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2920 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2921 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2922 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2923 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2924 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2925 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2926 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2927 DEFINE_PROP_END_OF_LIST()
2928};
2929
5fd2087a
AF		 2930static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2931{
2932 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2933 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2934 DeviceClass *dc = DEVICE_CLASS(oc);
2935
2936 xcc->parent_realize = dc->realize;
2937 dc->realize = x86_cpu_realizefn;
62fc403f 2938 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2939 dc->props = x86_cpu_properties;
5fd2087a
AF		 2940
2941 xcc->parent_reset = cc->reset;
2942 cc->reset = x86_cpu_reset;
91b1df8c 2943 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2944
500050d1 2945 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2946 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2947 cc->has_work = x86_cpu_has_work;
97a8ea5a 2948 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 2949 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 2950 cc->dump_state = x86_cpu_dump_state;
f45748f1 2951 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2952 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2953 cc->gdb_read_register = x86_cpu_gdb_read_register;
2954 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2955 cc->get_arch_id = x86_cpu_get_arch_id;
2956 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2957#ifdef CONFIG_USER_ONLY
2958 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2959#else
a23bbfda 2960 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2961 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2962 cc->write_elf64_note = x86_cpu_write_elf64_note;
2963 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2964 cc->write_elf32_note = x86_cpu_write_elf32_note;
2965 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2966 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2967#endif
a0e372f0 2968 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 2969#ifndef CONFIG_USER_ONLY
2970 cc->debug_excp_handler = breakpoint_handler;
2971#endif
374e0cd4
RH		 2972 cc->cpu_exec_enter = x86_cpu_exec_enter;
2973 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 2974}
2975
2976static const TypeInfo x86_cpu_type_info = {
2977 .name = TYPE_X86_CPU,
2978 .parent = TYPE_CPU,
2979 .instance_size = sizeof(X86CPU),
de024815 2980 .instance_init = x86_cpu_initfn,
d940ee9b 2981 .abstract = true,
5fd2087a
AF		 2982 .class_size = sizeof(X86CPUClass),
2983 .class_init = x86_cpu_common_class_init,
2984};
2985
2986static void x86_cpu_register_types(void)
2987{
d940ee9b
EH		 2988 int i;
2989
5fd2087a 2990 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 2991 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2992 x86_register_cpudef_type(&builtin_x86_defs[i]);
2993 }
2994#ifdef CONFIG_KVM
2995 type_register_static(&host_x86_cpu_type_info);
2996#endif
5fd2087a
AF		 2997}
2998
2999type_init(x86_cpu_register_types)
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