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target-i386: add VME to all CPUs
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
8932cfdf 28#include "topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 260 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 262 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 264};
265
303752a9
MT		 266static const char *cpuid_apm_edx_feature_name[] = {
267 NULL, NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 "invtsc", NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275};
276
0bb0b2d2
PB		 277static const char *cpuid_xsave_feature_name[] = {
278 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286};
287
621626ce
EH		 288#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
289#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
290 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
291#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
292 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
293 CPUID_PSE36 | CPUID_FXSR)
294#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
295#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
296 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
297 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
298 CPUID_PAE | CPUID_SEP | CPUID_APIC)
299
300#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
301 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
302 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
303 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
304 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
305 /* partly implemented:
306 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
307 /* missing:
308 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
309#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
310 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
311 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
312 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
313 /* missing:
314 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
315 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
316 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
317 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
318 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
319 CPUID_EXT_RDRAND */
320
321#ifdef TARGET_X86_64
322#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
323#else
324#define TCG_EXT2_X86_64_FEATURES 0
325#endif
326
327#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
328 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
329 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
330 TCG_EXT2_X86_64_FEATURES)
331#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
332 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
333#define TCG_EXT4_FEATURES 0
334#define TCG_SVM_FEATURES 0
335#define TCG_KVM_FEATURES 0
336#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
337 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
338 /* missing:
339 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
340 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
341 CPUID_7_0_EBX_RDSEED */
303752a9 342#define TCG_APM_FEATURES 0
621626ce
EH		 343
344
5ef57876
EH		 345typedef struct FeatureWordInfo {
346 const char **feat_names;
04d104b6
EH		 347 uint32_t cpuid_eax; /* Input EAX for CPUID */
348 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
349 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
350 int cpuid_reg; /* output register (R_* constant) */
37ce3522 351 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 352 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 353} FeatureWordInfo;
354
355static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 356 [FEAT_1_EDX] = {
357 .feat_names = feature_name,
358 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 359 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 360 },
361 [FEAT_1_ECX] = {
362 .feat_names = ext_feature_name,
363 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 364 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 365 },
366 [FEAT_8000_0001_EDX] = {
367 .feat_names = ext2_feature_name,
368 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 369 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 370 },
371 [FEAT_8000_0001_ECX] = {
372 .feat_names = ext3_feature_name,
373 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 374 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 375 },
89e49c8b
EH		 376 [FEAT_C000_0001_EDX] = {
377 .feat_names = ext4_feature_name,
378 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 379 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 380 },
bffd67b0
EH		 381 [FEAT_KVM] = {
382 .feat_names = kvm_feature_name,
383 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 384 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 385 },
386 [FEAT_SVM] = {
387 .feat_names = svm_feature_name,
388 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 389 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 390 },
391 [FEAT_7_0_EBX] = {
392 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 393 .cpuid_eax = 7,
394 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
395 .cpuid_reg = R_EBX,
37ce3522 396 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 397 },
303752a9
MT		 398 [FEAT_8000_0007_EDX] = {
399 .feat_names = cpuid_apm_edx_feature_name,
400 .cpuid_eax = 0x80000007,
401 .cpuid_reg = R_EDX,
402 .tcg_features = TCG_APM_FEATURES,
403 .unmigratable_flags = CPUID_APM_INVTSC,
404 },
0bb0b2d2
PB		 405 [FEAT_XSAVE] = {
406 .feat_names = cpuid_xsave_feature_name,
407 .cpuid_eax = 0xd,
408 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
409 .cpuid_reg = R_EAX,
410 .tcg_features = 0,
0bb0b2d2 411 },
5ef57876
EH		 412};
413
8e8aba50
EH		 414typedef struct X86RegisterInfo32 {
415 /* Name of register */
416 const char *name;
417 /* QAPI enum value register */
418 X86CPURegister32 qapi_enum;
419} X86RegisterInfo32;
420
421#define REGISTER(reg) \
5d371f41 422 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 423static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 424 REGISTER(EAX),
425 REGISTER(ECX),
426 REGISTER(EDX),
427 REGISTER(EBX),
428 REGISTER(ESP),
429 REGISTER(EBP),
430 REGISTER(ESI),
431 REGISTER(EDI),
432};
433#undef REGISTER
434
2560f19f
PB		 435typedef struct ExtSaveArea {
436 uint32_t feature, bits;
437 uint32_t offset, size;
438} ExtSaveArea;
439
440static const ExtSaveArea ext_save_areas[] = {
441 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 442 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 443 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
444 .offset = 0x3c0, .size = 0x40 },
445 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 446 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 447 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
448 .offset = 0x440, .size = 0x40 },
449 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
450 .offset = 0x480, .size = 0x200 },
451 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
452 .offset = 0x680, .size = 0x400 },
2560f19f 453};
8e8aba50 454
8b4beddc
EH		 455const char *get_register_name_32(unsigned int reg)
456{
31ccdde2 457 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 458 return NULL;
459 }
8e8aba50 460 return x86_reg_info_32[reg].name;
8b4beddc
EH		 461}
462
5fcca9ff
EH		 463/* KVM-specific features that are automatically added to all CPU models
464 * when KVM is enabled.
465 */
466static uint32_t kvm_default_features[FEATURE_WORDS] = {
467 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 468 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 469 (1 << KVM_FEATURE_CLOCKSOURCE2) |
470 (1 << KVM_FEATURE_ASYNC_PF) |
471 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 472 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 473 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 474 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 475};
dc59944b 476
136a7e9a
EH		 477/* Features that are not added by default to any CPU model when KVM is enabled.
478 */
479static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 480 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a 481 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
75d373ef 482 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
136a7e9a
EH		 483};
484
1cadaa94 485void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 486{
8fb4f821 487 kvm_default_features[w] &= ~features;
dc59944b
MT		 488}
489
75d373ef
EH		 490void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
491{
492 kvm_default_unset_features[w] &= ~features;
493}
494
84f1b92f
EH		 495/*
496 * Returns the set of feature flags that are supported and migratable by
497 * QEMU, for a given FeatureWord.
498 */
499static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
500{
501 FeatureWordInfo *wi = &feature_word_info[w];
502 uint32_t r = 0;
503 int i;
504
505 for (i = 0; i < 32; i++) {
506 uint32_t f = 1U << i;
507 /* If the feature name is unknown, it is not supported by QEMU yet */
508 if (!wi->feat_names[i]) {
509 continue;
510 }
511 /* Skip features known to QEMU, but explicitly marked as unmigratable */
512 if (wi->unmigratable_flags & f) {
513 continue;
514 }
515 r |= f;
516 }
517 return r;
518}
519
bb44e0d1
JK		 520void host_cpuid(uint32_t function, uint32_t count,
521 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 522{
a1fd24af
AL		 523 uint32_t vec[4];
524
525#ifdef __x86_64__
526 asm volatile("cpuid"
527 : "=a"(vec[0]), "=b"(vec[1]),
528 "=c"(vec[2]), "=d"(vec[3])
529 : "0"(function), "c"(count) : "cc");
c1f41226 530#elif defined(__i386__)
a1fd24af
AL		 531 asm volatile("pusha \n\t"
532 "cpuid \n\t"
533 "mov %%eax, 0(%2) \n\t"
534 "mov %%ebx, 4(%2) \n\t"
535 "mov %%ecx, 8(%2) \n\t"
536 "mov %%edx, 12(%2) \n\t"
537 "popa"
538 : : "a"(function), "c"(count), "S"(vec)
539 : "memory", "cc");
c1f41226
EH		 540#else
541 abort();
a1fd24af
AL		 542#endif
543
bdde476a 544 if (eax)
a1fd24af 545 *eax = vec[0];
bdde476a 546 if (ebx)
a1fd24af 547 *ebx = vec[1];
bdde476a 548 if (ecx)
a1fd24af 549 *ecx = vec[2];
bdde476a 550 if (edx)
a1fd24af 551 *edx = vec[3];
bdde476a 552}
c6dc6f63
AP		 553
554#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
555
556/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
557 * a substring. ex if !NULL points to the first char after a substring,
558 * otherwise the string is assumed to sized by a terminating nul.
559 * Return lexical ordering of *s1:*s2.
560 */
8f9d989c
CF		 561static int sstrcmp(const char *s1, const char *e1,
562 const char *s2, const char *e2)
c6dc6f63
AP		 563{
564 for (;;) {
565 if (!*s1 || !*s2 || *s1 != *s2)
566 return (*s1 - *s2);
567 ++s1, ++s2;
568 if (s1 == e1 && s2 == e2)
569 return (0);
570 else if (s1 == e1)
571 return (*s2);
572 else if (s2 == e2)
573 return (*s1);
574 }
575}
576
577/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
578 * '|' delimited (possibly empty) strings in which case search for a match
579 * within the alternatives proceeds left to right. Return 0 for success,
580 * non-zero otherwise.
581 */
582static int altcmp(const char *s, const char *e, const char *altstr)
583{
584 const char *p, *q;
585
586 for (q = p = altstr; ; ) {
587 while (*p && *p != '|')
588 ++p;
589 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
590 return (0);
591 if (!*p)
592 return (1);
593 else
594 q = ++p;
595 }
596}
597
598/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 599 * *pval and return true, otherwise return false
c6dc6f63 600 */
e41e0fc6
JK		 601static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
602 const char **featureset)
c6dc6f63
AP		 603{
604 uint32_t mask;
605 const char **ppc;
e41e0fc6 606 bool found = false;
c6dc6f63 607
e41e0fc6 608 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 609 if (*ppc && !altcmp(s, e, *ppc)) {
610 *pval |= mask;
e41e0fc6 611 found = true;
c6dc6f63 612 }
e41e0fc6
JK		 613 }
614 return found;
c6dc6f63
AP		 615}
616
5ef57876 617static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 618 FeatureWordArray words,
619 Error **errp)
c6dc6f63 620{
5ef57876
EH		 621 FeatureWord w;
622 for (w = 0; w < FEATURE_WORDS; w++) {
623 FeatureWordInfo *wi = &feature_word_info[w];
624 if (wi->feat_names &&
625 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
626 break;
627 }
628 }
629 if (w == FEATURE_WORDS) {
c00c94ab 630 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 631 }
c6dc6f63
AP		 632}
633
d940ee9b
EH		 634/* CPU class name definitions: */
635
636#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
637#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
638
639/* Return type name for a given CPU model name
640 * Caller is responsible for freeing the returned string.
641 */
642static char *x86_cpu_type_name(const char *model_name)
643{
644 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
645}
646
500050d1
AF		 647static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
648{
d940ee9b
EH		 649 ObjectClass *oc;
650 char *typename;
651
500050d1
AF		 652 if (cpu_model == NULL) {
653 return NULL;
654 }
655
d940ee9b
EH		 656 typename = x86_cpu_type_name(cpu_model);
657 oc = object_class_by_name(typename);
658 g_free(typename);
659 return oc;
500050d1
AF		 660}
661
d940ee9b 662struct X86CPUDefinition {
c6dc6f63
AP		 663 const char *name;
664 uint32_t level;
90e4b0c3
EH		 665 uint32_t xlevel;
666 uint32_t xlevel2;
99b88a17
IM		 667 /* vendor is zero-terminated, 12 character ASCII string */
668 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 669 int family;
670 int model;
671 int stepping;
0514ef2f 672 FeatureWordArray features;
c6dc6f63 673 char model_id[48];
787aaf57 674 bool cache_info_passthrough;
d940ee9b 675};
c6dc6f63 676
9576de75 677static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 678 {
679 .name = "qemu64",
680 .level = 4,
99b88a17 681 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 682 .family = 6,
f8e6a11a 683 .model = 6,
c6dc6f63 684 .stepping = 3,
0514ef2f 685 .features[FEAT_1_EDX] =
27861ecc 686 PPRO_FEATURES |
c6dc6f63 687 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 688 CPUID_PSE36,
0514ef2f 689 .features[FEAT_1_ECX] =
27861ecc 690 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 691 .features[FEAT_8000_0001_EDX] =
27861ecc 692 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 693 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 694 .features[FEAT_8000_0001_ECX] =
27861ecc 695 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 696 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
697 .xlevel = 0x8000000A,
c6dc6f63
AP		 698 },
699 {
700 .name = "phenom",
701 .level = 5,
99b88a17 702 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 703 .family = 16,
704 .model = 2,
705 .stepping = 3,
b9fc20bc 706 /* Missing: CPUID_HT */
0514ef2f 707 .features[FEAT_1_EDX] =
27861ecc 708 PPRO_FEATURES |
c6dc6f63 709 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 710 CPUID_PSE36 | CPUID_VME,
0514ef2f 711 .features[FEAT_1_ECX] =
27861ecc 712 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 713 CPUID_EXT_POPCNT,
0514ef2f 714 .features[FEAT_8000_0001_EDX] =
27861ecc 715 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 716 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
717 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 718 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 719 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
720 CPUID_EXT3_CR8LEG,
721 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
722 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 723 .features[FEAT_8000_0001_ECX] =
27861ecc 724 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 725 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 726 /* Missing: CPUID_SVM_LBRV */
0514ef2f 727 .features[FEAT_SVM] =
b9fc20bc 728 CPUID_SVM_NPT,
c6dc6f63
AP		 729 .xlevel = 0x8000001A,
730 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
731 },
732 {
733 .name = "core2duo",
734 .level = 10,
99b88a17 735 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 736 .family = 6,
737 .model = 15,
738 .stepping = 11,
b9fc20bc 739 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 740 .features[FEAT_1_EDX] =
27861ecc 741 PPRO_FEATURES |
c6dc6f63 742 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 743 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
744 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 745 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 746 .features[FEAT_1_ECX] =
27861ecc 747 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 748 CPUID_EXT_CX16,
0514ef2f 749 .features[FEAT_8000_0001_EDX] =
27861ecc 750 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 751 .features[FEAT_8000_0001_ECX] =
27861ecc 752 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 753 .xlevel = 0x80000008,
754 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
755 },
756 {
757 .name = "kvm64",
758 .level = 5,
99b88a17 759 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 760 .family = 15,
761 .model = 6,
762 .stepping = 1,
b3a4f0b1 763 /* Missing: CPUID_HT */
0514ef2f 764 .features[FEAT_1_EDX] =
b3a4f0b1 765 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 766 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
767 CPUID_PSE36,
768 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 769 .features[FEAT_1_ECX] =
27861ecc 770 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 771 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 772 .features[FEAT_8000_0001_EDX] =
27861ecc 773 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 774 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
775 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
776 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
777 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
778 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 779 .features[FEAT_8000_0001_ECX] =
27861ecc 780 0,
c6dc6f63
AP		 781 .xlevel = 0x80000008,
782 .model_id = "Common KVM processor"
783 },
c6dc6f63
AP		 784 {
785 .name = "qemu32",
786 .level = 4,
99b88a17 787 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 788 .family = 6,
f8e6a11a 789 .model = 6,
c6dc6f63 790 .stepping = 3,
0514ef2f 791 .features[FEAT_1_EDX] =
27861ecc 792 PPRO_FEATURES,
0514ef2f 793 .features[FEAT_1_ECX] =
27861ecc 794 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 795 .xlevel = 0x80000004,
c6dc6f63 796 },
eafaf1e5
AP		 797 {
798 .name = "kvm32",
799 .level = 5,
99b88a17 800 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 801 .family = 15,
802 .model = 6,
803 .stepping = 1,
0514ef2f 804 .features[FEAT_1_EDX] =
b3a4f0b1 805 PPRO_FEATURES | CPUID_VME |
eafaf1e5 806 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 807 .features[FEAT_1_ECX] =
27861ecc 808 CPUID_EXT_SSE3,
0514ef2f 809 .features[FEAT_8000_0001_EDX] =
27861ecc 810 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 811 .features[FEAT_8000_0001_ECX] =
27861ecc 812 0,
eafaf1e5
AP		 813 .xlevel = 0x80000008,
814 .model_id = "Common 32-bit KVM processor"
815 },
c6dc6f63
AP		 816 {
817 .name = "coreduo",
818 .level = 10,
99b88a17 819 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 820 .family = 6,
821 .model = 14,
822 .stepping = 8,
b9fc20bc 823 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 824 .features[FEAT_1_EDX] =
27861ecc 825 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 826 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
827 CPUID_SS,
828 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 829 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 830 .features[FEAT_1_ECX] =
e93abc14 831 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 832 .features[FEAT_8000_0001_EDX] =
27861ecc 833 CPUID_EXT2_NX,
c6dc6f63
AP		 834 .xlevel = 0x80000008,
835 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
836 },
837 {
838 .name = "486",
58012d66 839 .level = 1,
99b88a17 840 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 841 .family = 4,
b2a856d9 842 .model = 8,
c6dc6f63 843 .stepping = 0,
0514ef2f 844 .features[FEAT_1_EDX] =
27861ecc 845 I486_FEATURES,
c6dc6f63
AP		 846 .xlevel = 0,
847 },
848 {
849 .name = "pentium",
850 .level = 1,
99b88a17 851 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 852 .family = 5,
853 .model = 4,
854 .stepping = 3,
0514ef2f 855 .features[FEAT_1_EDX] =
27861ecc 856 PENTIUM_FEATURES,
c6dc6f63
AP		 857 .xlevel = 0,
858 },
859 {
860 .name = "pentium2",
861 .level = 2,
99b88a17 862 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 863 .family = 6,
864 .model = 5,
865 .stepping = 2,
0514ef2f 866 .features[FEAT_1_EDX] =
27861ecc 867 PENTIUM2_FEATURES,
c6dc6f63
AP		 868 .xlevel = 0,
869 },
870 {
871 .name = "pentium3",
872 .level = 2,
99b88a17 873 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 874 .family = 6,
875 .model = 7,
876 .stepping = 3,
0514ef2f 877 .features[FEAT_1_EDX] =
27861ecc 878 PENTIUM3_FEATURES,
c6dc6f63
AP		 879 .xlevel = 0,
880 },
881 {
882 .name = "athlon",
883 .level = 2,
99b88a17 884 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 885 .family = 6,
886 .model = 2,
887 .stepping = 3,
0514ef2f 888 .features[FEAT_1_EDX] =
27861ecc 889 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 890 CPUID_MCA,
0514ef2f 891 .features[FEAT_8000_0001_EDX] =
27861ecc 892 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 893 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 894 .xlevel = 0x80000008,
c6dc6f63
AP		 895 },
896 {
897 .name = "n270",
898 /* original is on level 10 */
899 .level = 5,
99b88a17 900 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 901 .family = 6,
902 .model = 28,
903 .stepping = 2,
b9fc20bc 904 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 905 .features[FEAT_1_EDX] =
27861ecc 906 PPRO_FEATURES |
b9fc20bc
EH		 907 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
908 CPUID_ACPI | CPUID_SS,
c6dc6f63 909 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 910 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
911 * CPUID_EXT_XTPR */
0514ef2f 912 .features[FEAT_1_ECX] =
27861ecc 913 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 914 CPUID_EXT_MOVBE,
0514ef2f 915 .features[FEAT_8000_0001_EDX] =
27861ecc 916 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 917 CPUID_EXT2_NX,
0514ef2f 918 .features[FEAT_8000_0001_ECX] =
27861ecc 919 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 920 .xlevel = 0x8000000A,
921 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
922 },
3eca4642
EH		 923 {
924 .name = "Conroe",
6b11322e 925 .level = 4,
99b88a17 926 .vendor = CPUID_VENDOR_INTEL,
3eca4642 927 .family = 6,
ffce9ebb 928 .model = 15,
3eca4642 929 .stepping = 3,
0514ef2f 930 .features[FEAT_1_EDX] =
b3a4f0b1 931 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 932 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
933 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
934 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
935 CPUID_DE | CPUID_FP87,
0514ef2f 936 .features[FEAT_1_ECX] =
27861ecc 937 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 938 .features[FEAT_8000_0001_EDX] =
27861ecc 939 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 940 .features[FEAT_8000_0001_ECX] =
27861ecc 941 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 942 .xlevel = 0x8000000A,
943 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
944 },
945 {
946 .name = "Penryn",
6b11322e 947 .level = 4,
99b88a17 948 .vendor = CPUID_VENDOR_INTEL,
3eca4642 949 .family = 6,
ffce9ebb 950 .model = 23,
3eca4642 951 .stepping = 3,
0514ef2f 952 .features[FEAT_1_EDX] =
b3a4f0b1 953 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 954 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
955 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
956 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
957 CPUID_DE | CPUID_FP87,
0514ef2f 958 .features[FEAT_1_ECX] =
27861ecc 959 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 960 CPUID_EXT_SSE3,
0514ef2f 961 .features[FEAT_8000_0001_EDX] =
27861ecc 962 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 963 .features[FEAT_8000_0001_ECX] =
27861ecc 964 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 965 .xlevel = 0x8000000A,
966 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
967 },
968 {
969 .name = "Nehalem",
6b11322e 970 .level = 4,
99b88a17 971 .vendor = CPUID_VENDOR_INTEL,
3eca4642 972 .family = 6,
ffce9ebb 973 .model = 26,
3eca4642 974 .stepping = 3,
0514ef2f 975 .features[FEAT_1_EDX] =
b3a4f0b1 976 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 977 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
978 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
979 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
980 CPUID_DE | CPUID_FP87,
0514ef2f 981 .features[FEAT_1_ECX] =
27861ecc 982 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 983 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 984 .features[FEAT_8000_0001_EDX] =
27861ecc 985 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 986 .features[FEAT_8000_0001_ECX] =
27861ecc 987 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 988 .xlevel = 0x8000000A,
989 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
990 },
991 {
992 .name = "Westmere",
993 .level = 11,
99b88a17 994 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 995 .family = 6,
996 .model = 44,
997 .stepping = 1,
0514ef2f 998 .features[FEAT_1_EDX] =
b3a4f0b1 999 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1000 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1001 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1002 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1003 CPUID_DE | CPUID_FP87,
0514ef2f 1004 .features[FEAT_1_ECX] =
27861ecc 1005 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1006 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1007 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1008 .features[FEAT_8000_0001_EDX] =
27861ecc 1009 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1010 .features[FEAT_8000_0001_ECX] =
27861ecc 1011 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1012 .xlevel = 0x8000000A,
1013 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1014 },
1015 {
1016 .name = "SandyBridge",
1017 .level = 0xd,
99b88a17 1018 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1019 .family = 6,
1020 .model = 42,
1021 .stepping = 1,
0514ef2f 1022 .features[FEAT_1_EDX] =
b3a4f0b1 1023 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1024 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1025 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1026 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1027 CPUID_DE | CPUID_FP87,
0514ef2f 1028 .features[FEAT_1_ECX] =
27861ecc 1029 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1030 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1031 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1032 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1033 CPUID_EXT_SSE3,
0514ef2f 1034 .features[FEAT_8000_0001_EDX] =
27861ecc 1035 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1036 CPUID_EXT2_SYSCALL,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1039 .features[FEAT_XSAVE] =
1040 CPUID_XSAVE_XSAVEOPT,
3eca4642
EH		 1041 .xlevel = 0x8000000A,
1042 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1043 },
37507094
EH		 1044 {
1045 .name = "Haswell",
1046 .level = 0xd,
99b88a17 1047 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1048 .family = 6,
1049 .model = 60,
1050 .stepping = 1,
0514ef2f 1051 .features[FEAT_1_EDX] =
b3a4f0b1 1052 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1053 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1054 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1055 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1056 CPUID_DE | CPUID_FP87,
0514ef2f 1057 .features[FEAT_1_ECX] =
27861ecc 1058 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1059 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1060 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1061 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1062 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1063 CPUID_EXT_PCID,
0514ef2f 1064 .features[FEAT_8000_0001_EDX] =
27861ecc 1065 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1066 CPUID_EXT2_SYSCALL,
0514ef2f 1067 .features[FEAT_8000_0001_ECX] =
27861ecc 1068 CPUID_EXT3_LAHF_LM,
0514ef2f 1069 .features[FEAT_7_0_EBX] =
27861ecc 1070 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
37507094
EH		 1071 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1072 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1073 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1074 .features[FEAT_XSAVE] =
1075 CPUID_XSAVE_XSAVEOPT,
37507094
EH		 1076 .xlevel = 0x8000000A,
1077 .model_id = "Intel Core Processor (Haswell)",
1078 },
ece01354
EH		 1079 {
1080 .name = "Broadwell",
1081 .level = 0xd,
1082 .vendor = CPUID_VENDOR_INTEL,
1083 .family = 6,
1084 .model = 61,
1085 .stepping = 2,
1086 .features[FEAT_1_EDX] =
b3a4f0b1 1087 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1088 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1089 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1090 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1091 CPUID_DE | CPUID_FP87,
1092 .features[FEAT_1_ECX] =
1093 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1094 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1095 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1096 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1097 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1098 CPUID_EXT_PCID,
1099 .features[FEAT_8000_0001_EDX] =
1100 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1101 CPUID_EXT2_SYSCALL,
1102 .features[FEAT_8000_0001_ECX] =
1103 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1104 .features[FEAT_7_0_EBX] =
1105 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1106 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1107 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1108 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1109 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1110 .features[FEAT_XSAVE] =
1111 CPUID_XSAVE_XSAVEOPT,
ece01354
EH		 1112 .xlevel = 0x8000000A,
1113 .model_id = "Intel Core Processor (Broadwell)",
1114 },
3eca4642
EH		 1115 {
1116 .name = "Opteron_G1",
1117 .level = 5,
99b88a17 1118 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1119 .family = 15,
1120 .model = 6,
1121 .stepping = 1,
0514ef2f 1122 .features[FEAT_1_EDX] =
b3a4f0b1 1123 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1124 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1125 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1126 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1127 CPUID_DE | CPUID_FP87,
0514ef2f 1128 .features[FEAT_1_ECX] =
27861ecc 1129 CPUID_EXT_SSE3,
0514ef2f 1130 .features[FEAT_8000_0001_EDX] =
27861ecc 1131 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1132 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1133 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1134 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1135 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1136 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1137 .xlevel = 0x80000008,
1138 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1139 },
1140 {
1141 .name = "Opteron_G2",
1142 .level = 5,
99b88a17 1143 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1144 .family = 15,
1145 .model = 6,
1146 .stepping = 1,
0514ef2f 1147 .features[FEAT_1_EDX] =
b3a4f0b1 1148 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1149 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1150 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1151 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1152 CPUID_DE | CPUID_FP87,
0514ef2f 1153 .features[FEAT_1_ECX] =
27861ecc 1154 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1155 .features[FEAT_8000_0001_EDX] =
27861ecc 1156 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1157 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1158 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1159 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1160 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1161 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1162 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1163 .features[FEAT_8000_0001_ECX] =
27861ecc 1164 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1165 .xlevel = 0x80000008,
1166 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1167 },
1168 {
1169 .name = "Opteron_G3",
1170 .level = 5,
99b88a17 1171 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1172 .family = 15,
1173 .model = 6,
1174 .stepping = 1,
0514ef2f 1175 .features[FEAT_1_EDX] =
b3a4f0b1 1176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1180 CPUID_DE | CPUID_FP87,
0514ef2f 1181 .features[FEAT_1_ECX] =
27861ecc 1182 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1183 CPUID_EXT_SSE3,
0514ef2f 1184 .features[FEAT_8000_0001_EDX] =
27861ecc 1185 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1186 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1187 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1188 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1189 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1190 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1191 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1192 .features[FEAT_8000_0001_ECX] =
27861ecc 1193 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1194 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1195 .xlevel = 0x80000008,
1196 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1197 },
1198 {
1199 .name = "Opteron_G4",
1200 .level = 0xd,
99b88a17 1201 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1202 .family = 21,
1203 .model = 1,
1204 .stepping = 2,
0514ef2f 1205 .features[FEAT_1_EDX] =
b3a4f0b1 1206 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1207 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1208 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1209 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1210 CPUID_DE | CPUID_FP87,
0514ef2f 1211 .features[FEAT_1_ECX] =
27861ecc 1212 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1213 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1214 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1215 CPUID_EXT_SSE3,
0514ef2f 1216 .features[FEAT_8000_0001_EDX] =
27861ecc 1217 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1218 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1219 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1220 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1221 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1222 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1223 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1224 .features[FEAT_8000_0001_ECX] =
27861ecc 1225 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1226 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1227 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1228 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1229 /* no xsaveopt! */
3eca4642
EH		 1230 .xlevel = 0x8000001A,
1231 .model_id = "AMD Opteron 62xx class CPU",
1232 },
021941b9
AP		 1233 {
1234 .name = "Opteron_G5",
1235 .level = 0xd,
99b88a17 1236 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1237 .family = 21,
1238 .model = 2,
1239 .stepping = 0,
0514ef2f 1240 .features[FEAT_1_EDX] =
b3a4f0b1 1241 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1242 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1243 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1244 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1245 CPUID_DE | CPUID_FP87,
0514ef2f 1246 .features[FEAT_1_ECX] =
27861ecc 1247 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1248 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1249 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1250 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1251 .features[FEAT_8000_0001_EDX] =
27861ecc 1252 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1253 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1254 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1255 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1256 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1257 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1258 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1259 .features[FEAT_8000_0001_ECX] =
27861ecc 1260 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1261 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1262 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1263 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1264 /* no xsaveopt! */
021941b9
AP		 1265 .xlevel = 0x8000001A,
1266 .model_id = "AMD Opteron 63xx class CPU",
1267 },
c6dc6f63
AP		 1268};
1269
0668af54
EH		 1270/**
1271 * x86_cpu_compat_set_features:
1272 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1273 * @w: Identifies the feature word to be changed.
1274 * @feat_add: Feature bits to be added to feature word
1275 * @feat_remove: Feature bits to be removed from feature word
1276 *
1277 * Change CPU model feature bits for compatibility.
1278 *
1279 * This function may be used by machine-type compatibility functions
1280 * to enable or disable feature bits on specific CPU models.
1281 */
1282void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1283 uint32_t feat_add, uint32_t feat_remove)
1284{
9576de75 1285 X86CPUDefinition *def;
0668af54
EH		 1286 int i;
1287 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1288 def = &builtin_x86_defs[i];
1289 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1290 def->features[w] |= feat_add;
1291 def->features[w] &= ~feat_remove;
1292 }
1293 }
1294}
1295
4d1b279b
EH		 1296static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1297 bool migratable_only);
1298
d940ee9b
EH		 1299#ifdef CONFIG_KVM
1300
c6dc6f63
AP		 1301static int cpu_x86_fill_model_id(char *str)
1302{
1303 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1304 int i;
1305
1306 for (i = 0; i < 3; i++) {
1307 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1308 memcpy(str + i * 16 + 0, &eax, 4);
1309 memcpy(str + i * 16 + 4, &ebx, 4);
1310 memcpy(str + i * 16 + 8, &ecx, 4);
1311 memcpy(str + i * 16 + 12, &edx, 4);
1312 }
1313 return 0;
1314}
1315
d940ee9b
EH		 1316static X86CPUDefinition host_cpudef;
1317
84f1b92f 1318static Property host_x86_cpu_properties[] = {
120eee7d 1319 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1320 DEFINE_PROP_END_OF_LIST()
1321};
1322
d940ee9b 1323/* class_init for the "host" CPU model
6e746f30 1324 *
d940ee9b 1325 * This function may be called before KVM is initialized.
6e746f30 1326 */
d940ee9b 1327static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1328{
84f1b92f 1329 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1330 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1331 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1332
d940ee9b 1333 xcc->kvm_required = true;
6e746f30 1334
c6dc6f63 1335 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1336 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1337
1338 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1339 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1340 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1341 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1342
d940ee9b 1343 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1344
d940ee9b
EH		 1345 xcc->cpu_def = &host_cpudef;
1346 host_cpudef.cache_info_passthrough = true;
1347
1348 /* level, xlevel, xlevel2, and the feature words are initialized on
1349 * instance_init, because they require KVM to be initialized.
1350 */
84f1b92f
EH		 1351
1352 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1353}
1354
1355static void host_x86_cpu_initfn(Object *obj)
1356{
1357 X86CPU *cpu = X86_CPU(obj);
1358 CPUX86State *env = &cpu->env;
1359 KVMState *s = kvm_state;
d940ee9b
EH		 1360
1361 assert(kvm_enabled());
1362
4d1b279b
EH		 1363 /* We can't fill the features array here because we don't know yet if
1364 * "migratable" is true or false.
1365 */
1366 cpu->host_features = true;
1367
d940ee9b
EH		 1368 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1369 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1370 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1371
d940ee9b 1372 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1373}
1374
d940ee9b
EH		 1375static const TypeInfo host_x86_cpu_type_info = {
1376 .name = X86_CPU_TYPE_NAME("host"),
1377 .parent = TYPE_X86_CPU,
1378 .instance_init = host_x86_cpu_initfn,
1379 .class_init = host_x86_cpu_class_init,
1380};
1381
1382#endif
1383
8459e396 1384static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1385{
8459e396 1386 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1387 int i;
1388
857aee33 1389 for (i = 0; i < 32; ++i) {
c6dc6f63 1390 if (1 << i & mask) {
bffd67b0 1391 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1392 assert(reg);
fefb41bf 1393 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1394 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1395 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1396 f->cpuid_eax, reg,
1397 f->feat_names[i] ? "." : "",
1398 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1399 }
857aee33 1400 }
c6dc6f63
AP		 1401}
1402
95b8519d
AF		 1403static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1404 const char *name, Error **errp)
1405{
1406 X86CPU *cpu = X86_CPU(obj);
1407 CPUX86State *env = &cpu->env;
1408 int64_t value;
1409
1410 value = (env->cpuid_version >> 8) & 0xf;
1411 if (value == 0xf) {
1412 value += (env->cpuid_version >> 20) & 0xff;
1413 }
1414 visit_type_int(v, &value, name, errp);
1415}
1416
71ad61d3
AF		 1417static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1418 const char *name, Error **errp)
ed5e1ec3 1419{
71ad61d3
AF		 1420 X86CPU *cpu = X86_CPU(obj);
1421 CPUX86State *env = &cpu->env;
1422 const int64_t min = 0;
1423 const int64_t max = 0xff + 0xf;
65cd9064 1424 Error *local_err = NULL;
71ad61d3
AF		 1425 int64_t value;
1426
65cd9064
MA		 1427 visit_type_int(v, &value, name, &local_err);
1428 if (local_err) {
1429 error_propagate(errp, local_err);
71ad61d3
AF		 1430 return;
1431 }
1432 if (value < min || value > max) {
1433 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1434 name ? name : "null", value, min, max);
1435 return;
1436 }
1437
ed5e1ec3 1438 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1439 if (value > 0x0f) {
1440 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1441 } else {
71ad61d3 1442 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1443 }
1444}
1445
67e30c83
AF		 1446static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1447 const char *name, Error **errp)
1448{
1449 X86CPU *cpu = X86_CPU(obj);
1450 CPUX86State *env = &cpu->env;
1451 int64_t value;
1452
1453 value = (env->cpuid_version >> 4) & 0xf;
1454 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1455 visit_type_int(v, &value, name, errp);
1456}
1457
c5291a4f
AF		 1458static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1459 const char *name, Error **errp)
b0704cbd 1460{
c5291a4f
AF		 1461 X86CPU *cpu = X86_CPU(obj);
1462 CPUX86State *env = &cpu->env;
1463 const int64_t min = 0;
1464 const int64_t max = 0xff;
65cd9064 1465 Error *local_err = NULL;
c5291a4f
AF		 1466 int64_t value;
1467
65cd9064
MA		 1468 visit_type_int(v, &value, name, &local_err);
1469 if (local_err) {
1470 error_propagate(errp, local_err);
c5291a4f
AF		 1471 return;
1472 }
1473 if (value < min || value > max) {
1474 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1475 name ? name : "null", value, min, max);
1476 return;
1477 }
1478
b0704cbd 1479 env->cpuid_version &= ~0xf00f0;
c5291a4f 1480 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1481}
1482
35112e41
AF		 1483static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1484 void *opaque, const char *name,
1485 Error **errp)
1486{
1487 X86CPU *cpu = X86_CPU(obj);
1488 CPUX86State *env = &cpu->env;
1489 int64_t value;
1490
1491 value = env->cpuid_version & 0xf;
1492 visit_type_int(v, &value, name, errp);
1493}
1494
036e2222
AF		 1495static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1496 void *opaque, const char *name,
1497 Error **errp)
38c3dc46 1498{
036e2222
AF		 1499 X86CPU *cpu = X86_CPU(obj);
1500 CPUX86State *env = &cpu->env;
1501 const int64_t min = 0;
1502 const int64_t max = 0xf;
65cd9064 1503 Error *local_err = NULL;
036e2222
AF		 1504 int64_t value;
1505
65cd9064
MA		 1506 visit_type_int(v, &value, name, &local_err);
1507 if (local_err) {
1508 error_propagate(errp, local_err);
036e2222
AF		 1509 return;
1510 }
1511 if (value < min || value > max) {
1512 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1513 name ? name : "null", value, min, max);
1514 return;
1515 }
1516
38c3dc46 1517 env->cpuid_version &= ~0xf;
036e2222 1518 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1519}
1520
8e1898bf
AF		 1521static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1522 const char *name, Error **errp)
1523{
1524 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1525
fa029887 1526 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1527}
1528
1529static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1530 const char *name, Error **errp)
1531{
1532 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1533
fa029887 1534 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1535}
1536
16b93aa8
AF		 1537static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1538 const char *name, Error **errp)
1539{
1540 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1541
fa029887 1542 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1543}
1544
1545static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1546 const char *name, Error **errp)
1547{
1548 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1549
fa029887 1550 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1551}
1552
d480e1af
AF		 1553static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1554{
1555 X86CPU *cpu = X86_CPU(obj);
1556 CPUX86State *env = &cpu->env;
1557 char *value;
d480e1af 1558
e42a92ae 1559 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1560 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1561 env->cpuid_vendor3);
d480e1af
AF		 1562 return value;
1563}
1564
1565static void x86_cpuid_set_vendor(Object *obj, const char *value,
1566 Error **errp)
1567{
1568 X86CPU *cpu = X86_CPU(obj);
1569 CPUX86State *env = &cpu->env;
1570 int i;
1571
9df694ee 1572 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1573 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1574 "vendor", value);
1575 return;
1576 }
1577
1578 env->cpuid_vendor1 = 0;
1579 env->cpuid_vendor2 = 0;
1580 env->cpuid_vendor3 = 0;
1581 for (i = 0; i < 4; i++) {
1582 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1583 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1584 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1585 }
d480e1af
AF		 1586}
1587
63e886eb
AF		 1588static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1589{
1590 X86CPU *cpu = X86_CPU(obj);
1591 CPUX86State *env = &cpu->env;
1592 char *value;
1593 int i;
1594
1595 value = g_malloc(48 + 1);
1596 for (i = 0; i < 48; i++) {
1597 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1598 }
1599 value[48] = '\0';
1600 return value;
1601}
1602
938d4c25
AF		 1603static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1604 Error **errp)
dcce6675 1605{
938d4c25
AF		 1606 X86CPU *cpu = X86_CPU(obj);
1607 CPUX86State *env = &cpu->env;
dcce6675
AF		 1608 int c, len, i;
1609
1610 if (model_id == NULL) {
1611 model_id = "";
1612 }
1613 len = strlen(model_id);
d0a6acf4 1614 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1615 for (i = 0; i < 48; i++) {
1616 if (i >= len) {
1617 c = '\0';
1618 } else {
1619 c = (uint8_t)model_id[i];
1620 }
1621 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1622 }
1623}
1624
89e48965
AF		 1625static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1626 const char *name, Error **errp)
1627{
1628 X86CPU *cpu = X86_CPU(obj);
1629 int64_t value;
1630
1631 value = cpu->env.tsc_khz * 1000;
1632 visit_type_int(v, &value, name, errp);
1633}
1634
1635static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1636 const char *name, Error **errp)
1637{
1638 X86CPU *cpu = X86_CPU(obj);
1639 const int64_t min = 0;
2e84849a 1640 const int64_t max = INT64_MAX;
65cd9064 1641 Error *local_err = NULL;
89e48965
AF		 1642 int64_t value;
1643
65cd9064
MA		 1644 visit_type_int(v, &value, name, &local_err);
1645 if (local_err) {
1646 error_propagate(errp, local_err);
89e48965
AF		 1647 return;
1648 }
1649 if (value < min || value > max) {
1650 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1651 name ? name : "null", value, min, max);
1652 return;
1653 }
1654
1655 cpu->env.tsc_khz = value / 1000;
1656}
1657
31050930
IM		 1658static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1659 const char *name, Error **errp)
1660{
1661 X86CPU *cpu = X86_CPU(obj);
1662 int64_t value = cpu->env.cpuid_apic_id;
1663
1664 visit_type_int(v, &value, name, errp);
1665}
1666
1667static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1668 const char *name, Error **errp)
1669{
1670 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1671 DeviceState *dev = DEVICE(obj);
31050930
IM		 1672 const int64_t min = 0;
1673 const int64_t max = UINT32_MAX;
1674 Error *error = NULL;
1675 int64_t value;
1676
8d6d4980
IM		 1677 if (dev->realized) {
1678 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1679 "it was realized", name, object_get_typename(obj));
1680 return;
1681 }
1682
31050930
IM		 1683 visit_type_int(v, &value, name, &error);
1684 if (error) {
1685 error_propagate(errp, error);
1686 return;
1687 }
1688 if (value < min || value > max) {
1689 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1690 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1691 object_get_typename(obj), name, value, min, max);
1692 return;
1693 }
1694
1695 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1696 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1697 return;
1698 }
1699 cpu->env.cpuid_apic_id = value;
1700}
1701
7e5292b5 1702/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1703static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1704 const char *name, Error **errp)
1705{
7e5292b5 1706 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1707 FeatureWord w;
1708 Error *err = NULL;
1709 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1710 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1711 X86CPUFeatureWordInfoList *list = NULL;
1712
1713 for (w = 0; w < FEATURE_WORDS; w++) {
1714 FeatureWordInfo *wi = &feature_word_info[w];
1715 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1716 qwi->cpuid_input_eax = wi->cpuid_eax;
1717 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1718 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1719 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1720 qwi->features = array[w];
8e8aba50
EH		 1721
1722 /* List will be in reverse order, but order shouldn't matter */
1723 list_entries[w].next = list;
1724 list_entries[w].value = &word_infos[w];
1725 list = &list_entries[w];
1726 }
1727
1728 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1729 error_propagate(errp, err);
1730}
1731
c8f0f88e
IM		 1732static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1733 const char *name, Error **errp)
1734{
1735 X86CPU *cpu = X86_CPU(obj);
1736 int64_t value = cpu->hyperv_spinlock_attempts;
1737
1738 visit_type_int(v, &value, name, errp);
1739}
1740
1741static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1742 const char *name, Error **errp)
1743{
1744 const int64_t min = 0xFFF;
1745 const int64_t max = UINT_MAX;
1746 X86CPU *cpu = X86_CPU(obj);
1747 Error *err = NULL;
1748 int64_t value;
1749
1750 visit_type_int(v, &value, name, &err);
1751 if (err) {
1752 error_propagate(errp, err);
1753 return;
1754 }
1755
1756 if (value < min || value > max) {
1757 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1758 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1759 object_get_typename(obj), name ? name : "null",
1760 value, min, max);
c8f0f88e
IM		 1761 return;
1762 }
1763 cpu->hyperv_spinlock_attempts = value;
1764}
1765
1766static PropertyInfo qdev_prop_spinlocks = {
1767 .name = "int",
1768 .get = x86_get_hv_spinlocks,
1769 .set = x86_set_hv_spinlocks,
1770};
1771
72ac2e87
IM		 1772/* Convert all '_' in a feature string option name to '-', to make feature
1773 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1774 */
1775static inline void feat2prop(char *s)
1776{
1777 while ((s = strchr(s, '_'))) {
1778 *s = '-';
1779 }
1780}
1781
8f961357
EH		 1782/* Parse "+feature,-feature,feature=foo" CPU feature string
1783 */
94a444b2
AF		 1784static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1785 Error **errp)
8f961357 1786{
94a444b2 1787 X86CPU *cpu = X86_CPU(cs);
8f961357 1788 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1789 FeatureWord w;
8f961357 1790 /* Features to be added */
077c68c3 1791 FeatureWordArray plus_features = { 0 };
8f961357 1792 /* Features to be removed */
5ef57876 1793 FeatureWordArray minus_features = { 0 };
8f961357 1794 uint32_t numvalue;
a91987c2 1795 CPUX86State *env = &cpu->env;
94a444b2 1796 Error *local_err = NULL;
8f961357 1797
8f961357 1798 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1799
1800 while (featurestr) {
1801 char *val;
1802 if (featurestr[0] == '+') {
c00c94ab 1803 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1804 } else if (featurestr[0] == '-') {
c00c94ab 1805 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1806 } else if ((val = strchr(featurestr, '='))) {
1807 *val = 0; val++;
72ac2e87 1808 feat2prop(featurestr);
d024d209 1809 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1810 char *err;
a91987c2
IM		 1811 char num[32];
1812
c6dc6f63
AP		 1813 numvalue = strtoul(val, &err, 0);
1814 if (!*val || *err) {
6b1dd54b
PB		 1815 error_setg(errp, "bad numerical value %s", val);
1816 return;
c6dc6f63
AP		 1817 }
1818 if (numvalue < 0x80000000) {
94a444b2
AF		 1819 error_report("xlevel value shall always be >= 0x80000000"
1820 ", fixup will be removed in future versions");
2f7a21c4 1821 numvalue += 0x80000000;
c6dc6f63 1822 }
a91987c2 1823 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1824 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1825 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1826 int64_t tsc_freq;
1827 char *err;
a91987c2 1828 char num[32];
b862d1fe
JR		 1829
1830 tsc_freq = strtosz_suffix_unit(val, &err,
1831 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1832 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1833 error_setg(errp, "bad numerical value %s", val);
1834 return;
b862d1fe 1835 }
a91987c2 1836 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1837 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1838 &local_err);
72ac2e87 1839 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1840 char *err;
92067bf4 1841 const int min = 0xFFF;
c8f0f88e 1842 char num[32];
28f52cc0
VR		 1843 numvalue = strtoul(val, &err, 0);
1844 if (!*val || *err) {
6b1dd54b
PB		 1845 error_setg(errp, "bad numerical value %s", val);
1846 return;
28f52cc0 1847 }
92067bf4 1848 if (numvalue < min) {
94a444b2 1849 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1850 ", fixup will be removed in future versions",
1851 min);
92067bf4
IM		 1852 numvalue = min;
1853 }
c8f0f88e 1854 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1855 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1856 } else {
94a444b2 1857 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1858 }
c6dc6f63 1859 } else {
258f5abe 1860 feat2prop(featurestr);
94a444b2 1861 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1862 }
94a444b2
AF		 1863 if (local_err) {
1864 error_propagate(errp, local_err);
6b1dd54b 1865 return;
c6dc6f63
AP		 1866 }
1867 featurestr = strtok(NULL, ",");
1868 }
e1c224b4 1869
4d1b279b
EH		 1870 if (cpu->host_features) {
1871 for (w = 0; w < FEATURE_WORDS; w++) {
1872 env->features[w] =
1873 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1874 }
1875 }
1876
e1c224b4
EH		 1877 for (w = 0; w < FEATURE_WORDS; w++) {
1878 env->features[w] |= plus_features[w];
1879 env->features[w] &= ~minus_features[w];
1880 }
c6dc6f63
AP		 1881}
1882
1883/* generate a composite string into buf of all cpuid names in featureset
1884 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1885 * if flags, suppress names undefined in featureset.
1886 */
1887static void listflags(char *buf, int bufsize, uint32_t fbits,
8f9d989c 1888 const char **featureset, uint32_t flags)
c6dc6f63
AP		 1889{
1890 const char **p = &featureset[31];
1891 char *q, *b, bit;
1892 int nc;
1893
1894 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1895 *buf = '\0';
1896 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1897 if (fbits & 1 << bit && (*p || !flags)) {
1898 if (*p)
1899 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1900 else
1901 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1902 if (bufsize <= nc) {
1903 if (b) {
1904 memcpy(b, "...", sizeof("..."));
1905 }
1906 return;
1907 }
1908 q += nc;
1909 bufsize -= nc;
1910 }
1911}
1912
e916cbf8
PM		 1913/* generate CPU information. */
1914void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1915{
9576de75 1916 X86CPUDefinition *def;
c6dc6f63 1917 char buf[256];
7fc9b714 1918 int i;
c6dc6f63 1919
7fc9b714
AF		 1920 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1921 def = &builtin_x86_defs[i];
c04321b3 1922 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1923 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1924 }
21ad7789
JK		 1925#ifdef CONFIG_KVM
1926 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1927 "KVM processor with all supported host features "
1928 "(only available in KVM mode)");
1929#endif
1930
6cdf8854 1931 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1932 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1933 FeatureWordInfo *fw = &feature_word_info[i];
1934
1935 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1936 (*cpu_fprintf)(f, " %s\n", buf);
1937 }
c6dc6f63
AP		 1938}
1939
76b64a7a 1940CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1941{
1942 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1943 X86CPUDefinition *def;
7fc9b714 1944 int i;
e3966126 1945
7fc9b714 1946 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1947 CpuDefinitionInfoList *entry;
1948 CpuDefinitionInfo *info;
1949
7fc9b714 1950 def = &builtin_x86_defs[i];
e3966126
AL		 1951 info = g_malloc0(sizeof(*info));
1952 info->name = g_strdup(def->name);
1953
1954 entry = g_malloc0(sizeof(*entry));
1955 entry->value = info;
1956 entry->next = cpu_list;
1957 cpu_list = entry;
1958 }
1959
1960 return cpu_list;
1961}
1962
84f1b92f
EH		 1963static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1964 bool migratable_only)
27418adf
EH		 1965{
1966 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 1967 uint32_t r;
27418adf 1968
fefb41bf 1969 if (kvm_enabled()) {
84f1b92f
EH		 1970 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1971 wi->cpuid_ecx,
1972 wi->cpuid_reg);
fefb41bf 1973 } else if (tcg_enabled()) {
84f1b92f 1974 r = wi->tcg_features;
fefb41bf
EH		 1975 } else {
1976 return ~0;
1977 }
84f1b92f
EH		 1978 if (migratable_only) {
1979 r &= x86_cpu_get_migratable_flags(w);
1980 }
1981 return r;
27418adf
EH		 1982}
1983
51f63aed
EH		 1984/*
1985 * Filters CPU feature words based on host availability of each feature.
1986 *
51f63aed
EH		 1987 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1988 */
27418adf 1989static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 1990{
1991 CPUX86State *env = &cpu->env;
bd87d2a2 1992 FeatureWord w;
51f63aed
EH		 1993 int rv = 0;
1994
bd87d2a2 1995 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 1996 uint32_t host_feat =
1997 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 1998 uint32_t requested_features = env->features[w];
1999 env->features[w] &= host_feat;
2000 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2001 if (cpu->filtered_features[w]) {
2002 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2003 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2004 }
2005 rv = 1;
2006 }
bd87d2a2 2007 }
51f63aed
EH		 2008
2009 return rv;
bc74b7db 2010}
bc74b7db 2011
d940ee9b 2012/* Load data from X86CPUDefinition
c080e30e 2013 */
d940ee9b 2014static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2015{
61dcd775 2016 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2017 const char *vendor;
2018 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2019 FeatureWord w;
c6dc6f63 2020
2d64255b
AF		 2021 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2022 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2023 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2024 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2025 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 2026 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 2027 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2028 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2029 for (w = 0; w < FEATURE_WORDS; w++) {
2030 env->features[w] = def->features[w];
2031 }
82beb536 2032
9576de75 2033 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2034 if (kvm_enabled()) {
5fcca9ff
EH		 2035 FeatureWord w;
2036 for (w = 0; w < FEATURE_WORDS; w++) {
2037 env->features[w] |= kvm_default_features[w];
136a7e9a 2038 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2039 }
82beb536 2040 }
5fcca9ff 2041
82beb536 2042 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2043
2044 /* sysenter isn't supported in compatibility mode on AMD,
2045 * syscall isn't supported in compatibility mode on Intel.
2046 * Normally we advertise the actual CPU vendor, but you can
2047 * override this using the 'vendor' property if you want to use
2048 * KVM's sysenter/syscall emulation in compatibility mode and
2049 * when doing cross vendor migration
2050 */
74f54bc4 2051 vendor = def->vendor;
7c08db30
EH		 2052 if (kvm_enabled()) {
2053 uint32_t ebx = 0, ecx = 0, edx = 0;
2054 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2055 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2056 vendor = host_vendor;
2057 }
2058
2059 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2060
c6dc6f63
AP		 2061}
2062
62fc403f
IM		 2063X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
2064 Error **errp)
5c3c6a68 2065{
2d64255b 2066 X86CPU *cpu = NULL;
d940ee9b 2067 X86CPUClass *xcc;
500050d1 2068 ObjectClass *oc;
2d64255b
AF		 2069 gchar **model_pieces;
2070 char *name, *features;
5c3c6a68
AF		 2071 Error *error = NULL;
2072
2d64255b
AF		 2073 model_pieces = g_strsplit(cpu_model, ",", 2);
2074 if (!model_pieces[0]) {
2075 error_setg(&error, "Invalid/empty CPU model name");
2076 goto out;
2077 }
2078 name = model_pieces[0];
2079 features = model_pieces[1];
2080
500050d1
AF		 2081 oc = x86_cpu_class_by_name(name);
2082 if (oc == NULL) {
2083 error_setg(&error, "Unable to find CPU definition: %s", name);
2084 goto out;
2085 }
d940ee9b
EH		 2086 xcc = X86_CPU_CLASS(oc);
2087
2088 if (xcc->kvm_required && !kvm_enabled()) {
2089 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2090 goto out;
2091 }
2092
d940ee9b
EH		 2093 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2094
62fc403f
IM		 2095#ifndef CONFIG_USER_ONLY
2096 if (icc_bridge == NULL) {
2097 error_setg(&error, "Invalid icc-bridge value");
2098 goto out;
2099 }
2100 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2101 object_unref(OBJECT(cpu));
2102#endif
5c3c6a68 2103
94a444b2 2104 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2105 if (error) {
2106 goto out;
5c3c6a68
AF		 2107 }
2108
7f833247 2109out:
cd7b87ff
AF		 2110 if (error != NULL) {
2111 error_propagate(errp, error);
500050d1
AF		 2112 if (cpu) {
2113 object_unref(OBJECT(cpu));
2114 cpu = NULL;
2115 }
cd7b87ff 2116 }
7f833247
IM		 2117 g_strfreev(model_pieces);
2118 return cpu;
2119}
2120
2121X86CPU *cpu_x86_init(const char *cpu_model)
2122{
2123 Error *error = NULL;
2124 X86CPU *cpu;
2125
62fc403f 2126 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 2127 if (error) {
2d64255b
AF		 2128 goto out;
2129 }
2130
7f833247
IM		 2131 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2132
2d64255b 2133out:
2d64255b 2134 if (error) {
4a44d85e 2135 error_report("%s", error_get_pretty(error));
5c3c6a68 2136 error_free(error);
2d64255b
AF		 2137 if (cpu != NULL) {
2138 object_unref(OBJECT(cpu));
2139 cpu = NULL;
2140 }
5c3c6a68
AF		 2141 }
2142 return cpu;
2143}
2144
d940ee9b
EH		 2145static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2146{
2147 X86CPUDefinition *cpudef = data;
2148 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2149
2150 xcc->cpu_def = cpudef;
2151}
2152
2153static void x86_register_cpudef_type(X86CPUDefinition *def)
2154{
2155 char *typename = x86_cpu_type_name(def->name);
2156 TypeInfo ti = {
2157 .name = typename,
2158 .parent = TYPE_X86_CPU,
2159 .class_init = x86_cpu_cpudef_class_init,
2160 .class_data = def,
2161 };
2162
2163 type_register(&ti);
2164 g_free(typename);
2165}
2166
c6dc6f63 2167#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2168
0e26b7b8
BS		 2169void cpu_clear_apic_feature(CPUX86State *env)
2170{
0514ef2f 2171 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2172}
2173
c6dc6f63
AP		 2174#endif /* !CONFIG_USER_ONLY */
2175
c04321b3 2176/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2177 */
2178void x86_cpudef_setup(void)
2179{
93bfef4c
CV		 2180 int i, j;
2181 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2182
2183 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2184 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2185
2186 /* Look for specific "cpudef" models that */
09faecf2 2187 /* have the QEMU version in .model_id */
93bfef4c 2188 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2189 if (strcmp(model_with_versions[j], def->name) == 0) {
2190 pstrcpy(def->model_id, sizeof(def->model_id),
2191 "QEMU Virtual CPU version ");
2192 pstrcat(def->model_id, sizeof(def->model_id),
2193 qemu_get_version());
93bfef4c
CV		 2194 break;
2195 }
2196 }
c6dc6f63 2197 }
c6dc6f63
AP		 2198}
2199
c6dc6f63
AP		 2200static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2201 uint32_t *ecx, uint32_t *edx)
2202{
2203 *ebx = env->cpuid_vendor1;
2204 *edx = env->cpuid_vendor2;
2205 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2206}
2207
2208void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2209 uint32_t *eax, uint32_t *ebx,
2210 uint32_t *ecx, uint32_t *edx)
2211{
a60f24b5
AF		 2212 X86CPU *cpu = x86_env_get_cpu(env);
2213 CPUState *cs = CPU(cpu);
2214
c6dc6f63
AP		 2215 /* test if maximum index reached */
2216 if (index & 0x80000000) {
b3baa152
BW		 2217 if (index > env->cpuid_xlevel) {
2218 if (env->cpuid_xlevel2 > 0) {
2219 /* Handle the Centaur's CPUID instruction. */
2220 if (index > env->cpuid_xlevel2) {
2221 index = env->cpuid_xlevel2;
2222 } else if (index < 0xC0000000) {
2223 index = env->cpuid_xlevel;
2224 }
2225 } else {
57f26ae7
EH		 2226 /* Intel documentation states that invalid EAX input will
2227 * return the same information as EAX=cpuid_level
2228 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2229 */
2230 index = env->cpuid_level;
b3baa152
BW		 2231 }
2232 }
c6dc6f63
AP		 2233 } else {
2234 if (index > env->cpuid_level)
2235 index = env->cpuid_level;
2236 }
2237
2238 switch(index) {
2239 case 0:
2240 *eax = env->cpuid_level;
2241 get_cpuid_vendor(env, ebx, ecx, edx);
2242 break;
2243 case 1:
2244 *eax = env->cpuid_version;
2245 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2246 *ecx = env->features[FEAT_1_ECX];
2247 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2248 if (cs->nr_cores * cs->nr_threads > 1) {
2249 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2250 *edx |= 1 << 28; /* HTT bit */
2251 }
2252 break;
2253 case 2:
2254 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2255 if (cpu->cache_info_passthrough) {
2256 host_cpuid(index, 0, eax, ebx, ecx, edx);
2257 break;
2258 }
5e891bf8 2259 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2260 *ebx = 0;
2261 *ecx = 0;
5e891bf8
EH		 2262 *edx = (L1D_DESCRIPTOR << 16) | \
2263 (L1I_DESCRIPTOR << 8) | \
2264 (L2_DESCRIPTOR);
c6dc6f63
AP		 2265 break;
2266 case 4:
2267 /* cache info: needed for Core compatibility */
787aaf57
BC		 2268 if (cpu->cache_info_passthrough) {
2269 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2270 *eax &= ~0xFC000000;
c6dc6f63 2271 } else {
2f7a21c4 2272 *eax = 0;
76c2975a 2273 switch (count) {
c6dc6f63 2274 case 0: /* L1 dcache info */
5e891bf8
EH		 2275 *eax |= CPUID_4_TYPE_DCACHE | \
2276 CPUID_4_LEVEL(1) | \
2277 CPUID_4_SELF_INIT_LEVEL;
2278 *ebx = (L1D_LINE_SIZE - 1) | \
2279 ((L1D_PARTITIONS - 1) << 12) | \
2280 ((L1D_ASSOCIATIVITY - 1) << 22);
2281 *ecx = L1D_SETS - 1;
2282 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2283 break;
2284 case 1: /* L1 icache info */
5e891bf8
EH		 2285 *eax |= CPUID_4_TYPE_ICACHE | \
2286 CPUID_4_LEVEL(1) | \
2287 CPUID_4_SELF_INIT_LEVEL;
2288 *ebx = (L1I_LINE_SIZE - 1) | \
2289 ((L1I_PARTITIONS - 1) << 12) | \
2290 ((L1I_ASSOCIATIVITY - 1) << 22);
2291 *ecx = L1I_SETS - 1;
2292 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2293 break;
2294 case 2: /* L2 cache info */
5e891bf8
EH		 2295 *eax |= CPUID_4_TYPE_UNIFIED | \
2296 CPUID_4_LEVEL(2) | \
2297 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2298 if (cs->nr_threads > 1) {
2299 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2300 }
5e891bf8
EH		 2301 *ebx = (L2_LINE_SIZE - 1) | \
2302 ((L2_PARTITIONS - 1) << 12) | \
2303 ((L2_ASSOCIATIVITY - 1) << 22);
2304 *ecx = L2_SETS - 1;
2305 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2306 break;
2307 default: /* end of info */
2308 *eax = 0;
2309 *ebx = 0;
2310 *ecx = 0;
2311 *edx = 0;
2312 break;
76c2975a
PB		 2313 }
2314 }
2315
2316 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2317 if ((*eax & 31) && cs->nr_cores > 1) {
2318 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2319 }
2320 break;
2321 case 5:
2322 /* mwait info: needed for Core compatibility */
2323 *eax = 0; /* Smallest monitor-line size in bytes */
2324 *ebx = 0; /* Largest monitor-line size in bytes */
2325 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2326 *edx = 0;
2327 break;
2328 case 6:
2329 /* Thermal and Power Leaf */
2330 *eax = 0;
2331 *ebx = 0;
2332 *ecx = 0;
2333 *edx = 0;
2334 break;
f7911686 2335 case 7:
13526728
EH		 2336 /* Structured Extended Feature Flags Enumeration Leaf */
2337 if (count == 0) {
2338 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2339 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2340 *ecx = 0; /* Reserved */
2341 *edx = 0; /* Reserved */
f7911686
YW		 2342 } else {
2343 *eax = 0;
2344 *ebx = 0;
2345 *ecx = 0;
2346 *edx = 0;
2347 }
2348 break;
c6dc6f63
AP		 2349 case 9:
2350 /* Direct Cache Access Information Leaf */
2351 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2352 *ebx = 0;
2353 *ecx = 0;
2354 *edx = 0;
2355 break;
2356 case 0xA:
2357 /* Architectural Performance Monitoring Leaf */
9337e3b6 2358 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2359 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2360
2361 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2362 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2363 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2364 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2365 } else {
2366 *eax = 0;
2367 *ebx = 0;
2368 *ecx = 0;
2369 *edx = 0;
2370 }
c6dc6f63 2371 break;
2560f19f
PB		 2372 case 0xD: {
2373 KVMState *s = cs->kvm_state;
2374 uint64_t kvm_mask;
2375 int i;
2376
51e49430 2377 /* Processor Extended State */
2560f19f
PB		 2378 *eax = 0;
2379 *ebx = 0;
2380 *ecx = 0;
2381 *edx = 0;
2382 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2383 break;
2384 }
2560f19f
PB		 2385 kvm_mask =
2386 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2387 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2388
2560f19f
PB		 2389 if (count == 0) {
2390 *ecx = 0x240;
2391 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2392 const ExtSaveArea *esa = &ext_save_areas[i];
2393 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2394 (kvm_mask & (1 << i)) != 0) {
2395 if (i < 32) {
2396 *eax |= 1 << i;
2397 } else {
2398 *edx |= 1 << (i - 32);
2399 }
2400 *ecx = MAX(*ecx, esa->offset + esa->size);
2401 }
2402 }
2403 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2404 *ebx = *ecx;
2405 } else if (count == 1) {
0bb0b2d2 2406 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2407 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2408 const ExtSaveArea *esa = &ext_save_areas[count];
2409 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2410 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2411 *eax = esa->size;
2412 *ebx = esa->offset;
2560f19f 2413 }
51e49430
SY		 2414 }
2415 break;
2560f19f 2416 }
c6dc6f63
AP		 2417 case 0x80000000:
2418 *eax = env->cpuid_xlevel;
2419 *ebx = env->cpuid_vendor1;
2420 *edx = env->cpuid_vendor2;
2421 *ecx = env->cpuid_vendor3;
2422 break;
2423 case 0x80000001:
2424 *eax = env->cpuid_version;
2425 *ebx = 0;
0514ef2f
EH		 2426 *ecx = env->features[FEAT_8000_0001_ECX];
2427 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2428
2429 /* The Linux kernel checks for the CMPLegacy bit and
2430 * discards multiple thread information if it is set.
2431 * So dont set it here for Intel to make Linux guests happy.
2432 */
ce3960eb 2433 if (cs->nr_cores * cs->nr_threads > 1) {
c6dc6f63
AP		 2434 uint32_t tebx, tecx, tedx;
2435 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2436 if (tebx != CPUID_VENDOR_INTEL_1 ||
2437 tedx != CPUID_VENDOR_INTEL_2 ||
2438 tecx != CPUID_VENDOR_INTEL_3) {
2439 *ecx |= 1 << 1; /* CmpLegacy bit */
2440 }
2441 }
c6dc6f63
AP		 2442 break;
2443 case 0x80000002:
2444 case 0x80000003:
2445 case 0x80000004:
2446 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2447 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2448 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2449 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2450 break;
2451 case 0x80000005:
2452 /* cache info (L1 cache) */
787aaf57
BC		 2453 if (cpu->cache_info_passthrough) {
2454 host_cpuid(index, 0, eax, ebx, ecx, edx);
2455 break;
2456 }
5e891bf8
EH		 2457 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2458 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2459 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2460 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2461 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2462 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2463 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2464 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2465 break;
2466 case 0x80000006:
2467 /* cache info (L2 cache) */
787aaf57
BC		 2468 if (cpu->cache_info_passthrough) {
2469 host_cpuid(index, 0, eax, ebx, ecx, edx);
2470 break;
2471 }
5e891bf8
EH		 2472 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2473 (L2_DTLB_2M_ENTRIES << 16) | \
2474 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2475 (L2_ITLB_2M_ENTRIES);
2476 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2477 (L2_DTLB_4K_ENTRIES << 16) | \
2478 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2479 (L2_ITLB_4K_ENTRIES);
2480 *ecx = (L2_SIZE_KB_AMD << 16) | \
2481 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2482 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2483 *edx = ((L3_SIZE_KB/512) << 18) | \
2484 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2485 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2486 break;
303752a9
MT		 2487 case 0x80000007:
2488 *eax = 0;
2489 *ebx = 0;
2490 *ecx = 0;
2491 *edx = env->features[FEAT_8000_0007_EDX];
2492 break;
c6dc6f63
AP		 2493 case 0x80000008:
2494 /* virtual & phys address size in low 2 bytes. */
2495/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2496 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2497 /* 64 bit processor */
2498/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2499 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2500 } else {
0514ef2f 2501 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2502 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2503 } else {
c6dc6f63 2504 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2505 }
c6dc6f63
AP		 2506 }
2507 *ebx = 0;
2508 *ecx = 0;
2509 *edx = 0;
ce3960eb
AF		 2510 if (cs->nr_cores * cs->nr_threads > 1) {
2511 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2512 }
2513 break;
2514 case 0x8000000A:
0514ef2f 2515 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2516 *eax = 0x00000001; /* SVM Revision */
2517 *ebx = 0x00000010; /* nr of ASIDs */
2518 *ecx = 0;
0514ef2f 2519 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2520 } else {
2521 *eax = 0;
2522 *ebx = 0;
2523 *ecx = 0;
2524 *edx = 0;
2525 }
c6dc6f63 2526 break;
b3baa152
BW		 2527 case 0xC0000000:
2528 *eax = env->cpuid_xlevel2;
2529 *ebx = 0;
2530 *ecx = 0;
2531 *edx = 0;
2532 break;
2533 case 0xC0000001:
2534 /* Support for VIA CPU's CPUID instruction */
2535 *eax = env->cpuid_version;
2536 *ebx = 0;
2537 *ecx = 0;
0514ef2f 2538 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2539 break;
2540 case 0xC0000002:
2541 case 0xC0000003:
2542 case 0xC0000004:
2543 /* Reserved for the future, and now filled with zero */
2544 *eax = 0;
2545 *ebx = 0;
2546 *ecx = 0;
2547 *edx = 0;
2548 break;
c6dc6f63
AP		 2549 default:
2550 /* reserved values: zero */
2551 *eax = 0;
2552 *ebx = 0;
2553 *ecx = 0;
2554 *edx = 0;
2555 break;
2556 }
2557}
5fd2087a
AF		 2558
2559/* CPUClass::reset() */
2560static void x86_cpu_reset(CPUState *s)
2561{
2562 X86CPU *cpu = X86_CPU(s);
2563 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2564 CPUX86State *env = &cpu->env;
c1958aea
AF		 2565 int i;
2566
5fd2087a
AF		 2567 xcc->parent_reset(s);
2568
43175fa9 2569 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2570
00c8cb0a 2571 tlb_flush(s, 1);
c1958aea
AF		 2572
2573 env->old_exception = -1;
2574
2575 /* init to reset state */
2576
2577#ifdef CONFIG_SOFTMMU
2578 env->hflags |= HF_SOFTMMU_MASK;
2579#endif
2580 env->hflags2 |= HF2_GIF_MASK;
2581
2582 cpu_x86_update_cr0(env, 0x60000010);
2583 env->a20_mask = ~0x0;
2584 env->smbase = 0x30000;
2585
2586 env->idt.limit = 0xffff;
2587 env->gdt.limit = 0xffff;
2588 env->ldt.limit = 0xffff;
2589 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2590 env->tr.limit = 0xffff;
2591 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2592
2593 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2594 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2595 DESC_R_MASK | DESC_A_MASK);
2596 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2597 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2598 DESC_A_MASK);
2599 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2600 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2601 DESC_A_MASK);
2602 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2603 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2604 DESC_A_MASK);
2605 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2606 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2607 DESC_A_MASK);
2608 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2609 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2610 DESC_A_MASK);
2611
2612 env->eip = 0xfff0;
2613 env->regs[R_EDX] = env->cpuid_version;
2614
2615 env->eflags = 0x2;
2616
2617 /* FPU init */
2618 for (i = 0; i < 8; i++) {
2619 env->fptags[i] = 1;
2620 }
5bde1407 2621 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2622
2623 env->mxcsr = 0x1f80;
c74f41bb 2624 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2625
2626 env->pat = 0x0007040600070406ULL;
2627 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2628
2629 memset(env->dr, 0, sizeof(env->dr));
2630 env->dr[6] = DR6_FIXED_1;
2631 env->dr[7] = DR7_FIXED_1;
b3310ab3 2632 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2633 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2634
05e7e819 2635 env->xcr0 = 1;
0522604b 2636
9db2efd9
AW		 2637 /*
2638 * SDM 11.11.5 requires:
2639 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2640 * - IA32_MTRR_PHYSMASKn.V = 0
2641 * All other bits are undefined. For simplification, zero it all.
2642 */
2643 env->mtrr_deftype = 0;
2644 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2645 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2646
dd673288
IM		 2647#if !defined(CONFIG_USER_ONLY)
2648 /* We hard-wire the BSP to the first CPU. */
55e5c285 2649 if (s->cpu_index == 0) {
02e51483 2650 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2651 }
2652
259186a7 2653 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2654
2655 if (kvm_enabled()) {
2656 kvm_arch_reset_vcpu(cpu);
2657 }
dd673288 2658#endif
5fd2087a
AF		 2659}
2660
dd673288
IM		 2661#ifndef CONFIG_USER_ONLY
2662bool cpu_is_bsp(X86CPU *cpu)
2663{
02e51483 2664 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2665}
65dee380
IM		 2666
2667/* TODO: remove me, when reset over QOM tree is implemented */
2668static void x86_cpu_machine_reset_cb(void *opaque)
2669{
2670 X86CPU *cpu = opaque;
2671 cpu_reset(CPU(cpu));
2672}
dd673288
IM		 2673#endif
2674
de024815
AF		 2675static void mce_init(X86CPU *cpu)
2676{
2677 CPUX86State *cenv = &cpu->env;
2678 unsigned int bank;
2679
2680 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2681 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2682 (CPUID_MCE | CPUID_MCA)) {
2683 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2684 cenv->mcg_ctl = ~(uint64_t)0;
2685 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2686 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2687 }
2688 }
2689}
2690
bdeec802 2691#ifndef CONFIG_USER_ONLY
d3c64d6a 2692static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2693{
bdeec802 2694 CPUX86State *env = &cpu->env;
53a89e26 2695 DeviceState *dev = DEVICE(cpu);
449994eb 2696 APICCommonState *apic;
bdeec802
IM		 2697 const char *apic_type = "apic";
2698
2699 if (kvm_irqchip_in_kernel()) {
2700 apic_type = "kvm-apic";
2701 } else if (xen_enabled()) {
2702 apic_type = "xen-apic";
2703 }
2704
02e51483
CF		 2705 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2706 if (cpu->apic_state == NULL) {
bdeec802
IM		 2707 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2708 return;
2709 }
2710
2711 object_property_add_child(OBJECT(cpu), "apic",
02e51483
CF		 2712 OBJECT(cpu->apic_state), NULL);
2713 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2714 /* TODO: convert to link<> */
02e51483 2715 apic = APIC_COMMON(cpu->apic_state);
60671e58 2716 apic->cpu = cpu;
d3c64d6a
IM		 2717}
2718
2719static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2720{
02e51483 2721 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2722 return;
2723 }
bdeec802 2724
02e51483 2725 if (qdev_init(cpu->apic_state)) {
bdeec802 2726 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2727 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2728 return;
2729 }
bdeec802 2730}
d3c64d6a
IM		 2731#else
2732static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2733{
2734}
bdeec802
IM		 2735#endif
2736
e48638fd
WH		 2737
2738#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2739 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2740 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2741#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2742 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2743 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2744static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2745{
14a10fc3 2746 CPUState *cs = CPU(dev);
2b6f294c
AF		 2747 X86CPU *cpu = X86_CPU(dev);
2748 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2749 CPUX86State *env = &cpu->env;
2b6f294c 2750 Error *local_err = NULL;
e48638fd 2751 static bool ht_warned;
b34d12d1 2752
0514ef2f 2753 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2754 env->cpuid_level = 7;
2755 }
7a059953 2756
9b15cd9e
IM		 2757 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2758 * CPUID[1].EDX.
2759 */
e48638fd 2760 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2761 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2762 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2763 & CPUID_EXT2_AMD_ALIASES);
2764 }
2765
fefb41bf
EH		 2766
2767 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2768 error_setg(&local_err,
2769 kvm_enabled() ?
2770 "Host doesn't support requested features" :
2771 "TCG doesn't support requested features");
2772 goto out;
4586f157
IM		 2773 }
2774
65dee380
IM		 2775#ifndef CONFIG_USER_ONLY
2776 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2777
0514ef2f 2778 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2779 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2780 if (local_err != NULL) {
4dc1f449 2781 goto out;
bdeec802
IM		 2782 }
2783 }
65dee380
IM		 2784#endif
2785
7a059953 2786 mce_init(cpu);
14a10fc3 2787 qemu_init_vcpu(cs);
d3c64d6a 2788
e48638fd
WH		 2789 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2790 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2791 * based on inputs (sockets,cores,threads), it is still better to gives
2792 * users a warning.
2793 *
2794 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2795 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2796 */
2797 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2798 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2799 " -smp options properly.");
2800 ht_warned = true;
2801 }
2802
d3c64d6a
IM		 2803 x86_cpu_apic_realize(cpu, &local_err);
2804 if (local_err != NULL) {
2805 goto out;
2806 }
14a10fc3 2807 cpu_reset(cs);
2b6f294c 2808
4dc1f449
IM		 2809 xcc->parent_realize(dev, &local_err);
2810out:
2811 if (local_err != NULL) {
2812 error_propagate(errp, local_err);
2813 return;
2814 }
7a059953
AF		 2815}
2816
8932cfdf
EH		 2817/* Enables contiguous-apic-ID mode, for compatibility */
2818static bool compat_apic_id_mode;
2819
2820void enable_compat_apic_id_mode(void)
2821{
2822 compat_apic_id_mode = true;
2823}
2824
cb41bad3
EH		 2825/* Calculates initial APIC ID for a specific CPU index
2826 *
2827 * Currently we need to be able to calculate the APIC ID from the CPU index
2828 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2829 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2830 * all CPUs up to max_cpus.
2831 */
2832uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2833{
8932cfdf
EH		 2834 uint32_t correct_id;
2835 static bool warned;
2836
2837 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2838 if (compat_apic_id_mode) {
2839 if (cpu_index != correct_id && !warned) {
2840 error_report("APIC IDs set in compatibility mode, "
2841 "CPU topology won't match the configuration");
2842 warned = true;
2843 }
2844 return cpu_index;
2845 } else {
2846 return correct_id;
2847 }
cb41bad3
EH		 2848}
2849
de024815
AF		 2850static void x86_cpu_initfn(Object *obj)
2851{
55e5c285 2852 CPUState *cs = CPU(obj);
de024815 2853 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2854 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2855 CPUX86State *env = &cpu->env;
d65e9815 2856 static int inited;
de024815 2857
c05efcb1 2858 cs->env_ptr = env;
de024815 2859 cpu_exec_init(env);
71ad61d3
AF		 2860
2861 object_property_add(obj, "family", "int",
95b8519d 2862 x86_cpuid_version_get_family,
71ad61d3 2863 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2864 object_property_add(obj, "model", "int",
67e30c83 2865 x86_cpuid_version_get_model,
c5291a4f 2866 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2867 object_property_add(obj, "stepping", "int",
35112e41 2868 x86_cpuid_version_get_stepping,
036e2222 2869 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2870 object_property_add(obj, "level", "int",
2871 x86_cpuid_get_level,
2872 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2873 object_property_add(obj, "xlevel", "int",
2874 x86_cpuid_get_xlevel,
2875 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2876 object_property_add_str(obj, "vendor",
2877 x86_cpuid_get_vendor,
2878 x86_cpuid_set_vendor, NULL);
938d4c25 2879 object_property_add_str(obj, "model-id",
63e886eb 2880 x86_cpuid_get_model_id,
938d4c25 2881 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2882 object_property_add(obj, "tsc-frequency", "int",
2883 x86_cpuid_get_tsc_freq,
2884 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2885 object_property_add(obj, "apic-id", "int",
2886 x86_cpuid_get_apic_id,
2887 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2888 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2889 x86_cpu_get_feature_words,
7e5292b5
EH		 2890 NULL, NULL, (void *)env->features, NULL);
2891 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2892 x86_cpu_get_feature_words,
2893 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2894
92067bf4 2895 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
cb41bad3 2896 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2897
d940ee9b
EH		 2898 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2899
d65e9815
IM		 2900 /* init various static tables used in TCG mode */
2901 if (tcg_enabled() && !inited) {
2902 inited = 1;
2903 optimize_flags_init();
d65e9815 2904 }
de024815
AF		 2905}
2906
997395d3
IM		 2907static int64_t x86_cpu_get_arch_id(CPUState *cs)
2908{
2909 X86CPU *cpu = X86_CPU(cs);
2910 CPUX86State *env = &cpu->env;
2911
2912 return env->cpuid_apic_id;
2913}
2914
444d5590
AF		 2915static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2916{
2917 X86CPU *cpu = X86_CPU(cs);
2918
2919 return cpu->env.cr[0] & CR0_PG_MASK;
2920}
2921
f45748f1
AF		 2922static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2923{
2924 X86CPU *cpu = X86_CPU(cs);
2925
2926 cpu->env.eip = value;
2927}
2928
bdf7ae5b
AF		 2929static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2930{
2931 X86CPU *cpu = X86_CPU(cs);
2932
2933 cpu->env.eip = tb->pc - tb->cs_base;
2934}
2935
8c2e1b00
AF		 2936static bool x86_cpu_has_work(CPUState *cs)
2937{
2938 X86CPU *cpu = X86_CPU(cs);
2939 CPUX86State *env = &cpu->env;
2940
60e68042
PB		 2941#if !defined(CONFIG_USER_ONLY)
2942 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2943 apic_poll_irq(cpu->apic_state);
2944 cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
2945 }
2946#endif
2947
2948 return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
8c2e1b00
AF		 2949 (env->eflags & IF_MASK)) ||
2950 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2951 CPU_INTERRUPT_INIT |
2952 CPU_INTERRUPT_SIPI |
2953 CPU_INTERRUPT_MCE));
2954}
2955
9337e3b6
EH		 2956static Property x86_cpu_properties[] = {
2957 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2958 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2959 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2960 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2961 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2962 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2963 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2964 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2965 DEFINE_PROP_END_OF_LIST()
2966};
2967
5fd2087a
AF		 2968static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2969{
2970 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2971 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2972 DeviceClass *dc = DEVICE_CLASS(oc);
2973
2974 xcc->parent_realize = dc->realize;
2975 dc->realize = x86_cpu_realizefn;
62fc403f 2976 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2977 dc->props = x86_cpu_properties;
5fd2087a
AF		 2978
2979 xcc->parent_reset = cc->reset;
2980 cc->reset = x86_cpu_reset;
91b1df8c 2981 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2982
500050d1 2983 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2984 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2985 cc->has_work = x86_cpu_has_work;
97a8ea5a 2986 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 2987 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 2988 cc->dump_state = x86_cpu_dump_state;
f45748f1 2989 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2990 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2991 cc->gdb_read_register = x86_cpu_gdb_read_register;
2992 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2993 cc->get_arch_id = x86_cpu_get_arch_id;
2994 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2995#ifdef CONFIG_USER_ONLY
2996 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2997#else
a23bbfda 2998 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2999 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3000 cc->write_elf64_note = x86_cpu_write_elf64_note;
3001 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3002 cc->write_elf32_note = x86_cpu_write_elf32_note;
3003 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3004 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3005#endif
a0e372f0 3006 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3007#ifndef CONFIG_USER_ONLY
3008 cc->debug_excp_handler = breakpoint_handler;
3009#endif
374e0cd4
RH		 3010 cc->cpu_exec_enter = x86_cpu_exec_enter;
3011 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 3012}
3013
3014static const TypeInfo x86_cpu_type_info = {
3015 .name = TYPE_X86_CPU,
3016 .parent = TYPE_CPU,
3017 .instance_size = sizeof(X86CPU),
de024815 3018 .instance_init = x86_cpu_initfn,
d940ee9b 3019 .abstract = true,
5fd2087a
AF		 3020 .class_size = sizeof(X86CPUClass),
3021 .class_init = x86_cpu_common_class_init,
3022};
3023
3024static void x86_cpu_register_types(void)
3025{
d940ee9b
EH		 3026 int i;
3027
5fd2087a 3028 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3029 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3030 x86_register_cpudef_type(&builtin_x86_defs[i]);
3031 }
3032#ifdef CONFIG_KVM
3033 type_register_static(&host_x86_cpu_type_info);
3034#endif
5fd2087a
AF		 3035}
3036
3037type_init(x86_cpu_register_types)
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