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KVM: nVMX: Fully support nested VMX preemption timer
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
bfd0a56b 715static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
f5c4368f 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
155a97a3
NHE		 1048static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049{
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051}
1052
644d711a
NHE		 1053static inline bool is_exception(u32 intr_info)
1054{
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057}
1058
1059static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1060static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1063
8b9cf98c 1064static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1065{
1066 int i;
1067
a2fa3e9f 1068 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1070 return i;
1071 return -1;
1072}
1073
2384d2b3
SY		 1074static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075{
1076 struct {
1077 u64 vpid : 16;
1078 u64 rsvd : 48;
1079 u64 gva;
1080 } operand = { vpid, 0, gva };
1081
4ecac3fd 1082 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1086}
1087
1439442c
SY		 1088static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089{
1090 struct {
1091 u64 eptp, gpa;
1092 } operand = {eptp, gpa};
1093
4ecac3fd 1094 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1098}
1099
26bb0981 1100static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1101{
1102 int i;
1103
8b9cf98c 1104 i = __find_msr_index(vmx, msr);
a75beee6 1105 if (i >= 0)
a2fa3e9f 1106 return &vmx->guest_msrs[i];
8b6d44c7 1107 return NULL;
7725f0ba
AK		 1108}
1109
6aa8b732
AK		 1110static void vmcs_clear(struct vmcs *vmcs)
1111{
1112 u64 phys_addr = __pa(vmcs);
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1117 : "cc", "memory");
1118 if (error)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120 vmcs, phys_addr);
1121}
1122
d462b819
NHE		 1123static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124{
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1128}
1129
7725b894
DX		 1130static void vmcs_load(struct vmcs *vmcs)
1131{
1132 u64 phys_addr = __pa(vmcs);
1133 u8 error;
1134
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1137 : "cc", "memory");
1138 if (error)
2844d849 1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1140 vmcs, phys_addr);
1141}
1142
8f536b76
ZY		 1143#ifdef CONFIG_KEXEC
1144/*
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1147 * default.
1148 */
1149static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151static inline void crash_enable_local_vmclear(int cpu)
1152{
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline void crash_disable_local_vmclear(int cpu)
1157{
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static inline int crash_local_vmclear_enabled(int cpu)
1162{
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164}
1165
1166static void crash_vmclear_local_loaded_vmcss(void)
1167{
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1170
1171 if (!crash_local_vmclear_enabled(cpu))
1172 return;
1173
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1177}
1178#else
1179static inline void crash_enable_local_vmclear(int cpu) { }
1180static inline void crash_disable_local_vmclear(int cpu) { }
1181#endif /* CONFIG_KEXEC */
1182
d462b819 1183static void __loaded_vmcs_clear(void *arg)
6aa8b732 1184{
d462b819 1185 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1186 int cpu = raw_smp_processor_id();
6aa8b732 1187
d462b819
NHE		 1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1191 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1192 crash_disable_local_vmclear(cpu);
d462b819 1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1194
1195 /*
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1200 */
1201 smp_wmb();
1202
d462b819 1203 loaded_vmcs_init(loaded_vmcs);
8f536b76 1204 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1205}
1206
d462b819 1207static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1208{
e6c7d321
XG		 1209 int cpu = loaded_vmcs->cpu;
1210
1211 if (cpu != -1)
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1214}
1215
1760dd49 1216static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1217{
1218 if (vmx->vpid == 0)
1219 return;
1220
518c8aee
GJ		 1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1223}
1224
b9d762fa
GJ		 1225static inline void vpid_sync_vcpu_global(void)
1226{
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229}
1230
1231static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232{
1233 if (cpu_has_vmx_invvpid_single())
1760dd49 1234 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1235 else
1236 vpid_sync_vcpu_global();
1237}
1238
1439442c
SY		 1239static inline void ept_sync_global(void)
1240{
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243}
1244
1245static inline void ept_sync_context(u64 eptp)
1246{
089d034e 1247 if (enable_ept) {
1439442c
SY		 1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250 else
1251 ept_sync_global();
1252 }
1253}
1254
96304217 1255static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1256{
5e520e62 1257 unsigned long value;
6aa8b732 1258
5e520e62
AK		 1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1261 return value;
1262}
1263
96304217 1264static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1270{
1271 return vmcs_readl(field);
1272}
1273
96304217 1274static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1275{
05b3e0c2 1276#ifdef CONFIG_X86_64
6aa8b732
AK		 1277 return vmcs_readl(field);
1278#else
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280#endif
1281}
1282
e52de1b8
AK		 1283static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284{
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287 dump_stack();
1288}
1289
6aa8b732
AK		 1290static void vmcs_writel(unsigned long field, unsigned long value)
1291{
1292 u8 error;
1293
4ecac3fd 1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1296 if (unlikely(error))
1297 vmwrite_error(field, value);
6aa8b732
AK		 1298}
1299
1300static void vmcs_write16(unsigned long field, u16 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write32(unsigned long field, u32 value)
1306{
1307 vmcs_writel(field, value);
1308}
1309
1310static void vmcs_write64(unsigned long field, u64 value)
1311{
6aa8b732 1312 vmcs_writel(field, value);
7682f2d0 1313#ifndef CONFIG_X86_64
6aa8b732
AK		 1314 asm volatile ("");
1315 vmcs_writel(field+1, value >> 32);
1316#endif
1317}
1318
2ab455cc
AL		 1319static void vmcs_clear_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1322}
1323
1324static void vmcs_set_bits(unsigned long field, u32 mask)
1325{
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1327}
1328
2fb92db1
AK		 1329static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330{
1331 vmx->segment_cache.bitmask = 0;
1332}
1333
1334static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335 unsigned field)
1336{
1337 bool ret;
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1343 }
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1346 return ret;
1347}
1348
1349static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350{
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355 return *p;
1356}
1357
1358static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359{
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364 return *p;
1365}
1366
1367static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368{
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373 return *p;
1374}
1375
1376static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377{
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382 return *p;
1383}
1384
abd3f2d6
AK		 1385static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386{
1387 u32 eb;
1388
fd7373cc
JK		 1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
7ffd92c5 1395 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1396 eb = ~0;
089d034e 1397 if (enable_ept)
1439442c 1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1401
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1406 */
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
abd3f2d6
AK		 1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1411}
1412
8bf00a52
GN		 1413static void clear_atomic_switch_msr_special(unsigned long entry,
1414 unsigned long exit)
1415{
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418}
1419
61d2ef2c
AK		 1420static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421{
1422 unsigned i;
1423 struct msr_autoload *m = &vmx->msr_autoload;
1424
8bf00a52
GN		 1425 switch (msr) {
1426 case MSR_EFER:
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1430 return;
1431 }
1432 break;
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438 return;
1439 }
1440 break;
110312c8
AK		 1441 }
1442
61d2ef2c
AK		 1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1445 break;
1446
1447 if (i == m->nr)
1448 return;
1449 --m->nr;
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454}
1455
8bf00a52
GN		 1456static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459{
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464}
1465
61d2ef2c
AK		 1466static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1468{
1469 unsigned i;
1470 struct msr_autoload *m = &vmx->msr_autoload;
1471
8bf00a52
GN		 1472 switch (msr) {
1473 case MSR_EFER:
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1477 GUEST_IA32_EFER,
1478 HOST_IA32_EFER,
1479 guest_val, host_val);
1480 return;
1481 }
1482 break;
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1491 return;
1492 }
1493 break;
110312c8
AK		 1494 }
1495
61d2ef2c
AK		 1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1498 break;
1499
e7fc6f93
GN		 1500 if (i == NR_AUTOLOAD_MSRS) {
1501 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr);
1503 return;
1504 } else if (i == m->nr) {
61d2ef2c
AK		 1505 ++m->nr;
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508 }
1509
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1514}
1515
33ed6329
AK		 1516static void reload_tss(void)
1517{
33ed6329
AK		 1518 /*
1519 * VT restores TR but not its size. Useless.
1520 */
d359192f 1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1522 struct desc_struct *descs;
33ed6329 1523
d359192f 1524 descs = (void *)gdt->address;
33ed6329
AK		 1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526 load_TR_desc();
33ed6329
AK		 1527}
1528
92c0d900 1529static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1530{
3a34a881 1531 u64 guest_efer;
51c6cf66
AK		 1532 u64 ignore_bits;
1533
f6801dff 1534 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1535
51c6cf66 1536 /*
0fa06071 1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1538 * outside long mode
1539 */
1540 ignore_bits = EFER_NX | EFER_SCE;
1541#ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1546#endif
51c6cf66
AK		 1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
26bb0981 1549 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1551
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559 return false;
1560 }
1561
26bb0981 1562 return true;
51c6cf66
AK		 1563}
1564
2d49ec72
GN		 1565static unsigned long segment_base(u16 selector)
1566{
d359192f 1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1568 struct desc_struct *d;
1569 unsigned long table_base;
1570 unsigned long v;
1571
1572 if (!(selector & ~3))
1573 return 0;
1574
d359192f 1575 table_base = gdt->address;
2d49ec72
GN		 1576
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1579
1580 if (!(ldt_selector & ~3))
1581 return 0;
1582
1583 table_base = segment_base(ldt_selector);
1584 }
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587#ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590#endif
1591 return v;
1592}
1593
1594static inline unsigned long kvm_read_tr_base(void)
1595{
1596 u16 tr;
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1599}
1600
04d2cc77 1601static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1602{
04d2cc77 1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1604 int i;
04d2cc77 1605
a2fa3e9f 1606 if (vmx->host_state.loaded)
33ed6329
AK		 1607 return;
1608
a2fa3e9f 1609 vmx->host_state.loaded = 1;
33ed6329
AK		 1610 /*
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1613 */
d6e88aec 1614 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1616 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1617 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1619 vmx->host_state.fs_reload_needed = 0;
1620 } else {
33ed6329 1621 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1622 vmx->host_state.fs_reload_needed = 1;
33ed6329 1623 }
9581d442 1624 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1627 else {
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1629 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1630 }
1631
b2da15ac
AK		 1632#ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1635#endif
1636
33ed6329
AK		 1637#ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640#else
a2fa3e9f
GH		 1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1643#endif
707c0874
AK		 1644
1645#ifdef CONFIG_X86_64
c8770e7b
AK		 1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
44ea2b17 1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1649#endif
26bb0981
AK		 1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
33ed6329
AK		 1654}
1655
a9b21b62 1656static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1657{
a2fa3e9f 1658 if (!vmx->host_state.loaded)
33ed6329
AK		 1659 return;
1660
e1beb1d3 1661 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1662 vmx->host_state.loaded = 0;
c8770e7b
AK		 1663#ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666#endif
152d3f2f 1667 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1668 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1669#ifdef CONFIG_X86_64
9581d442 1670 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1671#else
1672 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1673#endif
33ed6329 1674 }
0a77fe4c
AK		 1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1677#ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1681 }
b2da15ac 1682#endif
152d3f2f 1683 reload_tss();
44ea2b17 1684#ifdef CONFIG_X86_64
c8770e7b 1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1686#endif
b1a74bf8
SS		 1687 /*
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1690 */
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692 stts();
3444d7da 1693 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1694}
1695
a9b21b62
AK		 1696static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697{
1698 preempt_disable();
1699 __vmx_load_host_state(vmx);
1700 preempt_enable();
1701}
1702
6aa8b732
AK		 1703/*
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1706 */
15ad7146 1707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1708{
a2fa3e9f 1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1711
4610c9cc
DX		 1712 if (!vmm_exclusive)
1713 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1716
d462b819
NHE		 1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1720 }
1721
d462b819 1722 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1724 unsigned long sysenter_esp;
1725
a8eeb04a 1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1727 local_irq_disable();
8f536b76 1728 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1729
1730 /*
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1734 */
1735 smp_rmb();
1736
d462b819
NHE		 1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1739 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1740 local_irq_enable();
1741
6aa8b732
AK		 1742 /*
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1744 * processors.
1745 */
d6e88aec 1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1748
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1751 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1752 }
6aa8b732
AK		 1753}
1754
1755static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756{
a9b21b62 1757 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1758 if (!vmm_exclusive) {
d462b819
NHE		 1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760 vcpu->cpu = -1;
4610c9cc
DX		 1761 kvm_cpu_vmxoff();
1762 }
6aa8b732
AK		 1763}
1764
5fd86fcf
AK		 1765static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766{
81231c69
AK		 1767 ulong cr0;
1768
5fd86fcf
AK		 1769 if (vcpu->fpu_active)
1770 return;
1771 vcpu->fpu_active = 1;
81231c69
AK		 1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1776 update_exception_bitmap(vcpu);
edcafe3c 1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1782}
1783
edcafe3c
AK		 1784static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
fe3ef05c
NHE		 1786/*
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1790 */
1791static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795}
1796static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797{
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800}
1801
5fd86fcf
AK		 1802static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803{
36cf24e0
NHE		 1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1806 */
edcafe3c 1807 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1809 update_exception_bitmap(vcpu);
edcafe3c
AK		 1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1812 if (is_guest_mode(vcpu)) {
1813 /*
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1820 */
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825 } else
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1827}
1828
6aa8b732
AK		 1829static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830{
78ac8b47 1831 unsigned long rflags, save_rflags;
345dcaa8 1832
6de12732
AK		 1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 }
1841 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1842 }
6de12732 1843 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1844}
1845
1846static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847{
6de12732
AK		 1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1853 }
6aa8b732
AK		 1854 vmcs_writel(GUEST_RFLAGS, rflags);
1855}
1856
2809f5d2
GC		 1857static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858{
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 int ret = 0;
1861
1862 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1863 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1866
1867 return ret & mask;
1868}
1869
1870static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871{
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1874
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
48005f64 1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1879 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1880 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884}
1885
6aa8b732
AK		 1886static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887{
1888 unsigned long rip;
6aa8b732 1889
5fdbf976 1890 rip = kvm_rip_read(vcpu);
6aa8b732 1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1892 kvm_rip_write(vcpu, rip);
6aa8b732 1893
2809f5d2
GC		 1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1896}
1897
0b6ac343
NHE		 1898/*
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1901 */
e011c663 1902static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1903{
1904 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1905
e011c663 1906 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1907 return 0;
1908
1909 nested_vmx_vmexit(vcpu);
1910 return 1;
1911}
1912
298101da 1913static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1914 bool has_error_code, u32 error_code,
1915 bool reinject)
298101da 1916{
77ab6db0 1917 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1918 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1919
e011c663
GN		 1920 if (!reinject && is_guest_mode(vcpu) &&
1921 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1922 return;
1923
8ab2d2e2 1924 if (has_error_code) {
77ab6db0 1925 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1926 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927 }
77ab6db0 1928
7ffd92c5 1929 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1930 int inc_eip = 0;
1931 if (kvm_exception_is_soft(nr))
1932 inc_eip = vcpu->arch.event_exit_inst_len;
1933 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1934 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1935 return;
1936 }
1937
66fd3f7f
GN		 1938 if (kvm_exception_is_soft(nr)) {
1939 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1941 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942 } else
1943 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1946}
1947
4e47c7a6
SY		 1948static bool vmx_rdtscp_supported(void)
1949{
1950 return cpu_has_vmx_rdtscp();
1951}
1952
ad756a16
MJ		 1953static bool vmx_invpcid_supported(void)
1954{
1955 return cpu_has_vmx_invpcid() && enable_ept;
1956}
1957
a75beee6
ED		 1958/*
1959 * Swap MSR entry in host/guest MSR entry array.
1960 */
8b9cf98c 1961static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1962{
26bb0981 1963 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1964
1965 tmp = vmx->guest_msrs[to];
1966 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1968}
1969
8d14695f
YZ		 1970static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971{
1972 unsigned long *msr_bitmap;
1973
1974 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975 if (is_long_mode(vcpu))
1976 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977 else
1978 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979 } else {
1980 if (is_long_mode(vcpu))
1981 msr_bitmap = vmx_msr_bitmap_longmode;
1982 else
1983 msr_bitmap = vmx_msr_bitmap_legacy;
1984 }
1985
1986 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987}
1988
e38aea3e
AK		 1989/*
1990 * Set up the vmcs to automatically save and restore system
1991 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1992 * mode, as fiddling with msrs is very expensive.
1993 */
8b9cf98c 1994static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1995{
26bb0981 1996 int save_nmsrs, index;
e38aea3e 1997
a75beee6
ED		 1998 save_nmsrs = 0;
1999#ifdef CONFIG_X86_64
8b9cf98c 2000 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2001 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2002 if (index >= 0)
8b9cf98c
RR		 2003 move_msr_up(vmx, index, save_nmsrs++);
2004 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2005 if (index >= 0)
8b9cf98c
RR		 2006 move_msr_up(vmx, index, save_nmsrs++);
2007 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2008 if (index >= 0)
8b9cf98c 2009 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2010 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011 if (index >= 0 && vmx->rdtscp_enabled)
2012 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2013 /*
8c06585d 2014 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2015 * if efer.sce is enabled.
2016 */
8c06585d 2017 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2018 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2019 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2020 }
2021#endif
92c0d900
AK		 2022 index = __find_msr_index(vmx, MSR_EFER);
2023 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2024 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2025
26bb0981 2026 vmx->save_nmsrs = save_nmsrs;
5897297b 2027
8d14695f
YZ		 2028 if (cpu_has_vmx_msr_bitmap())
2029 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2030}
2031
6aa8b732
AK		 2032/*
2033 * reads and returns guest's timestamp counter "register"
2034 * guest_tsc = host_tsc + tsc_offset -- 21.3
2035 */
2036static u64 guest_read_tsc(void)
2037{
2038 u64 host_tsc, tsc_offset;
2039
2040 rdtscll(host_tsc);
2041 tsc_offset = vmcs_read64(TSC_OFFSET);
2042 return host_tsc + tsc_offset;
2043}
2044
d5c1785d
NHE		 2045/*
2046 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047 * counter, even if a nested guest (L2) is currently running.
2048 */
886b470c 2049u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2050{
886b470c 2051 u64 tsc_offset;
d5c1785d 2052
d5c1785d
NHE		 2053 tsc_offset = is_guest_mode(vcpu) ?
2054 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055 vmcs_read64(TSC_OFFSET);
2056 return host_tsc + tsc_offset;
2057}
2058
4051b188 2059/*
cc578287
ZA		 2060 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2061 * software catchup for faster rates on slower CPUs.
4051b188 2062 */
cc578287 2063static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2064{
cc578287
ZA		 2065 if (!scale)
2066 return;
2067
2068 if (user_tsc_khz > tsc_khz) {
2069 vcpu->arch.tsc_catchup = 1;
2070 vcpu->arch.tsc_always_catchup = 1;
2071 } else
2072 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2073}
2074
ba904635
WA		 2075static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076{
2077 return vmcs_read64(TSC_OFFSET);
2078}
2079
6aa8b732 2080/*
99e3e30a 2081 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2082 */
99e3e30a 2083static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2084{
27fc51b2 2085 if (is_guest_mode(vcpu)) {
7991825b 2086 /*
27fc51b2
NHE		 2087 * We're here if L1 chose not to trap WRMSR to TSC. According
2088 * to the spec, this should set L1's TSC; The offset that L1
2089 * set for L2 remains unchanged, and still needs to be added
2090 * to the newly set TSC to get L2's TSC.
7991825b 2091 */
27fc51b2
NHE		 2092 struct vmcs12 *vmcs12;
2093 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094 /* recalculate vmcs02.TSC_OFFSET: */
2095 vmcs12 = get_vmcs12(vcpu);
2096 vmcs_write64(TSC_OFFSET, offset +
2097 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098 vmcs12->tsc_offset : 0));
2099 } else {
489223ed
YY		 2100 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2102 vmcs_write64(TSC_OFFSET, offset);
2103 }
6aa8b732
AK		 2104}
2105
f1e2b260 2106static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2107{
2108 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2109
e48672fa 2110 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2111 if (is_guest_mode(vcpu)) {
2112 /* Even when running L2, the adjustment needs to apply to L1 */
2113 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2114 } else
2115 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116 offset + adjustment);
e48672fa
ZA		 2117}
2118
857e4099
JR		 2119static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120{
2121 return target_tsc - native_read_tsc();
2122}
2123
801d3424
NHE		 2124static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125{
2126 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128}
2129
2130/*
2131 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133 * all guests if the "nested" module option is off, and can also be disabled
2134 * for a single guest by disabling its VMX cpuid bit.
2135 */
2136static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137{
2138 return nested && guest_cpuid_has_vmx(vcpu);
2139}
2140
b87a51ae
NHE		 2141/*
2142 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143 * returned for the various VMX controls MSRs when nested VMX is enabled.
2144 * The same values should also be used to verify that vmcs12 control fields are
2145 * valid during nested entry from L1 to L2.
2146 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148 * bit in the high half is on if the corresponding bit in the control field
2149 * may be on. See also vmx_control_verify().
2150 * TODO: allow these variables to be modified (downgraded) by module options
2151 * or other means.
2152 */
2153static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2158static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2159static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2160static __init void nested_vmx_setup_ctls_msrs(void)
2161{
2162 /*
2163 * Note that as a general rule, the high half of the MSRs (bits in
2164 * the control fields which may be 1) should be initialized by the
2165 * intersection of the underlying hardware's MSR (i.e., features which
2166 * can be supported) and the list of features we want to expose -
2167 * because they are known to be properly supported in our code.
2168 * Also, usually, the low half of the MSRs (bits which must be 1) can
2169 * be set to 0, meaning that L1 may turn off any of these bits. The
2170 * reason is that if one of these bits is necessary, it will appear
2171 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172 * fields of vmcs01 and vmcs02, will turn these bits off - and
2173 * nested_vmx_exit_handled() will not pass related exits to L1.
2174 * These rules have exceptions below.
2175 */
2176
2177 /* pin-based controls */
eabeaacc
JK		 2178 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2179 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2180 /*
2181 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2183 */
eabeaacc
JK		 2184 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2185 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2186 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2187 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2188 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2189
33fb20c3
JK		 2190 /*
2191 * Exit controls
2192 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2193 * 17 must be 1.
2194 */
c0dfee58
ACL		 2195 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2196 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2197 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2199 nested_vmx_exit_ctls_high &=
b87a51ae 2200#ifdef CONFIG_X86_64
c0dfee58 2201 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2202#endif
7854cbca
ACL		 2203 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2204 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2205 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2206 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2207 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2208 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2209 }
8049d651 2210 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2211 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2212
2213 /* entry controls */
2214 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2215 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2216 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2217 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2218 nested_vmx_entry_ctls_high &=
57435349
JK		 2219#ifdef CONFIG_X86_64
2220 VM_ENTRY_IA32E_MODE |
2221#endif
2222 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2223 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2224 VM_ENTRY_LOAD_IA32_EFER);
57435349 2225
b87a51ae
NHE		 2226 /* cpu-based controls */
2227 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2228 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2229 nested_vmx_procbased_ctls_low = 0;
2230 nested_vmx_procbased_ctls_high &=
2231 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2232 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2233 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2234 CPU_BASED_CR3_STORE_EXITING |
2235#ifdef CONFIG_X86_64
2236 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2237#endif
2238 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2239 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2240 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2241 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2242 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2243 /*
2244 * We can allow some features even when not supported by the
2245 * hardware. For example, L1 can specify an MSR bitmap - and we
2246 * can use it to avoid exits to L1 - even when L0 runs L2
2247 * without MSR bitmaps.
2248 */
2249 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2250
2251 /* secondary cpu-based controls */
2252 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2253 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2254 nested_vmx_secondary_ctls_low = 0;
2255 nested_vmx_secondary_ctls_high &=
d6851fbe 2256 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2257 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2258 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2259
afa61f75
NHE		 2260 if (enable_ept) {
2261 /* nested EPT: emulate EPT also to L1 */
2262 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970
JK		 2263 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2264 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2265 nested_vmx_ept_caps &= vmx_capability.ept;
2266 /*
2267 * Since invept is completely emulated we support both global
2268 * and context invalidation independent of what host cpu
2269 * supports
2270 */
2271 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2272 VMX_EPT_EXTENT_CONTEXT_BIT;
2273 } else
2274 nested_vmx_ept_caps = 0;
2275
c18911a2
JK		 2276 /* miscellaneous data */
2277 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2278 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2279 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2280 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2281}
2282
2283static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2284{
2285 /*
2286 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2287 */
2288 return ((control & high) | low) == control;
2289}
2290
2291static inline u64 vmx_control_msr(u32 low, u32 high)
2292{
2293 return low | ((u64)high << 32);
2294}
2295
2296/*
2297 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2298 * also let it use VMX-specific MSRs.
2299 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2300 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2301 * like all other MSRs).
2302 */
2303static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2304{
2305 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2306 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2307 /*
2308 * According to the spec, processors which do not support VMX
2309 * should throw a #GP(0) when VMX capability MSRs are read.
2310 */
2311 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2312 return 1;
2313 }
2314
2315 switch (msr_index) {
2316 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2317 if (nested_vmx_allowed(vcpu)) {
2318 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2319 break;
2320 }
2321 return 0;
b87a51ae
NHE		 2322 case MSR_IA32_VMX_BASIC:
2323 /*
2324 * This MSR reports some information about VMX support. We
2325 * should return information about the VMX we emulate for the
2326 * guest, and the VMCS structure we give it - not about the
2327 * VMX support of the underlying hardware.
2328 */
2329 *pdata = VMCS12_REVISION |
2330 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2331 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2332 break;
2333 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2334 case MSR_IA32_VMX_PINBASED_CTLS:
2335 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2336 nested_vmx_pinbased_ctls_high);
2337 break;
2338 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2339 case MSR_IA32_VMX_PROCBASED_CTLS:
2340 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2341 nested_vmx_procbased_ctls_high);
2342 break;
2343 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2344 case MSR_IA32_VMX_EXIT_CTLS:
2345 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2346 nested_vmx_exit_ctls_high);
2347 break;
2348 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2349 case MSR_IA32_VMX_ENTRY_CTLS:
2350 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2351 nested_vmx_entry_ctls_high);
2352 break;
2353 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2354 *pdata = vmx_control_msr(nested_vmx_misc_low,
2355 nested_vmx_misc_high);
b87a51ae
NHE		 2356 break;
2357 /*
2358 * These MSRs specify bits which the guest must keep fixed (on or off)
2359 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2360 * We picked the standard core2 setting.
2361 */
2362#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2363#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2364 case MSR_IA32_VMX_CR0_FIXED0:
2365 *pdata = VMXON_CR0_ALWAYSON;
2366 break;
2367 case MSR_IA32_VMX_CR0_FIXED1:
2368 *pdata = -1ULL;
2369 break;
2370 case MSR_IA32_VMX_CR4_FIXED0:
2371 *pdata = VMXON_CR4_ALWAYSON;
2372 break;
2373 case MSR_IA32_VMX_CR4_FIXED1:
2374 *pdata = -1ULL;
2375 break;
2376 case MSR_IA32_VMX_VMCS_ENUM:
2377 *pdata = 0x1f;
2378 break;
2379 case MSR_IA32_VMX_PROCBASED_CTLS2:
2380 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2381 nested_vmx_secondary_ctls_high);
2382 break;
2383 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2384 /* Currently, no nested vpid support */
2385 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2386 break;
2387 default:
2388 return 0;
2389 }
2390
2391 return 1;
2392}
2393
b3897a49 2394static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2395{
b3897a49
NHE		 2396 u32 msr_index = msr_info->index;
2397 u64 data = msr_info->data;
2398 bool host_initialized = msr_info->host_initiated;
2399
b87a51ae
NHE		 2400 if (!nested_vmx_allowed(vcpu))
2401 return 0;
2402
b3897a49
NHE		 2403 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2404 if (!host_initialized &&
2405 to_vmx(vcpu)->nested.msr_ia32_feature_control
2406 & FEATURE_CONTROL_LOCKED)
2407 return 0;
2408 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2409 return 1;
b3897a49
NHE		 2410 }
2411
b87a51ae
NHE		 2412 /*
2413 * No need to treat VMX capability MSRs specially: If we don't handle
2414 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2415 */
2416 return 0;
2417}
2418
6aa8b732
AK		 2419/*
2420 * Reads an msr value (of 'msr_index') into 'pdata'.
2421 * Returns 0 on success, non-0 otherwise.
2422 * Assumes vcpu_load() was already called.
2423 */
2424static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2425{
2426 u64 data;
26bb0981 2427 struct shared_msr_entry *msr;
6aa8b732
AK		 2428
2429 if (!pdata) {
2430 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2431 return -EINVAL;
2432 }
2433
2434 switch (msr_index) {
05b3e0c2 2435#ifdef CONFIG_X86_64
6aa8b732
AK		 2436 case MSR_FS_BASE:
2437 data = vmcs_readl(GUEST_FS_BASE);
2438 break;
2439 case MSR_GS_BASE:
2440 data = vmcs_readl(GUEST_GS_BASE);
2441 break;
44ea2b17
AK		 2442 case MSR_KERNEL_GS_BASE:
2443 vmx_load_host_state(to_vmx(vcpu));
2444 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2445 break;
26bb0981 2446#endif
6aa8b732 2447 case MSR_EFER:
3bab1f5d 2448 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2449 case MSR_IA32_TSC:
6aa8b732
AK		 2450 data = guest_read_tsc();
2451 break;
2452 case MSR_IA32_SYSENTER_CS:
2453 data = vmcs_read32(GUEST_SYSENTER_CS);
2454 break;
2455 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2456 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2457 break;
2458 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2459 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2460 break;
4e47c7a6
SY		 2461 case MSR_TSC_AUX:
2462 if (!to_vmx(vcpu)->rdtscp_enabled)
2463 return 1;
2464 /* Otherwise falls through */
6aa8b732 2465 default:
b87a51ae
NHE		 2466 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2467 return 0;
8b9cf98c 2468 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2469 if (msr) {
2470 data = msr->data;
2471 break;
6aa8b732 2472 }
3bab1f5d 2473 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2474 }
2475
2476 *pdata = data;
2477 return 0;
2478}
2479
2480/*
2481 * Writes msr value into into the appropriate "register".
2482 * Returns 0 on success, non-0 otherwise.
2483 * Assumes vcpu_load() was already called.
2484 */
8fe8ab46 2485static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2486{
a2fa3e9f 2487 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2488 struct shared_msr_entry *msr;
2cc51560 2489 int ret = 0;
8fe8ab46
WA		 2490 u32 msr_index = msr_info->index;
2491 u64 data = msr_info->data;
2cc51560 2492
6aa8b732 2493 switch (msr_index) {
3bab1f5d 2494 case MSR_EFER:
8fe8ab46 2495 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2496 break;
16175a79 2497#ifdef CONFIG_X86_64
6aa8b732 2498 case MSR_FS_BASE:
2fb92db1 2499 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2500 vmcs_writel(GUEST_FS_BASE, data);
2501 break;
2502 case MSR_GS_BASE:
2fb92db1 2503 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2504 vmcs_writel(GUEST_GS_BASE, data);
2505 break;
44ea2b17
AK		 2506 case MSR_KERNEL_GS_BASE:
2507 vmx_load_host_state(vmx);
2508 vmx->msr_guest_kernel_gs_base = data;
2509 break;
6aa8b732
AK		 2510#endif
2511 case MSR_IA32_SYSENTER_CS:
2512 vmcs_write32(GUEST_SYSENTER_CS, data);
2513 break;
2514 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2515 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2516 break;
2517 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2518 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2519 break;
af24a4e4 2520 case MSR_IA32_TSC:
8fe8ab46 2521 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2522 break;
468d472f
SY		 2523 case MSR_IA32_CR_PAT:
2524 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2525 vmcs_write64(GUEST_IA32_PAT, data);
2526 vcpu->arch.pat = data;
2527 break;
2528 }
8fe8ab46 2529 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2530 break;
ba904635
WA		 2531 case MSR_IA32_TSC_ADJUST:
2532 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2533 break;
2534 case MSR_TSC_AUX:
2535 if (!vmx->rdtscp_enabled)
2536 return 1;
2537 /* Check reserved bit, higher 32 bits should be zero */
2538 if ((data >> 32) != 0)
2539 return 1;
2540 /* Otherwise falls through */
6aa8b732 2541 default:
b3897a49 2542 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2543 break;
8b9cf98c 2544 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2545 if (msr) {
2546 msr->data = data;
2225fd56
AK		 2547 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2548 preempt_disable();
9ee73970
AK		 2549 kvm_set_shared_msr(msr->index, msr->data,
2550 msr->mask);
2225fd56
AK		 2551 preempt_enable();
2552 }
3bab1f5d 2553 break;
6aa8b732 2554 }
8fe8ab46 2555 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2556 }
2557
2cc51560 2558 return ret;
6aa8b732
AK		 2559}
2560
5fdbf976 2561static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2562{
5fdbf976
MT		 2563 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2564 switch (reg) {
2565 case VCPU_REGS_RSP:
2566 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2567 break;
2568 case VCPU_REGS_RIP:
2569 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2570 break;
6de4f3ad
AK		 2571 case VCPU_EXREG_PDPTR:
2572 if (enable_ept)
2573 ept_save_pdptrs(vcpu);
2574 break;
5fdbf976
MT		 2575 default:
2576 break;
2577 }
6aa8b732
AK		 2578}
2579
6aa8b732
AK		 2580static __init int cpu_has_kvm_support(void)
2581{
6210e37b 2582 return cpu_has_vmx();
6aa8b732
AK		 2583}
2584
2585static __init int vmx_disabled_by_bios(void)
2586{
2587 u64 msr;
2588
2589 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2590 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2591 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2592 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2593 && tboot_enabled())
2594 return 1;
23f3e991 2595 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2596 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2597 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2598 && !tboot_enabled()) {
2599 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2600 "activate TXT before enabling KVM\n");
cafd6659 2601 return 1;
f9335afe 2602 }
23f3e991
JC		 2603 /* launched w/o TXT and VMX disabled */
2604 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2605 && !tboot_enabled())
2606 return 1;
cafd6659
SW		 2607 }
2608
2609 return 0;
6aa8b732
AK		 2610}
2611
7725b894
DX		 2612static void kvm_cpu_vmxon(u64 addr)
2613{
2614 asm volatile (ASM_VMX_VMXON_RAX
2615 : : "a"(&addr), "m"(addr)
2616 : "memory", "cc");
2617}
2618
10474ae8 2619static int hardware_enable(void *garbage)
6aa8b732
AK		 2620{
2621 int cpu = raw_smp_processor_id();
2622 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2623 u64 old, test_bits;
6aa8b732 2624
10474ae8
AG		 2625 if (read_cr4() & X86_CR4_VMXE)
2626 return -EBUSY;
2627
d462b819 2628 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2629
2630 /*
2631 * Now we can enable the vmclear operation in kdump
2632 * since the loaded_vmcss_on_cpu list on this cpu
2633 * has been initialized.
2634 *
2635 * Though the cpu is not in VMX operation now, there
2636 * is no problem to enable the vmclear operation
2637 * for the loaded_vmcss_on_cpu list is empty!
2638 */
2639 crash_enable_local_vmclear(cpu);
2640
6aa8b732 2641 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2642
2643 test_bits = FEATURE_CONTROL_LOCKED;
2644 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2645 if (tboot_enabled())
2646 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2647
2648 if ((old & test_bits) != test_bits) {
6aa8b732 2649 /* enable and lock */
cafd6659
SW		 2650 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2651 }
66aee91a 2652 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2653
4610c9cc
DX		 2654 if (vmm_exclusive) {
2655 kvm_cpu_vmxon(phys_addr);
2656 ept_sync_global();
2657 }
10474ae8 2658
357d1226 2659 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2660
10474ae8 2661 return 0;
6aa8b732
AK		 2662}
2663
d462b819 2664static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2665{
2666 int cpu = raw_smp_processor_id();
d462b819 2667 struct loaded_vmcs *v, *n;
543e4243 2668
d462b819
NHE		 2669 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2670 loaded_vmcss_on_cpu_link)
2671 __loaded_vmcs_clear(v);
543e4243
AK		 2672}
2673
710ff4a8
EH		 2674
2675/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2676 * tricks.
2677 */
2678static void kvm_cpu_vmxoff(void)
6aa8b732 2679{
4ecac3fd 2680 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2681}
2682
710ff4a8
EH		 2683static void hardware_disable(void *garbage)
2684{
4610c9cc 2685 if (vmm_exclusive) {
d462b819 2686 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2687 kvm_cpu_vmxoff();
2688 }
7725b894 2689 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2690}
2691
1c3d14fe 2692static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2693 u32 msr, u32 *result)
1c3d14fe
YS		 2694{
2695 u32 vmx_msr_low, vmx_msr_high;
2696 u32 ctl = ctl_min | ctl_opt;
2697
2698 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2699
2700 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2701 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2702
2703 /* Ensure minimum (required) set of control bits are supported. */
2704 if (ctl_min & ~ctl)
002c7f7c 2705 return -EIO;
1c3d14fe
YS		 2706
2707 *result = ctl;
2708 return 0;
2709}
2710
110312c8
AK		 2711static __init bool allow_1_setting(u32 msr, u32 ctl)
2712{
2713 u32 vmx_msr_low, vmx_msr_high;
2714
2715 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2716 return vmx_msr_high & ctl;
2717}
2718
002c7f7c 2719static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2720{
2721 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2722 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2723 u32 _pin_based_exec_control = 0;
2724 u32 _cpu_based_exec_control = 0;
f78e0e2e 2725 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2726 u32 _vmexit_control = 0;
2727 u32 _vmentry_control = 0;
2728
10166744 2729 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2730#ifdef CONFIG_X86_64
2731 CPU_BASED_CR8_LOAD_EXITING |
2732 CPU_BASED_CR8_STORE_EXITING |
2733#endif
d56f546d
SY		 2734 CPU_BASED_CR3_LOAD_EXITING |
2735 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2736 CPU_BASED_USE_IO_BITMAPS |
2737 CPU_BASED_MOV_DR_EXITING |
a7052897 2738 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2739 CPU_BASED_MWAIT_EXITING |
2740 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2741 CPU_BASED_INVLPG_EXITING |
2742 CPU_BASED_RDPMC_EXITING;
443381a8 2743
f78e0e2e 2744 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2745 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2746 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2747 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2748 &_cpu_based_exec_control) < 0)
002c7f7c 2749 return -EIO;
6e5d865c
YS		 2750#ifdef CONFIG_X86_64
2751 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2752 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2753 ~CPU_BASED_CR8_STORE_EXITING;
2754#endif
f78e0e2e 2755 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2756 min2 = 0;
2757 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2758 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2759 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2760 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2761 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2762 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2763 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2764 SECONDARY_EXEC_RDTSCP |
83d4c286 2765 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2766 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2767 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2768 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2769 if (adjust_vmx_controls(min2, opt2,
2770 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2771 &_cpu_based_2nd_exec_control) < 0)
2772 return -EIO;
2773 }
2774#ifndef CONFIG_X86_64
2775 if (!(_cpu_based_2nd_exec_control &
2776 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2777 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2778#endif
83d4c286
YZ		 2779
2780 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2781 _cpu_based_2nd_exec_control &= ~(
8d14695f 2782 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2783 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2784 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2785
d56f546d 2786 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2787 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2788 enabled */
5fff7d27
GN		 2789 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2790 CPU_BASED_CR3_STORE_EXITING |
2791 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2792 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2793 vmx_capability.ept, vmx_capability.vpid);
2794 }
1c3d14fe
YS		 2795
2796 min = 0;
2797#ifdef CONFIG_X86_64
2798 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2799#endif
a547c6db
YZ		 2800 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2801 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2802 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2803 &_vmexit_control) < 0)
002c7f7c 2804 return -EIO;
1c3d14fe 2805
01e439be
YZ		 2806 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2807 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2808 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2809 &_pin_based_exec_control) < 0)
2810 return -EIO;
2811
2812 if (!(_cpu_based_2nd_exec_control &
2813 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2814 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2815 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2816
468d472f
SY		 2817 min = 0;
2818 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2819 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2820 &_vmentry_control) < 0)
002c7f7c 2821 return -EIO;
6aa8b732 2822
c68876fd 2823 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2824
2825 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2826 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2827 return -EIO;
1c3d14fe
YS		 2828
2829#ifdef CONFIG_X86_64
2830 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2831 if (vmx_msr_high & (1u<<16))
002c7f7c 2832 return -EIO;
1c3d14fe
YS		 2833#endif
2834
2835 /* Require Write-Back (WB) memory type for VMCS accesses. */
2836 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2837 return -EIO;
1c3d14fe 2838
002c7f7c
YS		 2839 vmcs_conf->size = vmx_msr_high & 0x1fff;
2840 vmcs_conf->order = get_order(vmcs_config.size);
2841 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2842
002c7f7c
YS		 2843 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2844 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2845 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2846 vmcs_conf->vmexit_ctrl = _vmexit_control;
2847 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2848
110312c8
AK		 2849 cpu_has_load_ia32_efer =
2850 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2851 VM_ENTRY_LOAD_IA32_EFER)
2852 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2853 VM_EXIT_LOAD_IA32_EFER);
2854
8bf00a52
GN		 2855 cpu_has_load_perf_global_ctrl =
2856 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2857 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2858 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2859 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2860
2861 /*
2862 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2863 * but due to arrata below it can't be used. Workaround is to use
2864 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2865 *
2866 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2867 *
2868 * AAK155 (model 26)
2869 * AAP115 (model 30)
2870 * AAT100 (model 37)
2871 * BC86,AAY89,BD102 (model 44)
2872 * BA97 (model 46)
2873 *
2874 */
2875 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2876 switch (boot_cpu_data.x86_model) {
2877 case 26:
2878 case 30:
2879 case 37:
2880 case 44:
2881 case 46:
2882 cpu_has_load_perf_global_ctrl = false;
2883 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2884 "does not work properly. Using workaround\n");
2885 break;
2886 default:
2887 break;
2888 }
2889 }
2890
1c3d14fe 2891 return 0;
c68876fd 2892}
6aa8b732
AK		 2893
2894static struct vmcs *alloc_vmcs_cpu(int cpu)
2895{
2896 int node = cpu_to_node(cpu);
2897 struct page *pages;
2898 struct vmcs *vmcs;
2899
6484eb3e 2900 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2901 if (!pages)
2902 return NULL;
2903 vmcs = page_address(pages);
1c3d14fe
YS		 2904 memset(vmcs, 0, vmcs_config.size);
2905 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2906 return vmcs;
2907}
2908
2909static struct vmcs *alloc_vmcs(void)
2910{
d3b2c338 2911 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2912}
2913
2914static void free_vmcs(struct vmcs *vmcs)
2915{
1c3d14fe 2916 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2917}
2918
d462b819
NHE		 2919/*
2920 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2921 */
2922static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2923{
2924 if (!loaded_vmcs->vmcs)
2925 return;
2926 loaded_vmcs_clear(loaded_vmcs);
2927 free_vmcs(loaded_vmcs->vmcs);
2928 loaded_vmcs->vmcs = NULL;
2929}
2930
39959588 2931static void free_kvm_area(void)
6aa8b732
AK		 2932{
2933 int cpu;
2934
3230bb47 2935 for_each_possible_cpu(cpu) {
6aa8b732 2936 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2937 per_cpu(vmxarea, cpu) = NULL;
2938 }
6aa8b732
AK		 2939}
2940
6aa8b732
AK		 2941static __init int alloc_kvm_area(void)
2942{
2943 int cpu;
2944
3230bb47 2945 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2946 struct vmcs *vmcs;
2947
2948 vmcs = alloc_vmcs_cpu(cpu);
2949 if (!vmcs) {
2950 free_kvm_area();
2951 return -ENOMEM;
2952 }
2953
2954 per_cpu(vmxarea, cpu) = vmcs;
2955 }
2956 return 0;
2957}
2958
2959static __init int hardware_setup(void)
2960{
002c7f7c
YS		 2961 if (setup_vmcs_config(&vmcs_config) < 0)
2962 return -EIO;
50a37eb4
JR		 2963
2964 if (boot_cpu_has(X86_FEATURE_NX))
2965 kvm_enable_efer_bits(EFER_NX);
2966
93ba03c2
SY		 2967 if (!cpu_has_vmx_vpid())
2968 enable_vpid = 0;
abc4fc58
AG		 2969 if (!cpu_has_vmx_shadow_vmcs())
2970 enable_shadow_vmcs = 0;
93ba03c2 2971
4bc9b982
SY		 2972 if (!cpu_has_vmx_ept() ||
2973 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2974 enable_ept = 0;
3a624e29 2975 enable_unrestricted_guest = 0;
83c3a331 2976 enable_ept_ad_bits = 0;
3a624e29
NK		 2977 }
2978
83c3a331
XH		 2979 if (!cpu_has_vmx_ept_ad_bits())
2980 enable_ept_ad_bits = 0;
2981
3a624e29
NK		 2982 if (!cpu_has_vmx_unrestricted_guest())
2983 enable_unrestricted_guest = 0;
93ba03c2
SY		 2984
2985 if (!cpu_has_vmx_flexpriority())
2986 flexpriority_enabled = 0;
2987
95ba8273
GN		 2988 if (!cpu_has_vmx_tpr_shadow())
2989 kvm_x86_ops->update_cr8_intercept = NULL;
2990
54dee993
MT		 2991 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2992 kvm_disable_largepages();
2993
4b8d54f9
ZE		 2994 if (!cpu_has_vmx_ple())
2995 ple_gap = 0;
2996
01e439be
YZ		 2997 if (!cpu_has_vmx_apicv())
2998 enable_apicv = 0;
c7c9c56c 2999
01e439be 3000 if (enable_apicv)
c7c9c56c 3001 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3002 else {
c7c9c56c 3003 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3004 kvm_x86_ops->deliver_posted_interrupt = NULL;
3005 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3006 }
83d4c286 3007
b87a51ae
NHE		 3008 if (nested)
3009 nested_vmx_setup_ctls_msrs();
3010
6aa8b732
AK		 3011 return alloc_kvm_area();
3012}
3013
3014static __exit void hardware_unsetup(void)
3015{
3016 free_kvm_area();
3017}
3018
14168786
GN		 3019static bool emulation_required(struct kvm_vcpu *vcpu)
3020{
3021 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3022}
3023
91b0aa2c 3024static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3025 struct kvm_segment *save)
6aa8b732 3026{
d99e4152
GN		 3027 if (!emulate_invalid_guest_state) {
3028 /*
3029 * CS and SS RPL should be equal during guest entry according
3030 * to VMX spec, but in reality it is not always so. Since vcpu
3031 * is in the middle of the transition from real mode to
3032 * protected mode it is safe to assume that RPL 0 is a good
3033 * default value.
3034 */
3035 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3036 save->selector &= ~SELECTOR_RPL_MASK;
3037 save->dpl = save->selector & SELECTOR_RPL_MASK;
3038 save->s = 1;
6aa8b732 3039 }
d99e4152 3040 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3041}
3042
3043static void enter_pmode(struct kvm_vcpu *vcpu)
3044{
3045 unsigned long flags;
a89a8fb9 3046 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3047
d99e4152
GN		 3048 /*
3049 * Update real mode segment cache. It may be not up-to-date if sement
3050 * register was written while vcpu was in a guest mode.
3051 */
3052 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3053 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3054 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3055 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3056 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3057 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3058
7ffd92c5 3059 vmx->rmode.vm86_active = 0;
6aa8b732 3060
2fb92db1
AK		 3061 vmx_segment_cache_clear(vmx);
3062
f5f7b2fe 3063 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3064
3065 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3066 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3067 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3068 vmcs_writel(GUEST_RFLAGS, flags);
3069
66aee91a
RR		 3070 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3071 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3072
3073 update_exception_bitmap(vcpu);
3074
91b0aa2c
GN		 3075 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3076 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3077 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3078 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3079 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3080 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3081
3082 /* CPL is always 0 when CPU enters protected mode */
3083 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3084 vmx->cpl = 0;
6aa8b732
AK		 3085}
3086
f5f7b2fe 3087static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3088{
772e0318 3089 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3090 struct kvm_segment var = *save;
3091
3092 var.dpl = 0x3;
3093 if (seg == VCPU_SREG_CS)
3094 var.type = 0x3;
3095
3096 if (!emulate_invalid_guest_state) {
3097 var.selector = var.base >> 4;
3098 var.base = var.base & 0xffff0;
3099 var.limit = 0xffff;
3100 var.g = 0;
3101 var.db = 0;
3102 var.present = 1;
3103 var.s = 1;
3104 var.l = 0;
3105 var.unusable = 0;
3106 var.type = 0x3;
3107 var.avl = 0;
3108 if (save->base & 0xf)
3109 printk_once(KERN_WARNING "kvm: segment base is not "
3110 "paragraph aligned when entering "
3111 "protected mode (seg=%d)", seg);
3112 }
6aa8b732 3113
d99e4152
GN		 3114 vmcs_write16(sf->selector, var.selector);
3115 vmcs_write32(sf->base, var.base);
3116 vmcs_write32(sf->limit, var.limit);
3117 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3118}
3119
3120static void enter_rmode(struct kvm_vcpu *vcpu)
3121{
3122 unsigned long flags;
a89a8fb9 3123 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3124
f5f7b2fe
AK		 3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3126 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3128 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3129 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3130 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3131 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3132
7ffd92c5 3133 vmx->rmode.vm86_active = 1;
6aa8b732 3134
776e58ea
GN		 3135 /*
3136 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3137 * vcpu. Warn the user that an update is overdue.
776e58ea 3138 */
4918c6ca 3139 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3140 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3141 "called before entering vcpu\n");
776e58ea 3142
2fb92db1
AK		 3143 vmx_segment_cache_clear(vmx);
3144
4918c6ca 3145 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3146 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3147 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3148
3149 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3150 vmx->rmode.save_rflags = flags;
6aa8b732 3151
053de044 3152 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3153
3154 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3155 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3156 update_exception_bitmap(vcpu);
3157
d99e4152
GN		 3158 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3159 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3160 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3161 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3162 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3163 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3164
8668a3c4 3165 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3166}
3167
401d10de
AS		 3168static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3169{
3170 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3171 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3172
3173 if (!msr)
3174 return;
401d10de 3175
44ea2b17
AK		 3176 /*
3177 * Force kernel_gs_base reloading before EFER changes, as control
3178 * of this msr depends on is_long_mode().
3179 */
3180 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3181 vcpu->arch.efer = efer;
401d10de
AS		 3182 if (efer & EFER_LMA) {
3183 vmcs_write32(VM_ENTRY_CONTROLS,
3184 vmcs_read32(VM_ENTRY_CONTROLS) |
3185 VM_ENTRY_IA32E_MODE);
3186 msr->data = efer;
3187 } else {
3188 vmcs_write32(VM_ENTRY_CONTROLS,
3189 vmcs_read32(VM_ENTRY_CONTROLS) &
3190 ~VM_ENTRY_IA32E_MODE);
3191
3192 msr->data = efer & ~EFER_LME;
3193 }
3194 setup_msrs(vmx);
3195}
3196
05b3e0c2 3197#ifdef CONFIG_X86_64
6aa8b732
AK		 3198
3199static void enter_lmode(struct kvm_vcpu *vcpu)
3200{
3201 u32 guest_tr_ar;
3202
2fb92db1
AK		 3203 vmx_segment_cache_clear(to_vmx(vcpu));
3204
6aa8b732
AK		 3205 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3206 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3207 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3208 __func__);
6aa8b732
AK		 3209 vmcs_write32(GUEST_TR_AR_BYTES,
3210 (guest_tr_ar & ~AR_TYPE_MASK)
3211 | AR_TYPE_BUSY_64_TSS);
3212 }
da38f438 3213 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3214}
3215
3216static void exit_lmode(struct kvm_vcpu *vcpu)
3217{
6aa8b732
AK		 3218 vmcs_write32(VM_ENTRY_CONTROLS,
3219 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3220 & ~VM_ENTRY_IA32E_MODE);
da38f438 3221 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3222}
3223
3224#endif
3225
2384d2b3
SY		 3226static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3227{
b9d762fa 3228 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3229 if (enable_ept) {
3230 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3231 return;
4e1096d2 3232 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3233 }
2384d2b3
SY		 3234}
3235
e8467fda
AK		 3236static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3237{
3238 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3239
3240 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3241 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3242}
3243
aff48baa
AK		 3244static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3245{
3246 if (enable_ept && is_paging(vcpu))
3247 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3248 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3249}
3250
25c4c276 3251static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3252{
fc78f519
AK		 3253 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3254
3255 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3256 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3257}
3258
1439442c
SY		 3259static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3260{
6de4f3ad
AK		 3261 if (!test_bit(VCPU_EXREG_PDPTR,
3262 (unsigned long *)&vcpu->arch.regs_dirty))
3263 return;
3264
1439442c 3265 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3266 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3267 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3268 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3269 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3270 }
3271}
3272
8f5d549f
AK		 3273static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3274{
3275 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3276 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3277 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3278 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3279 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3280 }
6de4f3ad
AK		 3281
3282 __set_bit(VCPU_EXREG_PDPTR,
3283 (unsigned long *)&vcpu->arch.regs_avail);
3284 __set_bit(VCPU_EXREG_PDPTR,
3285 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3286}
3287
5e1746d6 3288static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3289
3290static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3291 unsigned long cr0,
3292 struct kvm_vcpu *vcpu)
3293{
5233dd51
MT		 3294 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3295 vmx_decache_cr3(vcpu);
1439442c
SY		 3296 if (!(cr0 & X86_CR0_PG)) {
3297 /* From paging/starting to nonpaging */
3298 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3299 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3300 (CPU_BASED_CR3_LOAD_EXITING |
3301 CPU_BASED_CR3_STORE_EXITING));
3302 vcpu->arch.cr0 = cr0;
fc78f519 3303 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3304 } else if (!is_paging(vcpu)) {
3305 /* From nonpaging to paging */
3306 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3307 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3308 ~(CPU_BASED_CR3_LOAD_EXITING |
3309 CPU_BASED_CR3_STORE_EXITING));
3310 vcpu->arch.cr0 = cr0;
fc78f519 3311 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3312 }
95eb84a7
SY		 3313
3314 if (!(cr0 & X86_CR0_WP))
3315 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3316}
3317
6aa8b732
AK		 3318static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3319{
7ffd92c5 3320 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3321 unsigned long hw_cr0;
3322
5037878e 3323 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3324 if (enable_unrestricted_guest)
5037878e 3325 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3326 else {
5037878e 3327 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3328
218e763f
GN		 3329 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3330 enter_pmode(vcpu);
6aa8b732 3331
218e763f
GN		 3332 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3333 enter_rmode(vcpu);
3334 }
6aa8b732 3335
05b3e0c2 3336#ifdef CONFIG_X86_64
f6801dff 3337 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3338 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3339 enter_lmode(vcpu);
707d92fa 3340 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3341 exit_lmode(vcpu);
3342 }
3343#endif
3344
089d034e 3345 if (enable_ept)
1439442c
SY		 3346 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3347
02daab21 3348 if (!vcpu->fpu_active)
81231c69 3349 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3350
6aa8b732 3351 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3352 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3353 vcpu->arch.cr0 = cr0;
14168786
GN		 3354
3355 /* depends on vcpu->arch.cr0 to be set to a new value */
3356 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3357}
3358
1439442c
SY		 3359static u64 construct_eptp(unsigned long root_hpa)
3360{
3361 u64 eptp;
3362
3363 /* TODO write the value reading from MSR */
3364 eptp = VMX_EPT_DEFAULT_MT |
3365 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3366 if (enable_ept_ad_bits)
3367 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3368 eptp |= (root_hpa & PAGE_MASK);
3369
3370 return eptp;
3371}
3372
6aa8b732
AK		 3373static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3374{
1439442c
SY		 3375 unsigned long guest_cr3;
3376 u64 eptp;
3377
3378 guest_cr3 = cr3;
089d034e 3379 if (enable_ept) {
1439442c
SY		 3380 eptp = construct_eptp(cr3);
3381 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3382 if (is_paging(vcpu) || is_guest_mode(vcpu))
3383 guest_cr3 = kvm_read_cr3(vcpu);
3384 else
3385 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3386 ept_load_pdptrs(vcpu);
1439442c
SY		 3387 }
3388
2384d2b3 3389 vmx_flush_tlb(vcpu);
1439442c 3390 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3391}
3392
5e1746d6 3393static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3394{
7ffd92c5 3395 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3396 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3397
5e1746d6
NHE		 3398 if (cr4 & X86_CR4_VMXE) {
3399 /*
3400 * To use VMXON (and later other VMX instructions), a guest
3401 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3402 * So basically the check on whether to allow nested VMX
3403 * is here.
3404 */
3405 if (!nested_vmx_allowed(vcpu))
3406 return 1;
1a0d74e6
JK		 3407 }
3408 if (to_vmx(vcpu)->nested.vmxon &&
3409 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3410 return 1;
3411
ad312c7c 3412 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3413 if (enable_ept) {
3414 if (!is_paging(vcpu)) {
3415 hw_cr4 &= ~X86_CR4_PAE;
3416 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3417 /*
3418 * SMEP is disabled if CPU is in non-paging mode in
3419 * hardware. However KVM always uses paging mode to
3420 * emulate guest non-paging mode with TDP.
3421 * To emulate this behavior, SMEP needs to be manually
3422 * disabled when guest switches to non-paging mode.
3423 */
3424 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3425 } else if (!(cr4 & X86_CR4_PAE)) {
3426 hw_cr4 &= ~X86_CR4_PAE;
3427 }
3428 }
1439442c
SY		 3429
3430 vmcs_writel(CR4_READ_SHADOW, cr4);
3431 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3432 return 0;
6aa8b732
AK		 3433}
3434
6aa8b732
AK		 3435static void vmx_get_segment(struct kvm_vcpu *vcpu,
3436 struct kvm_segment *var, int seg)
3437{
a9179499 3438 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3439 u32 ar;
3440
c6ad1153 3441 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3442 *var = vmx->rmode.segs[seg];
a9179499 3443 if (seg == VCPU_SREG_TR
2fb92db1 3444 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3445 return;
1390a28b
AK		 3446 var->base = vmx_read_guest_seg_base(vmx, seg);
3447 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3448 return;
a9179499 3449 }
2fb92db1
AK		 3450 var->base = vmx_read_guest_seg_base(vmx, seg);
3451 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3452 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3453 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3454 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3455 var->type = ar & 15;
3456 var->s = (ar >> 4) & 1;
3457 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3458 /*
3459 * Some userspaces do not preserve unusable property. Since usable
3460 * segment has to be present according to VMX spec we can use present
3461 * property to amend userspace bug by making unusable segment always
3462 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3463 * segment as unusable.
3464 */
3465 var->present = !var->unusable;
6aa8b732
AK		 3466 var->avl = (ar >> 12) & 1;
3467 var->l = (ar >> 13) & 1;
3468 var->db = (ar >> 14) & 1;
3469 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3470}
3471
a9179499
AK		 3472static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3473{
a9179499
AK		 3474 struct kvm_segment s;
3475
3476 if (to_vmx(vcpu)->rmode.vm86_active) {
3477 vmx_get_segment(vcpu, &s, seg);
3478 return s.base;
3479 }
2fb92db1 3480 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3481}
3482
b09408d0 3483static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3484{
b09408d0
MT		 3485 struct vcpu_vmx *vmx = to_vmx(vcpu);
3486
3eeb3288 3487 if (!is_protmode(vcpu))
2e4d2653
IE		 3488 return 0;
3489
f4c63e5d
AK		 3490 if (!is_long_mode(vcpu)
3491 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3492 return 3;
3493
69c73028
AK		 3494 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3495 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3496 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3497 }
d881e6f6
AK		 3498
3499 return vmx->cpl;
69c73028
AK		 3500}
3501
3502
653e3108 3503static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3504{
6aa8b732
AK		 3505 u32 ar;
3506
f0495f9b 3507 if (var->unusable || !var->present)
6aa8b732
AK		 3508 ar = 1 << 16;
3509 else {
3510 ar = var->type & 15;
3511 ar |= (var->s & 1) << 4;
3512 ar |= (var->dpl & 3) << 5;
3513 ar |= (var->present & 1) << 7;
3514 ar |= (var->avl & 1) << 12;
3515 ar |= (var->l & 1) << 13;
3516 ar |= (var->db & 1) << 14;
3517 ar |= (var->g & 1) << 15;
3518 }
653e3108
AK		 3519
3520 return ar;
3521}
3522
3523static void vmx_set_segment(struct kvm_vcpu *vcpu,
3524 struct kvm_segment *var, int seg)
3525{
7ffd92c5 3526 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3527 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3528
2fb92db1 3529 vmx_segment_cache_clear(vmx);
2f143240
GN		 3530 if (seg == VCPU_SREG_CS)
3531 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3532
1ecd50a9
GN		 3533 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3534 vmx->rmode.segs[seg] = *var;
3535 if (seg == VCPU_SREG_TR)
3536 vmcs_write16(sf->selector, var->selector);
3537 else if (var->s)
3538 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3539 goto out;
653e3108 3540 }
1ecd50a9 3541
653e3108
AK		 3542 vmcs_writel(sf->base, var->base);
3543 vmcs_write32(sf->limit, var->limit);
3544 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3545
3546 /*
3547 * Fix the "Accessed" bit in AR field of segment registers for older
3548 * qemu binaries.
3549 * IA32 arch specifies that at the time of processor reset the
3550 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3551 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3552 * state vmexit when "unrestricted guest" mode is turned on.
3553 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3554 * tree. Newer qemu binaries with that qemu fix would not need this
3555 * kvm hack.
3556 */
3557 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3558 var->type |= 0x1; /* Accessed */
3a624e29 3559
f924d66d 3560 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3561
3562out:
14168786 3563 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3564}
3565
6aa8b732
AK		 3566static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3567{
2fb92db1 3568 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3569
3570 *db = (ar >> 14) & 1;
3571 *l = (ar >> 13) & 1;
3572}
3573
89a27f4d 3574static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3575{
89a27f4d
GN		 3576 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3577 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3578}
3579
89a27f4d 3580static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3581{
89a27f4d
GN		 3582 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3583 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3584}
3585
89a27f4d 3586static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3587{
89a27f4d
GN		 3588 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3589 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3590}
3591
89a27f4d 3592static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3593{
89a27f4d
GN		 3594 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3595 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3596}
3597
648dfaa7
MG		 3598static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3599{
3600 struct kvm_segment var;
3601 u32 ar;
3602
3603 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3604 var.dpl = 0x3;
0647f4aa
GN		 3605 if (seg == VCPU_SREG_CS)
3606 var.type = 0x3;
648dfaa7
MG		 3607 ar = vmx_segment_access_rights(&var);
3608
3609 if (var.base != (var.selector << 4))
3610 return false;
89efbed0 3611 if (var.limit != 0xffff)
648dfaa7 3612 return false;
07f42f5f 3613 if (ar != 0xf3)
648dfaa7
MG		 3614 return false;
3615
3616 return true;
3617}
3618
3619static bool code_segment_valid(struct kvm_vcpu *vcpu)
3620{
3621 struct kvm_segment cs;
3622 unsigned int cs_rpl;
3623
3624 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3625 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3626
1872a3f4
AK		 3627 if (cs.unusable)
3628 return false;
648dfaa7
MG		 3629 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3630 return false;
3631 if (!cs.s)
3632 return false;
1872a3f4 3633 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3634 if (cs.dpl > cs_rpl)
3635 return false;
1872a3f4 3636 } else {
648dfaa7
MG		 3637 if (cs.dpl != cs_rpl)
3638 return false;
3639 }
3640 if (!cs.present)
3641 return false;
3642
3643 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3644 return true;
3645}
3646
3647static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3648{
3649 struct kvm_segment ss;
3650 unsigned int ss_rpl;
3651
3652 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3653 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3654
1872a3f4
AK		 3655 if (ss.unusable)
3656 return true;
3657 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3658 return false;
3659 if (!ss.s)
3660 return false;
3661 if (ss.dpl != ss_rpl) /* DPL != RPL */
3662 return false;
3663 if (!ss.present)
3664 return false;
3665
3666 return true;
3667}
3668
3669static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3670{
3671 struct kvm_segment var;
3672 unsigned int rpl;
3673
3674 vmx_get_segment(vcpu, &var, seg);
3675 rpl = var.selector & SELECTOR_RPL_MASK;
3676
1872a3f4
AK		 3677 if (var.unusable)
3678 return true;
648dfaa7
MG		 3679 if (!var.s)
3680 return false;
3681 if (!var.present)
3682 return false;
3683 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3684 if (var.dpl < rpl) /* DPL < RPL */
3685 return false;
3686 }
3687
3688 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3689 * rights flags
3690 */
3691 return true;
3692}
3693
3694static bool tr_valid(struct kvm_vcpu *vcpu)
3695{
3696 struct kvm_segment tr;
3697
3698 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3699
1872a3f4
AK		 3700 if (tr.unusable)
3701 return false;
648dfaa7
MG		 3702 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3703 return false;
1872a3f4 3704 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3705 return false;
3706 if (!tr.present)
3707 return false;
3708
3709 return true;
3710}
3711
3712static bool ldtr_valid(struct kvm_vcpu *vcpu)
3713{
3714 struct kvm_segment ldtr;
3715
3716 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3717
1872a3f4
AK		 3718 if (ldtr.unusable)
3719 return true;
648dfaa7
MG		 3720 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3721 return false;
3722 if (ldtr.type != 2)
3723 return false;
3724 if (!ldtr.present)
3725 return false;
3726
3727 return true;
3728}
3729
3730static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3731{
3732 struct kvm_segment cs, ss;
3733
3734 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3735 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3736
3737 return ((cs.selector & SELECTOR_RPL_MASK) ==
3738 (ss.selector & SELECTOR_RPL_MASK));
3739}
3740
3741/*
3742 * Check if guest state is valid. Returns true if valid, false if
3743 * not.
3744 * We assume that registers are always usable
3745 */
3746static bool guest_state_valid(struct kvm_vcpu *vcpu)
3747{
c5e97c80
GN		 3748 if (enable_unrestricted_guest)
3749 return true;
3750
648dfaa7 3751 /* real mode guest state checks */
f13882d8 3752 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3753 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3754 return false;
3755 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3756 return false;
3757 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3758 return false;
3759 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3760 return false;
3761 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3762 return false;
3763 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3764 return false;
3765 } else {
3766 /* protected mode guest state checks */
3767 if (!cs_ss_rpl_check(vcpu))
3768 return false;
3769 if (!code_segment_valid(vcpu))
3770 return false;
3771 if (!stack_segment_valid(vcpu))
3772 return false;
3773 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3774 return false;
3775 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3776 return false;
3777 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3778 return false;
3779 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3780 return false;
3781 if (!tr_valid(vcpu))
3782 return false;
3783 if (!ldtr_valid(vcpu))
3784 return false;
3785 }
3786 /* TODO:
3787 * - Add checks on RIP
3788 * - Add checks on RFLAGS
3789 */
3790
3791 return true;
3792}
3793
d77c26fc 3794static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3795{
40dcaa9f 3796 gfn_t fn;
195aefde 3797 u16 data = 0;
40dcaa9f 3798 int r, idx, ret = 0;
6aa8b732 3799
40dcaa9f 3800 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3801 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3802 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3803 if (r < 0)
10589a46 3804 goto out;
195aefde 3805 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3806 r = kvm_write_guest_page(kvm, fn++, &data,
3807 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3808 if (r < 0)
10589a46 3809 goto out;
195aefde
IE		 3810 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3811 if (r < 0)
10589a46 3812 goto out;
195aefde
IE		 3813 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3814 if (r < 0)
10589a46 3815 goto out;
195aefde 3816 data = ~0;
10589a46
MT		 3817 r = kvm_write_guest_page(kvm, fn, &data,
3818 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3819 sizeof(u8));
195aefde 3820 if (r < 0)
10589a46
MT		 3821 goto out;
3822
3823 ret = 1;
3824out:
40dcaa9f 3825 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3826 return ret;
6aa8b732
AK		 3827}
3828
b7ebfb05
SY		 3829static int init_rmode_identity_map(struct kvm *kvm)
3830{
40dcaa9f 3831 int i, idx, r, ret;
b7ebfb05
SY		 3832 pfn_t identity_map_pfn;
3833 u32 tmp;
3834
089d034e 3835 if (!enable_ept)
b7ebfb05
SY		 3836 return 1;
3837 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3838 printk(KERN_ERR "EPT: identity-mapping pagetable "
3839 "haven't been allocated!\n");
3840 return 0;
3841 }
3842 if (likely(kvm->arch.ept_identity_pagetable_done))
3843 return 1;
3844 ret = 0;
b927a3ce 3845 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3846 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3847 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3848 if (r < 0)
3849 goto out;
3850 /* Set up identity-mapping pagetable for EPT in real mode */
3851 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3852 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3853 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3854 r = kvm_write_guest_page(kvm, identity_map_pfn,
3855 &tmp, i * sizeof(tmp), sizeof(tmp));
3856 if (r < 0)
3857 goto out;
3858 }
3859 kvm->arch.ept_identity_pagetable_done = true;
3860 ret = 1;
3861out:
40dcaa9f 3862 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3863 return ret;
3864}
3865
6aa8b732
AK		 3866static void seg_setup(int seg)
3867{
772e0318 3868 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3869 unsigned int ar;
6aa8b732
AK		 3870
3871 vmcs_write16(sf->selector, 0);
3872 vmcs_writel(sf->base, 0);
3873 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3874 ar = 0x93;
3875 if (seg == VCPU_SREG_CS)
3876 ar |= 0x08; /* code segment */
3a624e29
NK		 3877
3878 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3879}
3880
f78e0e2e
SY		 3881static int alloc_apic_access_page(struct kvm *kvm)
3882{
4484141a 3883 struct page *page;
f78e0e2e
SY		 3884 struct kvm_userspace_memory_region kvm_userspace_mem;
3885 int r = 0;
3886
79fac95e 3887 mutex_lock(&kvm->slots_lock);
bfc6d222 3888 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3889 goto out;
3890 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3891 kvm_userspace_mem.flags = 0;
3892 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3893 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3894 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3895 if (r)
3896 goto out;
72dc67a6 3897
4484141a
XG		 3898 page = gfn_to_page(kvm, 0xfee00);
3899 if (is_error_page(page)) {
3900 r = -EFAULT;
3901 goto out;
3902 }
3903
3904 kvm->arch.apic_access_page = page;
f78e0e2e 3905out:
79fac95e 3906 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3907 return r;
3908}
3909
b7ebfb05
SY		 3910static int alloc_identity_pagetable(struct kvm *kvm)
3911{
4484141a 3912 struct page *page;
b7ebfb05
SY		 3913 struct kvm_userspace_memory_region kvm_userspace_mem;
3914 int r = 0;
3915
79fac95e 3916 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3917 if (kvm->arch.ept_identity_pagetable)
3918 goto out;
3919 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3920 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3921 kvm_userspace_mem.guest_phys_addr =
3922 kvm->arch.ept_identity_map_addr;
b7ebfb05 3923 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3924 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3925 if (r)
3926 goto out;
3927
4484141a
XG		 3928 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3929 if (is_error_page(page)) {
3930 r = -EFAULT;
3931 goto out;
3932 }
3933
3934 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3935out:
79fac95e 3936 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3937 return r;
3938}
3939
2384d2b3
SY		 3940static void allocate_vpid(struct vcpu_vmx *vmx)
3941{
3942 int vpid;
3943
3944 vmx->vpid = 0;
919818ab 3945 if (!enable_vpid)
2384d2b3
SY		 3946 return;
3947 spin_lock(&vmx_vpid_lock);
3948 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3949 if (vpid < VMX_NR_VPIDS) {
3950 vmx->vpid = vpid;
3951 __set_bit(vpid, vmx_vpid_bitmap);
3952 }
3953 spin_unlock(&vmx_vpid_lock);
3954}
3955
cdbecfc3
LJ		 3956static void free_vpid(struct vcpu_vmx *vmx)
3957{
3958 if (!enable_vpid)
3959 return;
3960 spin_lock(&vmx_vpid_lock);
3961 if (vmx->vpid != 0)
3962 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3963 spin_unlock(&vmx_vpid_lock);
3964}
3965
8d14695f
YZ		 3966#define MSR_TYPE_R 1
3967#define MSR_TYPE_W 2
3968static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3969 u32 msr, int type)
25c5f225 3970{
3e7c73e9 3971 int f = sizeof(unsigned long);
25c5f225
SY		 3972
3973 if (!cpu_has_vmx_msr_bitmap())
3974 return;
3975
3976 /*
3977 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3978 * have the write-low and read-high bitmap offsets the wrong way round.
3979 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3980 */
25c5f225 3981 if (msr <= 0x1fff) {
8d14695f
YZ		 3982 if (type & MSR_TYPE_R)
3983 /* read-low */
3984 __clear_bit(msr, msr_bitmap + 0x000 / f);
3985
3986 if (type & MSR_TYPE_W)
3987 /* write-low */
3988 __clear_bit(msr, msr_bitmap + 0x800 / f);
3989
25c5f225
SY		 3990 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3991 msr &= 0x1fff;
8d14695f
YZ		 3992 if (type & MSR_TYPE_R)
3993 /* read-high */
3994 __clear_bit(msr, msr_bitmap + 0x400 / f);
3995
3996 if (type & MSR_TYPE_W)
3997 /* write-high */
3998 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3999
4000 }
4001}
4002
4003static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4004 u32 msr, int type)
4005{
4006 int f = sizeof(unsigned long);
4007
4008 if (!cpu_has_vmx_msr_bitmap())
4009 return;
4010
4011 /*
4012 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4013 * have the write-low and read-high bitmap offsets the wrong way round.
4014 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4015 */
4016 if (msr <= 0x1fff) {
4017 if (type & MSR_TYPE_R)
4018 /* read-low */
4019 __set_bit(msr, msr_bitmap + 0x000 / f);
4020
4021 if (type & MSR_TYPE_W)
4022 /* write-low */
4023 __set_bit(msr, msr_bitmap + 0x800 / f);
4024
4025 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4026 msr &= 0x1fff;
4027 if (type & MSR_TYPE_R)
4028 /* read-high */
4029 __set_bit(msr, msr_bitmap + 0x400 / f);
4030
4031 if (type & MSR_TYPE_W)
4032 /* write-high */
4033 __set_bit(msr, msr_bitmap + 0xc00 / f);
4034
25c5f225 4035 }
25c5f225
SY		 4036}
4037
5897297b
AK		 4038static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4039{
4040 if (!longmode_only)
8d14695f
YZ		 4041 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4042 msr, MSR_TYPE_R | MSR_TYPE_W);
4043 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4044 msr, MSR_TYPE_R | MSR_TYPE_W);
4045}
4046
4047static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4048{
4049 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4050 msr, MSR_TYPE_R);
4051 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4052 msr, MSR_TYPE_R);
4053}
4054
4055static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4056{
4057 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4058 msr, MSR_TYPE_R);
4059 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4060 msr, MSR_TYPE_R);
4061}
4062
4063static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4064{
4065 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4066 msr, MSR_TYPE_W);
4067 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4068 msr, MSR_TYPE_W);
5897297b
AK		 4069}
4070
01e439be
YZ		 4071static int vmx_vm_has_apicv(struct kvm *kvm)
4072{
4073 return enable_apicv && irqchip_in_kernel(kvm);
4074}
4075
a20ed54d
YZ		 4076/*
4077 * Send interrupt to vcpu via posted interrupt way.
4078 * 1. If target vcpu is running(non-root mode), send posted interrupt
4079 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4080 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4081 * interrupt from PIR in next vmentry.
4082 */
4083static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4084{
4085 struct vcpu_vmx *vmx = to_vmx(vcpu);
4086 int r;
4087
4088 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4089 return;
4090
4091 r = pi_test_and_set_on(&vmx->pi_desc);
4092 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4093#ifdef CONFIG_SMP
a20ed54d
YZ		 4094 if (!r && (vcpu->mode == IN_GUEST_MODE))
4095 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4096 POSTED_INTR_VECTOR);
4097 else
6ffbbbba 4098#endif
a20ed54d
YZ		 4099 kvm_vcpu_kick(vcpu);
4100}
4101
4102static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4103{
4104 struct vcpu_vmx *vmx = to_vmx(vcpu);
4105
4106 if (!pi_test_and_clear_on(&vmx->pi_desc))
4107 return;
4108
4109 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4110}
4111
4112static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4113{
4114 return;
4115}
4116
a3a8ff8e
NHE		 4117/*
4118 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4119 * will not change in the lifetime of the guest.
4120 * Note that host-state that does change is set elsewhere. E.g., host-state
4121 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4122 */
a547c6db 4123static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4124{
4125 u32 low32, high32;
4126 unsigned long tmpl;
4127 struct desc_ptr dt;
4128
b1a74bf8 4129 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4130 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4131 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4132
4133 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4134#ifdef CONFIG_X86_64
4135 /*
4136 * Load null selectors, so we can avoid reloading them in
4137 * __vmx_load_host_state(), in case userspace uses the null selectors
4138 * too (the expected case).
4139 */
4140 vmcs_write16(HOST_DS_SELECTOR, 0);
4141 vmcs_write16(HOST_ES_SELECTOR, 0);
4142#else
a3a8ff8e
NHE		 4143 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4144 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4145#endif
a3a8ff8e
NHE		 4146 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4147 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4148
4149 native_store_idt(&dt);
4150 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4151 vmx->host_idt_base = dt.address;
a3a8ff8e 4152
83287ea4 4153 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4154
4155 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4156 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4157 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4158 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4159
4160 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4161 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4162 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4163 }
4164}
4165
bf8179a0
NHE		 4166static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4167{
4168 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4169 if (enable_ept)
4170 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4171 if (is_guest_mode(&vmx->vcpu))
4172 vmx->vcpu.arch.cr4_guest_owned_bits &=
4173 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4174 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4175}
4176
01e439be
YZ		 4177static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4178{
4179 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4180
4181 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4182 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4183 return pin_based_exec_ctrl;
4184}
4185
bf8179a0
NHE		 4186static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4187{
4188 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4189 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4190 exec_control &= ~CPU_BASED_TPR_SHADOW;
4191#ifdef CONFIG_X86_64
4192 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4193 CPU_BASED_CR8_LOAD_EXITING;
4194#endif
4195 }
4196 if (!enable_ept)
4197 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4198 CPU_BASED_CR3_LOAD_EXITING |
4199 CPU_BASED_INVLPG_EXITING;
4200 return exec_control;
4201}
4202
4203static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4204{
4205 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4206 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4207 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4208 if (vmx->vpid == 0)
4209 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4210 if (!enable_ept) {
4211 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4212 enable_unrestricted_guest = 0;
ad756a16
MJ		 4213 /* Enable INVPCID for non-ept guests may cause performance regression. */
4214 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4215 }
4216 if (!enable_unrestricted_guest)
4217 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4218 if (!ple_gap)
4219 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4220 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4221 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4222 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4223 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4224 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4225 (handle_vmptrld).
4226 We can NOT enable shadow_vmcs here because we don't have yet
4227 a current VMCS12
4228 */
4229 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4230 return exec_control;
4231}
4232
ce88decf
XG		 4233static void ept_set_mmio_spte_mask(void)
4234{
4235 /*
4236 * EPT Misconfigurations can be generated if the value of bits 2:0
4237 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4238 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4239 * spte.
4240 */
885032b9 4241 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4242}
4243
6aa8b732
AK		 4244/*
4245 * Sets up the vmcs for emulated real mode.
4246 */
8b9cf98c 4247static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4248{
2e4ce7f5 4249#ifdef CONFIG_X86_64
6aa8b732 4250 unsigned long a;
2e4ce7f5 4251#endif
6aa8b732 4252 int i;
6aa8b732 4253
6aa8b732 4254 /* I/O */
3e7c73e9
AK		 4255 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4256 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4257
4607c2d7
AG		 4258 if (enable_shadow_vmcs) {
4259 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4260 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4261 }
25c5f225 4262 if (cpu_has_vmx_msr_bitmap())
5897297b 4263 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4264
6aa8b732
AK		 4265 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4266
6aa8b732 4267 /* Control */
01e439be 4268 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4269
bf8179a0 4270 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4271
83ff3b9d 4272 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4273 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4274 vmx_secondary_exec_control(vmx));
83ff3b9d 4275 }
f78e0e2e 4276
01e439be 4277 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4278 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4279 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4280 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4281 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4282
4283 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4284
4285 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4286 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4287 }
4288
4b8d54f9
ZE		 4289 if (ple_gap) {
4290 vmcs_write32(PLE_GAP, ple_gap);
4291 vmcs_write32(PLE_WINDOW, ple_window);
4292 }
4293
c3707958
XG		 4294 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4295 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4296 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4297
9581d442
AK		 4298 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4299 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4300 vmx_set_constant_host_state(vmx);
05b3e0c2 4301#ifdef CONFIG_X86_64
6aa8b732
AK		 4302 rdmsrl(MSR_FS_BASE, a);
4303 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4304 rdmsrl(MSR_GS_BASE, a);
4305 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4306#else
4307 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4308 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4309#endif
4310
2cc51560
ED		 4311 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4312 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4313 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4314 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4315 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4316
468d472f 4317 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4318 u32 msr_low, msr_high;
4319 u64 host_pat;
468d472f
SY		 4320 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4321 host_pat = msr_low | ((u64) msr_high << 32);
4322 /* Write the default value follow host pat */
4323 vmcs_write64(GUEST_IA32_PAT, host_pat);
4324 /* Keep arch.pat sync with GUEST_IA32_PAT */
4325 vmx->vcpu.arch.pat = host_pat;
4326 }
4327
6aa8b732
AK		 4328 for (i = 0; i < NR_VMX_MSR; ++i) {
4329 u32 index = vmx_msr_index[i];
4330 u32 data_low, data_high;
a2fa3e9f 4331 int j = vmx->nmsrs;
6aa8b732
AK		 4332
4333 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4334 continue;
432bd6cb
AK		 4335 if (wrmsr_safe(index, data_low, data_high) < 0)
4336 continue;
26bb0981
AK		 4337 vmx->guest_msrs[j].index = i;
4338 vmx->guest_msrs[j].data = 0;
d5696725 4339 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4340 ++vmx->nmsrs;
6aa8b732 4341 }
6aa8b732 4342
1c3d14fe 4343 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4344
4345 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4346 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4347
e00c8cf2 4348 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4349 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4350
4351 return 0;
4352}
4353
57f252f2 4354static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4355{
4356 struct vcpu_vmx *vmx = to_vmx(vcpu);
4357 u64 msr;
e00c8cf2 4358
7ffd92c5 4359 vmx->rmode.vm86_active = 0;
e00c8cf2 4360
3b86cd99
JK		 4361 vmx->soft_vnmi_blocked = 0;
4362
ad312c7c 4363 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4364 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4365 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4366 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4367 msr |= MSR_IA32_APICBASE_BSP;
4368 kvm_set_apic_base(&vmx->vcpu, msr);
4369
2fb92db1
AK		 4370 vmx_segment_cache_clear(vmx);
4371
5706be0d 4372 seg_setup(VCPU_SREG_CS);
66450a21 4373 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4374 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4375
4376 seg_setup(VCPU_SREG_DS);
4377 seg_setup(VCPU_SREG_ES);
4378 seg_setup(VCPU_SREG_FS);
4379 seg_setup(VCPU_SREG_GS);
4380 seg_setup(VCPU_SREG_SS);
4381
4382 vmcs_write16(GUEST_TR_SELECTOR, 0);
4383 vmcs_writel(GUEST_TR_BASE, 0);
4384 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4385 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4386
4387 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4388 vmcs_writel(GUEST_LDTR_BASE, 0);
4389 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4390 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4391
4392 vmcs_write32(GUEST_SYSENTER_CS, 0);
4393 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4394 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4395
4396 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4397 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4398
e00c8cf2
AK		 4399 vmcs_writel(GUEST_GDTR_BASE, 0);
4400 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4401
4402 vmcs_writel(GUEST_IDTR_BASE, 0);
4403 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4404
443381a8 4405 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4406 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4407 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4408
e00c8cf2
AK		 4409 /* Special registers */
4410 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4411
4412 setup_msrs(vmx);
4413
6aa8b732
AK		 4414 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4415
f78e0e2e
SY		 4416 if (cpu_has_vmx_tpr_shadow()) {
4417 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4418 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4419 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4420 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4421 vmcs_write32(TPR_THRESHOLD, 0);
4422 }
4423
4424 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4425 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4426 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4427
01e439be
YZ		 4428 if (vmx_vm_has_apicv(vcpu->kvm))
4429 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4430
2384d2b3
SY		 4431 if (vmx->vpid != 0)
4432 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4433
fa40052c 4434 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4435 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4436 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4437 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4438 vmx_fpu_activate(&vmx->vcpu);
4439 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4440
b9d762fa 4441 vpid_sync_context(vmx);
6aa8b732
AK		 4442}
4443
b6f1250e
NHE		 4444/*
4445 * In nested virtualization, check if L1 asked to exit on external interrupts.
4446 * For most existing hypervisors, this will always return true.
4447 */
4448static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4449{
4450 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4451 PIN_BASED_EXT_INTR_MASK;
4452}
4453
ea8ceb83
JK		 4454static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4455{
4456 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4457 PIN_BASED_NMI_EXITING;
4458}
4459
730dca42 4460static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4461{
4462 u32 cpu_based_vm_exec_control;
730dca42
JK		 4463
4464 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4465 /*
4466 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4467 * inject to L1 now because L2 must run. The caller will have
4468 * to make L2 exit right after entry, so we can inject to L1
4469 * more promptly.
b6f1250e 4470 */
730dca42 4471 return -EBUSY;
3b86cd99
JK		 4472
4473 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4474 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4475 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4476 return 0;
3b86cd99
JK		 4477}
4478
03b28f81 4479static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4480{
4481 u32 cpu_based_vm_exec_control;
4482
03b28f81
JK		 4483 if (!cpu_has_virtual_nmis())
4484 return enable_irq_window(vcpu);
4485
4486 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4487 return enable_irq_window(vcpu);
3b86cd99
JK		 4488
4489 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4490 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4491 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4492 return 0;
3b86cd99
JK		 4493}
4494
66fd3f7f 4495static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4496{
9c8cba37 4497 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4498 uint32_t intr;
4499 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4500
229456fc 4501 trace_kvm_inj_virq(irq);
2714d1d3 4502
fa89a817 4503 ++vcpu->stat.irq_injections;
7ffd92c5 4504 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4505 int inc_eip = 0;
4506 if (vcpu->arch.interrupt.soft)
4507 inc_eip = vcpu->arch.event_exit_inst_len;
4508 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4509 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4510 return;
4511 }
66fd3f7f
GN		 4512 intr = irq | INTR_INFO_VALID_MASK;
4513 if (vcpu->arch.interrupt.soft) {
4514 intr |= INTR_TYPE_SOFT_INTR;
4515 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4516 vmx->vcpu.arch.event_exit_inst_len);
4517 } else
4518 intr |= INTR_TYPE_EXT_INTR;
4519 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4520}
4521
f08864b4
SY		 4522static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4523{
66a5a347
JK		 4524 struct vcpu_vmx *vmx = to_vmx(vcpu);
4525
0b6ac343
NHE		 4526 if (is_guest_mode(vcpu))
4527 return;
4528
3b86cd99
JK		 4529 if (!cpu_has_virtual_nmis()) {
4530 /*
4531 * Tracking the NMI-blocked state in software is built upon
4532 * finding the next open IRQ window. This, in turn, depends on
4533 * well-behaving guests: They have to keep IRQs disabled at
4534 * least as long as the NMI handler runs. Otherwise we may
4535 * cause NMI nesting, maybe breaking the guest. But as this is
4536 * highly unlikely, we can live with the residual risk.
4537 */
4538 vmx->soft_vnmi_blocked = 1;
4539 vmx->vnmi_blocked_time = 0;
4540 }
4541
487b391d 4542 ++vcpu->stat.nmi_injections;
9d58b931 4543 vmx->nmi_known_unmasked = false;
7ffd92c5 4544 if (vmx->rmode.vm86_active) {
71f9833b 4545 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4546 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4547 return;
4548 }
f08864b4
SY		 4549 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4550 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4551}
4552
3cfc3092
JK		 4553static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4554{
4555 if (!cpu_has_virtual_nmis())
4556 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4557 if (to_vmx(vcpu)->nmi_known_unmasked)
4558 return false;
c332c83a 4559 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4560}
4561
4562static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4563{
4564 struct vcpu_vmx *vmx = to_vmx(vcpu);
4565
4566 if (!cpu_has_virtual_nmis()) {
4567 if (vmx->soft_vnmi_blocked != masked) {
4568 vmx->soft_vnmi_blocked = masked;
4569 vmx->vnmi_blocked_time = 0;
4570 }
4571 } else {
9d58b931 4572 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4573 if (masked)
4574 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4575 GUEST_INTR_STATE_NMI);
4576 else
4577 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4578 GUEST_INTR_STATE_NMI);
4579 }
4580}
4581
2505dc9f
JK		 4582static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4583{
ea8ceb83
JK		 4584 if (is_guest_mode(vcpu)) {
4585 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4586
4587 if (to_vmx(vcpu)->nested.nested_run_pending)
4588 return 0;
4589 if (nested_exit_on_nmi(vcpu)) {
4590 nested_vmx_vmexit(vcpu);
4591 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4592 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4593 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4594 /*
4595 * The NMI-triggered VM exit counts as injection:
4596 * clear this one and block further NMIs.
4597 */
4598 vcpu->arch.nmi_pending = 0;
4599 vmx_set_nmi_mask(vcpu, true);
4600 return 0;
4601 }
4602 }
4603
2505dc9f
JK		 4604 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4605 return 0;
4606
4607 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4608 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4609 | GUEST_INTR_STATE_NMI));
4610}
4611
78646121
GN		 4612static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4613{
e8457c67 4614 if (is_guest_mode(vcpu)) {
51cfe38e 4615 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4616
4617 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4618 return 0;
e8457c67
JK		 4619 if (nested_exit_on_intr(vcpu)) {
4620 nested_vmx_vmexit(vcpu);
4621 vmcs12->vm_exit_reason =
4622 EXIT_REASON_EXTERNAL_INTERRUPT;
4623 vmcs12->vm_exit_intr_info = 0;
4624 /*
4625 * fall through to normal code, but now in L1, not L2
4626 */
4627 }
b6f1250e
NHE		 4628 }
4629
c4282df9
GN		 4630 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4631 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4632 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4633}
4634
cbc94022
IE		 4635static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4636{
4637 int ret;
4638 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4639 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4640 .guest_phys_addr = addr,
4641 .memory_size = PAGE_SIZE * 3,
4642 .flags = 0,
4643 };
4644
47ae31e2 4645 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4646 if (ret)
4647 return ret;
bfc6d222 4648 kvm->arch.tss_addr = addr;
93ea5388
GN		 4649 if (!init_rmode_tss(kvm))
4650 return -ENOMEM;
4651
cbc94022
IE		 4652 return 0;
4653}
4654
0ca1b4f4 4655static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4656{
77ab6db0 4657 switch (vec) {
77ab6db0 4658 case BP_VECTOR:
c573cd22
JK		 4659 /*
4660 * Update instruction length as we may reinject the exception
4661 * from user space while in guest debugging mode.
4662 */
4663 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4664 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4665 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4666 return false;
4667 /* fall through */
4668 case DB_VECTOR:
4669 if (vcpu->guest_debug &
4670 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4671 return false;
d0bfb940
JK		 4672 /* fall through */
4673 case DE_VECTOR:
77ab6db0
JK		 4674 case OF_VECTOR:
4675 case BR_VECTOR:
4676 case UD_VECTOR:
4677 case DF_VECTOR:
4678 case SS_VECTOR:
4679 case GP_VECTOR:
4680 case MF_VECTOR:
0ca1b4f4
GN		 4681 return true;
4682 break;
77ab6db0 4683 }
0ca1b4f4
GN		 4684 return false;
4685}
4686
4687static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4688 int vec, u32 err_code)
4689{
4690 /*
4691 * Instruction with address size override prefix opcode 0x67
4692 * Cause the #SS fault with 0 error code in VM86 mode.
4693 */
4694 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4695 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4696 if (vcpu->arch.halt_request) {
4697 vcpu->arch.halt_request = 0;
4698 return kvm_emulate_halt(vcpu);
4699 }
4700 return 1;
4701 }
4702 return 0;
4703 }
4704
4705 /*
4706 * Forward all other exceptions that are valid in real mode.
4707 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4708 * the required debugging infrastructure rework.
4709 */
4710 kvm_queue_exception(vcpu, vec);
4711 return 1;
6aa8b732
AK		 4712}
4713
a0861c02
AK		 4714/*
4715 * Trigger machine check on the host. We assume all the MSRs are already set up
4716 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4717 * We pass a fake environment to the machine check handler because we want
4718 * the guest to be always treated like user space, no matter what context
4719 * it used internally.
4720 */
4721static void kvm_machine_check(void)
4722{
4723#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4724 struct pt_regs regs = {
4725 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4726 .flags = X86_EFLAGS_IF,
4727 };
4728
4729 do_machine_check(&regs, 0);
4730#endif
4731}
4732
851ba692 4733static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4734{
4735 /* already handled by vcpu_run */
4736 return 1;
4737}
4738
851ba692 4739static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4740{
1155f76a 4741 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4742 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4743 u32 intr_info, ex_no, error_code;
42dbaa5a 4744 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4745 u32 vect_info;
4746 enum emulation_result er;
4747
1155f76a 4748 vect_info = vmx->idt_vectoring_info;
88786475 4749 intr_info = vmx->exit_intr_info;
6aa8b732 4750
a0861c02 4751 if (is_machine_check(intr_info))
851ba692 4752 return handle_machine_check(vcpu);
a0861c02 4753
e4a41889 4754 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4755 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4756
4757 if (is_no_device(intr_info)) {
5fd86fcf 4758 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4759 return 1;
4760 }
4761
7aa81cc0 4762 if (is_invalid_opcode(intr_info)) {
51d8b661 4763 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4764 if (er != EMULATE_DONE)
7ee5d940 4765 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4766 return 1;
4767 }
4768
6aa8b732 4769 error_code = 0;
2e11384c 4770 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4771 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4772
4773 /*
4774 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4775 * MMIO, it is better to report an internal error.
4776 * See the comments in vmx_handle_exit.
4777 */
4778 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4779 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4780 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4781 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4782 vcpu->run->internal.ndata = 2;
4783 vcpu->run->internal.data[0] = vect_info;
4784 vcpu->run->internal.data[1] = intr_info;
4785 return 0;
4786 }
4787
6aa8b732 4788 if (is_page_fault(intr_info)) {
1439442c 4789 /* EPT won't cause page fault directly */
cf3ace79 4790 BUG_ON(enable_ept);
6aa8b732 4791 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4792 trace_kvm_page_fault(cr2, error_code);
4793
3298b75c 4794 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4795 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4796 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4797 }
4798
d0bfb940 4799 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4800
4801 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4802 return handle_rmode_exception(vcpu, ex_no, error_code);
4803
42dbaa5a
JK		 4804 switch (ex_no) {
4805 case DB_VECTOR:
4806 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4807 if (!(vcpu->guest_debug &
4808 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4809 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4810 kvm_queue_exception(vcpu, DB_VECTOR);
4811 return 1;
4812 }
4813 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4814 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4815 /* fall through */
4816 case BP_VECTOR:
c573cd22
JK		 4817 /*
4818 * Update instruction length as we may reinject #BP from
4819 * user space while in guest debugging mode. Reading it for
4820 * #DB as well causes no harm, it is not used in that case.
4821 */
4822 vmx->vcpu.arch.event_exit_inst_len =
4823 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4824 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4825 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4826 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4827 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4828 break;
4829 default:
d0bfb940
JK		 4830 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4831 kvm_run->ex.exception = ex_no;
4832 kvm_run->ex.error_code = error_code;
42dbaa5a 4833 break;
6aa8b732 4834 }
6aa8b732
AK		 4835 return 0;
4836}
4837
851ba692 4838static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4839{
1165f5fe 4840 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4841 return 1;
4842}
4843
851ba692 4844static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4845{
851ba692 4846 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4847 return 0;
4848}
6aa8b732 4849
851ba692 4850static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4851{
bfdaab09 4852 unsigned long exit_qualification;
34c33d16 4853 int size, in, string;
039576c0 4854 unsigned port;
6aa8b732 4855
bfdaab09 4856 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4857 string = (exit_qualification & 16) != 0;
cf8f70bf 4858 in = (exit_qualification & 8) != 0;
e70669ab 4859
cf8f70bf 4860 ++vcpu->stat.io_exits;
e70669ab 4861
cf8f70bf 4862 if (string || in)
51d8b661 4863 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4864
cf8f70bf
GN		 4865 port = exit_qualification >> 16;
4866 size = (exit_qualification & 7) + 1;
e93f36bc 4867 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4868
4869 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4870}
4871
102d8325
IM		 4872static void
4873vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4874{
4875 /*
4876 * Patch in the VMCALL instruction:
4877 */
4878 hypercall[0] = 0x0f;
4879 hypercall[1] = 0x01;
4880 hypercall[2] = 0xc1;
102d8325
IM		 4881}
4882
92fbc7b1
JK		 4883static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4884{
4885 unsigned long always_on = VMXON_CR0_ALWAYSON;
4886
4887 if (nested_vmx_secondary_ctls_high &
4888 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4889 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4890 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4891 return (val & always_on) == always_on;
4892}
4893
0fa06071 4894/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4895static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4896{
eeadf9e7 4897 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4898 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4899 unsigned long orig_val = val;
4900
eeadf9e7
NHE		 4901 /*
4902 * We get here when L2 changed cr0 in a way that did not change
4903 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4904 * but did change L0 shadowed bits. So we first calculate the
4905 * effective cr0 value that L1 would like to write into the
4906 * hardware. It consists of the L2-owned bits from the new
4907 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4908 */
1a0d74e6
JK		 4909 val = (val & ~vmcs12->cr0_guest_host_mask) |
4910 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4911
92fbc7b1 4912 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4913 return 1;
1a0d74e6
JK		 4914
4915 if (kvm_set_cr0(vcpu, val))
4916 return 1;
4917 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4918 return 0;
1a0d74e6
JK		 4919 } else {
4920 if (to_vmx(vcpu)->nested.vmxon &&
4921 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4922 return 1;
eeadf9e7 4923 return kvm_set_cr0(vcpu, val);
1a0d74e6 4924 }
eeadf9e7
NHE		 4925}
4926
4927static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4928{
4929 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4930 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4931 unsigned long orig_val = val;
4932
4933 /* analogously to handle_set_cr0 */
4934 val = (val & ~vmcs12->cr4_guest_host_mask) |
4935 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4936 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4937 return 1;
1a0d74e6 4938 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4939 return 0;
4940 } else
4941 return kvm_set_cr4(vcpu, val);
4942}
4943
4944/* called to set cr0 as approriate for clts instruction exit. */
4945static void handle_clts(struct kvm_vcpu *vcpu)
4946{
4947 if (is_guest_mode(vcpu)) {
4948 /*
4949 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4950 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4951 * just pretend it's off (also in arch.cr0 for fpu_activate).
4952 */
4953 vmcs_writel(CR0_READ_SHADOW,
4954 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4955 vcpu->arch.cr0 &= ~X86_CR0_TS;
4956 } else
4957 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4958}
4959
851ba692 4960static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4961{
229456fc 4962 unsigned long exit_qualification, val;
6aa8b732
AK		 4963 int cr;
4964 int reg;
49a9b07e 4965 int err;
6aa8b732 4966
bfdaab09 4967 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4968 cr = exit_qualification & 15;
4969 reg = (exit_qualification >> 8) & 15;
4970 switch ((exit_qualification >> 4) & 3) {
4971 case 0: /* mov to cr */
229456fc
MT		 4972 val = kvm_register_read(vcpu, reg);
4973 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4974 switch (cr) {
4975 case 0:
eeadf9e7 4976 err = handle_set_cr0(vcpu, val);
db8fcefa 4977 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4978 return 1;
4979 case 3:
2390218b 4980 err = kvm_set_cr3(vcpu, val);
db8fcefa 4981 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4982 return 1;
4983 case 4:
eeadf9e7 4984 err = handle_set_cr4(vcpu, val);
db8fcefa 4985 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4986 return 1;
0a5fff19
GN		 4987 case 8: {
4988 u8 cr8_prev = kvm_get_cr8(vcpu);
4989 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4990 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4991 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4992 if (irqchip_in_kernel(vcpu->kvm))
4993 return 1;
4994 if (cr8_prev <= cr8)
4995 return 1;
851ba692 4996 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4997 return 0;
4998 }
4b8073e4 4999 }
6aa8b732 5000 break;
25c4c276 5001 case 2: /* clts */
eeadf9e7 5002 handle_clts(vcpu);
4d4ec087 5003 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5004 skip_emulated_instruction(vcpu);
6b52d186 5005 vmx_fpu_activate(vcpu);
25c4c276 5006 return 1;
6aa8b732
AK		 5007 case 1: /*mov from cr*/
5008 switch (cr) {
5009 case 3:
9f8fe504
AK		 5010 val = kvm_read_cr3(vcpu);
5011 kvm_register_write(vcpu, reg, val);
5012 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5013 skip_emulated_instruction(vcpu);
5014 return 1;
5015 case 8:
229456fc
MT		 5016 val = kvm_get_cr8(vcpu);
5017 kvm_register_write(vcpu, reg, val);
5018 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5019 skip_emulated_instruction(vcpu);
5020 return 1;
5021 }
5022 break;
5023 case 3: /* lmsw */
a1f83a74 5024 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5025 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5026 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5027
5028 skip_emulated_instruction(vcpu);
5029 return 1;
5030 default:
5031 break;
5032 }
851ba692 5033 vcpu->run->exit_reason = 0;
a737f256 5034 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5035 (int)(exit_qualification >> 4) & 3, cr);
5036 return 0;
5037}
5038
851ba692 5039static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5040{
bfdaab09 5041 unsigned long exit_qualification;
6aa8b732
AK		 5042 int dr, reg;
5043
f2483415 5044 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5045 if (!kvm_require_cpl(vcpu, 0))
5046 return 1;
42dbaa5a
JK		 5047 dr = vmcs_readl(GUEST_DR7);
5048 if (dr & DR7_GD) {
5049 /*
5050 * As the vm-exit takes precedence over the debug trap, we
5051 * need to emulate the latter, either for the host or the
5052 * guest debugging itself.
5053 */
5054 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5055 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5056 vcpu->run->debug.arch.dr7 = dr;
5057 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5058 vmcs_readl(GUEST_CS_BASE) +
5059 vmcs_readl(GUEST_RIP);
851ba692
AK		 5060 vcpu->run->debug.arch.exception = DB_VECTOR;
5061 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5062 return 0;
5063 } else {
5064 vcpu->arch.dr7 &= ~DR7_GD;
5065 vcpu->arch.dr6 |= DR6_BD;
5066 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5067 kvm_queue_exception(vcpu, DB_VECTOR);
5068 return 1;
5069 }
5070 }
5071
bfdaab09 5072 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5073 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5074 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5075 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5076 unsigned long val;
5077 if (!kvm_get_dr(vcpu, dr, &val))
5078 kvm_register_write(vcpu, reg, val);
5079 } else
5080 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5081 skip_emulated_instruction(vcpu);
5082 return 1;
5083}
5084
020df079
GN		 5085static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5086{
5087 vmcs_writel(GUEST_DR7, val);
5088}
5089
851ba692 5090static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5091{
06465c5a
AK		 5092 kvm_emulate_cpuid(vcpu);
5093 return 1;
6aa8b732
AK		 5094}
5095
851ba692 5096static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5097{
ad312c7c 5098 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5099 u64 data;
5100
5101 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5102 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5103 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5104 return 1;
5105 }
5106
229456fc 5107 trace_kvm_msr_read(ecx, data);
2714d1d3 5108
6aa8b732 5109 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5110 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5111 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5112 skip_emulated_instruction(vcpu);
5113 return 1;
5114}
5115
851ba692 5116static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5117{
8fe8ab46 5118 struct msr_data msr;
ad312c7c
ZX		 5119 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5120 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5121 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5122
8fe8ab46
WA		 5123 msr.data = data;
5124 msr.index = ecx;
5125 msr.host_initiated = false;
5126 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5127 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5128 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5129 return 1;
5130 }
5131
59200273 5132 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5133 skip_emulated_instruction(vcpu);
5134 return 1;
5135}
5136
851ba692 5137static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5138{
3842d135 5139 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5140 return 1;
5141}
5142
851ba692 5143static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5144{
85f455f7
ED		 5145 u32 cpu_based_vm_exec_control;
5146
5147 /* clear pending irq */
5148 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5149 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5150 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5151
3842d135
AK		 5152 kvm_make_request(KVM_REQ_EVENT, vcpu);
5153
a26bf12a 5154 ++vcpu->stat.irq_window_exits;
2714d1d3 5155
c1150d8c
DL		 5156 /*
5157 * If the user space waits to inject interrupts, exit as soon as
5158 * possible
5159 */
8061823a 5160 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5161 vcpu->run->request_interrupt_window &&
8061823a 5162 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5163 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5164 return 0;
5165 }
6aa8b732
AK		 5166 return 1;
5167}
5168
851ba692 5169static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5170{
5171 skip_emulated_instruction(vcpu);
d3bef15f 5172 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5173}
5174
851ba692 5175static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5176{
510043da 5177 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5178 kvm_emulate_hypercall(vcpu);
5179 return 1;
c21415e8
IM		 5180}
5181
ec25d5e6
GN		 5182static int handle_invd(struct kvm_vcpu *vcpu)
5183{
51d8b661 5184 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5185}
5186
851ba692 5187static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5188{
f9c617f6 5189 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5190
5191 kvm_mmu_invlpg(vcpu, exit_qualification);
5192 skip_emulated_instruction(vcpu);
5193 return 1;
5194}
5195
fee84b07
AK		 5196static int handle_rdpmc(struct kvm_vcpu *vcpu)
5197{
5198 int err;
5199
5200 err = kvm_rdpmc(vcpu);
5201 kvm_complete_insn_gp(vcpu, err);
5202
5203 return 1;
5204}
5205
851ba692 5206static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5207{
5208 skip_emulated_instruction(vcpu);
f5f48ee1 5209 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5210 return 1;
5211}
5212
2acf923e
DC		 5213static int handle_xsetbv(struct kvm_vcpu *vcpu)
5214{
5215 u64 new_bv = kvm_read_edx_eax(vcpu);
5216 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5217
5218 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5219 skip_emulated_instruction(vcpu);
5220 return 1;
5221}
5222
851ba692 5223static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5224{
58fbbf26
KT		 5225 if (likely(fasteoi)) {
5226 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5227 int access_type, offset;
5228
5229 access_type = exit_qualification & APIC_ACCESS_TYPE;
5230 offset = exit_qualification & APIC_ACCESS_OFFSET;
5231 /*
5232 * Sane guest uses MOV to write EOI, with written value
5233 * not cared. So make a short-circuit here by avoiding
5234 * heavy instruction emulation.
5235 */
5236 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5237 (offset == APIC_EOI)) {
5238 kvm_lapic_set_eoi(vcpu);
5239 skip_emulated_instruction(vcpu);
5240 return 1;
5241 }
5242 }
51d8b661 5243 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5244}
5245
c7c9c56c
YZ		 5246static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5247{
5248 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5249 int vector = exit_qualification & 0xff;
5250
5251 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5252 kvm_apic_set_eoi_accelerated(vcpu, vector);
5253 return 1;
5254}
5255
83d4c286
YZ		 5256static int handle_apic_write(struct kvm_vcpu *vcpu)
5257{
5258 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5259 u32 offset = exit_qualification & 0xfff;
5260
5261 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5262 kvm_apic_write_nodecode(vcpu, offset);
5263 return 1;
5264}
5265
851ba692 5266static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5267{
60637aac 5268 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5269 unsigned long exit_qualification;
e269fb21
JK		 5270 bool has_error_code = false;
5271 u32 error_code = 0;
37817f29 5272 u16 tss_selector;
7f3d35fd 5273 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5274
5275 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5276 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5277 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5278
5279 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5280
5281 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5282 if (reason == TASK_SWITCH_GATE && idt_v) {
5283 switch (type) {
5284 case INTR_TYPE_NMI_INTR:
5285 vcpu->arch.nmi_injected = false;
654f06fc 5286 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5287 break;
5288 case INTR_TYPE_EXT_INTR:
66fd3f7f 5289 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5290 kvm_clear_interrupt_queue(vcpu);
5291 break;
5292 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5293 if (vmx->idt_vectoring_info &
5294 VECTORING_INFO_DELIVER_CODE_MASK) {
5295 has_error_code = true;
5296 error_code =
5297 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5298 }
5299 /* fall through */
64a7ec06
GN		 5300 case INTR_TYPE_SOFT_EXCEPTION:
5301 kvm_clear_exception_queue(vcpu);
5302 break;
5303 default:
5304 break;
5305 }
60637aac 5306 }
37817f29
IE		 5307 tss_selector = exit_qualification;
5308
64a7ec06
GN		 5309 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5310 type != INTR_TYPE_EXT_INTR &&
5311 type != INTR_TYPE_NMI_INTR))
5312 skip_emulated_instruction(vcpu);
5313
7f3d35fd
KW		 5314 if (kvm_task_switch(vcpu, tss_selector,
5315 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5316 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5317 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5318 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5319 vcpu->run->internal.ndata = 0;
42dbaa5a 5320 return 0;
acb54517 5321 }
42dbaa5a
JK		 5322
5323 /* clear all local breakpoint enable flags */
5324 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5325
5326 /*
5327 * TODO: What about debug traps on tss switch?
5328 * Are we supposed to inject them and update dr6?
5329 */
5330
5331 return 1;
37817f29
IE		 5332}
5333
851ba692 5334static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5335{
f9c617f6 5336 unsigned long exit_qualification;
1439442c 5337 gpa_t gpa;
4f5982a5 5338 u32 error_code;
1439442c 5339 int gla_validity;
1439442c 5340
f9c617f6 5341 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5342
1439442c
SY		 5343 gla_validity = (exit_qualification >> 7) & 0x3;
5344 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5345 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5346 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5347 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5348 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5349 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5350 (long unsigned int)exit_qualification);
851ba692
AK		 5351 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5352 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5353 return 0;
1439442c
SY		 5354 }
5355
0be9c7a8
GN		 5356 /*
5357 * EPT violation happened while executing iret from NMI,
5358 * "blocked by NMI" bit has to be set before next VM entry.
5359 * There are errata that may cause this bit to not be set:
5360 * AAK134, BY25.
5361 */
5362 if (exit_qualification & INTR_INFO_UNBLOCK_NMI)
5363 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5364
1439442c 5365 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5366 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5367
5368 /* It is a write fault? */
5369 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5370 /* It is a fetch fault? */
5371 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5372 /* ept page table is present? */
5373 error_code |= (exit_qualification >> 3) & 0x1;
5374
25d92081
YZ		 5375 vcpu->arch.exit_qualification = exit_qualification;
5376
4f5982a5 5377 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5378}
5379
68f89400
MT		 5380static u64 ept_rsvd_mask(u64 spte, int level)
5381{
5382 int i;
5383 u64 mask = 0;
5384
5385 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5386 mask |= (1ULL << i);
5387
5388 if (level > 2)
5389 /* bits 7:3 reserved */
5390 mask |= 0xf8;
5391 else if (level == 2) {
5392 if (spte & (1ULL << 7))
5393 /* 2MB ref, bits 20:12 reserved */
5394 mask |= 0x1ff000;
5395 else
5396 /* bits 6:3 reserved */
5397 mask |= 0x78;
5398 }
5399
5400 return mask;
5401}
5402
5403static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5404 int level)
5405{
5406 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5407
5408 /* 010b (write-only) */
5409 WARN_ON((spte & 0x7) == 0x2);
5410
5411 /* 110b (write/execute) */
5412 WARN_ON((spte & 0x7) == 0x6);
5413
5414 /* 100b (execute-only) and value not supported by logical processor */
5415 if (!cpu_has_vmx_ept_execute_only())
5416 WARN_ON((spte & 0x7) == 0x4);
5417
5418 /* not 000b */
5419 if ((spte & 0x7)) {
5420 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5421
5422 if (rsvd_bits != 0) {
5423 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5424 __func__, rsvd_bits);
5425 WARN_ON(1);
5426 }
5427
5428 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5429 u64 ept_mem_type = (spte & 0x38) >> 3;
5430
5431 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5432 ept_mem_type == 7) {
5433 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5434 __func__, ept_mem_type);
5435 WARN_ON(1);
5436 }
5437 }
5438 }
5439}
5440
851ba692 5441static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5442{
5443 u64 sptes[4];
ce88decf 5444 int nr_sptes, i, ret;
68f89400
MT		 5445 gpa_t gpa;
5446
5447 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5448
ce88decf 5449 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5450 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5451 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5452 EMULATE_DONE;
f8f55942
XG		 5453
5454 if (unlikely(ret == RET_MMIO_PF_INVALID))
5455 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5456
b37fbea6 5457 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5458 return 1;
5459
5460 /* It is the real ept misconfig */
68f89400
MT		 5461 printk(KERN_ERR "EPT: Misconfiguration.\n");
5462 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5463
5464 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5465
5466 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5467 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5468
851ba692
AK		 5469 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5470 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5471
5472 return 0;
5473}
5474
851ba692 5475static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5476{
5477 u32 cpu_based_vm_exec_control;
5478
5479 /* clear pending NMI */
5480 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5481 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5482 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5483 ++vcpu->stat.nmi_window_exits;
3842d135 5484 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5485
5486 return 1;
5487}
5488
80ced186 5489static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5490{
8b3079a5
AK		 5491 struct vcpu_vmx *vmx = to_vmx(vcpu);
5492 enum emulation_result err = EMULATE_DONE;
80ced186 5493 int ret = 1;
49e9d557
AK		 5494 u32 cpu_exec_ctrl;
5495 bool intr_window_requested;
b8405c18 5496 unsigned count = 130;
49e9d557
AK		 5497
5498 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5499 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5500
b8405c18 5501 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5502 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5503 return handle_interrupt_window(&vmx->vcpu);
5504
de87dcdd
AK		 5505 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5506 return 1;
5507
991eebf9 5508 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5509
ac0a48c3 5510 if (err == EMULATE_USER_EXIT) {
94452b9e 5511 ++vcpu->stat.mmio_exits;
80ced186
MG		 5512 ret = 0;
5513 goto out;
5514 }
1d5a4d9b 5515
de5f70e0
AK		 5516 if (err != EMULATE_DONE) {
5517 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5518 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5519 vcpu->run->internal.ndata = 0;
6d77dbfc 5520 return 0;
de5f70e0 5521 }
ea953ef0 5522
8d76c49e
GN		 5523 if (vcpu->arch.halt_request) {
5524 vcpu->arch.halt_request = 0;
5525 ret = kvm_emulate_halt(vcpu);
5526 goto out;
5527 }
5528
ea953ef0 5529 if (signal_pending(current))
80ced186 5530 goto out;
ea953ef0
MG		 5531 if (need_resched())
5532 schedule();
5533 }
5534
14168786 5535 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5536out:
5537 return ret;
ea953ef0
MG		 5538}
5539
4b8d54f9
ZE		 5540/*
5541 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5542 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5543 */
9fb41ba8 5544static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5545{
5546 skip_emulated_instruction(vcpu);
5547 kvm_vcpu_on_spin(vcpu);
5548
5549 return 1;
5550}
5551
59708670
SY		 5552static int handle_invalid_op(struct kvm_vcpu *vcpu)
5553{
5554 kvm_queue_exception(vcpu, UD_VECTOR);
5555 return 1;
5556}
5557
ff2f6fe9
NHE		 5558/*
5559 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5560 * We could reuse a single VMCS for all the L2 guests, but we also want the
5561 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5562 * allows keeping them loaded on the processor, and in the future will allow
5563 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5564 * every entry if they never change.
5565 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5566 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5567 *
5568 * The following functions allocate and free a vmcs02 in this pool.
5569 */
5570
5571/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5572static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5573{
5574 struct vmcs02_list *item;
5575 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5576 if (item->vmptr == vmx->nested.current_vmptr) {
5577 list_move(&item->list, &vmx->nested.vmcs02_pool);
5578 return &item->vmcs02;
5579 }
5580
5581 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5582 /* Recycle the least recently used VMCS. */
5583 item = list_entry(vmx->nested.vmcs02_pool.prev,
5584 struct vmcs02_list, list);
5585 item->vmptr = vmx->nested.current_vmptr;
5586 list_move(&item->list, &vmx->nested.vmcs02_pool);
5587 return &item->vmcs02;
5588 }
5589
5590 /* Create a new VMCS */
0fa24ce3 5591 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5592 if (!item)
5593 return NULL;
5594 item->vmcs02.vmcs = alloc_vmcs();
5595 if (!item->vmcs02.vmcs) {
5596 kfree(item);
5597 return NULL;
5598 }
5599 loaded_vmcs_init(&item->vmcs02);
5600 item->vmptr = vmx->nested.current_vmptr;
5601 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5602 vmx->nested.vmcs02_num++;
5603 return &item->vmcs02;
5604}
5605
5606/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5607static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5608{
5609 struct vmcs02_list *item;
5610 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5611 if (item->vmptr == vmptr) {
5612 free_loaded_vmcs(&item->vmcs02);
5613 list_del(&item->list);
5614 kfree(item);
5615 vmx->nested.vmcs02_num--;
5616 return;
5617 }
5618}
5619
5620/*
5621 * Free all VMCSs saved for this vcpu, except the one pointed by
5622 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5623 * currently used, if running L2), and vmcs01 when running L2.
5624 */
5625static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5626{
5627 struct vmcs02_list *item, *n;
5628 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5629 if (vmx->loaded_vmcs != &item->vmcs02)
5630 free_loaded_vmcs(&item->vmcs02);
5631 list_del(&item->list);
5632 kfree(item);
5633 }
5634 vmx->nested.vmcs02_num = 0;
5635
5636 if (vmx->loaded_vmcs != &vmx->vmcs01)
5637 free_loaded_vmcs(&vmx->vmcs01);
5638}
5639
0658fbaa
ACL		 5640/*
5641 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5642 * set the success or error code of an emulated VMX instruction, as specified
5643 * by Vol 2B, VMX Instruction Reference, "Conventions".
5644 */
5645static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5646{
5647 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5648 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5649 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5650}
5651
5652static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5653{
5654 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5655 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5656 X86_EFLAGS_SF | X86_EFLAGS_OF))
5657 | X86_EFLAGS_CF);
5658}
5659
145c28dd 5660static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5661 u32 vm_instruction_error)
5662{
5663 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5664 /*
5665 * failValid writes the error number to the current VMCS, which
5666 * can't be done there isn't a current VMCS.
5667 */
5668 nested_vmx_failInvalid(vcpu);
5669 return;
5670 }
5671 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5672 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5673 X86_EFLAGS_SF | X86_EFLAGS_OF))
5674 | X86_EFLAGS_ZF);
5675 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5676 /*
5677 * We don't need to force a shadow sync because
5678 * VM_INSTRUCTION_ERROR is not shadowed
5679 */
5680}
145c28dd 5681
ec378aee
NHE		 5682/*
5683 * Emulate the VMXON instruction.
5684 * Currently, we just remember that VMX is active, and do not save or even
5685 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5686 * do not currently need to store anything in that guest-allocated memory
5687 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5688 * argument is different from the VMXON pointer (which the spec says they do).
5689 */
5690static int handle_vmon(struct kvm_vcpu *vcpu)
5691{
5692 struct kvm_segment cs;
5693 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5694 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5695 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5696 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5697
5698 /* The Intel VMX Instruction Reference lists a bunch of bits that
5699 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5700 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5701 * Otherwise, we should fail with #UD. We test these now:
5702 */
5703 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5704 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5705 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5706 kvm_queue_exception(vcpu, UD_VECTOR);
5707 return 1;
5708 }
5709
5710 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5711 if (is_long_mode(vcpu) && !cs.l) {
5712 kvm_queue_exception(vcpu, UD_VECTOR);
5713 return 1;
5714 }
5715
5716 if (vmx_get_cpl(vcpu)) {
5717 kvm_inject_gp(vcpu, 0);
5718 return 1;
5719 }
145c28dd
AG		 5720 if (vmx->nested.vmxon) {
5721 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5722 skip_emulated_instruction(vcpu);
5723 return 1;
5724 }
b3897a49
NHE		 5725
5726 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5727 != VMXON_NEEDED_FEATURES) {
5728 kvm_inject_gp(vcpu, 0);
5729 return 1;
5730 }
5731
8de48833
AG		 5732 if (enable_shadow_vmcs) {
5733 shadow_vmcs = alloc_vmcs();
5734 if (!shadow_vmcs)
5735 return -ENOMEM;
5736 /* mark vmcs as shadow */
5737 shadow_vmcs->revision_id |= (1u << 31);
5738 /* init shadow vmcs */
5739 vmcs_clear(shadow_vmcs);
5740 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5741 }
ec378aee 5742
ff2f6fe9
NHE		 5743 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5744 vmx->nested.vmcs02_num = 0;
5745
ec378aee
NHE		 5746 vmx->nested.vmxon = true;
5747
5748 skip_emulated_instruction(vcpu);
a25eb114 5749 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5750 return 1;
5751}
5752
5753/*
5754 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5755 * for running VMX instructions (except VMXON, whose prerequisites are
5756 * slightly different). It also specifies what exception to inject otherwise.
5757 */
5758static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5759{
5760 struct kvm_segment cs;
5761 struct vcpu_vmx *vmx = to_vmx(vcpu);
5762
5763 if (!vmx->nested.vmxon) {
5764 kvm_queue_exception(vcpu, UD_VECTOR);
5765 return 0;
5766 }
5767
5768 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5769 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5770 (is_long_mode(vcpu) && !cs.l)) {
5771 kvm_queue_exception(vcpu, UD_VECTOR);
5772 return 0;
5773 }
5774
5775 if (vmx_get_cpl(vcpu)) {
5776 kvm_inject_gp(vcpu, 0);
5777 return 0;
5778 }
5779
5780 return 1;
5781}
5782
e7953d7f
AG		 5783static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5784{
8a1b9dd0 5785 u32 exec_control;
012f83cb
AG		 5786 if (enable_shadow_vmcs) {
5787 if (vmx->nested.current_vmcs12 != NULL) {
5788 /* copy to memory all shadowed fields in case
5789 they were modified */
5790 copy_shadow_to_vmcs12(vmx);
5791 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5792 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5793 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5794 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5795 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5796 }
5797 }
e7953d7f
AG		 5798 kunmap(vmx->nested.current_vmcs12_page);
5799 nested_release_page(vmx->nested.current_vmcs12_page);
5800}
5801
ec378aee
NHE		 5802/*
5803 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5804 * just stops using VMX.
5805 */
5806static void free_nested(struct vcpu_vmx *vmx)
5807{
5808 if (!vmx->nested.vmxon)
5809 return;
5810 vmx->nested.vmxon = false;
a9d30f33 5811 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5812 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5813 vmx->nested.current_vmptr = -1ull;
5814 vmx->nested.current_vmcs12 = NULL;
5815 }
e7953d7f
AG		 5816 if (enable_shadow_vmcs)
5817 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5818 /* Unpin physical memory we referred to in current vmcs02 */
5819 if (vmx->nested.apic_access_page) {
5820 nested_release_page(vmx->nested.apic_access_page);
5821 vmx->nested.apic_access_page = 0;
5822 }
ff2f6fe9
NHE		 5823
5824 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5825}
5826
5827/* Emulate the VMXOFF instruction */
5828static int handle_vmoff(struct kvm_vcpu *vcpu)
5829{
5830 if (!nested_vmx_check_permission(vcpu))
5831 return 1;
5832 free_nested(to_vmx(vcpu));
5833 skip_emulated_instruction(vcpu);
a25eb114 5834 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5835 return 1;
5836}
5837
064aea77
NHE		 5838/*
5839 * Decode the memory-address operand of a vmx instruction, as recorded on an
5840 * exit caused by such an instruction (run by a guest hypervisor).
5841 * On success, returns 0. When the operand is invalid, returns 1 and throws
5842 * #UD or #GP.
5843 */
5844static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5845 unsigned long exit_qualification,
5846 u32 vmx_instruction_info, gva_t *ret)
5847{
5848 /*
5849 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5850 * Execution", on an exit, vmx_instruction_info holds most of the
5851 * addressing components of the operand. Only the displacement part
5852 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5853 * For how an actual address is calculated from all these components,
5854 * refer to Vol. 1, "Operand Addressing".
5855 */
5856 int scaling = vmx_instruction_info & 3;
5857 int addr_size = (vmx_instruction_info >> 7) & 7;
5858 bool is_reg = vmx_instruction_info & (1u << 10);
5859 int seg_reg = (vmx_instruction_info >> 15) & 7;
5860 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5861 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5862 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5863 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5864
5865 if (is_reg) {
5866 kvm_queue_exception(vcpu, UD_VECTOR);
5867 return 1;
5868 }
5869
5870 /* Addr = segment_base + offset */
5871 /* offset = base + [index * scale] + displacement */
5872 *ret = vmx_get_segment_base(vcpu, seg_reg);
5873 if (base_is_valid)
5874 *ret += kvm_register_read(vcpu, base_reg);
5875 if (index_is_valid)
5876 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5877 *ret += exit_qualification; /* holds the displacement */
5878
5879 if (addr_size == 1) /* 32 bit */
5880 *ret &= 0xffffffff;
5881
5882 /*
5883 * TODO: throw #GP (and return 1) in various cases that the VM*
5884 * instructions require it - e.g., offset beyond segment limit,
5885 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5886 * address, and so on. Currently these are not checked.
5887 */
5888 return 0;
5889}
5890
27d6c865
NHE		 5891/* Emulate the VMCLEAR instruction */
5892static int handle_vmclear(struct kvm_vcpu *vcpu)
5893{
5894 struct vcpu_vmx *vmx = to_vmx(vcpu);
5895 gva_t gva;
5896 gpa_t vmptr;
5897 struct vmcs12 *vmcs12;
5898 struct page *page;
5899 struct x86_exception e;
5900
5901 if (!nested_vmx_check_permission(vcpu))
5902 return 1;
5903
5904 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5905 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5906 return 1;
5907
5908 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5909 sizeof(vmptr), &e)) {
5910 kvm_inject_page_fault(vcpu, &e);
5911 return 1;
5912 }
5913
5914 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5915 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5916 skip_emulated_instruction(vcpu);
5917 return 1;
5918 }
5919
5920 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5921 nested_release_vmcs12(vmx);
27d6c865
NHE		 5922 vmx->nested.current_vmptr = -1ull;
5923 vmx->nested.current_vmcs12 = NULL;
5924 }
5925
5926 page = nested_get_page(vcpu, vmptr);
5927 if (page == NULL) {
5928 /*
5929 * For accurate processor emulation, VMCLEAR beyond available
5930 * physical memory should do nothing at all. However, it is
5931 * possible that a nested vmx bug, not a guest hypervisor bug,
5932 * resulted in this case, so let's shut down before doing any
5933 * more damage:
5934 */
5935 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5936 return 1;
5937 }
5938 vmcs12 = kmap(page);
5939 vmcs12->launch_state = 0;
5940 kunmap(page);
5941 nested_release_page(page);
5942
5943 nested_free_vmcs02(vmx, vmptr);
5944
5945 skip_emulated_instruction(vcpu);
5946 nested_vmx_succeed(vcpu);
5947 return 1;
5948}
5949
cd232ad0
NHE		 5950static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5951
5952/* Emulate the VMLAUNCH instruction */
5953static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5954{
5955 return nested_vmx_run(vcpu, true);
5956}
5957
5958/* Emulate the VMRESUME instruction */
5959static int handle_vmresume(struct kvm_vcpu *vcpu)
5960{
5961
5962 return nested_vmx_run(vcpu, false);
5963}
5964
49f705c5
NHE		 5965enum vmcs_field_type {
5966 VMCS_FIELD_TYPE_U16 = 0,
5967 VMCS_FIELD_TYPE_U64 = 1,
5968 VMCS_FIELD_TYPE_U32 = 2,
5969 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5970};
5971
5972static inline int vmcs_field_type(unsigned long field)
5973{
5974 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5975 return VMCS_FIELD_TYPE_U32;
5976 return (field >> 13) & 0x3 ;
5977}
5978
5979static inline int vmcs_field_readonly(unsigned long field)
5980{
5981 return (((field >> 10) & 0x3) == 1);
5982}
5983
5984/*
5985 * Read a vmcs12 field. Since these can have varying lengths and we return
5986 * one type, we chose the biggest type (u64) and zero-extend the return value
5987 * to that size. Note that the caller, handle_vmread, might need to use only
5988 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5989 * 64-bit fields are to be returned).
5990 */
5991static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5992 unsigned long field, u64 *ret)
5993{
5994 short offset = vmcs_field_to_offset(field);
5995 char *p;
5996
5997 if (offset < 0)
5998 return 0;
5999
6000 p = ((char *)(get_vmcs12(vcpu))) + offset;
6001
6002 switch (vmcs_field_type(field)) {
6003 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6004 *ret = *((natural_width *)p);
6005 return 1;
6006 case VMCS_FIELD_TYPE_U16:
6007 *ret = *((u16 *)p);
6008 return 1;
6009 case VMCS_FIELD_TYPE_U32:
6010 *ret = *((u32 *)p);
6011 return 1;
6012 case VMCS_FIELD_TYPE_U64:
6013 *ret = *((u64 *)p);
6014 return 1;
6015 default:
6016 return 0; /* can never happen. */
6017 }
6018}
6019
20b97fea
AG		 6020
6021static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6022 unsigned long field, u64 field_value){
6023 short offset = vmcs_field_to_offset(field);
6024 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6025 if (offset < 0)
6026 return false;
6027
6028 switch (vmcs_field_type(field)) {
6029 case VMCS_FIELD_TYPE_U16:
6030 *(u16 *)p = field_value;
6031 return true;
6032 case VMCS_FIELD_TYPE_U32:
6033 *(u32 *)p = field_value;
6034 return true;
6035 case VMCS_FIELD_TYPE_U64:
6036 *(u64 *)p = field_value;
6037 return true;
6038 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6039 *(natural_width *)p = field_value;
6040 return true;
6041 default:
6042 return false; /* can never happen. */
6043 }
6044
6045}
6046
16f5b903
AG		 6047static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6048{
6049 int i;
6050 unsigned long field;
6051 u64 field_value;
6052 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6053 const unsigned long *fields = shadow_read_write_fields;
6054 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6055
6056 vmcs_load(shadow_vmcs);
6057
6058 for (i = 0; i < num_fields; i++) {
6059 field = fields[i];
6060 switch (vmcs_field_type(field)) {
6061 case VMCS_FIELD_TYPE_U16:
6062 field_value = vmcs_read16(field);
6063 break;
6064 case VMCS_FIELD_TYPE_U32:
6065 field_value = vmcs_read32(field);
6066 break;
6067 case VMCS_FIELD_TYPE_U64:
6068 field_value = vmcs_read64(field);
6069 break;
6070 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6071 field_value = vmcs_readl(field);
6072 break;
6073 }
6074 vmcs12_write_any(&vmx->vcpu, field, field_value);
6075 }
6076
6077 vmcs_clear(shadow_vmcs);
6078 vmcs_load(vmx->loaded_vmcs->vmcs);
6079}
6080
c3114420
AG		 6081static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6082{
c2bae893
MK		 6083 const unsigned long *fields[] = {
6084 shadow_read_write_fields,
6085 shadow_read_only_fields
c3114420 6086 };
c2bae893 6087 const int max_fields[] = {
c3114420
AG		 6088 max_shadow_read_write_fields,
6089 max_shadow_read_only_fields
6090 };
6091 int i, q;
6092 unsigned long field;
6093 u64 field_value = 0;
6094 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6095
6096 vmcs_load(shadow_vmcs);
6097
c2bae893 6098 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6099 for (i = 0; i < max_fields[q]; i++) {
6100 field = fields[q][i];
6101 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6102
6103 switch (vmcs_field_type(field)) {
6104 case VMCS_FIELD_TYPE_U16:
6105 vmcs_write16(field, (u16)field_value);
6106 break;
6107 case VMCS_FIELD_TYPE_U32:
6108 vmcs_write32(field, (u32)field_value);
6109 break;
6110 case VMCS_FIELD_TYPE_U64:
6111 vmcs_write64(field, (u64)field_value);
6112 break;
6113 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6114 vmcs_writel(field, (long)field_value);
6115 break;
6116 }
6117 }
6118 }
6119
6120 vmcs_clear(shadow_vmcs);
6121 vmcs_load(vmx->loaded_vmcs->vmcs);
6122}
6123
49f705c5
NHE		 6124/*
6125 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6126 * used before) all generate the same failure when it is missing.
6127 */
6128static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6129{
6130 struct vcpu_vmx *vmx = to_vmx(vcpu);
6131 if (vmx->nested.current_vmptr == -1ull) {
6132 nested_vmx_failInvalid(vcpu);
6133 skip_emulated_instruction(vcpu);
6134 return 0;
6135 }
6136 return 1;
6137}
6138
6139static int handle_vmread(struct kvm_vcpu *vcpu)
6140{
6141 unsigned long field;
6142 u64 field_value;
6143 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6144 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6145 gva_t gva = 0;
6146
6147 if (!nested_vmx_check_permission(vcpu) ||
6148 !nested_vmx_check_vmcs12(vcpu))
6149 return 1;
6150
6151 /* Decode instruction info and find the field to read */
6152 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6153 /* Read the field, zero-extended to a u64 field_value */
6154 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6155 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6156 skip_emulated_instruction(vcpu);
6157 return 1;
6158 }
6159 /*
6160 * Now copy part of this value to register or memory, as requested.
6161 * Note that the number of bits actually copied is 32 or 64 depending
6162 * on the guest's mode (32 or 64 bit), not on the given field's length.
6163 */
6164 if (vmx_instruction_info & (1u << 10)) {
6165 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6166 field_value);
6167 } else {
6168 if (get_vmx_mem_address(vcpu, exit_qualification,
6169 vmx_instruction_info, &gva))
6170 return 1;
6171 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6172 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6173 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6174 }
6175
6176 nested_vmx_succeed(vcpu);
6177 skip_emulated_instruction(vcpu);
6178 return 1;
6179}
6180
6181
6182static int handle_vmwrite(struct kvm_vcpu *vcpu)
6183{
6184 unsigned long field;
6185 gva_t gva;
6186 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6187 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6188 /* The value to write might be 32 or 64 bits, depending on L1's long
6189 * mode, and eventually we need to write that into a field of several
6190 * possible lengths. The code below first zero-extends the value to 64
6191 * bit (field_value), and then copies only the approriate number of
6192 * bits into the vmcs12 field.
6193 */
6194 u64 field_value = 0;
6195 struct x86_exception e;
6196
6197 if (!nested_vmx_check_permission(vcpu) ||
6198 !nested_vmx_check_vmcs12(vcpu))
6199 return 1;
6200
6201 if (vmx_instruction_info & (1u << 10))
6202 field_value = kvm_register_read(vcpu,
6203 (((vmx_instruction_info) >> 3) & 0xf));
6204 else {
6205 if (get_vmx_mem_address(vcpu, exit_qualification,
6206 vmx_instruction_info, &gva))
6207 return 1;
6208 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6209 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6210 kvm_inject_page_fault(vcpu, &e);
6211 return 1;
6212 }
6213 }
6214
6215
6216 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6217 if (vmcs_field_readonly(field)) {
6218 nested_vmx_failValid(vcpu,
6219 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6220 skip_emulated_instruction(vcpu);
6221 return 1;
6222 }
6223
20b97fea 6224 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6225 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6226 skip_emulated_instruction(vcpu);
6227 return 1;
6228 }
6229
6230 nested_vmx_succeed(vcpu);
6231 skip_emulated_instruction(vcpu);
6232 return 1;
6233}
6234
63846663
NHE		 6235/* Emulate the VMPTRLD instruction */
6236static int handle_vmptrld(struct kvm_vcpu *vcpu)
6237{
6238 struct vcpu_vmx *vmx = to_vmx(vcpu);
6239 gva_t gva;
6240 gpa_t vmptr;
6241 struct x86_exception e;
8a1b9dd0 6242 u32 exec_control;
63846663
NHE		 6243
6244 if (!nested_vmx_check_permission(vcpu))
6245 return 1;
6246
6247 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6248 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6249 return 1;
6250
6251 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6252 sizeof(vmptr), &e)) {
6253 kvm_inject_page_fault(vcpu, &e);
6254 return 1;
6255 }
6256
6257 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6258 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6259 skip_emulated_instruction(vcpu);
6260 return 1;
6261 }
6262
6263 if (vmx->nested.current_vmptr != vmptr) {
6264 struct vmcs12 *new_vmcs12;
6265 struct page *page;
6266 page = nested_get_page(vcpu, vmptr);
6267 if (page == NULL) {
6268 nested_vmx_failInvalid(vcpu);
6269 skip_emulated_instruction(vcpu);
6270 return 1;
6271 }
6272 new_vmcs12 = kmap(page);
6273 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6274 kunmap(page);
6275 nested_release_page_clean(page);
6276 nested_vmx_failValid(vcpu,
6277 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6278 skip_emulated_instruction(vcpu);
6279 return 1;
6280 }
e7953d7f
AG		 6281 if (vmx->nested.current_vmptr != -1ull)
6282 nested_release_vmcs12(vmx);
63846663
NHE		 6283
6284 vmx->nested.current_vmptr = vmptr;
6285 vmx->nested.current_vmcs12 = new_vmcs12;
6286 vmx->nested.current_vmcs12_page = page;
012f83cb 6287 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6288 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6289 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6290 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6291 vmcs_write64(VMCS_LINK_POINTER,
6292 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6293 vmx->nested.sync_shadow_vmcs = true;
6294 }
63846663
NHE		 6295 }
6296
6297 nested_vmx_succeed(vcpu);
6298 skip_emulated_instruction(vcpu);
6299 return 1;
6300}
6301
6a4d7550
NHE		 6302/* Emulate the VMPTRST instruction */
6303static int handle_vmptrst(struct kvm_vcpu *vcpu)
6304{
6305 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6306 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6307 gva_t vmcs_gva;
6308 struct x86_exception e;
6309
6310 if (!nested_vmx_check_permission(vcpu))
6311 return 1;
6312
6313 if (get_vmx_mem_address(vcpu, exit_qualification,
6314 vmx_instruction_info, &vmcs_gva))
6315 return 1;
6316 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6317 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6318 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6319 sizeof(u64), &e)) {
6320 kvm_inject_page_fault(vcpu, &e);
6321 return 1;
6322 }
6323 nested_vmx_succeed(vcpu);
6324 skip_emulated_instruction(vcpu);
6325 return 1;
6326}
6327
bfd0a56b
NHE		 6328/* Emulate the INVEPT instruction */
6329static int handle_invept(struct kvm_vcpu *vcpu)
6330{
6331 u32 vmx_instruction_info, types;
6332 unsigned long type;
6333 gva_t gva;
6334 struct x86_exception e;
6335 struct {
6336 u64 eptp, gpa;
6337 } operand;
6338 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6339
6340 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6341 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6342 kvm_queue_exception(vcpu, UD_VECTOR);
6343 return 1;
6344 }
6345
6346 if (!nested_vmx_check_permission(vcpu))
6347 return 1;
6348
6349 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6350 kvm_queue_exception(vcpu, UD_VECTOR);
6351 return 1;
6352 }
6353
6354 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6355 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6356
6357 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6358
6359 if (!(types & (1UL << type))) {
6360 nested_vmx_failValid(vcpu,
6361 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6362 return 1;
6363 }
6364
6365 /* According to the Intel VMX instruction reference, the memory
6366 * operand is read even if it isn't needed (e.g., for type==global)
6367 */
6368 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6369 vmx_instruction_info, &gva))
6370 return 1;
6371 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6372 sizeof(operand), &e)) {
6373 kvm_inject_page_fault(vcpu, &e);
6374 return 1;
6375 }
6376
6377 switch (type) {
6378 case VMX_EPT_EXTENT_CONTEXT:
6379 if ((operand.eptp & eptp_mask) !=
6380 (nested_ept_get_cr3(vcpu) & eptp_mask))
6381 break;
6382 case VMX_EPT_EXTENT_GLOBAL:
6383 kvm_mmu_sync_roots(vcpu);
6384 kvm_mmu_flush_tlb(vcpu);
6385 nested_vmx_succeed(vcpu);
6386 break;
6387 default:
6388 BUG_ON(1);
6389 break;
6390 }
6391
6392 skip_emulated_instruction(vcpu);
6393 return 1;
6394}
6395
6aa8b732
AK		 6396/*
6397 * The exit handlers return 1 if the exit was handled fully and guest execution
6398 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6399 * to be done to userspace and return 0.
6400 */
772e0318 6401static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6402 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6403 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6404 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6405 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6406 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6407 [EXIT_REASON_CR_ACCESS] = handle_cr,
6408 [EXIT_REASON_DR_ACCESS] = handle_dr,
6409 [EXIT_REASON_CPUID] = handle_cpuid,
6410 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6411 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6412 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6413 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6414 [EXIT_REASON_INVD] = handle_invd,
a7052897 6415 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6416 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6417 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6418 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6419 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6420 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6421 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6422 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6423 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6424 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6425 [EXIT_REASON_VMOFF] = handle_vmoff,
6426 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6427 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6428 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6429 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6430 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6431 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6432 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6433 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6434 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6435 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6436 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6437 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6438 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6439 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6440 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6441};
6442
6443static const int kvm_vmx_max_exit_handlers =
50a3485c 6444 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6445
908a7bdd
JK		 6446static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6447 struct vmcs12 *vmcs12)
6448{
6449 unsigned long exit_qualification;
6450 gpa_t bitmap, last_bitmap;
6451 unsigned int port;
6452 int size;
6453 u8 b;
6454
6455 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6456 return 1;
6457
6458 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6459 return 0;
6460
6461 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6462
6463 port = exit_qualification >> 16;
6464 size = (exit_qualification & 7) + 1;
6465
6466 last_bitmap = (gpa_t)-1;
6467 b = -1;
6468
6469 while (size > 0) {
6470 if (port < 0x8000)
6471 bitmap = vmcs12->io_bitmap_a;
6472 else if (port < 0x10000)
6473 bitmap = vmcs12->io_bitmap_b;
6474 else
6475 return 1;
6476 bitmap += (port & 0x7fff) / 8;
6477
6478 if (last_bitmap != bitmap)
6479 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6480 return 1;
6481 if (b & (1 << (port & 7)))
6482 return 1;
6483
6484 port++;
6485 size--;
6486 last_bitmap = bitmap;
6487 }
6488
6489 return 0;
6490}
6491
644d711a
NHE		 6492/*
6493 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6494 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6495 * disinterest in the current event (read or write a specific MSR) by using an
6496 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6497 */
6498static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6499 struct vmcs12 *vmcs12, u32 exit_reason)
6500{
6501 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6502 gpa_t bitmap;
6503
cbd29cb6 6504 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6505 return 1;
6506
6507 /*
6508 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6509 * for the four combinations of read/write and low/high MSR numbers.
6510 * First we need to figure out which of the four to use:
6511 */
6512 bitmap = vmcs12->msr_bitmap;
6513 if (exit_reason == EXIT_REASON_MSR_WRITE)
6514 bitmap += 2048;
6515 if (msr_index >= 0xc0000000) {
6516 msr_index -= 0xc0000000;
6517 bitmap += 1024;
6518 }
6519
6520 /* Then read the msr_index'th bit from this bitmap: */
6521 if (msr_index < 1024*8) {
6522 unsigned char b;
bd31a7f5
JK		 6523 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6524 return 1;
644d711a
NHE		 6525 return 1 & (b >> (msr_index & 7));
6526 } else
6527 return 1; /* let L1 handle the wrong parameter */
6528}
6529
6530/*
6531 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6532 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6533 * intercept (via guest_host_mask etc.) the current event.
6534 */
6535static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6536 struct vmcs12 *vmcs12)
6537{
6538 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6539 int cr = exit_qualification & 15;
6540 int reg = (exit_qualification >> 8) & 15;
6541 unsigned long val = kvm_register_read(vcpu, reg);
6542
6543 switch ((exit_qualification >> 4) & 3) {
6544 case 0: /* mov to cr */
6545 switch (cr) {
6546 case 0:
6547 if (vmcs12->cr0_guest_host_mask &
6548 (val ^ vmcs12->cr0_read_shadow))
6549 return 1;
6550 break;
6551 case 3:
6552 if ((vmcs12->cr3_target_count >= 1 &&
6553 vmcs12->cr3_target_value0 == val) ||
6554 (vmcs12->cr3_target_count >= 2 &&
6555 vmcs12->cr3_target_value1 == val) ||
6556 (vmcs12->cr3_target_count >= 3 &&
6557 vmcs12->cr3_target_value2 == val) ||
6558 (vmcs12->cr3_target_count >= 4 &&
6559 vmcs12->cr3_target_value3 == val))
6560 return 0;
6561 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6562 return 1;
6563 break;
6564 case 4:
6565 if (vmcs12->cr4_guest_host_mask &
6566 (vmcs12->cr4_read_shadow ^ val))
6567 return 1;
6568 break;
6569 case 8:
6570 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6571 return 1;
6572 break;
6573 }
6574 break;
6575 case 2: /* clts */
6576 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6577 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6578 return 1;
6579 break;
6580 case 1: /* mov from cr */
6581 switch (cr) {
6582 case 3:
6583 if (vmcs12->cpu_based_vm_exec_control &
6584 CPU_BASED_CR3_STORE_EXITING)
6585 return 1;
6586 break;
6587 case 8:
6588 if (vmcs12->cpu_based_vm_exec_control &
6589 CPU_BASED_CR8_STORE_EXITING)
6590 return 1;
6591 break;
6592 }
6593 break;
6594 case 3: /* lmsw */
6595 /*
6596 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6597 * cr0. Other attempted changes are ignored, with no exit.
6598 */
6599 if (vmcs12->cr0_guest_host_mask & 0xe &
6600 (val ^ vmcs12->cr0_read_shadow))
6601 return 1;
6602 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6603 !(vmcs12->cr0_read_shadow & 0x1) &&
6604 (val & 0x1))
6605 return 1;
6606 break;
6607 }
6608 return 0;
6609}
6610
6611/*
6612 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6613 * should handle it ourselves in L0 (and then continue L2). Only call this
6614 * when in is_guest_mode (L2).
6615 */
6616static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6617{
644d711a
NHE		 6618 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6619 struct vcpu_vmx *vmx = to_vmx(vcpu);
6620 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6621 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6622
6623 if (vmx->nested.nested_run_pending)
6624 return 0;
6625
6626 if (unlikely(vmx->fail)) {
bd80158a
JK		 6627 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6628 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6629 return 1;
6630 }
6631
6632 switch (exit_reason) {
6633 case EXIT_REASON_EXCEPTION_NMI:
6634 if (!is_exception(intr_info))
6635 return 0;
6636 else if (is_page_fault(intr_info))
6637 return enable_ept;
6638 return vmcs12->exception_bitmap &
6639 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6640 case EXIT_REASON_EXTERNAL_INTERRUPT:
6641 return 0;
6642 case EXIT_REASON_TRIPLE_FAULT:
6643 return 1;
6644 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6645 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6646 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6647 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6648 case EXIT_REASON_TASK_SWITCH:
6649 return 1;
6650 case EXIT_REASON_CPUID:
6651 return 1;
6652 case EXIT_REASON_HLT:
6653 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6654 case EXIT_REASON_INVD:
6655 return 1;
6656 case EXIT_REASON_INVLPG:
6657 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6658 case EXIT_REASON_RDPMC:
6659 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6660 case EXIT_REASON_RDTSC:
6661 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6662 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6663 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6664 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6665 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6666 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6667 case EXIT_REASON_INVEPT:
644d711a
NHE		 6668 /*
6669 * VMX instructions trap unconditionally. This allows L1 to
6670 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6671 */
6672 return 1;
6673 case EXIT_REASON_CR_ACCESS:
6674 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6675 case EXIT_REASON_DR_ACCESS:
6676 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6677 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6678 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6679 case EXIT_REASON_MSR_READ:
6680 case EXIT_REASON_MSR_WRITE:
6681 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6682 case EXIT_REASON_INVALID_STATE:
6683 return 1;
6684 case EXIT_REASON_MWAIT_INSTRUCTION:
6685 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6686 case EXIT_REASON_MONITOR_INSTRUCTION:
6687 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6688 case EXIT_REASON_PAUSE_INSTRUCTION:
6689 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6690 nested_cpu_has2(vmcs12,
6691 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6692 case EXIT_REASON_MCE_DURING_VMENTRY:
6693 return 0;
6694 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6695 return 1;
6696 case EXIT_REASON_APIC_ACCESS:
6697 return nested_cpu_has2(vmcs12,
6698 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6699 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6700 /*
6701 * L0 always deals with the EPT violation. If nested EPT is
6702 * used, and the nested mmu code discovers that the address is
6703 * missing in the guest EPT table (EPT12), the EPT violation
6704 * will be injected with nested_ept_inject_page_fault()
6705 */
6706 return 0;
644d711a 6707 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6708 /*
6709 * L2 never uses directly L1's EPT, but rather L0's own EPT
6710 * table (shadow on EPT) or a merged EPT table that L0 built
6711 * (EPT on EPT). So any problems with the structure of the
6712 * table is L0's fault.
6713 */
644d711a 6714 return 0;
0238ea91
JK		 6715 case EXIT_REASON_PREEMPTION_TIMER:
6716 return vmcs12->pin_based_vm_exec_control &
6717 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6718 case EXIT_REASON_WBINVD:
6719 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6720 case EXIT_REASON_XSETBV:
6721 return 1;
6722 default:
6723 return 1;
6724 }
6725}
6726
586f9607
AK		 6727static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6728{
6729 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6730 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6731}
6732
7854cbca
ACL		 6733static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6734{
6735 u64 delta_tsc_l1;
6736 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6737
6738 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6739 PIN_BASED_VMX_PREEMPTION_TIMER))
6740 return;
6741 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6742 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6743 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6744 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6745 - vcpu->arch.last_guest_tsc;
6746 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6747 if (preempt_val_l2 <= preempt_val_l1)
6748 preempt_val_l2 = 0;
6749 else
6750 preempt_val_l2 -= preempt_val_l1;
6751 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6752}
6753
6aa8b732
AK		 6754/*
6755 * The guest has exited. See if we can fix it or if we need userspace
6756 * assistance.
6757 */
851ba692 6758static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6759{
29bd8a78 6760 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6761 u32 exit_reason = vmx->exit_reason;
1155f76a 6762 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6763
80ced186 6764 /* If guest state is invalid, start emulating */
14168786 6765 if (vmx->emulation_required)
80ced186 6766 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6767
644d711a
NHE		 6768 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6769 nested_vmx_vmexit(vcpu);
6770 return 1;
6771 }
6772
5120702e
MG		 6773 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6774 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6775 vcpu->run->fail_entry.hardware_entry_failure_reason
6776 = exit_reason;
6777 return 0;
6778 }
6779
29bd8a78 6780 if (unlikely(vmx->fail)) {
851ba692
AK		 6781 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6782 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6783 = vmcs_read32(VM_INSTRUCTION_ERROR);
6784 return 0;
6785 }
6aa8b732 6786
b9bf6882
XG		 6787 /*
6788 * Note:
6789 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6790 * delivery event since it indicates guest is accessing MMIO.
6791 * The vm-exit can be triggered again after return to guest that
6792 * will cause infinite loop.
6793 */
d77c26fc 6794 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6795 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6796 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6797 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6798 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6799 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6800 vcpu->run->internal.ndata = 2;
6801 vcpu->run->internal.data[0] = vectoring_info;
6802 vcpu->run->internal.data[1] = exit_reason;
6803 return 0;
6804 }
3b86cd99 6805
644d711a
NHE		 6806 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6807 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6808 get_vmcs12(vcpu))))) {
c4282df9 6809 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6810 vmx->soft_vnmi_blocked = 0;
3b86cd99 6811 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6812 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6813 /*
6814 * This CPU don't support us in finding the end of an
6815 * NMI-blocked window if the guest runs with IRQs
6816 * disabled. So we pull the trigger after 1 s of
6817 * futile waiting, but inform the user about this.
6818 */
6819 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6820 "state on VCPU %d after 1 s timeout\n",
6821 __func__, vcpu->vcpu_id);
6822 vmx->soft_vnmi_blocked = 0;
3b86cd99 6823 }
3b86cd99
JK		 6824 }
6825
6aa8b732
AK		 6826 if (exit_reason < kvm_vmx_max_exit_handlers
6827 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6828 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6829 else {
851ba692
AK		 6830 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6831 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6832 }
6833 return 0;
6834}
6835
95ba8273 6836static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6837{
95ba8273 6838 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6839 vmcs_write32(TPR_THRESHOLD, 0);
6840 return;
6841 }
6842
95ba8273 6843 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6844}
6845
8d14695f
YZ		 6846static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6847{
6848 u32 sec_exec_control;
6849
6850 /*
6851 * There is not point to enable virtualize x2apic without enable
6852 * apicv
6853 */
c7c9c56c
YZ		 6854 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6855 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6856 return;
6857
6858 if (!vm_need_tpr_shadow(vcpu->kvm))
6859 return;
6860
6861 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6862
6863 if (set) {
6864 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6865 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6866 } else {
6867 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6868 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6869 }
6870 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6871
6872 vmx_set_msr_bitmap(vcpu);
6873}
6874
c7c9c56c
YZ		 6875static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6876{
6877 u16 status;
6878 u8 old;
6879
6880 if (!vmx_vm_has_apicv(kvm))
6881 return;
6882
6883 if (isr == -1)
6884 isr = 0;
6885
6886 status = vmcs_read16(GUEST_INTR_STATUS);
6887 old = status >> 8;
6888 if (isr != old) {
6889 status &= 0xff;
6890 status |= isr << 8;
6891 vmcs_write16(GUEST_INTR_STATUS, status);
6892 }
6893}
6894
6895static void vmx_set_rvi(int vector)
6896{
6897 u16 status;
6898 u8 old;
6899
6900 status = vmcs_read16(GUEST_INTR_STATUS);
6901 old = (u8)status & 0xff;
6902 if ((u8)vector != old) {
6903 status &= ~0xff;
6904 status |= (u8)vector;
6905 vmcs_write16(GUEST_INTR_STATUS, status);
6906 }
6907}
6908
6909static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6910{
6911 if (max_irr == -1)
6912 return;
6913
6914 vmx_set_rvi(max_irr);
6915}
6916
6917static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6918{
3d81bc7e
YZ		 6919 if (!vmx_vm_has_apicv(vcpu->kvm))
6920 return;
6921
c7c9c56c
YZ		 6922 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6923 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6924 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6925 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6926}
6927
51aa01d1 6928static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6929{
00eba012
AK		 6930 u32 exit_intr_info;
6931
6932 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6933 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6934 return;
6935
c5ca8e57 6936 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6937 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6938
6939 /* Handle machine checks before interrupts are enabled */
00eba012 6940 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6941 kvm_machine_check();
6942
20f65983 6943 /* We need to handle NMIs before interrupts are enabled */
00eba012 6944 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6945 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6946 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6947 asm("int $2");
ff9d07a0
ZY		 6948 kvm_after_handle_nmi(&vmx->vcpu);
6949 }
51aa01d1 6950}
20f65983 6951
a547c6db
YZ		 6952static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6953{
6954 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6955
6956 /*
6957 * If external interrupt exists, IF bit is set in rflags/eflags on the
6958 * interrupt stack frame, and interrupt will be enabled on a return
6959 * from interrupt handler.
6960 */
6961 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6962 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6963 unsigned int vector;
6964 unsigned long entry;
6965 gate_desc *desc;
6966 struct vcpu_vmx *vmx = to_vmx(vcpu);
6967#ifdef CONFIG_X86_64
6968 unsigned long tmp;
6969#endif
6970
6971 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6972 desc = (gate_desc *)vmx->host_idt_base + vector;
6973 entry = gate_offset(*desc);
6974 asm volatile(
6975#ifdef CONFIG_X86_64
6976 "mov %%" _ASM_SP ", %[sp]\n\t"
6977 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6978 "push $%c[ss]\n\t"
6979 "push %[sp]\n\t"
6980#endif
6981 "pushf\n\t"
6982 "orl $0x200, (%%" _ASM_SP ")\n\t"
6983 __ASM_SIZE(push) " $%c[cs]\n\t"
6984 "call *%[entry]\n\t"
6985 :
6986#ifdef CONFIG_X86_64
6987 [sp]"=&r"(tmp)
6988#endif
6989 :
6990 [entry]"r"(entry),
6991 [ss]"i"(__KERNEL_DS),
6992 [cs]"i"(__KERNEL_CS)
6993 );
6994 } else
6995 local_irq_enable();
6996}
6997
51aa01d1
AK		 6998static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6999{
c5ca8e57 7000 u32 exit_intr_info;
51aa01d1
AK		 7001 bool unblock_nmi;
7002 u8 vector;
7003 bool idtv_info_valid;
7004
7005 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7006
cf393f75 7007 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7008 if (vmx->nmi_known_unmasked)
7009 return;
c5ca8e57
AK		 7010 /*
7011 * Can't use vmx->exit_intr_info since we're not sure what
7012 * the exit reason is.
7013 */
7014 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7015 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7016 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7017 /*
7b4a25cb 7018 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7019 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7020 * a guest IRET fault.
7b4a25cb
GN		 7021 * SDM 3: 23.2.2 (September 2008)
7022 * Bit 12 is undefined in any of the following cases:
7023 * If the VM exit sets the valid bit in the IDT-vectoring
7024 * information field.
7025 * If the VM exit is due to a double fault.
cf393f75 7026 */
7b4a25cb
GN		 7027 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7028 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7029 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7030 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7031 else
7032 vmx->nmi_known_unmasked =
7033 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7034 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7035 } else if (unlikely(vmx->soft_vnmi_blocked))
7036 vmx->vnmi_blocked_time +=
7037 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7038}
7039
3ab66e8a 7040static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7041 u32 idt_vectoring_info,
7042 int instr_len_field,
7043 int error_code_field)
51aa01d1 7044{
51aa01d1
AK		 7045 u8 vector;
7046 int type;
7047 bool idtv_info_valid;
7048
7049 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7050
3ab66e8a
JK		 7051 vcpu->arch.nmi_injected = false;
7052 kvm_clear_exception_queue(vcpu);
7053 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7054
7055 if (!idtv_info_valid)
7056 return;
7057
3ab66e8a 7058 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7059
668f612f
AK		 7060 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7061 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7062
64a7ec06 7063 switch (type) {
37b96e98 7064 case INTR_TYPE_NMI_INTR:
3ab66e8a 7065 vcpu->arch.nmi_injected = true;
668f612f 7066 /*
7b4a25cb 7067 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7068 * Clear bit "block by NMI" before VM entry if a NMI
7069 * delivery faulted.
668f612f 7070 */
3ab66e8a 7071 vmx_set_nmi_mask(vcpu, false);
37b96e98 7072 break;
37b96e98 7073 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7074 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7075 /* fall through */
7076 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7077 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7078 u32 err = vmcs_read32(error_code_field);
851eb667 7079 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7080 } else
851eb667 7081 kvm_requeue_exception(vcpu, vector);
37b96e98 7082 break;
66fd3f7f 7083 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7084 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7085 /* fall through */
37b96e98 7086 case INTR_TYPE_EXT_INTR:
3ab66e8a 7087 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7088 break;
7089 default:
7090 break;
f7d9238f 7091 }
cf393f75
AK		 7092}
7093
83422e17
AK		 7094static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7095{
3ab66e8a 7096 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7097 VM_EXIT_INSTRUCTION_LEN,
7098 IDT_VECTORING_ERROR_CODE);
7099}
7100
b463a6f7
AK		 7101static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7102{
3ab66e8a 7103 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7104 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7105 VM_ENTRY_INSTRUCTION_LEN,
7106 VM_ENTRY_EXCEPTION_ERROR_CODE);
7107
7108 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7109}
7110
d7cd9796
GN		 7111static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7112{
7113 int i, nr_msrs;
7114 struct perf_guest_switch_msr *msrs;
7115
7116 msrs = perf_guest_get_msrs(&nr_msrs);
7117
7118 if (!msrs)
7119 return;
7120
7121 for (i = 0; i < nr_msrs; i++)
7122 if (msrs[i].host == msrs[i].guest)
7123 clear_atomic_switch_msr(vmx, msrs[i].msr);
7124 else
7125 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7126 msrs[i].host);
7127}
7128
a3b5ba49 7129static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7130{
a2fa3e9f 7131 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7132 unsigned long debugctlmsr;
104f226b
AK		 7133
7134 /* Record the guest's net vcpu time for enforced NMI injections. */
7135 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7136 vmx->entry_time = ktime_get();
7137
7138 /* Don't enter VMX if guest state is invalid, let the exit handler
7139 start emulation until we arrive back to a valid state */
14168786 7140 if (vmx->emulation_required)
104f226b
AK		 7141 return;
7142
012f83cb
AG		 7143 if (vmx->nested.sync_shadow_vmcs) {
7144 copy_vmcs12_to_shadow(vmx);
7145 vmx->nested.sync_shadow_vmcs = false;
7146 }
7147
104f226b
AK		 7148 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7149 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7150 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7151 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7152
7153 /* When single-stepping over STI and MOV SS, we must clear the
7154 * corresponding interruptibility bits in the guest state. Otherwise
7155 * vmentry fails as it then expects bit 14 (BS) in pending debug
7156 * exceptions being set, but that's not correct for the guest debugging
7157 * case. */
7158 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7159 vmx_set_interrupt_shadow(vcpu, 0);
7160
d7cd9796 7161 atomic_switch_perf_msrs(vmx);
2a7921b7 7162 debugctlmsr = get_debugctlmsr();
d7cd9796 7163
7854cbca
ACL		 7164 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7165 nested_adjust_preemption_timer(vcpu);
d462b819 7166 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7167 asm(
6aa8b732 7168 /* Store host registers */
b188c81f
AK		 7169 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7170 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7171 "push %%" _ASM_CX " \n\t"
7172 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7173 "je 1f \n\t"
b188c81f 7174 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7175 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7176 "1: \n\t"
d3edefc0 7177 /* Reload cr2 if changed */
b188c81f
AK		 7178 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7179 "mov %%cr2, %%" _ASM_DX " \n\t"
7180 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7181 "je 2f \n\t"
b188c81f 7182 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7183 "2: \n\t"
6aa8b732 7184 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7185 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7186 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7187 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7188 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7189 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7190 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7191 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7192 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7193#ifdef CONFIG_X86_64
e08aa78a
AK		 7194 "mov %c[r8](%0), %%r8 \n\t"
7195 "mov %c[r9](%0), %%r9 \n\t"
7196 "mov %c[r10](%0), %%r10 \n\t"
7197 "mov %c[r11](%0), %%r11 \n\t"
7198 "mov %c[r12](%0), %%r12 \n\t"
7199 "mov %c[r13](%0), %%r13 \n\t"
7200 "mov %c[r14](%0), %%r14 \n\t"
7201 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7202#endif
b188c81f 7203 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7204
6aa8b732 7205 /* Enter guest mode */
83287ea4 7206 "jne 1f \n\t"
4ecac3fd 7207 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7208 "jmp 2f \n\t"
7209 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7210 "2: "
6aa8b732 7211 /* Save guest registers, load host registers, keep flags */
b188c81f 7212 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7213 "pop %0 \n\t"
b188c81f
AK		 7214 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7215 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7216 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7217 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7218 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7219 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7220 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7221#ifdef CONFIG_X86_64
e08aa78a
AK		 7222 "mov %%r8, %c[r8](%0) \n\t"
7223 "mov %%r9, %c[r9](%0) \n\t"
7224 "mov %%r10, %c[r10](%0) \n\t"
7225 "mov %%r11, %c[r11](%0) \n\t"
7226 "mov %%r12, %c[r12](%0) \n\t"
7227 "mov %%r13, %c[r13](%0) \n\t"
7228 "mov %%r14, %c[r14](%0) \n\t"
7229 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7230#endif
b188c81f
AK		 7231 "mov %%cr2, %%" _ASM_AX " \n\t"
7232 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7233
b188c81f 7234 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7235 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7236 ".pushsection .rodata \n\t"
7237 ".global vmx_return \n\t"
7238 "vmx_return: " _ASM_PTR " 2b \n\t"
7239 ".popsection"
e08aa78a 7240 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7241 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7242 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7243 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7244 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7245 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7246 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7247 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7248 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7249 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7250 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7251#ifdef CONFIG_X86_64
ad312c7c
ZX		 7252 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7253 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7254 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7255 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7256 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7257 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7258 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7259 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7260#endif
40712fae
AK		 7261 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7262 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7263 : "cc", "memory"
7264#ifdef CONFIG_X86_64
b188c81f 7265 , "rax", "rbx", "rdi", "rsi"
c2036300 7266 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7267#else
7268 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7269#endif
7270 );
6aa8b732 7271
2a7921b7
GN		 7272 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7273 if (debugctlmsr)
7274 update_debugctlmsr(debugctlmsr);
7275
aa67f609
AK		 7276#ifndef CONFIG_X86_64
7277 /*
7278 * The sysexit path does not restore ds/es, so we must set them to
7279 * a reasonable value ourselves.
7280 *
7281 * We can't defer this to vmx_load_host_state() since that function
7282 * may be executed in interrupt context, which saves and restore segments
7283 * around it, nullifying its effect.
7284 */
7285 loadsegment(ds, __USER_DS);
7286 loadsegment(es, __USER_DS);
7287#endif
7288
6de4f3ad 7289 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7290 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7291 | (1 << VCPU_EXREG_CPL)
aff48baa 7292 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7293 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7294 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7295 vcpu->arch.regs_dirty = 0;
7296
1155f76a
AK		 7297 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7298
d462b819 7299 vmx->loaded_vmcs->launched = 1;
1b6269db 7300
51aa01d1 7301 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7302 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7303
e0b890d3
GN		 7304 /*
7305 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7306 * we did not inject a still-pending event to L1 now because of
7307 * nested_run_pending, we need to re-enable this bit.
7308 */
7309 if (vmx->nested.nested_run_pending)
7310 kvm_make_request(KVM_REQ_EVENT, vcpu);
7311
7312 vmx->nested.nested_run_pending = 0;
7313
51aa01d1
AK		 7314 vmx_complete_atomic_exit(vmx);
7315 vmx_recover_nmi_blocking(vmx);
cf393f75 7316 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7317}
7318
6aa8b732
AK		 7319static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7320{
fb3f0f51
RR		 7321 struct vcpu_vmx *vmx = to_vmx(vcpu);
7322
cdbecfc3 7323 free_vpid(vmx);
ec378aee 7324 free_nested(vmx);
d462b819 7325 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7326 kfree(vmx->guest_msrs);
7327 kvm_vcpu_uninit(vcpu);
a4770347 7328 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7329}
7330
fb3f0f51 7331static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7332{
fb3f0f51 7333 int err;
c16f862d 7334 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7335 int cpu;
6aa8b732 7336
a2fa3e9f 7337 if (!vmx)
fb3f0f51
RR		 7338 return ERR_PTR(-ENOMEM);
7339
2384d2b3
SY		 7340 allocate_vpid(vmx);
7341
fb3f0f51
RR		 7342 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7343 if (err)
7344 goto free_vcpu;
965b58a5 7345
a2fa3e9f 7346 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7347 err = -ENOMEM;
fb3f0f51 7348 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7349 goto uninit_vcpu;
7350 }
965b58a5 7351
d462b819
NHE		 7352 vmx->loaded_vmcs = &vmx->vmcs01;
7353 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7354 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7355 goto free_msrs;
d462b819
NHE		 7356 if (!vmm_exclusive)
7357 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7358 loaded_vmcs_init(vmx->loaded_vmcs);
7359 if (!vmm_exclusive)
7360 kvm_cpu_vmxoff();
a2fa3e9f 7361
15ad7146
AK		 7362 cpu = get_cpu();
7363 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7364 vmx->vcpu.cpu = cpu;
8b9cf98c 7365 err = vmx_vcpu_setup(vmx);
fb3f0f51 7366 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7367 put_cpu();
fb3f0f51
RR		 7368 if (err)
7369 goto free_vmcs;
a63cb560 7370 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7371 err = alloc_apic_access_page(kvm);
7372 if (err)
5e4a0b3c 7373 goto free_vmcs;
a63cb560 7374 }
fb3f0f51 7375
b927a3ce
SY		 7376 if (enable_ept) {
7377 if (!kvm->arch.ept_identity_map_addr)
7378 kvm->arch.ept_identity_map_addr =
7379 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7380 err = -ENOMEM;
b7ebfb05
SY		 7381 if (alloc_identity_pagetable(kvm) != 0)
7382 goto free_vmcs;
93ea5388
GN		 7383 if (!init_rmode_identity_map(kvm))
7384 goto free_vmcs;
b927a3ce 7385 }
b7ebfb05 7386
a9d30f33
NHE		 7387 vmx->nested.current_vmptr = -1ull;
7388 vmx->nested.current_vmcs12 = NULL;
7389
fb3f0f51
RR		 7390 return &vmx->vcpu;
7391
7392free_vmcs:
5f3fbc34 7393 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7394free_msrs:
fb3f0f51
RR		 7395 kfree(vmx->guest_msrs);
7396uninit_vcpu:
7397 kvm_vcpu_uninit(&vmx->vcpu);
7398free_vcpu:
cdbecfc3 7399 free_vpid(vmx);
a4770347 7400 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7401 return ERR_PTR(err);
6aa8b732
AK		 7402}
7403
002c7f7c
YS		 7404static void __init vmx_check_processor_compat(void *rtn)
7405{
7406 struct vmcs_config vmcs_conf;
7407
7408 *(int *)rtn = 0;
7409 if (setup_vmcs_config(&vmcs_conf) < 0)
7410 *(int *)rtn = -EIO;
7411 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7412 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7413 smp_processor_id());
7414 *(int *)rtn = -EIO;
7415 }
7416}
7417
67253af5
SY		 7418static int get_ept_level(void)
7419{
7420 return VMX_EPT_DEFAULT_GAW + 1;
7421}
7422
4b12f0de 7423static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7424{
4b12f0de
SY		 7425 u64 ret;
7426
522c68c4
SY		 7427 /* For VT-d and EPT combination
7428 * 1. MMIO: always map as UC
7429 * 2. EPT with VT-d:
7430 * a. VT-d without snooping control feature: can't guarantee the
7431 * result, try to trust guest.
7432 * b. VT-d with snooping control feature: snooping control feature of
7433 * VT-d engine can guarantee the cache correctness. Just set it
7434 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7435 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7436 * consistent with host MTRR
7437 */
4b12f0de
SY		 7438 if (is_mmio)
7439 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7440 else if (vcpu->kvm->arch.iommu_domain &&
7441 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7442 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7443 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7444 else
522c68c4 7445 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7446 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7447
7448 return ret;
64d4d521
SY		 7449}
7450
17cc3935 7451static int vmx_get_lpage_level(void)
344f414f 7452{
878403b7
SY		 7453 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7454 return PT_DIRECTORY_LEVEL;
7455 else
7456 /* For shadow and EPT supported 1GB page */
7457 return PT_PDPE_LEVEL;
344f414f
JR		 7458}
7459
0e851880
SY		 7460static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7461{
4e47c7a6
SY		 7462 struct kvm_cpuid_entry2 *best;
7463 struct vcpu_vmx *vmx = to_vmx(vcpu);
7464 u32 exec_control;
7465
7466 vmx->rdtscp_enabled = false;
7467 if (vmx_rdtscp_supported()) {
7468 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7469 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7470 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7471 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7472 vmx->rdtscp_enabled = true;
7473 else {
7474 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7475 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7476 exec_control);
7477 }
7478 }
7479 }
ad756a16 7480
ad756a16
MJ		 7481 /* Exposing INVPCID only when PCID is exposed */
7482 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7483 if (vmx_invpcid_supported() &&
4f977045 7484 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7485 guest_cpuid_has_pcid(vcpu)) {
29282fde 7486 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7487 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7488 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7489 exec_control);
7490 } else {
29282fde
TI		 7491 if (cpu_has_secondary_exec_ctrls()) {
7492 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7493 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7494 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7495 exec_control);
7496 }
ad756a16 7497 if (best)
4f977045 7498 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7499 }
0e851880
SY		 7500}
7501
d4330ef2
JR		 7502static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7503{
7b8050f5
NHE		 7504 if (func == 1 && nested)
7505 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7506}
7507
25d92081
YZ		 7508static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7509 struct x86_exception *fault)
7510{
7511 struct vmcs12 *vmcs12;
7512 nested_vmx_vmexit(vcpu);
7513 vmcs12 = get_vmcs12(vcpu);
7514
7515 if (fault->error_code & PFERR_RSVD_MASK)
7516 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7517 else
7518 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7519 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7520 vmcs12->guest_physical_address = fault->address;
7521}
7522
155a97a3
NHE		 7523/* Callbacks for nested_ept_init_mmu_context: */
7524
7525static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7526{
7527 /* return the page table to be shadowed - in our case, EPT12 */
7528 return get_vmcs12(vcpu)->ept_pointer;
7529}
7530
8a3c1a33 7531static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7532{
8a3c1a33 7533 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7534 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7535
7536 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7537 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7538 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7539
7540 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7541}
7542
7543static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7544{
7545 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7546}
7547
feaf0c7d
GN		 7548static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7549 struct x86_exception *fault)
7550{
7551 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7552
7553 WARN_ON(!is_guest_mode(vcpu));
7554
7555 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7556 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7557 nested_vmx_vmexit(vcpu);
7558 else
7559 kvm_inject_page_fault(vcpu, fault);
7560}
7561
fe3ef05c
NHE		 7562/*
7563 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7564 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7565 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7566 * guest in a way that will both be appropriate to L1's requests, and our
7567 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7568 * function also has additional necessary side-effects, like setting various
7569 * vcpu->arch fields.
7570 */
7571static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7572{
7573 struct vcpu_vmx *vmx = to_vmx(vcpu);
7574 u32 exec_control;
7854cbca 7575 u32 exit_control;
fe3ef05c
NHE		 7576
7577 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7578 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7579 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7580 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7581 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7582 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7583 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7584 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7585 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7586 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7587 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7588 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7589 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7590 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7591 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7592 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7593 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7594 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7595 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7596 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7597 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7598 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7599 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7600 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7601 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7602 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7603 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7604 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7605 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7606 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7607 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7608 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7609 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7610 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7611 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7612 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7613
7614 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7615 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7616 vmcs12->vm_entry_intr_info_field);
7617 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7618 vmcs12->vm_entry_exception_error_code);
7619 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7620 vmcs12->vm_entry_instruction_len);
7621 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7622 vmcs12->guest_interruptibility_info);
fe3ef05c 7623 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7624 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7625 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7626 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7627 vmcs12->guest_pending_dbg_exceptions);
7628 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7629 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7630
7631 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7632
7633 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7634 (vmcs_config.pin_based_exec_ctrl |
7635 vmcs12->pin_based_vm_exec_control));
7636
0238ea91
JK		 7637 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7638 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7639 vmcs12->vmx_preemption_timer_value);
7640
fe3ef05c
NHE		 7641 /*
7642 * Whether page-faults are trapped is determined by a combination of
7643 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7644 * If enable_ept, L0 doesn't care about page faults and we should
7645 * set all of these to L1's desires. However, if !enable_ept, L0 does
7646 * care about (at least some) page faults, and because it is not easy
7647 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7648 * to exit on each and every L2 page fault. This is done by setting
7649 * MASK=MATCH=0 and (see below) EB.PF=1.
7650 * Note that below we don't need special code to set EB.PF beyond the
7651 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7652 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7653 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7654 *
7655 * A problem with this approach (when !enable_ept) is that L1 may be
7656 * injected with more page faults than it asked for. This could have
7657 * caused problems, but in practice existing hypervisors don't care.
7658 * To fix this, we will need to emulate the PFEC checking (on the L1
7659 * page tables), using walk_addr(), when injecting PFs to L1.
7660 */
7661 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7662 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7663 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7664 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7665
7666 if (cpu_has_secondary_exec_ctrls()) {
7667 u32 exec_control = vmx_secondary_exec_control(vmx);
7668 if (!vmx->rdtscp_enabled)
7669 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7670 /* Take the following fields only from vmcs12 */
7671 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7672 if (nested_cpu_has(vmcs12,
7673 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7674 exec_control |= vmcs12->secondary_vm_exec_control;
7675
7676 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7677 /*
7678 * Translate L1 physical address to host physical
7679 * address for vmcs02. Keep the page pinned, so this
7680 * physical address remains valid. We keep a reference
7681 * to it so we can release it later.
7682 */
7683 if (vmx->nested.apic_access_page) /* shouldn't happen */
7684 nested_release_page(vmx->nested.apic_access_page);
7685 vmx->nested.apic_access_page =
7686 nested_get_page(vcpu, vmcs12->apic_access_addr);
7687 /*
7688 * If translation failed, no matter: This feature asks
7689 * to exit when accessing the given address, and if it
7690 * can never be accessed, this feature won't do
7691 * anything anyway.
7692 */
7693 if (!vmx->nested.apic_access_page)
7694 exec_control &=
7695 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7696 else
7697 vmcs_write64(APIC_ACCESS_ADDR,
7698 page_to_phys(vmx->nested.apic_access_page));
7699 }
7700
7701 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7702 }
7703
7704
7705 /*
7706 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7707 * Some constant fields are set here by vmx_set_constant_host_state().
7708 * Other fields are different per CPU, and will be set later when
7709 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7710 */
a547c6db 7711 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7712
7713 /*
7714 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7715 * entry, but only if the current (host) sp changed from the value
7716 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7717 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7718 * here we just force the write to happen on entry.
7719 */
7720 vmx->host_rsp = 0;
7721
7722 exec_control = vmx_exec_control(vmx); /* L0's desires */
7723 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7724 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7725 exec_control &= ~CPU_BASED_TPR_SHADOW;
7726 exec_control |= vmcs12->cpu_based_vm_exec_control;
7727 /*
7728 * Merging of IO and MSR bitmaps not currently supported.
7729 * Rather, exit every time.
7730 */
7731 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7732 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7733 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7734
7735 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7736
7737 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7738 * bitwise-or of what L1 wants to trap for L2, and what we want to
7739 * trap. Note that CR0.TS also needs updating - we do this later.
7740 */
7741 update_exception_bitmap(vcpu);
7742 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7743 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7744
8049d651
NHE		 7745 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7746 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7747 * bits are further modified by vmx_set_efer() below.
7748 */
7854cbca
ACL		 7749 exit_control = vmcs_config.vmexit_ctrl;
7750 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7751 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
7752 vmcs_write32(VM_EXIT_CONTROLS, exit_control);
8049d651
NHE		 7753
7754 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7755 * emulated by vmx_set_efer(), below.
7756 */
7757 vmcs_write32(VM_ENTRY_CONTROLS,
7758 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7759 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7760 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7761
44811c02 7762 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7763 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7764 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7765 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7766 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7767
7768
7769 set_cr4_guest_host_mask(vmx);
7770
27fc51b2
NHE		 7771 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7772 vmcs_write64(TSC_OFFSET,
7773 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7774 else
7775 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7776
7777 if (enable_vpid) {
7778 /*
7779 * Trivially support vpid by letting L2s share their parent
7780 * L1's vpid. TODO: move to a more elaborate solution, giving
7781 * each L2 its own vpid and exposing the vpid feature to L1.
7782 */
7783 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7784 vmx_flush_tlb(vcpu);
7785 }
7786
155a97a3
NHE		 7787 if (nested_cpu_has_ept(vmcs12)) {
7788 kvm_mmu_unload(vcpu);
7789 nested_ept_init_mmu_context(vcpu);
7790 }
7791
fe3ef05c
NHE		 7792 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7793 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7794 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7795 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7796 else
7797 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7798 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7799 vmx_set_efer(vcpu, vcpu->arch.efer);
7800
7801 /*
7802 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7803 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7804 * The CR0_READ_SHADOW is what L2 should have expected to read given
7805 * the specifications by L1; It's not enough to take
7806 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7807 * have more bits than L1 expected.
7808 */
7809 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7810 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7811
7812 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7813 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7814
7815 /* shadow page tables on either EPT or shadow page tables */
7816 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7817 kvm_mmu_reset_context(vcpu);
7818
feaf0c7d
GN		 7819 if (!enable_ept)
7820 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7821
3633cfc3
NHE		 7822 /*
7823 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7824 */
7825 if (enable_ept) {
7826 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7827 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7828 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7829 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
72f85795
GN		 7830 __clear_bit(VCPU_EXREG_PDPTR,
7831 (unsigned long *)&vcpu->arch.regs_avail);
7832 __clear_bit(VCPU_EXREG_PDPTR,
7833 (unsigned long *)&vcpu->arch.regs_dirty);
3633cfc3
NHE		 7834 }
7835
fe3ef05c
NHE		 7836 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7837 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7838}
7839
cd232ad0
NHE		 7840/*
7841 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7842 * for running an L2 nested guest.
7843 */
7844static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7845{
7846 struct vmcs12 *vmcs12;
7847 struct vcpu_vmx *vmx = to_vmx(vcpu);
7848 int cpu;
7849 struct loaded_vmcs *vmcs02;
384bb783 7850 bool ia32e;
cd232ad0
NHE		 7851
7852 if (!nested_vmx_check_permission(vcpu) ||
7853 !nested_vmx_check_vmcs12(vcpu))
7854 return 1;
7855
7856 skip_emulated_instruction(vcpu);
7857 vmcs12 = get_vmcs12(vcpu);
7858
012f83cb
AG		 7859 if (enable_shadow_vmcs)
7860 copy_shadow_to_vmcs12(vmx);
7861
7c177938
NHE		 7862 /*
7863 * The nested entry process starts with enforcing various prerequisites
7864 * on vmcs12 as required by the Intel SDM, and act appropriately when
7865 * they fail: As the SDM explains, some conditions should cause the
7866 * instruction to fail, while others will cause the instruction to seem
7867 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7868 * To speed up the normal (success) code path, we should avoid checking
7869 * for misconfigurations which will anyway be caught by the processor
7870 * when using the merged vmcs02.
7871 */
7872 if (vmcs12->launch_state == launch) {
7873 nested_vmx_failValid(vcpu,
7874 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7875 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7876 return 1;
7877 }
7878
26539bd0
PB		 7879 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7880 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7881 return 1;
7882 }
7883
7c177938
NHE		 7884 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7885 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7886 /*TODO: Also verify bits beyond physical address width are 0*/
7887 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7888 return 1;
7889 }
7890
7891 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7892 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7893 /*TODO: Also verify bits beyond physical address width are 0*/
7894 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7895 return 1;
7896 }
7897
7898 if (vmcs12->vm_entry_msr_load_count > 0 ||
7899 vmcs12->vm_exit_msr_load_count > 0 ||
7900 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7901 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7902 __func__);
7c177938
NHE		 7903 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7904 return 1;
7905 }
7906
7907 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7908 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7909 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7910 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7911 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7912 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7913 !vmx_control_verify(vmcs12->vm_exit_controls,
7914 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7915 !vmx_control_verify(vmcs12->vm_entry_controls,
7916 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7917 {
7918 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7919 return 1;
7920 }
7921
7922 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7923 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7924 nested_vmx_failValid(vcpu,
7925 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7926 return 1;
7927 }
7928
92fbc7b1 7929 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 7930 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7931 nested_vmx_entry_failure(vcpu, vmcs12,
7932 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7933 return 1;
7934 }
7935 if (vmcs12->vmcs_link_pointer != -1ull) {
7936 nested_vmx_entry_failure(vcpu, vmcs12,
7937 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7938 return 1;
7939 }
7940
384bb783 7941 /*
cb0c8cda 7942 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7943 * are performed on the field for the IA32_EFER MSR:
7944 * - Bits reserved in the IA32_EFER MSR must be 0.
7945 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7946 * the IA-32e mode guest VM-exit control. It must also be identical
7947 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7948 * CR0.PG) is 1.
7949 */
7950 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7951 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7952 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7953 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7954 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7955 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7956 nested_vmx_entry_failure(vcpu, vmcs12,
7957 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7958 return 1;
7959 }
7960 }
7961
7962 /*
7963 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7964 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7965 * the values of the LMA and LME bits in the field must each be that of
7966 * the host address-space size VM-exit control.
7967 */
7968 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7969 ia32e = (vmcs12->vm_exit_controls &
7970 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7971 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7972 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7973 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7974 nested_vmx_entry_failure(vcpu, vmcs12,
7975 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7976 return 1;
7977 }
7978 }
7979
7c177938
NHE		 7980 /*
7981 * We're finally done with prerequisite checking, and can start with
7982 * the nested entry.
7983 */
7984
cd232ad0
NHE		 7985 vmcs02 = nested_get_current_vmcs02(vmx);
7986 if (!vmcs02)
7987 return -ENOMEM;
7988
7989 enter_guest_mode(vcpu);
7990
e0b890d3
GN		 7991 vmx->nested.nested_run_pending = 1;
7992
cd232ad0
NHE		 7993 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7994
7995 cpu = get_cpu();
7996 vmx->loaded_vmcs = vmcs02;
7997 vmx_vcpu_put(vcpu);
7998 vmx_vcpu_load(vcpu, cpu);
7999 vcpu->cpu = cpu;
8000 put_cpu();
8001
36c3cc42
JK		 8002 vmx_segment_cache_clear(vmx);
8003
cd232ad0
NHE		 8004 vmcs12->launch_state = 1;
8005
8006 prepare_vmcs02(vcpu, vmcs12);
8007
8008 /*
8009 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8010 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8011 * returned as far as L1 is concerned. It will only return (and set
8012 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8013 */
8014 return 1;
8015}
8016
4704d0be
NHE		 8017/*
8018 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8019 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8020 * This function returns the new value we should put in vmcs12.guest_cr0.
8021 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8022 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8023 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8024 * didn't trap the bit, because if L1 did, so would L0).
8025 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8026 * been modified by L2, and L1 knows it. So just leave the old value of
8027 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8028 * isn't relevant, because if L0 traps this bit it can set it to anything.
8029 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8030 * changed these bits, and therefore they need to be updated, but L0
8031 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8032 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8033 */
8034static inline unsigned long
8035vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8036{
8037 return
8038 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8039 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8040 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8041 vcpu->arch.cr0_guest_owned_bits));
8042}
8043
8044static inline unsigned long
8045vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8046{
8047 return
8048 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8049 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8050 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8051 vcpu->arch.cr4_guest_owned_bits));
8052}
8053
5f3d5799
JK		 8054static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8055 struct vmcs12 *vmcs12)
8056{
8057 u32 idt_vectoring;
8058 unsigned int nr;
8059
851eb667 8060 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8061 nr = vcpu->arch.exception.nr;
8062 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8063
8064 if (kvm_exception_is_soft(nr)) {
8065 vmcs12->vm_exit_instruction_len =
8066 vcpu->arch.event_exit_inst_len;
8067 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8068 } else
8069 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8070
8071 if (vcpu->arch.exception.has_error_code) {
8072 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8073 vmcs12->idt_vectoring_error_code =
8074 vcpu->arch.exception.error_code;
8075 }
8076
8077 vmcs12->idt_vectoring_info_field = idt_vectoring;
8078 } else if (vcpu->arch.nmi_pending) {
8079 vmcs12->idt_vectoring_info_field =
8080 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8081 } else if (vcpu->arch.interrupt.pending) {
8082 nr = vcpu->arch.interrupt.nr;
8083 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8084
8085 if (vcpu->arch.interrupt.soft) {
8086 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8087 vmcs12->vm_entry_instruction_len =
8088 vcpu->arch.event_exit_inst_len;
8089 } else
8090 idt_vectoring |= INTR_TYPE_EXT_INTR;
8091
8092 vmcs12->idt_vectoring_info_field = idt_vectoring;
8093 }
8094}
8095
4704d0be
NHE		 8096/*
8097 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8098 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8099 * and this function updates it to reflect the changes to the guest state while
8100 * L2 was running (and perhaps made some exits which were handled directly by L0
8101 * without going back to L1), and to reflect the exit reason.
8102 * Note that we do not have to copy here all VMCS fields, just those that
8103 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8104 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8105 * which already writes to vmcs12 directly.
8106 */
733568f9 8107static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8108{
8109 /* update guest state fields: */
8110 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8111 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8112
8113 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8114 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8115 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8116 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8117
8118 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8119 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8120 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8121 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8122 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8123 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8124 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8125 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8126 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8127 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8128 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8129 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8130 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8131 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8132 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8133 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8134 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8135 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8136 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8137 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8138 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8139 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8140 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8141 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8142 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8143 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8144 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8145 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8146 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8147 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8148 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8149 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8150 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8151 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8152 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8153 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8154
4704d0be
NHE		 8155 vmcs12->guest_interruptibility_info =
8156 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8157 vmcs12->guest_pending_dbg_exceptions =
8158 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8159
7854cbca
ACL		 8160 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8161 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8162 vmcs12->vmx_preemption_timer_value =
8163 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8164
3633cfc3
NHE		 8165 /*
8166 * In some cases (usually, nested EPT), L2 is allowed to change its
8167 * own CR3 without exiting. If it has changed it, we must keep it.
8168 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8169 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8170 *
8171 * Additionally, restore L2's PDPTR to vmcs12.
8172 */
8173 if (enable_ept) {
8174 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8175 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8176 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8177 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8178 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8179 }
8180
c18911a2
JK		 8181 vmcs12->vm_entry_controls =
8182 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8183 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8184
4704d0be
NHE		 8185 /* TODO: These cannot have changed unless we have MSR bitmaps and
8186 * the relevant bit asks not to trap the change */
8187 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8188 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8189 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8190 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8191 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8192 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8193 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8194 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8195
8196 /* update exit information fields: */
8197
957c897e 8198 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8199 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8200
8201 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8202 if ((vmcs12->vm_exit_intr_info &
8203 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8204 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8205 vmcs12->vm_exit_intr_error_code =
8206 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8207 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8208 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8209 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8210
5f3d5799
JK		 8211 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8212 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8213 * instead of reading the real value. */
4704d0be 8214 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8215
8216 /*
8217 * Transfer the event that L0 or L1 may wanted to inject into
8218 * L2 to IDT_VECTORING_INFO_FIELD.
8219 */
8220 vmcs12_save_pending_event(vcpu, vmcs12);
8221 }
8222
8223 /*
8224 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8225 * preserved above and would only end up incorrectly in L1.
8226 */
8227 vcpu->arch.nmi_injected = false;
8228 kvm_clear_exception_queue(vcpu);
8229 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8230}
8231
8232/*
8233 * A part of what we need to when the nested L2 guest exits and we want to
8234 * run its L1 parent, is to reset L1's guest state to the host state specified
8235 * in vmcs12.
8236 * This function is to be called not only on normal nested exit, but also on
8237 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8238 * Failures During or After Loading Guest State").
8239 * This function should be called when the active VMCS is L1's (vmcs01).
8240 */
733568f9
JK		 8241static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8242 struct vmcs12 *vmcs12)
4704d0be 8243{
21feb4eb
ACL		 8244 struct kvm_segment seg;
8245
4704d0be
NHE		 8246 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8247 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8248 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8249 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8250 else
8251 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8252 vmx_set_efer(vcpu, vcpu->arch.efer);
8253
8254 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8255 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8256 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8257 /*
8258 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8259 * actually changed, because it depends on the current state of
8260 * fpu_active (which may have changed).
8261 * Note that vmx_set_cr0 refers to efer set above.
8262 */
9e3e4dbf 8263 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8264 /*
8265 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8266 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8267 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8268 */
8269 update_exception_bitmap(vcpu);
8270 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8271 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8272
8273 /*
8274 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8275 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8276 */
8277 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8278 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8279
155a97a3
NHE		 8280 if (nested_cpu_has_ept(vmcs12))
8281 nested_ept_uninit_mmu_context(vcpu);
8282
4704d0be
NHE		 8283 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8284 kvm_mmu_reset_context(vcpu);
8285
feaf0c7d
GN		 8286 if (!enable_ept)
8287 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8288
4704d0be
NHE		 8289 if (enable_vpid) {
8290 /*
8291 * Trivially support vpid by letting L2s share their parent
8292 * L1's vpid. TODO: move to a more elaborate solution, giving
8293 * each L2 its own vpid and exposing the vpid feature to L1.
8294 */
8295 vmx_flush_tlb(vcpu);
8296 }
8297
8298
8299 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8300 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8301 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8302 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8303 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8304
44811c02 8305 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8306 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8307 vcpu->arch.pat = vmcs12->host_ia32_pat;
8308 }
4704d0be
NHE		 8309 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8310 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8311 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8312
21feb4eb
ACL		 8313 /* Set L1 segment info according to Intel SDM
8314 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8315 seg = (struct kvm_segment) {
8316 .base = 0,
8317 .limit = 0xFFFFFFFF,
8318 .selector = vmcs12->host_cs_selector,
8319 .type = 11,
8320 .present = 1,
8321 .s = 1,
8322 .g = 1
8323 };
8324 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8325 seg.l = 1;
8326 else
8327 seg.db = 1;
8328 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8329 seg = (struct kvm_segment) {
8330 .base = 0,
8331 .limit = 0xFFFFFFFF,
8332 .type = 3,
8333 .present = 1,
8334 .s = 1,
8335 .db = 1,
8336 .g = 1
8337 };
8338 seg.selector = vmcs12->host_ds_selector;
8339 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8340 seg.selector = vmcs12->host_es_selector;
8341 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8342 seg.selector = vmcs12->host_ss_selector;
8343 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8344 seg.selector = vmcs12->host_fs_selector;
8345 seg.base = vmcs12->host_fs_base;
8346 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8347 seg.selector = vmcs12->host_gs_selector;
8348 seg.base = vmcs12->host_gs_base;
8349 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8350 seg = (struct kvm_segment) {
205befd9 8351 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8352 .limit = 0x67,
8353 .selector = vmcs12->host_tr_selector,
8354 .type = 11,
8355 .present = 1
8356 };
8357 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8358
503cd0c5
JK		 8359 kvm_set_dr(vcpu, 7, 0x400);
8360 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8361}
8362
8363/*
8364 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8365 * and modify vmcs12 to make it see what it would expect to see there if
8366 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8367 */
8368static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8369{
8370 struct vcpu_vmx *vmx = to_vmx(vcpu);
8371 int cpu;
8372 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8373
5f3d5799
JK		 8374 /* trying to cancel vmlaunch/vmresume is a bug */
8375 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8376
4704d0be
NHE		 8377 leave_guest_mode(vcpu);
8378 prepare_vmcs12(vcpu, vmcs12);
8379
8380 cpu = get_cpu();
8381 vmx->loaded_vmcs = &vmx->vmcs01;
8382 vmx_vcpu_put(vcpu);
8383 vmx_vcpu_load(vcpu, cpu);
8384 vcpu->cpu = cpu;
8385 put_cpu();
8386
36c3cc42
JK		 8387 vmx_segment_cache_clear(vmx);
8388
4704d0be
NHE		 8389 /* if no vmcs02 cache requested, remove the one we used */
8390 if (VMCS02_POOL_SIZE == 0)
8391 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8392
8393 load_vmcs12_host_state(vcpu, vmcs12);
8394
27fc51b2 8395 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8396 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8397
8398 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8399 vmx->host_rsp = 0;
8400
8401 /* Unpin physical memory we referred to in vmcs02 */
8402 if (vmx->nested.apic_access_page) {
8403 nested_release_page(vmx->nested.apic_access_page);
8404 vmx->nested.apic_access_page = 0;
8405 }
8406
8407 /*
8408 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8409 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8410 * success or failure flag accordingly.
8411 */
8412 if (unlikely(vmx->fail)) {
8413 vmx->fail = 0;
8414 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8415 } else
8416 nested_vmx_succeed(vcpu);
012f83cb
AG		 8417 if (enable_shadow_vmcs)
8418 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8419}
8420
7c177938
NHE		 8421/*
8422 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8423 * 23.7 "VM-entry failures during or after loading guest state" (this also
8424 * lists the acceptable exit-reason and exit-qualification parameters).
8425 * It should only be called before L2 actually succeeded to run, and when
8426 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8427 */
8428static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8429 struct vmcs12 *vmcs12,
8430 u32 reason, unsigned long qualification)
8431{
8432 load_vmcs12_host_state(vcpu, vmcs12);
8433 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8434 vmcs12->exit_qualification = qualification;
8435 nested_vmx_succeed(vcpu);
012f83cb
AG		 8436 if (enable_shadow_vmcs)
8437 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8438}
8439
8a76d7f2
JR		 8440static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8441 struct x86_instruction_info *info,
8442 enum x86_intercept_stage stage)
8443{
8444 return X86EMUL_CONTINUE;
8445}
8446
cbdd1bea 8447static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8448 .cpu_has_kvm_support = cpu_has_kvm_support,
8449 .disabled_by_bios = vmx_disabled_by_bios,
8450 .hardware_setup = hardware_setup,
8451 .hardware_unsetup = hardware_unsetup,
002c7f7c 8452 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8453 .hardware_enable = hardware_enable,
8454 .hardware_disable = hardware_disable,
04547156 8455 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8456
8457 .vcpu_create = vmx_create_vcpu,
8458 .vcpu_free = vmx_free_vcpu,
04d2cc77 8459 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8460
04d2cc77 8461 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8462 .vcpu_load = vmx_vcpu_load,
8463 .vcpu_put = vmx_vcpu_put,
8464
c8639010 8465 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8466 .get_msr = vmx_get_msr,
8467 .set_msr = vmx_set_msr,
8468 .get_segment_base = vmx_get_segment_base,
8469 .get_segment = vmx_get_segment,
8470 .set_segment = vmx_set_segment,
2e4d2653 8471 .get_cpl = vmx_get_cpl,
6aa8b732 8472 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8473 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8474 .decache_cr3 = vmx_decache_cr3,
25c4c276 8475 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8476 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8477 .set_cr3 = vmx_set_cr3,
8478 .set_cr4 = vmx_set_cr4,
6aa8b732 8479 .set_efer = vmx_set_efer,
6aa8b732
AK		 8480 .get_idt = vmx_get_idt,
8481 .set_idt = vmx_set_idt,
8482 .get_gdt = vmx_get_gdt,
8483 .set_gdt = vmx_set_gdt,
020df079 8484 .set_dr7 = vmx_set_dr7,
5fdbf976 8485 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8486 .get_rflags = vmx_get_rflags,
8487 .set_rflags = vmx_set_rflags,
ebcbab4c 8488 .fpu_activate = vmx_fpu_activate,
02daab21 8489 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8490
8491 .tlb_flush = vmx_flush_tlb,
6aa8b732 8492
6aa8b732 8493 .run = vmx_vcpu_run,
6062d012 8494 .handle_exit = vmx_handle_exit,
6aa8b732 8495 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8496 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8497 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8498 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8499 .set_irq = vmx_inject_irq,
95ba8273 8500 .set_nmi = vmx_inject_nmi,
298101da 8501 .queue_exception = vmx_queue_exception,
b463a6f7 8502 .cancel_injection = vmx_cancel_injection,
78646121 8503 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8504 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8505 .get_nmi_mask = vmx_get_nmi_mask,
8506 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8507 .enable_nmi_window = enable_nmi_window,
8508 .enable_irq_window = enable_irq_window,
8509 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8510 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8511 .vm_has_apicv = vmx_vm_has_apicv,
8512 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8513 .hwapic_irr_update = vmx_hwapic_irr_update,
8514 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8515 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8516 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8517
cbc94022 8518 .set_tss_addr = vmx_set_tss_addr,
67253af5 8519 .get_tdp_level = get_ept_level,
4b12f0de 8520 .get_mt_mask = vmx_get_mt_mask,
229456fc 8521
586f9607 8522 .get_exit_info = vmx_get_exit_info,
586f9607 8523
17cc3935 8524 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8525
8526 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8527
8528 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8529 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8530
8531 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8532
8533 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8534
4051b188 8535 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8536 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8537 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8538 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8539 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8540 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8541
8542 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8543
8544 .check_intercept = vmx_check_intercept,
a547c6db 8545 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8546};
8547
8548static int __init vmx_init(void)
8549{
8d14695f 8550 int r, i, msr;
26bb0981
AK		 8551
8552 rdmsrl_safe(MSR_EFER, &host_efer);
8553
8554 for (i = 0; i < NR_VMX_MSR; ++i)
8555 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8556
3e7c73e9 8557 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8558 if (!vmx_io_bitmap_a)
8559 return -ENOMEM;
8560
2106a548
GC		 8561 r = -ENOMEM;
8562
3e7c73e9 8563 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8564 if (!vmx_io_bitmap_b)
fdef3ad1 8565 goto out;
fdef3ad1 8566
5897297b 8567 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8568 if (!vmx_msr_bitmap_legacy)
25c5f225 8569 goto out1;
2106a548 8570
8d14695f
YZ		 8571 vmx_msr_bitmap_legacy_x2apic =
8572 (unsigned long *)__get_free_page(GFP_KERNEL);
8573 if (!vmx_msr_bitmap_legacy_x2apic)
8574 goto out2;
25c5f225 8575
5897297b 8576 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8577 if (!vmx_msr_bitmap_longmode)
8d14695f 8578 goto out3;
2106a548 8579
8d14695f
YZ		 8580 vmx_msr_bitmap_longmode_x2apic =
8581 (unsigned long *)__get_free_page(GFP_KERNEL);
8582 if (!vmx_msr_bitmap_longmode_x2apic)
8583 goto out4;
4607c2d7
AG		 8584 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8585 if (!vmx_vmread_bitmap)
8586 goto out5;
8587
8588 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8589 if (!vmx_vmwrite_bitmap)
8590 goto out6;
8591
8592 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8593 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8594 /* shadowed read/write fields */
8595 for (i = 0; i < max_shadow_read_write_fields; i++) {
8596 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8597 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8598 }
8599 /* shadowed read only fields */
8600 for (i = 0; i < max_shadow_read_only_fields; i++)
8601 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8602
fdef3ad1
HQ		 8603 /*
8604 * Allow direct access to the PC debug port (it is often used for I/O
8605 * delays, but the vmexits simply slow things down).
8606 */
3e7c73e9
AK		 8607 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8608 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8609
3e7c73e9 8610 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8611
5897297b
AK		 8612 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8613 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8614
2384d2b3
SY		 8615 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8616
0ee75bea
AK		 8617 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8618 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8619 if (r)
4607c2d7 8620 goto out7;
25c5f225 8621
8f536b76
ZY		 8622#ifdef CONFIG_KEXEC
8623 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8624 crash_vmclear_local_loaded_vmcss);
8625#endif
8626
5897297b
AK		 8627 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8628 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8629 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8630 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8631 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8632 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8633 memcpy(vmx_msr_bitmap_legacy_x2apic,
8634 vmx_msr_bitmap_legacy, PAGE_SIZE);
8635 memcpy(vmx_msr_bitmap_longmode_x2apic,
8636 vmx_msr_bitmap_longmode, PAGE_SIZE);
8637
01e439be 8638 if (enable_apicv) {
8d14695f
YZ		 8639 for (msr = 0x800; msr <= 0x8ff; msr++)
8640 vmx_disable_intercept_msr_read_x2apic(msr);
8641
8642 /* According SDM, in x2apic mode, the whole id reg is used.
8643 * But in KVM, it only use the highest eight bits. Need to
8644 * intercept it */
8645 vmx_enable_intercept_msr_read_x2apic(0x802);
8646 /* TMCCT */
8647 vmx_enable_intercept_msr_read_x2apic(0x839);
8648 /* TPR */
8649 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8650 /* EOI */
8651 vmx_disable_intercept_msr_write_x2apic(0x80b);
8652 /* SELF-IPI */
8653 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8654 }
fdef3ad1 8655
089d034e 8656 if (enable_ept) {
3f6d8c8a
XH		 8657 kvm_mmu_set_mask_ptes(0ull,
8658 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8659 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8660 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8661 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8662 kvm_enable_tdp();
8663 } else
8664 kvm_disable_tdp();
1439442c 8665
fdef3ad1
HQ		 8666 return 0;
8667
4607c2d7
AG		 8668out7:
8669 free_page((unsigned long)vmx_vmwrite_bitmap);
8670out6:
8671 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8672out5:
8673 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8674out4:
5897297b 8675 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8676out3:
8677 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8678out2:
5897297b 8679 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8680out1:
3e7c73e9 8681 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8682out:
3e7c73e9 8683 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8684 return r;
6aa8b732
AK		 8685}
8686
8687static void __exit vmx_exit(void)
8688{
8d14695f
YZ		 8689 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8690 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8691 free_page((unsigned long)vmx_msr_bitmap_legacy);
8692 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8693 free_page((unsigned long)vmx_io_bitmap_b);
8694 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8695 free_page((unsigned long)vmx_vmwrite_bitmap);
8696 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8697
8f536b76
ZY		 8698#ifdef CONFIG_KEXEC
8699 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8700 synchronize_rcu();
8701#endif
8702
cb498ea2 8703 kvm_exit();
6aa8b732
AK		 8704}
8705
8706module_init(vmx_init)
8707module_exit(vmx_exit)
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