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KVM: nVMX: Check all exceptions for intercept during delivery to L2
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
bfd0a56b 715static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
f5c4368f 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
155a97a3
NHE		 1048static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049{
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051}
1052
644d711a
NHE		 1053static inline bool is_exception(u32 intr_info)
1054{
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057}
1058
1059static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1060static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1063
8b9cf98c 1064static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1065{
1066 int i;
1067
a2fa3e9f 1068 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1070 return i;
1071 return -1;
1072}
1073
2384d2b3
SY		 1074static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075{
1076 struct {
1077 u64 vpid : 16;
1078 u64 rsvd : 48;
1079 u64 gva;
1080 } operand = { vpid, 0, gva };
1081
4ecac3fd 1082 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1086}
1087
1439442c
SY		 1088static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089{
1090 struct {
1091 u64 eptp, gpa;
1092 } operand = {eptp, gpa};
1093
4ecac3fd 1094 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1098}
1099
26bb0981 1100static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1101{
1102 int i;
1103
8b9cf98c 1104 i = __find_msr_index(vmx, msr);
a75beee6 1105 if (i >= 0)
a2fa3e9f 1106 return &vmx->guest_msrs[i];
8b6d44c7 1107 return NULL;
7725f0ba
AK		 1108}
1109
6aa8b732
AK		 1110static void vmcs_clear(struct vmcs *vmcs)
1111{
1112 u64 phys_addr = __pa(vmcs);
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1117 : "cc", "memory");
1118 if (error)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120 vmcs, phys_addr);
1121}
1122
d462b819
NHE		 1123static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124{
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1128}
1129
7725b894
DX		 1130static void vmcs_load(struct vmcs *vmcs)
1131{
1132 u64 phys_addr = __pa(vmcs);
1133 u8 error;
1134
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1137 : "cc", "memory");
1138 if (error)
2844d849 1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1140 vmcs, phys_addr);
1141}
1142
8f536b76
ZY		 1143#ifdef CONFIG_KEXEC
1144/*
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1147 * default.
1148 */
1149static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151static inline void crash_enable_local_vmclear(int cpu)
1152{
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline void crash_disable_local_vmclear(int cpu)
1157{
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static inline int crash_local_vmclear_enabled(int cpu)
1162{
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164}
1165
1166static void crash_vmclear_local_loaded_vmcss(void)
1167{
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1170
1171 if (!crash_local_vmclear_enabled(cpu))
1172 return;
1173
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1177}
1178#else
1179static inline void crash_enable_local_vmclear(int cpu) { }
1180static inline void crash_disable_local_vmclear(int cpu) { }
1181#endif /* CONFIG_KEXEC */
1182
d462b819 1183static void __loaded_vmcs_clear(void *arg)
6aa8b732 1184{
d462b819 1185 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1186 int cpu = raw_smp_processor_id();
6aa8b732 1187
d462b819
NHE		 1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1191 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1192 crash_disable_local_vmclear(cpu);
d462b819 1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1194
1195 /*
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1200 */
1201 smp_wmb();
1202
d462b819 1203 loaded_vmcs_init(loaded_vmcs);
8f536b76 1204 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1205}
1206
d462b819 1207static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1208{
e6c7d321
XG		 1209 int cpu = loaded_vmcs->cpu;
1210
1211 if (cpu != -1)
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1214}
1215
1760dd49 1216static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1217{
1218 if (vmx->vpid == 0)
1219 return;
1220
518c8aee
GJ		 1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1223}
1224
b9d762fa
GJ		 1225static inline void vpid_sync_vcpu_global(void)
1226{
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229}
1230
1231static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232{
1233 if (cpu_has_vmx_invvpid_single())
1760dd49 1234 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1235 else
1236 vpid_sync_vcpu_global();
1237}
1238
1439442c
SY		 1239static inline void ept_sync_global(void)
1240{
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243}
1244
1245static inline void ept_sync_context(u64 eptp)
1246{
089d034e 1247 if (enable_ept) {
1439442c
SY		 1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250 else
1251 ept_sync_global();
1252 }
1253}
1254
96304217 1255static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1256{
5e520e62 1257 unsigned long value;
6aa8b732 1258
5e520e62
AK		 1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1261 return value;
1262}
1263
96304217 1264static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1270{
1271 return vmcs_readl(field);
1272}
1273
96304217 1274static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1275{
05b3e0c2 1276#ifdef CONFIG_X86_64
6aa8b732
AK		 1277 return vmcs_readl(field);
1278#else
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280#endif
1281}
1282
e52de1b8
AK		 1283static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284{
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287 dump_stack();
1288}
1289
6aa8b732
AK		 1290static void vmcs_writel(unsigned long field, unsigned long value)
1291{
1292 u8 error;
1293
4ecac3fd 1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1296 if (unlikely(error))
1297 vmwrite_error(field, value);
6aa8b732
AK		 1298}
1299
1300static void vmcs_write16(unsigned long field, u16 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write32(unsigned long field, u32 value)
1306{
1307 vmcs_writel(field, value);
1308}
1309
1310static void vmcs_write64(unsigned long field, u64 value)
1311{
6aa8b732 1312 vmcs_writel(field, value);
7682f2d0 1313#ifndef CONFIG_X86_64
6aa8b732
AK		 1314 asm volatile ("");
1315 vmcs_writel(field+1, value >> 32);
1316#endif
1317}
1318
2ab455cc
AL		 1319static void vmcs_clear_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1322}
1323
1324static void vmcs_set_bits(unsigned long field, u32 mask)
1325{
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1327}
1328
2fb92db1
AK		 1329static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330{
1331 vmx->segment_cache.bitmask = 0;
1332}
1333
1334static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335 unsigned field)
1336{
1337 bool ret;
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1343 }
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1346 return ret;
1347}
1348
1349static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350{
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355 return *p;
1356}
1357
1358static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359{
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364 return *p;
1365}
1366
1367static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368{
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373 return *p;
1374}
1375
1376static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377{
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382 return *p;
1383}
1384
abd3f2d6
AK		 1385static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386{
1387 u32 eb;
1388
fd7373cc
JK		 1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
7ffd92c5 1395 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1396 eb = ~0;
089d034e 1397 if (enable_ept)
1439442c 1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1401
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1406 */
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
abd3f2d6
AK		 1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1411}
1412
8bf00a52
GN		 1413static void clear_atomic_switch_msr_special(unsigned long entry,
1414 unsigned long exit)
1415{
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418}
1419
61d2ef2c
AK		 1420static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421{
1422 unsigned i;
1423 struct msr_autoload *m = &vmx->msr_autoload;
1424
8bf00a52
GN		 1425 switch (msr) {
1426 case MSR_EFER:
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1430 return;
1431 }
1432 break;
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438 return;
1439 }
1440 break;
110312c8
AK		 1441 }
1442
61d2ef2c
AK		 1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1445 break;
1446
1447 if (i == m->nr)
1448 return;
1449 --m->nr;
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454}
1455
8bf00a52
GN		 1456static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459{
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464}
1465
61d2ef2c
AK		 1466static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1468{
1469 unsigned i;
1470 struct msr_autoload *m = &vmx->msr_autoload;
1471
8bf00a52
GN		 1472 switch (msr) {
1473 case MSR_EFER:
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1477 GUEST_IA32_EFER,
1478 HOST_IA32_EFER,
1479 guest_val, host_val);
1480 return;
1481 }
1482 break;
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1491 return;
1492 }
1493 break;
110312c8
AK		 1494 }
1495
61d2ef2c
AK		 1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1498 break;
1499
e7fc6f93
GN		 1500 if (i == NR_AUTOLOAD_MSRS) {
1501 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr);
1503 return;
1504 } else if (i == m->nr) {
61d2ef2c
AK		 1505 ++m->nr;
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508 }
1509
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1514}
1515
33ed6329
AK		 1516static void reload_tss(void)
1517{
33ed6329
AK		 1518 /*
1519 * VT restores TR but not its size. Useless.
1520 */
d359192f 1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1522 struct desc_struct *descs;
33ed6329 1523
d359192f 1524 descs = (void *)gdt->address;
33ed6329
AK		 1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526 load_TR_desc();
33ed6329
AK		 1527}
1528
92c0d900 1529static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1530{
3a34a881 1531 u64 guest_efer;
51c6cf66
AK		 1532 u64 ignore_bits;
1533
f6801dff 1534 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1535
51c6cf66 1536 /*
0fa06071 1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1538 * outside long mode
1539 */
1540 ignore_bits = EFER_NX | EFER_SCE;
1541#ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1546#endif
51c6cf66
AK		 1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
26bb0981 1549 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1551
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559 return false;
1560 }
1561
26bb0981 1562 return true;
51c6cf66
AK		 1563}
1564
2d49ec72
GN		 1565static unsigned long segment_base(u16 selector)
1566{
d359192f 1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1568 struct desc_struct *d;
1569 unsigned long table_base;
1570 unsigned long v;
1571
1572 if (!(selector & ~3))
1573 return 0;
1574
d359192f 1575 table_base = gdt->address;
2d49ec72
GN		 1576
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1579
1580 if (!(ldt_selector & ~3))
1581 return 0;
1582
1583 table_base = segment_base(ldt_selector);
1584 }
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587#ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590#endif
1591 return v;
1592}
1593
1594static inline unsigned long kvm_read_tr_base(void)
1595{
1596 u16 tr;
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1599}
1600
04d2cc77 1601static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1602{
04d2cc77 1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1604 int i;
04d2cc77 1605
a2fa3e9f 1606 if (vmx->host_state.loaded)
33ed6329
AK		 1607 return;
1608
a2fa3e9f 1609 vmx->host_state.loaded = 1;
33ed6329
AK		 1610 /*
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1613 */
d6e88aec 1614 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1616 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1617 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1619 vmx->host_state.fs_reload_needed = 0;
1620 } else {
33ed6329 1621 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1622 vmx->host_state.fs_reload_needed = 1;
33ed6329 1623 }
9581d442 1624 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1627 else {
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1629 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1630 }
1631
b2da15ac
AK		 1632#ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1635#endif
1636
33ed6329
AK		 1637#ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640#else
a2fa3e9f
GH		 1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1643#endif
707c0874
AK		 1644
1645#ifdef CONFIG_X86_64
c8770e7b
AK		 1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
44ea2b17 1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1649#endif
26bb0981
AK		 1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
33ed6329
AK		 1654}
1655
a9b21b62 1656static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1657{
a2fa3e9f 1658 if (!vmx->host_state.loaded)
33ed6329
AK		 1659 return;
1660
e1beb1d3 1661 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1662 vmx->host_state.loaded = 0;
c8770e7b
AK		 1663#ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666#endif
152d3f2f 1667 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1668 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1669#ifdef CONFIG_X86_64
9581d442 1670 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1671#else
1672 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1673#endif
33ed6329 1674 }
0a77fe4c
AK		 1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1677#ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1681 }
b2da15ac 1682#endif
152d3f2f 1683 reload_tss();
44ea2b17 1684#ifdef CONFIG_X86_64
c8770e7b 1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1686#endif
b1a74bf8
SS		 1687 /*
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1690 */
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692 stts();
3444d7da 1693 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1694}
1695
a9b21b62
AK		 1696static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697{
1698 preempt_disable();
1699 __vmx_load_host_state(vmx);
1700 preempt_enable();
1701}
1702
6aa8b732
AK		 1703/*
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1706 */
15ad7146 1707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1708{
a2fa3e9f 1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1711
4610c9cc
DX		 1712 if (!vmm_exclusive)
1713 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1716
d462b819
NHE		 1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1720 }
1721
d462b819 1722 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1724 unsigned long sysenter_esp;
1725
a8eeb04a 1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1727 local_irq_disable();
8f536b76 1728 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1729
1730 /*
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1734 */
1735 smp_rmb();
1736
d462b819
NHE		 1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1739 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1740 local_irq_enable();
1741
6aa8b732
AK		 1742 /*
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1744 * processors.
1745 */
d6e88aec 1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1748
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1751 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1752 }
6aa8b732
AK		 1753}
1754
1755static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756{
a9b21b62 1757 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1758 if (!vmm_exclusive) {
d462b819
NHE		 1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760 vcpu->cpu = -1;
4610c9cc
DX		 1761 kvm_cpu_vmxoff();
1762 }
6aa8b732
AK		 1763}
1764
5fd86fcf
AK		 1765static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766{
81231c69
AK		 1767 ulong cr0;
1768
5fd86fcf
AK		 1769 if (vcpu->fpu_active)
1770 return;
1771 vcpu->fpu_active = 1;
81231c69
AK		 1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1776 update_exception_bitmap(vcpu);
edcafe3c 1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1782}
1783
edcafe3c
AK		 1784static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
fe3ef05c
NHE		 1786/*
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1790 */
1791static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795}
1796static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797{
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800}
1801
5fd86fcf
AK		 1802static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803{
36cf24e0
NHE		 1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1806 */
edcafe3c 1807 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1809 update_exception_bitmap(vcpu);
edcafe3c
AK		 1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1812 if (is_guest_mode(vcpu)) {
1813 /*
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1820 */
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825 } else
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1827}
1828
6aa8b732
AK		 1829static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830{
78ac8b47 1831 unsigned long rflags, save_rflags;
345dcaa8 1832
6de12732
AK		 1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 }
1841 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1842 }
6de12732 1843 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1844}
1845
1846static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847{
6de12732
AK		 1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1853 }
6aa8b732
AK		 1854 vmcs_writel(GUEST_RFLAGS, rflags);
1855}
1856
2809f5d2
GC		 1857static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858{
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 int ret = 0;
1861
1862 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1863 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1866
1867 return ret & mask;
1868}
1869
1870static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871{
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1874
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
48005f64 1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1879 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1880 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884}
1885
6aa8b732
AK		 1886static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887{
1888 unsigned long rip;
6aa8b732 1889
5fdbf976 1890 rip = kvm_rip_read(vcpu);
6aa8b732 1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1892 kvm_rip_write(vcpu, rip);
6aa8b732 1893
2809f5d2
GC		 1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1896}
1897
0b6ac343
NHE		 1898/*
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1901 */
e011c663 1902static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1903{
1904 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1905
e011c663 1906 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1907 return 0;
1908
1909 nested_vmx_vmexit(vcpu);
1910 return 1;
1911}
1912
298101da 1913static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1914 bool has_error_code, u32 error_code,
1915 bool reinject)
298101da 1916{
77ab6db0 1917 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1918 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1919
e011c663
GN		 1920 if (!reinject && is_guest_mode(vcpu) &&
1921 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1922 return;
1923
8ab2d2e2 1924 if (has_error_code) {
77ab6db0 1925 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1926 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927 }
77ab6db0 1928
7ffd92c5 1929 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1930 int inc_eip = 0;
1931 if (kvm_exception_is_soft(nr))
1932 inc_eip = vcpu->arch.event_exit_inst_len;
1933 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1934 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1935 return;
1936 }
1937
66fd3f7f
GN		 1938 if (kvm_exception_is_soft(nr)) {
1939 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1941 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942 } else
1943 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1946}
1947
4e47c7a6
SY		 1948static bool vmx_rdtscp_supported(void)
1949{
1950 return cpu_has_vmx_rdtscp();
1951}
1952
ad756a16
MJ		 1953static bool vmx_invpcid_supported(void)
1954{
1955 return cpu_has_vmx_invpcid() && enable_ept;
1956}
1957
a75beee6
ED		 1958/*
1959 * Swap MSR entry in host/guest MSR entry array.
1960 */
8b9cf98c 1961static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1962{
26bb0981 1963 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1964
1965 tmp = vmx->guest_msrs[to];
1966 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1968}
1969
8d14695f
YZ		 1970static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971{
1972 unsigned long *msr_bitmap;
1973
1974 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975 if (is_long_mode(vcpu))
1976 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977 else
1978 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979 } else {
1980 if (is_long_mode(vcpu))
1981 msr_bitmap = vmx_msr_bitmap_longmode;
1982 else
1983 msr_bitmap = vmx_msr_bitmap_legacy;
1984 }
1985
1986 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987}
1988
e38aea3e
AK		 1989/*
1990 * Set up the vmcs to automatically save and restore system
1991 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1992 * mode, as fiddling with msrs is very expensive.
1993 */
8b9cf98c 1994static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1995{
26bb0981 1996 int save_nmsrs, index;
e38aea3e 1997
a75beee6
ED		 1998 save_nmsrs = 0;
1999#ifdef CONFIG_X86_64
8b9cf98c 2000 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2001 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2002 if (index >= 0)
8b9cf98c
RR		 2003 move_msr_up(vmx, index, save_nmsrs++);
2004 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2005 if (index >= 0)
8b9cf98c
RR		 2006 move_msr_up(vmx, index, save_nmsrs++);
2007 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2008 if (index >= 0)
8b9cf98c 2009 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2010 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011 if (index >= 0 && vmx->rdtscp_enabled)
2012 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2013 /*
8c06585d 2014 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2015 * if efer.sce is enabled.
2016 */
8c06585d 2017 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2018 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2019 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2020 }
2021#endif
92c0d900
AK		 2022 index = __find_msr_index(vmx, MSR_EFER);
2023 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2024 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2025
26bb0981 2026 vmx->save_nmsrs = save_nmsrs;
5897297b 2027
8d14695f
YZ		 2028 if (cpu_has_vmx_msr_bitmap())
2029 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2030}
2031
6aa8b732
AK		 2032/*
2033 * reads and returns guest's timestamp counter "register"
2034 * guest_tsc = host_tsc + tsc_offset -- 21.3
2035 */
2036static u64 guest_read_tsc(void)
2037{
2038 u64 host_tsc, tsc_offset;
2039
2040 rdtscll(host_tsc);
2041 tsc_offset = vmcs_read64(TSC_OFFSET);
2042 return host_tsc + tsc_offset;
2043}
2044
d5c1785d
NHE		 2045/*
2046 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047 * counter, even if a nested guest (L2) is currently running.
2048 */
886b470c 2049u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2050{
886b470c 2051 u64 tsc_offset;
d5c1785d 2052
d5c1785d
NHE		 2053 tsc_offset = is_guest_mode(vcpu) ?
2054 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055 vmcs_read64(TSC_OFFSET);
2056 return host_tsc + tsc_offset;
2057}
2058
4051b188 2059/*
cc578287
ZA		 2060 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2061 * software catchup for faster rates on slower CPUs.
4051b188 2062 */
cc578287 2063static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2064{
cc578287
ZA		 2065 if (!scale)
2066 return;
2067
2068 if (user_tsc_khz > tsc_khz) {
2069 vcpu->arch.tsc_catchup = 1;
2070 vcpu->arch.tsc_always_catchup = 1;
2071 } else
2072 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2073}
2074
ba904635
WA		 2075static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076{
2077 return vmcs_read64(TSC_OFFSET);
2078}
2079
6aa8b732 2080/*
99e3e30a 2081 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2082 */
99e3e30a 2083static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2084{
27fc51b2 2085 if (is_guest_mode(vcpu)) {
7991825b 2086 /*
27fc51b2
NHE		 2087 * We're here if L1 chose not to trap WRMSR to TSC. According
2088 * to the spec, this should set L1's TSC; The offset that L1
2089 * set for L2 remains unchanged, and still needs to be added
2090 * to the newly set TSC to get L2's TSC.
7991825b 2091 */
27fc51b2
NHE		 2092 struct vmcs12 *vmcs12;
2093 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094 /* recalculate vmcs02.TSC_OFFSET: */
2095 vmcs12 = get_vmcs12(vcpu);
2096 vmcs_write64(TSC_OFFSET, offset +
2097 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098 vmcs12->tsc_offset : 0));
2099 } else {
489223ed
YY		 2100 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2102 vmcs_write64(TSC_OFFSET, offset);
2103 }
6aa8b732
AK		 2104}
2105
f1e2b260 2106static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2107{
2108 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2109
e48672fa 2110 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2111 if (is_guest_mode(vcpu)) {
2112 /* Even when running L2, the adjustment needs to apply to L1 */
2113 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2114 } else
2115 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116 offset + adjustment);
e48672fa
ZA		 2117}
2118
857e4099
JR		 2119static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120{
2121 return target_tsc - native_read_tsc();
2122}
2123
801d3424
NHE		 2124static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125{
2126 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128}
2129
2130/*
2131 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133 * all guests if the "nested" module option is off, and can also be disabled
2134 * for a single guest by disabling its VMX cpuid bit.
2135 */
2136static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137{
2138 return nested && guest_cpuid_has_vmx(vcpu);
2139}
2140
b87a51ae
NHE		 2141/*
2142 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143 * returned for the various VMX controls MSRs when nested VMX is enabled.
2144 * The same values should also be used to verify that vmcs12 control fields are
2145 * valid during nested entry from L1 to L2.
2146 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148 * bit in the high half is on if the corresponding bit in the control field
2149 * may be on. See also vmx_control_verify().
2150 * TODO: allow these variables to be modified (downgraded) by module options
2151 * or other means.
2152 */
2153static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2158static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2159static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2160static __init void nested_vmx_setup_ctls_msrs(void)
2161{
2162 /*
2163 * Note that as a general rule, the high half of the MSRs (bits in
2164 * the control fields which may be 1) should be initialized by the
2165 * intersection of the underlying hardware's MSR (i.e., features which
2166 * can be supported) and the list of features we want to expose -
2167 * because they are known to be properly supported in our code.
2168 * Also, usually, the low half of the MSRs (bits which must be 1) can
2169 * be set to 0, meaning that L1 may turn off any of these bits. The
2170 * reason is that if one of these bits is necessary, it will appear
2171 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172 * fields of vmcs01 and vmcs02, will turn these bits off - and
2173 * nested_vmx_exit_handled() will not pass related exits to L1.
2174 * These rules have exceptions below.
2175 */
2176
2177 /* pin-based controls */
eabeaacc
JK		 2178 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2179 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2180 /*
2181 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2183 */
eabeaacc
JK		 2184 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2185 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2186 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2187 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2188 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2189
33fb20c3
JK		 2190 /*
2191 * Exit controls
2192 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2193 * 17 must be 1.
2194 */
c0dfee58
ACL		 2195 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2196 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2197 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2199 nested_vmx_exit_ctls_high &=
b87a51ae 2200#ifdef CONFIG_X86_64
c0dfee58 2201 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2202#endif
c0dfee58 2203 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
8049d651 2204 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2205 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2206
2207 /* entry controls */
2208 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2209 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2210 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2211 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2212 nested_vmx_entry_ctls_high &=
57435349
JK		 2213#ifdef CONFIG_X86_64
2214 VM_ENTRY_IA32E_MODE |
2215#endif
2216 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2217 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2218 VM_ENTRY_LOAD_IA32_EFER);
57435349 2219
b87a51ae
NHE		 2220 /* cpu-based controls */
2221 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2222 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2223 nested_vmx_procbased_ctls_low = 0;
2224 nested_vmx_procbased_ctls_high &=
2225 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2226 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2227 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2228 CPU_BASED_CR3_STORE_EXITING |
2229#ifdef CONFIG_X86_64
2230 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2231#endif
2232 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2233 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2234 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2235 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2236 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2237 /*
2238 * We can allow some features even when not supported by the
2239 * hardware. For example, L1 can specify an MSR bitmap - and we
2240 * can use it to avoid exits to L1 - even when L0 runs L2
2241 * without MSR bitmaps.
2242 */
2243 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2244
2245 /* secondary cpu-based controls */
2246 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2247 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2248 nested_vmx_secondary_ctls_low = 0;
2249 nested_vmx_secondary_ctls_high &=
d6851fbe 2250 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2251 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2252 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2253
afa61f75
NHE		 2254 if (enable_ept) {
2255 /* nested EPT: emulate EPT also to L1 */
2256 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970
JK		 2257 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2258 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2259 nested_vmx_ept_caps &= vmx_capability.ept;
2260 /*
2261 * Since invept is completely emulated we support both global
2262 * and context invalidation independent of what host cpu
2263 * supports
2264 */
2265 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2266 VMX_EPT_EXTENT_CONTEXT_BIT;
2267 } else
2268 nested_vmx_ept_caps = 0;
2269
c18911a2
JK		 2270 /* miscellaneous data */
2271 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2272 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2273 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2274 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2275}
2276
2277static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2278{
2279 /*
2280 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2281 */
2282 return ((control & high) | low) == control;
2283}
2284
2285static inline u64 vmx_control_msr(u32 low, u32 high)
2286{
2287 return low | ((u64)high << 32);
2288}
2289
2290/*
2291 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2292 * also let it use VMX-specific MSRs.
2293 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2294 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2295 * like all other MSRs).
2296 */
2297static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2298{
2299 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2300 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2301 /*
2302 * According to the spec, processors which do not support VMX
2303 * should throw a #GP(0) when VMX capability MSRs are read.
2304 */
2305 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2306 return 1;
2307 }
2308
2309 switch (msr_index) {
2310 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2311 if (nested_vmx_allowed(vcpu)) {
2312 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2313 break;
2314 }
2315 return 0;
b87a51ae
NHE		 2316 case MSR_IA32_VMX_BASIC:
2317 /*
2318 * This MSR reports some information about VMX support. We
2319 * should return information about the VMX we emulate for the
2320 * guest, and the VMCS structure we give it - not about the
2321 * VMX support of the underlying hardware.
2322 */
2323 *pdata = VMCS12_REVISION |
2324 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2325 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2326 break;
2327 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2328 case MSR_IA32_VMX_PINBASED_CTLS:
2329 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2330 nested_vmx_pinbased_ctls_high);
2331 break;
2332 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2333 case MSR_IA32_VMX_PROCBASED_CTLS:
2334 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2335 nested_vmx_procbased_ctls_high);
2336 break;
2337 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2338 case MSR_IA32_VMX_EXIT_CTLS:
2339 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2340 nested_vmx_exit_ctls_high);
2341 break;
2342 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2343 case MSR_IA32_VMX_ENTRY_CTLS:
2344 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2345 nested_vmx_entry_ctls_high);
2346 break;
2347 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2348 *pdata = vmx_control_msr(nested_vmx_misc_low,
2349 nested_vmx_misc_high);
b87a51ae
NHE		 2350 break;
2351 /*
2352 * These MSRs specify bits which the guest must keep fixed (on or off)
2353 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2354 * We picked the standard core2 setting.
2355 */
2356#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2357#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2358 case MSR_IA32_VMX_CR0_FIXED0:
2359 *pdata = VMXON_CR0_ALWAYSON;
2360 break;
2361 case MSR_IA32_VMX_CR0_FIXED1:
2362 *pdata = -1ULL;
2363 break;
2364 case MSR_IA32_VMX_CR4_FIXED0:
2365 *pdata = VMXON_CR4_ALWAYSON;
2366 break;
2367 case MSR_IA32_VMX_CR4_FIXED1:
2368 *pdata = -1ULL;
2369 break;
2370 case MSR_IA32_VMX_VMCS_ENUM:
2371 *pdata = 0x1f;
2372 break;
2373 case MSR_IA32_VMX_PROCBASED_CTLS2:
2374 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2375 nested_vmx_secondary_ctls_high);
2376 break;
2377 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2378 /* Currently, no nested vpid support */
2379 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2380 break;
2381 default:
2382 return 0;
2383 }
2384
2385 return 1;
2386}
2387
b3897a49 2388static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2389{
b3897a49
NHE		 2390 u32 msr_index = msr_info->index;
2391 u64 data = msr_info->data;
2392 bool host_initialized = msr_info->host_initiated;
2393
b87a51ae
NHE		 2394 if (!nested_vmx_allowed(vcpu))
2395 return 0;
2396
b3897a49
NHE		 2397 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2398 if (!host_initialized &&
2399 to_vmx(vcpu)->nested.msr_ia32_feature_control
2400 & FEATURE_CONTROL_LOCKED)
2401 return 0;
2402 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2403 return 1;
b3897a49
NHE		 2404 }
2405
b87a51ae
NHE		 2406 /*
2407 * No need to treat VMX capability MSRs specially: If we don't handle
2408 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2409 */
2410 return 0;
2411}
2412
6aa8b732
AK		 2413/*
2414 * Reads an msr value (of 'msr_index') into 'pdata'.
2415 * Returns 0 on success, non-0 otherwise.
2416 * Assumes vcpu_load() was already called.
2417 */
2418static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2419{
2420 u64 data;
26bb0981 2421 struct shared_msr_entry *msr;
6aa8b732
AK		 2422
2423 if (!pdata) {
2424 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2425 return -EINVAL;
2426 }
2427
2428 switch (msr_index) {
05b3e0c2 2429#ifdef CONFIG_X86_64
6aa8b732
AK		 2430 case MSR_FS_BASE:
2431 data = vmcs_readl(GUEST_FS_BASE);
2432 break;
2433 case MSR_GS_BASE:
2434 data = vmcs_readl(GUEST_GS_BASE);
2435 break;
44ea2b17
AK		 2436 case MSR_KERNEL_GS_BASE:
2437 vmx_load_host_state(to_vmx(vcpu));
2438 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2439 break;
26bb0981 2440#endif
6aa8b732 2441 case MSR_EFER:
3bab1f5d 2442 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2443 case MSR_IA32_TSC:
6aa8b732
AK		 2444 data = guest_read_tsc();
2445 break;
2446 case MSR_IA32_SYSENTER_CS:
2447 data = vmcs_read32(GUEST_SYSENTER_CS);
2448 break;
2449 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2450 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2451 break;
2452 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2453 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2454 break;
4e47c7a6
SY		 2455 case MSR_TSC_AUX:
2456 if (!to_vmx(vcpu)->rdtscp_enabled)
2457 return 1;
2458 /* Otherwise falls through */
6aa8b732 2459 default:
b87a51ae
NHE		 2460 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2461 return 0;
8b9cf98c 2462 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2463 if (msr) {
2464 data = msr->data;
2465 break;
6aa8b732 2466 }
3bab1f5d 2467 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2468 }
2469
2470 *pdata = data;
2471 return 0;
2472}
2473
2474/*
2475 * Writes msr value into into the appropriate "register".
2476 * Returns 0 on success, non-0 otherwise.
2477 * Assumes vcpu_load() was already called.
2478 */
8fe8ab46 2479static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2480{
a2fa3e9f 2481 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2482 struct shared_msr_entry *msr;
2cc51560 2483 int ret = 0;
8fe8ab46
WA		 2484 u32 msr_index = msr_info->index;
2485 u64 data = msr_info->data;
2cc51560 2486
6aa8b732 2487 switch (msr_index) {
3bab1f5d 2488 case MSR_EFER:
8fe8ab46 2489 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2490 break;
16175a79 2491#ifdef CONFIG_X86_64
6aa8b732 2492 case MSR_FS_BASE:
2fb92db1 2493 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2494 vmcs_writel(GUEST_FS_BASE, data);
2495 break;
2496 case MSR_GS_BASE:
2fb92db1 2497 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2498 vmcs_writel(GUEST_GS_BASE, data);
2499 break;
44ea2b17
AK		 2500 case MSR_KERNEL_GS_BASE:
2501 vmx_load_host_state(vmx);
2502 vmx->msr_guest_kernel_gs_base = data;
2503 break;
6aa8b732
AK		 2504#endif
2505 case MSR_IA32_SYSENTER_CS:
2506 vmcs_write32(GUEST_SYSENTER_CS, data);
2507 break;
2508 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2509 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2510 break;
2511 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2512 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2513 break;
af24a4e4 2514 case MSR_IA32_TSC:
8fe8ab46 2515 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2516 break;
468d472f
SY		 2517 case MSR_IA32_CR_PAT:
2518 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2519 vmcs_write64(GUEST_IA32_PAT, data);
2520 vcpu->arch.pat = data;
2521 break;
2522 }
8fe8ab46 2523 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2524 break;
ba904635
WA		 2525 case MSR_IA32_TSC_ADJUST:
2526 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2527 break;
2528 case MSR_TSC_AUX:
2529 if (!vmx->rdtscp_enabled)
2530 return 1;
2531 /* Check reserved bit, higher 32 bits should be zero */
2532 if ((data >> 32) != 0)
2533 return 1;
2534 /* Otherwise falls through */
6aa8b732 2535 default:
b3897a49 2536 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2537 break;
8b9cf98c 2538 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2539 if (msr) {
2540 msr->data = data;
2225fd56
AK		 2541 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2542 preempt_disable();
9ee73970
AK		 2543 kvm_set_shared_msr(msr->index, msr->data,
2544 msr->mask);
2225fd56
AK		 2545 preempt_enable();
2546 }
3bab1f5d 2547 break;
6aa8b732 2548 }
8fe8ab46 2549 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2550 }
2551
2cc51560 2552 return ret;
6aa8b732
AK		 2553}
2554
5fdbf976 2555static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2556{
5fdbf976
MT		 2557 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2558 switch (reg) {
2559 case VCPU_REGS_RSP:
2560 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2561 break;
2562 case VCPU_REGS_RIP:
2563 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2564 break;
6de4f3ad
AK		 2565 case VCPU_EXREG_PDPTR:
2566 if (enable_ept)
2567 ept_save_pdptrs(vcpu);
2568 break;
5fdbf976
MT		 2569 default:
2570 break;
2571 }
6aa8b732
AK		 2572}
2573
6aa8b732
AK		 2574static __init int cpu_has_kvm_support(void)
2575{
6210e37b 2576 return cpu_has_vmx();
6aa8b732
AK		 2577}
2578
2579static __init int vmx_disabled_by_bios(void)
2580{
2581 u64 msr;
2582
2583 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2584 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2585 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2586 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2587 && tboot_enabled())
2588 return 1;
23f3e991 2589 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2590 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2591 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2592 && !tboot_enabled()) {
2593 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2594 "activate TXT before enabling KVM\n");
cafd6659 2595 return 1;
f9335afe 2596 }
23f3e991
JC		 2597 /* launched w/o TXT and VMX disabled */
2598 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2599 && !tboot_enabled())
2600 return 1;
cafd6659
SW		 2601 }
2602
2603 return 0;
6aa8b732
AK		 2604}
2605
7725b894
DX		 2606static void kvm_cpu_vmxon(u64 addr)
2607{
2608 asm volatile (ASM_VMX_VMXON_RAX
2609 : : "a"(&addr), "m"(addr)
2610 : "memory", "cc");
2611}
2612
10474ae8 2613static int hardware_enable(void *garbage)
6aa8b732
AK		 2614{
2615 int cpu = raw_smp_processor_id();
2616 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2617 u64 old, test_bits;
6aa8b732 2618
10474ae8
AG		 2619 if (read_cr4() & X86_CR4_VMXE)
2620 return -EBUSY;
2621
d462b819 2622 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2623
2624 /*
2625 * Now we can enable the vmclear operation in kdump
2626 * since the loaded_vmcss_on_cpu list on this cpu
2627 * has been initialized.
2628 *
2629 * Though the cpu is not in VMX operation now, there
2630 * is no problem to enable the vmclear operation
2631 * for the loaded_vmcss_on_cpu list is empty!
2632 */
2633 crash_enable_local_vmclear(cpu);
2634
6aa8b732 2635 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2636
2637 test_bits = FEATURE_CONTROL_LOCKED;
2638 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2639 if (tboot_enabled())
2640 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2641
2642 if ((old & test_bits) != test_bits) {
6aa8b732 2643 /* enable and lock */
cafd6659
SW		 2644 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2645 }
66aee91a 2646 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2647
4610c9cc
DX		 2648 if (vmm_exclusive) {
2649 kvm_cpu_vmxon(phys_addr);
2650 ept_sync_global();
2651 }
10474ae8 2652
357d1226 2653 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2654
10474ae8 2655 return 0;
6aa8b732
AK		 2656}
2657
d462b819 2658static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2659{
2660 int cpu = raw_smp_processor_id();
d462b819 2661 struct loaded_vmcs *v, *n;
543e4243 2662
d462b819
NHE		 2663 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2664 loaded_vmcss_on_cpu_link)
2665 __loaded_vmcs_clear(v);
543e4243
AK		 2666}
2667
710ff4a8
EH		 2668
2669/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2670 * tricks.
2671 */
2672static void kvm_cpu_vmxoff(void)
6aa8b732 2673{
4ecac3fd 2674 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2675}
2676
710ff4a8
EH		 2677static void hardware_disable(void *garbage)
2678{
4610c9cc 2679 if (vmm_exclusive) {
d462b819 2680 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2681 kvm_cpu_vmxoff();
2682 }
7725b894 2683 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2684}
2685
1c3d14fe 2686static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2687 u32 msr, u32 *result)
1c3d14fe
YS		 2688{
2689 u32 vmx_msr_low, vmx_msr_high;
2690 u32 ctl = ctl_min | ctl_opt;
2691
2692 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2693
2694 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2695 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2696
2697 /* Ensure minimum (required) set of control bits are supported. */
2698 if (ctl_min & ~ctl)
002c7f7c 2699 return -EIO;
1c3d14fe
YS		 2700
2701 *result = ctl;
2702 return 0;
2703}
2704
110312c8
AK		 2705static __init bool allow_1_setting(u32 msr, u32 ctl)
2706{
2707 u32 vmx_msr_low, vmx_msr_high;
2708
2709 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2710 return vmx_msr_high & ctl;
2711}
2712
002c7f7c 2713static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2714{
2715 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2716 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2717 u32 _pin_based_exec_control = 0;
2718 u32 _cpu_based_exec_control = 0;
f78e0e2e 2719 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2720 u32 _vmexit_control = 0;
2721 u32 _vmentry_control = 0;
2722
10166744 2723 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2724#ifdef CONFIG_X86_64
2725 CPU_BASED_CR8_LOAD_EXITING |
2726 CPU_BASED_CR8_STORE_EXITING |
2727#endif
d56f546d
SY		 2728 CPU_BASED_CR3_LOAD_EXITING |
2729 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2730 CPU_BASED_USE_IO_BITMAPS |
2731 CPU_BASED_MOV_DR_EXITING |
a7052897 2732 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2733 CPU_BASED_MWAIT_EXITING |
2734 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2735 CPU_BASED_INVLPG_EXITING |
2736 CPU_BASED_RDPMC_EXITING;
443381a8 2737
f78e0e2e 2738 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2739 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2740 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2741 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2742 &_cpu_based_exec_control) < 0)
002c7f7c 2743 return -EIO;
6e5d865c
YS		 2744#ifdef CONFIG_X86_64
2745 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2746 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2747 ~CPU_BASED_CR8_STORE_EXITING;
2748#endif
f78e0e2e 2749 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2750 min2 = 0;
2751 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2752 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2753 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2754 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2755 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2756 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2757 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2758 SECONDARY_EXEC_RDTSCP |
83d4c286 2759 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2760 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2761 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2762 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2763 if (adjust_vmx_controls(min2, opt2,
2764 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2765 &_cpu_based_2nd_exec_control) < 0)
2766 return -EIO;
2767 }
2768#ifndef CONFIG_X86_64
2769 if (!(_cpu_based_2nd_exec_control &
2770 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2771 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2772#endif
83d4c286
YZ		 2773
2774 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2775 _cpu_based_2nd_exec_control &= ~(
8d14695f 2776 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2777 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2778 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2779
d56f546d 2780 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2781 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2782 enabled */
5fff7d27
GN		 2783 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2784 CPU_BASED_CR3_STORE_EXITING |
2785 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2786 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2787 vmx_capability.ept, vmx_capability.vpid);
2788 }
1c3d14fe
YS		 2789
2790 min = 0;
2791#ifdef CONFIG_X86_64
2792 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2793#endif
a547c6db
YZ		 2794 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2795 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2796 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2797 &_vmexit_control) < 0)
002c7f7c 2798 return -EIO;
1c3d14fe 2799
01e439be
YZ		 2800 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2801 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2802 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2803 &_pin_based_exec_control) < 0)
2804 return -EIO;
2805
2806 if (!(_cpu_based_2nd_exec_control &
2807 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2808 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2809 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2810
468d472f
SY		 2811 min = 0;
2812 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2813 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2814 &_vmentry_control) < 0)
002c7f7c 2815 return -EIO;
6aa8b732 2816
c68876fd 2817 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2818
2819 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2820 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2821 return -EIO;
1c3d14fe
YS		 2822
2823#ifdef CONFIG_X86_64
2824 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2825 if (vmx_msr_high & (1u<<16))
002c7f7c 2826 return -EIO;
1c3d14fe
YS		 2827#endif
2828
2829 /* Require Write-Back (WB) memory type for VMCS accesses. */
2830 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2831 return -EIO;
1c3d14fe 2832
002c7f7c
YS		 2833 vmcs_conf->size = vmx_msr_high & 0x1fff;
2834 vmcs_conf->order = get_order(vmcs_config.size);
2835 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2836
002c7f7c
YS		 2837 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2838 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2839 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2840 vmcs_conf->vmexit_ctrl = _vmexit_control;
2841 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2842
110312c8
AK		 2843 cpu_has_load_ia32_efer =
2844 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2845 VM_ENTRY_LOAD_IA32_EFER)
2846 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2847 VM_EXIT_LOAD_IA32_EFER);
2848
8bf00a52
GN		 2849 cpu_has_load_perf_global_ctrl =
2850 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2851 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2852 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2853 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2854
2855 /*
2856 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2857 * but due to arrata below it can't be used. Workaround is to use
2858 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2859 *
2860 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2861 *
2862 * AAK155 (model 26)
2863 * AAP115 (model 30)
2864 * AAT100 (model 37)
2865 * BC86,AAY89,BD102 (model 44)
2866 * BA97 (model 46)
2867 *
2868 */
2869 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2870 switch (boot_cpu_data.x86_model) {
2871 case 26:
2872 case 30:
2873 case 37:
2874 case 44:
2875 case 46:
2876 cpu_has_load_perf_global_ctrl = false;
2877 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2878 "does not work properly. Using workaround\n");
2879 break;
2880 default:
2881 break;
2882 }
2883 }
2884
1c3d14fe 2885 return 0;
c68876fd 2886}
6aa8b732
AK		 2887
2888static struct vmcs *alloc_vmcs_cpu(int cpu)
2889{
2890 int node = cpu_to_node(cpu);
2891 struct page *pages;
2892 struct vmcs *vmcs;
2893
6484eb3e 2894 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2895 if (!pages)
2896 return NULL;
2897 vmcs = page_address(pages);
1c3d14fe
YS		 2898 memset(vmcs, 0, vmcs_config.size);
2899 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2900 return vmcs;
2901}
2902
2903static struct vmcs *alloc_vmcs(void)
2904{
d3b2c338 2905 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2906}
2907
2908static void free_vmcs(struct vmcs *vmcs)
2909{
1c3d14fe 2910 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2911}
2912
d462b819
NHE		 2913/*
2914 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2915 */
2916static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2917{
2918 if (!loaded_vmcs->vmcs)
2919 return;
2920 loaded_vmcs_clear(loaded_vmcs);
2921 free_vmcs(loaded_vmcs->vmcs);
2922 loaded_vmcs->vmcs = NULL;
2923}
2924
39959588 2925static void free_kvm_area(void)
6aa8b732
AK		 2926{
2927 int cpu;
2928
3230bb47 2929 for_each_possible_cpu(cpu) {
6aa8b732 2930 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2931 per_cpu(vmxarea, cpu) = NULL;
2932 }
6aa8b732
AK		 2933}
2934
6aa8b732
AK		 2935static __init int alloc_kvm_area(void)
2936{
2937 int cpu;
2938
3230bb47 2939 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2940 struct vmcs *vmcs;
2941
2942 vmcs = alloc_vmcs_cpu(cpu);
2943 if (!vmcs) {
2944 free_kvm_area();
2945 return -ENOMEM;
2946 }
2947
2948 per_cpu(vmxarea, cpu) = vmcs;
2949 }
2950 return 0;
2951}
2952
2953static __init int hardware_setup(void)
2954{
002c7f7c
YS		 2955 if (setup_vmcs_config(&vmcs_config) < 0)
2956 return -EIO;
50a37eb4
JR		 2957
2958 if (boot_cpu_has(X86_FEATURE_NX))
2959 kvm_enable_efer_bits(EFER_NX);
2960
93ba03c2
SY		 2961 if (!cpu_has_vmx_vpid())
2962 enable_vpid = 0;
abc4fc58
AG		 2963 if (!cpu_has_vmx_shadow_vmcs())
2964 enable_shadow_vmcs = 0;
93ba03c2 2965
4bc9b982
SY		 2966 if (!cpu_has_vmx_ept() ||
2967 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2968 enable_ept = 0;
3a624e29 2969 enable_unrestricted_guest = 0;
83c3a331 2970 enable_ept_ad_bits = 0;
3a624e29
NK		 2971 }
2972
83c3a331
XH		 2973 if (!cpu_has_vmx_ept_ad_bits())
2974 enable_ept_ad_bits = 0;
2975
3a624e29
NK		 2976 if (!cpu_has_vmx_unrestricted_guest())
2977 enable_unrestricted_guest = 0;
93ba03c2
SY		 2978
2979 if (!cpu_has_vmx_flexpriority())
2980 flexpriority_enabled = 0;
2981
95ba8273
GN		 2982 if (!cpu_has_vmx_tpr_shadow())
2983 kvm_x86_ops->update_cr8_intercept = NULL;
2984
54dee993
MT		 2985 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2986 kvm_disable_largepages();
2987
4b8d54f9
ZE		 2988 if (!cpu_has_vmx_ple())
2989 ple_gap = 0;
2990
01e439be
YZ		 2991 if (!cpu_has_vmx_apicv())
2992 enable_apicv = 0;
c7c9c56c 2993
01e439be 2994 if (enable_apicv)
c7c9c56c 2995 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2996 else {
c7c9c56c 2997 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2998 kvm_x86_ops->deliver_posted_interrupt = NULL;
2999 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3000 }
83d4c286 3001
b87a51ae
NHE		 3002 if (nested)
3003 nested_vmx_setup_ctls_msrs();
3004
6aa8b732
AK		 3005 return alloc_kvm_area();
3006}
3007
3008static __exit void hardware_unsetup(void)
3009{
3010 free_kvm_area();
3011}
3012
14168786
GN		 3013static bool emulation_required(struct kvm_vcpu *vcpu)
3014{
3015 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3016}
3017
91b0aa2c 3018static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3019 struct kvm_segment *save)
6aa8b732 3020{
d99e4152
GN		 3021 if (!emulate_invalid_guest_state) {
3022 /*
3023 * CS and SS RPL should be equal during guest entry according
3024 * to VMX spec, but in reality it is not always so. Since vcpu
3025 * is in the middle of the transition from real mode to
3026 * protected mode it is safe to assume that RPL 0 is a good
3027 * default value.
3028 */
3029 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3030 save->selector &= ~SELECTOR_RPL_MASK;
3031 save->dpl = save->selector & SELECTOR_RPL_MASK;
3032 save->s = 1;
6aa8b732 3033 }
d99e4152 3034 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3035}
3036
3037static void enter_pmode(struct kvm_vcpu *vcpu)
3038{
3039 unsigned long flags;
a89a8fb9 3040 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3041
d99e4152
GN		 3042 /*
3043 * Update real mode segment cache. It may be not up-to-date if sement
3044 * register was written while vcpu was in a guest mode.
3045 */
3046 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3047 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3048 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3049 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3050 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3051 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3052
7ffd92c5 3053 vmx->rmode.vm86_active = 0;
6aa8b732 3054
2fb92db1
AK		 3055 vmx_segment_cache_clear(vmx);
3056
f5f7b2fe 3057 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3058
3059 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3060 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3061 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3062 vmcs_writel(GUEST_RFLAGS, flags);
3063
66aee91a
RR		 3064 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3065 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3066
3067 update_exception_bitmap(vcpu);
3068
91b0aa2c
GN		 3069 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3070 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3071 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3072 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3073 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3074 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3075
3076 /* CPL is always 0 when CPU enters protected mode */
3077 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3078 vmx->cpl = 0;
6aa8b732
AK		 3079}
3080
f5f7b2fe 3081static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3082{
772e0318 3083 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3084 struct kvm_segment var = *save;
3085
3086 var.dpl = 0x3;
3087 if (seg == VCPU_SREG_CS)
3088 var.type = 0x3;
3089
3090 if (!emulate_invalid_guest_state) {
3091 var.selector = var.base >> 4;
3092 var.base = var.base & 0xffff0;
3093 var.limit = 0xffff;
3094 var.g = 0;
3095 var.db = 0;
3096 var.present = 1;
3097 var.s = 1;
3098 var.l = 0;
3099 var.unusable = 0;
3100 var.type = 0x3;
3101 var.avl = 0;
3102 if (save->base & 0xf)
3103 printk_once(KERN_WARNING "kvm: segment base is not "
3104 "paragraph aligned when entering "
3105 "protected mode (seg=%d)", seg);
3106 }
6aa8b732 3107
d99e4152
GN		 3108 vmcs_write16(sf->selector, var.selector);
3109 vmcs_write32(sf->base, var.base);
3110 vmcs_write32(sf->limit, var.limit);
3111 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3112}
3113
3114static void enter_rmode(struct kvm_vcpu *vcpu)
3115{
3116 unsigned long flags;
a89a8fb9 3117 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3118
f5f7b2fe
AK		 3119 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3121 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3123 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3126
7ffd92c5 3127 vmx->rmode.vm86_active = 1;
6aa8b732 3128
776e58ea
GN		 3129 /*
3130 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3131 * vcpu. Warn the user that an update is overdue.
776e58ea 3132 */
4918c6ca 3133 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3134 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3135 "called before entering vcpu\n");
776e58ea 3136
2fb92db1
AK		 3137 vmx_segment_cache_clear(vmx);
3138
4918c6ca 3139 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3140 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3141 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3142
3143 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3144 vmx->rmode.save_rflags = flags;
6aa8b732 3145
053de044 3146 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3147
3148 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3149 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3150 update_exception_bitmap(vcpu);
3151
d99e4152
GN		 3152 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3153 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3154 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3155 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3156 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3157 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3158
8668a3c4 3159 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3160}
3161
401d10de
AS		 3162static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3163{
3164 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3165 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3166
3167 if (!msr)
3168 return;
401d10de 3169
44ea2b17
AK		 3170 /*
3171 * Force kernel_gs_base reloading before EFER changes, as control
3172 * of this msr depends on is_long_mode().
3173 */
3174 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3175 vcpu->arch.efer = efer;
401d10de
AS		 3176 if (efer & EFER_LMA) {
3177 vmcs_write32(VM_ENTRY_CONTROLS,
3178 vmcs_read32(VM_ENTRY_CONTROLS) |
3179 VM_ENTRY_IA32E_MODE);
3180 msr->data = efer;
3181 } else {
3182 vmcs_write32(VM_ENTRY_CONTROLS,
3183 vmcs_read32(VM_ENTRY_CONTROLS) &
3184 ~VM_ENTRY_IA32E_MODE);
3185
3186 msr->data = efer & ~EFER_LME;
3187 }
3188 setup_msrs(vmx);
3189}
3190
05b3e0c2 3191#ifdef CONFIG_X86_64
6aa8b732
AK		 3192
3193static void enter_lmode(struct kvm_vcpu *vcpu)
3194{
3195 u32 guest_tr_ar;
3196
2fb92db1
AK		 3197 vmx_segment_cache_clear(to_vmx(vcpu));
3198
6aa8b732
AK		 3199 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3200 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3201 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3202 __func__);
6aa8b732
AK		 3203 vmcs_write32(GUEST_TR_AR_BYTES,
3204 (guest_tr_ar & ~AR_TYPE_MASK)
3205 | AR_TYPE_BUSY_64_TSS);
3206 }
da38f438 3207 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3208}
3209
3210static void exit_lmode(struct kvm_vcpu *vcpu)
3211{
6aa8b732
AK		 3212 vmcs_write32(VM_ENTRY_CONTROLS,
3213 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3214 & ~VM_ENTRY_IA32E_MODE);
da38f438 3215 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3216}
3217
3218#endif
3219
2384d2b3
SY		 3220static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3221{
b9d762fa 3222 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3223 if (enable_ept) {
3224 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3225 return;
4e1096d2 3226 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3227 }
2384d2b3
SY		 3228}
3229
e8467fda
AK		 3230static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3231{
3232 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3233
3234 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3235 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3236}
3237
aff48baa
AK		 3238static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3239{
3240 if (enable_ept && is_paging(vcpu))
3241 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3242 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3243}
3244
25c4c276 3245static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3246{
fc78f519
AK		 3247 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3248
3249 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3250 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3251}
3252
1439442c
SY		 3253static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3254{
6de4f3ad
AK		 3255 if (!test_bit(VCPU_EXREG_PDPTR,
3256 (unsigned long *)&vcpu->arch.regs_dirty))
3257 return;
3258
1439442c 3259 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3260 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3261 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3262 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3263 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3264 }
3265}
3266
8f5d549f
AK		 3267static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3268{
3269 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3270 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3271 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3272 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3273 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3274 }
6de4f3ad
AK		 3275
3276 __set_bit(VCPU_EXREG_PDPTR,
3277 (unsigned long *)&vcpu->arch.regs_avail);
3278 __set_bit(VCPU_EXREG_PDPTR,
3279 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3280}
3281
5e1746d6 3282static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3283
3284static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3285 unsigned long cr0,
3286 struct kvm_vcpu *vcpu)
3287{
5233dd51
MT		 3288 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3289 vmx_decache_cr3(vcpu);
1439442c
SY		 3290 if (!(cr0 & X86_CR0_PG)) {
3291 /* From paging/starting to nonpaging */
3292 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3293 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3294 (CPU_BASED_CR3_LOAD_EXITING |
3295 CPU_BASED_CR3_STORE_EXITING));
3296 vcpu->arch.cr0 = cr0;
fc78f519 3297 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3298 } else if (!is_paging(vcpu)) {
3299 /* From nonpaging to paging */
3300 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3301 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3302 ~(CPU_BASED_CR3_LOAD_EXITING |
3303 CPU_BASED_CR3_STORE_EXITING));
3304 vcpu->arch.cr0 = cr0;
fc78f519 3305 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3306 }
95eb84a7
SY		 3307
3308 if (!(cr0 & X86_CR0_WP))
3309 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3310}
3311
6aa8b732
AK		 3312static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3313{
7ffd92c5 3314 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3315 unsigned long hw_cr0;
3316
5037878e 3317 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3318 if (enable_unrestricted_guest)
5037878e 3319 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3320 else {
5037878e 3321 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3322
218e763f
GN		 3323 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3324 enter_pmode(vcpu);
6aa8b732 3325
218e763f
GN		 3326 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3327 enter_rmode(vcpu);
3328 }
6aa8b732 3329
05b3e0c2 3330#ifdef CONFIG_X86_64
f6801dff 3331 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3332 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3333 enter_lmode(vcpu);
707d92fa 3334 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3335 exit_lmode(vcpu);
3336 }
3337#endif
3338
089d034e 3339 if (enable_ept)
1439442c
SY		 3340 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3341
02daab21 3342 if (!vcpu->fpu_active)
81231c69 3343 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3344
6aa8b732 3345 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3346 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3347 vcpu->arch.cr0 = cr0;
14168786
GN		 3348
3349 /* depends on vcpu->arch.cr0 to be set to a new value */
3350 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3351}
3352
1439442c
SY		 3353static u64 construct_eptp(unsigned long root_hpa)
3354{
3355 u64 eptp;
3356
3357 /* TODO write the value reading from MSR */
3358 eptp = VMX_EPT_DEFAULT_MT |
3359 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3360 if (enable_ept_ad_bits)
3361 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3362 eptp |= (root_hpa & PAGE_MASK);
3363
3364 return eptp;
3365}
3366
6aa8b732
AK		 3367static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3368{
1439442c
SY		 3369 unsigned long guest_cr3;
3370 u64 eptp;
3371
3372 guest_cr3 = cr3;
089d034e 3373 if (enable_ept) {
1439442c
SY		 3374 eptp = construct_eptp(cr3);
3375 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3376 if (is_paging(vcpu) || is_guest_mode(vcpu))
3377 guest_cr3 = kvm_read_cr3(vcpu);
3378 else
3379 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3380 ept_load_pdptrs(vcpu);
1439442c
SY		 3381 }
3382
2384d2b3 3383 vmx_flush_tlb(vcpu);
1439442c 3384 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3385}
3386
5e1746d6 3387static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3388{
7ffd92c5 3389 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3390 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3391
5e1746d6
NHE		 3392 if (cr4 & X86_CR4_VMXE) {
3393 /*
3394 * To use VMXON (and later other VMX instructions), a guest
3395 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3396 * So basically the check on whether to allow nested VMX
3397 * is here.
3398 */
3399 if (!nested_vmx_allowed(vcpu))
3400 return 1;
1a0d74e6
JK		 3401 }
3402 if (to_vmx(vcpu)->nested.vmxon &&
3403 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3404 return 1;
3405
ad312c7c 3406 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3407 if (enable_ept) {
3408 if (!is_paging(vcpu)) {
3409 hw_cr4 &= ~X86_CR4_PAE;
3410 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3411 /*
3412 * SMEP is disabled if CPU is in non-paging mode in
3413 * hardware. However KVM always uses paging mode to
3414 * emulate guest non-paging mode with TDP.
3415 * To emulate this behavior, SMEP needs to be manually
3416 * disabled when guest switches to non-paging mode.
3417 */
3418 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3419 } else if (!(cr4 & X86_CR4_PAE)) {
3420 hw_cr4 &= ~X86_CR4_PAE;
3421 }
3422 }
1439442c
SY		 3423
3424 vmcs_writel(CR4_READ_SHADOW, cr4);
3425 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3426 return 0;
6aa8b732
AK		 3427}
3428
6aa8b732
AK		 3429static void vmx_get_segment(struct kvm_vcpu *vcpu,
3430 struct kvm_segment *var, int seg)
3431{
a9179499 3432 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3433 u32 ar;
3434
c6ad1153 3435 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3436 *var = vmx->rmode.segs[seg];
a9179499 3437 if (seg == VCPU_SREG_TR
2fb92db1 3438 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3439 return;
1390a28b
AK		 3440 var->base = vmx_read_guest_seg_base(vmx, seg);
3441 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3442 return;
a9179499 3443 }
2fb92db1
AK		 3444 var->base = vmx_read_guest_seg_base(vmx, seg);
3445 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3446 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3447 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3448 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3449 var->type = ar & 15;
3450 var->s = (ar >> 4) & 1;
3451 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3452 /*
3453 * Some userspaces do not preserve unusable property. Since usable
3454 * segment has to be present according to VMX spec we can use present
3455 * property to amend userspace bug by making unusable segment always
3456 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3457 * segment as unusable.
3458 */
3459 var->present = !var->unusable;
6aa8b732
AK		 3460 var->avl = (ar >> 12) & 1;
3461 var->l = (ar >> 13) & 1;
3462 var->db = (ar >> 14) & 1;
3463 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3464}
3465
a9179499
AK		 3466static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3467{
a9179499
AK		 3468 struct kvm_segment s;
3469
3470 if (to_vmx(vcpu)->rmode.vm86_active) {
3471 vmx_get_segment(vcpu, &s, seg);
3472 return s.base;
3473 }
2fb92db1 3474 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3475}
3476
b09408d0 3477static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3478{
b09408d0
MT		 3479 struct vcpu_vmx *vmx = to_vmx(vcpu);
3480
3eeb3288 3481 if (!is_protmode(vcpu))
2e4d2653
IE		 3482 return 0;
3483
f4c63e5d
AK		 3484 if (!is_long_mode(vcpu)
3485 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3486 return 3;
3487
69c73028
AK		 3488 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3489 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3490 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3491 }
d881e6f6
AK		 3492
3493 return vmx->cpl;
69c73028
AK		 3494}
3495
3496
653e3108 3497static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3498{
6aa8b732
AK		 3499 u32 ar;
3500
f0495f9b 3501 if (var->unusable || !var->present)
6aa8b732
AK		 3502 ar = 1 << 16;
3503 else {
3504 ar = var->type & 15;
3505 ar |= (var->s & 1) << 4;
3506 ar |= (var->dpl & 3) << 5;
3507 ar |= (var->present & 1) << 7;
3508 ar |= (var->avl & 1) << 12;
3509 ar |= (var->l & 1) << 13;
3510 ar |= (var->db & 1) << 14;
3511 ar |= (var->g & 1) << 15;
3512 }
653e3108
AK		 3513
3514 return ar;
3515}
3516
3517static void vmx_set_segment(struct kvm_vcpu *vcpu,
3518 struct kvm_segment *var, int seg)
3519{
7ffd92c5 3520 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3521 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3522
2fb92db1 3523 vmx_segment_cache_clear(vmx);
2f143240
GN		 3524 if (seg == VCPU_SREG_CS)
3525 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3526
1ecd50a9
GN		 3527 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3528 vmx->rmode.segs[seg] = *var;
3529 if (seg == VCPU_SREG_TR)
3530 vmcs_write16(sf->selector, var->selector);
3531 else if (var->s)
3532 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3533 goto out;
653e3108 3534 }
1ecd50a9 3535
653e3108
AK		 3536 vmcs_writel(sf->base, var->base);
3537 vmcs_write32(sf->limit, var->limit);
3538 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3539
3540 /*
3541 * Fix the "Accessed" bit in AR field of segment registers for older
3542 * qemu binaries.
3543 * IA32 arch specifies that at the time of processor reset the
3544 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3545 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3546 * state vmexit when "unrestricted guest" mode is turned on.
3547 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3548 * tree. Newer qemu binaries with that qemu fix would not need this
3549 * kvm hack.
3550 */
3551 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3552 var->type |= 0x1; /* Accessed */
3a624e29 3553
f924d66d 3554 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3555
3556out:
14168786 3557 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3558}
3559
6aa8b732
AK		 3560static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3561{
2fb92db1 3562 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3563
3564 *db = (ar >> 14) & 1;
3565 *l = (ar >> 13) & 1;
3566}
3567
89a27f4d 3568static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3569{
89a27f4d
GN		 3570 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3571 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3572}
3573
89a27f4d 3574static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3575{
89a27f4d
GN		 3576 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3577 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3578}
3579
89a27f4d 3580static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3581{
89a27f4d
GN		 3582 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3583 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3584}
3585
89a27f4d 3586static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3587{
89a27f4d
GN		 3588 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3589 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3590}
3591
648dfaa7
MG		 3592static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3593{
3594 struct kvm_segment var;
3595 u32 ar;
3596
3597 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3598 var.dpl = 0x3;
0647f4aa
GN		 3599 if (seg == VCPU_SREG_CS)
3600 var.type = 0x3;
648dfaa7
MG		 3601 ar = vmx_segment_access_rights(&var);
3602
3603 if (var.base != (var.selector << 4))
3604 return false;
89efbed0 3605 if (var.limit != 0xffff)
648dfaa7 3606 return false;
07f42f5f 3607 if (ar != 0xf3)
648dfaa7
MG		 3608 return false;
3609
3610 return true;
3611}
3612
3613static bool code_segment_valid(struct kvm_vcpu *vcpu)
3614{
3615 struct kvm_segment cs;
3616 unsigned int cs_rpl;
3617
3618 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3619 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3620
1872a3f4
AK		 3621 if (cs.unusable)
3622 return false;
648dfaa7
MG		 3623 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3624 return false;
3625 if (!cs.s)
3626 return false;
1872a3f4 3627 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3628 if (cs.dpl > cs_rpl)
3629 return false;
1872a3f4 3630 } else {
648dfaa7
MG		 3631 if (cs.dpl != cs_rpl)
3632 return false;
3633 }
3634 if (!cs.present)
3635 return false;
3636
3637 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3638 return true;
3639}
3640
3641static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3642{
3643 struct kvm_segment ss;
3644 unsigned int ss_rpl;
3645
3646 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3647 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3648
1872a3f4
AK		 3649 if (ss.unusable)
3650 return true;
3651 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3652 return false;
3653 if (!ss.s)
3654 return false;
3655 if (ss.dpl != ss_rpl) /* DPL != RPL */
3656 return false;
3657 if (!ss.present)
3658 return false;
3659
3660 return true;
3661}
3662
3663static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3664{
3665 struct kvm_segment var;
3666 unsigned int rpl;
3667
3668 vmx_get_segment(vcpu, &var, seg);
3669 rpl = var.selector & SELECTOR_RPL_MASK;
3670
1872a3f4
AK		 3671 if (var.unusable)
3672 return true;
648dfaa7
MG		 3673 if (!var.s)
3674 return false;
3675 if (!var.present)
3676 return false;
3677 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3678 if (var.dpl < rpl) /* DPL < RPL */
3679 return false;
3680 }
3681
3682 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3683 * rights flags
3684 */
3685 return true;
3686}
3687
3688static bool tr_valid(struct kvm_vcpu *vcpu)
3689{
3690 struct kvm_segment tr;
3691
3692 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3693
1872a3f4
AK		 3694 if (tr.unusable)
3695 return false;
648dfaa7
MG		 3696 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3697 return false;
1872a3f4 3698 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3699 return false;
3700 if (!tr.present)
3701 return false;
3702
3703 return true;
3704}
3705
3706static bool ldtr_valid(struct kvm_vcpu *vcpu)
3707{
3708 struct kvm_segment ldtr;
3709
3710 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3711
1872a3f4
AK		 3712 if (ldtr.unusable)
3713 return true;
648dfaa7
MG		 3714 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3715 return false;
3716 if (ldtr.type != 2)
3717 return false;
3718 if (!ldtr.present)
3719 return false;
3720
3721 return true;
3722}
3723
3724static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3725{
3726 struct kvm_segment cs, ss;
3727
3728 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3729 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3730
3731 return ((cs.selector & SELECTOR_RPL_MASK) ==
3732 (ss.selector & SELECTOR_RPL_MASK));
3733}
3734
3735/*
3736 * Check if guest state is valid. Returns true if valid, false if
3737 * not.
3738 * We assume that registers are always usable
3739 */
3740static bool guest_state_valid(struct kvm_vcpu *vcpu)
3741{
c5e97c80
GN		 3742 if (enable_unrestricted_guest)
3743 return true;
3744
648dfaa7 3745 /* real mode guest state checks */
f13882d8 3746 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3747 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3748 return false;
3749 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3750 return false;
3751 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3752 return false;
3753 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3754 return false;
3755 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3756 return false;
3757 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3758 return false;
3759 } else {
3760 /* protected mode guest state checks */
3761 if (!cs_ss_rpl_check(vcpu))
3762 return false;
3763 if (!code_segment_valid(vcpu))
3764 return false;
3765 if (!stack_segment_valid(vcpu))
3766 return false;
3767 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3768 return false;
3769 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3770 return false;
3771 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3772 return false;
3773 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3774 return false;
3775 if (!tr_valid(vcpu))
3776 return false;
3777 if (!ldtr_valid(vcpu))
3778 return false;
3779 }
3780 /* TODO:
3781 * - Add checks on RIP
3782 * - Add checks on RFLAGS
3783 */
3784
3785 return true;
3786}
3787
d77c26fc 3788static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3789{
40dcaa9f 3790 gfn_t fn;
195aefde 3791 u16 data = 0;
40dcaa9f 3792 int r, idx, ret = 0;
6aa8b732 3793
40dcaa9f 3794 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3795 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3796 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3797 if (r < 0)
10589a46 3798 goto out;
195aefde 3799 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3800 r = kvm_write_guest_page(kvm, fn++, &data,
3801 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3802 if (r < 0)
10589a46 3803 goto out;
195aefde
IE		 3804 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3805 if (r < 0)
10589a46 3806 goto out;
195aefde
IE		 3807 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3808 if (r < 0)
10589a46 3809 goto out;
195aefde 3810 data = ~0;
10589a46
MT		 3811 r = kvm_write_guest_page(kvm, fn, &data,
3812 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3813 sizeof(u8));
195aefde 3814 if (r < 0)
10589a46
MT		 3815 goto out;
3816
3817 ret = 1;
3818out:
40dcaa9f 3819 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3820 return ret;
6aa8b732
AK		 3821}
3822
b7ebfb05
SY		 3823static int init_rmode_identity_map(struct kvm *kvm)
3824{
40dcaa9f 3825 int i, idx, r, ret;
b7ebfb05
SY		 3826 pfn_t identity_map_pfn;
3827 u32 tmp;
3828
089d034e 3829 if (!enable_ept)
b7ebfb05
SY		 3830 return 1;
3831 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3832 printk(KERN_ERR "EPT: identity-mapping pagetable "
3833 "haven't been allocated!\n");
3834 return 0;
3835 }
3836 if (likely(kvm->arch.ept_identity_pagetable_done))
3837 return 1;
3838 ret = 0;
b927a3ce 3839 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3840 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3841 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3842 if (r < 0)
3843 goto out;
3844 /* Set up identity-mapping pagetable for EPT in real mode */
3845 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3846 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3847 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3848 r = kvm_write_guest_page(kvm, identity_map_pfn,
3849 &tmp, i * sizeof(tmp), sizeof(tmp));
3850 if (r < 0)
3851 goto out;
3852 }
3853 kvm->arch.ept_identity_pagetable_done = true;
3854 ret = 1;
3855out:
40dcaa9f 3856 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3857 return ret;
3858}
3859
6aa8b732
AK		 3860static void seg_setup(int seg)
3861{
772e0318 3862 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3863 unsigned int ar;
6aa8b732
AK		 3864
3865 vmcs_write16(sf->selector, 0);
3866 vmcs_writel(sf->base, 0);
3867 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3868 ar = 0x93;
3869 if (seg == VCPU_SREG_CS)
3870 ar |= 0x08; /* code segment */
3a624e29
NK		 3871
3872 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3873}
3874
f78e0e2e
SY		 3875static int alloc_apic_access_page(struct kvm *kvm)
3876{
4484141a 3877 struct page *page;
f78e0e2e
SY		 3878 struct kvm_userspace_memory_region kvm_userspace_mem;
3879 int r = 0;
3880
79fac95e 3881 mutex_lock(&kvm->slots_lock);
bfc6d222 3882 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3883 goto out;
3884 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3885 kvm_userspace_mem.flags = 0;
3886 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3887 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3888 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3889 if (r)
3890 goto out;
72dc67a6 3891
4484141a
XG		 3892 page = gfn_to_page(kvm, 0xfee00);
3893 if (is_error_page(page)) {
3894 r = -EFAULT;
3895 goto out;
3896 }
3897
3898 kvm->arch.apic_access_page = page;
f78e0e2e 3899out:
79fac95e 3900 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3901 return r;
3902}
3903
b7ebfb05
SY		 3904static int alloc_identity_pagetable(struct kvm *kvm)
3905{
4484141a 3906 struct page *page;
b7ebfb05
SY		 3907 struct kvm_userspace_memory_region kvm_userspace_mem;
3908 int r = 0;
3909
79fac95e 3910 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3911 if (kvm->arch.ept_identity_pagetable)
3912 goto out;
3913 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3914 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3915 kvm_userspace_mem.guest_phys_addr =
3916 kvm->arch.ept_identity_map_addr;
b7ebfb05 3917 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3918 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3919 if (r)
3920 goto out;
3921
4484141a
XG		 3922 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3923 if (is_error_page(page)) {
3924 r = -EFAULT;
3925 goto out;
3926 }
3927
3928 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3929out:
79fac95e 3930 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3931 return r;
3932}
3933
2384d2b3
SY		 3934static void allocate_vpid(struct vcpu_vmx *vmx)
3935{
3936 int vpid;
3937
3938 vmx->vpid = 0;
919818ab 3939 if (!enable_vpid)
2384d2b3
SY		 3940 return;
3941 spin_lock(&vmx_vpid_lock);
3942 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3943 if (vpid < VMX_NR_VPIDS) {
3944 vmx->vpid = vpid;
3945 __set_bit(vpid, vmx_vpid_bitmap);
3946 }
3947 spin_unlock(&vmx_vpid_lock);
3948}
3949
cdbecfc3
LJ		 3950static void free_vpid(struct vcpu_vmx *vmx)
3951{
3952 if (!enable_vpid)
3953 return;
3954 spin_lock(&vmx_vpid_lock);
3955 if (vmx->vpid != 0)
3956 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3957 spin_unlock(&vmx_vpid_lock);
3958}
3959
8d14695f
YZ		 3960#define MSR_TYPE_R 1
3961#define MSR_TYPE_W 2
3962static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3963 u32 msr, int type)
25c5f225 3964{
3e7c73e9 3965 int f = sizeof(unsigned long);
25c5f225
SY		 3966
3967 if (!cpu_has_vmx_msr_bitmap())
3968 return;
3969
3970 /*
3971 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3972 * have the write-low and read-high bitmap offsets the wrong way round.
3973 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3974 */
25c5f225 3975 if (msr <= 0x1fff) {
8d14695f
YZ		 3976 if (type & MSR_TYPE_R)
3977 /* read-low */
3978 __clear_bit(msr, msr_bitmap + 0x000 / f);
3979
3980 if (type & MSR_TYPE_W)
3981 /* write-low */
3982 __clear_bit(msr, msr_bitmap + 0x800 / f);
3983
25c5f225
SY		 3984 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3985 msr &= 0x1fff;
8d14695f
YZ		 3986 if (type & MSR_TYPE_R)
3987 /* read-high */
3988 __clear_bit(msr, msr_bitmap + 0x400 / f);
3989
3990 if (type & MSR_TYPE_W)
3991 /* write-high */
3992 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3993
3994 }
3995}
3996
3997static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3998 u32 msr, int type)
3999{
4000 int f = sizeof(unsigned long);
4001
4002 if (!cpu_has_vmx_msr_bitmap())
4003 return;
4004
4005 /*
4006 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4007 * have the write-low and read-high bitmap offsets the wrong way round.
4008 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4009 */
4010 if (msr <= 0x1fff) {
4011 if (type & MSR_TYPE_R)
4012 /* read-low */
4013 __set_bit(msr, msr_bitmap + 0x000 / f);
4014
4015 if (type & MSR_TYPE_W)
4016 /* write-low */
4017 __set_bit(msr, msr_bitmap + 0x800 / f);
4018
4019 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4020 msr &= 0x1fff;
4021 if (type & MSR_TYPE_R)
4022 /* read-high */
4023 __set_bit(msr, msr_bitmap + 0x400 / f);
4024
4025 if (type & MSR_TYPE_W)
4026 /* write-high */
4027 __set_bit(msr, msr_bitmap + 0xc00 / f);
4028
25c5f225 4029 }
25c5f225
SY		 4030}
4031
5897297b
AK		 4032static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4033{
4034 if (!longmode_only)
8d14695f
YZ		 4035 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4036 msr, MSR_TYPE_R | MSR_TYPE_W);
4037 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4038 msr, MSR_TYPE_R | MSR_TYPE_W);
4039}
4040
4041static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4042{
4043 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4044 msr, MSR_TYPE_R);
4045 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4046 msr, MSR_TYPE_R);
4047}
4048
4049static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4050{
4051 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4052 msr, MSR_TYPE_R);
4053 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4054 msr, MSR_TYPE_R);
4055}
4056
4057static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4058{
4059 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4060 msr, MSR_TYPE_W);
4061 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4062 msr, MSR_TYPE_W);
5897297b
AK		 4063}
4064
01e439be
YZ		 4065static int vmx_vm_has_apicv(struct kvm *kvm)
4066{
4067 return enable_apicv && irqchip_in_kernel(kvm);
4068}
4069
a20ed54d
YZ		 4070/*
4071 * Send interrupt to vcpu via posted interrupt way.
4072 * 1. If target vcpu is running(non-root mode), send posted interrupt
4073 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4074 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4075 * interrupt from PIR in next vmentry.
4076 */
4077static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4078{
4079 struct vcpu_vmx *vmx = to_vmx(vcpu);
4080 int r;
4081
4082 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4083 return;
4084
4085 r = pi_test_and_set_on(&vmx->pi_desc);
4086 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4087#ifdef CONFIG_SMP
a20ed54d
YZ		 4088 if (!r && (vcpu->mode == IN_GUEST_MODE))
4089 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4090 POSTED_INTR_VECTOR);
4091 else
6ffbbbba 4092#endif
a20ed54d
YZ		 4093 kvm_vcpu_kick(vcpu);
4094}
4095
4096static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4097{
4098 struct vcpu_vmx *vmx = to_vmx(vcpu);
4099
4100 if (!pi_test_and_clear_on(&vmx->pi_desc))
4101 return;
4102
4103 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4104}
4105
4106static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4107{
4108 return;
4109}
4110
a3a8ff8e
NHE		 4111/*
4112 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4113 * will not change in the lifetime of the guest.
4114 * Note that host-state that does change is set elsewhere. E.g., host-state
4115 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4116 */
a547c6db 4117static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4118{
4119 u32 low32, high32;
4120 unsigned long tmpl;
4121 struct desc_ptr dt;
4122
b1a74bf8 4123 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4124 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4125 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4126
4127 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4128#ifdef CONFIG_X86_64
4129 /*
4130 * Load null selectors, so we can avoid reloading them in
4131 * __vmx_load_host_state(), in case userspace uses the null selectors
4132 * too (the expected case).
4133 */
4134 vmcs_write16(HOST_DS_SELECTOR, 0);
4135 vmcs_write16(HOST_ES_SELECTOR, 0);
4136#else
a3a8ff8e
NHE		 4137 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4138 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4139#endif
a3a8ff8e
NHE		 4140 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4141 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4142
4143 native_store_idt(&dt);
4144 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4145 vmx->host_idt_base = dt.address;
a3a8ff8e 4146
83287ea4 4147 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4148
4149 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4150 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4151 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4152 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4153
4154 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4155 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4156 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4157 }
4158}
4159
bf8179a0
NHE		 4160static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4161{
4162 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4163 if (enable_ept)
4164 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4165 if (is_guest_mode(&vmx->vcpu))
4166 vmx->vcpu.arch.cr4_guest_owned_bits &=
4167 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4168 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4169}
4170
01e439be
YZ		 4171static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4172{
4173 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4174
4175 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4176 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4177 return pin_based_exec_ctrl;
4178}
4179
bf8179a0
NHE		 4180static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4181{
4182 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4183 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4184 exec_control &= ~CPU_BASED_TPR_SHADOW;
4185#ifdef CONFIG_X86_64
4186 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4187 CPU_BASED_CR8_LOAD_EXITING;
4188#endif
4189 }
4190 if (!enable_ept)
4191 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4192 CPU_BASED_CR3_LOAD_EXITING |
4193 CPU_BASED_INVLPG_EXITING;
4194 return exec_control;
4195}
4196
4197static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4198{
4199 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4200 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4201 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4202 if (vmx->vpid == 0)
4203 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4204 if (!enable_ept) {
4205 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4206 enable_unrestricted_guest = 0;
ad756a16
MJ		 4207 /* Enable INVPCID for non-ept guests may cause performance regression. */
4208 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4209 }
4210 if (!enable_unrestricted_guest)
4211 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4212 if (!ple_gap)
4213 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4214 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4215 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4216 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4217 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4218 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4219 (handle_vmptrld).
4220 We can NOT enable shadow_vmcs here because we don't have yet
4221 a current VMCS12
4222 */
4223 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4224 return exec_control;
4225}
4226
ce88decf
XG		 4227static void ept_set_mmio_spte_mask(void)
4228{
4229 /*
4230 * EPT Misconfigurations can be generated if the value of bits 2:0
4231 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4232 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4233 * spte.
4234 */
885032b9 4235 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4236}
4237
6aa8b732
AK		 4238/*
4239 * Sets up the vmcs for emulated real mode.
4240 */
8b9cf98c 4241static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4242{
2e4ce7f5 4243#ifdef CONFIG_X86_64
6aa8b732 4244 unsigned long a;
2e4ce7f5 4245#endif
6aa8b732 4246 int i;
6aa8b732 4247
6aa8b732 4248 /* I/O */
3e7c73e9
AK		 4249 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4250 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4251
4607c2d7
AG		 4252 if (enable_shadow_vmcs) {
4253 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4254 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4255 }
25c5f225 4256 if (cpu_has_vmx_msr_bitmap())
5897297b 4257 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4258
6aa8b732
AK		 4259 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4260
6aa8b732 4261 /* Control */
01e439be 4262 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4263
bf8179a0 4264 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4265
83ff3b9d 4266 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4267 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4268 vmx_secondary_exec_control(vmx));
83ff3b9d 4269 }
f78e0e2e 4270
01e439be 4271 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4272 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4273 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4274 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4275 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4276
4277 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4278
4279 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4280 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4281 }
4282
4b8d54f9
ZE		 4283 if (ple_gap) {
4284 vmcs_write32(PLE_GAP, ple_gap);
4285 vmcs_write32(PLE_WINDOW, ple_window);
4286 }
4287
c3707958
XG		 4288 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4289 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4290 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4291
9581d442
AK		 4292 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4293 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4294 vmx_set_constant_host_state(vmx);
05b3e0c2 4295#ifdef CONFIG_X86_64
6aa8b732
AK		 4296 rdmsrl(MSR_FS_BASE, a);
4297 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4298 rdmsrl(MSR_GS_BASE, a);
4299 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4300#else
4301 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4302 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4303#endif
4304
2cc51560
ED		 4305 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4306 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4307 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4308 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4309 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4310
468d472f 4311 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4312 u32 msr_low, msr_high;
4313 u64 host_pat;
468d472f
SY		 4314 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4315 host_pat = msr_low | ((u64) msr_high << 32);
4316 /* Write the default value follow host pat */
4317 vmcs_write64(GUEST_IA32_PAT, host_pat);
4318 /* Keep arch.pat sync with GUEST_IA32_PAT */
4319 vmx->vcpu.arch.pat = host_pat;
4320 }
4321
6aa8b732
AK		 4322 for (i = 0; i < NR_VMX_MSR; ++i) {
4323 u32 index = vmx_msr_index[i];
4324 u32 data_low, data_high;
a2fa3e9f 4325 int j = vmx->nmsrs;
6aa8b732
AK		 4326
4327 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4328 continue;
432bd6cb
AK		 4329 if (wrmsr_safe(index, data_low, data_high) < 0)
4330 continue;
26bb0981
AK		 4331 vmx->guest_msrs[j].index = i;
4332 vmx->guest_msrs[j].data = 0;
d5696725 4333 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4334 ++vmx->nmsrs;
6aa8b732 4335 }
6aa8b732 4336
1c3d14fe 4337 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4338
4339 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4340 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4341
e00c8cf2 4342 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4343 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4344
4345 return 0;
4346}
4347
57f252f2 4348static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4349{
4350 struct vcpu_vmx *vmx = to_vmx(vcpu);
4351 u64 msr;
e00c8cf2 4352
7ffd92c5 4353 vmx->rmode.vm86_active = 0;
e00c8cf2 4354
3b86cd99
JK		 4355 vmx->soft_vnmi_blocked = 0;
4356
ad312c7c 4357 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4358 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4359 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4360 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4361 msr |= MSR_IA32_APICBASE_BSP;
4362 kvm_set_apic_base(&vmx->vcpu, msr);
4363
2fb92db1
AK		 4364 vmx_segment_cache_clear(vmx);
4365
5706be0d 4366 seg_setup(VCPU_SREG_CS);
66450a21 4367 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4368 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4369
4370 seg_setup(VCPU_SREG_DS);
4371 seg_setup(VCPU_SREG_ES);
4372 seg_setup(VCPU_SREG_FS);
4373 seg_setup(VCPU_SREG_GS);
4374 seg_setup(VCPU_SREG_SS);
4375
4376 vmcs_write16(GUEST_TR_SELECTOR, 0);
4377 vmcs_writel(GUEST_TR_BASE, 0);
4378 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4379 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4380
4381 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4382 vmcs_writel(GUEST_LDTR_BASE, 0);
4383 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4384 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4385
4386 vmcs_write32(GUEST_SYSENTER_CS, 0);
4387 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4388 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4389
4390 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4391 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4392
e00c8cf2
AK		 4393 vmcs_writel(GUEST_GDTR_BASE, 0);
4394 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4395
4396 vmcs_writel(GUEST_IDTR_BASE, 0);
4397 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4398
443381a8 4399 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4400 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4401 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4402
e00c8cf2
AK		 4403 /* Special registers */
4404 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4405
4406 setup_msrs(vmx);
4407
6aa8b732
AK		 4408 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4409
f78e0e2e
SY		 4410 if (cpu_has_vmx_tpr_shadow()) {
4411 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4412 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4413 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4414 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4415 vmcs_write32(TPR_THRESHOLD, 0);
4416 }
4417
4418 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4419 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4420 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4421
01e439be
YZ		 4422 if (vmx_vm_has_apicv(vcpu->kvm))
4423 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4424
2384d2b3
SY		 4425 if (vmx->vpid != 0)
4426 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4427
fa40052c 4428 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4429 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4430 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4431 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4432 vmx_fpu_activate(&vmx->vcpu);
4433 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4434
b9d762fa 4435 vpid_sync_context(vmx);
6aa8b732
AK		 4436}
4437
b6f1250e
NHE		 4438/*
4439 * In nested virtualization, check if L1 asked to exit on external interrupts.
4440 * For most existing hypervisors, this will always return true.
4441 */
4442static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4443{
4444 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4445 PIN_BASED_EXT_INTR_MASK;
4446}
4447
ea8ceb83
JK		 4448static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4449{
4450 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4451 PIN_BASED_NMI_EXITING;
4452}
4453
730dca42 4454static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4455{
4456 u32 cpu_based_vm_exec_control;
730dca42
JK		 4457
4458 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4459 /*
4460 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4461 * inject to L1 now because L2 must run. The caller will have
4462 * to make L2 exit right after entry, so we can inject to L1
4463 * more promptly.
b6f1250e 4464 */
730dca42 4465 return -EBUSY;
3b86cd99
JK		 4466
4467 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4468 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4469 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4470 return 0;
3b86cd99
JK		 4471}
4472
03b28f81 4473static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4474{
4475 u32 cpu_based_vm_exec_control;
4476
03b28f81
JK		 4477 if (!cpu_has_virtual_nmis())
4478 return enable_irq_window(vcpu);
4479
4480 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4481 return enable_irq_window(vcpu);
3b86cd99
JK		 4482
4483 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4484 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4485 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4486 return 0;
3b86cd99
JK		 4487}
4488
66fd3f7f 4489static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4490{
9c8cba37 4491 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4492 uint32_t intr;
4493 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4494
229456fc 4495 trace_kvm_inj_virq(irq);
2714d1d3 4496
fa89a817 4497 ++vcpu->stat.irq_injections;
7ffd92c5 4498 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4499 int inc_eip = 0;
4500 if (vcpu->arch.interrupt.soft)
4501 inc_eip = vcpu->arch.event_exit_inst_len;
4502 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4503 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4504 return;
4505 }
66fd3f7f
GN		 4506 intr = irq | INTR_INFO_VALID_MASK;
4507 if (vcpu->arch.interrupt.soft) {
4508 intr |= INTR_TYPE_SOFT_INTR;
4509 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4510 vmx->vcpu.arch.event_exit_inst_len);
4511 } else
4512 intr |= INTR_TYPE_EXT_INTR;
4513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4514}
4515
f08864b4
SY		 4516static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4517{
66a5a347
JK		 4518 struct vcpu_vmx *vmx = to_vmx(vcpu);
4519
0b6ac343
NHE		 4520 if (is_guest_mode(vcpu))
4521 return;
4522
3b86cd99
JK		 4523 if (!cpu_has_virtual_nmis()) {
4524 /*
4525 * Tracking the NMI-blocked state in software is built upon
4526 * finding the next open IRQ window. This, in turn, depends on
4527 * well-behaving guests: They have to keep IRQs disabled at
4528 * least as long as the NMI handler runs. Otherwise we may
4529 * cause NMI nesting, maybe breaking the guest. But as this is
4530 * highly unlikely, we can live with the residual risk.
4531 */
4532 vmx->soft_vnmi_blocked = 1;
4533 vmx->vnmi_blocked_time = 0;
4534 }
4535
487b391d 4536 ++vcpu->stat.nmi_injections;
9d58b931 4537 vmx->nmi_known_unmasked = false;
7ffd92c5 4538 if (vmx->rmode.vm86_active) {
71f9833b 4539 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4540 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4541 return;
4542 }
f08864b4
SY		 4543 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4544 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4545}
4546
3cfc3092
JK		 4547static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4548{
4549 if (!cpu_has_virtual_nmis())
4550 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4551 if (to_vmx(vcpu)->nmi_known_unmasked)
4552 return false;
c332c83a 4553 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4554}
4555
4556static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4557{
4558 struct vcpu_vmx *vmx = to_vmx(vcpu);
4559
4560 if (!cpu_has_virtual_nmis()) {
4561 if (vmx->soft_vnmi_blocked != masked) {
4562 vmx->soft_vnmi_blocked = masked;
4563 vmx->vnmi_blocked_time = 0;
4564 }
4565 } else {
9d58b931 4566 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4567 if (masked)
4568 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4569 GUEST_INTR_STATE_NMI);
4570 else
4571 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4572 GUEST_INTR_STATE_NMI);
4573 }
4574}
4575
2505dc9f
JK		 4576static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4577{
ea8ceb83
JK		 4578 if (is_guest_mode(vcpu)) {
4579 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4580
4581 if (to_vmx(vcpu)->nested.nested_run_pending)
4582 return 0;
4583 if (nested_exit_on_nmi(vcpu)) {
4584 nested_vmx_vmexit(vcpu);
4585 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4586 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4587 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4588 /*
4589 * The NMI-triggered VM exit counts as injection:
4590 * clear this one and block further NMIs.
4591 */
4592 vcpu->arch.nmi_pending = 0;
4593 vmx_set_nmi_mask(vcpu, true);
4594 return 0;
4595 }
4596 }
4597
2505dc9f
JK		 4598 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4599 return 0;
4600
4601 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4602 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4603 | GUEST_INTR_STATE_NMI));
4604}
4605
78646121
GN		 4606static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4607{
e8457c67 4608 if (is_guest_mode(vcpu)) {
51cfe38e 4609 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4610
4611 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4612 return 0;
e8457c67
JK		 4613 if (nested_exit_on_intr(vcpu)) {
4614 nested_vmx_vmexit(vcpu);
4615 vmcs12->vm_exit_reason =
4616 EXIT_REASON_EXTERNAL_INTERRUPT;
4617 vmcs12->vm_exit_intr_info = 0;
4618 /*
4619 * fall through to normal code, but now in L1, not L2
4620 */
4621 }
b6f1250e
NHE		 4622 }
4623
c4282df9
GN		 4624 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4625 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4626 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4627}
4628
cbc94022
IE		 4629static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4630{
4631 int ret;
4632 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4633 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4634 .guest_phys_addr = addr,
4635 .memory_size = PAGE_SIZE * 3,
4636 .flags = 0,
4637 };
4638
47ae31e2 4639 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4640 if (ret)
4641 return ret;
bfc6d222 4642 kvm->arch.tss_addr = addr;
93ea5388
GN		 4643 if (!init_rmode_tss(kvm))
4644 return -ENOMEM;
4645
cbc94022
IE		 4646 return 0;
4647}
4648
0ca1b4f4 4649static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4650{
77ab6db0 4651 switch (vec) {
77ab6db0 4652 case BP_VECTOR:
c573cd22
JK		 4653 /*
4654 * Update instruction length as we may reinject the exception
4655 * from user space while in guest debugging mode.
4656 */
4657 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4658 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4659 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4660 return false;
4661 /* fall through */
4662 case DB_VECTOR:
4663 if (vcpu->guest_debug &
4664 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4665 return false;
d0bfb940
JK		 4666 /* fall through */
4667 case DE_VECTOR:
77ab6db0
JK		 4668 case OF_VECTOR:
4669 case BR_VECTOR:
4670 case UD_VECTOR:
4671 case DF_VECTOR:
4672 case SS_VECTOR:
4673 case GP_VECTOR:
4674 case MF_VECTOR:
0ca1b4f4
GN		 4675 return true;
4676 break;
77ab6db0 4677 }
0ca1b4f4
GN		 4678 return false;
4679}
4680
4681static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4682 int vec, u32 err_code)
4683{
4684 /*
4685 * Instruction with address size override prefix opcode 0x67
4686 * Cause the #SS fault with 0 error code in VM86 mode.
4687 */
4688 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4689 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4690 if (vcpu->arch.halt_request) {
4691 vcpu->arch.halt_request = 0;
4692 return kvm_emulate_halt(vcpu);
4693 }
4694 return 1;
4695 }
4696 return 0;
4697 }
4698
4699 /*
4700 * Forward all other exceptions that are valid in real mode.
4701 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4702 * the required debugging infrastructure rework.
4703 */
4704 kvm_queue_exception(vcpu, vec);
4705 return 1;
6aa8b732
AK		 4706}
4707
a0861c02
AK		 4708/*
4709 * Trigger machine check on the host. We assume all the MSRs are already set up
4710 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4711 * We pass a fake environment to the machine check handler because we want
4712 * the guest to be always treated like user space, no matter what context
4713 * it used internally.
4714 */
4715static void kvm_machine_check(void)
4716{
4717#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4718 struct pt_regs regs = {
4719 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4720 .flags = X86_EFLAGS_IF,
4721 };
4722
4723 do_machine_check(&regs, 0);
4724#endif
4725}
4726
851ba692 4727static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4728{
4729 /* already handled by vcpu_run */
4730 return 1;
4731}
4732
851ba692 4733static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4734{
1155f76a 4735 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4736 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4737 u32 intr_info, ex_no, error_code;
42dbaa5a 4738 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4739 u32 vect_info;
4740 enum emulation_result er;
4741
1155f76a 4742 vect_info = vmx->idt_vectoring_info;
88786475 4743 intr_info = vmx->exit_intr_info;
6aa8b732 4744
a0861c02 4745 if (is_machine_check(intr_info))
851ba692 4746 return handle_machine_check(vcpu);
a0861c02 4747
e4a41889 4748 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4749 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4750
4751 if (is_no_device(intr_info)) {
5fd86fcf 4752 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4753 return 1;
4754 }
4755
7aa81cc0 4756 if (is_invalid_opcode(intr_info)) {
51d8b661 4757 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4758 if (er != EMULATE_DONE)
7ee5d940 4759 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4760 return 1;
4761 }
4762
6aa8b732 4763 error_code = 0;
2e11384c 4764 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4765 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4766
4767 /*
4768 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4769 * MMIO, it is better to report an internal error.
4770 * See the comments in vmx_handle_exit.
4771 */
4772 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4773 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4774 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4775 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4776 vcpu->run->internal.ndata = 2;
4777 vcpu->run->internal.data[0] = vect_info;
4778 vcpu->run->internal.data[1] = intr_info;
4779 return 0;
4780 }
4781
6aa8b732 4782 if (is_page_fault(intr_info)) {
1439442c 4783 /* EPT won't cause page fault directly */
cf3ace79 4784 BUG_ON(enable_ept);
6aa8b732 4785 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4786 trace_kvm_page_fault(cr2, error_code);
4787
3298b75c 4788 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4789 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4790 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4791 }
4792
d0bfb940 4793 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4794
4795 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4796 return handle_rmode_exception(vcpu, ex_no, error_code);
4797
42dbaa5a
JK		 4798 switch (ex_no) {
4799 case DB_VECTOR:
4800 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4801 if (!(vcpu->guest_debug &
4802 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4803 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4804 kvm_queue_exception(vcpu, DB_VECTOR);
4805 return 1;
4806 }
4807 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4808 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4809 /* fall through */
4810 case BP_VECTOR:
c573cd22
JK		 4811 /*
4812 * Update instruction length as we may reinject #BP from
4813 * user space while in guest debugging mode. Reading it for
4814 * #DB as well causes no harm, it is not used in that case.
4815 */
4816 vmx->vcpu.arch.event_exit_inst_len =
4817 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4818 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4819 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4820 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4821 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4822 break;
4823 default:
d0bfb940
JK		 4824 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4825 kvm_run->ex.exception = ex_no;
4826 kvm_run->ex.error_code = error_code;
42dbaa5a 4827 break;
6aa8b732 4828 }
6aa8b732
AK		 4829 return 0;
4830}
4831
851ba692 4832static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4833{
1165f5fe 4834 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4835 return 1;
4836}
4837
851ba692 4838static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4839{
851ba692 4840 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4841 return 0;
4842}
6aa8b732 4843
851ba692 4844static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4845{
bfdaab09 4846 unsigned long exit_qualification;
34c33d16 4847 int size, in, string;
039576c0 4848 unsigned port;
6aa8b732 4849
bfdaab09 4850 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4851 string = (exit_qualification & 16) != 0;
cf8f70bf 4852 in = (exit_qualification & 8) != 0;
e70669ab 4853
cf8f70bf 4854 ++vcpu->stat.io_exits;
e70669ab 4855
cf8f70bf 4856 if (string || in)
51d8b661 4857 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4858
cf8f70bf
GN		 4859 port = exit_qualification >> 16;
4860 size = (exit_qualification & 7) + 1;
e93f36bc 4861 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4862
4863 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4864}
4865
102d8325
IM		 4866static void
4867vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4868{
4869 /*
4870 * Patch in the VMCALL instruction:
4871 */
4872 hypercall[0] = 0x0f;
4873 hypercall[1] = 0x01;
4874 hypercall[2] = 0xc1;
102d8325
IM		 4875}
4876
92fbc7b1
JK		 4877static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4878{
4879 unsigned long always_on = VMXON_CR0_ALWAYSON;
4880
4881 if (nested_vmx_secondary_ctls_high &
4882 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4883 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4884 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4885 return (val & always_on) == always_on;
4886}
4887
0fa06071 4888/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4889static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4890{
eeadf9e7 4891 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4892 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4893 unsigned long orig_val = val;
4894
eeadf9e7
NHE		 4895 /*
4896 * We get here when L2 changed cr0 in a way that did not change
4897 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4898 * but did change L0 shadowed bits. So we first calculate the
4899 * effective cr0 value that L1 would like to write into the
4900 * hardware. It consists of the L2-owned bits from the new
4901 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4902 */
1a0d74e6
JK		 4903 val = (val & ~vmcs12->cr0_guest_host_mask) |
4904 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4905
92fbc7b1 4906 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4907 return 1;
1a0d74e6
JK		 4908
4909 if (kvm_set_cr0(vcpu, val))
4910 return 1;
4911 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4912 return 0;
1a0d74e6
JK		 4913 } else {
4914 if (to_vmx(vcpu)->nested.vmxon &&
4915 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4916 return 1;
eeadf9e7 4917 return kvm_set_cr0(vcpu, val);
1a0d74e6 4918 }
eeadf9e7
NHE		 4919}
4920
4921static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4922{
4923 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4924 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4925 unsigned long orig_val = val;
4926
4927 /* analogously to handle_set_cr0 */
4928 val = (val & ~vmcs12->cr4_guest_host_mask) |
4929 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4930 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4931 return 1;
1a0d74e6 4932 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4933 return 0;
4934 } else
4935 return kvm_set_cr4(vcpu, val);
4936}
4937
4938/* called to set cr0 as approriate for clts instruction exit. */
4939static void handle_clts(struct kvm_vcpu *vcpu)
4940{
4941 if (is_guest_mode(vcpu)) {
4942 /*
4943 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4944 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4945 * just pretend it's off (also in arch.cr0 for fpu_activate).
4946 */
4947 vmcs_writel(CR0_READ_SHADOW,
4948 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4949 vcpu->arch.cr0 &= ~X86_CR0_TS;
4950 } else
4951 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4952}
4953
851ba692 4954static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4955{
229456fc 4956 unsigned long exit_qualification, val;
6aa8b732
AK		 4957 int cr;
4958 int reg;
49a9b07e 4959 int err;
6aa8b732 4960
bfdaab09 4961 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4962 cr = exit_qualification & 15;
4963 reg = (exit_qualification >> 8) & 15;
4964 switch ((exit_qualification >> 4) & 3) {
4965 case 0: /* mov to cr */
229456fc
MT		 4966 val = kvm_register_read(vcpu, reg);
4967 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4968 switch (cr) {
4969 case 0:
eeadf9e7 4970 err = handle_set_cr0(vcpu, val);
db8fcefa 4971 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4972 return 1;
4973 case 3:
2390218b 4974 err = kvm_set_cr3(vcpu, val);
db8fcefa 4975 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4976 return 1;
4977 case 4:
eeadf9e7 4978 err = handle_set_cr4(vcpu, val);
db8fcefa 4979 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4980 return 1;
0a5fff19
GN		 4981 case 8: {
4982 u8 cr8_prev = kvm_get_cr8(vcpu);
4983 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4984 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4985 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4986 if (irqchip_in_kernel(vcpu->kvm))
4987 return 1;
4988 if (cr8_prev <= cr8)
4989 return 1;
851ba692 4990 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4991 return 0;
4992 }
4b8073e4 4993 }
6aa8b732 4994 break;
25c4c276 4995 case 2: /* clts */
eeadf9e7 4996 handle_clts(vcpu);
4d4ec087 4997 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4998 skip_emulated_instruction(vcpu);
6b52d186 4999 vmx_fpu_activate(vcpu);
25c4c276 5000 return 1;
6aa8b732
AK		 5001 case 1: /*mov from cr*/
5002 switch (cr) {
5003 case 3:
9f8fe504
AK		 5004 val = kvm_read_cr3(vcpu);
5005 kvm_register_write(vcpu, reg, val);
5006 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5007 skip_emulated_instruction(vcpu);
5008 return 1;
5009 case 8:
229456fc
MT		 5010 val = kvm_get_cr8(vcpu);
5011 kvm_register_write(vcpu, reg, val);
5012 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5013 skip_emulated_instruction(vcpu);
5014 return 1;
5015 }
5016 break;
5017 case 3: /* lmsw */
a1f83a74 5018 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5019 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5020 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5021
5022 skip_emulated_instruction(vcpu);
5023 return 1;
5024 default:
5025 break;
5026 }
851ba692 5027 vcpu->run->exit_reason = 0;
a737f256 5028 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5029 (int)(exit_qualification >> 4) & 3, cr);
5030 return 0;
5031}
5032
851ba692 5033static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5034{
bfdaab09 5035 unsigned long exit_qualification;
6aa8b732
AK		 5036 int dr, reg;
5037
f2483415 5038 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5039 if (!kvm_require_cpl(vcpu, 0))
5040 return 1;
42dbaa5a
JK		 5041 dr = vmcs_readl(GUEST_DR7);
5042 if (dr & DR7_GD) {
5043 /*
5044 * As the vm-exit takes precedence over the debug trap, we
5045 * need to emulate the latter, either for the host or the
5046 * guest debugging itself.
5047 */
5048 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5049 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5050 vcpu->run->debug.arch.dr7 = dr;
5051 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5052 vmcs_readl(GUEST_CS_BASE) +
5053 vmcs_readl(GUEST_RIP);
851ba692
AK		 5054 vcpu->run->debug.arch.exception = DB_VECTOR;
5055 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5056 return 0;
5057 } else {
5058 vcpu->arch.dr7 &= ~DR7_GD;
5059 vcpu->arch.dr6 |= DR6_BD;
5060 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5061 kvm_queue_exception(vcpu, DB_VECTOR);
5062 return 1;
5063 }
5064 }
5065
bfdaab09 5066 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5067 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5068 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5069 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5070 unsigned long val;
5071 if (!kvm_get_dr(vcpu, dr, &val))
5072 kvm_register_write(vcpu, reg, val);
5073 } else
5074 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5075 skip_emulated_instruction(vcpu);
5076 return 1;
5077}
5078
020df079
GN		 5079static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5080{
5081 vmcs_writel(GUEST_DR7, val);
5082}
5083
851ba692 5084static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5085{
06465c5a
AK		 5086 kvm_emulate_cpuid(vcpu);
5087 return 1;
6aa8b732
AK		 5088}
5089
851ba692 5090static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5091{
ad312c7c 5092 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5093 u64 data;
5094
5095 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5096 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5097 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5098 return 1;
5099 }
5100
229456fc 5101 trace_kvm_msr_read(ecx, data);
2714d1d3 5102
6aa8b732 5103 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5104 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5105 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5106 skip_emulated_instruction(vcpu);
5107 return 1;
5108}
5109
851ba692 5110static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5111{
8fe8ab46 5112 struct msr_data msr;
ad312c7c
ZX		 5113 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5114 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5115 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5116
8fe8ab46
WA		 5117 msr.data = data;
5118 msr.index = ecx;
5119 msr.host_initiated = false;
5120 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5121 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5122 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5123 return 1;
5124 }
5125
59200273 5126 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5127 skip_emulated_instruction(vcpu);
5128 return 1;
5129}
5130
851ba692 5131static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5132{
3842d135 5133 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5134 return 1;
5135}
5136
851ba692 5137static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5138{
85f455f7
ED		 5139 u32 cpu_based_vm_exec_control;
5140
5141 /* clear pending irq */
5142 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5143 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5144 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5145
3842d135
AK		 5146 kvm_make_request(KVM_REQ_EVENT, vcpu);
5147
a26bf12a 5148 ++vcpu->stat.irq_window_exits;
2714d1d3 5149
c1150d8c
DL		 5150 /*
5151 * If the user space waits to inject interrupts, exit as soon as
5152 * possible
5153 */
8061823a 5154 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5155 vcpu->run->request_interrupt_window &&
8061823a 5156 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5157 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5158 return 0;
5159 }
6aa8b732
AK		 5160 return 1;
5161}
5162
851ba692 5163static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5164{
5165 skip_emulated_instruction(vcpu);
d3bef15f 5166 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5167}
5168
851ba692 5169static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5170{
510043da 5171 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5172 kvm_emulate_hypercall(vcpu);
5173 return 1;
c21415e8
IM		 5174}
5175
ec25d5e6
GN		 5176static int handle_invd(struct kvm_vcpu *vcpu)
5177{
51d8b661 5178 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5179}
5180
851ba692 5181static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5182{
f9c617f6 5183 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5184
5185 kvm_mmu_invlpg(vcpu, exit_qualification);
5186 skip_emulated_instruction(vcpu);
5187 return 1;
5188}
5189
fee84b07
AK		 5190static int handle_rdpmc(struct kvm_vcpu *vcpu)
5191{
5192 int err;
5193
5194 err = kvm_rdpmc(vcpu);
5195 kvm_complete_insn_gp(vcpu, err);
5196
5197 return 1;
5198}
5199
851ba692 5200static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5201{
5202 skip_emulated_instruction(vcpu);
f5f48ee1 5203 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5204 return 1;
5205}
5206
2acf923e
DC		 5207static int handle_xsetbv(struct kvm_vcpu *vcpu)
5208{
5209 u64 new_bv = kvm_read_edx_eax(vcpu);
5210 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5211
5212 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5213 skip_emulated_instruction(vcpu);
5214 return 1;
5215}
5216
851ba692 5217static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5218{
58fbbf26
KT		 5219 if (likely(fasteoi)) {
5220 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5221 int access_type, offset;
5222
5223 access_type = exit_qualification & APIC_ACCESS_TYPE;
5224 offset = exit_qualification & APIC_ACCESS_OFFSET;
5225 /*
5226 * Sane guest uses MOV to write EOI, with written value
5227 * not cared. So make a short-circuit here by avoiding
5228 * heavy instruction emulation.
5229 */
5230 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5231 (offset == APIC_EOI)) {
5232 kvm_lapic_set_eoi(vcpu);
5233 skip_emulated_instruction(vcpu);
5234 return 1;
5235 }
5236 }
51d8b661 5237 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5238}
5239
c7c9c56c
YZ		 5240static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5241{
5242 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5243 int vector = exit_qualification & 0xff;
5244
5245 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5246 kvm_apic_set_eoi_accelerated(vcpu, vector);
5247 return 1;
5248}
5249
83d4c286
YZ		 5250static int handle_apic_write(struct kvm_vcpu *vcpu)
5251{
5252 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5253 u32 offset = exit_qualification & 0xfff;
5254
5255 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5256 kvm_apic_write_nodecode(vcpu, offset);
5257 return 1;
5258}
5259
851ba692 5260static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5261{
60637aac 5262 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5263 unsigned long exit_qualification;
e269fb21
JK		 5264 bool has_error_code = false;
5265 u32 error_code = 0;
37817f29 5266 u16 tss_selector;
7f3d35fd 5267 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5268
5269 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5270 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5271 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5272
5273 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5274
5275 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5276 if (reason == TASK_SWITCH_GATE && idt_v) {
5277 switch (type) {
5278 case INTR_TYPE_NMI_INTR:
5279 vcpu->arch.nmi_injected = false;
654f06fc 5280 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5281 break;
5282 case INTR_TYPE_EXT_INTR:
66fd3f7f 5283 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5284 kvm_clear_interrupt_queue(vcpu);
5285 break;
5286 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5287 if (vmx->idt_vectoring_info &
5288 VECTORING_INFO_DELIVER_CODE_MASK) {
5289 has_error_code = true;
5290 error_code =
5291 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5292 }
5293 /* fall through */
64a7ec06
GN		 5294 case INTR_TYPE_SOFT_EXCEPTION:
5295 kvm_clear_exception_queue(vcpu);
5296 break;
5297 default:
5298 break;
5299 }
60637aac 5300 }
37817f29
IE		 5301 tss_selector = exit_qualification;
5302
64a7ec06
GN		 5303 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5304 type != INTR_TYPE_EXT_INTR &&
5305 type != INTR_TYPE_NMI_INTR))
5306 skip_emulated_instruction(vcpu);
5307
7f3d35fd
KW		 5308 if (kvm_task_switch(vcpu, tss_selector,
5309 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5310 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5311 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5312 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5313 vcpu->run->internal.ndata = 0;
42dbaa5a 5314 return 0;
acb54517 5315 }
42dbaa5a
JK		 5316
5317 /* clear all local breakpoint enable flags */
5318 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5319
5320 /*
5321 * TODO: What about debug traps on tss switch?
5322 * Are we supposed to inject them and update dr6?
5323 */
5324
5325 return 1;
37817f29
IE		 5326}
5327
851ba692 5328static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5329{
f9c617f6 5330 unsigned long exit_qualification;
1439442c 5331 gpa_t gpa;
4f5982a5 5332 u32 error_code;
1439442c 5333 int gla_validity;
1439442c 5334
f9c617f6 5335 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5336
1439442c
SY		 5337 gla_validity = (exit_qualification >> 7) & 0x3;
5338 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5339 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5340 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5341 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5342 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5343 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5344 (long unsigned int)exit_qualification);
851ba692
AK		 5345 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5346 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5347 return 0;
1439442c
SY		 5348 }
5349
0be9c7a8
GN		 5350 /*
5351 * EPT violation happened while executing iret from NMI,
5352 * "blocked by NMI" bit has to be set before next VM entry.
5353 * There are errata that may cause this bit to not be set:
5354 * AAK134, BY25.
5355 */
5356 if (exit_qualification & INTR_INFO_UNBLOCK_NMI)
5357 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5358
1439442c 5359 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5360 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5361
5362 /* It is a write fault? */
5363 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5364 /* It is a fetch fault? */
5365 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5366 /* ept page table is present? */
5367 error_code |= (exit_qualification >> 3) & 0x1;
5368
25d92081
YZ		 5369 vcpu->arch.exit_qualification = exit_qualification;
5370
4f5982a5 5371 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5372}
5373
68f89400
MT		 5374static u64 ept_rsvd_mask(u64 spte, int level)
5375{
5376 int i;
5377 u64 mask = 0;
5378
5379 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5380 mask |= (1ULL << i);
5381
5382 if (level > 2)
5383 /* bits 7:3 reserved */
5384 mask |= 0xf8;
5385 else if (level == 2) {
5386 if (spte & (1ULL << 7))
5387 /* 2MB ref, bits 20:12 reserved */
5388 mask |= 0x1ff000;
5389 else
5390 /* bits 6:3 reserved */
5391 mask |= 0x78;
5392 }
5393
5394 return mask;
5395}
5396
5397static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5398 int level)
5399{
5400 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5401
5402 /* 010b (write-only) */
5403 WARN_ON((spte & 0x7) == 0x2);
5404
5405 /* 110b (write/execute) */
5406 WARN_ON((spte & 0x7) == 0x6);
5407
5408 /* 100b (execute-only) and value not supported by logical processor */
5409 if (!cpu_has_vmx_ept_execute_only())
5410 WARN_ON((spte & 0x7) == 0x4);
5411
5412 /* not 000b */
5413 if ((spte & 0x7)) {
5414 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5415
5416 if (rsvd_bits != 0) {
5417 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5418 __func__, rsvd_bits);
5419 WARN_ON(1);
5420 }
5421
5422 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5423 u64 ept_mem_type = (spte & 0x38) >> 3;
5424
5425 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5426 ept_mem_type == 7) {
5427 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5428 __func__, ept_mem_type);
5429 WARN_ON(1);
5430 }
5431 }
5432 }
5433}
5434
851ba692 5435static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5436{
5437 u64 sptes[4];
ce88decf 5438 int nr_sptes, i, ret;
68f89400
MT		 5439 gpa_t gpa;
5440
5441 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5442
ce88decf 5443 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5444 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5445 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5446 EMULATE_DONE;
f8f55942
XG		 5447
5448 if (unlikely(ret == RET_MMIO_PF_INVALID))
5449 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5450
b37fbea6 5451 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5452 return 1;
5453
5454 /* It is the real ept misconfig */
68f89400
MT		 5455 printk(KERN_ERR "EPT: Misconfiguration.\n");
5456 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5457
5458 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5459
5460 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5461 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5462
851ba692
AK		 5463 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5464 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5465
5466 return 0;
5467}
5468
851ba692 5469static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5470{
5471 u32 cpu_based_vm_exec_control;
5472
5473 /* clear pending NMI */
5474 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5475 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5476 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5477 ++vcpu->stat.nmi_window_exits;
3842d135 5478 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5479
5480 return 1;
5481}
5482
80ced186 5483static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5484{
8b3079a5
AK		 5485 struct vcpu_vmx *vmx = to_vmx(vcpu);
5486 enum emulation_result err = EMULATE_DONE;
80ced186 5487 int ret = 1;
49e9d557
AK		 5488 u32 cpu_exec_ctrl;
5489 bool intr_window_requested;
b8405c18 5490 unsigned count = 130;
49e9d557
AK		 5491
5492 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5493 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5494
b8405c18 5495 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5496 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5497 return handle_interrupt_window(&vmx->vcpu);
5498
de87dcdd
AK		 5499 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5500 return 1;
5501
991eebf9 5502 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5503
ac0a48c3 5504 if (err == EMULATE_USER_EXIT) {
94452b9e 5505 ++vcpu->stat.mmio_exits;
80ced186
MG		 5506 ret = 0;
5507 goto out;
5508 }
1d5a4d9b 5509
de5f70e0
AK		 5510 if (err != EMULATE_DONE) {
5511 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5512 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5513 vcpu->run->internal.ndata = 0;
6d77dbfc 5514 return 0;
de5f70e0 5515 }
ea953ef0 5516
8d76c49e
GN		 5517 if (vcpu->arch.halt_request) {
5518 vcpu->arch.halt_request = 0;
5519 ret = kvm_emulate_halt(vcpu);
5520 goto out;
5521 }
5522
ea953ef0 5523 if (signal_pending(current))
80ced186 5524 goto out;
ea953ef0
MG		 5525 if (need_resched())
5526 schedule();
5527 }
5528
14168786 5529 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5530out:
5531 return ret;
ea953ef0
MG		 5532}
5533
4b8d54f9
ZE		 5534/*
5535 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5536 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5537 */
9fb41ba8 5538static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5539{
5540 skip_emulated_instruction(vcpu);
5541 kvm_vcpu_on_spin(vcpu);
5542
5543 return 1;
5544}
5545
59708670
SY		 5546static int handle_invalid_op(struct kvm_vcpu *vcpu)
5547{
5548 kvm_queue_exception(vcpu, UD_VECTOR);
5549 return 1;
5550}
5551
ff2f6fe9
NHE		 5552/*
5553 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5554 * We could reuse a single VMCS for all the L2 guests, but we also want the
5555 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5556 * allows keeping them loaded on the processor, and in the future will allow
5557 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5558 * every entry if they never change.
5559 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5560 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5561 *
5562 * The following functions allocate and free a vmcs02 in this pool.
5563 */
5564
5565/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5566static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5567{
5568 struct vmcs02_list *item;
5569 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5570 if (item->vmptr == vmx->nested.current_vmptr) {
5571 list_move(&item->list, &vmx->nested.vmcs02_pool);
5572 return &item->vmcs02;
5573 }
5574
5575 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5576 /* Recycle the least recently used VMCS. */
5577 item = list_entry(vmx->nested.vmcs02_pool.prev,
5578 struct vmcs02_list, list);
5579 item->vmptr = vmx->nested.current_vmptr;
5580 list_move(&item->list, &vmx->nested.vmcs02_pool);
5581 return &item->vmcs02;
5582 }
5583
5584 /* Create a new VMCS */
0fa24ce3 5585 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5586 if (!item)
5587 return NULL;
5588 item->vmcs02.vmcs = alloc_vmcs();
5589 if (!item->vmcs02.vmcs) {
5590 kfree(item);
5591 return NULL;
5592 }
5593 loaded_vmcs_init(&item->vmcs02);
5594 item->vmptr = vmx->nested.current_vmptr;
5595 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5596 vmx->nested.vmcs02_num++;
5597 return &item->vmcs02;
5598}
5599
5600/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5601static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5602{
5603 struct vmcs02_list *item;
5604 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5605 if (item->vmptr == vmptr) {
5606 free_loaded_vmcs(&item->vmcs02);
5607 list_del(&item->list);
5608 kfree(item);
5609 vmx->nested.vmcs02_num--;
5610 return;
5611 }
5612}
5613
5614/*
5615 * Free all VMCSs saved for this vcpu, except the one pointed by
5616 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5617 * currently used, if running L2), and vmcs01 when running L2.
5618 */
5619static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5620{
5621 struct vmcs02_list *item, *n;
5622 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5623 if (vmx->loaded_vmcs != &item->vmcs02)
5624 free_loaded_vmcs(&item->vmcs02);
5625 list_del(&item->list);
5626 kfree(item);
5627 }
5628 vmx->nested.vmcs02_num = 0;
5629
5630 if (vmx->loaded_vmcs != &vmx->vmcs01)
5631 free_loaded_vmcs(&vmx->vmcs01);
5632}
5633
0658fbaa
ACL		 5634/*
5635 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5636 * set the success or error code of an emulated VMX instruction, as specified
5637 * by Vol 2B, VMX Instruction Reference, "Conventions".
5638 */
5639static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5640{
5641 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5642 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5643 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5644}
5645
5646static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5647{
5648 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5649 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5650 X86_EFLAGS_SF | X86_EFLAGS_OF))
5651 | X86_EFLAGS_CF);
5652}
5653
145c28dd 5654static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5655 u32 vm_instruction_error)
5656{
5657 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5658 /*
5659 * failValid writes the error number to the current VMCS, which
5660 * can't be done there isn't a current VMCS.
5661 */
5662 nested_vmx_failInvalid(vcpu);
5663 return;
5664 }
5665 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5666 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5667 X86_EFLAGS_SF | X86_EFLAGS_OF))
5668 | X86_EFLAGS_ZF);
5669 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5670 /*
5671 * We don't need to force a shadow sync because
5672 * VM_INSTRUCTION_ERROR is not shadowed
5673 */
5674}
145c28dd 5675
ec378aee
NHE		 5676/*
5677 * Emulate the VMXON instruction.
5678 * Currently, we just remember that VMX is active, and do not save or even
5679 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5680 * do not currently need to store anything in that guest-allocated memory
5681 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5682 * argument is different from the VMXON pointer (which the spec says they do).
5683 */
5684static int handle_vmon(struct kvm_vcpu *vcpu)
5685{
5686 struct kvm_segment cs;
5687 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5688 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5689 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5690 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5691
5692 /* The Intel VMX Instruction Reference lists a bunch of bits that
5693 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5694 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5695 * Otherwise, we should fail with #UD. We test these now:
5696 */
5697 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5698 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5699 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5700 kvm_queue_exception(vcpu, UD_VECTOR);
5701 return 1;
5702 }
5703
5704 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5705 if (is_long_mode(vcpu) && !cs.l) {
5706 kvm_queue_exception(vcpu, UD_VECTOR);
5707 return 1;
5708 }
5709
5710 if (vmx_get_cpl(vcpu)) {
5711 kvm_inject_gp(vcpu, 0);
5712 return 1;
5713 }
145c28dd
AG		 5714 if (vmx->nested.vmxon) {
5715 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5716 skip_emulated_instruction(vcpu);
5717 return 1;
5718 }
b3897a49
NHE		 5719
5720 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5721 != VMXON_NEEDED_FEATURES) {
5722 kvm_inject_gp(vcpu, 0);
5723 return 1;
5724 }
5725
8de48833
AG		 5726 if (enable_shadow_vmcs) {
5727 shadow_vmcs = alloc_vmcs();
5728 if (!shadow_vmcs)
5729 return -ENOMEM;
5730 /* mark vmcs as shadow */
5731 shadow_vmcs->revision_id |= (1u << 31);
5732 /* init shadow vmcs */
5733 vmcs_clear(shadow_vmcs);
5734 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5735 }
ec378aee 5736
ff2f6fe9
NHE		 5737 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5738 vmx->nested.vmcs02_num = 0;
5739
ec378aee
NHE		 5740 vmx->nested.vmxon = true;
5741
5742 skip_emulated_instruction(vcpu);
a25eb114 5743 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5744 return 1;
5745}
5746
5747/*
5748 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5749 * for running VMX instructions (except VMXON, whose prerequisites are
5750 * slightly different). It also specifies what exception to inject otherwise.
5751 */
5752static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5753{
5754 struct kvm_segment cs;
5755 struct vcpu_vmx *vmx = to_vmx(vcpu);
5756
5757 if (!vmx->nested.vmxon) {
5758 kvm_queue_exception(vcpu, UD_VECTOR);
5759 return 0;
5760 }
5761
5762 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5763 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5764 (is_long_mode(vcpu) && !cs.l)) {
5765 kvm_queue_exception(vcpu, UD_VECTOR);
5766 return 0;
5767 }
5768
5769 if (vmx_get_cpl(vcpu)) {
5770 kvm_inject_gp(vcpu, 0);
5771 return 0;
5772 }
5773
5774 return 1;
5775}
5776
e7953d7f
AG		 5777static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5778{
8a1b9dd0 5779 u32 exec_control;
012f83cb
AG		 5780 if (enable_shadow_vmcs) {
5781 if (vmx->nested.current_vmcs12 != NULL) {
5782 /* copy to memory all shadowed fields in case
5783 they were modified */
5784 copy_shadow_to_vmcs12(vmx);
5785 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5786 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5787 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5788 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5789 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5790 }
5791 }
e7953d7f
AG		 5792 kunmap(vmx->nested.current_vmcs12_page);
5793 nested_release_page(vmx->nested.current_vmcs12_page);
5794}
5795
ec378aee
NHE		 5796/*
5797 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5798 * just stops using VMX.
5799 */
5800static void free_nested(struct vcpu_vmx *vmx)
5801{
5802 if (!vmx->nested.vmxon)
5803 return;
5804 vmx->nested.vmxon = false;
a9d30f33 5805 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5806 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5807 vmx->nested.current_vmptr = -1ull;
5808 vmx->nested.current_vmcs12 = NULL;
5809 }
e7953d7f
AG		 5810 if (enable_shadow_vmcs)
5811 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5812 /* Unpin physical memory we referred to in current vmcs02 */
5813 if (vmx->nested.apic_access_page) {
5814 nested_release_page(vmx->nested.apic_access_page);
5815 vmx->nested.apic_access_page = 0;
5816 }
ff2f6fe9
NHE		 5817
5818 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5819}
5820
5821/* Emulate the VMXOFF instruction */
5822static int handle_vmoff(struct kvm_vcpu *vcpu)
5823{
5824 if (!nested_vmx_check_permission(vcpu))
5825 return 1;
5826 free_nested(to_vmx(vcpu));
5827 skip_emulated_instruction(vcpu);
a25eb114 5828 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5829 return 1;
5830}
5831
064aea77
NHE		 5832/*
5833 * Decode the memory-address operand of a vmx instruction, as recorded on an
5834 * exit caused by such an instruction (run by a guest hypervisor).
5835 * On success, returns 0. When the operand is invalid, returns 1 and throws
5836 * #UD or #GP.
5837 */
5838static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5839 unsigned long exit_qualification,
5840 u32 vmx_instruction_info, gva_t *ret)
5841{
5842 /*
5843 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5844 * Execution", on an exit, vmx_instruction_info holds most of the
5845 * addressing components of the operand. Only the displacement part
5846 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5847 * For how an actual address is calculated from all these components,
5848 * refer to Vol. 1, "Operand Addressing".
5849 */
5850 int scaling = vmx_instruction_info & 3;
5851 int addr_size = (vmx_instruction_info >> 7) & 7;
5852 bool is_reg = vmx_instruction_info & (1u << 10);
5853 int seg_reg = (vmx_instruction_info >> 15) & 7;
5854 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5855 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5856 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5857 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5858
5859 if (is_reg) {
5860 kvm_queue_exception(vcpu, UD_VECTOR);
5861 return 1;
5862 }
5863
5864 /* Addr = segment_base + offset */
5865 /* offset = base + [index * scale] + displacement */
5866 *ret = vmx_get_segment_base(vcpu, seg_reg);
5867 if (base_is_valid)
5868 *ret += kvm_register_read(vcpu, base_reg);
5869 if (index_is_valid)
5870 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5871 *ret += exit_qualification; /* holds the displacement */
5872
5873 if (addr_size == 1) /* 32 bit */
5874 *ret &= 0xffffffff;
5875
5876 /*
5877 * TODO: throw #GP (and return 1) in various cases that the VM*
5878 * instructions require it - e.g., offset beyond segment limit,
5879 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5880 * address, and so on. Currently these are not checked.
5881 */
5882 return 0;
5883}
5884
27d6c865
NHE		 5885/* Emulate the VMCLEAR instruction */
5886static int handle_vmclear(struct kvm_vcpu *vcpu)
5887{
5888 struct vcpu_vmx *vmx = to_vmx(vcpu);
5889 gva_t gva;
5890 gpa_t vmptr;
5891 struct vmcs12 *vmcs12;
5892 struct page *page;
5893 struct x86_exception e;
5894
5895 if (!nested_vmx_check_permission(vcpu))
5896 return 1;
5897
5898 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5899 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5900 return 1;
5901
5902 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5903 sizeof(vmptr), &e)) {
5904 kvm_inject_page_fault(vcpu, &e);
5905 return 1;
5906 }
5907
5908 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5909 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5910 skip_emulated_instruction(vcpu);
5911 return 1;
5912 }
5913
5914 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5915 nested_release_vmcs12(vmx);
27d6c865
NHE		 5916 vmx->nested.current_vmptr = -1ull;
5917 vmx->nested.current_vmcs12 = NULL;
5918 }
5919
5920 page = nested_get_page(vcpu, vmptr);
5921 if (page == NULL) {
5922 /*
5923 * For accurate processor emulation, VMCLEAR beyond available
5924 * physical memory should do nothing at all. However, it is
5925 * possible that a nested vmx bug, not a guest hypervisor bug,
5926 * resulted in this case, so let's shut down before doing any
5927 * more damage:
5928 */
5929 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5930 return 1;
5931 }
5932 vmcs12 = kmap(page);
5933 vmcs12->launch_state = 0;
5934 kunmap(page);
5935 nested_release_page(page);
5936
5937 nested_free_vmcs02(vmx, vmptr);
5938
5939 skip_emulated_instruction(vcpu);
5940 nested_vmx_succeed(vcpu);
5941 return 1;
5942}
5943
cd232ad0
NHE		 5944static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5945
5946/* Emulate the VMLAUNCH instruction */
5947static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5948{
5949 return nested_vmx_run(vcpu, true);
5950}
5951
5952/* Emulate the VMRESUME instruction */
5953static int handle_vmresume(struct kvm_vcpu *vcpu)
5954{
5955
5956 return nested_vmx_run(vcpu, false);
5957}
5958
49f705c5
NHE		 5959enum vmcs_field_type {
5960 VMCS_FIELD_TYPE_U16 = 0,
5961 VMCS_FIELD_TYPE_U64 = 1,
5962 VMCS_FIELD_TYPE_U32 = 2,
5963 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5964};
5965
5966static inline int vmcs_field_type(unsigned long field)
5967{
5968 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5969 return VMCS_FIELD_TYPE_U32;
5970 return (field >> 13) & 0x3 ;
5971}
5972
5973static inline int vmcs_field_readonly(unsigned long field)
5974{
5975 return (((field >> 10) & 0x3) == 1);
5976}
5977
5978/*
5979 * Read a vmcs12 field. Since these can have varying lengths and we return
5980 * one type, we chose the biggest type (u64) and zero-extend the return value
5981 * to that size. Note that the caller, handle_vmread, might need to use only
5982 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5983 * 64-bit fields are to be returned).
5984 */
5985static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5986 unsigned long field, u64 *ret)
5987{
5988 short offset = vmcs_field_to_offset(field);
5989 char *p;
5990
5991 if (offset < 0)
5992 return 0;
5993
5994 p = ((char *)(get_vmcs12(vcpu))) + offset;
5995
5996 switch (vmcs_field_type(field)) {
5997 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5998 *ret = *((natural_width *)p);
5999 return 1;
6000 case VMCS_FIELD_TYPE_U16:
6001 *ret = *((u16 *)p);
6002 return 1;
6003 case VMCS_FIELD_TYPE_U32:
6004 *ret = *((u32 *)p);
6005 return 1;
6006 case VMCS_FIELD_TYPE_U64:
6007 *ret = *((u64 *)p);
6008 return 1;
6009 default:
6010 return 0; /* can never happen. */
6011 }
6012}
6013
20b97fea
AG		 6014
6015static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6016 unsigned long field, u64 field_value){
6017 short offset = vmcs_field_to_offset(field);
6018 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6019 if (offset < 0)
6020 return false;
6021
6022 switch (vmcs_field_type(field)) {
6023 case VMCS_FIELD_TYPE_U16:
6024 *(u16 *)p = field_value;
6025 return true;
6026 case VMCS_FIELD_TYPE_U32:
6027 *(u32 *)p = field_value;
6028 return true;
6029 case VMCS_FIELD_TYPE_U64:
6030 *(u64 *)p = field_value;
6031 return true;
6032 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6033 *(natural_width *)p = field_value;
6034 return true;
6035 default:
6036 return false; /* can never happen. */
6037 }
6038
6039}
6040
16f5b903
AG		 6041static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6042{
6043 int i;
6044 unsigned long field;
6045 u64 field_value;
6046 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6047 const unsigned long *fields = shadow_read_write_fields;
6048 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6049
6050 vmcs_load(shadow_vmcs);
6051
6052 for (i = 0; i < num_fields; i++) {
6053 field = fields[i];
6054 switch (vmcs_field_type(field)) {
6055 case VMCS_FIELD_TYPE_U16:
6056 field_value = vmcs_read16(field);
6057 break;
6058 case VMCS_FIELD_TYPE_U32:
6059 field_value = vmcs_read32(field);
6060 break;
6061 case VMCS_FIELD_TYPE_U64:
6062 field_value = vmcs_read64(field);
6063 break;
6064 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6065 field_value = vmcs_readl(field);
6066 break;
6067 }
6068 vmcs12_write_any(&vmx->vcpu, field, field_value);
6069 }
6070
6071 vmcs_clear(shadow_vmcs);
6072 vmcs_load(vmx->loaded_vmcs->vmcs);
6073}
6074
c3114420
AG		 6075static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6076{
c2bae893
MK		 6077 const unsigned long *fields[] = {
6078 shadow_read_write_fields,
6079 shadow_read_only_fields
c3114420 6080 };
c2bae893 6081 const int max_fields[] = {
c3114420
AG		 6082 max_shadow_read_write_fields,
6083 max_shadow_read_only_fields
6084 };
6085 int i, q;
6086 unsigned long field;
6087 u64 field_value = 0;
6088 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6089
6090 vmcs_load(shadow_vmcs);
6091
c2bae893 6092 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6093 for (i = 0; i < max_fields[q]; i++) {
6094 field = fields[q][i];
6095 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6096
6097 switch (vmcs_field_type(field)) {
6098 case VMCS_FIELD_TYPE_U16:
6099 vmcs_write16(field, (u16)field_value);
6100 break;
6101 case VMCS_FIELD_TYPE_U32:
6102 vmcs_write32(field, (u32)field_value);
6103 break;
6104 case VMCS_FIELD_TYPE_U64:
6105 vmcs_write64(field, (u64)field_value);
6106 break;
6107 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6108 vmcs_writel(field, (long)field_value);
6109 break;
6110 }
6111 }
6112 }
6113
6114 vmcs_clear(shadow_vmcs);
6115 vmcs_load(vmx->loaded_vmcs->vmcs);
6116}
6117
49f705c5
NHE		 6118/*
6119 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6120 * used before) all generate the same failure when it is missing.
6121 */
6122static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6123{
6124 struct vcpu_vmx *vmx = to_vmx(vcpu);
6125 if (vmx->nested.current_vmptr == -1ull) {
6126 nested_vmx_failInvalid(vcpu);
6127 skip_emulated_instruction(vcpu);
6128 return 0;
6129 }
6130 return 1;
6131}
6132
6133static int handle_vmread(struct kvm_vcpu *vcpu)
6134{
6135 unsigned long field;
6136 u64 field_value;
6137 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6138 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6139 gva_t gva = 0;
6140
6141 if (!nested_vmx_check_permission(vcpu) ||
6142 !nested_vmx_check_vmcs12(vcpu))
6143 return 1;
6144
6145 /* Decode instruction info and find the field to read */
6146 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6147 /* Read the field, zero-extended to a u64 field_value */
6148 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6149 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6150 skip_emulated_instruction(vcpu);
6151 return 1;
6152 }
6153 /*
6154 * Now copy part of this value to register or memory, as requested.
6155 * Note that the number of bits actually copied is 32 or 64 depending
6156 * on the guest's mode (32 or 64 bit), not on the given field's length.
6157 */
6158 if (vmx_instruction_info & (1u << 10)) {
6159 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6160 field_value);
6161 } else {
6162 if (get_vmx_mem_address(vcpu, exit_qualification,
6163 vmx_instruction_info, &gva))
6164 return 1;
6165 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6166 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6167 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6168 }
6169
6170 nested_vmx_succeed(vcpu);
6171 skip_emulated_instruction(vcpu);
6172 return 1;
6173}
6174
6175
6176static int handle_vmwrite(struct kvm_vcpu *vcpu)
6177{
6178 unsigned long field;
6179 gva_t gva;
6180 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6181 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6182 /* The value to write might be 32 or 64 bits, depending on L1's long
6183 * mode, and eventually we need to write that into a field of several
6184 * possible lengths. The code below first zero-extends the value to 64
6185 * bit (field_value), and then copies only the approriate number of
6186 * bits into the vmcs12 field.
6187 */
6188 u64 field_value = 0;
6189 struct x86_exception e;
6190
6191 if (!nested_vmx_check_permission(vcpu) ||
6192 !nested_vmx_check_vmcs12(vcpu))
6193 return 1;
6194
6195 if (vmx_instruction_info & (1u << 10))
6196 field_value = kvm_register_read(vcpu,
6197 (((vmx_instruction_info) >> 3) & 0xf));
6198 else {
6199 if (get_vmx_mem_address(vcpu, exit_qualification,
6200 vmx_instruction_info, &gva))
6201 return 1;
6202 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6203 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6204 kvm_inject_page_fault(vcpu, &e);
6205 return 1;
6206 }
6207 }
6208
6209
6210 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6211 if (vmcs_field_readonly(field)) {
6212 nested_vmx_failValid(vcpu,
6213 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6214 skip_emulated_instruction(vcpu);
6215 return 1;
6216 }
6217
20b97fea 6218 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6219 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6220 skip_emulated_instruction(vcpu);
6221 return 1;
6222 }
6223
6224 nested_vmx_succeed(vcpu);
6225 skip_emulated_instruction(vcpu);
6226 return 1;
6227}
6228
63846663
NHE		 6229/* Emulate the VMPTRLD instruction */
6230static int handle_vmptrld(struct kvm_vcpu *vcpu)
6231{
6232 struct vcpu_vmx *vmx = to_vmx(vcpu);
6233 gva_t gva;
6234 gpa_t vmptr;
6235 struct x86_exception e;
8a1b9dd0 6236 u32 exec_control;
63846663
NHE		 6237
6238 if (!nested_vmx_check_permission(vcpu))
6239 return 1;
6240
6241 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6242 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6243 return 1;
6244
6245 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6246 sizeof(vmptr), &e)) {
6247 kvm_inject_page_fault(vcpu, &e);
6248 return 1;
6249 }
6250
6251 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6252 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6253 skip_emulated_instruction(vcpu);
6254 return 1;
6255 }
6256
6257 if (vmx->nested.current_vmptr != vmptr) {
6258 struct vmcs12 *new_vmcs12;
6259 struct page *page;
6260 page = nested_get_page(vcpu, vmptr);
6261 if (page == NULL) {
6262 nested_vmx_failInvalid(vcpu);
6263 skip_emulated_instruction(vcpu);
6264 return 1;
6265 }
6266 new_vmcs12 = kmap(page);
6267 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6268 kunmap(page);
6269 nested_release_page_clean(page);
6270 nested_vmx_failValid(vcpu,
6271 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6272 skip_emulated_instruction(vcpu);
6273 return 1;
6274 }
e7953d7f
AG		 6275 if (vmx->nested.current_vmptr != -1ull)
6276 nested_release_vmcs12(vmx);
63846663
NHE		 6277
6278 vmx->nested.current_vmptr = vmptr;
6279 vmx->nested.current_vmcs12 = new_vmcs12;
6280 vmx->nested.current_vmcs12_page = page;
012f83cb 6281 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6282 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6283 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6284 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6285 vmcs_write64(VMCS_LINK_POINTER,
6286 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6287 vmx->nested.sync_shadow_vmcs = true;
6288 }
63846663
NHE		 6289 }
6290
6291 nested_vmx_succeed(vcpu);
6292 skip_emulated_instruction(vcpu);
6293 return 1;
6294}
6295
6a4d7550
NHE		 6296/* Emulate the VMPTRST instruction */
6297static int handle_vmptrst(struct kvm_vcpu *vcpu)
6298{
6299 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6300 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6301 gva_t vmcs_gva;
6302 struct x86_exception e;
6303
6304 if (!nested_vmx_check_permission(vcpu))
6305 return 1;
6306
6307 if (get_vmx_mem_address(vcpu, exit_qualification,
6308 vmx_instruction_info, &vmcs_gva))
6309 return 1;
6310 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6311 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6312 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6313 sizeof(u64), &e)) {
6314 kvm_inject_page_fault(vcpu, &e);
6315 return 1;
6316 }
6317 nested_vmx_succeed(vcpu);
6318 skip_emulated_instruction(vcpu);
6319 return 1;
6320}
6321
bfd0a56b
NHE		 6322/* Emulate the INVEPT instruction */
6323static int handle_invept(struct kvm_vcpu *vcpu)
6324{
6325 u32 vmx_instruction_info, types;
6326 unsigned long type;
6327 gva_t gva;
6328 struct x86_exception e;
6329 struct {
6330 u64 eptp, gpa;
6331 } operand;
6332 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6333
6334 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6335 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6336 kvm_queue_exception(vcpu, UD_VECTOR);
6337 return 1;
6338 }
6339
6340 if (!nested_vmx_check_permission(vcpu))
6341 return 1;
6342
6343 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6344 kvm_queue_exception(vcpu, UD_VECTOR);
6345 return 1;
6346 }
6347
6348 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6349 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6350
6351 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6352
6353 if (!(types & (1UL << type))) {
6354 nested_vmx_failValid(vcpu,
6355 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6356 return 1;
6357 }
6358
6359 /* According to the Intel VMX instruction reference, the memory
6360 * operand is read even if it isn't needed (e.g., for type==global)
6361 */
6362 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6363 vmx_instruction_info, &gva))
6364 return 1;
6365 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6366 sizeof(operand), &e)) {
6367 kvm_inject_page_fault(vcpu, &e);
6368 return 1;
6369 }
6370
6371 switch (type) {
6372 case VMX_EPT_EXTENT_CONTEXT:
6373 if ((operand.eptp & eptp_mask) !=
6374 (nested_ept_get_cr3(vcpu) & eptp_mask))
6375 break;
6376 case VMX_EPT_EXTENT_GLOBAL:
6377 kvm_mmu_sync_roots(vcpu);
6378 kvm_mmu_flush_tlb(vcpu);
6379 nested_vmx_succeed(vcpu);
6380 break;
6381 default:
6382 BUG_ON(1);
6383 break;
6384 }
6385
6386 skip_emulated_instruction(vcpu);
6387 return 1;
6388}
6389
6aa8b732
AK		 6390/*
6391 * The exit handlers return 1 if the exit was handled fully and guest execution
6392 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6393 * to be done to userspace and return 0.
6394 */
772e0318 6395static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6396 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6397 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6398 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6399 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6400 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6401 [EXIT_REASON_CR_ACCESS] = handle_cr,
6402 [EXIT_REASON_DR_ACCESS] = handle_dr,
6403 [EXIT_REASON_CPUID] = handle_cpuid,
6404 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6405 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6406 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6407 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6408 [EXIT_REASON_INVD] = handle_invd,
a7052897 6409 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6410 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6411 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6412 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6413 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6414 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6415 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6416 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6417 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6418 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6419 [EXIT_REASON_VMOFF] = handle_vmoff,
6420 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6421 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6422 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6423 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6424 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6425 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6426 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6427 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6428 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6429 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6430 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6431 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6432 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6433 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6434 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6435};
6436
6437static const int kvm_vmx_max_exit_handlers =
50a3485c 6438 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6439
908a7bdd
JK		 6440static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6441 struct vmcs12 *vmcs12)
6442{
6443 unsigned long exit_qualification;
6444 gpa_t bitmap, last_bitmap;
6445 unsigned int port;
6446 int size;
6447 u8 b;
6448
6449 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6450 return 1;
6451
6452 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6453 return 0;
6454
6455 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6456
6457 port = exit_qualification >> 16;
6458 size = (exit_qualification & 7) + 1;
6459
6460 last_bitmap = (gpa_t)-1;
6461 b = -1;
6462
6463 while (size > 0) {
6464 if (port < 0x8000)
6465 bitmap = vmcs12->io_bitmap_a;
6466 else if (port < 0x10000)
6467 bitmap = vmcs12->io_bitmap_b;
6468 else
6469 return 1;
6470 bitmap += (port & 0x7fff) / 8;
6471
6472 if (last_bitmap != bitmap)
6473 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6474 return 1;
6475 if (b & (1 << (port & 7)))
6476 return 1;
6477
6478 port++;
6479 size--;
6480 last_bitmap = bitmap;
6481 }
6482
6483 return 0;
6484}
6485
644d711a
NHE		 6486/*
6487 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6488 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6489 * disinterest in the current event (read or write a specific MSR) by using an
6490 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6491 */
6492static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6493 struct vmcs12 *vmcs12, u32 exit_reason)
6494{
6495 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6496 gpa_t bitmap;
6497
cbd29cb6 6498 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6499 return 1;
6500
6501 /*
6502 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6503 * for the four combinations of read/write and low/high MSR numbers.
6504 * First we need to figure out which of the four to use:
6505 */
6506 bitmap = vmcs12->msr_bitmap;
6507 if (exit_reason == EXIT_REASON_MSR_WRITE)
6508 bitmap += 2048;
6509 if (msr_index >= 0xc0000000) {
6510 msr_index -= 0xc0000000;
6511 bitmap += 1024;
6512 }
6513
6514 /* Then read the msr_index'th bit from this bitmap: */
6515 if (msr_index < 1024*8) {
6516 unsigned char b;
bd31a7f5
JK		 6517 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6518 return 1;
644d711a
NHE		 6519 return 1 & (b >> (msr_index & 7));
6520 } else
6521 return 1; /* let L1 handle the wrong parameter */
6522}
6523
6524/*
6525 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6526 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6527 * intercept (via guest_host_mask etc.) the current event.
6528 */
6529static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6530 struct vmcs12 *vmcs12)
6531{
6532 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6533 int cr = exit_qualification & 15;
6534 int reg = (exit_qualification >> 8) & 15;
6535 unsigned long val = kvm_register_read(vcpu, reg);
6536
6537 switch ((exit_qualification >> 4) & 3) {
6538 case 0: /* mov to cr */
6539 switch (cr) {
6540 case 0:
6541 if (vmcs12->cr0_guest_host_mask &
6542 (val ^ vmcs12->cr0_read_shadow))
6543 return 1;
6544 break;
6545 case 3:
6546 if ((vmcs12->cr3_target_count >= 1 &&
6547 vmcs12->cr3_target_value0 == val) ||
6548 (vmcs12->cr3_target_count >= 2 &&
6549 vmcs12->cr3_target_value1 == val) ||
6550 (vmcs12->cr3_target_count >= 3 &&
6551 vmcs12->cr3_target_value2 == val) ||
6552 (vmcs12->cr3_target_count >= 4 &&
6553 vmcs12->cr3_target_value3 == val))
6554 return 0;
6555 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6556 return 1;
6557 break;
6558 case 4:
6559 if (vmcs12->cr4_guest_host_mask &
6560 (vmcs12->cr4_read_shadow ^ val))
6561 return 1;
6562 break;
6563 case 8:
6564 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6565 return 1;
6566 break;
6567 }
6568 break;
6569 case 2: /* clts */
6570 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6571 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6572 return 1;
6573 break;
6574 case 1: /* mov from cr */
6575 switch (cr) {
6576 case 3:
6577 if (vmcs12->cpu_based_vm_exec_control &
6578 CPU_BASED_CR3_STORE_EXITING)
6579 return 1;
6580 break;
6581 case 8:
6582 if (vmcs12->cpu_based_vm_exec_control &
6583 CPU_BASED_CR8_STORE_EXITING)
6584 return 1;
6585 break;
6586 }
6587 break;
6588 case 3: /* lmsw */
6589 /*
6590 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6591 * cr0. Other attempted changes are ignored, with no exit.
6592 */
6593 if (vmcs12->cr0_guest_host_mask & 0xe &
6594 (val ^ vmcs12->cr0_read_shadow))
6595 return 1;
6596 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6597 !(vmcs12->cr0_read_shadow & 0x1) &&
6598 (val & 0x1))
6599 return 1;
6600 break;
6601 }
6602 return 0;
6603}
6604
6605/*
6606 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6607 * should handle it ourselves in L0 (and then continue L2). Only call this
6608 * when in is_guest_mode (L2).
6609 */
6610static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6611{
644d711a
NHE		 6612 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6613 struct vcpu_vmx *vmx = to_vmx(vcpu);
6614 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6615 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6616
6617 if (vmx->nested.nested_run_pending)
6618 return 0;
6619
6620 if (unlikely(vmx->fail)) {
bd80158a
JK		 6621 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6622 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6623 return 1;
6624 }
6625
6626 switch (exit_reason) {
6627 case EXIT_REASON_EXCEPTION_NMI:
6628 if (!is_exception(intr_info))
6629 return 0;
6630 else if (is_page_fault(intr_info))
6631 return enable_ept;
6632 return vmcs12->exception_bitmap &
6633 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6634 case EXIT_REASON_EXTERNAL_INTERRUPT:
6635 return 0;
6636 case EXIT_REASON_TRIPLE_FAULT:
6637 return 1;
6638 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6639 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6640 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6641 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6642 case EXIT_REASON_TASK_SWITCH:
6643 return 1;
6644 case EXIT_REASON_CPUID:
6645 return 1;
6646 case EXIT_REASON_HLT:
6647 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6648 case EXIT_REASON_INVD:
6649 return 1;
6650 case EXIT_REASON_INVLPG:
6651 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6652 case EXIT_REASON_RDPMC:
6653 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6654 case EXIT_REASON_RDTSC:
6655 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6656 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6657 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6658 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6659 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6660 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6661 case EXIT_REASON_INVEPT:
644d711a
NHE		 6662 /*
6663 * VMX instructions trap unconditionally. This allows L1 to
6664 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6665 */
6666 return 1;
6667 case EXIT_REASON_CR_ACCESS:
6668 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6669 case EXIT_REASON_DR_ACCESS:
6670 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6671 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6672 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6673 case EXIT_REASON_MSR_READ:
6674 case EXIT_REASON_MSR_WRITE:
6675 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6676 case EXIT_REASON_INVALID_STATE:
6677 return 1;
6678 case EXIT_REASON_MWAIT_INSTRUCTION:
6679 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6680 case EXIT_REASON_MONITOR_INSTRUCTION:
6681 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6682 case EXIT_REASON_PAUSE_INSTRUCTION:
6683 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6684 nested_cpu_has2(vmcs12,
6685 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6686 case EXIT_REASON_MCE_DURING_VMENTRY:
6687 return 0;
6688 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6689 return 1;
6690 case EXIT_REASON_APIC_ACCESS:
6691 return nested_cpu_has2(vmcs12,
6692 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6693 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6694 /*
6695 * L0 always deals with the EPT violation. If nested EPT is
6696 * used, and the nested mmu code discovers that the address is
6697 * missing in the guest EPT table (EPT12), the EPT violation
6698 * will be injected with nested_ept_inject_page_fault()
6699 */
6700 return 0;
644d711a 6701 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6702 /*
6703 * L2 never uses directly L1's EPT, but rather L0's own EPT
6704 * table (shadow on EPT) or a merged EPT table that L0 built
6705 * (EPT on EPT). So any problems with the structure of the
6706 * table is L0's fault.
6707 */
644d711a 6708 return 0;
0238ea91
JK		 6709 case EXIT_REASON_PREEMPTION_TIMER:
6710 return vmcs12->pin_based_vm_exec_control &
6711 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6712 case EXIT_REASON_WBINVD:
6713 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6714 case EXIT_REASON_XSETBV:
6715 return 1;
6716 default:
6717 return 1;
6718 }
6719}
6720
586f9607
AK		 6721static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6722{
6723 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6724 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6725}
6726
6aa8b732
AK		 6727/*
6728 * The guest has exited. See if we can fix it or if we need userspace
6729 * assistance.
6730 */
851ba692 6731static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6732{
29bd8a78 6733 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6734 u32 exit_reason = vmx->exit_reason;
1155f76a 6735 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6736
80ced186 6737 /* If guest state is invalid, start emulating */
14168786 6738 if (vmx->emulation_required)
80ced186 6739 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6740
644d711a
NHE		 6741 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6742 nested_vmx_vmexit(vcpu);
6743 return 1;
6744 }
6745
5120702e
MG		 6746 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6747 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6748 vcpu->run->fail_entry.hardware_entry_failure_reason
6749 = exit_reason;
6750 return 0;
6751 }
6752
29bd8a78 6753 if (unlikely(vmx->fail)) {
851ba692
AK		 6754 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6755 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6756 = vmcs_read32(VM_INSTRUCTION_ERROR);
6757 return 0;
6758 }
6aa8b732 6759
b9bf6882
XG		 6760 /*
6761 * Note:
6762 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6763 * delivery event since it indicates guest is accessing MMIO.
6764 * The vm-exit can be triggered again after return to guest that
6765 * will cause infinite loop.
6766 */
d77c26fc 6767 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6768 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6769 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6770 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6771 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6772 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6773 vcpu->run->internal.ndata = 2;
6774 vcpu->run->internal.data[0] = vectoring_info;
6775 vcpu->run->internal.data[1] = exit_reason;
6776 return 0;
6777 }
3b86cd99 6778
644d711a
NHE		 6779 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6780 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6781 get_vmcs12(vcpu))))) {
c4282df9 6782 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6783 vmx->soft_vnmi_blocked = 0;
3b86cd99 6784 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6785 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6786 /*
6787 * This CPU don't support us in finding the end of an
6788 * NMI-blocked window if the guest runs with IRQs
6789 * disabled. So we pull the trigger after 1 s of
6790 * futile waiting, but inform the user about this.
6791 */
6792 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6793 "state on VCPU %d after 1 s timeout\n",
6794 __func__, vcpu->vcpu_id);
6795 vmx->soft_vnmi_blocked = 0;
3b86cd99 6796 }
3b86cd99
JK		 6797 }
6798
6aa8b732
AK		 6799 if (exit_reason < kvm_vmx_max_exit_handlers
6800 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6801 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6802 else {
851ba692
AK		 6803 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6804 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6805 }
6806 return 0;
6807}
6808
95ba8273 6809static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6810{
95ba8273 6811 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6812 vmcs_write32(TPR_THRESHOLD, 0);
6813 return;
6814 }
6815
95ba8273 6816 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6817}
6818
8d14695f
YZ		 6819static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6820{
6821 u32 sec_exec_control;
6822
6823 /*
6824 * There is not point to enable virtualize x2apic without enable
6825 * apicv
6826 */
c7c9c56c
YZ		 6827 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6828 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6829 return;
6830
6831 if (!vm_need_tpr_shadow(vcpu->kvm))
6832 return;
6833
6834 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6835
6836 if (set) {
6837 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6838 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6839 } else {
6840 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6841 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6842 }
6843 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6844
6845 vmx_set_msr_bitmap(vcpu);
6846}
6847
c7c9c56c
YZ		 6848static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6849{
6850 u16 status;
6851 u8 old;
6852
6853 if (!vmx_vm_has_apicv(kvm))
6854 return;
6855
6856 if (isr == -1)
6857 isr = 0;
6858
6859 status = vmcs_read16(GUEST_INTR_STATUS);
6860 old = status >> 8;
6861 if (isr != old) {
6862 status &= 0xff;
6863 status |= isr << 8;
6864 vmcs_write16(GUEST_INTR_STATUS, status);
6865 }
6866}
6867
6868static void vmx_set_rvi(int vector)
6869{
6870 u16 status;
6871 u8 old;
6872
6873 status = vmcs_read16(GUEST_INTR_STATUS);
6874 old = (u8)status & 0xff;
6875 if ((u8)vector != old) {
6876 status &= ~0xff;
6877 status |= (u8)vector;
6878 vmcs_write16(GUEST_INTR_STATUS, status);
6879 }
6880}
6881
6882static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6883{
6884 if (max_irr == -1)
6885 return;
6886
6887 vmx_set_rvi(max_irr);
6888}
6889
6890static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6891{
3d81bc7e
YZ		 6892 if (!vmx_vm_has_apicv(vcpu->kvm))
6893 return;
6894
c7c9c56c
YZ		 6895 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6896 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6897 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6898 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6899}
6900
51aa01d1 6901static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6902{
00eba012
AK		 6903 u32 exit_intr_info;
6904
6905 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6906 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6907 return;
6908
c5ca8e57 6909 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6910 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6911
6912 /* Handle machine checks before interrupts are enabled */
00eba012 6913 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6914 kvm_machine_check();
6915
20f65983 6916 /* We need to handle NMIs before interrupts are enabled */
00eba012 6917 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6918 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6919 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6920 asm("int $2");
ff9d07a0
ZY		 6921 kvm_after_handle_nmi(&vmx->vcpu);
6922 }
51aa01d1 6923}
20f65983 6924
a547c6db
YZ		 6925static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6926{
6927 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6928
6929 /*
6930 * If external interrupt exists, IF bit is set in rflags/eflags on the
6931 * interrupt stack frame, and interrupt will be enabled on a return
6932 * from interrupt handler.
6933 */
6934 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6935 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6936 unsigned int vector;
6937 unsigned long entry;
6938 gate_desc *desc;
6939 struct vcpu_vmx *vmx = to_vmx(vcpu);
6940#ifdef CONFIG_X86_64
6941 unsigned long tmp;
6942#endif
6943
6944 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6945 desc = (gate_desc *)vmx->host_idt_base + vector;
6946 entry = gate_offset(*desc);
6947 asm volatile(
6948#ifdef CONFIG_X86_64
6949 "mov %%" _ASM_SP ", %[sp]\n\t"
6950 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6951 "push $%c[ss]\n\t"
6952 "push %[sp]\n\t"
6953#endif
6954 "pushf\n\t"
6955 "orl $0x200, (%%" _ASM_SP ")\n\t"
6956 __ASM_SIZE(push) " $%c[cs]\n\t"
6957 "call *%[entry]\n\t"
6958 :
6959#ifdef CONFIG_X86_64
6960 [sp]"=&r"(tmp)
6961#endif
6962 :
6963 [entry]"r"(entry),
6964 [ss]"i"(__KERNEL_DS),
6965 [cs]"i"(__KERNEL_CS)
6966 );
6967 } else
6968 local_irq_enable();
6969}
6970
51aa01d1
AK		 6971static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6972{
c5ca8e57 6973 u32 exit_intr_info;
51aa01d1
AK		 6974 bool unblock_nmi;
6975 u8 vector;
6976 bool idtv_info_valid;
6977
6978 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6979
cf393f75 6980 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6981 if (vmx->nmi_known_unmasked)
6982 return;
c5ca8e57
AK		 6983 /*
6984 * Can't use vmx->exit_intr_info since we're not sure what
6985 * the exit reason is.
6986 */
6987 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6988 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6989 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6990 /*
7b4a25cb 6991 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6992 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6993 * a guest IRET fault.
7b4a25cb
GN		 6994 * SDM 3: 23.2.2 (September 2008)
6995 * Bit 12 is undefined in any of the following cases:
6996 * If the VM exit sets the valid bit in the IDT-vectoring
6997 * information field.
6998 * If the VM exit is due to a double fault.
cf393f75 6999 */
7b4a25cb
GN		 7000 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7001 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7002 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7003 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7004 else
7005 vmx->nmi_known_unmasked =
7006 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7007 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7008 } else if (unlikely(vmx->soft_vnmi_blocked))
7009 vmx->vnmi_blocked_time +=
7010 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7011}
7012
3ab66e8a 7013static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7014 u32 idt_vectoring_info,
7015 int instr_len_field,
7016 int error_code_field)
51aa01d1 7017{
51aa01d1
AK		 7018 u8 vector;
7019 int type;
7020 bool idtv_info_valid;
7021
7022 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7023
3ab66e8a
JK		 7024 vcpu->arch.nmi_injected = false;
7025 kvm_clear_exception_queue(vcpu);
7026 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7027
7028 if (!idtv_info_valid)
7029 return;
7030
3ab66e8a 7031 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7032
668f612f
AK		 7033 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7034 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7035
64a7ec06 7036 switch (type) {
37b96e98 7037 case INTR_TYPE_NMI_INTR:
3ab66e8a 7038 vcpu->arch.nmi_injected = true;
668f612f 7039 /*
7b4a25cb 7040 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7041 * Clear bit "block by NMI" before VM entry if a NMI
7042 * delivery faulted.
668f612f 7043 */
3ab66e8a 7044 vmx_set_nmi_mask(vcpu, false);
37b96e98 7045 break;
37b96e98 7046 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7047 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7048 /* fall through */
7049 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7050 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7051 u32 err = vmcs_read32(error_code_field);
851eb667 7052 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7053 } else
851eb667 7054 kvm_requeue_exception(vcpu, vector);
37b96e98 7055 break;
66fd3f7f 7056 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7057 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7058 /* fall through */
37b96e98 7059 case INTR_TYPE_EXT_INTR:
3ab66e8a 7060 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7061 break;
7062 default:
7063 break;
f7d9238f 7064 }
cf393f75
AK		 7065}
7066
83422e17
AK		 7067static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7068{
3ab66e8a 7069 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7070 VM_EXIT_INSTRUCTION_LEN,
7071 IDT_VECTORING_ERROR_CODE);
7072}
7073
b463a6f7
AK		 7074static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7075{
3ab66e8a 7076 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7077 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7078 VM_ENTRY_INSTRUCTION_LEN,
7079 VM_ENTRY_EXCEPTION_ERROR_CODE);
7080
7081 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7082}
7083
d7cd9796
GN		 7084static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7085{
7086 int i, nr_msrs;
7087 struct perf_guest_switch_msr *msrs;
7088
7089 msrs = perf_guest_get_msrs(&nr_msrs);
7090
7091 if (!msrs)
7092 return;
7093
7094 for (i = 0; i < nr_msrs; i++)
7095 if (msrs[i].host == msrs[i].guest)
7096 clear_atomic_switch_msr(vmx, msrs[i].msr);
7097 else
7098 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7099 msrs[i].host);
7100}
7101
a3b5ba49 7102static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7103{
a2fa3e9f 7104 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7105 unsigned long debugctlmsr;
104f226b
AK		 7106
7107 /* Record the guest's net vcpu time for enforced NMI injections. */
7108 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7109 vmx->entry_time = ktime_get();
7110
7111 /* Don't enter VMX if guest state is invalid, let the exit handler
7112 start emulation until we arrive back to a valid state */
14168786 7113 if (vmx->emulation_required)
104f226b
AK		 7114 return;
7115
012f83cb
AG		 7116 if (vmx->nested.sync_shadow_vmcs) {
7117 copy_vmcs12_to_shadow(vmx);
7118 vmx->nested.sync_shadow_vmcs = false;
7119 }
7120
104f226b
AK		 7121 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7122 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7123 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7124 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7125
7126 /* When single-stepping over STI and MOV SS, we must clear the
7127 * corresponding interruptibility bits in the guest state. Otherwise
7128 * vmentry fails as it then expects bit 14 (BS) in pending debug
7129 * exceptions being set, but that's not correct for the guest debugging
7130 * case. */
7131 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7132 vmx_set_interrupt_shadow(vcpu, 0);
7133
d7cd9796 7134 atomic_switch_perf_msrs(vmx);
2a7921b7 7135 debugctlmsr = get_debugctlmsr();
d7cd9796 7136
d462b819 7137 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7138 asm(
6aa8b732 7139 /* Store host registers */
b188c81f
AK		 7140 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7141 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7142 "push %%" _ASM_CX " \n\t"
7143 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7144 "je 1f \n\t"
b188c81f 7145 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7146 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7147 "1: \n\t"
d3edefc0 7148 /* Reload cr2 if changed */
b188c81f
AK		 7149 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7150 "mov %%cr2, %%" _ASM_DX " \n\t"
7151 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7152 "je 2f \n\t"
b188c81f 7153 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7154 "2: \n\t"
6aa8b732 7155 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7156 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7157 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7158 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7159 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7160 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7161 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7162 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7163 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7164#ifdef CONFIG_X86_64
e08aa78a
AK		 7165 "mov %c[r8](%0), %%r8 \n\t"
7166 "mov %c[r9](%0), %%r9 \n\t"
7167 "mov %c[r10](%0), %%r10 \n\t"
7168 "mov %c[r11](%0), %%r11 \n\t"
7169 "mov %c[r12](%0), %%r12 \n\t"
7170 "mov %c[r13](%0), %%r13 \n\t"
7171 "mov %c[r14](%0), %%r14 \n\t"
7172 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7173#endif
b188c81f 7174 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7175
6aa8b732 7176 /* Enter guest mode */
83287ea4 7177 "jne 1f \n\t"
4ecac3fd 7178 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7179 "jmp 2f \n\t"
7180 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7181 "2: "
6aa8b732 7182 /* Save guest registers, load host registers, keep flags */
b188c81f 7183 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7184 "pop %0 \n\t"
b188c81f
AK		 7185 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7186 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7187 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7188 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7189 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7190 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7191 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7192#ifdef CONFIG_X86_64
e08aa78a
AK		 7193 "mov %%r8, %c[r8](%0) \n\t"
7194 "mov %%r9, %c[r9](%0) \n\t"
7195 "mov %%r10, %c[r10](%0) \n\t"
7196 "mov %%r11, %c[r11](%0) \n\t"
7197 "mov %%r12, %c[r12](%0) \n\t"
7198 "mov %%r13, %c[r13](%0) \n\t"
7199 "mov %%r14, %c[r14](%0) \n\t"
7200 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7201#endif
b188c81f
AK		 7202 "mov %%cr2, %%" _ASM_AX " \n\t"
7203 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7204
b188c81f 7205 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7206 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7207 ".pushsection .rodata \n\t"
7208 ".global vmx_return \n\t"
7209 "vmx_return: " _ASM_PTR " 2b \n\t"
7210 ".popsection"
e08aa78a 7211 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7212 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7213 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7214 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7215 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7216 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7217 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7218 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7219 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7220 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7221 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7222#ifdef CONFIG_X86_64
ad312c7c
ZX		 7223 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7224 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7225 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7226 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7227 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7228 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7229 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7230 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7231#endif
40712fae
AK		 7232 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7233 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7234 : "cc", "memory"
7235#ifdef CONFIG_X86_64
b188c81f 7236 , "rax", "rbx", "rdi", "rsi"
c2036300 7237 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7238#else
7239 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7240#endif
7241 );
6aa8b732 7242
2a7921b7
GN		 7243 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7244 if (debugctlmsr)
7245 update_debugctlmsr(debugctlmsr);
7246
aa67f609
AK		 7247#ifndef CONFIG_X86_64
7248 /*
7249 * The sysexit path does not restore ds/es, so we must set them to
7250 * a reasonable value ourselves.
7251 *
7252 * We can't defer this to vmx_load_host_state() since that function
7253 * may be executed in interrupt context, which saves and restore segments
7254 * around it, nullifying its effect.
7255 */
7256 loadsegment(ds, __USER_DS);
7257 loadsegment(es, __USER_DS);
7258#endif
7259
6de4f3ad 7260 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7261 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7262 | (1 << VCPU_EXREG_CPL)
aff48baa 7263 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7264 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7265 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7266 vcpu->arch.regs_dirty = 0;
7267
1155f76a
AK		 7268 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7269
d462b819 7270 vmx->loaded_vmcs->launched = 1;
1b6269db 7271
51aa01d1 7272 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7273 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7274
e0b890d3
GN		 7275 /*
7276 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7277 * we did not inject a still-pending event to L1 now because of
7278 * nested_run_pending, we need to re-enable this bit.
7279 */
7280 if (vmx->nested.nested_run_pending)
7281 kvm_make_request(KVM_REQ_EVENT, vcpu);
7282
7283 vmx->nested.nested_run_pending = 0;
7284
51aa01d1
AK		 7285 vmx_complete_atomic_exit(vmx);
7286 vmx_recover_nmi_blocking(vmx);
cf393f75 7287 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7288}
7289
6aa8b732
AK		 7290static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7291{
fb3f0f51
RR		 7292 struct vcpu_vmx *vmx = to_vmx(vcpu);
7293
cdbecfc3 7294 free_vpid(vmx);
ec378aee 7295 free_nested(vmx);
d462b819 7296 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7297 kfree(vmx->guest_msrs);
7298 kvm_vcpu_uninit(vcpu);
a4770347 7299 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7300}
7301
fb3f0f51 7302static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7303{
fb3f0f51 7304 int err;
c16f862d 7305 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7306 int cpu;
6aa8b732 7307
a2fa3e9f 7308 if (!vmx)
fb3f0f51
RR		 7309 return ERR_PTR(-ENOMEM);
7310
2384d2b3
SY		 7311 allocate_vpid(vmx);
7312
fb3f0f51
RR		 7313 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7314 if (err)
7315 goto free_vcpu;
965b58a5 7316
a2fa3e9f 7317 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7318 err = -ENOMEM;
fb3f0f51 7319 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7320 goto uninit_vcpu;
7321 }
965b58a5 7322
d462b819
NHE		 7323 vmx->loaded_vmcs = &vmx->vmcs01;
7324 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7325 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7326 goto free_msrs;
d462b819
NHE		 7327 if (!vmm_exclusive)
7328 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7329 loaded_vmcs_init(vmx->loaded_vmcs);
7330 if (!vmm_exclusive)
7331 kvm_cpu_vmxoff();
a2fa3e9f 7332
15ad7146
AK		 7333 cpu = get_cpu();
7334 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7335 vmx->vcpu.cpu = cpu;
8b9cf98c 7336 err = vmx_vcpu_setup(vmx);
fb3f0f51 7337 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7338 put_cpu();
fb3f0f51
RR		 7339 if (err)
7340 goto free_vmcs;
a63cb560 7341 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7342 err = alloc_apic_access_page(kvm);
7343 if (err)
5e4a0b3c 7344 goto free_vmcs;
a63cb560 7345 }
fb3f0f51 7346
b927a3ce
SY		 7347 if (enable_ept) {
7348 if (!kvm->arch.ept_identity_map_addr)
7349 kvm->arch.ept_identity_map_addr =
7350 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7351 err = -ENOMEM;
b7ebfb05
SY		 7352 if (alloc_identity_pagetable(kvm) != 0)
7353 goto free_vmcs;
93ea5388
GN		 7354 if (!init_rmode_identity_map(kvm))
7355 goto free_vmcs;
b927a3ce 7356 }
b7ebfb05 7357
a9d30f33
NHE		 7358 vmx->nested.current_vmptr = -1ull;
7359 vmx->nested.current_vmcs12 = NULL;
7360
fb3f0f51
RR		 7361 return &vmx->vcpu;
7362
7363free_vmcs:
5f3fbc34 7364 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7365free_msrs:
fb3f0f51
RR		 7366 kfree(vmx->guest_msrs);
7367uninit_vcpu:
7368 kvm_vcpu_uninit(&vmx->vcpu);
7369free_vcpu:
cdbecfc3 7370 free_vpid(vmx);
a4770347 7371 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7372 return ERR_PTR(err);
6aa8b732
AK		 7373}
7374
002c7f7c
YS		 7375static void __init vmx_check_processor_compat(void *rtn)
7376{
7377 struct vmcs_config vmcs_conf;
7378
7379 *(int *)rtn = 0;
7380 if (setup_vmcs_config(&vmcs_conf) < 0)
7381 *(int *)rtn = -EIO;
7382 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7383 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7384 smp_processor_id());
7385 *(int *)rtn = -EIO;
7386 }
7387}
7388
67253af5
SY		 7389static int get_ept_level(void)
7390{
7391 return VMX_EPT_DEFAULT_GAW + 1;
7392}
7393
4b12f0de 7394static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7395{
4b12f0de
SY		 7396 u64 ret;
7397
522c68c4
SY		 7398 /* For VT-d and EPT combination
7399 * 1. MMIO: always map as UC
7400 * 2. EPT with VT-d:
7401 * a. VT-d without snooping control feature: can't guarantee the
7402 * result, try to trust guest.
7403 * b. VT-d with snooping control feature: snooping control feature of
7404 * VT-d engine can guarantee the cache correctness. Just set it
7405 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7406 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7407 * consistent with host MTRR
7408 */
4b12f0de
SY		 7409 if (is_mmio)
7410 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7411 else if (vcpu->kvm->arch.iommu_domain &&
7412 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7413 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7414 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7415 else
522c68c4 7416 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7417 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7418
7419 return ret;
64d4d521
SY		 7420}
7421
17cc3935 7422static int vmx_get_lpage_level(void)
344f414f 7423{
878403b7
SY		 7424 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7425 return PT_DIRECTORY_LEVEL;
7426 else
7427 /* For shadow and EPT supported 1GB page */
7428 return PT_PDPE_LEVEL;
344f414f
JR		 7429}
7430
0e851880
SY		 7431static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7432{
4e47c7a6
SY		 7433 struct kvm_cpuid_entry2 *best;
7434 struct vcpu_vmx *vmx = to_vmx(vcpu);
7435 u32 exec_control;
7436
7437 vmx->rdtscp_enabled = false;
7438 if (vmx_rdtscp_supported()) {
7439 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7440 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7441 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7442 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7443 vmx->rdtscp_enabled = true;
7444 else {
7445 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7446 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7447 exec_control);
7448 }
7449 }
7450 }
ad756a16 7451
ad756a16
MJ		 7452 /* Exposing INVPCID only when PCID is exposed */
7453 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7454 if (vmx_invpcid_supported() &&
4f977045 7455 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7456 guest_cpuid_has_pcid(vcpu)) {
29282fde 7457 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7458 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7459 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7460 exec_control);
7461 } else {
29282fde
TI		 7462 if (cpu_has_secondary_exec_ctrls()) {
7463 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7464 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7465 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7466 exec_control);
7467 }
ad756a16 7468 if (best)
4f977045 7469 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7470 }
0e851880
SY		 7471}
7472
d4330ef2
JR		 7473static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7474{
7b8050f5
NHE		 7475 if (func == 1 && nested)
7476 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7477}
7478
25d92081
YZ		 7479static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7480 struct x86_exception *fault)
7481{
7482 struct vmcs12 *vmcs12;
7483 nested_vmx_vmexit(vcpu);
7484 vmcs12 = get_vmcs12(vcpu);
7485
7486 if (fault->error_code & PFERR_RSVD_MASK)
7487 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7488 else
7489 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7490 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7491 vmcs12->guest_physical_address = fault->address;
7492}
7493
155a97a3
NHE		 7494/* Callbacks for nested_ept_init_mmu_context: */
7495
7496static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7497{
7498 /* return the page table to be shadowed - in our case, EPT12 */
7499 return get_vmcs12(vcpu)->ept_pointer;
7500}
7501
7502static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7503{
7504 int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7505 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7506
7507 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7508 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7509 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7510
7511 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7512
7513 return r;
7514}
7515
7516static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7517{
7518 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7519}
7520
fe3ef05c
NHE		 7521/*
7522 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7523 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7524 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7525 * guest in a way that will both be appropriate to L1's requests, and our
7526 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7527 * function also has additional necessary side-effects, like setting various
7528 * vcpu->arch fields.
7529 */
7530static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7531{
7532 struct vcpu_vmx *vmx = to_vmx(vcpu);
7533 u32 exec_control;
7534
7535 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7536 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7537 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7538 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7539 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7540 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7541 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7542 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7543 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7544 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7545 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7546 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7547 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7548 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7549 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7550 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7551 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7552 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7553 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7554 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7555 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7556 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7557 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7558 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7559 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7560 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7561 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7562 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7563 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7564 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7565 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7566 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7567 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7568 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7569 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7570 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7571
7572 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7573 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7574 vmcs12->vm_entry_intr_info_field);
7575 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7576 vmcs12->vm_entry_exception_error_code);
7577 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7578 vmcs12->vm_entry_instruction_len);
7579 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7580 vmcs12->guest_interruptibility_info);
fe3ef05c 7581 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7582 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7583 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7584 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7585 vmcs12->guest_pending_dbg_exceptions);
7586 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7587 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7588
7589 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7590
7591 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7592 (vmcs_config.pin_based_exec_ctrl |
7593 vmcs12->pin_based_vm_exec_control));
7594
0238ea91
JK		 7595 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7596 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7597 vmcs12->vmx_preemption_timer_value);
7598
fe3ef05c
NHE		 7599 /*
7600 * Whether page-faults are trapped is determined by a combination of
7601 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7602 * If enable_ept, L0 doesn't care about page faults and we should
7603 * set all of these to L1's desires. However, if !enable_ept, L0 does
7604 * care about (at least some) page faults, and because it is not easy
7605 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7606 * to exit on each and every L2 page fault. This is done by setting
7607 * MASK=MATCH=0 and (see below) EB.PF=1.
7608 * Note that below we don't need special code to set EB.PF beyond the
7609 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7610 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7611 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7612 *
7613 * A problem with this approach (when !enable_ept) is that L1 may be
7614 * injected with more page faults than it asked for. This could have
7615 * caused problems, but in practice existing hypervisors don't care.
7616 * To fix this, we will need to emulate the PFEC checking (on the L1
7617 * page tables), using walk_addr(), when injecting PFs to L1.
7618 */
7619 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7620 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7621 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7622 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7623
7624 if (cpu_has_secondary_exec_ctrls()) {
7625 u32 exec_control = vmx_secondary_exec_control(vmx);
7626 if (!vmx->rdtscp_enabled)
7627 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7628 /* Take the following fields only from vmcs12 */
7629 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7630 if (nested_cpu_has(vmcs12,
7631 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7632 exec_control |= vmcs12->secondary_vm_exec_control;
7633
7634 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7635 /*
7636 * Translate L1 physical address to host physical
7637 * address for vmcs02. Keep the page pinned, so this
7638 * physical address remains valid. We keep a reference
7639 * to it so we can release it later.
7640 */
7641 if (vmx->nested.apic_access_page) /* shouldn't happen */
7642 nested_release_page(vmx->nested.apic_access_page);
7643 vmx->nested.apic_access_page =
7644 nested_get_page(vcpu, vmcs12->apic_access_addr);
7645 /*
7646 * If translation failed, no matter: This feature asks
7647 * to exit when accessing the given address, and if it
7648 * can never be accessed, this feature won't do
7649 * anything anyway.
7650 */
7651 if (!vmx->nested.apic_access_page)
7652 exec_control &=
7653 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7654 else
7655 vmcs_write64(APIC_ACCESS_ADDR,
7656 page_to_phys(vmx->nested.apic_access_page));
7657 }
7658
7659 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7660 }
7661
7662
7663 /*
7664 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7665 * Some constant fields are set here by vmx_set_constant_host_state().
7666 * Other fields are different per CPU, and will be set later when
7667 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7668 */
a547c6db 7669 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7670
7671 /*
7672 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7673 * entry, but only if the current (host) sp changed from the value
7674 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7675 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7676 * here we just force the write to happen on entry.
7677 */
7678 vmx->host_rsp = 0;
7679
7680 exec_control = vmx_exec_control(vmx); /* L0's desires */
7681 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7682 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7683 exec_control &= ~CPU_BASED_TPR_SHADOW;
7684 exec_control |= vmcs12->cpu_based_vm_exec_control;
7685 /*
7686 * Merging of IO and MSR bitmaps not currently supported.
7687 * Rather, exit every time.
7688 */
7689 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7690 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7691 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7692
7693 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7694
7695 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7696 * bitwise-or of what L1 wants to trap for L2, and what we want to
7697 * trap. Note that CR0.TS also needs updating - we do this later.
7698 */
7699 update_exception_bitmap(vcpu);
7700 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7701 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7702
8049d651
NHE		 7703 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7704 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7705 * bits are further modified by vmx_set_efer() below.
7706 */
7707 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7708
7709 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7710 * emulated by vmx_set_efer(), below.
7711 */
7712 vmcs_write32(VM_ENTRY_CONTROLS,
7713 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7714 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7715 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7716
44811c02 7717 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7718 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7719 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7720 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7721 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7722
7723
7724 set_cr4_guest_host_mask(vmx);
7725
27fc51b2
NHE		 7726 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7727 vmcs_write64(TSC_OFFSET,
7728 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7729 else
7730 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7731
7732 if (enable_vpid) {
7733 /*
7734 * Trivially support vpid by letting L2s share their parent
7735 * L1's vpid. TODO: move to a more elaborate solution, giving
7736 * each L2 its own vpid and exposing the vpid feature to L1.
7737 */
7738 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7739 vmx_flush_tlb(vcpu);
7740 }
7741
155a97a3
NHE		 7742 if (nested_cpu_has_ept(vmcs12)) {
7743 kvm_mmu_unload(vcpu);
7744 nested_ept_init_mmu_context(vcpu);
7745 }
7746
fe3ef05c
NHE		 7747 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7748 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7749 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7750 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7751 else
7752 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7753 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7754 vmx_set_efer(vcpu, vcpu->arch.efer);
7755
7756 /*
7757 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7758 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7759 * The CR0_READ_SHADOW is what L2 should have expected to read given
7760 * the specifications by L1; It's not enough to take
7761 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7762 * have more bits than L1 expected.
7763 */
7764 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7765 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7766
7767 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7768 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7769
7770 /* shadow page tables on either EPT or shadow page tables */
7771 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7772 kvm_mmu_reset_context(vcpu);
7773
3633cfc3
NHE		 7774 /*
7775 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7776 */
7777 if (enable_ept) {
7778 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7779 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7780 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7781 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
72f85795
GN		 7782 __clear_bit(VCPU_EXREG_PDPTR,
7783 (unsigned long *)&vcpu->arch.regs_avail);
7784 __clear_bit(VCPU_EXREG_PDPTR,
7785 (unsigned long *)&vcpu->arch.regs_dirty);
3633cfc3
NHE		 7786 }
7787
fe3ef05c
NHE		 7788 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7789 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7790}
7791
cd232ad0
NHE		 7792/*
7793 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7794 * for running an L2 nested guest.
7795 */
7796static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7797{
7798 struct vmcs12 *vmcs12;
7799 struct vcpu_vmx *vmx = to_vmx(vcpu);
7800 int cpu;
7801 struct loaded_vmcs *vmcs02;
384bb783 7802 bool ia32e;
cd232ad0
NHE		 7803
7804 if (!nested_vmx_check_permission(vcpu) ||
7805 !nested_vmx_check_vmcs12(vcpu))
7806 return 1;
7807
7808 skip_emulated_instruction(vcpu);
7809 vmcs12 = get_vmcs12(vcpu);
7810
012f83cb
AG		 7811 if (enable_shadow_vmcs)
7812 copy_shadow_to_vmcs12(vmx);
7813
7c177938
NHE		 7814 /*
7815 * The nested entry process starts with enforcing various prerequisites
7816 * on vmcs12 as required by the Intel SDM, and act appropriately when
7817 * they fail: As the SDM explains, some conditions should cause the
7818 * instruction to fail, while others will cause the instruction to seem
7819 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7820 * To speed up the normal (success) code path, we should avoid checking
7821 * for misconfigurations which will anyway be caught by the processor
7822 * when using the merged vmcs02.
7823 */
7824 if (vmcs12->launch_state == launch) {
7825 nested_vmx_failValid(vcpu,
7826 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7827 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7828 return 1;
7829 }
7830
26539bd0
PB		 7831 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7832 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7833 return 1;
7834 }
7835
7c177938
NHE		 7836 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7837 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7838 /*TODO: Also verify bits beyond physical address width are 0*/
7839 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7840 return 1;
7841 }
7842
7843 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7844 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7845 /*TODO: Also verify bits beyond physical address width are 0*/
7846 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7847 return 1;
7848 }
7849
7850 if (vmcs12->vm_entry_msr_load_count > 0 ||
7851 vmcs12->vm_exit_msr_load_count > 0 ||
7852 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7853 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7854 __func__);
7c177938
NHE		 7855 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7856 return 1;
7857 }
7858
7859 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7860 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7861 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7862 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7863 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7864 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7865 !vmx_control_verify(vmcs12->vm_exit_controls,
7866 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7867 !vmx_control_verify(vmcs12->vm_entry_controls,
7868 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7869 {
7870 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7871 return 1;
7872 }
7873
7874 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7875 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7876 nested_vmx_failValid(vcpu,
7877 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7878 return 1;
7879 }
7880
92fbc7b1 7881 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 7882 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7883 nested_vmx_entry_failure(vcpu, vmcs12,
7884 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7885 return 1;
7886 }
7887 if (vmcs12->vmcs_link_pointer != -1ull) {
7888 nested_vmx_entry_failure(vcpu, vmcs12,
7889 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7890 return 1;
7891 }
7892
384bb783 7893 /*
cb0c8cda 7894 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7895 * are performed on the field for the IA32_EFER MSR:
7896 * - Bits reserved in the IA32_EFER MSR must be 0.
7897 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7898 * the IA-32e mode guest VM-exit control. It must also be identical
7899 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7900 * CR0.PG) is 1.
7901 */
7902 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7903 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7904 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7905 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7906 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7907 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7908 nested_vmx_entry_failure(vcpu, vmcs12,
7909 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7910 return 1;
7911 }
7912 }
7913
7914 /*
7915 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7916 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7917 * the values of the LMA and LME bits in the field must each be that of
7918 * the host address-space size VM-exit control.
7919 */
7920 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7921 ia32e = (vmcs12->vm_exit_controls &
7922 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7923 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7924 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7925 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7926 nested_vmx_entry_failure(vcpu, vmcs12,
7927 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7928 return 1;
7929 }
7930 }
7931
7c177938
NHE		 7932 /*
7933 * We're finally done with prerequisite checking, and can start with
7934 * the nested entry.
7935 */
7936
cd232ad0
NHE		 7937 vmcs02 = nested_get_current_vmcs02(vmx);
7938 if (!vmcs02)
7939 return -ENOMEM;
7940
7941 enter_guest_mode(vcpu);
7942
e0b890d3
GN		 7943 vmx->nested.nested_run_pending = 1;
7944
cd232ad0
NHE		 7945 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7946
7947 cpu = get_cpu();
7948 vmx->loaded_vmcs = vmcs02;
7949 vmx_vcpu_put(vcpu);
7950 vmx_vcpu_load(vcpu, cpu);
7951 vcpu->cpu = cpu;
7952 put_cpu();
7953
36c3cc42
JK		 7954 vmx_segment_cache_clear(vmx);
7955
cd232ad0
NHE		 7956 vmcs12->launch_state = 1;
7957
7958 prepare_vmcs02(vcpu, vmcs12);
7959
7960 /*
7961 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7962 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7963 * returned as far as L1 is concerned. It will only return (and set
7964 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7965 */
7966 return 1;
7967}
7968
4704d0be
NHE		 7969/*
7970 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7971 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7972 * This function returns the new value we should put in vmcs12.guest_cr0.
7973 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7974 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7975 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7976 * didn't trap the bit, because if L1 did, so would L0).
7977 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7978 * been modified by L2, and L1 knows it. So just leave the old value of
7979 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7980 * isn't relevant, because if L0 traps this bit it can set it to anything.
7981 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7982 * changed these bits, and therefore they need to be updated, but L0
7983 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7984 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7985 */
7986static inline unsigned long
7987vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7988{
7989 return
7990 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7991 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7992 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7993 vcpu->arch.cr0_guest_owned_bits));
7994}
7995
7996static inline unsigned long
7997vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7998{
7999 return
8000 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8001 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8002 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8003 vcpu->arch.cr4_guest_owned_bits));
8004}
8005
5f3d5799
JK		 8006static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8007 struct vmcs12 *vmcs12)
8008{
8009 u32 idt_vectoring;
8010 unsigned int nr;
8011
851eb667 8012 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8013 nr = vcpu->arch.exception.nr;
8014 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8015
8016 if (kvm_exception_is_soft(nr)) {
8017 vmcs12->vm_exit_instruction_len =
8018 vcpu->arch.event_exit_inst_len;
8019 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8020 } else
8021 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8022
8023 if (vcpu->arch.exception.has_error_code) {
8024 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8025 vmcs12->idt_vectoring_error_code =
8026 vcpu->arch.exception.error_code;
8027 }
8028
8029 vmcs12->idt_vectoring_info_field = idt_vectoring;
8030 } else if (vcpu->arch.nmi_pending) {
8031 vmcs12->idt_vectoring_info_field =
8032 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8033 } else if (vcpu->arch.interrupt.pending) {
8034 nr = vcpu->arch.interrupt.nr;
8035 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8036
8037 if (vcpu->arch.interrupt.soft) {
8038 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8039 vmcs12->vm_entry_instruction_len =
8040 vcpu->arch.event_exit_inst_len;
8041 } else
8042 idt_vectoring |= INTR_TYPE_EXT_INTR;
8043
8044 vmcs12->idt_vectoring_info_field = idt_vectoring;
8045 }
8046}
8047
4704d0be
NHE		 8048/*
8049 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8050 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8051 * and this function updates it to reflect the changes to the guest state while
8052 * L2 was running (and perhaps made some exits which were handled directly by L0
8053 * without going back to L1), and to reflect the exit reason.
8054 * Note that we do not have to copy here all VMCS fields, just those that
8055 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8056 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8057 * which already writes to vmcs12 directly.
8058 */
733568f9 8059static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8060{
8061 /* update guest state fields: */
8062 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8063 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8064
8065 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8066 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8067 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8068 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8069
8070 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8071 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8072 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8073 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8074 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8075 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8076 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8077 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8078 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8079 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8080 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8081 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8082 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8083 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8084 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8085 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8086 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8087 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8088 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8089 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8090 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8091 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8092 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8093 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8094 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8095 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8096 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8097 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8098 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8099 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8100 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8101 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8102 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8103 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8104 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8105 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8106
4704d0be
NHE		 8107 vmcs12->guest_interruptibility_info =
8108 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8109 vmcs12->guest_pending_dbg_exceptions =
8110 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8111
3633cfc3
NHE		 8112 /*
8113 * In some cases (usually, nested EPT), L2 is allowed to change its
8114 * own CR3 without exiting. If it has changed it, we must keep it.
8115 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8116 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8117 *
8118 * Additionally, restore L2's PDPTR to vmcs12.
8119 */
8120 if (enable_ept) {
8121 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8122 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8123 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8124 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8125 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8126 }
8127
c18911a2
JK		 8128 vmcs12->vm_entry_controls =
8129 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8130 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8131
4704d0be
NHE		 8132 /* TODO: These cannot have changed unless we have MSR bitmaps and
8133 * the relevant bit asks not to trap the change */
8134 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8135 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8136 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8137 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8138 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8139 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8140 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8141 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8142
8143 /* update exit information fields: */
8144
957c897e 8145 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8146 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8147
8148 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8149 if ((vmcs12->vm_exit_intr_info &
8150 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8151 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8152 vmcs12->vm_exit_intr_error_code =
8153 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8154 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8155 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8156 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8157
5f3d5799
JK		 8158 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8159 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8160 * instead of reading the real value. */
4704d0be 8161 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8162
8163 /*
8164 * Transfer the event that L0 or L1 may wanted to inject into
8165 * L2 to IDT_VECTORING_INFO_FIELD.
8166 */
8167 vmcs12_save_pending_event(vcpu, vmcs12);
8168 }
8169
8170 /*
8171 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8172 * preserved above and would only end up incorrectly in L1.
8173 */
8174 vcpu->arch.nmi_injected = false;
8175 kvm_clear_exception_queue(vcpu);
8176 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8177}
8178
8179/*
8180 * A part of what we need to when the nested L2 guest exits and we want to
8181 * run its L1 parent, is to reset L1's guest state to the host state specified
8182 * in vmcs12.
8183 * This function is to be called not only on normal nested exit, but also on
8184 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8185 * Failures During or After Loading Guest State").
8186 * This function should be called when the active VMCS is L1's (vmcs01).
8187 */
733568f9
JK		 8188static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8189 struct vmcs12 *vmcs12)
4704d0be 8190{
21feb4eb
ACL		 8191 struct kvm_segment seg;
8192
4704d0be
NHE		 8193 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8194 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8195 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8196 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8197 else
8198 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8199 vmx_set_efer(vcpu, vcpu->arch.efer);
8200
8201 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8202 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8203 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8204 /*
8205 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8206 * actually changed, because it depends on the current state of
8207 * fpu_active (which may have changed).
8208 * Note that vmx_set_cr0 refers to efer set above.
8209 */
9e3e4dbf 8210 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8211 /*
8212 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8213 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8214 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8215 */
8216 update_exception_bitmap(vcpu);
8217 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8218 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8219
8220 /*
8221 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8222 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8223 */
8224 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8225 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8226
155a97a3
NHE		 8227 if (nested_cpu_has_ept(vmcs12))
8228 nested_ept_uninit_mmu_context(vcpu);
8229
4704d0be
NHE		 8230 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8231 kvm_mmu_reset_context(vcpu);
8232
8233 if (enable_vpid) {
8234 /*
8235 * Trivially support vpid by letting L2s share their parent
8236 * L1's vpid. TODO: move to a more elaborate solution, giving
8237 * each L2 its own vpid and exposing the vpid feature to L1.
8238 */
8239 vmx_flush_tlb(vcpu);
8240 }
8241
8242
8243 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8244 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8245 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8246 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8247 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8248
44811c02 8249 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8250 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8251 vcpu->arch.pat = vmcs12->host_ia32_pat;
8252 }
4704d0be
NHE		 8253 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8254 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8255 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8256
21feb4eb
ACL		 8257 /* Set L1 segment info according to Intel SDM
8258 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8259 seg = (struct kvm_segment) {
8260 .base = 0,
8261 .limit = 0xFFFFFFFF,
8262 .selector = vmcs12->host_cs_selector,
8263 .type = 11,
8264 .present = 1,
8265 .s = 1,
8266 .g = 1
8267 };
8268 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8269 seg.l = 1;
8270 else
8271 seg.db = 1;
8272 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8273 seg = (struct kvm_segment) {
8274 .base = 0,
8275 .limit = 0xFFFFFFFF,
8276 .type = 3,
8277 .present = 1,
8278 .s = 1,
8279 .db = 1,
8280 .g = 1
8281 };
8282 seg.selector = vmcs12->host_ds_selector;
8283 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8284 seg.selector = vmcs12->host_es_selector;
8285 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8286 seg.selector = vmcs12->host_ss_selector;
8287 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8288 seg.selector = vmcs12->host_fs_selector;
8289 seg.base = vmcs12->host_fs_base;
8290 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8291 seg.selector = vmcs12->host_gs_selector;
8292 seg.base = vmcs12->host_gs_base;
8293 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8294 seg = (struct kvm_segment) {
205befd9 8295 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8296 .limit = 0x67,
8297 .selector = vmcs12->host_tr_selector,
8298 .type = 11,
8299 .present = 1
8300 };
8301 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8302
503cd0c5
JK		 8303 kvm_set_dr(vcpu, 7, 0x400);
8304 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8305}
8306
8307/*
8308 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8309 * and modify vmcs12 to make it see what it would expect to see there if
8310 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8311 */
8312static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8313{
8314 struct vcpu_vmx *vmx = to_vmx(vcpu);
8315 int cpu;
8316 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8317
5f3d5799
JK		 8318 /* trying to cancel vmlaunch/vmresume is a bug */
8319 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8320
4704d0be
NHE		 8321 leave_guest_mode(vcpu);
8322 prepare_vmcs12(vcpu, vmcs12);
8323
8324 cpu = get_cpu();
8325 vmx->loaded_vmcs = &vmx->vmcs01;
8326 vmx_vcpu_put(vcpu);
8327 vmx_vcpu_load(vcpu, cpu);
8328 vcpu->cpu = cpu;
8329 put_cpu();
8330
36c3cc42
JK		 8331 vmx_segment_cache_clear(vmx);
8332
4704d0be
NHE		 8333 /* if no vmcs02 cache requested, remove the one we used */
8334 if (VMCS02_POOL_SIZE == 0)
8335 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8336
8337 load_vmcs12_host_state(vcpu, vmcs12);
8338
27fc51b2 8339 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8340 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8341
8342 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8343 vmx->host_rsp = 0;
8344
8345 /* Unpin physical memory we referred to in vmcs02 */
8346 if (vmx->nested.apic_access_page) {
8347 nested_release_page(vmx->nested.apic_access_page);
8348 vmx->nested.apic_access_page = 0;
8349 }
8350
8351 /*
8352 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8353 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8354 * success or failure flag accordingly.
8355 */
8356 if (unlikely(vmx->fail)) {
8357 vmx->fail = 0;
8358 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8359 } else
8360 nested_vmx_succeed(vcpu);
012f83cb
AG		 8361 if (enable_shadow_vmcs)
8362 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8363}
8364
7c177938
NHE		 8365/*
8366 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8367 * 23.7 "VM-entry failures during or after loading guest state" (this also
8368 * lists the acceptable exit-reason and exit-qualification parameters).
8369 * It should only be called before L2 actually succeeded to run, and when
8370 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8371 */
8372static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8373 struct vmcs12 *vmcs12,
8374 u32 reason, unsigned long qualification)
8375{
8376 load_vmcs12_host_state(vcpu, vmcs12);
8377 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8378 vmcs12->exit_qualification = qualification;
8379 nested_vmx_succeed(vcpu);
012f83cb
AG		 8380 if (enable_shadow_vmcs)
8381 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8382}
8383
8a76d7f2
JR		 8384static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8385 struct x86_instruction_info *info,
8386 enum x86_intercept_stage stage)
8387{
8388 return X86EMUL_CONTINUE;
8389}
8390
cbdd1bea 8391static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8392 .cpu_has_kvm_support = cpu_has_kvm_support,
8393 .disabled_by_bios = vmx_disabled_by_bios,
8394 .hardware_setup = hardware_setup,
8395 .hardware_unsetup = hardware_unsetup,
002c7f7c 8396 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8397 .hardware_enable = hardware_enable,
8398 .hardware_disable = hardware_disable,
04547156 8399 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8400
8401 .vcpu_create = vmx_create_vcpu,
8402 .vcpu_free = vmx_free_vcpu,
04d2cc77 8403 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8404
04d2cc77 8405 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8406 .vcpu_load = vmx_vcpu_load,
8407 .vcpu_put = vmx_vcpu_put,
8408
c8639010 8409 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8410 .get_msr = vmx_get_msr,
8411 .set_msr = vmx_set_msr,
8412 .get_segment_base = vmx_get_segment_base,
8413 .get_segment = vmx_get_segment,
8414 .set_segment = vmx_set_segment,
2e4d2653 8415 .get_cpl = vmx_get_cpl,
6aa8b732 8416 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8417 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8418 .decache_cr3 = vmx_decache_cr3,
25c4c276 8419 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8420 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8421 .set_cr3 = vmx_set_cr3,
8422 .set_cr4 = vmx_set_cr4,
6aa8b732 8423 .set_efer = vmx_set_efer,
6aa8b732
AK		 8424 .get_idt = vmx_get_idt,
8425 .set_idt = vmx_set_idt,
8426 .get_gdt = vmx_get_gdt,
8427 .set_gdt = vmx_set_gdt,
020df079 8428 .set_dr7 = vmx_set_dr7,
5fdbf976 8429 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8430 .get_rflags = vmx_get_rflags,
8431 .set_rflags = vmx_set_rflags,
ebcbab4c 8432 .fpu_activate = vmx_fpu_activate,
02daab21 8433 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8434
8435 .tlb_flush = vmx_flush_tlb,
6aa8b732 8436
6aa8b732 8437 .run = vmx_vcpu_run,
6062d012 8438 .handle_exit = vmx_handle_exit,
6aa8b732 8439 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8440 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8441 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8442 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8443 .set_irq = vmx_inject_irq,
95ba8273 8444 .set_nmi = vmx_inject_nmi,
298101da 8445 .queue_exception = vmx_queue_exception,
b463a6f7 8446 .cancel_injection = vmx_cancel_injection,
78646121 8447 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8448 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8449 .get_nmi_mask = vmx_get_nmi_mask,
8450 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8451 .enable_nmi_window = enable_nmi_window,
8452 .enable_irq_window = enable_irq_window,
8453 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8454 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8455 .vm_has_apicv = vmx_vm_has_apicv,
8456 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8457 .hwapic_irr_update = vmx_hwapic_irr_update,
8458 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8459 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8460 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8461
cbc94022 8462 .set_tss_addr = vmx_set_tss_addr,
67253af5 8463 .get_tdp_level = get_ept_level,
4b12f0de 8464 .get_mt_mask = vmx_get_mt_mask,
229456fc 8465
586f9607 8466 .get_exit_info = vmx_get_exit_info,
586f9607 8467
17cc3935 8468 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8469
8470 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8471
8472 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8473 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8474
8475 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8476
8477 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8478
4051b188 8479 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8480 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8481 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8482 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8483 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8484 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8485
8486 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8487
8488 .check_intercept = vmx_check_intercept,
a547c6db 8489 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8490};
8491
8492static int __init vmx_init(void)
8493{
8d14695f 8494 int r, i, msr;
26bb0981
AK		 8495
8496 rdmsrl_safe(MSR_EFER, &host_efer);
8497
8498 for (i = 0; i < NR_VMX_MSR; ++i)
8499 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8500
3e7c73e9 8501 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8502 if (!vmx_io_bitmap_a)
8503 return -ENOMEM;
8504
2106a548
GC		 8505 r = -ENOMEM;
8506
3e7c73e9 8507 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8508 if (!vmx_io_bitmap_b)
fdef3ad1 8509 goto out;
fdef3ad1 8510
5897297b 8511 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8512 if (!vmx_msr_bitmap_legacy)
25c5f225 8513 goto out1;
2106a548 8514
8d14695f
YZ		 8515 vmx_msr_bitmap_legacy_x2apic =
8516 (unsigned long *)__get_free_page(GFP_KERNEL);
8517 if (!vmx_msr_bitmap_legacy_x2apic)
8518 goto out2;
25c5f225 8519
5897297b 8520 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8521 if (!vmx_msr_bitmap_longmode)
8d14695f 8522 goto out3;
2106a548 8523
8d14695f
YZ		 8524 vmx_msr_bitmap_longmode_x2apic =
8525 (unsigned long *)__get_free_page(GFP_KERNEL);
8526 if (!vmx_msr_bitmap_longmode_x2apic)
8527 goto out4;
4607c2d7
AG		 8528 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8529 if (!vmx_vmread_bitmap)
8530 goto out5;
8531
8532 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8533 if (!vmx_vmwrite_bitmap)
8534 goto out6;
8535
8536 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8537 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8538 /* shadowed read/write fields */
8539 for (i = 0; i < max_shadow_read_write_fields; i++) {
8540 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8541 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8542 }
8543 /* shadowed read only fields */
8544 for (i = 0; i < max_shadow_read_only_fields; i++)
8545 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8546
fdef3ad1
HQ		 8547 /*
8548 * Allow direct access to the PC debug port (it is often used for I/O
8549 * delays, but the vmexits simply slow things down).
8550 */
3e7c73e9
AK		 8551 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8552 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8553
3e7c73e9 8554 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8555
5897297b
AK		 8556 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8557 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8558
2384d2b3
SY		 8559 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8560
0ee75bea
AK		 8561 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8562 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8563 if (r)
4607c2d7 8564 goto out7;
25c5f225 8565
8f536b76
ZY		 8566#ifdef CONFIG_KEXEC
8567 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8568 crash_vmclear_local_loaded_vmcss);
8569#endif
8570
5897297b
AK		 8571 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8572 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8573 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8574 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8575 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8576 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8577 memcpy(vmx_msr_bitmap_legacy_x2apic,
8578 vmx_msr_bitmap_legacy, PAGE_SIZE);
8579 memcpy(vmx_msr_bitmap_longmode_x2apic,
8580 vmx_msr_bitmap_longmode, PAGE_SIZE);
8581
01e439be 8582 if (enable_apicv) {
8d14695f
YZ		 8583 for (msr = 0x800; msr <= 0x8ff; msr++)
8584 vmx_disable_intercept_msr_read_x2apic(msr);
8585
8586 /* According SDM, in x2apic mode, the whole id reg is used.
8587 * But in KVM, it only use the highest eight bits. Need to
8588 * intercept it */
8589 vmx_enable_intercept_msr_read_x2apic(0x802);
8590 /* TMCCT */
8591 vmx_enable_intercept_msr_read_x2apic(0x839);
8592 /* TPR */
8593 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8594 /* EOI */
8595 vmx_disable_intercept_msr_write_x2apic(0x80b);
8596 /* SELF-IPI */
8597 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8598 }
fdef3ad1 8599
089d034e 8600 if (enable_ept) {
3f6d8c8a
XH		 8601 kvm_mmu_set_mask_ptes(0ull,
8602 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8603 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8604 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8605 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8606 kvm_enable_tdp();
8607 } else
8608 kvm_disable_tdp();
1439442c 8609
fdef3ad1
HQ		 8610 return 0;
8611
4607c2d7
AG		 8612out7:
8613 free_page((unsigned long)vmx_vmwrite_bitmap);
8614out6:
8615 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8616out5:
8617 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8618out4:
5897297b 8619 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8620out3:
8621 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8622out2:
5897297b 8623 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8624out1:
3e7c73e9 8625 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8626out:
3e7c73e9 8627 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8628 return r;
6aa8b732
AK		 8629}
8630
8631static void __exit vmx_exit(void)
8632{
8d14695f
YZ		 8633 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8634 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8635 free_page((unsigned long)vmx_msr_bitmap_legacy);
8636 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8637 free_page((unsigned long)vmx_io_bitmap_b);
8638 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8639 free_page((unsigned long)vmx_vmwrite_bitmap);
8640 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8641
8f536b76
ZY		 8642#ifdef CONFIG_KEXEC
8643 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8644 synchronize_rcu();
8645#endif
8646
cb498ea2 8647 kvm_exit();
6aa8b732
AK		 8648}
8649
8650module_init(vmx_init)
8651module_exit(vmx_exit)
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