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Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
8248c36a 243 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 259 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 261 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 263};
264
303752a9
MT		 265static const char *cpuid_apm_edx_feature_name[] = {
266 NULL, NULL, NULL, NULL,
267 NULL, NULL, NULL, NULL,
268 "invtsc", NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274};
275
0bb0b2d2
PB		 276static const char *cpuid_xsave_feature_name[] = {
277 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
278 NULL, NULL, NULL, NULL,
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285};
286
621626ce
EH		 287#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
288#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
289 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
290#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
291 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
292 CPUID_PSE36 | CPUID_FXSR)
293#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
294#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
295 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
296 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
297 CPUID_PAE | CPUID_SEP | CPUID_APIC)
298
299#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
300 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
301 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
302 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
303 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
304 /* partly implemented:
305 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
306 /* missing:
307 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
308#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
309 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
310 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
311 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
312 /* missing:
313 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
314 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
315 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
316 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
317 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
318 CPUID_EXT_RDRAND */
319
320#ifdef TARGET_X86_64
321#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
322#else
323#define TCG_EXT2_X86_64_FEATURES 0
324#endif
325
326#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
327 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
328 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
329 TCG_EXT2_X86_64_FEATURES)
330#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
331 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
332#define TCG_EXT4_FEATURES 0
333#define TCG_SVM_FEATURES 0
334#define TCG_KVM_FEATURES 0
335#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
336 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
337 /* missing:
338 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
339 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
340 CPUID_7_0_EBX_RDSEED */
303752a9 341#define TCG_APM_FEATURES 0
621626ce
EH		 342
343
5ef57876
EH		 344typedef struct FeatureWordInfo {
345 const char **feat_names;
04d104b6
EH		 346 uint32_t cpuid_eax; /* Input EAX for CPUID */
347 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
348 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
349 int cpuid_reg; /* output register (R_* constant) */
37ce3522 350 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 351 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 352} FeatureWordInfo;
353
354static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 355 [FEAT_1_EDX] = {
356 .feat_names = feature_name,
357 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 358 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 359 },
360 [FEAT_1_ECX] = {
361 .feat_names = ext_feature_name,
362 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 363 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 364 },
365 [FEAT_8000_0001_EDX] = {
366 .feat_names = ext2_feature_name,
367 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 368 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 369 },
370 [FEAT_8000_0001_ECX] = {
371 .feat_names = ext3_feature_name,
372 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 373 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 374 },
89e49c8b
EH		 375 [FEAT_C000_0001_EDX] = {
376 .feat_names = ext4_feature_name,
377 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 378 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 379 },
bffd67b0
EH		 380 [FEAT_KVM] = {
381 .feat_names = kvm_feature_name,
382 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 383 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 384 },
385 [FEAT_SVM] = {
386 .feat_names = svm_feature_name,
387 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 388 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 389 },
390 [FEAT_7_0_EBX] = {
391 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 392 .cpuid_eax = 7,
393 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
394 .cpuid_reg = R_EBX,
37ce3522 395 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 396 },
303752a9
MT		 397 [FEAT_8000_0007_EDX] = {
398 .feat_names = cpuid_apm_edx_feature_name,
399 .cpuid_eax = 0x80000007,
400 .cpuid_reg = R_EDX,
401 .tcg_features = TCG_APM_FEATURES,
402 .unmigratable_flags = CPUID_APM_INVTSC,
403 },
0bb0b2d2
PB		 404 [FEAT_XSAVE] = {
405 .feat_names = cpuid_xsave_feature_name,
406 .cpuid_eax = 0xd,
407 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
408 .cpuid_reg = R_EAX,
409 .tcg_features = 0,
0bb0b2d2 410 },
5ef57876
EH		 411};
412
8e8aba50
EH		 413typedef struct X86RegisterInfo32 {
414 /* Name of register */
415 const char *name;
416 /* QAPI enum value register */
417 X86CPURegister32 qapi_enum;
418} X86RegisterInfo32;
419
420#define REGISTER(reg) \
5d371f41 421 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 422static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 423 REGISTER(EAX),
424 REGISTER(ECX),
425 REGISTER(EDX),
426 REGISTER(EBX),
427 REGISTER(ESP),
428 REGISTER(EBP),
429 REGISTER(ESI),
430 REGISTER(EDI),
431};
432#undef REGISTER
433
2560f19f
PB		 434typedef struct ExtSaveArea {
435 uint32_t feature, bits;
436 uint32_t offset, size;
437} ExtSaveArea;
438
439static const ExtSaveArea ext_save_areas[] = {
440 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 441 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 442 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
443 .offset = 0x3c0, .size = 0x40 },
444 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 445 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 446 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
447 .offset = 0x440, .size = 0x40 },
448 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
449 .offset = 0x480, .size = 0x200 },
450 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
451 .offset = 0x680, .size = 0x400 },
2560f19f 452};
8e8aba50 453
8b4beddc
EH		 454const char *get_register_name_32(unsigned int reg)
455{
31ccdde2 456 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 457 return NULL;
458 }
8e8aba50 459 return x86_reg_info_32[reg].name;
8b4beddc
EH		 460}
461
5fcca9ff
EH		 462/* KVM-specific features that are automatically added to all CPU models
463 * when KVM is enabled.
464 */
465static uint32_t kvm_default_features[FEATURE_WORDS] = {
466 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 467 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 468 (1 << KVM_FEATURE_CLOCKSOURCE2) |
469 (1 << KVM_FEATURE_ASYNC_PF) |
470 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 471 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 472 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 473 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 474};
dc59944b 475
136a7e9a
EH		 476/* Features that are not added by default to any CPU model when KVM is enabled.
477 */
478static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 479 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a 480 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
75d373ef 481 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
136a7e9a
EH		 482};
483
1cadaa94 484void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 485{
8fb4f821 486 kvm_default_features[w] &= ~features;
dc59944b
MT		 487}
488
75d373ef
EH		 489void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
490{
491 kvm_default_unset_features[w] &= ~features;
492}
493
84f1b92f
EH		 494/*
495 * Returns the set of feature flags that are supported and migratable by
496 * QEMU, for a given FeatureWord.
497 */
498static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
499{
500 FeatureWordInfo *wi = &feature_word_info[w];
501 uint32_t r = 0;
502 int i;
503
504 for (i = 0; i < 32; i++) {
505 uint32_t f = 1U << i;
506 /* If the feature name is unknown, it is not supported by QEMU yet */
507 if (!wi->feat_names[i]) {
508 continue;
509 }
510 /* Skip features known to QEMU, but explicitly marked as unmigratable */
511 if (wi->unmigratable_flags & f) {
512 continue;
513 }
514 r |= f;
515 }
516 return r;
517}
518
bb44e0d1
JK		 519void host_cpuid(uint32_t function, uint32_t count,
520 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 521{
a1fd24af
AL		 522 uint32_t vec[4];
523
524#ifdef __x86_64__
525 asm volatile("cpuid"
526 : "=a"(vec[0]), "=b"(vec[1]),
527 "=c"(vec[2]), "=d"(vec[3])
528 : "0"(function), "c"(count) : "cc");
c1f41226 529#elif defined(__i386__)
a1fd24af
AL		 530 asm volatile("pusha \n\t"
531 "cpuid \n\t"
532 "mov %%eax, 0(%2) \n\t"
533 "mov %%ebx, 4(%2) \n\t"
534 "mov %%ecx, 8(%2) \n\t"
535 "mov %%edx, 12(%2) \n\t"
536 "popa"
537 : : "a"(function), "c"(count), "S"(vec)
538 : "memory", "cc");
c1f41226
EH		 539#else
540 abort();
a1fd24af
AL		 541#endif
542
bdde476a 543 if (eax)
a1fd24af 544 *eax = vec[0];
bdde476a 545 if (ebx)
a1fd24af 546 *ebx = vec[1];
bdde476a 547 if (ecx)
a1fd24af 548 *ecx = vec[2];
bdde476a 549 if (edx)
a1fd24af 550 *edx = vec[3];
bdde476a 551}
c6dc6f63
AP		 552
553#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
554
555/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
556 * a substring. ex if !NULL points to the first char after a substring,
557 * otherwise the string is assumed to sized by a terminating nul.
558 * Return lexical ordering of *s1:*s2.
559 */
8f9d989c
CF		 560static int sstrcmp(const char *s1, const char *e1,
561 const char *s2, const char *e2)
c6dc6f63
AP		 562{
563 for (;;) {
564 if (!*s1 || !*s2 || *s1 != *s2)
565 return (*s1 - *s2);
566 ++s1, ++s2;
567 if (s1 == e1 && s2 == e2)
568 return (0);
569 else if (s1 == e1)
570 return (*s2);
571 else if (s2 == e2)
572 return (*s1);
573 }
574}
575
576/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
577 * '|' delimited (possibly empty) strings in which case search for a match
578 * within the alternatives proceeds left to right. Return 0 for success,
579 * non-zero otherwise.
580 */
581static int altcmp(const char *s, const char *e, const char *altstr)
582{
583 const char *p, *q;
584
585 for (q = p = altstr; ; ) {
586 while (*p && *p != '|')
587 ++p;
588 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
589 return (0);
590 if (!*p)
591 return (1);
592 else
593 q = ++p;
594 }
595}
596
597/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 598 * *pval and return true, otherwise return false
c6dc6f63 599 */
e41e0fc6
JK		 600static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
601 const char **featureset)
c6dc6f63
AP		 602{
603 uint32_t mask;
604 const char **ppc;
e41e0fc6 605 bool found = false;
c6dc6f63 606
e41e0fc6 607 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 608 if (*ppc && !altcmp(s, e, *ppc)) {
609 *pval |= mask;
e41e0fc6 610 found = true;
c6dc6f63 611 }
e41e0fc6
JK		 612 }
613 return found;
c6dc6f63
AP		 614}
615
5ef57876 616static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 617 FeatureWordArray words,
618 Error **errp)
c6dc6f63 619{
5ef57876
EH		 620 FeatureWord w;
621 for (w = 0; w < FEATURE_WORDS; w++) {
622 FeatureWordInfo *wi = &feature_word_info[w];
623 if (wi->feat_names &&
624 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
625 break;
626 }
627 }
628 if (w == FEATURE_WORDS) {
c00c94ab 629 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 630 }
c6dc6f63
AP		 631}
632
d940ee9b
EH		 633/* CPU class name definitions: */
634
635#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
636#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
637
638/* Return type name for a given CPU model name
639 * Caller is responsible for freeing the returned string.
640 */
641static char *x86_cpu_type_name(const char *model_name)
642{
643 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
644}
645
500050d1
AF		 646static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
647{
d940ee9b
EH		 648 ObjectClass *oc;
649 char *typename;
650
500050d1
AF		 651 if (cpu_model == NULL) {
652 return NULL;
653 }
654
d940ee9b
EH		 655 typename = x86_cpu_type_name(cpu_model);
656 oc = object_class_by_name(typename);
657 g_free(typename);
658 return oc;
500050d1
AF		 659}
660
d940ee9b 661struct X86CPUDefinition {
c6dc6f63
AP		 662 const char *name;
663 uint32_t level;
90e4b0c3
EH		 664 uint32_t xlevel;
665 uint32_t xlevel2;
99b88a17
IM		 666 /* vendor is zero-terminated, 12 character ASCII string */
667 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 668 int family;
669 int model;
670 int stepping;
0514ef2f 671 FeatureWordArray features;
c6dc6f63 672 char model_id[48];
787aaf57 673 bool cache_info_passthrough;
d940ee9b 674};
c6dc6f63 675
9576de75 676static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 677 {
678 .name = "qemu64",
679 .level = 4,
99b88a17 680 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 681 .family = 6,
f8e6a11a 682 .model = 6,
c6dc6f63 683 .stepping = 3,
0514ef2f 684 .features[FEAT_1_EDX] =
27861ecc 685 PPRO_FEATURES |
c6dc6f63 686 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 687 CPUID_PSE36,
0514ef2f 688 .features[FEAT_1_ECX] =
27861ecc 689 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 690 .features[FEAT_8000_0001_EDX] =
27861ecc 691 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 692 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 693 .features[FEAT_8000_0001_ECX] =
27861ecc 694 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 695 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
696 .xlevel = 0x8000000A,
c6dc6f63
AP		 697 },
698 {
699 .name = "phenom",
700 .level = 5,
99b88a17 701 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 702 .family = 16,
703 .model = 2,
704 .stepping = 3,
b9fc20bc 705 /* Missing: CPUID_HT */
0514ef2f 706 .features[FEAT_1_EDX] =
27861ecc 707 PPRO_FEATURES |
c6dc6f63 708 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 709 CPUID_PSE36 | CPUID_VME,
0514ef2f 710 .features[FEAT_1_ECX] =
27861ecc 711 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 712 CPUID_EXT_POPCNT,
0514ef2f 713 .features[FEAT_8000_0001_EDX] =
27861ecc 714 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 715 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
716 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 717 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 718 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
719 CPUID_EXT3_CR8LEG,
720 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
721 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 722 .features[FEAT_8000_0001_ECX] =
27861ecc 723 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 724 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 725 /* Missing: CPUID_SVM_LBRV */
0514ef2f 726 .features[FEAT_SVM] =
b9fc20bc 727 CPUID_SVM_NPT,
c6dc6f63
AP		 728 .xlevel = 0x8000001A,
729 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
730 },
731 {
732 .name = "core2duo",
733 .level = 10,
99b88a17 734 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 735 .family = 6,
736 .model = 15,
737 .stepping = 11,
b9fc20bc 738 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 739 .features[FEAT_1_EDX] =
27861ecc 740 PPRO_FEATURES |
c6dc6f63 741 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 742 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
743 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 744 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 745 .features[FEAT_1_ECX] =
27861ecc 746 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 747 CPUID_EXT_CX16,
0514ef2f 748 .features[FEAT_8000_0001_EDX] =
27861ecc 749 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 750 .features[FEAT_8000_0001_ECX] =
27861ecc 751 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 752 .xlevel = 0x80000008,
753 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
754 },
755 {
756 .name = "kvm64",
757 .level = 5,
99b88a17 758 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 759 .family = 15,
760 .model = 6,
761 .stepping = 1,
b3a4f0b1 762 /* Missing: CPUID_HT */
0514ef2f 763 .features[FEAT_1_EDX] =
b3a4f0b1 764 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
766 CPUID_PSE36,
767 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 768 .features[FEAT_1_ECX] =
27861ecc 769 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 770 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 771 .features[FEAT_8000_0001_EDX] =
27861ecc 772 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 773 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
774 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
775 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
776 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
777 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 778 .features[FEAT_8000_0001_ECX] =
27861ecc 779 0,
c6dc6f63
AP		 780 .xlevel = 0x80000008,
781 .model_id = "Common KVM processor"
782 },
c6dc6f63
AP		 783 {
784 .name = "qemu32",
785 .level = 4,
99b88a17 786 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 787 .family = 6,
f8e6a11a 788 .model = 6,
c6dc6f63 789 .stepping = 3,
0514ef2f 790 .features[FEAT_1_EDX] =
27861ecc 791 PPRO_FEATURES,
0514ef2f 792 .features[FEAT_1_ECX] =
27861ecc 793 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 794 .xlevel = 0x80000004,
c6dc6f63 795 },
eafaf1e5
AP		 796 {
797 .name = "kvm32",
798 .level = 5,
99b88a17 799 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 800 .family = 15,
801 .model = 6,
802 .stepping = 1,
0514ef2f 803 .features[FEAT_1_EDX] =
b3a4f0b1 804 PPRO_FEATURES | CPUID_VME |
eafaf1e5 805 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 806 .features[FEAT_1_ECX] =
27861ecc 807 CPUID_EXT_SSE3,
0514ef2f 808 .features[FEAT_8000_0001_EDX] =
27861ecc 809 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 810 .features[FEAT_8000_0001_ECX] =
27861ecc 811 0,
eafaf1e5
AP		 812 .xlevel = 0x80000008,
813 .model_id = "Common 32-bit KVM processor"
814 },
c6dc6f63
AP		 815 {
816 .name = "coreduo",
817 .level = 10,
99b88a17 818 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 819 .family = 6,
820 .model = 14,
821 .stepping = 8,
b9fc20bc 822 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 823 .features[FEAT_1_EDX] =
27861ecc 824 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 825 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
826 CPUID_SS,
827 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 828 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 829 .features[FEAT_1_ECX] =
e93abc14 830 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 831 .features[FEAT_8000_0001_EDX] =
27861ecc 832 CPUID_EXT2_NX,
c6dc6f63
AP		 833 .xlevel = 0x80000008,
834 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
835 },
836 {
837 .name = "486",
58012d66 838 .level = 1,
99b88a17 839 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 840 .family = 4,
b2a856d9 841 .model = 8,
c6dc6f63 842 .stepping = 0,
0514ef2f 843 .features[FEAT_1_EDX] =
27861ecc 844 I486_FEATURES,
c6dc6f63
AP		 845 .xlevel = 0,
846 },
847 {
848 .name = "pentium",
849 .level = 1,
99b88a17 850 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 851 .family = 5,
852 .model = 4,
853 .stepping = 3,
0514ef2f 854 .features[FEAT_1_EDX] =
27861ecc 855 PENTIUM_FEATURES,
c6dc6f63
AP		 856 .xlevel = 0,
857 },
858 {
859 .name = "pentium2",
860 .level = 2,
99b88a17 861 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 862 .family = 6,
863 .model = 5,
864 .stepping = 2,
0514ef2f 865 .features[FEAT_1_EDX] =
27861ecc 866 PENTIUM2_FEATURES,
c6dc6f63
AP		 867 .xlevel = 0,
868 },
869 {
870 .name = "pentium3",
871 .level = 2,
99b88a17 872 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 873 .family = 6,
874 .model = 7,
875 .stepping = 3,
0514ef2f 876 .features[FEAT_1_EDX] =
27861ecc 877 PENTIUM3_FEATURES,
c6dc6f63
AP		 878 .xlevel = 0,
879 },
880 {
881 .name = "athlon",
882 .level = 2,
99b88a17 883 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 884 .family = 6,
885 .model = 2,
886 .stepping = 3,
0514ef2f 887 .features[FEAT_1_EDX] =
27861ecc 888 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 889 CPUID_MCA,
0514ef2f 890 .features[FEAT_8000_0001_EDX] =
27861ecc 891 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 892 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 893 .xlevel = 0x80000008,
c6dc6f63
AP		 894 },
895 {
896 .name = "n270",
897 /* original is on level 10 */
898 .level = 5,
99b88a17 899 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 900 .family = 6,
901 .model = 28,
902 .stepping = 2,
b9fc20bc 903 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 904 .features[FEAT_1_EDX] =
27861ecc 905 PPRO_FEATURES |
b9fc20bc
EH		 906 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
907 CPUID_ACPI | CPUID_SS,
c6dc6f63 908 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 909 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
910 * CPUID_EXT_XTPR */
0514ef2f 911 .features[FEAT_1_ECX] =
27861ecc 912 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 913 CPUID_EXT_MOVBE,
0514ef2f 914 .features[FEAT_8000_0001_EDX] =
27861ecc 915 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 916 CPUID_EXT2_NX,
0514ef2f 917 .features[FEAT_8000_0001_ECX] =
27861ecc 918 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 919 .xlevel = 0x8000000A,
920 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
921 },
3eca4642
EH		 922 {
923 .name = "Conroe",
6b11322e 924 .level = 4,
99b88a17 925 .vendor = CPUID_VENDOR_INTEL,
3eca4642 926 .family = 6,
ffce9ebb 927 .model = 15,
3eca4642 928 .stepping = 3,
0514ef2f 929 .features[FEAT_1_EDX] =
b3a4f0b1 930 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 931 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
932 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
933 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
934 CPUID_DE | CPUID_FP87,
0514ef2f 935 .features[FEAT_1_ECX] =
27861ecc 936 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 937 .features[FEAT_8000_0001_EDX] =
27861ecc 938 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 939 .features[FEAT_8000_0001_ECX] =
27861ecc 940 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 941 .xlevel = 0x8000000A,
942 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
943 },
944 {
945 .name = "Penryn",
6b11322e 946 .level = 4,
99b88a17 947 .vendor = CPUID_VENDOR_INTEL,
3eca4642 948 .family = 6,
ffce9ebb 949 .model = 23,
3eca4642 950 .stepping = 3,
0514ef2f 951 .features[FEAT_1_EDX] =
b3a4f0b1 952 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 953 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
954 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
955 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
956 CPUID_DE | CPUID_FP87,
0514ef2f 957 .features[FEAT_1_ECX] =
27861ecc 958 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 959 CPUID_EXT_SSE3,
0514ef2f 960 .features[FEAT_8000_0001_EDX] =
27861ecc 961 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 962 .features[FEAT_8000_0001_ECX] =
27861ecc 963 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 964 .xlevel = 0x8000000A,
965 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
966 },
967 {
968 .name = "Nehalem",
6b11322e 969 .level = 4,
99b88a17 970 .vendor = CPUID_VENDOR_INTEL,
3eca4642 971 .family = 6,
ffce9ebb 972 .model = 26,
3eca4642 973 .stepping = 3,
0514ef2f 974 .features[FEAT_1_EDX] =
b3a4f0b1 975 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 976 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
977 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
978 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
979 CPUID_DE | CPUID_FP87,
0514ef2f 980 .features[FEAT_1_ECX] =
27861ecc 981 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 982 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 983 .features[FEAT_8000_0001_EDX] =
27861ecc 984 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 985 .features[FEAT_8000_0001_ECX] =
27861ecc 986 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 987 .xlevel = 0x8000000A,
988 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
989 },
990 {
991 .name = "Westmere",
992 .level = 11,
99b88a17 993 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 994 .family = 6,
995 .model = 44,
996 .stepping = 1,
0514ef2f 997 .features[FEAT_1_EDX] =
b3a4f0b1 998 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 999 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1000 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1001 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1002 CPUID_DE | CPUID_FP87,
0514ef2f 1003 .features[FEAT_1_ECX] =
27861ecc 1004 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1005 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1006 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1007 .features[FEAT_8000_0001_EDX] =
27861ecc 1008 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1009 .features[FEAT_8000_0001_ECX] =
27861ecc 1010 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1011 .xlevel = 0x8000000A,
1012 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1013 },
1014 {
1015 .name = "SandyBridge",
1016 .level = 0xd,
99b88a17 1017 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1018 .family = 6,
1019 .model = 42,
1020 .stepping = 1,
0514ef2f 1021 .features[FEAT_1_EDX] =
b3a4f0b1 1022 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1023 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1024 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1025 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1026 CPUID_DE | CPUID_FP87,
0514ef2f 1027 .features[FEAT_1_ECX] =
27861ecc 1028 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1029 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1030 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1031 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1032 CPUID_EXT_SSE3,
0514ef2f 1033 .features[FEAT_8000_0001_EDX] =
27861ecc 1034 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1035 CPUID_EXT2_SYSCALL,
0514ef2f 1036 .features[FEAT_8000_0001_ECX] =
27861ecc 1037 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1038 .features[FEAT_XSAVE] =
1039 CPUID_XSAVE_XSAVEOPT,
3eca4642
EH		 1040 .xlevel = 0x8000000A,
1041 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1042 },
2f9ac42a
PB		 1043 {
1044 .name = "IvyBridge",
1045 .level = 0xd,
1046 .vendor = CPUID_VENDOR_INTEL,
1047 .family = 6,
1048 .model = 58,
1049 .stepping = 9,
1050 .features[FEAT_1_EDX] =
1051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1055 CPUID_DE | CPUID_FP87,
1056 .features[FEAT_1_ECX] =
1057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1058 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1059 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1060 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1061 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1062 .features[FEAT_7_0_EBX] =
1063 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1064 CPUID_7_0_EBX_ERMS,
1065 .features[FEAT_8000_0001_EDX] =
1066 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1067 CPUID_EXT2_SYSCALL,
1068 .features[FEAT_8000_0001_ECX] =
1069 CPUID_EXT3_LAHF_LM,
1070 .features[FEAT_XSAVE] =
1071 CPUID_XSAVE_XSAVEOPT,
1072 .xlevel = 0x8000000A,
1073 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1074 },
37507094
EH		 1075 {
1076 .name = "Haswell",
1077 .level = 0xd,
99b88a17 1078 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1079 .family = 6,
1080 .model = 60,
1081 .stepping = 1,
0514ef2f 1082 .features[FEAT_1_EDX] =
b3a4f0b1 1083 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1084 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1085 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1086 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1087 CPUID_DE | CPUID_FP87,
0514ef2f 1088 .features[FEAT_1_ECX] =
27861ecc 1089 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1090 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1091 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1092 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1093 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1094 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1095 .features[FEAT_8000_0001_EDX] =
27861ecc 1096 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1097 CPUID_EXT2_SYSCALL,
0514ef2f 1098 .features[FEAT_8000_0001_ECX] =
27861ecc 1099 CPUID_EXT3_LAHF_LM,
0514ef2f 1100 .features[FEAT_7_0_EBX] =
27861ecc 1101 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
13704e4c
EH		 1102 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1103 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
0bb0b2d2
PB		 1104 .features[FEAT_XSAVE] =
1105 CPUID_XSAVE_XSAVEOPT,
37507094
EH		 1106 .xlevel = 0x8000000A,
1107 .model_id = "Intel Core Processor (Haswell)",
1108 },
ece01354
EH		 1109 {
1110 .name = "Broadwell",
1111 .level = 0xd,
1112 .vendor = CPUID_VENDOR_INTEL,
1113 .family = 6,
1114 .model = 61,
1115 .stepping = 2,
1116 .features[FEAT_1_EDX] =
b3a4f0b1 1117 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1118 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1119 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1120 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1121 CPUID_DE | CPUID_FP87,
1122 .features[FEAT_1_ECX] =
1123 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1124 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1125 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1126 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1127 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1128 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1129 .features[FEAT_8000_0001_EDX] =
1130 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1131 CPUID_EXT2_SYSCALL,
1132 .features[FEAT_8000_0001_ECX] =
1133 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1134 .features[FEAT_7_0_EBX] =
1135 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
13704e4c 1136 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1137 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
13704e4c 1138 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1139 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1140 .features[FEAT_XSAVE] =
1141 CPUID_XSAVE_XSAVEOPT,
ece01354
EH		 1142 .xlevel = 0x8000000A,
1143 .model_id = "Intel Core Processor (Broadwell)",
1144 },
3eca4642
EH		 1145 {
1146 .name = "Opteron_G1",
1147 .level = 5,
99b88a17 1148 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1149 .family = 15,
1150 .model = 6,
1151 .stepping = 1,
0514ef2f 1152 .features[FEAT_1_EDX] =
b3a4f0b1 1153 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1154 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1155 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1156 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1157 CPUID_DE | CPUID_FP87,
0514ef2f 1158 .features[FEAT_1_ECX] =
27861ecc 1159 CPUID_EXT_SSE3,
0514ef2f 1160 .features[FEAT_8000_0001_EDX] =
27861ecc 1161 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1162 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1163 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1164 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1165 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1166 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1167 .xlevel = 0x80000008,
1168 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1169 },
1170 {
1171 .name = "Opteron_G2",
1172 .level = 5,
99b88a17 1173 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1174 .family = 15,
1175 .model = 6,
1176 .stepping = 1,
0514ef2f 1177 .features[FEAT_1_EDX] =
b3a4f0b1 1178 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1179 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1180 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1181 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1182 CPUID_DE | CPUID_FP87,
0514ef2f 1183 .features[FEAT_1_ECX] =
27861ecc 1184 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1185 .features[FEAT_8000_0001_EDX] =
27861ecc 1186 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1187 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1188 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1189 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1190 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1191 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1192 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1193 .features[FEAT_8000_0001_ECX] =
27861ecc 1194 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1195 .xlevel = 0x80000008,
1196 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1197 },
1198 {
1199 .name = "Opteron_G3",
1200 .level = 5,
99b88a17 1201 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1202 .family = 15,
1203 .model = 6,
1204 .stepping = 1,
0514ef2f 1205 .features[FEAT_1_EDX] =
b3a4f0b1 1206 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1207 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1208 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1209 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1210 CPUID_DE | CPUID_FP87,
0514ef2f 1211 .features[FEAT_1_ECX] =
27861ecc 1212 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1213 CPUID_EXT_SSE3,
0514ef2f 1214 .features[FEAT_8000_0001_EDX] =
27861ecc 1215 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1216 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1217 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1218 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1219 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1220 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1221 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1222 .features[FEAT_8000_0001_ECX] =
27861ecc 1223 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1224 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1225 .xlevel = 0x80000008,
1226 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1227 },
1228 {
1229 .name = "Opteron_G4",
1230 .level = 0xd,
99b88a17 1231 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1232 .family = 21,
1233 .model = 1,
1234 .stepping = 2,
0514ef2f 1235 .features[FEAT_1_EDX] =
b3a4f0b1 1236 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1237 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1238 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1239 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1240 CPUID_DE | CPUID_FP87,
0514ef2f 1241 .features[FEAT_1_ECX] =
27861ecc 1242 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1243 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1244 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1245 CPUID_EXT_SSE3,
0514ef2f 1246 .features[FEAT_8000_0001_EDX] =
27861ecc 1247 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1248 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1249 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1250 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1251 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1252 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1253 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1254 .features[FEAT_8000_0001_ECX] =
27861ecc 1255 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1256 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1257 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1258 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1259 /* no xsaveopt! */
3eca4642
EH		 1260 .xlevel = 0x8000001A,
1261 .model_id = "AMD Opteron 62xx class CPU",
1262 },
021941b9
AP		 1263 {
1264 .name = "Opteron_G5",
1265 .level = 0xd,
99b88a17 1266 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1267 .family = 21,
1268 .model = 2,
1269 .stepping = 0,
0514ef2f 1270 .features[FEAT_1_EDX] =
b3a4f0b1 1271 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1272 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1273 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1274 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1275 CPUID_DE | CPUID_FP87,
0514ef2f 1276 .features[FEAT_1_ECX] =
27861ecc 1277 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1278 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1279 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1280 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1281 .features[FEAT_8000_0001_EDX] =
27861ecc 1282 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1283 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1284 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1285 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1286 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1287 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1288 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1289 .features[FEAT_8000_0001_ECX] =
27861ecc 1290 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1291 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1292 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1293 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1294 /* no xsaveopt! */
021941b9
AP		 1295 .xlevel = 0x8000001A,
1296 .model_id = "AMD Opteron 63xx class CPU",
1297 },
c6dc6f63
AP		 1298};
1299
0668af54
EH		 1300/**
1301 * x86_cpu_compat_set_features:
1302 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1303 * @w: Identifies the feature word to be changed.
1304 * @feat_add: Feature bits to be added to feature word
1305 * @feat_remove: Feature bits to be removed from feature word
1306 *
1307 * Change CPU model feature bits for compatibility.
1308 *
1309 * This function may be used by machine-type compatibility functions
1310 * to enable or disable feature bits on specific CPU models.
1311 */
1312void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1313 uint32_t feat_add, uint32_t feat_remove)
1314{
9576de75 1315 X86CPUDefinition *def;
0668af54
EH		 1316 int i;
1317 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1318 def = &builtin_x86_defs[i];
1319 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1320 def->features[w] |= feat_add;
1321 def->features[w] &= ~feat_remove;
1322 }
1323 }
1324}
1325
4d1b279b
EH		 1326static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1327 bool migratable_only);
1328
d940ee9b
EH		 1329#ifdef CONFIG_KVM
1330
c6dc6f63
AP		 1331static int cpu_x86_fill_model_id(char *str)
1332{
1333 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1334 int i;
1335
1336 for (i = 0; i < 3; i++) {
1337 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1338 memcpy(str + i * 16 + 0, &eax, 4);
1339 memcpy(str + i * 16 + 4, &ebx, 4);
1340 memcpy(str + i * 16 + 8, &ecx, 4);
1341 memcpy(str + i * 16 + 12, &edx, 4);
1342 }
1343 return 0;
1344}
1345
d940ee9b
EH		 1346static X86CPUDefinition host_cpudef;
1347
84f1b92f 1348static Property host_x86_cpu_properties[] = {
120eee7d 1349 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1350 DEFINE_PROP_END_OF_LIST()
1351};
1352
d940ee9b 1353/* class_init for the "host" CPU model
6e746f30 1354 *
d940ee9b 1355 * This function may be called before KVM is initialized.
6e746f30 1356 */
d940ee9b 1357static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1358{
84f1b92f 1359 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1360 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1361 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1362
d940ee9b 1363 xcc->kvm_required = true;
6e746f30 1364
c6dc6f63 1365 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1366 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1367
1368 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1369 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1370 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1371 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1372
d940ee9b 1373 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1374
d940ee9b
EH		 1375 xcc->cpu_def = &host_cpudef;
1376 host_cpudef.cache_info_passthrough = true;
1377
1378 /* level, xlevel, xlevel2, and the feature words are initialized on
1379 * instance_init, because they require KVM to be initialized.
1380 */
84f1b92f
EH		 1381
1382 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1383}
1384
1385static void host_x86_cpu_initfn(Object *obj)
1386{
1387 X86CPU *cpu = X86_CPU(obj);
1388 CPUX86State *env = &cpu->env;
1389 KVMState *s = kvm_state;
d940ee9b
EH		 1390
1391 assert(kvm_enabled());
1392
4d1b279b
EH		 1393 /* We can't fill the features array here because we don't know yet if
1394 * "migratable" is true or false.
1395 */
1396 cpu->host_features = true;
1397
d940ee9b
EH		 1398 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1399 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1400 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1401
d940ee9b 1402 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1403}
1404
d940ee9b
EH		 1405static const TypeInfo host_x86_cpu_type_info = {
1406 .name = X86_CPU_TYPE_NAME("host"),
1407 .parent = TYPE_X86_CPU,
1408 .instance_init = host_x86_cpu_initfn,
1409 .class_init = host_x86_cpu_class_init,
1410};
1411
1412#endif
1413
8459e396 1414static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1415{
8459e396 1416 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1417 int i;
1418
857aee33 1419 for (i = 0; i < 32; ++i) {
c6dc6f63 1420 if (1 << i & mask) {
bffd67b0 1421 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1422 assert(reg);
fefb41bf 1423 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1424 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1425 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1426 f->cpuid_eax, reg,
1427 f->feat_names[i] ? "." : "",
1428 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1429 }
857aee33 1430 }
c6dc6f63
AP		 1431}
1432
95b8519d
AF		 1433static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1434 const char *name, Error **errp)
1435{
1436 X86CPU *cpu = X86_CPU(obj);
1437 CPUX86State *env = &cpu->env;
1438 int64_t value;
1439
1440 value = (env->cpuid_version >> 8) & 0xf;
1441 if (value == 0xf) {
1442 value += (env->cpuid_version >> 20) & 0xff;
1443 }
1444 visit_type_int(v, &value, name, errp);
1445}
1446
71ad61d3
AF		 1447static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1448 const char *name, Error **errp)
ed5e1ec3 1449{
71ad61d3
AF		 1450 X86CPU *cpu = X86_CPU(obj);
1451 CPUX86State *env = &cpu->env;
1452 const int64_t min = 0;
1453 const int64_t max = 0xff + 0xf;
65cd9064 1454 Error *local_err = NULL;
71ad61d3
AF		 1455 int64_t value;
1456
65cd9064
MA		 1457 visit_type_int(v, &value, name, &local_err);
1458 if (local_err) {
1459 error_propagate(errp, local_err);
71ad61d3
AF		 1460 return;
1461 }
1462 if (value < min || value > max) {
1463 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1464 name ? name : "null", value, min, max);
1465 return;
1466 }
1467
ed5e1ec3 1468 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1469 if (value > 0x0f) {
1470 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1471 } else {
71ad61d3 1472 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1473 }
1474}
1475
67e30c83
AF		 1476static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1477 const char *name, Error **errp)
1478{
1479 X86CPU *cpu = X86_CPU(obj);
1480 CPUX86State *env = &cpu->env;
1481 int64_t value;
1482
1483 value = (env->cpuid_version >> 4) & 0xf;
1484 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1485 visit_type_int(v, &value, name, errp);
1486}
1487
c5291a4f
AF		 1488static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1489 const char *name, Error **errp)
b0704cbd 1490{
c5291a4f
AF		 1491 X86CPU *cpu = X86_CPU(obj);
1492 CPUX86State *env = &cpu->env;
1493 const int64_t min = 0;
1494 const int64_t max = 0xff;
65cd9064 1495 Error *local_err = NULL;
c5291a4f
AF		 1496 int64_t value;
1497
65cd9064
MA		 1498 visit_type_int(v, &value, name, &local_err);
1499 if (local_err) {
1500 error_propagate(errp, local_err);
c5291a4f
AF		 1501 return;
1502 }
1503 if (value < min || value > max) {
1504 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1505 name ? name : "null", value, min, max);
1506 return;
1507 }
1508
b0704cbd 1509 env->cpuid_version &= ~0xf00f0;
c5291a4f 1510 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1511}
1512
35112e41
AF		 1513static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1514 void *opaque, const char *name,
1515 Error **errp)
1516{
1517 X86CPU *cpu = X86_CPU(obj);
1518 CPUX86State *env = &cpu->env;
1519 int64_t value;
1520
1521 value = env->cpuid_version & 0xf;
1522 visit_type_int(v, &value, name, errp);
1523}
1524
036e2222
AF		 1525static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1526 void *opaque, const char *name,
1527 Error **errp)
38c3dc46 1528{
036e2222
AF		 1529 X86CPU *cpu = X86_CPU(obj);
1530 CPUX86State *env = &cpu->env;
1531 const int64_t min = 0;
1532 const int64_t max = 0xf;
65cd9064 1533 Error *local_err = NULL;
036e2222
AF		 1534 int64_t value;
1535
65cd9064
MA		 1536 visit_type_int(v, &value, name, &local_err);
1537 if (local_err) {
1538 error_propagate(errp, local_err);
036e2222
AF		 1539 return;
1540 }
1541 if (value < min || value > max) {
1542 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1543 name ? name : "null", value, min, max);
1544 return;
1545 }
1546
38c3dc46 1547 env->cpuid_version &= ~0xf;
036e2222 1548 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1549}
1550
8e1898bf
AF		 1551static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1552 const char *name, Error **errp)
1553{
1554 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1555
fa029887 1556 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1557}
1558
1559static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1560 const char *name, Error **errp)
1561{
1562 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1563
fa029887 1564 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1565}
1566
16b93aa8
AF		 1567static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1568 const char *name, Error **errp)
1569{
1570 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1571
fa029887 1572 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1573}
1574
1575static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1576 const char *name, Error **errp)
1577{
1578 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1579
fa029887 1580 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1581}
1582
d480e1af
AF		 1583static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1584{
1585 X86CPU *cpu = X86_CPU(obj);
1586 CPUX86State *env = &cpu->env;
1587 char *value;
d480e1af 1588
e42a92ae 1589 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1590 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1591 env->cpuid_vendor3);
d480e1af
AF		 1592 return value;
1593}
1594
1595static void x86_cpuid_set_vendor(Object *obj, const char *value,
1596 Error **errp)
1597{
1598 X86CPU *cpu = X86_CPU(obj);
1599 CPUX86State *env = &cpu->env;
1600 int i;
1601
9df694ee 1602 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1603 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1604 "vendor", value);
1605 return;
1606 }
1607
1608 env->cpuid_vendor1 = 0;
1609 env->cpuid_vendor2 = 0;
1610 env->cpuid_vendor3 = 0;
1611 for (i = 0; i < 4; i++) {
1612 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1613 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1614 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1615 }
d480e1af
AF		 1616}
1617
63e886eb
AF		 1618static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1619{
1620 X86CPU *cpu = X86_CPU(obj);
1621 CPUX86State *env = &cpu->env;
1622 char *value;
1623 int i;
1624
1625 value = g_malloc(48 + 1);
1626 for (i = 0; i < 48; i++) {
1627 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1628 }
1629 value[48] = '\0';
1630 return value;
1631}
1632
938d4c25
AF		 1633static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1634 Error **errp)
dcce6675 1635{
938d4c25
AF		 1636 X86CPU *cpu = X86_CPU(obj);
1637 CPUX86State *env = &cpu->env;
dcce6675
AF		 1638 int c, len, i;
1639
1640 if (model_id == NULL) {
1641 model_id = "";
1642 }
1643 len = strlen(model_id);
d0a6acf4 1644 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1645 for (i = 0; i < 48; i++) {
1646 if (i >= len) {
1647 c = '\0';
1648 } else {
1649 c = (uint8_t)model_id[i];
1650 }
1651 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1652 }
1653}
1654
89e48965
AF		 1655static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1656 const char *name, Error **errp)
1657{
1658 X86CPU *cpu = X86_CPU(obj);
1659 int64_t value;
1660
1661 value = cpu->env.tsc_khz * 1000;
1662 visit_type_int(v, &value, name, errp);
1663}
1664
1665static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1666 const char *name, Error **errp)
1667{
1668 X86CPU *cpu = X86_CPU(obj);
1669 const int64_t min = 0;
2e84849a 1670 const int64_t max = INT64_MAX;
65cd9064 1671 Error *local_err = NULL;
89e48965
AF		 1672 int64_t value;
1673
65cd9064
MA		 1674 visit_type_int(v, &value, name, &local_err);
1675 if (local_err) {
1676 error_propagate(errp, local_err);
89e48965
AF		 1677 return;
1678 }
1679 if (value < min || value > max) {
1680 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1681 name ? name : "null", value, min, max);
1682 return;
1683 }
1684
1685 cpu->env.tsc_khz = value / 1000;
1686}
1687
31050930
IM		 1688static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1689 const char *name, Error **errp)
1690{
1691 X86CPU *cpu = X86_CPU(obj);
9e9d3863 1692 int64_t value = cpu->apic_id;
31050930
IM		 1693
1694 visit_type_int(v, &value, name, errp);
1695}
1696
1697static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1698 const char *name, Error **errp)
1699{
1700 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1701 DeviceState *dev = DEVICE(obj);
31050930
IM		 1702 const int64_t min = 0;
1703 const int64_t max = UINT32_MAX;
1704 Error *error = NULL;
1705 int64_t value;
1706
8d6d4980
IM		 1707 if (dev->realized) {
1708 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1709 "it was realized", name, object_get_typename(obj));
1710 return;
1711 }
1712
31050930
IM		 1713 visit_type_int(v, &value, name, &error);
1714 if (error) {
1715 error_propagate(errp, error);
1716 return;
1717 }
1718 if (value < min || value > max) {
1719 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1720 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1721 object_get_typename(obj), name, value, min, max);
1722 return;
1723 }
1724
9e9d3863 1725 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1726 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1727 return;
1728 }
9e9d3863 1729 cpu->apic_id = value;
31050930
IM		 1730}
1731
7e5292b5 1732/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1733static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1734 const char *name, Error **errp)
1735{
7e5292b5 1736 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1737 FeatureWord w;
1738 Error *err = NULL;
1739 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1740 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1741 X86CPUFeatureWordInfoList *list = NULL;
1742
1743 for (w = 0; w < FEATURE_WORDS; w++) {
1744 FeatureWordInfo *wi = &feature_word_info[w];
1745 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1746 qwi->cpuid_input_eax = wi->cpuid_eax;
1747 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1748 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1749 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1750 qwi->features = array[w];
8e8aba50
EH		 1751
1752 /* List will be in reverse order, but order shouldn't matter */
1753 list_entries[w].next = list;
1754 list_entries[w].value = &word_infos[w];
1755 list = &list_entries[w];
1756 }
1757
1758 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1759 error_propagate(errp, err);
1760}
1761
c8f0f88e
IM		 1762static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1763 const char *name, Error **errp)
1764{
1765 X86CPU *cpu = X86_CPU(obj);
1766 int64_t value = cpu->hyperv_spinlock_attempts;
1767
1768 visit_type_int(v, &value, name, errp);
1769}
1770
1771static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1772 const char *name, Error **errp)
1773{
1774 const int64_t min = 0xFFF;
1775 const int64_t max = UINT_MAX;
1776 X86CPU *cpu = X86_CPU(obj);
1777 Error *err = NULL;
1778 int64_t value;
1779
1780 visit_type_int(v, &value, name, &err);
1781 if (err) {
1782 error_propagate(errp, err);
1783 return;
1784 }
1785
1786 if (value < min || value > max) {
1787 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1788 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1789 object_get_typename(obj), name ? name : "null",
1790 value, min, max);
c8f0f88e
IM		 1791 return;
1792 }
1793 cpu->hyperv_spinlock_attempts = value;
1794}
1795
1796static PropertyInfo qdev_prop_spinlocks = {
1797 .name = "int",
1798 .get = x86_get_hv_spinlocks,
1799 .set = x86_set_hv_spinlocks,
1800};
1801
72ac2e87
IM		 1802/* Convert all '_' in a feature string option name to '-', to make feature
1803 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1804 */
1805static inline void feat2prop(char *s)
1806{
1807 while ((s = strchr(s, '_'))) {
1808 *s = '-';
1809 }
1810}
1811
8f961357
EH		 1812/* Parse "+feature,-feature,feature=foo" CPU feature string
1813 */
94a444b2
AF		 1814static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1815 Error **errp)
8f961357 1816{
94a444b2 1817 X86CPU *cpu = X86_CPU(cs);
8f961357 1818 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1819 FeatureWord w;
8f961357 1820 /* Features to be added */
077c68c3 1821 FeatureWordArray plus_features = { 0 };
8f961357 1822 /* Features to be removed */
5ef57876 1823 FeatureWordArray minus_features = { 0 };
8f961357 1824 uint32_t numvalue;
a91987c2 1825 CPUX86State *env = &cpu->env;
94a444b2 1826 Error *local_err = NULL;
8f961357 1827
8f961357 1828 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1829
1830 while (featurestr) {
1831 char *val;
1832 if (featurestr[0] == '+') {
c00c94ab 1833 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1834 } else if (featurestr[0] == '-') {
c00c94ab 1835 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1836 } else if ((val = strchr(featurestr, '='))) {
1837 *val = 0; val++;
72ac2e87 1838 feat2prop(featurestr);
d024d209 1839 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1840 char *err;
a91987c2
IM		 1841 char num[32];
1842
c6dc6f63
AP		 1843 numvalue = strtoul(val, &err, 0);
1844 if (!*val || *err) {
6b1dd54b
PB		 1845 error_setg(errp, "bad numerical value %s", val);
1846 return;
c6dc6f63
AP		 1847 }
1848 if (numvalue < 0x80000000) {
94a444b2
AF		 1849 error_report("xlevel value shall always be >= 0x80000000"
1850 ", fixup will be removed in future versions");
2f7a21c4 1851 numvalue += 0x80000000;
c6dc6f63 1852 }
a91987c2 1853 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1854 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1855 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1856 int64_t tsc_freq;
1857 char *err;
a91987c2 1858 char num[32];
b862d1fe
JR		 1859
1860 tsc_freq = strtosz_suffix_unit(val, &err,
1861 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1862 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1863 error_setg(errp, "bad numerical value %s", val);
1864 return;
b862d1fe 1865 }
a91987c2 1866 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1867 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1868 &local_err);
72ac2e87 1869 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1870 char *err;
92067bf4 1871 const int min = 0xFFF;
c8f0f88e 1872 char num[32];
28f52cc0
VR		 1873 numvalue = strtoul(val, &err, 0);
1874 if (!*val || *err) {
6b1dd54b
PB		 1875 error_setg(errp, "bad numerical value %s", val);
1876 return;
28f52cc0 1877 }
92067bf4 1878 if (numvalue < min) {
94a444b2 1879 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1880 ", fixup will be removed in future versions",
1881 min);
92067bf4
IM		 1882 numvalue = min;
1883 }
c8f0f88e 1884 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1885 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1886 } else {
94a444b2 1887 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1888 }
c6dc6f63 1889 } else {
258f5abe 1890 feat2prop(featurestr);
94a444b2 1891 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1892 }
94a444b2
AF		 1893 if (local_err) {
1894 error_propagate(errp, local_err);
6b1dd54b 1895 return;
c6dc6f63
AP		 1896 }
1897 featurestr = strtok(NULL, ",");
1898 }
e1c224b4 1899
4d1b279b
EH		 1900 if (cpu->host_features) {
1901 for (w = 0; w < FEATURE_WORDS; w++) {
1902 env->features[w] =
1903 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1904 }
1905 }
1906
e1c224b4
EH		 1907 for (w = 0; w < FEATURE_WORDS; w++) {
1908 env->features[w] |= plus_features[w];
1909 env->features[w] &= ~minus_features[w];
1910 }
c6dc6f63
AP		 1911}
1912
a3c2ca7d 1913/* Print all cpuid feature names in featureset
c6dc6f63 1914 */
a3c2ca7d 1915static void listflags(FILE *f, fprintf_function print, const char **featureset)
c6dc6f63 1916{
a3c2ca7d
EH		 1917 int bit;
1918 bool first = true;
1919
1920 for (bit = 0; bit < 32; bit++) {
1921 if (featureset[bit]) {
1922 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1923 first = false;
c6dc6f63 1924 }
a3c2ca7d 1925 }
c6dc6f63
AP		 1926}
1927
e916cbf8
PM		 1928/* generate CPU information. */
1929void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1930{
9576de75 1931 X86CPUDefinition *def;
c6dc6f63 1932 char buf[256];
7fc9b714 1933 int i;
c6dc6f63 1934
7fc9b714
AF		 1935 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1936 def = &builtin_x86_defs[i];
c04321b3 1937 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1938 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1939 }
21ad7789
JK		 1940#ifdef CONFIG_KVM
1941 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1942 "KVM processor with all supported host features "
1943 "(only available in KVM mode)");
1944#endif
1945
6cdf8854 1946 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1947 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1948 FeatureWordInfo *fw = &feature_word_info[i];
1949
a3c2ca7d
EH		 1950 (*cpu_fprintf)(f, " ");
1951 listflags(f, cpu_fprintf, fw->feat_names);
1952 (*cpu_fprintf)(f, "\n");
3af60be2 1953 }
c6dc6f63
AP		 1954}
1955
76b64a7a 1956CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1957{
1958 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1959 X86CPUDefinition *def;
7fc9b714 1960 int i;
e3966126 1961
7fc9b714 1962 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1963 CpuDefinitionInfoList *entry;
1964 CpuDefinitionInfo *info;
1965
7fc9b714 1966 def = &builtin_x86_defs[i];
e3966126
AL		 1967 info = g_malloc0(sizeof(*info));
1968 info->name = g_strdup(def->name);
1969
1970 entry = g_malloc0(sizeof(*entry));
1971 entry->value = info;
1972 entry->next = cpu_list;
1973 cpu_list = entry;
1974 }
1975
1976 return cpu_list;
1977}
1978
84f1b92f
EH		 1979static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1980 bool migratable_only)
27418adf
EH		 1981{
1982 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 1983 uint32_t r;
27418adf 1984
fefb41bf 1985 if (kvm_enabled()) {
84f1b92f
EH		 1986 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1987 wi->cpuid_ecx,
1988 wi->cpuid_reg);
fefb41bf 1989 } else if (tcg_enabled()) {
84f1b92f 1990 r = wi->tcg_features;
fefb41bf
EH		 1991 } else {
1992 return ~0;
1993 }
84f1b92f
EH		 1994 if (migratable_only) {
1995 r &= x86_cpu_get_migratable_flags(w);
1996 }
1997 return r;
27418adf
EH		 1998}
1999
51f63aed
EH		 2000/*
2001 * Filters CPU feature words based on host availability of each feature.
2002 *
51f63aed
EH		 2003 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2004 */
27418adf 2005static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2006{
2007 CPUX86State *env = &cpu->env;
bd87d2a2 2008 FeatureWord w;
51f63aed
EH		 2009 int rv = 0;
2010
bd87d2a2 2011 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2012 uint32_t host_feat =
2013 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2014 uint32_t requested_features = env->features[w];
2015 env->features[w] &= host_feat;
2016 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2017 if (cpu->filtered_features[w]) {
2018 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2019 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2020 }
2021 rv = 1;
2022 }
bd87d2a2 2023 }
51f63aed
EH		 2024
2025 return rv;
bc74b7db 2026}
bc74b7db 2027
d940ee9b 2028/* Load data from X86CPUDefinition
c080e30e 2029 */
d940ee9b 2030static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2031{
61dcd775 2032 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2033 const char *vendor;
2034 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2035 FeatureWord w;
c6dc6f63 2036
2d64255b
AF		 2037 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2038 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2039 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2040 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2041 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 2042 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 2043 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2044 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2045 for (w = 0; w < FEATURE_WORDS; w++) {
2046 env->features[w] = def->features[w];
2047 }
82beb536 2048
9576de75 2049 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2050 if (kvm_enabled()) {
5fcca9ff
EH		 2051 FeatureWord w;
2052 for (w = 0; w < FEATURE_WORDS; w++) {
2053 env->features[w] |= kvm_default_features[w];
136a7e9a 2054 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2055 }
82beb536 2056 }
5fcca9ff 2057
82beb536 2058 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2059
2060 /* sysenter isn't supported in compatibility mode on AMD,
2061 * syscall isn't supported in compatibility mode on Intel.
2062 * Normally we advertise the actual CPU vendor, but you can
2063 * override this using the 'vendor' property if you want to use
2064 * KVM's sysenter/syscall emulation in compatibility mode and
2065 * when doing cross vendor migration
2066 */
74f54bc4 2067 vendor = def->vendor;
7c08db30
EH		 2068 if (kvm_enabled()) {
2069 uint32_t ebx = 0, ecx = 0, edx = 0;
2070 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2071 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2072 vendor = host_vendor;
2073 }
2074
2075 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2076
c6dc6f63
AP		 2077}
2078
62fc403f
IM		 2079X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
2080 Error **errp)
5c3c6a68 2081{
2d64255b 2082 X86CPU *cpu = NULL;
d940ee9b 2083 X86CPUClass *xcc;
500050d1 2084 ObjectClass *oc;
2d64255b
AF		 2085 gchar **model_pieces;
2086 char *name, *features;
5c3c6a68
AF		 2087 Error *error = NULL;
2088
2d64255b
AF		 2089 model_pieces = g_strsplit(cpu_model, ",", 2);
2090 if (!model_pieces[0]) {
2091 error_setg(&error, "Invalid/empty CPU model name");
2092 goto out;
2093 }
2094 name = model_pieces[0];
2095 features = model_pieces[1];
2096
500050d1
AF		 2097 oc = x86_cpu_class_by_name(name);
2098 if (oc == NULL) {
2099 error_setg(&error, "Unable to find CPU definition: %s", name);
2100 goto out;
2101 }
d940ee9b
EH		 2102 xcc = X86_CPU_CLASS(oc);
2103
2104 if (xcc->kvm_required && !kvm_enabled()) {
2105 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2106 goto out;
2107 }
2108
d940ee9b
EH		 2109 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2110
62fc403f
IM		 2111#ifndef CONFIG_USER_ONLY
2112 if (icc_bridge == NULL) {
2113 error_setg(&error, "Invalid icc-bridge value");
2114 goto out;
2115 }
2116 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2117 object_unref(OBJECT(cpu));
2118#endif
5c3c6a68 2119
94a444b2 2120 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2121 if (error) {
2122 goto out;
5c3c6a68
AF		 2123 }
2124
7f833247 2125out:
cd7b87ff
AF		 2126 if (error != NULL) {
2127 error_propagate(errp, error);
500050d1
AF		 2128 if (cpu) {
2129 object_unref(OBJECT(cpu));
2130 cpu = NULL;
2131 }
cd7b87ff 2132 }
7f833247
IM		 2133 g_strfreev(model_pieces);
2134 return cpu;
2135}
2136
15258d46 2137CPUX86State *cpu_x86_init_user(const char *cpu_model)
7f833247
IM		 2138{
2139 Error *error = NULL;
2140 X86CPU *cpu;
2141
62fc403f 2142 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 2143 if (error) {
18b0e4e7 2144 goto error;
2d64255b
AF		 2145 }
2146
9c235e83
EH		 2147 object_property_set_int(OBJECT(cpu), CPU(cpu)->cpu_index, "apic-id",
2148 &error);
2149 if (error) {
2150 goto error;
2151 }
7f833247 2152
7f833247 2153 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2d64255b 2154 if (error) {
18b0e4e7 2155 goto error;
5c3c6a68 2156 }
18b0e4e7 2157
15258d46 2158 return &cpu->env;
18b0e4e7
EH		 2159
2160error:
b8a173b2 2161 error_report_err(error);
18b0e4e7
EH		 2162 if (cpu != NULL) {
2163 object_unref(OBJECT(cpu));
2164 }
2165 return NULL;
5c3c6a68
AF		 2166}
2167
d940ee9b
EH		 2168static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2169{
2170 X86CPUDefinition *cpudef = data;
2171 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2172
2173 xcc->cpu_def = cpudef;
2174}
2175
2176static void x86_register_cpudef_type(X86CPUDefinition *def)
2177{
2178 char *typename = x86_cpu_type_name(def->name);
2179 TypeInfo ti = {
2180 .name = typename,
2181 .parent = TYPE_X86_CPU,
2182 .class_init = x86_cpu_cpudef_class_init,
2183 .class_data = def,
2184 };
2185
2186 type_register(&ti);
2187 g_free(typename);
2188}
2189
c6dc6f63 2190#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2191
0e26b7b8
BS		 2192void cpu_clear_apic_feature(CPUX86State *env)
2193{
0514ef2f 2194 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2195}
2196
c6dc6f63
AP		 2197#endif /* !CONFIG_USER_ONLY */
2198
c04321b3 2199/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2200 */
2201void x86_cpudef_setup(void)
2202{
93bfef4c
CV		 2203 int i, j;
2204 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2205
2206 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2207 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2208
2209 /* Look for specific "cpudef" models that */
09faecf2 2210 /* have the QEMU version in .model_id */
93bfef4c 2211 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2212 if (strcmp(model_with_versions[j], def->name) == 0) {
2213 pstrcpy(def->model_id, sizeof(def->model_id),
2214 "QEMU Virtual CPU version ");
2215 pstrcat(def->model_id, sizeof(def->model_id),
2216 qemu_get_version());
93bfef4c
CV		 2217 break;
2218 }
2219 }
c6dc6f63 2220 }
c6dc6f63
AP		 2221}
2222
c6dc6f63
AP		 2223void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2224 uint32_t *eax, uint32_t *ebx,
2225 uint32_t *ecx, uint32_t *edx)
2226{
a60f24b5
AF		 2227 X86CPU *cpu = x86_env_get_cpu(env);
2228 CPUState *cs = CPU(cpu);
2229
c6dc6f63
AP		 2230 /* test if maximum index reached */
2231 if (index & 0x80000000) {
b3baa152
BW		 2232 if (index > env->cpuid_xlevel) {
2233 if (env->cpuid_xlevel2 > 0) {
2234 /* Handle the Centaur's CPUID instruction. */
2235 if (index > env->cpuid_xlevel2) {
2236 index = env->cpuid_xlevel2;
2237 } else if (index < 0xC0000000) {
2238 index = env->cpuid_xlevel;
2239 }
2240 } else {
57f26ae7
EH		 2241 /* Intel documentation states that invalid EAX input will
2242 * return the same information as EAX=cpuid_level
2243 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2244 */
2245 index = env->cpuid_level;
b3baa152
BW		 2246 }
2247 }
c6dc6f63
AP		 2248 } else {
2249 if (index > env->cpuid_level)
2250 index = env->cpuid_level;
2251 }
2252
2253 switch(index) {
2254 case 0:
2255 *eax = env->cpuid_level;
08e1a1e5
EH		 2256 *ebx = env->cpuid_vendor1;
2257 *edx = env->cpuid_vendor2;
2258 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2259 break;
2260 case 1:
2261 *eax = env->cpuid_version;
9e9d3863
EH		 2262 *ebx = (cpu->apic_id << 24) |
2263 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2264 *ecx = env->features[FEAT_1_ECX];
2265 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2266 if (cs->nr_cores * cs->nr_threads > 1) {
2267 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2268 *edx |= 1 << 28; /* HTT bit */
2269 }
2270 break;
2271 case 2:
2272 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2273 if (cpu->cache_info_passthrough) {
2274 host_cpuid(index, 0, eax, ebx, ecx, edx);
2275 break;
2276 }
5e891bf8 2277 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2278 *ebx = 0;
2279 *ecx = 0;
5e891bf8
EH		 2280 *edx = (L1D_DESCRIPTOR << 16) | \
2281 (L1I_DESCRIPTOR << 8) | \
2282 (L2_DESCRIPTOR);
c6dc6f63
AP		 2283 break;
2284 case 4:
2285 /* cache info: needed for Core compatibility */
787aaf57
BC		 2286 if (cpu->cache_info_passthrough) {
2287 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2288 *eax &= ~0xFC000000;
c6dc6f63 2289 } else {
2f7a21c4 2290 *eax = 0;
76c2975a 2291 switch (count) {
c6dc6f63 2292 case 0: /* L1 dcache info */
5e891bf8
EH		 2293 *eax |= CPUID_4_TYPE_DCACHE | \
2294 CPUID_4_LEVEL(1) | \
2295 CPUID_4_SELF_INIT_LEVEL;
2296 *ebx = (L1D_LINE_SIZE - 1) | \
2297 ((L1D_PARTITIONS - 1) << 12) | \
2298 ((L1D_ASSOCIATIVITY - 1) << 22);
2299 *ecx = L1D_SETS - 1;
2300 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2301 break;
2302 case 1: /* L1 icache info */
5e891bf8
EH		 2303 *eax |= CPUID_4_TYPE_ICACHE | \
2304 CPUID_4_LEVEL(1) | \
2305 CPUID_4_SELF_INIT_LEVEL;
2306 *ebx = (L1I_LINE_SIZE - 1) | \
2307 ((L1I_PARTITIONS - 1) << 12) | \
2308 ((L1I_ASSOCIATIVITY - 1) << 22);
2309 *ecx = L1I_SETS - 1;
2310 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2311 break;
2312 case 2: /* L2 cache info */
5e891bf8
EH		 2313 *eax |= CPUID_4_TYPE_UNIFIED | \
2314 CPUID_4_LEVEL(2) | \
2315 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2316 if (cs->nr_threads > 1) {
2317 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2318 }
5e891bf8
EH		 2319 *ebx = (L2_LINE_SIZE - 1) | \
2320 ((L2_PARTITIONS - 1) << 12) | \
2321 ((L2_ASSOCIATIVITY - 1) << 22);
2322 *ecx = L2_SETS - 1;
2323 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2324 break;
2325 default: /* end of info */
2326 *eax = 0;
2327 *ebx = 0;
2328 *ecx = 0;
2329 *edx = 0;
2330 break;
76c2975a
PB		 2331 }
2332 }
2333
2334 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2335 if ((*eax & 31) && cs->nr_cores > 1) {
2336 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2337 }
2338 break;
2339 case 5:
2340 /* mwait info: needed for Core compatibility */
2341 *eax = 0; /* Smallest monitor-line size in bytes */
2342 *ebx = 0; /* Largest monitor-line size in bytes */
2343 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2344 *edx = 0;
2345 break;
2346 case 6:
2347 /* Thermal and Power Leaf */
2348 *eax = 0;
2349 *ebx = 0;
2350 *ecx = 0;
2351 *edx = 0;
2352 break;
f7911686 2353 case 7:
13526728
EH		 2354 /* Structured Extended Feature Flags Enumeration Leaf */
2355 if (count == 0) {
2356 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2357 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2358 *ecx = 0; /* Reserved */
2359 *edx = 0; /* Reserved */
f7911686
YW		 2360 } else {
2361 *eax = 0;
2362 *ebx = 0;
2363 *ecx = 0;
2364 *edx = 0;
2365 }
2366 break;
c6dc6f63
AP		 2367 case 9:
2368 /* Direct Cache Access Information Leaf */
2369 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2370 *ebx = 0;
2371 *ecx = 0;
2372 *edx = 0;
2373 break;
2374 case 0xA:
2375 /* Architectural Performance Monitoring Leaf */
9337e3b6 2376 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2377 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2378
2379 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2380 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2381 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2382 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2383 } else {
2384 *eax = 0;
2385 *ebx = 0;
2386 *ecx = 0;
2387 *edx = 0;
2388 }
c6dc6f63 2389 break;
2560f19f
PB		 2390 case 0xD: {
2391 KVMState *s = cs->kvm_state;
2392 uint64_t kvm_mask;
2393 int i;
2394
51e49430 2395 /* Processor Extended State */
2560f19f
PB		 2396 *eax = 0;
2397 *ebx = 0;
2398 *ecx = 0;
2399 *edx = 0;
2400 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2401 break;
2402 }
2560f19f
PB		 2403 kvm_mask =
2404 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2405 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2406
2560f19f
PB		 2407 if (count == 0) {
2408 *ecx = 0x240;
2409 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2410 const ExtSaveArea *esa = &ext_save_areas[i];
2411 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2412 (kvm_mask & (1 << i)) != 0) {
2413 if (i < 32) {
2414 *eax |= 1 << i;
2415 } else {
2416 *edx |= 1 << (i - 32);
2417 }
2418 *ecx = MAX(*ecx, esa->offset + esa->size);
2419 }
2420 }
2421 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2422 *ebx = *ecx;
2423 } else if (count == 1) {
0bb0b2d2 2424 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2425 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2426 const ExtSaveArea *esa = &ext_save_areas[count];
2427 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2428 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2429 *eax = esa->size;
2430 *ebx = esa->offset;
2560f19f 2431 }
51e49430
SY		 2432 }
2433 break;
2560f19f 2434 }
c6dc6f63
AP		 2435 case 0x80000000:
2436 *eax = env->cpuid_xlevel;
2437 *ebx = env->cpuid_vendor1;
2438 *edx = env->cpuid_vendor2;
2439 *ecx = env->cpuid_vendor3;
2440 break;
2441 case 0x80000001:
2442 *eax = env->cpuid_version;
2443 *ebx = 0;
0514ef2f
EH		 2444 *ecx = env->features[FEAT_8000_0001_ECX];
2445 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2446
2447 /* The Linux kernel checks for the CMPLegacy bit and
2448 * discards multiple thread information if it is set.
2449 * So dont set it here for Intel to make Linux guests happy.
2450 */
ce3960eb 2451 if (cs->nr_cores * cs->nr_threads > 1) {
08e1a1e5
EH		 2452 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2453 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2454 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2455 *ecx |= 1 << 1; /* CmpLegacy bit */
2456 }
2457 }
c6dc6f63
AP		 2458 break;
2459 case 0x80000002:
2460 case 0x80000003:
2461 case 0x80000004:
2462 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2463 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2464 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2465 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2466 break;
2467 case 0x80000005:
2468 /* cache info (L1 cache) */
787aaf57
BC		 2469 if (cpu->cache_info_passthrough) {
2470 host_cpuid(index, 0, eax, ebx, ecx, edx);
2471 break;
2472 }
5e891bf8
EH		 2473 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2474 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2475 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2476 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2477 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2478 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2479 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2480 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2481 break;
2482 case 0x80000006:
2483 /* cache info (L2 cache) */
787aaf57
BC		 2484 if (cpu->cache_info_passthrough) {
2485 host_cpuid(index, 0, eax, ebx, ecx, edx);
2486 break;
2487 }
5e891bf8
EH		 2488 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2489 (L2_DTLB_2M_ENTRIES << 16) | \
2490 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2491 (L2_ITLB_2M_ENTRIES);
2492 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2493 (L2_DTLB_4K_ENTRIES << 16) | \
2494 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2495 (L2_ITLB_4K_ENTRIES);
2496 *ecx = (L2_SIZE_KB_AMD << 16) | \
2497 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2498 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2499 *edx = ((L3_SIZE_KB/512) << 18) | \
2500 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2501 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2502 break;
303752a9
MT		 2503 case 0x80000007:
2504 *eax = 0;
2505 *ebx = 0;
2506 *ecx = 0;
2507 *edx = env->features[FEAT_8000_0007_EDX];
2508 break;
c6dc6f63
AP		 2509 case 0x80000008:
2510 /* virtual & phys address size in low 2 bytes. */
2511/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2512 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2513 /* 64 bit processor */
2514/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2515 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2516 } else {
0514ef2f 2517 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2518 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2519 } else {
c6dc6f63 2520 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2521 }
c6dc6f63
AP		 2522 }
2523 *ebx = 0;
2524 *ecx = 0;
2525 *edx = 0;
ce3960eb
AF		 2526 if (cs->nr_cores * cs->nr_threads > 1) {
2527 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2528 }
2529 break;
2530 case 0x8000000A:
0514ef2f 2531 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2532 *eax = 0x00000001; /* SVM Revision */
2533 *ebx = 0x00000010; /* nr of ASIDs */
2534 *ecx = 0;
0514ef2f 2535 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2536 } else {
2537 *eax = 0;
2538 *ebx = 0;
2539 *ecx = 0;
2540 *edx = 0;
2541 }
c6dc6f63 2542 break;
b3baa152
BW		 2543 case 0xC0000000:
2544 *eax = env->cpuid_xlevel2;
2545 *ebx = 0;
2546 *ecx = 0;
2547 *edx = 0;
2548 break;
2549 case 0xC0000001:
2550 /* Support for VIA CPU's CPUID instruction */
2551 *eax = env->cpuid_version;
2552 *ebx = 0;
2553 *ecx = 0;
0514ef2f 2554 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2555 break;
2556 case 0xC0000002:
2557 case 0xC0000003:
2558 case 0xC0000004:
2559 /* Reserved for the future, and now filled with zero */
2560 *eax = 0;
2561 *ebx = 0;
2562 *ecx = 0;
2563 *edx = 0;
2564 break;
c6dc6f63
AP		 2565 default:
2566 /* reserved values: zero */
2567 *eax = 0;
2568 *ebx = 0;
2569 *ecx = 0;
2570 *edx = 0;
2571 break;
2572 }
2573}
5fd2087a
AF		 2574
2575/* CPUClass::reset() */
2576static void x86_cpu_reset(CPUState *s)
2577{
2578 X86CPU *cpu = X86_CPU(s);
2579 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2580 CPUX86State *env = &cpu->env;
c1958aea
AF		 2581 int i;
2582
5fd2087a
AF		 2583 xcc->parent_reset(s);
2584
43175fa9 2585 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2586
00c8cb0a 2587 tlb_flush(s, 1);
c1958aea
AF		 2588
2589 env->old_exception = -1;
2590
2591 /* init to reset state */
2592
2593#ifdef CONFIG_SOFTMMU
2594 env->hflags |= HF_SOFTMMU_MASK;
2595#endif
2596 env->hflags2 |= HF2_GIF_MASK;
2597
2598 cpu_x86_update_cr0(env, 0x60000010);
2599 env->a20_mask = ~0x0;
2600 env->smbase = 0x30000;
2601
2602 env->idt.limit = 0xffff;
2603 env->gdt.limit = 0xffff;
2604 env->ldt.limit = 0xffff;
2605 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2606 env->tr.limit = 0xffff;
2607 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2608
2609 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2610 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2611 DESC_R_MASK | DESC_A_MASK);
2612 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2613 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2614 DESC_A_MASK);
2615 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2616 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2617 DESC_A_MASK);
2618 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2619 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2620 DESC_A_MASK);
2621 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2622 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2623 DESC_A_MASK);
2624 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2625 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2626 DESC_A_MASK);
2627
2628 env->eip = 0xfff0;
2629 env->regs[R_EDX] = env->cpuid_version;
2630
2631 env->eflags = 0x2;
2632
2633 /* FPU init */
2634 for (i = 0; i < 8; i++) {
2635 env->fptags[i] = 1;
2636 }
5bde1407 2637 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2638
2639 env->mxcsr = 0x1f80;
c74f41bb 2640 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2641
2642 env->pat = 0x0007040600070406ULL;
2643 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2644
2645 memset(env->dr, 0, sizeof(env->dr));
2646 env->dr[6] = DR6_FIXED_1;
2647 env->dr[7] = DR7_FIXED_1;
b3310ab3 2648 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2649 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2650
05e7e819 2651 env->xcr0 = 1;
0522604b 2652
9db2efd9
AW		 2653 /*
2654 * SDM 11.11.5 requires:
2655 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2656 * - IA32_MTRR_PHYSMASKn.V = 0
2657 * All other bits are undefined. For simplification, zero it all.
2658 */
2659 env->mtrr_deftype = 0;
2660 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2661 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2662
dd673288
IM		 2663#if !defined(CONFIG_USER_ONLY)
2664 /* We hard-wire the BSP to the first CPU. */
55e5c285 2665 if (s->cpu_index == 0) {
02e51483 2666 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2667 }
2668
259186a7 2669 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2670
2671 if (kvm_enabled()) {
2672 kvm_arch_reset_vcpu(cpu);
2673 }
dd673288 2674#endif
5fd2087a
AF		 2675}
2676
dd673288
IM		 2677#ifndef CONFIG_USER_ONLY
2678bool cpu_is_bsp(X86CPU *cpu)
2679{
02e51483 2680 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2681}
65dee380
IM		 2682
2683/* TODO: remove me, when reset over QOM tree is implemented */
2684static void x86_cpu_machine_reset_cb(void *opaque)
2685{
2686 X86CPU *cpu = opaque;
2687 cpu_reset(CPU(cpu));
2688}
dd673288
IM		 2689#endif
2690
de024815
AF		 2691static void mce_init(X86CPU *cpu)
2692{
2693 CPUX86State *cenv = &cpu->env;
2694 unsigned int bank;
2695
2696 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2697 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2698 (CPUID_MCE | CPUID_MCA)) {
2699 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2700 cenv->mcg_ctl = ~(uint64_t)0;
2701 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2702 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2703 }
2704 }
2705}
2706
bdeec802 2707#ifndef CONFIG_USER_ONLY
d3c64d6a 2708static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2709{
53a89e26 2710 DeviceState *dev = DEVICE(cpu);
449994eb 2711 APICCommonState *apic;
bdeec802
IM		 2712 const char *apic_type = "apic";
2713
2714 if (kvm_irqchip_in_kernel()) {
2715 apic_type = "kvm-apic";
2716 } else if (xen_enabled()) {
2717 apic_type = "xen-apic";
2718 }
2719
02e51483
CF		 2720 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2721 if (cpu->apic_state == NULL) {
bdeec802
IM		 2722 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2723 return;
2724 }
2725
2726 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2727 OBJECT(cpu->apic_state), NULL);
9e9d3863 2728 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2729 /* TODO: convert to link<> */
02e51483 2730 apic = APIC_COMMON(cpu->apic_state);
60671e58 2731 apic->cpu = cpu;
d3c64d6a
IM		 2732}
2733
2734static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2735{
02e51483 2736 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2737 return;
2738 }
bdeec802 2739
02e51483 2740 if (qdev_init(cpu->apic_state)) {
bdeec802 2741 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2742 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2743 return;
2744 }
bdeec802 2745}
d3c64d6a
IM		 2746#else
2747static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2748{
2749}
bdeec802
IM		 2750#endif
2751
e48638fd
WH		 2752
2753#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2754 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2755 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2756#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2757 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2758 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2759static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2760{
14a10fc3 2761 CPUState *cs = CPU(dev);
2b6f294c
AF		 2762 X86CPU *cpu = X86_CPU(dev);
2763 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2764 CPUX86State *env = &cpu->env;
2b6f294c 2765 Error *local_err = NULL;
e48638fd 2766 static bool ht_warned;
b34d12d1 2767
e1356dd7
EH		 2768 if (cpu->apic_id < 0) {
2769 error_setg(errp, "apic-id property was not initialized properly");
2770 return;
2771 }
2772
0514ef2f 2773 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2774 env->cpuid_level = 7;
2775 }
7a059953 2776
9b15cd9e
IM		 2777 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2778 * CPUID[1].EDX.
2779 */
e48638fd 2780 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2781 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2782 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2783 & CPUID_EXT2_AMD_ALIASES);
2784 }
2785
fefb41bf
EH		 2786
2787 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2788 error_setg(&local_err,
2789 kvm_enabled() ?
2790 "Host doesn't support requested features" :
2791 "TCG doesn't support requested features");
2792 goto out;
4586f157
IM		 2793 }
2794
65dee380
IM		 2795#ifndef CONFIG_USER_ONLY
2796 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2797
0514ef2f 2798 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2799 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2800 if (local_err != NULL) {
4dc1f449 2801 goto out;
bdeec802
IM		 2802 }
2803 }
65dee380
IM		 2804#endif
2805
7a059953 2806 mce_init(cpu);
14a10fc3 2807 qemu_init_vcpu(cs);
d3c64d6a 2808
e48638fd
WH		 2809 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2810 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2811 * based on inputs (sockets,cores,threads), it is still better to gives
2812 * users a warning.
2813 *
2814 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2815 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2816 */
2817 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2818 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2819 " -smp options properly.");
2820 ht_warned = true;
2821 }
2822
d3c64d6a
IM		 2823 x86_cpu_apic_realize(cpu, &local_err);
2824 if (local_err != NULL) {
2825 goto out;
2826 }
14a10fc3 2827 cpu_reset(cs);
2b6f294c 2828
4dc1f449
IM		 2829 xcc->parent_realize(dev, &local_err);
2830out:
2831 if (local_err != NULL) {
2832 error_propagate(errp, local_err);
2833 return;
2834 }
7a059953
AF		 2835}
2836
de024815
AF		 2837static void x86_cpu_initfn(Object *obj)
2838{
55e5c285 2839 CPUState *cs = CPU(obj);
de024815 2840 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2841 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2842 CPUX86State *env = &cpu->env;
d65e9815 2843 static int inited;
de024815 2844
c05efcb1 2845 cs->env_ptr = env;
de024815 2846 cpu_exec_init(env);
71ad61d3
AF		 2847
2848 object_property_add(obj, "family", "int",
95b8519d 2849 x86_cpuid_version_get_family,
71ad61d3 2850 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2851 object_property_add(obj, "model", "int",
67e30c83 2852 x86_cpuid_version_get_model,
c5291a4f 2853 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2854 object_property_add(obj, "stepping", "int",
35112e41 2855 x86_cpuid_version_get_stepping,
036e2222 2856 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2857 object_property_add(obj, "level", "int",
2858 x86_cpuid_get_level,
2859 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2860 object_property_add(obj, "xlevel", "int",
2861 x86_cpuid_get_xlevel,
2862 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2863 object_property_add_str(obj, "vendor",
2864 x86_cpuid_get_vendor,
2865 x86_cpuid_set_vendor, NULL);
938d4c25 2866 object_property_add_str(obj, "model-id",
63e886eb 2867 x86_cpuid_get_model_id,
938d4c25 2868 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2869 object_property_add(obj, "tsc-frequency", "int",
2870 x86_cpuid_get_tsc_freq,
2871 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2872 object_property_add(obj, "apic-id", "int",
2873 x86_cpuid_get_apic_id,
2874 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2875 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2876 x86_cpu_get_feature_words,
7e5292b5
EH		 2877 NULL, NULL, (void *)env->features, NULL);
2878 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2879 x86_cpu_get_feature_words,
2880 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2881
92067bf4 2882 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
e1356dd7 2883 cpu->apic_id = -1;
d65e9815 2884
d940ee9b
EH		 2885 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2886
d65e9815
IM		 2887 /* init various static tables used in TCG mode */
2888 if (tcg_enabled() && !inited) {
2889 inited = 1;
2890 optimize_flags_init();
d65e9815 2891 }
de024815
AF		 2892}
2893
997395d3
IM		 2894static int64_t x86_cpu_get_arch_id(CPUState *cs)
2895{
2896 X86CPU *cpu = X86_CPU(cs);
997395d3 2897
9e9d3863 2898 return cpu->apic_id;
997395d3
IM		 2899}
2900
444d5590
AF		 2901static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2902{
2903 X86CPU *cpu = X86_CPU(cs);
2904
2905 return cpu->env.cr[0] & CR0_PG_MASK;
2906}
2907
f45748f1
AF		 2908static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2909{
2910 X86CPU *cpu = X86_CPU(cs);
2911
2912 cpu->env.eip = value;
2913}
2914
bdf7ae5b
AF		 2915static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2916{
2917 X86CPU *cpu = X86_CPU(cs);
2918
2919 cpu->env.eip = tb->pc - tb->cs_base;
2920}
2921
8c2e1b00
AF		 2922static bool x86_cpu_has_work(CPUState *cs)
2923{
2924 X86CPU *cpu = X86_CPU(cs);
2925 CPUX86State *env = &cpu->env;
2926
60e68042
PB		 2927#if !defined(CONFIG_USER_ONLY)
2928 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2929 apic_poll_irq(cpu->apic_state);
2930 cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
2931 }
2932#endif
2933
2934 return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
8c2e1b00
AF		 2935 (env->eflags & IF_MASK)) ||
2936 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2937 CPU_INTERRUPT_INIT |
2938 CPU_INTERRUPT_SIPI |
2939 CPU_INTERRUPT_MCE));
2940}
2941
9337e3b6
EH		 2942static Property x86_cpu_properties[] = {
2943 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2944 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2945 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2946 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2947 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2948 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2949 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2950 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2951 DEFINE_PROP_END_OF_LIST()
2952};
2953
5fd2087a
AF		 2954static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2955{
2956 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2957 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2958 DeviceClass *dc = DEVICE_CLASS(oc);
2959
2960 xcc->parent_realize = dc->realize;
2961 dc->realize = x86_cpu_realizefn;
62fc403f 2962 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2963 dc->props = x86_cpu_properties;
5fd2087a
AF		 2964
2965 xcc->parent_reset = cc->reset;
2966 cc->reset = x86_cpu_reset;
91b1df8c 2967 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2968
500050d1 2969 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2970 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2971 cc->has_work = x86_cpu_has_work;
97a8ea5a 2972 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 2973 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 2974 cc->dump_state = x86_cpu_dump_state;
f45748f1 2975 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2976 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2977 cc->gdb_read_register = x86_cpu_gdb_read_register;
2978 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2979 cc->get_arch_id = x86_cpu_get_arch_id;
2980 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2981#ifdef CONFIG_USER_ONLY
2982 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2983#else
a23bbfda 2984 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2985 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2986 cc->write_elf64_note = x86_cpu_write_elf64_note;
2987 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2988 cc->write_elf32_note = x86_cpu_write_elf32_note;
2989 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2990 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2991#endif
a0e372f0 2992 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 2993#ifndef CONFIG_USER_ONLY
2994 cc->debug_excp_handler = breakpoint_handler;
2995#endif
374e0cd4
RH		 2996 cc->cpu_exec_enter = x86_cpu_exec_enter;
2997 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 2998}
2999
3000static const TypeInfo x86_cpu_type_info = {
3001 .name = TYPE_X86_CPU,
3002 .parent = TYPE_CPU,
3003 .instance_size = sizeof(X86CPU),
de024815 3004 .instance_init = x86_cpu_initfn,
d940ee9b 3005 .abstract = true,
5fd2087a
AF		 3006 .class_size = sizeof(X86CPUClass),
3007 .class_init = x86_cpu_common_class_init,
3008};
3009
3010static void x86_cpu_register_types(void)
3011{
d940ee9b
EH		 3012 int i;
3013
5fd2087a 3014 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3015 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3016 x86_register_cpudef_type(&builtin_x86_defs[i]);
3017 }
3018#ifdef CONFIG_KVM
3019 type_register_static(&host_x86_cpu_type_info);
3020#endif
5fd2087a
AF		 3021}
3022
3023type_init(x86_cpu_register_types)
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