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target-i386: Simplify listflags() function
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
869b7649 28#include "hw/i386/topology.h"
c6dc6f63 29
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 260 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 262 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 264};
265
303752a9
MT		 266static const char *cpuid_apm_edx_feature_name[] = {
267 NULL, NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 "invtsc", NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275};
276
0bb0b2d2
PB		 277static const char *cpuid_xsave_feature_name[] = {
278 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286};
287
621626ce
EH		 288#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
289#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
290 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
291#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
292 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
293 CPUID_PSE36 | CPUID_FXSR)
294#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
295#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
296 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
297 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
298 CPUID_PAE | CPUID_SEP | CPUID_APIC)
299
300#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
301 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
302 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
303 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
304 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
305 /* partly implemented:
306 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
307 /* missing:
308 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
309#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
310 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
311 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
312 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
313 /* missing:
314 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
315 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
316 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
317 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
318 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
319 CPUID_EXT_RDRAND */
320
321#ifdef TARGET_X86_64
322#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
323#else
324#define TCG_EXT2_X86_64_FEATURES 0
325#endif
326
327#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
328 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
329 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
330 TCG_EXT2_X86_64_FEATURES)
331#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
332 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
333#define TCG_EXT4_FEATURES 0
334#define TCG_SVM_FEATURES 0
335#define TCG_KVM_FEATURES 0
336#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
337 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
338 /* missing:
339 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
340 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
341 CPUID_7_0_EBX_RDSEED */
303752a9 342#define TCG_APM_FEATURES 0
621626ce
EH		 343
344
5ef57876
EH		 345typedef struct FeatureWordInfo {
346 const char **feat_names;
04d104b6
EH		 347 uint32_t cpuid_eax; /* Input EAX for CPUID */
348 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
349 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
350 int cpuid_reg; /* output register (R_* constant) */
37ce3522 351 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 352 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 353} FeatureWordInfo;
354
355static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 356 [FEAT_1_EDX] = {
357 .feat_names = feature_name,
358 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 359 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 360 },
361 [FEAT_1_ECX] = {
362 .feat_names = ext_feature_name,
363 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 364 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 365 },
366 [FEAT_8000_0001_EDX] = {
367 .feat_names = ext2_feature_name,
368 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 369 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 370 },
371 [FEAT_8000_0001_ECX] = {
372 .feat_names = ext3_feature_name,
373 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 374 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 375 },
89e49c8b
EH		 376 [FEAT_C000_0001_EDX] = {
377 .feat_names = ext4_feature_name,
378 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 379 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 380 },
bffd67b0
EH		 381 [FEAT_KVM] = {
382 .feat_names = kvm_feature_name,
383 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 384 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 385 },
386 [FEAT_SVM] = {
387 .feat_names = svm_feature_name,
388 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 389 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 390 },
391 [FEAT_7_0_EBX] = {
392 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 393 .cpuid_eax = 7,
394 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
395 .cpuid_reg = R_EBX,
37ce3522 396 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 397 },
303752a9
MT		 398 [FEAT_8000_0007_EDX] = {
399 .feat_names = cpuid_apm_edx_feature_name,
400 .cpuid_eax = 0x80000007,
401 .cpuid_reg = R_EDX,
402 .tcg_features = TCG_APM_FEATURES,
403 .unmigratable_flags = CPUID_APM_INVTSC,
404 },
0bb0b2d2
PB		 405 [FEAT_XSAVE] = {
406 .feat_names = cpuid_xsave_feature_name,
407 .cpuid_eax = 0xd,
408 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
409 .cpuid_reg = R_EAX,
410 .tcg_features = 0,
0bb0b2d2 411 },
5ef57876
EH		 412};
413
8e8aba50
EH		 414typedef struct X86RegisterInfo32 {
415 /* Name of register */
416 const char *name;
417 /* QAPI enum value register */
418 X86CPURegister32 qapi_enum;
419} X86RegisterInfo32;
420
421#define REGISTER(reg) \
5d371f41 422 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 423static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 424 REGISTER(EAX),
425 REGISTER(ECX),
426 REGISTER(EDX),
427 REGISTER(EBX),
428 REGISTER(ESP),
429 REGISTER(EBP),
430 REGISTER(ESI),
431 REGISTER(EDI),
432};
433#undef REGISTER
434
2560f19f
PB		 435typedef struct ExtSaveArea {
436 uint32_t feature, bits;
437 uint32_t offset, size;
438} ExtSaveArea;
439
440static const ExtSaveArea ext_save_areas[] = {
441 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 442 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 443 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
444 .offset = 0x3c0, .size = 0x40 },
445 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 446 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 447 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
448 .offset = 0x440, .size = 0x40 },
449 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
450 .offset = 0x480, .size = 0x200 },
451 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
452 .offset = 0x680, .size = 0x400 },
2560f19f 453};
8e8aba50 454
8b4beddc
EH		 455const char *get_register_name_32(unsigned int reg)
456{
31ccdde2 457 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 458 return NULL;
459 }
8e8aba50 460 return x86_reg_info_32[reg].name;
8b4beddc
EH		 461}
462
5fcca9ff
EH		 463/* KVM-specific features that are automatically added to all CPU models
464 * when KVM is enabled.
465 */
466static uint32_t kvm_default_features[FEATURE_WORDS] = {
467 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 468 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 469 (1 << KVM_FEATURE_CLOCKSOURCE2) |
470 (1 << KVM_FEATURE_ASYNC_PF) |
471 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 472 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 473 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 474 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 475};
dc59944b 476
136a7e9a
EH		 477/* Features that are not added by default to any CPU model when KVM is enabled.
478 */
479static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 480 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a 481 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
75d373ef 482 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
136a7e9a
EH		 483};
484
1cadaa94 485void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 486{
8fb4f821 487 kvm_default_features[w] &= ~features;
dc59944b
MT		 488}
489
75d373ef
EH		 490void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
491{
492 kvm_default_unset_features[w] &= ~features;
493}
494
84f1b92f
EH		 495/*
496 * Returns the set of feature flags that are supported and migratable by
497 * QEMU, for a given FeatureWord.
498 */
499static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
500{
501 FeatureWordInfo *wi = &feature_word_info[w];
502 uint32_t r = 0;
503 int i;
504
505 for (i = 0; i < 32; i++) {
506 uint32_t f = 1U << i;
507 /* If the feature name is unknown, it is not supported by QEMU yet */
508 if (!wi->feat_names[i]) {
509 continue;
510 }
511 /* Skip features known to QEMU, but explicitly marked as unmigratable */
512 if (wi->unmigratable_flags & f) {
513 continue;
514 }
515 r |= f;
516 }
517 return r;
518}
519
bb44e0d1
JK		 520void host_cpuid(uint32_t function, uint32_t count,
521 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 522{
a1fd24af
AL		 523 uint32_t vec[4];
524
525#ifdef __x86_64__
526 asm volatile("cpuid"
527 : "=a"(vec[0]), "=b"(vec[1]),
528 "=c"(vec[2]), "=d"(vec[3])
529 : "0"(function), "c"(count) : "cc");
c1f41226 530#elif defined(__i386__)
a1fd24af
AL		 531 asm volatile("pusha \n\t"
532 "cpuid \n\t"
533 "mov %%eax, 0(%2) \n\t"
534 "mov %%ebx, 4(%2) \n\t"
535 "mov %%ecx, 8(%2) \n\t"
536 "mov %%edx, 12(%2) \n\t"
537 "popa"
538 : : "a"(function), "c"(count), "S"(vec)
539 : "memory", "cc");
c1f41226
EH		 540#else
541 abort();
a1fd24af
AL		 542#endif
543
bdde476a 544 if (eax)
a1fd24af 545 *eax = vec[0];
bdde476a 546 if (ebx)
a1fd24af 547 *ebx = vec[1];
bdde476a 548 if (ecx)
a1fd24af 549 *ecx = vec[2];
bdde476a 550 if (edx)
a1fd24af 551 *edx = vec[3];
bdde476a 552}
c6dc6f63
AP		 553
554#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
555
556/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
557 * a substring. ex if !NULL points to the first char after a substring,
558 * otherwise the string is assumed to sized by a terminating nul.
559 * Return lexical ordering of *s1:*s2.
560 */
8f9d989c
CF		 561static int sstrcmp(const char *s1, const char *e1,
562 const char *s2, const char *e2)
c6dc6f63
AP		 563{
564 for (;;) {
565 if (!*s1 || !*s2 || *s1 != *s2)
566 return (*s1 - *s2);
567 ++s1, ++s2;
568 if (s1 == e1 && s2 == e2)
569 return (0);
570 else if (s1 == e1)
571 return (*s2);
572 else if (s2 == e2)
573 return (*s1);
574 }
575}
576
577/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
578 * '|' delimited (possibly empty) strings in which case search for a match
579 * within the alternatives proceeds left to right. Return 0 for success,
580 * non-zero otherwise.
581 */
582static int altcmp(const char *s, const char *e, const char *altstr)
583{
584 const char *p, *q;
585
586 for (q = p = altstr; ; ) {
587 while (*p && *p != '|')
588 ++p;
589 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
590 return (0);
591 if (!*p)
592 return (1);
593 else
594 q = ++p;
595 }
596}
597
598/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 599 * *pval and return true, otherwise return false
c6dc6f63 600 */
e41e0fc6
JK		 601static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
602 const char **featureset)
c6dc6f63
AP		 603{
604 uint32_t mask;
605 const char **ppc;
e41e0fc6 606 bool found = false;
c6dc6f63 607
e41e0fc6 608 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 609 if (*ppc && !altcmp(s, e, *ppc)) {
610 *pval |= mask;
e41e0fc6 611 found = true;
c6dc6f63 612 }
e41e0fc6
JK		 613 }
614 return found;
c6dc6f63
AP		 615}
616
5ef57876 617static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 618 FeatureWordArray words,
619 Error **errp)
c6dc6f63 620{
5ef57876
EH		 621 FeatureWord w;
622 for (w = 0; w < FEATURE_WORDS; w++) {
623 FeatureWordInfo *wi = &feature_word_info[w];
624 if (wi->feat_names &&
625 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
626 break;
627 }
628 }
629 if (w == FEATURE_WORDS) {
c00c94ab 630 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 631 }
c6dc6f63
AP		 632}
633
d940ee9b
EH		 634/* CPU class name definitions: */
635
636#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
637#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
638
639/* Return type name for a given CPU model name
640 * Caller is responsible for freeing the returned string.
641 */
642static char *x86_cpu_type_name(const char *model_name)
643{
644 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
645}
646
500050d1
AF		 647static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
648{
d940ee9b
EH		 649 ObjectClass *oc;
650 char *typename;
651
500050d1
AF		 652 if (cpu_model == NULL) {
653 return NULL;
654 }
655
d940ee9b
EH		 656 typename = x86_cpu_type_name(cpu_model);
657 oc = object_class_by_name(typename);
658 g_free(typename);
659 return oc;
500050d1
AF		 660}
661
d940ee9b 662struct X86CPUDefinition {
c6dc6f63
AP		 663 const char *name;
664 uint32_t level;
90e4b0c3
EH		 665 uint32_t xlevel;
666 uint32_t xlevel2;
99b88a17
IM		 667 /* vendor is zero-terminated, 12 character ASCII string */
668 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 669 int family;
670 int model;
671 int stepping;
0514ef2f 672 FeatureWordArray features;
c6dc6f63 673 char model_id[48];
787aaf57 674 bool cache_info_passthrough;
d940ee9b 675};
c6dc6f63 676
9576de75 677static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 678 {
679 .name = "qemu64",
680 .level = 4,
99b88a17 681 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 682 .family = 6,
f8e6a11a 683 .model = 6,
c6dc6f63 684 .stepping = 3,
0514ef2f 685 .features[FEAT_1_EDX] =
27861ecc 686 PPRO_FEATURES |
c6dc6f63 687 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 688 CPUID_PSE36,
0514ef2f 689 .features[FEAT_1_ECX] =
27861ecc 690 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 691 .features[FEAT_8000_0001_EDX] =
27861ecc 692 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63 693 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 694 .features[FEAT_8000_0001_ECX] =
27861ecc 695 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 696 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
697 .xlevel = 0x8000000A,
c6dc6f63
AP		 698 },
699 {
700 .name = "phenom",
701 .level = 5,
99b88a17 702 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 703 .family = 16,
704 .model = 2,
705 .stepping = 3,
b9fc20bc 706 /* Missing: CPUID_HT */
0514ef2f 707 .features[FEAT_1_EDX] =
27861ecc 708 PPRO_FEATURES |
c6dc6f63 709 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 710 CPUID_PSE36 | CPUID_VME,
0514ef2f 711 .features[FEAT_1_ECX] =
27861ecc 712 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 713 CPUID_EXT_POPCNT,
0514ef2f 714 .features[FEAT_8000_0001_EDX] =
27861ecc 715 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 716 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
717 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 718 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 719 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
720 CPUID_EXT3_CR8LEG,
721 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
722 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 723 .features[FEAT_8000_0001_ECX] =
27861ecc 724 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 725 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 726 /* Missing: CPUID_SVM_LBRV */
0514ef2f 727 .features[FEAT_SVM] =
b9fc20bc 728 CPUID_SVM_NPT,
c6dc6f63
AP		 729 .xlevel = 0x8000001A,
730 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
731 },
732 {
733 .name = "core2duo",
734 .level = 10,
99b88a17 735 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 736 .family = 6,
737 .model = 15,
738 .stepping = 11,
b9fc20bc 739 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 740 .features[FEAT_1_EDX] =
27861ecc 741 PPRO_FEATURES |
c6dc6f63 742 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 743 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
744 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 745 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 746 .features[FEAT_1_ECX] =
27861ecc 747 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 748 CPUID_EXT_CX16,
0514ef2f 749 .features[FEAT_8000_0001_EDX] =
27861ecc 750 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 751 .features[FEAT_8000_0001_ECX] =
27861ecc 752 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 753 .xlevel = 0x80000008,
754 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
755 },
756 {
757 .name = "kvm64",
758 .level = 5,
99b88a17 759 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 760 .family = 15,
761 .model = 6,
762 .stepping = 1,
b3a4f0b1 763 /* Missing: CPUID_HT */
0514ef2f 764 .features[FEAT_1_EDX] =
b3a4f0b1 765 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 766 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
767 CPUID_PSE36,
768 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 769 .features[FEAT_1_ECX] =
27861ecc 770 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 771 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 772 .features[FEAT_8000_0001_EDX] =
27861ecc 773 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
c6dc6f63
AP		 774 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
775 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
776 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
777 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
778 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 779 .features[FEAT_8000_0001_ECX] =
27861ecc 780 0,
c6dc6f63
AP		 781 .xlevel = 0x80000008,
782 .model_id = "Common KVM processor"
783 },
c6dc6f63
AP		 784 {
785 .name = "qemu32",
786 .level = 4,
99b88a17 787 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 788 .family = 6,
f8e6a11a 789 .model = 6,
c6dc6f63 790 .stepping = 3,
0514ef2f 791 .features[FEAT_1_EDX] =
27861ecc 792 PPRO_FEATURES,
0514ef2f 793 .features[FEAT_1_ECX] =
27861ecc 794 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 795 .xlevel = 0x80000004,
c6dc6f63 796 },
eafaf1e5
AP		 797 {
798 .name = "kvm32",
799 .level = 5,
99b88a17 800 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 801 .family = 15,
802 .model = 6,
803 .stepping = 1,
0514ef2f 804 .features[FEAT_1_EDX] =
b3a4f0b1 805 PPRO_FEATURES | CPUID_VME |
eafaf1e5 806 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 807 .features[FEAT_1_ECX] =
27861ecc 808 CPUID_EXT_SSE3,
0514ef2f 809 .features[FEAT_8000_0001_EDX] =
27861ecc 810 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
0514ef2f 811 .features[FEAT_8000_0001_ECX] =
27861ecc 812 0,
eafaf1e5
AP		 813 .xlevel = 0x80000008,
814 .model_id = "Common 32-bit KVM processor"
815 },
c6dc6f63
AP		 816 {
817 .name = "coreduo",
818 .level = 10,
99b88a17 819 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 820 .family = 6,
821 .model = 14,
822 .stepping = 8,
b9fc20bc 823 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 824 .features[FEAT_1_EDX] =
27861ecc 825 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 826 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
827 CPUID_SS,
828 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 829 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 830 .features[FEAT_1_ECX] =
e93abc14 831 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 832 .features[FEAT_8000_0001_EDX] =
27861ecc 833 CPUID_EXT2_NX,
c6dc6f63
AP		 834 .xlevel = 0x80000008,
835 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
836 },
837 {
838 .name = "486",
58012d66 839 .level = 1,
99b88a17 840 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 841 .family = 4,
b2a856d9 842 .model = 8,
c6dc6f63 843 .stepping = 0,
0514ef2f 844 .features[FEAT_1_EDX] =
27861ecc 845 I486_FEATURES,
c6dc6f63
AP		 846 .xlevel = 0,
847 },
848 {
849 .name = "pentium",
850 .level = 1,
99b88a17 851 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 852 .family = 5,
853 .model = 4,
854 .stepping = 3,
0514ef2f 855 .features[FEAT_1_EDX] =
27861ecc 856 PENTIUM_FEATURES,
c6dc6f63
AP		 857 .xlevel = 0,
858 },
859 {
860 .name = "pentium2",
861 .level = 2,
99b88a17 862 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 863 .family = 6,
864 .model = 5,
865 .stepping = 2,
0514ef2f 866 .features[FEAT_1_EDX] =
27861ecc 867 PENTIUM2_FEATURES,
c6dc6f63
AP		 868 .xlevel = 0,
869 },
870 {
871 .name = "pentium3",
872 .level = 2,
99b88a17 873 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 874 .family = 6,
875 .model = 7,
876 .stepping = 3,
0514ef2f 877 .features[FEAT_1_EDX] =
27861ecc 878 PENTIUM3_FEATURES,
c6dc6f63
AP		 879 .xlevel = 0,
880 },
881 {
882 .name = "athlon",
883 .level = 2,
99b88a17 884 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 885 .family = 6,
886 .model = 2,
887 .stepping = 3,
0514ef2f 888 .features[FEAT_1_EDX] =
27861ecc 889 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 890 CPUID_MCA,
0514ef2f 891 .features[FEAT_8000_0001_EDX] =
27861ecc 892 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 893 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 894 .xlevel = 0x80000008,
c6dc6f63
AP		 895 },
896 {
897 .name = "n270",
898 /* original is on level 10 */
899 .level = 5,
99b88a17 900 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 901 .family = 6,
902 .model = 28,
903 .stepping = 2,
b9fc20bc 904 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 905 .features[FEAT_1_EDX] =
27861ecc 906 PPRO_FEATURES |
b9fc20bc
EH		 907 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
908 CPUID_ACPI | CPUID_SS,
c6dc6f63 909 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 910 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
911 * CPUID_EXT_XTPR */
0514ef2f 912 .features[FEAT_1_ECX] =
27861ecc 913 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 914 CPUID_EXT_MOVBE,
0514ef2f 915 .features[FEAT_8000_0001_EDX] =
27861ecc 916 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
60032ac0 917 CPUID_EXT2_NX,
0514ef2f 918 .features[FEAT_8000_0001_ECX] =
27861ecc 919 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 920 .xlevel = 0x8000000A,
921 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
922 },
3eca4642
EH		 923 {
924 .name = "Conroe",
6b11322e 925 .level = 4,
99b88a17 926 .vendor = CPUID_VENDOR_INTEL,
3eca4642 927 .family = 6,
ffce9ebb 928 .model = 15,
3eca4642 929 .stepping = 3,
0514ef2f 930 .features[FEAT_1_EDX] =
b3a4f0b1 931 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 932 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
933 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
934 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
935 CPUID_DE | CPUID_FP87,
0514ef2f 936 .features[FEAT_1_ECX] =
27861ecc 937 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 938 .features[FEAT_8000_0001_EDX] =
27861ecc 939 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 940 .features[FEAT_8000_0001_ECX] =
27861ecc 941 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 942 .xlevel = 0x8000000A,
943 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
944 },
945 {
946 .name = "Penryn",
6b11322e 947 .level = 4,
99b88a17 948 .vendor = CPUID_VENDOR_INTEL,
3eca4642 949 .family = 6,
ffce9ebb 950 .model = 23,
3eca4642 951 .stepping = 3,
0514ef2f 952 .features[FEAT_1_EDX] =
b3a4f0b1 953 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 954 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
955 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
956 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
957 CPUID_DE | CPUID_FP87,
0514ef2f 958 .features[FEAT_1_ECX] =
27861ecc 959 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 960 CPUID_EXT_SSE3,
0514ef2f 961 .features[FEAT_8000_0001_EDX] =
27861ecc 962 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 963 .features[FEAT_8000_0001_ECX] =
27861ecc 964 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 965 .xlevel = 0x8000000A,
966 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
967 },
968 {
969 .name = "Nehalem",
6b11322e 970 .level = 4,
99b88a17 971 .vendor = CPUID_VENDOR_INTEL,
3eca4642 972 .family = 6,
ffce9ebb 973 .model = 26,
3eca4642 974 .stepping = 3,
0514ef2f 975 .features[FEAT_1_EDX] =
b3a4f0b1 976 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 977 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
978 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
979 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
980 CPUID_DE | CPUID_FP87,
0514ef2f 981 .features[FEAT_1_ECX] =
27861ecc 982 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 983 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 984 .features[FEAT_8000_0001_EDX] =
27861ecc 985 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 986 .features[FEAT_8000_0001_ECX] =
27861ecc 987 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 988 .xlevel = 0x8000000A,
989 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
990 },
991 {
992 .name = "Westmere",
993 .level = 11,
99b88a17 994 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 995 .family = 6,
996 .model = 44,
997 .stepping = 1,
0514ef2f 998 .features[FEAT_1_EDX] =
b3a4f0b1 999 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1000 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1001 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1002 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1003 CPUID_DE | CPUID_FP87,
0514ef2f 1004 .features[FEAT_1_ECX] =
27861ecc 1005 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1006 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1007 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1008 .features[FEAT_8000_0001_EDX] =
27861ecc 1009 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1010 .features[FEAT_8000_0001_ECX] =
27861ecc 1011 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1012 .xlevel = 0x8000000A,
1013 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1014 },
1015 {
1016 .name = "SandyBridge",
1017 .level = 0xd,
99b88a17 1018 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1019 .family = 6,
1020 .model = 42,
1021 .stepping = 1,
0514ef2f 1022 .features[FEAT_1_EDX] =
b3a4f0b1 1023 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1024 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1025 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1026 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1027 CPUID_DE | CPUID_FP87,
0514ef2f 1028 .features[FEAT_1_ECX] =
27861ecc 1029 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1030 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1031 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1032 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1033 CPUID_EXT_SSE3,
0514ef2f 1034 .features[FEAT_8000_0001_EDX] =
27861ecc 1035 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1036 CPUID_EXT2_SYSCALL,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1039 .features[FEAT_XSAVE] =
1040 CPUID_XSAVE_XSAVEOPT,
3eca4642
EH		 1041 .xlevel = 0x8000000A,
1042 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1043 },
2f9ac42a
PB		 1044 {
1045 .name = "IvyBridge",
1046 .level = 0xd,
1047 .vendor = CPUID_VENDOR_INTEL,
1048 .family = 6,
1049 .model = 58,
1050 .stepping = 9,
1051 .features[FEAT_1_EDX] =
1052 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1053 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1054 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1055 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1056 CPUID_DE | CPUID_FP87,
1057 .features[FEAT_1_ECX] =
1058 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1059 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1060 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1061 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1062 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1063 .features[FEAT_7_0_EBX] =
1064 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1065 CPUID_7_0_EBX_ERMS,
1066 .features[FEAT_8000_0001_EDX] =
1067 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1068 CPUID_EXT2_SYSCALL,
1069 .features[FEAT_8000_0001_ECX] =
1070 CPUID_EXT3_LAHF_LM,
1071 .features[FEAT_XSAVE] =
1072 CPUID_XSAVE_XSAVEOPT,
1073 .xlevel = 0x8000000A,
1074 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1075 },
37507094
EH		 1076 {
1077 .name = "Haswell",
1078 .level = 0xd,
99b88a17 1079 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1080 .family = 6,
1081 .model = 60,
1082 .stepping = 1,
0514ef2f 1083 .features[FEAT_1_EDX] =
b3a4f0b1 1084 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1085 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1086 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1087 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1088 CPUID_DE | CPUID_FP87,
0514ef2f 1089 .features[FEAT_1_ECX] =
27861ecc 1090 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1091 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1092 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1093 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1094 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1095 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1096 .features[FEAT_8000_0001_EDX] =
27861ecc 1097 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1098 CPUID_EXT2_SYSCALL,
0514ef2f 1099 .features[FEAT_8000_0001_ECX] =
27861ecc 1100 CPUID_EXT3_LAHF_LM,
0514ef2f 1101 .features[FEAT_7_0_EBX] =
27861ecc 1102 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
13704e4c
EH		 1103 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1104 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
0bb0b2d2
PB		 1105 .features[FEAT_XSAVE] =
1106 CPUID_XSAVE_XSAVEOPT,
37507094
EH		 1107 .xlevel = 0x8000000A,
1108 .model_id = "Intel Core Processor (Haswell)",
1109 },
ece01354
EH		 1110 {
1111 .name = "Broadwell",
1112 .level = 0xd,
1113 .vendor = CPUID_VENDOR_INTEL,
1114 .family = 6,
1115 .model = 61,
1116 .stepping = 2,
1117 .features[FEAT_1_EDX] =
b3a4f0b1 1118 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1119 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1120 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1121 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1122 CPUID_DE | CPUID_FP87,
1123 .features[FEAT_1_ECX] =
1124 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1125 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1126 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1127 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1128 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1129 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1130 .features[FEAT_8000_0001_EDX] =
1131 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1132 CPUID_EXT2_SYSCALL,
1133 .features[FEAT_8000_0001_ECX] =
1134 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1135 .features[FEAT_7_0_EBX] =
1136 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
13704e4c 1137 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1138 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
13704e4c 1139 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1140 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1141 .features[FEAT_XSAVE] =
1142 CPUID_XSAVE_XSAVEOPT,
ece01354
EH		 1143 .xlevel = 0x8000000A,
1144 .model_id = "Intel Core Processor (Broadwell)",
1145 },
3eca4642
EH		 1146 {
1147 .name = "Opteron_G1",
1148 .level = 5,
99b88a17 1149 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1150 .family = 15,
1151 .model = 6,
1152 .stepping = 1,
0514ef2f 1153 .features[FEAT_1_EDX] =
b3a4f0b1 1154 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1155 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1156 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1157 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1158 CPUID_DE | CPUID_FP87,
0514ef2f 1159 .features[FEAT_1_ECX] =
27861ecc 1160 CPUID_EXT_SSE3,
0514ef2f 1161 .features[FEAT_8000_0001_EDX] =
27861ecc 1162 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1163 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1164 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1165 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1166 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1167 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1168 .xlevel = 0x80000008,
1169 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1170 },
1171 {
1172 .name = "Opteron_G2",
1173 .level = 5,
99b88a17 1174 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1175 .family = 15,
1176 .model = 6,
1177 .stepping = 1,
0514ef2f 1178 .features[FEAT_1_EDX] =
b3a4f0b1 1179 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1180 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1181 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1182 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1183 CPUID_DE | CPUID_FP87,
0514ef2f 1184 .features[FEAT_1_ECX] =
27861ecc 1185 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1186 .features[FEAT_8000_0001_EDX] =
27861ecc 1187 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1188 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1189 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1190 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1191 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1192 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1193 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1194 .features[FEAT_8000_0001_ECX] =
27861ecc 1195 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1196 .xlevel = 0x80000008,
1197 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1198 },
1199 {
1200 .name = "Opteron_G3",
1201 .level = 5,
99b88a17 1202 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1203 .family = 15,
1204 .model = 6,
1205 .stepping = 1,
0514ef2f 1206 .features[FEAT_1_EDX] =
b3a4f0b1 1207 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1208 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1209 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1210 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1211 CPUID_DE | CPUID_FP87,
0514ef2f 1212 .features[FEAT_1_ECX] =
27861ecc 1213 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1214 CPUID_EXT_SSE3,
0514ef2f 1215 .features[FEAT_8000_0001_EDX] =
27861ecc 1216 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1217 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1218 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1219 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1220 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1221 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1222 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1223 .features[FEAT_8000_0001_ECX] =
27861ecc 1224 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1225 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1226 .xlevel = 0x80000008,
1227 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1228 },
1229 {
1230 .name = "Opteron_G4",
1231 .level = 0xd,
99b88a17 1232 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1233 .family = 21,
1234 .model = 1,
1235 .stepping = 2,
0514ef2f 1236 .features[FEAT_1_EDX] =
b3a4f0b1 1237 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1238 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1239 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1240 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1241 CPUID_DE | CPUID_FP87,
0514ef2f 1242 .features[FEAT_1_ECX] =
27861ecc 1243 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1244 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1245 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1246 CPUID_EXT_SSE3,
0514ef2f 1247 .features[FEAT_8000_0001_EDX] =
27861ecc 1248 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1249 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1250 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1251 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1252 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1253 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1254 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1255 .features[FEAT_8000_0001_ECX] =
27861ecc 1256 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1257 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1258 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1259 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1260 /* no xsaveopt! */
3eca4642
EH		 1261 .xlevel = 0x8000001A,
1262 .model_id = "AMD Opteron 62xx class CPU",
1263 },
021941b9
AP		 1264 {
1265 .name = "Opteron_G5",
1266 .level = 0xd,
99b88a17 1267 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1268 .family = 21,
1269 .model = 2,
1270 .stepping = 0,
0514ef2f 1271 .features[FEAT_1_EDX] =
b3a4f0b1 1272 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1273 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1274 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1275 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1276 CPUID_DE | CPUID_FP87,
0514ef2f 1277 .features[FEAT_1_ECX] =
27861ecc 1278 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1279 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1280 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1281 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1282 .features[FEAT_8000_0001_EDX] =
27861ecc 1283 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1284 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1285 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1286 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1287 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1288 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1289 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1290 .features[FEAT_8000_0001_ECX] =
27861ecc 1291 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1292 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1293 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1294 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1295 /* no xsaveopt! */
021941b9
AP		 1296 .xlevel = 0x8000001A,
1297 .model_id = "AMD Opteron 63xx class CPU",
1298 },
c6dc6f63
AP		 1299};
1300
0668af54
EH		 1301/**
1302 * x86_cpu_compat_set_features:
1303 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1304 * @w: Identifies the feature word to be changed.
1305 * @feat_add: Feature bits to be added to feature word
1306 * @feat_remove: Feature bits to be removed from feature word
1307 *
1308 * Change CPU model feature bits for compatibility.
1309 *
1310 * This function may be used by machine-type compatibility functions
1311 * to enable or disable feature bits on specific CPU models.
1312 */
1313void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1314 uint32_t feat_add, uint32_t feat_remove)
1315{
9576de75 1316 X86CPUDefinition *def;
0668af54
EH		 1317 int i;
1318 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1319 def = &builtin_x86_defs[i];
1320 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1321 def->features[w] |= feat_add;
1322 def->features[w] &= ~feat_remove;
1323 }
1324 }
1325}
1326
4d1b279b
EH		 1327static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1328 bool migratable_only);
1329
d940ee9b
EH		 1330#ifdef CONFIG_KVM
1331
c6dc6f63
AP		 1332static int cpu_x86_fill_model_id(char *str)
1333{
1334 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1335 int i;
1336
1337 for (i = 0; i < 3; i++) {
1338 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1339 memcpy(str + i * 16 + 0, &eax, 4);
1340 memcpy(str + i * 16 + 4, &ebx, 4);
1341 memcpy(str + i * 16 + 8, &ecx, 4);
1342 memcpy(str + i * 16 + 12, &edx, 4);
1343 }
1344 return 0;
1345}
1346
d940ee9b
EH		 1347static X86CPUDefinition host_cpudef;
1348
84f1b92f 1349static Property host_x86_cpu_properties[] = {
120eee7d 1350 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1351 DEFINE_PROP_END_OF_LIST()
1352};
1353
d940ee9b 1354/* class_init for the "host" CPU model
6e746f30 1355 *
d940ee9b 1356 * This function may be called before KVM is initialized.
6e746f30 1357 */
d940ee9b 1358static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1359{
84f1b92f 1360 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1361 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1362 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1363
d940ee9b 1364 xcc->kvm_required = true;
6e746f30 1365
c6dc6f63 1366 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1367 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1368
1369 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1370 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1371 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1372 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1373
d940ee9b 1374 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1375
d940ee9b
EH		 1376 xcc->cpu_def = &host_cpudef;
1377 host_cpudef.cache_info_passthrough = true;
1378
1379 /* level, xlevel, xlevel2, and the feature words are initialized on
1380 * instance_init, because they require KVM to be initialized.
1381 */
84f1b92f
EH		 1382
1383 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1384}
1385
1386static void host_x86_cpu_initfn(Object *obj)
1387{
1388 X86CPU *cpu = X86_CPU(obj);
1389 CPUX86State *env = &cpu->env;
1390 KVMState *s = kvm_state;
d940ee9b
EH		 1391
1392 assert(kvm_enabled());
1393
4d1b279b
EH		 1394 /* We can't fill the features array here because we don't know yet if
1395 * "migratable" is true or false.
1396 */
1397 cpu->host_features = true;
1398
d940ee9b
EH		 1399 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1400 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1401 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1402
d940ee9b 1403 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1404}
1405
d940ee9b
EH		 1406static const TypeInfo host_x86_cpu_type_info = {
1407 .name = X86_CPU_TYPE_NAME("host"),
1408 .parent = TYPE_X86_CPU,
1409 .instance_init = host_x86_cpu_initfn,
1410 .class_init = host_x86_cpu_class_init,
1411};
1412
1413#endif
1414
8459e396 1415static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1416{
8459e396 1417 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1418 int i;
1419
857aee33 1420 for (i = 0; i < 32; ++i) {
c6dc6f63 1421 if (1 << i & mask) {
bffd67b0 1422 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1423 assert(reg);
fefb41bf 1424 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1425 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1426 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1427 f->cpuid_eax, reg,
1428 f->feat_names[i] ? "." : "",
1429 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1430 }
857aee33 1431 }
c6dc6f63
AP		 1432}
1433
95b8519d
AF		 1434static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1435 const char *name, Error **errp)
1436{
1437 X86CPU *cpu = X86_CPU(obj);
1438 CPUX86State *env = &cpu->env;
1439 int64_t value;
1440
1441 value = (env->cpuid_version >> 8) & 0xf;
1442 if (value == 0xf) {
1443 value += (env->cpuid_version >> 20) & 0xff;
1444 }
1445 visit_type_int(v, &value, name, errp);
1446}
1447
71ad61d3
AF		 1448static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1449 const char *name, Error **errp)
ed5e1ec3 1450{
71ad61d3
AF		 1451 X86CPU *cpu = X86_CPU(obj);
1452 CPUX86State *env = &cpu->env;
1453 const int64_t min = 0;
1454 const int64_t max = 0xff + 0xf;
65cd9064 1455 Error *local_err = NULL;
71ad61d3
AF		 1456 int64_t value;
1457
65cd9064
MA		 1458 visit_type_int(v, &value, name, &local_err);
1459 if (local_err) {
1460 error_propagate(errp, local_err);
71ad61d3
AF		 1461 return;
1462 }
1463 if (value < min || value > max) {
1464 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1465 name ? name : "null", value, min, max);
1466 return;
1467 }
1468
ed5e1ec3 1469 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1470 if (value > 0x0f) {
1471 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1472 } else {
71ad61d3 1473 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1474 }
1475}
1476
67e30c83
AF		 1477static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1478 const char *name, Error **errp)
1479{
1480 X86CPU *cpu = X86_CPU(obj);
1481 CPUX86State *env = &cpu->env;
1482 int64_t value;
1483
1484 value = (env->cpuid_version >> 4) & 0xf;
1485 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1486 visit_type_int(v, &value, name, errp);
1487}
1488
c5291a4f
AF		 1489static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1490 const char *name, Error **errp)
b0704cbd 1491{
c5291a4f
AF		 1492 X86CPU *cpu = X86_CPU(obj);
1493 CPUX86State *env = &cpu->env;
1494 const int64_t min = 0;
1495 const int64_t max = 0xff;
65cd9064 1496 Error *local_err = NULL;
c5291a4f
AF		 1497 int64_t value;
1498
65cd9064
MA		 1499 visit_type_int(v, &value, name, &local_err);
1500 if (local_err) {
1501 error_propagate(errp, local_err);
c5291a4f
AF		 1502 return;
1503 }
1504 if (value < min || value > max) {
1505 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1506 name ? name : "null", value, min, max);
1507 return;
1508 }
1509
b0704cbd 1510 env->cpuid_version &= ~0xf00f0;
c5291a4f 1511 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1512}
1513
35112e41
AF		 1514static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1515 void *opaque, const char *name,
1516 Error **errp)
1517{
1518 X86CPU *cpu = X86_CPU(obj);
1519 CPUX86State *env = &cpu->env;
1520 int64_t value;
1521
1522 value = env->cpuid_version & 0xf;
1523 visit_type_int(v, &value, name, errp);
1524}
1525
036e2222
AF		 1526static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1527 void *opaque, const char *name,
1528 Error **errp)
38c3dc46 1529{
036e2222
AF		 1530 X86CPU *cpu = X86_CPU(obj);
1531 CPUX86State *env = &cpu->env;
1532 const int64_t min = 0;
1533 const int64_t max = 0xf;
65cd9064 1534 Error *local_err = NULL;
036e2222
AF		 1535 int64_t value;
1536
65cd9064
MA		 1537 visit_type_int(v, &value, name, &local_err);
1538 if (local_err) {
1539 error_propagate(errp, local_err);
036e2222
AF		 1540 return;
1541 }
1542 if (value < min || value > max) {
1543 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1544 name ? name : "null", value, min, max);
1545 return;
1546 }
1547
38c3dc46 1548 env->cpuid_version &= ~0xf;
036e2222 1549 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1550}
1551
8e1898bf
AF		 1552static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1553 const char *name, Error **errp)
1554{
1555 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1556
fa029887 1557 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1558}
1559
1560static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1561 const char *name, Error **errp)
1562{
1563 X86CPU *cpu = X86_CPU(obj);
8e1898bf 1564
fa029887 1565 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 1566}
1567
16b93aa8
AF		 1568static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1569 const char *name, Error **errp)
1570{
1571 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1572
fa029887 1573 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1574}
1575
1576static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1577 const char *name, Error **errp)
1578{
1579 X86CPU *cpu = X86_CPU(obj);
16b93aa8 1580
fa029887 1581 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 1582}
1583
d480e1af
AF		 1584static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1585{
1586 X86CPU *cpu = X86_CPU(obj);
1587 CPUX86State *env = &cpu->env;
1588 char *value;
d480e1af 1589
e42a92ae 1590 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1591 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1592 env->cpuid_vendor3);
d480e1af
AF		 1593 return value;
1594}
1595
1596static void x86_cpuid_set_vendor(Object *obj, const char *value,
1597 Error **errp)
1598{
1599 X86CPU *cpu = X86_CPU(obj);
1600 CPUX86State *env = &cpu->env;
1601 int i;
1602
9df694ee 1603 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1604 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1605 "vendor", value);
1606 return;
1607 }
1608
1609 env->cpuid_vendor1 = 0;
1610 env->cpuid_vendor2 = 0;
1611 env->cpuid_vendor3 = 0;
1612 for (i = 0; i < 4; i++) {
1613 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1614 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1615 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1616 }
d480e1af
AF		 1617}
1618
63e886eb
AF		 1619static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1620{
1621 X86CPU *cpu = X86_CPU(obj);
1622 CPUX86State *env = &cpu->env;
1623 char *value;
1624 int i;
1625
1626 value = g_malloc(48 + 1);
1627 for (i = 0; i < 48; i++) {
1628 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1629 }
1630 value[48] = '\0';
1631 return value;
1632}
1633
938d4c25
AF		 1634static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1635 Error **errp)
dcce6675 1636{
938d4c25
AF		 1637 X86CPU *cpu = X86_CPU(obj);
1638 CPUX86State *env = &cpu->env;
dcce6675
AF		 1639 int c, len, i;
1640
1641 if (model_id == NULL) {
1642 model_id = "";
1643 }
1644 len = strlen(model_id);
d0a6acf4 1645 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1646 for (i = 0; i < 48; i++) {
1647 if (i >= len) {
1648 c = '\0';
1649 } else {
1650 c = (uint8_t)model_id[i];
1651 }
1652 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1653 }
1654}
1655
89e48965
AF		 1656static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1657 const char *name, Error **errp)
1658{
1659 X86CPU *cpu = X86_CPU(obj);
1660 int64_t value;
1661
1662 value = cpu->env.tsc_khz * 1000;
1663 visit_type_int(v, &value, name, errp);
1664}
1665
1666static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1667 const char *name, Error **errp)
1668{
1669 X86CPU *cpu = X86_CPU(obj);
1670 const int64_t min = 0;
2e84849a 1671 const int64_t max = INT64_MAX;
65cd9064 1672 Error *local_err = NULL;
89e48965
AF		 1673 int64_t value;
1674
65cd9064
MA		 1675 visit_type_int(v, &value, name, &local_err);
1676 if (local_err) {
1677 error_propagate(errp, local_err);
89e48965
AF		 1678 return;
1679 }
1680 if (value < min || value > max) {
1681 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1682 name ? name : "null", value, min, max);
1683 return;
1684 }
1685
1686 cpu->env.tsc_khz = value / 1000;
1687}
1688
31050930
IM		 1689static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1690 const char *name, Error **errp)
1691{
1692 X86CPU *cpu = X86_CPU(obj);
0856579c 1693 int64_t value = cpu->env.cpuid_apic_id;
31050930
IM		 1694
1695 visit_type_int(v, &value, name, errp);
1696}
1697
1698static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1699 const char *name, Error **errp)
1700{
1701 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1702 DeviceState *dev = DEVICE(obj);
31050930
IM		 1703 const int64_t min = 0;
1704 const int64_t max = UINT32_MAX;
1705 Error *error = NULL;
1706 int64_t value;
1707
8d6d4980
IM		 1708 if (dev->realized) {
1709 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1710 "it was realized", name, object_get_typename(obj));
1711 return;
1712 }
1713
31050930
IM		 1714 visit_type_int(v, &value, name, &error);
1715 if (error) {
1716 error_propagate(errp, error);
1717 return;
1718 }
1719 if (value < min || value > max) {
1720 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1721 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1722 object_get_typename(obj), name, value, min, max);
1723 return;
1724 }
1725
0856579c 1726 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
31050930
IM		 1727 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1728 return;
1729 }
0856579c 1730 cpu->env.cpuid_apic_id = value;
31050930
IM		 1731}
1732
7e5292b5 1733/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1734static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1735 const char *name, Error **errp)
1736{
7e5292b5 1737 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1738 FeatureWord w;
1739 Error *err = NULL;
1740 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1741 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1742 X86CPUFeatureWordInfoList *list = NULL;
1743
1744 for (w = 0; w < FEATURE_WORDS; w++) {
1745 FeatureWordInfo *wi = &feature_word_info[w];
1746 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1747 qwi->cpuid_input_eax = wi->cpuid_eax;
1748 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1749 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1750 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1751 qwi->features = array[w];
8e8aba50
EH		 1752
1753 /* List will be in reverse order, but order shouldn't matter */
1754 list_entries[w].next = list;
1755 list_entries[w].value = &word_infos[w];
1756 list = &list_entries[w];
1757 }
1758
1759 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1760 error_propagate(errp, err);
1761}
1762
c8f0f88e
IM		 1763static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1764 const char *name, Error **errp)
1765{
1766 X86CPU *cpu = X86_CPU(obj);
1767 int64_t value = cpu->hyperv_spinlock_attempts;
1768
1769 visit_type_int(v, &value, name, errp);
1770}
1771
1772static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1773 const char *name, Error **errp)
1774{
1775 const int64_t min = 0xFFF;
1776 const int64_t max = UINT_MAX;
1777 X86CPU *cpu = X86_CPU(obj);
1778 Error *err = NULL;
1779 int64_t value;
1780
1781 visit_type_int(v, &value, name, &err);
1782 if (err) {
1783 error_propagate(errp, err);
1784 return;
1785 }
1786
1787 if (value < min || value > max) {
1788 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1789 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1790 object_get_typename(obj), name ? name : "null",
1791 value, min, max);
c8f0f88e
IM		 1792 return;
1793 }
1794 cpu->hyperv_spinlock_attempts = value;
1795}
1796
1797static PropertyInfo qdev_prop_spinlocks = {
1798 .name = "int",
1799 .get = x86_get_hv_spinlocks,
1800 .set = x86_set_hv_spinlocks,
1801};
1802
72ac2e87
IM		 1803/* Convert all '_' in a feature string option name to '-', to make feature
1804 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1805 */
1806static inline void feat2prop(char *s)
1807{
1808 while ((s = strchr(s, '_'))) {
1809 *s = '-';
1810 }
1811}
1812
8f961357
EH		 1813/* Parse "+feature,-feature,feature=foo" CPU feature string
1814 */
94a444b2
AF		 1815static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1816 Error **errp)
8f961357 1817{
94a444b2 1818 X86CPU *cpu = X86_CPU(cs);
8f961357 1819 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1820 FeatureWord w;
8f961357 1821 /* Features to be added */
077c68c3 1822 FeatureWordArray plus_features = { 0 };
8f961357 1823 /* Features to be removed */
5ef57876 1824 FeatureWordArray minus_features = { 0 };
8f961357 1825 uint32_t numvalue;
a91987c2 1826 CPUX86State *env = &cpu->env;
94a444b2 1827 Error *local_err = NULL;
8f961357 1828
8f961357 1829 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1830
1831 while (featurestr) {
1832 char *val;
1833 if (featurestr[0] == '+') {
c00c94ab 1834 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1835 } else if (featurestr[0] == '-') {
c00c94ab 1836 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1837 } else if ((val = strchr(featurestr, '='))) {
1838 *val = 0; val++;
72ac2e87 1839 feat2prop(featurestr);
d024d209 1840 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1841 char *err;
a91987c2
IM		 1842 char num[32];
1843
c6dc6f63
AP		 1844 numvalue = strtoul(val, &err, 0);
1845 if (!*val || *err) {
6b1dd54b
PB		 1846 error_setg(errp, "bad numerical value %s", val);
1847 return;
c6dc6f63
AP		 1848 }
1849 if (numvalue < 0x80000000) {
94a444b2
AF		 1850 error_report("xlevel value shall always be >= 0x80000000"
1851 ", fixup will be removed in future versions");
2f7a21c4 1852 numvalue += 0x80000000;
c6dc6f63 1853 }
a91987c2 1854 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1855 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1856 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1857 int64_t tsc_freq;
1858 char *err;
a91987c2 1859 char num[32];
b862d1fe
JR		 1860
1861 tsc_freq = strtosz_suffix_unit(val, &err,
1862 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1863 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1864 error_setg(errp, "bad numerical value %s", val);
1865 return;
b862d1fe 1866 }
a91987c2 1867 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1868 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1869 &local_err);
72ac2e87 1870 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1871 char *err;
92067bf4 1872 const int min = 0xFFF;
c8f0f88e 1873 char num[32];
28f52cc0
VR		 1874 numvalue = strtoul(val, &err, 0);
1875 if (!*val || *err) {
6b1dd54b
PB		 1876 error_setg(errp, "bad numerical value %s", val);
1877 return;
28f52cc0 1878 }
92067bf4 1879 if (numvalue < min) {
94a444b2 1880 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1881 ", fixup will be removed in future versions",
1882 min);
92067bf4
IM		 1883 numvalue = min;
1884 }
c8f0f88e 1885 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1886 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1887 } else {
94a444b2 1888 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1889 }
c6dc6f63 1890 } else {
258f5abe 1891 feat2prop(featurestr);
94a444b2 1892 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1893 }
94a444b2
AF		 1894 if (local_err) {
1895 error_propagate(errp, local_err);
6b1dd54b 1896 return;
c6dc6f63
AP		 1897 }
1898 featurestr = strtok(NULL, ",");
1899 }
e1c224b4 1900
4d1b279b
EH		 1901 if (cpu->host_features) {
1902 for (w = 0; w < FEATURE_WORDS; w++) {
1903 env->features[w] =
1904 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1905 }
1906 }
1907
e1c224b4
EH		 1908 for (w = 0; w < FEATURE_WORDS; w++) {
1909 env->features[w] |= plus_features[w];
1910 env->features[w] &= ~minus_features[w];
1911 }
c6dc6f63
AP		 1912}
1913
8c3329e5 1914/* Print all cpuid feature names in featureset
c6dc6f63 1915 */
8c3329e5 1916static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1917{
8c3329e5
EH		 1918 int bit;
1919 bool first = true;
1920
1921 for (bit = 0; bit < 32; bit++) {
1922 if (featureset[bit]) {
1923 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1924 first = false;
c6dc6f63 1925 }
8c3329e5 1926 }
c6dc6f63
AP		 1927}
1928
e916cbf8
PM		 1929/* generate CPU information. */
1930void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1931{
9576de75 1932 X86CPUDefinition *def;
c6dc6f63 1933 char buf[256];
7fc9b714 1934 int i;
c6dc6f63 1935
7fc9b714
AF		 1936 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1937 def = &builtin_x86_defs[i];
c04321b3 1938 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1939 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1940 }
21ad7789
JK		 1941#ifdef CONFIG_KVM
1942 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1943 "KVM processor with all supported host features "
1944 "(only available in KVM mode)");
1945#endif
1946
6cdf8854 1947 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1948 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1949 FeatureWordInfo *fw = &feature_word_info[i];
1950
8c3329e5
EH		 1951 (*cpu_fprintf)(f, " ");
1952 listflags(f, cpu_fprintf, fw->feat_names);
1953 (*cpu_fprintf)(f, "\n");
3af60be2 1954 }
c6dc6f63
AP		 1955}
1956
76b64a7a 1957CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1958{
1959 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1960 X86CPUDefinition *def;
7fc9b714 1961 int i;
e3966126 1962
7fc9b714 1963 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1964 CpuDefinitionInfoList *entry;
1965 CpuDefinitionInfo *info;
1966
7fc9b714 1967 def = &builtin_x86_defs[i];
e3966126
AL		 1968 info = g_malloc0(sizeof(*info));
1969 info->name = g_strdup(def->name);
1970
1971 entry = g_malloc0(sizeof(*entry));
1972 entry->value = info;
1973 entry->next = cpu_list;
1974 cpu_list = entry;
1975 }
1976
1977 return cpu_list;
1978}
1979
84f1b92f
EH		 1980static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1981 bool migratable_only)
27418adf
EH		 1982{
1983 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 1984 uint32_t r;
27418adf 1985
fefb41bf 1986 if (kvm_enabled()) {
84f1b92f
EH		 1987 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1988 wi->cpuid_ecx,
1989 wi->cpuid_reg);
fefb41bf 1990 } else if (tcg_enabled()) {
84f1b92f 1991 r = wi->tcg_features;
fefb41bf
EH		 1992 } else {
1993 return ~0;
1994 }
84f1b92f
EH		 1995 if (migratable_only) {
1996 r &= x86_cpu_get_migratable_flags(w);
1997 }
1998 return r;
27418adf
EH		 1999}
2000
51f63aed
EH		 2001/*
2002 * Filters CPU feature words based on host availability of each feature.
2003 *
51f63aed
EH		 2004 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2005 */
27418adf 2006static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2007{
2008 CPUX86State *env = &cpu->env;
bd87d2a2 2009 FeatureWord w;
51f63aed
EH		 2010 int rv = 0;
2011
bd87d2a2 2012 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2013 uint32_t host_feat =
2014 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2015 uint32_t requested_features = env->features[w];
2016 env->features[w] &= host_feat;
2017 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2018 if (cpu->filtered_features[w]) {
2019 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2020 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2021 }
2022 rv = 1;
2023 }
bd87d2a2 2024 }
51f63aed
EH		 2025
2026 return rv;
bc74b7db 2027}
bc74b7db 2028
d940ee9b 2029/* Load data from X86CPUDefinition
c080e30e 2030 */
d940ee9b 2031static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2032{
61dcd775 2033 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2034 const char *vendor;
2035 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2036 FeatureWord w;
c6dc6f63 2037
2d64255b
AF		 2038 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2039 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2040 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2041 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2042 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
b3baa152 2043 env->cpuid_xlevel2 = def->xlevel2;
787aaf57 2044 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2045 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2046 for (w = 0; w < FEATURE_WORDS; w++) {
2047 env->features[w] = def->features[w];
2048 }
82beb536 2049
9576de75 2050 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2051 if (kvm_enabled()) {
5fcca9ff
EH		 2052 FeatureWord w;
2053 for (w = 0; w < FEATURE_WORDS; w++) {
2054 env->features[w] |= kvm_default_features[w];
136a7e9a 2055 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2056 }
82beb536 2057 }
5fcca9ff 2058
82beb536 2059 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2060
2061 /* sysenter isn't supported in compatibility mode on AMD,
2062 * syscall isn't supported in compatibility mode on Intel.
2063 * Normally we advertise the actual CPU vendor, but you can
2064 * override this using the 'vendor' property if you want to use
2065 * KVM's sysenter/syscall emulation in compatibility mode and
2066 * when doing cross vendor migration
2067 */
74f54bc4 2068 vendor = def->vendor;
7c08db30
EH		 2069 if (kvm_enabled()) {
2070 uint32_t ebx = 0, ecx = 0, edx = 0;
2071 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2072 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2073 vendor = host_vendor;
2074 }
2075
2076 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2077
c6dc6f63
AP		 2078}
2079
62fc403f
IM		 2080X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
2081 Error **errp)
5c3c6a68 2082{
2d64255b 2083 X86CPU *cpu = NULL;
d940ee9b 2084 X86CPUClass *xcc;
500050d1 2085 ObjectClass *oc;
2d64255b
AF		 2086 gchar **model_pieces;
2087 char *name, *features;
5c3c6a68
AF		 2088 Error *error = NULL;
2089
2d64255b
AF		 2090 model_pieces = g_strsplit(cpu_model, ",", 2);
2091 if (!model_pieces[0]) {
2092 error_setg(&error, "Invalid/empty CPU model name");
2093 goto out;
2094 }
2095 name = model_pieces[0];
2096 features = model_pieces[1];
2097
500050d1
AF		 2098 oc = x86_cpu_class_by_name(name);
2099 if (oc == NULL) {
2100 error_setg(&error, "Unable to find CPU definition: %s", name);
2101 goto out;
2102 }
d940ee9b
EH		 2103 xcc = X86_CPU_CLASS(oc);
2104
2105 if (xcc->kvm_required && !kvm_enabled()) {
2106 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2107 goto out;
2108 }
2109
d940ee9b
EH		 2110 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2111
62fc403f
IM		 2112#ifndef CONFIG_USER_ONLY
2113 if (icc_bridge == NULL) {
2114 error_setg(&error, "Invalid icc-bridge value");
2115 goto out;
2116 }
2117 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2118 object_unref(OBJECT(cpu));
2119#endif
5c3c6a68 2120
94a444b2 2121 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2122 if (error) {
2123 goto out;
5c3c6a68
AF		 2124 }
2125
7f833247 2126out:
cd7b87ff
AF		 2127 if (error != NULL) {
2128 error_propagate(errp, error);
500050d1
AF		 2129 if (cpu) {
2130 object_unref(OBJECT(cpu));
2131 cpu = NULL;
2132 }
cd7b87ff 2133 }
7f833247
IM		 2134 g_strfreev(model_pieces);
2135 return cpu;
2136}
2137
0856579c 2138X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2139{
2140 Error *error = NULL;
2141 X86CPU *cpu;
2142
62fc403f 2143 cpu = cpu_x86_create(cpu_model, NULL, &error);
5c3c6a68 2144 if (error) {
0856579c 2145 goto out;
9c235e83 2146 }
7f833247 2147
7f833247 2148 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2149
0856579c
PM		 2150out:
2151 if (error) {
2152 error_report_err(error);
2153 if (cpu != NULL) {
2154 object_unref(OBJECT(cpu));
2155 cpu = NULL;
2156 }
18b0e4e7 2157 }
0856579c 2158 return cpu;
5c3c6a68
AF		 2159}
2160
d940ee9b
EH		 2161static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2162{
2163 X86CPUDefinition *cpudef = data;
2164 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2165
2166 xcc->cpu_def = cpudef;
2167}
2168
2169static void x86_register_cpudef_type(X86CPUDefinition *def)
2170{
2171 char *typename = x86_cpu_type_name(def->name);
2172 TypeInfo ti = {
2173 .name = typename,
2174 .parent = TYPE_X86_CPU,
2175 .class_init = x86_cpu_cpudef_class_init,
2176 .class_data = def,
2177 };
2178
2179 type_register(&ti);
2180 g_free(typename);
2181}
2182
c6dc6f63 2183#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2184
0e26b7b8
BS		 2185void cpu_clear_apic_feature(CPUX86State *env)
2186{
0514ef2f 2187 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2188}
2189
c6dc6f63
AP		 2190#endif /* !CONFIG_USER_ONLY */
2191
c04321b3 2192/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2193 */
2194void x86_cpudef_setup(void)
2195{
93bfef4c
CV		 2196 int i, j;
2197 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2198
2199 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2200 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2201
2202 /* Look for specific "cpudef" models that */
09faecf2 2203 /* have the QEMU version in .model_id */
93bfef4c 2204 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2205 if (strcmp(model_with_versions[j], def->name) == 0) {
2206 pstrcpy(def->model_id, sizeof(def->model_id),
2207 "QEMU Virtual CPU version ");
2208 pstrcat(def->model_id, sizeof(def->model_id),
2209 qemu_get_version());
93bfef4c
CV		 2210 break;
2211 }
2212 }
c6dc6f63 2213 }
c6dc6f63
AP		 2214}
2215
0856579c
PM		 2216static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2217 uint32_t *ecx, uint32_t *edx)
2218{
2219 *ebx = env->cpuid_vendor1;
2220 *edx = env->cpuid_vendor2;
2221 *ecx = env->cpuid_vendor3;
2222}
2223
c6dc6f63
AP		 2224void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2225 uint32_t *eax, uint32_t *ebx,
2226 uint32_t *ecx, uint32_t *edx)
2227{
a60f24b5
AF		 2228 X86CPU *cpu = x86_env_get_cpu(env);
2229 CPUState *cs = CPU(cpu);
2230
c6dc6f63
AP		 2231 /* test if maximum index reached */
2232 if (index & 0x80000000) {
b3baa152
BW		 2233 if (index > env->cpuid_xlevel) {
2234 if (env->cpuid_xlevel2 > 0) {
2235 /* Handle the Centaur's CPUID instruction. */
2236 if (index > env->cpuid_xlevel2) {
2237 index = env->cpuid_xlevel2;
2238 } else if (index < 0xC0000000) {
2239 index = env->cpuid_xlevel;
2240 }
2241 } else {
57f26ae7
EH		 2242 /* Intel documentation states that invalid EAX input will
2243 * return the same information as EAX=cpuid_level
2244 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2245 */
2246 index = env->cpuid_level;
b3baa152
BW		 2247 }
2248 }
c6dc6f63
AP		 2249 } else {
2250 if (index > env->cpuid_level)
2251 index = env->cpuid_level;
2252 }
2253
2254 switch(index) {
2255 case 0:
2256 *eax = env->cpuid_level;
0856579c 2257 get_cpuid_vendor(env, ebx, ecx, edx);
c6dc6f63
AP		 2258 break;
2259 case 1:
2260 *eax = env->cpuid_version;
0856579c 2261 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2262 *ecx = env->features[FEAT_1_ECX];
2263 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2264 if (cs->nr_cores * cs->nr_threads > 1) {
2265 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2266 *edx |= 1 << 28; /* HTT bit */
2267 }
2268 break;
2269 case 2:
2270 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2271 if (cpu->cache_info_passthrough) {
2272 host_cpuid(index, 0, eax, ebx, ecx, edx);
2273 break;
2274 }
5e891bf8 2275 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2276 *ebx = 0;
2277 *ecx = 0;
5e891bf8
EH		 2278 *edx = (L1D_DESCRIPTOR << 16) | \
2279 (L1I_DESCRIPTOR << 8) | \
2280 (L2_DESCRIPTOR);
c6dc6f63
AP		 2281 break;
2282 case 4:
2283 /* cache info: needed for Core compatibility */
787aaf57
BC		 2284 if (cpu->cache_info_passthrough) {
2285 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2286 *eax &= ~0xFC000000;
c6dc6f63 2287 } else {
2f7a21c4 2288 *eax = 0;
76c2975a 2289 switch (count) {
c6dc6f63 2290 case 0: /* L1 dcache info */
5e891bf8
EH		 2291 *eax |= CPUID_4_TYPE_DCACHE | \
2292 CPUID_4_LEVEL(1) | \
2293 CPUID_4_SELF_INIT_LEVEL;
2294 *ebx = (L1D_LINE_SIZE - 1) | \
2295 ((L1D_PARTITIONS - 1) << 12) | \
2296 ((L1D_ASSOCIATIVITY - 1) << 22);
2297 *ecx = L1D_SETS - 1;
2298 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2299 break;
2300 case 1: /* L1 icache info */
5e891bf8
EH		 2301 *eax |= CPUID_4_TYPE_ICACHE | \
2302 CPUID_4_LEVEL(1) | \
2303 CPUID_4_SELF_INIT_LEVEL;
2304 *ebx = (L1I_LINE_SIZE - 1) | \
2305 ((L1I_PARTITIONS - 1) << 12) | \
2306 ((L1I_ASSOCIATIVITY - 1) << 22);
2307 *ecx = L1I_SETS - 1;
2308 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2309 break;
2310 case 2: /* L2 cache info */
5e891bf8
EH		 2311 *eax |= CPUID_4_TYPE_UNIFIED | \
2312 CPUID_4_LEVEL(2) | \
2313 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2314 if (cs->nr_threads > 1) {
2315 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2316 }
5e891bf8
EH		 2317 *ebx = (L2_LINE_SIZE - 1) | \
2318 ((L2_PARTITIONS - 1) << 12) | \
2319 ((L2_ASSOCIATIVITY - 1) << 22);
2320 *ecx = L2_SETS - 1;
2321 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2322 break;
2323 default: /* end of info */
2324 *eax = 0;
2325 *ebx = 0;
2326 *ecx = 0;
2327 *edx = 0;
2328 break;
76c2975a
PB		 2329 }
2330 }
2331
2332 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2333 if ((*eax & 31) && cs->nr_cores > 1) {
2334 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2335 }
2336 break;
2337 case 5:
2338 /* mwait info: needed for Core compatibility */
2339 *eax = 0; /* Smallest monitor-line size in bytes */
2340 *ebx = 0; /* Largest monitor-line size in bytes */
2341 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2342 *edx = 0;
2343 break;
2344 case 6:
2345 /* Thermal and Power Leaf */
2346 *eax = 0;
2347 *ebx = 0;
2348 *ecx = 0;
2349 *edx = 0;
2350 break;
f7911686 2351 case 7:
13526728
EH		 2352 /* Structured Extended Feature Flags Enumeration Leaf */
2353 if (count == 0) {
2354 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2355 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2356 *ecx = 0; /* Reserved */
2357 *edx = 0; /* Reserved */
f7911686
YW		 2358 } else {
2359 *eax = 0;
2360 *ebx = 0;
2361 *ecx = 0;
2362 *edx = 0;
2363 }
2364 break;
c6dc6f63
AP		 2365 case 9:
2366 /* Direct Cache Access Information Leaf */
2367 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2368 *ebx = 0;
2369 *ecx = 0;
2370 *edx = 0;
2371 break;
2372 case 0xA:
2373 /* Architectural Performance Monitoring Leaf */
9337e3b6 2374 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2375 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2376
2377 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2378 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2379 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2380 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2381 } else {
2382 *eax = 0;
2383 *ebx = 0;
2384 *ecx = 0;
2385 *edx = 0;
2386 }
c6dc6f63 2387 break;
2560f19f
PB		 2388 case 0xD: {
2389 KVMState *s = cs->kvm_state;
2390 uint64_t kvm_mask;
2391 int i;
2392
51e49430 2393 /* Processor Extended State */
2560f19f
PB		 2394 *eax = 0;
2395 *ebx = 0;
2396 *ecx = 0;
2397 *edx = 0;
2398 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2399 break;
2400 }
2560f19f
PB		 2401 kvm_mask =
2402 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2403 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2404
2560f19f
PB		 2405 if (count == 0) {
2406 *ecx = 0x240;
2407 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2408 const ExtSaveArea *esa = &ext_save_areas[i];
2409 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2410 (kvm_mask & (1 << i)) != 0) {
2411 if (i < 32) {
2412 *eax |= 1 << i;
2413 } else {
2414 *edx |= 1 << (i - 32);
2415 }
2416 *ecx = MAX(*ecx, esa->offset + esa->size);
2417 }
2418 }
2419 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2420 *ebx = *ecx;
2421 } else if (count == 1) {
0bb0b2d2 2422 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2423 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2424 const ExtSaveArea *esa = &ext_save_areas[count];
2425 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2426 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2427 *eax = esa->size;
2428 *ebx = esa->offset;
2560f19f 2429 }
51e49430
SY		 2430 }
2431 break;
2560f19f 2432 }
c6dc6f63
AP		 2433 case 0x80000000:
2434 *eax = env->cpuid_xlevel;
2435 *ebx = env->cpuid_vendor1;
2436 *edx = env->cpuid_vendor2;
2437 *ecx = env->cpuid_vendor3;
2438 break;
2439 case 0x80000001:
2440 *eax = env->cpuid_version;
2441 *ebx = 0;
0514ef2f
EH		 2442 *ecx = env->features[FEAT_8000_0001_ECX];
2443 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2444
2445 /* The Linux kernel checks for the CMPLegacy bit and
2446 * discards multiple thread information if it is set.
2447 * So dont set it here for Intel to make Linux guests happy.
2448 */
ce3960eb 2449 if (cs->nr_cores * cs->nr_threads > 1) {
0856579c
PM		 2450 uint32_t tebx, tecx, tedx;
2451 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2452 if (tebx != CPUID_VENDOR_INTEL_1 ||
2453 tedx != CPUID_VENDOR_INTEL_2 ||
2454 tecx != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2455 *ecx |= 1 << 1; /* CmpLegacy bit */
2456 }
2457 }
c6dc6f63
AP		 2458 break;
2459 case 0x80000002:
2460 case 0x80000003:
2461 case 0x80000004:
2462 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2463 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2464 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2465 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2466 break;
2467 case 0x80000005:
2468 /* cache info (L1 cache) */
787aaf57
BC		 2469 if (cpu->cache_info_passthrough) {
2470 host_cpuid(index, 0, eax, ebx, ecx, edx);
2471 break;
2472 }
5e891bf8
EH		 2473 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2474 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2475 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2476 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2477 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2478 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2479 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2480 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2481 break;
2482 case 0x80000006:
2483 /* cache info (L2 cache) */
787aaf57
BC		 2484 if (cpu->cache_info_passthrough) {
2485 host_cpuid(index, 0, eax, ebx, ecx, edx);
2486 break;
2487 }
5e891bf8
EH		 2488 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2489 (L2_DTLB_2M_ENTRIES << 16) | \
2490 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2491 (L2_ITLB_2M_ENTRIES);
2492 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2493 (L2_DTLB_4K_ENTRIES << 16) | \
2494 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2495 (L2_ITLB_4K_ENTRIES);
2496 *ecx = (L2_SIZE_KB_AMD << 16) | \
2497 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2498 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2499 *edx = ((L3_SIZE_KB/512) << 18) | \
2500 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2501 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2502 break;
303752a9
MT		 2503 case 0x80000007:
2504 *eax = 0;
2505 *ebx = 0;
2506 *ecx = 0;
2507 *edx = env->features[FEAT_8000_0007_EDX];
2508 break;
c6dc6f63
AP		 2509 case 0x80000008:
2510 /* virtual & phys address size in low 2 bytes. */
2511/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2512 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2513 /* 64 bit processor */
2514/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2515 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2516 } else {
0514ef2f 2517 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2518 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2519 } else {
c6dc6f63 2520 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2521 }
c6dc6f63
AP		 2522 }
2523 *ebx = 0;
2524 *ecx = 0;
2525 *edx = 0;
ce3960eb
AF		 2526 if (cs->nr_cores * cs->nr_threads > 1) {
2527 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2528 }
2529 break;
2530 case 0x8000000A:
0514ef2f 2531 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2532 *eax = 0x00000001; /* SVM Revision */
2533 *ebx = 0x00000010; /* nr of ASIDs */
2534 *ecx = 0;
0514ef2f 2535 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2536 } else {
2537 *eax = 0;
2538 *ebx = 0;
2539 *ecx = 0;
2540 *edx = 0;
2541 }
c6dc6f63 2542 break;
b3baa152
BW		 2543 case 0xC0000000:
2544 *eax = env->cpuid_xlevel2;
2545 *ebx = 0;
2546 *ecx = 0;
2547 *edx = 0;
2548 break;
2549 case 0xC0000001:
2550 /* Support for VIA CPU's CPUID instruction */
2551 *eax = env->cpuid_version;
2552 *ebx = 0;
2553 *ecx = 0;
0514ef2f 2554 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2555 break;
2556 case 0xC0000002:
2557 case 0xC0000003:
2558 case 0xC0000004:
2559 /* Reserved for the future, and now filled with zero */
2560 *eax = 0;
2561 *ebx = 0;
2562 *ecx = 0;
2563 *edx = 0;
2564 break;
c6dc6f63
AP		 2565 default:
2566 /* reserved values: zero */
2567 *eax = 0;
2568 *ebx = 0;
2569 *ecx = 0;
2570 *edx = 0;
2571 break;
2572 }
2573}
5fd2087a
AF		 2574
2575/* CPUClass::reset() */
2576static void x86_cpu_reset(CPUState *s)
2577{
2578 X86CPU *cpu = X86_CPU(s);
2579 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2580 CPUX86State *env = &cpu->env;
c1958aea
AF		 2581 int i;
2582
5fd2087a
AF		 2583 xcc->parent_reset(s);
2584
43175fa9 2585 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2586
00c8cb0a 2587 tlb_flush(s, 1);
c1958aea
AF		 2588
2589 env->old_exception = -1;
2590
2591 /* init to reset state */
2592
2593#ifdef CONFIG_SOFTMMU
2594 env->hflags |= HF_SOFTMMU_MASK;
2595#endif
2596 env->hflags2 |= HF2_GIF_MASK;
2597
2598 cpu_x86_update_cr0(env, 0x60000010);
2599 env->a20_mask = ~0x0;
2600 env->smbase = 0x30000;
2601
2602 env->idt.limit = 0xffff;
2603 env->gdt.limit = 0xffff;
2604 env->ldt.limit = 0xffff;
2605 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2606 env->tr.limit = 0xffff;
2607 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2608
2609 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2610 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2611 DESC_R_MASK | DESC_A_MASK);
2612 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2613 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2614 DESC_A_MASK);
2615 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2616 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2617 DESC_A_MASK);
2618 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2619 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2620 DESC_A_MASK);
2621 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2622 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2623 DESC_A_MASK);
2624 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2625 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2626 DESC_A_MASK);
2627
2628 env->eip = 0xfff0;
2629 env->regs[R_EDX] = env->cpuid_version;
2630
2631 env->eflags = 0x2;
2632
2633 /* FPU init */
2634 for (i = 0; i < 8; i++) {
2635 env->fptags[i] = 1;
2636 }
5bde1407 2637 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2638
2639 env->mxcsr = 0x1f80;
c74f41bb 2640 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2641
2642 env->pat = 0x0007040600070406ULL;
2643 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2644
2645 memset(env->dr, 0, sizeof(env->dr));
2646 env->dr[6] = DR6_FIXED_1;
2647 env->dr[7] = DR7_FIXED_1;
b3310ab3 2648 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2649 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2650
05e7e819 2651 env->xcr0 = 1;
0522604b 2652
9db2efd9
AW		 2653 /*
2654 * SDM 11.11.5 requires:
2655 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2656 * - IA32_MTRR_PHYSMASKn.V = 0
2657 * All other bits are undefined. For simplification, zero it all.
2658 */
2659 env->mtrr_deftype = 0;
2660 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2661 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2662
dd673288
IM		 2663#if !defined(CONFIG_USER_ONLY)
2664 /* We hard-wire the BSP to the first CPU. */
55e5c285 2665 if (s->cpu_index == 0) {
02e51483 2666 apic_designate_bsp(cpu->apic_state);
dd673288
IM		 2667 }
2668
259186a7 2669 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2670
2671 if (kvm_enabled()) {
2672 kvm_arch_reset_vcpu(cpu);
2673 }
dd673288 2674#endif
5fd2087a
AF		 2675}
2676
dd673288
IM		 2677#ifndef CONFIG_USER_ONLY
2678bool cpu_is_bsp(X86CPU *cpu)
2679{
02e51483 2680 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2681}
65dee380
IM		 2682
2683/* TODO: remove me, when reset over QOM tree is implemented */
2684static void x86_cpu_machine_reset_cb(void *opaque)
2685{
2686 X86CPU *cpu = opaque;
2687 cpu_reset(CPU(cpu));
2688}
dd673288
IM		 2689#endif
2690
de024815
AF		 2691static void mce_init(X86CPU *cpu)
2692{
2693 CPUX86State *cenv = &cpu->env;
2694 unsigned int bank;
2695
2696 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2697 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2698 (CPUID_MCE | CPUID_MCA)) {
2699 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2700 cenv->mcg_ctl = ~(uint64_t)0;
2701 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2702 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2703 }
2704 }
2705}
2706
bdeec802 2707#ifndef CONFIG_USER_ONLY
d3c64d6a 2708static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2709{
0856579c 2710 CPUX86State *env = &cpu->env;
53a89e26 2711 DeviceState *dev = DEVICE(cpu);
449994eb 2712 APICCommonState *apic;
bdeec802
IM		 2713 const char *apic_type = "apic";
2714
2715 if (kvm_irqchip_in_kernel()) {
2716 apic_type = "kvm-apic";
2717 } else if (xen_enabled()) {
2718 apic_type = "xen-apic";
2719 }
2720
02e51483
CF		 2721 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2722 if (cpu->apic_state == NULL) {
bdeec802
IM		 2723 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2724 return;
2725 }
2726
2727 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2728 OBJECT(cpu->apic_state), NULL);
0856579c 2729 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
bdeec802 2730 /* TODO: convert to link<> */
02e51483 2731 apic = APIC_COMMON(cpu->apic_state);
60671e58 2732 apic->cpu = cpu;
d3c64d6a
IM		 2733}
2734
2735static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2736{
02e51483 2737 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2738 return;
2739 }
bdeec802 2740
02e51483 2741 if (qdev_init(cpu->apic_state)) {
bdeec802 2742 error_setg(errp, "APIC device '%s' could not be initialized",
02e51483 2743 object_get_typename(OBJECT(cpu->apic_state)));
bdeec802
IM		 2744 return;
2745 }
bdeec802 2746}
d3c64d6a
IM		 2747#else
2748static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2749{
2750}
bdeec802
IM		 2751#endif
2752
e48638fd
WH		 2753
2754#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2755 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2756 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2757#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2758 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2759 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2760static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2761{
14a10fc3 2762 CPUState *cs = CPU(dev);
2b6f294c
AF		 2763 X86CPU *cpu = X86_CPU(dev);
2764 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2765 CPUX86State *env = &cpu->env;
2b6f294c 2766 Error *local_err = NULL;
e48638fd 2767 static bool ht_warned;
b34d12d1 2768
0514ef2f 2769 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2770 env->cpuid_level = 7;
2771 }
7a059953 2772
9b15cd9e
IM		 2773 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2774 * CPUID[1].EDX.
2775 */
e48638fd 2776 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2777 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2778 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2779 & CPUID_EXT2_AMD_ALIASES);
2780 }
2781
fefb41bf
EH		 2782
2783 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2784 error_setg(&local_err,
2785 kvm_enabled() ?
2786 "Host doesn't support requested features" :
2787 "TCG doesn't support requested features");
2788 goto out;
4586f157
IM		 2789 }
2790
65dee380
IM		 2791#ifndef CONFIG_USER_ONLY
2792 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2793
0514ef2f 2794 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2795 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2796 if (local_err != NULL) {
4dc1f449 2797 goto out;
bdeec802
IM		 2798 }
2799 }
65dee380
IM		 2800#endif
2801
7a059953 2802 mce_init(cpu);
14a10fc3 2803 qemu_init_vcpu(cs);
d3c64d6a 2804
e48638fd
WH		 2805 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2806 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2807 * based on inputs (sockets,cores,threads), it is still better to gives
2808 * users a warning.
2809 *
2810 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2811 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2812 */
2813 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2814 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2815 " -smp options properly.");
2816 ht_warned = true;
2817 }
2818
d3c64d6a
IM		 2819 x86_cpu_apic_realize(cpu, &local_err);
2820 if (local_err != NULL) {
2821 goto out;
2822 }
14a10fc3 2823 cpu_reset(cs);
2b6f294c 2824
4dc1f449
IM		 2825 xcc->parent_realize(dev, &local_err);
2826out:
2827 if (local_err != NULL) {
2828 error_propagate(errp, local_err);
2829 return;
2830 }
7a059953
AF		 2831}
2832
0856579c
PM		 2833/* Enables contiguous-apic-ID mode, for compatibility */
2834static bool compat_apic_id_mode;
2835
2836void enable_compat_apic_id_mode(void)
2837{
2838 compat_apic_id_mode = true;
2839}
2840
2841/* Calculates initial APIC ID for a specific CPU index
2842 *
2843 * Currently we need to be able to calculate the APIC ID from the CPU index
2844 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2845 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2846 * all CPUs up to max_cpus.
2847 */
2848uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2849{
2850 uint32_t correct_id;
2851 static bool warned;
2852
2853 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2854 if (compat_apic_id_mode) {
2855 if (cpu_index != correct_id && !warned) {
2856 error_report("APIC IDs set in compatibility mode, "
2857 "CPU topology won't match the configuration");
2858 warned = true;
2859 }
2860 return cpu_index;
2861 } else {
2862 return correct_id;
2863 }
2864}
2865
de024815
AF		 2866static void x86_cpu_initfn(Object *obj)
2867{
55e5c285 2868 CPUState *cs = CPU(obj);
de024815 2869 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2870 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2871 CPUX86State *env = &cpu->env;
d65e9815 2872 static int inited;
de024815 2873
c05efcb1 2874 cs->env_ptr = env;
de024815 2875 cpu_exec_init(env);
71ad61d3
AF		 2876
2877 object_property_add(obj, "family", "int",
95b8519d 2878 x86_cpuid_version_get_family,
71ad61d3 2879 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2880 object_property_add(obj, "model", "int",
67e30c83 2881 x86_cpuid_version_get_model,
c5291a4f 2882 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2883 object_property_add(obj, "stepping", "int",
35112e41 2884 x86_cpuid_version_get_stepping,
036e2222 2885 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 2886 object_property_add(obj, "level", "int",
2887 x86_cpuid_get_level,
2888 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 2889 object_property_add(obj, "xlevel", "int",
2890 x86_cpuid_get_xlevel,
2891 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 2892 object_property_add_str(obj, "vendor",
2893 x86_cpuid_get_vendor,
2894 x86_cpuid_set_vendor, NULL);
938d4c25 2895 object_property_add_str(obj, "model-id",
63e886eb 2896 x86_cpuid_get_model_id,
938d4c25 2897 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2898 object_property_add(obj, "tsc-frequency", "int",
2899 x86_cpuid_get_tsc_freq,
2900 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2901 object_property_add(obj, "apic-id", "int",
2902 x86_cpuid_get_apic_id,
2903 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2904 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2905 x86_cpu_get_feature_words,
7e5292b5
EH		 2906 NULL, NULL, (void *)env->features, NULL);
2907 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2908 x86_cpu_get_feature_words,
2909 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2910
92067bf4 2911 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
0856579c 2912 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
d65e9815 2913
d940ee9b
EH		 2914 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2915
d65e9815
IM		 2916 /* init various static tables used in TCG mode */
2917 if (tcg_enabled() && !inited) {
2918 inited = 1;
2919 optimize_flags_init();
d65e9815 2920 }
de024815
AF		 2921}
2922
997395d3
IM		 2923static int64_t x86_cpu_get_arch_id(CPUState *cs)
2924{
2925 X86CPU *cpu = X86_CPU(cs);
0856579c 2926 CPUX86State *env = &cpu->env;
997395d3 2927
0856579c 2928 return env->cpuid_apic_id;
997395d3
IM		 2929}
2930
444d5590
AF		 2931static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2932{
2933 X86CPU *cpu = X86_CPU(cs);
2934
2935 return cpu->env.cr[0] & CR0_PG_MASK;
2936}
2937
f45748f1
AF		 2938static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2939{
2940 X86CPU *cpu = X86_CPU(cs);
2941
2942 cpu->env.eip = value;
2943}
2944
bdf7ae5b
AF		 2945static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2946{
2947 X86CPU *cpu = X86_CPU(cs);
2948
2949 cpu->env.eip = tb->pc - tb->cs_base;
2950}
2951
8c2e1b00
AF		 2952static bool x86_cpu_has_work(CPUState *cs)
2953{
2954 X86CPU *cpu = X86_CPU(cs);
2955 CPUX86State *env = &cpu->env;
2956
60e68042
PB		 2957#if !defined(CONFIG_USER_ONLY)
2958 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2959 apic_poll_irq(cpu->apic_state);
2960 cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
2961 }
2962#endif
2963
2964 return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
8c2e1b00
AF		 2965 (env->eflags & IF_MASK)) ||
2966 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2967 CPU_INTERRUPT_INIT |
2968 CPU_INTERRUPT_SIPI |
2969 CPU_INTERRUPT_MCE));
2970}
2971
9337e3b6
EH		 2972static Property x86_cpu_properties[] = {
2973 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2974 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2975 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2976 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2977 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2978 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2979 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2980 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
9337e3b6
EH		 2981 DEFINE_PROP_END_OF_LIST()
2982};
2983
5fd2087a
AF		 2984static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2985{
2986 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2987 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2988 DeviceClass *dc = DEVICE_CLASS(oc);
2989
2990 xcc->parent_realize = dc->realize;
2991 dc->realize = x86_cpu_realizefn;
62fc403f 2992 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2993 dc->props = x86_cpu_properties;
5fd2087a
AF		 2994
2995 xcc->parent_reset = cc->reset;
2996 cc->reset = x86_cpu_reset;
91b1df8c 2997 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2998
500050d1 2999 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3000 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3001 cc->has_work = x86_cpu_has_work;
97a8ea5a 3002 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3003 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3004 cc->dump_state = x86_cpu_dump_state;
f45748f1 3005 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3006 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3007 cc->gdb_read_register = x86_cpu_gdb_read_register;
3008 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3009 cc->get_arch_id = x86_cpu_get_arch_id;
3010 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3011#ifdef CONFIG_USER_ONLY
3012 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3013#else
a23bbfda 3014 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3015 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3016 cc->write_elf64_note = x86_cpu_write_elf64_note;
3017 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3018 cc->write_elf32_note = x86_cpu_write_elf32_note;
3019 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3020 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3021#endif
a0e372f0 3022 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3023#ifndef CONFIG_USER_ONLY
3024 cc->debug_excp_handler = breakpoint_handler;
3025#endif
374e0cd4
RH		 3026 cc->cpu_exec_enter = x86_cpu_exec_enter;
3027 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 3028}
3029
3030static const TypeInfo x86_cpu_type_info = {
3031 .name = TYPE_X86_CPU,
3032 .parent = TYPE_CPU,
3033 .instance_size = sizeof(X86CPU),
de024815 3034 .instance_init = x86_cpu_initfn,
d940ee9b 3035 .abstract = true,
5fd2087a
AF		 3036 .class_size = sizeof(X86CPUClass),
3037 .class_init = x86_cpu_common_class_init,
3038};
3039
3040static void x86_cpu_register_types(void)
3041{
d940ee9b
EH		 3042 int i;
3043
5fd2087a 3044 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3045 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3046 x86_register_cpudef_type(&builtin_x86_defs[i]);
3047 }
3048#ifdef CONFIG_KVM
3049 type_register_static(&host_x86_cpu_type_info);
3050#endif
5fd2087a
AF		 3051}
3052
3053type_init(x86_cpu_register_types)
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