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apic: convert ->busdev.qdev casts to C casts
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
8248c36a 243 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 259 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 261 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 263};
264
303752a9
MT		 265static const char *cpuid_apm_edx_feature_name[] = {
266 NULL, NULL, NULL, NULL,
267 NULL, NULL, NULL, NULL,
268 "invtsc", NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274};
275
0bb0b2d2
PB		 276static const char *cpuid_xsave_feature_name[] = {
277 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
278 NULL, NULL, NULL, NULL,
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285};
286
621626ce
EH		 287#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
288#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
289 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
290#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
291 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
292 CPUID_PSE36 | CPUID_FXSR)
293#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
294#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
295 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
296 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
297 CPUID_PAE | CPUID_SEP | CPUID_APIC)
298
299#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
300 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
301 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
302 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
303 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
304 /* partly implemented:
305 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
306 /* missing:
307 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
308#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
309 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
310 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
311 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
312 /* missing:
313 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
314 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
315 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
316 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
317 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
318 CPUID_EXT_RDRAND */
319
320#ifdef TARGET_X86_64
321#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
322#else
323#define TCG_EXT2_X86_64_FEATURES 0
324#endif
325
326#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
327 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
328 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
329 TCG_EXT2_X86_64_FEATURES)
330#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
331 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
332#define TCG_EXT4_FEATURES 0
333#define TCG_SVM_FEATURES 0
334#define TCG_KVM_FEATURES 0
335#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
336 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
337 /* missing:
338 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
339 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
340 CPUID_7_0_EBX_RDSEED */
303752a9 341#define TCG_APM_FEATURES 0
621626ce
EH		 342
343
5ef57876
EH		 344typedef struct FeatureWordInfo {
345 const char **feat_names;
04d104b6
EH		 346 uint32_t cpuid_eax; /* Input EAX for CPUID */
347 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
348 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
349 int cpuid_reg; /* output register (R_* constant) */
37ce3522 350 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 351 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 352} FeatureWordInfo;
353
354static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 355 [FEAT_1_EDX] = {
356 .feat_names = feature_name,
357 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 358 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 359 },
360 [FEAT_1_ECX] = {
361 .feat_names = ext_feature_name,
362 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 363 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 364 },
365 [FEAT_8000_0001_EDX] = {
366 .feat_names = ext2_feature_name,
367 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 368 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 369 },
370 [FEAT_8000_0001_ECX] = {
371 .feat_names = ext3_feature_name,
372 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 373 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 374 },
89e49c8b
EH		 375 [FEAT_C000_0001_EDX] = {
376 .feat_names = ext4_feature_name,
377 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 378 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 379 },
bffd67b0
EH		 380 [FEAT_KVM] = {
381 .feat_names = kvm_feature_name,
382 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 383 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 384 },
385 [FEAT_SVM] = {
386 .feat_names = svm_feature_name,
387 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 388 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 389 },
390 [FEAT_7_0_EBX] = {
391 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 392 .cpuid_eax = 7,
393 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
394 .cpuid_reg = R_EBX,
37ce3522 395 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 396 },
303752a9
MT		 397 [FEAT_8000_0007_EDX] = {
398 .feat_names = cpuid_apm_edx_feature_name,
399 .cpuid_eax = 0x80000007,
400 .cpuid_reg = R_EDX,
401 .tcg_features = TCG_APM_FEATURES,
402 .unmigratable_flags = CPUID_APM_INVTSC,
403 },
0bb0b2d2
PB		 404 [FEAT_XSAVE] = {
405 .feat_names = cpuid_xsave_feature_name,
406 .cpuid_eax = 0xd,
407 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
408 .cpuid_reg = R_EAX,
409 .tcg_features = 0,
0bb0b2d2 410 },
5ef57876
EH		 411};
412
8e8aba50
EH		 413typedef struct X86RegisterInfo32 {
414 /* Name of register */
415 const char *name;
416 /* QAPI enum value register */
417 X86CPURegister32 qapi_enum;
418} X86RegisterInfo32;
419
420#define REGISTER(reg) \
5d371f41 421 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 422static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 423 REGISTER(EAX),
424 REGISTER(ECX),
425 REGISTER(EDX),
426 REGISTER(EBX),
427 REGISTER(ESP),
428 REGISTER(EBP),
429 REGISTER(ESI),
430 REGISTER(EDI),
431};
432#undef REGISTER
433
2560f19f
PB		 434typedef struct ExtSaveArea {
435 uint32_t feature, bits;
436 uint32_t offset, size;
437} ExtSaveArea;
438
439static const ExtSaveArea ext_save_areas[] = {
440 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 441 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 442 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
443 .offset = 0x3c0, .size = 0x40 },
444 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 445 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 446 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
447 .offset = 0x440, .size = 0x40 },
448 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
449 .offset = 0x480, .size = 0x200 },
450 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
451 .offset = 0x680, .size = 0x400 },
2560f19f 452};
8e8aba50 453
8b4beddc
EH		 454const char *get_register_name_32(unsigned int reg)
455{
31ccdde2 456 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 457 return NULL;
458 }
8e8aba50 459 return x86_reg_info_32[reg].name;
8b4beddc
EH		 460}
461
5fcca9ff
EH		 462/* KVM-specific features that are automatically added to all CPU models
463 * when KVM is enabled.
464 */
465static uint32_t kvm_default_features[FEATURE_WORDS] = {
466 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 467 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 468 (1 << KVM_FEATURE_CLOCKSOURCE2) |
469 (1 << KVM_FEATURE_ASYNC_PF) |
470 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 471 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 472 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 473 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 474};
dc59944b 475
136a7e9a
EH		 476/* Features that are not added by default to any CPU model when KVM is enabled.
477 */
478static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 479 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a 480 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
75d373ef 481 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
136a7e9a
EH		 482};
483
1cadaa94 484void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 485{
8fb4f821 486 kvm_default_features[w] &= ~features;
dc59944b
MT		 487}
488
75d373ef
EH		 489void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
490{
491 kvm_default_unset_features[w] &= ~features;
492}
493
84f1b92f
EH		 494/*
495 * Returns the set of feature flags that are supported and migratable by
496 * QEMU, for a given FeatureWord.
497 */
498static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
499{
500 FeatureWordInfo *wi = &feature_word_info[w];
501 uint32_t r = 0;
502 int i;
503
504 for (i = 0; i < 32; i++) {
505 uint32_t f = 1U << i;
506 /* If the feature name is unknown, it is not supported by QEMU yet */
507 if (!wi->feat_names[i]) {
508 continue;
509 }
510 /* Skip features known to QEMU, but explicitly marked as unmigratable */
511 if (wi->unmigratable_flags & f) {
512 continue;
513 }
514 r |= f;
515 }
516 return r;
517}
518
bb44e0d1
JK		 519void host_cpuid(uint32_t function, uint32_t count,
520 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 521{
a1fd24af
AL		 522 uint32_t vec[4];
523
524#ifdef __x86_64__
525 asm volatile("cpuid"
526 : "=a"(vec[0]), "=b"(vec[1]),
527 "=c"(vec[2]), "=d"(vec[3])
528 : "0"(function), "c"(count) : "cc");
c1f41226 529#elif defined(__i386__)
a1fd24af
AL		 530 asm volatile("pusha \n\t"
531 "cpuid \n\t"
532 "mov %%eax, 0(%2) \n\t"
533 "mov %%ebx, 4(%2) \n\t"
534 "mov %%ecx, 8(%2) \n\t"
535 "mov %%edx, 12(%2) \n\t"
536 "popa"
537 : : "a"(function), "c"(count), "S"(vec)
538 : "memory", "cc");
c1f41226
EH		 539#else
540 abort();
a1fd24af
AL		 541#endif
542
bdde476a 543 if (eax)
a1fd24af 544 *eax = vec[0];
bdde476a 545 if (ebx)
a1fd24af 546 *ebx = vec[1];
bdde476a 547 if (ecx)
a1fd24af 548 *ecx = vec[2];
bdde476a 549 if (edx)
a1fd24af 550 *edx = vec[3];
bdde476a 551}
c6dc6f63
AP		 552
553#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
554
555/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
556 * a substring. ex if !NULL points to the first char after a substring,
557 * otherwise the string is assumed to sized by a terminating nul.
558 * Return lexical ordering of *s1:*s2.
559 */
8f9d989c
CF		 560static int sstrcmp(const char *s1, const char *e1,
561 const char *s2, const char *e2)
c6dc6f63
AP		 562{
563 for (;;) {
564 if (!*s1 || !*s2 || *s1 != *s2)
565 return (*s1 - *s2);
566 ++s1, ++s2;
567 if (s1 == e1 && s2 == e2)
568 return (0);
569 else if (s1 == e1)
570 return (*s2);
571 else if (s2 == e2)
572 return (*s1);
573 }
574}
575
576/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
577 * '|' delimited (possibly empty) strings in which case search for a match
578 * within the alternatives proceeds left to right. Return 0 for success,
579 * non-zero otherwise.
580 */
581static int altcmp(const char *s, const char *e, const char *altstr)
582{
583 const char *p, *q;
584
585 for (q = p = altstr; ; ) {
586 while (*p && *p != '|')
587 ++p;
588 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
589 return (0);
590 if (!*p)
591 return (1);
592 else
593 q = ++p;
594 }
595}
596
597/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 598 * *pval and return true, otherwise return false
c6dc6f63 599 */
e41e0fc6
JK		 600static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
601 const char **featureset)
c6dc6f63
AP		 602{
603 uint32_t mask;
604 const char **ppc;
e41e0fc6 605 bool found = false;
c6dc6f63 606
e41e0fc6 607 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 608 if (*ppc && !altcmp(s, e, *ppc)) {
609 *pval |= mask;
e41e0fc6 610 found = true;
c6dc6f63 611 }
e41e0fc6
JK		 612 }
613 return found;
c6dc6f63
AP		 614}
615
5ef57876 616static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 617 FeatureWordArray words,
618 Error **errp)
c6dc6f63 619{
5ef57876
EH		 620 FeatureWord w;
621 for (w = 0; w < FEATURE_WORDS; w++) {
622 FeatureWordInfo *wi = &feature_word_info[w];
623 if (wi->feat_names &&
624 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
625 break;
626 }
627 }
628 if (w == FEATURE_WORDS) {
c00c94ab 629 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 630 }
c6dc6f63
AP		 631}
632
d940ee9b
EH		 633/* CPU class name definitions: */
634
635#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
636#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
637
638/* Return type name for a given CPU model name
639 * Caller is responsible for freeing the returned string.
640 */
641static char *x86_cpu_type_name(const char *model_name)
642{
643 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
644}
645
500050d1
AF		 646static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
647{
d940ee9b
EH		 648 ObjectClass *oc;
649 char *typename;
650
500050d1
AF		 651 if (cpu_model == NULL) {
652 return NULL;
653 }
654
d940ee9b
EH		 655 typename = x86_cpu_type_name(cpu_model);
656 oc = object_class_by_name(typename);
657 g_free(typename);
658 return oc;
500050d1
AF		 659}
660
d940ee9b 661struct X86CPUDefinition {
c6dc6f63
AP		 662 const char *name;
663 uint32_t level;
90e4b0c3
EH		 664 uint32_t xlevel;
665 uint32_t xlevel2;
99b88a17
IM		 666 /* vendor is zero-terminated, 12 character ASCII string */
667 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 668 int family;
669 int model;
670 int stepping;
0514ef2f 671 FeatureWordArray features;
c6dc6f63 672 char model_id[48];
787aaf57 673 bool cache_info_passthrough;
d940ee9b 674};
c6dc6f63 675
9576de75 676static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 677 {
678 .name = "qemu64",
679 .level = 4,
99b88a17 680 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 681 .family = 6,
f8e6a11a 682 .model = 6,
c6dc6f63 683 .stepping = 3,
0514ef2f 684 .features[FEAT_1_EDX] =
27861ecc 685 PPRO_FEATURES |
c6dc6f63 686 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 687 CPUID_PSE36,
0514ef2f 688 .features[FEAT_1_ECX] =
27861ecc 689 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 690 .features[FEAT_8000_0001_EDX] =
c6dc6f63 691 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 692 .features[FEAT_8000_0001_ECX] =
27861ecc 693 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 694 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
695 .xlevel = 0x8000000A,
c6dc6f63
AP		 696 },
697 {
698 .name = "phenom",
699 .level = 5,
99b88a17 700 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 701 .family = 16,
702 .model = 2,
703 .stepping = 3,
b9fc20bc 704 /* Missing: CPUID_HT */
0514ef2f 705 .features[FEAT_1_EDX] =
27861ecc 706 PPRO_FEATURES |
c6dc6f63 707 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 708 CPUID_PSE36 | CPUID_VME,
0514ef2f 709 .features[FEAT_1_ECX] =
27861ecc 710 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 711 CPUID_EXT_POPCNT,
0514ef2f 712 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 713 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
714 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 715 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 716 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
717 CPUID_EXT3_CR8LEG,
718 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
719 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 720 .features[FEAT_8000_0001_ECX] =
27861ecc 721 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 722 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 723 /* Missing: CPUID_SVM_LBRV */
0514ef2f 724 .features[FEAT_SVM] =
b9fc20bc 725 CPUID_SVM_NPT,
c6dc6f63
AP		 726 .xlevel = 0x8000001A,
727 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
728 },
729 {
730 .name = "core2duo",
731 .level = 10,
99b88a17 732 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 733 .family = 6,
734 .model = 15,
735 .stepping = 11,
b9fc20bc 736 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 737 .features[FEAT_1_EDX] =
27861ecc 738 PPRO_FEATURES |
c6dc6f63 739 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 740 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
741 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 742 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 743 .features[FEAT_1_ECX] =
27861ecc 744 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 745 CPUID_EXT_CX16,
0514ef2f 746 .features[FEAT_8000_0001_EDX] =
27861ecc 747 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 748 .features[FEAT_8000_0001_ECX] =
27861ecc 749 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 750 .xlevel = 0x80000008,
751 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
752 },
753 {
754 .name = "kvm64",
755 .level = 5,
99b88a17 756 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 757 .family = 15,
758 .model = 6,
759 .stepping = 1,
b3a4f0b1 760 /* Missing: CPUID_HT */
0514ef2f 761 .features[FEAT_1_EDX] =
b3a4f0b1 762 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 763 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
764 CPUID_PSE36,
765 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 766 .features[FEAT_1_ECX] =
27861ecc 767 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 768 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 769 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 770 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
771 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
772 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
773 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
774 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 775 .features[FEAT_8000_0001_ECX] =
27861ecc 776 0,
c6dc6f63
AP		 777 .xlevel = 0x80000008,
778 .model_id = "Common KVM processor"
779 },
c6dc6f63
AP		 780 {
781 .name = "qemu32",
782 .level = 4,
99b88a17 783 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 784 .family = 6,
f8e6a11a 785 .model = 6,
c6dc6f63 786 .stepping = 3,
0514ef2f 787 .features[FEAT_1_EDX] =
27861ecc 788 PPRO_FEATURES,
0514ef2f 789 .features[FEAT_1_ECX] =
27861ecc 790 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 791 .xlevel = 0x80000004,
c6dc6f63 792 },
eafaf1e5
AP		 793 {
794 .name = "kvm32",
795 .level = 5,
99b88a17 796 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 797 .family = 15,
798 .model = 6,
799 .stepping = 1,
0514ef2f 800 .features[FEAT_1_EDX] =
b3a4f0b1 801 PPRO_FEATURES | CPUID_VME |
eafaf1e5 802 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 803 .features[FEAT_1_ECX] =
27861ecc 804 CPUID_EXT_SSE3,
0514ef2f 805 .features[FEAT_8000_0001_ECX] =
27861ecc 806 0,
eafaf1e5
AP		 807 .xlevel = 0x80000008,
808 .model_id = "Common 32-bit KVM processor"
809 },
c6dc6f63
AP		 810 {
811 .name = "coreduo",
812 .level = 10,
99b88a17 813 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 814 .family = 6,
815 .model = 14,
816 .stepping = 8,
b9fc20bc 817 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 818 .features[FEAT_1_EDX] =
27861ecc 819 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 820 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
821 CPUID_SS,
822 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 823 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 824 .features[FEAT_1_ECX] =
e93abc14 825 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 826 .features[FEAT_8000_0001_EDX] =
27861ecc 827 CPUID_EXT2_NX,
c6dc6f63
AP		 828 .xlevel = 0x80000008,
829 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
830 },
831 {
832 .name = "486",
58012d66 833 .level = 1,
99b88a17 834 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 835 .family = 4,
b2a856d9 836 .model = 8,
c6dc6f63 837 .stepping = 0,
0514ef2f 838 .features[FEAT_1_EDX] =
27861ecc 839 I486_FEATURES,
c6dc6f63
AP		 840 .xlevel = 0,
841 },
842 {
843 .name = "pentium",
844 .level = 1,
99b88a17 845 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 846 .family = 5,
847 .model = 4,
848 .stepping = 3,
0514ef2f 849 .features[FEAT_1_EDX] =
27861ecc 850 PENTIUM_FEATURES,
c6dc6f63
AP		 851 .xlevel = 0,
852 },
853 {
854 .name = "pentium2",
855 .level = 2,
99b88a17 856 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 857 .family = 6,
858 .model = 5,
859 .stepping = 2,
0514ef2f 860 .features[FEAT_1_EDX] =
27861ecc 861 PENTIUM2_FEATURES,
c6dc6f63
AP		 862 .xlevel = 0,
863 },
864 {
865 .name = "pentium3",
866 .level = 2,
99b88a17 867 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 868 .family = 6,
869 .model = 7,
870 .stepping = 3,
0514ef2f 871 .features[FEAT_1_EDX] =
27861ecc 872 PENTIUM3_FEATURES,
c6dc6f63
AP		 873 .xlevel = 0,
874 },
875 {
876 .name = "athlon",
877 .level = 2,
99b88a17 878 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 879 .family = 6,
880 .model = 2,
881 .stepping = 3,
0514ef2f 882 .features[FEAT_1_EDX] =
27861ecc 883 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 884 CPUID_MCA,
0514ef2f 885 .features[FEAT_8000_0001_EDX] =
60032ac0 886 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 887 .xlevel = 0x80000008,
c6dc6f63
AP		 888 },
889 {
890 .name = "n270",
891 /* original is on level 10 */
892 .level = 5,
99b88a17 893 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 894 .family = 6,
895 .model = 28,
896 .stepping = 2,
b9fc20bc 897 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 898 .features[FEAT_1_EDX] =
27861ecc 899 PPRO_FEATURES |
b9fc20bc
EH		 900 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
901 CPUID_ACPI | CPUID_SS,
c6dc6f63 902 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 903 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
904 * CPUID_EXT_XTPR */
0514ef2f 905 .features[FEAT_1_ECX] =
27861ecc 906 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 907 CPUID_EXT_MOVBE,
0514ef2f 908 .features[FEAT_8000_0001_EDX] =
60032ac0 909 CPUID_EXT2_NX,
0514ef2f 910 .features[FEAT_8000_0001_ECX] =
27861ecc 911 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 912 .xlevel = 0x8000000A,
913 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
914 },
3eca4642
EH		 915 {
916 .name = "Conroe",
6b11322e 917 .level = 4,
99b88a17 918 .vendor = CPUID_VENDOR_INTEL,
3eca4642 919 .family = 6,
ffce9ebb 920 .model = 15,
3eca4642 921 .stepping = 3,
0514ef2f 922 .features[FEAT_1_EDX] =
b3a4f0b1 923 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
927 CPUID_DE | CPUID_FP87,
0514ef2f 928 .features[FEAT_1_ECX] =
27861ecc 929 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 930 .features[FEAT_8000_0001_EDX] =
27861ecc 931 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 932 .features[FEAT_8000_0001_ECX] =
27861ecc 933 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 934 .xlevel = 0x8000000A,
935 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
936 },
937 {
938 .name = "Penryn",
6b11322e 939 .level = 4,
99b88a17 940 .vendor = CPUID_VENDOR_INTEL,
3eca4642 941 .family = 6,
ffce9ebb 942 .model = 23,
3eca4642 943 .stepping = 3,
0514ef2f 944 .features[FEAT_1_EDX] =
b3a4f0b1 945 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 946 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
947 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
948 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
949 CPUID_DE | CPUID_FP87,
0514ef2f 950 .features[FEAT_1_ECX] =
27861ecc 951 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 952 CPUID_EXT_SSE3,
0514ef2f 953 .features[FEAT_8000_0001_EDX] =
27861ecc 954 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 955 .features[FEAT_8000_0001_ECX] =
27861ecc 956 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 957 .xlevel = 0x8000000A,
958 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
959 },
960 {
961 .name = "Nehalem",
6b11322e 962 .level = 4,
99b88a17 963 .vendor = CPUID_VENDOR_INTEL,
3eca4642 964 .family = 6,
ffce9ebb 965 .model = 26,
3eca4642 966 .stepping = 3,
0514ef2f 967 .features[FEAT_1_EDX] =
b3a4f0b1 968 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 969 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
970 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
971 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
972 CPUID_DE | CPUID_FP87,
0514ef2f 973 .features[FEAT_1_ECX] =
27861ecc 974 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 975 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 976 .features[FEAT_8000_0001_EDX] =
27861ecc 977 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 978 .features[FEAT_8000_0001_ECX] =
27861ecc 979 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 980 .xlevel = 0x8000000A,
981 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
982 },
983 {
984 .name = "Westmere",
985 .level = 11,
99b88a17 986 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 987 .family = 6,
988 .model = 44,
989 .stepping = 1,
0514ef2f 990 .features[FEAT_1_EDX] =
b3a4f0b1 991 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 992 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
993 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
994 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
995 CPUID_DE | CPUID_FP87,
0514ef2f 996 .features[FEAT_1_ECX] =
27861ecc 997 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 998 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
999 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1000 .features[FEAT_8000_0001_EDX] =
27861ecc 1001 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1002 .features[FEAT_8000_0001_ECX] =
27861ecc 1003 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1004 .xlevel = 0x8000000A,
1005 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1006 },
1007 {
1008 .name = "SandyBridge",
1009 .level = 0xd,
99b88a17 1010 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1011 .family = 6,
1012 .model = 42,
1013 .stepping = 1,
0514ef2f 1014 .features[FEAT_1_EDX] =
b3a4f0b1 1015 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1016 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1017 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1018 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1019 CPUID_DE | CPUID_FP87,
0514ef2f 1020 .features[FEAT_1_ECX] =
27861ecc 1021 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1022 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1023 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1024 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1025 CPUID_EXT_SSE3,
0514ef2f 1026 .features[FEAT_8000_0001_EDX] =
27861ecc 1027 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1028 CPUID_EXT2_SYSCALL,
0514ef2f 1029 .features[FEAT_8000_0001_ECX] =
27861ecc 1030 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1031 .features[FEAT_XSAVE] =
1032 CPUID_XSAVE_XSAVEOPT,
3eca4642
EH		 1033 .xlevel = 0x8000000A,
1034 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1035 },
2f9ac42a
PB		 1036 {
1037 .name = "IvyBridge",
1038 .level = 0xd,
1039 .vendor = CPUID_VENDOR_INTEL,
1040 .family = 6,
1041 .model = 58,
1042 .stepping = 9,
1043 .features[FEAT_1_EDX] =
1044 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1045 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1046 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1047 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1048 CPUID_DE | CPUID_FP87,
1049 .features[FEAT_1_ECX] =
1050 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1051 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1052 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1053 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1054 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1055 .features[FEAT_7_0_EBX] =
1056 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1057 CPUID_7_0_EBX_ERMS,
1058 .features[FEAT_8000_0001_EDX] =
1059 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1060 CPUID_EXT2_SYSCALL,
1061 .features[FEAT_8000_0001_ECX] =
1062 CPUID_EXT3_LAHF_LM,
1063 .features[FEAT_XSAVE] =
1064 CPUID_XSAVE_XSAVEOPT,
1065 .xlevel = 0x8000000A,
1066 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1067 },
37507094 1068 {
a356850b
EH		 1069 .name = "Haswell-noTSX",
1070 .level = 0xd,
1071 .vendor = CPUID_VENDOR_INTEL,
1072 .family = 6,
1073 .model = 60,
1074 .stepping = 1,
1075 .features[FEAT_1_EDX] =
1076 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1077 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1078 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1079 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1080 CPUID_DE | CPUID_FP87,
1081 .features[FEAT_1_ECX] =
1082 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1083 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1084 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1085 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1086 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1087 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1088 .features[FEAT_8000_0001_EDX] =
1089 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1090 CPUID_EXT2_SYSCALL,
1091 .features[FEAT_8000_0001_ECX] =
1092 CPUID_EXT3_LAHF_LM,
1093 .features[FEAT_7_0_EBX] =
1094 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1095 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1096 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1097 .features[FEAT_XSAVE] =
1098 CPUID_XSAVE_XSAVEOPT,
1099 .xlevel = 0x8000000A,
1100 .model_id = "Intel Core Processor (Haswell, no TSX)",
1101 }, {
37507094
EH		 1102 .name = "Haswell",
1103 .level = 0xd,
99b88a17 1104 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1105 .family = 6,
1106 .model = 60,
1107 .stepping = 1,
0514ef2f 1108 .features[FEAT_1_EDX] =
b3a4f0b1 1109 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1110 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1111 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1112 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1113 CPUID_DE | CPUID_FP87,
0514ef2f 1114 .features[FEAT_1_ECX] =
27861ecc 1115 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1116 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1117 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1118 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1119 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1120 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1121 .features[FEAT_8000_0001_EDX] =
27861ecc 1122 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1123 CPUID_EXT2_SYSCALL,
0514ef2f 1124 .features[FEAT_8000_0001_ECX] =
27861ecc 1125 CPUID_EXT3_LAHF_LM,
0514ef2f 1126 .features[FEAT_7_0_EBX] =
27861ecc 1127 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1128 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1129 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1130 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1131 .features[FEAT_XSAVE] =
1132 CPUID_XSAVE_XSAVEOPT,
37507094
EH		 1133 .xlevel = 0x8000000A,
1134 .model_id = "Intel Core Processor (Haswell)",
1135 },
a356850b
EH		 1136 {
1137 .name = "Broadwell-noTSX",
1138 .level = 0xd,
1139 .vendor = CPUID_VENDOR_INTEL,
1140 .family = 6,
1141 .model = 61,
1142 .stepping = 2,
1143 .features[FEAT_1_EDX] =
1144 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1145 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1146 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1147 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1148 CPUID_DE | CPUID_FP87,
1149 .features[FEAT_1_ECX] =
1150 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1151 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1152 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1153 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1154 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1155 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1156 .features[FEAT_8000_0001_EDX] =
1157 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1158 CPUID_EXT2_SYSCALL,
1159 .features[FEAT_8000_0001_ECX] =
1160 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1161 .features[FEAT_7_0_EBX] =
1162 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1163 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1164 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1165 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1166 CPUID_7_0_EBX_SMAP,
1167 .features[FEAT_XSAVE] =
1168 CPUID_XSAVE_XSAVEOPT,
1169 .xlevel = 0x8000000A,
1170 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1171 },
ece01354
EH		 1172 {
1173 .name = "Broadwell",
1174 .level = 0xd,
1175 .vendor = CPUID_VENDOR_INTEL,
1176 .family = 6,
1177 .model = 61,
1178 .stepping = 2,
1179 .features[FEAT_1_EDX] =
b3a4f0b1 1180 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1181 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1182 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1183 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1184 CPUID_DE | CPUID_FP87,
1185 .features[FEAT_1_ECX] =
1186 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1187 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1188 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1189 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1190 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1191 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1192 .features[FEAT_8000_0001_EDX] =
1193 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1194 CPUID_EXT2_SYSCALL,
1195 .features[FEAT_8000_0001_ECX] =
1196 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1197 .features[FEAT_7_0_EBX] =
1198 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1199 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1200 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1201 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1202 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1203 .features[FEAT_XSAVE] =
1204 CPUID_XSAVE_XSAVEOPT,
ece01354
EH		 1205 .xlevel = 0x8000000A,
1206 .model_id = "Intel Core Processor (Broadwell)",
1207 },
3eca4642
EH		 1208 {
1209 .name = "Opteron_G1",
1210 .level = 5,
99b88a17 1211 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1212 .family = 15,
1213 .model = 6,
1214 .stepping = 1,
0514ef2f 1215 .features[FEAT_1_EDX] =
b3a4f0b1 1216 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1217 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1218 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1219 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1220 CPUID_DE | CPUID_FP87,
0514ef2f 1221 .features[FEAT_1_ECX] =
27861ecc 1222 CPUID_EXT_SSE3,
0514ef2f 1223 .features[FEAT_8000_0001_EDX] =
27861ecc 1224 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1225 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1226 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1227 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1228 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1229 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1230 .xlevel = 0x80000008,
1231 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1232 },
1233 {
1234 .name = "Opteron_G2",
1235 .level = 5,
99b88a17 1236 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1237 .family = 15,
1238 .model = 6,
1239 .stepping = 1,
0514ef2f 1240 .features[FEAT_1_EDX] =
b3a4f0b1 1241 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1242 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1243 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1244 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1245 CPUID_DE | CPUID_FP87,
0514ef2f 1246 .features[FEAT_1_ECX] =
27861ecc 1247 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1248 .features[FEAT_8000_0001_EDX] =
27861ecc 1249 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1250 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1251 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1252 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1253 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1254 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1255 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1256 .features[FEAT_8000_0001_ECX] =
27861ecc 1257 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1258 .xlevel = 0x80000008,
1259 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1260 },
1261 {
1262 .name = "Opteron_G3",
1263 .level = 5,
99b88a17 1264 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1265 .family = 15,
1266 .model = 6,
1267 .stepping = 1,
0514ef2f 1268 .features[FEAT_1_EDX] =
b3a4f0b1 1269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1273 CPUID_DE | CPUID_FP87,
0514ef2f 1274 .features[FEAT_1_ECX] =
27861ecc 1275 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1276 CPUID_EXT_SSE3,
0514ef2f 1277 .features[FEAT_8000_0001_EDX] =
27861ecc 1278 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1279 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1280 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1281 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1282 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1283 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1284 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1285 .features[FEAT_8000_0001_ECX] =
27861ecc 1286 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1287 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1288 .xlevel = 0x80000008,
1289 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1290 },
1291 {
1292 .name = "Opteron_G4",
1293 .level = 0xd,
99b88a17 1294 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1295 .family = 21,
1296 .model = 1,
1297 .stepping = 2,
0514ef2f 1298 .features[FEAT_1_EDX] =
b3a4f0b1 1299 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1300 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1301 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1302 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1303 CPUID_DE | CPUID_FP87,
0514ef2f 1304 .features[FEAT_1_ECX] =
27861ecc 1305 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1306 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1307 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1308 CPUID_EXT_SSE3,
0514ef2f 1309 .features[FEAT_8000_0001_EDX] =
27861ecc 1310 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1311 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1312 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1313 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1314 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1315 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1316 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1317 .features[FEAT_8000_0001_ECX] =
27861ecc 1318 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1319 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1320 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1321 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1322 /* no xsaveopt! */
3eca4642
EH		 1323 .xlevel = 0x8000001A,
1324 .model_id = "AMD Opteron 62xx class CPU",
1325 },
021941b9
AP		 1326 {
1327 .name = "Opteron_G5",
1328 .level = 0xd,
99b88a17 1329 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1330 .family = 21,
1331 .model = 2,
1332 .stepping = 0,
0514ef2f 1333 .features[FEAT_1_EDX] =
b3a4f0b1 1334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1338 CPUID_DE | CPUID_FP87,
0514ef2f 1339 .features[FEAT_1_ECX] =
27861ecc 1340 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1341 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1342 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1343 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1344 .features[FEAT_8000_0001_EDX] =
27861ecc 1345 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1346 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1347 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1348 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1349 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1350 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1351 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1352 .features[FEAT_8000_0001_ECX] =
27861ecc 1353 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1354 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1355 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1356 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1357 /* no xsaveopt! */
021941b9
AP		 1358 .xlevel = 0x8000001A,
1359 .model_id = "AMD Opteron 63xx class CPU",
1360 },
c6dc6f63
AP		 1361};
1362
0668af54
EH		 1363/**
1364 * x86_cpu_compat_set_features:
1365 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1366 * @w: Identifies the feature word to be changed.
1367 * @feat_add: Feature bits to be added to feature word
1368 * @feat_remove: Feature bits to be removed from feature word
1369 *
1370 * Change CPU model feature bits for compatibility.
1371 *
1372 * This function may be used by machine-type compatibility functions
1373 * to enable or disable feature bits on specific CPU models.
1374 */
1375void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1376 uint32_t feat_add, uint32_t feat_remove)
1377{
9576de75 1378 X86CPUDefinition *def;
0668af54
EH		 1379 int i;
1380 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1381 def = &builtin_x86_defs[i];
1382 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1383 def->features[w] |= feat_add;
1384 def->features[w] &= ~feat_remove;
1385 }
1386 }
1387}
1388
4d1b279b
EH		 1389static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1390 bool migratable_only);
1391
d940ee9b
EH		 1392#ifdef CONFIG_KVM
1393
c6dc6f63
AP		 1394static int cpu_x86_fill_model_id(char *str)
1395{
1396 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1397 int i;
1398
1399 for (i = 0; i < 3; i++) {
1400 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1401 memcpy(str + i * 16 + 0, &eax, 4);
1402 memcpy(str + i * 16 + 4, &ebx, 4);
1403 memcpy(str + i * 16 + 8, &ecx, 4);
1404 memcpy(str + i * 16 + 12, &edx, 4);
1405 }
1406 return 0;
1407}
1408
d940ee9b
EH		 1409static X86CPUDefinition host_cpudef;
1410
84f1b92f 1411static Property host_x86_cpu_properties[] = {
120eee7d 1412 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1413 DEFINE_PROP_END_OF_LIST()
1414};
1415
d940ee9b 1416/* class_init for the "host" CPU model
6e746f30 1417 *
d940ee9b 1418 * This function may be called before KVM is initialized.
6e746f30 1419 */
d940ee9b 1420static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1421{
84f1b92f 1422 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1423 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1424 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1425
d940ee9b 1426 xcc->kvm_required = true;
6e746f30 1427
c6dc6f63 1428 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1429 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1430
1431 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1432 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1433 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1434 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1435
d940ee9b 1436 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1437
d940ee9b
EH		 1438 xcc->cpu_def = &host_cpudef;
1439 host_cpudef.cache_info_passthrough = true;
1440
1441 /* level, xlevel, xlevel2, and the feature words are initialized on
1442 * instance_init, because they require KVM to be initialized.
1443 */
84f1b92f
EH		 1444
1445 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1446}
1447
1448static void host_x86_cpu_initfn(Object *obj)
1449{
1450 X86CPU *cpu = X86_CPU(obj);
1451 CPUX86State *env = &cpu->env;
1452 KVMState *s = kvm_state;
d940ee9b
EH		 1453
1454 assert(kvm_enabled());
1455
4d1b279b
EH		 1456 /* We can't fill the features array here because we don't know yet if
1457 * "migratable" is true or false.
1458 */
1459 cpu->host_features = true;
1460
d940ee9b
EH		 1461 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1462 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1463 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1464
d940ee9b 1465 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1466}
1467
d940ee9b
EH		 1468static const TypeInfo host_x86_cpu_type_info = {
1469 .name = X86_CPU_TYPE_NAME("host"),
1470 .parent = TYPE_X86_CPU,
1471 .instance_init = host_x86_cpu_initfn,
1472 .class_init = host_x86_cpu_class_init,
1473};
1474
1475#endif
1476
8459e396 1477static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1478{
8459e396 1479 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1480 int i;
1481
857aee33 1482 for (i = 0; i < 32; ++i) {
c6dc6f63 1483 if (1 << i & mask) {
bffd67b0 1484 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1485 assert(reg);
fefb41bf 1486 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1487 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1488 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1489 f->cpuid_eax, reg,
1490 f->feat_names[i] ? "." : "",
1491 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1492 }
857aee33 1493 }
c6dc6f63
AP		 1494}
1495
95b8519d
AF		 1496static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1497 const char *name, Error **errp)
1498{
1499 X86CPU *cpu = X86_CPU(obj);
1500 CPUX86State *env = &cpu->env;
1501 int64_t value;
1502
1503 value = (env->cpuid_version >> 8) & 0xf;
1504 if (value == 0xf) {
1505 value += (env->cpuid_version >> 20) & 0xff;
1506 }
1507 visit_type_int(v, &value, name, errp);
1508}
1509
71ad61d3
AF		 1510static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1511 const char *name, Error **errp)
ed5e1ec3 1512{
71ad61d3
AF		 1513 X86CPU *cpu = X86_CPU(obj);
1514 CPUX86State *env = &cpu->env;
1515 const int64_t min = 0;
1516 const int64_t max = 0xff + 0xf;
65cd9064 1517 Error *local_err = NULL;
71ad61d3
AF		 1518 int64_t value;
1519
65cd9064
MA		 1520 visit_type_int(v, &value, name, &local_err);
1521 if (local_err) {
1522 error_propagate(errp, local_err);
71ad61d3
AF		 1523 return;
1524 }
1525 if (value < min || value > max) {
1526 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1527 name ? name : "null", value, min, max);
1528 return;
1529 }
1530
ed5e1ec3 1531 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1532 if (value > 0x0f) {
1533 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1534 } else {
71ad61d3 1535 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1536 }
1537}
1538
67e30c83
AF		 1539static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1540 const char *name, Error **errp)
1541{
1542 X86CPU *cpu = X86_CPU(obj);
1543 CPUX86State *env = &cpu->env;
1544 int64_t value;
1545
1546 value = (env->cpuid_version >> 4) & 0xf;
1547 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1548 visit_type_int(v, &value, name, errp);
1549}
1550
c5291a4f
AF		 1551static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1552 const char *name, Error **errp)
b0704cbd 1553{
c5291a4f
AF		 1554 X86CPU *cpu = X86_CPU(obj);
1555 CPUX86State *env = &cpu->env;
1556 const int64_t min = 0;
1557 const int64_t max = 0xff;
65cd9064 1558 Error *local_err = NULL;
c5291a4f
AF		 1559 int64_t value;
1560
65cd9064
MA		 1561 visit_type_int(v, &value, name, &local_err);
1562 if (local_err) {
1563 error_propagate(errp, local_err);
c5291a4f
AF		 1564 return;
1565 }
1566 if (value < min || value > max) {
1567 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1568 name ? name : "null", value, min, max);
1569 return;
1570 }
1571
b0704cbd 1572 env->cpuid_version &= ~0xf00f0;
c5291a4f 1573 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1574}
1575
35112e41
AF		 1576static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1577 void *opaque, const char *name,
1578 Error **errp)
1579{
1580 X86CPU *cpu = X86_CPU(obj);
1581 CPUX86State *env = &cpu->env;
1582 int64_t value;
1583
1584 value = env->cpuid_version & 0xf;
1585 visit_type_int(v, &value, name, errp);
1586}
1587
036e2222
AF		 1588static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1589 void *opaque, const char *name,
1590 Error **errp)
38c3dc46 1591{
036e2222
AF		 1592 X86CPU *cpu = X86_CPU(obj);
1593 CPUX86State *env = &cpu->env;
1594 const int64_t min = 0;
1595 const int64_t max = 0xf;
65cd9064 1596 Error *local_err = NULL;
036e2222
AF		 1597 int64_t value;
1598
65cd9064
MA		 1599 visit_type_int(v, &value, name, &local_err);
1600 if (local_err) {
1601 error_propagate(errp, local_err);
036e2222
AF		 1602 return;
1603 }
1604 if (value < min || value > max) {
1605 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1606 name ? name : "null", value, min, max);
1607 return;
1608 }
1609
38c3dc46 1610 env->cpuid_version &= ~0xf;
036e2222 1611 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1612}
1613
d480e1af
AF		 1614static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1615{
1616 X86CPU *cpu = X86_CPU(obj);
1617 CPUX86State *env = &cpu->env;
1618 char *value;
d480e1af 1619
e42a92ae 1620 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1621 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1622 env->cpuid_vendor3);
d480e1af
AF		 1623 return value;
1624}
1625
1626static void x86_cpuid_set_vendor(Object *obj, const char *value,
1627 Error **errp)
1628{
1629 X86CPU *cpu = X86_CPU(obj);
1630 CPUX86State *env = &cpu->env;
1631 int i;
1632
9df694ee 1633 if (strlen(value) != CPUID_VENDOR_SZ) {
d480e1af
AF		 1634 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1635 "vendor", value);
1636 return;
1637 }
1638
1639 env->cpuid_vendor1 = 0;
1640 env->cpuid_vendor2 = 0;
1641 env->cpuid_vendor3 = 0;
1642 for (i = 0; i < 4; i++) {
1643 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1644 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1645 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1646 }
d480e1af
AF		 1647}
1648
63e886eb
AF		 1649static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1650{
1651 X86CPU *cpu = X86_CPU(obj);
1652 CPUX86State *env = &cpu->env;
1653 char *value;
1654 int i;
1655
1656 value = g_malloc(48 + 1);
1657 for (i = 0; i < 48; i++) {
1658 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1659 }
1660 value[48] = '\0';
1661 return value;
1662}
1663
938d4c25
AF		 1664static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1665 Error **errp)
dcce6675 1666{
938d4c25
AF		 1667 X86CPU *cpu = X86_CPU(obj);
1668 CPUX86State *env = &cpu->env;
dcce6675
AF		 1669 int c, len, i;
1670
1671 if (model_id == NULL) {
1672 model_id = "";
1673 }
1674 len = strlen(model_id);
d0a6acf4 1675 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1676 for (i = 0; i < 48; i++) {
1677 if (i >= len) {
1678 c = '\0';
1679 } else {
1680 c = (uint8_t)model_id[i];
1681 }
1682 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1683 }
1684}
1685
89e48965
AF		 1686static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1687 const char *name, Error **errp)
1688{
1689 X86CPU *cpu = X86_CPU(obj);
1690 int64_t value;
1691
1692 value = cpu->env.tsc_khz * 1000;
1693 visit_type_int(v, &value, name, errp);
1694}
1695
1696static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1697 const char *name, Error **errp)
1698{
1699 X86CPU *cpu = X86_CPU(obj);
1700 const int64_t min = 0;
2e84849a 1701 const int64_t max = INT64_MAX;
65cd9064 1702 Error *local_err = NULL;
89e48965
AF		 1703 int64_t value;
1704
65cd9064
MA		 1705 visit_type_int(v, &value, name, &local_err);
1706 if (local_err) {
1707 error_propagate(errp, local_err);
89e48965
AF		 1708 return;
1709 }
1710 if (value < min || value > max) {
1711 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1712 name ? name : "null", value, min, max);
1713 return;
1714 }
1715
1716 cpu->env.tsc_khz = value / 1000;
1717}
1718
31050930
IM		 1719static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1720 const char *name, Error **errp)
1721{
1722 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1723 int64_t value = cpu->apic_id;
31050930
IM		 1724
1725 visit_type_int(v, &value, name, errp);
1726}
1727
1728static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1729 const char *name, Error **errp)
1730{
1731 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1732 DeviceState *dev = DEVICE(obj);
31050930
IM		 1733 const int64_t min = 0;
1734 const int64_t max = UINT32_MAX;
1735 Error *error = NULL;
1736 int64_t value;
1737
8d6d4980
IM		 1738 if (dev->realized) {
1739 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1740 "it was realized", name, object_get_typename(obj));
1741 return;
1742 }
1743
31050930
IM		 1744 visit_type_int(v, &value, name, &error);
1745 if (error) {
1746 error_propagate(errp, error);
1747 return;
1748 }
1749 if (value < min || value > max) {
1750 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1751 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1752 object_get_typename(obj), name, value, min, max);
1753 return;
1754 }
1755
7e72a45c 1756 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1757 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1758 return;
1759 }
7e72a45c 1760 cpu->apic_id = value;
31050930
IM		 1761}
1762
7e5292b5 1763/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1764static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1765 const char *name, Error **errp)
1766{
7e5292b5 1767 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1768 FeatureWord w;
1769 Error *err = NULL;
1770 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1771 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1772 X86CPUFeatureWordInfoList *list = NULL;
1773
1774 for (w = 0; w < FEATURE_WORDS; w++) {
1775 FeatureWordInfo *wi = &feature_word_info[w];
1776 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1777 qwi->cpuid_input_eax = wi->cpuid_eax;
1778 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1779 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1780 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1781 qwi->features = array[w];
8e8aba50
EH		 1782
1783 /* List will be in reverse order, but order shouldn't matter */
1784 list_entries[w].next = list;
1785 list_entries[w].value = &word_infos[w];
1786 list = &list_entries[w];
1787 }
1788
1789 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1790 error_propagate(errp, err);
1791}
1792
c8f0f88e
IM		 1793static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1794 const char *name, Error **errp)
1795{
1796 X86CPU *cpu = X86_CPU(obj);
1797 int64_t value = cpu->hyperv_spinlock_attempts;
1798
1799 visit_type_int(v, &value, name, errp);
1800}
1801
1802static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1803 const char *name, Error **errp)
1804{
1805 const int64_t min = 0xFFF;
1806 const int64_t max = UINT_MAX;
1807 X86CPU *cpu = X86_CPU(obj);
1808 Error *err = NULL;
1809 int64_t value;
1810
1811 visit_type_int(v, &value, name, &err);
1812 if (err) {
1813 error_propagate(errp, err);
1814 return;
1815 }
1816
1817 if (value < min || value > max) {
1818 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1819 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1820 object_get_typename(obj), name ? name : "null",
1821 value, min, max);
c8f0f88e
IM		 1822 return;
1823 }
1824 cpu->hyperv_spinlock_attempts = value;
1825}
1826
1827static PropertyInfo qdev_prop_spinlocks = {
1828 .name = "int",
1829 .get = x86_get_hv_spinlocks,
1830 .set = x86_set_hv_spinlocks,
1831};
1832
72ac2e87
IM		 1833/* Convert all '_' in a feature string option name to '-', to make feature
1834 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1835 */
1836static inline void feat2prop(char *s)
1837{
1838 while ((s = strchr(s, '_'))) {
1839 *s = '-';
1840 }
1841}
1842
8f961357
EH		 1843/* Parse "+feature,-feature,feature=foo" CPU feature string
1844 */
94a444b2
AF		 1845static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1846 Error **errp)
8f961357 1847{
94a444b2 1848 X86CPU *cpu = X86_CPU(cs);
8f961357 1849 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1850 FeatureWord w;
8f961357 1851 /* Features to be added */
077c68c3 1852 FeatureWordArray plus_features = { 0 };
8f961357 1853 /* Features to be removed */
5ef57876 1854 FeatureWordArray minus_features = { 0 };
8f961357 1855 uint32_t numvalue;
a91987c2 1856 CPUX86State *env = &cpu->env;
94a444b2 1857 Error *local_err = NULL;
8f961357 1858
8f961357 1859 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1860
1861 while (featurestr) {
1862 char *val;
1863 if (featurestr[0] == '+') {
c00c94ab 1864 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1865 } else if (featurestr[0] == '-') {
c00c94ab 1866 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1867 } else if ((val = strchr(featurestr, '='))) {
1868 *val = 0; val++;
72ac2e87 1869 feat2prop(featurestr);
d024d209 1870 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1871 char *err;
a91987c2
IM		 1872 char num[32];
1873
c6dc6f63
AP		 1874 numvalue = strtoul(val, &err, 0);
1875 if (!*val || *err) {
6b1dd54b
PB		 1876 error_setg(errp, "bad numerical value %s", val);
1877 return;
c6dc6f63
AP		 1878 }
1879 if (numvalue < 0x80000000) {
94a444b2
AF		 1880 error_report("xlevel value shall always be >= 0x80000000"
1881 ", fixup will be removed in future versions");
2f7a21c4 1882 numvalue += 0x80000000;
c6dc6f63 1883 }
a91987c2 1884 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1885 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1886 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1887 int64_t tsc_freq;
1888 char *err;
a91987c2 1889 char num[32];
b862d1fe
JR		 1890
1891 tsc_freq = strtosz_suffix_unit(val, &err,
1892 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1893 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1894 error_setg(errp, "bad numerical value %s", val);
1895 return;
b862d1fe 1896 }
a91987c2 1897 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1898 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1899 &local_err);
72ac2e87 1900 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1901 char *err;
92067bf4 1902 const int min = 0xFFF;
c8f0f88e 1903 char num[32];
28f52cc0
VR		 1904 numvalue = strtoul(val, &err, 0);
1905 if (!*val || *err) {
6b1dd54b
PB		 1906 error_setg(errp, "bad numerical value %s", val);
1907 return;
28f52cc0 1908 }
92067bf4 1909 if (numvalue < min) {
94a444b2 1910 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1911 ", fixup will be removed in future versions",
1912 min);
92067bf4
IM		 1913 numvalue = min;
1914 }
c8f0f88e 1915 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1916 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1917 } else {
94a444b2 1918 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1919 }
c6dc6f63 1920 } else {
258f5abe 1921 feat2prop(featurestr);
94a444b2 1922 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1923 }
94a444b2
AF		 1924 if (local_err) {
1925 error_propagate(errp, local_err);
6b1dd54b 1926 return;
c6dc6f63
AP		 1927 }
1928 featurestr = strtok(NULL, ",");
1929 }
e1c224b4 1930
4d1b279b
EH		 1931 if (cpu->host_features) {
1932 for (w = 0; w < FEATURE_WORDS; w++) {
1933 env->features[w] =
1934 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1935 }
1936 }
1937
e1c224b4
EH		 1938 for (w = 0; w < FEATURE_WORDS; w++) {
1939 env->features[w] |= plus_features[w];
1940 env->features[w] &= ~minus_features[w];
1941 }
c6dc6f63
AP		 1942}
1943
8c3329e5 1944/* Print all cpuid feature names in featureset
c6dc6f63 1945 */
8c3329e5 1946static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1947{
8c3329e5
EH		 1948 int bit;
1949 bool first = true;
1950
1951 for (bit = 0; bit < 32; bit++) {
1952 if (featureset[bit]) {
1953 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1954 first = false;
c6dc6f63 1955 }
8c3329e5 1956 }
c6dc6f63
AP		 1957}
1958
e916cbf8
PM		 1959/* generate CPU information. */
1960void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1961{
9576de75 1962 X86CPUDefinition *def;
c6dc6f63 1963 char buf[256];
7fc9b714 1964 int i;
c6dc6f63 1965
7fc9b714
AF		 1966 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1967 def = &builtin_x86_defs[i];
c04321b3 1968 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1969 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1970 }
21ad7789
JK		 1971#ifdef CONFIG_KVM
1972 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1973 "KVM processor with all supported host features "
1974 "(only available in KVM mode)");
1975#endif
1976
6cdf8854 1977 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1978 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1979 FeatureWordInfo *fw = &feature_word_info[i];
1980
8c3329e5
EH		 1981 (*cpu_fprintf)(f, " ");
1982 listflags(f, cpu_fprintf, fw->feat_names);
1983 (*cpu_fprintf)(f, "\n");
3af60be2 1984 }
c6dc6f63
AP		 1985}
1986
76b64a7a 1987CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1988{
1989 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1990 X86CPUDefinition *def;
7fc9b714 1991 int i;
e3966126 1992
7fc9b714 1993 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1994 CpuDefinitionInfoList *entry;
1995 CpuDefinitionInfo *info;
1996
7fc9b714 1997 def = &builtin_x86_defs[i];
e3966126
AL		 1998 info = g_malloc0(sizeof(*info));
1999 info->name = g_strdup(def->name);
2000
2001 entry = g_malloc0(sizeof(*entry));
2002 entry->value = info;
2003 entry->next = cpu_list;
2004 cpu_list = entry;
2005 }
2006
2007 return cpu_list;
2008}
2009
84f1b92f
EH		 2010static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2011 bool migratable_only)
27418adf
EH		 2012{
2013 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2014 uint32_t r;
27418adf 2015
fefb41bf 2016 if (kvm_enabled()) {
84f1b92f
EH		 2017 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2018 wi->cpuid_ecx,
2019 wi->cpuid_reg);
fefb41bf 2020 } else if (tcg_enabled()) {
84f1b92f 2021 r = wi->tcg_features;
fefb41bf
EH		 2022 } else {
2023 return ~0;
2024 }
84f1b92f
EH		 2025 if (migratable_only) {
2026 r &= x86_cpu_get_migratable_flags(w);
2027 }
2028 return r;
27418adf
EH		 2029}
2030
51f63aed
EH		 2031/*
2032 * Filters CPU feature words based on host availability of each feature.
2033 *
51f63aed
EH		 2034 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2035 */
27418adf 2036static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2037{
2038 CPUX86State *env = &cpu->env;
bd87d2a2 2039 FeatureWord w;
51f63aed
EH		 2040 int rv = 0;
2041
bd87d2a2 2042 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2043 uint32_t host_feat =
2044 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2045 uint32_t requested_features = env->features[w];
2046 env->features[w] &= host_feat;
2047 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2048 if (cpu->filtered_features[w]) {
2049 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2050 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2051 }
2052 rv = 1;
2053 }
bd87d2a2 2054 }
51f63aed
EH		 2055
2056 return rv;
bc74b7db 2057}
bc74b7db 2058
d940ee9b 2059/* Load data from X86CPUDefinition
c080e30e 2060 */
d940ee9b 2061static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2062{
61dcd775 2063 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2064 const char *vendor;
2065 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2066 FeatureWord w;
c6dc6f63 2067
2d64255b
AF		 2068 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2069 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2070 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2071 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2072 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2073 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
787aaf57 2074 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2075 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2076 for (w = 0; w < FEATURE_WORDS; w++) {
2077 env->features[w] = def->features[w];
2078 }
82beb536 2079
9576de75 2080 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2081 if (kvm_enabled()) {
5fcca9ff
EH		 2082 FeatureWord w;
2083 for (w = 0; w < FEATURE_WORDS; w++) {
2084 env->features[w] |= kvm_default_features[w];
136a7e9a 2085 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2086 }
82beb536 2087 }
5fcca9ff 2088
82beb536 2089 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2090
2091 /* sysenter isn't supported in compatibility mode on AMD,
2092 * syscall isn't supported in compatibility mode on Intel.
2093 * Normally we advertise the actual CPU vendor, but you can
2094 * override this using the 'vendor' property if you want to use
2095 * KVM's sysenter/syscall emulation in compatibility mode and
2096 * when doing cross vendor migration
2097 */
74f54bc4 2098 vendor = def->vendor;
7c08db30
EH		 2099 if (kvm_enabled()) {
2100 uint32_t ebx = 0, ecx = 0, edx = 0;
2101 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2102 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2103 vendor = host_vendor;
2104 }
2105
2106 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2107
c6dc6f63
AP		 2108}
2109
e1570d00 2110X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2111{
2d64255b 2112 X86CPU *cpu = NULL;
d940ee9b 2113 X86CPUClass *xcc;
500050d1 2114 ObjectClass *oc;
2d64255b
AF		 2115 gchar **model_pieces;
2116 char *name, *features;
5c3c6a68
AF		 2117 Error *error = NULL;
2118
2d64255b
AF		 2119 model_pieces = g_strsplit(cpu_model, ",", 2);
2120 if (!model_pieces[0]) {
2121 error_setg(&error, "Invalid/empty CPU model name");
2122 goto out;
2123 }
2124 name = model_pieces[0];
2125 features = model_pieces[1];
2126
500050d1
AF		 2127 oc = x86_cpu_class_by_name(name);
2128 if (oc == NULL) {
2129 error_setg(&error, "Unable to find CPU definition: %s", name);
2130 goto out;
2131 }
d940ee9b
EH		 2132 xcc = X86_CPU_CLASS(oc);
2133
2134 if (xcc->kvm_required && !kvm_enabled()) {
2135 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2136 goto out;
2137 }
2138
d940ee9b
EH		 2139 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2140
94a444b2 2141 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2142 if (error) {
2143 goto out;
5c3c6a68
AF		 2144 }
2145
7f833247 2146out:
cd7b87ff
AF		 2147 if (error != NULL) {
2148 error_propagate(errp, error);
500050d1
AF		 2149 if (cpu) {
2150 object_unref(OBJECT(cpu));
2151 cpu = NULL;
2152 }
cd7b87ff 2153 }
7f833247
IM		 2154 g_strfreev(model_pieces);
2155 return cpu;
2156}
2157
0856579c 2158X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2159{
2160 Error *error = NULL;
2161 X86CPU *cpu;
2162
e1570d00 2163 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2164 if (error) {
0856579c 2165 goto out;
9c235e83 2166 }
7f833247 2167
7f833247 2168 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2169
0856579c
PM		 2170out:
2171 if (error) {
2172 error_report_err(error);
2173 if (cpu != NULL) {
2174 object_unref(OBJECT(cpu));
2175 cpu = NULL;
2176 }
18b0e4e7 2177 }
0856579c 2178 return cpu;
5c3c6a68
AF		 2179}
2180
d940ee9b
EH		 2181static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2182{
2183 X86CPUDefinition *cpudef = data;
2184 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2185
2186 xcc->cpu_def = cpudef;
2187}
2188
2189static void x86_register_cpudef_type(X86CPUDefinition *def)
2190{
2191 char *typename = x86_cpu_type_name(def->name);
2192 TypeInfo ti = {
2193 .name = typename,
2194 .parent = TYPE_X86_CPU,
2195 .class_init = x86_cpu_cpudef_class_init,
2196 .class_data = def,
2197 };
2198
2199 type_register(&ti);
2200 g_free(typename);
2201}
2202
c6dc6f63 2203#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2204
0e26b7b8
BS		 2205void cpu_clear_apic_feature(CPUX86State *env)
2206{
0514ef2f 2207 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2208}
2209
c6dc6f63
AP		 2210#endif /* !CONFIG_USER_ONLY */
2211
c04321b3 2212/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2213 */
2214void x86_cpudef_setup(void)
2215{
93bfef4c
CV		 2216 int i, j;
2217 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2218
2219 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2220 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2221
2222 /* Look for specific "cpudef" models that */
09faecf2 2223 /* have the QEMU version in .model_id */
93bfef4c 2224 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2225 if (strcmp(model_with_versions[j], def->name) == 0) {
2226 pstrcpy(def->model_id, sizeof(def->model_id),
2227 "QEMU Virtual CPU version ");
2228 pstrcat(def->model_id, sizeof(def->model_id),
2229 qemu_get_version());
93bfef4c
CV		 2230 break;
2231 }
2232 }
c6dc6f63 2233 }
c6dc6f63
AP		 2234}
2235
c6dc6f63
AP		 2236void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2237 uint32_t *eax, uint32_t *ebx,
2238 uint32_t *ecx, uint32_t *edx)
2239{
a60f24b5
AF		 2240 X86CPU *cpu = x86_env_get_cpu(env);
2241 CPUState *cs = CPU(cpu);
2242
c6dc6f63
AP		 2243 /* test if maximum index reached */
2244 if (index & 0x80000000) {
b3baa152
BW		 2245 if (index > env->cpuid_xlevel) {
2246 if (env->cpuid_xlevel2 > 0) {
2247 /* Handle the Centaur's CPUID instruction. */
2248 if (index > env->cpuid_xlevel2) {
2249 index = env->cpuid_xlevel2;
2250 } else if (index < 0xC0000000) {
2251 index = env->cpuid_xlevel;
2252 }
2253 } else {
57f26ae7
EH		 2254 /* Intel documentation states that invalid EAX input will
2255 * return the same information as EAX=cpuid_level
2256 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2257 */
2258 index = env->cpuid_level;
b3baa152
BW		 2259 }
2260 }
c6dc6f63
AP		 2261 } else {
2262 if (index > env->cpuid_level)
2263 index = env->cpuid_level;
2264 }
2265
2266 switch(index) {
2267 case 0:
2268 *eax = env->cpuid_level;
5eb2f7a4
EH		 2269 *ebx = env->cpuid_vendor1;
2270 *edx = env->cpuid_vendor2;
2271 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2272 break;
2273 case 1:
2274 *eax = env->cpuid_version;
7e72a45c
EH		 2275 *ebx = (cpu->apic_id << 24) |
2276 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2277 *ecx = env->features[FEAT_1_ECX];
2278 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2279 if (cs->nr_cores * cs->nr_threads > 1) {
2280 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2281 *edx |= 1 << 28; /* HTT bit */
2282 }
2283 break;
2284 case 2:
2285 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2286 if (cpu->cache_info_passthrough) {
2287 host_cpuid(index, 0, eax, ebx, ecx, edx);
2288 break;
2289 }
5e891bf8 2290 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2291 *ebx = 0;
2292 *ecx = 0;
5e891bf8
EH		 2293 *edx = (L1D_DESCRIPTOR << 16) | \
2294 (L1I_DESCRIPTOR << 8) | \
2295 (L2_DESCRIPTOR);
c6dc6f63
AP		 2296 break;
2297 case 4:
2298 /* cache info: needed for Core compatibility */
787aaf57
BC		 2299 if (cpu->cache_info_passthrough) {
2300 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2301 *eax &= ~0xFC000000;
c6dc6f63 2302 } else {
2f7a21c4 2303 *eax = 0;
76c2975a 2304 switch (count) {
c6dc6f63 2305 case 0: /* L1 dcache info */
5e891bf8
EH		 2306 *eax |= CPUID_4_TYPE_DCACHE | \
2307 CPUID_4_LEVEL(1) | \
2308 CPUID_4_SELF_INIT_LEVEL;
2309 *ebx = (L1D_LINE_SIZE - 1) | \
2310 ((L1D_PARTITIONS - 1) << 12) | \
2311 ((L1D_ASSOCIATIVITY - 1) << 22);
2312 *ecx = L1D_SETS - 1;
2313 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2314 break;
2315 case 1: /* L1 icache info */
5e891bf8
EH		 2316 *eax |= CPUID_4_TYPE_ICACHE | \
2317 CPUID_4_LEVEL(1) | \
2318 CPUID_4_SELF_INIT_LEVEL;
2319 *ebx = (L1I_LINE_SIZE - 1) | \
2320 ((L1I_PARTITIONS - 1) << 12) | \
2321 ((L1I_ASSOCIATIVITY - 1) << 22);
2322 *ecx = L1I_SETS - 1;
2323 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2324 break;
2325 case 2: /* L2 cache info */
5e891bf8
EH		 2326 *eax |= CPUID_4_TYPE_UNIFIED | \
2327 CPUID_4_LEVEL(2) | \
2328 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2329 if (cs->nr_threads > 1) {
2330 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2331 }
5e891bf8
EH		 2332 *ebx = (L2_LINE_SIZE - 1) | \
2333 ((L2_PARTITIONS - 1) << 12) | \
2334 ((L2_ASSOCIATIVITY - 1) << 22);
2335 *ecx = L2_SETS - 1;
2336 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2337 break;
2338 default: /* end of info */
2339 *eax = 0;
2340 *ebx = 0;
2341 *ecx = 0;
2342 *edx = 0;
2343 break;
76c2975a
PB		 2344 }
2345 }
2346
2347 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2348 if ((*eax & 31) && cs->nr_cores > 1) {
2349 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2350 }
2351 break;
2352 case 5:
2353 /* mwait info: needed for Core compatibility */
2354 *eax = 0; /* Smallest monitor-line size in bytes */
2355 *ebx = 0; /* Largest monitor-line size in bytes */
2356 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2357 *edx = 0;
2358 break;
2359 case 6:
2360 /* Thermal and Power Leaf */
2361 *eax = 0;
2362 *ebx = 0;
2363 *ecx = 0;
2364 *edx = 0;
2365 break;
f7911686 2366 case 7:
13526728
EH		 2367 /* Structured Extended Feature Flags Enumeration Leaf */
2368 if (count == 0) {
2369 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2370 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2371 *ecx = 0; /* Reserved */
2372 *edx = 0; /* Reserved */
f7911686
YW		 2373 } else {
2374 *eax = 0;
2375 *ebx = 0;
2376 *ecx = 0;
2377 *edx = 0;
2378 }
2379 break;
c6dc6f63
AP		 2380 case 9:
2381 /* Direct Cache Access Information Leaf */
2382 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2383 *ebx = 0;
2384 *ecx = 0;
2385 *edx = 0;
2386 break;
2387 case 0xA:
2388 /* Architectural Performance Monitoring Leaf */
9337e3b6 2389 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2390 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2391
2392 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2393 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2394 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2395 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2396 } else {
2397 *eax = 0;
2398 *ebx = 0;
2399 *ecx = 0;
2400 *edx = 0;
2401 }
c6dc6f63 2402 break;
2560f19f
PB		 2403 case 0xD: {
2404 KVMState *s = cs->kvm_state;
2405 uint64_t kvm_mask;
2406 int i;
2407
51e49430 2408 /* Processor Extended State */
2560f19f
PB		 2409 *eax = 0;
2410 *ebx = 0;
2411 *ecx = 0;
2412 *edx = 0;
2413 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2414 break;
2415 }
2560f19f
PB		 2416 kvm_mask =
2417 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2418 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2419
2560f19f
PB		 2420 if (count == 0) {
2421 *ecx = 0x240;
2422 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2423 const ExtSaveArea *esa = &ext_save_areas[i];
2424 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2425 (kvm_mask & (1 << i)) != 0) {
2426 if (i < 32) {
2427 *eax |= 1 << i;
2428 } else {
2429 *edx |= 1 << (i - 32);
2430 }
2431 *ecx = MAX(*ecx, esa->offset + esa->size);
2432 }
2433 }
2434 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2435 *ebx = *ecx;
2436 } else if (count == 1) {
0bb0b2d2 2437 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2438 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2439 const ExtSaveArea *esa = &ext_save_areas[count];
2440 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2441 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2442 *eax = esa->size;
2443 *ebx = esa->offset;
2560f19f 2444 }
51e49430
SY		 2445 }
2446 break;
2560f19f 2447 }
c6dc6f63
AP		 2448 case 0x80000000:
2449 *eax = env->cpuid_xlevel;
2450 *ebx = env->cpuid_vendor1;
2451 *edx = env->cpuid_vendor2;
2452 *ecx = env->cpuid_vendor3;
2453 break;
2454 case 0x80000001:
2455 *eax = env->cpuid_version;
2456 *ebx = 0;
0514ef2f
EH		 2457 *ecx = env->features[FEAT_8000_0001_ECX];
2458 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2459
2460 /* The Linux kernel checks for the CMPLegacy bit and
2461 * discards multiple thread information if it is set.
2462 * So dont set it here for Intel to make Linux guests happy.
2463 */
ce3960eb 2464 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2465 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2466 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2467 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2468 *ecx |= 1 << 1; /* CmpLegacy bit */
2469 }
2470 }
c6dc6f63
AP		 2471 break;
2472 case 0x80000002:
2473 case 0x80000003:
2474 case 0x80000004:
2475 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2476 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2477 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2478 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2479 break;
2480 case 0x80000005:
2481 /* cache info (L1 cache) */
787aaf57
BC		 2482 if (cpu->cache_info_passthrough) {
2483 host_cpuid(index, 0, eax, ebx, ecx, edx);
2484 break;
2485 }
5e891bf8
EH		 2486 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2487 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2488 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2489 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2490 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2491 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2492 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2493 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2494 break;
2495 case 0x80000006:
2496 /* cache info (L2 cache) */
787aaf57
BC		 2497 if (cpu->cache_info_passthrough) {
2498 host_cpuid(index, 0, eax, ebx, ecx, edx);
2499 break;
2500 }
5e891bf8
EH		 2501 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2502 (L2_DTLB_2M_ENTRIES << 16) | \
2503 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2504 (L2_ITLB_2M_ENTRIES);
2505 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2506 (L2_DTLB_4K_ENTRIES << 16) | \
2507 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2508 (L2_ITLB_4K_ENTRIES);
2509 *ecx = (L2_SIZE_KB_AMD << 16) | \
2510 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2511 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2512 *edx = ((L3_SIZE_KB/512) << 18) | \
2513 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2514 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2515 break;
303752a9
MT		 2516 case 0x80000007:
2517 *eax = 0;
2518 *ebx = 0;
2519 *ecx = 0;
2520 *edx = env->features[FEAT_8000_0007_EDX];
2521 break;
c6dc6f63
AP		 2522 case 0x80000008:
2523 /* virtual & phys address size in low 2 bytes. */
2524/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2525 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2526 /* 64 bit processor */
2527/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2528 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2529 } else {
0514ef2f 2530 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2531 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2532 } else {
c6dc6f63 2533 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2534 }
c6dc6f63
AP		 2535 }
2536 *ebx = 0;
2537 *ecx = 0;
2538 *edx = 0;
ce3960eb
AF		 2539 if (cs->nr_cores * cs->nr_threads > 1) {
2540 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2541 }
2542 break;
2543 case 0x8000000A:
0514ef2f 2544 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2545 *eax = 0x00000001; /* SVM Revision */
2546 *ebx = 0x00000010; /* nr of ASIDs */
2547 *ecx = 0;
0514ef2f 2548 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2549 } else {
2550 *eax = 0;
2551 *ebx = 0;
2552 *ecx = 0;
2553 *edx = 0;
2554 }
c6dc6f63 2555 break;
b3baa152
BW		 2556 case 0xC0000000:
2557 *eax = env->cpuid_xlevel2;
2558 *ebx = 0;
2559 *ecx = 0;
2560 *edx = 0;
2561 break;
2562 case 0xC0000001:
2563 /* Support for VIA CPU's CPUID instruction */
2564 *eax = env->cpuid_version;
2565 *ebx = 0;
2566 *ecx = 0;
0514ef2f 2567 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2568 break;
2569 case 0xC0000002:
2570 case 0xC0000003:
2571 case 0xC0000004:
2572 /* Reserved for the future, and now filled with zero */
2573 *eax = 0;
2574 *ebx = 0;
2575 *ecx = 0;
2576 *edx = 0;
2577 break;
c6dc6f63
AP		 2578 default:
2579 /* reserved values: zero */
2580 *eax = 0;
2581 *ebx = 0;
2582 *ecx = 0;
2583 *edx = 0;
2584 break;
2585 }
2586}
5fd2087a
AF		 2587
2588/* CPUClass::reset() */
2589static void x86_cpu_reset(CPUState *s)
2590{
2591 X86CPU *cpu = X86_CPU(s);
2592 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2593 CPUX86State *env = &cpu->env;
c1958aea
AF		 2594 int i;
2595
5fd2087a
AF		 2596 xcc->parent_reset(s);
2597
43175fa9 2598 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2599
00c8cb0a 2600 tlb_flush(s, 1);
c1958aea
AF		 2601
2602 env->old_exception = -1;
2603
2604 /* init to reset state */
2605
2606#ifdef CONFIG_SOFTMMU
2607 env->hflags |= HF_SOFTMMU_MASK;
2608#endif
2609 env->hflags2 |= HF2_GIF_MASK;
2610
2611 cpu_x86_update_cr0(env, 0x60000010);
2612 env->a20_mask = ~0x0;
2613 env->smbase = 0x30000;
2614
2615 env->idt.limit = 0xffff;
2616 env->gdt.limit = 0xffff;
2617 env->ldt.limit = 0xffff;
2618 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2619 env->tr.limit = 0xffff;
2620 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2621
2622 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2623 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2624 DESC_R_MASK | DESC_A_MASK);
2625 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2626 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2627 DESC_A_MASK);
2628 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2629 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2630 DESC_A_MASK);
2631 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2632 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2633 DESC_A_MASK);
2634 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2635 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2636 DESC_A_MASK);
2637 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2638 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2639 DESC_A_MASK);
2640
2641 env->eip = 0xfff0;
2642 env->regs[R_EDX] = env->cpuid_version;
2643
2644 env->eflags = 0x2;
2645
2646 /* FPU init */
2647 for (i = 0; i < 8; i++) {
2648 env->fptags[i] = 1;
2649 }
5bde1407 2650 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2651
2652 env->mxcsr = 0x1f80;
c74f41bb 2653 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2654
2655 env->pat = 0x0007040600070406ULL;
2656 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2657
2658 memset(env->dr, 0, sizeof(env->dr));
2659 env->dr[6] = DR6_FIXED_1;
2660 env->dr[7] = DR7_FIXED_1;
b3310ab3 2661 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2662 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2663
05e7e819 2664 env->xcr0 = 1;
0522604b 2665
9db2efd9
AW		 2666 /*
2667 * SDM 11.11.5 requires:
2668 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2669 * - IA32_MTRR_PHYSMASKn.V = 0
2670 * All other bits are undefined. For simplification, zero it all.
2671 */
2672 env->mtrr_deftype = 0;
2673 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2674 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2675
dd673288
IM		 2676#if !defined(CONFIG_USER_ONLY)
2677 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2678 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2679
259186a7 2680 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2681
2682 if (kvm_enabled()) {
2683 kvm_arch_reset_vcpu(cpu);
2684 }
dd673288 2685#endif
5fd2087a
AF		 2686}
2687
dd673288
IM		 2688#ifndef CONFIG_USER_ONLY
2689bool cpu_is_bsp(X86CPU *cpu)
2690{
02e51483 2691 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2692}
65dee380
IM		 2693
2694/* TODO: remove me, when reset over QOM tree is implemented */
2695static void x86_cpu_machine_reset_cb(void *opaque)
2696{
2697 X86CPU *cpu = opaque;
2698 cpu_reset(CPU(cpu));
2699}
dd673288
IM		 2700#endif
2701
de024815
AF		 2702static void mce_init(X86CPU *cpu)
2703{
2704 CPUX86State *cenv = &cpu->env;
2705 unsigned int bank;
2706
2707 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2708 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2709 (CPUID_MCE | CPUID_MCA)) {
2710 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2711 cenv->mcg_ctl = ~(uint64_t)0;
2712 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2713 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2714 }
2715 }
2716}
2717
bdeec802 2718#ifndef CONFIG_USER_ONLY
d3c64d6a 2719static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2720{
53a89e26 2721 DeviceState *dev = DEVICE(cpu);
449994eb 2722 APICCommonState *apic;
bdeec802
IM		 2723 const char *apic_type = "apic";
2724
2725 if (kvm_irqchip_in_kernel()) {
2726 apic_type = "kvm-apic";
2727 } else if (xen_enabled()) {
2728 apic_type = "xen-apic";
2729 }
2730
02e51483
CF		 2731 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2732 if (cpu->apic_state == NULL) {
bdeec802
IM		 2733 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2734 return;
2735 }
2736
2737 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2738 OBJECT(cpu->apic_state), NULL);
7e72a45c 2739 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2740 /* TODO: convert to link<> */
02e51483 2741 apic = APIC_COMMON(cpu->apic_state);
60671e58 2742 apic->cpu = cpu;
d3c64d6a
IM		 2743}
2744
2745static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2746{
02e51483 2747 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2748 return;
2749 }
6e8e2651
MA		 2750 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2751 errp);
bdeec802 2752}
d3c64d6a
IM		 2753#else
2754static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2755{
2756}
bdeec802
IM		 2757#endif
2758
e48638fd
WH		 2759
2760#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2761 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2762 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2763#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2764 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2765 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2766static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2767{
14a10fc3 2768 CPUState *cs = CPU(dev);
2b6f294c
AF		 2769 X86CPU *cpu = X86_CPU(dev);
2770 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2771 CPUX86State *env = &cpu->env;
2b6f294c 2772 Error *local_err = NULL;
e48638fd 2773 static bool ht_warned;
b34d12d1 2774
9886e834
EH		 2775 if (cpu->apic_id < 0) {
2776 error_setg(errp, "apic-id property was not initialized properly");
2777 return;
2778 }
2779
0514ef2f 2780 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2781 env->cpuid_level = 7;
2782 }
7a059953 2783
9b15cd9e
IM		 2784 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2785 * CPUID[1].EDX.
2786 */
e48638fd 2787 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2788 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2789 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2790 & CPUID_EXT2_AMD_ALIASES);
2791 }
2792
fefb41bf
EH		 2793
2794 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2795 error_setg(&local_err,
2796 kvm_enabled() ?
2797 "Host doesn't support requested features" :
2798 "TCG doesn't support requested features");
2799 goto out;
4586f157
IM		 2800 }
2801
65dee380
IM		 2802#ifndef CONFIG_USER_ONLY
2803 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2804
0514ef2f 2805 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2806 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2807 if (local_err != NULL) {
4dc1f449 2808 goto out;
bdeec802
IM		 2809 }
2810 }
65dee380
IM		 2811#endif
2812
7a059953 2813 mce_init(cpu);
14a10fc3 2814 qemu_init_vcpu(cs);
d3c64d6a 2815
e48638fd
WH		 2816 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2817 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2818 * based on inputs (sockets,cores,threads), it is still better to gives
2819 * users a warning.
2820 *
2821 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2822 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2823 */
2824 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2825 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2826 " -smp options properly.");
2827 ht_warned = true;
2828 }
2829
d3c64d6a
IM		 2830 x86_cpu_apic_realize(cpu, &local_err);
2831 if (local_err != NULL) {
2832 goto out;
2833 }
14a10fc3 2834 cpu_reset(cs);
2b6f294c 2835
4dc1f449
IM		 2836 xcc->parent_realize(dev, &local_err);
2837out:
2838 if (local_err != NULL) {
2839 error_propagate(errp, local_err);
2840 return;
2841 }
7a059953
AF		 2842}
2843
de024815
AF		 2844static void x86_cpu_initfn(Object *obj)
2845{
55e5c285 2846 CPUState *cs = CPU(obj);
de024815 2847 X86CPU *cpu = X86_CPU(obj);
d940ee9b 2848 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 2849 CPUX86State *env = &cpu->env;
d65e9815 2850 static int inited;
de024815 2851
c05efcb1 2852 cs->env_ptr = env;
de024815 2853 cpu_exec_init(env);
71ad61d3
AF		 2854
2855 object_property_add(obj, "family", "int",
95b8519d 2856 x86_cpuid_version_get_family,
71ad61d3 2857 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 2858 object_property_add(obj, "model", "int",
67e30c83 2859 x86_cpuid_version_get_model,
c5291a4f 2860 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 2861 object_property_add(obj, "stepping", "int",
35112e41 2862 x86_cpuid_version_get_stepping,
036e2222 2863 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 2864 object_property_add_str(obj, "vendor",
2865 x86_cpuid_get_vendor,
2866 x86_cpuid_set_vendor, NULL);
938d4c25 2867 object_property_add_str(obj, "model-id",
63e886eb 2868 x86_cpuid_get_model_id,
938d4c25 2869 x86_cpuid_set_model_id, NULL);
89e48965
AF		 2870 object_property_add(obj, "tsc-frequency", "int",
2871 x86_cpuid_get_tsc_freq,
2872 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 2873 object_property_add(obj, "apic-id", "int",
2874 x86_cpuid_get_apic_id,
2875 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 2876 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2877 x86_cpu_get_feature_words,
7e5292b5
EH		 2878 NULL, NULL, (void *)env->features, NULL);
2879 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2880 x86_cpu_get_feature_words,
2881 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 2882
92067bf4 2883 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 2884
9886e834
EH		 2885#ifndef CONFIG_USER_ONLY
2886 /* Any code creating new X86CPU objects have to set apic-id explicitly */
2887 cpu->apic_id = -1;
2888#endif
2889
d940ee9b
EH		 2890 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2891
d65e9815
IM		 2892 /* init various static tables used in TCG mode */
2893 if (tcg_enabled() && !inited) {
2894 inited = 1;
2895 optimize_flags_init();
d65e9815 2896 }
de024815
AF		 2897}
2898
997395d3
IM		 2899static int64_t x86_cpu_get_arch_id(CPUState *cs)
2900{
2901 X86CPU *cpu = X86_CPU(cs);
997395d3 2902
7e72a45c 2903 return cpu->apic_id;
997395d3
IM		 2904}
2905
444d5590
AF		 2906static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2907{
2908 X86CPU *cpu = X86_CPU(cs);
2909
2910 return cpu->env.cr[0] & CR0_PG_MASK;
2911}
2912
f45748f1
AF		 2913static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2914{
2915 X86CPU *cpu = X86_CPU(cs);
2916
2917 cpu->env.eip = value;
2918}
2919
bdf7ae5b
AF		 2920static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2921{
2922 X86CPU *cpu = X86_CPU(cs);
2923
2924 cpu->env.eip = tb->pc - tb->cs_base;
2925}
2926
8c2e1b00
AF		 2927static bool x86_cpu_has_work(CPUState *cs)
2928{
2929 X86CPU *cpu = X86_CPU(cs);
2930 CPUX86State *env = &cpu->env;
2931
60e68042
PB		 2932#if !defined(CONFIG_USER_ONLY)
2933 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2934 apic_poll_irq(cpu->apic_state);
2935 cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
2936 }
2937#endif
2938
2939 return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
8c2e1b00
AF		 2940 (env->eflags & IF_MASK)) ||
2941 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2942 CPU_INTERRUPT_INIT |
2943 CPU_INTERRUPT_SIPI |
2944 CPU_INTERRUPT_MCE));
2945}
2946
9337e3b6
EH		 2947static Property x86_cpu_properties[] = {
2948 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 2949 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 2950 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 2951 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 2952 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 2953 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2954 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 2955 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 2956 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
2957 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 2958 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
9337e3b6
EH		 2959 DEFINE_PROP_END_OF_LIST()
2960};
2961
5fd2087a
AF		 2962static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2963{
2964 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2965 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 2966 DeviceClass *dc = DEVICE_CLASS(oc);
2967
2968 xcc->parent_realize = dc->realize;
2969 dc->realize = x86_cpu_realizefn;
62fc403f 2970 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 2971 dc->props = x86_cpu_properties;
5fd2087a
AF		 2972
2973 xcc->parent_reset = cc->reset;
2974 cc->reset = x86_cpu_reset;
91b1df8c 2975 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 2976
500050d1 2977 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 2978 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 2979 cc->has_work = x86_cpu_has_work;
97a8ea5a 2980 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 2981 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 2982 cc->dump_state = x86_cpu_dump_state;
f45748f1 2983 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 2984 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 2985 cc->gdb_read_register = x86_cpu_gdb_read_register;
2986 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 2987 cc->get_arch_id = x86_cpu_get_arch_id;
2988 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 2989#ifdef CONFIG_USER_ONLY
2990 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2991#else
a23bbfda 2992 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 2993 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 2994 cc->write_elf64_note = x86_cpu_write_elf64_note;
2995 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2996 cc->write_elf32_note = x86_cpu_write_elf32_note;
2997 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 2998 cc->vmsd = &vmstate_x86_cpu;
c72bf468 2999#endif
a0e372f0 3000 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3001#ifndef CONFIG_USER_ONLY
3002 cc->debug_excp_handler = breakpoint_handler;
3003#endif
374e0cd4
RH		 3004 cc->cpu_exec_enter = x86_cpu_exec_enter;
3005 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 3006}
3007
3008static const TypeInfo x86_cpu_type_info = {
3009 .name = TYPE_X86_CPU,
3010 .parent = TYPE_CPU,
3011 .instance_size = sizeof(X86CPU),
de024815 3012 .instance_init = x86_cpu_initfn,
d940ee9b 3013 .abstract = true,
5fd2087a
AF		 3014 .class_size = sizeof(X86CPUClass),
3015 .class_init = x86_cpu_common_class_init,
3016};
3017
3018static void x86_cpu_register_types(void)
3019{
d940ee9b
EH		 3020 int i;
3021
5fd2087a 3022 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3023 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3024 x86_register_cpudef_type(&builtin_x86_defs[i]);
3025 }
3026#ifdef CONFIG_KVM
3027 type_register_static(&host_x86_cpu_type_info);
3028#endif
5fd2087a
AF		 3029}
3030
3031type_init(x86_cpu_register_types)
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