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qerror: Finally unused, clean up
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
65dee380 38#include "hw/hw.h"
b834b508 39#if defined(CONFIG_KVM)
ef8621b1 40#include <linux/kvm_para.h>
b834b508 41#endif
65dee380 42
9c17d615 43#include "sysemu/sysemu.h"
53a89e26 44#include "hw/qdev-properties.h"
62fc403f 45#include "hw/cpu/icc_bus.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
2001d0cd 47#include "exec/address-spaces.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 260 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 262 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 264};
265
303752a9
MT		 266static const char *cpuid_apm_edx_feature_name[] = {
267 NULL, NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 "invtsc", NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275};
276
0bb0b2d2
PB		 277static const char *cpuid_xsave_feature_name[] = {
278 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286};
287
621626ce
EH		 288#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
289#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
290 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
291#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
292 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
293 CPUID_PSE36 | CPUID_FXSR)
294#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
295#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
296 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
297 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
298 CPUID_PAE | CPUID_SEP | CPUID_APIC)
299
300#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
301 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
302 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
303 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
304 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
305 /* partly implemented:
306 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
307 /* missing:
308 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
309#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
310 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
311 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
312 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
313 /* missing:
314 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
315 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
316 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
317 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
318 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
319 CPUID_EXT_RDRAND */
320
321#ifdef TARGET_X86_64
322#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
323#else
324#define TCG_EXT2_X86_64_FEATURES 0
325#endif
326
327#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
328 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
329 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
330 TCG_EXT2_X86_64_FEATURES)
331#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
332 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
333#define TCG_EXT4_FEATURES 0
334#define TCG_SVM_FEATURES 0
335#define TCG_KVM_FEATURES 0
336#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
337 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
338 /* missing:
339 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
340 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
341 CPUID_7_0_EBX_RDSEED */
303752a9 342#define TCG_APM_FEATURES 0
621626ce
EH		 343
344
5ef57876
EH		 345typedef struct FeatureWordInfo {
346 const char **feat_names;
04d104b6
EH		 347 uint32_t cpuid_eax; /* Input EAX for CPUID */
348 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
349 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
350 int cpuid_reg; /* output register (R_* constant) */
37ce3522 351 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 352 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 353} FeatureWordInfo;
354
355static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 356 [FEAT_1_EDX] = {
357 .feat_names = feature_name,
358 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 359 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 360 },
361 [FEAT_1_ECX] = {
362 .feat_names = ext_feature_name,
363 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 364 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 365 },
366 [FEAT_8000_0001_EDX] = {
367 .feat_names = ext2_feature_name,
368 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 369 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 370 },
371 [FEAT_8000_0001_ECX] = {
372 .feat_names = ext3_feature_name,
373 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 374 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 375 },
89e49c8b
EH		 376 [FEAT_C000_0001_EDX] = {
377 .feat_names = ext4_feature_name,
378 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 379 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 380 },
bffd67b0
EH		 381 [FEAT_KVM] = {
382 .feat_names = kvm_feature_name,
383 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 384 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 385 },
386 [FEAT_SVM] = {
387 .feat_names = svm_feature_name,
388 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 389 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 390 },
391 [FEAT_7_0_EBX] = {
392 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 393 .cpuid_eax = 7,
394 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
395 .cpuid_reg = R_EBX,
37ce3522 396 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 397 },
303752a9
MT		 398 [FEAT_8000_0007_EDX] = {
399 .feat_names = cpuid_apm_edx_feature_name,
400 .cpuid_eax = 0x80000007,
401 .cpuid_reg = R_EDX,
402 .tcg_features = TCG_APM_FEATURES,
403 .unmigratable_flags = CPUID_APM_INVTSC,
404 },
0bb0b2d2
PB		 405 [FEAT_XSAVE] = {
406 .feat_names = cpuid_xsave_feature_name,
407 .cpuid_eax = 0xd,
408 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
409 .cpuid_reg = R_EAX,
410 .tcg_features = 0,
0bb0b2d2 411 },
5ef57876
EH		 412};
413
8e8aba50
EH		 414typedef struct X86RegisterInfo32 {
415 /* Name of register */
416 const char *name;
417 /* QAPI enum value register */
418 X86CPURegister32 qapi_enum;
419} X86RegisterInfo32;
420
421#define REGISTER(reg) \
5d371f41 422 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 423static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 424 REGISTER(EAX),
425 REGISTER(ECX),
426 REGISTER(EDX),
427 REGISTER(EBX),
428 REGISTER(ESP),
429 REGISTER(EBP),
430 REGISTER(ESI),
431 REGISTER(EDI),
432};
433#undef REGISTER
434
2560f19f
PB		 435typedef struct ExtSaveArea {
436 uint32_t feature, bits;
437 uint32_t offset, size;
438} ExtSaveArea;
439
440static const ExtSaveArea ext_save_areas[] = {
441 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 442 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 443 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
444 .offset = 0x3c0, .size = 0x40 },
445 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 446 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 447 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
448 .offset = 0x440, .size = 0x40 },
449 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
450 .offset = 0x480, .size = 0x200 },
451 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
452 .offset = 0x680, .size = 0x400 },
2560f19f 453};
8e8aba50 454
8b4beddc
EH		 455const char *get_register_name_32(unsigned int reg)
456{
31ccdde2 457 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 458 return NULL;
459 }
8e8aba50 460 return x86_reg_info_32[reg].name;
8b4beddc
EH		 461}
462
5fcca9ff
EH		 463/* KVM-specific features that are automatically added to all CPU models
464 * when KVM is enabled.
465 */
466static uint32_t kvm_default_features[FEATURE_WORDS] = {
467 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 468 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 469 (1 << KVM_FEATURE_CLOCKSOURCE2) |
470 (1 << KVM_FEATURE_ASYNC_PF) |
471 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 472 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 473 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 474 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 475};
dc59944b 476
136a7e9a
EH		 477/* Features that are not added by default to any CPU model when KVM is enabled.
478 */
479static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 480 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a 481 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
75d373ef 482 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
136a7e9a
EH		 483};
484
1cadaa94 485void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 486{
8fb4f821 487 kvm_default_features[w] &= ~features;
dc59944b
MT		 488}
489
75d373ef
EH		 490void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
491{
492 kvm_default_unset_features[w] &= ~features;
493}
494
84f1b92f
EH		 495/*
496 * Returns the set of feature flags that are supported and migratable by
497 * QEMU, for a given FeatureWord.
498 */
499static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
500{
501 FeatureWordInfo *wi = &feature_word_info[w];
502 uint32_t r = 0;
503 int i;
504
505 for (i = 0; i < 32; i++) {
506 uint32_t f = 1U << i;
507 /* If the feature name is unknown, it is not supported by QEMU yet */
508 if (!wi->feat_names[i]) {
509 continue;
510 }
511 /* Skip features known to QEMU, but explicitly marked as unmigratable */
512 if (wi->unmigratable_flags & f) {
513 continue;
514 }
515 r |= f;
516 }
517 return r;
518}
519
bb44e0d1
JK		 520void host_cpuid(uint32_t function, uint32_t count,
521 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 522{
a1fd24af
AL		 523 uint32_t vec[4];
524
525#ifdef __x86_64__
526 asm volatile("cpuid"
527 : "=a"(vec[0]), "=b"(vec[1]),
528 "=c"(vec[2]), "=d"(vec[3])
529 : "0"(function), "c"(count) : "cc");
c1f41226 530#elif defined(__i386__)
a1fd24af
AL		 531 asm volatile("pusha \n\t"
532 "cpuid \n\t"
533 "mov %%eax, 0(%2) \n\t"
534 "mov %%ebx, 4(%2) \n\t"
535 "mov %%ecx, 8(%2) \n\t"
536 "mov %%edx, 12(%2) \n\t"
537 "popa"
538 : : "a"(function), "c"(count), "S"(vec)
539 : "memory", "cc");
c1f41226
EH		 540#else
541 abort();
a1fd24af
AL		 542#endif
543
bdde476a 544 if (eax)
a1fd24af 545 *eax = vec[0];
bdde476a 546 if (ebx)
a1fd24af 547 *ebx = vec[1];
bdde476a 548 if (ecx)
a1fd24af 549 *ecx = vec[2];
bdde476a 550 if (edx)
a1fd24af 551 *edx = vec[3];
bdde476a 552}
c6dc6f63
AP		 553
554#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
555
556/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
557 * a substring. ex if !NULL points to the first char after a substring,
558 * otherwise the string is assumed to sized by a terminating nul.
559 * Return lexical ordering of *s1:*s2.
560 */
8f9d989c
CF		 561static int sstrcmp(const char *s1, const char *e1,
562 const char *s2, const char *e2)
c6dc6f63
AP		 563{
564 for (;;) {
565 if (!*s1 || !*s2 || *s1 != *s2)
566 return (*s1 - *s2);
567 ++s1, ++s2;
568 if (s1 == e1 && s2 == e2)
569 return (0);
570 else if (s1 == e1)
571 return (*s2);
572 else if (s2 == e2)
573 return (*s1);
574 }
575}
576
577/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
578 * '|' delimited (possibly empty) strings in which case search for a match
579 * within the alternatives proceeds left to right. Return 0 for success,
580 * non-zero otherwise.
581 */
582static int altcmp(const char *s, const char *e, const char *altstr)
583{
584 const char *p, *q;
585
586 for (q = p = altstr; ; ) {
587 while (*p && *p != '|')
588 ++p;
589 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
590 return (0);
591 if (!*p)
592 return (1);
593 else
594 q = ++p;
595 }
596}
597
598/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 599 * *pval and return true, otherwise return false
c6dc6f63 600 */
e41e0fc6
JK		 601static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
602 const char **featureset)
c6dc6f63
AP		 603{
604 uint32_t mask;
605 const char **ppc;
e41e0fc6 606 bool found = false;
c6dc6f63 607
e41e0fc6 608 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 609 if (*ppc && !altcmp(s, e, *ppc)) {
610 *pval |= mask;
e41e0fc6 611 found = true;
c6dc6f63 612 }
e41e0fc6
JK		 613 }
614 return found;
c6dc6f63
AP		 615}
616
5ef57876 617static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 618 FeatureWordArray words,
619 Error **errp)
c6dc6f63 620{
5ef57876
EH		 621 FeatureWord w;
622 for (w = 0; w < FEATURE_WORDS; w++) {
623 FeatureWordInfo *wi = &feature_word_info[w];
624 if (wi->feat_names &&
625 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
626 break;
627 }
628 }
629 if (w == FEATURE_WORDS) {
c00c94ab 630 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 631 }
c6dc6f63
AP		 632}
633
d940ee9b
EH		 634/* CPU class name definitions: */
635
636#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
637#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
638
639/* Return type name for a given CPU model name
640 * Caller is responsible for freeing the returned string.
641 */
642static char *x86_cpu_type_name(const char *model_name)
643{
644 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
645}
646
500050d1
AF		 647static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
648{
d940ee9b
EH		 649 ObjectClass *oc;
650 char *typename;
651
500050d1
AF		 652 if (cpu_model == NULL) {
653 return NULL;
654 }
655
d940ee9b
EH		 656 typename = x86_cpu_type_name(cpu_model);
657 oc = object_class_by_name(typename);
658 g_free(typename);
659 return oc;
500050d1
AF		 660}
661
d940ee9b 662struct X86CPUDefinition {
c6dc6f63
AP		 663 const char *name;
664 uint32_t level;
90e4b0c3
EH		 665 uint32_t xlevel;
666 uint32_t xlevel2;
99b88a17
IM		 667 /* vendor is zero-terminated, 12 character ASCII string */
668 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 669 int family;
670 int model;
671 int stepping;
0514ef2f 672 FeatureWordArray features;
c6dc6f63 673 char model_id[48];
787aaf57 674 bool cache_info_passthrough;
d940ee9b 675};
c6dc6f63 676
9576de75 677static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 678 {
679 .name = "qemu64",
680 .level = 4,
99b88a17 681 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 682 .family = 6,
f8e6a11a 683 .model = 6,
c6dc6f63 684 .stepping = 3,
0514ef2f 685 .features[FEAT_1_EDX] =
27861ecc 686 PPRO_FEATURES |
c6dc6f63 687 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 688 CPUID_PSE36,
0514ef2f 689 .features[FEAT_1_ECX] =
27861ecc 690 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 691 .features[FEAT_8000_0001_EDX] =
c6dc6f63 692 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 693 .features[FEAT_8000_0001_ECX] =
27861ecc 694 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 695 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
696 .xlevel = 0x8000000A,
c6dc6f63
AP		 697 },
698 {
699 .name = "phenom",
700 .level = 5,
99b88a17 701 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 702 .family = 16,
703 .model = 2,
704 .stepping = 3,
b9fc20bc 705 /* Missing: CPUID_HT */
0514ef2f 706 .features[FEAT_1_EDX] =
27861ecc 707 PPRO_FEATURES |
c6dc6f63 708 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 709 CPUID_PSE36 | CPUID_VME,
0514ef2f 710 .features[FEAT_1_ECX] =
27861ecc 711 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 712 CPUID_EXT_POPCNT,
0514ef2f 713 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 714 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
715 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 716 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 717 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
718 CPUID_EXT3_CR8LEG,
719 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
720 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 721 .features[FEAT_8000_0001_ECX] =
27861ecc 722 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 723 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 724 /* Missing: CPUID_SVM_LBRV */
0514ef2f 725 .features[FEAT_SVM] =
b9fc20bc 726 CPUID_SVM_NPT,
c6dc6f63
AP		 727 .xlevel = 0x8000001A,
728 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
729 },
730 {
731 .name = "core2duo",
732 .level = 10,
99b88a17 733 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 734 .family = 6,
735 .model = 15,
736 .stepping = 11,
b9fc20bc 737 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 738 .features[FEAT_1_EDX] =
27861ecc 739 PPRO_FEATURES |
c6dc6f63 740 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 741 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
742 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 743 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 744 .features[FEAT_1_ECX] =
27861ecc 745 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 746 CPUID_EXT_CX16,
0514ef2f 747 .features[FEAT_8000_0001_EDX] =
27861ecc 748 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 749 .features[FEAT_8000_0001_ECX] =
27861ecc 750 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 751 .xlevel = 0x80000008,
752 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
753 },
754 {
755 .name = "kvm64",
756 .level = 5,
99b88a17 757 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 758 .family = 15,
759 .model = 6,
760 .stepping = 1,
b3a4f0b1 761 /* Missing: CPUID_HT */
0514ef2f 762 .features[FEAT_1_EDX] =
b3a4f0b1 763 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 764 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
765 CPUID_PSE36,
766 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 767 .features[FEAT_1_ECX] =
27861ecc 768 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 769 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 770 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 771 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
772 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
773 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
774 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
775 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 776 .features[FEAT_8000_0001_ECX] =
27861ecc 777 0,
c6dc6f63
AP		 778 .xlevel = 0x80000008,
779 .model_id = "Common KVM processor"
780 },
c6dc6f63
AP		 781 {
782 .name = "qemu32",
783 .level = 4,
99b88a17 784 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 785 .family = 6,
f8e6a11a 786 .model = 6,
c6dc6f63 787 .stepping = 3,
0514ef2f 788 .features[FEAT_1_EDX] =
27861ecc 789 PPRO_FEATURES,
0514ef2f 790 .features[FEAT_1_ECX] =
27861ecc 791 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 792 .xlevel = 0x80000004,
c6dc6f63 793 },
eafaf1e5
AP		 794 {
795 .name = "kvm32",
796 .level = 5,
99b88a17 797 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 798 .family = 15,
799 .model = 6,
800 .stepping = 1,
0514ef2f 801 .features[FEAT_1_EDX] =
b3a4f0b1 802 PPRO_FEATURES | CPUID_VME |
eafaf1e5 803 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 804 .features[FEAT_1_ECX] =
27861ecc 805 CPUID_EXT_SSE3,
0514ef2f 806 .features[FEAT_8000_0001_ECX] =
27861ecc 807 0,
eafaf1e5
AP		 808 .xlevel = 0x80000008,
809 .model_id = "Common 32-bit KVM processor"
810 },
c6dc6f63
AP		 811 {
812 .name = "coreduo",
813 .level = 10,
99b88a17 814 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 815 .family = 6,
816 .model = 14,
817 .stepping = 8,
b9fc20bc 818 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 819 .features[FEAT_1_EDX] =
27861ecc 820 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
822 CPUID_SS,
823 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 824 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 825 .features[FEAT_1_ECX] =
e93abc14 826 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 827 .features[FEAT_8000_0001_EDX] =
27861ecc 828 CPUID_EXT2_NX,
c6dc6f63
AP		 829 .xlevel = 0x80000008,
830 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
831 },
832 {
833 .name = "486",
58012d66 834 .level = 1,
99b88a17 835 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 836 .family = 4,
b2a856d9 837 .model = 8,
c6dc6f63 838 .stepping = 0,
0514ef2f 839 .features[FEAT_1_EDX] =
27861ecc 840 I486_FEATURES,
c6dc6f63
AP		 841 .xlevel = 0,
842 },
843 {
844 .name = "pentium",
845 .level = 1,
99b88a17 846 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 847 .family = 5,
848 .model = 4,
849 .stepping = 3,
0514ef2f 850 .features[FEAT_1_EDX] =
27861ecc 851 PENTIUM_FEATURES,
c6dc6f63
AP		 852 .xlevel = 0,
853 },
854 {
855 .name = "pentium2",
856 .level = 2,
99b88a17 857 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 858 .family = 6,
859 .model = 5,
860 .stepping = 2,
0514ef2f 861 .features[FEAT_1_EDX] =
27861ecc 862 PENTIUM2_FEATURES,
c6dc6f63
AP		 863 .xlevel = 0,
864 },
865 {
866 .name = "pentium3",
867 .level = 2,
99b88a17 868 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 869 .family = 6,
870 .model = 7,
871 .stepping = 3,
0514ef2f 872 .features[FEAT_1_EDX] =
27861ecc 873 PENTIUM3_FEATURES,
c6dc6f63
AP		 874 .xlevel = 0,
875 },
876 {
877 .name = "athlon",
878 .level = 2,
99b88a17 879 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 880 .family = 6,
881 .model = 2,
882 .stepping = 3,
0514ef2f 883 .features[FEAT_1_EDX] =
27861ecc 884 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 885 CPUID_MCA,
0514ef2f 886 .features[FEAT_8000_0001_EDX] =
60032ac0 887 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 888 .xlevel = 0x80000008,
c6dc6f63
AP		 889 },
890 {
891 .name = "n270",
892 /* original is on level 10 */
893 .level = 5,
99b88a17 894 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 895 .family = 6,
896 .model = 28,
897 .stepping = 2,
b9fc20bc 898 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 899 .features[FEAT_1_EDX] =
27861ecc 900 PPRO_FEATURES |
b9fc20bc
EH		 901 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
902 CPUID_ACPI | CPUID_SS,
c6dc6f63 903 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 904 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
905 * CPUID_EXT_XTPR */
0514ef2f 906 .features[FEAT_1_ECX] =
27861ecc 907 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 908 CPUID_EXT_MOVBE,
0514ef2f 909 .features[FEAT_8000_0001_EDX] =
60032ac0 910 CPUID_EXT2_NX,
0514ef2f 911 .features[FEAT_8000_0001_ECX] =
27861ecc 912 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 913 .xlevel = 0x8000000A,
914 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
915 },
3eca4642
EH		 916 {
917 .name = "Conroe",
6b11322e 918 .level = 4,
99b88a17 919 .vendor = CPUID_VENDOR_INTEL,
3eca4642 920 .family = 6,
ffce9ebb 921 .model = 15,
3eca4642 922 .stepping = 3,
0514ef2f 923 .features[FEAT_1_EDX] =
b3a4f0b1 924 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 925 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
926 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
927 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
928 CPUID_DE | CPUID_FP87,
0514ef2f 929 .features[FEAT_1_ECX] =
27861ecc 930 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 931 .features[FEAT_8000_0001_EDX] =
27861ecc 932 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 933 .features[FEAT_8000_0001_ECX] =
27861ecc 934 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 935 .xlevel = 0x8000000A,
936 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
937 },
938 {
939 .name = "Penryn",
6b11322e 940 .level = 4,
99b88a17 941 .vendor = CPUID_VENDOR_INTEL,
3eca4642 942 .family = 6,
ffce9ebb 943 .model = 23,
3eca4642 944 .stepping = 3,
0514ef2f 945 .features[FEAT_1_EDX] =
b3a4f0b1 946 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 947 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
948 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
949 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
950 CPUID_DE | CPUID_FP87,
0514ef2f 951 .features[FEAT_1_ECX] =
27861ecc 952 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 953 CPUID_EXT_SSE3,
0514ef2f 954 .features[FEAT_8000_0001_EDX] =
27861ecc 955 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 956 .features[FEAT_8000_0001_ECX] =
27861ecc 957 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 958 .xlevel = 0x8000000A,
959 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
960 },
961 {
962 .name = "Nehalem",
6b11322e 963 .level = 4,
99b88a17 964 .vendor = CPUID_VENDOR_INTEL,
3eca4642 965 .family = 6,
ffce9ebb 966 .model = 26,
3eca4642 967 .stepping = 3,
0514ef2f 968 .features[FEAT_1_EDX] =
b3a4f0b1 969 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 970 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
971 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
972 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
973 CPUID_DE | CPUID_FP87,
0514ef2f 974 .features[FEAT_1_ECX] =
27861ecc 975 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 976 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 977 .features[FEAT_8000_0001_EDX] =
27861ecc 978 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 979 .features[FEAT_8000_0001_ECX] =
27861ecc 980 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 981 .xlevel = 0x8000000A,
982 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
983 },
984 {
985 .name = "Westmere",
986 .level = 11,
99b88a17 987 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 988 .family = 6,
989 .model = 44,
990 .stepping = 1,
0514ef2f 991 .features[FEAT_1_EDX] =
b3a4f0b1 992 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 993 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
994 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
995 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
996 CPUID_DE | CPUID_FP87,
0514ef2f 997 .features[FEAT_1_ECX] =
27861ecc 998 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 999 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1000 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1001 .features[FEAT_8000_0001_EDX] =
27861ecc 1002 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1003 .features[FEAT_8000_0001_ECX] =
27861ecc 1004 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1005 .xlevel = 0x8000000A,
1006 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1007 },
1008 {
1009 .name = "SandyBridge",
1010 .level = 0xd,
99b88a17 1011 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1012 .family = 6,
1013 .model = 42,
1014 .stepping = 1,
0514ef2f 1015 .features[FEAT_1_EDX] =
b3a4f0b1 1016 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1017 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1018 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1019 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1020 CPUID_DE | CPUID_FP87,
0514ef2f 1021 .features[FEAT_1_ECX] =
27861ecc 1022 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1023 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1024 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1025 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1026 CPUID_EXT_SSE3,
0514ef2f 1027 .features[FEAT_8000_0001_EDX] =
27861ecc 1028 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1029 CPUID_EXT2_SYSCALL,
0514ef2f 1030 .features[FEAT_8000_0001_ECX] =
27861ecc 1031 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1032 .features[FEAT_XSAVE] =
1033 CPUID_XSAVE_XSAVEOPT,
3eca4642
EH		 1034 .xlevel = 0x8000000A,
1035 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1036 },
2f9ac42a
PB		 1037 {
1038 .name = "IvyBridge",
1039 .level = 0xd,
1040 .vendor = CPUID_VENDOR_INTEL,
1041 .family = 6,
1042 .model = 58,
1043 .stepping = 9,
1044 .features[FEAT_1_EDX] =
1045 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1046 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1047 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1048 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1049 CPUID_DE | CPUID_FP87,
1050 .features[FEAT_1_ECX] =
1051 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1052 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1053 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1054 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1055 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1056 .features[FEAT_7_0_EBX] =
1057 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1058 CPUID_7_0_EBX_ERMS,
1059 .features[FEAT_8000_0001_EDX] =
1060 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1061 CPUID_EXT2_SYSCALL,
1062 .features[FEAT_8000_0001_ECX] =
1063 CPUID_EXT3_LAHF_LM,
1064 .features[FEAT_XSAVE] =
1065 CPUID_XSAVE_XSAVEOPT,
1066 .xlevel = 0x8000000A,
1067 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1068 },
37507094 1069 {
a356850b
EH		 1070 .name = "Haswell-noTSX",
1071 .level = 0xd,
1072 .vendor = CPUID_VENDOR_INTEL,
1073 .family = 6,
1074 .model = 60,
1075 .stepping = 1,
1076 .features[FEAT_1_EDX] =
1077 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1078 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1079 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1080 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1081 CPUID_DE | CPUID_FP87,
1082 .features[FEAT_1_ECX] =
1083 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1084 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1085 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1086 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1087 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1088 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1089 .features[FEAT_8000_0001_EDX] =
1090 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1091 CPUID_EXT2_SYSCALL,
1092 .features[FEAT_8000_0001_ECX] =
1093 CPUID_EXT3_LAHF_LM,
1094 .features[FEAT_7_0_EBX] =
1095 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1096 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1097 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1098 .features[FEAT_XSAVE] =
1099 CPUID_XSAVE_XSAVEOPT,
1100 .xlevel = 0x8000000A,
1101 .model_id = "Intel Core Processor (Haswell, no TSX)",
1102 }, {
37507094
EH		 1103 .name = "Haswell",
1104 .level = 0xd,
99b88a17 1105 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1106 .family = 6,
1107 .model = 60,
1108 .stepping = 1,
0514ef2f 1109 .features[FEAT_1_EDX] =
b3a4f0b1 1110 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1111 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1112 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1113 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1114 CPUID_DE | CPUID_FP87,
0514ef2f 1115 .features[FEAT_1_ECX] =
27861ecc 1116 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1117 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1118 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1119 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1120 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1121 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1122 .features[FEAT_8000_0001_EDX] =
27861ecc 1123 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1124 CPUID_EXT2_SYSCALL,
0514ef2f 1125 .features[FEAT_8000_0001_ECX] =
27861ecc 1126 CPUID_EXT3_LAHF_LM,
0514ef2f 1127 .features[FEAT_7_0_EBX] =
27861ecc 1128 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1129 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1130 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1131 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1132 .features[FEAT_XSAVE] =
1133 CPUID_XSAVE_XSAVEOPT,
37507094
EH		 1134 .xlevel = 0x8000000A,
1135 .model_id = "Intel Core Processor (Haswell)",
1136 },
a356850b
EH		 1137 {
1138 .name = "Broadwell-noTSX",
1139 .level = 0xd,
1140 .vendor = CPUID_VENDOR_INTEL,
1141 .family = 6,
1142 .model = 61,
1143 .stepping = 2,
1144 .features[FEAT_1_EDX] =
1145 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1146 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1147 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1148 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1149 CPUID_DE | CPUID_FP87,
1150 .features[FEAT_1_ECX] =
1151 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1152 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1153 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1154 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1155 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1156 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1157 .features[FEAT_8000_0001_EDX] =
1158 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1159 CPUID_EXT2_SYSCALL,
1160 .features[FEAT_8000_0001_ECX] =
1161 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1162 .features[FEAT_7_0_EBX] =
1163 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1164 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1165 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1166 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1167 CPUID_7_0_EBX_SMAP,
1168 .features[FEAT_XSAVE] =
1169 CPUID_XSAVE_XSAVEOPT,
1170 .xlevel = 0x8000000A,
1171 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1172 },
ece01354
EH		 1173 {
1174 .name = "Broadwell",
1175 .level = 0xd,
1176 .vendor = CPUID_VENDOR_INTEL,
1177 .family = 6,
1178 .model = 61,
1179 .stepping = 2,
1180 .features[FEAT_1_EDX] =
b3a4f0b1 1181 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1182 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1183 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1184 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1185 CPUID_DE | CPUID_FP87,
1186 .features[FEAT_1_ECX] =
1187 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1188 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1189 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1190 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1191 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1192 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1193 .features[FEAT_8000_0001_EDX] =
1194 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1195 CPUID_EXT2_SYSCALL,
1196 .features[FEAT_8000_0001_ECX] =
1197 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1198 .features[FEAT_7_0_EBX] =
1199 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1200 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1201 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1202 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1203 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1204 .features[FEAT_XSAVE] =
1205 CPUID_XSAVE_XSAVEOPT,
ece01354
EH		 1206 .xlevel = 0x8000000A,
1207 .model_id = "Intel Core Processor (Broadwell)",
1208 },
3eca4642
EH		 1209 {
1210 .name = "Opteron_G1",
1211 .level = 5,
99b88a17 1212 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1213 .family = 15,
1214 .model = 6,
1215 .stepping = 1,
0514ef2f 1216 .features[FEAT_1_EDX] =
b3a4f0b1 1217 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1218 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1219 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1220 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1221 CPUID_DE | CPUID_FP87,
0514ef2f 1222 .features[FEAT_1_ECX] =
27861ecc 1223 CPUID_EXT_SSE3,
0514ef2f 1224 .features[FEAT_8000_0001_EDX] =
27861ecc 1225 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1226 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1227 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1228 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1229 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1230 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1231 .xlevel = 0x80000008,
1232 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1233 },
1234 {
1235 .name = "Opteron_G2",
1236 .level = 5,
99b88a17 1237 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1238 .family = 15,
1239 .model = 6,
1240 .stepping = 1,
0514ef2f 1241 .features[FEAT_1_EDX] =
b3a4f0b1 1242 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1243 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1244 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1245 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1246 CPUID_DE | CPUID_FP87,
0514ef2f 1247 .features[FEAT_1_ECX] =
27861ecc 1248 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1249 .features[FEAT_8000_0001_EDX] =
27861ecc 1250 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1251 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1252 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1253 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1254 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1255 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1256 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1257 .features[FEAT_8000_0001_ECX] =
27861ecc 1258 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1259 .xlevel = 0x80000008,
1260 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1261 },
1262 {
1263 .name = "Opteron_G3",
1264 .level = 5,
99b88a17 1265 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1266 .family = 15,
1267 .model = 6,
1268 .stepping = 1,
0514ef2f 1269 .features[FEAT_1_EDX] =
b3a4f0b1 1270 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1271 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1272 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1273 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1274 CPUID_DE | CPUID_FP87,
0514ef2f 1275 .features[FEAT_1_ECX] =
27861ecc 1276 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1277 CPUID_EXT_SSE3,
0514ef2f 1278 .features[FEAT_8000_0001_EDX] =
27861ecc 1279 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1280 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1281 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1282 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1283 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1284 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1285 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1286 .features[FEAT_8000_0001_ECX] =
27861ecc 1287 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1288 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1289 .xlevel = 0x80000008,
1290 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1291 },
1292 {
1293 .name = "Opteron_G4",
1294 .level = 0xd,
99b88a17 1295 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1296 .family = 21,
1297 .model = 1,
1298 .stepping = 2,
0514ef2f 1299 .features[FEAT_1_EDX] =
b3a4f0b1 1300 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1301 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1302 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1303 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1304 CPUID_DE | CPUID_FP87,
0514ef2f 1305 .features[FEAT_1_ECX] =
27861ecc 1306 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1307 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1308 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1309 CPUID_EXT_SSE3,
0514ef2f 1310 .features[FEAT_8000_0001_EDX] =
27861ecc 1311 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1312 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1313 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1314 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1315 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1316 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1317 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1318 .features[FEAT_8000_0001_ECX] =
27861ecc 1319 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1320 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1321 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1322 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1323 /* no xsaveopt! */
3eca4642
EH		 1324 .xlevel = 0x8000001A,
1325 .model_id = "AMD Opteron 62xx class CPU",
1326 },
021941b9
AP		 1327 {
1328 .name = "Opteron_G5",
1329 .level = 0xd,
99b88a17 1330 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1331 .family = 21,
1332 .model = 2,
1333 .stepping = 0,
0514ef2f 1334 .features[FEAT_1_EDX] =
b3a4f0b1 1335 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1336 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1337 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1338 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1339 CPUID_DE | CPUID_FP87,
0514ef2f 1340 .features[FEAT_1_ECX] =
27861ecc 1341 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1342 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1343 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1344 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1345 .features[FEAT_8000_0001_EDX] =
27861ecc 1346 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1347 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1348 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1349 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1350 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1351 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1352 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1353 .features[FEAT_8000_0001_ECX] =
27861ecc 1354 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1355 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1356 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1357 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1358 /* no xsaveopt! */
021941b9
AP		 1359 .xlevel = 0x8000001A,
1360 .model_id = "AMD Opteron 63xx class CPU",
1361 },
c6dc6f63
AP		 1362};
1363
0668af54
EH		 1364/**
1365 * x86_cpu_compat_set_features:
1366 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1367 * @w: Identifies the feature word to be changed.
1368 * @feat_add: Feature bits to be added to feature word
1369 * @feat_remove: Feature bits to be removed from feature word
1370 *
1371 * Change CPU model feature bits for compatibility.
1372 *
1373 * This function may be used by machine-type compatibility functions
1374 * to enable or disable feature bits on specific CPU models.
1375 */
1376void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1377 uint32_t feat_add, uint32_t feat_remove)
1378{
9576de75 1379 X86CPUDefinition *def;
0668af54
EH		 1380 int i;
1381 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1382 def = &builtin_x86_defs[i];
1383 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1384 def->features[w] |= feat_add;
1385 def->features[w] &= ~feat_remove;
1386 }
1387 }
1388}
1389
4d1b279b
EH		 1390static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1391 bool migratable_only);
1392
d940ee9b
EH		 1393#ifdef CONFIG_KVM
1394
c6dc6f63
AP		 1395static int cpu_x86_fill_model_id(char *str)
1396{
1397 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1398 int i;
1399
1400 for (i = 0; i < 3; i++) {
1401 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1402 memcpy(str + i * 16 + 0, &eax, 4);
1403 memcpy(str + i * 16 + 4, &ebx, 4);
1404 memcpy(str + i * 16 + 8, &ecx, 4);
1405 memcpy(str + i * 16 + 12, &edx, 4);
1406 }
1407 return 0;
1408}
1409
d940ee9b
EH		 1410static X86CPUDefinition host_cpudef;
1411
84f1b92f 1412static Property host_x86_cpu_properties[] = {
120eee7d 1413 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1414 DEFINE_PROP_END_OF_LIST()
1415};
1416
d940ee9b 1417/* class_init for the "host" CPU model
6e746f30 1418 *
d940ee9b 1419 * This function may be called before KVM is initialized.
6e746f30 1420 */
d940ee9b 1421static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1422{
84f1b92f 1423 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1424 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1425 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1426
d940ee9b 1427 xcc->kvm_required = true;
6e746f30 1428
c6dc6f63 1429 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1430 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1431
1432 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1433 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1434 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1435 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1436
d940ee9b 1437 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1438
d940ee9b
EH		 1439 xcc->cpu_def = &host_cpudef;
1440 host_cpudef.cache_info_passthrough = true;
1441
1442 /* level, xlevel, xlevel2, and the feature words are initialized on
1443 * instance_init, because they require KVM to be initialized.
1444 */
84f1b92f
EH		 1445
1446 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1447}
1448
1449static void host_x86_cpu_initfn(Object *obj)
1450{
1451 X86CPU *cpu = X86_CPU(obj);
1452 CPUX86State *env = &cpu->env;
1453 KVMState *s = kvm_state;
d940ee9b
EH		 1454
1455 assert(kvm_enabled());
1456
4d1b279b
EH		 1457 /* We can't fill the features array here because we don't know yet if
1458 * "migratable" is true or false.
1459 */
1460 cpu->host_features = true;
1461
d940ee9b
EH		 1462 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1463 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1464 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1465
d940ee9b 1466 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1467}
1468
d940ee9b
EH		 1469static const TypeInfo host_x86_cpu_type_info = {
1470 .name = X86_CPU_TYPE_NAME("host"),
1471 .parent = TYPE_X86_CPU,
1472 .instance_init = host_x86_cpu_initfn,
1473 .class_init = host_x86_cpu_class_init,
1474};
1475
1476#endif
1477
8459e396 1478static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1479{
8459e396 1480 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1481 int i;
1482
857aee33 1483 for (i = 0; i < 32; ++i) {
c6dc6f63 1484 if (1 << i & mask) {
bffd67b0 1485 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1486 assert(reg);
fefb41bf 1487 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1488 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1489 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1490 f->cpuid_eax, reg,
1491 f->feat_names[i] ? "." : "",
1492 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1493 }
857aee33 1494 }
c6dc6f63
AP		 1495}
1496
95b8519d
AF		 1497static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1498 const char *name, Error **errp)
1499{
1500 X86CPU *cpu = X86_CPU(obj);
1501 CPUX86State *env = &cpu->env;
1502 int64_t value;
1503
1504 value = (env->cpuid_version >> 8) & 0xf;
1505 if (value == 0xf) {
1506 value += (env->cpuid_version >> 20) & 0xff;
1507 }
1508 visit_type_int(v, &value, name, errp);
1509}
1510
71ad61d3
AF		 1511static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1512 const char *name, Error **errp)
ed5e1ec3 1513{
71ad61d3
AF		 1514 X86CPU *cpu = X86_CPU(obj);
1515 CPUX86State *env = &cpu->env;
1516 const int64_t min = 0;
1517 const int64_t max = 0xff + 0xf;
65cd9064 1518 Error *local_err = NULL;
71ad61d3
AF		 1519 int64_t value;
1520
65cd9064
MA		 1521 visit_type_int(v, &value, name, &local_err);
1522 if (local_err) {
1523 error_propagate(errp, local_err);
71ad61d3
AF		 1524 return;
1525 }
1526 if (value < min || value > max) {
c6bd8c70
MA		 1527 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1528 name ? name : "null", value, min, max);
71ad61d3
AF		 1529 return;
1530 }
1531
ed5e1ec3 1532 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1533 if (value > 0x0f) {
1534 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1535 } else {
71ad61d3 1536 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1537 }
1538}
1539
67e30c83
AF		 1540static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1541 const char *name, Error **errp)
1542{
1543 X86CPU *cpu = X86_CPU(obj);
1544 CPUX86State *env = &cpu->env;
1545 int64_t value;
1546
1547 value = (env->cpuid_version >> 4) & 0xf;
1548 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1549 visit_type_int(v, &value, name, errp);
1550}
1551
c5291a4f
AF		 1552static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1553 const char *name, Error **errp)
b0704cbd 1554{
c5291a4f
AF		 1555 X86CPU *cpu = X86_CPU(obj);
1556 CPUX86State *env = &cpu->env;
1557 const int64_t min = 0;
1558 const int64_t max = 0xff;
65cd9064 1559 Error *local_err = NULL;
c5291a4f
AF		 1560 int64_t value;
1561
65cd9064
MA		 1562 visit_type_int(v, &value, name, &local_err);
1563 if (local_err) {
1564 error_propagate(errp, local_err);
c5291a4f
AF		 1565 return;
1566 }
1567 if (value < min || value > max) {
c6bd8c70
MA		 1568 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1569 name ? name : "null", value, min, max);
c5291a4f
AF		 1570 return;
1571 }
1572
b0704cbd 1573 env->cpuid_version &= ~0xf00f0;
c5291a4f 1574 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1575}
1576
35112e41
AF		 1577static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1578 void *opaque, const char *name,
1579 Error **errp)
1580{
1581 X86CPU *cpu = X86_CPU(obj);
1582 CPUX86State *env = &cpu->env;
1583 int64_t value;
1584
1585 value = env->cpuid_version & 0xf;
1586 visit_type_int(v, &value, name, errp);
1587}
1588
036e2222
AF		 1589static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1590 void *opaque, const char *name,
1591 Error **errp)
38c3dc46 1592{
036e2222
AF		 1593 X86CPU *cpu = X86_CPU(obj);
1594 CPUX86State *env = &cpu->env;
1595 const int64_t min = 0;
1596 const int64_t max = 0xf;
65cd9064 1597 Error *local_err = NULL;
036e2222
AF		 1598 int64_t value;
1599
65cd9064
MA		 1600 visit_type_int(v, &value, name, &local_err);
1601 if (local_err) {
1602 error_propagate(errp, local_err);
036e2222
AF		 1603 return;
1604 }
1605 if (value < min || value > max) {
c6bd8c70
MA		 1606 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1607 name ? name : "null", value, min, max);
036e2222
AF		 1608 return;
1609 }
1610
38c3dc46 1611 env->cpuid_version &= ~0xf;
036e2222 1612 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1613}
1614
d480e1af
AF		 1615static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1616{
1617 X86CPU *cpu = X86_CPU(obj);
1618 CPUX86State *env = &cpu->env;
1619 char *value;
d480e1af 1620
e42a92ae 1621 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1622 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1623 env->cpuid_vendor3);
d480e1af
AF		 1624 return value;
1625}
1626
1627static void x86_cpuid_set_vendor(Object *obj, const char *value,
1628 Error **errp)
1629{
1630 X86CPU *cpu = X86_CPU(obj);
1631 CPUX86State *env = &cpu->env;
1632 int i;
1633
9df694ee 1634 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1635 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1636 return;
1637 }
1638
1639 env->cpuid_vendor1 = 0;
1640 env->cpuid_vendor2 = 0;
1641 env->cpuid_vendor3 = 0;
1642 for (i = 0; i < 4; i++) {
1643 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1644 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1645 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1646 }
d480e1af
AF		 1647}
1648
63e886eb
AF		 1649static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1650{
1651 X86CPU *cpu = X86_CPU(obj);
1652 CPUX86State *env = &cpu->env;
1653 char *value;
1654 int i;
1655
1656 value = g_malloc(48 + 1);
1657 for (i = 0; i < 48; i++) {
1658 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1659 }
1660 value[48] = '\0';
1661 return value;
1662}
1663
938d4c25
AF		 1664static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1665 Error **errp)
dcce6675 1666{
938d4c25
AF		 1667 X86CPU *cpu = X86_CPU(obj);
1668 CPUX86State *env = &cpu->env;
dcce6675
AF		 1669 int c, len, i;
1670
1671 if (model_id == NULL) {
1672 model_id = "";
1673 }
1674 len = strlen(model_id);
d0a6acf4 1675 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1676 for (i = 0; i < 48; i++) {
1677 if (i >= len) {
1678 c = '\0';
1679 } else {
1680 c = (uint8_t)model_id[i];
1681 }
1682 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1683 }
1684}
1685
89e48965
AF		 1686static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1687 const char *name, Error **errp)
1688{
1689 X86CPU *cpu = X86_CPU(obj);
1690 int64_t value;
1691
1692 value = cpu->env.tsc_khz * 1000;
1693 visit_type_int(v, &value, name, errp);
1694}
1695
1696static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1697 const char *name, Error **errp)
1698{
1699 X86CPU *cpu = X86_CPU(obj);
1700 const int64_t min = 0;
2e84849a 1701 const int64_t max = INT64_MAX;
65cd9064 1702 Error *local_err = NULL;
89e48965
AF		 1703 int64_t value;
1704
65cd9064
MA		 1705 visit_type_int(v, &value, name, &local_err);
1706 if (local_err) {
1707 error_propagate(errp, local_err);
89e48965
AF		 1708 return;
1709 }
1710 if (value < min || value > max) {
c6bd8c70
MA		 1711 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1712 name ? name : "null", value, min, max);
89e48965
AF		 1713 return;
1714 }
1715
1716 cpu->env.tsc_khz = value / 1000;
1717}
1718
31050930
IM		 1719static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1720 const char *name, Error **errp)
1721{
1722 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1723 int64_t value = cpu->apic_id;
31050930
IM		 1724
1725 visit_type_int(v, &value, name, errp);
1726}
1727
1728static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1729 const char *name, Error **errp)
1730{
1731 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1732 DeviceState *dev = DEVICE(obj);
31050930
IM		 1733 const int64_t min = 0;
1734 const int64_t max = UINT32_MAX;
1735 Error *error = NULL;
1736 int64_t value;
1737
8d6d4980
IM		 1738 if (dev->realized) {
1739 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1740 "it was realized", name, object_get_typename(obj));
1741 return;
1742 }
1743
31050930
IM		 1744 visit_type_int(v, &value, name, &error);
1745 if (error) {
1746 error_propagate(errp, error);
1747 return;
1748 }
1749 if (value < min || value > max) {
1750 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1751 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1752 object_get_typename(obj), name, value, min, max);
1753 return;
1754 }
1755
7e72a45c 1756 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1757 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1758 return;
1759 }
7e72a45c 1760 cpu->apic_id = value;
31050930
IM		 1761}
1762
7e5292b5 1763/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1764static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1765 const char *name, Error **errp)
1766{
7e5292b5 1767 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1768 FeatureWord w;
1769 Error *err = NULL;
1770 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1771 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1772 X86CPUFeatureWordInfoList *list = NULL;
1773
1774 for (w = 0; w < FEATURE_WORDS; w++) {
1775 FeatureWordInfo *wi = &feature_word_info[w];
1776 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1777 qwi->cpuid_input_eax = wi->cpuid_eax;
1778 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1779 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1780 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1781 qwi->features = array[w];
8e8aba50
EH		 1782
1783 /* List will be in reverse order, but order shouldn't matter */
1784 list_entries[w].next = list;
1785 list_entries[w].value = &word_infos[w];
1786 list = &list_entries[w];
1787 }
1788
1789 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1790 error_propagate(errp, err);
1791}
1792
c8f0f88e
IM		 1793static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1794 const char *name, Error **errp)
1795{
1796 X86CPU *cpu = X86_CPU(obj);
1797 int64_t value = cpu->hyperv_spinlock_attempts;
1798
1799 visit_type_int(v, &value, name, errp);
1800}
1801
1802static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1803 const char *name, Error **errp)
1804{
1805 const int64_t min = 0xFFF;
1806 const int64_t max = UINT_MAX;
1807 X86CPU *cpu = X86_CPU(obj);
1808 Error *err = NULL;
1809 int64_t value;
1810
1811 visit_type_int(v, &value, name, &err);
1812 if (err) {
1813 error_propagate(errp, err);
1814 return;
1815 }
1816
1817 if (value < min || value > max) {
1818 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1819 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1820 object_get_typename(obj), name ? name : "null",
1821 value, min, max);
c8f0f88e
IM		 1822 return;
1823 }
1824 cpu->hyperv_spinlock_attempts = value;
1825}
1826
1827static PropertyInfo qdev_prop_spinlocks = {
1828 .name = "int",
1829 .get = x86_get_hv_spinlocks,
1830 .set = x86_set_hv_spinlocks,
1831};
1832
72ac2e87
IM		 1833/* Convert all '_' in a feature string option name to '-', to make feature
1834 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1835 */
1836static inline void feat2prop(char *s)
1837{
1838 while ((s = strchr(s, '_'))) {
1839 *s = '-';
1840 }
1841}
1842
8f961357
EH		 1843/* Parse "+feature,-feature,feature=foo" CPU feature string
1844 */
94a444b2
AF		 1845static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1846 Error **errp)
8f961357 1847{
94a444b2 1848 X86CPU *cpu = X86_CPU(cs);
8f961357 1849 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1850 FeatureWord w;
8f961357 1851 /* Features to be added */
077c68c3 1852 FeatureWordArray plus_features = { 0 };
8f961357 1853 /* Features to be removed */
5ef57876 1854 FeatureWordArray minus_features = { 0 };
8f961357 1855 uint32_t numvalue;
a91987c2 1856 CPUX86State *env = &cpu->env;
94a444b2 1857 Error *local_err = NULL;
8f961357 1858
8f961357 1859 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1860
1861 while (featurestr) {
1862 char *val;
1863 if (featurestr[0] == '+') {
c00c94ab 1864 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1865 } else if (featurestr[0] == '-') {
c00c94ab 1866 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1867 } else if ((val = strchr(featurestr, '='))) {
1868 *val = 0; val++;
72ac2e87 1869 feat2prop(featurestr);
d024d209 1870 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1871 char *err;
a91987c2
IM		 1872 char num[32];
1873
c6dc6f63
AP		 1874 numvalue = strtoul(val, &err, 0);
1875 if (!*val || *err) {
6b1dd54b
PB		 1876 error_setg(errp, "bad numerical value %s", val);
1877 return;
c6dc6f63
AP		 1878 }
1879 if (numvalue < 0x80000000) {
94a444b2
AF		 1880 error_report("xlevel value shall always be >= 0x80000000"
1881 ", fixup will be removed in future versions");
2f7a21c4 1882 numvalue += 0x80000000;
c6dc6f63 1883 }
a91987c2 1884 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1885 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1886 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1887 int64_t tsc_freq;
1888 char *err;
a91987c2 1889 char num[32];
b862d1fe
JR		 1890
1891 tsc_freq = strtosz_suffix_unit(val, &err,
1892 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1893 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1894 error_setg(errp, "bad numerical value %s", val);
1895 return;
b862d1fe 1896 }
a91987c2 1897 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1898 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1899 &local_err);
72ac2e87 1900 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1901 char *err;
92067bf4 1902 const int min = 0xFFF;
c8f0f88e 1903 char num[32];
28f52cc0
VR		 1904 numvalue = strtoul(val, &err, 0);
1905 if (!*val || *err) {
6b1dd54b
PB		 1906 error_setg(errp, "bad numerical value %s", val);
1907 return;
28f52cc0 1908 }
92067bf4 1909 if (numvalue < min) {
94a444b2 1910 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1911 ", fixup will be removed in future versions",
1912 min);
92067bf4
IM		 1913 numvalue = min;
1914 }
c8f0f88e 1915 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1916 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1917 } else {
94a444b2 1918 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1919 }
c6dc6f63 1920 } else {
258f5abe 1921 feat2prop(featurestr);
94a444b2 1922 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1923 }
94a444b2
AF		 1924 if (local_err) {
1925 error_propagate(errp, local_err);
6b1dd54b 1926 return;
c6dc6f63
AP		 1927 }
1928 featurestr = strtok(NULL, ",");
1929 }
e1c224b4 1930
4d1b279b
EH		 1931 if (cpu->host_features) {
1932 for (w = 0; w < FEATURE_WORDS; w++) {
1933 env->features[w] =
1934 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1935 }
1936 }
1937
e1c224b4
EH		 1938 for (w = 0; w < FEATURE_WORDS; w++) {
1939 env->features[w] |= plus_features[w];
1940 env->features[w] &= ~minus_features[w];
1941 }
c6dc6f63
AP		 1942}
1943
8c3329e5 1944/* Print all cpuid feature names in featureset
c6dc6f63 1945 */
8c3329e5 1946static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1947{
8c3329e5
EH		 1948 int bit;
1949 bool first = true;
1950
1951 for (bit = 0; bit < 32; bit++) {
1952 if (featureset[bit]) {
1953 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1954 first = false;
c6dc6f63 1955 }
8c3329e5 1956 }
c6dc6f63
AP		 1957}
1958
e916cbf8
PM		 1959/* generate CPU information. */
1960void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1961{
9576de75 1962 X86CPUDefinition *def;
c6dc6f63 1963 char buf[256];
7fc9b714 1964 int i;
c6dc6f63 1965
7fc9b714
AF		 1966 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1967 def = &builtin_x86_defs[i];
c04321b3 1968 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1969 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1970 }
21ad7789
JK		 1971#ifdef CONFIG_KVM
1972 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1973 "KVM processor with all supported host features "
1974 "(only available in KVM mode)");
1975#endif
1976
6cdf8854 1977 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1978 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1979 FeatureWordInfo *fw = &feature_word_info[i];
1980
8c3329e5
EH		 1981 (*cpu_fprintf)(f, " ");
1982 listflags(f, cpu_fprintf, fw->feat_names);
1983 (*cpu_fprintf)(f, "\n");
3af60be2 1984 }
c6dc6f63
AP		 1985}
1986
76b64a7a 1987CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1988{
1989 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1990 X86CPUDefinition *def;
7fc9b714 1991 int i;
e3966126 1992
7fc9b714 1993 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1994 CpuDefinitionInfoList *entry;
1995 CpuDefinitionInfo *info;
1996
7fc9b714 1997 def = &builtin_x86_defs[i];
e3966126
AL		 1998 info = g_malloc0(sizeof(*info));
1999 info->name = g_strdup(def->name);
2000
2001 entry = g_malloc0(sizeof(*entry));
2002 entry->value = info;
2003 entry->next = cpu_list;
2004 cpu_list = entry;
2005 }
2006
2007 return cpu_list;
2008}
2009
84f1b92f
EH		 2010static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2011 bool migratable_only)
27418adf
EH		 2012{
2013 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2014 uint32_t r;
27418adf 2015
fefb41bf 2016 if (kvm_enabled()) {
84f1b92f
EH		 2017 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2018 wi->cpuid_ecx,
2019 wi->cpuid_reg);
fefb41bf 2020 } else if (tcg_enabled()) {
84f1b92f 2021 r = wi->tcg_features;
fefb41bf
EH		 2022 } else {
2023 return ~0;
2024 }
84f1b92f
EH		 2025 if (migratable_only) {
2026 r &= x86_cpu_get_migratable_flags(w);
2027 }
2028 return r;
27418adf
EH		 2029}
2030
51f63aed
EH		 2031/*
2032 * Filters CPU feature words based on host availability of each feature.
2033 *
51f63aed
EH		 2034 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2035 */
27418adf 2036static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2037{
2038 CPUX86State *env = &cpu->env;
bd87d2a2 2039 FeatureWord w;
51f63aed
EH		 2040 int rv = 0;
2041
bd87d2a2 2042 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2043 uint32_t host_feat =
2044 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2045 uint32_t requested_features = env->features[w];
2046 env->features[w] &= host_feat;
2047 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2048 if (cpu->filtered_features[w]) {
2049 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2050 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2051 }
2052 rv = 1;
2053 }
bd87d2a2 2054 }
51f63aed
EH		 2055
2056 return rv;
bc74b7db 2057}
bc74b7db 2058
d940ee9b 2059/* Load data from X86CPUDefinition
c080e30e 2060 */
d940ee9b 2061static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2062{
61dcd775 2063 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2064 const char *vendor;
2065 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2066 FeatureWord w;
c6dc6f63 2067
2d64255b
AF		 2068 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2069 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2070 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2071 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2072 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2073 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
787aaf57 2074 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2075 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2076 for (w = 0; w < FEATURE_WORDS; w++) {
2077 env->features[w] = def->features[w];
2078 }
82beb536 2079
9576de75 2080 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2081 if (kvm_enabled()) {
5fcca9ff
EH		 2082 FeatureWord w;
2083 for (w = 0; w < FEATURE_WORDS; w++) {
2084 env->features[w] |= kvm_default_features[w];
136a7e9a 2085 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2086 }
82beb536 2087 }
5fcca9ff 2088
82beb536 2089 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2090
2091 /* sysenter isn't supported in compatibility mode on AMD,
2092 * syscall isn't supported in compatibility mode on Intel.
2093 * Normally we advertise the actual CPU vendor, but you can
2094 * override this using the 'vendor' property if you want to use
2095 * KVM's sysenter/syscall emulation in compatibility mode and
2096 * when doing cross vendor migration
2097 */
74f54bc4 2098 vendor = def->vendor;
7c08db30
EH		 2099 if (kvm_enabled()) {
2100 uint32_t ebx = 0, ecx = 0, edx = 0;
2101 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2102 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2103 vendor = host_vendor;
2104 }
2105
2106 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2107
c6dc6f63
AP		 2108}
2109
e1570d00 2110X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2111{
2d64255b 2112 X86CPU *cpu = NULL;
d940ee9b 2113 X86CPUClass *xcc;
500050d1 2114 ObjectClass *oc;
2d64255b
AF		 2115 gchar **model_pieces;
2116 char *name, *features;
5c3c6a68
AF		 2117 Error *error = NULL;
2118
2d64255b
AF		 2119 model_pieces = g_strsplit(cpu_model, ",", 2);
2120 if (!model_pieces[0]) {
2121 error_setg(&error, "Invalid/empty CPU model name");
2122 goto out;
2123 }
2124 name = model_pieces[0];
2125 features = model_pieces[1];
2126
500050d1
AF		 2127 oc = x86_cpu_class_by_name(name);
2128 if (oc == NULL) {
2129 error_setg(&error, "Unable to find CPU definition: %s", name);
2130 goto out;
2131 }
d940ee9b
EH		 2132 xcc = X86_CPU_CLASS(oc);
2133
2134 if (xcc->kvm_required && !kvm_enabled()) {
2135 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2136 goto out;
2137 }
2138
d940ee9b
EH		 2139 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2140
94a444b2 2141 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2142 if (error) {
2143 goto out;
5c3c6a68
AF		 2144 }
2145
7f833247 2146out:
cd7b87ff
AF		 2147 if (error != NULL) {
2148 error_propagate(errp, error);
500050d1
AF		 2149 if (cpu) {
2150 object_unref(OBJECT(cpu));
2151 cpu = NULL;
2152 }
cd7b87ff 2153 }
7f833247
IM		 2154 g_strfreev(model_pieces);
2155 return cpu;
2156}
2157
0856579c 2158X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2159{
2160 Error *error = NULL;
2161 X86CPU *cpu;
2162
e1570d00 2163 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2164 if (error) {
0856579c 2165 goto out;
9c235e83 2166 }
7f833247 2167
7f833247 2168 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2169
0856579c
PM		 2170out:
2171 if (error) {
2172 error_report_err(error);
2173 if (cpu != NULL) {
2174 object_unref(OBJECT(cpu));
2175 cpu = NULL;
2176 }
18b0e4e7 2177 }
0856579c 2178 return cpu;
5c3c6a68
AF		 2179}
2180
d940ee9b
EH		 2181static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2182{
2183 X86CPUDefinition *cpudef = data;
2184 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2185
2186 xcc->cpu_def = cpudef;
2187}
2188
2189static void x86_register_cpudef_type(X86CPUDefinition *def)
2190{
2191 char *typename = x86_cpu_type_name(def->name);
2192 TypeInfo ti = {
2193 .name = typename,
2194 .parent = TYPE_X86_CPU,
2195 .class_init = x86_cpu_cpudef_class_init,
2196 .class_data = def,
2197 };
2198
2199 type_register(&ti);
2200 g_free(typename);
2201}
2202
c6dc6f63 2203#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2204
0e26b7b8
BS		 2205void cpu_clear_apic_feature(CPUX86State *env)
2206{
0514ef2f 2207 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2208}
2209
c6dc6f63
AP		 2210#endif /* !CONFIG_USER_ONLY */
2211
c04321b3 2212/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2213 */
2214void x86_cpudef_setup(void)
2215{
93bfef4c
CV		 2216 int i, j;
2217 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2218
2219 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2220 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2221
2222 /* Look for specific "cpudef" models that */
09faecf2 2223 /* have the QEMU version in .model_id */
93bfef4c 2224 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2225 if (strcmp(model_with_versions[j], def->name) == 0) {
2226 pstrcpy(def->model_id, sizeof(def->model_id),
2227 "QEMU Virtual CPU version ");
2228 pstrcat(def->model_id, sizeof(def->model_id),
2229 qemu_get_version());
93bfef4c
CV		 2230 break;
2231 }
2232 }
c6dc6f63 2233 }
c6dc6f63
AP		 2234}
2235
c6dc6f63
AP		 2236void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2237 uint32_t *eax, uint32_t *ebx,
2238 uint32_t *ecx, uint32_t *edx)
2239{
a60f24b5
AF		 2240 X86CPU *cpu = x86_env_get_cpu(env);
2241 CPUState *cs = CPU(cpu);
2242
c6dc6f63
AP		 2243 /* test if maximum index reached */
2244 if (index & 0x80000000) {
b3baa152
BW		 2245 if (index > env->cpuid_xlevel) {
2246 if (env->cpuid_xlevel2 > 0) {
2247 /* Handle the Centaur's CPUID instruction. */
2248 if (index > env->cpuid_xlevel2) {
2249 index = env->cpuid_xlevel2;
2250 } else if (index < 0xC0000000) {
2251 index = env->cpuid_xlevel;
2252 }
2253 } else {
57f26ae7
EH		 2254 /* Intel documentation states that invalid EAX input will
2255 * return the same information as EAX=cpuid_level
2256 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2257 */
2258 index = env->cpuid_level;
b3baa152
BW		 2259 }
2260 }
c6dc6f63
AP		 2261 } else {
2262 if (index > env->cpuid_level)
2263 index = env->cpuid_level;
2264 }
2265
2266 switch(index) {
2267 case 0:
2268 *eax = env->cpuid_level;
5eb2f7a4
EH		 2269 *ebx = env->cpuid_vendor1;
2270 *edx = env->cpuid_vendor2;
2271 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2272 break;
2273 case 1:
2274 *eax = env->cpuid_version;
7e72a45c
EH		 2275 *ebx = (cpu->apic_id << 24) |
2276 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2277 *ecx = env->features[FEAT_1_ECX];
2278 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2279 if (cs->nr_cores * cs->nr_threads > 1) {
2280 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2281 *edx |= 1 << 28; /* HTT bit */
2282 }
2283 break;
2284 case 2:
2285 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2286 if (cpu->cache_info_passthrough) {
2287 host_cpuid(index, 0, eax, ebx, ecx, edx);
2288 break;
2289 }
5e891bf8 2290 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2291 *ebx = 0;
2292 *ecx = 0;
5e891bf8
EH		 2293 *edx = (L1D_DESCRIPTOR << 16) | \
2294 (L1I_DESCRIPTOR << 8) | \
2295 (L2_DESCRIPTOR);
c6dc6f63
AP		 2296 break;
2297 case 4:
2298 /* cache info: needed for Core compatibility */
787aaf57
BC		 2299 if (cpu->cache_info_passthrough) {
2300 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2301 *eax &= ~0xFC000000;
c6dc6f63 2302 } else {
2f7a21c4 2303 *eax = 0;
76c2975a 2304 switch (count) {
c6dc6f63 2305 case 0: /* L1 dcache info */
5e891bf8
EH		 2306 *eax |= CPUID_4_TYPE_DCACHE | \
2307 CPUID_4_LEVEL(1) | \
2308 CPUID_4_SELF_INIT_LEVEL;
2309 *ebx = (L1D_LINE_SIZE - 1) | \
2310 ((L1D_PARTITIONS - 1) << 12) | \
2311 ((L1D_ASSOCIATIVITY - 1) << 22);
2312 *ecx = L1D_SETS - 1;
2313 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2314 break;
2315 case 1: /* L1 icache info */
5e891bf8
EH		 2316 *eax |= CPUID_4_TYPE_ICACHE | \
2317 CPUID_4_LEVEL(1) | \
2318 CPUID_4_SELF_INIT_LEVEL;
2319 *ebx = (L1I_LINE_SIZE - 1) | \
2320 ((L1I_PARTITIONS - 1) << 12) | \
2321 ((L1I_ASSOCIATIVITY - 1) << 22);
2322 *ecx = L1I_SETS - 1;
2323 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2324 break;
2325 case 2: /* L2 cache info */
5e891bf8
EH		 2326 *eax |= CPUID_4_TYPE_UNIFIED | \
2327 CPUID_4_LEVEL(2) | \
2328 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2329 if (cs->nr_threads > 1) {
2330 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2331 }
5e891bf8
EH		 2332 *ebx = (L2_LINE_SIZE - 1) | \
2333 ((L2_PARTITIONS - 1) << 12) | \
2334 ((L2_ASSOCIATIVITY - 1) << 22);
2335 *ecx = L2_SETS - 1;
2336 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2337 break;
2338 default: /* end of info */
2339 *eax = 0;
2340 *ebx = 0;
2341 *ecx = 0;
2342 *edx = 0;
2343 break;
76c2975a
PB		 2344 }
2345 }
2346
2347 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2348 if ((*eax & 31) && cs->nr_cores > 1) {
2349 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2350 }
2351 break;
2352 case 5:
2353 /* mwait info: needed for Core compatibility */
2354 *eax = 0; /* Smallest monitor-line size in bytes */
2355 *ebx = 0; /* Largest monitor-line size in bytes */
2356 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2357 *edx = 0;
2358 break;
2359 case 6:
2360 /* Thermal and Power Leaf */
2361 *eax = 0;
2362 *ebx = 0;
2363 *ecx = 0;
2364 *edx = 0;
2365 break;
f7911686 2366 case 7:
13526728
EH		 2367 /* Structured Extended Feature Flags Enumeration Leaf */
2368 if (count == 0) {
2369 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2370 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2371 *ecx = 0; /* Reserved */
2372 *edx = 0; /* Reserved */
f7911686
YW		 2373 } else {
2374 *eax = 0;
2375 *ebx = 0;
2376 *ecx = 0;
2377 *edx = 0;
2378 }
2379 break;
c6dc6f63
AP		 2380 case 9:
2381 /* Direct Cache Access Information Leaf */
2382 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2383 *ebx = 0;
2384 *ecx = 0;
2385 *edx = 0;
2386 break;
2387 case 0xA:
2388 /* Architectural Performance Monitoring Leaf */
9337e3b6 2389 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2390 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2391
2392 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2393 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2394 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2395 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2396 } else {
2397 *eax = 0;
2398 *ebx = 0;
2399 *ecx = 0;
2400 *edx = 0;
2401 }
c6dc6f63 2402 break;
2560f19f
PB		 2403 case 0xD: {
2404 KVMState *s = cs->kvm_state;
2405 uint64_t kvm_mask;
2406 int i;
2407
51e49430 2408 /* Processor Extended State */
2560f19f
PB		 2409 *eax = 0;
2410 *ebx = 0;
2411 *ecx = 0;
2412 *edx = 0;
2413 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2414 break;
2415 }
2560f19f
PB		 2416 kvm_mask =
2417 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2418 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2419
2560f19f
PB		 2420 if (count == 0) {
2421 *ecx = 0x240;
2422 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2423 const ExtSaveArea *esa = &ext_save_areas[i];
2424 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2425 (kvm_mask & (1 << i)) != 0) {
2426 if (i < 32) {
2427 *eax |= 1 << i;
2428 } else {
2429 *edx |= 1 << (i - 32);
2430 }
2431 *ecx = MAX(*ecx, esa->offset + esa->size);
2432 }
2433 }
2434 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2435 *ebx = *ecx;
2436 } else if (count == 1) {
0bb0b2d2 2437 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2438 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2439 const ExtSaveArea *esa = &ext_save_areas[count];
2440 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2441 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2442 *eax = esa->size;
2443 *ebx = esa->offset;
2560f19f 2444 }
51e49430
SY		 2445 }
2446 break;
2560f19f 2447 }
c6dc6f63
AP		 2448 case 0x80000000:
2449 *eax = env->cpuid_xlevel;
2450 *ebx = env->cpuid_vendor1;
2451 *edx = env->cpuid_vendor2;
2452 *ecx = env->cpuid_vendor3;
2453 break;
2454 case 0x80000001:
2455 *eax = env->cpuid_version;
2456 *ebx = 0;
0514ef2f
EH		 2457 *ecx = env->features[FEAT_8000_0001_ECX];
2458 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2459
2460 /* The Linux kernel checks for the CMPLegacy bit and
2461 * discards multiple thread information if it is set.
2462 * So dont set it here for Intel to make Linux guests happy.
2463 */
ce3960eb 2464 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2465 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2466 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2467 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2468 *ecx |= 1 << 1; /* CmpLegacy bit */
2469 }
2470 }
c6dc6f63
AP		 2471 break;
2472 case 0x80000002:
2473 case 0x80000003:
2474 case 0x80000004:
2475 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2476 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2477 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2478 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2479 break;
2480 case 0x80000005:
2481 /* cache info (L1 cache) */
787aaf57
BC		 2482 if (cpu->cache_info_passthrough) {
2483 host_cpuid(index, 0, eax, ebx, ecx, edx);
2484 break;
2485 }
5e891bf8
EH		 2486 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2487 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2488 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2489 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2490 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2491 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2492 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2493 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2494 break;
2495 case 0x80000006:
2496 /* cache info (L2 cache) */
787aaf57
BC		 2497 if (cpu->cache_info_passthrough) {
2498 host_cpuid(index, 0, eax, ebx, ecx, edx);
2499 break;
2500 }
5e891bf8
EH		 2501 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2502 (L2_DTLB_2M_ENTRIES << 16) | \
2503 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2504 (L2_ITLB_2M_ENTRIES);
2505 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2506 (L2_DTLB_4K_ENTRIES << 16) | \
2507 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2508 (L2_ITLB_4K_ENTRIES);
2509 *ecx = (L2_SIZE_KB_AMD << 16) | \
2510 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2511 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2512 *edx = ((L3_SIZE_KB/512) << 18) | \
2513 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2514 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2515 break;
303752a9
MT		 2516 case 0x80000007:
2517 *eax = 0;
2518 *ebx = 0;
2519 *ecx = 0;
2520 *edx = env->features[FEAT_8000_0007_EDX];
2521 break;
c6dc6f63
AP		 2522 case 0x80000008:
2523 /* virtual & phys address size in low 2 bytes. */
2524/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2525 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2526 /* 64 bit processor */
2527/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2528 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2529 } else {
0514ef2f 2530 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2531 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2532 } else {
c6dc6f63 2533 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2534 }
c6dc6f63
AP		 2535 }
2536 *ebx = 0;
2537 *ecx = 0;
2538 *edx = 0;
ce3960eb
AF		 2539 if (cs->nr_cores * cs->nr_threads > 1) {
2540 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2541 }
2542 break;
2543 case 0x8000000A:
0514ef2f 2544 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2545 *eax = 0x00000001; /* SVM Revision */
2546 *ebx = 0x00000010; /* nr of ASIDs */
2547 *ecx = 0;
0514ef2f 2548 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2549 } else {
2550 *eax = 0;
2551 *ebx = 0;
2552 *ecx = 0;
2553 *edx = 0;
2554 }
c6dc6f63 2555 break;
b3baa152
BW		 2556 case 0xC0000000:
2557 *eax = env->cpuid_xlevel2;
2558 *ebx = 0;
2559 *ecx = 0;
2560 *edx = 0;
2561 break;
2562 case 0xC0000001:
2563 /* Support for VIA CPU's CPUID instruction */
2564 *eax = env->cpuid_version;
2565 *ebx = 0;
2566 *ecx = 0;
0514ef2f 2567 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2568 break;
2569 case 0xC0000002:
2570 case 0xC0000003:
2571 case 0xC0000004:
2572 /* Reserved for the future, and now filled with zero */
2573 *eax = 0;
2574 *ebx = 0;
2575 *ecx = 0;
2576 *edx = 0;
2577 break;
c6dc6f63
AP		 2578 default:
2579 /* reserved values: zero */
2580 *eax = 0;
2581 *ebx = 0;
2582 *ecx = 0;
2583 *edx = 0;
2584 break;
2585 }
2586}
5fd2087a
AF		 2587
2588/* CPUClass::reset() */
2589static void x86_cpu_reset(CPUState *s)
2590{
2591 X86CPU *cpu = X86_CPU(s);
2592 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2593 CPUX86State *env = &cpu->env;
c1958aea
AF		 2594 int i;
2595
5fd2087a
AF		 2596 xcc->parent_reset(s);
2597
43175fa9 2598 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2599
00c8cb0a 2600 tlb_flush(s, 1);
c1958aea
AF		 2601
2602 env->old_exception = -1;
2603
2604 /* init to reset state */
2605
2606#ifdef CONFIG_SOFTMMU
2607 env->hflags |= HF_SOFTMMU_MASK;
2608#endif
2609 env->hflags2 |= HF2_GIF_MASK;
2610
2611 cpu_x86_update_cr0(env, 0x60000010);
2612 env->a20_mask = ~0x0;
2613 env->smbase = 0x30000;
2614
2615 env->idt.limit = 0xffff;
2616 env->gdt.limit = 0xffff;
2617 env->ldt.limit = 0xffff;
2618 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2619 env->tr.limit = 0xffff;
2620 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2621
2622 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2623 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2624 DESC_R_MASK | DESC_A_MASK);
2625 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2626 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2627 DESC_A_MASK);
2628 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2629 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2630 DESC_A_MASK);
2631 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2632 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2633 DESC_A_MASK);
2634 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2635 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2636 DESC_A_MASK);
2637 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2638 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2639 DESC_A_MASK);
2640
2641 env->eip = 0xfff0;
2642 env->regs[R_EDX] = env->cpuid_version;
2643
2644 env->eflags = 0x2;
2645
2646 /* FPU init */
2647 for (i = 0; i < 8; i++) {
2648 env->fptags[i] = 1;
2649 }
5bde1407 2650 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2651
2652 env->mxcsr = 0x1f80;
c74f41bb 2653 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2654
2655 env->pat = 0x0007040600070406ULL;
2656 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2657
2658 memset(env->dr, 0, sizeof(env->dr));
2659 env->dr[6] = DR6_FIXED_1;
2660 env->dr[7] = DR7_FIXED_1;
b3310ab3 2661 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2662 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2663
05e7e819 2664 env->xcr0 = 1;
0522604b 2665
9db2efd9
AW		 2666 /*
2667 * SDM 11.11.5 requires:
2668 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2669 * - IA32_MTRR_PHYSMASKn.V = 0
2670 * All other bits are undefined. For simplification, zero it all.
2671 */
2672 env->mtrr_deftype = 0;
2673 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2674 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2675
dd673288
IM		 2676#if !defined(CONFIG_USER_ONLY)
2677 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2678 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2679
259186a7 2680 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2681
2682 if (kvm_enabled()) {
2683 kvm_arch_reset_vcpu(cpu);
2684 }
dd673288 2685#endif
5fd2087a
AF		 2686}
2687
dd673288
IM		 2688#ifndef CONFIG_USER_ONLY
2689bool cpu_is_bsp(X86CPU *cpu)
2690{
02e51483 2691 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2692}
65dee380
IM		 2693
2694/* TODO: remove me, when reset over QOM tree is implemented */
2695static void x86_cpu_machine_reset_cb(void *opaque)
2696{
2697 X86CPU *cpu = opaque;
2698 cpu_reset(CPU(cpu));
2699}
dd673288
IM		 2700#endif
2701
de024815
AF		 2702static void mce_init(X86CPU *cpu)
2703{
2704 CPUX86State *cenv = &cpu->env;
2705 unsigned int bank;
2706
2707 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2708 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2709 (CPUID_MCE | CPUID_MCA)) {
2710 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2711 cenv->mcg_ctl = ~(uint64_t)0;
2712 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2713 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2714 }
2715 }
2716}
2717
bdeec802 2718#ifndef CONFIG_USER_ONLY
d3c64d6a 2719static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2720{
53a89e26 2721 DeviceState *dev = DEVICE(cpu);
449994eb 2722 APICCommonState *apic;
bdeec802
IM		 2723 const char *apic_type = "apic";
2724
2725 if (kvm_irqchip_in_kernel()) {
2726 apic_type = "kvm-apic";
2727 } else if (xen_enabled()) {
2728 apic_type = "xen-apic";
2729 }
2730
02e51483
CF		 2731 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2732 if (cpu->apic_state == NULL) {
bdeec802
IM		 2733 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2734 return;
2735 }
2736
2737 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2738 OBJECT(cpu->apic_state), NULL);
7e72a45c 2739 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2740 /* TODO: convert to link<> */
02e51483 2741 apic = APIC_COMMON(cpu->apic_state);
60671e58 2742 apic->cpu = cpu;
d3c64d6a
IM		 2743}
2744
2745static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2746{
02e51483 2747 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2748 return;
2749 }
6e8e2651
MA		 2750 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2751 errp);
bdeec802 2752}
f809c605
PB		 2753
2754static void x86_cpu_machine_done(Notifier *n, void *unused)
2755{
2756 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2757 MemoryRegion *smram =
2758 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2759
2760 if (smram) {
2761 cpu->smram = g_new(MemoryRegion, 1);
2762 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2763 smram, 0, 1ull << 32);
2764 memory_region_set_enabled(cpu->smram, false);
2765 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2766 }
2767}
d3c64d6a
IM		 2768#else
2769static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2770{
2771}
bdeec802
IM		 2772#endif
2773
e48638fd
WH		 2774
2775#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2776 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2777 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2778#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2779 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2780 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2781static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2782{
14a10fc3 2783 CPUState *cs = CPU(dev);
2b6f294c
AF		 2784 X86CPU *cpu = X86_CPU(dev);
2785 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2786 CPUX86State *env = &cpu->env;
2b6f294c 2787 Error *local_err = NULL;
e48638fd 2788 static bool ht_warned;
b34d12d1 2789
9886e834
EH		 2790 if (cpu->apic_id < 0) {
2791 error_setg(errp, "apic-id property was not initialized properly");
2792 return;
2793 }
2794
0514ef2f 2795 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2796 env->cpuid_level = 7;
2797 }
7a059953 2798
9b15cd9e
IM		 2799 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2800 * CPUID[1].EDX.
2801 */
e48638fd 2802 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2803 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2804 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2805 & CPUID_EXT2_AMD_ALIASES);
2806 }
2807
fefb41bf
EH		 2808
2809 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2810 error_setg(&local_err,
2811 kvm_enabled() ?
2812 "Host doesn't support requested features" :
2813 "TCG doesn't support requested features");
2814 goto out;
4586f157
IM		 2815 }
2816
65dee380
IM		 2817#ifndef CONFIG_USER_ONLY
2818 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2819
0514ef2f 2820 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2821 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2822 if (local_err != NULL) {
4dc1f449 2823 goto out;
bdeec802
IM		 2824 }
2825 }
65dee380
IM		 2826#endif
2827
7a059953 2828 mce_init(cpu);
2001d0cd
PB		 2829
2830#ifndef CONFIG_USER_ONLY
2831 if (tcg_enabled()) {
f809c605 2832 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd
PB		 2833 cpu->cpu_as_root = g_new(MemoryRegion, 1);
2834 cs->as = g_new(AddressSpace, 1);
f809c605
PB		 2835
2836 /* Outer container... */
2837 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2838 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2839
2840 /* ... with two regions inside: normal system memory with low
2841 * priority, and...
2842 */
2843 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2844 get_system_memory(), 0, ~0ull);
2845 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2846 memory_region_set_enabled(cpu->cpu_as_mem, true);
2001d0cd 2847 address_space_init(cs->as, cpu->cpu_as_root, "CPU");
f809c605
PB		 2848
2849 /* ... SMRAM with higher priority, linked from /machine/smram. */
2850 cpu->machine_done.notify = x86_cpu_machine_done;
2851 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2852 }
2853#endif
2854
14a10fc3 2855 qemu_init_vcpu(cs);
d3c64d6a 2856
e48638fd
WH		 2857 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2858 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2859 * based on inputs (sockets,cores,threads), it is still better to gives
2860 * users a warning.
2861 *
2862 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2863 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2864 */
2865 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2866 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2867 " -smp options properly.");
2868 ht_warned = true;
2869 }
2870
d3c64d6a
IM		 2871 x86_cpu_apic_realize(cpu, &local_err);
2872 if (local_err != NULL) {
2873 goto out;
2874 }
14a10fc3 2875 cpu_reset(cs);
2b6f294c 2876
4dc1f449 2877 xcc->parent_realize(dev, &local_err);
2001d0cd 2878
4dc1f449
IM		 2879out:
2880 if (local_err != NULL) {
2881 error_propagate(errp, local_err);
2882 return;
2883 }
7a059953
AF		 2884}
2885
38e5c119
EH		 2886typedef struct BitProperty {
2887 uint32_t *ptr;
2888 uint32_t mask;
2889} BitProperty;
2890
2891static void x86_cpu_get_bit_prop(Object *obj,
2892 struct Visitor *v,
2893 void *opaque,
2894 const char *name,
2895 Error **errp)
2896{
2897 BitProperty *fp = opaque;
2898 bool value = (*fp->ptr & fp->mask) == fp->mask;
2899 visit_type_bool(v, &value, name, errp);
2900}
2901
2902static void x86_cpu_set_bit_prop(Object *obj,
2903 struct Visitor *v,
2904 void *opaque,
2905 const char *name,
2906 Error **errp)
2907{
2908 DeviceState *dev = DEVICE(obj);
2909 BitProperty *fp = opaque;
2910 Error *local_err = NULL;
2911 bool value;
2912
2913 if (dev->realized) {
2914 qdev_prop_set_after_realize(dev, name, errp);
2915 return;
2916 }
2917
2918 visit_type_bool(v, &value, name, &local_err);
2919 if (local_err) {
2920 error_propagate(errp, local_err);
2921 return;
2922 }
2923
2924 if (value) {
2925 *fp->ptr |= fp->mask;
2926 } else {
2927 *fp->ptr &= ~fp->mask;
2928 }
2929}
2930
2931static void x86_cpu_release_bit_prop(Object *obj, const char *name,
2932 void *opaque)
2933{
2934 BitProperty *prop = opaque;
2935 g_free(prop);
2936}
2937
2938/* Register a boolean property to get/set a single bit in a uint32_t field.
2939 *
2940 * The same property name can be registered multiple times to make it affect
2941 * multiple bits in the same FeatureWord. In that case, the getter will return
2942 * true only if all bits are set.
2943 */
2944static void x86_cpu_register_bit_prop(X86CPU *cpu,
2945 const char *prop_name,
2946 uint32_t *field,
2947 int bitnr)
2948{
2949 BitProperty *fp;
2950 ObjectProperty *op;
2951 uint32_t mask = (1UL << bitnr);
2952
2953 op = object_property_find(OBJECT(cpu), prop_name, NULL);
2954 if (op) {
2955 fp = op->opaque;
2956 assert(fp->ptr == field);
2957 fp->mask |= mask;
2958 } else {
2959 fp = g_new0(BitProperty, 1);
2960 fp->ptr = field;
2961 fp->mask = mask;
2962 object_property_add(OBJECT(cpu), prop_name, "bool",
2963 x86_cpu_get_bit_prop,
2964 x86_cpu_set_bit_prop,
2965 x86_cpu_release_bit_prop, fp, &error_abort);
2966 }
2967}
2968
2969static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
2970 FeatureWord w,
2971 int bitnr)
2972{
2973 Object *obj = OBJECT(cpu);
2974 int i;
2975 char **names;
2976 FeatureWordInfo *fi = &feature_word_info[w];
2977
2978 if (!fi->feat_names) {
2979 return;
2980 }
2981 if (!fi->feat_names[bitnr]) {
2982 return;
2983 }
2984
2985 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
2986
2987 feat2prop(names[0]);
2988 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
2989
2990 for (i = 1; names[i]; i++) {
2991 feat2prop(names[i]);
2992 object_property_add_alias(obj, names[i], obj, g_strdup(names[0]),
2993 &error_abort);
2994 }
2995
2996 g_strfreev(names);
2997}
2998
de024815
AF		 2999static void x86_cpu_initfn(Object *obj)
3000{
55e5c285 3001 CPUState *cs = CPU(obj);
de024815 3002 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3003 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3004 CPUX86State *env = &cpu->env;
38e5c119 3005 FeatureWord w;
d65e9815 3006 static int inited;
de024815 3007
c05efcb1 3008 cs->env_ptr = env;
de024815 3009 cpu_exec_init(env);
71ad61d3
AF		 3010
3011 object_property_add(obj, "family", "int",
95b8519d 3012 x86_cpuid_version_get_family,
71ad61d3 3013 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3014 object_property_add(obj, "model", "int",
67e30c83 3015 x86_cpuid_version_get_model,
c5291a4f 3016 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3017 object_property_add(obj, "stepping", "int",
35112e41 3018 x86_cpuid_version_get_stepping,
036e2222 3019 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3020 object_property_add_str(obj, "vendor",
3021 x86_cpuid_get_vendor,
3022 x86_cpuid_set_vendor, NULL);
938d4c25 3023 object_property_add_str(obj, "model-id",
63e886eb 3024 x86_cpuid_get_model_id,
938d4c25 3025 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3026 object_property_add(obj, "tsc-frequency", "int",
3027 x86_cpuid_get_tsc_freq,
3028 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3029 object_property_add(obj, "apic-id", "int",
3030 x86_cpuid_get_apic_id,
3031 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3032 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3033 x86_cpu_get_feature_words,
7e5292b5
EH		 3034 NULL, NULL, (void *)env->features, NULL);
3035 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3036 x86_cpu_get_feature_words,
3037 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3038
92067bf4 3039 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3040
9886e834
EH		 3041#ifndef CONFIG_USER_ONLY
3042 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3043 cpu->apic_id = -1;
3044#endif
3045
38e5c119
EH		 3046 for (w = 0; w < FEATURE_WORDS; w++) {
3047 int bitnr;
3048
3049 for (bitnr = 0; bitnr < 32; bitnr++) {
3050 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3051 }
3052 }
3053
d940ee9b
EH		 3054 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3055
d65e9815
IM		 3056 /* init various static tables used in TCG mode */
3057 if (tcg_enabled() && !inited) {
3058 inited = 1;
3059 optimize_flags_init();
d65e9815 3060 }
de024815
AF		 3061}
3062
997395d3
IM		 3063static int64_t x86_cpu_get_arch_id(CPUState *cs)
3064{
3065 X86CPU *cpu = X86_CPU(cs);
997395d3 3066
7e72a45c 3067 return cpu->apic_id;
997395d3
IM		 3068}
3069
444d5590
AF		 3070static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3071{
3072 X86CPU *cpu = X86_CPU(cs);
3073
3074 return cpu->env.cr[0] & CR0_PG_MASK;
3075}
3076
f45748f1
AF		 3077static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3078{
3079 X86CPU *cpu = X86_CPU(cs);
3080
3081 cpu->env.eip = value;
3082}
3083
bdf7ae5b
AF		 3084static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3085{
3086 X86CPU *cpu = X86_CPU(cs);
3087
3088 cpu->env.eip = tb->pc - tb->cs_base;
3089}
3090
8c2e1b00
AF		 3091static bool x86_cpu_has_work(CPUState *cs)
3092{
3093 X86CPU *cpu = X86_CPU(cs);
3094 CPUX86State *env = &cpu->env;
3095
60e68042
PB		 3096#if !defined(CONFIG_USER_ONLY)
3097 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3098 apic_poll_irq(cpu->apic_state);
3099 cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
3100 }
3101#endif
3102
3103 return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
8c2e1b00
AF		 3104 (env->eflags & IF_MASK)) ||
3105 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3106 CPU_INTERRUPT_INIT |
3107 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3108 CPU_INTERRUPT_MCE)) ||
3109 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3110 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3111}
3112
9337e3b6
EH		 3113static Property x86_cpu_properties[] = {
3114 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3115 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3116 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3117 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3118 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 3119 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
3120 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3121 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3122 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3123 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3124 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
9337e3b6
EH		 3125 DEFINE_PROP_END_OF_LIST()
3126};
3127
5fd2087a
AF		 3128static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3129{
3130 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3131 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3132 DeviceClass *dc = DEVICE_CLASS(oc);
3133
3134 xcc->parent_realize = dc->realize;
3135 dc->realize = x86_cpu_realizefn;
62fc403f 3136 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 3137 dc->props = x86_cpu_properties;
5fd2087a
AF		 3138
3139 xcc->parent_reset = cc->reset;
3140 cc->reset = x86_cpu_reset;
91b1df8c 3141 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3142
500050d1 3143 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3144 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3145 cc->has_work = x86_cpu_has_work;
97a8ea5a 3146 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3147 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3148 cc->dump_state = x86_cpu_dump_state;
f45748f1 3149 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3150 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3151 cc->gdb_read_register = x86_cpu_gdb_read_register;
3152 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3153 cc->get_arch_id = x86_cpu_get_arch_id;
3154 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3155#ifdef CONFIG_USER_ONLY
3156 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3157#else
a23bbfda 3158 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3159 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3160 cc->write_elf64_note = x86_cpu_write_elf64_note;
3161 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3162 cc->write_elf32_note = x86_cpu_write_elf32_note;
3163 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3164 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3165#endif
a0e372f0 3166 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3167#ifndef CONFIG_USER_ONLY
3168 cc->debug_excp_handler = breakpoint_handler;
3169#endif
374e0cd4
RH		 3170 cc->cpu_exec_enter = x86_cpu_exec_enter;
3171 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 3172}
3173
3174static const TypeInfo x86_cpu_type_info = {
3175 .name = TYPE_X86_CPU,
3176 .parent = TYPE_CPU,
3177 .instance_size = sizeof(X86CPU),
de024815 3178 .instance_init = x86_cpu_initfn,
d940ee9b 3179 .abstract = true,
5fd2087a
AF		 3180 .class_size = sizeof(X86CPUClass),
3181 .class_init = x86_cpu_common_class_init,
3182};
3183
3184static void x86_cpu_register_types(void)
3185{
d940ee9b
EH		 3186 int i;
3187
5fd2087a 3188 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3189 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3190 x86_register_cpudef_type(&builtin_x86_defs[i]);
3191 }
3192#ifdef CONFIG_KVM
3193 type_register_static(&host_x86_cpu_type_info);
3194#endif
5fd2087a
AF		 3195}
3196
3197type_init(x86_cpu_register_types)
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