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KVM: x86: Allow the guest to run with dirty debug registers
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
8f536b76 46#include <asm/kexec.h>
6aa8b732 47
229456fc
MT		 48#include "trace.h"
49
4ecac3fd 50#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 51#define __ex_clear(x, reg) \
52 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 53
6aa8b732
AK		 54MODULE_AUTHOR("Qumranet");
55MODULE_LICENSE("GPL");
56
e9bda3b3
JT		 57static const struct x86_cpu_id vmx_cpu_id[] = {
58 X86_FEATURE_MATCH(X86_FEATURE_VMX),
59 {}
60};
61MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
62
476bc001 63static bool __read_mostly enable_vpid = 1;
736caefe 64module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 65
476bc001 66static bool __read_mostly flexpriority_enabled = 1;
736caefe 67module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 68
476bc001 69static bool __read_mostly enable_ept = 1;
736caefe 70module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 71
476bc001 72static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 73module_param_named(unrestricted_guest,
74 enable_unrestricted_guest, bool, S_IRUGO);
75
83c3a331
XH		 76static bool __read_mostly enable_ept_ad_bits = 1;
77module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
78
a27685c3 79static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 80module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 81
476bc001 82static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 83module_param(vmm_exclusive, bool, S_IRUGO);
84
476bc001 85static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 86module_param(fasteoi, bool, S_IRUGO);
87
5a71785d 88static bool __read_mostly enable_apicv = 1;
01e439be 89module_param(enable_apicv, bool, S_IRUGO);
83d4c286 90
abc4fc58
AG		 91static bool __read_mostly enable_shadow_vmcs = 1;
92module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 93/*
94 * If nested=1, nested virtualization is supported, i.e., guests may use
95 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
96 * use VMX instructions.
97 */
476bc001 98static bool __read_mostly nested = 0;
801d3424
NHE		 99module_param(nested, bool, S_IRUGO);
100
5037878e
GN		 101#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
102#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 103#define KVM_VM_CR0_ALWAYS_ON \
104 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 105#define KVM_CR4_GUEST_OWNED_BITS \
106 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
107 | X86_CR4_OSXMMEXCPT)
108
cdc0e244
AK		 109#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
110#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111
78ac8b47
AK		 112#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
113
f4124500
JK		 114#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
115
4b8d54f9
ZE		 116/*
117 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
118 * ple_gap: upper bound on the amount of time between two successive
119 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 120 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 121 * ple_window: upper bound on the amount of time a guest is allowed to execute
122 * in a PAUSE loop. Tests indicate that most spinlocks are held for
123 * less than 2^12 cycles
124 * Time is measured based on a counter that runs at the same rate as the TSC,
125 * refer SDM volume 3b section 21.6.13 & 22.1.3.
126 */
00c25bce 127#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 128#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
129static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
130module_param(ple_gap, int, S_IRUGO);
131
132static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
133module_param(ple_window, int, S_IRUGO);
134
83287ea4
AK		 135extern const ulong vmx_return;
136
8bf00a52 137#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 138#define VMCS02_POOL_SIZE 1
61d2ef2c 139
a2fa3e9f
GH		 140struct vmcs {
141 u32 revision_id;
142 u32 abort;
143 char data[0];
144};
145
d462b819
NHE		 146/*
147 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
148 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
149 * loaded on this CPU (so we can clear them if the CPU goes down).
150 */
151struct loaded_vmcs {
152 struct vmcs *vmcs;
153 int cpu;
154 int launched;
155 struct list_head loaded_vmcss_on_cpu_link;
156};
157
26bb0981
AK		 158struct shared_msr_entry {
159 unsigned index;
160 u64 data;
d5696725 161 u64 mask;
26bb0981
AK		 162};
163
a9d30f33
NHE		 164/*
165 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
166 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
167 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
168 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
169 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
170 * More than one of these structures may exist, if L1 runs multiple L2 guests.
171 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
172 * underlying hardware which will be used to run L2.
173 * This structure is packed to ensure that its layout is identical across
174 * machines (necessary for live migration).
175 * If there are changes in this struct, VMCS12_REVISION must be changed.
176 */
22bd0358 177typedef u64 natural_width;
a9d30f33
NHE		 178struct __packed vmcs12 {
179 /* According to the Intel spec, a VMCS region must start with the
180 * following two fields. Then follow implementation-specific data.
181 */
182 u32 revision_id;
183 u32 abort;
22bd0358 184
27d6c865
NHE		 185 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
186 u32 padding[7]; /* room for future expansion */
187
22bd0358
NHE		 188 u64 io_bitmap_a;
189 u64 io_bitmap_b;
190 u64 msr_bitmap;
191 u64 vm_exit_msr_store_addr;
192 u64 vm_exit_msr_load_addr;
193 u64 vm_entry_msr_load_addr;
194 u64 tsc_offset;
195 u64 virtual_apic_page_addr;
196 u64 apic_access_addr;
197 u64 ept_pointer;
198 u64 guest_physical_address;
199 u64 vmcs_link_pointer;
200 u64 guest_ia32_debugctl;
201 u64 guest_ia32_pat;
202 u64 guest_ia32_efer;
203 u64 guest_ia32_perf_global_ctrl;
204 u64 guest_pdptr0;
205 u64 guest_pdptr1;
206 u64 guest_pdptr2;
207 u64 guest_pdptr3;
208 u64 host_ia32_pat;
209 u64 host_ia32_efer;
210 u64 host_ia32_perf_global_ctrl;
211 u64 padding64[8]; /* room for future expansion */
212 /*
213 * To allow migration of L1 (complete with its L2 guests) between
214 * machines of different natural widths (32 or 64 bit), we cannot have
215 * unsigned long fields with no explict size. We use u64 (aliased
216 * natural_width) instead. Luckily, x86 is little-endian.
217 */
218 natural_width cr0_guest_host_mask;
219 natural_width cr4_guest_host_mask;
220 natural_width cr0_read_shadow;
221 natural_width cr4_read_shadow;
222 natural_width cr3_target_value0;
223 natural_width cr3_target_value1;
224 natural_width cr3_target_value2;
225 natural_width cr3_target_value3;
226 natural_width exit_qualification;
227 natural_width guest_linear_address;
228 natural_width guest_cr0;
229 natural_width guest_cr3;
230 natural_width guest_cr4;
231 natural_width guest_es_base;
232 natural_width guest_cs_base;
233 natural_width guest_ss_base;
234 natural_width guest_ds_base;
235 natural_width guest_fs_base;
236 natural_width guest_gs_base;
237 natural_width guest_ldtr_base;
238 natural_width guest_tr_base;
239 natural_width guest_gdtr_base;
240 natural_width guest_idtr_base;
241 natural_width guest_dr7;
242 natural_width guest_rsp;
243 natural_width guest_rip;
244 natural_width guest_rflags;
245 natural_width guest_pending_dbg_exceptions;
246 natural_width guest_sysenter_esp;
247 natural_width guest_sysenter_eip;
248 natural_width host_cr0;
249 natural_width host_cr3;
250 natural_width host_cr4;
251 natural_width host_fs_base;
252 natural_width host_gs_base;
253 natural_width host_tr_base;
254 natural_width host_gdtr_base;
255 natural_width host_idtr_base;
256 natural_width host_ia32_sysenter_esp;
257 natural_width host_ia32_sysenter_eip;
258 natural_width host_rsp;
259 natural_width host_rip;
260 natural_width paddingl[8]; /* room for future expansion */
261 u32 pin_based_vm_exec_control;
262 u32 cpu_based_vm_exec_control;
263 u32 exception_bitmap;
264 u32 page_fault_error_code_mask;
265 u32 page_fault_error_code_match;
266 u32 cr3_target_count;
267 u32 vm_exit_controls;
268 u32 vm_exit_msr_store_count;
269 u32 vm_exit_msr_load_count;
270 u32 vm_entry_controls;
271 u32 vm_entry_msr_load_count;
272 u32 vm_entry_intr_info_field;
273 u32 vm_entry_exception_error_code;
274 u32 vm_entry_instruction_len;
275 u32 tpr_threshold;
276 u32 secondary_vm_exec_control;
277 u32 vm_instruction_error;
278 u32 vm_exit_reason;
279 u32 vm_exit_intr_info;
280 u32 vm_exit_intr_error_code;
281 u32 idt_vectoring_info_field;
282 u32 idt_vectoring_error_code;
283 u32 vm_exit_instruction_len;
284 u32 vmx_instruction_info;
285 u32 guest_es_limit;
286 u32 guest_cs_limit;
287 u32 guest_ss_limit;
288 u32 guest_ds_limit;
289 u32 guest_fs_limit;
290 u32 guest_gs_limit;
291 u32 guest_ldtr_limit;
292 u32 guest_tr_limit;
293 u32 guest_gdtr_limit;
294 u32 guest_idtr_limit;
295 u32 guest_es_ar_bytes;
296 u32 guest_cs_ar_bytes;
297 u32 guest_ss_ar_bytes;
298 u32 guest_ds_ar_bytes;
299 u32 guest_fs_ar_bytes;
300 u32 guest_gs_ar_bytes;
301 u32 guest_ldtr_ar_bytes;
302 u32 guest_tr_ar_bytes;
303 u32 guest_interruptibility_info;
304 u32 guest_activity_state;
305 u32 guest_sysenter_cs;
306 u32 host_ia32_sysenter_cs;
0238ea91
JK		 307 u32 vmx_preemption_timer_value;
308 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 309 u16 virtual_processor_id;
310 u16 guest_es_selector;
311 u16 guest_cs_selector;
312 u16 guest_ss_selector;
313 u16 guest_ds_selector;
314 u16 guest_fs_selector;
315 u16 guest_gs_selector;
316 u16 guest_ldtr_selector;
317 u16 guest_tr_selector;
318 u16 host_es_selector;
319 u16 host_cs_selector;
320 u16 host_ss_selector;
321 u16 host_ds_selector;
322 u16 host_fs_selector;
323 u16 host_gs_selector;
324 u16 host_tr_selector;
a9d30f33
NHE		 325};
326
327/*
328 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
329 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
330 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
331 */
332#define VMCS12_REVISION 0x11e57ed0
333
334/*
335 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
336 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
337 * current implementation, 4K are reserved to avoid future complications.
338 */
339#define VMCS12_SIZE 0x1000
340
ff2f6fe9
NHE		 341/* Used to remember the last vmcs02 used for some recently used vmcs12s */
342struct vmcs02_list {
343 struct list_head list;
344 gpa_t vmptr;
345 struct loaded_vmcs vmcs02;
346};
347
ec378aee
NHE		 348/*
349 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
350 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
351 */
352struct nested_vmx {
353 /* Has the level1 guest done vmxon? */
354 bool vmxon;
a9d30f33
NHE		 355
356 /* The guest-physical address of the current VMCS L1 keeps for L2 */
357 gpa_t current_vmptr;
358 /* The host-usable pointer to the above */
359 struct page *current_vmcs12_page;
360 struct vmcs12 *current_vmcs12;
8de48833 361 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 362 /*
363 * Indicates if the shadow vmcs must be updated with the
364 * data hold by vmcs12
365 */
366 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 367
368 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
369 struct list_head vmcs02_pool;
370 int vmcs02_num;
fe3ef05c 371 u64 vmcs01_tsc_offset;
644d711a
NHE		 372 /* L2 must run next, and mustn't decide to exit to L1. */
373 bool nested_run_pending;
fe3ef05c
NHE		 374 /*
375 * Guest pages referred to in vmcs02 with host-physical pointers, so
376 * we must keep them pinned while L2 runs.
377 */
378 struct page *apic_access_page;
b3897a49 379 u64 msr_ia32_feature_control;
f4124500
JK		 380
381 struct hrtimer preemption_timer;
382 bool preemption_timer_expired;
ec378aee
NHE		 383};
384
01e439be
YZ		 385#define POSTED_INTR_ON 0
386/* Posted-Interrupt Descriptor */
387struct pi_desc {
388 u32 pir[8]; /* Posted interrupt requested */
389 u32 control; /* bit 0 of control is outstanding notification bit */
390 u32 rsvd[7];
391} __aligned(64);
392
a20ed54d
YZ		 393static bool pi_test_and_set_on(struct pi_desc *pi_desc)
394{
395 return test_and_set_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
400{
401 return test_and_clear_bit(POSTED_INTR_ON,
402 (unsigned long *)&pi_desc->control);
403}
404
405static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
406{
407 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
408}
409
a2fa3e9f 410struct vcpu_vmx {
fb3f0f51 411 struct kvm_vcpu vcpu;
313dbd49 412 unsigned long host_rsp;
29bd8a78 413 u8 fail;
69c73028 414 u8 cpl;
9d58b931 415 bool nmi_known_unmasked;
51aa01d1 416 u32 exit_intr_info;
1155f76a 417 u32 idt_vectoring_info;
6de12732 418 ulong rflags;
26bb0981 419 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 420 int nmsrs;
421 int save_nmsrs;
a547c6db 422 unsigned long host_idt_base;
a2fa3e9f 423#ifdef CONFIG_X86_64
44ea2b17
AK		 424 u64 msr_host_kernel_gs_base;
425 u64 msr_guest_kernel_gs_base;
a2fa3e9f 426#endif
2961e876
GN		 427 u32 vm_entry_controls_shadow;
428 u32 vm_exit_controls_shadow;
d462b819
NHE		 429 /*
430 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
431 * non-nested (L1) guest, it always points to vmcs01. For a nested
432 * guest (L2), it points to a different VMCS.
433 */
434 struct loaded_vmcs vmcs01;
435 struct loaded_vmcs *loaded_vmcs;
436 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 437 struct msr_autoload {
438 unsigned nr;
439 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
440 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
441 } msr_autoload;
a2fa3e9f
GH		 442 struct {
443 int loaded;
444 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 445#ifdef CONFIG_X86_64
446 u16 ds_sel, es_sel;
447#endif
152d3f2f
LV		 448 int gs_ldt_reload_needed;
449 int fs_reload_needed;
da8999d3 450 u64 msr_host_bndcfgs;
d77c26fc 451 } host_state;
9c8cba37 452 struct {
7ffd92c5 453 int vm86_active;
78ac8b47 454 ulong save_rflags;
f5f7b2fe
AK		 455 struct kvm_segment segs[8];
456 } rmode;
457 struct {
458 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 459 struct kvm_save_segment {
460 u16 selector;
461 unsigned long base;
462 u32 limit;
463 u32 ar;
f5f7b2fe 464 } seg[8];
2fb92db1 465 } segment_cache;
2384d2b3 466 int vpid;
04fa4d32 467 bool emulation_required;
3b86cd99
JK		 468
469 /* Support for vnmi-less CPUs */
470 int soft_vnmi_blocked;
471 ktime_t entry_time;
472 s64 vnmi_blocked_time;
a0861c02 473 u32 exit_reason;
4e47c7a6
SY		 474
475 bool rdtscp_enabled;
ec378aee 476
01e439be
YZ		 477 /* Posted interrupt descriptor */
478 struct pi_desc pi_desc;
479
ec378aee
NHE		 480 /* Support for a guest hypervisor (nested VMX) */
481 struct nested_vmx nested;
a2fa3e9f
GH		 482};
483
2fb92db1
AK		 484enum segment_cache_field {
485 SEG_FIELD_SEL = 0,
486 SEG_FIELD_BASE = 1,
487 SEG_FIELD_LIMIT = 2,
488 SEG_FIELD_AR = 3,
489
490 SEG_FIELD_NR = 4
491};
492
a2fa3e9f
GH		 493static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
494{
fb3f0f51 495 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 496}
497
22bd0358
NHE		 498#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
499#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
500#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
501 [number##_HIGH] = VMCS12_OFFSET(name)+4
502
4607c2d7
AG		 503
504static const unsigned long shadow_read_only_fields[] = {
505 /*
506 * We do NOT shadow fields that are modified when L0
507 * traps and emulates any vmx instruction (e.g. VMPTRLD,
508 * VMXON...) executed by L1.
509 * For example, VM_INSTRUCTION_ERROR is read
510 * by L1 if a vmx instruction fails (part of the error path).
511 * Note the code assumes this logic. If for some reason
512 * we start shadowing these fields then we need to
513 * force a shadow sync when L0 emulates vmx instructions
514 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
515 * by nested_vmx_failValid)
516 */
517 VM_EXIT_REASON,
518 VM_EXIT_INTR_INFO,
519 VM_EXIT_INSTRUCTION_LEN,
520 IDT_VECTORING_INFO_FIELD,
521 IDT_VECTORING_ERROR_CODE,
522 VM_EXIT_INTR_ERROR_CODE,
523 EXIT_QUALIFICATION,
524 GUEST_LINEAR_ADDRESS,
525 GUEST_PHYSICAL_ADDRESS
526};
527static const int max_shadow_read_only_fields =
528 ARRAY_SIZE(shadow_read_only_fields);
529
530static const unsigned long shadow_read_write_fields[] = {
531 GUEST_RIP,
532 GUEST_RSP,
533 GUEST_CR0,
534 GUEST_CR3,
535 GUEST_CR4,
536 GUEST_INTERRUPTIBILITY_INFO,
537 GUEST_RFLAGS,
538 GUEST_CS_SELECTOR,
539 GUEST_CS_AR_BYTES,
540 GUEST_CS_LIMIT,
541 GUEST_CS_BASE,
542 GUEST_ES_BASE,
543 CR0_GUEST_HOST_MASK,
544 CR0_READ_SHADOW,
545 CR4_READ_SHADOW,
546 TSC_OFFSET,
547 EXCEPTION_BITMAP,
548 CPU_BASED_VM_EXEC_CONTROL,
549 VM_ENTRY_EXCEPTION_ERROR_CODE,
550 VM_ENTRY_INTR_INFO_FIELD,
551 VM_ENTRY_INSTRUCTION_LEN,
552 VM_ENTRY_EXCEPTION_ERROR_CODE,
553 HOST_FS_BASE,
554 HOST_GS_BASE,
555 HOST_FS_SELECTOR,
556 HOST_GS_SELECTOR
557};
558static const int max_shadow_read_write_fields =
559 ARRAY_SIZE(shadow_read_write_fields);
560
772e0318 561static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 562 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
563 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
564 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
565 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
566 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
567 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
568 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
569 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
570 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
571 FIELD(HOST_ES_SELECTOR, host_es_selector),
572 FIELD(HOST_CS_SELECTOR, host_cs_selector),
573 FIELD(HOST_SS_SELECTOR, host_ss_selector),
574 FIELD(HOST_DS_SELECTOR, host_ds_selector),
575 FIELD(HOST_FS_SELECTOR, host_fs_selector),
576 FIELD(HOST_GS_SELECTOR, host_gs_selector),
577 FIELD(HOST_TR_SELECTOR, host_tr_selector),
578 FIELD64(IO_BITMAP_A, io_bitmap_a),
579 FIELD64(IO_BITMAP_B, io_bitmap_b),
580 FIELD64(MSR_BITMAP, msr_bitmap),
581 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
582 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
583 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
584 FIELD64(TSC_OFFSET, tsc_offset),
585 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
586 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
587 FIELD64(EPT_POINTER, ept_pointer),
588 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
589 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
590 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
591 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
592 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
593 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
594 FIELD64(GUEST_PDPTR0, guest_pdptr0),
595 FIELD64(GUEST_PDPTR1, guest_pdptr1),
596 FIELD64(GUEST_PDPTR2, guest_pdptr2),
597 FIELD64(GUEST_PDPTR3, guest_pdptr3),
598 FIELD64(HOST_IA32_PAT, host_ia32_pat),
599 FIELD64(HOST_IA32_EFER, host_ia32_efer),
600 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
601 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
602 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
603 FIELD(EXCEPTION_BITMAP, exception_bitmap),
604 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
605 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
606 FIELD(CR3_TARGET_COUNT, cr3_target_count),
607 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
608 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
609 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
610 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
611 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
612 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
613 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
614 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
615 FIELD(TPR_THRESHOLD, tpr_threshold),
616 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
617 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
618 FIELD(VM_EXIT_REASON, vm_exit_reason),
619 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
620 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
621 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
622 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
623 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
624 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
625 FIELD(GUEST_ES_LIMIT, guest_es_limit),
626 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
627 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
628 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
629 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
630 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
631 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
632 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
633 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
634 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
635 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
636 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
637 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
638 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
639 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
640 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
641 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
642 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
643 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
644 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
645 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
646 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 647 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 648 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
649 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
650 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
651 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
652 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
653 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
654 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
655 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
656 FIELD(EXIT_QUALIFICATION, exit_qualification),
657 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
658 FIELD(GUEST_CR0, guest_cr0),
659 FIELD(GUEST_CR3, guest_cr3),
660 FIELD(GUEST_CR4, guest_cr4),
661 FIELD(GUEST_ES_BASE, guest_es_base),
662 FIELD(GUEST_CS_BASE, guest_cs_base),
663 FIELD(GUEST_SS_BASE, guest_ss_base),
664 FIELD(GUEST_DS_BASE, guest_ds_base),
665 FIELD(GUEST_FS_BASE, guest_fs_base),
666 FIELD(GUEST_GS_BASE, guest_gs_base),
667 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
668 FIELD(GUEST_TR_BASE, guest_tr_base),
669 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
670 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
671 FIELD(GUEST_DR7, guest_dr7),
672 FIELD(GUEST_RSP, guest_rsp),
673 FIELD(GUEST_RIP, guest_rip),
674 FIELD(GUEST_RFLAGS, guest_rflags),
675 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
676 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
677 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
678 FIELD(HOST_CR0, host_cr0),
679 FIELD(HOST_CR3, host_cr3),
680 FIELD(HOST_CR4, host_cr4),
681 FIELD(HOST_FS_BASE, host_fs_base),
682 FIELD(HOST_GS_BASE, host_gs_base),
683 FIELD(HOST_TR_BASE, host_tr_base),
684 FIELD(HOST_GDTR_BASE, host_gdtr_base),
685 FIELD(HOST_IDTR_BASE, host_idtr_base),
686 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
687 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
688 FIELD(HOST_RSP, host_rsp),
689 FIELD(HOST_RIP, host_rip),
690};
691static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
692
693static inline short vmcs_field_to_offset(unsigned long field)
694{
695 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
696 return -1;
697 return vmcs_field_to_offset_table[field];
698}
699
a9d30f33
NHE		 700static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
701{
702 return to_vmx(vcpu)->nested.current_vmcs12;
703}
704
705static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
706{
707 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 708 if (is_error_page(page))
a9d30f33 709 return NULL;
32cad84f 710
a9d30f33
NHE		 711 return page;
712}
713
714static void nested_release_page(struct page *page)
715{
716 kvm_release_page_dirty(page);
717}
718
719static void nested_release_page_clean(struct page *page)
720{
721 kvm_release_page_clean(page);
722}
723
bfd0a56b 724static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 725static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 726static void kvm_cpu_vmxon(u64 addr);
727static void kvm_cpu_vmxoff(void);
776e58ea 728static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 729static void vmx_set_segment(struct kvm_vcpu *vcpu,
730 struct kvm_segment *var, int seg);
731static void vmx_get_segment(struct kvm_vcpu *vcpu,
732 struct kvm_segment *var, int seg);
d99e4152
GN		 733static bool guest_state_valid(struct kvm_vcpu *vcpu);
734static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 735static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 736static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 737static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 738
6aa8b732
AK		 739static DEFINE_PER_CPU(struct vmcs *, vmxarea);
740static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 741/*
742 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
743 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
744 */
745static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 746static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 747
3e7c73e9
AK		 748static unsigned long *vmx_io_bitmap_a;
749static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 750static unsigned long *vmx_msr_bitmap_legacy;
751static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 752static unsigned long *vmx_msr_bitmap_legacy_x2apic;
753static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 754static unsigned long *vmx_vmread_bitmap;
755static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 756
110312c8 757static bool cpu_has_load_ia32_efer;
8bf00a52 758static bool cpu_has_load_perf_global_ctrl;
110312c8 759
2384d2b3
SY		 760static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
761static DEFINE_SPINLOCK(vmx_vpid_lock);
762
1c3d14fe 763static struct vmcs_config {
6aa8b732
AK		 764 int size;
765 int order;
766 u32 revision_id;
1c3d14fe
YS		 767 u32 pin_based_exec_ctrl;
768 u32 cpu_based_exec_ctrl;
f78e0e2e 769 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 770 u32 vmexit_ctrl;
771 u32 vmentry_ctrl;
772} vmcs_config;
6aa8b732 773
efff9e53 774static struct vmx_capability {
d56f546d
SY		 775 u32 ept;
776 u32 vpid;
777} vmx_capability;
778
6aa8b732
AK		 779#define VMX_SEGMENT_FIELD(seg) \
780 [VCPU_SREG_##seg] = { \
781 .selector = GUEST_##seg##_SELECTOR, \
782 .base = GUEST_##seg##_BASE, \
783 .limit = GUEST_##seg##_LIMIT, \
784 .ar_bytes = GUEST_##seg##_AR_BYTES, \
785 }
786
772e0318 787static const struct kvm_vmx_segment_field {
6aa8b732
AK		 788 unsigned selector;
789 unsigned base;
790 unsigned limit;
791 unsigned ar_bytes;
792} kvm_vmx_segment_fields[] = {
793 VMX_SEGMENT_FIELD(CS),
794 VMX_SEGMENT_FIELD(DS),
795 VMX_SEGMENT_FIELD(ES),
796 VMX_SEGMENT_FIELD(FS),
797 VMX_SEGMENT_FIELD(GS),
798 VMX_SEGMENT_FIELD(SS),
799 VMX_SEGMENT_FIELD(TR),
800 VMX_SEGMENT_FIELD(LDTR),
801};
802
26bb0981
AK		 803static u64 host_efer;
804
6de4f3ad
AK		 805static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
806
4d56c8a7 807/*
8c06585d 808 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 809 * away by decrementing the array size.
810 */
6aa8b732 811static const u32 vmx_msr_index[] = {
05b3e0c2 812#ifdef CONFIG_X86_64
44ea2b17 813 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 814#endif
8c06585d 815 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 816};
9d8f549d 817#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 818
31299944 819static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 820{
821 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
822 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 823 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 824}
825
31299944 826static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 827{
828 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
829 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 830 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 831}
832
31299944 833static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 834{
835 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
836 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 837 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 838}
839
31299944 840static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 841{
842 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
843 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
844}
845
31299944 846static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 847{
848 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
849 INTR_INFO_VALID_MASK)) ==
850 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
851}
852
31299944 853static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 854{
04547156 855 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 856}
857
31299944 858static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 859{
04547156 860 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 861}
862
31299944 863static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 864{
04547156 865 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 866}
867
31299944 868static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 869{
04547156
SY		 870 return vmcs_config.cpu_based_exec_ctrl &
871 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 872}
873
774ead3a 874static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 875{
04547156
SY		 876 return vmcs_config.cpu_based_2nd_exec_ctrl &
877 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
878}
879
8d14695f
YZ		 880static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
881{
882 return vmcs_config.cpu_based_2nd_exec_ctrl &
883 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
884}
885
83d4c286
YZ		 886static inline bool cpu_has_vmx_apic_register_virt(void)
887{
888 return vmcs_config.cpu_based_2nd_exec_ctrl &
889 SECONDARY_EXEC_APIC_REGISTER_VIRT;
890}
891
c7c9c56c
YZ		 892static inline bool cpu_has_vmx_virtual_intr_delivery(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
896}
897
01e439be
YZ		 898static inline bool cpu_has_vmx_posted_intr(void)
899{
900 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
901}
902
903static inline bool cpu_has_vmx_apicv(void)
904{
905 return cpu_has_vmx_apic_register_virt() &&
906 cpu_has_vmx_virtual_intr_delivery() &&
907 cpu_has_vmx_posted_intr();
908}
909
04547156
SY		 910static inline bool cpu_has_vmx_flexpriority(void)
911{
912 return cpu_has_vmx_tpr_shadow() &&
913 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 914}
915
e799794e
MT		 916static inline bool cpu_has_vmx_ept_execute_only(void)
917{
31299944 918 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 919}
920
921static inline bool cpu_has_vmx_eptp_uncacheable(void)
922{
31299944 923 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 924}
925
926static inline bool cpu_has_vmx_eptp_writeback(void)
927{
31299944 928 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 929}
930
931static inline bool cpu_has_vmx_ept_2m_page(void)
932{
31299944 933 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 934}
935
878403b7
SY		 936static inline bool cpu_has_vmx_ept_1g_page(void)
937{
31299944 938 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 939}
940
4bc9b982
SY		 941static inline bool cpu_has_vmx_ept_4levels(void)
942{
943 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
944}
945
83c3a331
XH		 946static inline bool cpu_has_vmx_ept_ad_bits(void)
947{
948 return vmx_capability.ept & VMX_EPT_AD_BIT;
949}
950
31299944 951static inline bool cpu_has_vmx_invept_context(void)
d56f546d 952{
31299944 953 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 954}
955
31299944 956static inline bool cpu_has_vmx_invept_global(void)
d56f546d 957{
31299944 958 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 959}
960
518c8aee
GJ		 961static inline bool cpu_has_vmx_invvpid_single(void)
962{
963 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
964}
965
b9d762fa
GJ		 966static inline bool cpu_has_vmx_invvpid_global(void)
967{
968 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
969}
970
31299944 971static inline bool cpu_has_vmx_ept(void)
d56f546d 972{
04547156
SY		 973 return vmcs_config.cpu_based_2nd_exec_ctrl &
974 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 975}
976
31299944 977static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 978{
979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_UNRESTRICTED_GUEST;
981}
982
31299944 983static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 984{
985 return vmcs_config.cpu_based_2nd_exec_ctrl &
986 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
987}
988
31299944 989static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 990{
6d3e435e 991 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 992}
993
31299944 994static inline bool cpu_has_vmx_vpid(void)
2384d2b3 995{
04547156
SY		 996 return vmcs_config.cpu_based_2nd_exec_ctrl &
997 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 998}
999
31299944 1000static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1001{
1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_RDTSCP;
1004}
1005
ad756a16
MJ		 1006static inline bool cpu_has_vmx_invpcid(void)
1007{
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_ENABLE_INVPCID;
1010}
1011
31299944 1012static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1013{
1014 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1015}
1016
f5f48ee1
SY		 1017static inline bool cpu_has_vmx_wbinvd_exit(void)
1018{
1019 return vmcs_config.cpu_based_2nd_exec_ctrl &
1020 SECONDARY_EXEC_WBINVD_EXITING;
1021}
1022
abc4fc58
AG		 1023static inline bool cpu_has_vmx_shadow_vmcs(void)
1024{
1025 u64 vmx_msr;
1026 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1027 /* check if the cpu supports writing r/o exit information fields */
1028 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1029 return false;
1030
1031 return vmcs_config.cpu_based_2nd_exec_ctrl &
1032 SECONDARY_EXEC_SHADOW_VMCS;
1033}
1034
04547156
SY		 1035static inline bool report_flexpriority(void)
1036{
1037 return flexpriority_enabled;
1038}
1039
fe3ef05c
NHE		 1040static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1041{
1042 return vmcs12->cpu_based_vm_exec_control & bit;
1043}
1044
1045static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1046{
1047 return (vmcs12->cpu_based_vm_exec_control &
1048 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1049 (vmcs12->secondary_vm_exec_control & bit);
1050}
1051
f5c4368f 1052static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1053{
1054 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1055}
1056
f4124500
JK		 1057static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1058{
1059 return vmcs12->pin_based_vm_exec_control &
1060 PIN_BASED_VMX_PREEMPTION_TIMER;
1061}
1062
155a97a3
NHE		 1063static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1064{
1065 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1066}
1067
644d711a
NHE		 1068static inline bool is_exception(u32 intr_info)
1069{
1070 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1071 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1072}
1073
533558bc
JK		 1074static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1075 u32 exit_intr_info,
1076 unsigned long exit_qualification);
7c177938
NHE		 1077static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1078 struct vmcs12 *vmcs12,
1079 u32 reason, unsigned long qualification);
1080
8b9cf98c 1081static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1082{
1083 int i;
1084
a2fa3e9f 1085 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1086 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1087 return i;
1088 return -1;
1089}
1090
2384d2b3
SY		 1091static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1092{
1093 struct {
1094 u64 vpid : 16;
1095 u64 rsvd : 48;
1096 u64 gva;
1097 } operand = { vpid, 0, gva };
1098
4ecac3fd 1099 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1100 /* CF==1 or ZF==1 --> rc = -1 */
1101 "; ja 1f ; ud2 ; 1:"
1102 : : "a"(&operand), "c"(ext) : "cc", "memory");
1103}
1104
1439442c
SY		 1105static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1106{
1107 struct {
1108 u64 eptp, gpa;
1109 } operand = {eptp, gpa};
1110
4ecac3fd 1111 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1112 /* CF==1 or ZF==1 --> rc = -1 */
1113 "; ja 1f ; ud2 ; 1:\n"
1114 : : "a" (&operand), "c" (ext) : "cc", "memory");
1115}
1116
26bb0981 1117static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1118{
1119 int i;
1120
8b9cf98c 1121 i = __find_msr_index(vmx, msr);
a75beee6 1122 if (i >= 0)
a2fa3e9f 1123 return &vmx->guest_msrs[i];
8b6d44c7 1124 return NULL;
7725f0ba
AK		 1125}
1126
6aa8b732
AK		 1127static void vmcs_clear(struct vmcs *vmcs)
1128{
1129 u64 phys_addr = __pa(vmcs);
1130 u8 error;
1131
4ecac3fd 1132 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1133 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1134 : "cc", "memory");
1135 if (error)
1136 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1137 vmcs, phys_addr);
1138}
1139
d462b819
NHE		 1140static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1141{
1142 vmcs_clear(loaded_vmcs->vmcs);
1143 loaded_vmcs->cpu = -1;
1144 loaded_vmcs->launched = 0;
1145}
1146
7725b894
DX		 1147static void vmcs_load(struct vmcs *vmcs)
1148{
1149 u64 phys_addr = __pa(vmcs);
1150 u8 error;
1151
1152 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1153 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1154 : "cc", "memory");
1155 if (error)
2844d849 1156 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1157 vmcs, phys_addr);
1158}
1159
8f536b76
ZY		 1160#ifdef CONFIG_KEXEC
1161/*
1162 * This bitmap is used to indicate whether the vmclear
1163 * operation is enabled on all cpus. All disabled by
1164 * default.
1165 */
1166static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1167
1168static inline void crash_enable_local_vmclear(int cpu)
1169{
1170 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1171}
1172
1173static inline void crash_disable_local_vmclear(int cpu)
1174{
1175 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1176}
1177
1178static inline int crash_local_vmclear_enabled(int cpu)
1179{
1180 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1181}
1182
1183static void crash_vmclear_local_loaded_vmcss(void)
1184{
1185 int cpu = raw_smp_processor_id();
1186 struct loaded_vmcs *v;
1187
1188 if (!crash_local_vmclear_enabled(cpu))
1189 return;
1190
1191 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1192 loaded_vmcss_on_cpu_link)
1193 vmcs_clear(v->vmcs);
1194}
1195#else
1196static inline void crash_enable_local_vmclear(int cpu) { }
1197static inline void crash_disable_local_vmclear(int cpu) { }
1198#endif /* CONFIG_KEXEC */
1199
d462b819 1200static void __loaded_vmcs_clear(void *arg)
6aa8b732 1201{
d462b819 1202 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1203 int cpu = raw_smp_processor_id();
6aa8b732 1204
d462b819
NHE		 1205 if (loaded_vmcs->cpu != cpu)
1206 return; /* vcpu migration can race with cpu offline */
1207 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1208 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1209 crash_disable_local_vmclear(cpu);
d462b819 1210 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1211
1212 /*
1213 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1214 * is before setting loaded_vmcs->vcpu to -1 which is done in
1215 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1216 * then adds the vmcs into percpu list before it is deleted.
1217 */
1218 smp_wmb();
1219
d462b819 1220 loaded_vmcs_init(loaded_vmcs);
8f536b76 1221 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1222}
1223
d462b819 1224static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1225{
e6c7d321
XG		 1226 int cpu = loaded_vmcs->cpu;
1227
1228 if (cpu != -1)
1229 smp_call_function_single(cpu,
1230 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1231}
1232
1760dd49 1233static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1234{
1235 if (vmx->vpid == 0)
1236 return;
1237
518c8aee
GJ		 1238 if (cpu_has_vmx_invvpid_single())
1239 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1240}
1241
b9d762fa
GJ		 1242static inline void vpid_sync_vcpu_global(void)
1243{
1244 if (cpu_has_vmx_invvpid_global())
1245 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1246}
1247
1248static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1249{
1250 if (cpu_has_vmx_invvpid_single())
1760dd49 1251 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1252 else
1253 vpid_sync_vcpu_global();
1254}
1255
1439442c
SY		 1256static inline void ept_sync_global(void)
1257{
1258 if (cpu_has_vmx_invept_global())
1259 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1260}
1261
1262static inline void ept_sync_context(u64 eptp)
1263{
089d034e 1264 if (enable_ept) {
1439442c
SY		 1265 if (cpu_has_vmx_invept_context())
1266 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1267 else
1268 ept_sync_global();
1269 }
1270}
1271
96304217 1272static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1273{
5e520e62 1274 unsigned long value;
6aa8b732 1275
5e520e62
AK		 1276 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1277 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1278 return value;
1279}
1280
96304217 1281static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1282{
1283 return vmcs_readl(field);
1284}
1285
96304217 1286static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1287{
1288 return vmcs_readl(field);
1289}
1290
96304217 1291static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1292{
05b3e0c2 1293#ifdef CONFIG_X86_64
6aa8b732
AK		 1294 return vmcs_readl(field);
1295#else
1296 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1297#endif
1298}
1299
e52de1b8
AK		 1300static noinline void vmwrite_error(unsigned long field, unsigned long value)
1301{
1302 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1303 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1304 dump_stack();
1305}
1306
6aa8b732
AK		 1307static void vmcs_writel(unsigned long field, unsigned long value)
1308{
1309 u8 error;
1310
4ecac3fd 1311 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1312 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1313 if (unlikely(error))
1314 vmwrite_error(field, value);
6aa8b732
AK		 1315}
1316
1317static void vmcs_write16(unsigned long field, u16 value)
1318{
1319 vmcs_writel(field, value);
1320}
1321
1322static void vmcs_write32(unsigned long field, u32 value)
1323{
1324 vmcs_writel(field, value);
1325}
1326
1327static void vmcs_write64(unsigned long field, u64 value)
1328{
6aa8b732 1329 vmcs_writel(field, value);
7682f2d0 1330#ifndef CONFIG_X86_64
6aa8b732
AK		 1331 asm volatile ("");
1332 vmcs_writel(field+1, value >> 32);
1333#endif
1334}
1335
2ab455cc
AL		 1336static void vmcs_clear_bits(unsigned long field, u32 mask)
1337{
1338 vmcs_writel(field, vmcs_readl(field) & ~mask);
1339}
1340
1341static void vmcs_set_bits(unsigned long field, u32 mask)
1342{
1343 vmcs_writel(field, vmcs_readl(field) | mask);
1344}
1345
2961e876
GN		 1346static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1347{
1348 vmcs_write32(VM_ENTRY_CONTROLS, val);
1349 vmx->vm_entry_controls_shadow = val;
1350}
1351
1352static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1353{
1354 if (vmx->vm_entry_controls_shadow != val)
1355 vm_entry_controls_init(vmx, val);
1356}
1357
1358static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1359{
1360 return vmx->vm_entry_controls_shadow;
1361}
1362
1363
1364static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1365{
1366 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1367}
1368
1369static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1370{
1371 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1372}
1373
1374static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1375{
1376 vmcs_write32(VM_EXIT_CONTROLS, val);
1377 vmx->vm_exit_controls_shadow = val;
1378}
1379
1380static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1381{
1382 if (vmx->vm_exit_controls_shadow != val)
1383 vm_exit_controls_init(vmx, val);
1384}
1385
1386static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1387{
1388 return vmx->vm_exit_controls_shadow;
1389}
1390
1391
1392static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1393{
1394 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1395}
1396
1397static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1398{
1399 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1400}
1401
2fb92db1
AK		 1402static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1403{
1404 vmx->segment_cache.bitmask = 0;
1405}
1406
1407static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1408 unsigned field)
1409{
1410 bool ret;
1411 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1412
1413 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1414 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1415 vmx->segment_cache.bitmask = 0;
1416 }
1417 ret = vmx->segment_cache.bitmask & mask;
1418 vmx->segment_cache.bitmask |= mask;
1419 return ret;
1420}
1421
1422static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1423{
1424 u16 *p = &vmx->segment_cache.seg[seg].selector;
1425
1426 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1427 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1428 return *p;
1429}
1430
1431static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1432{
1433 ulong *p = &vmx->segment_cache.seg[seg].base;
1434
1435 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1436 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1437 return *p;
1438}
1439
1440static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1441{
1442 u32 *p = &vmx->segment_cache.seg[seg].limit;
1443
1444 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1445 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1446 return *p;
1447}
1448
1449static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1450{
1451 u32 *p = &vmx->segment_cache.seg[seg].ar;
1452
1453 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1454 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1455 return *p;
1456}
1457
abd3f2d6
AK		 1458static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1459{
1460 u32 eb;
1461
fd7373cc
JK		 1462 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1463 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1464 if ((vcpu->guest_debug &
1465 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1466 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1467 eb |= 1u << BP_VECTOR;
7ffd92c5 1468 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1469 eb = ~0;
089d034e 1470 if (enable_ept)
1439442c 1471 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1472 if (vcpu->fpu_active)
1473 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1474
1475 /* When we are running a nested L2 guest and L1 specified for it a
1476 * certain exception bitmap, we must trap the same exceptions and pass
1477 * them to L1. When running L2, we will only handle the exceptions
1478 * specified above if L1 did not want them.
1479 */
1480 if (is_guest_mode(vcpu))
1481 eb |= get_vmcs12(vcpu)->exception_bitmap;
1482
abd3f2d6
AK		 1483 vmcs_write32(EXCEPTION_BITMAP, eb);
1484}
1485
2961e876
GN		 1486static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1487 unsigned long entry, unsigned long exit)
8bf00a52 1488{
2961e876
GN		 1489 vm_entry_controls_clearbit(vmx, entry);
1490 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1491}
1492
61d2ef2c
AK		 1493static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1494{
1495 unsigned i;
1496 struct msr_autoload *m = &vmx->msr_autoload;
1497
8bf00a52
GN		 1498 switch (msr) {
1499 case MSR_EFER:
1500 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1501 clear_atomic_switch_msr_special(vmx,
1502 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1503 VM_EXIT_LOAD_IA32_EFER);
1504 return;
1505 }
1506 break;
1507 case MSR_CORE_PERF_GLOBAL_CTRL:
1508 if (cpu_has_load_perf_global_ctrl) {
2961e876 1509 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1510 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1511 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1512 return;
1513 }
1514 break;
110312c8
AK		 1515 }
1516
61d2ef2c
AK		 1517 for (i = 0; i < m->nr; ++i)
1518 if (m->guest[i].index == msr)
1519 break;
1520
1521 if (i == m->nr)
1522 return;
1523 --m->nr;
1524 m->guest[i] = m->guest[m->nr];
1525 m->host[i] = m->host[m->nr];
1526 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1527 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1528}
1529
2961e876
GN		 1530static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1531 unsigned long entry, unsigned long exit,
1532 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1533 u64 guest_val, u64 host_val)
8bf00a52
GN		 1534{
1535 vmcs_write64(guest_val_vmcs, guest_val);
1536 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1537 vm_entry_controls_setbit(vmx, entry);
1538 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1539}
1540
61d2ef2c
AK		 1541static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1542 u64 guest_val, u64 host_val)
1543{
1544 unsigned i;
1545 struct msr_autoload *m = &vmx->msr_autoload;
1546
8bf00a52
GN		 1547 switch (msr) {
1548 case MSR_EFER:
1549 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1550 add_atomic_switch_msr_special(vmx,
1551 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1552 VM_EXIT_LOAD_IA32_EFER,
1553 GUEST_IA32_EFER,
1554 HOST_IA32_EFER,
1555 guest_val, host_val);
1556 return;
1557 }
1558 break;
1559 case MSR_CORE_PERF_GLOBAL_CTRL:
1560 if (cpu_has_load_perf_global_ctrl) {
2961e876 1561 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1562 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1563 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1564 GUEST_IA32_PERF_GLOBAL_CTRL,
1565 HOST_IA32_PERF_GLOBAL_CTRL,
1566 guest_val, host_val);
1567 return;
1568 }
1569 break;
110312c8
AK		 1570 }
1571
61d2ef2c
AK		 1572 for (i = 0; i < m->nr; ++i)
1573 if (m->guest[i].index == msr)
1574 break;
1575
e7fc6f93 1576 if (i == NR_AUTOLOAD_MSRS) {
60266204 1577 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1578 "Can't add msr %x\n", msr);
1579 return;
1580 } else if (i == m->nr) {
61d2ef2c
AK		 1581 ++m->nr;
1582 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1583 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1584 }
1585
1586 m->guest[i].index = msr;
1587 m->guest[i].value = guest_val;
1588 m->host[i].index = msr;
1589 m->host[i].value = host_val;
1590}
1591
33ed6329
AK		 1592static void reload_tss(void)
1593{
33ed6329
AK		 1594 /*
1595 * VT restores TR but not its size. Useless.
1596 */
d359192f 1597 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1598 struct desc_struct *descs;
33ed6329 1599
d359192f 1600 descs = (void *)gdt->address;
33ed6329
AK		 1601 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1602 load_TR_desc();
33ed6329
AK		 1603}
1604
92c0d900 1605static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1606{
3a34a881 1607 u64 guest_efer;
51c6cf66
AK		 1608 u64 ignore_bits;
1609
f6801dff 1610 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1611
51c6cf66 1612 /*
0fa06071 1613 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1614 * outside long mode
1615 */
1616 ignore_bits = EFER_NX | EFER_SCE;
1617#ifdef CONFIG_X86_64
1618 ignore_bits |= EFER_LMA | EFER_LME;
1619 /* SCE is meaningful only in long mode on Intel */
1620 if (guest_efer & EFER_LMA)
1621 ignore_bits &= ~(u64)EFER_SCE;
1622#endif
51c6cf66
AK		 1623 guest_efer &= ~ignore_bits;
1624 guest_efer |= host_efer & ignore_bits;
26bb0981 1625 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1626 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1627
1628 clear_atomic_switch_msr(vmx, MSR_EFER);
1629 /* On ept, can't emulate nx, and must switch nx atomically */
1630 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1631 guest_efer = vmx->vcpu.arch.efer;
1632 if (!(guest_efer & EFER_LMA))
1633 guest_efer &= ~EFER_LME;
1634 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1635 return false;
1636 }
1637
26bb0981 1638 return true;
51c6cf66
AK		 1639}
1640
2d49ec72
GN		 1641static unsigned long segment_base(u16 selector)
1642{
d359192f 1643 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1644 struct desc_struct *d;
1645 unsigned long table_base;
1646 unsigned long v;
1647
1648 if (!(selector & ~3))
1649 return 0;
1650
d359192f 1651 table_base = gdt->address;
2d49ec72
GN		 1652
1653 if (selector & 4) { /* from ldt */
1654 u16 ldt_selector = kvm_read_ldt();
1655
1656 if (!(ldt_selector & ~3))
1657 return 0;
1658
1659 table_base = segment_base(ldt_selector);
1660 }
1661 d = (struct desc_struct *)(table_base + (selector & ~7));
1662 v = get_desc_base(d);
1663#ifdef CONFIG_X86_64
1664 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1665 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1666#endif
1667 return v;
1668}
1669
1670static inline unsigned long kvm_read_tr_base(void)
1671{
1672 u16 tr;
1673 asm("str %0" : "=g"(tr));
1674 return segment_base(tr);
1675}
1676
04d2cc77 1677static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1678{
04d2cc77 1679 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1680 int i;
04d2cc77 1681
a2fa3e9f 1682 if (vmx->host_state.loaded)
33ed6329
AK		 1683 return;
1684
a2fa3e9f 1685 vmx->host_state.loaded = 1;
33ed6329
AK		 1686 /*
1687 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1688 * allow segment selectors with cpl > 0 or ti == 1.
1689 */
d6e88aec 1690 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1691 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1692 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1693 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1694 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1695 vmx->host_state.fs_reload_needed = 0;
1696 } else {
33ed6329 1697 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1698 vmx->host_state.fs_reload_needed = 1;
33ed6329 1699 }
9581d442 1700 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1701 if (!(vmx->host_state.gs_sel & 7))
1702 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1703 else {
1704 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1705 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1706 }
1707
b2da15ac
AK		 1708#ifdef CONFIG_X86_64
1709 savesegment(ds, vmx->host_state.ds_sel);
1710 savesegment(es, vmx->host_state.es_sel);
1711#endif
1712
33ed6329
AK		 1713#ifdef CONFIG_X86_64
1714 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1715 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1716#else
a2fa3e9f
GH		 1717 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1718 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1719#endif
707c0874
AK		 1720
1721#ifdef CONFIG_X86_64
c8770e7b
AK		 1722 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1723 if (is_long_mode(&vmx->vcpu))
44ea2b17 1724 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1725#endif
da8999d3
LJ		 1726 if (boot_cpu_has(X86_FEATURE_MPX))
1727 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1728 for (i = 0; i < vmx->save_nmsrs; ++i)
1729 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1730 vmx->guest_msrs[i].data,
1731 vmx->guest_msrs[i].mask);
33ed6329
AK		 1732}
1733
a9b21b62 1734static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1735{
a2fa3e9f 1736 if (!vmx->host_state.loaded)
33ed6329
AK		 1737 return;
1738
e1beb1d3 1739 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1740 vmx->host_state.loaded = 0;
c8770e7b
AK		 1741#ifdef CONFIG_X86_64
1742 if (is_long_mode(&vmx->vcpu))
1743 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1744#endif
152d3f2f 1745 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1746 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1747#ifdef CONFIG_X86_64
9581d442 1748 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1749#else
1750 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1751#endif
33ed6329 1752 }
0a77fe4c
AK		 1753 if (vmx->host_state.fs_reload_needed)
1754 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1755#ifdef CONFIG_X86_64
1756 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1757 loadsegment(ds, vmx->host_state.ds_sel);
1758 loadsegment(es, vmx->host_state.es_sel);
1759 }
b2da15ac 1760#endif
152d3f2f 1761 reload_tss();
44ea2b17 1762#ifdef CONFIG_X86_64
c8770e7b 1763 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1764#endif
da8999d3
LJ		 1765 if (vmx->host_state.msr_host_bndcfgs)
1766 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1767 /*
1768 * If the FPU is not active (through the host task or
1769 * the guest vcpu), then restore the cr0.TS bit.
1770 */
1771 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1772 stts();
3444d7da 1773 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1774}
1775
a9b21b62
AK		 1776static void vmx_load_host_state(struct vcpu_vmx *vmx)
1777{
1778 preempt_disable();
1779 __vmx_load_host_state(vmx);
1780 preempt_enable();
1781}
1782
6aa8b732
AK		 1783/*
1784 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1785 * vcpu mutex is already taken.
1786 */
15ad7146 1787static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1788{
a2fa3e9f 1789 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1790 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1791
4610c9cc
DX		 1792 if (!vmm_exclusive)
1793 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1794 else if (vmx->loaded_vmcs->cpu != cpu)
1795 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1796
d462b819
NHE		 1797 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1798 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1799 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1800 }
1801
d462b819 1802 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1803 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1804 unsigned long sysenter_esp;
1805
a8eeb04a 1806 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1807 local_irq_disable();
8f536b76 1808 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1809
1810 /*
1811 * Read loaded_vmcs->cpu should be before fetching
1812 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1813 * See the comments in __loaded_vmcs_clear().
1814 */
1815 smp_rmb();
1816
d462b819
NHE		 1817 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1818 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1819 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1820 local_irq_enable();
1821
6aa8b732
AK		 1822 /*
1823 * Linux uses per-cpu TSS and GDT, so set these when switching
1824 * processors.
1825 */
d6e88aec 1826 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1827 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1828
1829 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1830 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1831 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1832 }
6aa8b732
AK		 1833}
1834
1835static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1836{
a9b21b62 1837 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1838 if (!vmm_exclusive) {
d462b819
NHE		 1839 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1840 vcpu->cpu = -1;
4610c9cc
DX		 1841 kvm_cpu_vmxoff();
1842 }
6aa8b732
AK		 1843}
1844
5fd86fcf
AK		 1845static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1846{
81231c69
AK		 1847 ulong cr0;
1848
5fd86fcf
AK		 1849 if (vcpu->fpu_active)
1850 return;
1851 vcpu->fpu_active = 1;
81231c69
AK		 1852 cr0 = vmcs_readl(GUEST_CR0);
1853 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1854 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1855 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1856 update_exception_bitmap(vcpu);
edcafe3c 1857 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1858 if (is_guest_mode(vcpu))
1859 vcpu->arch.cr0_guest_owned_bits &=
1860 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1861 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1862}
1863
edcafe3c
AK		 1864static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1865
fe3ef05c
NHE		 1866/*
1867 * Return the cr0 value that a nested guest would read. This is a combination
1868 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1869 * its hypervisor (cr0_read_shadow).
1870 */
1871static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1872{
1873 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1874 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1875}
1876static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1877{
1878 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1879 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1880}
1881
5fd86fcf
AK		 1882static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1883{
36cf24e0
NHE		 1884 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1885 * set this *before* calling this function.
1886 */
edcafe3c 1887 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1888 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1889 update_exception_bitmap(vcpu);
edcafe3c
AK		 1890 vcpu->arch.cr0_guest_owned_bits = 0;
1891 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1892 if (is_guest_mode(vcpu)) {
1893 /*
1894 * L1's specified read shadow might not contain the TS bit,
1895 * so now that we turned on shadowing of this bit, we need to
1896 * set this bit of the shadow. Like in nested_vmx_run we need
1897 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1898 * up-to-date here because we just decached cr0.TS (and we'll
1899 * only update vmcs12->guest_cr0 on nested exit).
1900 */
1901 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1902 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1903 (vcpu->arch.cr0 & X86_CR0_TS);
1904 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1905 } else
1906 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1907}
1908
6aa8b732
AK		 1909static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1910{
78ac8b47 1911 unsigned long rflags, save_rflags;
345dcaa8 1912
6de12732
AK		 1913 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1914 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1915 rflags = vmcs_readl(GUEST_RFLAGS);
1916 if (to_vmx(vcpu)->rmode.vm86_active) {
1917 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1918 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1919 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1920 }
1921 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1922 }
6de12732 1923 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1924}
1925
1926static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1927{
6de12732
AK		 1928 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1929 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1930 if (to_vmx(vcpu)->rmode.vm86_active) {
1931 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1932 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1933 }
6aa8b732
AK		 1934 vmcs_writel(GUEST_RFLAGS, rflags);
1935}
1936
2809f5d2
GC		 1937static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1938{
1939 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1940 int ret = 0;
1941
1942 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1943 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1944 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1945 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1946
1947 return ret & mask;
1948}
1949
1950static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1951{
1952 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1953 u32 interruptibility = interruptibility_old;
1954
1955 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1956
48005f64 1957 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1958 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1959 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1960 interruptibility |= GUEST_INTR_STATE_STI;
1961
1962 if ((interruptibility != interruptibility_old))
1963 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1964}
1965
6aa8b732
AK		 1966static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1967{
1968 unsigned long rip;
6aa8b732 1969
5fdbf976 1970 rip = kvm_rip_read(vcpu);
6aa8b732 1971 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1972 kvm_rip_write(vcpu, rip);
6aa8b732 1973
2809f5d2
GC		 1974 /* skipping an emulated instruction also counts */
1975 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1976}
1977
0b6ac343
NHE		 1978/*
1979 * KVM wants to inject page-faults which it got to the guest. This function
1980 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1981 */
e011c663 1982static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1983{
1984 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1985
e011c663 1986 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1987 return 0;
1988
533558bc
JK		 1989 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1990 vmcs_read32(VM_EXIT_INTR_INFO),
1991 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1992 return 1;
1993}
1994
298101da 1995static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1996 bool has_error_code, u32 error_code,
1997 bool reinject)
298101da 1998{
77ab6db0 1999 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2000 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2001
e011c663
GN		 2002 if (!reinject && is_guest_mode(vcpu) &&
2003 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2004 return;
2005
8ab2d2e2 2006 if (has_error_code) {
77ab6db0 2007 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2008 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2009 }
77ab6db0 2010
7ffd92c5 2011 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2012 int inc_eip = 0;
2013 if (kvm_exception_is_soft(nr))
2014 inc_eip = vcpu->arch.event_exit_inst_len;
2015 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2016 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2017 return;
2018 }
2019
66fd3f7f
GN		 2020 if (kvm_exception_is_soft(nr)) {
2021 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2022 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2023 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2024 } else
2025 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2026
2027 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2028}
2029
4e47c7a6
SY		 2030static bool vmx_rdtscp_supported(void)
2031{
2032 return cpu_has_vmx_rdtscp();
2033}
2034
ad756a16
MJ		 2035static bool vmx_invpcid_supported(void)
2036{
2037 return cpu_has_vmx_invpcid() && enable_ept;
2038}
2039
a75beee6
ED		 2040/*
2041 * Swap MSR entry in host/guest MSR entry array.
2042 */
8b9cf98c 2043static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2044{
26bb0981 2045 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2046
2047 tmp = vmx->guest_msrs[to];
2048 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2049 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2050}
2051
8d14695f
YZ		 2052static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2053{
2054 unsigned long *msr_bitmap;
2055
2056 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2057 if (is_long_mode(vcpu))
2058 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2059 else
2060 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2061 } else {
2062 if (is_long_mode(vcpu))
2063 msr_bitmap = vmx_msr_bitmap_longmode;
2064 else
2065 msr_bitmap = vmx_msr_bitmap_legacy;
2066 }
2067
2068 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2069}
2070
e38aea3e
AK		 2071/*
2072 * Set up the vmcs to automatically save and restore system
2073 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2074 * mode, as fiddling with msrs is very expensive.
2075 */
8b9cf98c 2076static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2077{
26bb0981 2078 int save_nmsrs, index;
e38aea3e 2079
a75beee6
ED		 2080 save_nmsrs = 0;
2081#ifdef CONFIG_X86_64
8b9cf98c 2082 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2083 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2084 if (index >= 0)
8b9cf98c
RR		 2085 move_msr_up(vmx, index, save_nmsrs++);
2086 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2087 if (index >= 0)
8b9cf98c
RR		 2088 move_msr_up(vmx, index, save_nmsrs++);
2089 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2090 if (index >= 0)
8b9cf98c 2091 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2092 index = __find_msr_index(vmx, MSR_TSC_AUX);
2093 if (index >= 0 && vmx->rdtscp_enabled)
2094 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2095 /*
8c06585d 2096 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2097 * if efer.sce is enabled.
2098 */
8c06585d 2099 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2100 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2101 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2102 }
2103#endif
92c0d900
AK		 2104 index = __find_msr_index(vmx, MSR_EFER);
2105 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2106 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2107
26bb0981 2108 vmx->save_nmsrs = save_nmsrs;
5897297b 2109
8d14695f
YZ		 2110 if (cpu_has_vmx_msr_bitmap())
2111 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2112}
2113
6aa8b732
AK		 2114/*
2115 * reads and returns guest's timestamp counter "register"
2116 * guest_tsc = host_tsc + tsc_offset -- 21.3
2117 */
2118static u64 guest_read_tsc(void)
2119{
2120 u64 host_tsc, tsc_offset;
2121
2122 rdtscll(host_tsc);
2123 tsc_offset = vmcs_read64(TSC_OFFSET);
2124 return host_tsc + tsc_offset;
2125}
2126
d5c1785d
NHE		 2127/*
2128 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2129 * counter, even if a nested guest (L2) is currently running.
2130 */
886b470c 2131u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2132{
886b470c 2133 u64 tsc_offset;
d5c1785d 2134
d5c1785d
NHE		 2135 tsc_offset = is_guest_mode(vcpu) ?
2136 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2137 vmcs_read64(TSC_OFFSET);
2138 return host_tsc + tsc_offset;
2139}
2140
4051b188 2141/*
cc578287
ZA		 2142 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2143 * software catchup for faster rates on slower CPUs.
4051b188 2144 */
cc578287 2145static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2146{
cc578287
ZA		 2147 if (!scale)
2148 return;
2149
2150 if (user_tsc_khz > tsc_khz) {
2151 vcpu->arch.tsc_catchup = 1;
2152 vcpu->arch.tsc_always_catchup = 1;
2153 } else
2154 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2155}
2156
ba904635
WA		 2157static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2158{
2159 return vmcs_read64(TSC_OFFSET);
2160}
2161
6aa8b732 2162/*
99e3e30a 2163 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2164 */
99e3e30a 2165static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2166{
27fc51b2 2167 if (is_guest_mode(vcpu)) {
7991825b 2168 /*
27fc51b2
NHE		 2169 * We're here if L1 chose not to trap WRMSR to TSC. According
2170 * to the spec, this should set L1's TSC; The offset that L1
2171 * set for L2 remains unchanged, and still needs to be added
2172 * to the newly set TSC to get L2's TSC.
7991825b 2173 */
27fc51b2
NHE		 2174 struct vmcs12 *vmcs12;
2175 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2176 /* recalculate vmcs02.TSC_OFFSET: */
2177 vmcs12 = get_vmcs12(vcpu);
2178 vmcs_write64(TSC_OFFSET, offset +
2179 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2180 vmcs12->tsc_offset : 0));
2181 } else {
489223ed
YY		 2182 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2183 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2184 vmcs_write64(TSC_OFFSET, offset);
2185 }
6aa8b732
AK		 2186}
2187
f1e2b260 2188static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2189{
2190 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2191
e48672fa 2192 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2193 if (is_guest_mode(vcpu)) {
2194 /* Even when running L2, the adjustment needs to apply to L1 */
2195 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2196 } else
2197 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2198 offset + adjustment);
e48672fa
ZA		 2199}
2200
857e4099
JR		 2201static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2202{
2203 return target_tsc - native_read_tsc();
2204}
2205
801d3424
NHE		 2206static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2207{
2208 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2209 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2210}
2211
2212/*
2213 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2214 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2215 * all guests if the "nested" module option is off, and can also be disabled
2216 * for a single guest by disabling its VMX cpuid bit.
2217 */
2218static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2219{
2220 return nested && guest_cpuid_has_vmx(vcpu);
2221}
2222
b87a51ae
NHE		 2223/*
2224 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2225 * returned for the various VMX controls MSRs when nested VMX is enabled.
2226 * The same values should also be used to verify that vmcs12 control fields are
2227 * valid during nested entry from L1 to L2.
2228 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2229 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2230 * bit in the high half is on if the corresponding bit in the control field
2231 * may be on. See also vmx_control_verify().
2232 * TODO: allow these variables to be modified (downgraded) by module options
2233 * or other means.
2234 */
2235static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2236static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2237static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2238static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2239static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2240static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2241static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2242static __init void nested_vmx_setup_ctls_msrs(void)
2243{
2244 /*
2245 * Note that as a general rule, the high half of the MSRs (bits in
2246 * the control fields which may be 1) should be initialized by the
2247 * intersection of the underlying hardware's MSR (i.e., features which
2248 * can be supported) and the list of features we want to expose -
2249 * because they are known to be properly supported in our code.
2250 * Also, usually, the low half of the MSRs (bits which must be 1) can
2251 * be set to 0, meaning that L1 may turn off any of these bits. The
2252 * reason is that if one of these bits is necessary, it will appear
2253 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2254 * fields of vmcs01 and vmcs02, will turn these bits off - and
2255 * nested_vmx_exit_handled() will not pass related exits to L1.
2256 * These rules have exceptions below.
2257 */
2258
2259 /* pin-based controls */
eabeaacc
JK		 2260 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2261 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2262 /*
2263 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2264 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2265 */
eabeaacc
JK		 2266 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2267 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2268 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2269 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2270 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2271
33fb20c3
JK		 2272 /*
2273 * Exit controls
2274 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2275 * 17 must be 1.
2276 */
c0dfee58
ACL		 2277 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2278 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2279 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2280 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2281 nested_vmx_exit_ctls_high &=
b87a51ae 2282#ifdef CONFIG_X86_64
c0dfee58 2283 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2284#endif
f4124500
JK		 2285 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2286 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2287 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
7854cbca 2288 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
b87a51ae
NHE		 2289
2290 /* entry controls */
2291 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2292 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2293 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2294 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2295 nested_vmx_entry_ctls_high &=
57435349
JK		 2296#ifdef CONFIG_X86_64
2297 VM_ENTRY_IA32E_MODE |
2298#endif
2299 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2300 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2301 VM_ENTRY_LOAD_IA32_EFER);
57435349 2302
b87a51ae
NHE		 2303 /* cpu-based controls */
2304 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2305 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2306 nested_vmx_procbased_ctls_low = 0;
2307 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2308 CPU_BASED_VIRTUAL_INTR_PENDING |
2309 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2310 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2311 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2312 CPU_BASED_CR3_STORE_EXITING |
2313#ifdef CONFIG_X86_64
2314 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2315#endif
2316 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2317 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2318 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2319 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2320 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2321 /*
2322 * We can allow some features even when not supported by the
2323 * hardware. For example, L1 can specify an MSR bitmap - and we
2324 * can use it to avoid exits to L1 - even when L0 runs L2
2325 * without MSR bitmaps.
2326 */
2327 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2328
2329 /* secondary cpu-based controls */
2330 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2331 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2332 nested_vmx_secondary_ctls_low = 0;
2333 nested_vmx_secondary_ctls_high &=
d6851fbe 2334 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2335 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2336 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2337
afa61f75
NHE		 2338 if (enable_ept) {
2339 /* nested EPT: emulate EPT also to L1 */
2340 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2341 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2342 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2343 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2344 nested_vmx_ept_caps &= vmx_capability.ept;
2345 /*
2346 * Since invept is completely emulated we support both global
2347 * and context invalidation independent of what host cpu
2348 * supports
2349 */
2350 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2351 VMX_EPT_EXTENT_CONTEXT_BIT;
2352 } else
2353 nested_vmx_ept_caps = 0;
2354
c18911a2
JK		 2355 /* miscellaneous data */
2356 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2357 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2358 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2359 VMX_MISC_ACTIVITY_HLT;
c18911a2 2360 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2361}
2362
2363static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2364{
2365 /*
2366 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2367 */
2368 return ((control & high) | low) == control;
2369}
2370
2371static inline u64 vmx_control_msr(u32 low, u32 high)
2372{
2373 return low | ((u64)high << 32);
2374}
2375
cae50139 2376/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2377static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2378{
b87a51ae 2379 switch (msr_index) {
b87a51ae
NHE		 2380 case MSR_IA32_VMX_BASIC:
2381 /*
2382 * This MSR reports some information about VMX support. We
2383 * should return information about the VMX we emulate for the
2384 * guest, and the VMCS structure we give it - not about the
2385 * VMX support of the underlying hardware.
2386 */
2387 *pdata = VMCS12_REVISION |
2388 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2389 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2390 break;
2391 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2392 case MSR_IA32_VMX_PINBASED_CTLS:
2393 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2394 nested_vmx_pinbased_ctls_high);
2395 break;
2396 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2397 case MSR_IA32_VMX_PROCBASED_CTLS:
2398 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2399 nested_vmx_procbased_ctls_high);
2400 break;
2401 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2402 case MSR_IA32_VMX_EXIT_CTLS:
2403 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2404 nested_vmx_exit_ctls_high);
2405 break;
2406 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2407 case MSR_IA32_VMX_ENTRY_CTLS:
2408 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2409 nested_vmx_entry_ctls_high);
2410 break;
2411 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2412 *pdata = vmx_control_msr(nested_vmx_misc_low,
2413 nested_vmx_misc_high);
b87a51ae
NHE		 2414 break;
2415 /*
2416 * These MSRs specify bits which the guest must keep fixed (on or off)
2417 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2418 * We picked the standard core2 setting.
2419 */
2420#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2421#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2422 case MSR_IA32_VMX_CR0_FIXED0:
2423 *pdata = VMXON_CR0_ALWAYSON;
2424 break;
2425 case MSR_IA32_VMX_CR0_FIXED1:
2426 *pdata = -1ULL;
2427 break;
2428 case MSR_IA32_VMX_CR4_FIXED0:
2429 *pdata = VMXON_CR4_ALWAYSON;
2430 break;
2431 case MSR_IA32_VMX_CR4_FIXED1:
2432 *pdata = -1ULL;
2433 break;
2434 case MSR_IA32_VMX_VMCS_ENUM:
2435 *pdata = 0x1f;
2436 break;
2437 case MSR_IA32_VMX_PROCBASED_CTLS2:
2438 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2439 nested_vmx_secondary_ctls_high);
2440 break;
2441 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2442 /* Currently, no nested vpid support */
2443 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2444 break;
2445 default:
b87a51ae 2446 return 1;
b3897a49
NHE		 2447 }
2448
b87a51ae
NHE		 2449 return 0;
2450}
2451
6aa8b732
AK		 2452/*
2453 * Reads an msr value (of 'msr_index') into 'pdata'.
2454 * Returns 0 on success, non-0 otherwise.
2455 * Assumes vcpu_load() was already called.
2456 */
2457static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2458{
2459 u64 data;
26bb0981 2460 struct shared_msr_entry *msr;
6aa8b732
AK		 2461
2462 if (!pdata) {
2463 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2464 return -EINVAL;
2465 }
2466
2467 switch (msr_index) {
05b3e0c2 2468#ifdef CONFIG_X86_64
6aa8b732
AK		 2469 case MSR_FS_BASE:
2470 data = vmcs_readl(GUEST_FS_BASE);
2471 break;
2472 case MSR_GS_BASE:
2473 data = vmcs_readl(GUEST_GS_BASE);
2474 break;
44ea2b17
AK		 2475 case MSR_KERNEL_GS_BASE:
2476 vmx_load_host_state(to_vmx(vcpu));
2477 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2478 break;
26bb0981 2479#endif
6aa8b732 2480 case MSR_EFER:
3bab1f5d 2481 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2482 case MSR_IA32_TSC:
6aa8b732
AK		 2483 data = guest_read_tsc();
2484 break;
2485 case MSR_IA32_SYSENTER_CS:
2486 data = vmcs_read32(GUEST_SYSENTER_CS);
2487 break;
2488 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2489 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2490 break;
2491 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2492 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2493 break;
0dd376e7
LJ		 2494 case MSR_IA32_BNDCFGS:
2495 data = vmcs_read64(GUEST_BNDCFGS);
2496 break;
cae50139
JK		 2497 case MSR_IA32_FEATURE_CONTROL:
2498 if (!nested_vmx_allowed(vcpu))
2499 return 1;
2500 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2501 break;
2502 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2503 if (!nested_vmx_allowed(vcpu))
2504 return 1;
2505 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2506 case MSR_TSC_AUX:
2507 if (!to_vmx(vcpu)->rdtscp_enabled)
2508 return 1;
2509 /* Otherwise falls through */
6aa8b732 2510 default:
8b9cf98c 2511 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2512 if (msr) {
2513 data = msr->data;
2514 break;
6aa8b732 2515 }
3bab1f5d 2516 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2517 }
2518
2519 *pdata = data;
2520 return 0;
2521}
2522
cae50139
JK		 2523static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2524
6aa8b732
AK		 2525/*
2526 * Writes msr value into into the appropriate "register".
2527 * Returns 0 on success, non-0 otherwise.
2528 * Assumes vcpu_load() was already called.
2529 */
8fe8ab46 2530static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2531{
a2fa3e9f 2532 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2533 struct shared_msr_entry *msr;
2cc51560 2534 int ret = 0;
8fe8ab46
WA		 2535 u32 msr_index = msr_info->index;
2536 u64 data = msr_info->data;
2cc51560 2537
6aa8b732 2538 switch (msr_index) {
3bab1f5d 2539 case MSR_EFER:
8fe8ab46 2540 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2541 break;
16175a79 2542#ifdef CONFIG_X86_64
6aa8b732 2543 case MSR_FS_BASE:
2fb92db1 2544 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2545 vmcs_writel(GUEST_FS_BASE, data);
2546 break;
2547 case MSR_GS_BASE:
2fb92db1 2548 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2549 vmcs_writel(GUEST_GS_BASE, data);
2550 break;
44ea2b17
AK		 2551 case MSR_KERNEL_GS_BASE:
2552 vmx_load_host_state(vmx);
2553 vmx->msr_guest_kernel_gs_base = data;
2554 break;
6aa8b732
AK		 2555#endif
2556 case MSR_IA32_SYSENTER_CS:
2557 vmcs_write32(GUEST_SYSENTER_CS, data);
2558 break;
2559 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2560 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2561 break;
2562 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2563 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2564 break;
0dd376e7
LJ		 2565 case MSR_IA32_BNDCFGS:
2566 vmcs_write64(GUEST_BNDCFGS, data);
2567 break;
af24a4e4 2568 case MSR_IA32_TSC:
8fe8ab46 2569 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2570 break;
468d472f
SY		 2571 case MSR_IA32_CR_PAT:
2572 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2573 vmcs_write64(GUEST_IA32_PAT, data);
2574 vcpu->arch.pat = data;
2575 break;
2576 }
8fe8ab46 2577 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2578 break;
ba904635
WA		 2579 case MSR_IA32_TSC_ADJUST:
2580 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2581 break;
cae50139
JK		 2582 case MSR_IA32_FEATURE_CONTROL:
2583 if (!nested_vmx_allowed(vcpu) ||
2584 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2585 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2586 return 1;
2587 vmx->nested.msr_ia32_feature_control = data;
2588 if (msr_info->host_initiated && data == 0)
2589 vmx_leave_nested(vcpu);
2590 break;
2591 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2592 return 1; /* they are read-only */
4e47c7a6
SY		 2593 case MSR_TSC_AUX:
2594 if (!vmx->rdtscp_enabled)
2595 return 1;
2596 /* Check reserved bit, higher 32 bits should be zero */
2597 if ((data >> 32) != 0)
2598 return 1;
2599 /* Otherwise falls through */
6aa8b732 2600 default:
8b9cf98c 2601 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2602 if (msr) {
2603 msr->data = data;
2225fd56
AK		 2604 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2605 preempt_disable();
9ee73970
AK		 2606 kvm_set_shared_msr(msr->index, msr->data,
2607 msr->mask);
2225fd56
AK		 2608 preempt_enable();
2609 }
3bab1f5d 2610 break;
6aa8b732 2611 }
8fe8ab46 2612 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2613 }
2614
2cc51560 2615 return ret;
6aa8b732
AK		 2616}
2617
5fdbf976 2618static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2619{
5fdbf976
MT		 2620 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2621 switch (reg) {
2622 case VCPU_REGS_RSP:
2623 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2624 break;
2625 case VCPU_REGS_RIP:
2626 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2627 break;
6de4f3ad
AK		 2628 case VCPU_EXREG_PDPTR:
2629 if (enable_ept)
2630 ept_save_pdptrs(vcpu);
2631 break;
5fdbf976
MT		 2632 default:
2633 break;
2634 }
6aa8b732
AK		 2635}
2636
6aa8b732
AK		 2637static __init int cpu_has_kvm_support(void)
2638{
6210e37b 2639 return cpu_has_vmx();
6aa8b732
AK		 2640}
2641
2642static __init int vmx_disabled_by_bios(void)
2643{
2644 u64 msr;
2645
2646 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2647 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2648 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2649 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2650 && tboot_enabled())
2651 return 1;
23f3e991 2652 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2653 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2654 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2655 && !tboot_enabled()) {
2656 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2657 "activate TXT before enabling KVM\n");
cafd6659 2658 return 1;
f9335afe 2659 }
23f3e991
JC		 2660 /* launched w/o TXT and VMX disabled */
2661 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2662 && !tboot_enabled())
2663 return 1;
cafd6659
SW		 2664 }
2665
2666 return 0;
6aa8b732
AK		 2667}
2668
7725b894
DX		 2669static void kvm_cpu_vmxon(u64 addr)
2670{
2671 asm volatile (ASM_VMX_VMXON_RAX
2672 : : "a"(&addr), "m"(addr)
2673 : "memory", "cc");
2674}
2675
10474ae8 2676static int hardware_enable(void *garbage)
6aa8b732
AK		 2677{
2678 int cpu = raw_smp_processor_id();
2679 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2680 u64 old, test_bits;
6aa8b732 2681
10474ae8
AG		 2682 if (read_cr4() & X86_CR4_VMXE)
2683 return -EBUSY;
2684
d462b819 2685 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2686
2687 /*
2688 * Now we can enable the vmclear operation in kdump
2689 * since the loaded_vmcss_on_cpu list on this cpu
2690 * has been initialized.
2691 *
2692 * Though the cpu is not in VMX operation now, there
2693 * is no problem to enable the vmclear operation
2694 * for the loaded_vmcss_on_cpu list is empty!
2695 */
2696 crash_enable_local_vmclear(cpu);
2697
6aa8b732 2698 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2699
2700 test_bits = FEATURE_CONTROL_LOCKED;
2701 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2702 if (tboot_enabled())
2703 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2704
2705 if ((old & test_bits) != test_bits) {
6aa8b732 2706 /* enable and lock */
cafd6659
SW		 2707 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2708 }
66aee91a 2709 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2710
4610c9cc
DX		 2711 if (vmm_exclusive) {
2712 kvm_cpu_vmxon(phys_addr);
2713 ept_sync_global();
2714 }
10474ae8 2715
357d1226 2716 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2717
10474ae8 2718 return 0;
6aa8b732
AK		 2719}
2720
d462b819 2721static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2722{
2723 int cpu = raw_smp_processor_id();
d462b819 2724 struct loaded_vmcs *v, *n;
543e4243 2725
d462b819
NHE		 2726 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2727 loaded_vmcss_on_cpu_link)
2728 __loaded_vmcs_clear(v);
543e4243
AK		 2729}
2730
710ff4a8
EH		 2731
2732/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2733 * tricks.
2734 */
2735static void kvm_cpu_vmxoff(void)
6aa8b732 2736{
4ecac3fd 2737 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2738}
2739
710ff4a8
EH		 2740static void hardware_disable(void *garbage)
2741{
4610c9cc 2742 if (vmm_exclusive) {
d462b819 2743 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2744 kvm_cpu_vmxoff();
2745 }
7725b894 2746 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2747}
2748
1c3d14fe 2749static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2750 u32 msr, u32 *result)
1c3d14fe
YS		 2751{
2752 u32 vmx_msr_low, vmx_msr_high;
2753 u32 ctl = ctl_min | ctl_opt;
2754
2755 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2756
2757 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2758 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2759
2760 /* Ensure minimum (required) set of control bits are supported. */
2761 if (ctl_min & ~ctl)
002c7f7c 2762 return -EIO;
1c3d14fe
YS		 2763
2764 *result = ctl;
2765 return 0;
2766}
2767
110312c8
AK		 2768static __init bool allow_1_setting(u32 msr, u32 ctl)
2769{
2770 u32 vmx_msr_low, vmx_msr_high;
2771
2772 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2773 return vmx_msr_high & ctl;
2774}
2775
002c7f7c 2776static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2777{
2778 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2779 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2780 u32 _pin_based_exec_control = 0;
2781 u32 _cpu_based_exec_control = 0;
f78e0e2e 2782 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2783 u32 _vmexit_control = 0;
2784 u32 _vmentry_control = 0;
2785
10166744 2786 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2787#ifdef CONFIG_X86_64
2788 CPU_BASED_CR8_LOAD_EXITING |
2789 CPU_BASED_CR8_STORE_EXITING |
2790#endif
d56f546d
SY		 2791 CPU_BASED_CR3_LOAD_EXITING |
2792 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2793 CPU_BASED_USE_IO_BITMAPS |
2794 CPU_BASED_MOV_DR_EXITING |
a7052897 2795 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2796 CPU_BASED_MWAIT_EXITING |
2797 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2798 CPU_BASED_INVLPG_EXITING |
2799 CPU_BASED_RDPMC_EXITING;
443381a8 2800
f78e0e2e 2801 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2802 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2803 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2804 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2805 &_cpu_based_exec_control) < 0)
002c7f7c 2806 return -EIO;
6e5d865c
YS		 2807#ifdef CONFIG_X86_64
2808 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2809 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2810 ~CPU_BASED_CR8_STORE_EXITING;
2811#endif
f78e0e2e 2812 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2813 min2 = 0;
2814 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2815 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2816 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2817 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2818 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2819 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2820 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2821 SECONDARY_EXEC_RDTSCP |
83d4c286 2822 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2823 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2824 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2825 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2826 if (adjust_vmx_controls(min2, opt2,
2827 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2828 &_cpu_based_2nd_exec_control) < 0)
2829 return -EIO;
2830 }
2831#ifndef CONFIG_X86_64
2832 if (!(_cpu_based_2nd_exec_control &
2833 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2834 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2835#endif
83d4c286
YZ		 2836
2837 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2838 _cpu_based_2nd_exec_control &= ~(
8d14695f 2839 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2840 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2841 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2842
d56f546d 2843 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2844 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2845 enabled */
5fff7d27
GN		 2846 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2847 CPU_BASED_CR3_STORE_EXITING |
2848 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2849 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2850 vmx_capability.ept, vmx_capability.vpid);
2851 }
1c3d14fe
YS		 2852
2853 min = 0;
2854#ifdef CONFIG_X86_64
2855 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2856#endif
a547c6db 2857 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2858 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2859 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2860 &_vmexit_control) < 0)
002c7f7c 2861 return -EIO;
1c3d14fe 2862
01e439be
YZ		 2863 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2864 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2865 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2866 &_pin_based_exec_control) < 0)
2867 return -EIO;
2868
2869 if (!(_cpu_based_2nd_exec_control &
2870 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2871 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2872 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2873
c845f9c6 2874 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2875 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2876 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2877 &_vmentry_control) < 0)
002c7f7c 2878 return -EIO;
6aa8b732 2879
c68876fd 2880 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2881
2882 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2883 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2884 return -EIO;
1c3d14fe
YS		 2885
2886#ifdef CONFIG_X86_64
2887 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2888 if (vmx_msr_high & (1u<<16))
002c7f7c 2889 return -EIO;
1c3d14fe
YS		 2890#endif
2891
2892 /* Require Write-Back (WB) memory type for VMCS accesses. */
2893 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2894 return -EIO;
1c3d14fe 2895
002c7f7c
YS		 2896 vmcs_conf->size = vmx_msr_high & 0x1fff;
2897 vmcs_conf->order = get_order(vmcs_config.size);
2898 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2899
002c7f7c
YS		 2900 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2901 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2902 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2903 vmcs_conf->vmexit_ctrl = _vmexit_control;
2904 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2905
110312c8
AK		 2906 cpu_has_load_ia32_efer =
2907 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2908 VM_ENTRY_LOAD_IA32_EFER)
2909 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2910 VM_EXIT_LOAD_IA32_EFER);
2911
8bf00a52
GN		 2912 cpu_has_load_perf_global_ctrl =
2913 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2914 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2915 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2916 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2917
2918 /*
2919 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2920 * but due to arrata below it can't be used. Workaround is to use
2921 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2922 *
2923 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2924 *
2925 * AAK155 (model 26)
2926 * AAP115 (model 30)
2927 * AAT100 (model 37)
2928 * BC86,AAY89,BD102 (model 44)
2929 * BA97 (model 46)
2930 *
2931 */
2932 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2933 switch (boot_cpu_data.x86_model) {
2934 case 26:
2935 case 30:
2936 case 37:
2937 case 44:
2938 case 46:
2939 cpu_has_load_perf_global_ctrl = false;
2940 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2941 "does not work properly. Using workaround\n");
2942 break;
2943 default:
2944 break;
2945 }
2946 }
2947
1c3d14fe 2948 return 0;
c68876fd 2949}
6aa8b732
AK		 2950
2951static struct vmcs *alloc_vmcs_cpu(int cpu)
2952{
2953 int node = cpu_to_node(cpu);
2954 struct page *pages;
2955 struct vmcs *vmcs;
2956
6484eb3e 2957 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2958 if (!pages)
2959 return NULL;
2960 vmcs = page_address(pages);
1c3d14fe
YS		 2961 memset(vmcs, 0, vmcs_config.size);
2962 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2963 return vmcs;
2964}
2965
2966static struct vmcs *alloc_vmcs(void)
2967{
d3b2c338 2968 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2969}
2970
2971static void free_vmcs(struct vmcs *vmcs)
2972{
1c3d14fe 2973 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2974}
2975
d462b819
NHE		 2976/*
2977 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2978 */
2979static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2980{
2981 if (!loaded_vmcs->vmcs)
2982 return;
2983 loaded_vmcs_clear(loaded_vmcs);
2984 free_vmcs(loaded_vmcs->vmcs);
2985 loaded_vmcs->vmcs = NULL;
2986}
2987
39959588 2988static void free_kvm_area(void)
6aa8b732
AK		 2989{
2990 int cpu;
2991
3230bb47 2992 for_each_possible_cpu(cpu) {
6aa8b732 2993 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2994 per_cpu(vmxarea, cpu) = NULL;
2995 }
6aa8b732
AK		 2996}
2997
6aa8b732
AK		 2998static __init int alloc_kvm_area(void)
2999{
3000 int cpu;
3001
3230bb47 3002 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3003 struct vmcs *vmcs;
3004
3005 vmcs = alloc_vmcs_cpu(cpu);
3006 if (!vmcs) {
3007 free_kvm_area();
3008 return -ENOMEM;
3009 }
3010
3011 per_cpu(vmxarea, cpu) = vmcs;
3012 }
3013 return 0;
3014}
3015
3016static __init int hardware_setup(void)
3017{
002c7f7c
YS		 3018 if (setup_vmcs_config(&vmcs_config) < 0)
3019 return -EIO;
50a37eb4
JR		 3020
3021 if (boot_cpu_has(X86_FEATURE_NX))
3022 kvm_enable_efer_bits(EFER_NX);
3023
93ba03c2
SY		 3024 if (!cpu_has_vmx_vpid())
3025 enable_vpid = 0;
abc4fc58
AG		 3026 if (!cpu_has_vmx_shadow_vmcs())
3027 enable_shadow_vmcs = 0;
93ba03c2 3028
4bc9b982
SY		 3029 if (!cpu_has_vmx_ept() ||
3030 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3031 enable_ept = 0;
3a624e29 3032 enable_unrestricted_guest = 0;
83c3a331 3033 enable_ept_ad_bits = 0;
3a624e29
NK		 3034 }
3035
83c3a331
XH		 3036 if (!cpu_has_vmx_ept_ad_bits())
3037 enable_ept_ad_bits = 0;
3038
3a624e29
NK		 3039 if (!cpu_has_vmx_unrestricted_guest())
3040 enable_unrestricted_guest = 0;
93ba03c2
SY		 3041
3042 if (!cpu_has_vmx_flexpriority())
3043 flexpriority_enabled = 0;
3044
95ba8273
GN		 3045 if (!cpu_has_vmx_tpr_shadow())
3046 kvm_x86_ops->update_cr8_intercept = NULL;
3047
54dee993
MT		 3048 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3049 kvm_disable_largepages();
3050
4b8d54f9
ZE		 3051 if (!cpu_has_vmx_ple())
3052 ple_gap = 0;
3053
01e439be
YZ		 3054 if (!cpu_has_vmx_apicv())
3055 enable_apicv = 0;
c7c9c56c 3056
01e439be 3057 if (enable_apicv)
c7c9c56c 3058 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3059 else {
c7c9c56c 3060 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3061 kvm_x86_ops->deliver_posted_interrupt = NULL;
3062 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3063 }
83d4c286 3064
b87a51ae
NHE		 3065 if (nested)
3066 nested_vmx_setup_ctls_msrs();
3067
6aa8b732
AK		 3068 return alloc_kvm_area();
3069}
3070
3071static __exit void hardware_unsetup(void)
3072{
3073 free_kvm_area();
3074}
3075
14168786
GN		 3076static bool emulation_required(struct kvm_vcpu *vcpu)
3077{
3078 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3079}
3080
91b0aa2c 3081static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3082 struct kvm_segment *save)
6aa8b732 3083{
d99e4152
GN		 3084 if (!emulate_invalid_guest_state) {
3085 /*
3086 * CS and SS RPL should be equal during guest entry according
3087 * to VMX spec, but in reality it is not always so. Since vcpu
3088 * is in the middle of the transition from real mode to
3089 * protected mode it is safe to assume that RPL 0 is a good
3090 * default value.
3091 */
3092 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3093 save->selector &= ~SELECTOR_RPL_MASK;
3094 save->dpl = save->selector & SELECTOR_RPL_MASK;
3095 save->s = 1;
6aa8b732 3096 }
d99e4152 3097 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3098}
3099
3100static void enter_pmode(struct kvm_vcpu *vcpu)
3101{
3102 unsigned long flags;
a89a8fb9 3103 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3104
d99e4152
GN		 3105 /*
3106 * Update real mode segment cache. It may be not up-to-date if sement
3107 * register was written while vcpu was in a guest mode.
3108 */
3109 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3110 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3111 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3112 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3113 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3114 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3115
7ffd92c5 3116 vmx->rmode.vm86_active = 0;
6aa8b732 3117
2fb92db1
AK		 3118 vmx_segment_cache_clear(vmx);
3119
f5f7b2fe 3120 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3121
3122 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3123 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3124 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3125 vmcs_writel(GUEST_RFLAGS, flags);
3126
66aee91a
RR		 3127 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3128 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3129
3130 update_exception_bitmap(vcpu);
3131
91b0aa2c
GN		 3132 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3133 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3134 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3135 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3136 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3137 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3138
3139 /* CPL is always 0 when CPU enters protected mode */
3140 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3141 vmx->cpl = 0;
6aa8b732
AK		 3142}
3143
f5f7b2fe 3144static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3145{
772e0318 3146 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3147 struct kvm_segment var = *save;
3148
3149 var.dpl = 0x3;
3150 if (seg == VCPU_SREG_CS)
3151 var.type = 0x3;
3152
3153 if (!emulate_invalid_guest_state) {
3154 var.selector = var.base >> 4;
3155 var.base = var.base & 0xffff0;
3156 var.limit = 0xffff;
3157 var.g = 0;
3158 var.db = 0;
3159 var.present = 1;
3160 var.s = 1;
3161 var.l = 0;
3162 var.unusable = 0;
3163 var.type = 0x3;
3164 var.avl = 0;
3165 if (save->base & 0xf)
3166 printk_once(KERN_WARNING "kvm: segment base is not "
3167 "paragraph aligned when entering "
3168 "protected mode (seg=%d)", seg);
3169 }
6aa8b732 3170
d99e4152
GN		 3171 vmcs_write16(sf->selector, var.selector);
3172 vmcs_write32(sf->base, var.base);
3173 vmcs_write32(sf->limit, var.limit);
3174 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3175}
3176
3177static void enter_rmode(struct kvm_vcpu *vcpu)
3178{
3179 unsigned long flags;
a89a8fb9 3180 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3181
f5f7b2fe
AK		 3182 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3183 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3184 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3185 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3186 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3187 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3188 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3189
7ffd92c5 3190 vmx->rmode.vm86_active = 1;
6aa8b732 3191
776e58ea
GN		 3192 /*
3193 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3194 * vcpu. Warn the user that an update is overdue.
776e58ea 3195 */
4918c6ca 3196 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3197 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3198 "called before entering vcpu\n");
776e58ea 3199
2fb92db1
AK		 3200 vmx_segment_cache_clear(vmx);
3201
4918c6ca 3202 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3203 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3204 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3205
3206 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3207 vmx->rmode.save_rflags = flags;
6aa8b732 3208
053de044 3209 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3210
3211 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3212 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3213 update_exception_bitmap(vcpu);
3214
d99e4152
GN		 3215 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3216 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3217 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3218 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3219 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3220 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3221
8668a3c4 3222 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3223}
3224
401d10de
AS		 3225static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3226{
3227 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3228 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3229
3230 if (!msr)
3231 return;
401d10de 3232
44ea2b17
AK		 3233 /*
3234 * Force kernel_gs_base reloading before EFER changes, as control
3235 * of this msr depends on is_long_mode().
3236 */
3237 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3238 vcpu->arch.efer = efer;
401d10de 3239 if (efer & EFER_LMA) {
2961e876 3240 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3241 msr->data = efer;
3242 } else {
2961e876 3243 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3244
3245 msr->data = efer & ~EFER_LME;
3246 }
3247 setup_msrs(vmx);
3248}
3249
05b3e0c2 3250#ifdef CONFIG_X86_64
6aa8b732
AK		 3251
3252static void enter_lmode(struct kvm_vcpu *vcpu)
3253{
3254 u32 guest_tr_ar;
3255
2fb92db1
AK		 3256 vmx_segment_cache_clear(to_vmx(vcpu));
3257
6aa8b732
AK		 3258 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3259 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3260 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3261 __func__);
6aa8b732
AK		 3262 vmcs_write32(GUEST_TR_AR_BYTES,
3263 (guest_tr_ar & ~AR_TYPE_MASK)
3264 | AR_TYPE_BUSY_64_TSS);
3265 }
da38f438 3266 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3267}
3268
3269static void exit_lmode(struct kvm_vcpu *vcpu)
3270{
2961e876 3271 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3272 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3273}
3274
3275#endif
3276
2384d2b3
SY		 3277static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3278{
b9d762fa 3279 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3280 if (enable_ept) {
3281 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3282 return;
4e1096d2 3283 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3284 }
2384d2b3
SY		 3285}
3286
e8467fda
AK		 3287static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3288{
3289 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3290
3291 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3292 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3293}
3294
aff48baa
AK		 3295static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3296{
3297 if (enable_ept && is_paging(vcpu))
3298 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3299 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3300}
3301
25c4c276 3302static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3303{
fc78f519
AK		 3304 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3305
3306 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3307 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3308}
3309
1439442c
SY		 3310static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3311{
d0d538b9
GN		 3312 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3313
6de4f3ad
AK		 3314 if (!test_bit(VCPU_EXREG_PDPTR,
3315 (unsigned long *)&vcpu->arch.regs_dirty))
3316 return;
3317
1439442c 3318 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3319 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3320 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3321 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3322 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3323 }
3324}
3325
8f5d549f
AK		 3326static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3327{
d0d538b9
GN		 3328 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3329
8f5d549f 3330 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3331 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3332 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3333 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3334 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3335 }
6de4f3ad
AK		 3336
3337 __set_bit(VCPU_EXREG_PDPTR,
3338 (unsigned long *)&vcpu->arch.regs_avail);
3339 __set_bit(VCPU_EXREG_PDPTR,
3340 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3341}
3342
5e1746d6 3343static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3344
3345static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3346 unsigned long cr0,
3347 struct kvm_vcpu *vcpu)
3348{
5233dd51
MT		 3349 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3350 vmx_decache_cr3(vcpu);
1439442c
SY		 3351 if (!(cr0 & X86_CR0_PG)) {
3352 /* From paging/starting to nonpaging */
3353 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3354 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3355 (CPU_BASED_CR3_LOAD_EXITING |
3356 CPU_BASED_CR3_STORE_EXITING));
3357 vcpu->arch.cr0 = cr0;
fc78f519 3358 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3359 } else if (!is_paging(vcpu)) {
3360 /* From nonpaging to paging */
3361 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3362 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3363 ~(CPU_BASED_CR3_LOAD_EXITING |
3364 CPU_BASED_CR3_STORE_EXITING));
3365 vcpu->arch.cr0 = cr0;
fc78f519 3366 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3367 }
95eb84a7
SY		 3368
3369 if (!(cr0 & X86_CR0_WP))
3370 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3371}
3372
6aa8b732
AK		 3373static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3374{
7ffd92c5 3375 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3376 unsigned long hw_cr0;
3377
5037878e 3378 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3379 if (enable_unrestricted_guest)
5037878e 3380 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3381 else {
5037878e 3382 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3383
218e763f
GN		 3384 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3385 enter_pmode(vcpu);
6aa8b732 3386
218e763f
GN		 3387 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3388 enter_rmode(vcpu);
3389 }
6aa8b732 3390
05b3e0c2 3391#ifdef CONFIG_X86_64
f6801dff 3392 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3393 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3394 enter_lmode(vcpu);
707d92fa 3395 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3396 exit_lmode(vcpu);
3397 }
3398#endif
3399
089d034e 3400 if (enable_ept)
1439442c
SY		 3401 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3402
02daab21 3403 if (!vcpu->fpu_active)
81231c69 3404 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3405
6aa8b732 3406 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3407 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3408 vcpu->arch.cr0 = cr0;
14168786
GN		 3409
3410 /* depends on vcpu->arch.cr0 to be set to a new value */
3411 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3412}
3413
1439442c
SY		 3414static u64 construct_eptp(unsigned long root_hpa)
3415{
3416 u64 eptp;
3417
3418 /* TODO write the value reading from MSR */
3419 eptp = VMX_EPT_DEFAULT_MT |
3420 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3421 if (enable_ept_ad_bits)
3422 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3423 eptp |= (root_hpa & PAGE_MASK);
3424
3425 return eptp;
3426}
3427
6aa8b732
AK		 3428static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3429{
1439442c
SY		 3430 unsigned long guest_cr3;
3431 u64 eptp;
3432
3433 guest_cr3 = cr3;
089d034e 3434 if (enable_ept) {
1439442c
SY		 3435 eptp = construct_eptp(cr3);
3436 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3437 if (is_paging(vcpu) || is_guest_mode(vcpu))
3438 guest_cr3 = kvm_read_cr3(vcpu);
3439 else
3440 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3441 ept_load_pdptrs(vcpu);
1439442c
SY		 3442 }
3443
2384d2b3 3444 vmx_flush_tlb(vcpu);
1439442c 3445 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3446}
3447
5e1746d6 3448static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3449{
7ffd92c5 3450 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3451 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3452
5e1746d6
NHE		 3453 if (cr4 & X86_CR4_VMXE) {
3454 /*
3455 * To use VMXON (and later other VMX instructions), a guest
3456 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3457 * So basically the check on whether to allow nested VMX
3458 * is here.
3459 */
3460 if (!nested_vmx_allowed(vcpu))
3461 return 1;
1a0d74e6
JK		 3462 }
3463 if (to_vmx(vcpu)->nested.vmxon &&
3464 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3465 return 1;
3466
ad312c7c 3467 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3468 if (enable_ept) {
3469 if (!is_paging(vcpu)) {
3470 hw_cr4 &= ~X86_CR4_PAE;
3471 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3472 /*
3473 * SMEP is disabled if CPU is in non-paging mode in
3474 * hardware. However KVM always uses paging mode to
3475 * emulate guest non-paging mode with TDP.
3476 * To emulate this behavior, SMEP needs to be manually
3477 * disabled when guest switches to non-paging mode.
3478 */
3479 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3480 } else if (!(cr4 & X86_CR4_PAE)) {
3481 hw_cr4 &= ~X86_CR4_PAE;
3482 }
3483 }
1439442c
SY		 3484
3485 vmcs_writel(CR4_READ_SHADOW, cr4);
3486 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3487 return 0;
6aa8b732
AK		 3488}
3489
6aa8b732
AK		 3490static void vmx_get_segment(struct kvm_vcpu *vcpu,
3491 struct kvm_segment *var, int seg)
3492{
a9179499 3493 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3494 u32 ar;
3495
c6ad1153 3496 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3497 *var = vmx->rmode.segs[seg];
a9179499 3498 if (seg == VCPU_SREG_TR
2fb92db1 3499 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3500 return;
1390a28b
AK		 3501 var->base = vmx_read_guest_seg_base(vmx, seg);
3502 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3503 return;
a9179499 3504 }
2fb92db1
AK		 3505 var->base = vmx_read_guest_seg_base(vmx, seg);
3506 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3507 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3508 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3509 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3510 var->type = ar & 15;
3511 var->s = (ar >> 4) & 1;
3512 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3513 /*
3514 * Some userspaces do not preserve unusable property. Since usable
3515 * segment has to be present according to VMX spec we can use present
3516 * property to amend userspace bug by making unusable segment always
3517 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3518 * segment as unusable.
3519 */
3520 var->present = !var->unusable;
6aa8b732
AK		 3521 var->avl = (ar >> 12) & 1;
3522 var->l = (ar >> 13) & 1;
3523 var->db = (ar >> 14) & 1;
3524 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3525}
3526
a9179499
AK		 3527static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3528{
a9179499
AK		 3529 struct kvm_segment s;
3530
3531 if (to_vmx(vcpu)->rmode.vm86_active) {
3532 vmx_get_segment(vcpu, &s, seg);
3533 return s.base;
3534 }
2fb92db1 3535 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3536}
3537
b09408d0 3538static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3539{
b09408d0
MT		 3540 struct vcpu_vmx *vmx = to_vmx(vcpu);
3541
3eeb3288 3542 if (!is_protmode(vcpu))
2e4d2653
IE		 3543 return 0;
3544
f4c63e5d
AK		 3545 if (!is_long_mode(vcpu)
3546 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3547 return 3;
3548
69c73028
AK		 3549 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3550 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3551 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3552 }
d881e6f6
AK		 3553
3554 return vmx->cpl;
69c73028
AK		 3555}
3556
3557
653e3108 3558static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3559{
6aa8b732
AK		 3560 u32 ar;
3561
f0495f9b 3562 if (var->unusable || !var->present)
6aa8b732
AK		 3563 ar = 1 << 16;
3564 else {
3565 ar = var->type & 15;
3566 ar |= (var->s & 1) << 4;
3567 ar |= (var->dpl & 3) << 5;
3568 ar |= (var->present & 1) << 7;
3569 ar |= (var->avl & 1) << 12;
3570 ar |= (var->l & 1) << 13;
3571 ar |= (var->db & 1) << 14;
3572 ar |= (var->g & 1) << 15;
3573 }
653e3108
AK		 3574
3575 return ar;
3576}
3577
3578static void vmx_set_segment(struct kvm_vcpu *vcpu,
3579 struct kvm_segment *var, int seg)
3580{
7ffd92c5 3581 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3582 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3583
2fb92db1 3584 vmx_segment_cache_clear(vmx);
2f143240
GN		 3585 if (seg == VCPU_SREG_CS)
3586 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3587
1ecd50a9
GN		 3588 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3589 vmx->rmode.segs[seg] = *var;
3590 if (seg == VCPU_SREG_TR)
3591 vmcs_write16(sf->selector, var->selector);
3592 else if (var->s)
3593 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3594 goto out;
653e3108 3595 }
1ecd50a9 3596
653e3108
AK		 3597 vmcs_writel(sf->base, var->base);
3598 vmcs_write32(sf->limit, var->limit);
3599 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3600
3601 /*
3602 * Fix the "Accessed" bit in AR field of segment registers for older
3603 * qemu binaries.
3604 * IA32 arch specifies that at the time of processor reset the
3605 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3606 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3607 * state vmexit when "unrestricted guest" mode is turned on.
3608 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3609 * tree. Newer qemu binaries with that qemu fix would not need this
3610 * kvm hack.
3611 */
3612 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3613 var->type |= 0x1; /* Accessed */
3a624e29 3614
f924d66d 3615 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3616
3617out:
14168786 3618 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3619}
3620
6aa8b732
AK		 3621static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3622{
2fb92db1 3623 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3624
3625 *db = (ar >> 14) & 1;
3626 *l = (ar >> 13) & 1;
3627}
3628
89a27f4d 3629static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3630{
89a27f4d
GN		 3631 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3632 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3633}
3634
89a27f4d 3635static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3636{
89a27f4d
GN		 3637 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3638 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3639}
3640
89a27f4d 3641static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3642{
89a27f4d
GN		 3643 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3644 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3645}
3646
89a27f4d 3647static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3648{
89a27f4d
GN		 3649 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3650 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3651}
3652
648dfaa7
MG		 3653static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3654{
3655 struct kvm_segment var;
3656 u32 ar;
3657
3658 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3659 var.dpl = 0x3;
0647f4aa
GN		 3660 if (seg == VCPU_SREG_CS)
3661 var.type = 0x3;
648dfaa7
MG		 3662 ar = vmx_segment_access_rights(&var);
3663
3664 if (var.base != (var.selector << 4))
3665 return false;
89efbed0 3666 if (var.limit != 0xffff)
648dfaa7 3667 return false;
07f42f5f 3668 if (ar != 0xf3)
648dfaa7
MG		 3669 return false;
3670
3671 return true;
3672}
3673
3674static bool code_segment_valid(struct kvm_vcpu *vcpu)
3675{
3676 struct kvm_segment cs;
3677 unsigned int cs_rpl;
3678
3679 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3680 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3681
1872a3f4
AK		 3682 if (cs.unusable)
3683 return false;
648dfaa7
MG		 3684 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3685 return false;
3686 if (!cs.s)
3687 return false;
1872a3f4 3688 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3689 if (cs.dpl > cs_rpl)
3690 return false;
1872a3f4 3691 } else {
648dfaa7
MG		 3692 if (cs.dpl != cs_rpl)
3693 return false;
3694 }
3695 if (!cs.present)
3696 return false;
3697
3698 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3699 return true;
3700}
3701
3702static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3703{
3704 struct kvm_segment ss;
3705 unsigned int ss_rpl;
3706
3707 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3708 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3709
1872a3f4
AK		 3710 if (ss.unusable)
3711 return true;
3712 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3713 return false;
3714 if (!ss.s)
3715 return false;
3716 if (ss.dpl != ss_rpl) /* DPL != RPL */
3717 return false;
3718 if (!ss.present)
3719 return false;
3720
3721 return true;
3722}
3723
3724static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3725{
3726 struct kvm_segment var;
3727 unsigned int rpl;
3728
3729 vmx_get_segment(vcpu, &var, seg);
3730 rpl = var.selector & SELECTOR_RPL_MASK;
3731
1872a3f4
AK		 3732 if (var.unusable)
3733 return true;
648dfaa7
MG		 3734 if (!var.s)
3735 return false;
3736 if (!var.present)
3737 return false;
3738 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3739 if (var.dpl < rpl) /* DPL < RPL */
3740 return false;
3741 }
3742
3743 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3744 * rights flags
3745 */
3746 return true;
3747}
3748
3749static bool tr_valid(struct kvm_vcpu *vcpu)
3750{
3751 struct kvm_segment tr;
3752
3753 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3754
1872a3f4
AK		 3755 if (tr.unusable)
3756 return false;
648dfaa7
MG		 3757 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3758 return false;
1872a3f4 3759 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3760 return false;
3761 if (!tr.present)
3762 return false;
3763
3764 return true;
3765}
3766
3767static bool ldtr_valid(struct kvm_vcpu *vcpu)
3768{
3769 struct kvm_segment ldtr;
3770
3771 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3772
1872a3f4
AK		 3773 if (ldtr.unusable)
3774 return true;
648dfaa7
MG		 3775 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3776 return false;
3777 if (ldtr.type != 2)
3778 return false;
3779 if (!ldtr.present)
3780 return false;
3781
3782 return true;
3783}
3784
3785static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3786{
3787 struct kvm_segment cs, ss;
3788
3789 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3790 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3791
3792 return ((cs.selector & SELECTOR_RPL_MASK) ==
3793 (ss.selector & SELECTOR_RPL_MASK));
3794}
3795
3796/*
3797 * Check if guest state is valid. Returns true if valid, false if
3798 * not.
3799 * We assume that registers are always usable
3800 */
3801static bool guest_state_valid(struct kvm_vcpu *vcpu)
3802{
c5e97c80
GN		 3803 if (enable_unrestricted_guest)
3804 return true;
3805
648dfaa7 3806 /* real mode guest state checks */
f13882d8 3807 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3808 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3809 return false;
3810 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3811 return false;
3812 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3813 return false;
3814 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3815 return false;
3816 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3817 return false;
3818 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3819 return false;
3820 } else {
3821 /* protected mode guest state checks */
3822 if (!cs_ss_rpl_check(vcpu))
3823 return false;
3824 if (!code_segment_valid(vcpu))
3825 return false;
3826 if (!stack_segment_valid(vcpu))
3827 return false;
3828 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3829 return false;
3830 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3831 return false;
3832 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3833 return false;
3834 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3835 return false;
3836 if (!tr_valid(vcpu))
3837 return false;
3838 if (!ldtr_valid(vcpu))
3839 return false;
3840 }
3841 /* TODO:
3842 * - Add checks on RIP
3843 * - Add checks on RFLAGS
3844 */
3845
3846 return true;
3847}
3848
d77c26fc 3849static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3850{
40dcaa9f 3851 gfn_t fn;
195aefde 3852 u16 data = 0;
40dcaa9f 3853 int r, idx, ret = 0;
6aa8b732 3854
40dcaa9f 3855 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3856 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3857 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3858 if (r < 0)
10589a46 3859 goto out;
195aefde 3860 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3861 r = kvm_write_guest_page(kvm, fn++, &data,
3862 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3863 if (r < 0)
10589a46 3864 goto out;
195aefde
IE		 3865 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3866 if (r < 0)
10589a46 3867 goto out;
195aefde
IE		 3868 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3869 if (r < 0)
10589a46 3870 goto out;
195aefde 3871 data = ~0;
10589a46
MT		 3872 r = kvm_write_guest_page(kvm, fn, &data,
3873 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3874 sizeof(u8));
195aefde 3875 if (r < 0)
10589a46
MT		 3876 goto out;
3877
3878 ret = 1;
3879out:
40dcaa9f 3880 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3881 return ret;
6aa8b732
AK		 3882}
3883
b7ebfb05
SY		 3884static int init_rmode_identity_map(struct kvm *kvm)
3885{
40dcaa9f 3886 int i, idx, r, ret;
b7ebfb05
SY		 3887 pfn_t identity_map_pfn;
3888 u32 tmp;
3889
089d034e 3890 if (!enable_ept)
b7ebfb05
SY		 3891 return 1;
3892 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3893 printk(KERN_ERR "EPT: identity-mapping pagetable "
3894 "haven't been allocated!\n");
3895 return 0;
3896 }
3897 if (likely(kvm->arch.ept_identity_pagetable_done))
3898 return 1;
3899 ret = 0;
b927a3ce 3900 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3901 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3902 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3903 if (r < 0)
3904 goto out;
3905 /* Set up identity-mapping pagetable for EPT in real mode */
3906 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3907 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3908 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3909 r = kvm_write_guest_page(kvm, identity_map_pfn,
3910 &tmp, i * sizeof(tmp), sizeof(tmp));
3911 if (r < 0)
3912 goto out;
3913 }
3914 kvm->arch.ept_identity_pagetable_done = true;
3915 ret = 1;
3916out:
40dcaa9f 3917 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3918 return ret;
3919}
3920
6aa8b732
AK		 3921static void seg_setup(int seg)
3922{
772e0318 3923 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3924 unsigned int ar;
6aa8b732
AK		 3925
3926 vmcs_write16(sf->selector, 0);
3927 vmcs_writel(sf->base, 0);
3928 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3929 ar = 0x93;
3930 if (seg == VCPU_SREG_CS)
3931 ar |= 0x08; /* code segment */
3a624e29
NK		 3932
3933 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3934}
3935
f78e0e2e
SY		 3936static int alloc_apic_access_page(struct kvm *kvm)
3937{
4484141a 3938 struct page *page;
f78e0e2e
SY		 3939 struct kvm_userspace_memory_region kvm_userspace_mem;
3940 int r = 0;
3941
79fac95e 3942 mutex_lock(&kvm->slots_lock);
bfc6d222 3943 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3944 goto out;
3945 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3946 kvm_userspace_mem.flags = 0;
3947 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3948 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3949 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3950 if (r)
3951 goto out;
72dc67a6 3952
4484141a
XG		 3953 page = gfn_to_page(kvm, 0xfee00);
3954 if (is_error_page(page)) {
3955 r = -EFAULT;
3956 goto out;
3957 }
3958
3959 kvm->arch.apic_access_page = page;
f78e0e2e 3960out:
79fac95e 3961 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3962 return r;
3963}
3964
b7ebfb05
SY		 3965static int alloc_identity_pagetable(struct kvm *kvm)
3966{
4484141a 3967 struct page *page;
b7ebfb05
SY		 3968 struct kvm_userspace_memory_region kvm_userspace_mem;
3969 int r = 0;
3970
79fac95e 3971 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3972 if (kvm->arch.ept_identity_pagetable)
3973 goto out;
3974 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3975 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3976 kvm_userspace_mem.guest_phys_addr =
3977 kvm->arch.ept_identity_map_addr;
b7ebfb05 3978 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3979 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3980 if (r)
3981 goto out;
3982
4484141a
XG		 3983 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3984 if (is_error_page(page)) {
3985 r = -EFAULT;
3986 goto out;
3987 }
3988
3989 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3990out:
79fac95e 3991 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3992 return r;
3993}
3994
2384d2b3
SY		 3995static void allocate_vpid(struct vcpu_vmx *vmx)
3996{
3997 int vpid;
3998
3999 vmx->vpid = 0;
919818ab 4000 if (!enable_vpid)
2384d2b3
SY		 4001 return;
4002 spin_lock(&vmx_vpid_lock);
4003 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4004 if (vpid < VMX_NR_VPIDS) {
4005 vmx->vpid = vpid;
4006 __set_bit(vpid, vmx_vpid_bitmap);
4007 }
4008 spin_unlock(&vmx_vpid_lock);
4009}
4010
cdbecfc3
LJ		 4011static void free_vpid(struct vcpu_vmx *vmx)
4012{
4013 if (!enable_vpid)
4014 return;
4015 spin_lock(&vmx_vpid_lock);
4016 if (vmx->vpid != 0)
4017 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4018 spin_unlock(&vmx_vpid_lock);
4019}
4020
8d14695f
YZ		 4021#define MSR_TYPE_R 1
4022#define MSR_TYPE_W 2
4023static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4024 u32 msr, int type)
25c5f225 4025{
3e7c73e9 4026 int f = sizeof(unsigned long);
25c5f225
SY		 4027
4028 if (!cpu_has_vmx_msr_bitmap())
4029 return;
4030
4031 /*
4032 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4033 * have the write-low and read-high bitmap offsets the wrong way round.
4034 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4035 */
25c5f225 4036 if (msr <= 0x1fff) {
8d14695f
YZ		 4037 if (type & MSR_TYPE_R)
4038 /* read-low */
4039 __clear_bit(msr, msr_bitmap + 0x000 / f);
4040
4041 if (type & MSR_TYPE_W)
4042 /* write-low */
4043 __clear_bit(msr, msr_bitmap + 0x800 / f);
4044
25c5f225
SY		 4045 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4046 msr &= 0x1fff;
8d14695f
YZ		 4047 if (type & MSR_TYPE_R)
4048 /* read-high */
4049 __clear_bit(msr, msr_bitmap + 0x400 / f);
4050
4051 if (type & MSR_TYPE_W)
4052 /* write-high */
4053 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4054
4055 }
4056}
4057
4058static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4059 u32 msr, int type)
4060{
4061 int f = sizeof(unsigned long);
4062
4063 if (!cpu_has_vmx_msr_bitmap())
4064 return;
4065
4066 /*
4067 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4068 * have the write-low and read-high bitmap offsets the wrong way round.
4069 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4070 */
4071 if (msr <= 0x1fff) {
4072 if (type & MSR_TYPE_R)
4073 /* read-low */
4074 __set_bit(msr, msr_bitmap + 0x000 / f);
4075
4076 if (type & MSR_TYPE_W)
4077 /* write-low */
4078 __set_bit(msr, msr_bitmap + 0x800 / f);
4079
4080 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4081 msr &= 0x1fff;
4082 if (type & MSR_TYPE_R)
4083 /* read-high */
4084 __set_bit(msr, msr_bitmap + 0x400 / f);
4085
4086 if (type & MSR_TYPE_W)
4087 /* write-high */
4088 __set_bit(msr, msr_bitmap + 0xc00 / f);
4089
25c5f225 4090 }
25c5f225
SY		 4091}
4092
5897297b
AK		 4093static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4094{
4095 if (!longmode_only)
8d14695f
YZ		 4096 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4097 msr, MSR_TYPE_R | MSR_TYPE_W);
4098 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4099 msr, MSR_TYPE_R | MSR_TYPE_W);
4100}
4101
4102static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4103{
4104 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4105 msr, MSR_TYPE_R);
4106 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4107 msr, MSR_TYPE_R);
4108}
4109
4110static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4111{
4112 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4113 msr, MSR_TYPE_R);
4114 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4115 msr, MSR_TYPE_R);
4116}
4117
4118static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4119{
4120 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4121 msr, MSR_TYPE_W);
4122 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4123 msr, MSR_TYPE_W);
5897297b
AK		 4124}
4125
01e439be
YZ		 4126static int vmx_vm_has_apicv(struct kvm *kvm)
4127{
4128 return enable_apicv && irqchip_in_kernel(kvm);
4129}
4130
a20ed54d
YZ		 4131/*
4132 * Send interrupt to vcpu via posted interrupt way.
4133 * 1. If target vcpu is running(non-root mode), send posted interrupt
4134 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4135 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4136 * interrupt from PIR in next vmentry.
4137 */
4138static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4139{
4140 struct vcpu_vmx *vmx = to_vmx(vcpu);
4141 int r;
4142
4143 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4144 return;
4145
4146 r = pi_test_and_set_on(&vmx->pi_desc);
4147 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4148#ifdef CONFIG_SMP
a20ed54d
YZ		 4149 if (!r && (vcpu->mode == IN_GUEST_MODE))
4150 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4151 POSTED_INTR_VECTOR);
4152 else
6ffbbbba 4153#endif
a20ed54d
YZ		 4154 kvm_vcpu_kick(vcpu);
4155}
4156
4157static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4158{
4159 struct vcpu_vmx *vmx = to_vmx(vcpu);
4160
4161 if (!pi_test_and_clear_on(&vmx->pi_desc))
4162 return;
4163
4164 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4165}
4166
4167static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4168{
4169 return;
4170}
4171
a3a8ff8e
NHE		 4172/*
4173 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4174 * will not change in the lifetime of the guest.
4175 * Note that host-state that does change is set elsewhere. E.g., host-state
4176 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4177 */
a547c6db 4178static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4179{
4180 u32 low32, high32;
4181 unsigned long tmpl;
4182 struct desc_ptr dt;
4183
b1a74bf8 4184 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4185 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4186 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4187
4188 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4189#ifdef CONFIG_X86_64
4190 /*
4191 * Load null selectors, so we can avoid reloading them in
4192 * __vmx_load_host_state(), in case userspace uses the null selectors
4193 * too (the expected case).
4194 */
4195 vmcs_write16(HOST_DS_SELECTOR, 0);
4196 vmcs_write16(HOST_ES_SELECTOR, 0);
4197#else
a3a8ff8e
NHE		 4198 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4199 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4200#endif
a3a8ff8e
NHE		 4201 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4202 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4203
4204 native_store_idt(&dt);
4205 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4206 vmx->host_idt_base = dt.address;
a3a8ff8e 4207
83287ea4 4208 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4209
4210 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4211 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4212 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4213 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4214
4215 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4216 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4217 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4218 }
4219}
4220
bf8179a0
NHE		 4221static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4222{
4223 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4224 if (enable_ept)
4225 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4226 if (is_guest_mode(&vmx->vcpu))
4227 vmx->vcpu.arch.cr4_guest_owned_bits &=
4228 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4229 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4230}
4231
01e439be
YZ		 4232static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4233{
4234 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4235
4236 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4237 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4238 return pin_based_exec_ctrl;
4239}
4240
bf8179a0
NHE		 4241static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4242{
4243 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4244 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4245 exec_control &= ~CPU_BASED_TPR_SHADOW;
4246#ifdef CONFIG_X86_64
4247 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4248 CPU_BASED_CR8_LOAD_EXITING;
4249#endif
4250 }
4251 if (!enable_ept)
4252 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4253 CPU_BASED_CR3_LOAD_EXITING |
4254 CPU_BASED_INVLPG_EXITING;
4255 return exec_control;
4256}
4257
4258static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4259{
4260 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4261 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4262 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4263 if (vmx->vpid == 0)
4264 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4265 if (!enable_ept) {
4266 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4267 enable_unrestricted_guest = 0;
ad756a16
MJ		 4268 /* Enable INVPCID for non-ept guests may cause performance regression. */
4269 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4270 }
4271 if (!enable_unrestricted_guest)
4272 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4273 if (!ple_gap)
4274 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4275 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4276 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4277 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4278 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4279 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4280 (handle_vmptrld).
4281 We can NOT enable shadow_vmcs here because we don't have yet
4282 a current VMCS12
4283 */
4284 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4285 return exec_control;
4286}
4287
ce88decf
XG		 4288static void ept_set_mmio_spte_mask(void)
4289{
4290 /*
4291 * EPT Misconfigurations can be generated if the value of bits 2:0
4292 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4293 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4294 * spte.
4295 */
885032b9 4296 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4297}
4298
6aa8b732
AK		 4299/*
4300 * Sets up the vmcs for emulated real mode.
4301 */
8b9cf98c 4302static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4303{
2e4ce7f5 4304#ifdef CONFIG_X86_64
6aa8b732 4305 unsigned long a;
2e4ce7f5 4306#endif
6aa8b732 4307 int i;
6aa8b732 4308
6aa8b732 4309 /* I/O */
3e7c73e9
AK		 4310 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4311 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4312
4607c2d7
AG		 4313 if (enable_shadow_vmcs) {
4314 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4315 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4316 }
25c5f225 4317 if (cpu_has_vmx_msr_bitmap())
5897297b 4318 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4319
6aa8b732
AK		 4320 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4321
6aa8b732 4322 /* Control */
01e439be 4323 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4324
bf8179a0 4325 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4326
83ff3b9d 4327 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4328 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4329 vmx_secondary_exec_control(vmx));
83ff3b9d 4330 }
f78e0e2e 4331
01e439be 4332 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4333 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4334 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4335 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4336 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4337
4338 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4339
4340 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4341 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4342 }
4343
4b8d54f9
ZE		 4344 if (ple_gap) {
4345 vmcs_write32(PLE_GAP, ple_gap);
4346 vmcs_write32(PLE_WINDOW, ple_window);
4347 }
4348
c3707958
XG		 4349 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4350 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4351 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4352
9581d442
AK		 4353 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4354 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4355 vmx_set_constant_host_state(vmx);
05b3e0c2 4356#ifdef CONFIG_X86_64
6aa8b732
AK		 4357 rdmsrl(MSR_FS_BASE, a);
4358 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4359 rdmsrl(MSR_GS_BASE, a);
4360 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4361#else
4362 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4363 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4364#endif
4365
2cc51560
ED		 4366 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4367 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4368 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4369 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4370 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4371
468d472f 4372 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4373 u32 msr_low, msr_high;
4374 u64 host_pat;
468d472f
SY		 4375 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4376 host_pat = msr_low | ((u64) msr_high << 32);
4377 /* Write the default value follow host pat */
4378 vmcs_write64(GUEST_IA32_PAT, host_pat);
4379 /* Keep arch.pat sync with GUEST_IA32_PAT */
4380 vmx->vcpu.arch.pat = host_pat;
4381 }
4382
6aa8b732
AK		 4383 for (i = 0; i < NR_VMX_MSR; ++i) {
4384 u32 index = vmx_msr_index[i];
4385 u32 data_low, data_high;
a2fa3e9f 4386 int j = vmx->nmsrs;
6aa8b732
AK		 4387
4388 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4389 continue;
432bd6cb
AK		 4390 if (wrmsr_safe(index, data_low, data_high) < 0)
4391 continue;
26bb0981
AK		 4392 vmx->guest_msrs[j].index = i;
4393 vmx->guest_msrs[j].data = 0;
d5696725 4394 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4395 ++vmx->nmsrs;
6aa8b732 4396 }
6aa8b732 4397
2961e876
GN		 4398
4399 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4400
4401 /* 22.2.1, 20.8.1 */
2961e876 4402 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4403
e00c8cf2 4404 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4405 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4406
4407 return 0;
4408}
4409
57f252f2 4410static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4411{
4412 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4413 struct msr_data apic_base_msr;
e00c8cf2 4414
7ffd92c5 4415 vmx->rmode.vm86_active = 0;
e00c8cf2 4416
3b86cd99
JK		 4417 vmx->soft_vnmi_blocked = 0;
4418
ad312c7c 4419 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4420 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4421 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4422 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4423 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4424 apic_base_msr.host_initiated = true;
4425 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4426
2fb92db1
AK		 4427 vmx_segment_cache_clear(vmx);
4428
5706be0d 4429 seg_setup(VCPU_SREG_CS);
66450a21 4430 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4431 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4432
4433 seg_setup(VCPU_SREG_DS);
4434 seg_setup(VCPU_SREG_ES);
4435 seg_setup(VCPU_SREG_FS);
4436 seg_setup(VCPU_SREG_GS);
4437 seg_setup(VCPU_SREG_SS);
4438
4439 vmcs_write16(GUEST_TR_SELECTOR, 0);
4440 vmcs_writel(GUEST_TR_BASE, 0);
4441 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4442 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4443
4444 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4445 vmcs_writel(GUEST_LDTR_BASE, 0);
4446 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4447 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4448
4449 vmcs_write32(GUEST_SYSENTER_CS, 0);
4450 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4451 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4452
4453 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4454 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4455
e00c8cf2
AK		 4456 vmcs_writel(GUEST_GDTR_BASE, 0);
4457 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4458
4459 vmcs_writel(GUEST_IDTR_BASE, 0);
4460 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4461
443381a8 4462 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4463 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4464 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4465
e00c8cf2
AK		 4466 /* Special registers */
4467 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4468
4469 setup_msrs(vmx);
4470
6aa8b732
AK		 4471 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4472
f78e0e2e
SY		 4473 if (cpu_has_vmx_tpr_shadow()) {
4474 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4475 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4476 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4477 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4478 vmcs_write32(TPR_THRESHOLD, 0);
4479 }
4480
4481 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4482 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4483 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4484
01e439be
YZ		 4485 if (vmx_vm_has_apicv(vcpu->kvm))
4486 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4487
2384d2b3
SY		 4488 if (vmx->vpid != 0)
4489 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4490
fa40052c 4491 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4492 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4493 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4494 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4495 vmx_fpu_activate(&vmx->vcpu);
4496 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4497
b9d762fa 4498 vpid_sync_context(vmx);
6aa8b732
AK		 4499}
4500
b6f1250e
NHE		 4501/*
4502 * In nested virtualization, check if L1 asked to exit on external interrupts.
4503 * For most existing hypervisors, this will always return true.
4504 */
4505static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4506{
4507 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4508 PIN_BASED_EXT_INTR_MASK;
4509}
4510
ea8ceb83
JK		 4511static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4512{
4513 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4514 PIN_BASED_NMI_EXITING;
4515}
4516
c9a7953f 4517static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4518{
4519 u32 cpu_based_vm_exec_control;
730dca42 4520
3b86cd99
JK		 4521 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4522 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4523 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4524}
4525
c9a7953f 4526static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4527{
4528 u32 cpu_based_vm_exec_control;
4529
c9a7953f
JK		 4530 if (!cpu_has_virtual_nmis() ||
4531 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4532 enable_irq_window(vcpu);
4533 return;
4534 }
3b86cd99
JK		 4535
4536 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4537 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4538 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4539}
4540
66fd3f7f 4541static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4542{
9c8cba37 4543 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4544 uint32_t intr;
4545 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4546
229456fc 4547 trace_kvm_inj_virq(irq);
2714d1d3 4548
fa89a817 4549 ++vcpu->stat.irq_injections;
7ffd92c5 4550 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4551 int inc_eip = 0;
4552 if (vcpu->arch.interrupt.soft)
4553 inc_eip = vcpu->arch.event_exit_inst_len;
4554 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4555 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4556 return;
4557 }
66fd3f7f
GN		 4558 intr = irq | INTR_INFO_VALID_MASK;
4559 if (vcpu->arch.interrupt.soft) {
4560 intr |= INTR_TYPE_SOFT_INTR;
4561 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4562 vmx->vcpu.arch.event_exit_inst_len);
4563 } else
4564 intr |= INTR_TYPE_EXT_INTR;
4565 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4566}
4567
f08864b4
SY		 4568static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4569{
66a5a347
JK		 4570 struct vcpu_vmx *vmx = to_vmx(vcpu);
4571
0b6ac343
NHE		 4572 if (is_guest_mode(vcpu))
4573 return;
4574
3b86cd99
JK		 4575 if (!cpu_has_virtual_nmis()) {
4576 /*
4577 * Tracking the NMI-blocked state in software is built upon
4578 * finding the next open IRQ window. This, in turn, depends on
4579 * well-behaving guests: They have to keep IRQs disabled at
4580 * least as long as the NMI handler runs. Otherwise we may
4581 * cause NMI nesting, maybe breaking the guest. But as this is
4582 * highly unlikely, we can live with the residual risk.
4583 */
4584 vmx->soft_vnmi_blocked = 1;
4585 vmx->vnmi_blocked_time = 0;
4586 }
4587
487b391d 4588 ++vcpu->stat.nmi_injections;
9d58b931 4589 vmx->nmi_known_unmasked = false;
7ffd92c5 4590 if (vmx->rmode.vm86_active) {
71f9833b 4591 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4592 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4593 return;
4594 }
f08864b4
SY		 4595 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4596 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4597}
4598
3cfc3092
JK		 4599static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4600{
4601 if (!cpu_has_virtual_nmis())
4602 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4603 if (to_vmx(vcpu)->nmi_known_unmasked)
4604 return false;
c332c83a 4605 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4606}
4607
4608static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4609{
4610 struct vcpu_vmx *vmx = to_vmx(vcpu);
4611
4612 if (!cpu_has_virtual_nmis()) {
4613 if (vmx->soft_vnmi_blocked != masked) {
4614 vmx->soft_vnmi_blocked = masked;
4615 vmx->vnmi_blocked_time = 0;
4616 }
4617 } else {
9d58b931 4618 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4619 if (masked)
4620 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4621 GUEST_INTR_STATE_NMI);
4622 else
4623 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4624 GUEST_INTR_STATE_NMI);
4625 }
4626}
4627
2505dc9f
JK		 4628static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4629{
b6b8a145
JK		 4630 if (to_vmx(vcpu)->nested.nested_run_pending)
4631 return 0;
ea8ceb83 4632
2505dc9f
JK		 4633 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4634 return 0;
4635
4636 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4637 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4638 | GUEST_INTR_STATE_NMI));
4639}
4640
78646121
GN		 4641static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4642{
b6b8a145
JK		 4643 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4644 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4645 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4646 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4647}
4648
cbc94022
IE		 4649static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4650{
4651 int ret;
4652 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4653 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4654 .guest_phys_addr = addr,
4655 .memory_size = PAGE_SIZE * 3,
4656 .flags = 0,
4657 };
4658
47ae31e2 4659 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4660 if (ret)
4661 return ret;
bfc6d222 4662 kvm->arch.tss_addr = addr;
93ea5388
GN		 4663 if (!init_rmode_tss(kvm))
4664 return -ENOMEM;
4665
cbc94022
IE		 4666 return 0;
4667}
4668
0ca1b4f4 4669static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4670{
77ab6db0 4671 switch (vec) {
77ab6db0 4672 case BP_VECTOR:
c573cd22
JK		 4673 /*
4674 * Update instruction length as we may reinject the exception
4675 * from user space while in guest debugging mode.
4676 */
4677 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4678 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4679 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4680 return false;
4681 /* fall through */
4682 case DB_VECTOR:
4683 if (vcpu->guest_debug &
4684 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4685 return false;
d0bfb940
JK		 4686 /* fall through */
4687 case DE_VECTOR:
77ab6db0
JK		 4688 case OF_VECTOR:
4689 case BR_VECTOR:
4690 case UD_VECTOR:
4691 case DF_VECTOR:
4692 case SS_VECTOR:
4693 case GP_VECTOR:
4694 case MF_VECTOR:
0ca1b4f4
GN		 4695 return true;
4696 break;
77ab6db0 4697 }
0ca1b4f4
GN		 4698 return false;
4699}
4700
4701static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4702 int vec, u32 err_code)
4703{
4704 /*
4705 * Instruction with address size override prefix opcode 0x67
4706 * Cause the #SS fault with 0 error code in VM86 mode.
4707 */
4708 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4709 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4710 if (vcpu->arch.halt_request) {
4711 vcpu->arch.halt_request = 0;
4712 return kvm_emulate_halt(vcpu);
4713 }
4714 return 1;
4715 }
4716 return 0;
4717 }
4718
4719 /*
4720 * Forward all other exceptions that are valid in real mode.
4721 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4722 * the required debugging infrastructure rework.
4723 */
4724 kvm_queue_exception(vcpu, vec);
4725 return 1;
6aa8b732
AK		 4726}
4727
a0861c02
AK		 4728/*
4729 * Trigger machine check on the host. We assume all the MSRs are already set up
4730 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4731 * We pass a fake environment to the machine check handler because we want
4732 * the guest to be always treated like user space, no matter what context
4733 * it used internally.
4734 */
4735static void kvm_machine_check(void)
4736{
4737#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4738 struct pt_regs regs = {
4739 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4740 .flags = X86_EFLAGS_IF,
4741 };
4742
4743 do_machine_check(&regs, 0);
4744#endif
4745}
4746
851ba692 4747static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4748{
4749 /* already handled by vcpu_run */
4750 return 1;
4751}
4752
851ba692 4753static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4754{
1155f76a 4755 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4756 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4757 u32 intr_info, ex_no, error_code;
42dbaa5a 4758 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4759 u32 vect_info;
4760 enum emulation_result er;
4761
1155f76a 4762 vect_info = vmx->idt_vectoring_info;
88786475 4763 intr_info = vmx->exit_intr_info;
6aa8b732 4764
a0861c02 4765 if (is_machine_check(intr_info))
851ba692 4766 return handle_machine_check(vcpu);
a0861c02 4767
e4a41889 4768 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4769 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4770
4771 if (is_no_device(intr_info)) {
5fd86fcf 4772 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4773 return 1;
4774 }
4775
7aa81cc0 4776 if (is_invalid_opcode(intr_info)) {
51d8b661 4777 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4778 if (er != EMULATE_DONE)
7ee5d940 4779 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4780 return 1;
4781 }
4782
6aa8b732 4783 error_code = 0;
2e11384c 4784 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4785 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4786
4787 /*
4788 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4789 * MMIO, it is better to report an internal error.
4790 * See the comments in vmx_handle_exit.
4791 */
4792 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4793 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4794 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4795 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4796 vcpu->run->internal.ndata = 2;
4797 vcpu->run->internal.data[0] = vect_info;
4798 vcpu->run->internal.data[1] = intr_info;
4799 return 0;
4800 }
4801
6aa8b732 4802 if (is_page_fault(intr_info)) {
1439442c 4803 /* EPT won't cause page fault directly */
cf3ace79 4804 BUG_ON(enable_ept);
6aa8b732 4805 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4806 trace_kvm_page_fault(cr2, error_code);
4807
3298b75c 4808 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4809 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4810 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4811 }
4812
d0bfb940 4813 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4814
4815 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4816 return handle_rmode_exception(vcpu, ex_no, error_code);
4817
42dbaa5a
JK		 4818 switch (ex_no) {
4819 case DB_VECTOR:
4820 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4821 if (!(vcpu->guest_debug &
4822 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4823 vcpu->arch.dr6 &= ~15;
4824 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4825 kvm_queue_exception(vcpu, DB_VECTOR);
4826 return 1;
4827 }
4828 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4829 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4830 /* fall through */
4831 case BP_VECTOR:
c573cd22
JK		 4832 /*
4833 * Update instruction length as we may reinject #BP from
4834 * user space while in guest debugging mode. Reading it for
4835 * #DB as well causes no harm, it is not used in that case.
4836 */
4837 vmx->vcpu.arch.event_exit_inst_len =
4838 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4839 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4840 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4841 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4842 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4843 break;
4844 default:
d0bfb940
JK		 4845 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4846 kvm_run->ex.exception = ex_no;
4847 kvm_run->ex.error_code = error_code;
42dbaa5a 4848 break;
6aa8b732 4849 }
6aa8b732
AK		 4850 return 0;
4851}
4852
851ba692 4853static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4854{
1165f5fe 4855 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4856 return 1;
4857}
4858
851ba692 4859static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4860{
851ba692 4861 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4862 return 0;
4863}
6aa8b732 4864
851ba692 4865static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4866{
bfdaab09 4867 unsigned long exit_qualification;
34c33d16 4868 int size, in, string;
039576c0 4869 unsigned port;
6aa8b732 4870
bfdaab09 4871 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4872 string = (exit_qualification & 16) != 0;
cf8f70bf 4873 in = (exit_qualification & 8) != 0;
e70669ab 4874
cf8f70bf 4875 ++vcpu->stat.io_exits;
e70669ab 4876
cf8f70bf 4877 if (string || in)
51d8b661 4878 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4879
cf8f70bf
GN		 4880 port = exit_qualification >> 16;
4881 size = (exit_qualification & 7) + 1;
e93f36bc 4882 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4883
4884 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4885}
4886
102d8325
IM		 4887static void
4888vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4889{
4890 /*
4891 * Patch in the VMCALL instruction:
4892 */
4893 hypercall[0] = 0x0f;
4894 hypercall[1] = 0x01;
4895 hypercall[2] = 0xc1;
102d8325
IM		 4896}
4897
92fbc7b1
JK		 4898static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4899{
4900 unsigned long always_on = VMXON_CR0_ALWAYSON;
4901
4902 if (nested_vmx_secondary_ctls_high &
4903 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4904 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4905 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4906 return (val & always_on) == always_on;
4907}
4908
0fa06071 4909/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4910static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4911{
eeadf9e7 4912 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4913 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4914 unsigned long orig_val = val;
4915
eeadf9e7
NHE		 4916 /*
4917 * We get here when L2 changed cr0 in a way that did not change
4918 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4919 * but did change L0 shadowed bits. So we first calculate the
4920 * effective cr0 value that L1 would like to write into the
4921 * hardware. It consists of the L2-owned bits from the new
4922 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4923 */
1a0d74e6
JK		 4924 val = (val & ~vmcs12->cr0_guest_host_mask) |
4925 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4926
92fbc7b1 4927 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4928 return 1;
1a0d74e6
JK		 4929
4930 if (kvm_set_cr0(vcpu, val))
4931 return 1;
4932 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4933 return 0;
1a0d74e6
JK		 4934 } else {
4935 if (to_vmx(vcpu)->nested.vmxon &&
4936 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4937 return 1;
eeadf9e7 4938 return kvm_set_cr0(vcpu, val);
1a0d74e6 4939 }
eeadf9e7
NHE		 4940}
4941
4942static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4943{
4944 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4945 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4946 unsigned long orig_val = val;
4947
4948 /* analogously to handle_set_cr0 */
4949 val = (val & ~vmcs12->cr4_guest_host_mask) |
4950 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4951 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4952 return 1;
1a0d74e6 4953 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4954 return 0;
4955 } else
4956 return kvm_set_cr4(vcpu, val);
4957}
4958
4959/* called to set cr0 as approriate for clts instruction exit. */
4960static void handle_clts(struct kvm_vcpu *vcpu)
4961{
4962 if (is_guest_mode(vcpu)) {
4963 /*
4964 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4965 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4966 * just pretend it's off (also in arch.cr0 for fpu_activate).
4967 */
4968 vmcs_writel(CR0_READ_SHADOW,
4969 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4970 vcpu->arch.cr0 &= ~X86_CR0_TS;
4971 } else
4972 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4973}
4974
851ba692 4975static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4976{
229456fc 4977 unsigned long exit_qualification, val;
6aa8b732
AK		 4978 int cr;
4979 int reg;
49a9b07e 4980 int err;
6aa8b732 4981
bfdaab09 4982 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4983 cr = exit_qualification & 15;
4984 reg = (exit_qualification >> 8) & 15;
4985 switch ((exit_qualification >> 4) & 3) {
4986 case 0: /* mov to cr */
229456fc
MT		 4987 val = kvm_register_read(vcpu, reg);
4988 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4989 switch (cr) {
4990 case 0:
eeadf9e7 4991 err = handle_set_cr0(vcpu, val);
db8fcefa 4992 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4993 return 1;
4994 case 3:
2390218b 4995 err = kvm_set_cr3(vcpu, val);
db8fcefa 4996 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4997 return 1;
4998 case 4:
eeadf9e7 4999 err = handle_set_cr4(vcpu, val);
db8fcefa 5000 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5001 return 1;
0a5fff19
GN		 5002 case 8: {
5003 u8 cr8_prev = kvm_get_cr8(vcpu);
5004 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5005 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5006 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5007 if (irqchip_in_kernel(vcpu->kvm))
5008 return 1;
5009 if (cr8_prev <= cr8)
5010 return 1;
851ba692 5011 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5012 return 0;
5013 }
4b8073e4 5014 }
6aa8b732 5015 break;
25c4c276 5016 case 2: /* clts */
eeadf9e7 5017 handle_clts(vcpu);
4d4ec087 5018 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5019 skip_emulated_instruction(vcpu);
6b52d186 5020 vmx_fpu_activate(vcpu);
25c4c276 5021 return 1;
6aa8b732
AK		 5022 case 1: /*mov from cr*/
5023 switch (cr) {
5024 case 3:
9f8fe504
AK		 5025 val = kvm_read_cr3(vcpu);
5026 kvm_register_write(vcpu, reg, val);
5027 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5028 skip_emulated_instruction(vcpu);
5029 return 1;
5030 case 8:
229456fc
MT		 5031 val = kvm_get_cr8(vcpu);
5032 kvm_register_write(vcpu, reg, val);
5033 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5034 skip_emulated_instruction(vcpu);
5035 return 1;
5036 }
5037 break;
5038 case 3: /* lmsw */
a1f83a74 5039 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5040 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5041 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5042
5043 skip_emulated_instruction(vcpu);
5044 return 1;
5045 default:
5046 break;
5047 }
851ba692 5048 vcpu->run->exit_reason = 0;
a737f256 5049 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5050 (int)(exit_qualification >> 4) & 3, cr);
5051 return 0;
5052}
5053
851ba692 5054static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5055{
bfdaab09 5056 unsigned long exit_qualification;
6aa8b732
AK		 5057 int dr, reg;
5058
f2483415 5059 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5060 if (!kvm_require_cpl(vcpu, 0))
5061 return 1;
42dbaa5a
JK		 5062 dr = vmcs_readl(GUEST_DR7);
5063 if (dr & DR7_GD) {
5064 /*
5065 * As the vm-exit takes precedence over the debug trap, we
5066 * need to emulate the latter, either for the host or the
5067 * guest debugging itself.
5068 */
5069 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5070 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5071 vcpu->run->debug.arch.dr7 = dr;
5072 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5073 vmcs_readl(GUEST_CS_BASE) +
5074 vmcs_readl(GUEST_RIP);
851ba692
AK		 5075 vcpu->run->debug.arch.exception = DB_VECTOR;
5076 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5077 return 0;
5078 } else {
5079 vcpu->arch.dr7 &= ~DR7_GD;
5080 vcpu->arch.dr6 |= DR6_BD;
5081 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5082 kvm_queue_exception(vcpu, DB_VECTOR);
5083 return 1;
5084 }
5085 }
5086
bfdaab09 5087 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5088 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5089 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5090 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5091 unsigned long val;
4c4d563b
JK		 5092
5093 if (kvm_get_dr(vcpu, dr, &val))
5094 return 1;
5095 kvm_register_write(vcpu, reg, val);
020df079 5096 } else
4c4d563b
JK		 5097 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5098 return 1;
5099
6aa8b732
AK		 5100 skip_emulated_instruction(vcpu);
5101 return 1;
5102}
5103
73aaf249
JK		 5104static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5105{
5106 return vcpu->arch.dr6;
5107}
5108
5109static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5110{
5111}
5112
020df079
GN		 5113static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5114{
5115 vmcs_writel(GUEST_DR7, val);
5116}
5117
851ba692 5118static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5119{
06465c5a
AK		 5120 kvm_emulate_cpuid(vcpu);
5121 return 1;
6aa8b732
AK		 5122}
5123
851ba692 5124static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5125{
ad312c7c 5126 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5127 u64 data;
5128
5129 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5130 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5131 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5132 return 1;
5133 }
5134
229456fc 5135 trace_kvm_msr_read(ecx, data);
2714d1d3 5136
6aa8b732 5137 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5138 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5139 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5140 skip_emulated_instruction(vcpu);
5141 return 1;
5142}
5143
851ba692 5144static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5145{
8fe8ab46 5146 struct msr_data msr;
ad312c7c
ZX		 5147 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5148 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5149 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5150
8fe8ab46
WA		 5151 msr.data = data;
5152 msr.index = ecx;
5153 msr.host_initiated = false;
5154 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5155 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5156 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5157 return 1;
5158 }
5159
59200273 5160 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5161 skip_emulated_instruction(vcpu);
5162 return 1;
5163}
5164
851ba692 5165static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5166{
3842d135 5167 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5168 return 1;
5169}
5170
851ba692 5171static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5172{
85f455f7
ED		 5173 u32 cpu_based_vm_exec_control;
5174
5175 /* clear pending irq */
5176 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5177 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5178 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5179
3842d135
AK		 5180 kvm_make_request(KVM_REQ_EVENT, vcpu);
5181
a26bf12a 5182 ++vcpu->stat.irq_window_exits;
2714d1d3 5183
c1150d8c
DL		 5184 /*
5185 * If the user space waits to inject interrupts, exit as soon as
5186 * possible
5187 */
8061823a 5188 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5189 vcpu->run->request_interrupt_window &&
8061823a 5190 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5191 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5192 return 0;
5193 }
6aa8b732
AK		 5194 return 1;
5195}
5196
851ba692 5197static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5198{
5199 skip_emulated_instruction(vcpu);
d3bef15f 5200 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5201}
5202
851ba692 5203static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5204{
510043da 5205 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5206 kvm_emulate_hypercall(vcpu);
5207 return 1;
c21415e8
IM		 5208}
5209
ec25d5e6
GN		 5210static int handle_invd(struct kvm_vcpu *vcpu)
5211{
51d8b661 5212 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5213}
5214
851ba692 5215static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5216{
f9c617f6 5217 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5218
5219 kvm_mmu_invlpg(vcpu, exit_qualification);
5220 skip_emulated_instruction(vcpu);
5221 return 1;
5222}
5223
fee84b07
AK		 5224static int handle_rdpmc(struct kvm_vcpu *vcpu)
5225{
5226 int err;
5227
5228 err = kvm_rdpmc(vcpu);
5229 kvm_complete_insn_gp(vcpu, err);
5230
5231 return 1;
5232}
5233
851ba692 5234static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5235{
5236 skip_emulated_instruction(vcpu);
f5f48ee1 5237 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5238 return 1;
5239}
5240
2acf923e
DC		 5241static int handle_xsetbv(struct kvm_vcpu *vcpu)
5242{
5243 u64 new_bv = kvm_read_edx_eax(vcpu);
5244 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5245
5246 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5247 skip_emulated_instruction(vcpu);
5248 return 1;
5249}
5250
851ba692 5251static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5252{
58fbbf26
KT		 5253 if (likely(fasteoi)) {
5254 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5255 int access_type, offset;
5256
5257 access_type = exit_qualification & APIC_ACCESS_TYPE;
5258 offset = exit_qualification & APIC_ACCESS_OFFSET;
5259 /*
5260 * Sane guest uses MOV to write EOI, with written value
5261 * not cared. So make a short-circuit here by avoiding
5262 * heavy instruction emulation.
5263 */
5264 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5265 (offset == APIC_EOI)) {
5266 kvm_lapic_set_eoi(vcpu);
5267 skip_emulated_instruction(vcpu);
5268 return 1;
5269 }
5270 }
51d8b661 5271 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5272}
5273
c7c9c56c
YZ		 5274static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5275{
5276 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5277 int vector = exit_qualification & 0xff;
5278
5279 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5280 kvm_apic_set_eoi_accelerated(vcpu, vector);
5281 return 1;
5282}
5283
83d4c286
YZ		 5284static int handle_apic_write(struct kvm_vcpu *vcpu)
5285{
5286 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5287 u32 offset = exit_qualification & 0xfff;
5288
5289 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5290 kvm_apic_write_nodecode(vcpu, offset);
5291 return 1;
5292}
5293
851ba692 5294static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5295{
60637aac 5296 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5297 unsigned long exit_qualification;
e269fb21
JK		 5298 bool has_error_code = false;
5299 u32 error_code = 0;
37817f29 5300 u16 tss_selector;
7f3d35fd 5301 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5302
5303 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5304 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5305 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5306
5307 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5308
5309 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5310 if (reason == TASK_SWITCH_GATE && idt_v) {
5311 switch (type) {
5312 case INTR_TYPE_NMI_INTR:
5313 vcpu->arch.nmi_injected = false;
654f06fc 5314 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5315 break;
5316 case INTR_TYPE_EXT_INTR:
66fd3f7f 5317 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5318 kvm_clear_interrupt_queue(vcpu);
5319 break;
5320 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5321 if (vmx->idt_vectoring_info &
5322 VECTORING_INFO_DELIVER_CODE_MASK) {
5323 has_error_code = true;
5324 error_code =
5325 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5326 }
5327 /* fall through */
64a7ec06
GN		 5328 case INTR_TYPE_SOFT_EXCEPTION:
5329 kvm_clear_exception_queue(vcpu);
5330 break;
5331 default:
5332 break;
5333 }
60637aac 5334 }
37817f29
IE		 5335 tss_selector = exit_qualification;
5336
64a7ec06
GN		 5337 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5338 type != INTR_TYPE_EXT_INTR &&
5339 type != INTR_TYPE_NMI_INTR))
5340 skip_emulated_instruction(vcpu);
5341
7f3d35fd
KW		 5342 if (kvm_task_switch(vcpu, tss_selector,
5343 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5344 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5345 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5346 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5347 vcpu->run->internal.ndata = 0;
42dbaa5a 5348 return 0;
acb54517 5349 }
42dbaa5a
JK		 5350
5351 /* clear all local breakpoint enable flags */
5352 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5353
5354 /*
5355 * TODO: What about debug traps on tss switch?
5356 * Are we supposed to inject them and update dr6?
5357 */
5358
5359 return 1;
37817f29
IE		 5360}
5361
851ba692 5362static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5363{
f9c617f6 5364 unsigned long exit_qualification;
1439442c 5365 gpa_t gpa;
4f5982a5 5366 u32 error_code;
1439442c 5367 int gla_validity;
1439442c 5368
f9c617f6 5369 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5370
1439442c
SY		 5371 gla_validity = (exit_qualification >> 7) & 0x3;
5372 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5373 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5374 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5375 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5376 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5377 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5378 (long unsigned int)exit_qualification);
851ba692
AK		 5379 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5380 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5381 return 0;
1439442c
SY		 5382 }
5383
0be9c7a8
GN		 5384 /*
5385 * EPT violation happened while executing iret from NMI,
5386 * "blocked by NMI" bit has to be set before next VM entry.
5387 * There are errata that may cause this bit to not be set:
5388 * AAK134, BY25.
5389 */
bcd1c294
GN		 5390 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5391 cpu_has_virtual_nmis() &&
5392 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5393 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5394
1439442c 5395 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5396 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5397
5398 /* It is a write fault? */
5399 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5400 /* It is a fetch fault? */
5401 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5402 /* ept page table is present? */
5403 error_code |= (exit_qualification >> 3) & 0x1;
5404
25d92081
YZ		 5405 vcpu->arch.exit_qualification = exit_qualification;
5406
4f5982a5 5407 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5408}
5409
68f89400
MT		 5410static u64 ept_rsvd_mask(u64 spte, int level)
5411{
5412 int i;
5413 u64 mask = 0;
5414
5415 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5416 mask |= (1ULL << i);
5417
5418 if (level > 2)
5419 /* bits 7:3 reserved */
5420 mask |= 0xf8;
5421 else if (level == 2) {
5422 if (spte & (1ULL << 7))
5423 /* 2MB ref, bits 20:12 reserved */
5424 mask |= 0x1ff000;
5425 else
5426 /* bits 6:3 reserved */
5427 mask |= 0x78;
5428 }
5429
5430 return mask;
5431}
5432
5433static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5434 int level)
5435{
5436 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5437
5438 /* 010b (write-only) */
5439 WARN_ON((spte & 0x7) == 0x2);
5440
5441 /* 110b (write/execute) */
5442 WARN_ON((spte & 0x7) == 0x6);
5443
5444 /* 100b (execute-only) and value not supported by logical processor */
5445 if (!cpu_has_vmx_ept_execute_only())
5446 WARN_ON((spte & 0x7) == 0x4);
5447
5448 /* not 000b */
5449 if ((spte & 0x7)) {
5450 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5451
5452 if (rsvd_bits != 0) {
5453 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5454 __func__, rsvd_bits);
5455 WARN_ON(1);
5456 }
5457
5458 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5459 u64 ept_mem_type = (spte & 0x38) >> 3;
5460
5461 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5462 ept_mem_type == 7) {
5463 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5464 __func__, ept_mem_type);
5465 WARN_ON(1);
5466 }
5467 }
5468 }
5469}
5470
851ba692 5471static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5472{
5473 u64 sptes[4];
ce88decf 5474 int nr_sptes, i, ret;
68f89400
MT		 5475 gpa_t gpa;
5476
5477 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5478
ce88decf 5479 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5480 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5481 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5482 EMULATE_DONE;
f8f55942
XG		 5483
5484 if (unlikely(ret == RET_MMIO_PF_INVALID))
5485 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5486
b37fbea6 5487 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5488 return 1;
5489
5490 /* It is the real ept misconfig */
68f89400
MT		 5491 printk(KERN_ERR "EPT: Misconfiguration.\n");
5492 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5493
5494 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5495
5496 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5497 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5498
851ba692
AK		 5499 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5500 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5501
5502 return 0;
5503}
5504
851ba692 5505static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5506{
5507 u32 cpu_based_vm_exec_control;
5508
5509 /* clear pending NMI */
5510 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5511 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5512 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5513 ++vcpu->stat.nmi_window_exits;
3842d135 5514 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5515
5516 return 1;
5517}
5518
80ced186 5519static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5520{
8b3079a5
AK		 5521 struct vcpu_vmx *vmx = to_vmx(vcpu);
5522 enum emulation_result err = EMULATE_DONE;
80ced186 5523 int ret = 1;
49e9d557
AK		 5524 u32 cpu_exec_ctrl;
5525 bool intr_window_requested;
b8405c18 5526 unsigned count = 130;
49e9d557
AK		 5527
5528 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5529 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5530
b8405c18 5531 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5532 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5533 return handle_interrupt_window(&vmx->vcpu);
5534
de87dcdd
AK		 5535 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5536 return 1;
5537
991eebf9 5538 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5539
ac0a48c3 5540 if (err == EMULATE_USER_EXIT) {
94452b9e 5541 ++vcpu->stat.mmio_exits;
80ced186
MG		 5542 ret = 0;
5543 goto out;
5544 }
1d5a4d9b 5545
de5f70e0
AK		 5546 if (err != EMULATE_DONE) {
5547 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5548 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5549 vcpu->run->internal.ndata = 0;
6d77dbfc 5550 return 0;
de5f70e0 5551 }
ea953ef0 5552
8d76c49e
GN		 5553 if (vcpu->arch.halt_request) {
5554 vcpu->arch.halt_request = 0;
5555 ret = kvm_emulate_halt(vcpu);
5556 goto out;
5557 }
5558
ea953ef0 5559 if (signal_pending(current))
80ced186 5560 goto out;
ea953ef0
MG		 5561 if (need_resched())
5562 schedule();
5563 }
5564
14168786 5565 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5566out:
5567 return ret;
ea953ef0
MG		 5568}
5569
4b8d54f9
ZE		 5570/*
5571 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5572 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5573 */
9fb41ba8 5574static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5575{
5576 skip_emulated_instruction(vcpu);
5577 kvm_vcpu_on_spin(vcpu);
5578
5579 return 1;
5580}
5581
59708670
SY		 5582static int handle_invalid_op(struct kvm_vcpu *vcpu)
5583{
5584 kvm_queue_exception(vcpu, UD_VECTOR);
5585 return 1;
5586}
5587
ff2f6fe9
NHE		 5588/*
5589 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5590 * We could reuse a single VMCS for all the L2 guests, but we also want the
5591 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5592 * allows keeping them loaded on the processor, and in the future will allow
5593 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5594 * every entry if they never change.
5595 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5596 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5597 *
5598 * The following functions allocate and free a vmcs02 in this pool.
5599 */
5600
5601/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5602static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5603{
5604 struct vmcs02_list *item;
5605 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5606 if (item->vmptr == vmx->nested.current_vmptr) {
5607 list_move(&item->list, &vmx->nested.vmcs02_pool);
5608 return &item->vmcs02;
5609 }
5610
5611 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5612 /* Recycle the least recently used VMCS. */
5613 item = list_entry(vmx->nested.vmcs02_pool.prev,
5614 struct vmcs02_list, list);
5615 item->vmptr = vmx->nested.current_vmptr;
5616 list_move(&item->list, &vmx->nested.vmcs02_pool);
5617 return &item->vmcs02;
5618 }
5619
5620 /* Create a new VMCS */
0fa24ce3 5621 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5622 if (!item)
5623 return NULL;
5624 item->vmcs02.vmcs = alloc_vmcs();
5625 if (!item->vmcs02.vmcs) {
5626 kfree(item);
5627 return NULL;
5628 }
5629 loaded_vmcs_init(&item->vmcs02);
5630 item->vmptr = vmx->nested.current_vmptr;
5631 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5632 vmx->nested.vmcs02_num++;
5633 return &item->vmcs02;
5634}
5635
5636/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5637static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5638{
5639 struct vmcs02_list *item;
5640 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5641 if (item->vmptr == vmptr) {
5642 free_loaded_vmcs(&item->vmcs02);
5643 list_del(&item->list);
5644 kfree(item);
5645 vmx->nested.vmcs02_num--;
5646 return;
5647 }
5648}
5649
5650/*
5651 * Free all VMCSs saved for this vcpu, except the one pointed by
5652 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5653 * currently used, if running L2), and vmcs01 when running L2.
5654 */
5655static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5656{
5657 struct vmcs02_list *item, *n;
5658 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5659 if (vmx->loaded_vmcs != &item->vmcs02)
5660 free_loaded_vmcs(&item->vmcs02);
5661 list_del(&item->list);
5662 kfree(item);
5663 }
5664 vmx->nested.vmcs02_num = 0;
5665
5666 if (vmx->loaded_vmcs != &vmx->vmcs01)
5667 free_loaded_vmcs(&vmx->vmcs01);
5668}
5669
0658fbaa
ACL		 5670/*
5671 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5672 * set the success or error code of an emulated VMX instruction, as specified
5673 * by Vol 2B, VMX Instruction Reference, "Conventions".
5674 */
5675static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5676{
5677 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5678 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5679 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5680}
5681
5682static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5683{
5684 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5685 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5686 X86_EFLAGS_SF | X86_EFLAGS_OF))
5687 | X86_EFLAGS_CF);
5688}
5689
145c28dd 5690static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5691 u32 vm_instruction_error)
5692{
5693 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5694 /*
5695 * failValid writes the error number to the current VMCS, which
5696 * can't be done there isn't a current VMCS.
5697 */
5698 nested_vmx_failInvalid(vcpu);
5699 return;
5700 }
5701 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5702 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5703 X86_EFLAGS_SF | X86_EFLAGS_OF))
5704 | X86_EFLAGS_ZF);
5705 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5706 /*
5707 * We don't need to force a shadow sync because
5708 * VM_INSTRUCTION_ERROR is not shadowed
5709 */
5710}
145c28dd 5711
f4124500
JK		 5712static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5713{
5714 struct vcpu_vmx *vmx =
5715 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5716
5717 vmx->nested.preemption_timer_expired = true;
5718 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5719 kvm_vcpu_kick(&vmx->vcpu);
5720
5721 return HRTIMER_NORESTART;
5722}
5723
ec378aee
NHE		 5724/*
5725 * Emulate the VMXON instruction.
5726 * Currently, we just remember that VMX is active, and do not save or even
5727 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5728 * do not currently need to store anything in that guest-allocated memory
5729 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5730 * argument is different from the VMXON pointer (which the spec says they do).
5731 */
5732static int handle_vmon(struct kvm_vcpu *vcpu)
5733{
5734 struct kvm_segment cs;
5735 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5736 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5737 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5738 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5739
5740 /* The Intel VMX Instruction Reference lists a bunch of bits that
5741 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5742 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5743 * Otherwise, we should fail with #UD. We test these now:
5744 */
5745 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5746 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5747 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5748 kvm_queue_exception(vcpu, UD_VECTOR);
5749 return 1;
5750 }
5751
5752 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5753 if (is_long_mode(vcpu) && !cs.l) {
5754 kvm_queue_exception(vcpu, UD_VECTOR);
5755 return 1;
5756 }
5757
5758 if (vmx_get_cpl(vcpu)) {
5759 kvm_inject_gp(vcpu, 0);
5760 return 1;
5761 }
145c28dd
AG		 5762 if (vmx->nested.vmxon) {
5763 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5764 skip_emulated_instruction(vcpu);
5765 return 1;
5766 }
b3897a49
NHE		 5767
5768 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5769 != VMXON_NEEDED_FEATURES) {
5770 kvm_inject_gp(vcpu, 0);
5771 return 1;
5772 }
5773
8de48833
AG		 5774 if (enable_shadow_vmcs) {
5775 shadow_vmcs = alloc_vmcs();
5776 if (!shadow_vmcs)
5777 return -ENOMEM;
5778 /* mark vmcs as shadow */
5779 shadow_vmcs->revision_id |= (1u << 31);
5780 /* init shadow vmcs */
5781 vmcs_clear(shadow_vmcs);
5782 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5783 }
ec378aee 5784
ff2f6fe9
NHE		 5785 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5786 vmx->nested.vmcs02_num = 0;
5787
f4124500
JK		 5788 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5789 HRTIMER_MODE_REL);
5790 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5791
ec378aee
NHE		 5792 vmx->nested.vmxon = true;
5793
5794 skip_emulated_instruction(vcpu);
a25eb114 5795 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5796 return 1;
5797}
5798
5799/*
5800 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5801 * for running VMX instructions (except VMXON, whose prerequisites are
5802 * slightly different). It also specifies what exception to inject otherwise.
5803 */
5804static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5805{
5806 struct kvm_segment cs;
5807 struct vcpu_vmx *vmx = to_vmx(vcpu);
5808
5809 if (!vmx->nested.vmxon) {
5810 kvm_queue_exception(vcpu, UD_VECTOR);
5811 return 0;
5812 }
5813
5814 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5815 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5816 (is_long_mode(vcpu) && !cs.l)) {
5817 kvm_queue_exception(vcpu, UD_VECTOR);
5818 return 0;
5819 }
5820
5821 if (vmx_get_cpl(vcpu)) {
5822 kvm_inject_gp(vcpu, 0);
5823 return 0;
5824 }
5825
5826 return 1;
5827}
5828
e7953d7f
AG		 5829static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5830{
8a1b9dd0 5831 u32 exec_control;
012f83cb
AG		 5832 if (enable_shadow_vmcs) {
5833 if (vmx->nested.current_vmcs12 != NULL) {
5834 /* copy to memory all shadowed fields in case
5835 they were modified */
5836 copy_shadow_to_vmcs12(vmx);
5837 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5838 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5839 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5840 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5841 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5842 }
5843 }
e7953d7f
AG		 5844 kunmap(vmx->nested.current_vmcs12_page);
5845 nested_release_page(vmx->nested.current_vmcs12_page);
5846}
5847
ec378aee
NHE		 5848/*
5849 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5850 * just stops using VMX.
5851 */
5852static void free_nested(struct vcpu_vmx *vmx)
5853{
5854 if (!vmx->nested.vmxon)
5855 return;
5856 vmx->nested.vmxon = false;
a9d30f33 5857 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5858 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5859 vmx->nested.current_vmptr = -1ull;
5860 vmx->nested.current_vmcs12 = NULL;
5861 }
e7953d7f
AG		 5862 if (enable_shadow_vmcs)
5863 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5864 /* Unpin physical memory we referred to in current vmcs02 */
5865 if (vmx->nested.apic_access_page) {
5866 nested_release_page(vmx->nested.apic_access_page);
5867 vmx->nested.apic_access_page = 0;
5868 }
ff2f6fe9
NHE		 5869
5870 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5871}
5872
5873/* Emulate the VMXOFF instruction */
5874static int handle_vmoff(struct kvm_vcpu *vcpu)
5875{
5876 if (!nested_vmx_check_permission(vcpu))
5877 return 1;
5878 free_nested(to_vmx(vcpu));
5879 skip_emulated_instruction(vcpu);
a25eb114 5880 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5881 return 1;
5882}
5883
064aea77
NHE		 5884/*
5885 * Decode the memory-address operand of a vmx instruction, as recorded on an
5886 * exit caused by such an instruction (run by a guest hypervisor).
5887 * On success, returns 0. When the operand is invalid, returns 1 and throws
5888 * #UD or #GP.
5889 */
5890static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5891 unsigned long exit_qualification,
5892 u32 vmx_instruction_info, gva_t *ret)
5893{
5894 /*
5895 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5896 * Execution", on an exit, vmx_instruction_info holds most of the
5897 * addressing components of the operand. Only the displacement part
5898 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5899 * For how an actual address is calculated from all these components,
5900 * refer to Vol. 1, "Operand Addressing".
5901 */
5902 int scaling = vmx_instruction_info & 3;
5903 int addr_size = (vmx_instruction_info >> 7) & 7;
5904 bool is_reg = vmx_instruction_info & (1u << 10);
5905 int seg_reg = (vmx_instruction_info >> 15) & 7;
5906 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5907 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5908 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5909 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5910
5911 if (is_reg) {
5912 kvm_queue_exception(vcpu, UD_VECTOR);
5913 return 1;
5914 }
5915
5916 /* Addr = segment_base + offset */
5917 /* offset = base + [index * scale] + displacement */
5918 *ret = vmx_get_segment_base(vcpu, seg_reg);
5919 if (base_is_valid)
5920 *ret += kvm_register_read(vcpu, base_reg);
5921 if (index_is_valid)
5922 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5923 *ret += exit_qualification; /* holds the displacement */
5924
5925 if (addr_size == 1) /* 32 bit */
5926 *ret &= 0xffffffff;
5927
5928 /*
5929 * TODO: throw #GP (and return 1) in various cases that the VM*
5930 * instructions require it - e.g., offset beyond segment limit,
5931 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5932 * address, and so on. Currently these are not checked.
5933 */
5934 return 0;
5935}
5936
27d6c865
NHE		 5937/* Emulate the VMCLEAR instruction */
5938static int handle_vmclear(struct kvm_vcpu *vcpu)
5939{
5940 struct vcpu_vmx *vmx = to_vmx(vcpu);
5941 gva_t gva;
5942 gpa_t vmptr;
5943 struct vmcs12 *vmcs12;
5944 struct page *page;
5945 struct x86_exception e;
5946
5947 if (!nested_vmx_check_permission(vcpu))
5948 return 1;
5949
5950 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5951 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5952 return 1;
5953
5954 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5955 sizeof(vmptr), &e)) {
5956 kvm_inject_page_fault(vcpu, &e);
5957 return 1;
5958 }
5959
5960 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5961 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5962 skip_emulated_instruction(vcpu);
5963 return 1;
5964 }
5965
5966 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5967 nested_release_vmcs12(vmx);
27d6c865
NHE		 5968 vmx->nested.current_vmptr = -1ull;
5969 vmx->nested.current_vmcs12 = NULL;
5970 }
5971
5972 page = nested_get_page(vcpu, vmptr);
5973 if (page == NULL) {
5974 /*
5975 * For accurate processor emulation, VMCLEAR beyond available
5976 * physical memory should do nothing at all. However, it is
5977 * possible that a nested vmx bug, not a guest hypervisor bug,
5978 * resulted in this case, so let's shut down before doing any
5979 * more damage:
5980 */
5981 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5982 return 1;
5983 }
5984 vmcs12 = kmap(page);
5985 vmcs12->launch_state = 0;
5986 kunmap(page);
5987 nested_release_page(page);
5988
5989 nested_free_vmcs02(vmx, vmptr);
5990
5991 skip_emulated_instruction(vcpu);
5992 nested_vmx_succeed(vcpu);
5993 return 1;
5994}
5995
cd232ad0
NHE		 5996static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5997
5998/* Emulate the VMLAUNCH instruction */
5999static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6000{
6001 return nested_vmx_run(vcpu, true);
6002}
6003
6004/* Emulate the VMRESUME instruction */
6005static int handle_vmresume(struct kvm_vcpu *vcpu)
6006{
6007
6008 return nested_vmx_run(vcpu, false);
6009}
6010
49f705c5
NHE		 6011enum vmcs_field_type {
6012 VMCS_FIELD_TYPE_U16 = 0,
6013 VMCS_FIELD_TYPE_U64 = 1,
6014 VMCS_FIELD_TYPE_U32 = 2,
6015 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6016};
6017
6018static inline int vmcs_field_type(unsigned long field)
6019{
6020 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6021 return VMCS_FIELD_TYPE_U32;
6022 return (field >> 13) & 0x3 ;
6023}
6024
6025static inline int vmcs_field_readonly(unsigned long field)
6026{
6027 return (((field >> 10) & 0x3) == 1);
6028}
6029
6030/*
6031 * Read a vmcs12 field. Since these can have varying lengths and we return
6032 * one type, we chose the biggest type (u64) and zero-extend the return value
6033 * to that size. Note that the caller, handle_vmread, might need to use only
6034 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6035 * 64-bit fields are to be returned).
6036 */
6037static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6038 unsigned long field, u64 *ret)
6039{
6040 short offset = vmcs_field_to_offset(field);
6041 char *p;
6042
6043 if (offset < 0)
6044 return 0;
6045
6046 p = ((char *)(get_vmcs12(vcpu))) + offset;
6047
6048 switch (vmcs_field_type(field)) {
6049 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6050 *ret = *((natural_width *)p);
6051 return 1;
6052 case VMCS_FIELD_TYPE_U16:
6053 *ret = *((u16 *)p);
6054 return 1;
6055 case VMCS_FIELD_TYPE_U32:
6056 *ret = *((u32 *)p);
6057 return 1;
6058 case VMCS_FIELD_TYPE_U64:
6059 *ret = *((u64 *)p);
6060 return 1;
6061 default:
6062 return 0; /* can never happen. */
6063 }
6064}
6065
20b97fea
AG		 6066
6067static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6068 unsigned long field, u64 field_value){
6069 short offset = vmcs_field_to_offset(field);
6070 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6071 if (offset < 0)
6072 return false;
6073
6074 switch (vmcs_field_type(field)) {
6075 case VMCS_FIELD_TYPE_U16:
6076 *(u16 *)p = field_value;
6077 return true;
6078 case VMCS_FIELD_TYPE_U32:
6079 *(u32 *)p = field_value;
6080 return true;
6081 case VMCS_FIELD_TYPE_U64:
6082 *(u64 *)p = field_value;
6083 return true;
6084 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6085 *(natural_width *)p = field_value;
6086 return true;
6087 default:
6088 return false; /* can never happen. */
6089 }
6090
6091}
6092
16f5b903
AG		 6093static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6094{
6095 int i;
6096 unsigned long field;
6097 u64 field_value;
6098 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6099 const unsigned long *fields = shadow_read_write_fields;
6100 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6101
6102 vmcs_load(shadow_vmcs);
6103
6104 for (i = 0; i < num_fields; i++) {
6105 field = fields[i];
6106 switch (vmcs_field_type(field)) {
6107 case VMCS_FIELD_TYPE_U16:
6108 field_value = vmcs_read16(field);
6109 break;
6110 case VMCS_FIELD_TYPE_U32:
6111 field_value = vmcs_read32(field);
6112 break;
6113 case VMCS_FIELD_TYPE_U64:
6114 field_value = vmcs_read64(field);
6115 break;
6116 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6117 field_value = vmcs_readl(field);
6118 break;
6119 }
6120 vmcs12_write_any(&vmx->vcpu, field, field_value);
6121 }
6122
6123 vmcs_clear(shadow_vmcs);
6124 vmcs_load(vmx->loaded_vmcs->vmcs);
6125}
6126
c3114420
AG		 6127static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6128{
c2bae893
MK		 6129 const unsigned long *fields[] = {
6130 shadow_read_write_fields,
6131 shadow_read_only_fields
c3114420 6132 };
c2bae893 6133 const int max_fields[] = {
c3114420
AG		 6134 max_shadow_read_write_fields,
6135 max_shadow_read_only_fields
6136 };
6137 int i, q;
6138 unsigned long field;
6139 u64 field_value = 0;
6140 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6141
6142 vmcs_load(shadow_vmcs);
6143
c2bae893 6144 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6145 for (i = 0; i < max_fields[q]; i++) {
6146 field = fields[q][i];
6147 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6148
6149 switch (vmcs_field_type(field)) {
6150 case VMCS_FIELD_TYPE_U16:
6151 vmcs_write16(field, (u16)field_value);
6152 break;
6153 case VMCS_FIELD_TYPE_U32:
6154 vmcs_write32(field, (u32)field_value);
6155 break;
6156 case VMCS_FIELD_TYPE_U64:
6157 vmcs_write64(field, (u64)field_value);
6158 break;
6159 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6160 vmcs_writel(field, (long)field_value);
6161 break;
6162 }
6163 }
6164 }
6165
6166 vmcs_clear(shadow_vmcs);
6167 vmcs_load(vmx->loaded_vmcs->vmcs);
6168}
6169
49f705c5
NHE		 6170/*
6171 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6172 * used before) all generate the same failure when it is missing.
6173 */
6174static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6175{
6176 struct vcpu_vmx *vmx = to_vmx(vcpu);
6177 if (vmx->nested.current_vmptr == -1ull) {
6178 nested_vmx_failInvalid(vcpu);
6179 skip_emulated_instruction(vcpu);
6180 return 0;
6181 }
6182 return 1;
6183}
6184
6185static int handle_vmread(struct kvm_vcpu *vcpu)
6186{
6187 unsigned long field;
6188 u64 field_value;
6189 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6190 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6191 gva_t gva = 0;
6192
6193 if (!nested_vmx_check_permission(vcpu) ||
6194 !nested_vmx_check_vmcs12(vcpu))
6195 return 1;
6196
6197 /* Decode instruction info and find the field to read */
6198 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6199 /* Read the field, zero-extended to a u64 field_value */
6200 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6201 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6202 skip_emulated_instruction(vcpu);
6203 return 1;
6204 }
6205 /*
6206 * Now copy part of this value to register or memory, as requested.
6207 * Note that the number of bits actually copied is 32 or 64 depending
6208 * on the guest's mode (32 or 64 bit), not on the given field's length.
6209 */
6210 if (vmx_instruction_info & (1u << 10)) {
6211 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6212 field_value);
6213 } else {
6214 if (get_vmx_mem_address(vcpu, exit_qualification,
6215 vmx_instruction_info, &gva))
6216 return 1;
6217 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6218 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6219 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6220 }
6221
6222 nested_vmx_succeed(vcpu);
6223 skip_emulated_instruction(vcpu);
6224 return 1;
6225}
6226
6227
6228static int handle_vmwrite(struct kvm_vcpu *vcpu)
6229{
6230 unsigned long field;
6231 gva_t gva;
6232 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6233 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6234 /* The value to write might be 32 or 64 bits, depending on L1's long
6235 * mode, and eventually we need to write that into a field of several
6236 * possible lengths. The code below first zero-extends the value to 64
6237 * bit (field_value), and then copies only the approriate number of
6238 * bits into the vmcs12 field.
6239 */
6240 u64 field_value = 0;
6241 struct x86_exception e;
6242
6243 if (!nested_vmx_check_permission(vcpu) ||
6244 !nested_vmx_check_vmcs12(vcpu))
6245 return 1;
6246
6247 if (vmx_instruction_info & (1u << 10))
6248 field_value = kvm_register_read(vcpu,
6249 (((vmx_instruction_info) >> 3) & 0xf));
6250 else {
6251 if (get_vmx_mem_address(vcpu, exit_qualification,
6252 vmx_instruction_info, &gva))
6253 return 1;
6254 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6255 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6256 kvm_inject_page_fault(vcpu, &e);
6257 return 1;
6258 }
6259 }
6260
6261
6262 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6263 if (vmcs_field_readonly(field)) {
6264 nested_vmx_failValid(vcpu,
6265 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6266 skip_emulated_instruction(vcpu);
6267 return 1;
6268 }
6269
20b97fea 6270 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6271 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6272 skip_emulated_instruction(vcpu);
6273 return 1;
6274 }
6275
6276 nested_vmx_succeed(vcpu);
6277 skip_emulated_instruction(vcpu);
6278 return 1;
6279}
6280
63846663
NHE		 6281/* Emulate the VMPTRLD instruction */
6282static int handle_vmptrld(struct kvm_vcpu *vcpu)
6283{
6284 struct vcpu_vmx *vmx = to_vmx(vcpu);
6285 gva_t gva;
6286 gpa_t vmptr;
6287 struct x86_exception e;
8a1b9dd0 6288 u32 exec_control;
63846663
NHE		 6289
6290 if (!nested_vmx_check_permission(vcpu))
6291 return 1;
6292
6293 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6294 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6295 return 1;
6296
6297 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6298 sizeof(vmptr), &e)) {
6299 kvm_inject_page_fault(vcpu, &e);
6300 return 1;
6301 }
6302
6303 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6304 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6305 skip_emulated_instruction(vcpu);
6306 return 1;
6307 }
6308
6309 if (vmx->nested.current_vmptr != vmptr) {
6310 struct vmcs12 *new_vmcs12;
6311 struct page *page;
6312 page = nested_get_page(vcpu, vmptr);
6313 if (page == NULL) {
6314 nested_vmx_failInvalid(vcpu);
6315 skip_emulated_instruction(vcpu);
6316 return 1;
6317 }
6318 new_vmcs12 = kmap(page);
6319 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6320 kunmap(page);
6321 nested_release_page_clean(page);
6322 nested_vmx_failValid(vcpu,
6323 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6324 skip_emulated_instruction(vcpu);
6325 return 1;
6326 }
e7953d7f
AG		 6327 if (vmx->nested.current_vmptr != -1ull)
6328 nested_release_vmcs12(vmx);
63846663
NHE		 6329
6330 vmx->nested.current_vmptr = vmptr;
6331 vmx->nested.current_vmcs12 = new_vmcs12;
6332 vmx->nested.current_vmcs12_page = page;
012f83cb 6333 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6334 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6335 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6336 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6337 vmcs_write64(VMCS_LINK_POINTER,
6338 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6339 vmx->nested.sync_shadow_vmcs = true;
6340 }
63846663
NHE		 6341 }
6342
6343 nested_vmx_succeed(vcpu);
6344 skip_emulated_instruction(vcpu);
6345 return 1;
6346}
6347
6a4d7550
NHE		 6348/* Emulate the VMPTRST instruction */
6349static int handle_vmptrst(struct kvm_vcpu *vcpu)
6350{
6351 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6352 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6353 gva_t vmcs_gva;
6354 struct x86_exception e;
6355
6356 if (!nested_vmx_check_permission(vcpu))
6357 return 1;
6358
6359 if (get_vmx_mem_address(vcpu, exit_qualification,
6360 vmx_instruction_info, &vmcs_gva))
6361 return 1;
6362 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6363 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6364 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6365 sizeof(u64), &e)) {
6366 kvm_inject_page_fault(vcpu, &e);
6367 return 1;
6368 }
6369 nested_vmx_succeed(vcpu);
6370 skip_emulated_instruction(vcpu);
6371 return 1;
6372}
6373
bfd0a56b
NHE		 6374/* Emulate the INVEPT instruction */
6375static int handle_invept(struct kvm_vcpu *vcpu)
6376{
6377 u32 vmx_instruction_info, types;
6378 unsigned long type;
6379 gva_t gva;
6380 struct x86_exception e;
6381 struct {
6382 u64 eptp, gpa;
6383 } operand;
6384 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6385
6386 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6387 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6388 kvm_queue_exception(vcpu, UD_VECTOR);
6389 return 1;
6390 }
6391
6392 if (!nested_vmx_check_permission(vcpu))
6393 return 1;
6394
6395 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6396 kvm_queue_exception(vcpu, UD_VECTOR);
6397 return 1;
6398 }
6399
6400 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6401 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6402
6403 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6404
6405 if (!(types & (1UL << type))) {
6406 nested_vmx_failValid(vcpu,
6407 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6408 return 1;
6409 }
6410
6411 /* According to the Intel VMX instruction reference, the memory
6412 * operand is read even if it isn't needed (e.g., for type==global)
6413 */
6414 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6415 vmx_instruction_info, &gva))
6416 return 1;
6417 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6418 sizeof(operand), &e)) {
6419 kvm_inject_page_fault(vcpu, &e);
6420 return 1;
6421 }
6422
6423 switch (type) {
6424 case VMX_EPT_EXTENT_CONTEXT:
6425 if ((operand.eptp & eptp_mask) !=
6426 (nested_ept_get_cr3(vcpu) & eptp_mask))
6427 break;
6428 case VMX_EPT_EXTENT_GLOBAL:
6429 kvm_mmu_sync_roots(vcpu);
6430 kvm_mmu_flush_tlb(vcpu);
6431 nested_vmx_succeed(vcpu);
6432 break;
6433 default:
6434 BUG_ON(1);
6435 break;
6436 }
6437
6438 skip_emulated_instruction(vcpu);
6439 return 1;
6440}
6441
6aa8b732
AK		 6442/*
6443 * The exit handlers return 1 if the exit was handled fully and guest execution
6444 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6445 * to be done to userspace and return 0.
6446 */
772e0318 6447static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6448 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6449 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6450 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6451 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6452 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6453 [EXIT_REASON_CR_ACCESS] = handle_cr,
6454 [EXIT_REASON_DR_ACCESS] = handle_dr,
6455 [EXIT_REASON_CPUID] = handle_cpuid,
6456 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6457 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6458 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6459 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6460 [EXIT_REASON_INVD] = handle_invd,
a7052897 6461 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6462 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6463 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6464 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6465 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6466 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6467 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6468 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6469 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6470 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6471 [EXIT_REASON_VMOFF] = handle_vmoff,
6472 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6473 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6474 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6475 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6476 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6477 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6478 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6479 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6480 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6481 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6482 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6483 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6484 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6485 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6486 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6487};
6488
6489static const int kvm_vmx_max_exit_handlers =
50a3485c 6490 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6491
908a7bdd
JK		 6492static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6493 struct vmcs12 *vmcs12)
6494{
6495 unsigned long exit_qualification;
6496 gpa_t bitmap, last_bitmap;
6497 unsigned int port;
6498 int size;
6499 u8 b;
6500
908a7bdd 6501 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6502 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6503
6504 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6505
6506 port = exit_qualification >> 16;
6507 size = (exit_qualification & 7) + 1;
6508
6509 last_bitmap = (gpa_t)-1;
6510 b = -1;
6511
6512 while (size > 0) {
6513 if (port < 0x8000)
6514 bitmap = vmcs12->io_bitmap_a;
6515 else if (port < 0x10000)
6516 bitmap = vmcs12->io_bitmap_b;
6517 else
6518 return 1;
6519 bitmap += (port & 0x7fff) / 8;
6520
6521 if (last_bitmap != bitmap)
6522 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6523 return 1;
6524 if (b & (1 << (port & 7)))
6525 return 1;
6526
6527 port++;
6528 size--;
6529 last_bitmap = bitmap;
6530 }
6531
6532 return 0;
6533}
6534
644d711a
NHE		 6535/*
6536 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6537 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6538 * disinterest in the current event (read or write a specific MSR) by using an
6539 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6540 */
6541static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6542 struct vmcs12 *vmcs12, u32 exit_reason)
6543{
6544 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6545 gpa_t bitmap;
6546
cbd29cb6 6547 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6548 return 1;
6549
6550 /*
6551 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6552 * for the four combinations of read/write and low/high MSR numbers.
6553 * First we need to figure out which of the four to use:
6554 */
6555 bitmap = vmcs12->msr_bitmap;
6556 if (exit_reason == EXIT_REASON_MSR_WRITE)
6557 bitmap += 2048;
6558 if (msr_index >= 0xc0000000) {
6559 msr_index -= 0xc0000000;
6560 bitmap += 1024;
6561 }
6562
6563 /* Then read the msr_index'th bit from this bitmap: */
6564 if (msr_index < 1024*8) {
6565 unsigned char b;
bd31a7f5
JK		 6566 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6567 return 1;
644d711a
NHE		 6568 return 1 & (b >> (msr_index & 7));
6569 } else
6570 return 1; /* let L1 handle the wrong parameter */
6571}
6572
6573/*
6574 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6575 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6576 * intercept (via guest_host_mask etc.) the current event.
6577 */
6578static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6579 struct vmcs12 *vmcs12)
6580{
6581 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6582 int cr = exit_qualification & 15;
6583 int reg = (exit_qualification >> 8) & 15;
6584 unsigned long val = kvm_register_read(vcpu, reg);
6585
6586 switch ((exit_qualification >> 4) & 3) {
6587 case 0: /* mov to cr */
6588 switch (cr) {
6589 case 0:
6590 if (vmcs12->cr0_guest_host_mask &
6591 (val ^ vmcs12->cr0_read_shadow))
6592 return 1;
6593 break;
6594 case 3:
6595 if ((vmcs12->cr3_target_count >= 1 &&
6596 vmcs12->cr3_target_value0 == val) ||
6597 (vmcs12->cr3_target_count >= 2 &&
6598 vmcs12->cr3_target_value1 == val) ||
6599 (vmcs12->cr3_target_count >= 3 &&
6600 vmcs12->cr3_target_value2 == val) ||
6601 (vmcs12->cr3_target_count >= 4 &&
6602 vmcs12->cr3_target_value3 == val))
6603 return 0;
6604 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6605 return 1;
6606 break;
6607 case 4:
6608 if (vmcs12->cr4_guest_host_mask &
6609 (vmcs12->cr4_read_shadow ^ val))
6610 return 1;
6611 break;
6612 case 8:
6613 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6614 return 1;
6615 break;
6616 }
6617 break;
6618 case 2: /* clts */
6619 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6620 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6621 return 1;
6622 break;
6623 case 1: /* mov from cr */
6624 switch (cr) {
6625 case 3:
6626 if (vmcs12->cpu_based_vm_exec_control &
6627 CPU_BASED_CR3_STORE_EXITING)
6628 return 1;
6629 break;
6630 case 8:
6631 if (vmcs12->cpu_based_vm_exec_control &
6632 CPU_BASED_CR8_STORE_EXITING)
6633 return 1;
6634 break;
6635 }
6636 break;
6637 case 3: /* lmsw */
6638 /*
6639 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6640 * cr0. Other attempted changes are ignored, with no exit.
6641 */
6642 if (vmcs12->cr0_guest_host_mask & 0xe &
6643 (val ^ vmcs12->cr0_read_shadow))
6644 return 1;
6645 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6646 !(vmcs12->cr0_read_shadow & 0x1) &&
6647 (val & 0x1))
6648 return 1;
6649 break;
6650 }
6651 return 0;
6652}
6653
6654/*
6655 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6656 * should handle it ourselves in L0 (and then continue L2). Only call this
6657 * when in is_guest_mode (L2).
6658 */
6659static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6660{
644d711a
NHE		 6661 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6662 struct vcpu_vmx *vmx = to_vmx(vcpu);
6663 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6664 u32 exit_reason = vmx->exit_reason;
644d711a 6665
542060ea
JK		 6666 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6667 vmcs_readl(EXIT_QUALIFICATION),
6668 vmx->idt_vectoring_info,
6669 intr_info,
6670 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6671 KVM_ISA_VMX);
6672
644d711a
NHE		 6673 if (vmx->nested.nested_run_pending)
6674 return 0;
6675
6676 if (unlikely(vmx->fail)) {
bd80158a
JK		 6677 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6678 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6679 return 1;
6680 }
6681
6682 switch (exit_reason) {
6683 case EXIT_REASON_EXCEPTION_NMI:
6684 if (!is_exception(intr_info))
6685 return 0;
6686 else if (is_page_fault(intr_info))
6687 return enable_ept;
e504c909 6688 else if (is_no_device(intr_info) &&
ccf9844e 6689 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6690 return 0;
644d711a
NHE		 6691 return vmcs12->exception_bitmap &
6692 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6693 case EXIT_REASON_EXTERNAL_INTERRUPT:
6694 return 0;
6695 case EXIT_REASON_TRIPLE_FAULT:
6696 return 1;
6697 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6698 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6699 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6700 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6701 case EXIT_REASON_TASK_SWITCH:
6702 return 1;
6703 case EXIT_REASON_CPUID:
6704 return 1;
6705 case EXIT_REASON_HLT:
6706 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6707 case EXIT_REASON_INVD:
6708 return 1;
6709 case EXIT_REASON_INVLPG:
6710 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6711 case EXIT_REASON_RDPMC:
6712 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6713 case EXIT_REASON_RDTSC:
6714 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6715 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6716 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6717 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6718 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6719 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6720 case EXIT_REASON_INVEPT:
644d711a
NHE		 6721 /*
6722 * VMX instructions trap unconditionally. This allows L1 to
6723 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6724 */
6725 return 1;
6726 case EXIT_REASON_CR_ACCESS:
6727 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6728 case EXIT_REASON_DR_ACCESS:
6729 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6730 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6731 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6732 case EXIT_REASON_MSR_READ:
6733 case EXIT_REASON_MSR_WRITE:
6734 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6735 case EXIT_REASON_INVALID_STATE:
6736 return 1;
6737 case EXIT_REASON_MWAIT_INSTRUCTION:
6738 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6739 case EXIT_REASON_MONITOR_INSTRUCTION:
6740 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6741 case EXIT_REASON_PAUSE_INSTRUCTION:
6742 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6743 nested_cpu_has2(vmcs12,
6744 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6745 case EXIT_REASON_MCE_DURING_VMENTRY:
6746 return 0;
6747 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6748 return 1;
6749 case EXIT_REASON_APIC_ACCESS:
6750 return nested_cpu_has2(vmcs12,
6751 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6752 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6753 /*
6754 * L0 always deals with the EPT violation. If nested EPT is
6755 * used, and the nested mmu code discovers that the address is
6756 * missing in the guest EPT table (EPT12), the EPT violation
6757 * will be injected with nested_ept_inject_page_fault()
6758 */
6759 return 0;
644d711a 6760 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6761 /*
6762 * L2 never uses directly L1's EPT, but rather L0's own EPT
6763 * table (shadow on EPT) or a merged EPT table that L0 built
6764 * (EPT on EPT). So any problems with the structure of the
6765 * table is L0's fault.
6766 */
644d711a
NHE		 6767 return 0;
6768 case EXIT_REASON_WBINVD:
6769 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6770 case EXIT_REASON_XSETBV:
6771 return 1;
6772 default:
6773 return 1;
6774 }
6775}
6776
586f9607
AK		 6777static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6778{
6779 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6780 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6781}
6782
6aa8b732
AK		 6783/*
6784 * The guest has exited. See if we can fix it or if we need userspace
6785 * assistance.
6786 */
851ba692 6787static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6788{
29bd8a78 6789 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6790 u32 exit_reason = vmx->exit_reason;
1155f76a 6791 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6792
80ced186 6793 /* If guest state is invalid, start emulating */
14168786 6794 if (vmx->emulation_required)
80ced186 6795 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6796
644d711a 6797 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6798 nested_vmx_vmexit(vcpu, exit_reason,
6799 vmcs_read32(VM_EXIT_INTR_INFO),
6800 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6801 return 1;
6802 }
6803
5120702e
MG		 6804 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6805 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6806 vcpu->run->fail_entry.hardware_entry_failure_reason
6807 = exit_reason;
6808 return 0;
6809 }
6810
29bd8a78 6811 if (unlikely(vmx->fail)) {
851ba692
AK		 6812 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6813 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6814 = vmcs_read32(VM_INSTRUCTION_ERROR);
6815 return 0;
6816 }
6aa8b732 6817
b9bf6882
XG		 6818 /*
6819 * Note:
6820 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6821 * delivery event since it indicates guest is accessing MMIO.
6822 * The vm-exit can be triggered again after return to guest that
6823 * will cause infinite loop.
6824 */
d77c26fc 6825 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6826 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6827 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6828 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6829 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6830 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6831 vcpu->run->internal.ndata = 2;
6832 vcpu->run->internal.data[0] = vectoring_info;
6833 vcpu->run->internal.data[1] = exit_reason;
6834 return 0;
6835 }
3b86cd99 6836
644d711a
NHE		 6837 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6838 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6839 get_vmcs12(vcpu))))) {
c4282df9 6840 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6841 vmx->soft_vnmi_blocked = 0;
3b86cd99 6842 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6843 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6844 /*
6845 * This CPU don't support us in finding the end of an
6846 * NMI-blocked window if the guest runs with IRQs
6847 * disabled. So we pull the trigger after 1 s of
6848 * futile waiting, but inform the user about this.
6849 */
6850 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6851 "state on VCPU %d after 1 s timeout\n",
6852 __func__, vcpu->vcpu_id);
6853 vmx->soft_vnmi_blocked = 0;
3b86cd99 6854 }
3b86cd99
JK		 6855 }
6856
6aa8b732
AK		 6857 if (exit_reason < kvm_vmx_max_exit_handlers
6858 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6859 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6860 else {
851ba692
AK		 6861 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6862 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6863 }
6864 return 0;
6865}
6866
95ba8273 6867static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6868{
95ba8273 6869 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6870 vmcs_write32(TPR_THRESHOLD, 0);
6871 return;
6872 }
6873
95ba8273 6874 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6875}
6876
8d14695f
YZ		 6877static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6878{
6879 u32 sec_exec_control;
6880
6881 /*
6882 * There is not point to enable virtualize x2apic without enable
6883 * apicv
6884 */
c7c9c56c
YZ		 6885 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6886 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6887 return;
6888
6889 if (!vm_need_tpr_shadow(vcpu->kvm))
6890 return;
6891
6892 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6893
6894 if (set) {
6895 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6896 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6897 } else {
6898 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6899 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6900 }
6901 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6902
6903 vmx_set_msr_bitmap(vcpu);
6904}
6905
c7c9c56c
YZ		 6906static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6907{
6908 u16 status;
6909 u8 old;
6910
6911 if (!vmx_vm_has_apicv(kvm))
6912 return;
6913
6914 if (isr == -1)
6915 isr = 0;
6916
6917 status = vmcs_read16(GUEST_INTR_STATUS);
6918 old = status >> 8;
6919 if (isr != old) {
6920 status &= 0xff;
6921 status |= isr << 8;
6922 vmcs_write16(GUEST_INTR_STATUS, status);
6923 }
6924}
6925
6926static void vmx_set_rvi(int vector)
6927{
6928 u16 status;
6929 u8 old;
6930
6931 status = vmcs_read16(GUEST_INTR_STATUS);
6932 old = (u8)status & 0xff;
6933 if ((u8)vector != old) {
6934 status &= ~0xff;
6935 status |= (u8)vector;
6936 vmcs_write16(GUEST_INTR_STATUS, status);
6937 }
6938}
6939
6940static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6941{
6942 if (max_irr == -1)
6943 return;
6944
6945 vmx_set_rvi(max_irr);
6946}
6947
6948static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6949{
3d81bc7e
YZ		 6950 if (!vmx_vm_has_apicv(vcpu->kvm))
6951 return;
6952
c7c9c56c
YZ		 6953 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6954 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6955 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6956 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6957}
6958
51aa01d1 6959static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6960{
00eba012
AK		 6961 u32 exit_intr_info;
6962
6963 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6964 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6965 return;
6966
c5ca8e57 6967 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6968 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6969
6970 /* Handle machine checks before interrupts are enabled */
00eba012 6971 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6972 kvm_machine_check();
6973
20f65983 6974 /* We need to handle NMIs before interrupts are enabled */
00eba012 6975 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6976 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6977 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6978 asm("int $2");
ff9d07a0
ZY		 6979 kvm_after_handle_nmi(&vmx->vcpu);
6980 }
51aa01d1 6981}
20f65983 6982
a547c6db
YZ		 6983static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6984{
6985 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6986
6987 /*
6988 * If external interrupt exists, IF bit is set in rflags/eflags on the
6989 * interrupt stack frame, and interrupt will be enabled on a return
6990 * from interrupt handler.
6991 */
6992 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6993 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6994 unsigned int vector;
6995 unsigned long entry;
6996 gate_desc *desc;
6997 struct vcpu_vmx *vmx = to_vmx(vcpu);
6998#ifdef CONFIG_X86_64
6999 unsigned long tmp;
7000#endif
7001
7002 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7003 desc = (gate_desc *)vmx->host_idt_base + vector;
7004 entry = gate_offset(*desc);
7005 asm volatile(
7006#ifdef CONFIG_X86_64
7007 "mov %%" _ASM_SP ", %[sp]\n\t"
7008 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7009 "push $%c[ss]\n\t"
7010 "push %[sp]\n\t"
7011#endif
7012 "pushf\n\t"
7013 "orl $0x200, (%%" _ASM_SP ")\n\t"
7014 __ASM_SIZE(push) " $%c[cs]\n\t"
7015 "call *%[entry]\n\t"
7016 :
7017#ifdef CONFIG_X86_64
7018 [sp]"=&r"(tmp)
7019#endif
7020 :
7021 [entry]"r"(entry),
7022 [ss]"i"(__KERNEL_DS),
7023 [cs]"i"(__KERNEL_CS)
7024 );
7025 } else
7026 local_irq_enable();
7027}
7028
da8999d3
LJ		 7029static bool vmx_mpx_supported(void)
7030{
7031 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7032 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7033}
7034
51aa01d1
AK		 7035static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7036{
c5ca8e57 7037 u32 exit_intr_info;
51aa01d1
AK		 7038 bool unblock_nmi;
7039 u8 vector;
7040 bool idtv_info_valid;
7041
7042 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7043
cf393f75 7044 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7045 if (vmx->nmi_known_unmasked)
7046 return;
c5ca8e57
AK		 7047 /*
7048 * Can't use vmx->exit_intr_info since we're not sure what
7049 * the exit reason is.
7050 */
7051 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7052 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7053 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7054 /*
7b4a25cb 7055 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7056 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7057 * a guest IRET fault.
7b4a25cb
GN		 7058 * SDM 3: 23.2.2 (September 2008)
7059 * Bit 12 is undefined in any of the following cases:
7060 * If the VM exit sets the valid bit in the IDT-vectoring
7061 * information field.
7062 * If the VM exit is due to a double fault.
cf393f75 7063 */
7b4a25cb
GN		 7064 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7065 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7066 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7067 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7068 else
7069 vmx->nmi_known_unmasked =
7070 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7071 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7072 } else if (unlikely(vmx->soft_vnmi_blocked))
7073 vmx->vnmi_blocked_time +=
7074 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7075}
7076
3ab66e8a 7077static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7078 u32 idt_vectoring_info,
7079 int instr_len_field,
7080 int error_code_field)
51aa01d1 7081{
51aa01d1
AK		 7082 u8 vector;
7083 int type;
7084 bool idtv_info_valid;
7085
7086 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7087
3ab66e8a
JK		 7088 vcpu->arch.nmi_injected = false;
7089 kvm_clear_exception_queue(vcpu);
7090 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7091
7092 if (!idtv_info_valid)
7093 return;
7094
3ab66e8a 7095 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7096
668f612f
AK		 7097 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7098 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7099
64a7ec06 7100 switch (type) {
37b96e98 7101 case INTR_TYPE_NMI_INTR:
3ab66e8a 7102 vcpu->arch.nmi_injected = true;
668f612f 7103 /*
7b4a25cb 7104 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7105 * Clear bit "block by NMI" before VM entry if a NMI
7106 * delivery faulted.
668f612f 7107 */
3ab66e8a 7108 vmx_set_nmi_mask(vcpu, false);
37b96e98 7109 break;
37b96e98 7110 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7111 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7112 /* fall through */
7113 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7114 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7115 u32 err = vmcs_read32(error_code_field);
851eb667 7116 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7117 } else
851eb667 7118 kvm_requeue_exception(vcpu, vector);
37b96e98 7119 break;
66fd3f7f 7120 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7121 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7122 /* fall through */
37b96e98 7123 case INTR_TYPE_EXT_INTR:
3ab66e8a 7124 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7125 break;
7126 default:
7127 break;
f7d9238f 7128 }
cf393f75
AK		 7129}
7130
83422e17
AK		 7131static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7132{
3ab66e8a 7133 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7134 VM_EXIT_INSTRUCTION_LEN,
7135 IDT_VECTORING_ERROR_CODE);
7136}
7137
b463a6f7
AK		 7138static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7139{
3ab66e8a 7140 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7141 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7142 VM_ENTRY_INSTRUCTION_LEN,
7143 VM_ENTRY_EXCEPTION_ERROR_CODE);
7144
7145 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7146}
7147
d7cd9796
GN		 7148static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7149{
7150 int i, nr_msrs;
7151 struct perf_guest_switch_msr *msrs;
7152
7153 msrs = perf_guest_get_msrs(&nr_msrs);
7154
7155 if (!msrs)
7156 return;
7157
7158 for (i = 0; i < nr_msrs; i++)
7159 if (msrs[i].host == msrs[i].guest)
7160 clear_atomic_switch_msr(vmx, msrs[i].msr);
7161 else
7162 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7163 msrs[i].host);
7164}
7165
a3b5ba49 7166static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7167{
a2fa3e9f 7168 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7169 unsigned long debugctlmsr;
104f226b
AK		 7170
7171 /* Record the guest's net vcpu time for enforced NMI injections. */
7172 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7173 vmx->entry_time = ktime_get();
7174
7175 /* Don't enter VMX if guest state is invalid, let the exit handler
7176 start emulation until we arrive back to a valid state */
14168786 7177 if (vmx->emulation_required)
104f226b
AK		 7178 return;
7179
012f83cb
AG		 7180 if (vmx->nested.sync_shadow_vmcs) {
7181 copy_vmcs12_to_shadow(vmx);
7182 vmx->nested.sync_shadow_vmcs = false;
7183 }
7184
104f226b
AK		 7185 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7186 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7187 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7188 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7189
7190 /* When single-stepping over STI and MOV SS, we must clear the
7191 * corresponding interruptibility bits in the guest state. Otherwise
7192 * vmentry fails as it then expects bit 14 (BS) in pending debug
7193 * exceptions being set, but that's not correct for the guest debugging
7194 * case. */
7195 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7196 vmx_set_interrupt_shadow(vcpu, 0);
7197
d7cd9796 7198 atomic_switch_perf_msrs(vmx);
2a7921b7 7199 debugctlmsr = get_debugctlmsr();
d7cd9796 7200
d462b819 7201 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7202 asm(
6aa8b732 7203 /* Store host registers */
b188c81f
AK		 7204 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7205 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7206 "push %%" _ASM_CX " \n\t"
7207 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7208 "je 1f \n\t"
b188c81f 7209 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7210 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7211 "1: \n\t"
d3edefc0 7212 /* Reload cr2 if changed */
b188c81f
AK		 7213 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7214 "mov %%cr2, %%" _ASM_DX " \n\t"
7215 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7216 "je 2f \n\t"
b188c81f 7217 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7218 "2: \n\t"
6aa8b732 7219 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7220 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7221 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7222 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7223 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7224 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7225 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7226 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7227 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7228#ifdef CONFIG_X86_64
e08aa78a
AK		 7229 "mov %c[r8](%0), %%r8 \n\t"
7230 "mov %c[r9](%0), %%r9 \n\t"
7231 "mov %c[r10](%0), %%r10 \n\t"
7232 "mov %c[r11](%0), %%r11 \n\t"
7233 "mov %c[r12](%0), %%r12 \n\t"
7234 "mov %c[r13](%0), %%r13 \n\t"
7235 "mov %c[r14](%0), %%r14 \n\t"
7236 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7237#endif
b188c81f 7238 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7239
6aa8b732 7240 /* Enter guest mode */
83287ea4 7241 "jne 1f \n\t"
4ecac3fd 7242 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7243 "jmp 2f \n\t"
7244 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7245 "2: "
6aa8b732 7246 /* Save guest registers, load host registers, keep flags */
b188c81f 7247 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7248 "pop %0 \n\t"
b188c81f
AK		 7249 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7250 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7251 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7252 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7253 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7254 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7255 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7256#ifdef CONFIG_X86_64
e08aa78a
AK		 7257 "mov %%r8, %c[r8](%0) \n\t"
7258 "mov %%r9, %c[r9](%0) \n\t"
7259 "mov %%r10, %c[r10](%0) \n\t"
7260 "mov %%r11, %c[r11](%0) \n\t"
7261 "mov %%r12, %c[r12](%0) \n\t"
7262 "mov %%r13, %c[r13](%0) \n\t"
7263 "mov %%r14, %c[r14](%0) \n\t"
7264 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7265#endif
b188c81f
AK		 7266 "mov %%cr2, %%" _ASM_AX " \n\t"
7267 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7268
b188c81f 7269 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7270 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7271 ".pushsection .rodata \n\t"
7272 ".global vmx_return \n\t"
7273 "vmx_return: " _ASM_PTR " 2b \n\t"
7274 ".popsection"
e08aa78a 7275 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7276 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7277 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7278 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7279 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7280 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7281 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7282 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7283 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7284 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7285 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7286#ifdef CONFIG_X86_64
ad312c7c
ZX		 7287 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7288 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7289 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7290 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7291 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7292 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7293 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7294 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7295#endif
40712fae
AK		 7296 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7297 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7298 : "cc", "memory"
7299#ifdef CONFIG_X86_64
b188c81f 7300 , "rax", "rbx", "rdi", "rsi"
c2036300 7301 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7302#else
7303 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7304#endif
7305 );
6aa8b732 7306
2a7921b7
GN		 7307 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7308 if (debugctlmsr)
7309 update_debugctlmsr(debugctlmsr);
7310
aa67f609
AK		 7311#ifndef CONFIG_X86_64
7312 /*
7313 * The sysexit path does not restore ds/es, so we must set them to
7314 * a reasonable value ourselves.
7315 *
7316 * We can't defer this to vmx_load_host_state() since that function
7317 * may be executed in interrupt context, which saves and restore segments
7318 * around it, nullifying its effect.
7319 */
7320 loadsegment(ds, __USER_DS);
7321 loadsegment(es, __USER_DS);
7322#endif
7323
6de4f3ad 7324 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7325 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7326 | (1 << VCPU_EXREG_CPL)
aff48baa 7327 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7328 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7329 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7330 vcpu->arch.regs_dirty = 0;
7331
1155f76a
AK		 7332 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7333
d462b819 7334 vmx->loaded_vmcs->launched = 1;
1b6269db 7335
51aa01d1 7336 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7337 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7338
e0b890d3
GN		 7339 /*
7340 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7341 * we did not inject a still-pending event to L1 now because of
7342 * nested_run_pending, we need to re-enable this bit.
7343 */
7344 if (vmx->nested.nested_run_pending)
7345 kvm_make_request(KVM_REQ_EVENT, vcpu);
7346
7347 vmx->nested.nested_run_pending = 0;
7348
51aa01d1
AK		 7349 vmx_complete_atomic_exit(vmx);
7350 vmx_recover_nmi_blocking(vmx);
cf393f75 7351 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7352}
7353
6aa8b732
AK		 7354static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7355{
fb3f0f51
RR		 7356 struct vcpu_vmx *vmx = to_vmx(vcpu);
7357
cdbecfc3 7358 free_vpid(vmx);
d462b819 7359 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7360 free_nested(vmx);
fb3f0f51
RR		 7361 kfree(vmx->guest_msrs);
7362 kvm_vcpu_uninit(vcpu);
a4770347 7363 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7364}
7365
fb3f0f51 7366static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7367{
fb3f0f51 7368 int err;
c16f862d 7369 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7370 int cpu;
6aa8b732 7371
a2fa3e9f 7372 if (!vmx)
fb3f0f51
RR		 7373 return ERR_PTR(-ENOMEM);
7374
2384d2b3
SY		 7375 allocate_vpid(vmx);
7376
fb3f0f51
RR		 7377 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7378 if (err)
7379 goto free_vcpu;
965b58a5 7380
a2fa3e9f 7381 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7382 err = -ENOMEM;
fb3f0f51 7383 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7384 goto uninit_vcpu;
7385 }
965b58a5 7386
d462b819
NHE		 7387 vmx->loaded_vmcs = &vmx->vmcs01;
7388 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7389 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7390 goto free_msrs;
d462b819
NHE		 7391 if (!vmm_exclusive)
7392 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7393 loaded_vmcs_init(vmx->loaded_vmcs);
7394 if (!vmm_exclusive)
7395 kvm_cpu_vmxoff();
a2fa3e9f 7396
15ad7146
AK		 7397 cpu = get_cpu();
7398 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7399 vmx->vcpu.cpu = cpu;
8b9cf98c 7400 err = vmx_vcpu_setup(vmx);
fb3f0f51 7401 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7402 put_cpu();
fb3f0f51
RR		 7403 if (err)
7404 goto free_vmcs;
a63cb560 7405 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7406 err = alloc_apic_access_page(kvm);
7407 if (err)
5e4a0b3c 7408 goto free_vmcs;
a63cb560 7409 }
fb3f0f51 7410
b927a3ce
SY		 7411 if (enable_ept) {
7412 if (!kvm->arch.ept_identity_map_addr)
7413 kvm->arch.ept_identity_map_addr =
7414 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7415 err = -ENOMEM;
b7ebfb05
SY		 7416 if (alloc_identity_pagetable(kvm) != 0)
7417 goto free_vmcs;
93ea5388
GN		 7418 if (!init_rmode_identity_map(kvm))
7419 goto free_vmcs;
b927a3ce 7420 }
b7ebfb05 7421
a9d30f33
NHE		 7422 vmx->nested.current_vmptr = -1ull;
7423 vmx->nested.current_vmcs12 = NULL;
7424
fb3f0f51
RR		 7425 return &vmx->vcpu;
7426
7427free_vmcs:
5f3fbc34 7428 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7429free_msrs:
fb3f0f51
RR		 7430 kfree(vmx->guest_msrs);
7431uninit_vcpu:
7432 kvm_vcpu_uninit(&vmx->vcpu);
7433free_vcpu:
cdbecfc3 7434 free_vpid(vmx);
a4770347 7435 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7436 return ERR_PTR(err);
6aa8b732
AK		 7437}
7438
002c7f7c
YS		 7439static void __init vmx_check_processor_compat(void *rtn)
7440{
7441 struct vmcs_config vmcs_conf;
7442
7443 *(int *)rtn = 0;
7444 if (setup_vmcs_config(&vmcs_conf) < 0)
7445 *(int *)rtn = -EIO;
7446 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7447 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7448 smp_processor_id());
7449 *(int *)rtn = -EIO;
7450 }
7451}
7452
67253af5
SY		 7453static int get_ept_level(void)
7454{
7455 return VMX_EPT_DEFAULT_GAW + 1;
7456}
7457
4b12f0de 7458static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7459{
4b12f0de
SY		 7460 u64 ret;
7461
522c68c4
SY		 7462 /* For VT-d and EPT combination
7463 * 1. MMIO: always map as UC
7464 * 2. EPT with VT-d:
7465 * a. VT-d without snooping control feature: can't guarantee the
7466 * result, try to trust guest.
7467 * b. VT-d with snooping control feature: snooping control feature of
7468 * VT-d engine can guarantee the cache correctness. Just set it
7469 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7470 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7471 * consistent with host MTRR
7472 */
4b12f0de
SY		 7473 if (is_mmio)
7474 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7475 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7476 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7477 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7478 else
522c68c4 7479 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7480 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7481
7482 return ret;
64d4d521
SY		 7483}
7484
17cc3935 7485static int vmx_get_lpage_level(void)
344f414f 7486{
878403b7
SY		 7487 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7488 return PT_DIRECTORY_LEVEL;
7489 else
7490 /* For shadow and EPT supported 1GB page */
7491 return PT_PDPE_LEVEL;
344f414f
JR		 7492}
7493
0e851880
SY		 7494static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7495{
4e47c7a6
SY		 7496 struct kvm_cpuid_entry2 *best;
7497 struct vcpu_vmx *vmx = to_vmx(vcpu);
7498 u32 exec_control;
7499
7500 vmx->rdtscp_enabled = false;
7501 if (vmx_rdtscp_supported()) {
7502 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7503 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7504 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7505 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7506 vmx->rdtscp_enabled = true;
7507 else {
7508 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7509 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7510 exec_control);
7511 }
7512 }
7513 }
ad756a16 7514
ad756a16
MJ		 7515 /* Exposing INVPCID only when PCID is exposed */
7516 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7517 if (vmx_invpcid_supported() &&
4f977045 7518 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7519 guest_cpuid_has_pcid(vcpu)) {
29282fde 7520 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7521 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7522 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7523 exec_control);
7524 } else {
29282fde
TI		 7525 if (cpu_has_secondary_exec_ctrls()) {
7526 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7527 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7528 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7529 exec_control);
7530 }
ad756a16 7531 if (best)
4f977045 7532 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7533 }
0e851880
SY		 7534}
7535
d4330ef2
JR		 7536static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7537{
7b8050f5
NHE		 7538 if (func == 1 && nested)
7539 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7540}
7541
25d92081
YZ		 7542static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7543 struct x86_exception *fault)
7544{
533558bc
JK		 7545 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7546 u32 exit_reason;
25d92081
YZ		 7547
7548 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7549 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7550 else
533558bc
JK		 7551 exit_reason = EXIT_REASON_EPT_VIOLATION;
7552 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7553 vmcs12->guest_physical_address = fault->address;
7554}
7555
155a97a3
NHE		 7556/* Callbacks for nested_ept_init_mmu_context: */
7557
7558static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7559{
7560 /* return the page table to be shadowed - in our case, EPT12 */
7561 return get_vmcs12(vcpu)->ept_pointer;
7562}
7563
8a3c1a33 7564static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7565{
8a3c1a33 7566 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7567 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7568
7569 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7570 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7571 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7572
7573 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7574}
7575
7576static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7577{
7578 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7579}
7580
feaf0c7d
GN		 7581static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7582 struct x86_exception *fault)
7583{
7584 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7585
7586 WARN_ON(!is_guest_mode(vcpu));
7587
7588 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7589 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7590 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7591 vmcs_read32(VM_EXIT_INTR_INFO),
7592 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7593 else
7594 kvm_inject_page_fault(vcpu, fault);
7595}
7596
f4124500
JK		 7597static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7598{
7599 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7600 struct vcpu_vmx *vmx = to_vmx(vcpu);
7601
7602 if (vcpu->arch.virtual_tsc_khz == 0)
7603 return;
7604
7605 /* Make sure short timeouts reliably trigger an immediate vmexit.
7606 * hrtimer_start does not guarantee this. */
7607 if (preemption_timeout <= 1) {
7608 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7609 return;
7610 }
7611
7612 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7613 preemption_timeout *= 1000000;
7614 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7615 hrtimer_start(&vmx->nested.preemption_timer,
7616 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7617}
7618
fe3ef05c
NHE		 7619/*
7620 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7621 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7622 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7623 * guest in a way that will both be appropriate to L1's requests, and our
7624 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7625 * function also has additional necessary side-effects, like setting various
7626 * vcpu->arch fields.
7627 */
7628static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7629{
7630 struct vcpu_vmx *vmx = to_vmx(vcpu);
7631 u32 exec_control;
7632
7633 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7634 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7635 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7636 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7637 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7638 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7639 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7640 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7641 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7642 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7643 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7644 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7645 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7646 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7647 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7648 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7649 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7650 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7651 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7652 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7653 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7654 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7655 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7656 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7657 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7658 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7659 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7660 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7661 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7662 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7663 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7664 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7665 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7666 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7667 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7668 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7669
7670 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7671 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7672 vmcs12->vm_entry_intr_info_field);
7673 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7674 vmcs12->vm_entry_exception_error_code);
7675 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7676 vmcs12->vm_entry_instruction_len);
7677 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7678 vmcs12->guest_interruptibility_info);
fe3ef05c 7679 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7680 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7681 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7682 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7683 vmcs12->guest_pending_dbg_exceptions);
7684 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7685 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7686
7687 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7688
f4124500
JK		 7689 exec_control = vmcs12->pin_based_vm_exec_control;
7690 exec_control |= vmcs_config.pin_based_exec_ctrl;
7691 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7692 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7693
f4124500
JK		 7694 vmx->nested.preemption_timer_expired = false;
7695 if (nested_cpu_has_preemption_timer(vmcs12))
7696 vmx_start_preemption_timer(vcpu);
0238ea91 7697
fe3ef05c
NHE		 7698 /*
7699 * Whether page-faults are trapped is determined by a combination of
7700 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7701 * If enable_ept, L0 doesn't care about page faults and we should
7702 * set all of these to L1's desires. However, if !enable_ept, L0 does
7703 * care about (at least some) page faults, and because it is not easy
7704 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7705 * to exit on each and every L2 page fault. This is done by setting
7706 * MASK=MATCH=0 and (see below) EB.PF=1.
7707 * Note that below we don't need special code to set EB.PF beyond the
7708 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7709 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7710 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7711 *
7712 * A problem with this approach (when !enable_ept) is that L1 may be
7713 * injected with more page faults than it asked for. This could have
7714 * caused problems, but in practice existing hypervisors don't care.
7715 * To fix this, we will need to emulate the PFEC checking (on the L1
7716 * page tables), using walk_addr(), when injecting PFs to L1.
7717 */
7718 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7719 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7720 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7721 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7722
7723 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7724 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7725 if (!vmx->rdtscp_enabled)
7726 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7727 /* Take the following fields only from vmcs12 */
7728 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7729 if (nested_cpu_has(vmcs12,
7730 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7731 exec_control |= vmcs12->secondary_vm_exec_control;
7732
7733 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7734 /*
7735 * Translate L1 physical address to host physical
7736 * address for vmcs02. Keep the page pinned, so this
7737 * physical address remains valid. We keep a reference
7738 * to it so we can release it later.
7739 */
7740 if (vmx->nested.apic_access_page) /* shouldn't happen */
7741 nested_release_page(vmx->nested.apic_access_page);
7742 vmx->nested.apic_access_page =
7743 nested_get_page(vcpu, vmcs12->apic_access_addr);
7744 /*
7745 * If translation failed, no matter: This feature asks
7746 * to exit when accessing the given address, and if it
7747 * can never be accessed, this feature won't do
7748 * anything anyway.
7749 */
7750 if (!vmx->nested.apic_access_page)
7751 exec_control &=
7752 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7753 else
7754 vmcs_write64(APIC_ACCESS_ADDR,
7755 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7756 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7757 exec_control |=
7758 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7759 vmcs_write64(APIC_ACCESS_ADDR,
7760 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7761 }
7762
7763 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7764 }
7765
7766
7767 /*
7768 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7769 * Some constant fields are set here by vmx_set_constant_host_state().
7770 * Other fields are different per CPU, and will be set later when
7771 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7772 */
a547c6db 7773 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7774
7775 /*
7776 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7777 * entry, but only if the current (host) sp changed from the value
7778 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7779 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7780 * here we just force the write to happen on entry.
7781 */
7782 vmx->host_rsp = 0;
7783
7784 exec_control = vmx_exec_control(vmx); /* L0's desires */
7785 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7786 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7787 exec_control &= ~CPU_BASED_TPR_SHADOW;
7788 exec_control |= vmcs12->cpu_based_vm_exec_control;
7789 /*
7790 * Merging of IO and MSR bitmaps not currently supported.
7791 * Rather, exit every time.
7792 */
7793 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7794 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7795 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7796
7797 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7798
7799 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7800 * bitwise-or of what L1 wants to trap for L2, and what we want to
7801 * trap. Note that CR0.TS also needs updating - we do this later.
7802 */
7803 update_exception_bitmap(vcpu);
7804 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7805 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7806
8049d651
NHE		 7807 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7808 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7809 * bits are further modified by vmx_set_efer() below.
7810 */
f4124500 7811 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7812
7813 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7814 * emulated by vmx_set_efer(), below.
7815 */
2961e876 7816 vm_entry_controls_init(vmx,
8049d651
NHE		 7817 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7818 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7819 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7820
44811c02 7821 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7822 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7823 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7824 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7825 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7826
7827
7828 set_cr4_guest_host_mask(vmx);
7829
27fc51b2
NHE		 7830 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7831 vmcs_write64(TSC_OFFSET,
7832 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7833 else
7834 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7835
7836 if (enable_vpid) {
7837 /*
7838 * Trivially support vpid by letting L2s share their parent
7839 * L1's vpid. TODO: move to a more elaborate solution, giving
7840 * each L2 its own vpid and exposing the vpid feature to L1.
7841 */
7842 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7843 vmx_flush_tlb(vcpu);
7844 }
7845
155a97a3
NHE		 7846 if (nested_cpu_has_ept(vmcs12)) {
7847 kvm_mmu_unload(vcpu);
7848 nested_ept_init_mmu_context(vcpu);
7849 }
7850
fe3ef05c
NHE		 7851 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7852 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7853 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7854 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7855 else
7856 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7857 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7858 vmx_set_efer(vcpu, vcpu->arch.efer);
7859
7860 /*
7861 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7862 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7863 * The CR0_READ_SHADOW is what L2 should have expected to read given
7864 * the specifications by L1; It's not enough to take
7865 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7866 * have more bits than L1 expected.
7867 */
7868 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7869 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7870
7871 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7872 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7873
7874 /* shadow page tables on either EPT or shadow page tables */
7875 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7876 kvm_mmu_reset_context(vcpu);
7877
feaf0c7d
GN		 7878 if (!enable_ept)
7879 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7880
3633cfc3
NHE		 7881 /*
7882 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7883 */
7884 if (enable_ept) {
7885 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7886 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7887 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7888 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7889 }
7890
fe3ef05c
NHE		 7891 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7892 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7893}
7894
cd232ad0
NHE		 7895/*
7896 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7897 * for running an L2 nested guest.
7898 */
7899static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7900{
7901 struct vmcs12 *vmcs12;
7902 struct vcpu_vmx *vmx = to_vmx(vcpu);
7903 int cpu;
7904 struct loaded_vmcs *vmcs02;
384bb783 7905 bool ia32e;
cd232ad0
NHE		 7906
7907 if (!nested_vmx_check_permission(vcpu) ||
7908 !nested_vmx_check_vmcs12(vcpu))
7909 return 1;
7910
7911 skip_emulated_instruction(vcpu);
7912 vmcs12 = get_vmcs12(vcpu);
7913
012f83cb
AG		 7914 if (enable_shadow_vmcs)
7915 copy_shadow_to_vmcs12(vmx);
7916
7c177938
NHE		 7917 /*
7918 * The nested entry process starts with enforcing various prerequisites
7919 * on vmcs12 as required by the Intel SDM, and act appropriately when
7920 * they fail: As the SDM explains, some conditions should cause the
7921 * instruction to fail, while others will cause the instruction to seem
7922 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7923 * To speed up the normal (success) code path, we should avoid checking
7924 * for misconfigurations which will anyway be caught by the processor
7925 * when using the merged vmcs02.
7926 */
7927 if (vmcs12->launch_state == launch) {
7928 nested_vmx_failValid(vcpu,
7929 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7930 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7931 return 1;
7932 }
7933
6dfacadd
JK		 7934 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7935 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7936 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7937 return 1;
7938 }
7939
7c177938
NHE		 7940 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7941 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7942 /*TODO: Also verify bits beyond physical address width are 0*/
7943 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7944 return 1;
7945 }
7946
7947 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7948 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7949 /*TODO: Also verify bits beyond physical address width are 0*/
7950 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7951 return 1;
7952 }
7953
7954 if (vmcs12->vm_entry_msr_load_count > 0 ||
7955 vmcs12->vm_exit_msr_load_count > 0 ||
7956 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7957 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7958 __func__);
7c177938
NHE		 7959 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7960 return 1;
7961 }
7962
7963 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7964 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7965 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7966 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7967 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7968 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7969 !vmx_control_verify(vmcs12->vm_exit_controls,
7970 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7971 !vmx_control_verify(vmcs12->vm_entry_controls,
7972 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7973 {
7974 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7975 return 1;
7976 }
7977
7978 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7979 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7980 nested_vmx_failValid(vcpu,
7981 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7982 return 1;
7983 }
7984
92fbc7b1 7985 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 7986 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7987 nested_vmx_entry_failure(vcpu, vmcs12,
7988 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7989 return 1;
7990 }
7991 if (vmcs12->vmcs_link_pointer != -1ull) {
7992 nested_vmx_entry_failure(vcpu, vmcs12,
7993 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7994 return 1;
7995 }
7996
384bb783 7997 /*
cb0c8cda 7998 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7999 * are performed on the field for the IA32_EFER MSR:
8000 * - Bits reserved in the IA32_EFER MSR must be 0.
8001 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8002 * the IA-32e mode guest VM-exit control. It must also be identical
8003 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8004 * CR0.PG) is 1.
8005 */
8006 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8007 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8008 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8009 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8010 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8011 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8012 nested_vmx_entry_failure(vcpu, vmcs12,
8013 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8014 return 1;
8015 }
8016 }
8017
8018 /*
8019 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8020 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8021 * the values of the LMA and LME bits in the field must each be that of
8022 * the host address-space size VM-exit control.
8023 */
8024 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8025 ia32e = (vmcs12->vm_exit_controls &
8026 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8027 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8028 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8029 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8030 nested_vmx_entry_failure(vcpu, vmcs12,
8031 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8032 return 1;
8033 }
8034 }
8035
7c177938
NHE		 8036 /*
8037 * We're finally done with prerequisite checking, and can start with
8038 * the nested entry.
8039 */
8040
cd232ad0
NHE		 8041 vmcs02 = nested_get_current_vmcs02(vmx);
8042 if (!vmcs02)
8043 return -ENOMEM;
8044
8045 enter_guest_mode(vcpu);
8046
8047 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8048
8049 cpu = get_cpu();
8050 vmx->loaded_vmcs = vmcs02;
8051 vmx_vcpu_put(vcpu);
8052 vmx_vcpu_load(vcpu, cpu);
8053 vcpu->cpu = cpu;
8054 put_cpu();
8055
36c3cc42
JK		 8056 vmx_segment_cache_clear(vmx);
8057
cd232ad0
NHE		 8058 vmcs12->launch_state = 1;
8059
8060 prepare_vmcs02(vcpu, vmcs12);
8061
6dfacadd
JK		 8062 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8063 return kvm_emulate_halt(vcpu);
8064
7af40ad3
JK		 8065 vmx->nested.nested_run_pending = 1;
8066
cd232ad0
NHE		 8067 /*
8068 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8069 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8070 * returned as far as L1 is concerned. It will only return (and set
8071 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8072 */
8073 return 1;
8074}
8075
4704d0be
NHE		 8076/*
8077 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8078 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8079 * This function returns the new value we should put in vmcs12.guest_cr0.
8080 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8081 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8082 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8083 * didn't trap the bit, because if L1 did, so would L0).
8084 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8085 * been modified by L2, and L1 knows it. So just leave the old value of
8086 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8087 * isn't relevant, because if L0 traps this bit it can set it to anything.
8088 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8089 * changed these bits, and therefore they need to be updated, but L0
8090 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8091 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8092 */
8093static inline unsigned long
8094vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8095{
8096 return
8097 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8098 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8099 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8100 vcpu->arch.cr0_guest_owned_bits));
8101}
8102
8103static inline unsigned long
8104vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8105{
8106 return
8107 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8108 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8109 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8110 vcpu->arch.cr4_guest_owned_bits));
8111}
8112
5f3d5799
JK		 8113static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8114 struct vmcs12 *vmcs12)
8115{
8116 u32 idt_vectoring;
8117 unsigned int nr;
8118
851eb667 8119 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8120 nr = vcpu->arch.exception.nr;
8121 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8122
8123 if (kvm_exception_is_soft(nr)) {
8124 vmcs12->vm_exit_instruction_len =
8125 vcpu->arch.event_exit_inst_len;
8126 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8127 } else
8128 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8129
8130 if (vcpu->arch.exception.has_error_code) {
8131 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8132 vmcs12->idt_vectoring_error_code =
8133 vcpu->arch.exception.error_code;
8134 }
8135
8136 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8137 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8138 vmcs12->idt_vectoring_info_field =
8139 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8140 } else if (vcpu->arch.interrupt.pending) {
8141 nr = vcpu->arch.interrupt.nr;
8142 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8143
8144 if (vcpu->arch.interrupt.soft) {
8145 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8146 vmcs12->vm_entry_instruction_len =
8147 vcpu->arch.event_exit_inst_len;
8148 } else
8149 idt_vectoring |= INTR_TYPE_EXT_INTR;
8150
8151 vmcs12->idt_vectoring_info_field = idt_vectoring;
8152 }
8153}
8154
b6b8a145
JK		 8155static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8156{
8157 struct vcpu_vmx *vmx = to_vmx(vcpu);
8158
f4124500
JK		 8159 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8160 vmx->nested.preemption_timer_expired) {
8161 if (vmx->nested.nested_run_pending)
8162 return -EBUSY;
8163 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8164 return 0;
8165 }
8166
b6b8a145 8167 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8168 if (vmx->nested.nested_run_pending ||
8169 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8170 return -EBUSY;
8171 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8172 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8173 INTR_INFO_VALID_MASK, 0);
8174 /*
8175 * The NMI-triggered VM exit counts as injection:
8176 * clear this one and block further NMIs.
8177 */
8178 vcpu->arch.nmi_pending = 0;
8179 vmx_set_nmi_mask(vcpu, true);
8180 return 0;
8181 }
8182
8183 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8184 nested_exit_on_intr(vcpu)) {
8185 if (vmx->nested.nested_run_pending)
8186 return -EBUSY;
8187 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8188 }
8189
8190 return 0;
8191}
8192
f4124500
JK		 8193static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8194{
8195 ktime_t remaining =
8196 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8197 u64 value;
8198
8199 if (ktime_to_ns(remaining) <= 0)
8200 return 0;
8201
8202 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8203 do_div(value, 1000000);
8204 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8205}
8206
4704d0be
NHE		 8207/*
8208 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8209 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8210 * and this function updates it to reflect the changes to the guest state while
8211 * L2 was running (and perhaps made some exits which were handled directly by L0
8212 * without going back to L1), and to reflect the exit reason.
8213 * Note that we do not have to copy here all VMCS fields, just those that
8214 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8215 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8216 * which already writes to vmcs12 directly.
8217 */
533558bc
JK		 8218static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8219 u32 exit_reason, u32 exit_intr_info,
8220 unsigned long exit_qualification)
4704d0be
NHE		 8221{
8222 /* update guest state fields: */
8223 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8224 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8225
8226 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8227 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8228 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8229 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8230
8231 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8232 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8233 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8234 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8235 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8236 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8237 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8238 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8239 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8240 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8241 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8242 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8243 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8244 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8245 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8246 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8247 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8248 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8249 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8250 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8251 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8252 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8253 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8254 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8255 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8256 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8257 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8258 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8259 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8260 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8261 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8262 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8263 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8264 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8265 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8266 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8267
4704d0be
NHE		 8268 vmcs12->guest_interruptibility_info =
8269 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8270 vmcs12->guest_pending_dbg_exceptions =
8271 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8272 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8273 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8274 else
8275 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8276
f4124500
JK		 8277 if (nested_cpu_has_preemption_timer(vmcs12)) {
8278 if (vmcs12->vm_exit_controls &
8279 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8280 vmcs12->vmx_preemption_timer_value =
8281 vmx_get_preemption_timer_value(vcpu);
8282 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8283 }
7854cbca 8284
3633cfc3
NHE		 8285 /*
8286 * In some cases (usually, nested EPT), L2 is allowed to change its
8287 * own CR3 without exiting. If it has changed it, we must keep it.
8288 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8289 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8290 *
8291 * Additionally, restore L2's PDPTR to vmcs12.
8292 */
8293 if (enable_ept) {
8294 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8295 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8296 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8297 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8298 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8299 }
8300
c18911a2
JK		 8301 vmcs12->vm_entry_controls =
8302 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8303 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8304
4704d0be
NHE		 8305 /* TODO: These cannot have changed unless we have MSR bitmaps and
8306 * the relevant bit asks not to trap the change */
8307 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8308 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8309 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8310 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8311 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8312 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8313 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8314 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8315
8316 /* update exit information fields: */
8317
533558bc
JK		 8318 vmcs12->vm_exit_reason = exit_reason;
8319 vmcs12->exit_qualification = exit_qualification;
4704d0be 8320
533558bc 8321 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8322 if ((vmcs12->vm_exit_intr_info &
8323 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8324 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8325 vmcs12->vm_exit_intr_error_code =
8326 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8327 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8328 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8329 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8330
5f3d5799
JK		 8331 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8332 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8333 * instead of reading the real value. */
4704d0be 8334 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8335
8336 /*
8337 * Transfer the event that L0 or L1 may wanted to inject into
8338 * L2 to IDT_VECTORING_INFO_FIELD.
8339 */
8340 vmcs12_save_pending_event(vcpu, vmcs12);
8341 }
8342
8343 /*
8344 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8345 * preserved above and would only end up incorrectly in L1.
8346 */
8347 vcpu->arch.nmi_injected = false;
8348 kvm_clear_exception_queue(vcpu);
8349 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8350}
8351
8352/*
8353 * A part of what we need to when the nested L2 guest exits and we want to
8354 * run its L1 parent, is to reset L1's guest state to the host state specified
8355 * in vmcs12.
8356 * This function is to be called not only on normal nested exit, but also on
8357 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8358 * Failures During or After Loading Guest State").
8359 * This function should be called when the active VMCS is L1's (vmcs01).
8360 */
733568f9
JK		 8361static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8362 struct vmcs12 *vmcs12)
4704d0be 8363{
21feb4eb
ACL		 8364 struct kvm_segment seg;
8365
4704d0be
NHE		 8366 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8367 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8368 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8369 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8370 else
8371 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8372 vmx_set_efer(vcpu, vcpu->arch.efer);
8373
8374 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8375 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8376 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8377 /*
8378 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8379 * actually changed, because it depends on the current state of
8380 * fpu_active (which may have changed).
8381 * Note that vmx_set_cr0 refers to efer set above.
8382 */
9e3e4dbf 8383 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8384 /*
8385 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8386 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8387 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8388 */
8389 update_exception_bitmap(vcpu);
8390 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8391 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8392
8393 /*
8394 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8395 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8396 */
8397 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8398 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8399
29bf08f1 8400 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8401
4704d0be
NHE		 8402 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8403 kvm_mmu_reset_context(vcpu);
8404
feaf0c7d
GN		 8405 if (!enable_ept)
8406 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8407
4704d0be
NHE		 8408 if (enable_vpid) {
8409 /*
8410 * Trivially support vpid by letting L2s share their parent
8411 * L1's vpid. TODO: move to a more elaborate solution, giving
8412 * each L2 its own vpid and exposing the vpid feature to L1.
8413 */
8414 vmx_flush_tlb(vcpu);
8415 }
8416
8417
8418 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8419 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8420 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8421 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8422 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8423
44811c02 8424 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8425 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8426 vcpu->arch.pat = vmcs12->host_ia32_pat;
8427 }
4704d0be
NHE		 8428 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8429 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8430 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8431
21feb4eb
ACL		 8432 /* Set L1 segment info according to Intel SDM
8433 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8434 seg = (struct kvm_segment) {
8435 .base = 0,
8436 .limit = 0xFFFFFFFF,
8437 .selector = vmcs12->host_cs_selector,
8438 .type = 11,
8439 .present = 1,
8440 .s = 1,
8441 .g = 1
8442 };
8443 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8444 seg.l = 1;
8445 else
8446 seg.db = 1;
8447 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8448 seg = (struct kvm_segment) {
8449 .base = 0,
8450 .limit = 0xFFFFFFFF,
8451 .type = 3,
8452 .present = 1,
8453 .s = 1,
8454 .db = 1,
8455 .g = 1
8456 };
8457 seg.selector = vmcs12->host_ds_selector;
8458 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8459 seg.selector = vmcs12->host_es_selector;
8460 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8461 seg.selector = vmcs12->host_ss_selector;
8462 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8463 seg.selector = vmcs12->host_fs_selector;
8464 seg.base = vmcs12->host_fs_base;
8465 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8466 seg.selector = vmcs12->host_gs_selector;
8467 seg.base = vmcs12->host_gs_base;
8468 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8469 seg = (struct kvm_segment) {
205befd9 8470 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8471 .limit = 0x67,
8472 .selector = vmcs12->host_tr_selector,
8473 .type = 11,
8474 .present = 1
8475 };
8476 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8477
503cd0c5
JK		 8478 kvm_set_dr(vcpu, 7, 0x400);
8479 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8480}
8481
8482/*
8483 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8484 * and modify vmcs12 to make it see what it would expect to see there if
8485 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8486 */
533558bc
JK		 8487static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8488 u32 exit_intr_info,
8489 unsigned long exit_qualification)
4704d0be
NHE		 8490{
8491 struct vcpu_vmx *vmx = to_vmx(vcpu);
8492 int cpu;
8493 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8494
5f3d5799
JK		 8495 /* trying to cancel vmlaunch/vmresume is a bug */
8496 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8497
4704d0be 8498 leave_guest_mode(vcpu);
533558bc
JK		 8499 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8500 exit_qualification);
4704d0be 8501
542060ea
JK		 8502 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8503 vmcs12->exit_qualification,
8504 vmcs12->idt_vectoring_info_field,
8505 vmcs12->vm_exit_intr_info,
8506 vmcs12->vm_exit_intr_error_code,
8507 KVM_ISA_VMX);
4704d0be
NHE		 8508
8509 cpu = get_cpu();
8510 vmx->loaded_vmcs = &vmx->vmcs01;
8511 vmx_vcpu_put(vcpu);
8512 vmx_vcpu_load(vcpu, cpu);
8513 vcpu->cpu = cpu;
8514 put_cpu();
8515
2961e876
GN		 8516 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8517 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8518 vmx_segment_cache_clear(vmx);
8519
4704d0be
NHE		 8520 /* if no vmcs02 cache requested, remove the one we used */
8521 if (VMCS02_POOL_SIZE == 0)
8522 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8523
8524 load_vmcs12_host_state(vcpu, vmcs12);
8525
27fc51b2 8526 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8527 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8528
8529 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8530 vmx->host_rsp = 0;
8531
8532 /* Unpin physical memory we referred to in vmcs02 */
8533 if (vmx->nested.apic_access_page) {
8534 nested_release_page(vmx->nested.apic_access_page);
8535 vmx->nested.apic_access_page = 0;
8536 }
8537
8538 /*
8539 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8540 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8541 * success or failure flag accordingly.
8542 */
8543 if (unlikely(vmx->fail)) {
8544 vmx->fail = 0;
8545 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8546 } else
8547 nested_vmx_succeed(vcpu);
012f83cb
AG		 8548 if (enable_shadow_vmcs)
8549 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8550
8551 /* in case we halted in L2 */
8552 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8553}
8554
42124925
JK		 8555/*
8556 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8557 */
8558static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8559{
8560 if (is_guest_mode(vcpu))
533558bc 8561 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8562 free_nested(to_vmx(vcpu));
8563}
8564
7c177938
NHE		 8565/*
8566 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8567 * 23.7 "VM-entry failures during or after loading guest state" (this also
8568 * lists the acceptable exit-reason and exit-qualification parameters).
8569 * It should only be called before L2 actually succeeded to run, and when
8570 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8571 */
8572static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8573 struct vmcs12 *vmcs12,
8574 u32 reason, unsigned long qualification)
8575{
8576 load_vmcs12_host_state(vcpu, vmcs12);
8577 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8578 vmcs12->exit_qualification = qualification;
8579 nested_vmx_succeed(vcpu);
012f83cb
AG		 8580 if (enable_shadow_vmcs)
8581 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8582}
8583
8a76d7f2
JR		 8584static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8585 struct x86_instruction_info *info,
8586 enum x86_intercept_stage stage)
8587{
8588 return X86EMUL_CONTINUE;
8589}
8590
cbdd1bea 8591static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8592 .cpu_has_kvm_support = cpu_has_kvm_support,
8593 .disabled_by_bios = vmx_disabled_by_bios,
8594 .hardware_setup = hardware_setup,
8595 .hardware_unsetup = hardware_unsetup,
002c7f7c 8596 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8597 .hardware_enable = hardware_enable,
8598 .hardware_disable = hardware_disable,
04547156 8599 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8600
8601 .vcpu_create = vmx_create_vcpu,
8602 .vcpu_free = vmx_free_vcpu,
04d2cc77 8603 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8604
04d2cc77 8605 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8606 .vcpu_load = vmx_vcpu_load,
8607 .vcpu_put = vmx_vcpu_put,
8608
c8639010 8609 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8610 .get_msr = vmx_get_msr,
8611 .set_msr = vmx_set_msr,
8612 .get_segment_base = vmx_get_segment_base,
8613 .get_segment = vmx_get_segment,
8614 .set_segment = vmx_set_segment,
2e4d2653 8615 .get_cpl = vmx_get_cpl,
6aa8b732 8616 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8617 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8618 .decache_cr3 = vmx_decache_cr3,
25c4c276 8619 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8620 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8621 .set_cr3 = vmx_set_cr3,
8622 .set_cr4 = vmx_set_cr4,
6aa8b732 8623 .set_efer = vmx_set_efer,
6aa8b732
AK		 8624 .get_idt = vmx_get_idt,
8625 .set_idt = vmx_set_idt,
8626 .get_gdt = vmx_get_gdt,
8627 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8628 .get_dr6 = vmx_get_dr6,
8629 .set_dr6 = vmx_set_dr6,
020df079 8630 .set_dr7 = vmx_set_dr7,
5fdbf976 8631 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8632 .get_rflags = vmx_get_rflags,
8633 .set_rflags = vmx_set_rflags,
ebcbab4c 8634 .fpu_activate = vmx_fpu_activate,
02daab21 8635 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8636
8637 .tlb_flush = vmx_flush_tlb,
6aa8b732 8638
6aa8b732 8639 .run = vmx_vcpu_run,
6062d012 8640 .handle_exit = vmx_handle_exit,
6aa8b732 8641 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8642 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8643 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8644 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8645 .set_irq = vmx_inject_irq,
95ba8273 8646 .set_nmi = vmx_inject_nmi,
298101da 8647 .queue_exception = vmx_queue_exception,
b463a6f7 8648 .cancel_injection = vmx_cancel_injection,
78646121 8649 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8650 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8651 .get_nmi_mask = vmx_get_nmi_mask,
8652 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8653 .enable_nmi_window = enable_nmi_window,
8654 .enable_irq_window = enable_irq_window,
8655 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8656 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8657 .vm_has_apicv = vmx_vm_has_apicv,
8658 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8659 .hwapic_irr_update = vmx_hwapic_irr_update,
8660 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8661 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8662 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8663
cbc94022 8664 .set_tss_addr = vmx_set_tss_addr,
67253af5 8665 .get_tdp_level = get_ept_level,
4b12f0de 8666 .get_mt_mask = vmx_get_mt_mask,
229456fc 8667
586f9607 8668 .get_exit_info = vmx_get_exit_info,
586f9607 8669
17cc3935 8670 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8671
8672 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8673
8674 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8675 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8676
8677 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8678
8679 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8680
4051b188 8681 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8682 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8683 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8684 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8685 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8686 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8687
8688 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8689
8690 .check_intercept = vmx_check_intercept,
a547c6db 8691 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8692 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8693
8694 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8695};
8696
8697static int __init vmx_init(void)
8698{
8d14695f 8699 int r, i, msr;
26bb0981
AK		 8700
8701 rdmsrl_safe(MSR_EFER, &host_efer);
8702
8703 for (i = 0; i < NR_VMX_MSR; ++i)
8704 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8705
3e7c73e9 8706 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8707 if (!vmx_io_bitmap_a)
8708 return -ENOMEM;
8709
2106a548
GC		 8710 r = -ENOMEM;
8711
3e7c73e9 8712 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8713 if (!vmx_io_bitmap_b)
fdef3ad1 8714 goto out;
fdef3ad1 8715
5897297b 8716 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8717 if (!vmx_msr_bitmap_legacy)
25c5f225 8718 goto out1;
2106a548 8719
8d14695f
YZ		 8720 vmx_msr_bitmap_legacy_x2apic =
8721 (unsigned long *)__get_free_page(GFP_KERNEL);
8722 if (!vmx_msr_bitmap_legacy_x2apic)
8723 goto out2;
25c5f225 8724
5897297b 8725 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8726 if (!vmx_msr_bitmap_longmode)
8d14695f 8727 goto out3;
2106a548 8728
8d14695f
YZ		 8729 vmx_msr_bitmap_longmode_x2apic =
8730 (unsigned long *)__get_free_page(GFP_KERNEL);
8731 if (!vmx_msr_bitmap_longmode_x2apic)
8732 goto out4;
4607c2d7
AG		 8733 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8734 if (!vmx_vmread_bitmap)
8735 goto out5;
8736
8737 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8738 if (!vmx_vmwrite_bitmap)
8739 goto out6;
8740
8741 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8742 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8743 /* shadowed read/write fields */
8744 for (i = 0; i < max_shadow_read_write_fields; i++) {
8745 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8746 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8747 }
8748 /* shadowed read only fields */
8749 for (i = 0; i < max_shadow_read_only_fields; i++)
8750 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8751
fdef3ad1
HQ		 8752 /*
8753 * Allow direct access to the PC debug port (it is often used for I/O
8754 * delays, but the vmexits simply slow things down).
8755 */
3e7c73e9
AK		 8756 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8757 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8758
3e7c73e9 8759 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8760
5897297b
AK		 8761 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8762 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8763
2384d2b3
SY		 8764 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8765
0ee75bea
AK		 8766 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8767 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8768 if (r)
4607c2d7 8769 goto out7;
25c5f225 8770
8f536b76
ZY		 8771#ifdef CONFIG_KEXEC
8772 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8773 crash_vmclear_local_loaded_vmcss);
8774#endif
8775
5897297b
AK		 8776 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8777 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8778 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8779 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8780 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8781 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8782 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8783
8d14695f
YZ		 8784 memcpy(vmx_msr_bitmap_legacy_x2apic,
8785 vmx_msr_bitmap_legacy, PAGE_SIZE);
8786 memcpy(vmx_msr_bitmap_longmode_x2apic,
8787 vmx_msr_bitmap_longmode, PAGE_SIZE);
8788
01e439be 8789 if (enable_apicv) {
8d14695f
YZ		 8790 for (msr = 0x800; msr <= 0x8ff; msr++)
8791 vmx_disable_intercept_msr_read_x2apic(msr);
8792
8793 /* According SDM, in x2apic mode, the whole id reg is used.
8794 * But in KVM, it only use the highest eight bits. Need to
8795 * intercept it */
8796 vmx_enable_intercept_msr_read_x2apic(0x802);
8797 /* TMCCT */
8798 vmx_enable_intercept_msr_read_x2apic(0x839);
8799 /* TPR */
8800 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8801 /* EOI */
8802 vmx_disable_intercept_msr_write_x2apic(0x80b);
8803 /* SELF-IPI */
8804 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8805 }
fdef3ad1 8806
089d034e 8807 if (enable_ept) {
3f6d8c8a
XH		 8808 kvm_mmu_set_mask_ptes(0ull,
8809 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8810 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8811 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8812 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8813 kvm_enable_tdp();
8814 } else
8815 kvm_disable_tdp();
1439442c 8816
fdef3ad1
HQ		 8817 return 0;
8818
4607c2d7
AG		 8819out7:
8820 free_page((unsigned long)vmx_vmwrite_bitmap);
8821out6:
8822 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8823out5:
8824 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8825out4:
5897297b 8826 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8827out3:
8828 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8829out2:
5897297b 8830 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8831out1:
3e7c73e9 8832 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8833out:
3e7c73e9 8834 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8835 return r;
6aa8b732
AK		 8836}
8837
8838static void __exit vmx_exit(void)
8839{
8d14695f
YZ		 8840 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8841 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8842 free_page((unsigned long)vmx_msr_bitmap_legacy);
8843 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8844 free_page((unsigned long)vmx_io_bitmap_b);
8845 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8846 free_page((unsigned long)vmx_vmwrite_bitmap);
8847 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8848
8f536b76
ZY		 8849#ifdef CONFIG_KEXEC
8850 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8851 synchronize_rcu();
8852#endif
8853
cb498ea2 8854 kvm_exit();
6aa8b732
AK		 8855}
8856
8857module_init(vmx_init)
8858module_exit(vmx_exit)
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