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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20150706.0' into...
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
d49b6836 29#include "qemu/error-report.h"
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
2001d0cd 48#include "exec/address-spaces.h"
0d09e41a 49#include "hw/xen/xen.h"
0d09e41a 50#include "hw/i386/apic_internal.h"
bdeec802
IM		 51#endif
52
5e891bf8
EH		 53
54/* Cache topology CPUID constants: */
55
56/* CPUID Leaf 2 Descriptors */
57
58#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
59#define CPUID_2_L1I_32KB_8WAY_64B 0x30
60#define CPUID_2_L2_2MB_8WAY_64B 0x7d
61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
135/* No L3 cache: */
136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
140
141/* TLB definitions: */
142
143#define L1_DTLB_2M_ASSOC 1
144#define L1_DTLB_2M_ENTRIES 255
145#define L1_DTLB_4K_ASSOC 1
146#define L1_DTLB_4K_ENTRIES 255
147
148#define L1_ITLB_2M_ASSOC 1
149#define L1_ITLB_2M_ENTRIES 255
150#define L1_ITLB_4K_ASSOC 1
151#define L1_ITLB_4K_ENTRIES 255
152
153#define L2_DTLB_2M_ASSOC 0 /* disabled */
154#define L2_DTLB_2M_ENTRIES 0 /* disabled */
155#define L2_DTLB_4K_ASSOC 4
156#define L2_DTLB_4K_ENTRIES 512
157
158#define L2_ITLB_2M_ASSOC 0 /* disabled */
159#define L2_ITLB_2M_ENTRIES 0 /* disabled */
160#define L2_ITLB_4K_ASSOC 4
161#define L2_ITLB_4K_ENTRIES 512
162
163
164
99b88a17
IM		 165static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
166 uint32_t vendor2, uint32_t vendor3)
167{
168 int i;
169 for (i = 0; i < 4; i++) {
170 dst[i] = vendor1 >> (8 * i);
171 dst[i + 4] = vendor2 >> (8 * i);
172 dst[i + 8] = vendor3 >> (8 * i);
173 }
174 dst[CPUID_VENDOR_SZ] = '\0';
175}
176
c6dc6f63
AP		 177/* feature flags taken from "Intel Processor Identification and the CPUID
178 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
179 * between feature naming conventions, aliases may be added.
180 */
181static const char *feature_name[] = {
182 "fpu", "vme", "de", "pse",
183 "tsc", "msr", "pae", "mce",
184 "cx8", "apic", NULL, "sep",
185 "mtrr", "pge", "mca", "cmov",
186 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
187 NULL, "ds" /* Intel dts */, "acpi", "mmx",
188 "fxsr", "sse", "sse2", "ss",
189 "ht" /* Intel htt */, "tm", "ia64", "pbe",
190};
191static const char *ext_feature_name[] = {
f370be3c 192 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 193 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 194 "tm2", "ssse3", "cid", NULL,
e117f772 195 "fma", "cx16", "xtpr", "pdcm",
434acb81 196 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 197 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 198 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 199 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 200};
3b671a40
EH		 201/* Feature names that are already defined on feature_name[] but are set on
202 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
203 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
204 * if and only if CPU vendor is AMD.
205 */
c6dc6f63 206static const char *ext2_feature_name[] = {
3b671a40
EH		 207 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
208 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
209 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
210 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
211 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
212 "nx|xd", NULL, "mmxext", NULL /* mmx */,
213 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 214 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 215};
216static const char *ext3_feature_name[] = {
217 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
218 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 219 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 220 "skinit", "wdt", NULL, "lwp",
221 "fma4", "tce", NULL, "nodeid_msr",
222 NULL, "tbm", "topoext", "perfctr_core",
223 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 224 NULL, NULL, NULL, NULL,
225};
226
89e49c8b
EH		 227static const char *ext4_feature_name[] = {
228 NULL, NULL, "xstore", "xstore-en",
229 NULL, NULL, "xcrypt", "xcrypt-en",
230 "ace2", "ace2-en", "phe", "phe-en",
231 "pmm", "pmm-en", NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235 NULL, NULL, NULL, NULL,
236};
237
c6dc6f63 238static const char *kvm_feature_name[] = {
c3d39807 239 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 240 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
8248c36a 245 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 246 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 247};
248
296acb64
JR		 249static const char *svm_feature_name[] = {
250 "npt", "lbrv", "svm_lock", "nrip_save",
251 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
252 NULL, NULL, "pause_filter", NULL,
253 "pfthreshold", NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257 NULL, NULL, NULL, NULL,
258};
259
a9321a4d 260static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 261 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 262 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 263 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
264 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 265};
266
303752a9
MT		 267static const char *cpuid_apm_edx_feature_name[] = {
268 NULL, NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 "invtsc", NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275 NULL, NULL, NULL, NULL,
276};
277
0bb0b2d2
PB		 278static const char *cpuid_xsave_feature_name[] = {
279 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286 NULL, NULL, NULL, NULL,
287};
288
621626ce
EH		 289#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
290#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
291 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
292#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
293 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
294 CPUID_PSE36 | CPUID_FXSR)
295#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
296#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
297 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
298 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
299 CPUID_PAE | CPUID_SEP | CPUID_APIC)
300
301#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
302 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
303 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
304 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
305 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
306 /* partly implemented:
307 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
308 /* missing:
309 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
310#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
311 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
312 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
313 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
314 /* missing:
315 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
316 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
317 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
318 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
319 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
320 CPUID_EXT_RDRAND */
321
322#ifdef TARGET_X86_64
323#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
324#else
325#define TCG_EXT2_X86_64_FEATURES 0
326#endif
327
328#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
329 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
330 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
331 TCG_EXT2_X86_64_FEATURES)
332#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
333 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
334#define TCG_EXT4_FEATURES 0
335#define TCG_SVM_FEATURES 0
336#define TCG_KVM_FEATURES 0
337#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
338 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
339 /* missing:
340 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
341 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
342 CPUID_7_0_EBX_RDSEED */
303752a9 343#define TCG_APM_FEATURES 0
621626ce
EH		 344
345
5ef57876
EH		 346typedef struct FeatureWordInfo {
347 const char **feat_names;
04d104b6
EH		 348 uint32_t cpuid_eax; /* Input EAX for CPUID */
349 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
350 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
351 int cpuid_reg; /* output register (R_* constant) */
37ce3522 352 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 353 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 354} FeatureWordInfo;
355
356static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 357 [FEAT_1_EDX] = {
358 .feat_names = feature_name,
359 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 360 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 361 },
362 [FEAT_1_ECX] = {
363 .feat_names = ext_feature_name,
364 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 365 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 366 },
367 [FEAT_8000_0001_EDX] = {
368 .feat_names = ext2_feature_name,
369 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 370 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 371 },
372 [FEAT_8000_0001_ECX] = {
373 .feat_names = ext3_feature_name,
374 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 375 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 376 },
89e49c8b
EH		 377 [FEAT_C000_0001_EDX] = {
378 .feat_names = ext4_feature_name,
379 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 380 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 381 },
bffd67b0
EH		 382 [FEAT_KVM] = {
383 .feat_names = kvm_feature_name,
384 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 385 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 386 },
387 [FEAT_SVM] = {
388 .feat_names = svm_feature_name,
389 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 390 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 391 },
392 [FEAT_7_0_EBX] = {
393 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 394 .cpuid_eax = 7,
395 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
396 .cpuid_reg = R_EBX,
37ce3522 397 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 398 },
303752a9
MT		 399 [FEAT_8000_0007_EDX] = {
400 .feat_names = cpuid_apm_edx_feature_name,
401 .cpuid_eax = 0x80000007,
402 .cpuid_reg = R_EDX,
403 .tcg_features = TCG_APM_FEATURES,
404 .unmigratable_flags = CPUID_APM_INVTSC,
405 },
0bb0b2d2
PB		 406 [FEAT_XSAVE] = {
407 .feat_names = cpuid_xsave_feature_name,
408 .cpuid_eax = 0xd,
409 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
410 .cpuid_reg = R_EAX,
411 .tcg_features = 0,
0bb0b2d2 412 },
5ef57876
EH		 413};
414
8e8aba50
EH		 415typedef struct X86RegisterInfo32 {
416 /* Name of register */
417 const char *name;
418 /* QAPI enum value register */
419 X86CPURegister32 qapi_enum;
420} X86RegisterInfo32;
421
422#define REGISTER(reg) \
5d371f41 423 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 424static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 425 REGISTER(EAX),
426 REGISTER(ECX),
427 REGISTER(EDX),
428 REGISTER(EBX),
429 REGISTER(ESP),
430 REGISTER(EBP),
431 REGISTER(ESI),
432 REGISTER(EDI),
433};
434#undef REGISTER
435
2560f19f
PB		 436typedef struct ExtSaveArea {
437 uint32_t feature, bits;
438 uint32_t offset, size;
439} ExtSaveArea;
440
441static const ExtSaveArea ext_save_areas[] = {
442 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 443 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 444 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
445 .offset = 0x3c0, .size = 0x40 },
446 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 447 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 448 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
449 .offset = 0x440, .size = 0x40 },
450 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
451 .offset = 0x480, .size = 0x200 },
452 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
453 .offset = 0x680, .size = 0x400 },
2560f19f 454};
8e8aba50 455
8b4beddc
EH		 456const char *get_register_name_32(unsigned int reg)
457{
31ccdde2 458 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 459 return NULL;
460 }
8e8aba50 461 return x86_reg_info_32[reg].name;
8b4beddc
EH		 462}
463
5fcca9ff
EH		 464/* KVM-specific features that are automatically added to all CPU models
465 * when KVM is enabled.
466 */
467static uint32_t kvm_default_features[FEATURE_WORDS] = {
468 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 469 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 470 (1 << KVM_FEATURE_CLOCKSOURCE2) |
471 (1 << KVM_FEATURE_ASYNC_PF) |
472 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 473 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 474 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 475 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 476};
dc59944b 477
136a7e9a
EH		 478/* Features that are not added by default to any CPU model when KVM is enabled.
479 */
480static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 481 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a 482 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
75d373ef 483 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
136a7e9a
EH		 484};
485
1cadaa94 486void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 487{
8fb4f821 488 kvm_default_features[w] &= ~features;
dc59944b
MT		 489}
490
75d373ef
EH		 491void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
492{
493 kvm_default_unset_features[w] &= ~features;
494}
495
84f1b92f
EH		 496/*
497 * Returns the set of feature flags that are supported and migratable by
498 * QEMU, for a given FeatureWord.
499 */
500static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
501{
502 FeatureWordInfo *wi = &feature_word_info[w];
503 uint32_t r = 0;
504 int i;
505
506 for (i = 0; i < 32; i++) {
507 uint32_t f = 1U << i;
508 /* If the feature name is unknown, it is not supported by QEMU yet */
509 if (!wi->feat_names[i]) {
510 continue;
511 }
512 /* Skip features known to QEMU, but explicitly marked as unmigratable */
513 if (wi->unmigratable_flags & f) {
514 continue;
515 }
516 r |= f;
517 }
518 return r;
519}
520
bb44e0d1
JK		 521void host_cpuid(uint32_t function, uint32_t count,
522 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 523{
a1fd24af
AL		 524 uint32_t vec[4];
525
526#ifdef __x86_64__
527 asm volatile("cpuid"
528 : "=a"(vec[0]), "=b"(vec[1]),
529 "=c"(vec[2]), "=d"(vec[3])
530 : "0"(function), "c"(count) : "cc");
c1f41226 531#elif defined(__i386__)
a1fd24af
AL		 532 asm volatile("pusha \n\t"
533 "cpuid \n\t"
534 "mov %%eax, 0(%2) \n\t"
535 "mov %%ebx, 4(%2) \n\t"
536 "mov %%ecx, 8(%2) \n\t"
537 "mov %%edx, 12(%2) \n\t"
538 "popa"
539 : : "a"(function), "c"(count), "S"(vec)
540 : "memory", "cc");
c1f41226
EH		 541#else
542 abort();
a1fd24af
AL		 543#endif
544
bdde476a 545 if (eax)
a1fd24af 546 *eax = vec[0];
bdde476a 547 if (ebx)
a1fd24af 548 *ebx = vec[1];
bdde476a 549 if (ecx)
a1fd24af 550 *ecx = vec[2];
bdde476a 551 if (edx)
a1fd24af 552 *edx = vec[3];
bdde476a 553}
c6dc6f63
AP		 554
555#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
556
557/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
558 * a substring. ex if !NULL points to the first char after a substring,
559 * otherwise the string is assumed to sized by a terminating nul.
560 * Return lexical ordering of *s1:*s2.
561 */
8f9d989c
CF		 562static int sstrcmp(const char *s1, const char *e1,
563 const char *s2, const char *e2)
c6dc6f63
AP		 564{
565 for (;;) {
566 if (!*s1 || !*s2 || *s1 != *s2)
567 return (*s1 - *s2);
568 ++s1, ++s2;
569 if (s1 == e1 && s2 == e2)
570 return (0);
571 else if (s1 == e1)
572 return (*s2);
573 else if (s2 == e2)
574 return (*s1);
575 }
576}
577
578/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
579 * '|' delimited (possibly empty) strings in which case search for a match
580 * within the alternatives proceeds left to right. Return 0 for success,
581 * non-zero otherwise.
582 */
583static int altcmp(const char *s, const char *e, const char *altstr)
584{
585 const char *p, *q;
586
587 for (q = p = altstr; ; ) {
588 while (*p && *p != '|')
589 ++p;
590 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
591 return (0);
592 if (!*p)
593 return (1);
594 else
595 q = ++p;
596 }
597}
598
599/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 600 * *pval and return true, otherwise return false
c6dc6f63 601 */
e41e0fc6
JK		 602static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
603 const char **featureset)
c6dc6f63
AP		 604{
605 uint32_t mask;
606 const char **ppc;
e41e0fc6 607 bool found = false;
c6dc6f63 608
e41e0fc6 609 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 610 if (*ppc && !altcmp(s, e, *ppc)) {
611 *pval |= mask;
e41e0fc6 612 found = true;
c6dc6f63 613 }
e41e0fc6
JK		 614 }
615 return found;
c6dc6f63
AP		 616}
617
5ef57876 618static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 619 FeatureWordArray words,
620 Error **errp)
c6dc6f63 621{
5ef57876
EH		 622 FeatureWord w;
623 for (w = 0; w < FEATURE_WORDS; w++) {
624 FeatureWordInfo *wi = &feature_word_info[w];
625 if (wi->feat_names &&
626 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
627 break;
628 }
629 }
630 if (w == FEATURE_WORDS) {
c00c94ab 631 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 632 }
c6dc6f63
AP		 633}
634
d940ee9b
EH		 635/* CPU class name definitions: */
636
637#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
638#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
639
640/* Return type name for a given CPU model name
641 * Caller is responsible for freeing the returned string.
642 */
643static char *x86_cpu_type_name(const char *model_name)
644{
645 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
646}
647
500050d1
AF		 648static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
649{
d940ee9b
EH		 650 ObjectClass *oc;
651 char *typename;
652
500050d1
AF		 653 if (cpu_model == NULL) {
654 return NULL;
655 }
656
d940ee9b
EH		 657 typename = x86_cpu_type_name(cpu_model);
658 oc = object_class_by_name(typename);
659 g_free(typename);
660 return oc;
500050d1
AF		 661}
662
d940ee9b 663struct X86CPUDefinition {
c6dc6f63
AP		 664 const char *name;
665 uint32_t level;
90e4b0c3
EH		 666 uint32_t xlevel;
667 uint32_t xlevel2;
99b88a17
IM		 668 /* vendor is zero-terminated, 12 character ASCII string */
669 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 670 int family;
671 int model;
672 int stepping;
0514ef2f 673 FeatureWordArray features;
c6dc6f63 674 char model_id[48];
787aaf57 675 bool cache_info_passthrough;
d940ee9b 676};
c6dc6f63 677
9576de75 678static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 679 {
680 .name = "qemu64",
681 .level = 4,
99b88a17 682 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 683 .family = 6,
f8e6a11a 684 .model = 6,
c6dc6f63 685 .stepping = 3,
0514ef2f 686 .features[FEAT_1_EDX] =
27861ecc 687 PPRO_FEATURES |
c6dc6f63 688 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 689 CPUID_PSE36,
0514ef2f 690 .features[FEAT_1_ECX] =
27861ecc 691 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 692 .features[FEAT_8000_0001_EDX] =
c6dc6f63 693 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 694 .features[FEAT_8000_0001_ECX] =
27861ecc 695 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 696 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
697 .xlevel = 0x8000000A,
c6dc6f63
AP		 698 },
699 {
700 .name = "phenom",
701 .level = 5,
99b88a17 702 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 703 .family = 16,
704 .model = 2,
705 .stepping = 3,
b9fc20bc 706 /* Missing: CPUID_HT */
0514ef2f 707 .features[FEAT_1_EDX] =
27861ecc 708 PPRO_FEATURES |
c6dc6f63 709 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 710 CPUID_PSE36 | CPUID_VME,
0514ef2f 711 .features[FEAT_1_ECX] =
27861ecc 712 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 713 CPUID_EXT_POPCNT,
0514ef2f 714 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 715 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
716 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 717 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 718 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
719 CPUID_EXT3_CR8LEG,
720 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
721 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 722 .features[FEAT_8000_0001_ECX] =
27861ecc 723 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 724 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 725 /* Missing: CPUID_SVM_LBRV */
0514ef2f 726 .features[FEAT_SVM] =
b9fc20bc 727 CPUID_SVM_NPT,
c6dc6f63
AP		 728 .xlevel = 0x8000001A,
729 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
730 },
731 {
732 .name = "core2duo",
733 .level = 10,
99b88a17 734 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 735 .family = 6,
736 .model = 15,
737 .stepping = 11,
b9fc20bc 738 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 739 .features[FEAT_1_EDX] =
27861ecc 740 PPRO_FEATURES |
c6dc6f63 741 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 742 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
743 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 744 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 745 .features[FEAT_1_ECX] =
27861ecc 746 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 747 CPUID_EXT_CX16,
0514ef2f 748 .features[FEAT_8000_0001_EDX] =
27861ecc 749 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 750 .features[FEAT_8000_0001_ECX] =
27861ecc 751 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 752 .xlevel = 0x80000008,
753 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
754 },
755 {
756 .name = "kvm64",
757 .level = 5,
99b88a17 758 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 759 .family = 15,
760 .model = 6,
761 .stepping = 1,
b3a4f0b1 762 /* Missing: CPUID_HT */
0514ef2f 763 .features[FEAT_1_EDX] =
b3a4f0b1 764 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
766 CPUID_PSE36,
767 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 768 .features[FEAT_1_ECX] =
27861ecc 769 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 770 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 771 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 772 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
773 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
774 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
775 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
776 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 777 .features[FEAT_8000_0001_ECX] =
27861ecc 778 0,
c6dc6f63
AP		 779 .xlevel = 0x80000008,
780 .model_id = "Common KVM processor"
781 },
c6dc6f63
AP		 782 {
783 .name = "qemu32",
784 .level = 4,
99b88a17 785 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 786 .family = 6,
f8e6a11a 787 .model = 6,
c6dc6f63 788 .stepping = 3,
0514ef2f 789 .features[FEAT_1_EDX] =
27861ecc 790 PPRO_FEATURES,
0514ef2f 791 .features[FEAT_1_ECX] =
27861ecc 792 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 793 .xlevel = 0x80000004,
c6dc6f63 794 },
eafaf1e5
AP		 795 {
796 .name = "kvm32",
797 .level = 5,
99b88a17 798 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 799 .family = 15,
800 .model = 6,
801 .stepping = 1,
0514ef2f 802 .features[FEAT_1_EDX] =
b3a4f0b1 803 PPRO_FEATURES | CPUID_VME |
eafaf1e5 804 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 805 .features[FEAT_1_ECX] =
27861ecc 806 CPUID_EXT_SSE3,
0514ef2f 807 .features[FEAT_8000_0001_ECX] =
27861ecc 808 0,
eafaf1e5
AP		 809 .xlevel = 0x80000008,
810 .model_id = "Common 32-bit KVM processor"
811 },
c6dc6f63
AP		 812 {
813 .name = "coreduo",
814 .level = 10,
99b88a17 815 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 816 .family = 6,
817 .model = 14,
818 .stepping = 8,
b9fc20bc 819 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 820 .features[FEAT_1_EDX] =
27861ecc 821 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 822 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
823 CPUID_SS,
824 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 825 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 826 .features[FEAT_1_ECX] =
e93abc14 827 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 828 .features[FEAT_8000_0001_EDX] =
27861ecc 829 CPUID_EXT2_NX,
c6dc6f63
AP		 830 .xlevel = 0x80000008,
831 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
832 },
833 {
834 .name = "486",
58012d66 835 .level = 1,
99b88a17 836 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 837 .family = 4,
b2a856d9 838 .model = 8,
c6dc6f63 839 .stepping = 0,
0514ef2f 840 .features[FEAT_1_EDX] =
27861ecc 841 I486_FEATURES,
c6dc6f63
AP		 842 .xlevel = 0,
843 },
844 {
845 .name = "pentium",
846 .level = 1,
99b88a17 847 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 848 .family = 5,
849 .model = 4,
850 .stepping = 3,
0514ef2f 851 .features[FEAT_1_EDX] =
27861ecc 852 PENTIUM_FEATURES,
c6dc6f63
AP		 853 .xlevel = 0,
854 },
855 {
856 .name = "pentium2",
857 .level = 2,
99b88a17 858 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 859 .family = 6,
860 .model = 5,
861 .stepping = 2,
0514ef2f 862 .features[FEAT_1_EDX] =
27861ecc 863 PENTIUM2_FEATURES,
c6dc6f63
AP		 864 .xlevel = 0,
865 },
866 {
867 .name = "pentium3",
868 .level = 2,
99b88a17 869 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 870 .family = 6,
871 .model = 7,
872 .stepping = 3,
0514ef2f 873 .features[FEAT_1_EDX] =
27861ecc 874 PENTIUM3_FEATURES,
c6dc6f63
AP		 875 .xlevel = 0,
876 },
877 {
878 .name = "athlon",
879 .level = 2,
99b88a17 880 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 881 .family = 6,
882 .model = 2,
883 .stepping = 3,
0514ef2f 884 .features[FEAT_1_EDX] =
27861ecc 885 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 886 CPUID_MCA,
0514ef2f 887 .features[FEAT_8000_0001_EDX] =
60032ac0 888 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 889 .xlevel = 0x80000008,
c6dc6f63
AP		 890 },
891 {
892 .name = "n270",
893 /* original is on level 10 */
894 .level = 5,
99b88a17 895 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 896 .family = 6,
897 .model = 28,
898 .stepping = 2,
b9fc20bc 899 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 900 .features[FEAT_1_EDX] =
27861ecc 901 PPRO_FEATURES |
b9fc20bc
EH		 902 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
903 CPUID_ACPI | CPUID_SS,
c6dc6f63 904 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 905 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
906 * CPUID_EXT_XTPR */
0514ef2f 907 .features[FEAT_1_ECX] =
27861ecc 908 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 909 CPUID_EXT_MOVBE,
0514ef2f 910 .features[FEAT_8000_0001_EDX] =
60032ac0 911 CPUID_EXT2_NX,
0514ef2f 912 .features[FEAT_8000_0001_ECX] =
27861ecc 913 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 914 .xlevel = 0x8000000A,
915 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
916 },
3eca4642
EH		 917 {
918 .name = "Conroe",
6b11322e 919 .level = 4,
99b88a17 920 .vendor = CPUID_VENDOR_INTEL,
3eca4642 921 .family = 6,
ffce9ebb 922 .model = 15,
3eca4642 923 .stepping = 3,
0514ef2f 924 .features[FEAT_1_EDX] =
b3a4f0b1 925 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 926 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
927 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
928 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
929 CPUID_DE | CPUID_FP87,
0514ef2f 930 .features[FEAT_1_ECX] =
27861ecc 931 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 932 .features[FEAT_8000_0001_EDX] =
27861ecc 933 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 934 .features[FEAT_8000_0001_ECX] =
27861ecc 935 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 936 .xlevel = 0x8000000A,
937 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
938 },
939 {
940 .name = "Penryn",
6b11322e 941 .level = 4,
99b88a17 942 .vendor = CPUID_VENDOR_INTEL,
3eca4642 943 .family = 6,
ffce9ebb 944 .model = 23,
3eca4642 945 .stepping = 3,
0514ef2f 946 .features[FEAT_1_EDX] =
b3a4f0b1 947 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 948 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
949 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
950 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
951 CPUID_DE | CPUID_FP87,
0514ef2f 952 .features[FEAT_1_ECX] =
27861ecc 953 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 954 CPUID_EXT_SSE3,
0514ef2f 955 .features[FEAT_8000_0001_EDX] =
27861ecc 956 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 957 .features[FEAT_8000_0001_ECX] =
27861ecc 958 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 959 .xlevel = 0x8000000A,
960 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
961 },
962 {
963 .name = "Nehalem",
6b11322e 964 .level = 4,
99b88a17 965 .vendor = CPUID_VENDOR_INTEL,
3eca4642 966 .family = 6,
ffce9ebb 967 .model = 26,
3eca4642 968 .stepping = 3,
0514ef2f 969 .features[FEAT_1_EDX] =
b3a4f0b1 970 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 971 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
972 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
973 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
974 CPUID_DE | CPUID_FP87,
0514ef2f 975 .features[FEAT_1_ECX] =
27861ecc 976 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 977 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 978 .features[FEAT_8000_0001_EDX] =
27861ecc 979 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 980 .features[FEAT_8000_0001_ECX] =
27861ecc 981 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 982 .xlevel = 0x8000000A,
983 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
984 },
985 {
986 .name = "Westmere",
987 .level = 11,
99b88a17 988 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 989 .family = 6,
990 .model = 44,
991 .stepping = 1,
0514ef2f 992 .features[FEAT_1_EDX] =
b3a4f0b1 993 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 994 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
995 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
996 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
997 CPUID_DE | CPUID_FP87,
0514ef2f 998 .features[FEAT_1_ECX] =
27861ecc 999 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1000 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1001 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1002 .features[FEAT_8000_0001_EDX] =
27861ecc 1003 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1004 .features[FEAT_8000_0001_ECX] =
27861ecc 1005 CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1006 .xlevel = 0x8000000A,
1007 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1008 },
1009 {
1010 .name = "SandyBridge",
1011 .level = 0xd,
99b88a17 1012 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1013 .family = 6,
1014 .model = 42,
1015 .stepping = 1,
0514ef2f 1016 .features[FEAT_1_EDX] =
b3a4f0b1 1017 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1018 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1019 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1020 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1021 CPUID_DE | CPUID_FP87,
0514ef2f 1022 .features[FEAT_1_ECX] =
27861ecc 1023 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1024 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1025 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1026 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1027 CPUID_EXT_SSE3,
0514ef2f 1028 .features[FEAT_8000_0001_EDX] =
27861ecc 1029 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1030 CPUID_EXT2_SYSCALL,
0514ef2f 1031 .features[FEAT_8000_0001_ECX] =
27861ecc 1032 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1033 .features[FEAT_XSAVE] =
1034 CPUID_XSAVE_XSAVEOPT,
3eca4642
EH		 1035 .xlevel = 0x8000000A,
1036 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1037 },
2f9ac42a
PB		 1038 {
1039 .name = "IvyBridge",
1040 .level = 0xd,
1041 .vendor = CPUID_VENDOR_INTEL,
1042 .family = 6,
1043 .model = 58,
1044 .stepping = 9,
1045 .features[FEAT_1_EDX] =
1046 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1047 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1048 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1049 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1050 CPUID_DE | CPUID_FP87,
1051 .features[FEAT_1_ECX] =
1052 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1053 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1054 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1055 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1056 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1057 .features[FEAT_7_0_EBX] =
1058 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1059 CPUID_7_0_EBX_ERMS,
1060 .features[FEAT_8000_0001_EDX] =
1061 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1062 CPUID_EXT2_SYSCALL,
1063 .features[FEAT_8000_0001_ECX] =
1064 CPUID_EXT3_LAHF_LM,
1065 .features[FEAT_XSAVE] =
1066 CPUID_XSAVE_XSAVEOPT,
1067 .xlevel = 0x8000000A,
1068 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1069 },
37507094 1070 {
a356850b
EH		 1071 .name = "Haswell-noTSX",
1072 .level = 0xd,
1073 .vendor = CPUID_VENDOR_INTEL,
1074 .family = 6,
1075 .model = 60,
1076 .stepping = 1,
1077 .features[FEAT_1_EDX] =
1078 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1079 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1080 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1081 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1082 CPUID_DE | CPUID_FP87,
1083 .features[FEAT_1_ECX] =
1084 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1085 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1086 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1087 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1088 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1089 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1090 .features[FEAT_8000_0001_EDX] =
1091 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1092 CPUID_EXT2_SYSCALL,
1093 .features[FEAT_8000_0001_ECX] =
1094 CPUID_EXT3_LAHF_LM,
1095 .features[FEAT_7_0_EBX] =
1096 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1097 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1098 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1099 .features[FEAT_XSAVE] =
1100 CPUID_XSAVE_XSAVEOPT,
1101 .xlevel = 0x8000000A,
1102 .model_id = "Intel Core Processor (Haswell, no TSX)",
1103 }, {
37507094
EH		 1104 .name = "Haswell",
1105 .level = 0xd,
99b88a17 1106 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1107 .family = 6,
1108 .model = 60,
1109 .stepping = 1,
0514ef2f 1110 .features[FEAT_1_EDX] =
b3a4f0b1 1111 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1112 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1113 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1114 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1115 CPUID_DE | CPUID_FP87,
0514ef2f 1116 .features[FEAT_1_ECX] =
27861ecc 1117 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1118 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1119 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1120 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1121 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1122 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1123 .features[FEAT_8000_0001_EDX] =
27861ecc 1124 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1125 CPUID_EXT2_SYSCALL,
0514ef2f 1126 .features[FEAT_8000_0001_ECX] =
27861ecc 1127 CPUID_EXT3_LAHF_LM,
0514ef2f 1128 .features[FEAT_7_0_EBX] =
27861ecc 1129 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1130 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1131 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1132 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1133 .features[FEAT_XSAVE] =
1134 CPUID_XSAVE_XSAVEOPT,
37507094
EH		 1135 .xlevel = 0x8000000A,
1136 .model_id = "Intel Core Processor (Haswell)",
1137 },
a356850b
EH		 1138 {
1139 .name = "Broadwell-noTSX",
1140 .level = 0xd,
1141 .vendor = CPUID_VENDOR_INTEL,
1142 .family = 6,
1143 .model = 61,
1144 .stepping = 2,
1145 .features[FEAT_1_EDX] =
1146 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1147 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1148 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1149 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1150 CPUID_DE | CPUID_FP87,
1151 .features[FEAT_1_ECX] =
1152 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1153 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1154 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1155 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1156 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1157 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1158 .features[FEAT_8000_0001_EDX] =
1159 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1160 CPUID_EXT2_SYSCALL,
1161 .features[FEAT_8000_0001_ECX] =
1162 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1163 .features[FEAT_7_0_EBX] =
1164 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1165 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1166 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1167 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1168 CPUID_7_0_EBX_SMAP,
1169 .features[FEAT_XSAVE] =
1170 CPUID_XSAVE_XSAVEOPT,
1171 .xlevel = 0x8000000A,
1172 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1173 },
ece01354
EH		 1174 {
1175 .name = "Broadwell",
1176 .level = 0xd,
1177 .vendor = CPUID_VENDOR_INTEL,
1178 .family = 6,
1179 .model = 61,
1180 .stepping = 2,
1181 .features[FEAT_1_EDX] =
b3a4f0b1 1182 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1183 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1184 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1185 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1186 CPUID_DE | CPUID_FP87,
1187 .features[FEAT_1_ECX] =
1188 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1189 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1190 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1191 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1192 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1193 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1194 .features[FEAT_8000_0001_EDX] =
1195 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1196 CPUID_EXT2_SYSCALL,
1197 .features[FEAT_8000_0001_ECX] =
1198 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1199 .features[FEAT_7_0_EBX] =
1200 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1201 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1202 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1203 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1204 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1205 .features[FEAT_XSAVE] =
1206 CPUID_XSAVE_XSAVEOPT,
ece01354
EH		 1207 .xlevel = 0x8000000A,
1208 .model_id = "Intel Core Processor (Broadwell)",
1209 },
3eca4642
EH		 1210 {
1211 .name = "Opteron_G1",
1212 .level = 5,
99b88a17 1213 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1214 .family = 15,
1215 .model = 6,
1216 .stepping = 1,
0514ef2f 1217 .features[FEAT_1_EDX] =
b3a4f0b1 1218 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1219 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1220 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1221 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1222 CPUID_DE | CPUID_FP87,
0514ef2f 1223 .features[FEAT_1_ECX] =
27861ecc 1224 CPUID_EXT_SSE3,
0514ef2f 1225 .features[FEAT_8000_0001_EDX] =
27861ecc 1226 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1227 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1228 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1229 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1230 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1231 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1232 .xlevel = 0x80000008,
1233 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1234 },
1235 {
1236 .name = "Opteron_G2",
1237 .level = 5,
99b88a17 1238 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1239 .family = 15,
1240 .model = 6,
1241 .stepping = 1,
0514ef2f 1242 .features[FEAT_1_EDX] =
b3a4f0b1 1243 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1244 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1245 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1246 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1247 CPUID_DE | CPUID_FP87,
0514ef2f 1248 .features[FEAT_1_ECX] =
27861ecc 1249 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1250 .features[FEAT_8000_0001_EDX] =
27861ecc 1251 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1252 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1253 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1254 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1255 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1256 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1257 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1258 .features[FEAT_8000_0001_ECX] =
27861ecc 1259 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1260 .xlevel = 0x80000008,
1261 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1262 },
1263 {
1264 .name = "Opteron_G3",
1265 .level = 5,
99b88a17 1266 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1267 .family = 15,
1268 .model = 6,
1269 .stepping = 1,
0514ef2f 1270 .features[FEAT_1_EDX] =
b3a4f0b1 1271 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1272 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1273 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1274 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1275 CPUID_DE | CPUID_FP87,
0514ef2f 1276 .features[FEAT_1_ECX] =
27861ecc 1277 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1278 CPUID_EXT_SSE3,
0514ef2f 1279 .features[FEAT_8000_0001_EDX] =
27861ecc 1280 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1281 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1282 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1283 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1284 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1285 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1286 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1287 .features[FEAT_8000_0001_ECX] =
27861ecc 1288 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1289 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1290 .xlevel = 0x80000008,
1291 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1292 },
1293 {
1294 .name = "Opteron_G4",
1295 .level = 0xd,
99b88a17 1296 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1297 .family = 21,
1298 .model = 1,
1299 .stepping = 2,
0514ef2f 1300 .features[FEAT_1_EDX] =
b3a4f0b1 1301 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1302 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1303 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1304 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1305 CPUID_DE | CPUID_FP87,
0514ef2f 1306 .features[FEAT_1_ECX] =
27861ecc 1307 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1308 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1309 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1310 CPUID_EXT_SSE3,
0514ef2f 1311 .features[FEAT_8000_0001_EDX] =
27861ecc 1312 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1313 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1314 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1315 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1316 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1317 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1318 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1319 .features[FEAT_8000_0001_ECX] =
27861ecc 1320 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1321 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1322 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1323 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1324 /* no xsaveopt! */
3eca4642
EH		 1325 .xlevel = 0x8000001A,
1326 .model_id = "AMD Opteron 62xx class CPU",
1327 },
021941b9
AP		 1328 {
1329 .name = "Opteron_G5",
1330 .level = 0xd,
99b88a17 1331 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1332 .family = 21,
1333 .model = 2,
1334 .stepping = 0,
0514ef2f 1335 .features[FEAT_1_EDX] =
b3a4f0b1 1336 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1337 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1338 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1339 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1340 CPUID_DE | CPUID_FP87,
0514ef2f 1341 .features[FEAT_1_ECX] =
27861ecc 1342 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1343 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1344 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1345 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1346 .features[FEAT_8000_0001_EDX] =
27861ecc 1347 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1348 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1349 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1350 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1351 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1352 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1353 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1354 .features[FEAT_8000_0001_ECX] =
27861ecc 1355 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1356 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1357 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1358 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1359 /* no xsaveopt! */
021941b9
AP		 1360 .xlevel = 0x8000001A,
1361 .model_id = "AMD Opteron 63xx class CPU",
1362 },
c6dc6f63
AP		 1363};
1364
0668af54
EH		 1365/**
1366 * x86_cpu_compat_set_features:
1367 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1368 * @w: Identifies the feature word to be changed.
1369 * @feat_add: Feature bits to be added to feature word
1370 * @feat_remove: Feature bits to be removed from feature word
1371 *
1372 * Change CPU model feature bits for compatibility.
1373 *
1374 * This function may be used by machine-type compatibility functions
1375 * to enable or disable feature bits on specific CPU models.
1376 */
1377void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1378 uint32_t feat_add, uint32_t feat_remove)
1379{
9576de75 1380 X86CPUDefinition *def;
0668af54
EH		 1381 int i;
1382 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1383 def = &builtin_x86_defs[i];
1384 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1385 def->features[w] |= feat_add;
1386 def->features[w] &= ~feat_remove;
1387 }
1388 }
1389}
1390
4d1b279b
EH		 1391static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1392 bool migratable_only);
1393
d940ee9b
EH		 1394#ifdef CONFIG_KVM
1395
c6dc6f63
AP		 1396static int cpu_x86_fill_model_id(char *str)
1397{
1398 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1399 int i;
1400
1401 for (i = 0; i < 3; i++) {
1402 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1403 memcpy(str + i * 16 + 0, &eax, 4);
1404 memcpy(str + i * 16 + 4, &ebx, 4);
1405 memcpy(str + i * 16 + 8, &ecx, 4);
1406 memcpy(str + i * 16 + 12, &edx, 4);
1407 }
1408 return 0;
1409}
1410
d940ee9b
EH		 1411static X86CPUDefinition host_cpudef;
1412
84f1b92f 1413static Property host_x86_cpu_properties[] = {
120eee7d 1414 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1415 DEFINE_PROP_END_OF_LIST()
1416};
1417
d940ee9b 1418/* class_init for the "host" CPU model
6e746f30 1419 *
d940ee9b 1420 * This function may be called before KVM is initialized.
6e746f30 1421 */
d940ee9b 1422static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1423{
84f1b92f 1424 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1425 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1426 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1427
d940ee9b 1428 xcc->kvm_required = true;
6e746f30 1429
c6dc6f63 1430 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1431 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1432
1433 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1434 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1435 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1436 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1437
d940ee9b 1438 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1439
d940ee9b
EH		 1440 xcc->cpu_def = &host_cpudef;
1441 host_cpudef.cache_info_passthrough = true;
1442
1443 /* level, xlevel, xlevel2, and the feature words are initialized on
1444 * instance_init, because they require KVM to be initialized.
1445 */
84f1b92f
EH		 1446
1447 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1448}
1449
1450static void host_x86_cpu_initfn(Object *obj)
1451{
1452 X86CPU *cpu = X86_CPU(obj);
1453 CPUX86State *env = &cpu->env;
1454 KVMState *s = kvm_state;
d940ee9b
EH		 1455
1456 assert(kvm_enabled());
1457
4d1b279b
EH		 1458 /* We can't fill the features array here because we don't know yet if
1459 * "migratable" is true or false.
1460 */
1461 cpu->host_features = true;
1462
d940ee9b
EH		 1463 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1464 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1465 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1466
d940ee9b 1467 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1468}
1469
d940ee9b
EH		 1470static const TypeInfo host_x86_cpu_type_info = {
1471 .name = X86_CPU_TYPE_NAME("host"),
1472 .parent = TYPE_X86_CPU,
1473 .instance_init = host_x86_cpu_initfn,
1474 .class_init = host_x86_cpu_class_init,
1475};
1476
1477#endif
1478
8459e396 1479static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1480{
8459e396 1481 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1482 int i;
1483
857aee33 1484 for (i = 0; i < 32; ++i) {
c6dc6f63 1485 if (1 << i & mask) {
bffd67b0 1486 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1487 assert(reg);
fefb41bf 1488 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1489 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1490 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1491 f->cpuid_eax, reg,
1492 f->feat_names[i] ? "." : "",
1493 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1494 }
857aee33 1495 }
c6dc6f63
AP		 1496}
1497
95b8519d
AF		 1498static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1499 const char *name, Error **errp)
1500{
1501 X86CPU *cpu = X86_CPU(obj);
1502 CPUX86State *env = &cpu->env;
1503 int64_t value;
1504
1505 value = (env->cpuid_version >> 8) & 0xf;
1506 if (value == 0xf) {
1507 value += (env->cpuid_version >> 20) & 0xff;
1508 }
1509 visit_type_int(v, &value, name, errp);
1510}
1511
71ad61d3
AF		 1512static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1513 const char *name, Error **errp)
ed5e1ec3 1514{
71ad61d3
AF		 1515 X86CPU *cpu = X86_CPU(obj);
1516 CPUX86State *env = &cpu->env;
1517 const int64_t min = 0;
1518 const int64_t max = 0xff + 0xf;
65cd9064 1519 Error *local_err = NULL;
71ad61d3
AF		 1520 int64_t value;
1521
65cd9064
MA		 1522 visit_type_int(v, &value, name, &local_err);
1523 if (local_err) {
1524 error_propagate(errp, local_err);
71ad61d3
AF		 1525 return;
1526 }
1527 if (value < min || value > max) {
c6bd8c70
MA		 1528 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1529 name ? name : "null", value, min, max);
71ad61d3
AF		 1530 return;
1531 }
1532
ed5e1ec3 1533 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1534 if (value > 0x0f) {
1535 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1536 } else {
71ad61d3 1537 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1538 }
1539}
1540
67e30c83
AF		 1541static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1542 const char *name, Error **errp)
1543{
1544 X86CPU *cpu = X86_CPU(obj);
1545 CPUX86State *env = &cpu->env;
1546 int64_t value;
1547
1548 value = (env->cpuid_version >> 4) & 0xf;
1549 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1550 visit_type_int(v, &value, name, errp);
1551}
1552
c5291a4f
AF		 1553static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1554 const char *name, Error **errp)
b0704cbd 1555{
c5291a4f
AF		 1556 X86CPU *cpu = X86_CPU(obj);
1557 CPUX86State *env = &cpu->env;
1558 const int64_t min = 0;
1559 const int64_t max = 0xff;
65cd9064 1560 Error *local_err = NULL;
c5291a4f
AF		 1561 int64_t value;
1562
65cd9064
MA		 1563 visit_type_int(v, &value, name, &local_err);
1564 if (local_err) {
1565 error_propagate(errp, local_err);
c5291a4f
AF		 1566 return;
1567 }
1568 if (value < min || value > max) {
c6bd8c70
MA		 1569 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1570 name ? name : "null", value, min, max);
c5291a4f
AF		 1571 return;
1572 }
1573
b0704cbd 1574 env->cpuid_version &= ~0xf00f0;
c5291a4f 1575 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1576}
1577
35112e41
AF		 1578static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1579 void *opaque, const char *name,
1580 Error **errp)
1581{
1582 X86CPU *cpu = X86_CPU(obj);
1583 CPUX86State *env = &cpu->env;
1584 int64_t value;
1585
1586 value = env->cpuid_version & 0xf;
1587 visit_type_int(v, &value, name, errp);
1588}
1589
036e2222
AF		 1590static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1591 void *opaque, const char *name,
1592 Error **errp)
38c3dc46 1593{
036e2222
AF		 1594 X86CPU *cpu = X86_CPU(obj);
1595 CPUX86State *env = &cpu->env;
1596 const int64_t min = 0;
1597 const int64_t max = 0xf;
65cd9064 1598 Error *local_err = NULL;
036e2222
AF		 1599 int64_t value;
1600
65cd9064
MA		 1601 visit_type_int(v, &value, name, &local_err);
1602 if (local_err) {
1603 error_propagate(errp, local_err);
036e2222
AF		 1604 return;
1605 }
1606 if (value < min || value > max) {
c6bd8c70
MA		 1607 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1608 name ? name : "null", value, min, max);
036e2222
AF		 1609 return;
1610 }
1611
38c3dc46 1612 env->cpuid_version &= ~0xf;
036e2222 1613 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1614}
1615
d480e1af
AF		 1616static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1617{
1618 X86CPU *cpu = X86_CPU(obj);
1619 CPUX86State *env = &cpu->env;
1620 char *value;
d480e1af 1621
e42a92ae 1622 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1623 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1624 env->cpuid_vendor3);
d480e1af
AF		 1625 return value;
1626}
1627
1628static void x86_cpuid_set_vendor(Object *obj, const char *value,
1629 Error **errp)
1630{
1631 X86CPU *cpu = X86_CPU(obj);
1632 CPUX86State *env = &cpu->env;
1633 int i;
1634
9df694ee 1635 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1636 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1637 return;
1638 }
1639
1640 env->cpuid_vendor1 = 0;
1641 env->cpuid_vendor2 = 0;
1642 env->cpuid_vendor3 = 0;
1643 for (i = 0; i < 4; i++) {
1644 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1645 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1646 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1647 }
d480e1af
AF		 1648}
1649
63e886eb
AF		 1650static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1651{
1652 X86CPU *cpu = X86_CPU(obj);
1653 CPUX86State *env = &cpu->env;
1654 char *value;
1655 int i;
1656
1657 value = g_malloc(48 + 1);
1658 for (i = 0; i < 48; i++) {
1659 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1660 }
1661 value[48] = '\0';
1662 return value;
1663}
1664
938d4c25
AF		 1665static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1666 Error **errp)
dcce6675 1667{
938d4c25
AF		 1668 X86CPU *cpu = X86_CPU(obj);
1669 CPUX86State *env = &cpu->env;
dcce6675
AF		 1670 int c, len, i;
1671
1672 if (model_id == NULL) {
1673 model_id = "";
1674 }
1675 len = strlen(model_id);
d0a6acf4 1676 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1677 for (i = 0; i < 48; i++) {
1678 if (i >= len) {
1679 c = '\0';
1680 } else {
1681 c = (uint8_t)model_id[i];
1682 }
1683 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1684 }
1685}
1686
89e48965
AF		 1687static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1688 const char *name, Error **errp)
1689{
1690 X86CPU *cpu = X86_CPU(obj);
1691 int64_t value;
1692
1693 value = cpu->env.tsc_khz * 1000;
1694 visit_type_int(v, &value, name, errp);
1695}
1696
1697static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1698 const char *name, Error **errp)
1699{
1700 X86CPU *cpu = X86_CPU(obj);
1701 const int64_t min = 0;
2e84849a 1702 const int64_t max = INT64_MAX;
65cd9064 1703 Error *local_err = NULL;
89e48965
AF		 1704 int64_t value;
1705
65cd9064
MA		 1706 visit_type_int(v, &value, name, &local_err);
1707 if (local_err) {
1708 error_propagate(errp, local_err);
89e48965
AF		 1709 return;
1710 }
1711 if (value < min || value > max) {
c6bd8c70
MA		 1712 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1713 name ? name : "null", value, min, max);
89e48965
AF		 1714 return;
1715 }
1716
1717 cpu->env.tsc_khz = value / 1000;
1718}
1719
31050930
IM		 1720static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1721 const char *name, Error **errp)
1722{
1723 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1724 int64_t value = cpu->apic_id;
31050930
IM		 1725
1726 visit_type_int(v, &value, name, errp);
1727}
1728
1729static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1730 const char *name, Error **errp)
1731{
1732 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1733 DeviceState *dev = DEVICE(obj);
31050930
IM		 1734 const int64_t min = 0;
1735 const int64_t max = UINT32_MAX;
1736 Error *error = NULL;
1737 int64_t value;
1738
8d6d4980
IM		 1739 if (dev->realized) {
1740 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1741 "it was realized", name, object_get_typename(obj));
1742 return;
1743 }
1744
31050930
IM		 1745 visit_type_int(v, &value, name, &error);
1746 if (error) {
1747 error_propagate(errp, error);
1748 return;
1749 }
1750 if (value < min || value > max) {
1751 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1752 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1753 object_get_typename(obj), name, value, min, max);
1754 return;
1755 }
1756
7e72a45c 1757 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1758 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1759 return;
1760 }
7e72a45c 1761 cpu->apic_id = value;
31050930
IM		 1762}
1763
7e5292b5 1764/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1765static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1766 const char *name, Error **errp)
1767{
7e5292b5 1768 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1769 FeatureWord w;
1770 Error *err = NULL;
1771 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1772 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1773 X86CPUFeatureWordInfoList *list = NULL;
1774
1775 for (w = 0; w < FEATURE_WORDS; w++) {
1776 FeatureWordInfo *wi = &feature_word_info[w];
1777 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1778 qwi->cpuid_input_eax = wi->cpuid_eax;
1779 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1780 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1781 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1782 qwi->features = array[w];
8e8aba50
EH		 1783
1784 /* List will be in reverse order, but order shouldn't matter */
1785 list_entries[w].next = list;
1786 list_entries[w].value = &word_infos[w];
1787 list = &list_entries[w];
1788 }
1789
1790 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1791 error_propagate(errp, err);
1792}
1793
c8f0f88e
IM		 1794static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1795 const char *name, Error **errp)
1796{
1797 X86CPU *cpu = X86_CPU(obj);
1798 int64_t value = cpu->hyperv_spinlock_attempts;
1799
1800 visit_type_int(v, &value, name, errp);
1801}
1802
1803static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1804 const char *name, Error **errp)
1805{
1806 const int64_t min = 0xFFF;
1807 const int64_t max = UINT_MAX;
1808 X86CPU *cpu = X86_CPU(obj);
1809 Error *err = NULL;
1810 int64_t value;
1811
1812 visit_type_int(v, &value, name, &err);
1813 if (err) {
1814 error_propagate(errp, err);
1815 return;
1816 }
1817
1818 if (value < min || value > max) {
1819 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1820 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1821 object_get_typename(obj), name ? name : "null",
1822 value, min, max);
c8f0f88e
IM		 1823 return;
1824 }
1825 cpu->hyperv_spinlock_attempts = value;
1826}
1827
1828static PropertyInfo qdev_prop_spinlocks = {
1829 .name = "int",
1830 .get = x86_get_hv_spinlocks,
1831 .set = x86_set_hv_spinlocks,
1832};
1833
72ac2e87
IM		 1834/* Convert all '_' in a feature string option name to '-', to make feature
1835 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1836 */
1837static inline void feat2prop(char *s)
1838{
1839 while ((s = strchr(s, '_'))) {
1840 *s = '-';
1841 }
1842}
1843
8f961357
EH		 1844/* Parse "+feature,-feature,feature=foo" CPU feature string
1845 */
94a444b2
AF		 1846static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1847 Error **errp)
8f961357 1848{
94a444b2 1849 X86CPU *cpu = X86_CPU(cs);
8f961357 1850 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1851 FeatureWord w;
8f961357 1852 /* Features to be added */
077c68c3 1853 FeatureWordArray plus_features = { 0 };
8f961357 1854 /* Features to be removed */
5ef57876 1855 FeatureWordArray minus_features = { 0 };
8f961357 1856 uint32_t numvalue;
a91987c2 1857 CPUX86State *env = &cpu->env;
94a444b2 1858 Error *local_err = NULL;
8f961357 1859
8f961357 1860 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1861
1862 while (featurestr) {
1863 char *val;
1864 if (featurestr[0] == '+') {
c00c94ab 1865 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1866 } else if (featurestr[0] == '-') {
c00c94ab 1867 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1868 } else if ((val = strchr(featurestr, '='))) {
1869 *val = 0; val++;
72ac2e87 1870 feat2prop(featurestr);
d024d209 1871 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1872 char *err;
a91987c2
IM		 1873 char num[32];
1874
c6dc6f63
AP		 1875 numvalue = strtoul(val, &err, 0);
1876 if (!*val || *err) {
6b1dd54b
PB		 1877 error_setg(errp, "bad numerical value %s", val);
1878 return;
c6dc6f63
AP		 1879 }
1880 if (numvalue < 0x80000000) {
94a444b2
AF		 1881 error_report("xlevel value shall always be >= 0x80000000"
1882 ", fixup will be removed in future versions");
2f7a21c4 1883 numvalue += 0x80000000;
c6dc6f63 1884 }
a91987c2 1885 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1886 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1887 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1888 int64_t tsc_freq;
1889 char *err;
a91987c2 1890 char num[32];
b862d1fe
JR		 1891
1892 tsc_freq = strtosz_suffix_unit(val, &err,
1893 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1894 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1895 error_setg(errp, "bad numerical value %s", val);
1896 return;
b862d1fe 1897 }
a91987c2 1898 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1899 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1900 &local_err);
72ac2e87 1901 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1902 char *err;
92067bf4 1903 const int min = 0xFFF;
c8f0f88e 1904 char num[32];
28f52cc0
VR		 1905 numvalue = strtoul(val, &err, 0);
1906 if (!*val || *err) {
6b1dd54b
PB		 1907 error_setg(errp, "bad numerical value %s", val);
1908 return;
28f52cc0 1909 }
92067bf4 1910 if (numvalue < min) {
94a444b2 1911 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1912 ", fixup will be removed in future versions",
1913 min);
92067bf4
IM		 1914 numvalue = min;
1915 }
c8f0f88e 1916 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1917 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1918 } else {
94a444b2 1919 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1920 }
c6dc6f63 1921 } else {
258f5abe 1922 feat2prop(featurestr);
94a444b2 1923 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1924 }
94a444b2
AF		 1925 if (local_err) {
1926 error_propagate(errp, local_err);
6b1dd54b 1927 return;
c6dc6f63
AP		 1928 }
1929 featurestr = strtok(NULL, ",");
1930 }
e1c224b4 1931
4d1b279b
EH		 1932 if (cpu->host_features) {
1933 for (w = 0; w < FEATURE_WORDS; w++) {
1934 env->features[w] =
1935 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1936 }
1937 }
1938
e1c224b4
EH		 1939 for (w = 0; w < FEATURE_WORDS; w++) {
1940 env->features[w] |= plus_features[w];
1941 env->features[w] &= ~minus_features[w];
1942 }
c6dc6f63
AP		 1943}
1944
8c3329e5 1945/* Print all cpuid feature names in featureset
c6dc6f63 1946 */
8c3329e5 1947static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1948{
8c3329e5
EH		 1949 int bit;
1950 bool first = true;
1951
1952 for (bit = 0; bit < 32; bit++) {
1953 if (featureset[bit]) {
1954 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1955 first = false;
c6dc6f63 1956 }
8c3329e5 1957 }
c6dc6f63
AP		 1958}
1959
e916cbf8
PM		 1960/* generate CPU information. */
1961void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1962{
9576de75 1963 X86CPUDefinition *def;
c6dc6f63 1964 char buf[256];
7fc9b714 1965 int i;
c6dc6f63 1966
7fc9b714
AF		 1967 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1968 def = &builtin_x86_defs[i];
c04321b3 1969 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1970 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1971 }
21ad7789
JK		 1972#ifdef CONFIG_KVM
1973 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1974 "KVM processor with all supported host features "
1975 "(only available in KVM mode)");
1976#endif
1977
6cdf8854 1978 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1979 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1980 FeatureWordInfo *fw = &feature_word_info[i];
1981
8c3329e5
EH		 1982 (*cpu_fprintf)(f, " ");
1983 listflags(f, cpu_fprintf, fw->feat_names);
1984 (*cpu_fprintf)(f, "\n");
3af60be2 1985 }
c6dc6f63
AP		 1986}
1987
76b64a7a 1988CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1989{
1990 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1991 X86CPUDefinition *def;
7fc9b714 1992 int i;
e3966126 1993
7fc9b714 1994 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1995 CpuDefinitionInfoList *entry;
1996 CpuDefinitionInfo *info;
1997
7fc9b714 1998 def = &builtin_x86_defs[i];
e3966126
AL		 1999 info = g_malloc0(sizeof(*info));
2000 info->name = g_strdup(def->name);
2001
2002 entry = g_malloc0(sizeof(*entry));
2003 entry->value = info;
2004 entry->next = cpu_list;
2005 cpu_list = entry;
2006 }
2007
2008 return cpu_list;
2009}
2010
84f1b92f
EH		 2011static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2012 bool migratable_only)
27418adf
EH		 2013{
2014 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2015 uint32_t r;
27418adf 2016
fefb41bf 2017 if (kvm_enabled()) {
84f1b92f
EH		 2018 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2019 wi->cpuid_ecx,
2020 wi->cpuid_reg);
fefb41bf 2021 } else if (tcg_enabled()) {
84f1b92f 2022 r = wi->tcg_features;
fefb41bf
EH		 2023 } else {
2024 return ~0;
2025 }
84f1b92f
EH		 2026 if (migratable_only) {
2027 r &= x86_cpu_get_migratable_flags(w);
2028 }
2029 return r;
27418adf
EH		 2030}
2031
51f63aed
EH		 2032/*
2033 * Filters CPU feature words based on host availability of each feature.
2034 *
51f63aed
EH		 2035 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2036 */
27418adf 2037static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2038{
2039 CPUX86State *env = &cpu->env;
bd87d2a2 2040 FeatureWord w;
51f63aed
EH		 2041 int rv = 0;
2042
bd87d2a2 2043 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2044 uint32_t host_feat =
2045 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2046 uint32_t requested_features = env->features[w];
2047 env->features[w] &= host_feat;
2048 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2049 if (cpu->filtered_features[w]) {
2050 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2051 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2052 }
2053 rv = 1;
2054 }
bd87d2a2 2055 }
51f63aed
EH		 2056
2057 return rv;
bc74b7db 2058}
bc74b7db 2059
d940ee9b 2060/* Load data from X86CPUDefinition
c080e30e 2061 */
d940ee9b 2062static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2063{
61dcd775 2064 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2065 const char *vendor;
2066 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2067 FeatureWord w;
c6dc6f63 2068
2d64255b
AF		 2069 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2070 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2071 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2072 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2073 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2074 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
787aaf57 2075 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2076 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2077 for (w = 0; w < FEATURE_WORDS; w++) {
2078 env->features[w] = def->features[w];
2079 }
82beb536 2080
9576de75 2081 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2082 if (kvm_enabled()) {
5fcca9ff
EH		 2083 FeatureWord w;
2084 for (w = 0; w < FEATURE_WORDS; w++) {
2085 env->features[w] |= kvm_default_features[w];
136a7e9a 2086 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2087 }
82beb536 2088 }
5fcca9ff 2089
82beb536 2090 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2091
2092 /* sysenter isn't supported in compatibility mode on AMD,
2093 * syscall isn't supported in compatibility mode on Intel.
2094 * Normally we advertise the actual CPU vendor, but you can
2095 * override this using the 'vendor' property if you want to use
2096 * KVM's sysenter/syscall emulation in compatibility mode and
2097 * when doing cross vendor migration
2098 */
74f54bc4 2099 vendor = def->vendor;
7c08db30
EH		 2100 if (kvm_enabled()) {
2101 uint32_t ebx = 0, ecx = 0, edx = 0;
2102 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2103 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2104 vendor = host_vendor;
2105 }
2106
2107 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2108
c6dc6f63
AP		 2109}
2110
e1570d00 2111X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2112{
2d64255b 2113 X86CPU *cpu = NULL;
d940ee9b 2114 X86CPUClass *xcc;
500050d1 2115 ObjectClass *oc;
2d64255b
AF		 2116 gchar **model_pieces;
2117 char *name, *features;
5c3c6a68
AF		 2118 Error *error = NULL;
2119
2d64255b
AF		 2120 model_pieces = g_strsplit(cpu_model, ",", 2);
2121 if (!model_pieces[0]) {
2122 error_setg(&error, "Invalid/empty CPU model name");
2123 goto out;
2124 }
2125 name = model_pieces[0];
2126 features = model_pieces[1];
2127
500050d1
AF		 2128 oc = x86_cpu_class_by_name(name);
2129 if (oc == NULL) {
2130 error_setg(&error, "Unable to find CPU definition: %s", name);
2131 goto out;
2132 }
d940ee9b
EH		 2133 xcc = X86_CPU_CLASS(oc);
2134
2135 if (xcc->kvm_required && !kvm_enabled()) {
2136 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2137 goto out;
2138 }
2139
d940ee9b
EH		 2140 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2141
94a444b2 2142 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2143 if (error) {
2144 goto out;
5c3c6a68
AF		 2145 }
2146
7f833247 2147out:
cd7b87ff
AF		 2148 if (error != NULL) {
2149 error_propagate(errp, error);
500050d1
AF		 2150 if (cpu) {
2151 object_unref(OBJECT(cpu));
2152 cpu = NULL;
2153 }
cd7b87ff 2154 }
7f833247
IM		 2155 g_strfreev(model_pieces);
2156 return cpu;
2157}
2158
0856579c 2159X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2160{
2161 Error *error = NULL;
2162 X86CPU *cpu;
2163
e1570d00 2164 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2165 if (error) {
0856579c 2166 goto out;
9c235e83 2167 }
7f833247 2168
7f833247 2169 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2170
0856579c
PM		 2171out:
2172 if (error) {
2173 error_report_err(error);
2174 if (cpu != NULL) {
2175 object_unref(OBJECT(cpu));
2176 cpu = NULL;
2177 }
18b0e4e7 2178 }
0856579c 2179 return cpu;
5c3c6a68
AF		 2180}
2181
d940ee9b
EH		 2182static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2183{
2184 X86CPUDefinition *cpudef = data;
2185 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2186
2187 xcc->cpu_def = cpudef;
2188}
2189
2190static void x86_register_cpudef_type(X86CPUDefinition *def)
2191{
2192 char *typename = x86_cpu_type_name(def->name);
2193 TypeInfo ti = {
2194 .name = typename,
2195 .parent = TYPE_X86_CPU,
2196 .class_init = x86_cpu_cpudef_class_init,
2197 .class_data = def,
2198 };
2199
2200 type_register(&ti);
2201 g_free(typename);
2202}
2203
c6dc6f63 2204#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2205
0e26b7b8
BS		 2206void cpu_clear_apic_feature(CPUX86State *env)
2207{
0514ef2f 2208 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2209}
2210
c6dc6f63
AP		 2211#endif /* !CONFIG_USER_ONLY */
2212
c04321b3 2213/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2214 */
2215void x86_cpudef_setup(void)
2216{
93bfef4c
CV		 2217 int i, j;
2218 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2219
2220 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2221 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2222
2223 /* Look for specific "cpudef" models that */
09faecf2 2224 /* have the QEMU version in .model_id */
93bfef4c 2225 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2226 if (strcmp(model_with_versions[j], def->name) == 0) {
2227 pstrcpy(def->model_id, sizeof(def->model_id),
2228 "QEMU Virtual CPU version ");
2229 pstrcat(def->model_id, sizeof(def->model_id),
2230 qemu_get_version());
93bfef4c
CV		 2231 break;
2232 }
2233 }
c6dc6f63 2234 }
c6dc6f63
AP		 2235}
2236
c6dc6f63
AP		 2237void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2238 uint32_t *eax, uint32_t *ebx,
2239 uint32_t *ecx, uint32_t *edx)
2240{
a60f24b5
AF		 2241 X86CPU *cpu = x86_env_get_cpu(env);
2242 CPUState *cs = CPU(cpu);
2243
c6dc6f63
AP		 2244 /* test if maximum index reached */
2245 if (index & 0x80000000) {
b3baa152
BW		 2246 if (index > env->cpuid_xlevel) {
2247 if (env->cpuid_xlevel2 > 0) {
2248 /* Handle the Centaur's CPUID instruction. */
2249 if (index > env->cpuid_xlevel2) {
2250 index = env->cpuid_xlevel2;
2251 } else if (index < 0xC0000000) {
2252 index = env->cpuid_xlevel;
2253 }
2254 } else {
57f26ae7
EH		 2255 /* Intel documentation states that invalid EAX input will
2256 * return the same information as EAX=cpuid_level
2257 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2258 */
2259 index = env->cpuid_level;
b3baa152
BW		 2260 }
2261 }
c6dc6f63
AP		 2262 } else {
2263 if (index > env->cpuid_level)
2264 index = env->cpuid_level;
2265 }
2266
2267 switch(index) {
2268 case 0:
2269 *eax = env->cpuid_level;
5eb2f7a4
EH		 2270 *ebx = env->cpuid_vendor1;
2271 *edx = env->cpuid_vendor2;
2272 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2273 break;
2274 case 1:
2275 *eax = env->cpuid_version;
7e72a45c
EH		 2276 *ebx = (cpu->apic_id << 24) |
2277 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2278 *ecx = env->features[FEAT_1_ECX];
2279 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2280 if (cs->nr_cores * cs->nr_threads > 1) {
2281 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2282 *edx |= 1 << 28; /* HTT bit */
2283 }
2284 break;
2285 case 2:
2286 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2287 if (cpu->cache_info_passthrough) {
2288 host_cpuid(index, 0, eax, ebx, ecx, edx);
2289 break;
2290 }
5e891bf8 2291 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2292 *ebx = 0;
2293 *ecx = 0;
5e891bf8
EH		 2294 *edx = (L1D_DESCRIPTOR << 16) | \
2295 (L1I_DESCRIPTOR << 8) | \
2296 (L2_DESCRIPTOR);
c6dc6f63
AP		 2297 break;
2298 case 4:
2299 /* cache info: needed for Core compatibility */
787aaf57
BC		 2300 if (cpu->cache_info_passthrough) {
2301 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2302 *eax &= ~0xFC000000;
c6dc6f63 2303 } else {
2f7a21c4 2304 *eax = 0;
76c2975a 2305 switch (count) {
c6dc6f63 2306 case 0: /* L1 dcache info */
5e891bf8
EH		 2307 *eax |= CPUID_4_TYPE_DCACHE | \
2308 CPUID_4_LEVEL(1) | \
2309 CPUID_4_SELF_INIT_LEVEL;
2310 *ebx = (L1D_LINE_SIZE - 1) | \
2311 ((L1D_PARTITIONS - 1) << 12) | \
2312 ((L1D_ASSOCIATIVITY - 1) << 22);
2313 *ecx = L1D_SETS - 1;
2314 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2315 break;
2316 case 1: /* L1 icache info */
5e891bf8
EH		 2317 *eax |= CPUID_4_TYPE_ICACHE | \
2318 CPUID_4_LEVEL(1) | \
2319 CPUID_4_SELF_INIT_LEVEL;
2320 *ebx = (L1I_LINE_SIZE - 1) | \
2321 ((L1I_PARTITIONS - 1) << 12) | \
2322 ((L1I_ASSOCIATIVITY - 1) << 22);
2323 *ecx = L1I_SETS - 1;
2324 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2325 break;
2326 case 2: /* L2 cache info */
5e891bf8
EH		 2327 *eax |= CPUID_4_TYPE_UNIFIED | \
2328 CPUID_4_LEVEL(2) | \
2329 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2330 if (cs->nr_threads > 1) {
2331 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2332 }
5e891bf8
EH		 2333 *ebx = (L2_LINE_SIZE - 1) | \
2334 ((L2_PARTITIONS - 1) << 12) | \
2335 ((L2_ASSOCIATIVITY - 1) << 22);
2336 *ecx = L2_SETS - 1;
2337 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2338 break;
2339 default: /* end of info */
2340 *eax = 0;
2341 *ebx = 0;
2342 *ecx = 0;
2343 *edx = 0;
2344 break;
76c2975a
PB		 2345 }
2346 }
2347
2348 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2349 if ((*eax & 31) && cs->nr_cores > 1) {
2350 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2351 }
2352 break;
2353 case 5:
2354 /* mwait info: needed for Core compatibility */
2355 *eax = 0; /* Smallest monitor-line size in bytes */
2356 *ebx = 0; /* Largest monitor-line size in bytes */
2357 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2358 *edx = 0;
2359 break;
2360 case 6:
2361 /* Thermal and Power Leaf */
2362 *eax = 0;
2363 *ebx = 0;
2364 *ecx = 0;
2365 *edx = 0;
2366 break;
f7911686 2367 case 7:
13526728
EH		 2368 /* Structured Extended Feature Flags Enumeration Leaf */
2369 if (count == 0) {
2370 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2371 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2372 *ecx = 0; /* Reserved */
2373 *edx = 0; /* Reserved */
f7911686
YW		 2374 } else {
2375 *eax = 0;
2376 *ebx = 0;
2377 *ecx = 0;
2378 *edx = 0;
2379 }
2380 break;
c6dc6f63
AP		 2381 case 9:
2382 /* Direct Cache Access Information Leaf */
2383 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2384 *ebx = 0;
2385 *ecx = 0;
2386 *edx = 0;
2387 break;
2388 case 0xA:
2389 /* Architectural Performance Monitoring Leaf */
9337e3b6 2390 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2391 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2392
2393 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2394 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2395 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2396 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2397 } else {
2398 *eax = 0;
2399 *ebx = 0;
2400 *ecx = 0;
2401 *edx = 0;
2402 }
c6dc6f63 2403 break;
2560f19f
PB		 2404 case 0xD: {
2405 KVMState *s = cs->kvm_state;
2406 uint64_t kvm_mask;
2407 int i;
2408
51e49430 2409 /* Processor Extended State */
2560f19f
PB		 2410 *eax = 0;
2411 *ebx = 0;
2412 *ecx = 0;
2413 *edx = 0;
2414 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2415 break;
2416 }
2560f19f
PB		 2417 kvm_mask =
2418 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2419 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2420
2560f19f
PB		 2421 if (count == 0) {
2422 *ecx = 0x240;
2423 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2424 const ExtSaveArea *esa = &ext_save_areas[i];
2425 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2426 (kvm_mask & (1 << i)) != 0) {
2427 if (i < 32) {
2428 *eax |= 1 << i;
2429 } else {
2430 *edx |= 1 << (i - 32);
2431 }
2432 *ecx = MAX(*ecx, esa->offset + esa->size);
2433 }
2434 }
2435 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2436 *ebx = *ecx;
2437 } else if (count == 1) {
0bb0b2d2 2438 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2439 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2440 const ExtSaveArea *esa = &ext_save_areas[count];
2441 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2442 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2443 *eax = esa->size;
2444 *ebx = esa->offset;
2560f19f 2445 }
51e49430
SY		 2446 }
2447 break;
2560f19f 2448 }
c6dc6f63
AP		 2449 case 0x80000000:
2450 *eax = env->cpuid_xlevel;
2451 *ebx = env->cpuid_vendor1;
2452 *edx = env->cpuid_vendor2;
2453 *ecx = env->cpuid_vendor3;
2454 break;
2455 case 0x80000001:
2456 *eax = env->cpuid_version;
2457 *ebx = 0;
0514ef2f
EH		 2458 *ecx = env->features[FEAT_8000_0001_ECX];
2459 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2460
2461 /* The Linux kernel checks for the CMPLegacy bit and
2462 * discards multiple thread information if it is set.
2463 * So dont set it here for Intel to make Linux guests happy.
2464 */
ce3960eb 2465 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2466 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2467 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2468 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2469 *ecx |= 1 << 1; /* CmpLegacy bit */
2470 }
2471 }
c6dc6f63
AP		 2472 break;
2473 case 0x80000002:
2474 case 0x80000003:
2475 case 0x80000004:
2476 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2477 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2478 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2479 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2480 break;
2481 case 0x80000005:
2482 /* cache info (L1 cache) */
787aaf57
BC		 2483 if (cpu->cache_info_passthrough) {
2484 host_cpuid(index, 0, eax, ebx, ecx, edx);
2485 break;
2486 }
5e891bf8
EH		 2487 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2488 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2489 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2490 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2491 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2492 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2493 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2494 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2495 break;
2496 case 0x80000006:
2497 /* cache info (L2 cache) */
787aaf57
BC		 2498 if (cpu->cache_info_passthrough) {
2499 host_cpuid(index, 0, eax, ebx, ecx, edx);
2500 break;
2501 }
5e891bf8
EH		 2502 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2503 (L2_DTLB_2M_ENTRIES << 16) | \
2504 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2505 (L2_ITLB_2M_ENTRIES);
2506 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2507 (L2_DTLB_4K_ENTRIES << 16) | \
2508 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2509 (L2_ITLB_4K_ENTRIES);
2510 *ecx = (L2_SIZE_KB_AMD << 16) | \
2511 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2512 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2513 *edx = ((L3_SIZE_KB/512) << 18) | \
2514 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2515 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2516 break;
303752a9
MT		 2517 case 0x80000007:
2518 *eax = 0;
2519 *ebx = 0;
2520 *ecx = 0;
2521 *edx = env->features[FEAT_8000_0007_EDX];
2522 break;
c6dc6f63
AP		 2523 case 0x80000008:
2524 /* virtual & phys address size in low 2 bytes. */
2525/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2526 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2527 /* 64 bit processor */
2528/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2529 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2530 } else {
0514ef2f 2531 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2532 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2533 } else {
c6dc6f63 2534 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2535 }
c6dc6f63
AP		 2536 }
2537 *ebx = 0;
2538 *ecx = 0;
2539 *edx = 0;
ce3960eb
AF		 2540 if (cs->nr_cores * cs->nr_threads > 1) {
2541 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2542 }
2543 break;
2544 case 0x8000000A:
0514ef2f 2545 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2546 *eax = 0x00000001; /* SVM Revision */
2547 *ebx = 0x00000010; /* nr of ASIDs */
2548 *ecx = 0;
0514ef2f 2549 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2550 } else {
2551 *eax = 0;
2552 *ebx = 0;
2553 *ecx = 0;
2554 *edx = 0;
2555 }
c6dc6f63 2556 break;
b3baa152
BW		 2557 case 0xC0000000:
2558 *eax = env->cpuid_xlevel2;
2559 *ebx = 0;
2560 *ecx = 0;
2561 *edx = 0;
2562 break;
2563 case 0xC0000001:
2564 /* Support for VIA CPU's CPUID instruction */
2565 *eax = env->cpuid_version;
2566 *ebx = 0;
2567 *ecx = 0;
0514ef2f 2568 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2569 break;
2570 case 0xC0000002:
2571 case 0xC0000003:
2572 case 0xC0000004:
2573 /* Reserved for the future, and now filled with zero */
2574 *eax = 0;
2575 *ebx = 0;
2576 *ecx = 0;
2577 *edx = 0;
2578 break;
c6dc6f63
AP		 2579 default:
2580 /* reserved values: zero */
2581 *eax = 0;
2582 *ebx = 0;
2583 *ecx = 0;
2584 *edx = 0;
2585 break;
2586 }
2587}
5fd2087a
AF		 2588
2589/* CPUClass::reset() */
2590static void x86_cpu_reset(CPUState *s)
2591{
2592 X86CPU *cpu = X86_CPU(s);
2593 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2594 CPUX86State *env = &cpu->env;
c1958aea
AF		 2595 int i;
2596
5fd2087a
AF		 2597 xcc->parent_reset(s);
2598
43175fa9 2599 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2600
00c8cb0a 2601 tlb_flush(s, 1);
c1958aea
AF		 2602
2603 env->old_exception = -1;
2604
2605 /* init to reset state */
2606
2607#ifdef CONFIG_SOFTMMU
2608 env->hflags |= HF_SOFTMMU_MASK;
2609#endif
2610 env->hflags2 |= HF2_GIF_MASK;
2611
2612 cpu_x86_update_cr0(env, 0x60000010);
2613 env->a20_mask = ~0x0;
2614 env->smbase = 0x30000;
2615
2616 env->idt.limit = 0xffff;
2617 env->gdt.limit = 0xffff;
2618 env->ldt.limit = 0xffff;
2619 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2620 env->tr.limit = 0xffff;
2621 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2622
2623 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2624 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2625 DESC_R_MASK | DESC_A_MASK);
2626 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2627 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2628 DESC_A_MASK);
2629 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2630 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2631 DESC_A_MASK);
2632 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2633 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2634 DESC_A_MASK);
2635 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2636 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2637 DESC_A_MASK);
2638 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2639 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2640 DESC_A_MASK);
2641
2642 env->eip = 0xfff0;
2643 env->regs[R_EDX] = env->cpuid_version;
2644
2645 env->eflags = 0x2;
2646
2647 /* FPU init */
2648 for (i = 0; i < 8; i++) {
2649 env->fptags[i] = 1;
2650 }
5bde1407 2651 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2652
2653 env->mxcsr = 0x1f80;
c74f41bb 2654 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2655
2656 env->pat = 0x0007040600070406ULL;
2657 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2658
2659 memset(env->dr, 0, sizeof(env->dr));
2660 env->dr[6] = DR6_FIXED_1;
2661 env->dr[7] = DR7_FIXED_1;
b3310ab3 2662 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2663 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2664
05e7e819 2665 env->xcr0 = 1;
0522604b 2666
9db2efd9
AW		 2667 /*
2668 * SDM 11.11.5 requires:
2669 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2670 * - IA32_MTRR_PHYSMASKn.V = 0
2671 * All other bits are undefined. For simplification, zero it all.
2672 */
2673 env->mtrr_deftype = 0;
2674 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2675 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2676
dd673288
IM		 2677#if !defined(CONFIG_USER_ONLY)
2678 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2679 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2680
259186a7 2681 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2682
2683 if (kvm_enabled()) {
2684 kvm_arch_reset_vcpu(cpu);
2685 }
dd673288 2686#endif
5fd2087a
AF		 2687}
2688
dd673288
IM		 2689#ifndef CONFIG_USER_ONLY
2690bool cpu_is_bsp(X86CPU *cpu)
2691{
02e51483 2692 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2693}
65dee380
IM		 2694
2695/* TODO: remove me, when reset over QOM tree is implemented */
2696static void x86_cpu_machine_reset_cb(void *opaque)
2697{
2698 X86CPU *cpu = opaque;
2699 cpu_reset(CPU(cpu));
2700}
dd673288
IM		 2701#endif
2702
de024815
AF		 2703static void mce_init(X86CPU *cpu)
2704{
2705 CPUX86State *cenv = &cpu->env;
2706 unsigned int bank;
2707
2708 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2709 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2710 (CPUID_MCE | CPUID_MCA)) {
2711 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2712 cenv->mcg_ctl = ~(uint64_t)0;
2713 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2714 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2715 }
2716 }
2717}
2718
bdeec802 2719#ifndef CONFIG_USER_ONLY
d3c64d6a 2720static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2721{
53a89e26 2722 DeviceState *dev = DEVICE(cpu);
449994eb 2723 APICCommonState *apic;
bdeec802
IM		 2724 const char *apic_type = "apic";
2725
2726 if (kvm_irqchip_in_kernel()) {
2727 apic_type = "kvm-apic";
2728 } else if (xen_enabled()) {
2729 apic_type = "xen-apic";
2730 }
2731
02e51483
CF		 2732 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2733 if (cpu->apic_state == NULL) {
bdeec802
IM		 2734 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2735 return;
2736 }
2737
2738 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2739 OBJECT(cpu->apic_state), NULL);
7e72a45c 2740 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2741 /* TODO: convert to link<> */
02e51483 2742 apic = APIC_COMMON(cpu->apic_state);
60671e58 2743 apic->cpu = cpu;
d3c64d6a
IM		 2744}
2745
2746static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2747{
02e51483 2748 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2749 return;
2750 }
6e8e2651
MA		 2751 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2752 errp);
bdeec802 2753}
f809c605
PB		 2754
2755static void x86_cpu_machine_done(Notifier *n, void *unused)
2756{
2757 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2758 MemoryRegion *smram =
2759 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2760
2761 if (smram) {
2762 cpu->smram = g_new(MemoryRegion, 1);
2763 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2764 smram, 0, 1ull << 32);
2765 memory_region_set_enabled(cpu->smram, false);
2766 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2767 }
2768}
d3c64d6a
IM		 2769#else
2770static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2771{
2772}
bdeec802
IM		 2773#endif
2774
e48638fd
WH		 2775
2776#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2777 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2778 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2779#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2780 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2781 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2782static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2783{
14a10fc3 2784 CPUState *cs = CPU(dev);
2b6f294c
AF		 2785 X86CPU *cpu = X86_CPU(dev);
2786 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2787 CPUX86State *env = &cpu->env;
2b6f294c 2788 Error *local_err = NULL;
e48638fd 2789 static bool ht_warned;
b34d12d1 2790
9886e834
EH		 2791 if (cpu->apic_id < 0) {
2792 error_setg(errp, "apic-id property was not initialized properly");
2793 return;
2794 }
2795
0514ef2f 2796 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2797 env->cpuid_level = 7;
2798 }
7a059953 2799
9b15cd9e
IM		 2800 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2801 * CPUID[1].EDX.
2802 */
e48638fd 2803 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2804 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2805 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2806 & CPUID_EXT2_AMD_ALIASES);
2807 }
2808
fefb41bf
EH		 2809
2810 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2811 error_setg(&local_err,
2812 kvm_enabled() ?
2813 "Host doesn't support requested features" :
2814 "TCG doesn't support requested features");
2815 goto out;
4586f157
IM		 2816 }
2817
65dee380
IM		 2818#ifndef CONFIG_USER_ONLY
2819 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2820
0514ef2f 2821 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2822 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2823 if (local_err != NULL) {
4dc1f449 2824 goto out;
bdeec802
IM		 2825 }
2826 }
65dee380
IM		 2827#endif
2828
7a059953 2829 mce_init(cpu);
2001d0cd
PB		 2830
2831#ifndef CONFIG_USER_ONLY
2832 if (tcg_enabled()) {
f809c605 2833 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd
PB		 2834 cpu->cpu_as_root = g_new(MemoryRegion, 1);
2835 cs->as = g_new(AddressSpace, 1);
f809c605
PB		 2836
2837 /* Outer container... */
2838 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2839 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2840
2841 /* ... with two regions inside: normal system memory with low
2842 * priority, and...
2843 */
2844 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2845 get_system_memory(), 0, ~0ull);
2846 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2847 memory_region_set_enabled(cpu->cpu_as_mem, true);
2001d0cd 2848 address_space_init(cs->as, cpu->cpu_as_root, "CPU");
f809c605
PB		 2849
2850 /* ... SMRAM with higher priority, linked from /machine/smram. */
2851 cpu->machine_done.notify = x86_cpu_machine_done;
2852 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2853 }
2854#endif
2855
14a10fc3 2856 qemu_init_vcpu(cs);
d3c64d6a 2857
e48638fd
WH		 2858 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2859 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2860 * based on inputs (sockets,cores,threads), it is still better to gives
2861 * users a warning.
2862 *
2863 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2864 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2865 */
2866 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2867 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2868 " -smp options properly.");
2869 ht_warned = true;
2870 }
2871
d3c64d6a
IM		 2872 x86_cpu_apic_realize(cpu, &local_err);
2873 if (local_err != NULL) {
2874 goto out;
2875 }
14a10fc3 2876 cpu_reset(cs);
2b6f294c 2877
4dc1f449 2878 xcc->parent_realize(dev, &local_err);
2001d0cd 2879
4dc1f449
IM		 2880out:
2881 if (local_err != NULL) {
2882 error_propagate(errp, local_err);
2883 return;
2884 }
7a059953
AF		 2885}
2886
38e5c119
EH		 2887typedef struct BitProperty {
2888 uint32_t *ptr;
2889 uint32_t mask;
2890} BitProperty;
2891
2892static void x86_cpu_get_bit_prop(Object *obj,
2893 struct Visitor *v,
2894 void *opaque,
2895 const char *name,
2896 Error **errp)
2897{
2898 BitProperty *fp = opaque;
2899 bool value = (*fp->ptr & fp->mask) == fp->mask;
2900 visit_type_bool(v, &value, name, errp);
2901}
2902
2903static void x86_cpu_set_bit_prop(Object *obj,
2904 struct Visitor *v,
2905 void *opaque,
2906 const char *name,
2907 Error **errp)
2908{
2909 DeviceState *dev = DEVICE(obj);
2910 BitProperty *fp = opaque;
2911 Error *local_err = NULL;
2912 bool value;
2913
2914 if (dev->realized) {
2915 qdev_prop_set_after_realize(dev, name, errp);
2916 return;
2917 }
2918
2919 visit_type_bool(v, &value, name, &local_err);
2920 if (local_err) {
2921 error_propagate(errp, local_err);
2922 return;
2923 }
2924
2925 if (value) {
2926 *fp->ptr |= fp->mask;
2927 } else {
2928 *fp->ptr &= ~fp->mask;
2929 }
2930}
2931
2932static void x86_cpu_release_bit_prop(Object *obj, const char *name,
2933 void *opaque)
2934{
2935 BitProperty *prop = opaque;
2936 g_free(prop);
2937}
2938
2939/* Register a boolean property to get/set a single bit in a uint32_t field.
2940 *
2941 * The same property name can be registered multiple times to make it affect
2942 * multiple bits in the same FeatureWord. In that case, the getter will return
2943 * true only if all bits are set.
2944 */
2945static void x86_cpu_register_bit_prop(X86CPU *cpu,
2946 const char *prop_name,
2947 uint32_t *field,
2948 int bitnr)
2949{
2950 BitProperty *fp;
2951 ObjectProperty *op;
2952 uint32_t mask = (1UL << bitnr);
2953
2954 op = object_property_find(OBJECT(cpu), prop_name, NULL);
2955 if (op) {
2956 fp = op->opaque;
2957 assert(fp->ptr == field);
2958 fp->mask |= mask;
2959 } else {
2960 fp = g_new0(BitProperty, 1);
2961 fp->ptr = field;
2962 fp->mask = mask;
2963 object_property_add(OBJECT(cpu), prop_name, "bool",
2964 x86_cpu_get_bit_prop,
2965 x86_cpu_set_bit_prop,
2966 x86_cpu_release_bit_prop, fp, &error_abort);
2967 }
2968}
2969
2970static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
2971 FeatureWord w,
2972 int bitnr)
2973{
2974 Object *obj = OBJECT(cpu);
2975 int i;
2976 char **names;
2977 FeatureWordInfo *fi = &feature_word_info[w];
2978
2979 if (!fi->feat_names) {
2980 return;
2981 }
2982 if (!fi->feat_names[bitnr]) {
2983 return;
2984 }
2985
2986 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
2987
2988 feat2prop(names[0]);
2989 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
2990
2991 for (i = 1; names[i]; i++) {
2992 feat2prop(names[i]);
2993 object_property_add_alias(obj, names[i], obj, g_strdup(names[0]),
2994 &error_abort);
2995 }
2996
2997 g_strfreev(names);
2998}
2999
de024815
AF		 3000static void x86_cpu_initfn(Object *obj)
3001{
55e5c285 3002 CPUState *cs = CPU(obj);
de024815 3003 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3004 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3005 CPUX86State *env = &cpu->env;
38e5c119 3006 FeatureWord w;
d65e9815 3007 static int inited;
de024815 3008
c05efcb1 3009 cs->env_ptr = env;
de024815 3010 cpu_exec_init(env);
71ad61d3
AF		 3011
3012 object_property_add(obj, "family", "int",
95b8519d 3013 x86_cpuid_version_get_family,
71ad61d3 3014 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3015 object_property_add(obj, "model", "int",
67e30c83 3016 x86_cpuid_version_get_model,
c5291a4f 3017 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3018 object_property_add(obj, "stepping", "int",
35112e41 3019 x86_cpuid_version_get_stepping,
036e2222 3020 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3021 object_property_add_str(obj, "vendor",
3022 x86_cpuid_get_vendor,
3023 x86_cpuid_set_vendor, NULL);
938d4c25 3024 object_property_add_str(obj, "model-id",
63e886eb 3025 x86_cpuid_get_model_id,
938d4c25 3026 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3027 object_property_add(obj, "tsc-frequency", "int",
3028 x86_cpuid_get_tsc_freq,
3029 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3030 object_property_add(obj, "apic-id", "int",
3031 x86_cpuid_get_apic_id,
3032 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3033 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3034 x86_cpu_get_feature_words,
7e5292b5
EH		 3035 NULL, NULL, (void *)env->features, NULL);
3036 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3037 x86_cpu_get_feature_words,
3038 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3039
92067bf4 3040 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3041
9886e834
EH		 3042#ifndef CONFIG_USER_ONLY
3043 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3044 cpu->apic_id = -1;
3045#endif
3046
38e5c119
EH		 3047 for (w = 0; w < FEATURE_WORDS; w++) {
3048 int bitnr;
3049
3050 for (bitnr = 0; bitnr < 32; bitnr++) {
3051 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3052 }
3053 }
3054
d940ee9b
EH		 3055 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3056
d65e9815
IM		 3057 /* init various static tables used in TCG mode */
3058 if (tcg_enabled() && !inited) {
3059 inited = 1;
3060 optimize_flags_init();
d65e9815 3061 }
de024815
AF		 3062}
3063
997395d3
IM		 3064static int64_t x86_cpu_get_arch_id(CPUState *cs)
3065{
3066 X86CPU *cpu = X86_CPU(cs);
997395d3 3067
7e72a45c 3068 return cpu->apic_id;
997395d3
IM		 3069}
3070
444d5590
AF		 3071static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3072{
3073 X86CPU *cpu = X86_CPU(cs);
3074
3075 return cpu->env.cr[0] & CR0_PG_MASK;
3076}
3077
f45748f1
AF		 3078static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3079{
3080 X86CPU *cpu = X86_CPU(cs);
3081
3082 cpu->env.eip = value;
3083}
3084
bdf7ae5b
AF		 3085static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3086{
3087 X86CPU *cpu = X86_CPU(cs);
3088
3089 cpu->env.eip = tb->pc - tb->cs_base;
3090}
3091
8c2e1b00
AF		 3092static bool x86_cpu_has_work(CPUState *cs)
3093{
3094 X86CPU *cpu = X86_CPU(cs);
3095 CPUX86State *env = &cpu->env;
3096
60e68042
PB		 3097#if !defined(CONFIG_USER_ONLY)
3098 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3099 apic_poll_irq(cpu->apic_state);
3100 cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
3101 }
3102#endif
3103
3104 return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
8c2e1b00
AF		 3105 (env->eflags & IF_MASK)) ||
3106 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3107 CPU_INTERRUPT_INIT |
3108 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3109 CPU_INTERRUPT_MCE)) ||
3110 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3111 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3112}
3113
9337e3b6
EH		 3114static Property x86_cpu_properties[] = {
3115 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3116 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3117 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3118 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3119 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
912ffc47
IM		 3120 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
3121 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3122 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3123 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3124 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3125 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
9337e3b6
EH		 3126 DEFINE_PROP_END_OF_LIST()
3127};
3128
5fd2087a
AF		 3129static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3130{
3131 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3132 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3133 DeviceClass *dc = DEVICE_CLASS(oc);
3134
3135 xcc->parent_realize = dc->realize;
3136 dc->realize = x86_cpu_realizefn;
62fc403f 3137 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 3138 dc->props = x86_cpu_properties;
5fd2087a
AF		 3139
3140 xcc->parent_reset = cc->reset;
3141 cc->reset = x86_cpu_reset;
91b1df8c 3142 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3143
500050d1 3144 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3145 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3146 cc->has_work = x86_cpu_has_work;
97a8ea5a 3147 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3148 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3149 cc->dump_state = x86_cpu_dump_state;
f45748f1 3150 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3151 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3152 cc->gdb_read_register = x86_cpu_gdb_read_register;
3153 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3154 cc->get_arch_id = x86_cpu_get_arch_id;
3155 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3156#ifdef CONFIG_USER_ONLY
3157 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3158#else
a23bbfda 3159 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3160 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3161 cc->write_elf64_note = x86_cpu_write_elf64_note;
3162 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3163 cc->write_elf32_note = x86_cpu_write_elf32_note;
3164 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3165 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3166#endif
a0e372f0 3167 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3168#ifndef CONFIG_USER_ONLY
3169 cc->debug_excp_handler = breakpoint_handler;
3170#endif
374e0cd4
RH		 3171 cc->cpu_exec_enter = x86_cpu_exec_enter;
3172 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 3173}
3174
3175static const TypeInfo x86_cpu_type_info = {
3176 .name = TYPE_X86_CPU,
3177 .parent = TYPE_CPU,
3178 .instance_size = sizeof(X86CPU),
de024815 3179 .instance_init = x86_cpu_initfn,
d940ee9b 3180 .abstract = true,
5fd2087a
AF		 3181 .class_size = sizeof(X86CPUClass),
3182 .class_init = x86_cpu_common_class_init,
3183};
3184
3185static void x86_cpu_register_types(void)
3186{
d940ee9b
EH		 3187 int i;
3188
5fd2087a 3189 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3190 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3191 x86_register_cpudef_type(&builtin_x86_defs[i]);
3192 }
3193#ifdef CONFIG_KVM
3194 type_register_static(&host_x86_cpu_type_info);
3195#endif
5fd2087a
AF		 3196}
3197
3198type_init(x86_cpu_register_types)
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