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KVM: x86: Add nested virtualization support for MPX
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
a9d30f33
NHE		 357
358 /* The guest-physical address of the current VMCS L1 keeps for L2 */
359 gpa_t current_vmptr;
360 /* The host-usable pointer to the above */
361 struct page *current_vmcs12_page;
362 struct vmcs12 *current_vmcs12;
8de48833 363 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 364 /*
365 * Indicates if the shadow vmcs must be updated with the
366 * data hold by vmcs12
367 */
368 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 369
370 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
371 struct list_head vmcs02_pool;
372 int vmcs02_num;
fe3ef05c 373 u64 vmcs01_tsc_offset;
644d711a
NHE		 374 /* L2 must run next, and mustn't decide to exit to L1. */
375 bool nested_run_pending;
fe3ef05c
NHE		 376 /*
377 * Guest pages referred to in vmcs02 with host-physical pointers, so
378 * we must keep them pinned while L2 runs.
379 */
380 struct page *apic_access_page;
b3897a49 381 u64 msr_ia32_feature_control;
f4124500
JK		 382
383 struct hrtimer preemption_timer;
384 bool preemption_timer_expired;
ec378aee
NHE		 385};
386
01e439be
YZ		 387#define POSTED_INTR_ON 0
388/* Posted-Interrupt Descriptor */
389struct pi_desc {
390 u32 pir[8]; /* Posted interrupt requested */
391 u32 control; /* bit 0 of control is outstanding notification bit */
392 u32 rsvd[7];
393} __aligned(64);
394
a20ed54d
YZ		 395static bool pi_test_and_set_on(struct pi_desc *pi_desc)
396{
397 return test_and_set_bit(POSTED_INTR_ON,
398 (unsigned long *)&pi_desc->control);
399}
400
401static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
402{
403 return test_and_clear_bit(POSTED_INTR_ON,
404 (unsigned long *)&pi_desc->control);
405}
406
407static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
408{
409 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
410}
411
a2fa3e9f 412struct vcpu_vmx {
fb3f0f51 413 struct kvm_vcpu vcpu;
313dbd49 414 unsigned long host_rsp;
29bd8a78 415 u8 fail;
69c73028 416 u8 cpl;
9d58b931 417 bool nmi_known_unmasked;
51aa01d1 418 u32 exit_intr_info;
1155f76a 419 u32 idt_vectoring_info;
6de12732 420 ulong rflags;
26bb0981 421 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 422 int nmsrs;
423 int save_nmsrs;
a547c6db 424 unsigned long host_idt_base;
a2fa3e9f 425#ifdef CONFIG_X86_64
44ea2b17
AK		 426 u64 msr_host_kernel_gs_base;
427 u64 msr_guest_kernel_gs_base;
a2fa3e9f 428#endif
2961e876
GN		 429 u32 vm_entry_controls_shadow;
430 u32 vm_exit_controls_shadow;
d462b819
NHE		 431 /*
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
435 */
436 struct loaded_vmcs vmcs01;
437 struct loaded_vmcs *loaded_vmcs;
438 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 439 struct msr_autoload {
440 unsigned nr;
441 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
442 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
443 } msr_autoload;
a2fa3e9f
GH		 444 struct {
445 int loaded;
446 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 447#ifdef CONFIG_X86_64
448 u16 ds_sel, es_sel;
449#endif
152d3f2f
LV		 450 int gs_ldt_reload_needed;
451 int fs_reload_needed;
da8999d3 452 u64 msr_host_bndcfgs;
d77c26fc 453 } host_state;
9c8cba37 454 struct {
7ffd92c5 455 int vm86_active;
78ac8b47 456 ulong save_rflags;
f5f7b2fe
AK		 457 struct kvm_segment segs[8];
458 } rmode;
459 struct {
460 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 461 struct kvm_save_segment {
462 u16 selector;
463 unsigned long base;
464 u32 limit;
465 u32 ar;
f5f7b2fe 466 } seg[8];
2fb92db1 467 } segment_cache;
2384d2b3 468 int vpid;
04fa4d32 469 bool emulation_required;
3b86cd99
JK		 470
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked;
473 ktime_t entry_time;
474 s64 vnmi_blocked_time;
a0861c02 475 u32 exit_reason;
4e47c7a6
SY		 476
477 bool rdtscp_enabled;
ec378aee 478
01e439be
YZ		 479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc;
481
ec378aee
NHE		 482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested;
a2fa3e9f
GH		 484};
485
2fb92db1
AK		 486enum segment_cache_field {
487 SEG_FIELD_SEL = 0,
488 SEG_FIELD_BASE = 1,
489 SEG_FIELD_LIMIT = 2,
490 SEG_FIELD_AR = 3,
491
492 SEG_FIELD_NR = 4
493};
494
a2fa3e9f
GH		 495static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
496{
fb3f0f51 497 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 498}
499
22bd0358
NHE		 500#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
504
4607c2d7
AG		 505
506static const unsigned long shadow_read_only_fields[] = {
507 /*
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
518 */
519 VM_EXIT_REASON,
520 VM_EXIT_INTR_INFO,
521 VM_EXIT_INSTRUCTION_LEN,
522 IDT_VECTORING_INFO_FIELD,
523 IDT_VECTORING_ERROR_CODE,
524 VM_EXIT_INTR_ERROR_CODE,
525 EXIT_QUALIFICATION,
526 GUEST_LINEAR_ADDRESS,
527 GUEST_PHYSICAL_ADDRESS
528};
529static const int max_shadow_read_only_fields =
530 ARRAY_SIZE(shadow_read_only_fields);
531
532static const unsigned long shadow_read_write_fields[] = {
533 GUEST_RIP,
534 GUEST_RSP,
535 GUEST_CR0,
536 GUEST_CR3,
537 GUEST_CR4,
538 GUEST_INTERRUPTIBILITY_INFO,
539 GUEST_RFLAGS,
540 GUEST_CS_SELECTOR,
541 GUEST_CS_AR_BYTES,
542 GUEST_CS_LIMIT,
543 GUEST_CS_BASE,
544 GUEST_ES_BASE,
36be0b9d 545 GUEST_BNDCFGS,
4607c2d7
AG		 546 CR0_GUEST_HOST_MASK,
547 CR0_READ_SHADOW,
548 CR4_READ_SHADOW,
549 TSC_OFFSET,
550 EXCEPTION_BITMAP,
551 CPU_BASED_VM_EXEC_CONTROL,
552 VM_ENTRY_EXCEPTION_ERROR_CODE,
553 VM_ENTRY_INTR_INFO_FIELD,
554 VM_ENTRY_INSTRUCTION_LEN,
555 VM_ENTRY_EXCEPTION_ERROR_CODE,
556 HOST_FS_BASE,
557 HOST_GS_BASE,
558 HOST_FS_SELECTOR,
559 HOST_GS_SELECTOR
560};
561static const int max_shadow_read_write_fields =
562 ARRAY_SIZE(shadow_read_write_fields);
563
772e0318 564static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 565 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
566 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
567 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
568 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
569 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
570 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
571 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
572 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
573 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
574 FIELD(HOST_ES_SELECTOR, host_es_selector),
575 FIELD(HOST_CS_SELECTOR, host_cs_selector),
576 FIELD(HOST_SS_SELECTOR, host_ss_selector),
577 FIELD(HOST_DS_SELECTOR, host_ds_selector),
578 FIELD(HOST_FS_SELECTOR, host_fs_selector),
579 FIELD(HOST_GS_SELECTOR, host_gs_selector),
580 FIELD(HOST_TR_SELECTOR, host_tr_selector),
581 FIELD64(IO_BITMAP_A, io_bitmap_a),
582 FIELD64(IO_BITMAP_B, io_bitmap_b),
583 FIELD64(MSR_BITMAP, msr_bitmap),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
587 FIELD64(TSC_OFFSET, tsc_offset),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
589 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
590 FIELD64(EPT_POINTER, ept_pointer),
591 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
592 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
593 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
594 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
595 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
597 FIELD64(GUEST_PDPTR0, guest_pdptr0),
598 FIELD64(GUEST_PDPTR1, guest_pdptr1),
599 FIELD64(GUEST_PDPTR2, guest_pdptr2),
600 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 601 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 602 FIELD64(HOST_IA32_PAT, host_ia32_pat),
603 FIELD64(HOST_IA32_EFER, host_ia32_efer),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
607 FIELD(EXCEPTION_BITMAP, exception_bitmap),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
610 FIELD(CR3_TARGET_COUNT, cr3_target_count),
611 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
612 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
614 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
619 FIELD(TPR_THRESHOLD, tpr_threshold),
620 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
621 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
622 FIELD(VM_EXIT_REASON, vm_exit_reason),
623 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
624 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
625 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
626 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
627 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
628 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
629 FIELD(GUEST_ES_LIMIT, guest_es_limit),
630 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
631 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
632 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
633 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
634 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
635 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
636 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
637 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
638 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
639 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
640 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
641 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
642 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
643 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
644 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
645 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
646 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
648 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
649 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
650 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 651 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 652 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
653 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
654 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
655 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
656 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
657 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
658 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
659 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
660 FIELD(EXIT_QUALIFICATION, exit_qualification),
661 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
662 FIELD(GUEST_CR0, guest_cr0),
663 FIELD(GUEST_CR3, guest_cr3),
664 FIELD(GUEST_CR4, guest_cr4),
665 FIELD(GUEST_ES_BASE, guest_es_base),
666 FIELD(GUEST_CS_BASE, guest_cs_base),
667 FIELD(GUEST_SS_BASE, guest_ss_base),
668 FIELD(GUEST_DS_BASE, guest_ds_base),
669 FIELD(GUEST_FS_BASE, guest_fs_base),
670 FIELD(GUEST_GS_BASE, guest_gs_base),
671 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
672 FIELD(GUEST_TR_BASE, guest_tr_base),
673 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
674 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
675 FIELD(GUEST_DR7, guest_dr7),
676 FIELD(GUEST_RSP, guest_rsp),
677 FIELD(GUEST_RIP, guest_rip),
678 FIELD(GUEST_RFLAGS, guest_rflags),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
680 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
681 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
682 FIELD(HOST_CR0, host_cr0),
683 FIELD(HOST_CR3, host_cr3),
684 FIELD(HOST_CR4, host_cr4),
685 FIELD(HOST_FS_BASE, host_fs_base),
686 FIELD(HOST_GS_BASE, host_gs_base),
687 FIELD(HOST_TR_BASE, host_tr_base),
688 FIELD(HOST_GDTR_BASE, host_gdtr_base),
689 FIELD(HOST_IDTR_BASE, host_idtr_base),
690 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
691 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
692 FIELD(HOST_RSP, host_rsp),
693 FIELD(HOST_RIP, host_rip),
694};
695static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
696
697static inline short vmcs_field_to_offset(unsigned long field)
698{
699 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
700 return -1;
701 return vmcs_field_to_offset_table[field];
702}
703
a9d30f33
NHE		 704static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
705{
706 return to_vmx(vcpu)->nested.current_vmcs12;
707}
708
709static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
710{
711 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 712 if (is_error_page(page))
a9d30f33 713 return NULL;
32cad84f 714
a9d30f33
NHE		 715 return page;
716}
717
718static void nested_release_page(struct page *page)
719{
720 kvm_release_page_dirty(page);
721}
722
723static void nested_release_page_clean(struct page *page)
724{
725 kvm_release_page_clean(page);
726}
727
bfd0a56b 728static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 729static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 730static void kvm_cpu_vmxon(u64 addr);
731static void kvm_cpu_vmxoff(void);
776e58ea 732static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 733static void vmx_set_segment(struct kvm_vcpu *vcpu,
734 struct kvm_segment *var, int seg);
735static void vmx_get_segment(struct kvm_vcpu *vcpu,
736 struct kvm_segment *var, int seg);
d99e4152
GN		 737static bool guest_state_valid(struct kvm_vcpu *vcpu);
738static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 739static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 740static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 741static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
36be0b9d 742static bool vmx_mpx_supported(void);
75880a01 743
6aa8b732
AK		 744static DEFINE_PER_CPU(struct vmcs *, vmxarea);
745static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 746/*
747 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
748 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
749 */
750static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 751static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 752
3e7c73e9
AK		 753static unsigned long *vmx_io_bitmap_a;
754static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 755static unsigned long *vmx_msr_bitmap_legacy;
756static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 757static unsigned long *vmx_msr_bitmap_legacy_x2apic;
758static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 759static unsigned long *vmx_vmread_bitmap;
760static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 761
110312c8 762static bool cpu_has_load_ia32_efer;
8bf00a52 763static bool cpu_has_load_perf_global_ctrl;
110312c8 764
2384d2b3
SY		 765static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
766static DEFINE_SPINLOCK(vmx_vpid_lock);
767
1c3d14fe 768static struct vmcs_config {
6aa8b732
AK		 769 int size;
770 int order;
771 u32 revision_id;
1c3d14fe
YS		 772 u32 pin_based_exec_ctrl;
773 u32 cpu_based_exec_ctrl;
f78e0e2e 774 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 775 u32 vmexit_ctrl;
776 u32 vmentry_ctrl;
777} vmcs_config;
6aa8b732 778
efff9e53 779static struct vmx_capability {
d56f546d
SY		 780 u32 ept;
781 u32 vpid;
782} vmx_capability;
783
6aa8b732
AK		 784#define VMX_SEGMENT_FIELD(seg) \
785 [VCPU_SREG_##seg] = { \
786 .selector = GUEST_##seg##_SELECTOR, \
787 .base = GUEST_##seg##_BASE, \
788 .limit = GUEST_##seg##_LIMIT, \
789 .ar_bytes = GUEST_##seg##_AR_BYTES, \
790 }
791
772e0318 792static const struct kvm_vmx_segment_field {
6aa8b732
AK		 793 unsigned selector;
794 unsigned base;
795 unsigned limit;
796 unsigned ar_bytes;
797} kvm_vmx_segment_fields[] = {
798 VMX_SEGMENT_FIELD(CS),
799 VMX_SEGMENT_FIELD(DS),
800 VMX_SEGMENT_FIELD(ES),
801 VMX_SEGMENT_FIELD(FS),
802 VMX_SEGMENT_FIELD(GS),
803 VMX_SEGMENT_FIELD(SS),
804 VMX_SEGMENT_FIELD(TR),
805 VMX_SEGMENT_FIELD(LDTR),
806};
807
26bb0981
AK		 808static u64 host_efer;
809
6de4f3ad
AK		 810static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
811
4d56c8a7 812/*
8c06585d 813 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 814 * away by decrementing the array size.
815 */
6aa8b732 816static const u32 vmx_msr_index[] = {
05b3e0c2 817#ifdef CONFIG_X86_64
44ea2b17 818 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 819#endif
8c06585d 820 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 821};
9d8f549d 822#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 823
31299944 824static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 829}
830
31299944 831static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
834 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 835 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 836}
837
31299944 838static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 839{
840 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
841 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 842 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 843}
844
31299944 845static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 846{
847 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
848 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
849}
850
31299944 851static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 852{
853 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
854 INTR_INFO_VALID_MASK)) ==
855 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
856}
857
31299944 858static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 859{
04547156 860 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 861}
862
31299944 863static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 864{
04547156 865 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 866}
867
31299944 868static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 869{
04547156 870 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 871}
872
31299944 873static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 874{
04547156
SY		 875 return vmcs_config.cpu_based_exec_ctrl &
876 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 877}
878
774ead3a 879static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 880{
04547156
SY		 881 return vmcs_config.cpu_based_2nd_exec_ctrl &
882 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
883}
884
8d14695f
YZ		 885static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
886{
887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
889}
890
83d4c286
YZ		 891static inline bool cpu_has_vmx_apic_register_virt(void)
892{
893 return vmcs_config.cpu_based_2nd_exec_ctrl &
894 SECONDARY_EXEC_APIC_REGISTER_VIRT;
895}
896
c7c9c56c
YZ		 897static inline bool cpu_has_vmx_virtual_intr_delivery(void)
898{
899 return vmcs_config.cpu_based_2nd_exec_ctrl &
900 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
901}
902
01e439be
YZ		 903static inline bool cpu_has_vmx_posted_intr(void)
904{
905 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
906}
907
908static inline bool cpu_has_vmx_apicv(void)
909{
910 return cpu_has_vmx_apic_register_virt() &&
911 cpu_has_vmx_virtual_intr_delivery() &&
912 cpu_has_vmx_posted_intr();
913}
914
04547156
SY		 915static inline bool cpu_has_vmx_flexpriority(void)
916{
917 return cpu_has_vmx_tpr_shadow() &&
918 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 919}
920
e799794e
MT		 921static inline bool cpu_has_vmx_ept_execute_only(void)
922{
31299944 923 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 924}
925
926static inline bool cpu_has_vmx_eptp_uncacheable(void)
927{
31299944 928 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 929}
930
931static inline bool cpu_has_vmx_eptp_writeback(void)
932{
31299944 933 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 934}
935
936static inline bool cpu_has_vmx_ept_2m_page(void)
937{
31299944 938 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 939}
940
878403b7
SY		 941static inline bool cpu_has_vmx_ept_1g_page(void)
942{
31299944 943 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 944}
945
4bc9b982
SY		 946static inline bool cpu_has_vmx_ept_4levels(void)
947{
948 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
949}
950
83c3a331
XH		 951static inline bool cpu_has_vmx_ept_ad_bits(void)
952{
953 return vmx_capability.ept & VMX_EPT_AD_BIT;
954}
955
31299944 956static inline bool cpu_has_vmx_invept_context(void)
d56f546d 957{
31299944 958 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 959}
960
31299944 961static inline bool cpu_has_vmx_invept_global(void)
d56f546d 962{
31299944 963 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 964}
965
518c8aee
GJ		 966static inline bool cpu_has_vmx_invvpid_single(void)
967{
968 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
969}
970
b9d762fa
GJ		 971static inline bool cpu_has_vmx_invvpid_global(void)
972{
973 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
974}
975
31299944 976static inline bool cpu_has_vmx_ept(void)
d56f546d 977{
04547156
SY		 978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 980}
981
31299944 982static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 983{
984 return vmcs_config.cpu_based_2nd_exec_ctrl &
985 SECONDARY_EXEC_UNRESTRICTED_GUEST;
986}
987
31299944 988static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 989{
990 return vmcs_config.cpu_based_2nd_exec_ctrl &
991 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
992}
993
31299944 994static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 995{
6d3e435e 996 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 997}
998
31299944 999static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1000{
04547156
SY		 1001 return vmcs_config.cpu_based_2nd_exec_ctrl &
1002 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1003}
1004
31299944 1005static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1006{
1007 return vmcs_config.cpu_based_2nd_exec_ctrl &
1008 SECONDARY_EXEC_RDTSCP;
1009}
1010
ad756a16
MJ		 1011static inline bool cpu_has_vmx_invpcid(void)
1012{
1013 return vmcs_config.cpu_based_2nd_exec_ctrl &
1014 SECONDARY_EXEC_ENABLE_INVPCID;
1015}
1016
31299944 1017static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1018{
1019 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1020}
1021
f5f48ee1
SY		 1022static inline bool cpu_has_vmx_wbinvd_exit(void)
1023{
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_WBINVD_EXITING;
1026}
1027
abc4fc58
AG		 1028static inline bool cpu_has_vmx_shadow_vmcs(void)
1029{
1030 u64 vmx_msr;
1031 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1032 /* check if the cpu supports writing r/o exit information fields */
1033 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1034 return false;
1035
1036 return vmcs_config.cpu_based_2nd_exec_ctrl &
1037 SECONDARY_EXEC_SHADOW_VMCS;
1038}
1039
04547156
SY		 1040static inline bool report_flexpriority(void)
1041{
1042 return flexpriority_enabled;
1043}
1044
fe3ef05c
NHE		 1045static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1046{
1047 return vmcs12->cpu_based_vm_exec_control & bit;
1048}
1049
1050static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1051{
1052 return (vmcs12->cpu_based_vm_exec_control &
1053 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1054 (vmcs12->secondary_vm_exec_control & bit);
1055}
1056
f5c4368f 1057static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1058{
1059 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1060}
1061
f4124500
JK		 1062static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1063{
1064 return vmcs12->pin_based_vm_exec_control &
1065 PIN_BASED_VMX_PREEMPTION_TIMER;
1066}
1067
155a97a3
NHE		 1068static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1069{
1070 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1071}
1072
644d711a
NHE		 1073static inline bool is_exception(u32 intr_info)
1074{
1075 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1076 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1077}
1078
533558bc
JK		 1079static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1080 u32 exit_intr_info,
1081 unsigned long exit_qualification);
7c177938
NHE		 1082static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1083 struct vmcs12 *vmcs12,
1084 u32 reason, unsigned long qualification);
1085
8b9cf98c 1086static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1087{
1088 int i;
1089
a2fa3e9f 1090 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1091 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1092 return i;
1093 return -1;
1094}
1095
2384d2b3
SY		 1096static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1097{
1098 struct {
1099 u64 vpid : 16;
1100 u64 rsvd : 48;
1101 u64 gva;
1102 } operand = { vpid, 0, gva };
1103
4ecac3fd 1104 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1105 /* CF==1 or ZF==1 --> rc = -1 */
1106 "; ja 1f ; ud2 ; 1:"
1107 : : "a"(&operand), "c"(ext) : "cc", "memory");
1108}
1109
1439442c
SY		 1110static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1111{
1112 struct {
1113 u64 eptp, gpa;
1114 } operand = {eptp, gpa};
1115
4ecac3fd 1116 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1117 /* CF==1 or ZF==1 --> rc = -1 */
1118 "; ja 1f ; ud2 ; 1:\n"
1119 : : "a" (&operand), "c" (ext) : "cc", "memory");
1120}
1121
26bb0981 1122static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1123{
1124 int i;
1125
8b9cf98c 1126 i = __find_msr_index(vmx, msr);
a75beee6 1127 if (i >= 0)
a2fa3e9f 1128 return &vmx->guest_msrs[i];
8b6d44c7 1129 return NULL;
7725f0ba
AK		 1130}
1131
6aa8b732
AK		 1132static void vmcs_clear(struct vmcs *vmcs)
1133{
1134 u64 phys_addr = __pa(vmcs);
1135 u8 error;
1136
4ecac3fd 1137 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1138 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1139 : "cc", "memory");
1140 if (error)
1141 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1142 vmcs, phys_addr);
1143}
1144
d462b819
NHE		 1145static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1146{
1147 vmcs_clear(loaded_vmcs->vmcs);
1148 loaded_vmcs->cpu = -1;
1149 loaded_vmcs->launched = 0;
1150}
1151
7725b894
DX		 1152static void vmcs_load(struct vmcs *vmcs)
1153{
1154 u64 phys_addr = __pa(vmcs);
1155 u8 error;
1156
1157 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1158 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1159 : "cc", "memory");
1160 if (error)
2844d849 1161 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1162 vmcs, phys_addr);
1163}
1164
8f536b76
ZY		 1165#ifdef CONFIG_KEXEC
1166/*
1167 * This bitmap is used to indicate whether the vmclear
1168 * operation is enabled on all cpus. All disabled by
1169 * default.
1170 */
1171static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1172
1173static inline void crash_enable_local_vmclear(int cpu)
1174{
1175 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1176}
1177
1178static inline void crash_disable_local_vmclear(int cpu)
1179{
1180 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1181}
1182
1183static inline int crash_local_vmclear_enabled(int cpu)
1184{
1185 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1186}
1187
1188static void crash_vmclear_local_loaded_vmcss(void)
1189{
1190 int cpu = raw_smp_processor_id();
1191 struct loaded_vmcs *v;
1192
1193 if (!crash_local_vmclear_enabled(cpu))
1194 return;
1195
1196 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1197 loaded_vmcss_on_cpu_link)
1198 vmcs_clear(v->vmcs);
1199}
1200#else
1201static inline void crash_enable_local_vmclear(int cpu) { }
1202static inline void crash_disable_local_vmclear(int cpu) { }
1203#endif /* CONFIG_KEXEC */
1204
d462b819 1205static void __loaded_vmcs_clear(void *arg)
6aa8b732 1206{
d462b819 1207 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1208 int cpu = raw_smp_processor_id();
6aa8b732 1209
d462b819
NHE		 1210 if (loaded_vmcs->cpu != cpu)
1211 return; /* vcpu migration can race with cpu offline */
1212 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1213 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1214 crash_disable_local_vmclear(cpu);
d462b819 1215 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1216
1217 /*
1218 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1219 * is before setting loaded_vmcs->vcpu to -1 which is done in
1220 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1221 * then adds the vmcs into percpu list before it is deleted.
1222 */
1223 smp_wmb();
1224
d462b819 1225 loaded_vmcs_init(loaded_vmcs);
8f536b76 1226 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1227}
1228
d462b819 1229static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1230{
e6c7d321
XG		 1231 int cpu = loaded_vmcs->cpu;
1232
1233 if (cpu != -1)
1234 smp_call_function_single(cpu,
1235 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1236}
1237
1760dd49 1238static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1239{
1240 if (vmx->vpid == 0)
1241 return;
1242
518c8aee
GJ		 1243 if (cpu_has_vmx_invvpid_single())
1244 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1245}
1246
b9d762fa
GJ		 1247static inline void vpid_sync_vcpu_global(void)
1248{
1249 if (cpu_has_vmx_invvpid_global())
1250 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1251}
1252
1253static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1254{
1255 if (cpu_has_vmx_invvpid_single())
1760dd49 1256 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1257 else
1258 vpid_sync_vcpu_global();
1259}
1260
1439442c
SY		 1261static inline void ept_sync_global(void)
1262{
1263 if (cpu_has_vmx_invept_global())
1264 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1265}
1266
1267static inline void ept_sync_context(u64 eptp)
1268{
089d034e 1269 if (enable_ept) {
1439442c
SY		 1270 if (cpu_has_vmx_invept_context())
1271 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1272 else
1273 ept_sync_global();
1274 }
1275}
1276
96304217 1277static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1278{
5e520e62 1279 unsigned long value;
6aa8b732 1280
5e520e62
AK		 1281 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1282 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1283 return value;
1284}
1285
96304217 1286static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1287{
1288 return vmcs_readl(field);
1289}
1290
96304217 1291static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1292{
1293 return vmcs_readl(field);
1294}
1295
96304217 1296static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1297{
05b3e0c2 1298#ifdef CONFIG_X86_64
6aa8b732
AK		 1299 return vmcs_readl(field);
1300#else
1301 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1302#endif
1303}
1304
e52de1b8
AK		 1305static noinline void vmwrite_error(unsigned long field, unsigned long value)
1306{
1307 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1308 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1309 dump_stack();
1310}
1311
6aa8b732
AK		 1312static void vmcs_writel(unsigned long field, unsigned long value)
1313{
1314 u8 error;
1315
4ecac3fd 1316 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1317 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1318 if (unlikely(error))
1319 vmwrite_error(field, value);
6aa8b732
AK		 1320}
1321
1322static void vmcs_write16(unsigned long field, u16 value)
1323{
1324 vmcs_writel(field, value);
1325}
1326
1327static void vmcs_write32(unsigned long field, u32 value)
1328{
1329 vmcs_writel(field, value);
1330}
1331
1332static void vmcs_write64(unsigned long field, u64 value)
1333{
6aa8b732 1334 vmcs_writel(field, value);
7682f2d0 1335#ifndef CONFIG_X86_64
6aa8b732
AK		 1336 asm volatile ("");
1337 vmcs_writel(field+1, value >> 32);
1338#endif
1339}
1340
2ab455cc
AL		 1341static void vmcs_clear_bits(unsigned long field, u32 mask)
1342{
1343 vmcs_writel(field, vmcs_readl(field) & ~mask);
1344}
1345
1346static void vmcs_set_bits(unsigned long field, u32 mask)
1347{
1348 vmcs_writel(field, vmcs_readl(field) | mask);
1349}
1350
2961e876
GN		 1351static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1352{
1353 vmcs_write32(VM_ENTRY_CONTROLS, val);
1354 vmx->vm_entry_controls_shadow = val;
1355}
1356
1357static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1358{
1359 if (vmx->vm_entry_controls_shadow != val)
1360 vm_entry_controls_init(vmx, val);
1361}
1362
1363static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1364{
1365 return vmx->vm_entry_controls_shadow;
1366}
1367
1368
1369static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1370{
1371 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1372}
1373
1374static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1375{
1376 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1377}
1378
1379static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1380{
1381 vmcs_write32(VM_EXIT_CONTROLS, val);
1382 vmx->vm_exit_controls_shadow = val;
1383}
1384
1385static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1386{
1387 if (vmx->vm_exit_controls_shadow != val)
1388 vm_exit_controls_init(vmx, val);
1389}
1390
1391static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1392{
1393 return vmx->vm_exit_controls_shadow;
1394}
1395
1396
1397static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1398{
1399 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1400}
1401
1402static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1403{
1404 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1405}
1406
2fb92db1
AK		 1407static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1408{
1409 vmx->segment_cache.bitmask = 0;
1410}
1411
1412static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1413 unsigned field)
1414{
1415 bool ret;
1416 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1417
1418 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1419 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1420 vmx->segment_cache.bitmask = 0;
1421 }
1422 ret = vmx->segment_cache.bitmask & mask;
1423 vmx->segment_cache.bitmask |= mask;
1424 return ret;
1425}
1426
1427static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1428{
1429 u16 *p = &vmx->segment_cache.seg[seg].selector;
1430
1431 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1432 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1433 return *p;
1434}
1435
1436static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1437{
1438 ulong *p = &vmx->segment_cache.seg[seg].base;
1439
1440 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1441 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1442 return *p;
1443}
1444
1445static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1446{
1447 u32 *p = &vmx->segment_cache.seg[seg].limit;
1448
1449 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1450 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1451 return *p;
1452}
1453
1454static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1455{
1456 u32 *p = &vmx->segment_cache.seg[seg].ar;
1457
1458 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1459 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1460 return *p;
1461}
1462
abd3f2d6
AK		 1463static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1464{
1465 u32 eb;
1466
fd7373cc
JK		 1467 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1468 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1469 if ((vcpu->guest_debug &
1470 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1471 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1472 eb |= 1u << BP_VECTOR;
7ffd92c5 1473 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1474 eb = ~0;
089d034e 1475 if (enable_ept)
1439442c 1476 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1477 if (vcpu->fpu_active)
1478 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1479
1480 /* When we are running a nested L2 guest and L1 specified for it a
1481 * certain exception bitmap, we must trap the same exceptions and pass
1482 * them to L1. When running L2, we will only handle the exceptions
1483 * specified above if L1 did not want them.
1484 */
1485 if (is_guest_mode(vcpu))
1486 eb |= get_vmcs12(vcpu)->exception_bitmap;
1487
abd3f2d6
AK		 1488 vmcs_write32(EXCEPTION_BITMAP, eb);
1489}
1490
2961e876
GN		 1491static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1492 unsigned long entry, unsigned long exit)
8bf00a52 1493{
2961e876
GN		 1494 vm_entry_controls_clearbit(vmx, entry);
1495 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1496}
1497
61d2ef2c
AK		 1498static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1499{
1500 unsigned i;
1501 struct msr_autoload *m = &vmx->msr_autoload;
1502
8bf00a52
GN		 1503 switch (msr) {
1504 case MSR_EFER:
1505 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1506 clear_atomic_switch_msr_special(vmx,
1507 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1508 VM_EXIT_LOAD_IA32_EFER);
1509 return;
1510 }
1511 break;
1512 case MSR_CORE_PERF_GLOBAL_CTRL:
1513 if (cpu_has_load_perf_global_ctrl) {
2961e876 1514 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1515 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1516 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1517 return;
1518 }
1519 break;
110312c8
AK		 1520 }
1521
61d2ef2c
AK		 1522 for (i = 0; i < m->nr; ++i)
1523 if (m->guest[i].index == msr)
1524 break;
1525
1526 if (i == m->nr)
1527 return;
1528 --m->nr;
1529 m->guest[i] = m->guest[m->nr];
1530 m->host[i] = m->host[m->nr];
1531 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1532 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1533}
1534
2961e876
GN		 1535static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1536 unsigned long entry, unsigned long exit,
1537 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1538 u64 guest_val, u64 host_val)
8bf00a52
GN		 1539{
1540 vmcs_write64(guest_val_vmcs, guest_val);
1541 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1542 vm_entry_controls_setbit(vmx, entry);
1543 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1544}
1545
61d2ef2c
AK		 1546static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1547 u64 guest_val, u64 host_val)
1548{
1549 unsigned i;
1550 struct msr_autoload *m = &vmx->msr_autoload;
1551
8bf00a52
GN		 1552 switch (msr) {
1553 case MSR_EFER:
1554 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1555 add_atomic_switch_msr_special(vmx,
1556 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1557 VM_EXIT_LOAD_IA32_EFER,
1558 GUEST_IA32_EFER,
1559 HOST_IA32_EFER,
1560 guest_val, host_val);
1561 return;
1562 }
1563 break;
1564 case MSR_CORE_PERF_GLOBAL_CTRL:
1565 if (cpu_has_load_perf_global_ctrl) {
2961e876 1566 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1567 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1568 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1569 GUEST_IA32_PERF_GLOBAL_CTRL,
1570 HOST_IA32_PERF_GLOBAL_CTRL,
1571 guest_val, host_val);
1572 return;
1573 }
1574 break;
110312c8
AK		 1575 }
1576
61d2ef2c
AK		 1577 for (i = 0; i < m->nr; ++i)
1578 if (m->guest[i].index == msr)
1579 break;
1580
e7fc6f93 1581 if (i == NR_AUTOLOAD_MSRS) {
60266204 1582 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1583 "Can't add msr %x\n", msr);
1584 return;
1585 } else if (i == m->nr) {
61d2ef2c
AK		 1586 ++m->nr;
1587 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1588 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1589 }
1590
1591 m->guest[i].index = msr;
1592 m->guest[i].value = guest_val;
1593 m->host[i].index = msr;
1594 m->host[i].value = host_val;
1595}
1596
33ed6329
AK		 1597static void reload_tss(void)
1598{
33ed6329
AK		 1599 /*
1600 * VT restores TR but not its size. Useless.
1601 */
d359192f 1602 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1603 struct desc_struct *descs;
33ed6329 1604
d359192f 1605 descs = (void *)gdt->address;
33ed6329
AK		 1606 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1607 load_TR_desc();
33ed6329
AK		 1608}
1609
92c0d900 1610static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1611{
3a34a881 1612 u64 guest_efer;
51c6cf66
AK		 1613 u64 ignore_bits;
1614
f6801dff 1615 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1616
51c6cf66 1617 /*
0fa06071 1618 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1619 * outside long mode
1620 */
1621 ignore_bits = EFER_NX | EFER_SCE;
1622#ifdef CONFIG_X86_64
1623 ignore_bits |= EFER_LMA | EFER_LME;
1624 /* SCE is meaningful only in long mode on Intel */
1625 if (guest_efer & EFER_LMA)
1626 ignore_bits &= ~(u64)EFER_SCE;
1627#endif
51c6cf66
AK		 1628 guest_efer &= ~ignore_bits;
1629 guest_efer |= host_efer & ignore_bits;
26bb0981 1630 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1631 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1632
1633 clear_atomic_switch_msr(vmx, MSR_EFER);
1634 /* On ept, can't emulate nx, and must switch nx atomically */
1635 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1636 guest_efer = vmx->vcpu.arch.efer;
1637 if (!(guest_efer & EFER_LMA))
1638 guest_efer &= ~EFER_LME;
1639 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1640 return false;
1641 }
1642
26bb0981 1643 return true;
51c6cf66
AK		 1644}
1645
2d49ec72
GN		 1646static unsigned long segment_base(u16 selector)
1647{
d359192f 1648 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1649 struct desc_struct *d;
1650 unsigned long table_base;
1651 unsigned long v;
1652
1653 if (!(selector & ~3))
1654 return 0;
1655
d359192f 1656 table_base = gdt->address;
2d49ec72
GN		 1657
1658 if (selector & 4) { /* from ldt */
1659 u16 ldt_selector = kvm_read_ldt();
1660
1661 if (!(ldt_selector & ~3))
1662 return 0;
1663
1664 table_base = segment_base(ldt_selector);
1665 }
1666 d = (struct desc_struct *)(table_base + (selector & ~7));
1667 v = get_desc_base(d);
1668#ifdef CONFIG_X86_64
1669 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1670 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1671#endif
1672 return v;
1673}
1674
1675static inline unsigned long kvm_read_tr_base(void)
1676{
1677 u16 tr;
1678 asm("str %0" : "=g"(tr));
1679 return segment_base(tr);
1680}
1681
04d2cc77 1682static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1683{
04d2cc77 1684 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1685 int i;
04d2cc77 1686
a2fa3e9f 1687 if (vmx->host_state.loaded)
33ed6329
AK		 1688 return;
1689
a2fa3e9f 1690 vmx->host_state.loaded = 1;
33ed6329
AK		 1691 /*
1692 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1693 * allow segment selectors with cpl > 0 or ti == 1.
1694 */
d6e88aec 1695 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1696 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1697 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1698 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1699 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1700 vmx->host_state.fs_reload_needed = 0;
1701 } else {
33ed6329 1702 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1703 vmx->host_state.fs_reload_needed = 1;
33ed6329 1704 }
9581d442 1705 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1706 if (!(vmx->host_state.gs_sel & 7))
1707 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1708 else {
1709 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1710 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1711 }
1712
b2da15ac
AK		 1713#ifdef CONFIG_X86_64
1714 savesegment(ds, vmx->host_state.ds_sel);
1715 savesegment(es, vmx->host_state.es_sel);
1716#endif
1717
33ed6329
AK		 1718#ifdef CONFIG_X86_64
1719 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1720 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1721#else
a2fa3e9f
GH		 1722 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1723 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1724#endif
707c0874
AK		 1725
1726#ifdef CONFIG_X86_64
c8770e7b
AK		 1727 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1728 if (is_long_mode(&vmx->vcpu))
44ea2b17 1729 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1730#endif
da8999d3
LJ		 1731 if (boot_cpu_has(X86_FEATURE_MPX))
1732 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1733 for (i = 0; i < vmx->save_nmsrs; ++i)
1734 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1735 vmx->guest_msrs[i].data,
1736 vmx->guest_msrs[i].mask);
33ed6329
AK		 1737}
1738
a9b21b62 1739static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1740{
a2fa3e9f 1741 if (!vmx->host_state.loaded)
33ed6329
AK		 1742 return;
1743
e1beb1d3 1744 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1745 vmx->host_state.loaded = 0;
c8770e7b
AK		 1746#ifdef CONFIG_X86_64
1747 if (is_long_mode(&vmx->vcpu))
1748 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1749#endif
152d3f2f 1750 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1751 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1752#ifdef CONFIG_X86_64
9581d442 1753 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1754#else
1755 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1756#endif
33ed6329 1757 }
0a77fe4c
AK		 1758 if (vmx->host_state.fs_reload_needed)
1759 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1760#ifdef CONFIG_X86_64
1761 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1762 loadsegment(ds, vmx->host_state.ds_sel);
1763 loadsegment(es, vmx->host_state.es_sel);
1764 }
b2da15ac 1765#endif
152d3f2f 1766 reload_tss();
44ea2b17 1767#ifdef CONFIG_X86_64
c8770e7b 1768 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1769#endif
da8999d3
LJ		 1770 if (vmx->host_state.msr_host_bndcfgs)
1771 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1772 /*
1773 * If the FPU is not active (through the host task or
1774 * the guest vcpu), then restore the cr0.TS bit.
1775 */
1776 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1777 stts();
3444d7da 1778 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1779}
1780
a9b21b62
AK		 1781static void vmx_load_host_state(struct vcpu_vmx *vmx)
1782{
1783 preempt_disable();
1784 __vmx_load_host_state(vmx);
1785 preempt_enable();
1786}
1787
6aa8b732
AK		 1788/*
1789 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1790 * vcpu mutex is already taken.
1791 */
15ad7146 1792static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1793{
a2fa3e9f 1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1795 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1796
4610c9cc
DX		 1797 if (!vmm_exclusive)
1798 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1799 else if (vmx->loaded_vmcs->cpu != cpu)
1800 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1801
d462b819
NHE		 1802 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1803 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1804 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1805 }
1806
d462b819 1807 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1808 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1809 unsigned long sysenter_esp;
1810
a8eeb04a 1811 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1812 local_irq_disable();
8f536b76 1813 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1814
1815 /*
1816 * Read loaded_vmcs->cpu should be before fetching
1817 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1818 * See the comments in __loaded_vmcs_clear().
1819 */
1820 smp_rmb();
1821
d462b819
NHE		 1822 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1823 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1824 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1825 local_irq_enable();
1826
6aa8b732
AK		 1827 /*
1828 * Linux uses per-cpu TSS and GDT, so set these when switching
1829 * processors.
1830 */
d6e88aec 1831 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1832 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1833
1834 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1835 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1836 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1837 }
6aa8b732
AK		 1838}
1839
1840static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1841{
a9b21b62 1842 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1843 if (!vmm_exclusive) {
d462b819
NHE		 1844 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1845 vcpu->cpu = -1;
4610c9cc
DX		 1846 kvm_cpu_vmxoff();
1847 }
6aa8b732
AK		 1848}
1849
5fd86fcf
AK		 1850static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1851{
81231c69
AK		 1852 ulong cr0;
1853
5fd86fcf
AK		 1854 if (vcpu->fpu_active)
1855 return;
1856 vcpu->fpu_active = 1;
81231c69
AK		 1857 cr0 = vmcs_readl(GUEST_CR0);
1858 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1859 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1860 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1861 update_exception_bitmap(vcpu);
edcafe3c 1862 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1863 if (is_guest_mode(vcpu))
1864 vcpu->arch.cr0_guest_owned_bits &=
1865 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1866 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1867}
1868
edcafe3c
AK		 1869static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1870
fe3ef05c
NHE		 1871/*
1872 * Return the cr0 value that a nested guest would read. This is a combination
1873 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1874 * its hypervisor (cr0_read_shadow).
1875 */
1876static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1877{
1878 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1879 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1880}
1881static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1882{
1883 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1884 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1885}
1886
5fd86fcf
AK		 1887static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1888{
36cf24e0
NHE		 1889 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1890 * set this *before* calling this function.
1891 */
edcafe3c 1892 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1893 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1894 update_exception_bitmap(vcpu);
edcafe3c
AK		 1895 vcpu->arch.cr0_guest_owned_bits = 0;
1896 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1897 if (is_guest_mode(vcpu)) {
1898 /*
1899 * L1's specified read shadow might not contain the TS bit,
1900 * so now that we turned on shadowing of this bit, we need to
1901 * set this bit of the shadow. Like in nested_vmx_run we need
1902 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1903 * up-to-date here because we just decached cr0.TS (and we'll
1904 * only update vmcs12->guest_cr0 on nested exit).
1905 */
1906 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1907 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1908 (vcpu->arch.cr0 & X86_CR0_TS);
1909 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1910 } else
1911 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1912}
1913
6aa8b732
AK		 1914static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1915{
78ac8b47 1916 unsigned long rflags, save_rflags;
345dcaa8 1917
6de12732
AK		 1918 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1919 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1920 rflags = vmcs_readl(GUEST_RFLAGS);
1921 if (to_vmx(vcpu)->rmode.vm86_active) {
1922 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1923 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1924 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1925 }
1926 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1927 }
6de12732 1928 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1929}
1930
1931static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1932{
6de12732
AK		 1933 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1934 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1935 if (to_vmx(vcpu)->rmode.vm86_active) {
1936 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1937 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1938 }
6aa8b732
AK		 1939 vmcs_writel(GUEST_RFLAGS, rflags);
1940}
1941
2809f5d2
GC		 1942static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1943{
1944 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1945 int ret = 0;
1946
1947 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1948 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1949 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1950 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1951
1952 return ret & mask;
1953}
1954
1955static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1956{
1957 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1958 u32 interruptibility = interruptibility_old;
1959
1960 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1961
48005f64 1962 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1963 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1964 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1965 interruptibility |= GUEST_INTR_STATE_STI;
1966
1967 if ((interruptibility != interruptibility_old))
1968 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1969}
1970
6aa8b732
AK		 1971static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1972{
1973 unsigned long rip;
6aa8b732 1974
5fdbf976 1975 rip = kvm_rip_read(vcpu);
6aa8b732 1976 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1977 kvm_rip_write(vcpu, rip);
6aa8b732 1978
2809f5d2
GC		 1979 /* skipping an emulated instruction also counts */
1980 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1981}
1982
0b6ac343
NHE		 1983/*
1984 * KVM wants to inject page-faults which it got to the guest. This function
1985 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1986 */
e011c663 1987static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1988{
1989 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1990
e011c663 1991 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1992 return 0;
1993
533558bc
JK		 1994 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1995 vmcs_read32(VM_EXIT_INTR_INFO),
1996 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1997 return 1;
1998}
1999
298101da 2000static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2001 bool has_error_code, u32 error_code,
2002 bool reinject)
298101da 2003{
77ab6db0 2004 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2005 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2006
e011c663
GN		 2007 if (!reinject && is_guest_mode(vcpu) &&
2008 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2009 return;
2010
8ab2d2e2 2011 if (has_error_code) {
77ab6db0 2012 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2013 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2014 }
77ab6db0 2015
7ffd92c5 2016 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2017 int inc_eip = 0;
2018 if (kvm_exception_is_soft(nr))
2019 inc_eip = vcpu->arch.event_exit_inst_len;
2020 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2021 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2022 return;
2023 }
2024
66fd3f7f
GN		 2025 if (kvm_exception_is_soft(nr)) {
2026 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2027 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2028 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2029 } else
2030 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2031
2032 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2033}
2034
4e47c7a6
SY		 2035static bool vmx_rdtscp_supported(void)
2036{
2037 return cpu_has_vmx_rdtscp();
2038}
2039
ad756a16
MJ		 2040static bool vmx_invpcid_supported(void)
2041{
2042 return cpu_has_vmx_invpcid() && enable_ept;
2043}
2044
a75beee6
ED		 2045/*
2046 * Swap MSR entry in host/guest MSR entry array.
2047 */
8b9cf98c 2048static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2049{
26bb0981 2050 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2051
2052 tmp = vmx->guest_msrs[to];
2053 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2054 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2055}
2056
8d14695f
YZ		 2057static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2058{
2059 unsigned long *msr_bitmap;
2060
2061 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2062 if (is_long_mode(vcpu))
2063 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2064 else
2065 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2066 } else {
2067 if (is_long_mode(vcpu))
2068 msr_bitmap = vmx_msr_bitmap_longmode;
2069 else
2070 msr_bitmap = vmx_msr_bitmap_legacy;
2071 }
2072
2073 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2074}
2075
e38aea3e
AK		 2076/*
2077 * Set up the vmcs to automatically save and restore system
2078 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2079 * mode, as fiddling with msrs is very expensive.
2080 */
8b9cf98c 2081static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2082{
26bb0981 2083 int save_nmsrs, index;
e38aea3e 2084
a75beee6
ED		 2085 save_nmsrs = 0;
2086#ifdef CONFIG_X86_64
8b9cf98c 2087 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2088 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2089 if (index >= 0)
8b9cf98c
RR		 2090 move_msr_up(vmx, index, save_nmsrs++);
2091 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2092 if (index >= 0)
8b9cf98c
RR		 2093 move_msr_up(vmx, index, save_nmsrs++);
2094 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2095 if (index >= 0)
8b9cf98c 2096 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2097 index = __find_msr_index(vmx, MSR_TSC_AUX);
2098 if (index >= 0 && vmx->rdtscp_enabled)
2099 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2100 /*
8c06585d 2101 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2102 * if efer.sce is enabled.
2103 */
8c06585d 2104 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2105 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2106 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2107 }
2108#endif
92c0d900
AK		 2109 index = __find_msr_index(vmx, MSR_EFER);
2110 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2111 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2112
26bb0981 2113 vmx->save_nmsrs = save_nmsrs;
5897297b 2114
8d14695f
YZ		 2115 if (cpu_has_vmx_msr_bitmap())
2116 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2117}
2118
6aa8b732
AK		 2119/*
2120 * reads and returns guest's timestamp counter "register"
2121 * guest_tsc = host_tsc + tsc_offset -- 21.3
2122 */
2123static u64 guest_read_tsc(void)
2124{
2125 u64 host_tsc, tsc_offset;
2126
2127 rdtscll(host_tsc);
2128 tsc_offset = vmcs_read64(TSC_OFFSET);
2129 return host_tsc + tsc_offset;
2130}
2131
d5c1785d
NHE		 2132/*
2133 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2134 * counter, even if a nested guest (L2) is currently running.
2135 */
886b470c 2136u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2137{
886b470c 2138 u64 tsc_offset;
d5c1785d 2139
d5c1785d
NHE		 2140 tsc_offset = is_guest_mode(vcpu) ?
2141 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2142 vmcs_read64(TSC_OFFSET);
2143 return host_tsc + tsc_offset;
2144}
2145
4051b188 2146/*
cc578287
ZA		 2147 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2148 * software catchup for faster rates on slower CPUs.
4051b188 2149 */
cc578287 2150static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2151{
cc578287
ZA		 2152 if (!scale)
2153 return;
2154
2155 if (user_tsc_khz > tsc_khz) {
2156 vcpu->arch.tsc_catchup = 1;
2157 vcpu->arch.tsc_always_catchup = 1;
2158 } else
2159 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2160}
2161
ba904635
WA		 2162static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2163{
2164 return vmcs_read64(TSC_OFFSET);
2165}
2166
6aa8b732 2167/*
99e3e30a 2168 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2169 */
99e3e30a 2170static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2171{
27fc51b2 2172 if (is_guest_mode(vcpu)) {
7991825b 2173 /*
27fc51b2
NHE		 2174 * We're here if L1 chose not to trap WRMSR to TSC. According
2175 * to the spec, this should set L1's TSC; The offset that L1
2176 * set for L2 remains unchanged, and still needs to be added
2177 * to the newly set TSC to get L2's TSC.
7991825b 2178 */
27fc51b2
NHE		 2179 struct vmcs12 *vmcs12;
2180 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2181 /* recalculate vmcs02.TSC_OFFSET: */
2182 vmcs12 = get_vmcs12(vcpu);
2183 vmcs_write64(TSC_OFFSET, offset +
2184 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2185 vmcs12->tsc_offset : 0));
2186 } else {
489223ed
YY		 2187 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2188 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2189 vmcs_write64(TSC_OFFSET, offset);
2190 }
6aa8b732
AK		 2191}
2192
f1e2b260 2193static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2194{
2195 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2196
e48672fa 2197 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2198 if (is_guest_mode(vcpu)) {
2199 /* Even when running L2, the adjustment needs to apply to L1 */
2200 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2201 } else
2202 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2203 offset + adjustment);
e48672fa
ZA		 2204}
2205
857e4099
JR		 2206static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2207{
2208 return target_tsc - native_read_tsc();
2209}
2210
801d3424
NHE		 2211static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2212{
2213 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2214 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2215}
2216
2217/*
2218 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2219 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2220 * all guests if the "nested" module option is off, and can also be disabled
2221 * for a single guest by disabling its VMX cpuid bit.
2222 */
2223static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2224{
2225 return nested && guest_cpuid_has_vmx(vcpu);
2226}
2227
b87a51ae
NHE		 2228/*
2229 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2230 * returned for the various VMX controls MSRs when nested VMX is enabled.
2231 * The same values should also be used to verify that vmcs12 control fields are
2232 * valid during nested entry from L1 to L2.
2233 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2234 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2235 * bit in the high half is on if the corresponding bit in the control field
2236 * may be on. See also vmx_control_verify().
2237 * TODO: allow these variables to be modified (downgraded) by module options
2238 * or other means.
2239 */
2240static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2241static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2242static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2243static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2244static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2245static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2246static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2247static __init void nested_vmx_setup_ctls_msrs(void)
2248{
2249 /*
2250 * Note that as a general rule, the high half of the MSRs (bits in
2251 * the control fields which may be 1) should be initialized by the
2252 * intersection of the underlying hardware's MSR (i.e., features which
2253 * can be supported) and the list of features we want to expose -
2254 * because they are known to be properly supported in our code.
2255 * Also, usually, the low half of the MSRs (bits which must be 1) can
2256 * be set to 0, meaning that L1 may turn off any of these bits. The
2257 * reason is that if one of these bits is necessary, it will appear
2258 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2259 * fields of vmcs01 and vmcs02, will turn these bits off - and
2260 * nested_vmx_exit_handled() will not pass related exits to L1.
2261 * These rules have exceptions below.
2262 */
2263
2264 /* pin-based controls */
eabeaacc
JK		 2265 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2266 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2267 /*
2268 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2269 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2270 */
eabeaacc
JK		 2271 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2272 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2273 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2274 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2275 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2276
33fb20c3
JK		 2277 /*
2278 * Exit controls
2279 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2280 * 17 must be 1.
2281 */
c0dfee58
ACL		 2282 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2283 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2284 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2285 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2286 nested_vmx_exit_ctls_high &=
b87a51ae 2287#ifdef CONFIG_X86_64
c0dfee58 2288 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2289#endif
f4124500
JK		 2290 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2291 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2292 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
7854cbca 2293 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
36be0b9d
PB		 2294 if (vmx_mpx_supported())
2295 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae
NHE		 2296
2297 /* entry controls */
2298 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2299 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2300 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2301 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2302 nested_vmx_entry_ctls_high &=
57435349
JK		 2303#ifdef CONFIG_X86_64
2304 VM_ENTRY_IA32E_MODE |
2305#endif
2306 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2307 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2308 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2309 if (vmx_mpx_supported())
2310 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2311
b87a51ae
NHE		 2312 /* cpu-based controls */
2313 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2314 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2315 nested_vmx_procbased_ctls_low = 0;
2316 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2317 CPU_BASED_VIRTUAL_INTR_PENDING |
2318 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2319 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2320 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2321 CPU_BASED_CR3_STORE_EXITING |
2322#ifdef CONFIG_X86_64
2323 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2324#endif
2325 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2326 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2327 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2328 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2329 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2330 /*
2331 * We can allow some features even when not supported by the
2332 * hardware. For example, L1 can specify an MSR bitmap - and we
2333 * can use it to avoid exits to L1 - even when L0 runs L2
2334 * without MSR bitmaps.
2335 */
2336 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2337
2338 /* secondary cpu-based controls */
2339 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2340 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2341 nested_vmx_secondary_ctls_low = 0;
2342 nested_vmx_secondary_ctls_high &=
d6851fbe 2343 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2344 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2345 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2346
afa61f75
NHE		 2347 if (enable_ept) {
2348 /* nested EPT: emulate EPT also to L1 */
2349 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2350 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2351 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2352 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2353 nested_vmx_ept_caps &= vmx_capability.ept;
2354 /*
2355 * Since invept is completely emulated we support both global
2356 * and context invalidation independent of what host cpu
2357 * supports
2358 */
2359 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2360 VMX_EPT_EXTENT_CONTEXT_BIT;
2361 } else
2362 nested_vmx_ept_caps = 0;
2363
c18911a2
JK		 2364 /* miscellaneous data */
2365 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2366 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2367 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2368 VMX_MISC_ACTIVITY_HLT;
c18911a2 2369 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2370}
2371
2372static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2373{
2374 /*
2375 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2376 */
2377 return ((control & high) | low) == control;
2378}
2379
2380static inline u64 vmx_control_msr(u32 low, u32 high)
2381{
2382 return low | ((u64)high << 32);
2383}
2384
cae50139 2385/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2386static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2387{
b87a51ae 2388 switch (msr_index) {
b87a51ae
NHE		 2389 case MSR_IA32_VMX_BASIC:
2390 /*
2391 * This MSR reports some information about VMX support. We
2392 * should return information about the VMX we emulate for the
2393 * guest, and the VMCS structure we give it - not about the
2394 * VMX support of the underlying hardware.
2395 */
2396 *pdata = VMCS12_REVISION |
2397 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2398 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2399 break;
2400 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2401 case MSR_IA32_VMX_PINBASED_CTLS:
2402 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2403 nested_vmx_pinbased_ctls_high);
2404 break;
2405 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2406 case MSR_IA32_VMX_PROCBASED_CTLS:
2407 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2408 nested_vmx_procbased_ctls_high);
2409 break;
2410 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2411 case MSR_IA32_VMX_EXIT_CTLS:
2412 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2413 nested_vmx_exit_ctls_high);
2414 break;
2415 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2416 case MSR_IA32_VMX_ENTRY_CTLS:
2417 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2418 nested_vmx_entry_ctls_high);
2419 break;
2420 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2421 *pdata = vmx_control_msr(nested_vmx_misc_low,
2422 nested_vmx_misc_high);
b87a51ae
NHE		 2423 break;
2424 /*
2425 * These MSRs specify bits which the guest must keep fixed (on or off)
2426 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2427 * We picked the standard core2 setting.
2428 */
2429#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2430#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2431 case MSR_IA32_VMX_CR0_FIXED0:
2432 *pdata = VMXON_CR0_ALWAYSON;
2433 break;
2434 case MSR_IA32_VMX_CR0_FIXED1:
2435 *pdata = -1ULL;
2436 break;
2437 case MSR_IA32_VMX_CR4_FIXED0:
2438 *pdata = VMXON_CR4_ALWAYSON;
2439 break;
2440 case MSR_IA32_VMX_CR4_FIXED1:
2441 *pdata = -1ULL;
2442 break;
2443 case MSR_IA32_VMX_VMCS_ENUM:
2444 *pdata = 0x1f;
2445 break;
2446 case MSR_IA32_VMX_PROCBASED_CTLS2:
2447 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2448 nested_vmx_secondary_ctls_high);
2449 break;
2450 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2451 /* Currently, no nested vpid support */
2452 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2453 break;
2454 default:
b87a51ae 2455 return 1;
b3897a49
NHE		 2456 }
2457
b87a51ae
NHE		 2458 return 0;
2459}
2460
6aa8b732
AK		 2461/*
2462 * Reads an msr value (of 'msr_index') into 'pdata'.
2463 * Returns 0 on success, non-0 otherwise.
2464 * Assumes vcpu_load() was already called.
2465 */
2466static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2467{
2468 u64 data;
26bb0981 2469 struct shared_msr_entry *msr;
6aa8b732
AK		 2470
2471 if (!pdata) {
2472 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2473 return -EINVAL;
2474 }
2475
2476 switch (msr_index) {
05b3e0c2 2477#ifdef CONFIG_X86_64
6aa8b732
AK		 2478 case MSR_FS_BASE:
2479 data = vmcs_readl(GUEST_FS_BASE);
2480 break;
2481 case MSR_GS_BASE:
2482 data = vmcs_readl(GUEST_GS_BASE);
2483 break;
44ea2b17
AK		 2484 case MSR_KERNEL_GS_BASE:
2485 vmx_load_host_state(to_vmx(vcpu));
2486 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2487 break;
26bb0981 2488#endif
6aa8b732 2489 case MSR_EFER:
3bab1f5d 2490 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2491 case MSR_IA32_TSC:
6aa8b732
AK		 2492 data = guest_read_tsc();
2493 break;
2494 case MSR_IA32_SYSENTER_CS:
2495 data = vmcs_read32(GUEST_SYSENTER_CS);
2496 break;
2497 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2498 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2499 break;
2500 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2501 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2502 break;
0dd376e7
LJ		 2503 case MSR_IA32_BNDCFGS:
2504 data = vmcs_read64(GUEST_BNDCFGS);
2505 break;
cae50139
JK		 2506 case MSR_IA32_FEATURE_CONTROL:
2507 if (!nested_vmx_allowed(vcpu))
2508 return 1;
2509 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2510 break;
2511 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2512 if (!nested_vmx_allowed(vcpu))
2513 return 1;
2514 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2515 case MSR_TSC_AUX:
2516 if (!to_vmx(vcpu)->rdtscp_enabled)
2517 return 1;
2518 /* Otherwise falls through */
6aa8b732 2519 default:
8b9cf98c 2520 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2521 if (msr) {
2522 data = msr->data;
2523 break;
6aa8b732 2524 }
3bab1f5d 2525 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2526 }
2527
2528 *pdata = data;
2529 return 0;
2530}
2531
cae50139
JK		 2532static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2533
6aa8b732
AK		 2534/*
2535 * Writes msr value into into the appropriate "register".
2536 * Returns 0 on success, non-0 otherwise.
2537 * Assumes vcpu_load() was already called.
2538 */
8fe8ab46 2539static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2540{
a2fa3e9f 2541 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2542 struct shared_msr_entry *msr;
2cc51560 2543 int ret = 0;
8fe8ab46
WA		 2544 u32 msr_index = msr_info->index;
2545 u64 data = msr_info->data;
2cc51560 2546
6aa8b732 2547 switch (msr_index) {
3bab1f5d 2548 case MSR_EFER:
8fe8ab46 2549 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2550 break;
16175a79 2551#ifdef CONFIG_X86_64
6aa8b732 2552 case MSR_FS_BASE:
2fb92db1 2553 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2554 vmcs_writel(GUEST_FS_BASE, data);
2555 break;
2556 case MSR_GS_BASE:
2fb92db1 2557 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2558 vmcs_writel(GUEST_GS_BASE, data);
2559 break;
44ea2b17
AK		 2560 case MSR_KERNEL_GS_BASE:
2561 vmx_load_host_state(vmx);
2562 vmx->msr_guest_kernel_gs_base = data;
2563 break;
6aa8b732
AK		 2564#endif
2565 case MSR_IA32_SYSENTER_CS:
2566 vmcs_write32(GUEST_SYSENTER_CS, data);
2567 break;
2568 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2569 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2570 break;
2571 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2572 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2573 break;
0dd376e7
LJ		 2574 case MSR_IA32_BNDCFGS:
2575 vmcs_write64(GUEST_BNDCFGS, data);
2576 break;
af24a4e4 2577 case MSR_IA32_TSC:
8fe8ab46 2578 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2579 break;
468d472f
SY		 2580 case MSR_IA32_CR_PAT:
2581 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2582 vmcs_write64(GUEST_IA32_PAT, data);
2583 vcpu->arch.pat = data;
2584 break;
2585 }
8fe8ab46 2586 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2587 break;
ba904635
WA		 2588 case MSR_IA32_TSC_ADJUST:
2589 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2590 break;
cae50139
JK		 2591 case MSR_IA32_FEATURE_CONTROL:
2592 if (!nested_vmx_allowed(vcpu) ||
2593 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2594 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2595 return 1;
2596 vmx->nested.msr_ia32_feature_control = data;
2597 if (msr_info->host_initiated && data == 0)
2598 vmx_leave_nested(vcpu);
2599 break;
2600 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2601 return 1; /* they are read-only */
4e47c7a6
SY		 2602 case MSR_TSC_AUX:
2603 if (!vmx->rdtscp_enabled)
2604 return 1;
2605 /* Check reserved bit, higher 32 bits should be zero */
2606 if ((data >> 32) != 0)
2607 return 1;
2608 /* Otherwise falls through */
6aa8b732 2609 default:
8b9cf98c 2610 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2611 if (msr) {
2612 msr->data = data;
2225fd56
AK		 2613 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2614 preempt_disable();
9ee73970
AK		 2615 kvm_set_shared_msr(msr->index, msr->data,
2616 msr->mask);
2225fd56
AK		 2617 preempt_enable();
2618 }
3bab1f5d 2619 break;
6aa8b732 2620 }
8fe8ab46 2621 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2622 }
2623
2cc51560 2624 return ret;
6aa8b732
AK		 2625}
2626
5fdbf976 2627static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2628{
5fdbf976
MT		 2629 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2630 switch (reg) {
2631 case VCPU_REGS_RSP:
2632 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2633 break;
2634 case VCPU_REGS_RIP:
2635 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2636 break;
6de4f3ad
AK		 2637 case VCPU_EXREG_PDPTR:
2638 if (enable_ept)
2639 ept_save_pdptrs(vcpu);
2640 break;
5fdbf976
MT		 2641 default:
2642 break;
2643 }
6aa8b732
AK		 2644}
2645
6aa8b732
AK		 2646static __init int cpu_has_kvm_support(void)
2647{
6210e37b 2648 return cpu_has_vmx();
6aa8b732
AK		 2649}
2650
2651static __init int vmx_disabled_by_bios(void)
2652{
2653 u64 msr;
2654
2655 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2656 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2657 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2658 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2659 && tboot_enabled())
2660 return 1;
23f3e991 2661 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2662 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2663 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2664 && !tboot_enabled()) {
2665 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2666 "activate TXT before enabling KVM\n");
cafd6659 2667 return 1;
f9335afe 2668 }
23f3e991
JC		 2669 /* launched w/o TXT and VMX disabled */
2670 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2671 && !tboot_enabled())
2672 return 1;
cafd6659
SW		 2673 }
2674
2675 return 0;
6aa8b732
AK		 2676}
2677
7725b894
DX		 2678static void kvm_cpu_vmxon(u64 addr)
2679{
2680 asm volatile (ASM_VMX_VMXON_RAX
2681 : : "a"(&addr), "m"(addr)
2682 : "memory", "cc");
2683}
2684
10474ae8 2685static int hardware_enable(void *garbage)
6aa8b732
AK		 2686{
2687 int cpu = raw_smp_processor_id();
2688 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2689 u64 old, test_bits;
6aa8b732 2690
10474ae8
AG		 2691 if (read_cr4() & X86_CR4_VMXE)
2692 return -EBUSY;
2693
d462b819 2694 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2695
2696 /*
2697 * Now we can enable the vmclear operation in kdump
2698 * since the loaded_vmcss_on_cpu list on this cpu
2699 * has been initialized.
2700 *
2701 * Though the cpu is not in VMX operation now, there
2702 * is no problem to enable the vmclear operation
2703 * for the loaded_vmcss_on_cpu list is empty!
2704 */
2705 crash_enable_local_vmclear(cpu);
2706
6aa8b732 2707 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2708
2709 test_bits = FEATURE_CONTROL_LOCKED;
2710 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2711 if (tboot_enabled())
2712 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2713
2714 if ((old & test_bits) != test_bits) {
6aa8b732 2715 /* enable and lock */
cafd6659
SW		 2716 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2717 }
66aee91a 2718 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2719
4610c9cc
DX		 2720 if (vmm_exclusive) {
2721 kvm_cpu_vmxon(phys_addr);
2722 ept_sync_global();
2723 }
10474ae8 2724
357d1226 2725 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2726
10474ae8 2727 return 0;
6aa8b732
AK		 2728}
2729
d462b819 2730static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2731{
2732 int cpu = raw_smp_processor_id();
d462b819 2733 struct loaded_vmcs *v, *n;
543e4243 2734
d462b819
NHE		 2735 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2736 loaded_vmcss_on_cpu_link)
2737 __loaded_vmcs_clear(v);
543e4243
AK		 2738}
2739
710ff4a8
EH		 2740
2741/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2742 * tricks.
2743 */
2744static void kvm_cpu_vmxoff(void)
6aa8b732 2745{
4ecac3fd 2746 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2747}
2748
710ff4a8
EH		 2749static void hardware_disable(void *garbage)
2750{
4610c9cc 2751 if (vmm_exclusive) {
d462b819 2752 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2753 kvm_cpu_vmxoff();
2754 }
7725b894 2755 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2756}
2757
1c3d14fe 2758static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2759 u32 msr, u32 *result)
1c3d14fe
YS		 2760{
2761 u32 vmx_msr_low, vmx_msr_high;
2762 u32 ctl = ctl_min | ctl_opt;
2763
2764 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2765
2766 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2767 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2768
2769 /* Ensure minimum (required) set of control bits are supported. */
2770 if (ctl_min & ~ctl)
002c7f7c 2771 return -EIO;
1c3d14fe
YS		 2772
2773 *result = ctl;
2774 return 0;
2775}
2776
110312c8
AK		 2777static __init bool allow_1_setting(u32 msr, u32 ctl)
2778{
2779 u32 vmx_msr_low, vmx_msr_high;
2780
2781 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2782 return vmx_msr_high & ctl;
2783}
2784
002c7f7c 2785static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2786{
2787 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2788 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2789 u32 _pin_based_exec_control = 0;
2790 u32 _cpu_based_exec_control = 0;
f78e0e2e 2791 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2792 u32 _vmexit_control = 0;
2793 u32 _vmentry_control = 0;
2794
10166744 2795 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2796#ifdef CONFIG_X86_64
2797 CPU_BASED_CR8_LOAD_EXITING |
2798 CPU_BASED_CR8_STORE_EXITING |
2799#endif
d56f546d
SY		 2800 CPU_BASED_CR3_LOAD_EXITING |
2801 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2802 CPU_BASED_USE_IO_BITMAPS |
2803 CPU_BASED_MOV_DR_EXITING |
a7052897 2804 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2805 CPU_BASED_MWAIT_EXITING |
2806 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2807 CPU_BASED_INVLPG_EXITING |
2808 CPU_BASED_RDPMC_EXITING;
443381a8 2809
f78e0e2e 2810 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2811 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2812 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2813 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2814 &_cpu_based_exec_control) < 0)
002c7f7c 2815 return -EIO;
6e5d865c
YS		 2816#ifdef CONFIG_X86_64
2817 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2818 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2819 ~CPU_BASED_CR8_STORE_EXITING;
2820#endif
f78e0e2e 2821 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2822 min2 = 0;
2823 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2824 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2825 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2826 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2827 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2828 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2829 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2830 SECONDARY_EXEC_RDTSCP |
83d4c286 2831 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2832 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2833 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2834 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2835 if (adjust_vmx_controls(min2, opt2,
2836 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2837 &_cpu_based_2nd_exec_control) < 0)
2838 return -EIO;
2839 }
2840#ifndef CONFIG_X86_64
2841 if (!(_cpu_based_2nd_exec_control &
2842 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2843 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2844#endif
83d4c286
YZ		 2845
2846 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2847 _cpu_based_2nd_exec_control &= ~(
8d14695f 2848 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2849 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2850 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2851
d56f546d 2852 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2853 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2854 enabled */
5fff7d27
GN		 2855 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2856 CPU_BASED_CR3_STORE_EXITING |
2857 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2858 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2859 vmx_capability.ept, vmx_capability.vpid);
2860 }
1c3d14fe 2861
81908bf4 2862 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2863#ifdef CONFIG_X86_64
2864 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2865#endif
a547c6db 2866 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2867 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2868 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2869 &_vmexit_control) < 0)
002c7f7c 2870 return -EIO;
1c3d14fe 2871
01e439be
YZ		 2872 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2873 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2874 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2875 &_pin_based_exec_control) < 0)
2876 return -EIO;
2877
2878 if (!(_cpu_based_2nd_exec_control &
2879 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2880 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2881 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2882
c845f9c6 2883 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2884 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2885 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2886 &_vmentry_control) < 0)
002c7f7c 2887 return -EIO;
6aa8b732 2888
c68876fd 2889 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2890
2891 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2892 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2893 return -EIO;
1c3d14fe
YS		 2894
2895#ifdef CONFIG_X86_64
2896 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2897 if (vmx_msr_high & (1u<<16))
002c7f7c 2898 return -EIO;
1c3d14fe
YS		 2899#endif
2900
2901 /* Require Write-Back (WB) memory type for VMCS accesses. */
2902 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2903 return -EIO;
1c3d14fe 2904
002c7f7c
YS		 2905 vmcs_conf->size = vmx_msr_high & 0x1fff;
2906 vmcs_conf->order = get_order(vmcs_config.size);
2907 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2908
002c7f7c
YS		 2909 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2910 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2911 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2912 vmcs_conf->vmexit_ctrl = _vmexit_control;
2913 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2914
110312c8
AK		 2915 cpu_has_load_ia32_efer =
2916 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2917 VM_ENTRY_LOAD_IA32_EFER)
2918 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2919 VM_EXIT_LOAD_IA32_EFER);
2920
8bf00a52
GN		 2921 cpu_has_load_perf_global_ctrl =
2922 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2923 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2924 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2925 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2926
2927 /*
2928 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2929 * but due to arrata below it can't be used. Workaround is to use
2930 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2931 *
2932 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2933 *
2934 * AAK155 (model 26)
2935 * AAP115 (model 30)
2936 * AAT100 (model 37)
2937 * BC86,AAY89,BD102 (model 44)
2938 * BA97 (model 46)
2939 *
2940 */
2941 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2942 switch (boot_cpu_data.x86_model) {
2943 case 26:
2944 case 30:
2945 case 37:
2946 case 44:
2947 case 46:
2948 cpu_has_load_perf_global_ctrl = false;
2949 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2950 "does not work properly. Using workaround\n");
2951 break;
2952 default:
2953 break;
2954 }
2955 }
2956
1c3d14fe 2957 return 0;
c68876fd 2958}
6aa8b732
AK		 2959
2960static struct vmcs *alloc_vmcs_cpu(int cpu)
2961{
2962 int node = cpu_to_node(cpu);
2963 struct page *pages;
2964 struct vmcs *vmcs;
2965
6484eb3e 2966 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2967 if (!pages)
2968 return NULL;
2969 vmcs = page_address(pages);
1c3d14fe
YS		 2970 memset(vmcs, 0, vmcs_config.size);
2971 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2972 return vmcs;
2973}
2974
2975static struct vmcs *alloc_vmcs(void)
2976{
d3b2c338 2977 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2978}
2979
2980static void free_vmcs(struct vmcs *vmcs)
2981{
1c3d14fe 2982 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2983}
2984
d462b819
NHE		 2985/*
2986 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2987 */
2988static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2989{
2990 if (!loaded_vmcs->vmcs)
2991 return;
2992 loaded_vmcs_clear(loaded_vmcs);
2993 free_vmcs(loaded_vmcs->vmcs);
2994 loaded_vmcs->vmcs = NULL;
2995}
2996
39959588 2997static void free_kvm_area(void)
6aa8b732
AK		 2998{
2999 int cpu;
3000
3230bb47 3001 for_each_possible_cpu(cpu) {
6aa8b732 3002 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3003 per_cpu(vmxarea, cpu) = NULL;
3004 }
6aa8b732
AK		 3005}
3006
6aa8b732
AK		 3007static __init int alloc_kvm_area(void)
3008{
3009 int cpu;
3010
3230bb47 3011 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3012 struct vmcs *vmcs;
3013
3014 vmcs = alloc_vmcs_cpu(cpu);
3015 if (!vmcs) {
3016 free_kvm_area();
3017 return -ENOMEM;
3018 }
3019
3020 per_cpu(vmxarea, cpu) = vmcs;
3021 }
3022 return 0;
3023}
3024
3025static __init int hardware_setup(void)
3026{
002c7f7c
YS		 3027 if (setup_vmcs_config(&vmcs_config) < 0)
3028 return -EIO;
50a37eb4
JR		 3029
3030 if (boot_cpu_has(X86_FEATURE_NX))
3031 kvm_enable_efer_bits(EFER_NX);
3032
93ba03c2
SY		 3033 if (!cpu_has_vmx_vpid())
3034 enable_vpid = 0;
abc4fc58
AG		 3035 if (!cpu_has_vmx_shadow_vmcs())
3036 enable_shadow_vmcs = 0;
93ba03c2 3037
4bc9b982
SY		 3038 if (!cpu_has_vmx_ept() ||
3039 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3040 enable_ept = 0;
3a624e29 3041 enable_unrestricted_guest = 0;
83c3a331 3042 enable_ept_ad_bits = 0;
3a624e29
NK		 3043 }
3044
83c3a331
XH		 3045 if (!cpu_has_vmx_ept_ad_bits())
3046 enable_ept_ad_bits = 0;
3047
3a624e29
NK		 3048 if (!cpu_has_vmx_unrestricted_guest())
3049 enable_unrestricted_guest = 0;
93ba03c2
SY		 3050
3051 if (!cpu_has_vmx_flexpriority())
3052 flexpriority_enabled = 0;
3053
95ba8273
GN		 3054 if (!cpu_has_vmx_tpr_shadow())
3055 kvm_x86_ops->update_cr8_intercept = NULL;
3056
54dee993
MT		 3057 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3058 kvm_disable_largepages();
3059
4b8d54f9
ZE		 3060 if (!cpu_has_vmx_ple())
3061 ple_gap = 0;
3062
01e439be
YZ		 3063 if (!cpu_has_vmx_apicv())
3064 enable_apicv = 0;
c7c9c56c 3065
01e439be 3066 if (enable_apicv)
c7c9c56c 3067 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3068 else {
c7c9c56c 3069 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3070 kvm_x86_ops->deliver_posted_interrupt = NULL;
3071 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3072 }
83d4c286 3073
b87a51ae
NHE		 3074 if (nested)
3075 nested_vmx_setup_ctls_msrs();
3076
6aa8b732
AK		 3077 return alloc_kvm_area();
3078}
3079
3080static __exit void hardware_unsetup(void)
3081{
3082 free_kvm_area();
3083}
3084
14168786
GN		 3085static bool emulation_required(struct kvm_vcpu *vcpu)
3086{
3087 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3088}
3089
91b0aa2c 3090static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3091 struct kvm_segment *save)
6aa8b732 3092{
d99e4152
GN		 3093 if (!emulate_invalid_guest_state) {
3094 /*
3095 * CS and SS RPL should be equal during guest entry according
3096 * to VMX spec, but in reality it is not always so. Since vcpu
3097 * is in the middle of the transition from real mode to
3098 * protected mode it is safe to assume that RPL 0 is a good
3099 * default value.
3100 */
3101 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3102 save->selector &= ~SELECTOR_RPL_MASK;
3103 save->dpl = save->selector & SELECTOR_RPL_MASK;
3104 save->s = 1;
6aa8b732 3105 }
d99e4152 3106 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3107}
3108
3109static void enter_pmode(struct kvm_vcpu *vcpu)
3110{
3111 unsigned long flags;
a89a8fb9 3112 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3113
d99e4152
GN		 3114 /*
3115 * Update real mode segment cache. It may be not up-to-date if sement
3116 * register was written while vcpu was in a guest mode.
3117 */
3118 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3119 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3121 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3123 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3124
7ffd92c5 3125 vmx->rmode.vm86_active = 0;
6aa8b732 3126
2fb92db1
AK		 3127 vmx_segment_cache_clear(vmx);
3128
f5f7b2fe 3129 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3130
3131 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3132 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3133 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3134 vmcs_writel(GUEST_RFLAGS, flags);
3135
66aee91a
RR		 3136 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3137 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3138
3139 update_exception_bitmap(vcpu);
3140
91b0aa2c
GN		 3141 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3142 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3143 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3144 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3145 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3146 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3147
3148 /* CPL is always 0 when CPU enters protected mode */
3149 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3150 vmx->cpl = 0;
6aa8b732
AK		 3151}
3152
f5f7b2fe 3153static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3154{
772e0318 3155 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3156 struct kvm_segment var = *save;
3157
3158 var.dpl = 0x3;
3159 if (seg == VCPU_SREG_CS)
3160 var.type = 0x3;
3161
3162 if (!emulate_invalid_guest_state) {
3163 var.selector = var.base >> 4;
3164 var.base = var.base & 0xffff0;
3165 var.limit = 0xffff;
3166 var.g = 0;
3167 var.db = 0;
3168 var.present = 1;
3169 var.s = 1;
3170 var.l = 0;
3171 var.unusable = 0;
3172 var.type = 0x3;
3173 var.avl = 0;
3174 if (save->base & 0xf)
3175 printk_once(KERN_WARNING "kvm: segment base is not "
3176 "paragraph aligned when entering "
3177 "protected mode (seg=%d)", seg);
3178 }
6aa8b732 3179
d99e4152
GN		 3180 vmcs_write16(sf->selector, var.selector);
3181 vmcs_write32(sf->base, var.base);
3182 vmcs_write32(sf->limit, var.limit);
3183 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3184}
3185
3186static void enter_rmode(struct kvm_vcpu *vcpu)
3187{
3188 unsigned long flags;
a89a8fb9 3189 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3190
f5f7b2fe
AK		 3191 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3192 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3193 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3194 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3195 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3196 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3197 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3198
7ffd92c5 3199 vmx->rmode.vm86_active = 1;
6aa8b732 3200
776e58ea
GN		 3201 /*
3202 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3203 * vcpu. Warn the user that an update is overdue.
776e58ea 3204 */
4918c6ca 3205 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3206 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3207 "called before entering vcpu\n");
776e58ea 3208
2fb92db1
AK		 3209 vmx_segment_cache_clear(vmx);
3210
4918c6ca 3211 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3212 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3213 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3214
3215 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3216 vmx->rmode.save_rflags = flags;
6aa8b732 3217
053de044 3218 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3219
3220 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3221 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3222 update_exception_bitmap(vcpu);
3223
d99e4152
GN		 3224 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3225 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3226 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3227 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3228 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3229 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3230
8668a3c4 3231 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3232}
3233
401d10de
AS		 3234static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3235{
3236 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3237 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3238
3239 if (!msr)
3240 return;
401d10de 3241
44ea2b17
AK		 3242 /*
3243 * Force kernel_gs_base reloading before EFER changes, as control
3244 * of this msr depends on is_long_mode().
3245 */
3246 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3247 vcpu->arch.efer = efer;
401d10de 3248 if (efer & EFER_LMA) {
2961e876 3249 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3250 msr->data = efer;
3251 } else {
2961e876 3252 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3253
3254 msr->data = efer & ~EFER_LME;
3255 }
3256 setup_msrs(vmx);
3257}
3258
05b3e0c2 3259#ifdef CONFIG_X86_64
6aa8b732
AK		 3260
3261static void enter_lmode(struct kvm_vcpu *vcpu)
3262{
3263 u32 guest_tr_ar;
3264
2fb92db1
AK		 3265 vmx_segment_cache_clear(to_vmx(vcpu));
3266
6aa8b732
AK		 3267 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3268 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3269 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3270 __func__);
6aa8b732
AK		 3271 vmcs_write32(GUEST_TR_AR_BYTES,
3272 (guest_tr_ar & ~AR_TYPE_MASK)
3273 | AR_TYPE_BUSY_64_TSS);
3274 }
da38f438 3275 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3276}
3277
3278static void exit_lmode(struct kvm_vcpu *vcpu)
3279{
2961e876 3280 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3281 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3282}
3283
3284#endif
3285
2384d2b3
SY		 3286static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3287{
b9d762fa 3288 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3289 if (enable_ept) {
3290 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3291 return;
4e1096d2 3292 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3293 }
2384d2b3
SY		 3294}
3295
e8467fda
AK		 3296static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3297{
3298 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3299
3300 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3301 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3302}
3303
aff48baa
AK		 3304static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3305{
3306 if (enable_ept && is_paging(vcpu))
3307 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3308 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3309}
3310
25c4c276 3311static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3312{
fc78f519
AK		 3313 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3314
3315 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3316 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3317}
3318
1439442c
SY		 3319static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3320{
d0d538b9
GN		 3321 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3322
6de4f3ad
AK		 3323 if (!test_bit(VCPU_EXREG_PDPTR,
3324 (unsigned long *)&vcpu->arch.regs_dirty))
3325 return;
3326
1439442c 3327 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3328 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3329 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3330 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3331 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3332 }
3333}
3334
8f5d549f
AK		 3335static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3336{
d0d538b9
GN		 3337 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3338
8f5d549f 3339 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3340 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3341 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3342 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3343 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3344 }
6de4f3ad
AK		 3345
3346 __set_bit(VCPU_EXREG_PDPTR,
3347 (unsigned long *)&vcpu->arch.regs_avail);
3348 __set_bit(VCPU_EXREG_PDPTR,
3349 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3350}
3351
5e1746d6 3352static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3353
3354static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3355 unsigned long cr0,
3356 struct kvm_vcpu *vcpu)
3357{
5233dd51
MT		 3358 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3359 vmx_decache_cr3(vcpu);
1439442c
SY		 3360 if (!(cr0 & X86_CR0_PG)) {
3361 /* From paging/starting to nonpaging */
3362 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3363 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3364 (CPU_BASED_CR3_LOAD_EXITING |
3365 CPU_BASED_CR3_STORE_EXITING));
3366 vcpu->arch.cr0 = cr0;
fc78f519 3367 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3368 } else if (!is_paging(vcpu)) {
3369 /* From nonpaging to paging */
3370 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3371 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3372 ~(CPU_BASED_CR3_LOAD_EXITING |
3373 CPU_BASED_CR3_STORE_EXITING));
3374 vcpu->arch.cr0 = cr0;
fc78f519 3375 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3376 }
95eb84a7
SY		 3377
3378 if (!(cr0 & X86_CR0_WP))
3379 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3380}
3381
6aa8b732
AK		 3382static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3383{
7ffd92c5 3384 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3385 unsigned long hw_cr0;
3386
5037878e 3387 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3388 if (enable_unrestricted_guest)
5037878e 3389 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3390 else {
5037878e 3391 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3392
218e763f
GN		 3393 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3394 enter_pmode(vcpu);
6aa8b732 3395
218e763f
GN		 3396 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3397 enter_rmode(vcpu);
3398 }
6aa8b732 3399
05b3e0c2 3400#ifdef CONFIG_X86_64
f6801dff 3401 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3402 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3403 enter_lmode(vcpu);
707d92fa 3404 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3405 exit_lmode(vcpu);
3406 }
3407#endif
3408
089d034e 3409 if (enable_ept)
1439442c
SY		 3410 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3411
02daab21 3412 if (!vcpu->fpu_active)
81231c69 3413 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3414
6aa8b732 3415 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3416 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3417 vcpu->arch.cr0 = cr0;
14168786
GN		 3418
3419 /* depends on vcpu->arch.cr0 to be set to a new value */
3420 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3421}
3422
1439442c
SY		 3423static u64 construct_eptp(unsigned long root_hpa)
3424{
3425 u64 eptp;
3426
3427 /* TODO write the value reading from MSR */
3428 eptp = VMX_EPT_DEFAULT_MT |
3429 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3430 if (enable_ept_ad_bits)
3431 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3432 eptp |= (root_hpa & PAGE_MASK);
3433
3434 return eptp;
3435}
3436
6aa8b732
AK		 3437static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3438{
1439442c
SY		 3439 unsigned long guest_cr3;
3440 u64 eptp;
3441
3442 guest_cr3 = cr3;
089d034e 3443 if (enable_ept) {
1439442c
SY		 3444 eptp = construct_eptp(cr3);
3445 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3446 if (is_paging(vcpu) || is_guest_mode(vcpu))
3447 guest_cr3 = kvm_read_cr3(vcpu);
3448 else
3449 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3450 ept_load_pdptrs(vcpu);
1439442c
SY		 3451 }
3452
2384d2b3 3453 vmx_flush_tlb(vcpu);
1439442c 3454 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3455}
3456
5e1746d6 3457static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3458{
7ffd92c5 3459 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3460 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3461
5e1746d6
NHE		 3462 if (cr4 & X86_CR4_VMXE) {
3463 /*
3464 * To use VMXON (and later other VMX instructions), a guest
3465 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3466 * So basically the check on whether to allow nested VMX
3467 * is here.
3468 */
3469 if (!nested_vmx_allowed(vcpu))
3470 return 1;
1a0d74e6
JK		 3471 }
3472 if (to_vmx(vcpu)->nested.vmxon &&
3473 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3474 return 1;
3475
ad312c7c 3476 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3477 if (enable_ept) {
3478 if (!is_paging(vcpu)) {
3479 hw_cr4 &= ~X86_CR4_PAE;
3480 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3481 /*
3482 * SMEP is disabled if CPU is in non-paging mode in
3483 * hardware. However KVM always uses paging mode to
3484 * emulate guest non-paging mode with TDP.
3485 * To emulate this behavior, SMEP needs to be manually
3486 * disabled when guest switches to non-paging mode.
3487 */
3488 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3489 } else if (!(cr4 & X86_CR4_PAE)) {
3490 hw_cr4 &= ~X86_CR4_PAE;
3491 }
3492 }
1439442c
SY		 3493
3494 vmcs_writel(CR4_READ_SHADOW, cr4);
3495 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3496 return 0;
6aa8b732
AK		 3497}
3498
6aa8b732
AK		 3499static void vmx_get_segment(struct kvm_vcpu *vcpu,
3500 struct kvm_segment *var, int seg)
3501{
a9179499 3502 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3503 u32 ar;
3504
c6ad1153 3505 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3506 *var = vmx->rmode.segs[seg];
a9179499 3507 if (seg == VCPU_SREG_TR
2fb92db1 3508 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3509 return;
1390a28b
AK		 3510 var->base = vmx_read_guest_seg_base(vmx, seg);
3511 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3512 return;
a9179499 3513 }
2fb92db1
AK		 3514 var->base = vmx_read_guest_seg_base(vmx, seg);
3515 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3516 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3517 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3518 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3519 var->type = ar & 15;
3520 var->s = (ar >> 4) & 1;
3521 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3522 /*
3523 * Some userspaces do not preserve unusable property. Since usable
3524 * segment has to be present according to VMX spec we can use present
3525 * property to amend userspace bug by making unusable segment always
3526 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3527 * segment as unusable.
3528 */
3529 var->present = !var->unusable;
6aa8b732
AK		 3530 var->avl = (ar >> 12) & 1;
3531 var->l = (ar >> 13) & 1;
3532 var->db = (ar >> 14) & 1;
3533 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3534}
3535
a9179499
AK		 3536static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3537{
a9179499
AK		 3538 struct kvm_segment s;
3539
3540 if (to_vmx(vcpu)->rmode.vm86_active) {
3541 vmx_get_segment(vcpu, &s, seg);
3542 return s.base;
3543 }
2fb92db1 3544 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3545}
3546
b09408d0 3547static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3548{
b09408d0
MT		 3549 struct vcpu_vmx *vmx = to_vmx(vcpu);
3550
3eeb3288 3551 if (!is_protmode(vcpu))
2e4d2653
IE		 3552 return 0;
3553
f4c63e5d
AK		 3554 if (!is_long_mode(vcpu)
3555 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3556 return 3;
3557
69c73028
AK		 3558 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3559 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3560 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3561 }
d881e6f6
AK		 3562
3563 return vmx->cpl;
69c73028
AK		 3564}
3565
3566
653e3108 3567static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3568{
6aa8b732
AK		 3569 u32 ar;
3570
f0495f9b 3571 if (var->unusable || !var->present)
6aa8b732
AK		 3572 ar = 1 << 16;
3573 else {
3574 ar = var->type & 15;
3575 ar |= (var->s & 1) << 4;
3576 ar |= (var->dpl & 3) << 5;
3577 ar |= (var->present & 1) << 7;
3578 ar |= (var->avl & 1) << 12;
3579 ar |= (var->l & 1) << 13;
3580 ar |= (var->db & 1) << 14;
3581 ar |= (var->g & 1) << 15;
3582 }
653e3108
AK		 3583
3584 return ar;
3585}
3586
3587static void vmx_set_segment(struct kvm_vcpu *vcpu,
3588 struct kvm_segment *var, int seg)
3589{
7ffd92c5 3590 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3591 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3592
2fb92db1 3593 vmx_segment_cache_clear(vmx);
2f143240
GN		 3594 if (seg == VCPU_SREG_CS)
3595 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3596
1ecd50a9
GN		 3597 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3598 vmx->rmode.segs[seg] = *var;
3599 if (seg == VCPU_SREG_TR)
3600 vmcs_write16(sf->selector, var->selector);
3601 else if (var->s)
3602 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3603 goto out;
653e3108 3604 }
1ecd50a9 3605
653e3108
AK		 3606 vmcs_writel(sf->base, var->base);
3607 vmcs_write32(sf->limit, var->limit);
3608 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3609
3610 /*
3611 * Fix the "Accessed" bit in AR field of segment registers for older
3612 * qemu binaries.
3613 * IA32 arch specifies that at the time of processor reset the
3614 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3615 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3616 * state vmexit when "unrestricted guest" mode is turned on.
3617 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3618 * tree. Newer qemu binaries with that qemu fix would not need this
3619 * kvm hack.
3620 */
3621 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3622 var->type |= 0x1; /* Accessed */
3a624e29 3623
f924d66d 3624 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3625
3626out:
14168786 3627 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3628}
3629
6aa8b732
AK		 3630static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3631{
2fb92db1 3632 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3633
3634 *db = (ar >> 14) & 1;
3635 *l = (ar >> 13) & 1;
3636}
3637
89a27f4d 3638static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3639{
89a27f4d
GN		 3640 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3641 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3642}
3643
89a27f4d 3644static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3645{
89a27f4d
GN		 3646 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3647 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3648}
3649
89a27f4d 3650static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3651{
89a27f4d
GN		 3652 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3653 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3654}
3655
89a27f4d 3656static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3657{
89a27f4d
GN		 3658 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3659 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3660}
3661
648dfaa7
MG		 3662static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3663{
3664 struct kvm_segment var;
3665 u32 ar;
3666
3667 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3668 var.dpl = 0x3;
0647f4aa
GN		 3669 if (seg == VCPU_SREG_CS)
3670 var.type = 0x3;
648dfaa7
MG		 3671 ar = vmx_segment_access_rights(&var);
3672
3673 if (var.base != (var.selector << 4))
3674 return false;
89efbed0 3675 if (var.limit != 0xffff)
648dfaa7 3676 return false;
07f42f5f 3677 if (ar != 0xf3)
648dfaa7
MG		 3678 return false;
3679
3680 return true;
3681}
3682
3683static bool code_segment_valid(struct kvm_vcpu *vcpu)
3684{
3685 struct kvm_segment cs;
3686 unsigned int cs_rpl;
3687
3688 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3689 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3690
1872a3f4
AK		 3691 if (cs.unusable)
3692 return false;
648dfaa7
MG		 3693 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3694 return false;
3695 if (!cs.s)
3696 return false;
1872a3f4 3697 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3698 if (cs.dpl > cs_rpl)
3699 return false;
1872a3f4 3700 } else {
648dfaa7
MG		 3701 if (cs.dpl != cs_rpl)
3702 return false;
3703 }
3704 if (!cs.present)
3705 return false;
3706
3707 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3708 return true;
3709}
3710
3711static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3712{
3713 struct kvm_segment ss;
3714 unsigned int ss_rpl;
3715
3716 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3717 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3718
1872a3f4
AK		 3719 if (ss.unusable)
3720 return true;
3721 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3722 return false;
3723 if (!ss.s)
3724 return false;
3725 if (ss.dpl != ss_rpl) /* DPL != RPL */
3726 return false;
3727 if (!ss.present)
3728 return false;
3729
3730 return true;
3731}
3732
3733static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3734{
3735 struct kvm_segment var;
3736 unsigned int rpl;
3737
3738 vmx_get_segment(vcpu, &var, seg);
3739 rpl = var.selector & SELECTOR_RPL_MASK;
3740
1872a3f4
AK		 3741 if (var.unusable)
3742 return true;
648dfaa7
MG		 3743 if (!var.s)
3744 return false;
3745 if (!var.present)
3746 return false;
3747 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3748 if (var.dpl < rpl) /* DPL < RPL */
3749 return false;
3750 }
3751
3752 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3753 * rights flags
3754 */
3755 return true;
3756}
3757
3758static bool tr_valid(struct kvm_vcpu *vcpu)
3759{
3760 struct kvm_segment tr;
3761
3762 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3763
1872a3f4
AK		 3764 if (tr.unusable)
3765 return false;
648dfaa7
MG		 3766 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3767 return false;
1872a3f4 3768 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3769 return false;
3770 if (!tr.present)
3771 return false;
3772
3773 return true;
3774}
3775
3776static bool ldtr_valid(struct kvm_vcpu *vcpu)
3777{
3778 struct kvm_segment ldtr;
3779
3780 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3781
1872a3f4
AK		 3782 if (ldtr.unusable)
3783 return true;
648dfaa7
MG		 3784 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3785 return false;
3786 if (ldtr.type != 2)
3787 return false;
3788 if (!ldtr.present)
3789 return false;
3790
3791 return true;
3792}
3793
3794static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3795{
3796 struct kvm_segment cs, ss;
3797
3798 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3799 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3800
3801 return ((cs.selector & SELECTOR_RPL_MASK) ==
3802 (ss.selector & SELECTOR_RPL_MASK));
3803}
3804
3805/*
3806 * Check if guest state is valid. Returns true if valid, false if
3807 * not.
3808 * We assume that registers are always usable
3809 */
3810static bool guest_state_valid(struct kvm_vcpu *vcpu)
3811{
c5e97c80
GN		 3812 if (enable_unrestricted_guest)
3813 return true;
3814
648dfaa7 3815 /* real mode guest state checks */
f13882d8 3816 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3817 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3818 return false;
3819 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3820 return false;
3821 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3822 return false;
3823 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3824 return false;
3825 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3826 return false;
3827 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3828 return false;
3829 } else {
3830 /* protected mode guest state checks */
3831 if (!cs_ss_rpl_check(vcpu))
3832 return false;
3833 if (!code_segment_valid(vcpu))
3834 return false;
3835 if (!stack_segment_valid(vcpu))
3836 return false;
3837 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3838 return false;
3839 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3840 return false;
3841 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3842 return false;
3843 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3844 return false;
3845 if (!tr_valid(vcpu))
3846 return false;
3847 if (!ldtr_valid(vcpu))
3848 return false;
3849 }
3850 /* TODO:
3851 * - Add checks on RIP
3852 * - Add checks on RFLAGS
3853 */
3854
3855 return true;
3856}
3857
d77c26fc 3858static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3859{
40dcaa9f 3860 gfn_t fn;
195aefde 3861 u16 data = 0;
40dcaa9f 3862 int r, idx, ret = 0;
6aa8b732 3863
40dcaa9f 3864 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3865 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3866 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3867 if (r < 0)
10589a46 3868 goto out;
195aefde 3869 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3870 r = kvm_write_guest_page(kvm, fn++, &data,
3871 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3872 if (r < 0)
10589a46 3873 goto out;
195aefde
IE		 3874 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3875 if (r < 0)
10589a46 3876 goto out;
195aefde
IE		 3877 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3878 if (r < 0)
10589a46 3879 goto out;
195aefde 3880 data = ~0;
10589a46
MT		 3881 r = kvm_write_guest_page(kvm, fn, &data,
3882 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3883 sizeof(u8));
195aefde 3884 if (r < 0)
10589a46
MT		 3885 goto out;
3886
3887 ret = 1;
3888out:
40dcaa9f 3889 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3890 return ret;
6aa8b732
AK		 3891}
3892
b7ebfb05
SY		 3893static int init_rmode_identity_map(struct kvm *kvm)
3894{
40dcaa9f 3895 int i, idx, r, ret;
b7ebfb05
SY		 3896 pfn_t identity_map_pfn;
3897 u32 tmp;
3898
089d034e 3899 if (!enable_ept)
b7ebfb05
SY		 3900 return 1;
3901 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3902 printk(KERN_ERR "EPT: identity-mapping pagetable "
3903 "haven't been allocated!\n");
3904 return 0;
3905 }
3906 if (likely(kvm->arch.ept_identity_pagetable_done))
3907 return 1;
3908 ret = 0;
b927a3ce 3909 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3910 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3911 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3912 if (r < 0)
3913 goto out;
3914 /* Set up identity-mapping pagetable for EPT in real mode */
3915 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3916 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3917 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3918 r = kvm_write_guest_page(kvm, identity_map_pfn,
3919 &tmp, i * sizeof(tmp), sizeof(tmp));
3920 if (r < 0)
3921 goto out;
3922 }
3923 kvm->arch.ept_identity_pagetable_done = true;
3924 ret = 1;
3925out:
40dcaa9f 3926 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3927 return ret;
3928}
3929
6aa8b732
AK		 3930static void seg_setup(int seg)
3931{
772e0318 3932 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3933 unsigned int ar;
6aa8b732
AK		 3934
3935 vmcs_write16(sf->selector, 0);
3936 vmcs_writel(sf->base, 0);
3937 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3938 ar = 0x93;
3939 if (seg == VCPU_SREG_CS)
3940 ar |= 0x08; /* code segment */
3a624e29
NK		 3941
3942 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3943}
3944
f78e0e2e
SY		 3945static int alloc_apic_access_page(struct kvm *kvm)
3946{
4484141a 3947 struct page *page;
f78e0e2e
SY		 3948 struct kvm_userspace_memory_region kvm_userspace_mem;
3949 int r = 0;
3950
79fac95e 3951 mutex_lock(&kvm->slots_lock);
bfc6d222 3952 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3953 goto out;
3954 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3955 kvm_userspace_mem.flags = 0;
3956 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3957 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3958 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3959 if (r)
3960 goto out;
72dc67a6 3961
4484141a
XG		 3962 page = gfn_to_page(kvm, 0xfee00);
3963 if (is_error_page(page)) {
3964 r = -EFAULT;
3965 goto out;
3966 }
3967
3968 kvm->arch.apic_access_page = page;
f78e0e2e 3969out:
79fac95e 3970 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3971 return r;
3972}
3973
b7ebfb05
SY		 3974static int alloc_identity_pagetable(struct kvm *kvm)
3975{
4484141a 3976 struct page *page;
b7ebfb05
SY		 3977 struct kvm_userspace_memory_region kvm_userspace_mem;
3978 int r = 0;
3979
79fac95e 3980 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3981 if (kvm->arch.ept_identity_pagetable)
3982 goto out;
3983 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3984 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3985 kvm_userspace_mem.guest_phys_addr =
3986 kvm->arch.ept_identity_map_addr;
b7ebfb05 3987 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3988 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3989 if (r)
3990 goto out;
3991
4484141a
XG		 3992 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3993 if (is_error_page(page)) {
3994 r = -EFAULT;
3995 goto out;
3996 }
3997
3998 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3999out:
79fac95e 4000 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4001 return r;
4002}
4003
2384d2b3
SY		 4004static void allocate_vpid(struct vcpu_vmx *vmx)
4005{
4006 int vpid;
4007
4008 vmx->vpid = 0;
919818ab 4009 if (!enable_vpid)
2384d2b3
SY		 4010 return;
4011 spin_lock(&vmx_vpid_lock);
4012 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4013 if (vpid < VMX_NR_VPIDS) {
4014 vmx->vpid = vpid;
4015 __set_bit(vpid, vmx_vpid_bitmap);
4016 }
4017 spin_unlock(&vmx_vpid_lock);
4018}
4019
cdbecfc3
LJ		 4020static void free_vpid(struct vcpu_vmx *vmx)
4021{
4022 if (!enable_vpid)
4023 return;
4024 spin_lock(&vmx_vpid_lock);
4025 if (vmx->vpid != 0)
4026 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4027 spin_unlock(&vmx_vpid_lock);
4028}
4029
8d14695f
YZ		 4030#define MSR_TYPE_R 1
4031#define MSR_TYPE_W 2
4032static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4033 u32 msr, int type)
25c5f225 4034{
3e7c73e9 4035 int f = sizeof(unsigned long);
25c5f225
SY		 4036
4037 if (!cpu_has_vmx_msr_bitmap())
4038 return;
4039
4040 /*
4041 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4042 * have the write-low and read-high bitmap offsets the wrong way round.
4043 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4044 */
25c5f225 4045 if (msr <= 0x1fff) {
8d14695f
YZ		 4046 if (type & MSR_TYPE_R)
4047 /* read-low */
4048 __clear_bit(msr, msr_bitmap + 0x000 / f);
4049
4050 if (type & MSR_TYPE_W)
4051 /* write-low */
4052 __clear_bit(msr, msr_bitmap + 0x800 / f);
4053
25c5f225
SY		 4054 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4055 msr &= 0x1fff;
8d14695f
YZ		 4056 if (type & MSR_TYPE_R)
4057 /* read-high */
4058 __clear_bit(msr, msr_bitmap + 0x400 / f);
4059
4060 if (type & MSR_TYPE_W)
4061 /* write-high */
4062 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4063
4064 }
4065}
4066
4067static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4068 u32 msr, int type)
4069{
4070 int f = sizeof(unsigned long);
4071
4072 if (!cpu_has_vmx_msr_bitmap())
4073 return;
4074
4075 /*
4076 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4077 * have the write-low and read-high bitmap offsets the wrong way round.
4078 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4079 */
4080 if (msr <= 0x1fff) {
4081 if (type & MSR_TYPE_R)
4082 /* read-low */
4083 __set_bit(msr, msr_bitmap + 0x000 / f);
4084
4085 if (type & MSR_TYPE_W)
4086 /* write-low */
4087 __set_bit(msr, msr_bitmap + 0x800 / f);
4088
4089 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4090 msr &= 0x1fff;
4091 if (type & MSR_TYPE_R)
4092 /* read-high */
4093 __set_bit(msr, msr_bitmap + 0x400 / f);
4094
4095 if (type & MSR_TYPE_W)
4096 /* write-high */
4097 __set_bit(msr, msr_bitmap + 0xc00 / f);
4098
25c5f225 4099 }
25c5f225
SY		 4100}
4101
5897297b
AK		 4102static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4103{
4104 if (!longmode_only)
8d14695f
YZ		 4105 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4106 msr, MSR_TYPE_R | MSR_TYPE_W);
4107 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4108 msr, MSR_TYPE_R | MSR_TYPE_W);
4109}
4110
4111static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4112{
4113 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4114 msr, MSR_TYPE_R);
4115 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4116 msr, MSR_TYPE_R);
4117}
4118
4119static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4120{
4121 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4122 msr, MSR_TYPE_R);
4123 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4124 msr, MSR_TYPE_R);
4125}
4126
4127static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4128{
4129 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4130 msr, MSR_TYPE_W);
4131 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4132 msr, MSR_TYPE_W);
5897297b
AK		 4133}
4134
01e439be
YZ		 4135static int vmx_vm_has_apicv(struct kvm *kvm)
4136{
4137 return enable_apicv && irqchip_in_kernel(kvm);
4138}
4139
a20ed54d
YZ		 4140/*
4141 * Send interrupt to vcpu via posted interrupt way.
4142 * 1. If target vcpu is running(non-root mode), send posted interrupt
4143 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4144 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4145 * interrupt from PIR in next vmentry.
4146 */
4147static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4148{
4149 struct vcpu_vmx *vmx = to_vmx(vcpu);
4150 int r;
4151
4152 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4153 return;
4154
4155 r = pi_test_and_set_on(&vmx->pi_desc);
4156 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4157#ifdef CONFIG_SMP
a20ed54d
YZ		 4158 if (!r && (vcpu->mode == IN_GUEST_MODE))
4159 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4160 POSTED_INTR_VECTOR);
4161 else
6ffbbbba 4162#endif
a20ed54d
YZ		 4163 kvm_vcpu_kick(vcpu);
4164}
4165
4166static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4167{
4168 struct vcpu_vmx *vmx = to_vmx(vcpu);
4169
4170 if (!pi_test_and_clear_on(&vmx->pi_desc))
4171 return;
4172
4173 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4174}
4175
4176static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4177{
4178 return;
4179}
4180
a3a8ff8e
NHE		 4181/*
4182 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4183 * will not change in the lifetime of the guest.
4184 * Note that host-state that does change is set elsewhere. E.g., host-state
4185 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4186 */
a547c6db 4187static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4188{
4189 u32 low32, high32;
4190 unsigned long tmpl;
4191 struct desc_ptr dt;
4192
b1a74bf8 4193 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4194 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4195 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4196
4197 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4198#ifdef CONFIG_X86_64
4199 /*
4200 * Load null selectors, so we can avoid reloading them in
4201 * __vmx_load_host_state(), in case userspace uses the null selectors
4202 * too (the expected case).
4203 */
4204 vmcs_write16(HOST_DS_SELECTOR, 0);
4205 vmcs_write16(HOST_ES_SELECTOR, 0);
4206#else
a3a8ff8e
NHE		 4207 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4208 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4209#endif
a3a8ff8e
NHE		 4210 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4211 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4212
4213 native_store_idt(&dt);
4214 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4215 vmx->host_idt_base = dt.address;
a3a8ff8e 4216
83287ea4 4217 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4218
4219 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4220 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4221 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4222 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4223
4224 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4225 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4226 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4227 }
4228}
4229
bf8179a0
NHE		 4230static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4231{
4232 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4233 if (enable_ept)
4234 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4235 if (is_guest_mode(&vmx->vcpu))
4236 vmx->vcpu.arch.cr4_guest_owned_bits &=
4237 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4238 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4239}
4240
01e439be
YZ		 4241static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4242{
4243 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4244
4245 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4246 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4247 return pin_based_exec_ctrl;
4248}
4249
bf8179a0
NHE		 4250static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4251{
4252 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4253
4254 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4255 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4256
bf8179a0
NHE		 4257 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4258 exec_control &= ~CPU_BASED_TPR_SHADOW;
4259#ifdef CONFIG_X86_64
4260 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4261 CPU_BASED_CR8_LOAD_EXITING;
4262#endif
4263 }
4264 if (!enable_ept)
4265 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4266 CPU_BASED_CR3_LOAD_EXITING |
4267 CPU_BASED_INVLPG_EXITING;
4268 return exec_control;
4269}
4270
4271static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4272{
4273 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4274 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4275 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4276 if (vmx->vpid == 0)
4277 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4278 if (!enable_ept) {
4279 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4280 enable_unrestricted_guest = 0;
ad756a16
MJ		 4281 /* Enable INVPCID for non-ept guests may cause performance regression. */
4282 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4283 }
4284 if (!enable_unrestricted_guest)
4285 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4286 if (!ple_gap)
4287 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4288 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4289 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4290 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4291 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4292 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4293 (handle_vmptrld).
4294 We can NOT enable shadow_vmcs here because we don't have yet
4295 a current VMCS12
4296 */
4297 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4298 return exec_control;
4299}
4300
ce88decf
XG		 4301static void ept_set_mmio_spte_mask(void)
4302{
4303 /*
4304 * EPT Misconfigurations can be generated if the value of bits 2:0
4305 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4306 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4307 * spte.
4308 */
885032b9 4309 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4310}
4311
6aa8b732
AK		 4312/*
4313 * Sets up the vmcs for emulated real mode.
4314 */
8b9cf98c 4315static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4316{
2e4ce7f5 4317#ifdef CONFIG_X86_64
6aa8b732 4318 unsigned long a;
2e4ce7f5 4319#endif
6aa8b732 4320 int i;
6aa8b732 4321
6aa8b732 4322 /* I/O */
3e7c73e9
AK		 4323 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4324 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4325
4607c2d7
AG		 4326 if (enable_shadow_vmcs) {
4327 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4328 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4329 }
25c5f225 4330 if (cpu_has_vmx_msr_bitmap())
5897297b 4331 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4332
6aa8b732
AK		 4333 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4334
6aa8b732 4335 /* Control */
01e439be 4336 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4337
bf8179a0 4338 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4339
83ff3b9d 4340 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4341 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4342 vmx_secondary_exec_control(vmx));
83ff3b9d 4343 }
f78e0e2e 4344
01e439be 4345 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4346 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4347 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4348 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4349 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4350
4351 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4352
4353 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4354 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4355 }
4356
4b8d54f9
ZE		 4357 if (ple_gap) {
4358 vmcs_write32(PLE_GAP, ple_gap);
4359 vmcs_write32(PLE_WINDOW, ple_window);
4360 }
4361
c3707958
XG		 4362 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4363 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4364 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4365
9581d442
AK		 4366 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4367 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4368 vmx_set_constant_host_state(vmx);
05b3e0c2 4369#ifdef CONFIG_X86_64
6aa8b732
AK		 4370 rdmsrl(MSR_FS_BASE, a);
4371 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4372 rdmsrl(MSR_GS_BASE, a);
4373 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4374#else
4375 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4376 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4377#endif
4378
2cc51560
ED		 4379 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4380 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4381 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4382 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4383 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4384
468d472f 4385 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4386 u32 msr_low, msr_high;
4387 u64 host_pat;
468d472f
SY		 4388 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4389 host_pat = msr_low | ((u64) msr_high << 32);
4390 /* Write the default value follow host pat */
4391 vmcs_write64(GUEST_IA32_PAT, host_pat);
4392 /* Keep arch.pat sync with GUEST_IA32_PAT */
4393 vmx->vcpu.arch.pat = host_pat;
4394 }
4395
6aa8b732
AK		 4396 for (i = 0; i < NR_VMX_MSR; ++i) {
4397 u32 index = vmx_msr_index[i];
4398 u32 data_low, data_high;
a2fa3e9f 4399 int j = vmx->nmsrs;
6aa8b732
AK		 4400
4401 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4402 continue;
432bd6cb
AK		 4403 if (wrmsr_safe(index, data_low, data_high) < 0)
4404 continue;
26bb0981
AK		 4405 vmx->guest_msrs[j].index = i;
4406 vmx->guest_msrs[j].data = 0;
d5696725 4407 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4408 ++vmx->nmsrs;
6aa8b732 4409 }
6aa8b732 4410
2961e876
GN		 4411
4412 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4413
4414 /* 22.2.1, 20.8.1 */
2961e876 4415 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4416
e00c8cf2 4417 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4418 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4419
4420 return 0;
4421}
4422
57f252f2 4423static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4424{
4425 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4426 struct msr_data apic_base_msr;
e00c8cf2 4427
7ffd92c5 4428 vmx->rmode.vm86_active = 0;
e00c8cf2 4429
3b86cd99
JK		 4430 vmx->soft_vnmi_blocked = 0;
4431
ad312c7c 4432 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4433 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4434 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4435 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4436 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4437 apic_base_msr.host_initiated = true;
4438 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4439
2fb92db1
AK		 4440 vmx_segment_cache_clear(vmx);
4441
5706be0d 4442 seg_setup(VCPU_SREG_CS);
66450a21 4443 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4444 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4445
4446 seg_setup(VCPU_SREG_DS);
4447 seg_setup(VCPU_SREG_ES);
4448 seg_setup(VCPU_SREG_FS);
4449 seg_setup(VCPU_SREG_GS);
4450 seg_setup(VCPU_SREG_SS);
4451
4452 vmcs_write16(GUEST_TR_SELECTOR, 0);
4453 vmcs_writel(GUEST_TR_BASE, 0);
4454 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4455 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4456
4457 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4458 vmcs_writel(GUEST_LDTR_BASE, 0);
4459 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4460 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4461
4462 vmcs_write32(GUEST_SYSENTER_CS, 0);
4463 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4464 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4465
4466 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4467 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4468
e00c8cf2
AK		 4469 vmcs_writel(GUEST_GDTR_BASE, 0);
4470 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4471
4472 vmcs_writel(GUEST_IDTR_BASE, 0);
4473 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4474
443381a8 4475 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4476 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4477 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4478
e00c8cf2
AK		 4479 /* Special registers */
4480 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4481
4482 setup_msrs(vmx);
4483
6aa8b732
AK		 4484 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4485
f78e0e2e
SY		 4486 if (cpu_has_vmx_tpr_shadow()) {
4487 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4488 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4489 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4490 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4491 vmcs_write32(TPR_THRESHOLD, 0);
4492 }
4493
4494 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4495 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4496 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4497
01e439be
YZ		 4498 if (vmx_vm_has_apicv(vcpu->kvm))
4499 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4500
2384d2b3
SY		 4501 if (vmx->vpid != 0)
4502 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4503
fa40052c 4504 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4505 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4506 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4507 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4508 vmx_fpu_activate(&vmx->vcpu);
4509 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4510
b9d762fa 4511 vpid_sync_context(vmx);
6aa8b732
AK		 4512}
4513
b6f1250e
NHE		 4514/*
4515 * In nested virtualization, check if L1 asked to exit on external interrupts.
4516 * For most existing hypervisors, this will always return true.
4517 */
4518static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4519{
4520 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4521 PIN_BASED_EXT_INTR_MASK;
4522}
4523
ea8ceb83
JK		 4524static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4525{
4526 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4527 PIN_BASED_NMI_EXITING;
4528}
4529
c9a7953f 4530static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4531{
4532 u32 cpu_based_vm_exec_control;
730dca42 4533
3b86cd99
JK		 4534 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4535 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4537}
4538
c9a7953f 4539static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4540{
4541 u32 cpu_based_vm_exec_control;
4542
c9a7953f
JK		 4543 if (!cpu_has_virtual_nmis() ||
4544 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4545 enable_irq_window(vcpu);
4546 return;
4547 }
3b86cd99
JK		 4548
4549 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4550 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4551 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4552}
4553
66fd3f7f 4554static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4555{
9c8cba37 4556 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4557 uint32_t intr;
4558 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4559
229456fc 4560 trace_kvm_inj_virq(irq);
2714d1d3 4561
fa89a817 4562 ++vcpu->stat.irq_injections;
7ffd92c5 4563 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4564 int inc_eip = 0;
4565 if (vcpu->arch.interrupt.soft)
4566 inc_eip = vcpu->arch.event_exit_inst_len;
4567 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4568 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4569 return;
4570 }
66fd3f7f
GN		 4571 intr = irq | INTR_INFO_VALID_MASK;
4572 if (vcpu->arch.interrupt.soft) {
4573 intr |= INTR_TYPE_SOFT_INTR;
4574 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4575 vmx->vcpu.arch.event_exit_inst_len);
4576 } else
4577 intr |= INTR_TYPE_EXT_INTR;
4578 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4579}
4580
f08864b4
SY		 4581static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4582{
66a5a347
JK		 4583 struct vcpu_vmx *vmx = to_vmx(vcpu);
4584
0b6ac343
NHE		 4585 if (is_guest_mode(vcpu))
4586 return;
4587
3b86cd99
JK		 4588 if (!cpu_has_virtual_nmis()) {
4589 /*
4590 * Tracking the NMI-blocked state in software is built upon
4591 * finding the next open IRQ window. This, in turn, depends on
4592 * well-behaving guests: They have to keep IRQs disabled at
4593 * least as long as the NMI handler runs. Otherwise we may
4594 * cause NMI nesting, maybe breaking the guest. But as this is
4595 * highly unlikely, we can live with the residual risk.
4596 */
4597 vmx->soft_vnmi_blocked = 1;
4598 vmx->vnmi_blocked_time = 0;
4599 }
4600
487b391d 4601 ++vcpu->stat.nmi_injections;
9d58b931 4602 vmx->nmi_known_unmasked = false;
7ffd92c5 4603 if (vmx->rmode.vm86_active) {
71f9833b 4604 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4605 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4606 return;
4607 }
f08864b4
SY		 4608 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4609 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4610}
4611
3cfc3092
JK		 4612static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4613{
4614 if (!cpu_has_virtual_nmis())
4615 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4616 if (to_vmx(vcpu)->nmi_known_unmasked)
4617 return false;
c332c83a 4618 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4619}
4620
4621static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4622{
4623 struct vcpu_vmx *vmx = to_vmx(vcpu);
4624
4625 if (!cpu_has_virtual_nmis()) {
4626 if (vmx->soft_vnmi_blocked != masked) {
4627 vmx->soft_vnmi_blocked = masked;
4628 vmx->vnmi_blocked_time = 0;
4629 }
4630 } else {
9d58b931 4631 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4632 if (masked)
4633 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4634 GUEST_INTR_STATE_NMI);
4635 else
4636 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4637 GUEST_INTR_STATE_NMI);
4638 }
4639}
4640
2505dc9f
JK		 4641static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4642{
b6b8a145
JK		 4643 if (to_vmx(vcpu)->nested.nested_run_pending)
4644 return 0;
ea8ceb83 4645
2505dc9f
JK		 4646 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4647 return 0;
4648
4649 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4650 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4651 | GUEST_INTR_STATE_NMI));
4652}
4653
78646121
GN		 4654static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4655{
b6b8a145
JK		 4656 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4657 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4658 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4659 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4660}
4661
cbc94022
IE		 4662static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4663{
4664 int ret;
4665 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4666 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4667 .guest_phys_addr = addr,
4668 .memory_size = PAGE_SIZE * 3,
4669 .flags = 0,
4670 };
4671
47ae31e2 4672 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4673 if (ret)
4674 return ret;
bfc6d222 4675 kvm->arch.tss_addr = addr;
93ea5388
GN		 4676 if (!init_rmode_tss(kvm))
4677 return -ENOMEM;
4678
cbc94022
IE		 4679 return 0;
4680}
4681
0ca1b4f4 4682static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4683{
77ab6db0 4684 switch (vec) {
77ab6db0 4685 case BP_VECTOR:
c573cd22
JK		 4686 /*
4687 * Update instruction length as we may reinject the exception
4688 * from user space while in guest debugging mode.
4689 */
4690 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4691 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4692 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4693 return false;
4694 /* fall through */
4695 case DB_VECTOR:
4696 if (vcpu->guest_debug &
4697 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4698 return false;
d0bfb940
JK		 4699 /* fall through */
4700 case DE_VECTOR:
77ab6db0
JK		 4701 case OF_VECTOR:
4702 case BR_VECTOR:
4703 case UD_VECTOR:
4704 case DF_VECTOR:
4705 case SS_VECTOR:
4706 case GP_VECTOR:
4707 case MF_VECTOR:
0ca1b4f4
GN		 4708 return true;
4709 break;
77ab6db0 4710 }
0ca1b4f4
GN		 4711 return false;
4712}
4713
4714static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4715 int vec, u32 err_code)
4716{
4717 /*
4718 * Instruction with address size override prefix opcode 0x67
4719 * Cause the #SS fault with 0 error code in VM86 mode.
4720 */
4721 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4722 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4723 if (vcpu->arch.halt_request) {
4724 vcpu->arch.halt_request = 0;
4725 return kvm_emulate_halt(vcpu);
4726 }
4727 return 1;
4728 }
4729 return 0;
4730 }
4731
4732 /*
4733 * Forward all other exceptions that are valid in real mode.
4734 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4735 * the required debugging infrastructure rework.
4736 */
4737 kvm_queue_exception(vcpu, vec);
4738 return 1;
6aa8b732
AK		 4739}
4740
a0861c02
AK		 4741/*
4742 * Trigger machine check on the host. We assume all the MSRs are already set up
4743 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4744 * We pass a fake environment to the machine check handler because we want
4745 * the guest to be always treated like user space, no matter what context
4746 * it used internally.
4747 */
4748static void kvm_machine_check(void)
4749{
4750#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4751 struct pt_regs regs = {
4752 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4753 .flags = X86_EFLAGS_IF,
4754 };
4755
4756 do_machine_check(&regs, 0);
4757#endif
4758}
4759
851ba692 4760static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4761{
4762 /* already handled by vcpu_run */
4763 return 1;
4764}
4765
851ba692 4766static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4767{
1155f76a 4768 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4769 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4770 u32 intr_info, ex_no, error_code;
42dbaa5a 4771 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4772 u32 vect_info;
4773 enum emulation_result er;
4774
1155f76a 4775 vect_info = vmx->idt_vectoring_info;
88786475 4776 intr_info = vmx->exit_intr_info;
6aa8b732 4777
a0861c02 4778 if (is_machine_check(intr_info))
851ba692 4779 return handle_machine_check(vcpu);
a0861c02 4780
e4a41889 4781 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4782 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4783
4784 if (is_no_device(intr_info)) {
5fd86fcf 4785 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4786 return 1;
4787 }
4788
7aa81cc0 4789 if (is_invalid_opcode(intr_info)) {
51d8b661 4790 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4791 if (er != EMULATE_DONE)
7ee5d940 4792 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4793 return 1;
4794 }
4795
6aa8b732 4796 error_code = 0;
2e11384c 4797 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4798 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4799
4800 /*
4801 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4802 * MMIO, it is better to report an internal error.
4803 * See the comments in vmx_handle_exit.
4804 */
4805 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4806 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4807 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4808 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4809 vcpu->run->internal.ndata = 2;
4810 vcpu->run->internal.data[0] = vect_info;
4811 vcpu->run->internal.data[1] = intr_info;
4812 return 0;
4813 }
4814
6aa8b732 4815 if (is_page_fault(intr_info)) {
1439442c 4816 /* EPT won't cause page fault directly */
cf3ace79 4817 BUG_ON(enable_ept);
6aa8b732 4818 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4819 trace_kvm_page_fault(cr2, error_code);
4820
3298b75c 4821 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4822 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4823 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4824 }
4825
d0bfb940 4826 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4827
4828 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4829 return handle_rmode_exception(vcpu, ex_no, error_code);
4830
42dbaa5a
JK		 4831 switch (ex_no) {
4832 case DB_VECTOR:
4833 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4834 if (!(vcpu->guest_debug &
4835 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4836 vcpu->arch.dr6 &= ~15;
4837 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4838 kvm_queue_exception(vcpu, DB_VECTOR);
4839 return 1;
4840 }
4841 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4842 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4843 /* fall through */
4844 case BP_VECTOR:
c573cd22
JK		 4845 /*
4846 * Update instruction length as we may reinject #BP from
4847 * user space while in guest debugging mode. Reading it for
4848 * #DB as well causes no harm, it is not used in that case.
4849 */
4850 vmx->vcpu.arch.event_exit_inst_len =
4851 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4852 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4853 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4854 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4855 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4856 break;
4857 default:
d0bfb940
JK		 4858 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4859 kvm_run->ex.exception = ex_no;
4860 kvm_run->ex.error_code = error_code;
42dbaa5a 4861 break;
6aa8b732 4862 }
6aa8b732
AK		 4863 return 0;
4864}
4865
851ba692 4866static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4867{
1165f5fe 4868 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4869 return 1;
4870}
4871
851ba692 4872static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4873{
851ba692 4874 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4875 return 0;
4876}
6aa8b732 4877
851ba692 4878static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4879{
bfdaab09 4880 unsigned long exit_qualification;
34c33d16 4881 int size, in, string;
039576c0 4882 unsigned port;
6aa8b732 4883
bfdaab09 4884 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4885 string = (exit_qualification & 16) != 0;
cf8f70bf 4886 in = (exit_qualification & 8) != 0;
e70669ab 4887
cf8f70bf 4888 ++vcpu->stat.io_exits;
e70669ab 4889
cf8f70bf 4890 if (string || in)
51d8b661 4891 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4892
cf8f70bf
GN		 4893 port = exit_qualification >> 16;
4894 size = (exit_qualification & 7) + 1;
e93f36bc 4895 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4896
4897 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4898}
4899
102d8325
IM		 4900static void
4901vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4902{
4903 /*
4904 * Patch in the VMCALL instruction:
4905 */
4906 hypercall[0] = 0x0f;
4907 hypercall[1] = 0x01;
4908 hypercall[2] = 0xc1;
102d8325
IM		 4909}
4910
92fbc7b1
JK		 4911static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4912{
4913 unsigned long always_on = VMXON_CR0_ALWAYSON;
4914
4915 if (nested_vmx_secondary_ctls_high &
4916 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4917 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4918 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4919 return (val & always_on) == always_on;
4920}
4921
0fa06071 4922/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4923static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4924{
eeadf9e7 4925 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4926 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4927 unsigned long orig_val = val;
4928
eeadf9e7
NHE		 4929 /*
4930 * We get here when L2 changed cr0 in a way that did not change
4931 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4932 * but did change L0 shadowed bits. So we first calculate the
4933 * effective cr0 value that L1 would like to write into the
4934 * hardware. It consists of the L2-owned bits from the new
4935 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4936 */
1a0d74e6
JK		 4937 val = (val & ~vmcs12->cr0_guest_host_mask) |
4938 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4939
92fbc7b1 4940 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4941 return 1;
1a0d74e6
JK		 4942
4943 if (kvm_set_cr0(vcpu, val))
4944 return 1;
4945 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4946 return 0;
1a0d74e6
JK		 4947 } else {
4948 if (to_vmx(vcpu)->nested.vmxon &&
4949 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4950 return 1;
eeadf9e7 4951 return kvm_set_cr0(vcpu, val);
1a0d74e6 4952 }
eeadf9e7
NHE		 4953}
4954
4955static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4956{
4957 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4958 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4959 unsigned long orig_val = val;
4960
4961 /* analogously to handle_set_cr0 */
4962 val = (val & ~vmcs12->cr4_guest_host_mask) |
4963 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4964 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4965 return 1;
1a0d74e6 4966 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4967 return 0;
4968 } else
4969 return kvm_set_cr4(vcpu, val);
4970}
4971
4972/* called to set cr0 as approriate for clts instruction exit. */
4973static void handle_clts(struct kvm_vcpu *vcpu)
4974{
4975 if (is_guest_mode(vcpu)) {
4976 /*
4977 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4978 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4979 * just pretend it's off (also in arch.cr0 for fpu_activate).
4980 */
4981 vmcs_writel(CR0_READ_SHADOW,
4982 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4983 vcpu->arch.cr0 &= ~X86_CR0_TS;
4984 } else
4985 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4986}
4987
851ba692 4988static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4989{
229456fc 4990 unsigned long exit_qualification, val;
6aa8b732
AK		 4991 int cr;
4992 int reg;
49a9b07e 4993 int err;
6aa8b732 4994
bfdaab09 4995 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4996 cr = exit_qualification & 15;
4997 reg = (exit_qualification >> 8) & 15;
4998 switch ((exit_qualification >> 4) & 3) {
4999 case 0: /* mov to cr */
229456fc
MT		 5000 val = kvm_register_read(vcpu, reg);
5001 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5002 switch (cr) {
5003 case 0:
eeadf9e7 5004 err = handle_set_cr0(vcpu, val);
db8fcefa 5005 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5006 return 1;
5007 case 3:
2390218b 5008 err = kvm_set_cr3(vcpu, val);
db8fcefa 5009 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5010 return 1;
5011 case 4:
eeadf9e7 5012 err = handle_set_cr4(vcpu, val);
db8fcefa 5013 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5014 return 1;
0a5fff19
GN		 5015 case 8: {
5016 u8 cr8_prev = kvm_get_cr8(vcpu);
5017 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5018 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5019 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5020 if (irqchip_in_kernel(vcpu->kvm))
5021 return 1;
5022 if (cr8_prev <= cr8)
5023 return 1;
851ba692 5024 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5025 return 0;
5026 }
4b8073e4 5027 }
6aa8b732 5028 break;
25c4c276 5029 case 2: /* clts */
eeadf9e7 5030 handle_clts(vcpu);
4d4ec087 5031 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5032 skip_emulated_instruction(vcpu);
6b52d186 5033 vmx_fpu_activate(vcpu);
25c4c276 5034 return 1;
6aa8b732
AK		 5035 case 1: /*mov from cr*/
5036 switch (cr) {
5037 case 3:
9f8fe504
AK		 5038 val = kvm_read_cr3(vcpu);
5039 kvm_register_write(vcpu, reg, val);
5040 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5041 skip_emulated_instruction(vcpu);
5042 return 1;
5043 case 8:
229456fc
MT		 5044 val = kvm_get_cr8(vcpu);
5045 kvm_register_write(vcpu, reg, val);
5046 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5047 skip_emulated_instruction(vcpu);
5048 return 1;
5049 }
5050 break;
5051 case 3: /* lmsw */
a1f83a74 5052 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5053 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5054 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5055
5056 skip_emulated_instruction(vcpu);
5057 return 1;
5058 default:
5059 break;
5060 }
851ba692 5061 vcpu->run->exit_reason = 0;
a737f256 5062 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5063 (int)(exit_qualification >> 4) & 3, cr);
5064 return 0;
5065}
5066
851ba692 5067static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5068{
bfdaab09 5069 unsigned long exit_qualification;
6aa8b732
AK		 5070 int dr, reg;
5071
f2483415 5072 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5073 if (!kvm_require_cpl(vcpu, 0))
5074 return 1;
42dbaa5a
JK		 5075 dr = vmcs_readl(GUEST_DR7);
5076 if (dr & DR7_GD) {
5077 /*
5078 * As the vm-exit takes precedence over the debug trap, we
5079 * need to emulate the latter, either for the host or the
5080 * guest debugging itself.
5081 */
5082 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5083 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5084 vcpu->run->debug.arch.dr7 = dr;
5085 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5086 vmcs_readl(GUEST_CS_BASE) +
5087 vmcs_readl(GUEST_RIP);
851ba692
AK		 5088 vcpu->run->debug.arch.exception = DB_VECTOR;
5089 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5090 return 0;
5091 } else {
5092 vcpu->arch.dr7 &= ~DR7_GD;
5093 vcpu->arch.dr6 |= DR6_BD;
5094 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5095 kvm_queue_exception(vcpu, DB_VECTOR);
5096 return 1;
5097 }
5098 }
5099
81908bf4
PB		 5100 if (vcpu->guest_debug == 0) {
5101 u32 cpu_based_vm_exec_control;
5102
5103 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5104 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5105 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5106
5107 /*
5108 * No more DR vmexits; force a reload of the debug registers
5109 * and reenter on this instruction. The next vmexit will
5110 * retrieve the full state of the debug registers.
5111 */
5112 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5113 return 1;
5114 }
5115
bfdaab09 5116 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5117 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5118 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5119 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5120 unsigned long val;
4c4d563b
JK		 5121
5122 if (kvm_get_dr(vcpu, dr, &val))
5123 return 1;
5124 kvm_register_write(vcpu, reg, val);
020df079 5125 } else
4c4d563b
JK		 5126 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5127 return 1;
5128
6aa8b732
AK		 5129 skip_emulated_instruction(vcpu);
5130 return 1;
5131}
5132
73aaf249
JK		 5133static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5134{
5135 return vcpu->arch.dr6;
5136}
5137
5138static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5139{
5140}
5141
81908bf4
PB		 5142static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5143{
5144 u32 cpu_based_vm_exec_control;
5145
5146 get_debugreg(vcpu->arch.db[0], 0);
5147 get_debugreg(vcpu->arch.db[1], 1);
5148 get_debugreg(vcpu->arch.db[2], 2);
5149 get_debugreg(vcpu->arch.db[3], 3);
5150 get_debugreg(vcpu->arch.dr6, 6);
5151 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5152
5153 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5154
5155 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5156 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5157 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5158}
5159
020df079
GN		 5160static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5161{
5162 vmcs_writel(GUEST_DR7, val);
5163}
5164
851ba692 5165static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5166{
06465c5a
AK		 5167 kvm_emulate_cpuid(vcpu);
5168 return 1;
6aa8b732
AK		 5169}
5170
851ba692 5171static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5172{
ad312c7c 5173 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5174 u64 data;
5175
5176 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5177 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5178 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5179 return 1;
5180 }
5181
229456fc 5182 trace_kvm_msr_read(ecx, data);
2714d1d3 5183
6aa8b732 5184 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5185 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5186 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5187 skip_emulated_instruction(vcpu);
5188 return 1;
5189}
5190
851ba692 5191static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5192{
8fe8ab46 5193 struct msr_data msr;
ad312c7c
ZX		 5194 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5195 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5196 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5197
8fe8ab46
WA		 5198 msr.data = data;
5199 msr.index = ecx;
5200 msr.host_initiated = false;
5201 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5202 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5203 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5204 return 1;
5205 }
5206
59200273 5207 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5208 skip_emulated_instruction(vcpu);
5209 return 1;
5210}
5211
851ba692 5212static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5213{
3842d135 5214 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5215 return 1;
5216}
5217
851ba692 5218static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5219{
85f455f7
ED		 5220 u32 cpu_based_vm_exec_control;
5221
5222 /* clear pending irq */
5223 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5224 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5225 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5226
3842d135
AK		 5227 kvm_make_request(KVM_REQ_EVENT, vcpu);
5228
a26bf12a 5229 ++vcpu->stat.irq_window_exits;
2714d1d3 5230
c1150d8c
DL		 5231 /*
5232 * If the user space waits to inject interrupts, exit as soon as
5233 * possible
5234 */
8061823a 5235 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5236 vcpu->run->request_interrupt_window &&
8061823a 5237 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5238 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5239 return 0;
5240 }
6aa8b732
AK		 5241 return 1;
5242}
5243
851ba692 5244static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5245{
5246 skip_emulated_instruction(vcpu);
d3bef15f 5247 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5248}
5249
851ba692 5250static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5251{
510043da 5252 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5253 kvm_emulate_hypercall(vcpu);
5254 return 1;
c21415e8
IM		 5255}
5256
ec25d5e6
GN		 5257static int handle_invd(struct kvm_vcpu *vcpu)
5258{
51d8b661 5259 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5260}
5261
851ba692 5262static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5263{
f9c617f6 5264 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5265
5266 kvm_mmu_invlpg(vcpu, exit_qualification);
5267 skip_emulated_instruction(vcpu);
5268 return 1;
5269}
5270
fee84b07
AK		 5271static int handle_rdpmc(struct kvm_vcpu *vcpu)
5272{
5273 int err;
5274
5275 err = kvm_rdpmc(vcpu);
5276 kvm_complete_insn_gp(vcpu, err);
5277
5278 return 1;
5279}
5280
851ba692 5281static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5282{
5283 skip_emulated_instruction(vcpu);
f5f48ee1 5284 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5285 return 1;
5286}
5287
2acf923e
DC		 5288static int handle_xsetbv(struct kvm_vcpu *vcpu)
5289{
5290 u64 new_bv = kvm_read_edx_eax(vcpu);
5291 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5292
5293 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5294 skip_emulated_instruction(vcpu);
5295 return 1;
5296}
5297
851ba692 5298static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5299{
58fbbf26
KT		 5300 if (likely(fasteoi)) {
5301 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5302 int access_type, offset;
5303
5304 access_type = exit_qualification & APIC_ACCESS_TYPE;
5305 offset = exit_qualification & APIC_ACCESS_OFFSET;
5306 /*
5307 * Sane guest uses MOV to write EOI, with written value
5308 * not cared. So make a short-circuit here by avoiding
5309 * heavy instruction emulation.
5310 */
5311 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5312 (offset == APIC_EOI)) {
5313 kvm_lapic_set_eoi(vcpu);
5314 skip_emulated_instruction(vcpu);
5315 return 1;
5316 }
5317 }
51d8b661 5318 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5319}
5320
c7c9c56c
YZ		 5321static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5322{
5323 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5324 int vector = exit_qualification & 0xff;
5325
5326 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5327 kvm_apic_set_eoi_accelerated(vcpu, vector);
5328 return 1;
5329}
5330
83d4c286
YZ		 5331static int handle_apic_write(struct kvm_vcpu *vcpu)
5332{
5333 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5334 u32 offset = exit_qualification & 0xfff;
5335
5336 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5337 kvm_apic_write_nodecode(vcpu, offset);
5338 return 1;
5339}
5340
851ba692 5341static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5342{
60637aac 5343 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5344 unsigned long exit_qualification;
e269fb21
JK		 5345 bool has_error_code = false;
5346 u32 error_code = 0;
37817f29 5347 u16 tss_selector;
7f3d35fd 5348 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5349
5350 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5351 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5352 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5353
5354 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5355
5356 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5357 if (reason == TASK_SWITCH_GATE && idt_v) {
5358 switch (type) {
5359 case INTR_TYPE_NMI_INTR:
5360 vcpu->arch.nmi_injected = false;
654f06fc 5361 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5362 break;
5363 case INTR_TYPE_EXT_INTR:
66fd3f7f 5364 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5365 kvm_clear_interrupt_queue(vcpu);
5366 break;
5367 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5368 if (vmx->idt_vectoring_info &
5369 VECTORING_INFO_DELIVER_CODE_MASK) {
5370 has_error_code = true;
5371 error_code =
5372 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5373 }
5374 /* fall through */
64a7ec06
GN		 5375 case INTR_TYPE_SOFT_EXCEPTION:
5376 kvm_clear_exception_queue(vcpu);
5377 break;
5378 default:
5379 break;
5380 }
60637aac 5381 }
37817f29
IE		 5382 tss_selector = exit_qualification;
5383
64a7ec06
GN		 5384 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5385 type != INTR_TYPE_EXT_INTR &&
5386 type != INTR_TYPE_NMI_INTR))
5387 skip_emulated_instruction(vcpu);
5388
7f3d35fd
KW		 5389 if (kvm_task_switch(vcpu, tss_selector,
5390 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5391 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5392 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5393 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5394 vcpu->run->internal.ndata = 0;
42dbaa5a 5395 return 0;
acb54517 5396 }
42dbaa5a
JK		 5397
5398 /* clear all local breakpoint enable flags */
5399 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5400
5401 /*
5402 * TODO: What about debug traps on tss switch?
5403 * Are we supposed to inject them and update dr6?
5404 */
5405
5406 return 1;
37817f29
IE		 5407}
5408
851ba692 5409static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5410{
f9c617f6 5411 unsigned long exit_qualification;
1439442c 5412 gpa_t gpa;
4f5982a5 5413 u32 error_code;
1439442c 5414 int gla_validity;
1439442c 5415
f9c617f6 5416 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5417
1439442c
SY		 5418 gla_validity = (exit_qualification >> 7) & 0x3;
5419 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5420 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5421 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5422 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5423 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5424 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5425 (long unsigned int)exit_qualification);
851ba692
AK		 5426 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5427 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5428 return 0;
1439442c
SY		 5429 }
5430
0be9c7a8
GN		 5431 /*
5432 * EPT violation happened while executing iret from NMI,
5433 * "blocked by NMI" bit has to be set before next VM entry.
5434 * There are errata that may cause this bit to not be set:
5435 * AAK134, BY25.
5436 */
bcd1c294
GN		 5437 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5438 cpu_has_virtual_nmis() &&
5439 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5440 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5441
1439442c 5442 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5443 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5444
5445 /* It is a write fault? */
5446 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5447 /* It is a fetch fault? */
5448 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5449 /* ept page table is present? */
5450 error_code |= (exit_qualification >> 3) & 0x1;
5451
25d92081
YZ		 5452 vcpu->arch.exit_qualification = exit_qualification;
5453
4f5982a5 5454 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5455}
5456
68f89400
MT		 5457static u64 ept_rsvd_mask(u64 spte, int level)
5458{
5459 int i;
5460 u64 mask = 0;
5461
5462 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5463 mask |= (1ULL << i);
5464
5465 if (level > 2)
5466 /* bits 7:3 reserved */
5467 mask |= 0xf8;
5468 else if (level == 2) {
5469 if (spte & (1ULL << 7))
5470 /* 2MB ref, bits 20:12 reserved */
5471 mask |= 0x1ff000;
5472 else
5473 /* bits 6:3 reserved */
5474 mask |= 0x78;
5475 }
5476
5477 return mask;
5478}
5479
5480static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5481 int level)
5482{
5483 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5484
5485 /* 010b (write-only) */
5486 WARN_ON((spte & 0x7) == 0x2);
5487
5488 /* 110b (write/execute) */
5489 WARN_ON((spte & 0x7) == 0x6);
5490
5491 /* 100b (execute-only) and value not supported by logical processor */
5492 if (!cpu_has_vmx_ept_execute_only())
5493 WARN_ON((spte & 0x7) == 0x4);
5494
5495 /* not 000b */
5496 if ((spte & 0x7)) {
5497 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5498
5499 if (rsvd_bits != 0) {
5500 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5501 __func__, rsvd_bits);
5502 WARN_ON(1);
5503 }
5504
5505 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5506 u64 ept_mem_type = (spte & 0x38) >> 3;
5507
5508 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5509 ept_mem_type == 7) {
5510 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5511 __func__, ept_mem_type);
5512 WARN_ON(1);
5513 }
5514 }
5515 }
5516}
5517
851ba692 5518static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5519{
5520 u64 sptes[4];
ce88decf 5521 int nr_sptes, i, ret;
68f89400
MT		 5522 gpa_t gpa;
5523
5524 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5525
ce88decf 5526 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5527 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5528 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5529 EMULATE_DONE;
f8f55942
XG		 5530
5531 if (unlikely(ret == RET_MMIO_PF_INVALID))
5532 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5533
b37fbea6 5534 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5535 return 1;
5536
5537 /* It is the real ept misconfig */
68f89400
MT		 5538 printk(KERN_ERR "EPT: Misconfiguration.\n");
5539 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5540
5541 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5542
5543 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5544 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5545
851ba692
AK		 5546 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5547 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5548
5549 return 0;
5550}
5551
851ba692 5552static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5553{
5554 u32 cpu_based_vm_exec_control;
5555
5556 /* clear pending NMI */
5557 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5558 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5559 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5560 ++vcpu->stat.nmi_window_exits;
3842d135 5561 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5562
5563 return 1;
5564}
5565
80ced186 5566static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5567{
8b3079a5
AK		 5568 struct vcpu_vmx *vmx = to_vmx(vcpu);
5569 enum emulation_result err = EMULATE_DONE;
80ced186 5570 int ret = 1;
49e9d557
AK		 5571 u32 cpu_exec_ctrl;
5572 bool intr_window_requested;
b8405c18 5573 unsigned count = 130;
49e9d557
AK		 5574
5575 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5576 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5577
b8405c18 5578 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5579 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5580 return handle_interrupt_window(&vmx->vcpu);
5581
de87dcdd
AK		 5582 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5583 return 1;
5584
991eebf9 5585 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5586
ac0a48c3 5587 if (err == EMULATE_USER_EXIT) {
94452b9e 5588 ++vcpu->stat.mmio_exits;
80ced186
MG		 5589 ret = 0;
5590 goto out;
5591 }
1d5a4d9b 5592
de5f70e0
AK		 5593 if (err != EMULATE_DONE) {
5594 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5595 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5596 vcpu->run->internal.ndata = 0;
6d77dbfc 5597 return 0;
de5f70e0 5598 }
ea953ef0 5599
8d76c49e
GN		 5600 if (vcpu->arch.halt_request) {
5601 vcpu->arch.halt_request = 0;
5602 ret = kvm_emulate_halt(vcpu);
5603 goto out;
5604 }
5605
ea953ef0 5606 if (signal_pending(current))
80ced186 5607 goto out;
ea953ef0
MG		 5608 if (need_resched())
5609 schedule();
5610 }
5611
14168786 5612 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5613out:
5614 return ret;
ea953ef0
MG		 5615}
5616
4b8d54f9
ZE		 5617/*
5618 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5619 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5620 */
9fb41ba8 5621static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5622{
5623 skip_emulated_instruction(vcpu);
5624 kvm_vcpu_on_spin(vcpu);
5625
5626 return 1;
5627}
5628
59708670
SY		 5629static int handle_invalid_op(struct kvm_vcpu *vcpu)
5630{
5631 kvm_queue_exception(vcpu, UD_VECTOR);
5632 return 1;
5633}
5634
ff2f6fe9
NHE		 5635/*
5636 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5637 * We could reuse a single VMCS for all the L2 guests, but we also want the
5638 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5639 * allows keeping them loaded on the processor, and in the future will allow
5640 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5641 * every entry if they never change.
5642 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5643 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5644 *
5645 * The following functions allocate and free a vmcs02 in this pool.
5646 */
5647
5648/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5649static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5650{
5651 struct vmcs02_list *item;
5652 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5653 if (item->vmptr == vmx->nested.current_vmptr) {
5654 list_move(&item->list, &vmx->nested.vmcs02_pool);
5655 return &item->vmcs02;
5656 }
5657
5658 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5659 /* Recycle the least recently used VMCS. */
5660 item = list_entry(vmx->nested.vmcs02_pool.prev,
5661 struct vmcs02_list, list);
5662 item->vmptr = vmx->nested.current_vmptr;
5663 list_move(&item->list, &vmx->nested.vmcs02_pool);
5664 return &item->vmcs02;
5665 }
5666
5667 /* Create a new VMCS */
0fa24ce3 5668 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5669 if (!item)
5670 return NULL;
5671 item->vmcs02.vmcs = alloc_vmcs();
5672 if (!item->vmcs02.vmcs) {
5673 kfree(item);
5674 return NULL;
5675 }
5676 loaded_vmcs_init(&item->vmcs02);
5677 item->vmptr = vmx->nested.current_vmptr;
5678 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5679 vmx->nested.vmcs02_num++;
5680 return &item->vmcs02;
5681}
5682
5683/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5684static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5685{
5686 struct vmcs02_list *item;
5687 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5688 if (item->vmptr == vmptr) {
5689 free_loaded_vmcs(&item->vmcs02);
5690 list_del(&item->list);
5691 kfree(item);
5692 vmx->nested.vmcs02_num--;
5693 return;
5694 }
5695}
5696
5697/*
5698 * Free all VMCSs saved for this vcpu, except the one pointed by
5699 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5700 * currently used, if running L2), and vmcs01 when running L2.
5701 */
5702static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5703{
5704 struct vmcs02_list *item, *n;
5705 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5706 if (vmx->loaded_vmcs != &item->vmcs02)
5707 free_loaded_vmcs(&item->vmcs02);
5708 list_del(&item->list);
5709 kfree(item);
5710 }
5711 vmx->nested.vmcs02_num = 0;
5712
5713 if (vmx->loaded_vmcs != &vmx->vmcs01)
5714 free_loaded_vmcs(&vmx->vmcs01);
5715}
5716
0658fbaa
ACL		 5717/*
5718 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5719 * set the success or error code of an emulated VMX instruction, as specified
5720 * by Vol 2B, VMX Instruction Reference, "Conventions".
5721 */
5722static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5723{
5724 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5725 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5726 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5727}
5728
5729static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5730{
5731 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5732 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5733 X86_EFLAGS_SF | X86_EFLAGS_OF))
5734 | X86_EFLAGS_CF);
5735}
5736
145c28dd 5737static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5738 u32 vm_instruction_error)
5739{
5740 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5741 /*
5742 * failValid writes the error number to the current VMCS, which
5743 * can't be done there isn't a current VMCS.
5744 */
5745 nested_vmx_failInvalid(vcpu);
5746 return;
5747 }
5748 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5749 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5750 X86_EFLAGS_SF | X86_EFLAGS_OF))
5751 | X86_EFLAGS_ZF);
5752 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5753 /*
5754 * We don't need to force a shadow sync because
5755 * VM_INSTRUCTION_ERROR is not shadowed
5756 */
5757}
145c28dd 5758
f4124500
JK		 5759static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5760{
5761 struct vcpu_vmx *vmx =
5762 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5763
5764 vmx->nested.preemption_timer_expired = true;
5765 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5766 kvm_vcpu_kick(&vmx->vcpu);
5767
5768 return HRTIMER_NORESTART;
5769}
5770
ec378aee
NHE		 5771/*
5772 * Emulate the VMXON instruction.
5773 * Currently, we just remember that VMX is active, and do not save or even
5774 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5775 * do not currently need to store anything in that guest-allocated memory
5776 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5777 * argument is different from the VMXON pointer (which the spec says they do).
5778 */
5779static int handle_vmon(struct kvm_vcpu *vcpu)
5780{
5781 struct kvm_segment cs;
5782 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5783 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5784 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5785 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5786
5787 /* The Intel VMX Instruction Reference lists a bunch of bits that
5788 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5789 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5790 * Otherwise, we should fail with #UD. We test these now:
5791 */
5792 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5793 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5794 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5795 kvm_queue_exception(vcpu, UD_VECTOR);
5796 return 1;
5797 }
5798
5799 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5800 if (is_long_mode(vcpu) && !cs.l) {
5801 kvm_queue_exception(vcpu, UD_VECTOR);
5802 return 1;
5803 }
5804
5805 if (vmx_get_cpl(vcpu)) {
5806 kvm_inject_gp(vcpu, 0);
5807 return 1;
5808 }
145c28dd
AG		 5809 if (vmx->nested.vmxon) {
5810 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5811 skip_emulated_instruction(vcpu);
5812 return 1;
5813 }
b3897a49
NHE		 5814
5815 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5816 != VMXON_NEEDED_FEATURES) {
5817 kvm_inject_gp(vcpu, 0);
5818 return 1;
5819 }
5820
8de48833
AG		 5821 if (enable_shadow_vmcs) {
5822 shadow_vmcs = alloc_vmcs();
5823 if (!shadow_vmcs)
5824 return -ENOMEM;
5825 /* mark vmcs as shadow */
5826 shadow_vmcs->revision_id |= (1u << 31);
5827 /* init shadow vmcs */
5828 vmcs_clear(shadow_vmcs);
5829 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5830 }
ec378aee 5831
ff2f6fe9
NHE		 5832 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5833 vmx->nested.vmcs02_num = 0;
5834
f4124500
JK		 5835 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5836 HRTIMER_MODE_REL);
5837 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5838
ec378aee
NHE		 5839 vmx->nested.vmxon = true;
5840
5841 skip_emulated_instruction(vcpu);
a25eb114 5842 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5843 return 1;
5844}
5845
5846/*
5847 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5848 * for running VMX instructions (except VMXON, whose prerequisites are
5849 * slightly different). It also specifies what exception to inject otherwise.
5850 */
5851static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5852{
5853 struct kvm_segment cs;
5854 struct vcpu_vmx *vmx = to_vmx(vcpu);
5855
5856 if (!vmx->nested.vmxon) {
5857 kvm_queue_exception(vcpu, UD_VECTOR);
5858 return 0;
5859 }
5860
5861 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5862 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5863 (is_long_mode(vcpu) && !cs.l)) {
5864 kvm_queue_exception(vcpu, UD_VECTOR);
5865 return 0;
5866 }
5867
5868 if (vmx_get_cpl(vcpu)) {
5869 kvm_inject_gp(vcpu, 0);
5870 return 0;
5871 }
5872
5873 return 1;
5874}
5875
e7953d7f
AG		 5876static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5877{
8a1b9dd0 5878 u32 exec_control;
012f83cb
AG		 5879 if (enable_shadow_vmcs) {
5880 if (vmx->nested.current_vmcs12 != NULL) {
5881 /* copy to memory all shadowed fields in case
5882 they were modified */
5883 copy_shadow_to_vmcs12(vmx);
5884 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5885 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5886 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5887 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5888 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5889 }
5890 }
e7953d7f
AG		 5891 kunmap(vmx->nested.current_vmcs12_page);
5892 nested_release_page(vmx->nested.current_vmcs12_page);
5893}
5894
ec378aee
NHE		 5895/*
5896 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5897 * just stops using VMX.
5898 */
5899static void free_nested(struct vcpu_vmx *vmx)
5900{
5901 if (!vmx->nested.vmxon)
5902 return;
5903 vmx->nested.vmxon = false;
a9d30f33 5904 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5905 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5906 vmx->nested.current_vmptr = -1ull;
5907 vmx->nested.current_vmcs12 = NULL;
5908 }
e7953d7f
AG		 5909 if (enable_shadow_vmcs)
5910 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5911 /* Unpin physical memory we referred to in current vmcs02 */
5912 if (vmx->nested.apic_access_page) {
5913 nested_release_page(vmx->nested.apic_access_page);
5914 vmx->nested.apic_access_page = 0;
5915 }
ff2f6fe9
NHE		 5916
5917 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5918}
5919
5920/* Emulate the VMXOFF instruction */
5921static int handle_vmoff(struct kvm_vcpu *vcpu)
5922{
5923 if (!nested_vmx_check_permission(vcpu))
5924 return 1;
5925 free_nested(to_vmx(vcpu));
5926 skip_emulated_instruction(vcpu);
a25eb114 5927 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5928 return 1;
5929}
5930
064aea77
NHE		 5931/*
5932 * Decode the memory-address operand of a vmx instruction, as recorded on an
5933 * exit caused by such an instruction (run by a guest hypervisor).
5934 * On success, returns 0. When the operand is invalid, returns 1 and throws
5935 * #UD or #GP.
5936 */
5937static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5938 unsigned long exit_qualification,
5939 u32 vmx_instruction_info, gva_t *ret)
5940{
5941 /*
5942 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5943 * Execution", on an exit, vmx_instruction_info holds most of the
5944 * addressing components of the operand. Only the displacement part
5945 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5946 * For how an actual address is calculated from all these components,
5947 * refer to Vol. 1, "Operand Addressing".
5948 */
5949 int scaling = vmx_instruction_info & 3;
5950 int addr_size = (vmx_instruction_info >> 7) & 7;
5951 bool is_reg = vmx_instruction_info & (1u << 10);
5952 int seg_reg = (vmx_instruction_info >> 15) & 7;
5953 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5954 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5955 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5956 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5957
5958 if (is_reg) {
5959 kvm_queue_exception(vcpu, UD_VECTOR);
5960 return 1;
5961 }
5962
5963 /* Addr = segment_base + offset */
5964 /* offset = base + [index * scale] + displacement */
5965 *ret = vmx_get_segment_base(vcpu, seg_reg);
5966 if (base_is_valid)
5967 *ret += kvm_register_read(vcpu, base_reg);
5968 if (index_is_valid)
5969 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5970 *ret += exit_qualification; /* holds the displacement */
5971
5972 if (addr_size == 1) /* 32 bit */
5973 *ret &= 0xffffffff;
5974
5975 /*
5976 * TODO: throw #GP (and return 1) in various cases that the VM*
5977 * instructions require it - e.g., offset beyond segment limit,
5978 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5979 * address, and so on. Currently these are not checked.
5980 */
5981 return 0;
5982}
5983
27d6c865
NHE		 5984/* Emulate the VMCLEAR instruction */
5985static int handle_vmclear(struct kvm_vcpu *vcpu)
5986{
5987 struct vcpu_vmx *vmx = to_vmx(vcpu);
5988 gva_t gva;
5989 gpa_t vmptr;
5990 struct vmcs12 *vmcs12;
5991 struct page *page;
5992 struct x86_exception e;
5993
5994 if (!nested_vmx_check_permission(vcpu))
5995 return 1;
5996
5997 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5998 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5999 return 1;
6000
6001 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6002 sizeof(vmptr), &e)) {
6003 kvm_inject_page_fault(vcpu, &e);
6004 return 1;
6005 }
6006
6007 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6008 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6009 skip_emulated_instruction(vcpu);
6010 return 1;
6011 }
6012
6013 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6014 nested_release_vmcs12(vmx);
27d6c865
NHE		 6015 vmx->nested.current_vmptr = -1ull;
6016 vmx->nested.current_vmcs12 = NULL;
6017 }
6018
6019 page = nested_get_page(vcpu, vmptr);
6020 if (page == NULL) {
6021 /*
6022 * For accurate processor emulation, VMCLEAR beyond available
6023 * physical memory should do nothing at all. However, it is
6024 * possible that a nested vmx bug, not a guest hypervisor bug,
6025 * resulted in this case, so let's shut down before doing any
6026 * more damage:
6027 */
6028 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6029 return 1;
6030 }
6031 vmcs12 = kmap(page);
6032 vmcs12->launch_state = 0;
6033 kunmap(page);
6034 nested_release_page(page);
6035
6036 nested_free_vmcs02(vmx, vmptr);
6037
6038 skip_emulated_instruction(vcpu);
6039 nested_vmx_succeed(vcpu);
6040 return 1;
6041}
6042
cd232ad0
NHE		 6043static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6044
6045/* Emulate the VMLAUNCH instruction */
6046static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6047{
6048 return nested_vmx_run(vcpu, true);
6049}
6050
6051/* Emulate the VMRESUME instruction */
6052static int handle_vmresume(struct kvm_vcpu *vcpu)
6053{
6054
6055 return nested_vmx_run(vcpu, false);
6056}
6057
49f705c5
NHE		 6058enum vmcs_field_type {
6059 VMCS_FIELD_TYPE_U16 = 0,
6060 VMCS_FIELD_TYPE_U64 = 1,
6061 VMCS_FIELD_TYPE_U32 = 2,
6062 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6063};
6064
6065static inline int vmcs_field_type(unsigned long field)
6066{
6067 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6068 return VMCS_FIELD_TYPE_U32;
6069 return (field >> 13) & 0x3 ;
6070}
6071
6072static inline int vmcs_field_readonly(unsigned long field)
6073{
6074 return (((field >> 10) & 0x3) == 1);
6075}
6076
6077/*
6078 * Read a vmcs12 field. Since these can have varying lengths and we return
6079 * one type, we chose the biggest type (u64) and zero-extend the return value
6080 * to that size. Note that the caller, handle_vmread, might need to use only
6081 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6082 * 64-bit fields are to be returned).
6083 */
6084static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6085 unsigned long field, u64 *ret)
6086{
6087 short offset = vmcs_field_to_offset(field);
6088 char *p;
6089
6090 if (offset < 0)
6091 return 0;
6092
6093 p = ((char *)(get_vmcs12(vcpu))) + offset;
6094
6095 switch (vmcs_field_type(field)) {
6096 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6097 *ret = *((natural_width *)p);
6098 return 1;
6099 case VMCS_FIELD_TYPE_U16:
6100 *ret = *((u16 *)p);
6101 return 1;
6102 case VMCS_FIELD_TYPE_U32:
6103 *ret = *((u32 *)p);
6104 return 1;
6105 case VMCS_FIELD_TYPE_U64:
6106 *ret = *((u64 *)p);
6107 return 1;
6108 default:
6109 return 0; /* can never happen. */
6110 }
6111}
6112
20b97fea
AG		 6113
6114static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6115 unsigned long field, u64 field_value){
6116 short offset = vmcs_field_to_offset(field);
6117 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6118 if (offset < 0)
6119 return false;
6120
6121 switch (vmcs_field_type(field)) {
6122 case VMCS_FIELD_TYPE_U16:
6123 *(u16 *)p = field_value;
6124 return true;
6125 case VMCS_FIELD_TYPE_U32:
6126 *(u32 *)p = field_value;
6127 return true;
6128 case VMCS_FIELD_TYPE_U64:
6129 *(u64 *)p = field_value;
6130 return true;
6131 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6132 *(natural_width *)p = field_value;
6133 return true;
6134 default:
6135 return false; /* can never happen. */
6136 }
6137
6138}
6139
16f5b903
AG		 6140static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6141{
6142 int i;
6143 unsigned long field;
6144 u64 field_value;
6145 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6146 const unsigned long *fields = shadow_read_write_fields;
6147 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6148
6149 vmcs_load(shadow_vmcs);
6150
6151 for (i = 0; i < num_fields; i++) {
6152 field = fields[i];
6153 switch (vmcs_field_type(field)) {
6154 case VMCS_FIELD_TYPE_U16:
6155 field_value = vmcs_read16(field);
6156 break;
6157 case VMCS_FIELD_TYPE_U32:
6158 field_value = vmcs_read32(field);
6159 break;
6160 case VMCS_FIELD_TYPE_U64:
6161 field_value = vmcs_read64(field);
6162 break;
6163 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6164 field_value = vmcs_readl(field);
6165 break;
6166 }
6167 vmcs12_write_any(&vmx->vcpu, field, field_value);
6168 }
6169
6170 vmcs_clear(shadow_vmcs);
6171 vmcs_load(vmx->loaded_vmcs->vmcs);
6172}
6173
c3114420
AG		 6174static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6175{
c2bae893
MK		 6176 const unsigned long *fields[] = {
6177 shadow_read_write_fields,
6178 shadow_read_only_fields
c3114420 6179 };
c2bae893 6180 const int max_fields[] = {
c3114420
AG		 6181 max_shadow_read_write_fields,
6182 max_shadow_read_only_fields
6183 };
6184 int i, q;
6185 unsigned long field;
6186 u64 field_value = 0;
6187 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6188
6189 vmcs_load(shadow_vmcs);
6190
c2bae893 6191 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6192 for (i = 0; i < max_fields[q]; i++) {
6193 field = fields[q][i];
6194 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6195
6196 switch (vmcs_field_type(field)) {
6197 case VMCS_FIELD_TYPE_U16:
6198 vmcs_write16(field, (u16)field_value);
6199 break;
6200 case VMCS_FIELD_TYPE_U32:
6201 vmcs_write32(field, (u32)field_value);
6202 break;
6203 case VMCS_FIELD_TYPE_U64:
6204 vmcs_write64(field, (u64)field_value);
6205 break;
6206 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6207 vmcs_writel(field, (long)field_value);
6208 break;
6209 }
6210 }
6211 }
6212
6213 vmcs_clear(shadow_vmcs);
6214 vmcs_load(vmx->loaded_vmcs->vmcs);
6215}
6216
49f705c5
NHE		 6217/*
6218 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6219 * used before) all generate the same failure when it is missing.
6220 */
6221static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6222{
6223 struct vcpu_vmx *vmx = to_vmx(vcpu);
6224 if (vmx->nested.current_vmptr == -1ull) {
6225 nested_vmx_failInvalid(vcpu);
6226 skip_emulated_instruction(vcpu);
6227 return 0;
6228 }
6229 return 1;
6230}
6231
6232static int handle_vmread(struct kvm_vcpu *vcpu)
6233{
6234 unsigned long field;
6235 u64 field_value;
6236 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6237 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6238 gva_t gva = 0;
6239
6240 if (!nested_vmx_check_permission(vcpu) ||
6241 !nested_vmx_check_vmcs12(vcpu))
6242 return 1;
6243
6244 /* Decode instruction info and find the field to read */
6245 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6246 /* Read the field, zero-extended to a u64 field_value */
6247 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6248 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6249 skip_emulated_instruction(vcpu);
6250 return 1;
6251 }
6252 /*
6253 * Now copy part of this value to register or memory, as requested.
6254 * Note that the number of bits actually copied is 32 or 64 depending
6255 * on the guest's mode (32 or 64 bit), not on the given field's length.
6256 */
6257 if (vmx_instruction_info & (1u << 10)) {
6258 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6259 field_value);
6260 } else {
6261 if (get_vmx_mem_address(vcpu, exit_qualification,
6262 vmx_instruction_info, &gva))
6263 return 1;
6264 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6265 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6266 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6267 }
6268
6269 nested_vmx_succeed(vcpu);
6270 skip_emulated_instruction(vcpu);
6271 return 1;
6272}
6273
6274
6275static int handle_vmwrite(struct kvm_vcpu *vcpu)
6276{
6277 unsigned long field;
6278 gva_t gva;
6279 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6280 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6281 /* The value to write might be 32 or 64 bits, depending on L1's long
6282 * mode, and eventually we need to write that into a field of several
6283 * possible lengths. The code below first zero-extends the value to 64
6284 * bit (field_value), and then copies only the approriate number of
6285 * bits into the vmcs12 field.
6286 */
6287 u64 field_value = 0;
6288 struct x86_exception e;
6289
6290 if (!nested_vmx_check_permission(vcpu) ||
6291 !nested_vmx_check_vmcs12(vcpu))
6292 return 1;
6293
6294 if (vmx_instruction_info & (1u << 10))
6295 field_value = kvm_register_read(vcpu,
6296 (((vmx_instruction_info) >> 3) & 0xf));
6297 else {
6298 if (get_vmx_mem_address(vcpu, exit_qualification,
6299 vmx_instruction_info, &gva))
6300 return 1;
6301 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6302 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6303 kvm_inject_page_fault(vcpu, &e);
6304 return 1;
6305 }
6306 }
6307
6308
6309 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6310 if (vmcs_field_readonly(field)) {
6311 nested_vmx_failValid(vcpu,
6312 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6313 skip_emulated_instruction(vcpu);
6314 return 1;
6315 }
6316
20b97fea 6317 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6318 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6319 skip_emulated_instruction(vcpu);
6320 return 1;
6321 }
6322
6323 nested_vmx_succeed(vcpu);
6324 skip_emulated_instruction(vcpu);
6325 return 1;
6326}
6327
63846663
NHE		 6328/* Emulate the VMPTRLD instruction */
6329static int handle_vmptrld(struct kvm_vcpu *vcpu)
6330{
6331 struct vcpu_vmx *vmx = to_vmx(vcpu);
6332 gva_t gva;
6333 gpa_t vmptr;
6334 struct x86_exception e;
8a1b9dd0 6335 u32 exec_control;
63846663
NHE		 6336
6337 if (!nested_vmx_check_permission(vcpu))
6338 return 1;
6339
6340 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6341 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6342 return 1;
6343
6344 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6345 sizeof(vmptr), &e)) {
6346 kvm_inject_page_fault(vcpu, &e);
6347 return 1;
6348 }
6349
6350 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6351 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6352 skip_emulated_instruction(vcpu);
6353 return 1;
6354 }
6355
6356 if (vmx->nested.current_vmptr != vmptr) {
6357 struct vmcs12 *new_vmcs12;
6358 struct page *page;
6359 page = nested_get_page(vcpu, vmptr);
6360 if (page == NULL) {
6361 nested_vmx_failInvalid(vcpu);
6362 skip_emulated_instruction(vcpu);
6363 return 1;
6364 }
6365 new_vmcs12 = kmap(page);
6366 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6367 kunmap(page);
6368 nested_release_page_clean(page);
6369 nested_vmx_failValid(vcpu,
6370 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6371 skip_emulated_instruction(vcpu);
6372 return 1;
6373 }
e7953d7f
AG		 6374 if (vmx->nested.current_vmptr != -1ull)
6375 nested_release_vmcs12(vmx);
63846663
NHE		 6376
6377 vmx->nested.current_vmptr = vmptr;
6378 vmx->nested.current_vmcs12 = new_vmcs12;
6379 vmx->nested.current_vmcs12_page = page;
012f83cb 6380 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6381 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6382 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6383 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6384 vmcs_write64(VMCS_LINK_POINTER,
6385 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6386 vmx->nested.sync_shadow_vmcs = true;
6387 }
63846663
NHE		 6388 }
6389
6390 nested_vmx_succeed(vcpu);
6391 skip_emulated_instruction(vcpu);
6392 return 1;
6393}
6394
6a4d7550
NHE		 6395/* Emulate the VMPTRST instruction */
6396static int handle_vmptrst(struct kvm_vcpu *vcpu)
6397{
6398 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6399 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6400 gva_t vmcs_gva;
6401 struct x86_exception e;
6402
6403 if (!nested_vmx_check_permission(vcpu))
6404 return 1;
6405
6406 if (get_vmx_mem_address(vcpu, exit_qualification,
6407 vmx_instruction_info, &vmcs_gva))
6408 return 1;
6409 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6410 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6411 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6412 sizeof(u64), &e)) {
6413 kvm_inject_page_fault(vcpu, &e);
6414 return 1;
6415 }
6416 nested_vmx_succeed(vcpu);
6417 skip_emulated_instruction(vcpu);
6418 return 1;
6419}
6420
bfd0a56b
NHE		 6421/* Emulate the INVEPT instruction */
6422static int handle_invept(struct kvm_vcpu *vcpu)
6423{
6424 u32 vmx_instruction_info, types;
6425 unsigned long type;
6426 gva_t gva;
6427 struct x86_exception e;
6428 struct {
6429 u64 eptp, gpa;
6430 } operand;
6431 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6432
6433 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6434 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6435 kvm_queue_exception(vcpu, UD_VECTOR);
6436 return 1;
6437 }
6438
6439 if (!nested_vmx_check_permission(vcpu))
6440 return 1;
6441
6442 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6443 kvm_queue_exception(vcpu, UD_VECTOR);
6444 return 1;
6445 }
6446
6447 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6448 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6449
6450 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6451
6452 if (!(types & (1UL << type))) {
6453 nested_vmx_failValid(vcpu,
6454 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6455 return 1;
6456 }
6457
6458 /* According to the Intel VMX instruction reference, the memory
6459 * operand is read even if it isn't needed (e.g., for type==global)
6460 */
6461 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6462 vmx_instruction_info, &gva))
6463 return 1;
6464 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6465 sizeof(operand), &e)) {
6466 kvm_inject_page_fault(vcpu, &e);
6467 return 1;
6468 }
6469
6470 switch (type) {
6471 case VMX_EPT_EXTENT_CONTEXT:
6472 if ((operand.eptp & eptp_mask) !=
6473 (nested_ept_get_cr3(vcpu) & eptp_mask))
6474 break;
6475 case VMX_EPT_EXTENT_GLOBAL:
6476 kvm_mmu_sync_roots(vcpu);
6477 kvm_mmu_flush_tlb(vcpu);
6478 nested_vmx_succeed(vcpu);
6479 break;
6480 default:
6481 BUG_ON(1);
6482 break;
6483 }
6484
6485 skip_emulated_instruction(vcpu);
6486 return 1;
6487}
6488
6aa8b732
AK		 6489/*
6490 * The exit handlers return 1 if the exit was handled fully and guest execution
6491 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6492 * to be done to userspace and return 0.
6493 */
772e0318 6494static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6495 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6496 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6497 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6498 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6499 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6500 [EXIT_REASON_CR_ACCESS] = handle_cr,
6501 [EXIT_REASON_DR_ACCESS] = handle_dr,
6502 [EXIT_REASON_CPUID] = handle_cpuid,
6503 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6504 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6505 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6506 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6507 [EXIT_REASON_INVD] = handle_invd,
a7052897 6508 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6509 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6510 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6511 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6512 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6513 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6514 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6515 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6516 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6517 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6518 [EXIT_REASON_VMOFF] = handle_vmoff,
6519 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6520 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6521 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6522 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6523 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6524 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6525 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6526 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6527 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6528 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6529 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6530 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6531 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6532 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6533 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6534};
6535
6536static const int kvm_vmx_max_exit_handlers =
50a3485c 6537 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6538
908a7bdd
JK		 6539static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6540 struct vmcs12 *vmcs12)
6541{
6542 unsigned long exit_qualification;
6543 gpa_t bitmap, last_bitmap;
6544 unsigned int port;
6545 int size;
6546 u8 b;
6547
908a7bdd 6548 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6549 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6550
6551 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6552
6553 port = exit_qualification >> 16;
6554 size = (exit_qualification & 7) + 1;
6555
6556 last_bitmap = (gpa_t)-1;
6557 b = -1;
6558
6559 while (size > 0) {
6560 if (port < 0x8000)
6561 bitmap = vmcs12->io_bitmap_a;
6562 else if (port < 0x10000)
6563 bitmap = vmcs12->io_bitmap_b;
6564 else
6565 return 1;
6566 bitmap += (port & 0x7fff) / 8;
6567
6568 if (last_bitmap != bitmap)
6569 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6570 return 1;
6571 if (b & (1 << (port & 7)))
6572 return 1;
6573
6574 port++;
6575 size--;
6576 last_bitmap = bitmap;
6577 }
6578
6579 return 0;
6580}
6581
644d711a
NHE		 6582/*
6583 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6584 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6585 * disinterest in the current event (read or write a specific MSR) by using an
6586 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6587 */
6588static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6589 struct vmcs12 *vmcs12, u32 exit_reason)
6590{
6591 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6592 gpa_t bitmap;
6593
cbd29cb6 6594 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6595 return 1;
6596
6597 /*
6598 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6599 * for the four combinations of read/write and low/high MSR numbers.
6600 * First we need to figure out which of the four to use:
6601 */
6602 bitmap = vmcs12->msr_bitmap;
6603 if (exit_reason == EXIT_REASON_MSR_WRITE)
6604 bitmap += 2048;
6605 if (msr_index >= 0xc0000000) {
6606 msr_index -= 0xc0000000;
6607 bitmap += 1024;
6608 }
6609
6610 /* Then read the msr_index'th bit from this bitmap: */
6611 if (msr_index < 1024*8) {
6612 unsigned char b;
bd31a7f5
JK		 6613 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6614 return 1;
644d711a
NHE		 6615 return 1 & (b >> (msr_index & 7));
6616 } else
6617 return 1; /* let L1 handle the wrong parameter */
6618}
6619
6620/*
6621 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6622 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6623 * intercept (via guest_host_mask etc.) the current event.
6624 */
6625static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6626 struct vmcs12 *vmcs12)
6627{
6628 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6629 int cr = exit_qualification & 15;
6630 int reg = (exit_qualification >> 8) & 15;
6631 unsigned long val = kvm_register_read(vcpu, reg);
6632
6633 switch ((exit_qualification >> 4) & 3) {
6634 case 0: /* mov to cr */
6635 switch (cr) {
6636 case 0:
6637 if (vmcs12->cr0_guest_host_mask &
6638 (val ^ vmcs12->cr0_read_shadow))
6639 return 1;
6640 break;
6641 case 3:
6642 if ((vmcs12->cr3_target_count >= 1 &&
6643 vmcs12->cr3_target_value0 == val) ||
6644 (vmcs12->cr3_target_count >= 2 &&
6645 vmcs12->cr3_target_value1 == val) ||
6646 (vmcs12->cr3_target_count >= 3 &&
6647 vmcs12->cr3_target_value2 == val) ||
6648 (vmcs12->cr3_target_count >= 4 &&
6649 vmcs12->cr3_target_value3 == val))
6650 return 0;
6651 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6652 return 1;
6653 break;
6654 case 4:
6655 if (vmcs12->cr4_guest_host_mask &
6656 (vmcs12->cr4_read_shadow ^ val))
6657 return 1;
6658 break;
6659 case 8:
6660 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6661 return 1;
6662 break;
6663 }
6664 break;
6665 case 2: /* clts */
6666 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6667 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6668 return 1;
6669 break;
6670 case 1: /* mov from cr */
6671 switch (cr) {
6672 case 3:
6673 if (vmcs12->cpu_based_vm_exec_control &
6674 CPU_BASED_CR3_STORE_EXITING)
6675 return 1;
6676 break;
6677 case 8:
6678 if (vmcs12->cpu_based_vm_exec_control &
6679 CPU_BASED_CR8_STORE_EXITING)
6680 return 1;
6681 break;
6682 }
6683 break;
6684 case 3: /* lmsw */
6685 /*
6686 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6687 * cr0. Other attempted changes are ignored, with no exit.
6688 */
6689 if (vmcs12->cr0_guest_host_mask & 0xe &
6690 (val ^ vmcs12->cr0_read_shadow))
6691 return 1;
6692 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6693 !(vmcs12->cr0_read_shadow & 0x1) &&
6694 (val & 0x1))
6695 return 1;
6696 break;
6697 }
6698 return 0;
6699}
6700
6701/*
6702 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6703 * should handle it ourselves in L0 (and then continue L2). Only call this
6704 * when in is_guest_mode (L2).
6705 */
6706static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6707{
644d711a
NHE		 6708 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6709 struct vcpu_vmx *vmx = to_vmx(vcpu);
6710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6711 u32 exit_reason = vmx->exit_reason;
644d711a 6712
542060ea
JK		 6713 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6714 vmcs_readl(EXIT_QUALIFICATION),
6715 vmx->idt_vectoring_info,
6716 intr_info,
6717 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6718 KVM_ISA_VMX);
6719
644d711a
NHE		 6720 if (vmx->nested.nested_run_pending)
6721 return 0;
6722
6723 if (unlikely(vmx->fail)) {
bd80158a
JK		 6724 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6725 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6726 return 1;
6727 }
6728
6729 switch (exit_reason) {
6730 case EXIT_REASON_EXCEPTION_NMI:
6731 if (!is_exception(intr_info))
6732 return 0;
6733 else if (is_page_fault(intr_info))
6734 return enable_ept;
e504c909 6735 else if (is_no_device(intr_info) &&
ccf9844e 6736 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6737 return 0;
644d711a
NHE		 6738 return vmcs12->exception_bitmap &
6739 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6740 case EXIT_REASON_EXTERNAL_INTERRUPT:
6741 return 0;
6742 case EXIT_REASON_TRIPLE_FAULT:
6743 return 1;
6744 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6745 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6746 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6747 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6748 case EXIT_REASON_TASK_SWITCH:
6749 return 1;
6750 case EXIT_REASON_CPUID:
6751 return 1;
6752 case EXIT_REASON_HLT:
6753 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6754 case EXIT_REASON_INVD:
6755 return 1;
6756 case EXIT_REASON_INVLPG:
6757 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6758 case EXIT_REASON_RDPMC:
6759 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6760 case EXIT_REASON_RDTSC:
6761 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6762 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6763 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6764 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6765 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6766 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6767 case EXIT_REASON_INVEPT:
644d711a
NHE		 6768 /*
6769 * VMX instructions trap unconditionally. This allows L1 to
6770 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6771 */
6772 return 1;
6773 case EXIT_REASON_CR_ACCESS:
6774 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6775 case EXIT_REASON_DR_ACCESS:
6776 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6777 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6778 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6779 case EXIT_REASON_MSR_READ:
6780 case EXIT_REASON_MSR_WRITE:
6781 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6782 case EXIT_REASON_INVALID_STATE:
6783 return 1;
6784 case EXIT_REASON_MWAIT_INSTRUCTION:
6785 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6786 case EXIT_REASON_MONITOR_INSTRUCTION:
6787 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6788 case EXIT_REASON_PAUSE_INSTRUCTION:
6789 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6790 nested_cpu_has2(vmcs12,
6791 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6792 case EXIT_REASON_MCE_DURING_VMENTRY:
6793 return 0;
6794 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6795 return 1;
6796 case EXIT_REASON_APIC_ACCESS:
6797 return nested_cpu_has2(vmcs12,
6798 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6799 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6800 /*
6801 * L0 always deals with the EPT violation. If nested EPT is
6802 * used, and the nested mmu code discovers that the address is
6803 * missing in the guest EPT table (EPT12), the EPT violation
6804 * will be injected with nested_ept_inject_page_fault()
6805 */
6806 return 0;
644d711a 6807 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6808 /*
6809 * L2 never uses directly L1's EPT, but rather L0's own EPT
6810 * table (shadow on EPT) or a merged EPT table that L0 built
6811 * (EPT on EPT). So any problems with the structure of the
6812 * table is L0's fault.
6813 */
644d711a
NHE		 6814 return 0;
6815 case EXIT_REASON_WBINVD:
6816 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6817 case EXIT_REASON_XSETBV:
6818 return 1;
6819 default:
6820 return 1;
6821 }
6822}
6823
586f9607
AK		 6824static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6825{
6826 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6827 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6828}
6829
6aa8b732
AK		 6830/*
6831 * The guest has exited. See if we can fix it or if we need userspace
6832 * assistance.
6833 */
851ba692 6834static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6835{
29bd8a78 6836 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6837 u32 exit_reason = vmx->exit_reason;
1155f76a 6838 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6839
80ced186 6840 /* If guest state is invalid, start emulating */
14168786 6841 if (vmx->emulation_required)
80ced186 6842 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6843
644d711a 6844 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6845 nested_vmx_vmexit(vcpu, exit_reason,
6846 vmcs_read32(VM_EXIT_INTR_INFO),
6847 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6848 return 1;
6849 }
6850
5120702e
MG		 6851 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6852 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6853 vcpu->run->fail_entry.hardware_entry_failure_reason
6854 = exit_reason;
6855 return 0;
6856 }
6857
29bd8a78 6858 if (unlikely(vmx->fail)) {
851ba692
AK		 6859 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6860 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6861 = vmcs_read32(VM_INSTRUCTION_ERROR);
6862 return 0;
6863 }
6aa8b732 6864
b9bf6882
XG		 6865 /*
6866 * Note:
6867 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6868 * delivery event since it indicates guest is accessing MMIO.
6869 * The vm-exit can be triggered again after return to guest that
6870 * will cause infinite loop.
6871 */
d77c26fc 6872 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6873 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6874 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6875 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6876 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6877 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6878 vcpu->run->internal.ndata = 2;
6879 vcpu->run->internal.data[0] = vectoring_info;
6880 vcpu->run->internal.data[1] = exit_reason;
6881 return 0;
6882 }
3b86cd99 6883
644d711a
NHE		 6884 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6885 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6886 get_vmcs12(vcpu))))) {
c4282df9 6887 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6888 vmx->soft_vnmi_blocked = 0;
3b86cd99 6889 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6890 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6891 /*
6892 * This CPU don't support us in finding the end of an
6893 * NMI-blocked window if the guest runs with IRQs
6894 * disabled. So we pull the trigger after 1 s of
6895 * futile waiting, but inform the user about this.
6896 */
6897 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6898 "state on VCPU %d after 1 s timeout\n",
6899 __func__, vcpu->vcpu_id);
6900 vmx->soft_vnmi_blocked = 0;
3b86cd99 6901 }
3b86cd99
JK		 6902 }
6903
6aa8b732
AK		 6904 if (exit_reason < kvm_vmx_max_exit_handlers
6905 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6906 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6907 else {
851ba692
AK		 6908 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6909 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6910 }
6911 return 0;
6912}
6913
95ba8273 6914static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6915{
95ba8273 6916 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6917 vmcs_write32(TPR_THRESHOLD, 0);
6918 return;
6919 }
6920
95ba8273 6921 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6922}
6923
8d14695f
YZ		 6924static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6925{
6926 u32 sec_exec_control;
6927
6928 /*
6929 * There is not point to enable virtualize x2apic without enable
6930 * apicv
6931 */
c7c9c56c
YZ		 6932 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6933 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6934 return;
6935
6936 if (!vm_need_tpr_shadow(vcpu->kvm))
6937 return;
6938
6939 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6940
6941 if (set) {
6942 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6943 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6944 } else {
6945 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6946 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6947 }
6948 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6949
6950 vmx_set_msr_bitmap(vcpu);
6951}
6952
c7c9c56c
YZ		 6953static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6954{
6955 u16 status;
6956 u8 old;
6957
6958 if (!vmx_vm_has_apicv(kvm))
6959 return;
6960
6961 if (isr == -1)
6962 isr = 0;
6963
6964 status = vmcs_read16(GUEST_INTR_STATUS);
6965 old = status >> 8;
6966 if (isr != old) {
6967 status &= 0xff;
6968 status |= isr << 8;
6969 vmcs_write16(GUEST_INTR_STATUS, status);
6970 }
6971}
6972
6973static void vmx_set_rvi(int vector)
6974{
6975 u16 status;
6976 u8 old;
6977
6978 status = vmcs_read16(GUEST_INTR_STATUS);
6979 old = (u8)status & 0xff;
6980 if ((u8)vector != old) {
6981 status &= ~0xff;
6982 status |= (u8)vector;
6983 vmcs_write16(GUEST_INTR_STATUS, status);
6984 }
6985}
6986
6987static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6988{
6989 if (max_irr == -1)
6990 return;
6991
6992 vmx_set_rvi(max_irr);
6993}
6994
6995static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6996{
3d81bc7e
YZ		 6997 if (!vmx_vm_has_apicv(vcpu->kvm))
6998 return;
6999
c7c9c56c
YZ		 7000 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7001 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7002 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7003 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7004}
7005
51aa01d1 7006static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7007{
00eba012
AK		 7008 u32 exit_intr_info;
7009
7010 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7011 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7012 return;
7013
c5ca8e57 7014 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7015 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7016
7017 /* Handle machine checks before interrupts are enabled */
00eba012 7018 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7019 kvm_machine_check();
7020
20f65983 7021 /* We need to handle NMIs before interrupts are enabled */
00eba012 7022 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7023 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7024 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7025 asm("int $2");
ff9d07a0
ZY		 7026 kvm_after_handle_nmi(&vmx->vcpu);
7027 }
51aa01d1 7028}
20f65983 7029
a547c6db
YZ		 7030static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7031{
7032 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7033
7034 /*
7035 * If external interrupt exists, IF bit is set in rflags/eflags on the
7036 * interrupt stack frame, and interrupt will be enabled on a return
7037 * from interrupt handler.
7038 */
7039 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7040 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7041 unsigned int vector;
7042 unsigned long entry;
7043 gate_desc *desc;
7044 struct vcpu_vmx *vmx = to_vmx(vcpu);
7045#ifdef CONFIG_X86_64
7046 unsigned long tmp;
7047#endif
7048
7049 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7050 desc = (gate_desc *)vmx->host_idt_base + vector;
7051 entry = gate_offset(*desc);
7052 asm volatile(
7053#ifdef CONFIG_X86_64
7054 "mov %%" _ASM_SP ", %[sp]\n\t"
7055 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7056 "push $%c[ss]\n\t"
7057 "push %[sp]\n\t"
7058#endif
7059 "pushf\n\t"
7060 "orl $0x200, (%%" _ASM_SP ")\n\t"
7061 __ASM_SIZE(push) " $%c[cs]\n\t"
7062 "call *%[entry]\n\t"
7063 :
7064#ifdef CONFIG_X86_64
7065 [sp]"=&r"(tmp)
7066#endif
7067 :
7068 [entry]"r"(entry),
7069 [ss]"i"(__KERNEL_DS),
7070 [cs]"i"(__KERNEL_CS)
7071 );
7072 } else
7073 local_irq_enable();
7074}
7075
da8999d3
LJ		 7076static bool vmx_mpx_supported(void)
7077{
7078 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7079 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7080}
7081
51aa01d1
AK		 7082static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7083{
c5ca8e57 7084 u32 exit_intr_info;
51aa01d1
AK		 7085 bool unblock_nmi;
7086 u8 vector;
7087 bool idtv_info_valid;
7088
7089 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7090
cf393f75 7091 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7092 if (vmx->nmi_known_unmasked)
7093 return;
c5ca8e57
AK		 7094 /*
7095 * Can't use vmx->exit_intr_info since we're not sure what
7096 * the exit reason is.
7097 */
7098 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7099 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7100 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7101 /*
7b4a25cb 7102 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7103 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7104 * a guest IRET fault.
7b4a25cb
GN		 7105 * SDM 3: 23.2.2 (September 2008)
7106 * Bit 12 is undefined in any of the following cases:
7107 * If the VM exit sets the valid bit in the IDT-vectoring
7108 * information field.
7109 * If the VM exit is due to a double fault.
cf393f75 7110 */
7b4a25cb
GN		 7111 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7112 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7113 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7114 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7115 else
7116 vmx->nmi_known_unmasked =
7117 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7118 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7119 } else if (unlikely(vmx->soft_vnmi_blocked))
7120 vmx->vnmi_blocked_time +=
7121 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7122}
7123
3ab66e8a 7124static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7125 u32 idt_vectoring_info,
7126 int instr_len_field,
7127 int error_code_field)
51aa01d1 7128{
51aa01d1
AK		 7129 u8 vector;
7130 int type;
7131 bool idtv_info_valid;
7132
7133 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7134
3ab66e8a
JK		 7135 vcpu->arch.nmi_injected = false;
7136 kvm_clear_exception_queue(vcpu);
7137 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7138
7139 if (!idtv_info_valid)
7140 return;
7141
3ab66e8a 7142 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7143
668f612f
AK		 7144 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7145 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7146
64a7ec06 7147 switch (type) {
37b96e98 7148 case INTR_TYPE_NMI_INTR:
3ab66e8a 7149 vcpu->arch.nmi_injected = true;
668f612f 7150 /*
7b4a25cb 7151 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7152 * Clear bit "block by NMI" before VM entry if a NMI
7153 * delivery faulted.
668f612f 7154 */
3ab66e8a 7155 vmx_set_nmi_mask(vcpu, false);
37b96e98 7156 break;
37b96e98 7157 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7158 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7159 /* fall through */
7160 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7161 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7162 u32 err = vmcs_read32(error_code_field);
851eb667 7163 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7164 } else
851eb667 7165 kvm_requeue_exception(vcpu, vector);
37b96e98 7166 break;
66fd3f7f 7167 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7168 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7169 /* fall through */
37b96e98 7170 case INTR_TYPE_EXT_INTR:
3ab66e8a 7171 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7172 break;
7173 default:
7174 break;
f7d9238f 7175 }
cf393f75
AK		 7176}
7177
83422e17
AK		 7178static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7179{
3ab66e8a 7180 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7181 VM_EXIT_INSTRUCTION_LEN,
7182 IDT_VECTORING_ERROR_CODE);
7183}
7184
b463a6f7
AK		 7185static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7186{
3ab66e8a 7187 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7188 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7189 VM_ENTRY_INSTRUCTION_LEN,
7190 VM_ENTRY_EXCEPTION_ERROR_CODE);
7191
7192 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7193}
7194
d7cd9796
GN		 7195static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7196{
7197 int i, nr_msrs;
7198 struct perf_guest_switch_msr *msrs;
7199
7200 msrs = perf_guest_get_msrs(&nr_msrs);
7201
7202 if (!msrs)
7203 return;
7204
7205 for (i = 0; i < nr_msrs; i++)
7206 if (msrs[i].host == msrs[i].guest)
7207 clear_atomic_switch_msr(vmx, msrs[i].msr);
7208 else
7209 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7210 msrs[i].host);
7211}
7212
a3b5ba49 7213static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7214{
a2fa3e9f 7215 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7216 unsigned long debugctlmsr;
104f226b
AK		 7217
7218 /* Record the guest's net vcpu time for enforced NMI injections. */
7219 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7220 vmx->entry_time = ktime_get();
7221
7222 /* Don't enter VMX if guest state is invalid, let the exit handler
7223 start emulation until we arrive back to a valid state */
14168786 7224 if (vmx->emulation_required)
104f226b
AK		 7225 return;
7226
012f83cb
AG		 7227 if (vmx->nested.sync_shadow_vmcs) {
7228 copy_vmcs12_to_shadow(vmx);
7229 vmx->nested.sync_shadow_vmcs = false;
7230 }
7231
104f226b
AK		 7232 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7233 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7234 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7235 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7236
7237 /* When single-stepping over STI and MOV SS, we must clear the
7238 * corresponding interruptibility bits in the guest state. Otherwise
7239 * vmentry fails as it then expects bit 14 (BS) in pending debug
7240 * exceptions being set, but that's not correct for the guest debugging
7241 * case. */
7242 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7243 vmx_set_interrupt_shadow(vcpu, 0);
7244
d7cd9796 7245 atomic_switch_perf_msrs(vmx);
2a7921b7 7246 debugctlmsr = get_debugctlmsr();
d7cd9796 7247
d462b819 7248 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7249 asm(
6aa8b732 7250 /* Store host registers */
b188c81f
AK		 7251 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7252 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7253 "push %%" _ASM_CX " \n\t"
7254 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7255 "je 1f \n\t"
b188c81f 7256 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7257 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7258 "1: \n\t"
d3edefc0 7259 /* Reload cr2 if changed */
b188c81f
AK		 7260 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7261 "mov %%cr2, %%" _ASM_DX " \n\t"
7262 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7263 "je 2f \n\t"
b188c81f 7264 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7265 "2: \n\t"
6aa8b732 7266 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7267 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7268 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7269 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7270 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7271 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7272 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7273 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7274 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7275#ifdef CONFIG_X86_64
e08aa78a
AK		 7276 "mov %c[r8](%0), %%r8 \n\t"
7277 "mov %c[r9](%0), %%r9 \n\t"
7278 "mov %c[r10](%0), %%r10 \n\t"
7279 "mov %c[r11](%0), %%r11 \n\t"
7280 "mov %c[r12](%0), %%r12 \n\t"
7281 "mov %c[r13](%0), %%r13 \n\t"
7282 "mov %c[r14](%0), %%r14 \n\t"
7283 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7284#endif
b188c81f 7285 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7286
6aa8b732 7287 /* Enter guest mode */
83287ea4 7288 "jne 1f \n\t"
4ecac3fd 7289 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7290 "jmp 2f \n\t"
7291 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7292 "2: "
6aa8b732 7293 /* Save guest registers, load host registers, keep flags */
b188c81f 7294 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7295 "pop %0 \n\t"
b188c81f
AK		 7296 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7297 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7298 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7299 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7300 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7301 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7302 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7303#ifdef CONFIG_X86_64
e08aa78a
AK		 7304 "mov %%r8, %c[r8](%0) \n\t"
7305 "mov %%r9, %c[r9](%0) \n\t"
7306 "mov %%r10, %c[r10](%0) \n\t"
7307 "mov %%r11, %c[r11](%0) \n\t"
7308 "mov %%r12, %c[r12](%0) \n\t"
7309 "mov %%r13, %c[r13](%0) \n\t"
7310 "mov %%r14, %c[r14](%0) \n\t"
7311 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7312#endif
b188c81f
AK		 7313 "mov %%cr2, %%" _ASM_AX " \n\t"
7314 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7315
b188c81f 7316 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7317 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7318 ".pushsection .rodata \n\t"
7319 ".global vmx_return \n\t"
7320 "vmx_return: " _ASM_PTR " 2b \n\t"
7321 ".popsection"
e08aa78a 7322 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7323 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7324 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7325 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7326 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7327 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7328 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7329 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7330 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7331 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7332 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7333#ifdef CONFIG_X86_64
ad312c7c
ZX		 7334 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7335 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7336 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7337 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7338 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7339 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7340 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7341 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7342#endif
40712fae
AK		 7343 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7344 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7345 : "cc", "memory"
7346#ifdef CONFIG_X86_64
b188c81f 7347 , "rax", "rbx", "rdi", "rsi"
c2036300 7348 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7349#else
7350 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7351#endif
7352 );
6aa8b732 7353
2a7921b7
GN		 7354 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7355 if (debugctlmsr)
7356 update_debugctlmsr(debugctlmsr);
7357
aa67f609
AK		 7358#ifndef CONFIG_X86_64
7359 /*
7360 * The sysexit path does not restore ds/es, so we must set them to
7361 * a reasonable value ourselves.
7362 *
7363 * We can't defer this to vmx_load_host_state() since that function
7364 * may be executed in interrupt context, which saves and restore segments
7365 * around it, nullifying its effect.
7366 */
7367 loadsegment(ds, __USER_DS);
7368 loadsegment(es, __USER_DS);
7369#endif
7370
6de4f3ad 7371 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7372 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7373 | (1 << VCPU_EXREG_CPL)
aff48baa 7374 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7375 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7376 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7377 vcpu->arch.regs_dirty = 0;
7378
1155f76a
AK		 7379 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7380
d462b819 7381 vmx->loaded_vmcs->launched = 1;
1b6269db 7382
51aa01d1 7383 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7384 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7385
e0b890d3
GN		 7386 /*
7387 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7388 * we did not inject a still-pending event to L1 now because of
7389 * nested_run_pending, we need to re-enable this bit.
7390 */
7391 if (vmx->nested.nested_run_pending)
7392 kvm_make_request(KVM_REQ_EVENT, vcpu);
7393
7394 vmx->nested.nested_run_pending = 0;
7395
51aa01d1
AK		 7396 vmx_complete_atomic_exit(vmx);
7397 vmx_recover_nmi_blocking(vmx);
cf393f75 7398 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7399}
7400
6aa8b732
AK		 7401static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7402{
fb3f0f51
RR		 7403 struct vcpu_vmx *vmx = to_vmx(vcpu);
7404
cdbecfc3 7405 free_vpid(vmx);
d462b819 7406 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7407 free_nested(vmx);
fb3f0f51
RR		 7408 kfree(vmx->guest_msrs);
7409 kvm_vcpu_uninit(vcpu);
a4770347 7410 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7411}
7412
fb3f0f51 7413static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7414{
fb3f0f51 7415 int err;
c16f862d 7416 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7417 int cpu;
6aa8b732 7418
a2fa3e9f 7419 if (!vmx)
fb3f0f51
RR		 7420 return ERR_PTR(-ENOMEM);
7421
2384d2b3
SY		 7422 allocate_vpid(vmx);
7423
fb3f0f51
RR		 7424 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7425 if (err)
7426 goto free_vcpu;
965b58a5 7427
a2fa3e9f 7428 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7429 err = -ENOMEM;
fb3f0f51 7430 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7431 goto uninit_vcpu;
7432 }
965b58a5 7433
d462b819
NHE		 7434 vmx->loaded_vmcs = &vmx->vmcs01;
7435 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7436 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7437 goto free_msrs;
d462b819
NHE		 7438 if (!vmm_exclusive)
7439 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7440 loaded_vmcs_init(vmx->loaded_vmcs);
7441 if (!vmm_exclusive)
7442 kvm_cpu_vmxoff();
a2fa3e9f 7443
15ad7146
AK		 7444 cpu = get_cpu();
7445 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7446 vmx->vcpu.cpu = cpu;
8b9cf98c 7447 err = vmx_vcpu_setup(vmx);
fb3f0f51 7448 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7449 put_cpu();
fb3f0f51
RR		 7450 if (err)
7451 goto free_vmcs;
a63cb560 7452 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7453 err = alloc_apic_access_page(kvm);
7454 if (err)
5e4a0b3c 7455 goto free_vmcs;
a63cb560 7456 }
fb3f0f51 7457
b927a3ce
SY		 7458 if (enable_ept) {
7459 if (!kvm->arch.ept_identity_map_addr)
7460 kvm->arch.ept_identity_map_addr =
7461 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7462 err = -ENOMEM;
b7ebfb05
SY		 7463 if (alloc_identity_pagetable(kvm) != 0)
7464 goto free_vmcs;
93ea5388
GN		 7465 if (!init_rmode_identity_map(kvm))
7466 goto free_vmcs;
b927a3ce 7467 }
b7ebfb05 7468
a9d30f33
NHE		 7469 vmx->nested.current_vmptr = -1ull;
7470 vmx->nested.current_vmcs12 = NULL;
7471
fb3f0f51
RR		 7472 return &vmx->vcpu;
7473
7474free_vmcs:
5f3fbc34 7475 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7476free_msrs:
fb3f0f51
RR		 7477 kfree(vmx->guest_msrs);
7478uninit_vcpu:
7479 kvm_vcpu_uninit(&vmx->vcpu);
7480free_vcpu:
cdbecfc3 7481 free_vpid(vmx);
a4770347 7482 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7483 return ERR_PTR(err);
6aa8b732
AK		 7484}
7485
002c7f7c
YS		 7486static void __init vmx_check_processor_compat(void *rtn)
7487{
7488 struct vmcs_config vmcs_conf;
7489
7490 *(int *)rtn = 0;
7491 if (setup_vmcs_config(&vmcs_conf) < 0)
7492 *(int *)rtn = -EIO;
7493 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7494 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7495 smp_processor_id());
7496 *(int *)rtn = -EIO;
7497 }
7498}
7499
67253af5
SY		 7500static int get_ept_level(void)
7501{
7502 return VMX_EPT_DEFAULT_GAW + 1;
7503}
7504
4b12f0de 7505static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7506{
4b12f0de
SY		 7507 u64 ret;
7508
522c68c4
SY		 7509 /* For VT-d and EPT combination
7510 * 1. MMIO: always map as UC
7511 * 2. EPT with VT-d:
7512 * a. VT-d without snooping control feature: can't guarantee the
7513 * result, try to trust guest.
7514 * b. VT-d with snooping control feature: snooping control feature of
7515 * VT-d engine can guarantee the cache correctness. Just set it
7516 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7517 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7518 * consistent with host MTRR
7519 */
4b12f0de
SY		 7520 if (is_mmio)
7521 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7522 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7523 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7524 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7525 else
522c68c4 7526 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7527 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7528
7529 return ret;
64d4d521
SY		 7530}
7531
17cc3935 7532static int vmx_get_lpage_level(void)
344f414f 7533{
878403b7
SY		 7534 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7535 return PT_DIRECTORY_LEVEL;
7536 else
7537 /* For shadow and EPT supported 1GB page */
7538 return PT_PDPE_LEVEL;
344f414f
JR		 7539}
7540
0e851880
SY		 7541static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7542{
4e47c7a6
SY		 7543 struct kvm_cpuid_entry2 *best;
7544 struct vcpu_vmx *vmx = to_vmx(vcpu);
7545 u32 exec_control;
7546
7547 vmx->rdtscp_enabled = false;
7548 if (vmx_rdtscp_supported()) {
7549 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7550 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7551 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7552 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7553 vmx->rdtscp_enabled = true;
7554 else {
7555 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7556 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7557 exec_control);
7558 }
7559 }
7560 }
ad756a16 7561
ad756a16
MJ		 7562 /* Exposing INVPCID only when PCID is exposed */
7563 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7564 if (vmx_invpcid_supported() &&
4f977045 7565 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7566 guest_cpuid_has_pcid(vcpu)) {
29282fde 7567 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7568 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7569 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7570 exec_control);
7571 } else {
29282fde
TI		 7572 if (cpu_has_secondary_exec_ctrls()) {
7573 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7574 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7575 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7576 exec_control);
7577 }
ad756a16 7578 if (best)
4f977045 7579 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7580 }
0e851880
SY		 7581}
7582
d4330ef2
JR		 7583static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7584{
7b8050f5
NHE		 7585 if (func == 1 && nested)
7586 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7587}
7588
25d92081
YZ		 7589static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7590 struct x86_exception *fault)
7591{
533558bc
JK		 7592 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7593 u32 exit_reason;
25d92081
YZ		 7594
7595 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7596 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7597 else
533558bc
JK		 7598 exit_reason = EXIT_REASON_EPT_VIOLATION;
7599 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7600 vmcs12->guest_physical_address = fault->address;
7601}
7602
155a97a3
NHE		 7603/* Callbacks for nested_ept_init_mmu_context: */
7604
7605static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7606{
7607 /* return the page table to be shadowed - in our case, EPT12 */
7608 return get_vmcs12(vcpu)->ept_pointer;
7609}
7610
8a3c1a33 7611static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7612{
8a3c1a33 7613 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7614 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7615
7616 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7617 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7618 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7619
7620 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7621}
7622
7623static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7624{
7625 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7626}
7627
feaf0c7d
GN		 7628static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7629 struct x86_exception *fault)
7630{
7631 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7632
7633 WARN_ON(!is_guest_mode(vcpu));
7634
7635 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7636 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7637 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7638 vmcs_read32(VM_EXIT_INTR_INFO),
7639 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7640 else
7641 kvm_inject_page_fault(vcpu, fault);
7642}
7643
f4124500
JK		 7644static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7645{
7646 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7647 struct vcpu_vmx *vmx = to_vmx(vcpu);
7648
7649 if (vcpu->arch.virtual_tsc_khz == 0)
7650 return;
7651
7652 /* Make sure short timeouts reliably trigger an immediate vmexit.
7653 * hrtimer_start does not guarantee this. */
7654 if (preemption_timeout <= 1) {
7655 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7656 return;
7657 }
7658
7659 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7660 preemption_timeout *= 1000000;
7661 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7662 hrtimer_start(&vmx->nested.preemption_timer,
7663 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7664}
7665
fe3ef05c
NHE		 7666/*
7667 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7668 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7669 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7670 * guest in a way that will both be appropriate to L1's requests, and our
7671 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7672 * function also has additional necessary side-effects, like setting various
7673 * vcpu->arch fields.
7674 */
7675static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7676{
7677 struct vcpu_vmx *vmx = to_vmx(vcpu);
7678 u32 exec_control;
7679
7680 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7681 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7682 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7683 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7684 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7685 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7686 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7687 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7688 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7689 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7690 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7691 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7692 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7693 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7694 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7695 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7696 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7697 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7698 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7699 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7700 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7701 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7702 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7703 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7704 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7705 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7706 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7707 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7708 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7709 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7710 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7711 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7712 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7713 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7714 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7715 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7716
7717 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7718 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7719 vmcs12->vm_entry_intr_info_field);
7720 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7721 vmcs12->vm_entry_exception_error_code);
7722 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7723 vmcs12->vm_entry_instruction_len);
7724 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7725 vmcs12->guest_interruptibility_info);
fe3ef05c 7726 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7727 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7728 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7729 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7730 vmcs12->guest_pending_dbg_exceptions);
7731 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7732 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7733
7734 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7735
f4124500
JK		 7736 exec_control = vmcs12->pin_based_vm_exec_control;
7737 exec_control |= vmcs_config.pin_based_exec_ctrl;
7738 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7739 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7740
f4124500
JK		 7741 vmx->nested.preemption_timer_expired = false;
7742 if (nested_cpu_has_preemption_timer(vmcs12))
7743 vmx_start_preemption_timer(vcpu);
0238ea91 7744
fe3ef05c
NHE		 7745 /*
7746 * Whether page-faults are trapped is determined by a combination of
7747 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7748 * If enable_ept, L0 doesn't care about page faults and we should
7749 * set all of these to L1's desires. However, if !enable_ept, L0 does
7750 * care about (at least some) page faults, and because it is not easy
7751 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7752 * to exit on each and every L2 page fault. This is done by setting
7753 * MASK=MATCH=0 and (see below) EB.PF=1.
7754 * Note that below we don't need special code to set EB.PF beyond the
7755 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7756 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7757 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7758 *
7759 * A problem with this approach (when !enable_ept) is that L1 may be
7760 * injected with more page faults than it asked for. This could have
7761 * caused problems, but in practice existing hypervisors don't care.
7762 * To fix this, we will need to emulate the PFEC checking (on the L1
7763 * page tables), using walk_addr(), when injecting PFs to L1.
7764 */
7765 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7766 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7767 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7768 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7769
7770 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7771 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7772 if (!vmx->rdtscp_enabled)
7773 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7774 /* Take the following fields only from vmcs12 */
7775 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7776 if (nested_cpu_has(vmcs12,
7777 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7778 exec_control |= vmcs12->secondary_vm_exec_control;
7779
7780 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7781 /*
7782 * Translate L1 physical address to host physical
7783 * address for vmcs02. Keep the page pinned, so this
7784 * physical address remains valid. We keep a reference
7785 * to it so we can release it later.
7786 */
7787 if (vmx->nested.apic_access_page) /* shouldn't happen */
7788 nested_release_page(vmx->nested.apic_access_page);
7789 vmx->nested.apic_access_page =
7790 nested_get_page(vcpu, vmcs12->apic_access_addr);
7791 /*
7792 * If translation failed, no matter: This feature asks
7793 * to exit when accessing the given address, and if it
7794 * can never be accessed, this feature won't do
7795 * anything anyway.
7796 */
7797 if (!vmx->nested.apic_access_page)
7798 exec_control &=
7799 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7800 else
7801 vmcs_write64(APIC_ACCESS_ADDR,
7802 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7803 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7804 exec_control |=
7805 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7806 vmcs_write64(APIC_ACCESS_ADDR,
7807 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7808 }
7809
7810 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7811 }
7812
7813
7814 /*
7815 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7816 * Some constant fields are set here by vmx_set_constant_host_state().
7817 * Other fields are different per CPU, and will be set later when
7818 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7819 */
a547c6db 7820 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7821
7822 /*
7823 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7824 * entry, but only if the current (host) sp changed from the value
7825 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7826 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7827 * here we just force the write to happen on entry.
7828 */
7829 vmx->host_rsp = 0;
7830
7831 exec_control = vmx_exec_control(vmx); /* L0's desires */
7832 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7833 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7834 exec_control &= ~CPU_BASED_TPR_SHADOW;
7835 exec_control |= vmcs12->cpu_based_vm_exec_control;
7836 /*
7837 * Merging of IO and MSR bitmaps not currently supported.
7838 * Rather, exit every time.
7839 */
7840 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7841 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7842 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7843
7844 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7845
7846 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7847 * bitwise-or of what L1 wants to trap for L2, and what we want to
7848 * trap. Note that CR0.TS also needs updating - we do this later.
7849 */
7850 update_exception_bitmap(vcpu);
7851 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7852 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7853
8049d651
NHE		 7854 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7855 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7856 * bits are further modified by vmx_set_efer() below.
7857 */
f4124500 7858 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7859
7860 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7861 * emulated by vmx_set_efer(), below.
7862 */
2961e876 7863 vm_entry_controls_init(vmx,
8049d651
NHE		 7864 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7865 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7866 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7867
44811c02 7868 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7869 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7870 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7871 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7872 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7873
7874
7875 set_cr4_guest_host_mask(vmx);
7876
36be0b9d
PB		 7877 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7878 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7879
27fc51b2
NHE		 7880 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7881 vmcs_write64(TSC_OFFSET,
7882 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7883 else
7884 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7885
7886 if (enable_vpid) {
7887 /*
7888 * Trivially support vpid by letting L2s share their parent
7889 * L1's vpid. TODO: move to a more elaborate solution, giving
7890 * each L2 its own vpid and exposing the vpid feature to L1.
7891 */
7892 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7893 vmx_flush_tlb(vcpu);
7894 }
7895
155a97a3
NHE		 7896 if (nested_cpu_has_ept(vmcs12)) {
7897 kvm_mmu_unload(vcpu);
7898 nested_ept_init_mmu_context(vcpu);
7899 }
7900
fe3ef05c
NHE		 7901 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7902 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7903 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7904 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7905 else
7906 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7907 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7908 vmx_set_efer(vcpu, vcpu->arch.efer);
7909
7910 /*
7911 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7912 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7913 * The CR0_READ_SHADOW is what L2 should have expected to read given
7914 * the specifications by L1; It's not enough to take
7915 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7916 * have more bits than L1 expected.
7917 */
7918 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7919 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7920
7921 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7922 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7923
7924 /* shadow page tables on either EPT or shadow page tables */
7925 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7926 kvm_mmu_reset_context(vcpu);
7927
feaf0c7d
GN		 7928 if (!enable_ept)
7929 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7930
3633cfc3
NHE		 7931 /*
7932 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7933 */
7934 if (enable_ept) {
7935 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7936 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7937 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7938 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7939 }
7940
fe3ef05c
NHE		 7941 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7942 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7943}
7944
cd232ad0
NHE		 7945/*
7946 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7947 * for running an L2 nested guest.
7948 */
7949static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7950{
7951 struct vmcs12 *vmcs12;
7952 struct vcpu_vmx *vmx = to_vmx(vcpu);
7953 int cpu;
7954 struct loaded_vmcs *vmcs02;
384bb783 7955 bool ia32e;
cd232ad0
NHE		 7956
7957 if (!nested_vmx_check_permission(vcpu) ||
7958 !nested_vmx_check_vmcs12(vcpu))
7959 return 1;
7960
7961 skip_emulated_instruction(vcpu);
7962 vmcs12 = get_vmcs12(vcpu);
7963
012f83cb
AG		 7964 if (enable_shadow_vmcs)
7965 copy_shadow_to_vmcs12(vmx);
7966
7c177938
NHE		 7967 /*
7968 * The nested entry process starts with enforcing various prerequisites
7969 * on vmcs12 as required by the Intel SDM, and act appropriately when
7970 * they fail: As the SDM explains, some conditions should cause the
7971 * instruction to fail, while others will cause the instruction to seem
7972 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7973 * To speed up the normal (success) code path, we should avoid checking
7974 * for misconfigurations which will anyway be caught by the processor
7975 * when using the merged vmcs02.
7976 */
7977 if (vmcs12->launch_state == launch) {
7978 nested_vmx_failValid(vcpu,
7979 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7980 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7981 return 1;
7982 }
7983
6dfacadd
JK		 7984 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7985 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7986 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7987 return 1;
7988 }
7989
7c177938
NHE		 7990 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7991 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7992 /*TODO: Also verify bits beyond physical address width are 0*/
7993 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7994 return 1;
7995 }
7996
7997 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7998 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7999 /*TODO: Also verify bits beyond physical address width are 0*/
8000 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8001 return 1;
8002 }
8003
8004 if (vmcs12->vm_entry_msr_load_count > 0 ||
8005 vmcs12->vm_exit_msr_load_count > 0 ||
8006 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8007 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8008 __func__);
7c177938
NHE		 8009 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8010 return 1;
8011 }
8012
8013 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8014 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8015 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8016 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8017 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8018 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8019 !vmx_control_verify(vmcs12->vm_exit_controls,
8020 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8021 !vmx_control_verify(vmcs12->vm_entry_controls,
8022 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8023 {
8024 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8025 return 1;
8026 }
8027
8028 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8029 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8030 nested_vmx_failValid(vcpu,
8031 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8032 return 1;
8033 }
8034
92fbc7b1 8035 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8036 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8037 nested_vmx_entry_failure(vcpu, vmcs12,
8038 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8039 return 1;
8040 }
8041 if (vmcs12->vmcs_link_pointer != -1ull) {
8042 nested_vmx_entry_failure(vcpu, vmcs12,
8043 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8044 return 1;
8045 }
8046
384bb783 8047 /*
cb0c8cda 8048 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8049 * are performed on the field for the IA32_EFER MSR:
8050 * - Bits reserved in the IA32_EFER MSR must be 0.
8051 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8052 * the IA-32e mode guest VM-exit control. It must also be identical
8053 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8054 * CR0.PG) is 1.
8055 */
8056 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8057 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8058 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8059 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8060 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8061 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8062 nested_vmx_entry_failure(vcpu, vmcs12,
8063 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8064 return 1;
8065 }
8066 }
8067
8068 /*
8069 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8070 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8071 * the values of the LMA and LME bits in the field must each be that of
8072 * the host address-space size VM-exit control.
8073 */
8074 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8075 ia32e = (vmcs12->vm_exit_controls &
8076 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8077 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8078 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8079 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8080 nested_vmx_entry_failure(vcpu, vmcs12,
8081 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8082 return 1;
8083 }
8084 }
8085
7c177938
NHE		 8086 /*
8087 * We're finally done with prerequisite checking, and can start with
8088 * the nested entry.
8089 */
8090
cd232ad0
NHE		 8091 vmcs02 = nested_get_current_vmcs02(vmx);
8092 if (!vmcs02)
8093 return -ENOMEM;
8094
8095 enter_guest_mode(vcpu);
8096
8097 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8098
8099 cpu = get_cpu();
8100 vmx->loaded_vmcs = vmcs02;
8101 vmx_vcpu_put(vcpu);
8102 vmx_vcpu_load(vcpu, cpu);
8103 vcpu->cpu = cpu;
8104 put_cpu();
8105
36c3cc42
JK		 8106 vmx_segment_cache_clear(vmx);
8107
cd232ad0
NHE		 8108 vmcs12->launch_state = 1;
8109
8110 prepare_vmcs02(vcpu, vmcs12);
8111
6dfacadd
JK		 8112 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8113 return kvm_emulate_halt(vcpu);
8114
7af40ad3
JK		 8115 vmx->nested.nested_run_pending = 1;
8116
cd232ad0
NHE		 8117 /*
8118 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8119 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8120 * returned as far as L1 is concerned. It will only return (and set
8121 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8122 */
8123 return 1;
8124}
8125
4704d0be
NHE		 8126/*
8127 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8128 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8129 * This function returns the new value we should put in vmcs12.guest_cr0.
8130 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8131 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8132 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8133 * didn't trap the bit, because if L1 did, so would L0).
8134 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8135 * been modified by L2, and L1 knows it. So just leave the old value of
8136 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8137 * isn't relevant, because if L0 traps this bit it can set it to anything.
8138 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8139 * changed these bits, and therefore they need to be updated, but L0
8140 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8141 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8142 */
8143static inline unsigned long
8144vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8145{
8146 return
8147 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8148 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8149 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8150 vcpu->arch.cr0_guest_owned_bits));
8151}
8152
8153static inline unsigned long
8154vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8155{
8156 return
8157 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8158 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8159 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8160 vcpu->arch.cr4_guest_owned_bits));
8161}
8162
5f3d5799
JK		 8163static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8164 struct vmcs12 *vmcs12)
8165{
8166 u32 idt_vectoring;
8167 unsigned int nr;
8168
851eb667 8169 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8170 nr = vcpu->arch.exception.nr;
8171 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8172
8173 if (kvm_exception_is_soft(nr)) {
8174 vmcs12->vm_exit_instruction_len =
8175 vcpu->arch.event_exit_inst_len;
8176 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8177 } else
8178 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8179
8180 if (vcpu->arch.exception.has_error_code) {
8181 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8182 vmcs12->idt_vectoring_error_code =
8183 vcpu->arch.exception.error_code;
8184 }
8185
8186 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8187 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8188 vmcs12->idt_vectoring_info_field =
8189 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8190 } else if (vcpu->arch.interrupt.pending) {
8191 nr = vcpu->arch.interrupt.nr;
8192 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8193
8194 if (vcpu->arch.interrupt.soft) {
8195 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8196 vmcs12->vm_entry_instruction_len =
8197 vcpu->arch.event_exit_inst_len;
8198 } else
8199 idt_vectoring |= INTR_TYPE_EXT_INTR;
8200
8201 vmcs12->idt_vectoring_info_field = idt_vectoring;
8202 }
8203}
8204
b6b8a145
JK		 8205static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8206{
8207 struct vcpu_vmx *vmx = to_vmx(vcpu);
8208
f4124500
JK		 8209 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8210 vmx->nested.preemption_timer_expired) {
8211 if (vmx->nested.nested_run_pending)
8212 return -EBUSY;
8213 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8214 return 0;
8215 }
8216
b6b8a145 8217 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8218 if (vmx->nested.nested_run_pending ||
8219 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8220 return -EBUSY;
8221 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8222 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8223 INTR_INFO_VALID_MASK, 0);
8224 /*
8225 * The NMI-triggered VM exit counts as injection:
8226 * clear this one and block further NMIs.
8227 */
8228 vcpu->arch.nmi_pending = 0;
8229 vmx_set_nmi_mask(vcpu, true);
8230 return 0;
8231 }
8232
8233 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8234 nested_exit_on_intr(vcpu)) {
8235 if (vmx->nested.nested_run_pending)
8236 return -EBUSY;
8237 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8238 }
8239
8240 return 0;
8241}
8242
f4124500
JK		 8243static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8244{
8245 ktime_t remaining =
8246 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8247 u64 value;
8248
8249 if (ktime_to_ns(remaining) <= 0)
8250 return 0;
8251
8252 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8253 do_div(value, 1000000);
8254 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8255}
8256
4704d0be
NHE		 8257/*
8258 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8259 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8260 * and this function updates it to reflect the changes to the guest state while
8261 * L2 was running (and perhaps made some exits which were handled directly by L0
8262 * without going back to L1), and to reflect the exit reason.
8263 * Note that we do not have to copy here all VMCS fields, just those that
8264 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8265 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8266 * which already writes to vmcs12 directly.
8267 */
533558bc
JK		 8268static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8269 u32 exit_reason, u32 exit_intr_info,
8270 unsigned long exit_qualification)
4704d0be
NHE		 8271{
8272 /* update guest state fields: */
8273 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8274 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8275
8276 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8277 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8278 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8279 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8280
8281 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8282 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8283 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8284 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8285 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8286 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8287 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8288 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8289 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8290 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8291 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8292 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8293 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8294 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8295 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8296 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8297 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8298 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8299 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8300 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8301 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8302 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8303 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8304 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8305 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8306 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8307 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8308 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8309 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8310 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8311 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8312 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8313 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8314 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8315 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8316 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8317
4704d0be
NHE		 8318 vmcs12->guest_interruptibility_info =
8319 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8320 vmcs12->guest_pending_dbg_exceptions =
8321 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8322 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8323 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8324 else
8325 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8326
f4124500
JK		 8327 if (nested_cpu_has_preemption_timer(vmcs12)) {
8328 if (vmcs12->vm_exit_controls &
8329 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8330 vmcs12->vmx_preemption_timer_value =
8331 vmx_get_preemption_timer_value(vcpu);
8332 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8333 }
7854cbca 8334
3633cfc3
NHE		 8335 /*
8336 * In some cases (usually, nested EPT), L2 is allowed to change its
8337 * own CR3 without exiting. If it has changed it, we must keep it.
8338 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8339 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8340 *
8341 * Additionally, restore L2's PDPTR to vmcs12.
8342 */
8343 if (enable_ept) {
8344 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8345 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8346 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8347 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8348 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8349 }
8350
c18911a2
JK		 8351 vmcs12->vm_entry_controls =
8352 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8353 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8354
4704d0be
NHE		 8355 /* TODO: These cannot have changed unless we have MSR bitmaps and
8356 * the relevant bit asks not to trap the change */
8357 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8358 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8359 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8360 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8361 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8362 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8363 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8364 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8365 if (vmx_mpx_supported())
8366 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8367
8368 /* update exit information fields: */
8369
533558bc
JK		 8370 vmcs12->vm_exit_reason = exit_reason;
8371 vmcs12->exit_qualification = exit_qualification;
4704d0be 8372
533558bc 8373 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8374 if ((vmcs12->vm_exit_intr_info &
8375 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8376 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8377 vmcs12->vm_exit_intr_error_code =
8378 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8379 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8380 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8381 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8382
5f3d5799
JK		 8383 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8384 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8385 * instead of reading the real value. */
4704d0be 8386 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8387
8388 /*
8389 * Transfer the event that L0 or L1 may wanted to inject into
8390 * L2 to IDT_VECTORING_INFO_FIELD.
8391 */
8392 vmcs12_save_pending_event(vcpu, vmcs12);
8393 }
8394
8395 /*
8396 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8397 * preserved above and would only end up incorrectly in L1.
8398 */
8399 vcpu->arch.nmi_injected = false;
8400 kvm_clear_exception_queue(vcpu);
8401 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8402}
8403
8404/*
8405 * A part of what we need to when the nested L2 guest exits and we want to
8406 * run its L1 parent, is to reset L1's guest state to the host state specified
8407 * in vmcs12.
8408 * This function is to be called not only on normal nested exit, but also on
8409 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8410 * Failures During or After Loading Guest State").
8411 * This function should be called when the active VMCS is L1's (vmcs01).
8412 */
733568f9
JK		 8413static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8414 struct vmcs12 *vmcs12)
4704d0be 8415{
21feb4eb
ACL		 8416 struct kvm_segment seg;
8417
4704d0be
NHE		 8418 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8419 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8420 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8421 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8422 else
8423 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8424 vmx_set_efer(vcpu, vcpu->arch.efer);
8425
8426 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8427 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8428 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8429 /*
8430 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8431 * actually changed, because it depends on the current state of
8432 * fpu_active (which may have changed).
8433 * Note that vmx_set_cr0 refers to efer set above.
8434 */
9e3e4dbf 8435 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8436 /*
8437 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8438 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8439 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8440 */
8441 update_exception_bitmap(vcpu);
8442 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8443 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8444
8445 /*
8446 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8447 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8448 */
8449 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8450 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8451
29bf08f1 8452 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8453
4704d0be
NHE		 8454 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8455 kvm_mmu_reset_context(vcpu);
8456
feaf0c7d
GN		 8457 if (!enable_ept)
8458 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8459
4704d0be
NHE		 8460 if (enable_vpid) {
8461 /*
8462 * Trivially support vpid by letting L2s share their parent
8463 * L1's vpid. TODO: move to a more elaborate solution, giving
8464 * each L2 its own vpid and exposing the vpid feature to L1.
8465 */
8466 vmx_flush_tlb(vcpu);
8467 }
8468
8469
8470 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8471 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8472 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8473 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8474 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8475
36be0b9d
PB		 8476 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8477 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8478 vmcs_write64(GUEST_BNDCFGS, 0);
8479
44811c02 8480 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8481 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8482 vcpu->arch.pat = vmcs12->host_ia32_pat;
8483 }
4704d0be
NHE		 8484 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8485 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8486 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8487
21feb4eb
ACL		 8488 /* Set L1 segment info according to Intel SDM
8489 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8490 seg = (struct kvm_segment) {
8491 .base = 0,
8492 .limit = 0xFFFFFFFF,
8493 .selector = vmcs12->host_cs_selector,
8494 .type = 11,
8495 .present = 1,
8496 .s = 1,
8497 .g = 1
8498 };
8499 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8500 seg.l = 1;
8501 else
8502 seg.db = 1;
8503 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8504 seg = (struct kvm_segment) {
8505 .base = 0,
8506 .limit = 0xFFFFFFFF,
8507 .type = 3,
8508 .present = 1,
8509 .s = 1,
8510 .db = 1,
8511 .g = 1
8512 };
8513 seg.selector = vmcs12->host_ds_selector;
8514 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8515 seg.selector = vmcs12->host_es_selector;
8516 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8517 seg.selector = vmcs12->host_ss_selector;
8518 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8519 seg.selector = vmcs12->host_fs_selector;
8520 seg.base = vmcs12->host_fs_base;
8521 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8522 seg.selector = vmcs12->host_gs_selector;
8523 seg.base = vmcs12->host_gs_base;
8524 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8525 seg = (struct kvm_segment) {
205befd9 8526 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8527 .limit = 0x67,
8528 .selector = vmcs12->host_tr_selector,
8529 .type = 11,
8530 .present = 1
8531 };
8532 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8533
503cd0c5
JK		 8534 kvm_set_dr(vcpu, 7, 0x400);
8535 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8536}
8537
8538/*
8539 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8540 * and modify vmcs12 to make it see what it would expect to see there if
8541 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8542 */
533558bc
JK		 8543static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8544 u32 exit_intr_info,
8545 unsigned long exit_qualification)
4704d0be
NHE		 8546{
8547 struct vcpu_vmx *vmx = to_vmx(vcpu);
8548 int cpu;
8549 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8550
5f3d5799
JK		 8551 /* trying to cancel vmlaunch/vmresume is a bug */
8552 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8553
4704d0be 8554 leave_guest_mode(vcpu);
533558bc
JK		 8555 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8556 exit_qualification);
4704d0be 8557
542060ea
JK		 8558 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8559 vmcs12->exit_qualification,
8560 vmcs12->idt_vectoring_info_field,
8561 vmcs12->vm_exit_intr_info,
8562 vmcs12->vm_exit_intr_error_code,
8563 KVM_ISA_VMX);
4704d0be
NHE		 8564
8565 cpu = get_cpu();
8566 vmx->loaded_vmcs = &vmx->vmcs01;
8567 vmx_vcpu_put(vcpu);
8568 vmx_vcpu_load(vcpu, cpu);
8569 vcpu->cpu = cpu;
8570 put_cpu();
8571
2961e876
GN		 8572 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8573 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8574 vmx_segment_cache_clear(vmx);
8575
4704d0be
NHE		 8576 /* if no vmcs02 cache requested, remove the one we used */
8577 if (VMCS02_POOL_SIZE == 0)
8578 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8579
8580 load_vmcs12_host_state(vcpu, vmcs12);
8581
27fc51b2 8582 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8583 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8584
8585 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8586 vmx->host_rsp = 0;
8587
8588 /* Unpin physical memory we referred to in vmcs02 */
8589 if (vmx->nested.apic_access_page) {
8590 nested_release_page(vmx->nested.apic_access_page);
8591 vmx->nested.apic_access_page = 0;
8592 }
8593
8594 /*
8595 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8596 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8597 * success or failure flag accordingly.
8598 */
8599 if (unlikely(vmx->fail)) {
8600 vmx->fail = 0;
8601 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8602 } else
8603 nested_vmx_succeed(vcpu);
012f83cb
AG		 8604 if (enable_shadow_vmcs)
8605 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8606
8607 /* in case we halted in L2 */
8608 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8609}
8610
42124925
JK		 8611/*
8612 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8613 */
8614static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8615{
8616 if (is_guest_mode(vcpu))
533558bc 8617 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8618 free_nested(to_vmx(vcpu));
8619}
8620
7c177938
NHE		 8621/*
8622 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8623 * 23.7 "VM-entry failures during or after loading guest state" (this also
8624 * lists the acceptable exit-reason and exit-qualification parameters).
8625 * It should only be called before L2 actually succeeded to run, and when
8626 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8627 */
8628static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8629 struct vmcs12 *vmcs12,
8630 u32 reason, unsigned long qualification)
8631{
8632 load_vmcs12_host_state(vcpu, vmcs12);
8633 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8634 vmcs12->exit_qualification = qualification;
8635 nested_vmx_succeed(vcpu);
012f83cb
AG		 8636 if (enable_shadow_vmcs)
8637 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8638}
8639
8a76d7f2
JR		 8640static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8641 struct x86_instruction_info *info,
8642 enum x86_intercept_stage stage)
8643{
8644 return X86EMUL_CONTINUE;
8645}
8646
cbdd1bea 8647static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8648 .cpu_has_kvm_support = cpu_has_kvm_support,
8649 .disabled_by_bios = vmx_disabled_by_bios,
8650 .hardware_setup = hardware_setup,
8651 .hardware_unsetup = hardware_unsetup,
002c7f7c 8652 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8653 .hardware_enable = hardware_enable,
8654 .hardware_disable = hardware_disable,
04547156 8655 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8656
8657 .vcpu_create = vmx_create_vcpu,
8658 .vcpu_free = vmx_free_vcpu,
04d2cc77 8659 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8660
04d2cc77 8661 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8662 .vcpu_load = vmx_vcpu_load,
8663 .vcpu_put = vmx_vcpu_put,
8664
c8639010 8665 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8666 .get_msr = vmx_get_msr,
8667 .set_msr = vmx_set_msr,
8668 .get_segment_base = vmx_get_segment_base,
8669 .get_segment = vmx_get_segment,
8670 .set_segment = vmx_set_segment,
2e4d2653 8671 .get_cpl = vmx_get_cpl,
6aa8b732 8672 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8673 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8674 .decache_cr3 = vmx_decache_cr3,
25c4c276 8675 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8676 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8677 .set_cr3 = vmx_set_cr3,
8678 .set_cr4 = vmx_set_cr4,
6aa8b732 8679 .set_efer = vmx_set_efer,
6aa8b732
AK		 8680 .get_idt = vmx_get_idt,
8681 .set_idt = vmx_set_idt,
8682 .get_gdt = vmx_get_gdt,
8683 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8684 .get_dr6 = vmx_get_dr6,
8685 .set_dr6 = vmx_set_dr6,
020df079 8686 .set_dr7 = vmx_set_dr7,
81908bf4 8687 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8688 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8689 .get_rflags = vmx_get_rflags,
8690 .set_rflags = vmx_set_rflags,
ebcbab4c 8691 .fpu_activate = vmx_fpu_activate,
02daab21 8692 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8693
8694 .tlb_flush = vmx_flush_tlb,
6aa8b732 8695
6aa8b732 8696 .run = vmx_vcpu_run,
6062d012 8697 .handle_exit = vmx_handle_exit,
6aa8b732 8698 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8699 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8700 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8701 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8702 .set_irq = vmx_inject_irq,
95ba8273 8703 .set_nmi = vmx_inject_nmi,
298101da 8704 .queue_exception = vmx_queue_exception,
b463a6f7 8705 .cancel_injection = vmx_cancel_injection,
78646121 8706 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8707 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8708 .get_nmi_mask = vmx_get_nmi_mask,
8709 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8710 .enable_nmi_window = enable_nmi_window,
8711 .enable_irq_window = enable_irq_window,
8712 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8713 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8714 .vm_has_apicv = vmx_vm_has_apicv,
8715 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8716 .hwapic_irr_update = vmx_hwapic_irr_update,
8717 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8718 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8719 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8720
cbc94022 8721 .set_tss_addr = vmx_set_tss_addr,
67253af5 8722 .get_tdp_level = get_ept_level,
4b12f0de 8723 .get_mt_mask = vmx_get_mt_mask,
229456fc 8724
586f9607 8725 .get_exit_info = vmx_get_exit_info,
586f9607 8726
17cc3935 8727 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8728
8729 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8730
8731 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8732 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8733
8734 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8735
8736 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8737
4051b188 8738 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8739 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8740 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8741 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8742 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8743 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8744
8745 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8746
8747 .check_intercept = vmx_check_intercept,
a547c6db 8748 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8749 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8750
8751 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8752};
8753
8754static int __init vmx_init(void)
8755{
8d14695f 8756 int r, i, msr;
26bb0981
AK		 8757
8758 rdmsrl_safe(MSR_EFER, &host_efer);
8759
8760 for (i = 0; i < NR_VMX_MSR; ++i)
8761 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8762
3e7c73e9 8763 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8764 if (!vmx_io_bitmap_a)
8765 return -ENOMEM;
8766
2106a548
GC		 8767 r = -ENOMEM;
8768
3e7c73e9 8769 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8770 if (!vmx_io_bitmap_b)
fdef3ad1 8771 goto out;
fdef3ad1 8772
5897297b 8773 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8774 if (!vmx_msr_bitmap_legacy)
25c5f225 8775 goto out1;
2106a548 8776
8d14695f
YZ		 8777 vmx_msr_bitmap_legacy_x2apic =
8778 (unsigned long *)__get_free_page(GFP_KERNEL);
8779 if (!vmx_msr_bitmap_legacy_x2apic)
8780 goto out2;
25c5f225 8781
5897297b 8782 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8783 if (!vmx_msr_bitmap_longmode)
8d14695f 8784 goto out3;
2106a548 8785
8d14695f
YZ		 8786 vmx_msr_bitmap_longmode_x2apic =
8787 (unsigned long *)__get_free_page(GFP_KERNEL);
8788 if (!vmx_msr_bitmap_longmode_x2apic)
8789 goto out4;
4607c2d7
AG		 8790 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8791 if (!vmx_vmread_bitmap)
8792 goto out5;
8793
8794 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8795 if (!vmx_vmwrite_bitmap)
8796 goto out6;
8797
8798 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8799 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8800 /* shadowed read/write fields */
8801 for (i = 0; i < max_shadow_read_write_fields; i++) {
8802 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8803 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8804 }
8805 /* shadowed read only fields */
8806 for (i = 0; i < max_shadow_read_only_fields; i++)
8807 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8808
fdef3ad1
HQ		 8809 /*
8810 * Allow direct access to the PC debug port (it is often used for I/O
8811 * delays, but the vmexits simply slow things down).
8812 */
3e7c73e9
AK		 8813 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8814 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8815
3e7c73e9 8816 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8817
5897297b
AK		 8818 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8819 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8820
2384d2b3
SY		 8821 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8822
0ee75bea
AK		 8823 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8824 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8825 if (r)
4607c2d7 8826 goto out7;
25c5f225 8827
8f536b76
ZY		 8828#ifdef CONFIG_KEXEC
8829 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8830 crash_vmclear_local_loaded_vmcss);
8831#endif
8832
5897297b
AK		 8833 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8834 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8835 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8836 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8837 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8838 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8839 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8840
8d14695f
YZ		 8841 memcpy(vmx_msr_bitmap_legacy_x2apic,
8842 vmx_msr_bitmap_legacy, PAGE_SIZE);
8843 memcpy(vmx_msr_bitmap_longmode_x2apic,
8844 vmx_msr_bitmap_longmode, PAGE_SIZE);
8845
01e439be 8846 if (enable_apicv) {
8d14695f
YZ		 8847 for (msr = 0x800; msr <= 0x8ff; msr++)
8848 vmx_disable_intercept_msr_read_x2apic(msr);
8849
8850 /* According SDM, in x2apic mode, the whole id reg is used.
8851 * But in KVM, it only use the highest eight bits. Need to
8852 * intercept it */
8853 vmx_enable_intercept_msr_read_x2apic(0x802);
8854 /* TMCCT */
8855 vmx_enable_intercept_msr_read_x2apic(0x839);
8856 /* TPR */
8857 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8858 /* EOI */
8859 vmx_disable_intercept_msr_write_x2apic(0x80b);
8860 /* SELF-IPI */
8861 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8862 }
fdef3ad1 8863
089d034e 8864 if (enable_ept) {
3f6d8c8a
XH		 8865 kvm_mmu_set_mask_ptes(0ull,
8866 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8867 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8868 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8869 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8870 kvm_enable_tdp();
8871 } else
8872 kvm_disable_tdp();
1439442c 8873
fdef3ad1
HQ		 8874 return 0;
8875
4607c2d7
AG		 8876out7:
8877 free_page((unsigned long)vmx_vmwrite_bitmap);
8878out6:
8879 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8880out5:
8881 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8882out4:
5897297b 8883 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8884out3:
8885 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8886out2:
5897297b 8887 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8888out1:
3e7c73e9 8889 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8890out:
3e7c73e9 8891 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8892 return r;
6aa8b732
AK		 8893}
8894
8895static void __exit vmx_exit(void)
8896{
8d14695f
YZ		 8897 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8898 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8899 free_page((unsigned long)vmx_msr_bitmap_legacy);
8900 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8901 free_page((unsigned long)vmx_io_bitmap_b);
8902 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8903 free_page((unsigned long)vmx_vmwrite_bitmap);
8904 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8905
8f536b76
ZY		 8906#ifdef CONFIG_KEXEC
8907 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8908 synchronize_rcu();
8909#endif
8910
cb498ea2 8911 kvm_exit();
6aa8b732
AK		 8912}
8913
8914module_init(vmx_init)
8915module_exit(vmx_exit)
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