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KVM: nVMX: Allow to disable CR3 access interception
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
3573e22c 357 gpa_t vmxon_ptr;
a9d30f33
NHE		 358
359 /* The guest-physical address of the current VMCS L1 keeps for L2 */
360 gpa_t current_vmptr;
361 /* The host-usable pointer to the above */
362 struct page *current_vmcs12_page;
363 struct vmcs12 *current_vmcs12;
8de48833 364 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 365 /*
366 * Indicates if the shadow vmcs must be updated with the
367 * data hold by vmcs12
368 */
369 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 370
371 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
372 struct list_head vmcs02_pool;
373 int vmcs02_num;
fe3ef05c 374 u64 vmcs01_tsc_offset;
644d711a
NHE		 375 /* L2 must run next, and mustn't decide to exit to L1. */
376 bool nested_run_pending;
fe3ef05c
NHE		 377 /*
378 * Guest pages referred to in vmcs02 with host-physical pointers, so
379 * we must keep them pinned while L2 runs.
380 */
381 struct page *apic_access_page;
b3897a49 382 u64 msr_ia32_feature_control;
f4124500
JK		 383
384 struct hrtimer preemption_timer;
385 bool preemption_timer_expired;
ec378aee
NHE		 386};
387
01e439be
YZ		 388#define POSTED_INTR_ON 0
389/* Posted-Interrupt Descriptor */
390struct pi_desc {
391 u32 pir[8]; /* Posted interrupt requested */
392 u32 control; /* bit 0 of control is outstanding notification bit */
393 u32 rsvd[7];
394} __aligned(64);
395
a20ed54d
YZ		 396static bool pi_test_and_set_on(struct pi_desc *pi_desc)
397{
398 return test_and_set_bit(POSTED_INTR_ON,
399 (unsigned long *)&pi_desc->control);
400}
401
402static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
403{
404 return test_and_clear_bit(POSTED_INTR_ON,
405 (unsigned long *)&pi_desc->control);
406}
407
408static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
409{
410 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
411}
412
a2fa3e9f 413struct vcpu_vmx {
fb3f0f51 414 struct kvm_vcpu vcpu;
313dbd49 415 unsigned long host_rsp;
29bd8a78 416 u8 fail;
9d58b931 417 bool nmi_known_unmasked;
51aa01d1 418 u32 exit_intr_info;
1155f76a 419 u32 idt_vectoring_info;
6de12732 420 ulong rflags;
26bb0981 421 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 422 int nmsrs;
423 int save_nmsrs;
a547c6db 424 unsigned long host_idt_base;
a2fa3e9f 425#ifdef CONFIG_X86_64
44ea2b17
AK		 426 u64 msr_host_kernel_gs_base;
427 u64 msr_guest_kernel_gs_base;
a2fa3e9f 428#endif
2961e876
GN		 429 u32 vm_entry_controls_shadow;
430 u32 vm_exit_controls_shadow;
d462b819
NHE		 431 /*
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
435 */
436 struct loaded_vmcs vmcs01;
437 struct loaded_vmcs *loaded_vmcs;
438 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 439 struct msr_autoload {
440 unsigned nr;
441 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
442 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
443 } msr_autoload;
a2fa3e9f
GH		 444 struct {
445 int loaded;
446 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 447#ifdef CONFIG_X86_64
448 u16 ds_sel, es_sel;
449#endif
152d3f2f
LV		 450 int gs_ldt_reload_needed;
451 int fs_reload_needed;
da8999d3 452 u64 msr_host_bndcfgs;
d77c26fc 453 } host_state;
9c8cba37 454 struct {
7ffd92c5 455 int vm86_active;
78ac8b47 456 ulong save_rflags;
f5f7b2fe
AK		 457 struct kvm_segment segs[8];
458 } rmode;
459 struct {
460 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 461 struct kvm_save_segment {
462 u16 selector;
463 unsigned long base;
464 u32 limit;
465 u32 ar;
f5f7b2fe 466 } seg[8];
2fb92db1 467 } segment_cache;
2384d2b3 468 int vpid;
04fa4d32 469 bool emulation_required;
3b86cd99
JK		 470
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked;
473 ktime_t entry_time;
474 s64 vnmi_blocked_time;
a0861c02 475 u32 exit_reason;
4e47c7a6
SY		 476
477 bool rdtscp_enabled;
ec378aee 478
01e439be
YZ		 479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc;
481
ec378aee
NHE		 482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested;
a2fa3e9f
GH		 484};
485
2fb92db1
AK		 486enum segment_cache_field {
487 SEG_FIELD_SEL = 0,
488 SEG_FIELD_BASE = 1,
489 SEG_FIELD_LIMIT = 2,
490 SEG_FIELD_AR = 3,
491
492 SEG_FIELD_NR = 4
493};
494
a2fa3e9f
GH		 495static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
496{
fb3f0f51 497 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 498}
499
22bd0358
NHE		 500#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
504
4607c2d7 505
fe2b201b 506static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 507 /*
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
518 */
519 VM_EXIT_REASON,
520 VM_EXIT_INTR_INFO,
521 VM_EXIT_INSTRUCTION_LEN,
522 IDT_VECTORING_INFO_FIELD,
523 IDT_VECTORING_ERROR_CODE,
524 VM_EXIT_INTR_ERROR_CODE,
525 EXIT_QUALIFICATION,
526 GUEST_LINEAR_ADDRESS,
527 GUEST_PHYSICAL_ADDRESS
528};
fe2b201b 529static int max_shadow_read_only_fields =
4607c2d7
AG		 530 ARRAY_SIZE(shadow_read_only_fields);
531
fe2b201b 532static unsigned long shadow_read_write_fields[] = {
4607c2d7
AG		 533 GUEST_RIP,
534 GUEST_RSP,
535 GUEST_CR0,
536 GUEST_CR3,
537 GUEST_CR4,
538 GUEST_INTERRUPTIBILITY_INFO,
539 GUEST_RFLAGS,
540 GUEST_CS_SELECTOR,
541 GUEST_CS_AR_BYTES,
542 GUEST_CS_LIMIT,
543 GUEST_CS_BASE,
544 GUEST_ES_BASE,
36be0b9d 545 GUEST_BNDCFGS,
4607c2d7
AG		 546 CR0_GUEST_HOST_MASK,
547 CR0_READ_SHADOW,
548 CR4_READ_SHADOW,
549 TSC_OFFSET,
550 EXCEPTION_BITMAP,
551 CPU_BASED_VM_EXEC_CONTROL,
552 VM_ENTRY_EXCEPTION_ERROR_CODE,
553 VM_ENTRY_INTR_INFO_FIELD,
554 VM_ENTRY_INSTRUCTION_LEN,
555 VM_ENTRY_EXCEPTION_ERROR_CODE,
556 HOST_FS_BASE,
557 HOST_GS_BASE,
558 HOST_FS_SELECTOR,
559 HOST_GS_SELECTOR
560};
fe2b201b 561static int max_shadow_read_write_fields =
4607c2d7
AG		 562 ARRAY_SIZE(shadow_read_write_fields);
563
772e0318 564static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 565 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
566 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
567 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
568 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
569 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
570 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
571 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
572 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
573 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
574 FIELD(HOST_ES_SELECTOR, host_es_selector),
575 FIELD(HOST_CS_SELECTOR, host_cs_selector),
576 FIELD(HOST_SS_SELECTOR, host_ss_selector),
577 FIELD(HOST_DS_SELECTOR, host_ds_selector),
578 FIELD(HOST_FS_SELECTOR, host_fs_selector),
579 FIELD(HOST_GS_SELECTOR, host_gs_selector),
580 FIELD(HOST_TR_SELECTOR, host_tr_selector),
581 FIELD64(IO_BITMAP_A, io_bitmap_a),
582 FIELD64(IO_BITMAP_B, io_bitmap_b),
583 FIELD64(MSR_BITMAP, msr_bitmap),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
587 FIELD64(TSC_OFFSET, tsc_offset),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
589 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
590 FIELD64(EPT_POINTER, ept_pointer),
591 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
592 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
593 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
594 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
595 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
597 FIELD64(GUEST_PDPTR0, guest_pdptr0),
598 FIELD64(GUEST_PDPTR1, guest_pdptr1),
599 FIELD64(GUEST_PDPTR2, guest_pdptr2),
600 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 601 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 602 FIELD64(HOST_IA32_PAT, host_ia32_pat),
603 FIELD64(HOST_IA32_EFER, host_ia32_efer),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
607 FIELD(EXCEPTION_BITMAP, exception_bitmap),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
610 FIELD(CR3_TARGET_COUNT, cr3_target_count),
611 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
612 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
614 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
619 FIELD(TPR_THRESHOLD, tpr_threshold),
620 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
621 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
622 FIELD(VM_EXIT_REASON, vm_exit_reason),
623 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
624 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
625 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
626 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
627 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
628 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
629 FIELD(GUEST_ES_LIMIT, guest_es_limit),
630 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
631 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
632 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
633 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
634 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
635 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
636 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
637 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
638 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
639 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
640 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
641 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
642 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
643 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
644 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
645 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
646 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
648 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
649 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
650 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 651 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 652 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
653 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
654 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
655 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
656 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
657 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
658 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
659 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
660 FIELD(EXIT_QUALIFICATION, exit_qualification),
661 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
662 FIELD(GUEST_CR0, guest_cr0),
663 FIELD(GUEST_CR3, guest_cr3),
664 FIELD(GUEST_CR4, guest_cr4),
665 FIELD(GUEST_ES_BASE, guest_es_base),
666 FIELD(GUEST_CS_BASE, guest_cs_base),
667 FIELD(GUEST_SS_BASE, guest_ss_base),
668 FIELD(GUEST_DS_BASE, guest_ds_base),
669 FIELD(GUEST_FS_BASE, guest_fs_base),
670 FIELD(GUEST_GS_BASE, guest_gs_base),
671 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
672 FIELD(GUEST_TR_BASE, guest_tr_base),
673 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
674 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
675 FIELD(GUEST_DR7, guest_dr7),
676 FIELD(GUEST_RSP, guest_rsp),
677 FIELD(GUEST_RIP, guest_rip),
678 FIELD(GUEST_RFLAGS, guest_rflags),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
680 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
681 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
682 FIELD(HOST_CR0, host_cr0),
683 FIELD(HOST_CR3, host_cr3),
684 FIELD(HOST_CR4, host_cr4),
685 FIELD(HOST_FS_BASE, host_fs_base),
686 FIELD(HOST_GS_BASE, host_gs_base),
687 FIELD(HOST_TR_BASE, host_tr_base),
688 FIELD(HOST_GDTR_BASE, host_gdtr_base),
689 FIELD(HOST_IDTR_BASE, host_idtr_base),
690 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
691 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
692 FIELD(HOST_RSP, host_rsp),
693 FIELD(HOST_RIP, host_rip),
694};
695static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
696
697static inline short vmcs_field_to_offset(unsigned long field)
698{
699 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
700 return -1;
701 return vmcs_field_to_offset_table[field];
702}
703
a9d30f33
NHE		 704static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
705{
706 return to_vmx(vcpu)->nested.current_vmcs12;
707}
708
709static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
710{
711 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 712 if (is_error_page(page))
a9d30f33 713 return NULL;
32cad84f 714
a9d30f33
NHE		 715 return page;
716}
717
718static void nested_release_page(struct page *page)
719{
720 kvm_release_page_dirty(page);
721}
722
723static void nested_release_page_clean(struct page *page)
724{
725 kvm_release_page_clean(page);
726}
727
bfd0a56b 728static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 729static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 730static void kvm_cpu_vmxon(u64 addr);
731static void kvm_cpu_vmxoff(void);
93c4adc7 732static bool vmx_mpx_supported(void);
776e58ea 733static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 734static void vmx_set_segment(struct kvm_vcpu *vcpu,
735 struct kvm_segment *var, int seg);
736static void vmx_get_segment(struct kvm_vcpu *vcpu,
737 struct kvm_segment *var, int seg);
d99e4152
GN		 738static bool guest_state_valid(struct kvm_vcpu *vcpu);
739static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 740static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 741static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 742static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
36be0b9d 743static bool vmx_mpx_supported(void);
75880a01 744
6aa8b732
AK		 745static DEFINE_PER_CPU(struct vmcs *, vmxarea);
746static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 747/*
748 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
749 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
750 */
751static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 752static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 753
3e7c73e9
AK		 754static unsigned long *vmx_io_bitmap_a;
755static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 756static unsigned long *vmx_msr_bitmap_legacy;
757static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 758static unsigned long *vmx_msr_bitmap_legacy_x2apic;
759static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 760static unsigned long *vmx_vmread_bitmap;
761static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 762
110312c8 763static bool cpu_has_load_ia32_efer;
8bf00a52 764static bool cpu_has_load_perf_global_ctrl;
110312c8 765
2384d2b3
SY		 766static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
767static DEFINE_SPINLOCK(vmx_vpid_lock);
768
1c3d14fe 769static struct vmcs_config {
6aa8b732
AK		 770 int size;
771 int order;
772 u32 revision_id;
1c3d14fe
YS		 773 u32 pin_based_exec_ctrl;
774 u32 cpu_based_exec_ctrl;
f78e0e2e 775 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 776 u32 vmexit_ctrl;
777 u32 vmentry_ctrl;
778} vmcs_config;
6aa8b732 779
efff9e53 780static struct vmx_capability {
d56f546d
SY		 781 u32 ept;
782 u32 vpid;
783} vmx_capability;
784
6aa8b732
AK		 785#define VMX_SEGMENT_FIELD(seg) \
786 [VCPU_SREG_##seg] = { \
787 .selector = GUEST_##seg##_SELECTOR, \
788 .base = GUEST_##seg##_BASE, \
789 .limit = GUEST_##seg##_LIMIT, \
790 .ar_bytes = GUEST_##seg##_AR_BYTES, \
791 }
792
772e0318 793static const struct kvm_vmx_segment_field {
6aa8b732
AK		 794 unsigned selector;
795 unsigned base;
796 unsigned limit;
797 unsigned ar_bytes;
798} kvm_vmx_segment_fields[] = {
799 VMX_SEGMENT_FIELD(CS),
800 VMX_SEGMENT_FIELD(DS),
801 VMX_SEGMENT_FIELD(ES),
802 VMX_SEGMENT_FIELD(FS),
803 VMX_SEGMENT_FIELD(GS),
804 VMX_SEGMENT_FIELD(SS),
805 VMX_SEGMENT_FIELD(TR),
806 VMX_SEGMENT_FIELD(LDTR),
807};
808
26bb0981
AK		 809static u64 host_efer;
810
6de4f3ad
AK		 811static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
812
4d56c8a7 813/*
8c06585d 814 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 815 * away by decrementing the array size.
816 */
6aa8b732 817static const u32 vmx_msr_index[] = {
05b3e0c2 818#ifdef CONFIG_X86_64
44ea2b17 819 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 820#endif
8c06585d 821 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 822};
9d8f549d 823#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 824
31299944 825static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 826{
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
828 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 829 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 830}
831
31299944 832static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 833{
834 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
835 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 836 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 837}
838
31299944 839static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 843 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 844}
845
31299944 846static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 847{
848 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
849 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
850}
851
31299944 852static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 853{
854 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
855 INTR_INFO_VALID_MASK)) ==
856 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
857}
858
31299944 859static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 860{
04547156 861 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 862}
863
31299944 864static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 865{
04547156 866 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 867}
868
31299944 869static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 870{
04547156 871 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 872}
873
31299944 874static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 875{
04547156
SY		 876 return vmcs_config.cpu_based_exec_ctrl &
877 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 878}
879
774ead3a 880static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 881{
04547156
SY		 882 return vmcs_config.cpu_based_2nd_exec_ctrl &
883 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
884}
885
8d14695f
YZ		 886static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
887{
888 return vmcs_config.cpu_based_2nd_exec_ctrl &
889 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
890}
891
83d4c286
YZ		 892static inline bool cpu_has_vmx_apic_register_virt(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_APIC_REGISTER_VIRT;
896}
897
c7c9c56c
YZ		 898static inline bool cpu_has_vmx_virtual_intr_delivery(void)
899{
900 return vmcs_config.cpu_based_2nd_exec_ctrl &
901 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
902}
903
01e439be
YZ		 904static inline bool cpu_has_vmx_posted_intr(void)
905{
906 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
907}
908
909static inline bool cpu_has_vmx_apicv(void)
910{
911 return cpu_has_vmx_apic_register_virt() &&
912 cpu_has_vmx_virtual_intr_delivery() &&
913 cpu_has_vmx_posted_intr();
914}
915
04547156
SY		 916static inline bool cpu_has_vmx_flexpriority(void)
917{
918 return cpu_has_vmx_tpr_shadow() &&
919 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 920}
921
e799794e
MT		 922static inline bool cpu_has_vmx_ept_execute_only(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 925}
926
927static inline bool cpu_has_vmx_eptp_uncacheable(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 930}
931
932static inline bool cpu_has_vmx_eptp_writeback(void)
933{
31299944 934 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 935}
936
937static inline bool cpu_has_vmx_ept_2m_page(void)
938{
31299944 939 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 940}
941
878403b7
SY		 942static inline bool cpu_has_vmx_ept_1g_page(void)
943{
31299944 944 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 945}
946
4bc9b982
SY		 947static inline bool cpu_has_vmx_ept_4levels(void)
948{
949 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
950}
951
83c3a331
XH		 952static inline bool cpu_has_vmx_ept_ad_bits(void)
953{
954 return vmx_capability.ept & VMX_EPT_AD_BIT;
955}
956
31299944 957static inline bool cpu_has_vmx_invept_context(void)
d56f546d 958{
31299944 959 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 960}
961
31299944 962static inline bool cpu_has_vmx_invept_global(void)
d56f546d 963{
31299944 964 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 965}
966
518c8aee
GJ		 967static inline bool cpu_has_vmx_invvpid_single(void)
968{
969 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
970}
971
b9d762fa
GJ		 972static inline bool cpu_has_vmx_invvpid_global(void)
973{
974 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
975}
976
31299944 977static inline bool cpu_has_vmx_ept(void)
d56f546d 978{
04547156
SY		 979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 981}
982
31299944 983static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 984{
985 return vmcs_config.cpu_based_2nd_exec_ctrl &
986 SECONDARY_EXEC_UNRESTRICTED_GUEST;
987}
988
31299944 989static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 990{
991 return vmcs_config.cpu_based_2nd_exec_ctrl &
992 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
993}
994
31299944 995static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 996{
6d3e435e 997 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 998}
999
31299944 1000static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1001{
04547156
SY		 1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1004}
1005
31299944 1006static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1007{
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_RDTSCP;
1010}
1011
ad756a16
MJ		 1012static inline bool cpu_has_vmx_invpcid(void)
1013{
1014 return vmcs_config.cpu_based_2nd_exec_ctrl &
1015 SECONDARY_EXEC_ENABLE_INVPCID;
1016}
1017
31299944 1018static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1019{
1020 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021}
1022
f5f48ee1
SY		 1023static inline bool cpu_has_vmx_wbinvd_exit(void)
1024{
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_WBINVD_EXITING;
1027}
1028
abc4fc58
AG		 1029static inline bool cpu_has_vmx_shadow_vmcs(void)
1030{
1031 u64 vmx_msr;
1032 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033 /* check if the cpu supports writing r/o exit information fields */
1034 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035 return false;
1036
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_SHADOW_VMCS;
1039}
1040
04547156
SY		 1041static inline bool report_flexpriority(void)
1042{
1043 return flexpriority_enabled;
1044}
1045
fe3ef05c
NHE		 1046static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047{
1048 return vmcs12->cpu_based_vm_exec_control & bit;
1049}
1050
1051static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052{
1053 return (vmcs12->cpu_based_vm_exec_control &
1054 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055 (vmcs12->secondary_vm_exec_control & bit);
1056}
1057
f5c4368f 1058static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1059{
1060 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061}
1062
f4124500
JK		 1063static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064{
1065 return vmcs12->pin_based_vm_exec_control &
1066 PIN_BASED_VMX_PREEMPTION_TIMER;
1067}
1068
155a97a3
NHE		 1069static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070{
1071 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072}
1073
644d711a
NHE		 1074static inline bool is_exception(u32 intr_info)
1075{
1076 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078}
1079
533558bc
JK		 1080static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081 u32 exit_intr_info,
1082 unsigned long exit_qualification);
7c177938
NHE		 1083static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084 struct vmcs12 *vmcs12,
1085 u32 reason, unsigned long qualification);
1086
8b9cf98c 1087static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1088{
1089 int i;
1090
a2fa3e9f 1091 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1092 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1093 return i;
1094 return -1;
1095}
1096
2384d2b3
SY		 1097static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098{
1099 struct {
1100 u64 vpid : 16;
1101 u64 rsvd : 48;
1102 u64 gva;
1103 } operand = { vpid, 0, gva };
1104
4ecac3fd 1105 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1106 /* CF==1 or ZF==1 --> rc = -1 */
1107 "; ja 1f ; ud2 ; 1:"
1108 : : "a"(&operand), "c"(ext) : "cc", "memory");
1109}
1110
1439442c
SY		 1111static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112{
1113 struct {
1114 u64 eptp, gpa;
1115 } operand = {eptp, gpa};
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1118 /* CF==1 or ZF==1 --> rc = -1 */
1119 "; ja 1f ; ud2 ; 1:\n"
1120 : : "a" (&operand), "c" (ext) : "cc", "memory");
1121}
1122
26bb0981 1123static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1124{
1125 int i;
1126
8b9cf98c 1127 i = __find_msr_index(vmx, msr);
a75beee6 1128 if (i >= 0)
a2fa3e9f 1129 return &vmx->guest_msrs[i];
8b6d44c7 1130 return NULL;
7725f0ba
AK		 1131}
1132
6aa8b732
AK		 1133static void vmcs_clear(struct vmcs *vmcs)
1134{
1135 u64 phys_addr = __pa(vmcs);
1136 u8 error;
1137
4ecac3fd 1138 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1139 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1140 : "cc", "memory");
1141 if (error)
1142 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143 vmcs, phys_addr);
1144}
1145
d462b819
NHE		 1146static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147{
1148 vmcs_clear(loaded_vmcs->vmcs);
1149 loaded_vmcs->cpu = -1;
1150 loaded_vmcs->launched = 0;
1151}
1152
7725b894
DX		 1153static void vmcs_load(struct vmcs *vmcs)
1154{
1155 u64 phys_addr = __pa(vmcs);
1156 u8 error;
1157
1158 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1159 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1160 : "cc", "memory");
1161 if (error)
2844d849 1162 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1163 vmcs, phys_addr);
1164}
1165
8f536b76
ZY		 1166#ifdef CONFIG_KEXEC
1167/*
1168 * This bitmap is used to indicate whether the vmclear
1169 * operation is enabled on all cpus. All disabled by
1170 * default.
1171 */
1172static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174static inline void crash_enable_local_vmclear(int cpu)
1175{
1176 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177}
1178
1179static inline void crash_disable_local_vmclear(int cpu)
1180{
1181 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182}
1183
1184static inline int crash_local_vmclear_enabled(int cpu)
1185{
1186 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187}
1188
1189static void crash_vmclear_local_loaded_vmcss(void)
1190{
1191 int cpu = raw_smp_processor_id();
1192 struct loaded_vmcs *v;
1193
1194 if (!crash_local_vmclear_enabled(cpu))
1195 return;
1196
1197 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198 loaded_vmcss_on_cpu_link)
1199 vmcs_clear(v->vmcs);
1200}
1201#else
1202static inline void crash_enable_local_vmclear(int cpu) { }
1203static inline void crash_disable_local_vmclear(int cpu) { }
1204#endif /* CONFIG_KEXEC */
1205
d462b819 1206static void __loaded_vmcs_clear(void *arg)
6aa8b732 1207{
d462b819 1208 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1209 int cpu = raw_smp_processor_id();
6aa8b732 1210
d462b819
NHE		 1211 if (loaded_vmcs->cpu != cpu)
1212 return; /* vcpu migration can race with cpu offline */
1213 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1214 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1215 crash_disable_local_vmclear(cpu);
d462b819 1216 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1217
1218 /*
1219 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220 * is before setting loaded_vmcs->vcpu to -1 which is done in
1221 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222 * then adds the vmcs into percpu list before it is deleted.
1223 */
1224 smp_wmb();
1225
d462b819 1226 loaded_vmcs_init(loaded_vmcs);
8f536b76 1227 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1228}
1229
d462b819 1230static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1231{
e6c7d321
XG		 1232 int cpu = loaded_vmcs->cpu;
1233
1234 if (cpu != -1)
1235 smp_call_function_single(cpu,
1236 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1237}
1238
1760dd49 1239static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1240{
1241 if (vmx->vpid == 0)
1242 return;
1243
518c8aee
GJ		 1244 if (cpu_has_vmx_invvpid_single())
1245 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1246}
1247
b9d762fa
GJ		 1248static inline void vpid_sync_vcpu_global(void)
1249{
1250 if (cpu_has_vmx_invvpid_global())
1251 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252}
1253
1254static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255{
1256 if (cpu_has_vmx_invvpid_single())
1760dd49 1257 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1258 else
1259 vpid_sync_vcpu_global();
1260}
1261
1439442c
SY		 1262static inline void ept_sync_global(void)
1263{
1264 if (cpu_has_vmx_invept_global())
1265 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266}
1267
1268static inline void ept_sync_context(u64 eptp)
1269{
089d034e 1270 if (enable_ept) {
1439442c
SY		 1271 if (cpu_has_vmx_invept_context())
1272 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273 else
1274 ept_sync_global();
1275 }
1276}
1277
96304217 1278static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1279{
5e520e62 1280 unsigned long value;
6aa8b732 1281
5e520e62
AK		 1282 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1284 return value;
1285}
1286
96304217 1287static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1288{
1289 return vmcs_readl(field);
1290}
1291
96304217 1292static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1293{
1294 return vmcs_readl(field);
1295}
1296
96304217 1297static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1298{
05b3e0c2 1299#ifdef CONFIG_X86_64
6aa8b732
AK		 1300 return vmcs_readl(field);
1301#else
1302 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303#endif
1304}
1305
e52de1b8
AK		 1306static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307{
1308 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310 dump_stack();
1311}
1312
6aa8b732
AK		 1313static void vmcs_writel(unsigned long field, unsigned long value)
1314{
1315 u8 error;
1316
4ecac3fd 1317 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1318 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1319 if (unlikely(error))
1320 vmwrite_error(field, value);
6aa8b732
AK		 1321}
1322
1323static void vmcs_write16(unsigned long field, u16 value)
1324{
1325 vmcs_writel(field, value);
1326}
1327
1328static void vmcs_write32(unsigned long field, u32 value)
1329{
1330 vmcs_writel(field, value);
1331}
1332
1333static void vmcs_write64(unsigned long field, u64 value)
1334{
6aa8b732 1335 vmcs_writel(field, value);
7682f2d0 1336#ifndef CONFIG_X86_64
6aa8b732
AK		 1337 asm volatile ("");
1338 vmcs_writel(field+1, value >> 32);
1339#endif
1340}
1341
2ab455cc
AL		 1342static void vmcs_clear_bits(unsigned long field, u32 mask)
1343{
1344 vmcs_writel(field, vmcs_readl(field) & ~mask);
1345}
1346
1347static void vmcs_set_bits(unsigned long field, u32 mask)
1348{
1349 vmcs_writel(field, vmcs_readl(field) | mask);
1350}
1351
2961e876
GN		 1352static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353{
1354 vmcs_write32(VM_ENTRY_CONTROLS, val);
1355 vmx->vm_entry_controls_shadow = val;
1356}
1357
1358static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359{
1360 if (vmx->vm_entry_controls_shadow != val)
1361 vm_entry_controls_init(vmx, val);
1362}
1363
1364static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365{
1366 return vmx->vm_entry_controls_shadow;
1367}
1368
1369
1370static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371{
1372 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373}
1374
1375static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376{
1377 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378}
1379
1380static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381{
1382 vmcs_write32(VM_EXIT_CONTROLS, val);
1383 vmx->vm_exit_controls_shadow = val;
1384}
1385
1386static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387{
1388 if (vmx->vm_exit_controls_shadow != val)
1389 vm_exit_controls_init(vmx, val);
1390}
1391
1392static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393{
1394 return vmx->vm_exit_controls_shadow;
1395}
1396
1397
1398static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399{
1400 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401}
1402
1403static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404{
1405 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406}
1407
2fb92db1
AK		 1408static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409{
1410 vmx->segment_cache.bitmask = 0;
1411}
1412
1413static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414 unsigned field)
1415{
1416 bool ret;
1417 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421 vmx->segment_cache.bitmask = 0;
1422 }
1423 ret = vmx->segment_cache.bitmask & mask;
1424 vmx->segment_cache.bitmask |= mask;
1425 return ret;
1426}
1427
1428static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429{
1430 u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434 return *p;
1435}
1436
1437static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438{
1439 ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443 return *p;
1444}
1445
1446static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447{
1448 u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452 return *p;
1453}
1454
1455static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456{
1457 u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461 return *p;
1462}
1463
abd3f2d6
AK		 1464static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465{
1466 u32 eb;
1467
fd7373cc
JK		 1468 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470 if ((vcpu->guest_debug &
1471 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473 eb |= 1u << BP_VECTOR;
7ffd92c5 1474 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1475 eb = ~0;
089d034e 1476 if (enable_ept)
1439442c 1477 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1478 if (vcpu->fpu_active)
1479 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1480
1481 /* When we are running a nested L2 guest and L1 specified for it a
1482 * certain exception bitmap, we must trap the same exceptions and pass
1483 * them to L1. When running L2, we will only handle the exceptions
1484 * specified above if L1 did not want them.
1485 */
1486 if (is_guest_mode(vcpu))
1487 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
abd3f2d6
AK		 1489 vmcs_write32(EXCEPTION_BITMAP, eb);
1490}
1491
2961e876
GN		 1492static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493 unsigned long entry, unsigned long exit)
8bf00a52 1494{
2961e876
GN		 1495 vm_entry_controls_clearbit(vmx, entry);
1496 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1497}
1498
61d2ef2c
AK		 1499static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500{
1501 unsigned i;
1502 struct msr_autoload *m = &vmx->msr_autoload;
1503
8bf00a52
GN		 1504 switch (msr) {
1505 case MSR_EFER:
1506 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1507 clear_atomic_switch_msr_special(vmx,
1508 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1509 VM_EXIT_LOAD_IA32_EFER);
1510 return;
1511 }
1512 break;
1513 case MSR_CORE_PERF_GLOBAL_CTRL:
1514 if (cpu_has_load_perf_global_ctrl) {
2961e876 1515 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1516 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518 return;
1519 }
1520 break;
110312c8
AK		 1521 }
1522
61d2ef2c
AK		 1523 for (i = 0; i < m->nr; ++i)
1524 if (m->guest[i].index == msr)
1525 break;
1526
1527 if (i == m->nr)
1528 return;
1529 --m->nr;
1530 m->guest[i] = m->guest[m->nr];
1531 m->host[i] = m->host[m->nr];
1532 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534}
1535
2961e876
GN		 1536static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537 unsigned long entry, unsigned long exit,
1538 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539 u64 guest_val, u64 host_val)
8bf00a52
GN		 1540{
1541 vmcs_write64(guest_val_vmcs, guest_val);
1542 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1543 vm_entry_controls_setbit(vmx, entry);
1544 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1545}
1546
61d2ef2c
AK		 1547static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548 u64 guest_val, u64 host_val)
1549{
1550 unsigned i;
1551 struct msr_autoload *m = &vmx->msr_autoload;
1552
8bf00a52
GN		 1553 switch (msr) {
1554 case MSR_EFER:
1555 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1556 add_atomic_switch_msr_special(vmx,
1557 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1558 VM_EXIT_LOAD_IA32_EFER,
1559 GUEST_IA32_EFER,
1560 HOST_IA32_EFER,
1561 guest_val, host_val);
1562 return;
1563 }
1564 break;
1565 case MSR_CORE_PERF_GLOBAL_CTRL:
1566 if (cpu_has_load_perf_global_ctrl) {
2961e876 1567 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1568 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570 GUEST_IA32_PERF_GLOBAL_CTRL,
1571 HOST_IA32_PERF_GLOBAL_CTRL,
1572 guest_val, host_val);
1573 return;
1574 }
1575 break;
110312c8
AK		 1576 }
1577
61d2ef2c
AK		 1578 for (i = 0; i < m->nr; ++i)
1579 if (m->guest[i].index == msr)
1580 break;
1581
e7fc6f93 1582 if (i == NR_AUTOLOAD_MSRS) {
60266204 1583 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1584 "Can't add msr %x\n", msr);
1585 return;
1586 } else if (i == m->nr) {
61d2ef2c
AK		 1587 ++m->nr;
1588 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590 }
1591
1592 m->guest[i].index = msr;
1593 m->guest[i].value = guest_val;
1594 m->host[i].index = msr;
1595 m->host[i].value = host_val;
1596}
1597
33ed6329
AK		 1598static void reload_tss(void)
1599{
33ed6329
AK		 1600 /*
1601 * VT restores TR but not its size. Useless.
1602 */
d359192f 1603 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1604 struct desc_struct *descs;
33ed6329 1605
d359192f 1606 descs = (void *)gdt->address;
33ed6329
AK		 1607 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608 load_TR_desc();
33ed6329
AK		 1609}
1610
92c0d900 1611static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1612{
3a34a881 1613 u64 guest_efer;
51c6cf66
AK		 1614 u64 ignore_bits;
1615
f6801dff 1616 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1617
51c6cf66 1618 /*
0fa06071 1619 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1620 * outside long mode
1621 */
1622 ignore_bits = EFER_NX | EFER_SCE;
1623#ifdef CONFIG_X86_64
1624 ignore_bits |= EFER_LMA | EFER_LME;
1625 /* SCE is meaningful only in long mode on Intel */
1626 if (guest_efer & EFER_LMA)
1627 ignore_bits &= ~(u64)EFER_SCE;
1628#endif
51c6cf66
AK		 1629 guest_efer &= ~ignore_bits;
1630 guest_efer |= host_efer & ignore_bits;
26bb0981 1631 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1632 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1633
1634 clear_atomic_switch_msr(vmx, MSR_EFER);
1635 /* On ept, can't emulate nx, and must switch nx atomically */
1636 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637 guest_efer = vmx->vcpu.arch.efer;
1638 if (!(guest_efer & EFER_LMA))
1639 guest_efer &= ~EFER_LME;
1640 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641 return false;
1642 }
1643
26bb0981 1644 return true;
51c6cf66
AK		 1645}
1646
2d49ec72
GN		 1647static unsigned long segment_base(u16 selector)
1648{
d359192f 1649 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1650 struct desc_struct *d;
1651 unsigned long table_base;
1652 unsigned long v;
1653
1654 if (!(selector & ~3))
1655 return 0;
1656
d359192f 1657 table_base = gdt->address;
2d49ec72
GN		 1658
1659 if (selector & 4) { /* from ldt */
1660 u16 ldt_selector = kvm_read_ldt();
1661
1662 if (!(ldt_selector & ~3))
1663 return 0;
1664
1665 table_base = segment_base(ldt_selector);
1666 }
1667 d = (struct desc_struct *)(table_base + (selector & ~7));
1668 v = get_desc_base(d);
1669#ifdef CONFIG_X86_64
1670 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672#endif
1673 return v;
1674}
1675
1676static inline unsigned long kvm_read_tr_base(void)
1677{
1678 u16 tr;
1679 asm("str %0" : "=g"(tr));
1680 return segment_base(tr);
1681}
1682
04d2cc77 1683static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1684{
04d2cc77 1685 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1686 int i;
04d2cc77 1687
a2fa3e9f 1688 if (vmx->host_state.loaded)
33ed6329
AK		 1689 return;
1690
a2fa3e9f 1691 vmx->host_state.loaded = 1;
33ed6329
AK		 1692 /*
1693 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1694 * allow segment selectors with cpl > 0 or ti == 1.
1695 */
d6e88aec 1696 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1697 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1698 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1699 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1700 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1701 vmx->host_state.fs_reload_needed = 0;
1702 } else {
33ed6329 1703 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1704 vmx->host_state.fs_reload_needed = 1;
33ed6329 1705 }
9581d442 1706 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1707 if (!(vmx->host_state.gs_sel & 7))
1708 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1709 else {
1710 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1711 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1712 }
1713
b2da15ac
AK		 1714#ifdef CONFIG_X86_64
1715 savesegment(ds, vmx->host_state.ds_sel);
1716 savesegment(es, vmx->host_state.es_sel);
1717#endif
1718
33ed6329
AK		 1719#ifdef CONFIG_X86_64
1720 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722#else
a2fa3e9f
GH		 1723 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1725#endif
707c0874
AK		 1726
1727#ifdef CONFIG_X86_64
c8770e7b
AK		 1728 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729 if (is_long_mode(&vmx->vcpu))
44ea2b17 1730 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1731#endif
da8999d3
LJ		 1732 if (boot_cpu_has(X86_FEATURE_MPX))
1733 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1734 for (i = 0; i < vmx->save_nmsrs; ++i)
1735 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1736 vmx->guest_msrs[i].data,
1737 vmx->guest_msrs[i].mask);
33ed6329
AK		 1738}
1739
a9b21b62 1740static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1741{
a2fa3e9f 1742 if (!vmx->host_state.loaded)
33ed6329
AK		 1743 return;
1744
e1beb1d3 1745 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1746 vmx->host_state.loaded = 0;
c8770e7b
AK		 1747#ifdef CONFIG_X86_64
1748 if (is_long_mode(&vmx->vcpu))
1749 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750#endif
152d3f2f 1751 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1752 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1753#ifdef CONFIG_X86_64
9581d442 1754 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1755#else
1756 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1757#endif
33ed6329 1758 }
0a77fe4c
AK		 1759 if (vmx->host_state.fs_reload_needed)
1760 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1761#ifdef CONFIG_X86_64
1762 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763 loadsegment(ds, vmx->host_state.ds_sel);
1764 loadsegment(es, vmx->host_state.es_sel);
1765 }
b2da15ac 1766#endif
152d3f2f 1767 reload_tss();
44ea2b17 1768#ifdef CONFIG_X86_64
c8770e7b 1769 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1770#endif
da8999d3
LJ		 1771 if (vmx->host_state.msr_host_bndcfgs)
1772 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1773 /*
1774 * If the FPU is not active (through the host task or
1775 * the guest vcpu), then restore the cr0.TS bit.
1776 */
1777 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778 stts();
3444d7da 1779 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1780}
1781
a9b21b62
AK		 1782static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783{
1784 preempt_disable();
1785 __vmx_load_host_state(vmx);
1786 preempt_enable();
1787}
1788
6aa8b732
AK		 1789/*
1790 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791 * vcpu mutex is already taken.
1792 */
15ad7146 1793static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1794{
a2fa3e9f 1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1796 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1797
4610c9cc
DX		 1798 if (!vmm_exclusive)
1799 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1800 else if (vmx->loaded_vmcs->cpu != cpu)
1801 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1802
d462b819
NHE		 1803 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1806 }
1807
d462b819 1808 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1809 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1810 unsigned long sysenter_esp;
1811
a8eeb04a 1812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1813 local_irq_disable();
8f536b76 1814 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1815
1816 /*
1817 * Read loaded_vmcs->cpu should be before fetching
1818 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819 * See the comments in __loaded_vmcs_clear().
1820 */
1821 smp_rmb();
1822
d462b819
NHE		 1823 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1825 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1826 local_irq_enable();
1827
6aa8b732
AK		 1828 /*
1829 * Linux uses per-cpu TSS and GDT, so set these when switching
1830 * processors.
1831 */
d6e88aec 1832 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1833 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1834
1835 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1837 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1838 }
6aa8b732
AK		 1839}
1840
1841static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842{
a9b21b62 1843 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1844 if (!vmm_exclusive) {
d462b819
NHE		 1845 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846 vcpu->cpu = -1;
4610c9cc
DX		 1847 kvm_cpu_vmxoff();
1848 }
6aa8b732
AK		 1849}
1850
5fd86fcf
AK		 1851static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852{
81231c69
AK		 1853 ulong cr0;
1854
5fd86fcf
AK		 1855 if (vcpu->fpu_active)
1856 return;
1857 vcpu->fpu_active = 1;
81231c69
AK		 1858 cr0 = vmcs_readl(GUEST_CR0);
1859 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1862 update_exception_bitmap(vcpu);
edcafe3c 1863 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1864 if (is_guest_mode(vcpu))
1865 vcpu->arch.cr0_guest_owned_bits &=
1866 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1867 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1868}
1869
edcafe3c
AK		 1870static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
fe3ef05c
NHE		 1872/*
1873 * Return the cr0 value that a nested guest would read. This is a combination
1874 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875 * its hypervisor (cr0_read_shadow).
1876 */
1877static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878{
1879 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881}
1882static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883{
1884 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886}
1887
5fd86fcf
AK		 1888static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889{
36cf24e0
NHE		 1890 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891 * set this *before* calling this function.
1892 */
edcafe3c 1893 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1894 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1895 update_exception_bitmap(vcpu);
edcafe3c
AK		 1896 vcpu->arch.cr0_guest_owned_bits = 0;
1897 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1898 if (is_guest_mode(vcpu)) {
1899 /*
1900 * L1's specified read shadow might not contain the TS bit,
1901 * so now that we turned on shadowing of this bit, we need to
1902 * set this bit of the shadow. Like in nested_vmx_run we need
1903 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904 * up-to-date here because we just decached cr0.TS (and we'll
1905 * only update vmcs12->guest_cr0 on nested exit).
1906 */
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909 (vcpu->arch.cr0 & X86_CR0_TS);
1910 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911 } else
1912 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1913}
1914
6aa8b732
AK		 1915static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916{
78ac8b47 1917 unsigned long rflags, save_rflags;
345dcaa8 1918
6de12732
AK		 1919 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921 rflags = vmcs_readl(GUEST_RFLAGS);
1922 if (to_vmx(vcpu)->rmode.vm86_active) {
1923 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926 }
1927 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1928 }
6de12732 1929 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1930}
1931
1932static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933{
6de12732
AK		 1934 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1936 if (to_vmx(vcpu)->rmode.vm86_active) {
1937 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1938 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1939 }
6aa8b732
AK		 1940 vmcs_writel(GUEST_RFLAGS, rflags);
1941}
1942
2809f5d2
GC		 1943static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944{
1945 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946 int ret = 0;
1947
1948 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1949 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1950 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1951 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1952
1953 return ret & mask;
1954}
1955
1956static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957{
1958 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959 u32 interruptibility = interruptibility_old;
1960
1961 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
48005f64 1963 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1964 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1965 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1966 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968 if ((interruptibility != interruptibility_old))
1969 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970}
1971
6aa8b732
AK		 1972static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973{
1974 unsigned long rip;
6aa8b732 1975
5fdbf976 1976 rip = kvm_rip_read(vcpu);
6aa8b732 1977 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1978 kvm_rip_write(vcpu, rip);
6aa8b732 1979
2809f5d2
GC		 1980 /* skipping an emulated instruction also counts */
1981 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1982}
1983
0b6ac343
NHE		 1984/*
1985 * KVM wants to inject page-faults which it got to the guest. This function
1986 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1987 */
e011c663 1988static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1989{
1990 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
e011c663 1992 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1993 return 0;
1994
533558bc
JK		 1995 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996 vmcs_read32(VM_EXIT_INTR_INFO),
1997 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1998 return 1;
1999}
2000
298101da 2001static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2002 bool has_error_code, u32 error_code,
2003 bool reinject)
298101da 2004{
77ab6db0 2005 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2006 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2007
e011c663
GN		 2008 if (!reinject && is_guest_mode(vcpu) &&
2009 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2010 return;
2011
8ab2d2e2 2012 if (has_error_code) {
77ab6db0 2013 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2014 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015 }
77ab6db0 2016
7ffd92c5 2017 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2018 int inc_eip = 0;
2019 if (kvm_exception_is_soft(nr))
2020 inc_eip = vcpu->arch.event_exit_inst_len;
2021 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2023 return;
2024 }
2025
66fd3f7f
GN		 2026 if (kvm_exception_is_soft(nr)) {
2027 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2029 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030 } else
2031 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2034}
2035
4e47c7a6
SY		 2036static bool vmx_rdtscp_supported(void)
2037{
2038 return cpu_has_vmx_rdtscp();
2039}
2040
ad756a16
MJ		 2041static bool vmx_invpcid_supported(void)
2042{
2043 return cpu_has_vmx_invpcid() && enable_ept;
2044}
2045
a75beee6
ED		 2046/*
2047 * Swap MSR entry in host/guest MSR entry array.
2048 */
8b9cf98c 2049static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2050{
26bb0981 2051 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2052
2053 tmp = vmx->guest_msrs[to];
2054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2056}
2057
8d14695f
YZ		 2058static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059{
2060 unsigned long *msr_bitmap;
2061
2062 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063 if (is_long_mode(vcpu))
2064 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065 else
2066 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067 } else {
2068 if (is_long_mode(vcpu))
2069 msr_bitmap = vmx_msr_bitmap_longmode;
2070 else
2071 msr_bitmap = vmx_msr_bitmap_legacy;
2072 }
2073
2074 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075}
2076
e38aea3e
AK		 2077/*
2078 * Set up the vmcs to automatically save and restore system
2079 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2080 * mode, as fiddling with msrs is very expensive.
2081 */
8b9cf98c 2082static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2083{
26bb0981 2084 int save_nmsrs, index;
e38aea3e 2085
a75beee6
ED		 2086 save_nmsrs = 0;
2087#ifdef CONFIG_X86_64
8b9cf98c 2088 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2089 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2090 if (index >= 0)
8b9cf98c
RR		 2091 move_msr_up(vmx, index, save_nmsrs++);
2092 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2093 if (index >= 0)
8b9cf98c
RR		 2094 move_msr_up(vmx, index, save_nmsrs++);
2095 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2096 if (index >= 0)
8b9cf98c 2097 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2098 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099 if (index >= 0 && vmx->rdtscp_enabled)
2100 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2101 /*
8c06585d 2102 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2103 * if efer.sce is enabled.
2104 */
8c06585d 2105 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2106 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2107 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2108 }
2109#endif
92c0d900
AK		 2110 index = __find_msr_index(vmx, MSR_EFER);
2111 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2112 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2113
26bb0981 2114 vmx->save_nmsrs = save_nmsrs;
5897297b 2115
8d14695f
YZ		 2116 if (cpu_has_vmx_msr_bitmap())
2117 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2118}
2119
6aa8b732
AK		 2120/*
2121 * reads and returns guest's timestamp counter "register"
2122 * guest_tsc = host_tsc + tsc_offset -- 21.3
2123 */
2124static u64 guest_read_tsc(void)
2125{
2126 u64 host_tsc, tsc_offset;
2127
2128 rdtscll(host_tsc);
2129 tsc_offset = vmcs_read64(TSC_OFFSET);
2130 return host_tsc + tsc_offset;
2131}
2132
d5c1785d
NHE		 2133/*
2134 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135 * counter, even if a nested guest (L2) is currently running.
2136 */
886b470c 2137u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2138{
886b470c 2139 u64 tsc_offset;
d5c1785d 2140
d5c1785d
NHE		 2141 tsc_offset = is_guest_mode(vcpu) ?
2142 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143 vmcs_read64(TSC_OFFSET);
2144 return host_tsc + tsc_offset;
2145}
2146
4051b188 2147/*
cc578287
ZA		 2148 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2149 * software catchup for faster rates on slower CPUs.
4051b188 2150 */
cc578287 2151static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2152{
cc578287
ZA		 2153 if (!scale)
2154 return;
2155
2156 if (user_tsc_khz > tsc_khz) {
2157 vcpu->arch.tsc_catchup = 1;
2158 vcpu->arch.tsc_always_catchup = 1;
2159 } else
2160 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2161}
2162
ba904635
WA		 2163static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164{
2165 return vmcs_read64(TSC_OFFSET);
2166}
2167
6aa8b732 2168/*
99e3e30a 2169 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2170 */
99e3e30a 2171static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2172{
27fc51b2 2173 if (is_guest_mode(vcpu)) {
7991825b 2174 /*
27fc51b2
NHE		 2175 * We're here if L1 chose not to trap WRMSR to TSC. According
2176 * to the spec, this should set L1's TSC; The offset that L1
2177 * set for L2 remains unchanged, and still needs to be added
2178 * to the newly set TSC to get L2's TSC.
7991825b 2179 */
27fc51b2
NHE		 2180 struct vmcs12 *vmcs12;
2181 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182 /* recalculate vmcs02.TSC_OFFSET: */
2183 vmcs12 = get_vmcs12(vcpu);
2184 vmcs_write64(TSC_OFFSET, offset +
2185 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186 vmcs12->tsc_offset : 0));
2187 } else {
489223ed
YY		 2188 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2190 vmcs_write64(TSC_OFFSET, offset);
2191 }
6aa8b732
AK		 2192}
2193
f1e2b260 2194static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2195{
2196 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2197
e48672fa 2198 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2199 if (is_guest_mode(vcpu)) {
2200 /* Even when running L2, the adjustment needs to apply to L1 */
2201 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2202 } else
2203 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204 offset + adjustment);
e48672fa
ZA		 2205}
2206
857e4099
JR		 2207static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208{
2209 return target_tsc - native_read_tsc();
2210}
2211
801d3424
NHE		 2212static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213{
2214 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216}
2217
2218/*
2219 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221 * all guests if the "nested" module option is off, and can also be disabled
2222 * for a single guest by disabling its VMX cpuid bit.
2223 */
2224static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225{
2226 return nested && guest_cpuid_has_vmx(vcpu);
2227}
2228
b87a51ae
NHE		 2229/*
2230 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231 * returned for the various VMX controls MSRs when nested VMX is enabled.
2232 * The same values should also be used to verify that vmcs12 control fields are
2233 * valid during nested entry from L1 to L2.
2234 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236 * bit in the high half is on if the corresponding bit in the control field
2237 * may be on. See also vmx_control_verify().
2238 * TODO: allow these variables to be modified (downgraded) by module options
2239 * or other means.
2240 */
2241static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2242static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2243static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2244static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2245static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2246static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2247static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2248static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2249static __init void nested_vmx_setup_ctls_msrs(void)
2250{
2251 /*
2252 * Note that as a general rule, the high half of the MSRs (bits in
2253 * the control fields which may be 1) should be initialized by the
2254 * intersection of the underlying hardware's MSR (i.e., features which
2255 * can be supported) and the list of features we want to expose -
2256 * because they are known to be properly supported in our code.
2257 * Also, usually, the low half of the MSRs (bits which must be 1) can
2258 * be set to 0, meaning that L1 may turn off any of these bits. The
2259 * reason is that if one of these bits is necessary, it will appear
2260 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2261 * fields of vmcs01 and vmcs02, will turn these bits off - and
2262 * nested_vmx_exit_handled() will not pass related exits to L1.
2263 * These rules have exceptions below.
2264 */
2265
2266 /* pin-based controls */
eabeaacc
JK		 2267 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2268 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2269 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2270 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2271 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2272 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2273 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2274
3dbcd8da 2275 /* exit controls */
c0dfee58
ACL		 2276 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2277 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2278 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2279
c0dfee58 2280 nested_vmx_exit_ctls_high &=
b87a51ae 2281#ifdef CONFIG_X86_64
c0dfee58 2282 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2283#endif
f4124500
JK		 2284 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2285 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2286 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2287 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2288
36be0b9d
PB		 2289 if (vmx_mpx_supported())
2290 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae
NHE		 2291
2292 /* entry controls */
2293 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2294 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2295 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2296 nested_vmx_entry_ctls_high &=
57435349
JK		 2297#ifdef CONFIG_X86_64
2298 VM_ENTRY_IA32E_MODE |
2299#endif
2300 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2301 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2302 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2303 if (vmx_mpx_supported())
2304 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2305
b87a51ae
NHE		 2306 /* cpu-based controls */
2307 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2308 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2309 nested_vmx_procbased_ctls_low = 0;
2310 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2311 CPU_BASED_VIRTUAL_INTR_PENDING |
2312 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2313 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2314 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2315 CPU_BASED_CR3_STORE_EXITING |
2316#ifdef CONFIG_X86_64
2317 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2318#endif
2319 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2320 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2321 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2322 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2323 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2324 /*
2325 * We can allow some features even when not supported by the
2326 * hardware. For example, L1 can specify an MSR bitmap - and we
2327 * can use it to avoid exits to L1 - even when L0 runs L2
2328 * without MSR bitmaps.
2329 */
2330 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2331
3dcdf3ec
JK		 2332 /* We support free control of CR3 access interception. */
2333 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2334 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2335
b87a51ae
NHE		 2336 /* secondary cpu-based controls */
2337 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2338 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2339 nested_vmx_secondary_ctls_low = 0;
2340 nested_vmx_secondary_ctls_high &=
d6851fbe 2341 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2342 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2343 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2344
afa61f75
NHE		 2345 if (enable_ept) {
2346 /* nested EPT: emulate EPT also to L1 */
2347 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2348 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2349 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2350 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2351 nested_vmx_ept_caps &= vmx_capability.ept;
2352 /*
4b855078
BD		 2353 * For nested guests, we don't do anything specific
2354 * for single context invalidation. Hence, only advertise
2355 * support for global context invalidation.
afa61f75 2356 */
4b855078 2357 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2358 } else
2359 nested_vmx_ept_caps = 0;
2360
c18911a2
JK		 2361 /* miscellaneous data */
2362 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2363 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2364 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2365 VMX_MISC_ACTIVITY_HLT;
c18911a2 2366 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2367}
2368
2369static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2370{
2371 /*
2372 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2373 */
2374 return ((control & high) | low) == control;
2375}
2376
2377static inline u64 vmx_control_msr(u32 low, u32 high)
2378{
2379 return low | ((u64)high << 32);
2380}
2381
cae50139 2382/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2383static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2384{
b87a51ae 2385 switch (msr_index) {
b87a51ae
NHE		 2386 case MSR_IA32_VMX_BASIC:
2387 /*
2388 * This MSR reports some information about VMX support. We
2389 * should return information about the VMX we emulate for the
2390 * guest, and the VMCS structure we give it - not about the
2391 * VMX support of the underlying hardware.
2392 */
3dbcd8da 2393 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2394 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2395 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2396 break;
2397 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2398 case MSR_IA32_VMX_PINBASED_CTLS:
2399 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2400 nested_vmx_pinbased_ctls_high);
2401 break;
2402 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2403 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2404 nested_vmx_procbased_ctls_high);
2405 break;
b87a51ae
NHE		 2406 case MSR_IA32_VMX_PROCBASED_CTLS:
2407 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2408 nested_vmx_procbased_ctls_high);
2409 break;
2410 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2411 case MSR_IA32_VMX_EXIT_CTLS:
2412 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2413 nested_vmx_exit_ctls_high);
2414 break;
2415 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2416 case MSR_IA32_VMX_ENTRY_CTLS:
2417 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2418 nested_vmx_entry_ctls_high);
2419 break;
2420 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2421 *pdata = vmx_control_msr(nested_vmx_misc_low,
2422 nested_vmx_misc_high);
b87a51ae
NHE		 2423 break;
2424 /*
2425 * These MSRs specify bits which the guest must keep fixed (on or off)
2426 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2427 * We picked the standard core2 setting.
2428 */
2429#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2430#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2431 case MSR_IA32_VMX_CR0_FIXED0:
2432 *pdata = VMXON_CR0_ALWAYSON;
2433 break;
2434 case MSR_IA32_VMX_CR0_FIXED1:
2435 *pdata = -1ULL;
2436 break;
2437 case MSR_IA32_VMX_CR4_FIXED0:
2438 *pdata = VMXON_CR4_ALWAYSON;
2439 break;
2440 case MSR_IA32_VMX_CR4_FIXED1:
2441 *pdata = -1ULL;
2442 break;
2443 case MSR_IA32_VMX_VMCS_ENUM:
2444 *pdata = 0x1f;
2445 break;
2446 case MSR_IA32_VMX_PROCBASED_CTLS2:
2447 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2448 nested_vmx_secondary_ctls_high);
2449 break;
2450 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2451 /* Currently, no nested vpid support */
2452 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2453 break;
2454 default:
b87a51ae 2455 return 1;
b3897a49
NHE		 2456 }
2457
b87a51ae
NHE		 2458 return 0;
2459}
2460
6aa8b732
AK		 2461/*
2462 * Reads an msr value (of 'msr_index') into 'pdata'.
2463 * Returns 0 on success, non-0 otherwise.
2464 * Assumes vcpu_load() was already called.
2465 */
2466static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2467{
2468 u64 data;
26bb0981 2469 struct shared_msr_entry *msr;
6aa8b732
AK		 2470
2471 if (!pdata) {
2472 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2473 return -EINVAL;
2474 }
2475
2476 switch (msr_index) {
05b3e0c2 2477#ifdef CONFIG_X86_64
6aa8b732
AK		 2478 case MSR_FS_BASE:
2479 data = vmcs_readl(GUEST_FS_BASE);
2480 break;
2481 case MSR_GS_BASE:
2482 data = vmcs_readl(GUEST_GS_BASE);
2483 break;
44ea2b17
AK		 2484 case MSR_KERNEL_GS_BASE:
2485 vmx_load_host_state(to_vmx(vcpu));
2486 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2487 break;
26bb0981 2488#endif
6aa8b732 2489 case MSR_EFER:
3bab1f5d 2490 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2491 case MSR_IA32_TSC:
6aa8b732
AK		 2492 data = guest_read_tsc();
2493 break;
2494 case MSR_IA32_SYSENTER_CS:
2495 data = vmcs_read32(GUEST_SYSENTER_CS);
2496 break;
2497 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2498 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2499 break;
2500 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2501 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2502 break;
0dd376e7 2503 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2504 if (!vmx_mpx_supported())
2505 return 1;
0dd376e7
LJ		 2506 data = vmcs_read64(GUEST_BNDCFGS);
2507 break;
cae50139
JK		 2508 case MSR_IA32_FEATURE_CONTROL:
2509 if (!nested_vmx_allowed(vcpu))
2510 return 1;
2511 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2512 break;
2513 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2514 if (!nested_vmx_allowed(vcpu))
2515 return 1;
2516 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2517 case MSR_TSC_AUX:
2518 if (!to_vmx(vcpu)->rdtscp_enabled)
2519 return 1;
2520 /* Otherwise falls through */
6aa8b732 2521 default:
8b9cf98c 2522 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2523 if (msr) {
2524 data = msr->data;
2525 break;
6aa8b732 2526 }
3bab1f5d 2527 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2528 }
2529
2530 *pdata = data;
2531 return 0;
2532}
2533
cae50139
JK		 2534static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2535
6aa8b732
AK		 2536/*
2537 * Writes msr value into into the appropriate "register".
2538 * Returns 0 on success, non-0 otherwise.
2539 * Assumes vcpu_load() was already called.
2540 */
8fe8ab46 2541static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2542{
a2fa3e9f 2543 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2544 struct shared_msr_entry *msr;
2cc51560 2545 int ret = 0;
8fe8ab46
WA		 2546 u32 msr_index = msr_info->index;
2547 u64 data = msr_info->data;
2cc51560 2548
6aa8b732 2549 switch (msr_index) {
3bab1f5d 2550 case MSR_EFER:
8fe8ab46 2551 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2552 break;
16175a79 2553#ifdef CONFIG_X86_64
6aa8b732 2554 case MSR_FS_BASE:
2fb92db1 2555 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2556 vmcs_writel(GUEST_FS_BASE, data);
2557 break;
2558 case MSR_GS_BASE:
2fb92db1 2559 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2560 vmcs_writel(GUEST_GS_BASE, data);
2561 break;
44ea2b17
AK		 2562 case MSR_KERNEL_GS_BASE:
2563 vmx_load_host_state(vmx);
2564 vmx->msr_guest_kernel_gs_base = data;
2565 break;
6aa8b732
AK		 2566#endif
2567 case MSR_IA32_SYSENTER_CS:
2568 vmcs_write32(GUEST_SYSENTER_CS, data);
2569 break;
2570 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2571 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2572 break;
2573 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2574 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2575 break;
0dd376e7 2576 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2577 if (!vmx_mpx_supported())
2578 return 1;
0dd376e7
LJ		 2579 vmcs_write64(GUEST_BNDCFGS, data);
2580 break;
af24a4e4 2581 case MSR_IA32_TSC:
8fe8ab46 2582 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2583 break;
468d472f
SY		 2584 case MSR_IA32_CR_PAT:
2585 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2586 vmcs_write64(GUEST_IA32_PAT, data);
2587 vcpu->arch.pat = data;
2588 break;
2589 }
8fe8ab46 2590 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2591 break;
ba904635
WA		 2592 case MSR_IA32_TSC_ADJUST:
2593 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2594 break;
cae50139
JK		 2595 case MSR_IA32_FEATURE_CONTROL:
2596 if (!nested_vmx_allowed(vcpu) ||
2597 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2598 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2599 return 1;
2600 vmx->nested.msr_ia32_feature_control = data;
2601 if (msr_info->host_initiated && data == 0)
2602 vmx_leave_nested(vcpu);
2603 break;
2604 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2605 return 1; /* they are read-only */
4e47c7a6
SY		 2606 case MSR_TSC_AUX:
2607 if (!vmx->rdtscp_enabled)
2608 return 1;
2609 /* Check reserved bit, higher 32 bits should be zero */
2610 if ((data >> 32) != 0)
2611 return 1;
2612 /* Otherwise falls through */
6aa8b732 2613 default:
8b9cf98c 2614 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2615 if (msr) {
2616 msr->data = data;
2225fd56
AK		 2617 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2618 preempt_disable();
9ee73970
AK		 2619 kvm_set_shared_msr(msr->index, msr->data,
2620 msr->mask);
2225fd56
AK		 2621 preempt_enable();
2622 }
3bab1f5d 2623 break;
6aa8b732 2624 }
8fe8ab46 2625 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2626 }
2627
2cc51560 2628 return ret;
6aa8b732
AK		 2629}
2630
5fdbf976 2631static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2632{
5fdbf976
MT		 2633 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2634 switch (reg) {
2635 case VCPU_REGS_RSP:
2636 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2637 break;
2638 case VCPU_REGS_RIP:
2639 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2640 break;
6de4f3ad
AK		 2641 case VCPU_EXREG_PDPTR:
2642 if (enable_ept)
2643 ept_save_pdptrs(vcpu);
2644 break;
5fdbf976
MT		 2645 default:
2646 break;
2647 }
6aa8b732
AK		 2648}
2649
6aa8b732
AK		 2650static __init int cpu_has_kvm_support(void)
2651{
6210e37b 2652 return cpu_has_vmx();
6aa8b732
AK		 2653}
2654
2655static __init int vmx_disabled_by_bios(void)
2656{
2657 u64 msr;
2658
2659 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2660 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2661 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2662 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2663 && tboot_enabled())
2664 return 1;
23f3e991 2665 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2666 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2667 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2668 && !tboot_enabled()) {
2669 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2670 "activate TXT before enabling KVM\n");
cafd6659 2671 return 1;
f9335afe 2672 }
23f3e991
JC		 2673 /* launched w/o TXT and VMX disabled */
2674 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2675 && !tboot_enabled())
2676 return 1;
cafd6659
SW		 2677 }
2678
2679 return 0;
6aa8b732
AK		 2680}
2681
7725b894
DX		 2682static void kvm_cpu_vmxon(u64 addr)
2683{
2684 asm volatile (ASM_VMX_VMXON_RAX
2685 : : "a"(&addr), "m"(addr)
2686 : "memory", "cc");
2687}
2688
10474ae8 2689static int hardware_enable(void *garbage)
6aa8b732
AK		 2690{
2691 int cpu = raw_smp_processor_id();
2692 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2693 u64 old, test_bits;
6aa8b732 2694
10474ae8
AG		 2695 if (read_cr4() & X86_CR4_VMXE)
2696 return -EBUSY;
2697
d462b819 2698 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2699
2700 /*
2701 * Now we can enable the vmclear operation in kdump
2702 * since the loaded_vmcss_on_cpu list on this cpu
2703 * has been initialized.
2704 *
2705 * Though the cpu is not in VMX operation now, there
2706 * is no problem to enable the vmclear operation
2707 * for the loaded_vmcss_on_cpu list is empty!
2708 */
2709 crash_enable_local_vmclear(cpu);
2710
6aa8b732 2711 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2712
2713 test_bits = FEATURE_CONTROL_LOCKED;
2714 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2715 if (tboot_enabled())
2716 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2717
2718 if ((old & test_bits) != test_bits) {
6aa8b732 2719 /* enable and lock */
cafd6659
SW		 2720 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2721 }
66aee91a 2722 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2723
4610c9cc
DX		 2724 if (vmm_exclusive) {
2725 kvm_cpu_vmxon(phys_addr);
2726 ept_sync_global();
2727 }
10474ae8 2728
357d1226 2729 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2730
10474ae8 2731 return 0;
6aa8b732
AK		 2732}
2733
d462b819 2734static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2735{
2736 int cpu = raw_smp_processor_id();
d462b819 2737 struct loaded_vmcs *v, *n;
543e4243 2738
d462b819
NHE		 2739 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2740 loaded_vmcss_on_cpu_link)
2741 __loaded_vmcs_clear(v);
543e4243
AK		 2742}
2743
710ff4a8
EH		 2744
2745/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2746 * tricks.
2747 */
2748static void kvm_cpu_vmxoff(void)
6aa8b732 2749{
4ecac3fd 2750 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2751}
2752
710ff4a8
EH		 2753static void hardware_disable(void *garbage)
2754{
4610c9cc 2755 if (vmm_exclusive) {
d462b819 2756 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2757 kvm_cpu_vmxoff();
2758 }
7725b894 2759 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2760}
2761
1c3d14fe 2762static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2763 u32 msr, u32 *result)
1c3d14fe
YS		 2764{
2765 u32 vmx_msr_low, vmx_msr_high;
2766 u32 ctl = ctl_min | ctl_opt;
2767
2768 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2769
2770 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2771 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2772
2773 /* Ensure minimum (required) set of control bits are supported. */
2774 if (ctl_min & ~ctl)
002c7f7c 2775 return -EIO;
1c3d14fe
YS		 2776
2777 *result = ctl;
2778 return 0;
2779}
2780
110312c8
AK		 2781static __init bool allow_1_setting(u32 msr, u32 ctl)
2782{
2783 u32 vmx_msr_low, vmx_msr_high;
2784
2785 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2786 return vmx_msr_high & ctl;
2787}
2788
002c7f7c 2789static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2790{
2791 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2792 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2793 u32 _pin_based_exec_control = 0;
2794 u32 _cpu_based_exec_control = 0;
f78e0e2e 2795 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2796 u32 _vmexit_control = 0;
2797 u32 _vmentry_control = 0;
2798
10166744 2799 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2800#ifdef CONFIG_X86_64
2801 CPU_BASED_CR8_LOAD_EXITING |
2802 CPU_BASED_CR8_STORE_EXITING |
2803#endif
d56f546d
SY		 2804 CPU_BASED_CR3_LOAD_EXITING |
2805 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2806 CPU_BASED_USE_IO_BITMAPS |
2807 CPU_BASED_MOV_DR_EXITING |
a7052897 2808 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2809 CPU_BASED_MWAIT_EXITING |
2810 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2811 CPU_BASED_INVLPG_EXITING |
2812 CPU_BASED_RDPMC_EXITING;
443381a8 2813
f78e0e2e 2814 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2815 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2816 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2817 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2818 &_cpu_based_exec_control) < 0)
002c7f7c 2819 return -EIO;
6e5d865c
YS		 2820#ifdef CONFIG_X86_64
2821 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2822 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2823 ~CPU_BASED_CR8_STORE_EXITING;
2824#endif
f78e0e2e 2825 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2826 min2 = 0;
2827 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2828 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2829 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2830 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2831 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2832 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2833 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2834 SECONDARY_EXEC_RDTSCP |
83d4c286 2835 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2836 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2837 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2838 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2839 if (adjust_vmx_controls(min2, opt2,
2840 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2841 &_cpu_based_2nd_exec_control) < 0)
2842 return -EIO;
2843 }
2844#ifndef CONFIG_X86_64
2845 if (!(_cpu_based_2nd_exec_control &
2846 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2847 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2848#endif
83d4c286
YZ		 2849
2850 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2851 _cpu_based_2nd_exec_control &= ~(
8d14695f 2852 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2853 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2854 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2855
d56f546d 2856 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2857 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2858 enabled */
5fff7d27
GN		 2859 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2860 CPU_BASED_CR3_STORE_EXITING |
2861 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2862 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2863 vmx_capability.ept, vmx_capability.vpid);
2864 }
1c3d14fe 2865
81908bf4 2866 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2867#ifdef CONFIG_X86_64
2868 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2869#endif
a547c6db 2870 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2871 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2872 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2873 &_vmexit_control) < 0)
002c7f7c 2874 return -EIO;
1c3d14fe 2875
01e439be
YZ		 2876 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2877 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2878 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2879 &_pin_based_exec_control) < 0)
2880 return -EIO;
2881
2882 if (!(_cpu_based_2nd_exec_control &
2883 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2884 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2885 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2886
c845f9c6 2887 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2888 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2889 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2890 &_vmentry_control) < 0)
002c7f7c 2891 return -EIO;
6aa8b732 2892
c68876fd 2893 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2894
2895 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2896 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2897 return -EIO;
1c3d14fe
YS		 2898
2899#ifdef CONFIG_X86_64
2900 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2901 if (vmx_msr_high & (1u<<16))
002c7f7c 2902 return -EIO;
1c3d14fe
YS		 2903#endif
2904
2905 /* Require Write-Back (WB) memory type for VMCS accesses. */
2906 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2907 return -EIO;
1c3d14fe 2908
002c7f7c
YS		 2909 vmcs_conf->size = vmx_msr_high & 0x1fff;
2910 vmcs_conf->order = get_order(vmcs_config.size);
2911 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2912
002c7f7c
YS		 2913 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2914 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2915 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2916 vmcs_conf->vmexit_ctrl = _vmexit_control;
2917 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2918
110312c8
AK		 2919 cpu_has_load_ia32_efer =
2920 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2921 VM_ENTRY_LOAD_IA32_EFER)
2922 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2923 VM_EXIT_LOAD_IA32_EFER);
2924
8bf00a52
GN		 2925 cpu_has_load_perf_global_ctrl =
2926 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2927 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2928 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2929 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2930
2931 /*
2932 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2933 * but due to arrata below it can't be used. Workaround is to use
2934 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2935 *
2936 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2937 *
2938 * AAK155 (model 26)
2939 * AAP115 (model 30)
2940 * AAT100 (model 37)
2941 * BC86,AAY89,BD102 (model 44)
2942 * BA97 (model 46)
2943 *
2944 */
2945 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2946 switch (boot_cpu_data.x86_model) {
2947 case 26:
2948 case 30:
2949 case 37:
2950 case 44:
2951 case 46:
2952 cpu_has_load_perf_global_ctrl = false;
2953 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2954 "does not work properly. Using workaround\n");
2955 break;
2956 default:
2957 break;
2958 }
2959 }
2960
1c3d14fe 2961 return 0;
c68876fd 2962}
6aa8b732
AK		 2963
2964static struct vmcs *alloc_vmcs_cpu(int cpu)
2965{
2966 int node = cpu_to_node(cpu);
2967 struct page *pages;
2968 struct vmcs *vmcs;
2969
6484eb3e 2970 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2971 if (!pages)
2972 return NULL;
2973 vmcs = page_address(pages);
1c3d14fe
YS		 2974 memset(vmcs, 0, vmcs_config.size);
2975 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2976 return vmcs;
2977}
2978
2979static struct vmcs *alloc_vmcs(void)
2980{
d3b2c338 2981 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2982}
2983
2984static void free_vmcs(struct vmcs *vmcs)
2985{
1c3d14fe 2986 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2987}
2988
d462b819
NHE		 2989/*
2990 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2991 */
2992static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2993{
2994 if (!loaded_vmcs->vmcs)
2995 return;
2996 loaded_vmcs_clear(loaded_vmcs);
2997 free_vmcs(loaded_vmcs->vmcs);
2998 loaded_vmcs->vmcs = NULL;
2999}
3000
39959588 3001static void free_kvm_area(void)
6aa8b732
AK		 3002{
3003 int cpu;
3004
3230bb47 3005 for_each_possible_cpu(cpu) {
6aa8b732 3006 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3007 per_cpu(vmxarea, cpu) = NULL;
3008 }
6aa8b732
AK		 3009}
3010
fe2b201b
BD		 3011static void init_vmcs_shadow_fields(void)
3012{
3013 int i, j;
3014
3015 /* No checks for read only fields yet */
3016
3017 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3018 switch (shadow_read_write_fields[i]) {
3019 case GUEST_BNDCFGS:
3020 if (!vmx_mpx_supported())
3021 continue;
3022 break;
3023 default:
3024 break;
3025 }
3026
3027 if (j < i)
3028 shadow_read_write_fields[j] =
3029 shadow_read_write_fields[i];
3030 j++;
3031 }
3032 max_shadow_read_write_fields = j;
3033
3034 /* shadowed fields guest access without vmexit */
3035 for (i = 0; i < max_shadow_read_write_fields; i++) {
3036 clear_bit(shadow_read_write_fields[i],
3037 vmx_vmwrite_bitmap);
3038 clear_bit(shadow_read_write_fields[i],
3039 vmx_vmread_bitmap);
3040 }
3041 for (i = 0; i < max_shadow_read_only_fields; i++)
3042 clear_bit(shadow_read_only_fields[i],
3043 vmx_vmread_bitmap);
3044}
3045
6aa8b732
AK		 3046static __init int alloc_kvm_area(void)
3047{
3048 int cpu;
3049
3230bb47 3050 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3051 struct vmcs *vmcs;
3052
3053 vmcs = alloc_vmcs_cpu(cpu);
3054 if (!vmcs) {
3055 free_kvm_area();
3056 return -ENOMEM;
3057 }
3058
3059 per_cpu(vmxarea, cpu) = vmcs;
3060 }
3061 return 0;
3062}
3063
3064static __init int hardware_setup(void)
3065{
002c7f7c
YS		 3066 if (setup_vmcs_config(&vmcs_config) < 0)
3067 return -EIO;
50a37eb4
JR		 3068
3069 if (boot_cpu_has(X86_FEATURE_NX))
3070 kvm_enable_efer_bits(EFER_NX);
3071
93ba03c2
SY		 3072 if (!cpu_has_vmx_vpid())
3073 enable_vpid = 0;
abc4fc58
AG		 3074 if (!cpu_has_vmx_shadow_vmcs())
3075 enable_shadow_vmcs = 0;
fe2b201b
BD		 3076 if (enable_shadow_vmcs)
3077 init_vmcs_shadow_fields();
93ba03c2 3078
4bc9b982
SY		 3079 if (!cpu_has_vmx_ept() ||
3080 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3081 enable_ept = 0;
3a624e29 3082 enable_unrestricted_guest = 0;
83c3a331 3083 enable_ept_ad_bits = 0;
3a624e29
NK		 3084 }
3085
83c3a331
XH		 3086 if (!cpu_has_vmx_ept_ad_bits())
3087 enable_ept_ad_bits = 0;
3088
3a624e29
NK		 3089 if (!cpu_has_vmx_unrestricted_guest())
3090 enable_unrestricted_guest = 0;
93ba03c2
SY		 3091
3092 if (!cpu_has_vmx_flexpriority())
3093 flexpriority_enabled = 0;
3094
95ba8273
GN		 3095 if (!cpu_has_vmx_tpr_shadow())
3096 kvm_x86_ops->update_cr8_intercept = NULL;
3097
54dee993
MT		 3098 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3099 kvm_disable_largepages();
3100
4b8d54f9
ZE		 3101 if (!cpu_has_vmx_ple())
3102 ple_gap = 0;
3103
01e439be
YZ		 3104 if (!cpu_has_vmx_apicv())
3105 enable_apicv = 0;
c7c9c56c 3106
01e439be 3107 if (enable_apicv)
c7c9c56c 3108 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3109 else {
c7c9c56c 3110 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3111 kvm_x86_ops->deliver_posted_interrupt = NULL;
3112 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3113 }
83d4c286 3114
b87a51ae
NHE		 3115 if (nested)
3116 nested_vmx_setup_ctls_msrs();
3117
6aa8b732
AK		 3118 return alloc_kvm_area();
3119}
3120
3121static __exit void hardware_unsetup(void)
3122{
3123 free_kvm_area();
3124}
3125
14168786
GN		 3126static bool emulation_required(struct kvm_vcpu *vcpu)
3127{
3128 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3129}
3130
91b0aa2c 3131static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3132 struct kvm_segment *save)
6aa8b732 3133{
d99e4152
GN		 3134 if (!emulate_invalid_guest_state) {
3135 /*
3136 * CS and SS RPL should be equal during guest entry according
3137 * to VMX spec, but in reality it is not always so. Since vcpu
3138 * is in the middle of the transition from real mode to
3139 * protected mode it is safe to assume that RPL 0 is a good
3140 * default value.
3141 */
3142 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3143 save->selector &= ~SELECTOR_RPL_MASK;
3144 save->dpl = save->selector & SELECTOR_RPL_MASK;
3145 save->s = 1;
6aa8b732 3146 }
d99e4152 3147 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3148}
3149
3150static void enter_pmode(struct kvm_vcpu *vcpu)
3151{
3152 unsigned long flags;
a89a8fb9 3153 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3154
d99e4152
GN		 3155 /*
3156 * Update real mode segment cache. It may be not up-to-date if sement
3157 * register was written while vcpu was in a guest mode.
3158 */
3159 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3161 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3162 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3163 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3164 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3165
7ffd92c5 3166 vmx->rmode.vm86_active = 0;
6aa8b732 3167
2fb92db1
AK		 3168 vmx_segment_cache_clear(vmx);
3169
f5f7b2fe 3170 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3171
3172 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3173 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3174 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3175 vmcs_writel(GUEST_RFLAGS, flags);
3176
66aee91a
RR		 3177 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3178 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3179
3180 update_exception_bitmap(vcpu);
3181
91b0aa2c
GN		 3182 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3183 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3184 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3185 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3186 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3187 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3188}
3189
f5f7b2fe 3190static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3191{
772e0318 3192 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3193 struct kvm_segment var = *save;
3194
3195 var.dpl = 0x3;
3196 if (seg == VCPU_SREG_CS)
3197 var.type = 0x3;
3198
3199 if (!emulate_invalid_guest_state) {
3200 var.selector = var.base >> 4;
3201 var.base = var.base & 0xffff0;
3202 var.limit = 0xffff;
3203 var.g = 0;
3204 var.db = 0;
3205 var.present = 1;
3206 var.s = 1;
3207 var.l = 0;
3208 var.unusable = 0;
3209 var.type = 0x3;
3210 var.avl = 0;
3211 if (save->base & 0xf)
3212 printk_once(KERN_WARNING "kvm: segment base is not "
3213 "paragraph aligned when entering "
3214 "protected mode (seg=%d)", seg);
3215 }
6aa8b732 3216
d99e4152
GN		 3217 vmcs_write16(sf->selector, var.selector);
3218 vmcs_write32(sf->base, var.base);
3219 vmcs_write32(sf->limit, var.limit);
3220 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3221}
3222
3223static void enter_rmode(struct kvm_vcpu *vcpu)
3224{
3225 unsigned long flags;
a89a8fb9 3226 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3227
f5f7b2fe
AK		 3228 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3229 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3230 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3231 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3232 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3233 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3234 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3235
7ffd92c5 3236 vmx->rmode.vm86_active = 1;
6aa8b732 3237
776e58ea
GN		 3238 /*
3239 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3240 * vcpu. Warn the user that an update is overdue.
776e58ea 3241 */
4918c6ca 3242 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3243 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3244 "called before entering vcpu\n");
776e58ea 3245
2fb92db1
AK		 3246 vmx_segment_cache_clear(vmx);
3247
4918c6ca 3248 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3249 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3250 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3251
3252 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3253 vmx->rmode.save_rflags = flags;
6aa8b732 3254
053de044 3255 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3256
3257 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3258 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3259 update_exception_bitmap(vcpu);
3260
d99e4152
GN		 3261 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3262 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3263 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3264 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3265 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3266 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3267
8668a3c4 3268 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3269}
3270
401d10de
AS		 3271static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3272{
3273 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3274 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3275
3276 if (!msr)
3277 return;
401d10de 3278
44ea2b17
AK		 3279 /*
3280 * Force kernel_gs_base reloading before EFER changes, as control
3281 * of this msr depends on is_long_mode().
3282 */
3283 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3284 vcpu->arch.efer = efer;
401d10de 3285 if (efer & EFER_LMA) {
2961e876 3286 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3287 msr->data = efer;
3288 } else {
2961e876 3289 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3290
3291 msr->data = efer & ~EFER_LME;
3292 }
3293 setup_msrs(vmx);
3294}
3295
05b3e0c2 3296#ifdef CONFIG_X86_64
6aa8b732
AK		 3297
3298static void enter_lmode(struct kvm_vcpu *vcpu)
3299{
3300 u32 guest_tr_ar;
3301
2fb92db1
AK		 3302 vmx_segment_cache_clear(to_vmx(vcpu));
3303
6aa8b732
AK		 3304 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3305 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3306 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3307 __func__);
6aa8b732
AK		 3308 vmcs_write32(GUEST_TR_AR_BYTES,
3309 (guest_tr_ar & ~AR_TYPE_MASK)
3310 | AR_TYPE_BUSY_64_TSS);
3311 }
da38f438 3312 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3313}
3314
3315static void exit_lmode(struct kvm_vcpu *vcpu)
3316{
2961e876 3317 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3318 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3319}
3320
3321#endif
3322
2384d2b3
SY		 3323static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3324{
b9d762fa 3325 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3326 if (enable_ept) {
3327 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3328 return;
4e1096d2 3329 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3330 }
2384d2b3
SY		 3331}
3332
e8467fda
AK		 3333static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3334{
3335 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3336
3337 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3338 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3339}
3340
aff48baa
AK		 3341static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3342{
3343 if (enable_ept && is_paging(vcpu))
3344 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3345 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3346}
3347
25c4c276 3348static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3349{
fc78f519
AK		 3350 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3351
3352 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3353 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3354}
3355
1439442c
SY		 3356static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3357{
d0d538b9
GN		 3358 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3359
6de4f3ad
AK		 3360 if (!test_bit(VCPU_EXREG_PDPTR,
3361 (unsigned long *)&vcpu->arch.regs_dirty))
3362 return;
3363
1439442c 3364 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3365 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3366 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3367 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3368 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3369 }
3370}
3371
8f5d549f
AK		 3372static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3373{
d0d538b9
GN		 3374 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3375
8f5d549f 3376 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3377 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3378 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3379 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3380 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3381 }
6de4f3ad
AK		 3382
3383 __set_bit(VCPU_EXREG_PDPTR,
3384 (unsigned long *)&vcpu->arch.regs_avail);
3385 __set_bit(VCPU_EXREG_PDPTR,
3386 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3387}
3388
5e1746d6 3389static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3390
3391static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3392 unsigned long cr0,
3393 struct kvm_vcpu *vcpu)
3394{
5233dd51
MT		 3395 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3396 vmx_decache_cr3(vcpu);
1439442c
SY		 3397 if (!(cr0 & X86_CR0_PG)) {
3398 /* From paging/starting to nonpaging */
3399 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3400 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3401 (CPU_BASED_CR3_LOAD_EXITING |
3402 CPU_BASED_CR3_STORE_EXITING));
3403 vcpu->arch.cr0 = cr0;
fc78f519 3404 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3405 } else if (!is_paging(vcpu)) {
3406 /* From nonpaging to paging */
3407 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3408 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3409 ~(CPU_BASED_CR3_LOAD_EXITING |
3410 CPU_BASED_CR3_STORE_EXITING));
3411 vcpu->arch.cr0 = cr0;
fc78f519 3412 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3413 }
95eb84a7
SY		 3414
3415 if (!(cr0 & X86_CR0_WP))
3416 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3417}
3418
6aa8b732
AK		 3419static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3420{
7ffd92c5 3421 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3422 unsigned long hw_cr0;
3423
5037878e 3424 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3425 if (enable_unrestricted_guest)
5037878e 3426 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3427 else {
5037878e 3428 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3429
218e763f
GN		 3430 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3431 enter_pmode(vcpu);
6aa8b732 3432
218e763f
GN		 3433 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3434 enter_rmode(vcpu);
3435 }
6aa8b732 3436
05b3e0c2 3437#ifdef CONFIG_X86_64
f6801dff 3438 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3439 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3440 enter_lmode(vcpu);
707d92fa 3441 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3442 exit_lmode(vcpu);
3443 }
3444#endif
3445
089d034e 3446 if (enable_ept)
1439442c
SY		 3447 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3448
02daab21 3449 if (!vcpu->fpu_active)
81231c69 3450 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3451
6aa8b732 3452 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3453 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3454 vcpu->arch.cr0 = cr0;
14168786
GN		 3455
3456 /* depends on vcpu->arch.cr0 to be set to a new value */
3457 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3458}
3459
1439442c
SY		 3460static u64 construct_eptp(unsigned long root_hpa)
3461{
3462 u64 eptp;
3463
3464 /* TODO write the value reading from MSR */
3465 eptp = VMX_EPT_DEFAULT_MT |
3466 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3467 if (enable_ept_ad_bits)
3468 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3469 eptp |= (root_hpa & PAGE_MASK);
3470
3471 return eptp;
3472}
3473
6aa8b732
AK		 3474static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3475{
1439442c
SY		 3476 unsigned long guest_cr3;
3477 u64 eptp;
3478
3479 guest_cr3 = cr3;
089d034e 3480 if (enable_ept) {
1439442c
SY		 3481 eptp = construct_eptp(cr3);
3482 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3483 if (is_paging(vcpu) || is_guest_mode(vcpu))
3484 guest_cr3 = kvm_read_cr3(vcpu);
3485 else
3486 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3487 ept_load_pdptrs(vcpu);
1439442c
SY		 3488 }
3489
2384d2b3 3490 vmx_flush_tlb(vcpu);
1439442c 3491 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3492}
3493
5e1746d6 3494static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3495{
7ffd92c5 3496 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3497 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3498
5e1746d6
NHE		 3499 if (cr4 & X86_CR4_VMXE) {
3500 /*
3501 * To use VMXON (and later other VMX instructions), a guest
3502 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3503 * So basically the check on whether to allow nested VMX
3504 * is here.
3505 */
3506 if (!nested_vmx_allowed(vcpu))
3507 return 1;
1a0d74e6
JK		 3508 }
3509 if (to_vmx(vcpu)->nested.vmxon &&
3510 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3511 return 1;
3512
ad312c7c 3513 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3514 if (enable_ept) {
3515 if (!is_paging(vcpu)) {
3516 hw_cr4 &= ~X86_CR4_PAE;
3517 hw_cr4 |= X86_CR4_PSE;
c08800a5 3518 /*
e1e746b3
FW		 3519 * SMEP/SMAP is disabled if CPU is in non-paging mode
3520 * in hardware. However KVM always uses paging mode to
c08800a5 3521 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3522 * To emulate this behavior, SMEP/SMAP needs to be
3523 * manually disabled when guest switches to non-paging
3524 * mode.
c08800a5 3525 */
e1e746b3 3526 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3527 } else if (!(cr4 & X86_CR4_PAE)) {
3528 hw_cr4 &= ~X86_CR4_PAE;
3529 }
3530 }
1439442c
SY		 3531
3532 vmcs_writel(CR4_READ_SHADOW, cr4);
3533 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3534 return 0;
6aa8b732
AK		 3535}
3536
6aa8b732
AK		 3537static void vmx_get_segment(struct kvm_vcpu *vcpu,
3538 struct kvm_segment *var, int seg)
3539{
a9179499 3540 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3541 u32 ar;
3542
c6ad1153 3543 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3544 *var = vmx->rmode.segs[seg];
a9179499 3545 if (seg == VCPU_SREG_TR
2fb92db1 3546 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3547 return;
1390a28b
AK		 3548 var->base = vmx_read_guest_seg_base(vmx, seg);
3549 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3550 return;
a9179499 3551 }
2fb92db1
AK		 3552 var->base = vmx_read_guest_seg_base(vmx, seg);
3553 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3554 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3555 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3556 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3557 var->type = ar & 15;
3558 var->s = (ar >> 4) & 1;
3559 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3560 /*
3561 * Some userspaces do not preserve unusable property. Since usable
3562 * segment has to be present according to VMX spec we can use present
3563 * property to amend userspace bug by making unusable segment always
3564 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3565 * segment as unusable.
3566 */
3567 var->present = !var->unusable;
6aa8b732
AK		 3568 var->avl = (ar >> 12) & 1;
3569 var->l = (ar >> 13) & 1;
3570 var->db = (ar >> 14) & 1;
3571 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3572}
3573
a9179499
AK		 3574static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3575{
a9179499
AK		 3576 struct kvm_segment s;
3577
3578 if (to_vmx(vcpu)->rmode.vm86_active) {
3579 vmx_get_segment(vcpu, &s, seg);
3580 return s.base;
3581 }
2fb92db1 3582 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3583}
3584
b09408d0 3585static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3586{
b09408d0
MT		 3587 struct vcpu_vmx *vmx = to_vmx(vcpu);
3588
ae9fedc7 3589 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3590 return 0;
ae9fedc7
PB		 3591 else {
3592 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3593 return AR_DPL(ar);
69c73028 3594 }
69c73028
AK		 3595}
3596
653e3108 3597static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3598{
6aa8b732
AK		 3599 u32 ar;
3600
f0495f9b 3601 if (var->unusable || !var->present)
6aa8b732
AK		 3602 ar = 1 << 16;
3603 else {
3604 ar = var->type & 15;
3605 ar |= (var->s & 1) << 4;
3606 ar |= (var->dpl & 3) << 5;
3607 ar |= (var->present & 1) << 7;
3608 ar |= (var->avl & 1) << 12;
3609 ar |= (var->l & 1) << 13;
3610 ar |= (var->db & 1) << 14;
3611 ar |= (var->g & 1) << 15;
3612 }
653e3108
AK		 3613
3614 return ar;
3615}
3616
3617static void vmx_set_segment(struct kvm_vcpu *vcpu,
3618 struct kvm_segment *var, int seg)
3619{
7ffd92c5 3620 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3621 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3622
2fb92db1
AK		 3623 vmx_segment_cache_clear(vmx);
3624
1ecd50a9
GN		 3625 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3626 vmx->rmode.segs[seg] = *var;
3627 if (seg == VCPU_SREG_TR)
3628 vmcs_write16(sf->selector, var->selector);
3629 else if (var->s)
3630 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3631 goto out;
653e3108 3632 }
1ecd50a9 3633
653e3108
AK		 3634 vmcs_writel(sf->base, var->base);
3635 vmcs_write32(sf->limit, var->limit);
3636 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3637
3638 /*
3639 * Fix the "Accessed" bit in AR field of segment registers for older
3640 * qemu binaries.
3641 * IA32 arch specifies that at the time of processor reset the
3642 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3643 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3644 * state vmexit when "unrestricted guest" mode is turned on.
3645 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3646 * tree. Newer qemu binaries with that qemu fix would not need this
3647 * kvm hack.
3648 */
3649 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3650 var->type |= 0x1; /* Accessed */
3a624e29 3651
f924d66d 3652 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3653
3654out:
14168786 3655 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3656}
3657
6aa8b732
AK		 3658static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3659{
2fb92db1 3660 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3661
3662 *db = (ar >> 14) & 1;
3663 *l = (ar >> 13) & 1;
3664}
3665
89a27f4d 3666static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3667{
89a27f4d
GN		 3668 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3669 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3670}
3671
89a27f4d 3672static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3673{
89a27f4d
GN		 3674 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3675 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3676}
3677
89a27f4d 3678static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3679{
89a27f4d
GN		 3680 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3681 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3682}
3683
89a27f4d 3684static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3685{
89a27f4d
GN		 3686 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3687 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3688}
3689
648dfaa7
MG		 3690static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3691{
3692 struct kvm_segment var;
3693 u32 ar;
3694
3695 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3696 var.dpl = 0x3;
0647f4aa
GN		 3697 if (seg == VCPU_SREG_CS)
3698 var.type = 0x3;
648dfaa7
MG		 3699 ar = vmx_segment_access_rights(&var);
3700
3701 if (var.base != (var.selector << 4))
3702 return false;
89efbed0 3703 if (var.limit != 0xffff)
648dfaa7 3704 return false;
07f42f5f 3705 if (ar != 0xf3)
648dfaa7
MG		 3706 return false;
3707
3708 return true;
3709}
3710
3711static bool code_segment_valid(struct kvm_vcpu *vcpu)
3712{
3713 struct kvm_segment cs;
3714 unsigned int cs_rpl;
3715
3716 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3717 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3718
1872a3f4
AK		 3719 if (cs.unusable)
3720 return false;
648dfaa7
MG		 3721 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3722 return false;
3723 if (!cs.s)
3724 return false;
1872a3f4 3725 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3726 if (cs.dpl > cs_rpl)
3727 return false;
1872a3f4 3728 } else {
648dfaa7
MG		 3729 if (cs.dpl != cs_rpl)
3730 return false;
3731 }
3732 if (!cs.present)
3733 return false;
3734
3735 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3736 return true;
3737}
3738
3739static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3740{
3741 struct kvm_segment ss;
3742 unsigned int ss_rpl;
3743
3744 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3745 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3746
1872a3f4
AK		 3747 if (ss.unusable)
3748 return true;
3749 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3750 return false;
3751 if (!ss.s)
3752 return false;
3753 if (ss.dpl != ss_rpl) /* DPL != RPL */
3754 return false;
3755 if (!ss.present)
3756 return false;
3757
3758 return true;
3759}
3760
3761static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3762{
3763 struct kvm_segment var;
3764 unsigned int rpl;
3765
3766 vmx_get_segment(vcpu, &var, seg);
3767 rpl = var.selector & SELECTOR_RPL_MASK;
3768
1872a3f4
AK		 3769 if (var.unusable)
3770 return true;
648dfaa7
MG		 3771 if (!var.s)
3772 return false;
3773 if (!var.present)
3774 return false;
3775 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3776 if (var.dpl < rpl) /* DPL < RPL */
3777 return false;
3778 }
3779
3780 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3781 * rights flags
3782 */
3783 return true;
3784}
3785
3786static bool tr_valid(struct kvm_vcpu *vcpu)
3787{
3788 struct kvm_segment tr;
3789
3790 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3791
1872a3f4
AK		 3792 if (tr.unusable)
3793 return false;
648dfaa7
MG		 3794 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3795 return false;
1872a3f4 3796 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3797 return false;
3798 if (!tr.present)
3799 return false;
3800
3801 return true;
3802}
3803
3804static bool ldtr_valid(struct kvm_vcpu *vcpu)
3805{
3806 struct kvm_segment ldtr;
3807
3808 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3809
1872a3f4
AK		 3810 if (ldtr.unusable)
3811 return true;
648dfaa7
MG		 3812 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3813 return false;
3814 if (ldtr.type != 2)
3815 return false;
3816 if (!ldtr.present)
3817 return false;
3818
3819 return true;
3820}
3821
3822static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3823{
3824 struct kvm_segment cs, ss;
3825
3826 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3827 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3828
3829 return ((cs.selector & SELECTOR_RPL_MASK) ==
3830 (ss.selector & SELECTOR_RPL_MASK));
3831}
3832
3833/*
3834 * Check if guest state is valid. Returns true if valid, false if
3835 * not.
3836 * We assume that registers are always usable
3837 */
3838static bool guest_state_valid(struct kvm_vcpu *vcpu)
3839{
c5e97c80
GN		 3840 if (enable_unrestricted_guest)
3841 return true;
3842
648dfaa7 3843 /* real mode guest state checks */
f13882d8 3844 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3845 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3846 return false;
3847 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3848 return false;
3849 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3850 return false;
3851 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3852 return false;
3853 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3854 return false;
3855 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3856 return false;
3857 } else {
3858 /* protected mode guest state checks */
3859 if (!cs_ss_rpl_check(vcpu))
3860 return false;
3861 if (!code_segment_valid(vcpu))
3862 return false;
3863 if (!stack_segment_valid(vcpu))
3864 return false;
3865 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3866 return false;
3867 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3868 return false;
3869 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3870 return false;
3871 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3872 return false;
3873 if (!tr_valid(vcpu))
3874 return false;
3875 if (!ldtr_valid(vcpu))
3876 return false;
3877 }
3878 /* TODO:
3879 * - Add checks on RIP
3880 * - Add checks on RFLAGS
3881 */
3882
3883 return true;
3884}
3885
d77c26fc 3886static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3887{
40dcaa9f 3888 gfn_t fn;
195aefde 3889 u16 data = 0;
40dcaa9f 3890 int r, idx, ret = 0;
6aa8b732 3891
40dcaa9f 3892 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3893 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3894 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3895 if (r < 0)
10589a46 3896 goto out;
195aefde 3897 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3898 r = kvm_write_guest_page(kvm, fn++, &data,
3899 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3900 if (r < 0)
10589a46 3901 goto out;
195aefde
IE		 3902 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3903 if (r < 0)
10589a46 3904 goto out;
195aefde
IE		 3905 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3906 if (r < 0)
10589a46 3907 goto out;
195aefde 3908 data = ~0;
10589a46
MT		 3909 r = kvm_write_guest_page(kvm, fn, &data,
3910 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3911 sizeof(u8));
195aefde 3912 if (r < 0)
10589a46
MT		 3913 goto out;
3914
3915 ret = 1;
3916out:
40dcaa9f 3917 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3918 return ret;
6aa8b732
AK		 3919}
3920
b7ebfb05
SY		 3921static int init_rmode_identity_map(struct kvm *kvm)
3922{
40dcaa9f 3923 int i, idx, r, ret;
b7ebfb05
SY		 3924 pfn_t identity_map_pfn;
3925 u32 tmp;
3926
089d034e 3927 if (!enable_ept)
b7ebfb05
SY		 3928 return 1;
3929 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3930 printk(KERN_ERR "EPT: identity-mapping pagetable "
3931 "haven't been allocated!\n");
3932 return 0;
3933 }
3934 if (likely(kvm->arch.ept_identity_pagetable_done))
3935 return 1;
3936 ret = 0;
b927a3ce 3937 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3938 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3939 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3940 if (r < 0)
3941 goto out;
3942 /* Set up identity-mapping pagetable for EPT in real mode */
3943 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3944 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3945 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3946 r = kvm_write_guest_page(kvm, identity_map_pfn,
3947 &tmp, i * sizeof(tmp), sizeof(tmp));
3948 if (r < 0)
3949 goto out;
3950 }
3951 kvm->arch.ept_identity_pagetable_done = true;
3952 ret = 1;
3953out:
40dcaa9f 3954 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3955 return ret;
3956}
3957
6aa8b732
AK		 3958static void seg_setup(int seg)
3959{
772e0318 3960 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3961 unsigned int ar;
6aa8b732
AK		 3962
3963 vmcs_write16(sf->selector, 0);
3964 vmcs_writel(sf->base, 0);
3965 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3966 ar = 0x93;
3967 if (seg == VCPU_SREG_CS)
3968 ar |= 0x08; /* code segment */
3a624e29
NK		 3969
3970 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3971}
3972
f78e0e2e
SY		 3973static int alloc_apic_access_page(struct kvm *kvm)
3974{
4484141a 3975 struct page *page;
f78e0e2e
SY		 3976 struct kvm_userspace_memory_region kvm_userspace_mem;
3977 int r = 0;
3978
79fac95e 3979 mutex_lock(&kvm->slots_lock);
bfc6d222 3980 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3981 goto out;
3982 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3983 kvm_userspace_mem.flags = 0;
3984 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3985 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3986 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3987 if (r)
3988 goto out;
72dc67a6 3989
4484141a
XG		 3990 page = gfn_to_page(kvm, 0xfee00);
3991 if (is_error_page(page)) {
3992 r = -EFAULT;
3993 goto out;
3994 }
3995
3996 kvm->arch.apic_access_page = page;
f78e0e2e 3997out:
79fac95e 3998 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3999 return r;
4000}
4001
b7ebfb05
SY		 4002static int alloc_identity_pagetable(struct kvm *kvm)
4003{
4484141a 4004 struct page *page;
b7ebfb05
SY		 4005 struct kvm_userspace_memory_region kvm_userspace_mem;
4006 int r = 0;
4007
79fac95e 4008 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 4009 if (kvm->arch.ept_identity_pagetable)
4010 goto out;
4011 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4012 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4013 kvm_userspace_mem.guest_phys_addr =
4014 kvm->arch.ept_identity_map_addr;
b7ebfb05 4015 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4016 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 4017 if (r)
4018 goto out;
4019
4484141a
XG		 4020 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4021 if (is_error_page(page)) {
4022 r = -EFAULT;
4023 goto out;
4024 }
4025
4026 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4027out:
79fac95e 4028 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4029 return r;
4030}
4031
2384d2b3
SY		 4032static void allocate_vpid(struct vcpu_vmx *vmx)
4033{
4034 int vpid;
4035
4036 vmx->vpid = 0;
919818ab 4037 if (!enable_vpid)
2384d2b3
SY		 4038 return;
4039 spin_lock(&vmx_vpid_lock);
4040 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4041 if (vpid < VMX_NR_VPIDS) {
4042 vmx->vpid = vpid;
4043 __set_bit(vpid, vmx_vpid_bitmap);
4044 }
4045 spin_unlock(&vmx_vpid_lock);
4046}
4047
cdbecfc3
LJ		 4048static void free_vpid(struct vcpu_vmx *vmx)
4049{
4050 if (!enable_vpid)
4051 return;
4052 spin_lock(&vmx_vpid_lock);
4053 if (vmx->vpid != 0)
4054 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4055 spin_unlock(&vmx_vpid_lock);
4056}
4057
8d14695f
YZ		 4058#define MSR_TYPE_R 1
4059#define MSR_TYPE_W 2
4060static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4061 u32 msr, int type)
25c5f225 4062{
3e7c73e9 4063 int f = sizeof(unsigned long);
25c5f225
SY		 4064
4065 if (!cpu_has_vmx_msr_bitmap())
4066 return;
4067
4068 /*
4069 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4070 * have the write-low and read-high bitmap offsets the wrong way round.
4071 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4072 */
25c5f225 4073 if (msr <= 0x1fff) {
8d14695f
YZ		 4074 if (type & MSR_TYPE_R)
4075 /* read-low */
4076 __clear_bit(msr, msr_bitmap + 0x000 / f);
4077
4078 if (type & MSR_TYPE_W)
4079 /* write-low */
4080 __clear_bit(msr, msr_bitmap + 0x800 / f);
4081
25c5f225
SY		 4082 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4083 msr &= 0x1fff;
8d14695f
YZ		 4084 if (type & MSR_TYPE_R)
4085 /* read-high */
4086 __clear_bit(msr, msr_bitmap + 0x400 / f);
4087
4088 if (type & MSR_TYPE_W)
4089 /* write-high */
4090 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4091
4092 }
4093}
4094
4095static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4096 u32 msr, int type)
4097{
4098 int f = sizeof(unsigned long);
4099
4100 if (!cpu_has_vmx_msr_bitmap())
4101 return;
4102
4103 /*
4104 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4105 * have the write-low and read-high bitmap offsets the wrong way round.
4106 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4107 */
4108 if (msr <= 0x1fff) {
4109 if (type & MSR_TYPE_R)
4110 /* read-low */
4111 __set_bit(msr, msr_bitmap + 0x000 / f);
4112
4113 if (type & MSR_TYPE_W)
4114 /* write-low */
4115 __set_bit(msr, msr_bitmap + 0x800 / f);
4116
4117 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4118 msr &= 0x1fff;
4119 if (type & MSR_TYPE_R)
4120 /* read-high */
4121 __set_bit(msr, msr_bitmap + 0x400 / f);
4122
4123 if (type & MSR_TYPE_W)
4124 /* write-high */
4125 __set_bit(msr, msr_bitmap + 0xc00 / f);
4126
25c5f225 4127 }
25c5f225
SY		 4128}
4129
5897297b
AK		 4130static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4131{
4132 if (!longmode_only)
8d14695f
YZ		 4133 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4134 msr, MSR_TYPE_R | MSR_TYPE_W);
4135 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4136 msr, MSR_TYPE_R | MSR_TYPE_W);
4137}
4138
4139static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4140{
4141 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4142 msr, MSR_TYPE_R);
4143 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4144 msr, MSR_TYPE_R);
4145}
4146
4147static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4148{
4149 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4150 msr, MSR_TYPE_R);
4151 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4152 msr, MSR_TYPE_R);
4153}
4154
4155static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4156{
4157 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4158 msr, MSR_TYPE_W);
4159 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4160 msr, MSR_TYPE_W);
5897297b
AK		 4161}
4162
01e439be
YZ		 4163static int vmx_vm_has_apicv(struct kvm *kvm)
4164{
4165 return enable_apicv && irqchip_in_kernel(kvm);
4166}
4167
a20ed54d
YZ		 4168/*
4169 * Send interrupt to vcpu via posted interrupt way.
4170 * 1. If target vcpu is running(non-root mode), send posted interrupt
4171 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4172 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4173 * interrupt from PIR in next vmentry.
4174 */
4175static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4176{
4177 struct vcpu_vmx *vmx = to_vmx(vcpu);
4178 int r;
4179
4180 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4181 return;
4182
4183 r = pi_test_and_set_on(&vmx->pi_desc);
4184 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4185#ifdef CONFIG_SMP
a20ed54d
YZ		 4186 if (!r && (vcpu->mode == IN_GUEST_MODE))
4187 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4188 POSTED_INTR_VECTOR);
4189 else
6ffbbbba 4190#endif
a20ed54d
YZ		 4191 kvm_vcpu_kick(vcpu);
4192}
4193
4194static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4195{
4196 struct vcpu_vmx *vmx = to_vmx(vcpu);
4197
4198 if (!pi_test_and_clear_on(&vmx->pi_desc))
4199 return;
4200
4201 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4202}
4203
4204static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4205{
4206 return;
4207}
4208
a3a8ff8e
NHE		 4209/*
4210 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4211 * will not change in the lifetime of the guest.
4212 * Note that host-state that does change is set elsewhere. E.g., host-state
4213 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4214 */
a547c6db 4215static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4216{
4217 u32 low32, high32;
4218 unsigned long tmpl;
4219 struct desc_ptr dt;
4220
b1a74bf8 4221 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4222 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4223 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4224
4225 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4226#ifdef CONFIG_X86_64
4227 /*
4228 * Load null selectors, so we can avoid reloading them in
4229 * __vmx_load_host_state(), in case userspace uses the null selectors
4230 * too (the expected case).
4231 */
4232 vmcs_write16(HOST_DS_SELECTOR, 0);
4233 vmcs_write16(HOST_ES_SELECTOR, 0);
4234#else
a3a8ff8e
NHE		 4235 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4236 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4237#endif
a3a8ff8e
NHE		 4238 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4239 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4240
4241 native_store_idt(&dt);
4242 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4243 vmx->host_idt_base = dt.address;
a3a8ff8e 4244
83287ea4 4245 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4246
4247 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4248 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4249 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4250 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4251
4252 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4253 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4254 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4255 }
4256}
4257
bf8179a0
NHE		 4258static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4259{
4260 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4261 if (enable_ept)
4262 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4263 if (is_guest_mode(&vmx->vcpu))
4264 vmx->vcpu.arch.cr4_guest_owned_bits &=
4265 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4266 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4267}
4268
01e439be
YZ		 4269static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4270{
4271 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4272
4273 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4274 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4275 return pin_based_exec_ctrl;
4276}
4277
bf8179a0
NHE		 4278static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4279{
4280 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4281
4282 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4283 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4284
bf8179a0
NHE		 4285 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4286 exec_control &= ~CPU_BASED_TPR_SHADOW;
4287#ifdef CONFIG_X86_64
4288 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4289 CPU_BASED_CR8_LOAD_EXITING;
4290#endif
4291 }
4292 if (!enable_ept)
4293 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4294 CPU_BASED_CR3_LOAD_EXITING |
4295 CPU_BASED_INVLPG_EXITING;
4296 return exec_control;
4297}
4298
4299static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4300{
4301 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4302 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4303 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4304 if (vmx->vpid == 0)
4305 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4306 if (!enable_ept) {
4307 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4308 enable_unrestricted_guest = 0;
ad756a16
MJ		 4309 /* Enable INVPCID for non-ept guests may cause performance regression. */
4310 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4311 }
4312 if (!enable_unrestricted_guest)
4313 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4314 if (!ple_gap)
4315 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4316 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4317 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4318 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4319 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4320 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4321 (handle_vmptrld).
4322 We can NOT enable shadow_vmcs here because we don't have yet
4323 a current VMCS12
4324 */
4325 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4326 return exec_control;
4327}
4328
ce88decf
XG		 4329static void ept_set_mmio_spte_mask(void)
4330{
4331 /*
4332 * EPT Misconfigurations can be generated if the value of bits 2:0
4333 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4334 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4335 * spte.
4336 */
885032b9 4337 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4338}
4339
6aa8b732
AK		 4340/*
4341 * Sets up the vmcs for emulated real mode.
4342 */
8b9cf98c 4343static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4344{
2e4ce7f5 4345#ifdef CONFIG_X86_64
6aa8b732 4346 unsigned long a;
2e4ce7f5 4347#endif
6aa8b732 4348 int i;
6aa8b732 4349
6aa8b732 4350 /* I/O */
3e7c73e9
AK		 4351 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4352 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4353
4607c2d7
AG		 4354 if (enable_shadow_vmcs) {
4355 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4356 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4357 }
25c5f225 4358 if (cpu_has_vmx_msr_bitmap())
5897297b 4359 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4360
6aa8b732
AK		 4361 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4362
6aa8b732 4363 /* Control */
01e439be 4364 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4365
bf8179a0 4366 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4367
83ff3b9d 4368 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4369 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4370 vmx_secondary_exec_control(vmx));
83ff3b9d 4371 }
f78e0e2e 4372
01e439be 4373 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4374 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4375 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4376 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4377 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4378
4379 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4380
4381 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4382 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4383 }
4384
4b8d54f9
ZE		 4385 if (ple_gap) {
4386 vmcs_write32(PLE_GAP, ple_gap);
4387 vmcs_write32(PLE_WINDOW, ple_window);
4388 }
4389
c3707958
XG		 4390 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4391 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4392 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4393
9581d442
AK		 4394 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4395 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4396 vmx_set_constant_host_state(vmx);
05b3e0c2 4397#ifdef CONFIG_X86_64
6aa8b732
AK		 4398 rdmsrl(MSR_FS_BASE, a);
4399 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4400 rdmsrl(MSR_GS_BASE, a);
4401 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4402#else
4403 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4404 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4405#endif
4406
2cc51560
ED		 4407 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4408 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4409 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4410 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4411 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4412
468d472f 4413 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4414 u32 msr_low, msr_high;
4415 u64 host_pat;
468d472f
SY		 4416 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4417 host_pat = msr_low | ((u64) msr_high << 32);
4418 /* Write the default value follow host pat */
4419 vmcs_write64(GUEST_IA32_PAT, host_pat);
4420 /* Keep arch.pat sync with GUEST_IA32_PAT */
4421 vmx->vcpu.arch.pat = host_pat;
4422 }
4423
6aa8b732
AK		 4424 for (i = 0; i < NR_VMX_MSR; ++i) {
4425 u32 index = vmx_msr_index[i];
4426 u32 data_low, data_high;
a2fa3e9f 4427 int j = vmx->nmsrs;
6aa8b732
AK		 4428
4429 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4430 continue;
432bd6cb
AK		 4431 if (wrmsr_safe(index, data_low, data_high) < 0)
4432 continue;
26bb0981
AK		 4433 vmx->guest_msrs[j].index = i;
4434 vmx->guest_msrs[j].data = 0;
d5696725 4435 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4436 ++vmx->nmsrs;
6aa8b732 4437 }
6aa8b732 4438
2961e876
GN		 4439
4440 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4441
4442 /* 22.2.1, 20.8.1 */
2961e876 4443 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4444
e00c8cf2 4445 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4446 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4447
4448 return 0;
4449}
4450
57f252f2 4451static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4452{
4453 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4454 struct msr_data apic_base_msr;
e00c8cf2 4455
7ffd92c5 4456 vmx->rmode.vm86_active = 0;
e00c8cf2 4457
3b86cd99
JK		 4458 vmx->soft_vnmi_blocked = 0;
4459
ad312c7c 4460 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4461 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4462 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4463 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4464 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4465 apic_base_msr.host_initiated = true;
4466 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4467
2fb92db1
AK		 4468 vmx_segment_cache_clear(vmx);
4469
5706be0d 4470 seg_setup(VCPU_SREG_CS);
66450a21 4471 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4472 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4473
4474 seg_setup(VCPU_SREG_DS);
4475 seg_setup(VCPU_SREG_ES);
4476 seg_setup(VCPU_SREG_FS);
4477 seg_setup(VCPU_SREG_GS);
4478 seg_setup(VCPU_SREG_SS);
4479
4480 vmcs_write16(GUEST_TR_SELECTOR, 0);
4481 vmcs_writel(GUEST_TR_BASE, 0);
4482 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4483 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4484
4485 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4486 vmcs_writel(GUEST_LDTR_BASE, 0);
4487 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4488 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4489
4490 vmcs_write32(GUEST_SYSENTER_CS, 0);
4491 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4492 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4493
4494 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4495 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4496
e00c8cf2
AK		 4497 vmcs_writel(GUEST_GDTR_BASE, 0);
4498 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4499
4500 vmcs_writel(GUEST_IDTR_BASE, 0);
4501 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4502
443381a8 4503 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4504 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4505 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4506
e00c8cf2
AK		 4507 /* Special registers */
4508 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4509
4510 setup_msrs(vmx);
4511
6aa8b732
AK		 4512 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4513
f78e0e2e
SY		 4514 if (cpu_has_vmx_tpr_shadow()) {
4515 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4516 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4517 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4518 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4519 vmcs_write32(TPR_THRESHOLD, 0);
4520 }
4521
4522 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4523 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4524 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4525
01e439be
YZ		 4526 if (vmx_vm_has_apicv(vcpu->kvm))
4527 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4528
2384d2b3
SY		 4529 if (vmx->vpid != 0)
4530 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4531
fa40052c 4532 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4533 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4534 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4535 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4536 vmx_fpu_activate(&vmx->vcpu);
4537 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4538
b9d762fa 4539 vpid_sync_context(vmx);
6aa8b732
AK		 4540}
4541
b6f1250e
NHE		 4542/*
4543 * In nested virtualization, check if L1 asked to exit on external interrupts.
4544 * For most existing hypervisors, this will always return true.
4545 */
4546static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4547{
4548 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4549 PIN_BASED_EXT_INTR_MASK;
4550}
4551
77b0f5d6
BD		 4552/*
4553 * In nested virtualization, check if L1 has set
4554 * VM_EXIT_ACK_INTR_ON_EXIT
4555 */
4556static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4557{
4558 return get_vmcs12(vcpu)->vm_exit_controls &
4559 VM_EXIT_ACK_INTR_ON_EXIT;
4560}
4561
ea8ceb83
JK		 4562static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4563{
4564 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4565 PIN_BASED_NMI_EXITING;
4566}
4567
c9a7953f 4568static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4569{
4570 u32 cpu_based_vm_exec_control;
730dca42 4571
3b86cd99
JK		 4572 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4573 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4574 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4575}
4576
c9a7953f 4577static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4578{
4579 u32 cpu_based_vm_exec_control;
4580
c9a7953f
JK		 4581 if (!cpu_has_virtual_nmis() ||
4582 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4583 enable_irq_window(vcpu);
4584 return;
4585 }
3b86cd99
JK		 4586
4587 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4588 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4589 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4590}
4591
66fd3f7f 4592static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4593{
9c8cba37 4594 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4595 uint32_t intr;
4596 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4597
229456fc 4598 trace_kvm_inj_virq(irq);
2714d1d3 4599
fa89a817 4600 ++vcpu->stat.irq_injections;
7ffd92c5 4601 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4602 int inc_eip = 0;
4603 if (vcpu->arch.interrupt.soft)
4604 inc_eip = vcpu->arch.event_exit_inst_len;
4605 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4606 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4607 return;
4608 }
66fd3f7f
GN		 4609 intr = irq | INTR_INFO_VALID_MASK;
4610 if (vcpu->arch.interrupt.soft) {
4611 intr |= INTR_TYPE_SOFT_INTR;
4612 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4613 vmx->vcpu.arch.event_exit_inst_len);
4614 } else
4615 intr |= INTR_TYPE_EXT_INTR;
4616 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4617}
4618
f08864b4
SY		 4619static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4620{
66a5a347
JK		 4621 struct vcpu_vmx *vmx = to_vmx(vcpu);
4622
0b6ac343
NHE		 4623 if (is_guest_mode(vcpu))
4624 return;
4625
3b86cd99
JK		 4626 if (!cpu_has_virtual_nmis()) {
4627 /*
4628 * Tracking the NMI-blocked state in software is built upon
4629 * finding the next open IRQ window. This, in turn, depends on
4630 * well-behaving guests: They have to keep IRQs disabled at
4631 * least as long as the NMI handler runs. Otherwise we may
4632 * cause NMI nesting, maybe breaking the guest. But as this is
4633 * highly unlikely, we can live with the residual risk.
4634 */
4635 vmx->soft_vnmi_blocked = 1;
4636 vmx->vnmi_blocked_time = 0;
4637 }
4638
487b391d 4639 ++vcpu->stat.nmi_injections;
9d58b931 4640 vmx->nmi_known_unmasked = false;
7ffd92c5 4641 if (vmx->rmode.vm86_active) {
71f9833b 4642 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4643 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4644 return;
4645 }
f08864b4
SY		 4646 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4647 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4648}
4649
3cfc3092
JK		 4650static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4651{
4652 if (!cpu_has_virtual_nmis())
4653 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4654 if (to_vmx(vcpu)->nmi_known_unmasked)
4655 return false;
c332c83a 4656 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4657}
4658
4659static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4660{
4661 struct vcpu_vmx *vmx = to_vmx(vcpu);
4662
4663 if (!cpu_has_virtual_nmis()) {
4664 if (vmx->soft_vnmi_blocked != masked) {
4665 vmx->soft_vnmi_blocked = masked;
4666 vmx->vnmi_blocked_time = 0;
4667 }
4668 } else {
9d58b931 4669 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4670 if (masked)
4671 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4672 GUEST_INTR_STATE_NMI);
4673 else
4674 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4675 GUEST_INTR_STATE_NMI);
4676 }
4677}
4678
2505dc9f
JK		 4679static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4680{
b6b8a145
JK		 4681 if (to_vmx(vcpu)->nested.nested_run_pending)
4682 return 0;
ea8ceb83 4683
2505dc9f
JK		 4684 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4685 return 0;
4686
4687 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4688 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4689 | GUEST_INTR_STATE_NMI));
4690}
4691
78646121
GN		 4692static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4693{
b6b8a145
JK		 4694 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4695 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4696 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4697 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4698}
4699
cbc94022
IE		 4700static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4701{
4702 int ret;
4703 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4704 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4705 .guest_phys_addr = addr,
4706 .memory_size = PAGE_SIZE * 3,
4707 .flags = 0,
4708 };
4709
47ae31e2 4710 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4711 if (ret)
4712 return ret;
bfc6d222 4713 kvm->arch.tss_addr = addr;
93ea5388
GN		 4714 if (!init_rmode_tss(kvm))
4715 return -ENOMEM;
4716
cbc94022
IE		 4717 return 0;
4718}
4719
0ca1b4f4 4720static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4721{
77ab6db0 4722 switch (vec) {
77ab6db0 4723 case BP_VECTOR:
c573cd22
JK		 4724 /*
4725 * Update instruction length as we may reinject the exception
4726 * from user space while in guest debugging mode.
4727 */
4728 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4729 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4730 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4731 return false;
4732 /* fall through */
4733 case DB_VECTOR:
4734 if (vcpu->guest_debug &
4735 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4736 return false;
d0bfb940
JK		 4737 /* fall through */
4738 case DE_VECTOR:
77ab6db0
JK		 4739 case OF_VECTOR:
4740 case BR_VECTOR:
4741 case UD_VECTOR:
4742 case DF_VECTOR:
4743 case SS_VECTOR:
4744 case GP_VECTOR:
4745 case MF_VECTOR:
0ca1b4f4
GN		 4746 return true;
4747 break;
77ab6db0 4748 }
0ca1b4f4
GN		 4749 return false;
4750}
4751
4752static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4753 int vec, u32 err_code)
4754{
4755 /*
4756 * Instruction with address size override prefix opcode 0x67
4757 * Cause the #SS fault with 0 error code in VM86 mode.
4758 */
4759 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4760 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4761 if (vcpu->arch.halt_request) {
4762 vcpu->arch.halt_request = 0;
4763 return kvm_emulate_halt(vcpu);
4764 }
4765 return 1;
4766 }
4767 return 0;
4768 }
4769
4770 /*
4771 * Forward all other exceptions that are valid in real mode.
4772 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4773 * the required debugging infrastructure rework.
4774 */
4775 kvm_queue_exception(vcpu, vec);
4776 return 1;
6aa8b732
AK		 4777}
4778
a0861c02
AK		 4779/*
4780 * Trigger machine check on the host. We assume all the MSRs are already set up
4781 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4782 * We pass a fake environment to the machine check handler because we want
4783 * the guest to be always treated like user space, no matter what context
4784 * it used internally.
4785 */
4786static void kvm_machine_check(void)
4787{
4788#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4789 struct pt_regs regs = {
4790 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4791 .flags = X86_EFLAGS_IF,
4792 };
4793
4794 do_machine_check(&regs, 0);
4795#endif
4796}
4797
851ba692 4798static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4799{
4800 /* already handled by vcpu_run */
4801 return 1;
4802}
4803
851ba692 4804static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4805{
1155f76a 4806 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4807 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4808 u32 intr_info, ex_no, error_code;
42dbaa5a 4809 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4810 u32 vect_info;
4811 enum emulation_result er;
4812
1155f76a 4813 vect_info = vmx->idt_vectoring_info;
88786475 4814 intr_info = vmx->exit_intr_info;
6aa8b732 4815
a0861c02 4816 if (is_machine_check(intr_info))
851ba692 4817 return handle_machine_check(vcpu);
a0861c02 4818
e4a41889 4819 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4820 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4821
4822 if (is_no_device(intr_info)) {
5fd86fcf 4823 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4824 return 1;
4825 }
4826
7aa81cc0 4827 if (is_invalid_opcode(intr_info)) {
51d8b661 4828 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4829 if (er != EMULATE_DONE)
7ee5d940 4830 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4831 return 1;
4832 }
4833
6aa8b732 4834 error_code = 0;
2e11384c 4835 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4836 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4837
4838 /*
4839 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4840 * MMIO, it is better to report an internal error.
4841 * See the comments in vmx_handle_exit.
4842 */
4843 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4844 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4845 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4846 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4847 vcpu->run->internal.ndata = 2;
4848 vcpu->run->internal.data[0] = vect_info;
4849 vcpu->run->internal.data[1] = intr_info;
4850 return 0;
4851 }
4852
6aa8b732 4853 if (is_page_fault(intr_info)) {
1439442c 4854 /* EPT won't cause page fault directly */
cf3ace79 4855 BUG_ON(enable_ept);
6aa8b732 4856 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4857 trace_kvm_page_fault(cr2, error_code);
4858
3298b75c 4859 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4860 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4861 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4862 }
4863
d0bfb940 4864 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4865
4866 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4867 return handle_rmode_exception(vcpu, ex_no, error_code);
4868
42dbaa5a
JK		 4869 switch (ex_no) {
4870 case DB_VECTOR:
4871 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4872 if (!(vcpu->guest_debug &
4873 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4874 vcpu->arch.dr6 &= ~15;
4875 vcpu->arch.dr6 |= dr6;
fd2a445a
HD		 4876 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4877 skip_emulated_instruction(vcpu);
4878
42dbaa5a
JK		 4879 kvm_queue_exception(vcpu, DB_VECTOR);
4880 return 1;
4881 }
4882 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4883 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4884 /* fall through */
4885 case BP_VECTOR:
c573cd22
JK		 4886 /*
4887 * Update instruction length as we may reinject #BP from
4888 * user space while in guest debugging mode. Reading it for
4889 * #DB as well causes no harm, it is not used in that case.
4890 */
4891 vmx->vcpu.arch.event_exit_inst_len =
4892 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4893 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4894 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4895 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4896 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4897 break;
4898 default:
d0bfb940
JK		 4899 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4900 kvm_run->ex.exception = ex_no;
4901 kvm_run->ex.error_code = error_code;
42dbaa5a 4902 break;
6aa8b732 4903 }
6aa8b732
AK		 4904 return 0;
4905}
4906
851ba692 4907static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4908{
1165f5fe 4909 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4910 return 1;
4911}
4912
851ba692 4913static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4914{
851ba692 4915 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4916 return 0;
4917}
6aa8b732 4918
851ba692 4919static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4920{
bfdaab09 4921 unsigned long exit_qualification;
34c33d16 4922 int size, in, string;
039576c0 4923 unsigned port;
6aa8b732 4924
bfdaab09 4925 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4926 string = (exit_qualification & 16) != 0;
cf8f70bf 4927 in = (exit_qualification & 8) != 0;
e70669ab 4928
cf8f70bf 4929 ++vcpu->stat.io_exits;
e70669ab 4930
cf8f70bf 4931 if (string || in)
51d8b661 4932 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4933
cf8f70bf
GN		 4934 port = exit_qualification >> 16;
4935 size = (exit_qualification & 7) + 1;
e93f36bc 4936 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4937
4938 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4939}
4940
102d8325
IM		 4941static void
4942vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4943{
4944 /*
4945 * Patch in the VMCALL instruction:
4946 */
4947 hypercall[0] = 0x0f;
4948 hypercall[1] = 0x01;
4949 hypercall[2] = 0xc1;
102d8325
IM		 4950}
4951
92fbc7b1
JK		 4952static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4953{
4954 unsigned long always_on = VMXON_CR0_ALWAYSON;
4955
4956 if (nested_vmx_secondary_ctls_high &
4957 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4958 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4959 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4960 return (val & always_on) == always_on;
4961}
4962
0fa06071 4963/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4964static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4965{
eeadf9e7 4966 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4967 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4968 unsigned long orig_val = val;
4969
eeadf9e7
NHE		 4970 /*
4971 * We get here when L2 changed cr0 in a way that did not change
4972 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4973 * but did change L0 shadowed bits. So we first calculate the
4974 * effective cr0 value that L1 would like to write into the
4975 * hardware. It consists of the L2-owned bits from the new
4976 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4977 */
1a0d74e6
JK		 4978 val = (val & ~vmcs12->cr0_guest_host_mask) |
4979 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4980
92fbc7b1 4981 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4982 return 1;
1a0d74e6
JK		 4983
4984 if (kvm_set_cr0(vcpu, val))
4985 return 1;
4986 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4987 return 0;
1a0d74e6
JK		 4988 } else {
4989 if (to_vmx(vcpu)->nested.vmxon &&
4990 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4991 return 1;
eeadf9e7 4992 return kvm_set_cr0(vcpu, val);
1a0d74e6 4993 }
eeadf9e7
NHE		 4994}
4995
4996static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4997{
4998 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4999 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5000 unsigned long orig_val = val;
5001
5002 /* analogously to handle_set_cr0 */
5003 val = (val & ~vmcs12->cr4_guest_host_mask) |
5004 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5005 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5006 return 1;
1a0d74e6 5007 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5008 return 0;
5009 } else
5010 return kvm_set_cr4(vcpu, val);
5011}
5012
5013/* called to set cr0 as approriate for clts instruction exit. */
5014static void handle_clts(struct kvm_vcpu *vcpu)
5015{
5016 if (is_guest_mode(vcpu)) {
5017 /*
5018 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5019 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5020 * just pretend it's off (also in arch.cr0 for fpu_activate).
5021 */
5022 vmcs_writel(CR0_READ_SHADOW,
5023 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5024 vcpu->arch.cr0 &= ~X86_CR0_TS;
5025 } else
5026 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5027}
5028
851ba692 5029static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5030{
229456fc 5031 unsigned long exit_qualification, val;
6aa8b732
AK		 5032 int cr;
5033 int reg;
49a9b07e 5034 int err;
6aa8b732 5035
bfdaab09 5036 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5037 cr = exit_qualification & 15;
5038 reg = (exit_qualification >> 8) & 15;
5039 switch ((exit_qualification >> 4) & 3) {
5040 case 0: /* mov to cr */
229456fc
MT		 5041 val = kvm_register_read(vcpu, reg);
5042 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5043 switch (cr) {
5044 case 0:
eeadf9e7 5045 err = handle_set_cr0(vcpu, val);
db8fcefa 5046 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5047 return 1;
5048 case 3:
2390218b 5049 err = kvm_set_cr3(vcpu, val);
db8fcefa 5050 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5051 return 1;
5052 case 4:
eeadf9e7 5053 err = handle_set_cr4(vcpu, val);
db8fcefa 5054 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5055 return 1;
0a5fff19
GN		 5056 case 8: {
5057 u8 cr8_prev = kvm_get_cr8(vcpu);
5058 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5059 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5060 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5061 if (irqchip_in_kernel(vcpu->kvm))
5062 return 1;
5063 if (cr8_prev <= cr8)
5064 return 1;
851ba692 5065 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5066 return 0;
5067 }
4b8073e4 5068 }
6aa8b732 5069 break;
25c4c276 5070 case 2: /* clts */
eeadf9e7 5071 handle_clts(vcpu);
4d4ec087 5072 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5073 skip_emulated_instruction(vcpu);
6b52d186 5074 vmx_fpu_activate(vcpu);
25c4c276 5075 return 1;
6aa8b732
AK		 5076 case 1: /*mov from cr*/
5077 switch (cr) {
5078 case 3:
9f8fe504
AK		 5079 val = kvm_read_cr3(vcpu);
5080 kvm_register_write(vcpu, reg, val);
5081 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5082 skip_emulated_instruction(vcpu);
5083 return 1;
5084 case 8:
229456fc
MT		 5085 val = kvm_get_cr8(vcpu);
5086 kvm_register_write(vcpu, reg, val);
5087 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5088 skip_emulated_instruction(vcpu);
5089 return 1;
5090 }
5091 break;
5092 case 3: /* lmsw */
a1f83a74 5093 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5094 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5095 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5096
5097 skip_emulated_instruction(vcpu);
5098 return 1;
5099 default:
5100 break;
5101 }
851ba692 5102 vcpu->run->exit_reason = 0;
a737f256 5103 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5104 (int)(exit_qualification >> 4) & 3, cr);
5105 return 0;
5106}
5107
851ba692 5108static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5109{
bfdaab09 5110 unsigned long exit_qualification;
6aa8b732
AK		 5111 int dr, reg;
5112
f2483415 5113 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5114 if (!kvm_require_cpl(vcpu, 0))
5115 return 1;
42dbaa5a
JK		 5116 dr = vmcs_readl(GUEST_DR7);
5117 if (dr & DR7_GD) {
5118 /*
5119 * As the vm-exit takes precedence over the debug trap, we
5120 * need to emulate the latter, either for the host or the
5121 * guest debugging itself.
5122 */
5123 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5124 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5125 vcpu->run->debug.arch.dr7 = dr;
5126 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5127 vmcs_readl(GUEST_CS_BASE) +
5128 vmcs_readl(GUEST_RIP);
851ba692
AK		 5129 vcpu->run->debug.arch.exception = DB_VECTOR;
5130 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5131 return 0;
5132 } else {
5133 vcpu->arch.dr7 &= ~DR7_GD;
5134 vcpu->arch.dr6 |= DR6_BD;
5135 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5136 kvm_queue_exception(vcpu, DB_VECTOR);
5137 return 1;
5138 }
5139 }
5140
81908bf4
PB		 5141 if (vcpu->guest_debug == 0) {
5142 u32 cpu_based_vm_exec_control;
5143
5144 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5145 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5146 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5147
5148 /*
5149 * No more DR vmexits; force a reload of the debug registers
5150 * and reenter on this instruction. The next vmexit will
5151 * retrieve the full state of the debug registers.
5152 */
5153 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5154 return 1;
5155 }
5156
bfdaab09 5157 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5158 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5159 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5160 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5161 unsigned long val;
4c4d563b
JK		 5162
5163 if (kvm_get_dr(vcpu, dr, &val))
5164 return 1;
5165 kvm_register_write(vcpu, reg, val);
020df079 5166 } else
a4ab9d0c 5167 if (kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg)))
4c4d563b
JK		 5168 return 1;
5169
6aa8b732
AK		 5170 skip_emulated_instruction(vcpu);
5171 return 1;
5172}
5173
73aaf249
JK		 5174static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5175{
5176 return vcpu->arch.dr6;
5177}
5178
5179static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5180{
5181}
5182
81908bf4
PB		 5183static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5184{
5185 u32 cpu_based_vm_exec_control;
5186
5187 get_debugreg(vcpu->arch.db[0], 0);
5188 get_debugreg(vcpu->arch.db[1], 1);
5189 get_debugreg(vcpu->arch.db[2], 2);
5190 get_debugreg(vcpu->arch.db[3], 3);
5191 get_debugreg(vcpu->arch.dr6, 6);
5192 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5193
5194 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5195
5196 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5197 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5198 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5199}
5200
020df079
GN		 5201static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5202{
5203 vmcs_writel(GUEST_DR7, val);
5204}
5205
851ba692 5206static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5207{
06465c5a
AK		 5208 kvm_emulate_cpuid(vcpu);
5209 return 1;
6aa8b732
AK		 5210}
5211
851ba692 5212static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5213{
ad312c7c 5214 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5215 u64 data;
5216
5217 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5218 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5219 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5220 return 1;
5221 }
5222
229456fc 5223 trace_kvm_msr_read(ecx, data);
2714d1d3 5224
6aa8b732 5225 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5226 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5227 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5228 skip_emulated_instruction(vcpu);
5229 return 1;
5230}
5231
851ba692 5232static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5233{
8fe8ab46 5234 struct msr_data msr;
ad312c7c
ZX		 5235 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5236 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5237 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5238
8fe8ab46
WA		 5239 msr.data = data;
5240 msr.index = ecx;
5241 msr.host_initiated = false;
5242 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5243 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5244 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5245 return 1;
5246 }
5247
59200273 5248 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5249 skip_emulated_instruction(vcpu);
5250 return 1;
5251}
5252
851ba692 5253static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5254{
3842d135 5255 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5256 return 1;
5257}
5258
851ba692 5259static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5260{
85f455f7
ED		 5261 u32 cpu_based_vm_exec_control;
5262
5263 /* clear pending irq */
5264 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5265 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5266 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5267
3842d135
AK		 5268 kvm_make_request(KVM_REQ_EVENT, vcpu);
5269
a26bf12a 5270 ++vcpu->stat.irq_window_exits;
2714d1d3 5271
c1150d8c
DL		 5272 /*
5273 * If the user space waits to inject interrupts, exit as soon as
5274 * possible
5275 */
8061823a 5276 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5277 vcpu->run->request_interrupt_window &&
8061823a 5278 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5279 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5280 return 0;
5281 }
6aa8b732
AK		 5282 return 1;
5283}
5284
851ba692 5285static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5286{
5287 skip_emulated_instruction(vcpu);
d3bef15f 5288 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5289}
5290
851ba692 5291static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5292{
510043da 5293 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5294 kvm_emulate_hypercall(vcpu);
5295 return 1;
c21415e8
IM		 5296}
5297
ec25d5e6
GN		 5298static int handle_invd(struct kvm_vcpu *vcpu)
5299{
51d8b661 5300 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5301}
5302
851ba692 5303static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5304{
f9c617f6 5305 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5306
5307 kvm_mmu_invlpg(vcpu, exit_qualification);
5308 skip_emulated_instruction(vcpu);
5309 return 1;
5310}
5311
fee84b07
AK		 5312static int handle_rdpmc(struct kvm_vcpu *vcpu)
5313{
5314 int err;
5315
5316 err = kvm_rdpmc(vcpu);
5317 kvm_complete_insn_gp(vcpu, err);
5318
5319 return 1;
5320}
5321
851ba692 5322static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5323{
5324 skip_emulated_instruction(vcpu);
f5f48ee1 5325 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5326 return 1;
5327}
5328
2acf923e
DC		 5329static int handle_xsetbv(struct kvm_vcpu *vcpu)
5330{
5331 u64 new_bv = kvm_read_edx_eax(vcpu);
5332 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5333
5334 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5335 skip_emulated_instruction(vcpu);
5336 return 1;
5337}
5338
851ba692 5339static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5340{
58fbbf26
KT		 5341 if (likely(fasteoi)) {
5342 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5343 int access_type, offset;
5344
5345 access_type = exit_qualification & APIC_ACCESS_TYPE;
5346 offset = exit_qualification & APIC_ACCESS_OFFSET;
5347 /*
5348 * Sane guest uses MOV to write EOI, with written value
5349 * not cared. So make a short-circuit here by avoiding
5350 * heavy instruction emulation.
5351 */
5352 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5353 (offset == APIC_EOI)) {
5354 kvm_lapic_set_eoi(vcpu);
5355 skip_emulated_instruction(vcpu);
5356 return 1;
5357 }
5358 }
51d8b661 5359 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5360}
5361
c7c9c56c
YZ		 5362static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5363{
5364 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5365 int vector = exit_qualification & 0xff;
5366
5367 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5368 kvm_apic_set_eoi_accelerated(vcpu, vector);
5369 return 1;
5370}
5371
83d4c286
YZ		 5372static int handle_apic_write(struct kvm_vcpu *vcpu)
5373{
5374 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5375 u32 offset = exit_qualification & 0xfff;
5376
5377 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5378 kvm_apic_write_nodecode(vcpu, offset);
5379 return 1;
5380}
5381
851ba692 5382static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5383{
60637aac 5384 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5385 unsigned long exit_qualification;
e269fb21
JK		 5386 bool has_error_code = false;
5387 u32 error_code = 0;
37817f29 5388 u16 tss_selector;
7f3d35fd 5389 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5390
5391 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5392 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5393 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5394
5395 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5396
5397 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5398 if (reason == TASK_SWITCH_GATE && idt_v) {
5399 switch (type) {
5400 case INTR_TYPE_NMI_INTR:
5401 vcpu->arch.nmi_injected = false;
654f06fc 5402 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5403 break;
5404 case INTR_TYPE_EXT_INTR:
66fd3f7f 5405 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5406 kvm_clear_interrupt_queue(vcpu);
5407 break;
5408 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5409 if (vmx->idt_vectoring_info &
5410 VECTORING_INFO_DELIVER_CODE_MASK) {
5411 has_error_code = true;
5412 error_code =
5413 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5414 }
5415 /* fall through */
64a7ec06
GN		 5416 case INTR_TYPE_SOFT_EXCEPTION:
5417 kvm_clear_exception_queue(vcpu);
5418 break;
5419 default:
5420 break;
5421 }
60637aac 5422 }
37817f29
IE		 5423 tss_selector = exit_qualification;
5424
64a7ec06
GN		 5425 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5426 type != INTR_TYPE_EXT_INTR &&
5427 type != INTR_TYPE_NMI_INTR))
5428 skip_emulated_instruction(vcpu);
5429
7f3d35fd
KW		 5430 if (kvm_task_switch(vcpu, tss_selector,
5431 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5432 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5433 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5434 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5435 vcpu->run->internal.ndata = 0;
42dbaa5a 5436 return 0;
acb54517 5437 }
42dbaa5a
JK		 5438
5439 /* clear all local breakpoint enable flags */
1f854112 5440 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5441
5442 /*
5443 * TODO: What about debug traps on tss switch?
5444 * Are we supposed to inject them and update dr6?
5445 */
5446
5447 return 1;
37817f29
IE		 5448}
5449
851ba692 5450static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5451{
f9c617f6 5452 unsigned long exit_qualification;
1439442c 5453 gpa_t gpa;
4f5982a5 5454 u32 error_code;
1439442c 5455 int gla_validity;
1439442c 5456
f9c617f6 5457 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5458
1439442c
SY		 5459 gla_validity = (exit_qualification >> 7) & 0x3;
5460 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5461 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5462 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5463 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5464 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5465 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5466 (long unsigned int)exit_qualification);
851ba692
AK		 5467 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5468 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5469 return 0;
1439442c
SY		 5470 }
5471
0be9c7a8
GN		 5472 /*
5473 * EPT violation happened while executing iret from NMI,
5474 * "blocked by NMI" bit has to be set before next VM entry.
5475 * There are errata that may cause this bit to not be set:
5476 * AAK134, BY25.
5477 */
bcd1c294
GN		 5478 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5479 cpu_has_virtual_nmis() &&
5480 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5481 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5482
1439442c 5483 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5484 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5485
5486 /* It is a write fault? */
5487 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5488 /* It is a fetch fault? */
5489 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5490 /* ept page table is present? */
5491 error_code |= (exit_qualification >> 3) & 0x1;
5492
25d92081
YZ		 5493 vcpu->arch.exit_qualification = exit_qualification;
5494
4f5982a5 5495 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5496}
5497
68f89400
MT		 5498static u64 ept_rsvd_mask(u64 spte, int level)
5499{
5500 int i;
5501 u64 mask = 0;
5502
5503 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5504 mask |= (1ULL << i);
5505
5506 if (level > 2)
5507 /* bits 7:3 reserved */
5508 mask |= 0xf8;
5509 else if (level == 2) {
5510 if (spte & (1ULL << 7))
5511 /* 2MB ref, bits 20:12 reserved */
5512 mask |= 0x1ff000;
5513 else
5514 /* bits 6:3 reserved */
5515 mask |= 0x78;
5516 }
5517
5518 return mask;
5519}
5520
5521static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5522 int level)
5523{
5524 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5525
5526 /* 010b (write-only) */
5527 WARN_ON((spte & 0x7) == 0x2);
5528
5529 /* 110b (write/execute) */
5530 WARN_ON((spte & 0x7) == 0x6);
5531
5532 /* 100b (execute-only) and value not supported by logical processor */
5533 if (!cpu_has_vmx_ept_execute_only())
5534 WARN_ON((spte & 0x7) == 0x4);
5535
5536 /* not 000b */
5537 if ((spte & 0x7)) {
5538 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5539
5540 if (rsvd_bits != 0) {
5541 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5542 __func__, rsvd_bits);
5543 WARN_ON(1);
5544 }
5545
5546 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5547 u64 ept_mem_type = (spte & 0x38) >> 3;
5548
5549 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5550 ept_mem_type == 7) {
5551 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5552 __func__, ept_mem_type);
5553 WARN_ON(1);
5554 }
5555 }
5556 }
5557}
5558
851ba692 5559static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5560{
5561 u64 sptes[4];
ce88decf 5562 int nr_sptes, i, ret;
68f89400
MT		 5563 gpa_t gpa;
5564
5565 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5566 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5567 skip_emulated_instruction(vcpu);
5568 return 1;
5569 }
68f89400 5570
ce88decf 5571 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5572 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5573 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5574 EMULATE_DONE;
f8f55942
XG		 5575
5576 if (unlikely(ret == RET_MMIO_PF_INVALID))
5577 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5578
b37fbea6 5579 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5580 return 1;
5581
5582 /* It is the real ept misconfig */
68f89400
MT		 5583 printk(KERN_ERR "EPT: Misconfiguration.\n");
5584 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5585
5586 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5587
5588 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5589 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5590
851ba692
AK		 5591 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5592 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5593
5594 return 0;
5595}
5596
851ba692 5597static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5598{
5599 u32 cpu_based_vm_exec_control;
5600
5601 /* clear pending NMI */
5602 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5603 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5604 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5605 ++vcpu->stat.nmi_window_exits;
3842d135 5606 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5607
5608 return 1;
5609}
5610
80ced186 5611static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5612{
8b3079a5
AK		 5613 struct vcpu_vmx *vmx = to_vmx(vcpu);
5614 enum emulation_result err = EMULATE_DONE;
80ced186 5615 int ret = 1;
49e9d557
AK		 5616 u32 cpu_exec_ctrl;
5617 bool intr_window_requested;
b8405c18 5618 unsigned count = 130;
49e9d557
AK		 5619
5620 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5621 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5622
b8405c18 5623 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5624 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5625 return handle_interrupt_window(&vmx->vcpu);
5626
de87dcdd
AK		 5627 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5628 return 1;
5629
991eebf9 5630 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5631
ac0a48c3 5632 if (err == EMULATE_USER_EXIT) {
94452b9e 5633 ++vcpu->stat.mmio_exits;
80ced186
MG		 5634 ret = 0;
5635 goto out;
5636 }
1d5a4d9b 5637
de5f70e0
AK		 5638 if (err != EMULATE_DONE) {
5639 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5640 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5641 vcpu->run->internal.ndata = 0;
6d77dbfc 5642 return 0;
de5f70e0 5643 }
ea953ef0 5644
8d76c49e
GN		 5645 if (vcpu->arch.halt_request) {
5646 vcpu->arch.halt_request = 0;
5647 ret = kvm_emulate_halt(vcpu);
5648 goto out;
5649 }
5650
ea953ef0 5651 if (signal_pending(current))
80ced186 5652 goto out;
ea953ef0
MG		 5653 if (need_resched())
5654 schedule();
5655 }
5656
14168786 5657 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5658out:
5659 return ret;
ea953ef0
MG		 5660}
5661
4b8d54f9
ZE		 5662/*
5663 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5664 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5665 */
9fb41ba8 5666static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5667{
5668 skip_emulated_instruction(vcpu);
5669 kvm_vcpu_on_spin(vcpu);
5670
5671 return 1;
5672}
5673
87c00572 5674static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5675{
87c00572 5676 skip_emulated_instruction(vcpu);
59708670
SY		 5677 return 1;
5678}
5679
87c00572
GS		 5680static int handle_mwait(struct kvm_vcpu *vcpu)
5681{
5682 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5683 return handle_nop(vcpu);
5684}
5685
5686static int handle_monitor(struct kvm_vcpu *vcpu)
5687{
5688 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5689 return handle_nop(vcpu);
5690}
5691
ff2f6fe9
NHE		 5692/*
5693 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5694 * We could reuse a single VMCS for all the L2 guests, but we also want the
5695 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5696 * allows keeping them loaded on the processor, and in the future will allow
5697 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5698 * every entry if they never change.
5699 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5700 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5701 *
5702 * The following functions allocate and free a vmcs02 in this pool.
5703 */
5704
5705/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5706static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5707{
5708 struct vmcs02_list *item;
5709 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5710 if (item->vmptr == vmx->nested.current_vmptr) {
5711 list_move(&item->list, &vmx->nested.vmcs02_pool);
5712 return &item->vmcs02;
5713 }
5714
5715 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5716 /* Recycle the least recently used VMCS. */
5717 item = list_entry(vmx->nested.vmcs02_pool.prev,
5718 struct vmcs02_list, list);
5719 item->vmptr = vmx->nested.current_vmptr;
5720 list_move(&item->list, &vmx->nested.vmcs02_pool);
5721 return &item->vmcs02;
5722 }
5723
5724 /* Create a new VMCS */
0fa24ce3 5725 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5726 if (!item)
5727 return NULL;
5728 item->vmcs02.vmcs = alloc_vmcs();
5729 if (!item->vmcs02.vmcs) {
5730 kfree(item);
5731 return NULL;
5732 }
5733 loaded_vmcs_init(&item->vmcs02);
5734 item->vmptr = vmx->nested.current_vmptr;
5735 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5736 vmx->nested.vmcs02_num++;
5737 return &item->vmcs02;
5738}
5739
5740/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5741static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5742{
5743 struct vmcs02_list *item;
5744 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5745 if (item->vmptr == vmptr) {
5746 free_loaded_vmcs(&item->vmcs02);
5747 list_del(&item->list);
5748 kfree(item);
5749 vmx->nested.vmcs02_num--;
5750 return;
5751 }
5752}
5753
5754/*
5755 * Free all VMCSs saved for this vcpu, except the one pointed by
5756 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5757 * currently used, if running L2), and vmcs01 when running L2.
5758 */
5759static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5760{
5761 struct vmcs02_list *item, *n;
5762 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5763 if (vmx->loaded_vmcs != &item->vmcs02)
5764 free_loaded_vmcs(&item->vmcs02);
5765 list_del(&item->list);
5766 kfree(item);
5767 }
5768 vmx->nested.vmcs02_num = 0;
5769
5770 if (vmx->loaded_vmcs != &vmx->vmcs01)
5771 free_loaded_vmcs(&vmx->vmcs01);
5772}
5773
0658fbaa
ACL		 5774/*
5775 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5776 * set the success or error code of an emulated VMX instruction, as specified
5777 * by Vol 2B, VMX Instruction Reference, "Conventions".
5778 */
5779static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5780{
5781 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5782 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5783 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5784}
5785
5786static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5787{
5788 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5789 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5790 X86_EFLAGS_SF | X86_EFLAGS_OF))
5791 | X86_EFLAGS_CF);
5792}
5793
145c28dd 5794static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5795 u32 vm_instruction_error)
5796{
5797 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5798 /*
5799 * failValid writes the error number to the current VMCS, which
5800 * can't be done there isn't a current VMCS.
5801 */
5802 nested_vmx_failInvalid(vcpu);
5803 return;
5804 }
5805 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5806 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5807 X86_EFLAGS_SF | X86_EFLAGS_OF))
5808 | X86_EFLAGS_ZF);
5809 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5810 /*
5811 * We don't need to force a shadow sync because
5812 * VM_INSTRUCTION_ERROR is not shadowed
5813 */
5814}
145c28dd 5815
f4124500
JK		 5816static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5817{
5818 struct vcpu_vmx *vmx =
5819 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5820
5821 vmx->nested.preemption_timer_expired = true;
5822 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5823 kvm_vcpu_kick(&vmx->vcpu);
5824
5825 return HRTIMER_NORESTART;
5826}
5827
19677e32
BD		 5828/*
5829 * Decode the memory-address operand of a vmx instruction, as recorded on an
5830 * exit caused by such an instruction (run by a guest hypervisor).
5831 * On success, returns 0. When the operand is invalid, returns 1 and throws
5832 * #UD or #GP.
5833 */
5834static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5835 unsigned long exit_qualification,
5836 u32 vmx_instruction_info, gva_t *ret)
5837{
5838 /*
5839 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5840 * Execution", on an exit, vmx_instruction_info holds most of the
5841 * addressing components of the operand. Only the displacement part
5842 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5843 * For how an actual address is calculated from all these components,
5844 * refer to Vol. 1, "Operand Addressing".
5845 */
5846 int scaling = vmx_instruction_info & 3;
5847 int addr_size = (vmx_instruction_info >> 7) & 7;
5848 bool is_reg = vmx_instruction_info & (1u << 10);
5849 int seg_reg = (vmx_instruction_info >> 15) & 7;
5850 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5851 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5852 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5853 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5854
5855 if (is_reg) {
5856 kvm_queue_exception(vcpu, UD_VECTOR);
5857 return 1;
5858 }
5859
5860 /* Addr = segment_base + offset */
5861 /* offset = base + [index * scale] + displacement */
5862 *ret = vmx_get_segment_base(vcpu, seg_reg);
5863 if (base_is_valid)
5864 *ret += kvm_register_read(vcpu, base_reg);
5865 if (index_is_valid)
5866 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5867 *ret += exit_qualification; /* holds the displacement */
5868
5869 if (addr_size == 1) /* 32 bit */
5870 *ret &= 0xffffffff;
5871
5872 /*
5873 * TODO: throw #GP (and return 1) in various cases that the VM*
5874 * instructions require it - e.g., offset beyond segment limit,
5875 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5876 * address, and so on. Currently these are not checked.
5877 */
5878 return 0;
5879}
5880
3573e22c
BD		 5881/*
5882 * This function performs the various checks including
5883 * - if it's 4KB aligned
5884 * - No bits beyond the physical address width are set
5885 * - Returns 0 on success or else 1
4291b588 5886 * (Intel SDM Section 30.3)
3573e22c 5887 */
4291b588
BD		 5888static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
5889 gpa_t *vmpointer)
3573e22c
BD		 5890{
5891 gva_t gva;
5892 gpa_t vmptr;
5893 struct x86_exception e;
5894 struct page *page;
5895 struct vcpu_vmx *vmx = to_vmx(vcpu);
5896 int maxphyaddr = cpuid_maxphyaddr(vcpu);
5897
5898 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5899 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5900 return 1;
5901
5902 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5903 sizeof(vmptr), &e)) {
5904 kvm_inject_page_fault(vcpu, &e);
5905 return 1;
5906 }
5907
5908 switch (exit_reason) {
5909 case EXIT_REASON_VMON:
5910 /*
5911 * SDM 3: 24.11.5
5912 * The first 4 bytes of VMXON region contain the supported
5913 * VMCS revision identifier
5914 *
5915 * Note - IA32_VMX_BASIC[48] will never be 1
5916 * for the nested case;
5917 * which replaces physical address width with 32
5918 *
5919 */
bc39c4db 5920 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 5921 nested_vmx_failInvalid(vcpu);
5922 skip_emulated_instruction(vcpu);
5923 return 1;
5924 }
5925
5926 page = nested_get_page(vcpu, vmptr);
5927 if (page == NULL ||
5928 *(u32 *)kmap(page) != VMCS12_REVISION) {
5929 nested_vmx_failInvalid(vcpu);
5930 kunmap(page);
5931 skip_emulated_instruction(vcpu);
5932 return 1;
5933 }
5934 kunmap(page);
5935 vmx->nested.vmxon_ptr = vmptr;
5936 break;
4291b588 5937 case EXIT_REASON_VMCLEAR:
bc39c4db 5938 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5939 nested_vmx_failValid(vcpu,
5940 VMXERR_VMCLEAR_INVALID_ADDRESS);
5941 skip_emulated_instruction(vcpu);
5942 return 1;
5943 }
5944
5945 if (vmptr == vmx->nested.vmxon_ptr) {
5946 nested_vmx_failValid(vcpu,
5947 VMXERR_VMCLEAR_VMXON_POINTER);
5948 skip_emulated_instruction(vcpu);
5949 return 1;
5950 }
5951 break;
5952 case EXIT_REASON_VMPTRLD:
bc39c4db 5953 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5954 nested_vmx_failValid(vcpu,
5955 VMXERR_VMPTRLD_INVALID_ADDRESS);
5956 skip_emulated_instruction(vcpu);
5957 return 1;
5958 }
3573e22c 5959
4291b588
BD		 5960 if (vmptr == vmx->nested.vmxon_ptr) {
5961 nested_vmx_failValid(vcpu,
5962 VMXERR_VMCLEAR_VMXON_POINTER);
5963 skip_emulated_instruction(vcpu);
5964 return 1;
5965 }
5966 break;
3573e22c
BD		 5967 default:
5968 return 1; /* shouldn't happen */
5969 }
5970
4291b588
BD		 5971 if (vmpointer)
5972 *vmpointer = vmptr;
3573e22c
BD		 5973 return 0;
5974}
5975
ec378aee
NHE		 5976/*
5977 * Emulate the VMXON instruction.
5978 * Currently, we just remember that VMX is active, and do not save or even
5979 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5980 * do not currently need to store anything in that guest-allocated memory
5981 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5982 * argument is different from the VMXON pointer (which the spec says they do).
5983 */
5984static int handle_vmon(struct kvm_vcpu *vcpu)
5985{
5986 struct kvm_segment cs;
5987 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5988 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5989 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5990 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5991
5992 /* The Intel VMX Instruction Reference lists a bunch of bits that
5993 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5994 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5995 * Otherwise, we should fail with #UD. We test these now:
5996 */
5997 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5998 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5999 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6000 kvm_queue_exception(vcpu, UD_VECTOR);
6001 return 1;
6002 }
6003
6004 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6005 if (is_long_mode(vcpu) && !cs.l) {
6006 kvm_queue_exception(vcpu, UD_VECTOR);
6007 return 1;
6008 }
6009
6010 if (vmx_get_cpl(vcpu)) {
6011 kvm_inject_gp(vcpu, 0);
6012 return 1;
6013 }
3573e22c 6014
4291b588 6015 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6016 return 1;
6017
145c28dd
AG		 6018 if (vmx->nested.vmxon) {
6019 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6020 skip_emulated_instruction(vcpu);
6021 return 1;
6022 }
b3897a49
NHE		 6023
6024 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6025 != VMXON_NEEDED_FEATURES) {
6026 kvm_inject_gp(vcpu, 0);
6027 return 1;
6028 }
6029
8de48833
AG		 6030 if (enable_shadow_vmcs) {
6031 shadow_vmcs = alloc_vmcs();
6032 if (!shadow_vmcs)
6033 return -ENOMEM;
6034 /* mark vmcs as shadow */
6035 shadow_vmcs->revision_id |= (1u << 31);
6036 /* init shadow vmcs */
6037 vmcs_clear(shadow_vmcs);
6038 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6039 }
ec378aee 6040
ff2f6fe9
NHE		 6041 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6042 vmx->nested.vmcs02_num = 0;
6043
f4124500
JK		 6044 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6045 HRTIMER_MODE_REL);
6046 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6047
ec378aee
NHE		 6048 vmx->nested.vmxon = true;
6049
6050 skip_emulated_instruction(vcpu);
a25eb114 6051 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6052 return 1;
6053}
6054
6055/*
6056 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6057 * for running VMX instructions (except VMXON, whose prerequisites are
6058 * slightly different). It also specifies what exception to inject otherwise.
6059 */
6060static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6061{
6062 struct kvm_segment cs;
6063 struct vcpu_vmx *vmx = to_vmx(vcpu);
6064
6065 if (!vmx->nested.vmxon) {
6066 kvm_queue_exception(vcpu, UD_VECTOR);
6067 return 0;
6068 }
6069
6070 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6071 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6072 (is_long_mode(vcpu) && !cs.l)) {
6073 kvm_queue_exception(vcpu, UD_VECTOR);
6074 return 0;
6075 }
6076
6077 if (vmx_get_cpl(vcpu)) {
6078 kvm_inject_gp(vcpu, 0);
6079 return 0;
6080 }
6081
6082 return 1;
6083}
6084
e7953d7f
AG		 6085static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6086{
8a1b9dd0 6087 u32 exec_control;
012f83cb
AG		 6088 if (enable_shadow_vmcs) {
6089 if (vmx->nested.current_vmcs12 != NULL) {
6090 /* copy to memory all shadowed fields in case
6091 they were modified */
6092 copy_shadow_to_vmcs12(vmx);
6093 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 6094 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6095 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6096 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6097 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 6098 }
6099 }
e7953d7f
AG		 6100 kunmap(vmx->nested.current_vmcs12_page);
6101 nested_release_page(vmx->nested.current_vmcs12_page);
6102}
6103
ec378aee
NHE		 6104/*
6105 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6106 * just stops using VMX.
6107 */
6108static void free_nested(struct vcpu_vmx *vmx)
6109{
6110 if (!vmx->nested.vmxon)
6111 return;
6112 vmx->nested.vmxon = false;
a9d30f33 6113 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 6114 nested_release_vmcs12(vmx);
a9d30f33
NHE		 6115 vmx->nested.current_vmptr = -1ull;
6116 vmx->nested.current_vmcs12 = NULL;
6117 }
e7953d7f
AG		 6118 if (enable_shadow_vmcs)
6119 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6120 /* Unpin physical memory we referred to in current vmcs02 */
6121 if (vmx->nested.apic_access_page) {
6122 nested_release_page(vmx->nested.apic_access_page);
6123 vmx->nested.apic_access_page = 0;
6124 }
ff2f6fe9
NHE		 6125
6126 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6127}
6128
6129/* Emulate the VMXOFF instruction */
6130static int handle_vmoff(struct kvm_vcpu *vcpu)
6131{
6132 if (!nested_vmx_check_permission(vcpu))
6133 return 1;
6134 free_nested(to_vmx(vcpu));
6135 skip_emulated_instruction(vcpu);
a25eb114 6136 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6137 return 1;
6138}
6139
27d6c865
NHE		 6140/* Emulate the VMCLEAR instruction */
6141static int handle_vmclear(struct kvm_vcpu *vcpu)
6142{
6143 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6144 gpa_t vmptr;
6145 struct vmcs12 *vmcs12;
6146 struct page *page;
27d6c865
NHE		 6147
6148 if (!nested_vmx_check_permission(vcpu))
6149 return 1;
6150
4291b588 6151 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6152 return 1;
27d6c865
NHE		 6153
6154 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6155 nested_release_vmcs12(vmx);
27d6c865
NHE		 6156 vmx->nested.current_vmptr = -1ull;
6157 vmx->nested.current_vmcs12 = NULL;
6158 }
6159
6160 page = nested_get_page(vcpu, vmptr);
6161 if (page == NULL) {
6162 /*
6163 * For accurate processor emulation, VMCLEAR beyond available
6164 * physical memory should do nothing at all. However, it is
6165 * possible that a nested vmx bug, not a guest hypervisor bug,
6166 * resulted in this case, so let's shut down before doing any
6167 * more damage:
6168 */
6169 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6170 return 1;
6171 }
6172 vmcs12 = kmap(page);
6173 vmcs12->launch_state = 0;
6174 kunmap(page);
6175 nested_release_page(page);
6176
6177 nested_free_vmcs02(vmx, vmptr);
6178
6179 skip_emulated_instruction(vcpu);
6180 nested_vmx_succeed(vcpu);
6181 return 1;
6182}
6183
cd232ad0
NHE		 6184static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6185
6186/* Emulate the VMLAUNCH instruction */
6187static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6188{
6189 return nested_vmx_run(vcpu, true);
6190}
6191
6192/* Emulate the VMRESUME instruction */
6193static int handle_vmresume(struct kvm_vcpu *vcpu)
6194{
6195
6196 return nested_vmx_run(vcpu, false);
6197}
6198
49f705c5
NHE		 6199enum vmcs_field_type {
6200 VMCS_FIELD_TYPE_U16 = 0,
6201 VMCS_FIELD_TYPE_U64 = 1,
6202 VMCS_FIELD_TYPE_U32 = 2,
6203 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6204};
6205
6206static inline int vmcs_field_type(unsigned long field)
6207{
6208 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6209 return VMCS_FIELD_TYPE_U32;
6210 return (field >> 13) & 0x3 ;
6211}
6212
6213static inline int vmcs_field_readonly(unsigned long field)
6214{
6215 return (((field >> 10) & 0x3) == 1);
6216}
6217
6218/*
6219 * Read a vmcs12 field. Since these can have varying lengths and we return
6220 * one type, we chose the biggest type (u64) and zero-extend the return value
6221 * to that size. Note that the caller, handle_vmread, might need to use only
6222 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6223 * 64-bit fields are to be returned).
6224 */
6225static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6226 unsigned long field, u64 *ret)
6227{
6228 short offset = vmcs_field_to_offset(field);
6229 char *p;
6230
6231 if (offset < 0)
6232 return 0;
6233
6234 p = ((char *)(get_vmcs12(vcpu))) + offset;
6235
6236 switch (vmcs_field_type(field)) {
6237 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6238 *ret = *((natural_width *)p);
6239 return 1;
6240 case VMCS_FIELD_TYPE_U16:
6241 *ret = *((u16 *)p);
6242 return 1;
6243 case VMCS_FIELD_TYPE_U32:
6244 *ret = *((u32 *)p);
6245 return 1;
6246 case VMCS_FIELD_TYPE_U64:
6247 *ret = *((u64 *)p);
6248 return 1;
6249 default:
6250 return 0; /* can never happen. */
6251 }
6252}
6253
20b97fea
AG		 6254
6255static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6256 unsigned long field, u64 field_value){
6257 short offset = vmcs_field_to_offset(field);
6258 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6259 if (offset < 0)
6260 return false;
6261
6262 switch (vmcs_field_type(field)) {
6263 case VMCS_FIELD_TYPE_U16:
6264 *(u16 *)p = field_value;
6265 return true;
6266 case VMCS_FIELD_TYPE_U32:
6267 *(u32 *)p = field_value;
6268 return true;
6269 case VMCS_FIELD_TYPE_U64:
6270 *(u64 *)p = field_value;
6271 return true;
6272 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6273 *(natural_width *)p = field_value;
6274 return true;
6275 default:
6276 return false; /* can never happen. */
6277 }
6278
6279}
6280
16f5b903
AG		 6281static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6282{
6283 int i;
6284 unsigned long field;
6285 u64 field_value;
6286 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6287 const unsigned long *fields = shadow_read_write_fields;
6288 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6289
6290 vmcs_load(shadow_vmcs);
6291
6292 for (i = 0; i < num_fields; i++) {
6293 field = fields[i];
6294 switch (vmcs_field_type(field)) {
6295 case VMCS_FIELD_TYPE_U16:
6296 field_value = vmcs_read16(field);
6297 break;
6298 case VMCS_FIELD_TYPE_U32:
6299 field_value = vmcs_read32(field);
6300 break;
6301 case VMCS_FIELD_TYPE_U64:
6302 field_value = vmcs_read64(field);
6303 break;
6304 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6305 field_value = vmcs_readl(field);
6306 break;
6307 }
6308 vmcs12_write_any(&vmx->vcpu, field, field_value);
6309 }
6310
6311 vmcs_clear(shadow_vmcs);
6312 vmcs_load(vmx->loaded_vmcs->vmcs);
6313}
6314
c3114420
AG		 6315static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6316{
c2bae893
MK		 6317 const unsigned long *fields[] = {
6318 shadow_read_write_fields,
6319 shadow_read_only_fields
c3114420 6320 };
c2bae893 6321 const int max_fields[] = {
c3114420
AG		 6322 max_shadow_read_write_fields,
6323 max_shadow_read_only_fields
6324 };
6325 int i, q;
6326 unsigned long field;
6327 u64 field_value = 0;
6328 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6329
6330 vmcs_load(shadow_vmcs);
6331
c2bae893 6332 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6333 for (i = 0; i < max_fields[q]; i++) {
6334 field = fields[q][i];
6335 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6336
6337 switch (vmcs_field_type(field)) {
6338 case VMCS_FIELD_TYPE_U16:
6339 vmcs_write16(field, (u16)field_value);
6340 break;
6341 case VMCS_FIELD_TYPE_U32:
6342 vmcs_write32(field, (u32)field_value);
6343 break;
6344 case VMCS_FIELD_TYPE_U64:
6345 vmcs_write64(field, (u64)field_value);
6346 break;
6347 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6348 vmcs_writel(field, (long)field_value);
6349 break;
6350 }
6351 }
6352 }
6353
6354 vmcs_clear(shadow_vmcs);
6355 vmcs_load(vmx->loaded_vmcs->vmcs);
6356}
6357
49f705c5
NHE		 6358/*
6359 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6360 * used before) all generate the same failure when it is missing.
6361 */
6362static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6363{
6364 struct vcpu_vmx *vmx = to_vmx(vcpu);
6365 if (vmx->nested.current_vmptr == -1ull) {
6366 nested_vmx_failInvalid(vcpu);
6367 skip_emulated_instruction(vcpu);
6368 return 0;
6369 }
6370 return 1;
6371}
6372
6373static int handle_vmread(struct kvm_vcpu *vcpu)
6374{
6375 unsigned long field;
6376 u64 field_value;
6377 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6378 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6379 gva_t gva = 0;
6380
6381 if (!nested_vmx_check_permission(vcpu) ||
6382 !nested_vmx_check_vmcs12(vcpu))
6383 return 1;
6384
6385 /* Decode instruction info and find the field to read */
6386 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6387 /* Read the field, zero-extended to a u64 field_value */
6388 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6389 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6390 skip_emulated_instruction(vcpu);
6391 return 1;
6392 }
6393 /*
6394 * Now copy part of this value to register or memory, as requested.
6395 * Note that the number of bits actually copied is 32 or 64 depending
6396 * on the guest's mode (32 or 64 bit), not on the given field's length.
6397 */
6398 if (vmx_instruction_info & (1u << 10)) {
6399 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6400 field_value);
6401 } else {
6402 if (get_vmx_mem_address(vcpu, exit_qualification,
6403 vmx_instruction_info, &gva))
6404 return 1;
6405 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6406 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6407 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6408 }
6409
6410 nested_vmx_succeed(vcpu);
6411 skip_emulated_instruction(vcpu);
6412 return 1;
6413}
6414
6415
6416static int handle_vmwrite(struct kvm_vcpu *vcpu)
6417{
6418 unsigned long field;
6419 gva_t gva;
6420 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6421 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6422 /* The value to write might be 32 or 64 bits, depending on L1's long
6423 * mode, and eventually we need to write that into a field of several
6424 * possible lengths. The code below first zero-extends the value to 64
6425 * bit (field_value), and then copies only the approriate number of
6426 * bits into the vmcs12 field.
6427 */
6428 u64 field_value = 0;
6429 struct x86_exception e;
6430
6431 if (!nested_vmx_check_permission(vcpu) ||
6432 !nested_vmx_check_vmcs12(vcpu))
6433 return 1;
6434
6435 if (vmx_instruction_info & (1u << 10))
6436 field_value = kvm_register_read(vcpu,
6437 (((vmx_instruction_info) >> 3) & 0xf));
6438 else {
6439 if (get_vmx_mem_address(vcpu, exit_qualification,
6440 vmx_instruction_info, &gva))
6441 return 1;
6442 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6443 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6444 kvm_inject_page_fault(vcpu, &e);
6445 return 1;
6446 }
6447 }
6448
6449
6450 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6451 if (vmcs_field_readonly(field)) {
6452 nested_vmx_failValid(vcpu,
6453 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6454 skip_emulated_instruction(vcpu);
6455 return 1;
6456 }
6457
20b97fea 6458 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6459 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6460 skip_emulated_instruction(vcpu);
6461 return 1;
6462 }
6463
6464 nested_vmx_succeed(vcpu);
6465 skip_emulated_instruction(vcpu);
6466 return 1;
6467}
6468
63846663
NHE		 6469/* Emulate the VMPTRLD instruction */
6470static int handle_vmptrld(struct kvm_vcpu *vcpu)
6471{
6472 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6473 gpa_t vmptr;
8a1b9dd0 6474 u32 exec_control;
63846663
NHE		 6475
6476 if (!nested_vmx_check_permission(vcpu))
6477 return 1;
6478
4291b588 6479 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6480 return 1;
63846663
NHE		 6481
6482 if (vmx->nested.current_vmptr != vmptr) {
6483 struct vmcs12 *new_vmcs12;
6484 struct page *page;
6485 page = nested_get_page(vcpu, vmptr);
6486 if (page == NULL) {
6487 nested_vmx_failInvalid(vcpu);
6488 skip_emulated_instruction(vcpu);
6489 return 1;
6490 }
6491 new_vmcs12 = kmap(page);
6492 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6493 kunmap(page);
6494 nested_release_page_clean(page);
6495 nested_vmx_failValid(vcpu,
6496 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6497 skip_emulated_instruction(vcpu);
6498 return 1;
6499 }
e7953d7f
AG		 6500 if (vmx->nested.current_vmptr != -1ull)
6501 nested_release_vmcs12(vmx);
63846663
NHE		 6502
6503 vmx->nested.current_vmptr = vmptr;
6504 vmx->nested.current_vmcs12 = new_vmcs12;
6505 vmx->nested.current_vmcs12_page = page;
012f83cb 6506 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6507 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6508 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6509 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6510 vmcs_write64(VMCS_LINK_POINTER,
6511 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6512 vmx->nested.sync_shadow_vmcs = true;
6513 }
63846663
NHE		 6514 }
6515
6516 nested_vmx_succeed(vcpu);
6517 skip_emulated_instruction(vcpu);
6518 return 1;
6519}
6520
6a4d7550
NHE		 6521/* Emulate the VMPTRST instruction */
6522static int handle_vmptrst(struct kvm_vcpu *vcpu)
6523{
6524 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6525 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6526 gva_t vmcs_gva;
6527 struct x86_exception e;
6528
6529 if (!nested_vmx_check_permission(vcpu))
6530 return 1;
6531
6532 if (get_vmx_mem_address(vcpu, exit_qualification,
6533 vmx_instruction_info, &vmcs_gva))
6534 return 1;
6535 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6536 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6537 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6538 sizeof(u64), &e)) {
6539 kvm_inject_page_fault(vcpu, &e);
6540 return 1;
6541 }
6542 nested_vmx_succeed(vcpu);
6543 skip_emulated_instruction(vcpu);
6544 return 1;
6545}
6546
bfd0a56b
NHE		 6547/* Emulate the INVEPT instruction */
6548static int handle_invept(struct kvm_vcpu *vcpu)
6549{
6550 u32 vmx_instruction_info, types;
6551 unsigned long type;
6552 gva_t gva;
6553 struct x86_exception e;
6554 struct {
6555 u64 eptp, gpa;
6556 } operand;
bfd0a56b
NHE		 6557
6558 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6559 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6560 kvm_queue_exception(vcpu, UD_VECTOR);
6561 return 1;
6562 }
6563
6564 if (!nested_vmx_check_permission(vcpu))
6565 return 1;
6566
6567 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6568 kvm_queue_exception(vcpu, UD_VECTOR);
6569 return 1;
6570 }
6571
6572 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6573 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6574
6575 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6576
6577 if (!(types & (1UL << type))) {
6578 nested_vmx_failValid(vcpu,
6579 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6580 return 1;
6581 }
6582
6583 /* According to the Intel VMX instruction reference, the memory
6584 * operand is read even if it isn't needed (e.g., for type==global)
6585 */
6586 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6587 vmx_instruction_info, &gva))
6588 return 1;
6589 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6590 sizeof(operand), &e)) {
6591 kvm_inject_page_fault(vcpu, &e);
6592 return 1;
6593 }
6594
6595 switch (type) {
bfd0a56b
NHE		 6596 case VMX_EPT_EXTENT_GLOBAL:
6597 kvm_mmu_sync_roots(vcpu);
6598 kvm_mmu_flush_tlb(vcpu);
6599 nested_vmx_succeed(vcpu);
6600 break;
6601 default:
4b855078 6602 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6603 BUG_ON(1);
6604 break;
6605 }
6606
6607 skip_emulated_instruction(vcpu);
6608 return 1;
6609}
6610
6aa8b732
AK		 6611/*
6612 * The exit handlers return 1 if the exit was handled fully and guest execution
6613 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6614 * to be done to userspace and return 0.
6615 */
772e0318 6616static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6617 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6618 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6619 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6620 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6621 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6622 [EXIT_REASON_CR_ACCESS] = handle_cr,
6623 [EXIT_REASON_DR_ACCESS] = handle_dr,
6624 [EXIT_REASON_CPUID] = handle_cpuid,
6625 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6626 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6627 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6628 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6629 [EXIT_REASON_INVD] = handle_invd,
a7052897 6630 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6631 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6632 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6633 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6634 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6635 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6636 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6637 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6638 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6639 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6640 [EXIT_REASON_VMOFF] = handle_vmoff,
6641 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6642 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6643 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6644 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6645 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6646 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6647 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6648 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6649 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6650 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6651 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6652 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6653 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6654 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6655 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6656};
6657
6658static const int kvm_vmx_max_exit_handlers =
50a3485c 6659 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6660
908a7bdd
JK		 6661static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6662 struct vmcs12 *vmcs12)
6663{
6664 unsigned long exit_qualification;
6665 gpa_t bitmap, last_bitmap;
6666 unsigned int port;
6667 int size;
6668 u8 b;
6669
908a7bdd 6670 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6671 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6672
6673 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6674
6675 port = exit_qualification >> 16;
6676 size = (exit_qualification & 7) + 1;
6677
6678 last_bitmap = (gpa_t)-1;
6679 b = -1;
6680
6681 while (size > 0) {
6682 if (port < 0x8000)
6683 bitmap = vmcs12->io_bitmap_a;
6684 else if (port < 0x10000)
6685 bitmap = vmcs12->io_bitmap_b;
6686 else
6687 return 1;
6688 bitmap += (port & 0x7fff) / 8;
6689
6690 if (last_bitmap != bitmap)
6691 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6692 return 1;
6693 if (b & (1 << (port & 7)))
6694 return 1;
6695
6696 port++;
6697 size--;
6698 last_bitmap = bitmap;
6699 }
6700
6701 return 0;
6702}
6703
644d711a
NHE		 6704/*
6705 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6706 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6707 * disinterest in the current event (read or write a specific MSR) by using an
6708 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6709 */
6710static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6711 struct vmcs12 *vmcs12, u32 exit_reason)
6712{
6713 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6714 gpa_t bitmap;
6715
cbd29cb6 6716 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6717 return 1;
6718
6719 /*
6720 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6721 * for the four combinations of read/write and low/high MSR numbers.
6722 * First we need to figure out which of the four to use:
6723 */
6724 bitmap = vmcs12->msr_bitmap;
6725 if (exit_reason == EXIT_REASON_MSR_WRITE)
6726 bitmap += 2048;
6727 if (msr_index >= 0xc0000000) {
6728 msr_index -= 0xc0000000;
6729 bitmap += 1024;
6730 }
6731
6732 /* Then read the msr_index'th bit from this bitmap: */
6733 if (msr_index < 1024*8) {
6734 unsigned char b;
bd31a7f5
JK		 6735 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6736 return 1;
644d711a
NHE		 6737 return 1 & (b >> (msr_index & 7));
6738 } else
6739 return 1; /* let L1 handle the wrong parameter */
6740}
6741
6742/*
6743 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6744 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6745 * intercept (via guest_host_mask etc.) the current event.
6746 */
6747static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6748 struct vmcs12 *vmcs12)
6749{
6750 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6751 int cr = exit_qualification & 15;
6752 int reg = (exit_qualification >> 8) & 15;
6753 unsigned long val = kvm_register_read(vcpu, reg);
6754
6755 switch ((exit_qualification >> 4) & 3) {
6756 case 0: /* mov to cr */
6757 switch (cr) {
6758 case 0:
6759 if (vmcs12->cr0_guest_host_mask &
6760 (val ^ vmcs12->cr0_read_shadow))
6761 return 1;
6762 break;
6763 case 3:
6764 if ((vmcs12->cr3_target_count >= 1 &&
6765 vmcs12->cr3_target_value0 == val) ||
6766 (vmcs12->cr3_target_count >= 2 &&
6767 vmcs12->cr3_target_value1 == val) ||
6768 (vmcs12->cr3_target_count >= 3 &&
6769 vmcs12->cr3_target_value2 == val) ||
6770 (vmcs12->cr3_target_count >= 4 &&
6771 vmcs12->cr3_target_value3 == val))
6772 return 0;
6773 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6774 return 1;
6775 break;
6776 case 4:
6777 if (vmcs12->cr4_guest_host_mask &
6778 (vmcs12->cr4_read_shadow ^ val))
6779 return 1;
6780 break;
6781 case 8:
6782 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6783 return 1;
6784 break;
6785 }
6786 break;
6787 case 2: /* clts */
6788 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6789 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6790 return 1;
6791 break;
6792 case 1: /* mov from cr */
6793 switch (cr) {
6794 case 3:
6795 if (vmcs12->cpu_based_vm_exec_control &
6796 CPU_BASED_CR3_STORE_EXITING)
6797 return 1;
6798 break;
6799 case 8:
6800 if (vmcs12->cpu_based_vm_exec_control &
6801 CPU_BASED_CR8_STORE_EXITING)
6802 return 1;
6803 break;
6804 }
6805 break;
6806 case 3: /* lmsw */
6807 /*
6808 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6809 * cr0. Other attempted changes are ignored, with no exit.
6810 */
6811 if (vmcs12->cr0_guest_host_mask & 0xe &
6812 (val ^ vmcs12->cr0_read_shadow))
6813 return 1;
6814 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6815 !(vmcs12->cr0_read_shadow & 0x1) &&
6816 (val & 0x1))
6817 return 1;
6818 break;
6819 }
6820 return 0;
6821}
6822
6823/*
6824 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6825 * should handle it ourselves in L0 (and then continue L2). Only call this
6826 * when in is_guest_mode (L2).
6827 */
6828static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6829{
644d711a
NHE		 6830 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6831 struct vcpu_vmx *vmx = to_vmx(vcpu);
6832 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6833 u32 exit_reason = vmx->exit_reason;
644d711a 6834
542060ea
JK		 6835 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6836 vmcs_readl(EXIT_QUALIFICATION),
6837 vmx->idt_vectoring_info,
6838 intr_info,
6839 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6840 KVM_ISA_VMX);
6841
644d711a
NHE		 6842 if (vmx->nested.nested_run_pending)
6843 return 0;
6844
6845 if (unlikely(vmx->fail)) {
bd80158a
JK		 6846 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6847 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6848 return 1;
6849 }
6850
6851 switch (exit_reason) {
6852 case EXIT_REASON_EXCEPTION_NMI:
6853 if (!is_exception(intr_info))
6854 return 0;
6855 else if (is_page_fault(intr_info))
6856 return enable_ept;
e504c909 6857 else if (is_no_device(intr_info) &&
ccf9844e 6858 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6859 return 0;
644d711a
NHE		 6860 return vmcs12->exception_bitmap &
6861 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6862 case EXIT_REASON_EXTERNAL_INTERRUPT:
6863 return 0;
6864 case EXIT_REASON_TRIPLE_FAULT:
6865 return 1;
6866 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6867 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6868 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6869 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6870 case EXIT_REASON_TASK_SWITCH:
6871 return 1;
6872 case EXIT_REASON_CPUID:
6873 return 1;
6874 case EXIT_REASON_HLT:
6875 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6876 case EXIT_REASON_INVD:
6877 return 1;
6878 case EXIT_REASON_INVLPG:
6879 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6880 case EXIT_REASON_RDPMC:
6881 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6882 case EXIT_REASON_RDTSC:
6883 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6884 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6885 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6886 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6887 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6888 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6889 case EXIT_REASON_INVEPT:
644d711a
NHE		 6890 /*
6891 * VMX instructions trap unconditionally. This allows L1 to
6892 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6893 */
6894 return 1;
6895 case EXIT_REASON_CR_ACCESS:
6896 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6897 case EXIT_REASON_DR_ACCESS:
6898 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6899 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6900 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6901 case EXIT_REASON_MSR_READ:
6902 case EXIT_REASON_MSR_WRITE:
6903 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6904 case EXIT_REASON_INVALID_STATE:
6905 return 1;
6906 case EXIT_REASON_MWAIT_INSTRUCTION:
6907 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6908 case EXIT_REASON_MONITOR_INSTRUCTION:
6909 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6910 case EXIT_REASON_PAUSE_INSTRUCTION:
6911 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6912 nested_cpu_has2(vmcs12,
6913 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6914 case EXIT_REASON_MCE_DURING_VMENTRY:
6915 return 0;
6916 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6917 return 1;
6918 case EXIT_REASON_APIC_ACCESS:
6919 return nested_cpu_has2(vmcs12,
6920 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6921 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6922 /*
6923 * L0 always deals with the EPT violation. If nested EPT is
6924 * used, and the nested mmu code discovers that the address is
6925 * missing in the guest EPT table (EPT12), the EPT violation
6926 * will be injected with nested_ept_inject_page_fault()
6927 */
6928 return 0;
644d711a 6929 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6930 /*
6931 * L2 never uses directly L1's EPT, but rather L0's own EPT
6932 * table (shadow on EPT) or a merged EPT table that L0 built
6933 * (EPT on EPT). So any problems with the structure of the
6934 * table is L0's fault.
6935 */
644d711a
NHE		 6936 return 0;
6937 case EXIT_REASON_WBINVD:
6938 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6939 case EXIT_REASON_XSETBV:
6940 return 1;
6941 default:
6942 return 1;
6943 }
6944}
6945
586f9607
AK		 6946static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6947{
6948 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6949 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6950}
6951
6aa8b732
AK		 6952/*
6953 * The guest has exited. See if we can fix it or if we need userspace
6954 * assistance.
6955 */
851ba692 6956static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6957{
29bd8a78 6958 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6959 u32 exit_reason = vmx->exit_reason;
1155f76a 6960 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6961
80ced186 6962 /* If guest state is invalid, start emulating */
14168786 6963 if (vmx->emulation_required)
80ced186 6964 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6965
644d711a 6966 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6967 nested_vmx_vmexit(vcpu, exit_reason,
6968 vmcs_read32(VM_EXIT_INTR_INFO),
6969 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6970 return 1;
6971 }
6972
5120702e
MG		 6973 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6974 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6975 vcpu->run->fail_entry.hardware_entry_failure_reason
6976 = exit_reason;
6977 return 0;
6978 }
6979
29bd8a78 6980 if (unlikely(vmx->fail)) {
851ba692
AK		 6981 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6982 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6983 = vmcs_read32(VM_INSTRUCTION_ERROR);
6984 return 0;
6985 }
6aa8b732 6986
b9bf6882
XG		 6987 /*
6988 * Note:
6989 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6990 * delivery event since it indicates guest is accessing MMIO.
6991 * The vm-exit can be triggered again after return to guest that
6992 * will cause infinite loop.
6993 */
d77c26fc 6994 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6995 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6996 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6997 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6998 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6999 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7000 vcpu->run->internal.ndata = 2;
7001 vcpu->run->internal.data[0] = vectoring_info;
7002 vcpu->run->internal.data[1] = exit_reason;
7003 return 0;
7004 }
3b86cd99 7005
644d711a
NHE		 7006 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7007 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7008 get_vmcs12(vcpu))))) {
c4282df9 7009 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7010 vmx->soft_vnmi_blocked = 0;
3b86cd99 7011 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7012 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7013 /*
7014 * This CPU don't support us in finding the end of an
7015 * NMI-blocked window if the guest runs with IRQs
7016 * disabled. So we pull the trigger after 1 s of
7017 * futile waiting, but inform the user about this.
7018 */
7019 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7020 "state on VCPU %d after 1 s timeout\n",
7021 __func__, vcpu->vcpu_id);
7022 vmx->soft_vnmi_blocked = 0;
3b86cd99 7023 }
3b86cd99
JK		 7024 }
7025
6aa8b732
AK		 7026 if (exit_reason < kvm_vmx_max_exit_handlers
7027 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7028 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7029 else {
851ba692
AK		 7030 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7031 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7032 }
7033 return 0;
7034}
7035
95ba8273 7036static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7037{
95ba8273 7038 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7039 vmcs_write32(TPR_THRESHOLD, 0);
7040 return;
7041 }
7042
95ba8273 7043 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7044}
7045
8d14695f
YZ		 7046static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7047{
7048 u32 sec_exec_control;
7049
7050 /*
7051 * There is not point to enable virtualize x2apic without enable
7052 * apicv
7053 */
c7c9c56c
YZ		 7054 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7055 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7056 return;
7057
7058 if (!vm_need_tpr_shadow(vcpu->kvm))
7059 return;
7060
7061 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7062
7063 if (set) {
7064 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7065 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7066 } else {
7067 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7068 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7069 }
7070 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7071
7072 vmx_set_msr_bitmap(vcpu);
7073}
7074
c7c9c56c
YZ		 7075static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7076{
7077 u16 status;
7078 u8 old;
7079
7080 if (!vmx_vm_has_apicv(kvm))
7081 return;
7082
7083 if (isr == -1)
7084 isr = 0;
7085
7086 status = vmcs_read16(GUEST_INTR_STATUS);
7087 old = status >> 8;
7088 if (isr != old) {
7089 status &= 0xff;
7090 status |= isr << 8;
7091 vmcs_write16(GUEST_INTR_STATUS, status);
7092 }
7093}
7094
7095static void vmx_set_rvi(int vector)
7096{
7097 u16 status;
7098 u8 old;
7099
7100 status = vmcs_read16(GUEST_INTR_STATUS);
7101 old = (u8)status & 0xff;
7102 if ((u8)vector != old) {
7103 status &= ~0xff;
7104 status |= (u8)vector;
7105 vmcs_write16(GUEST_INTR_STATUS, status);
7106 }
7107}
7108
7109static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7110{
7111 if (max_irr == -1)
7112 return;
7113
7114 vmx_set_rvi(max_irr);
7115}
7116
7117static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7118{
3d81bc7e
YZ		 7119 if (!vmx_vm_has_apicv(vcpu->kvm))
7120 return;
7121
c7c9c56c
YZ		 7122 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7123 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7124 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7125 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7126}
7127
51aa01d1 7128static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7129{
00eba012
AK		 7130 u32 exit_intr_info;
7131
7132 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7133 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7134 return;
7135
c5ca8e57 7136 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7137 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7138
7139 /* Handle machine checks before interrupts are enabled */
00eba012 7140 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7141 kvm_machine_check();
7142
20f65983 7143 /* We need to handle NMIs before interrupts are enabled */
00eba012 7144 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7145 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7146 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7147 asm("int $2");
ff9d07a0
ZY		 7148 kvm_after_handle_nmi(&vmx->vcpu);
7149 }
51aa01d1 7150}
20f65983 7151
a547c6db
YZ		 7152static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7153{
7154 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7155
7156 /*
7157 * If external interrupt exists, IF bit is set in rflags/eflags on the
7158 * interrupt stack frame, and interrupt will be enabled on a return
7159 * from interrupt handler.
7160 */
7161 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7162 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7163 unsigned int vector;
7164 unsigned long entry;
7165 gate_desc *desc;
7166 struct vcpu_vmx *vmx = to_vmx(vcpu);
7167#ifdef CONFIG_X86_64
7168 unsigned long tmp;
7169#endif
7170
7171 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7172 desc = (gate_desc *)vmx->host_idt_base + vector;
7173 entry = gate_offset(*desc);
7174 asm volatile(
7175#ifdef CONFIG_X86_64
7176 "mov %%" _ASM_SP ", %[sp]\n\t"
7177 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7178 "push $%c[ss]\n\t"
7179 "push %[sp]\n\t"
7180#endif
7181 "pushf\n\t"
7182 "orl $0x200, (%%" _ASM_SP ")\n\t"
7183 __ASM_SIZE(push) " $%c[cs]\n\t"
7184 "call *%[entry]\n\t"
7185 :
7186#ifdef CONFIG_X86_64
7187 [sp]"=&r"(tmp)
7188#endif
7189 :
7190 [entry]"r"(entry),
7191 [ss]"i"(__KERNEL_DS),
7192 [cs]"i"(__KERNEL_CS)
7193 );
7194 } else
7195 local_irq_enable();
7196}
7197
da8999d3
LJ		 7198static bool vmx_mpx_supported(void)
7199{
7200 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7201 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7202}
7203
51aa01d1
AK		 7204static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7205{
c5ca8e57 7206 u32 exit_intr_info;
51aa01d1
AK		 7207 bool unblock_nmi;
7208 u8 vector;
7209 bool idtv_info_valid;
7210
7211 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7212
cf393f75 7213 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7214 if (vmx->nmi_known_unmasked)
7215 return;
c5ca8e57
AK		 7216 /*
7217 * Can't use vmx->exit_intr_info since we're not sure what
7218 * the exit reason is.
7219 */
7220 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7221 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7222 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7223 /*
7b4a25cb 7224 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7225 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7226 * a guest IRET fault.
7b4a25cb
GN		 7227 * SDM 3: 23.2.2 (September 2008)
7228 * Bit 12 is undefined in any of the following cases:
7229 * If the VM exit sets the valid bit in the IDT-vectoring
7230 * information field.
7231 * If the VM exit is due to a double fault.
cf393f75 7232 */
7b4a25cb
GN		 7233 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7234 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7235 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7236 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7237 else
7238 vmx->nmi_known_unmasked =
7239 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7240 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7241 } else if (unlikely(vmx->soft_vnmi_blocked))
7242 vmx->vnmi_blocked_time +=
7243 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7244}
7245
3ab66e8a 7246static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7247 u32 idt_vectoring_info,
7248 int instr_len_field,
7249 int error_code_field)
51aa01d1 7250{
51aa01d1
AK		 7251 u8 vector;
7252 int type;
7253 bool idtv_info_valid;
7254
7255 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7256
3ab66e8a
JK		 7257 vcpu->arch.nmi_injected = false;
7258 kvm_clear_exception_queue(vcpu);
7259 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7260
7261 if (!idtv_info_valid)
7262 return;
7263
3ab66e8a 7264 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7265
668f612f
AK		 7266 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7267 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7268
64a7ec06 7269 switch (type) {
37b96e98 7270 case INTR_TYPE_NMI_INTR:
3ab66e8a 7271 vcpu->arch.nmi_injected = true;
668f612f 7272 /*
7b4a25cb 7273 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7274 * Clear bit "block by NMI" before VM entry if a NMI
7275 * delivery faulted.
668f612f 7276 */
3ab66e8a 7277 vmx_set_nmi_mask(vcpu, false);
37b96e98 7278 break;
37b96e98 7279 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7280 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7281 /* fall through */
7282 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7283 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7284 u32 err = vmcs_read32(error_code_field);
851eb667 7285 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7286 } else
851eb667 7287 kvm_requeue_exception(vcpu, vector);
37b96e98 7288 break;
66fd3f7f 7289 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7290 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7291 /* fall through */
37b96e98 7292 case INTR_TYPE_EXT_INTR:
3ab66e8a 7293 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7294 break;
7295 default:
7296 break;
f7d9238f 7297 }
cf393f75
AK		 7298}
7299
83422e17
AK		 7300static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7301{
3ab66e8a 7302 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7303 VM_EXIT_INSTRUCTION_LEN,
7304 IDT_VECTORING_ERROR_CODE);
7305}
7306
b463a6f7
AK		 7307static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7308{
3ab66e8a 7309 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7310 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7311 VM_ENTRY_INSTRUCTION_LEN,
7312 VM_ENTRY_EXCEPTION_ERROR_CODE);
7313
7314 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7315}
7316
d7cd9796
GN		 7317static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7318{
7319 int i, nr_msrs;
7320 struct perf_guest_switch_msr *msrs;
7321
7322 msrs = perf_guest_get_msrs(&nr_msrs);
7323
7324 if (!msrs)
7325 return;
7326
7327 for (i = 0; i < nr_msrs; i++)
7328 if (msrs[i].host == msrs[i].guest)
7329 clear_atomic_switch_msr(vmx, msrs[i].msr);
7330 else
7331 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7332 msrs[i].host);
7333}
7334
a3b5ba49 7335static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7336{
a2fa3e9f 7337 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7338 unsigned long debugctlmsr;
104f226b
AK		 7339
7340 /* Record the guest's net vcpu time for enforced NMI injections. */
7341 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7342 vmx->entry_time = ktime_get();
7343
7344 /* Don't enter VMX if guest state is invalid, let the exit handler
7345 start emulation until we arrive back to a valid state */
14168786 7346 if (vmx->emulation_required)
104f226b
AK		 7347 return;
7348
012f83cb
AG		 7349 if (vmx->nested.sync_shadow_vmcs) {
7350 copy_vmcs12_to_shadow(vmx);
7351 vmx->nested.sync_shadow_vmcs = false;
7352 }
7353
104f226b
AK		 7354 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7355 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7356 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7357 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7358
7359 /* When single-stepping over STI and MOV SS, we must clear the
7360 * corresponding interruptibility bits in the guest state. Otherwise
7361 * vmentry fails as it then expects bit 14 (BS) in pending debug
7362 * exceptions being set, but that's not correct for the guest debugging
7363 * case. */
7364 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7365 vmx_set_interrupt_shadow(vcpu, 0);
7366
d7cd9796 7367 atomic_switch_perf_msrs(vmx);
2a7921b7 7368 debugctlmsr = get_debugctlmsr();
d7cd9796 7369
d462b819 7370 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7371 asm(
6aa8b732 7372 /* Store host registers */
b188c81f
AK		 7373 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7374 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7375 "push %%" _ASM_CX " \n\t"
7376 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7377 "je 1f \n\t"
b188c81f 7378 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7379 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7380 "1: \n\t"
d3edefc0 7381 /* Reload cr2 if changed */
b188c81f
AK		 7382 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7383 "mov %%cr2, %%" _ASM_DX " \n\t"
7384 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7385 "je 2f \n\t"
b188c81f 7386 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7387 "2: \n\t"
6aa8b732 7388 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7389 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7390 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7391 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7392 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7393 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7394 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7395 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7396 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7397#ifdef CONFIG_X86_64
e08aa78a
AK		 7398 "mov %c[r8](%0), %%r8 \n\t"
7399 "mov %c[r9](%0), %%r9 \n\t"
7400 "mov %c[r10](%0), %%r10 \n\t"
7401 "mov %c[r11](%0), %%r11 \n\t"
7402 "mov %c[r12](%0), %%r12 \n\t"
7403 "mov %c[r13](%0), %%r13 \n\t"
7404 "mov %c[r14](%0), %%r14 \n\t"
7405 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7406#endif
b188c81f 7407 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7408
6aa8b732 7409 /* Enter guest mode */
83287ea4 7410 "jne 1f \n\t"
4ecac3fd 7411 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7412 "jmp 2f \n\t"
7413 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7414 "2: "
6aa8b732 7415 /* Save guest registers, load host registers, keep flags */
b188c81f 7416 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7417 "pop %0 \n\t"
b188c81f
AK		 7418 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7419 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7420 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7421 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7422 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7423 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7424 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7425#ifdef CONFIG_X86_64
e08aa78a
AK		 7426 "mov %%r8, %c[r8](%0) \n\t"
7427 "mov %%r9, %c[r9](%0) \n\t"
7428 "mov %%r10, %c[r10](%0) \n\t"
7429 "mov %%r11, %c[r11](%0) \n\t"
7430 "mov %%r12, %c[r12](%0) \n\t"
7431 "mov %%r13, %c[r13](%0) \n\t"
7432 "mov %%r14, %c[r14](%0) \n\t"
7433 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7434#endif
b188c81f
AK		 7435 "mov %%cr2, %%" _ASM_AX " \n\t"
7436 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7437
b188c81f 7438 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7439 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7440 ".pushsection .rodata \n\t"
7441 ".global vmx_return \n\t"
7442 "vmx_return: " _ASM_PTR " 2b \n\t"
7443 ".popsection"
e08aa78a 7444 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7445 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7446 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7447 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7448 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7449 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7450 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7451 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7452 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7453 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7454 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7455#ifdef CONFIG_X86_64
ad312c7c
ZX		 7456 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7457 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7458 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7459 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7460 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7461 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7462 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7463 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7464#endif
40712fae
AK		 7465 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7466 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7467 : "cc", "memory"
7468#ifdef CONFIG_X86_64
b188c81f 7469 , "rax", "rbx", "rdi", "rsi"
c2036300 7470 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7471#else
7472 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7473#endif
7474 );
6aa8b732 7475
2a7921b7
GN		 7476 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7477 if (debugctlmsr)
7478 update_debugctlmsr(debugctlmsr);
7479
aa67f609
AK		 7480#ifndef CONFIG_X86_64
7481 /*
7482 * The sysexit path does not restore ds/es, so we must set them to
7483 * a reasonable value ourselves.
7484 *
7485 * We can't defer this to vmx_load_host_state() since that function
7486 * may be executed in interrupt context, which saves and restore segments
7487 * around it, nullifying its effect.
7488 */
7489 loadsegment(ds, __USER_DS);
7490 loadsegment(es, __USER_DS);
7491#endif
7492
6de4f3ad 7493 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7494 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7495 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7496 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7497 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7498 vcpu->arch.regs_dirty = 0;
7499
1155f76a
AK		 7500 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7501
d462b819 7502 vmx->loaded_vmcs->launched = 1;
1b6269db 7503
51aa01d1 7504 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7505 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7506
e0b890d3
GN		 7507 /*
7508 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7509 * we did not inject a still-pending event to L1 now because of
7510 * nested_run_pending, we need to re-enable this bit.
7511 */
7512 if (vmx->nested.nested_run_pending)
7513 kvm_make_request(KVM_REQ_EVENT, vcpu);
7514
7515 vmx->nested.nested_run_pending = 0;
7516
51aa01d1
AK		 7517 vmx_complete_atomic_exit(vmx);
7518 vmx_recover_nmi_blocking(vmx);
cf393f75 7519 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7520}
7521
6aa8b732
AK		 7522static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7523{
fb3f0f51
RR		 7524 struct vcpu_vmx *vmx = to_vmx(vcpu);
7525
cdbecfc3 7526 free_vpid(vmx);
d462b819 7527 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7528 free_nested(vmx);
fb3f0f51
RR		 7529 kfree(vmx->guest_msrs);
7530 kvm_vcpu_uninit(vcpu);
a4770347 7531 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7532}
7533
fb3f0f51 7534static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7535{
fb3f0f51 7536 int err;
c16f862d 7537 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7538 int cpu;
6aa8b732 7539
a2fa3e9f 7540 if (!vmx)
fb3f0f51
RR		 7541 return ERR_PTR(-ENOMEM);
7542
2384d2b3
SY		 7543 allocate_vpid(vmx);
7544
fb3f0f51
RR		 7545 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7546 if (err)
7547 goto free_vcpu;
965b58a5 7548
a2fa3e9f 7549 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7550 err = -ENOMEM;
fb3f0f51 7551 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7552 goto uninit_vcpu;
7553 }
965b58a5 7554
d462b819
NHE		 7555 vmx->loaded_vmcs = &vmx->vmcs01;
7556 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7557 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7558 goto free_msrs;
d462b819
NHE		 7559 if (!vmm_exclusive)
7560 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7561 loaded_vmcs_init(vmx->loaded_vmcs);
7562 if (!vmm_exclusive)
7563 kvm_cpu_vmxoff();
a2fa3e9f 7564
15ad7146
AK		 7565 cpu = get_cpu();
7566 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7567 vmx->vcpu.cpu = cpu;
8b9cf98c 7568 err = vmx_vcpu_setup(vmx);
fb3f0f51 7569 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7570 put_cpu();
fb3f0f51
RR		 7571 if (err)
7572 goto free_vmcs;
a63cb560 7573 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7574 err = alloc_apic_access_page(kvm);
7575 if (err)
5e4a0b3c 7576 goto free_vmcs;
a63cb560 7577 }
fb3f0f51 7578
b927a3ce
SY		 7579 if (enable_ept) {
7580 if (!kvm->arch.ept_identity_map_addr)
7581 kvm->arch.ept_identity_map_addr =
7582 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7583 err = -ENOMEM;
b7ebfb05
SY		 7584 if (alloc_identity_pagetable(kvm) != 0)
7585 goto free_vmcs;
93ea5388
GN		 7586 if (!init_rmode_identity_map(kvm))
7587 goto free_vmcs;
b927a3ce 7588 }
b7ebfb05 7589
a9d30f33
NHE		 7590 vmx->nested.current_vmptr = -1ull;
7591 vmx->nested.current_vmcs12 = NULL;
7592
fb3f0f51
RR		 7593 return &vmx->vcpu;
7594
7595free_vmcs:
5f3fbc34 7596 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7597free_msrs:
fb3f0f51
RR		 7598 kfree(vmx->guest_msrs);
7599uninit_vcpu:
7600 kvm_vcpu_uninit(&vmx->vcpu);
7601free_vcpu:
cdbecfc3 7602 free_vpid(vmx);
a4770347 7603 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7604 return ERR_PTR(err);
6aa8b732
AK		 7605}
7606
002c7f7c
YS		 7607static void __init vmx_check_processor_compat(void *rtn)
7608{
7609 struct vmcs_config vmcs_conf;
7610
7611 *(int *)rtn = 0;
7612 if (setup_vmcs_config(&vmcs_conf) < 0)
7613 *(int *)rtn = -EIO;
7614 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7615 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7616 smp_processor_id());
7617 *(int *)rtn = -EIO;
7618 }
7619}
7620
67253af5
SY		 7621static int get_ept_level(void)
7622{
7623 return VMX_EPT_DEFAULT_GAW + 1;
7624}
7625
4b12f0de 7626static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7627{
4b12f0de
SY		 7628 u64 ret;
7629
522c68c4
SY		 7630 /* For VT-d and EPT combination
7631 * 1. MMIO: always map as UC
7632 * 2. EPT with VT-d:
7633 * a. VT-d without snooping control feature: can't guarantee the
7634 * result, try to trust guest.
7635 * b. VT-d with snooping control feature: snooping control feature of
7636 * VT-d engine can guarantee the cache correctness. Just set it
7637 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7638 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7639 * consistent with host MTRR
7640 */
4b12f0de
SY		 7641 if (is_mmio)
7642 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7643 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7644 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7645 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7646 else
522c68c4 7647 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7648 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7649
7650 return ret;
64d4d521
SY		 7651}
7652
17cc3935 7653static int vmx_get_lpage_level(void)
344f414f 7654{
878403b7
SY		 7655 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7656 return PT_DIRECTORY_LEVEL;
7657 else
7658 /* For shadow and EPT supported 1GB page */
7659 return PT_PDPE_LEVEL;
344f414f
JR		 7660}
7661
0e851880
SY		 7662static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7663{
4e47c7a6
SY		 7664 struct kvm_cpuid_entry2 *best;
7665 struct vcpu_vmx *vmx = to_vmx(vcpu);
7666 u32 exec_control;
7667
7668 vmx->rdtscp_enabled = false;
7669 if (vmx_rdtscp_supported()) {
7670 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7671 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7672 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7673 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7674 vmx->rdtscp_enabled = true;
7675 else {
7676 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7677 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7678 exec_control);
7679 }
7680 }
7681 }
ad756a16 7682
ad756a16
MJ		 7683 /* Exposing INVPCID only when PCID is exposed */
7684 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7685 if (vmx_invpcid_supported() &&
4f977045 7686 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7687 guest_cpuid_has_pcid(vcpu)) {
29282fde 7688 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7689 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7690 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7691 exec_control);
7692 } else {
29282fde
TI		 7693 if (cpu_has_secondary_exec_ctrls()) {
7694 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7695 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7696 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7697 exec_control);
7698 }
ad756a16 7699 if (best)
4f977045 7700 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7701 }
0e851880
SY		 7702}
7703
d4330ef2
JR		 7704static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7705{
7b8050f5
NHE		 7706 if (func == 1 && nested)
7707 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7708}
7709
25d92081
YZ		 7710static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7711 struct x86_exception *fault)
7712{
533558bc
JK		 7713 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7714 u32 exit_reason;
25d92081
YZ		 7715
7716 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7717 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7718 else
533558bc
JK		 7719 exit_reason = EXIT_REASON_EPT_VIOLATION;
7720 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7721 vmcs12->guest_physical_address = fault->address;
7722}
7723
155a97a3
NHE		 7724/* Callbacks for nested_ept_init_mmu_context: */
7725
7726static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7727{
7728 /* return the page table to be shadowed - in our case, EPT12 */
7729 return get_vmcs12(vcpu)->ept_pointer;
7730}
7731
8a3c1a33 7732static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7733{
8a3c1a33 7734 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7735 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7736
7737 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7738 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7739 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7740
7741 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7742}
7743
7744static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7745{
7746 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7747}
7748
feaf0c7d
GN		 7749static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7750 struct x86_exception *fault)
7751{
7752 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7753
7754 WARN_ON(!is_guest_mode(vcpu));
7755
7756 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7757 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7758 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7759 vmcs_read32(VM_EXIT_INTR_INFO),
7760 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7761 else
7762 kvm_inject_page_fault(vcpu, fault);
7763}
7764
f4124500
JK		 7765static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7766{
7767 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7768 struct vcpu_vmx *vmx = to_vmx(vcpu);
7769
7770 if (vcpu->arch.virtual_tsc_khz == 0)
7771 return;
7772
7773 /* Make sure short timeouts reliably trigger an immediate vmexit.
7774 * hrtimer_start does not guarantee this. */
7775 if (preemption_timeout <= 1) {
7776 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7777 return;
7778 }
7779
7780 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7781 preemption_timeout *= 1000000;
7782 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7783 hrtimer_start(&vmx->nested.preemption_timer,
7784 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7785}
7786
fe3ef05c
NHE		 7787/*
7788 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7789 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7790 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7791 * guest in a way that will both be appropriate to L1's requests, and our
7792 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7793 * function also has additional necessary side-effects, like setting various
7794 * vcpu->arch fields.
7795 */
7796static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7797{
7798 struct vcpu_vmx *vmx = to_vmx(vcpu);
7799 u32 exec_control;
7800
7801 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7802 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7803 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7804 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7805 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7806 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7807 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7808 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7809 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7810 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7811 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7812 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7813 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7814 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7815 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7816 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7817 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7818 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7819 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7820 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7821 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7822 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7823 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7824 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7825 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7826 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7827 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7828 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7829 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7830 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7831 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7832 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7833 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7834 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7835 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7836 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7837
7838 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7839 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7840 vmcs12->vm_entry_intr_info_field);
7841 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7842 vmcs12->vm_entry_exception_error_code);
7843 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7844 vmcs12->vm_entry_instruction_len);
7845 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7846 vmcs12->guest_interruptibility_info);
fe3ef05c 7847 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7848 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7849 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7850 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7851 vmcs12->guest_pending_dbg_exceptions);
7852 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7853 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7854
7855 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7856
f4124500
JK		 7857 exec_control = vmcs12->pin_based_vm_exec_control;
7858 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 7859 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
7860 PIN_BASED_POSTED_INTR);
f4124500 7861 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7862
f4124500
JK		 7863 vmx->nested.preemption_timer_expired = false;
7864 if (nested_cpu_has_preemption_timer(vmcs12))
7865 vmx_start_preemption_timer(vcpu);
0238ea91 7866
fe3ef05c
NHE		 7867 /*
7868 * Whether page-faults are trapped is determined by a combination of
7869 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7870 * If enable_ept, L0 doesn't care about page faults and we should
7871 * set all of these to L1's desires. However, if !enable_ept, L0 does
7872 * care about (at least some) page faults, and because it is not easy
7873 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7874 * to exit on each and every L2 page fault. This is done by setting
7875 * MASK=MATCH=0 and (see below) EB.PF=1.
7876 * Note that below we don't need special code to set EB.PF beyond the
7877 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7878 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7879 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7880 *
7881 * A problem with this approach (when !enable_ept) is that L1 may be
7882 * injected with more page faults than it asked for. This could have
7883 * caused problems, but in practice existing hypervisors don't care.
7884 * To fix this, we will need to emulate the PFEC checking (on the L1
7885 * page tables), using walk_addr(), when injecting PFs to L1.
7886 */
7887 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7888 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7889 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7890 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7891
7892 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7893 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7894 if (!vmx->rdtscp_enabled)
7895 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7896 /* Take the following fields only from vmcs12 */
696dfd95
PB		 7897 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7898 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
7899 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 7900 if (nested_cpu_has(vmcs12,
7901 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7902 exec_control |= vmcs12->secondary_vm_exec_control;
7903
7904 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7905 /*
7906 * Translate L1 physical address to host physical
7907 * address for vmcs02. Keep the page pinned, so this
7908 * physical address remains valid. We keep a reference
7909 * to it so we can release it later.
7910 */
7911 if (vmx->nested.apic_access_page) /* shouldn't happen */
7912 nested_release_page(vmx->nested.apic_access_page);
7913 vmx->nested.apic_access_page =
7914 nested_get_page(vcpu, vmcs12->apic_access_addr);
7915 /*
7916 * If translation failed, no matter: This feature asks
7917 * to exit when accessing the given address, and if it
7918 * can never be accessed, this feature won't do
7919 * anything anyway.
7920 */
7921 if (!vmx->nested.apic_access_page)
7922 exec_control &=
7923 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7924 else
7925 vmcs_write64(APIC_ACCESS_ADDR,
7926 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7927 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7928 exec_control |=
7929 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7930 vmcs_write64(APIC_ACCESS_ADDR,
7931 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7932 }
7933
7934 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7935 }
7936
7937
7938 /*
7939 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7940 * Some constant fields are set here by vmx_set_constant_host_state().
7941 * Other fields are different per CPU, and will be set later when
7942 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7943 */
a547c6db 7944 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7945
7946 /*
7947 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7948 * entry, but only if the current (host) sp changed from the value
7949 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7950 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7951 * here we just force the write to happen on entry.
7952 */
7953 vmx->host_rsp = 0;
7954
7955 exec_control = vmx_exec_control(vmx); /* L0's desires */
7956 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7957 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7958 exec_control &= ~CPU_BASED_TPR_SHADOW;
7959 exec_control |= vmcs12->cpu_based_vm_exec_control;
7960 /*
7961 * Merging of IO and MSR bitmaps not currently supported.
7962 * Rather, exit every time.
7963 */
7964 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7965 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7966 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7967
7968 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7969
7970 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7971 * bitwise-or of what L1 wants to trap for L2, and what we want to
7972 * trap. Note that CR0.TS also needs updating - we do this later.
7973 */
7974 update_exception_bitmap(vcpu);
7975 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7977
8049d651
NHE		 7978 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7979 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7980 * bits are further modified by vmx_set_efer() below.
7981 */
f4124500 7982 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7983
7984 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7985 * emulated by vmx_set_efer(), below.
7986 */
2961e876 7987 vm_entry_controls_init(vmx,
8049d651
NHE		 7988 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7989 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7990 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7991
44811c02 7992 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7993 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7994 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7995 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7996 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7997
7998
7999 set_cr4_guest_host_mask(vmx);
8000
36be0b9d
PB		 8001 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8002 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8003
27fc51b2
NHE		 8004 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8005 vmcs_write64(TSC_OFFSET,
8006 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8007 else
8008 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8009
8010 if (enable_vpid) {
8011 /*
8012 * Trivially support vpid by letting L2s share their parent
8013 * L1's vpid. TODO: move to a more elaborate solution, giving
8014 * each L2 its own vpid and exposing the vpid feature to L1.
8015 */
8016 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8017 vmx_flush_tlb(vcpu);
8018 }
8019
155a97a3
NHE		 8020 if (nested_cpu_has_ept(vmcs12)) {
8021 kvm_mmu_unload(vcpu);
8022 nested_ept_init_mmu_context(vcpu);
8023 }
8024
fe3ef05c
NHE		 8025 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8026 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8027 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8028 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8029 else
8030 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8031 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8032 vmx_set_efer(vcpu, vcpu->arch.efer);
8033
8034 /*
8035 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8036 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8037 * The CR0_READ_SHADOW is what L2 should have expected to read given
8038 * the specifications by L1; It's not enough to take
8039 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8040 * have more bits than L1 expected.
8041 */
8042 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8043 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8044
8045 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8046 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8047
8048 /* shadow page tables on either EPT or shadow page tables */
8049 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8050 kvm_mmu_reset_context(vcpu);
8051
feaf0c7d
GN		 8052 if (!enable_ept)
8053 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8054
3633cfc3
NHE		 8055 /*
8056 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8057 */
8058 if (enable_ept) {
8059 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8060 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8061 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8062 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8063 }
8064
fe3ef05c
NHE		 8065 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8066 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8067}
8068
cd232ad0
NHE		 8069/*
8070 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8071 * for running an L2 nested guest.
8072 */
8073static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8074{
8075 struct vmcs12 *vmcs12;
8076 struct vcpu_vmx *vmx = to_vmx(vcpu);
8077 int cpu;
8078 struct loaded_vmcs *vmcs02;
384bb783 8079 bool ia32e;
cd232ad0
NHE		 8080
8081 if (!nested_vmx_check_permission(vcpu) ||
8082 !nested_vmx_check_vmcs12(vcpu))
8083 return 1;
8084
8085 skip_emulated_instruction(vcpu);
8086 vmcs12 = get_vmcs12(vcpu);
8087
012f83cb
AG		 8088 if (enable_shadow_vmcs)
8089 copy_shadow_to_vmcs12(vmx);
8090
7c177938
NHE		 8091 /*
8092 * The nested entry process starts with enforcing various prerequisites
8093 * on vmcs12 as required by the Intel SDM, and act appropriately when
8094 * they fail: As the SDM explains, some conditions should cause the
8095 * instruction to fail, while others will cause the instruction to seem
8096 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8097 * To speed up the normal (success) code path, we should avoid checking
8098 * for misconfigurations which will anyway be caught by the processor
8099 * when using the merged vmcs02.
8100 */
8101 if (vmcs12->launch_state == launch) {
8102 nested_vmx_failValid(vcpu,
8103 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8104 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8105 return 1;
8106 }
8107
6dfacadd
JK		 8108 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8109 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8110 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8111 return 1;
8112 }
8113
7c177938 8114 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8115 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8116 /*TODO: Also verify bits beyond physical address width are 0*/
8117 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8118 return 1;
8119 }
8120
8121 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
bc39c4db 8122 !PAGE_ALIGNED(vmcs12->apic_access_addr)) {
7c177938
NHE		 8123 /*TODO: Also verify bits beyond physical address width are 0*/
8124 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8125 return 1;
8126 }
8127
8128 if (vmcs12->vm_entry_msr_load_count > 0 ||
8129 vmcs12->vm_exit_msr_load_count > 0 ||
8130 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8131 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8132 __func__);
7c177938
NHE		 8133 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8134 return 1;
8135 }
8136
8137 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8138 nested_vmx_true_procbased_ctls_low,
8139 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8140 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8141 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8142 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8143 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8144 !vmx_control_verify(vmcs12->vm_exit_controls,
8145 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8146 !vmx_control_verify(vmcs12->vm_entry_controls,
8147 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8148 {
8149 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8150 return 1;
8151 }
8152
8153 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8154 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8155 nested_vmx_failValid(vcpu,
8156 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8157 return 1;
8158 }
8159
92fbc7b1 8160 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8161 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8162 nested_vmx_entry_failure(vcpu, vmcs12,
8163 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8164 return 1;
8165 }
8166 if (vmcs12->vmcs_link_pointer != -1ull) {
8167 nested_vmx_entry_failure(vcpu, vmcs12,
8168 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8169 return 1;
8170 }
8171
384bb783 8172 /*
cb0c8cda 8173 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8174 * are performed on the field for the IA32_EFER MSR:
8175 * - Bits reserved in the IA32_EFER MSR must be 0.
8176 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8177 * the IA-32e mode guest VM-exit control. It must also be identical
8178 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8179 * CR0.PG) is 1.
8180 */
8181 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8182 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8183 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8184 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8185 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8186 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8187 nested_vmx_entry_failure(vcpu, vmcs12,
8188 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8189 return 1;
8190 }
8191 }
8192
8193 /*
8194 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8195 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8196 * the values of the LMA and LME bits in the field must each be that of
8197 * the host address-space size VM-exit control.
8198 */
8199 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8200 ia32e = (vmcs12->vm_exit_controls &
8201 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8202 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8203 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8204 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8205 nested_vmx_entry_failure(vcpu, vmcs12,
8206 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8207 return 1;
8208 }
8209 }
8210
7c177938
NHE		 8211 /*
8212 * We're finally done with prerequisite checking, and can start with
8213 * the nested entry.
8214 */
8215
cd232ad0
NHE		 8216 vmcs02 = nested_get_current_vmcs02(vmx);
8217 if (!vmcs02)
8218 return -ENOMEM;
8219
8220 enter_guest_mode(vcpu);
8221
8222 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8223
8224 cpu = get_cpu();
8225 vmx->loaded_vmcs = vmcs02;
8226 vmx_vcpu_put(vcpu);
8227 vmx_vcpu_load(vcpu, cpu);
8228 vcpu->cpu = cpu;
8229 put_cpu();
8230
36c3cc42
JK		 8231 vmx_segment_cache_clear(vmx);
8232
cd232ad0
NHE		 8233 vmcs12->launch_state = 1;
8234
8235 prepare_vmcs02(vcpu, vmcs12);
8236
6dfacadd
JK		 8237 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8238 return kvm_emulate_halt(vcpu);
8239
7af40ad3
JK		 8240 vmx->nested.nested_run_pending = 1;
8241
cd232ad0
NHE		 8242 /*
8243 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8244 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8245 * returned as far as L1 is concerned. It will only return (and set
8246 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8247 */
8248 return 1;
8249}
8250
4704d0be
NHE		 8251/*
8252 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8253 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8254 * This function returns the new value we should put in vmcs12.guest_cr0.
8255 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8256 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8257 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8258 * didn't trap the bit, because if L1 did, so would L0).
8259 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8260 * been modified by L2, and L1 knows it. So just leave the old value of
8261 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8262 * isn't relevant, because if L0 traps this bit it can set it to anything.
8263 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8264 * changed these bits, and therefore they need to be updated, but L0
8265 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8266 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8267 */
8268static inline unsigned long
8269vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8270{
8271 return
8272 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8273 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8274 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8275 vcpu->arch.cr0_guest_owned_bits));
8276}
8277
8278static inline unsigned long
8279vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8280{
8281 return
8282 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8283 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8284 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8285 vcpu->arch.cr4_guest_owned_bits));
8286}
8287
5f3d5799
JK		 8288static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8289 struct vmcs12 *vmcs12)
8290{
8291 u32 idt_vectoring;
8292 unsigned int nr;
8293
851eb667 8294 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8295 nr = vcpu->arch.exception.nr;
8296 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8297
8298 if (kvm_exception_is_soft(nr)) {
8299 vmcs12->vm_exit_instruction_len =
8300 vcpu->arch.event_exit_inst_len;
8301 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8302 } else
8303 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8304
8305 if (vcpu->arch.exception.has_error_code) {
8306 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8307 vmcs12->idt_vectoring_error_code =
8308 vcpu->arch.exception.error_code;
8309 }
8310
8311 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8312 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8313 vmcs12->idt_vectoring_info_field =
8314 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8315 } else if (vcpu->arch.interrupt.pending) {
8316 nr = vcpu->arch.interrupt.nr;
8317 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8318
8319 if (vcpu->arch.interrupt.soft) {
8320 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8321 vmcs12->vm_entry_instruction_len =
8322 vcpu->arch.event_exit_inst_len;
8323 } else
8324 idt_vectoring |= INTR_TYPE_EXT_INTR;
8325
8326 vmcs12->idt_vectoring_info_field = idt_vectoring;
8327 }
8328}
8329
b6b8a145
JK		 8330static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8331{
8332 struct vcpu_vmx *vmx = to_vmx(vcpu);
8333
f4124500
JK		 8334 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8335 vmx->nested.preemption_timer_expired) {
8336 if (vmx->nested.nested_run_pending)
8337 return -EBUSY;
8338 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8339 return 0;
8340 }
8341
b6b8a145 8342 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8343 if (vmx->nested.nested_run_pending ||
8344 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8345 return -EBUSY;
8346 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8347 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8348 INTR_INFO_VALID_MASK, 0);
8349 /*
8350 * The NMI-triggered VM exit counts as injection:
8351 * clear this one and block further NMIs.
8352 */
8353 vcpu->arch.nmi_pending = 0;
8354 vmx_set_nmi_mask(vcpu, true);
8355 return 0;
8356 }
8357
8358 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8359 nested_exit_on_intr(vcpu)) {
8360 if (vmx->nested.nested_run_pending)
8361 return -EBUSY;
8362 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8363 }
8364
8365 return 0;
8366}
8367
f4124500
JK		 8368static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8369{
8370 ktime_t remaining =
8371 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8372 u64 value;
8373
8374 if (ktime_to_ns(remaining) <= 0)
8375 return 0;
8376
8377 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8378 do_div(value, 1000000);
8379 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8380}
8381
4704d0be
NHE		 8382/*
8383 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8384 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8385 * and this function updates it to reflect the changes to the guest state while
8386 * L2 was running (and perhaps made some exits which were handled directly by L0
8387 * without going back to L1), and to reflect the exit reason.
8388 * Note that we do not have to copy here all VMCS fields, just those that
8389 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8390 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8391 * which already writes to vmcs12 directly.
8392 */
533558bc
JK		 8393static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8394 u32 exit_reason, u32 exit_intr_info,
8395 unsigned long exit_qualification)
4704d0be
NHE		 8396{
8397 /* update guest state fields: */
8398 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8399 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8400
8401 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8402 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8403 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8404 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8405
8406 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8407 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8408 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8409 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8410 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8411 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8412 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8413 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8414 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8415 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8416 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8417 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8418 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8419 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8420 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8421 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8422 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8423 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8424 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8425 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8426 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8427 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8428 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8429 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8430 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8431 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8432 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8433 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8434 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8435 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8436 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8437 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8438 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8439 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8440 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8441 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8442
4704d0be
NHE		 8443 vmcs12->guest_interruptibility_info =
8444 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8445 vmcs12->guest_pending_dbg_exceptions =
8446 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8447 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8448 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8449 else
8450 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8451
f4124500
JK		 8452 if (nested_cpu_has_preemption_timer(vmcs12)) {
8453 if (vmcs12->vm_exit_controls &
8454 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8455 vmcs12->vmx_preemption_timer_value =
8456 vmx_get_preemption_timer_value(vcpu);
8457 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8458 }
7854cbca 8459
3633cfc3
NHE		 8460 /*
8461 * In some cases (usually, nested EPT), L2 is allowed to change its
8462 * own CR3 without exiting. If it has changed it, we must keep it.
8463 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8464 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8465 *
8466 * Additionally, restore L2's PDPTR to vmcs12.
8467 */
8468 if (enable_ept) {
8469 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8470 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8471 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8472 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8473 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8474 }
8475
c18911a2
JK		 8476 vmcs12->vm_entry_controls =
8477 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8478 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8479
4704d0be
NHE		 8480 /* TODO: These cannot have changed unless we have MSR bitmaps and
8481 * the relevant bit asks not to trap the change */
8482 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8483 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8484 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8485 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8486 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8487 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8488 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8489 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8490 if (vmx_mpx_supported())
8491 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8492
8493 /* update exit information fields: */
8494
533558bc
JK		 8495 vmcs12->vm_exit_reason = exit_reason;
8496 vmcs12->exit_qualification = exit_qualification;
4704d0be 8497
533558bc 8498 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8499 if ((vmcs12->vm_exit_intr_info &
8500 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8501 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8502 vmcs12->vm_exit_intr_error_code =
8503 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8504 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8505 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8506 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8507
5f3d5799
JK		 8508 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8509 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8510 * instead of reading the real value. */
4704d0be 8511 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8512
8513 /*
8514 * Transfer the event that L0 or L1 may wanted to inject into
8515 * L2 to IDT_VECTORING_INFO_FIELD.
8516 */
8517 vmcs12_save_pending_event(vcpu, vmcs12);
8518 }
8519
8520 /*
8521 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8522 * preserved above and would only end up incorrectly in L1.
8523 */
8524 vcpu->arch.nmi_injected = false;
8525 kvm_clear_exception_queue(vcpu);
8526 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8527}
8528
8529/*
8530 * A part of what we need to when the nested L2 guest exits and we want to
8531 * run its L1 parent, is to reset L1's guest state to the host state specified
8532 * in vmcs12.
8533 * This function is to be called not only on normal nested exit, but also on
8534 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8535 * Failures During or After Loading Guest State").
8536 * This function should be called when the active VMCS is L1's (vmcs01).
8537 */
733568f9
JK		 8538static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8539 struct vmcs12 *vmcs12)
4704d0be 8540{
21feb4eb
ACL		 8541 struct kvm_segment seg;
8542
4704d0be
NHE		 8543 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8544 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8545 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8546 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8547 else
8548 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8549 vmx_set_efer(vcpu, vcpu->arch.efer);
8550
8551 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8552 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8553 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8554 /*
8555 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8556 * actually changed, because it depends on the current state of
8557 * fpu_active (which may have changed).
8558 * Note that vmx_set_cr0 refers to efer set above.
8559 */
9e3e4dbf 8560 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8561 /*
8562 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8563 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8564 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8565 */
8566 update_exception_bitmap(vcpu);
8567 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8568 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8569
8570 /*
8571 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8572 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8573 */
8574 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8575 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8576
29bf08f1 8577 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8578
4704d0be
NHE		 8579 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8580 kvm_mmu_reset_context(vcpu);
8581
feaf0c7d
GN		 8582 if (!enable_ept)
8583 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8584
4704d0be
NHE		 8585 if (enable_vpid) {
8586 /*
8587 * Trivially support vpid by letting L2s share their parent
8588 * L1's vpid. TODO: move to a more elaborate solution, giving
8589 * each L2 its own vpid and exposing the vpid feature to L1.
8590 */
8591 vmx_flush_tlb(vcpu);
8592 }
8593
8594
8595 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8596 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8597 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8598 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8599 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8600
36be0b9d
PB		 8601 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8602 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8603 vmcs_write64(GUEST_BNDCFGS, 0);
8604
44811c02 8605 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8606 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8607 vcpu->arch.pat = vmcs12->host_ia32_pat;
8608 }
4704d0be
NHE		 8609 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8610 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8611 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8612
21feb4eb
ACL		 8613 /* Set L1 segment info according to Intel SDM
8614 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8615 seg = (struct kvm_segment) {
8616 .base = 0,
8617 .limit = 0xFFFFFFFF,
8618 .selector = vmcs12->host_cs_selector,
8619 .type = 11,
8620 .present = 1,
8621 .s = 1,
8622 .g = 1
8623 };
8624 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8625 seg.l = 1;
8626 else
8627 seg.db = 1;
8628 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8629 seg = (struct kvm_segment) {
8630 .base = 0,
8631 .limit = 0xFFFFFFFF,
8632 .type = 3,
8633 .present = 1,
8634 .s = 1,
8635 .db = 1,
8636 .g = 1
8637 };
8638 seg.selector = vmcs12->host_ds_selector;
8639 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8640 seg.selector = vmcs12->host_es_selector;
8641 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8642 seg.selector = vmcs12->host_ss_selector;
8643 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8644 seg.selector = vmcs12->host_fs_selector;
8645 seg.base = vmcs12->host_fs_base;
8646 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8647 seg.selector = vmcs12->host_gs_selector;
8648 seg.base = vmcs12->host_gs_base;
8649 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8650 seg = (struct kvm_segment) {
205befd9 8651 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8652 .limit = 0x67,
8653 .selector = vmcs12->host_tr_selector,
8654 .type = 11,
8655 .present = 1
8656 };
8657 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8658
503cd0c5
JK		 8659 kvm_set_dr(vcpu, 7, 0x400);
8660 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8661}
8662
8663/*
8664 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8665 * and modify vmcs12 to make it see what it would expect to see there if
8666 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8667 */
533558bc
JK		 8668static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8669 u32 exit_intr_info,
8670 unsigned long exit_qualification)
4704d0be
NHE		 8671{
8672 struct vcpu_vmx *vmx = to_vmx(vcpu);
8673 int cpu;
8674 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8675
5f3d5799
JK		 8676 /* trying to cancel vmlaunch/vmresume is a bug */
8677 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8678
4704d0be 8679 leave_guest_mode(vcpu);
533558bc
JK		 8680 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8681 exit_qualification);
4704d0be 8682
77b0f5d6
BD		 8683 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8684 && nested_exit_intr_ack_set(vcpu)) {
8685 int irq = kvm_cpu_get_interrupt(vcpu);
8686 WARN_ON(irq < 0);
8687 vmcs12->vm_exit_intr_info = irq |
8688 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8689 }
8690
542060ea
JK		 8691 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8692 vmcs12->exit_qualification,
8693 vmcs12->idt_vectoring_info_field,
8694 vmcs12->vm_exit_intr_info,
8695 vmcs12->vm_exit_intr_error_code,
8696 KVM_ISA_VMX);
4704d0be
NHE		 8697
8698 cpu = get_cpu();
8699 vmx->loaded_vmcs = &vmx->vmcs01;
8700 vmx_vcpu_put(vcpu);
8701 vmx_vcpu_load(vcpu, cpu);
8702 vcpu->cpu = cpu;
8703 put_cpu();
8704
2961e876
GN		 8705 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8706 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8707 vmx_segment_cache_clear(vmx);
8708
4704d0be
NHE		 8709 /* if no vmcs02 cache requested, remove the one we used */
8710 if (VMCS02_POOL_SIZE == 0)
8711 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8712
8713 load_vmcs12_host_state(vcpu, vmcs12);
8714
27fc51b2 8715 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8716 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8717
8718 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8719 vmx->host_rsp = 0;
8720
8721 /* Unpin physical memory we referred to in vmcs02 */
8722 if (vmx->nested.apic_access_page) {
8723 nested_release_page(vmx->nested.apic_access_page);
8724 vmx->nested.apic_access_page = 0;
8725 }
8726
8727 /*
8728 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8729 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8730 * success or failure flag accordingly.
8731 */
8732 if (unlikely(vmx->fail)) {
8733 vmx->fail = 0;
8734 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8735 } else
8736 nested_vmx_succeed(vcpu);
012f83cb
AG		 8737 if (enable_shadow_vmcs)
8738 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8739
8740 /* in case we halted in L2 */
8741 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8742}
8743
42124925
JK		 8744/*
8745 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8746 */
8747static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8748{
8749 if (is_guest_mode(vcpu))
533558bc 8750 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8751 free_nested(to_vmx(vcpu));
8752}
8753
7c177938
NHE		 8754/*
8755 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8756 * 23.7 "VM-entry failures during or after loading guest state" (this also
8757 * lists the acceptable exit-reason and exit-qualification parameters).
8758 * It should only be called before L2 actually succeeded to run, and when
8759 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8760 */
8761static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8762 struct vmcs12 *vmcs12,
8763 u32 reason, unsigned long qualification)
8764{
8765 load_vmcs12_host_state(vcpu, vmcs12);
8766 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8767 vmcs12->exit_qualification = qualification;
8768 nested_vmx_succeed(vcpu);
012f83cb
AG		 8769 if (enable_shadow_vmcs)
8770 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8771}
8772
8a76d7f2
JR		 8773static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8774 struct x86_instruction_info *info,
8775 enum x86_intercept_stage stage)
8776{
8777 return X86EMUL_CONTINUE;
8778}
8779
cbdd1bea 8780static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8781 .cpu_has_kvm_support = cpu_has_kvm_support,
8782 .disabled_by_bios = vmx_disabled_by_bios,
8783 .hardware_setup = hardware_setup,
8784 .hardware_unsetup = hardware_unsetup,
002c7f7c 8785 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8786 .hardware_enable = hardware_enable,
8787 .hardware_disable = hardware_disable,
04547156 8788 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8789
8790 .vcpu_create = vmx_create_vcpu,
8791 .vcpu_free = vmx_free_vcpu,
04d2cc77 8792 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8793
04d2cc77 8794 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8795 .vcpu_load = vmx_vcpu_load,
8796 .vcpu_put = vmx_vcpu_put,
8797
c8639010 8798 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8799 .get_msr = vmx_get_msr,
8800 .set_msr = vmx_set_msr,
8801 .get_segment_base = vmx_get_segment_base,
8802 .get_segment = vmx_get_segment,
8803 .set_segment = vmx_set_segment,
2e4d2653 8804 .get_cpl = vmx_get_cpl,
6aa8b732 8805 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8806 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8807 .decache_cr3 = vmx_decache_cr3,
25c4c276 8808 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8809 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8810 .set_cr3 = vmx_set_cr3,
8811 .set_cr4 = vmx_set_cr4,
6aa8b732 8812 .set_efer = vmx_set_efer,
6aa8b732
AK		 8813 .get_idt = vmx_get_idt,
8814 .set_idt = vmx_set_idt,
8815 .get_gdt = vmx_get_gdt,
8816 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8817 .get_dr6 = vmx_get_dr6,
8818 .set_dr6 = vmx_set_dr6,
020df079 8819 .set_dr7 = vmx_set_dr7,
81908bf4 8820 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8821 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8822 .get_rflags = vmx_get_rflags,
8823 .set_rflags = vmx_set_rflags,
ebcbab4c 8824 .fpu_activate = vmx_fpu_activate,
02daab21 8825 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8826
8827 .tlb_flush = vmx_flush_tlb,
6aa8b732 8828
6aa8b732 8829 .run = vmx_vcpu_run,
6062d012 8830 .handle_exit = vmx_handle_exit,
6aa8b732 8831 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8832 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8833 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8834 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8835 .set_irq = vmx_inject_irq,
95ba8273 8836 .set_nmi = vmx_inject_nmi,
298101da 8837 .queue_exception = vmx_queue_exception,
b463a6f7 8838 .cancel_injection = vmx_cancel_injection,
78646121 8839 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8840 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8841 .get_nmi_mask = vmx_get_nmi_mask,
8842 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8843 .enable_nmi_window = enable_nmi_window,
8844 .enable_irq_window = enable_irq_window,
8845 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8846 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8847 .vm_has_apicv = vmx_vm_has_apicv,
8848 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8849 .hwapic_irr_update = vmx_hwapic_irr_update,
8850 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8851 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8852 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8853
cbc94022 8854 .set_tss_addr = vmx_set_tss_addr,
67253af5 8855 .get_tdp_level = get_ept_level,
4b12f0de 8856 .get_mt_mask = vmx_get_mt_mask,
229456fc 8857
586f9607 8858 .get_exit_info = vmx_get_exit_info,
586f9607 8859
17cc3935 8860 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8861
8862 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8863
8864 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8865 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8866
8867 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8868
8869 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8870
4051b188 8871 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8872 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8873 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8874 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8875 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8876 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8877
8878 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8879
8880 .check_intercept = vmx_check_intercept,
a547c6db 8881 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8882 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8883
8884 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8885};
8886
8887static int __init vmx_init(void)
8888{
8d14695f 8889 int r, i, msr;
26bb0981
AK		 8890
8891 rdmsrl_safe(MSR_EFER, &host_efer);
8892
8893 for (i = 0; i < NR_VMX_MSR; ++i)
8894 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8895
3e7c73e9 8896 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8897 if (!vmx_io_bitmap_a)
8898 return -ENOMEM;
8899
2106a548
GC		 8900 r = -ENOMEM;
8901
3e7c73e9 8902 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8903 if (!vmx_io_bitmap_b)
fdef3ad1 8904 goto out;
fdef3ad1 8905
5897297b 8906 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8907 if (!vmx_msr_bitmap_legacy)
25c5f225 8908 goto out1;
2106a548 8909
8d14695f
YZ		 8910 vmx_msr_bitmap_legacy_x2apic =
8911 (unsigned long *)__get_free_page(GFP_KERNEL);
8912 if (!vmx_msr_bitmap_legacy_x2apic)
8913 goto out2;
25c5f225 8914
5897297b 8915 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8916 if (!vmx_msr_bitmap_longmode)
8d14695f 8917 goto out3;
2106a548 8918
8d14695f
YZ		 8919 vmx_msr_bitmap_longmode_x2apic =
8920 (unsigned long *)__get_free_page(GFP_KERNEL);
8921 if (!vmx_msr_bitmap_longmode_x2apic)
8922 goto out4;
4607c2d7
AG		 8923 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8924 if (!vmx_vmread_bitmap)
8925 goto out5;
8926
8927 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8928 if (!vmx_vmwrite_bitmap)
8929 goto out6;
8930
8931 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8932 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 8933
fdef3ad1
HQ		 8934 /*
8935 * Allow direct access to the PC debug port (it is often used for I/O
8936 * delays, but the vmexits simply slow things down).
8937 */
3e7c73e9
AK		 8938 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8939 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8940
3e7c73e9 8941 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8942
5897297b
AK		 8943 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8944 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8945
2384d2b3
SY		 8946 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8947
0ee75bea
AK		 8948 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8949 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8950 if (r)
4607c2d7 8951 goto out7;
25c5f225 8952
8f536b76
ZY		 8953#ifdef CONFIG_KEXEC
8954 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8955 crash_vmclear_local_loaded_vmcss);
8956#endif
8957
5897297b
AK		 8958 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8959 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8960 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8961 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8962 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8963 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8964 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8965
8d14695f
YZ		 8966 memcpy(vmx_msr_bitmap_legacy_x2apic,
8967 vmx_msr_bitmap_legacy, PAGE_SIZE);
8968 memcpy(vmx_msr_bitmap_longmode_x2apic,
8969 vmx_msr_bitmap_longmode, PAGE_SIZE);
8970
01e439be 8971 if (enable_apicv) {
8d14695f
YZ		 8972 for (msr = 0x800; msr <= 0x8ff; msr++)
8973 vmx_disable_intercept_msr_read_x2apic(msr);
8974
8975 /* According SDM, in x2apic mode, the whole id reg is used.
8976 * But in KVM, it only use the highest eight bits. Need to
8977 * intercept it */
8978 vmx_enable_intercept_msr_read_x2apic(0x802);
8979 /* TMCCT */
8980 vmx_enable_intercept_msr_read_x2apic(0x839);
8981 /* TPR */
8982 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8983 /* EOI */
8984 vmx_disable_intercept_msr_write_x2apic(0x80b);
8985 /* SELF-IPI */
8986 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8987 }
fdef3ad1 8988
089d034e 8989 if (enable_ept) {
3f6d8c8a
XH		 8990 kvm_mmu_set_mask_ptes(0ull,
8991 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8992 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8993 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8994 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8995 kvm_enable_tdp();
8996 } else
8997 kvm_disable_tdp();
1439442c 8998
fdef3ad1
HQ		 8999 return 0;
9000
4607c2d7
AG		 9001out7:
9002 free_page((unsigned long)vmx_vmwrite_bitmap);
9003out6:
9004 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9005out5:
9006 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9007out4:
5897297b 9008 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9009out3:
9010 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9011out2:
5897297b 9012 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9013out1:
3e7c73e9 9014 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9015out:
3e7c73e9 9016 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9017 return r;
6aa8b732
AK		 9018}
9019
9020static void __exit vmx_exit(void)
9021{
8d14695f
YZ		 9022 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9023 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9024 free_page((unsigned long)vmx_msr_bitmap_legacy);
9025 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9026 free_page((unsigned long)vmx_io_bitmap_b);
9027 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9028 free_page((unsigned long)vmx_vmwrite_bitmap);
9029 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9030
8f536b76
ZY		 9031#ifdef CONFIG_KEXEC
9032 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
9033 synchronize_rcu();
9034#endif
9035
cb498ea2 9036 kvm_exit();
6aa8b732
AK		 9037}
9038
9039module_init(vmx_init)
9040module_exit(vmx_exit)
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