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KVM: nVMX: Don't advertise single context invalidation for invept
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
a9d30f33
NHE		 357
358 /* The guest-physical address of the current VMCS L1 keeps for L2 */
359 gpa_t current_vmptr;
360 /* The host-usable pointer to the above */
361 struct page *current_vmcs12_page;
362 struct vmcs12 *current_vmcs12;
8de48833 363 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 364 /*
365 * Indicates if the shadow vmcs must be updated with the
366 * data hold by vmcs12
367 */
368 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 369
370 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
371 struct list_head vmcs02_pool;
372 int vmcs02_num;
fe3ef05c 373 u64 vmcs01_tsc_offset;
644d711a
NHE		 374 /* L2 must run next, and mustn't decide to exit to L1. */
375 bool nested_run_pending;
fe3ef05c
NHE		 376 /*
377 * Guest pages referred to in vmcs02 with host-physical pointers, so
378 * we must keep them pinned while L2 runs.
379 */
380 struct page *apic_access_page;
b3897a49 381 u64 msr_ia32_feature_control;
f4124500
JK		 382
383 struct hrtimer preemption_timer;
384 bool preemption_timer_expired;
ec378aee
NHE		 385};
386
01e439be
YZ		 387#define POSTED_INTR_ON 0
388/* Posted-Interrupt Descriptor */
389struct pi_desc {
390 u32 pir[8]; /* Posted interrupt requested */
391 u32 control; /* bit 0 of control is outstanding notification bit */
392 u32 rsvd[7];
393} __aligned(64);
394
a20ed54d
YZ		 395static bool pi_test_and_set_on(struct pi_desc *pi_desc)
396{
397 return test_and_set_bit(POSTED_INTR_ON,
398 (unsigned long *)&pi_desc->control);
399}
400
401static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
402{
403 return test_and_clear_bit(POSTED_INTR_ON,
404 (unsigned long *)&pi_desc->control);
405}
406
407static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
408{
409 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
410}
411
a2fa3e9f 412struct vcpu_vmx {
fb3f0f51 413 struct kvm_vcpu vcpu;
313dbd49 414 unsigned long host_rsp;
29bd8a78 415 u8 fail;
69c73028 416 u8 cpl;
9d58b931 417 bool nmi_known_unmasked;
51aa01d1 418 u32 exit_intr_info;
1155f76a 419 u32 idt_vectoring_info;
6de12732 420 ulong rflags;
26bb0981 421 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 422 int nmsrs;
423 int save_nmsrs;
a547c6db 424 unsigned long host_idt_base;
a2fa3e9f 425#ifdef CONFIG_X86_64
44ea2b17
AK		 426 u64 msr_host_kernel_gs_base;
427 u64 msr_guest_kernel_gs_base;
a2fa3e9f 428#endif
2961e876
GN		 429 u32 vm_entry_controls_shadow;
430 u32 vm_exit_controls_shadow;
d462b819
NHE		 431 /*
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
435 */
436 struct loaded_vmcs vmcs01;
437 struct loaded_vmcs *loaded_vmcs;
438 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 439 struct msr_autoload {
440 unsigned nr;
441 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
442 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
443 } msr_autoload;
a2fa3e9f
GH		 444 struct {
445 int loaded;
446 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 447#ifdef CONFIG_X86_64
448 u16 ds_sel, es_sel;
449#endif
152d3f2f
LV		 450 int gs_ldt_reload_needed;
451 int fs_reload_needed;
da8999d3 452 u64 msr_host_bndcfgs;
d77c26fc 453 } host_state;
9c8cba37 454 struct {
7ffd92c5 455 int vm86_active;
78ac8b47 456 ulong save_rflags;
f5f7b2fe
AK		 457 struct kvm_segment segs[8];
458 } rmode;
459 struct {
460 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 461 struct kvm_save_segment {
462 u16 selector;
463 unsigned long base;
464 u32 limit;
465 u32 ar;
f5f7b2fe 466 } seg[8];
2fb92db1 467 } segment_cache;
2384d2b3 468 int vpid;
04fa4d32 469 bool emulation_required;
3b86cd99
JK		 470
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked;
473 ktime_t entry_time;
474 s64 vnmi_blocked_time;
a0861c02 475 u32 exit_reason;
4e47c7a6
SY		 476
477 bool rdtscp_enabled;
ec378aee 478
01e439be
YZ		 479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc;
481
ec378aee
NHE		 482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested;
a2fa3e9f
GH		 484};
485
2fb92db1
AK		 486enum segment_cache_field {
487 SEG_FIELD_SEL = 0,
488 SEG_FIELD_BASE = 1,
489 SEG_FIELD_LIMIT = 2,
490 SEG_FIELD_AR = 3,
491
492 SEG_FIELD_NR = 4
493};
494
a2fa3e9f
GH		 495static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
496{
fb3f0f51 497 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 498}
499
22bd0358
NHE		 500#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
504
4607c2d7
AG		 505
506static const unsigned long shadow_read_only_fields[] = {
507 /*
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
518 */
519 VM_EXIT_REASON,
520 VM_EXIT_INTR_INFO,
521 VM_EXIT_INSTRUCTION_LEN,
522 IDT_VECTORING_INFO_FIELD,
523 IDT_VECTORING_ERROR_CODE,
524 VM_EXIT_INTR_ERROR_CODE,
525 EXIT_QUALIFICATION,
526 GUEST_LINEAR_ADDRESS,
527 GUEST_PHYSICAL_ADDRESS
528};
529static const int max_shadow_read_only_fields =
530 ARRAY_SIZE(shadow_read_only_fields);
531
532static const unsigned long shadow_read_write_fields[] = {
533 GUEST_RIP,
534 GUEST_RSP,
535 GUEST_CR0,
536 GUEST_CR3,
537 GUEST_CR4,
538 GUEST_INTERRUPTIBILITY_INFO,
539 GUEST_RFLAGS,
540 GUEST_CS_SELECTOR,
541 GUEST_CS_AR_BYTES,
542 GUEST_CS_LIMIT,
543 GUEST_CS_BASE,
544 GUEST_ES_BASE,
36be0b9d 545 GUEST_BNDCFGS,
4607c2d7
AG		 546 CR0_GUEST_HOST_MASK,
547 CR0_READ_SHADOW,
548 CR4_READ_SHADOW,
549 TSC_OFFSET,
550 EXCEPTION_BITMAP,
551 CPU_BASED_VM_EXEC_CONTROL,
552 VM_ENTRY_EXCEPTION_ERROR_CODE,
553 VM_ENTRY_INTR_INFO_FIELD,
554 VM_ENTRY_INSTRUCTION_LEN,
555 VM_ENTRY_EXCEPTION_ERROR_CODE,
556 HOST_FS_BASE,
557 HOST_GS_BASE,
558 HOST_FS_SELECTOR,
559 HOST_GS_SELECTOR
560};
561static const int max_shadow_read_write_fields =
562 ARRAY_SIZE(shadow_read_write_fields);
563
772e0318 564static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 565 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
566 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
567 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
568 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
569 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
570 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
571 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
572 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
573 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
574 FIELD(HOST_ES_SELECTOR, host_es_selector),
575 FIELD(HOST_CS_SELECTOR, host_cs_selector),
576 FIELD(HOST_SS_SELECTOR, host_ss_selector),
577 FIELD(HOST_DS_SELECTOR, host_ds_selector),
578 FIELD(HOST_FS_SELECTOR, host_fs_selector),
579 FIELD(HOST_GS_SELECTOR, host_gs_selector),
580 FIELD(HOST_TR_SELECTOR, host_tr_selector),
581 FIELD64(IO_BITMAP_A, io_bitmap_a),
582 FIELD64(IO_BITMAP_B, io_bitmap_b),
583 FIELD64(MSR_BITMAP, msr_bitmap),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
587 FIELD64(TSC_OFFSET, tsc_offset),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
589 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
590 FIELD64(EPT_POINTER, ept_pointer),
591 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
592 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
593 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
594 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
595 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
597 FIELD64(GUEST_PDPTR0, guest_pdptr0),
598 FIELD64(GUEST_PDPTR1, guest_pdptr1),
599 FIELD64(GUEST_PDPTR2, guest_pdptr2),
600 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 601 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 602 FIELD64(HOST_IA32_PAT, host_ia32_pat),
603 FIELD64(HOST_IA32_EFER, host_ia32_efer),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
607 FIELD(EXCEPTION_BITMAP, exception_bitmap),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
610 FIELD(CR3_TARGET_COUNT, cr3_target_count),
611 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
612 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
614 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
619 FIELD(TPR_THRESHOLD, tpr_threshold),
620 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
621 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
622 FIELD(VM_EXIT_REASON, vm_exit_reason),
623 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
624 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
625 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
626 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
627 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
628 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
629 FIELD(GUEST_ES_LIMIT, guest_es_limit),
630 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
631 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
632 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
633 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
634 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
635 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
636 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
637 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
638 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
639 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
640 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
641 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
642 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
643 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
644 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
645 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
646 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
648 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
649 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
650 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 651 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 652 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
653 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
654 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
655 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
656 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
657 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
658 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
659 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
660 FIELD(EXIT_QUALIFICATION, exit_qualification),
661 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
662 FIELD(GUEST_CR0, guest_cr0),
663 FIELD(GUEST_CR3, guest_cr3),
664 FIELD(GUEST_CR4, guest_cr4),
665 FIELD(GUEST_ES_BASE, guest_es_base),
666 FIELD(GUEST_CS_BASE, guest_cs_base),
667 FIELD(GUEST_SS_BASE, guest_ss_base),
668 FIELD(GUEST_DS_BASE, guest_ds_base),
669 FIELD(GUEST_FS_BASE, guest_fs_base),
670 FIELD(GUEST_GS_BASE, guest_gs_base),
671 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
672 FIELD(GUEST_TR_BASE, guest_tr_base),
673 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
674 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
675 FIELD(GUEST_DR7, guest_dr7),
676 FIELD(GUEST_RSP, guest_rsp),
677 FIELD(GUEST_RIP, guest_rip),
678 FIELD(GUEST_RFLAGS, guest_rflags),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
680 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
681 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
682 FIELD(HOST_CR0, host_cr0),
683 FIELD(HOST_CR3, host_cr3),
684 FIELD(HOST_CR4, host_cr4),
685 FIELD(HOST_FS_BASE, host_fs_base),
686 FIELD(HOST_GS_BASE, host_gs_base),
687 FIELD(HOST_TR_BASE, host_tr_base),
688 FIELD(HOST_GDTR_BASE, host_gdtr_base),
689 FIELD(HOST_IDTR_BASE, host_idtr_base),
690 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
691 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
692 FIELD(HOST_RSP, host_rsp),
693 FIELD(HOST_RIP, host_rip),
694};
695static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
696
697static inline short vmcs_field_to_offset(unsigned long field)
698{
699 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
700 return -1;
701 return vmcs_field_to_offset_table[field];
702}
703
a9d30f33
NHE		 704static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
705{
706 return to_vmx(vcpu)->nested.current_vmcs12;
707}
708
709static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
710{
711 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 712 if (is_error_page(page))
a9d30f33 713 return NULL;
32cad84f 714
a9d30f33
NHE		 715 return page;
716}
717
718static void nested_release_page(struct page *page)
719{
720 kvm_release_page_dirty(page);
721}
722
723static void nested_release_page_clean(struct page *page)
724{
725 kvm_release_page_clean(page);
726}
727
bfd0a56b 728static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 729static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 730static void kvm_cpu_vmxon(u64 addr);
731static void kvm_cpu_vmxoff(void);
93c4adc7 732static bool vmx_mpx_supported(void);
776e58ea 733static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 734static void vmx_set_segment(struct kvm_vcpu *vcpu,
735 struct kvm_segment *var, int seg);
736static void vmx_get_segment(struct kvm_vcpu *vcpu,
737 struct kvm_segment *var, int seg);
d99e4152
GN		 738static bool guest_state_valid(struct kvm_vcpu *vcpu);
739static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 740static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 741static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 742static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
36be0b9d 743static bool vmx_mpx_supported(void);
75880a01 744
6aa8b732
AK		 745static DEFINE_PER_CPU(struct vmcs *, vmxarea);
746static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 747/*
748 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
749 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
750 */
751static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 752static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 753
3e7c73e9
AK		 754static unsigned long *vmx_io_bitmap_a;
755static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 756static unsigned long *vmx_msr_bitmap_legacy;
757static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 758static unsigned long *vmx_msr_bitmap_legacy_x2apic;
759static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 760static unsigned long *vmx_vmread_bitmap;
761static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 762
110312c8 763static bool cpu_has_load_ia32_efer;
8bf00a52 764static bool cpu_has_load_perf_global_ctrl;
110312c8 765
2384d2b3
SY		 766static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
767static DEFINE_SPINLOCK(vmx_vpid_lock);
768
1c3d14fe 769static struct vmcs_config {
6aa8b732
AK		 770 int size;
771 int order;
772 u32 revision_id;
1c3d14fe
YS		 773 u32 pin_based_exec_ctrl;
774 u32 cpu_based_exec_ctrl;
f78e0e2e 775 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 776 u32 vmexit_ctrl;
777 u32 vmentry_ctrl;
778} vmcs_config;
6aa8b732 779
efff9e53 780static struct vmx_capability {
d56f546d
SY		 781 u32 ept;
782 u32 vpid;
783} vmx_capability;
784
6aa8b732
AK		 785#define VMX_SEGMENT_FIELD(seg) \
786 [VCPU_SREG_##seg] = { \
787 .selector = GUEST_##seg##_SELECTOR, \
788 .base = GUEST_##seg##_BASE, \
789 .limit = GUEST_##seg##_LIMIT, \
790 .ar_bytes = GUEST_##seg##_AR_BYTES, \
791 }
792
772e0318 793static const struct kvm_vmx_segment_field {
6aa8b732
AK		 794 unsigned selector;
795 unsigned base;
796 unsigned limit;
797 unsigned ar_bytes;
798} kvm_vmx_segment_fields[] = {
799 VMX_SEGMENT_FIELD(CS),
800 VMX_SEGMENT_FIELD(DS),
801 VMX_SEGMENT_FIELD(ES),
802 VMX_SEGMENT_FIELD(FS),
803 VMX_SEGMENT_FIELD(GS),
804 VMX_SEGMENT_FIELD(SS),
805 VMX_SEGMENT_FIELD(TR),
806 VMX_SEGMENT_FIELD(LDTR),
807};
808
26bb0981
AK		 809static u64 host_efer;
810
6de4f3ad
AK		 811static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
812
4d56c8a7 813/*
8c06585d 814 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 815 * away by decrementing the array size.
816 */
6aa8b732 817static const u32 vmx_msr_index[] = {
05b3e0c2 818#ifdef CONFIG_X86_64
44ea2b17 819 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 820#endif
8c06585d 821 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 822};
9d8f549d 823#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 824
31299944 825static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 826{
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
828 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 829 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 830}
831
31299944 832static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 833{
834 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
835 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 836 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 837}
838
31299944 839static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 843 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 844}
845
31299944 846static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 847{
848 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
849 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
850}
851
31299944 852static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 853{
854 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
855 INTR_INFO_VALID_MASK)) ==
856 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
857}
858
31299944 859static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 860{
04547156 861 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 862}
863
31299944 864static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 865{
04547156 866 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 867}
868
31299944 869static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 870{
04547156 871 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 872}
873
31299944 874static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 875{
04547156
SY		 876 return vmcs_config.cpu_based_exec_ctrl &
877 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 878}
879
774ead3a 880static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 881{
04547156
SY		 882 return vmcs_config.cpu_based_2nd_exec_ctrl &
883 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
884}
885
8d14695f
YZ		 886static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
887{
888 return vmcs_config.cpu_based_2nd_exec_ctrl &
889 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
890}
891
83d4c286
YZ		 892static inline bool cpu_has_vmx_apic_register_virt(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_APIC_REGISTER_VIRT;
896}
897
c7c9c56c
YZ		 898static inline bool cpu_has_vmx_virtual_intr_delivery(void)
899{
900 return vmcs_config.cpu_based_2nd_exec_ctrl &
901 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
902}
903
01e439be
YZ		 904static inline bool cpu_has_vmx_posted_intr(void)
905{
906 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
907}
908
909static inline bool cpu_has_vmx_apicv(void)
910{
911 return cpu_has_vmx_apic_register_virt() &&
912 cpu_has_vmx_virtual_intr_delivery() &&
913 cpu_has_vmx_posted_intr();
914}
915
04547156
SY		 916static inline bool cpu_has_vmx_flexpriority(void)
917{
918 return cpu_has_vmx_tpr_shadow() &&
919 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 920}
921
e799794e
MT		 922static inline bool cpu_has_vmx_ept_execute_only(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 925}
926
927static inline bool cpu_has_vmx_eptp_uncacheable(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 930}
931
932static inline bool cpu_has_vmx_eptp_writeback(void)
933{
31299944 934 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 935}
936
937static inline bool cpu_has_vmx_ept_2m_page(void)
938{
31299944 939 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 940}
941
878403b7
SY		 942static inline bool cpu_has_vmx_ept_1g_page(void)
943{
31299944 944 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 945}
946
4bc9b982
SY		 947static inline bool cpu_has_vmx_ept_4levels(void)
948{
949 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
950}
951
83c3a331
XH		 952static inline bool cpu_has_vmx_ept_ad_bits(void)
953{
954 return vmx_capability.ept & VMX_EPT_AD_BIT;
955}
956
31299944 957static inline bool cpu_has_vmx_invept_context(void)
d56f546d 958{
31299944 959 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 960}
961
31299944 962static inline bool cpu_has_vmx_invept_global(void)
d56f546d 963{
31299944 964 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 965}
966
518c8aee
GJ		 967static inline bool cpu_has_vmx_invvpid_single(void)
968{
969 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
970}
971
b9d762fa
GJ		 972static inline bool cpu_has_vmx_invvpid_global(void)
973{
974 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
975}
976
31299944 977static inline bool cpu_has_vmx_ept(void)
d56f546d 978{
04547156
SY		 979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 981}
982
31299944 983static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 984{
985 return vmcs_config.cpu_based_2nd_exec_ctrl &
986 SECONDARY_EXEC_UNRESTRICTED_GUEST;
987}
988
31299944 989static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 990{
991 return vmcs_config.cpu_based_2nd_exec_ctrl &
992 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
993}
994
31299944 995static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 996{
6d3e435e 997 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 998}
999
31299944 1000static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1001{
04547156
SY		 1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1004}
1005
31299944 1006static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1007{
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_RDTSCP;
1010}
1011
ad756a16
MJ		 1012static inline bool cpu_has_vmx_invpcid(void)
1013{
1014 return vmcs_config.cpu_based_2nd_exec_ctrl &
1015 SECONDARY_EXEC_ENABLE_INVPCID;
1016}
1017
31299944 1018static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1019{
1020 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021}
1022
f5f48ee1
SY		 1023static inline bool cpu_has_vmx_wbinvd_exit(void)
1024{
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_WBINVD_EXITING;
1027}
1028
abc4fc58
AG		 1029static inline bool cpu_has_vmx_shadow_vmcs(void)
1030{
1031 u64 vmx_msr;
1032 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033 /* check if the cpu supports writing r/o exit information fields */
1034 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035 return false;
1036
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_SHADOW_VMCS;
1039}
1040
04547156
SY		 1041static inline bool report_flexpriority(void)
1042{
1043 return flexpriority_enabled;
1044}
1045
fe3ef05c
NHE		 1046static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047{
1048 return vmcs12->cpu_based_vm_exec_control & bit;
1049}
1050
1051static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052{
1053 return (vmcs12->cpu_based_vm_exec_control &
1054 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055 (vmcs12->secondary_vm_exec_control & bit);
1056}
1057
f5c4368f 1058static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1059{
1060 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061}
1062
f4124500
JK		 1063static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064{
1065 return vmcs12->pin_based_vm_exec_control &
1066 PIN_BASED_VMX_PREEMPTION_TIMER;
1067}
1068
155a97a3
NHE		 1069static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070{
1071 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072}
1073
644d711a
NHE		 1074static inline bool is_exception(u32 intr_info)
1075{
1076 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078}
1079
533558bc
JK		 1080static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081 u32 exit_intr_info,
1082 unsigned long exit_qualification);
7c177938
NHE		 1083static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084 struct vmcs12 *vmcs12,
1085 u32 reason, unsigned long qualification);
1086
8b9cf98c 1087static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1088{
1089 int i;
1090
a2fa3e9f 1091 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1092 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1093 return i;
1094 return -1;
1095}
1096
2384d2b3
SY		 1097static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098{
1099 struct {
1100 u64 vpid : 16;
1101 u64 rsvd : 48;
1102 u64 gva;
1103 } operand = { vpid, 0, gva };
1104
4ecac3fd 1105 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1106 /* CF==1 or ZF==1 --> rc = -1 */
1107 "; ja 1f ; ud2 ; 1:"
1108 : : "a"(&operand), "c"(ext) : "cc", "memory");
1109}
1110
1439442c
SY		 1111static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112{
1113 struct {
1114 u64 eptp, gpa;
1115 } operand = {eptp, gpa};
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1118 /* CF==1 or ZF==1 --> rc = -1 */
1119 "; ja 1f ; ud2 ; 1:\n"
1120 : : "a" (&operand), "c" (ext) : "cc", "memory");
1121}
1122
26bb0981 1123static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1124{
1125 int i;
1126
8b9cf98c 1127 i = __find_msr_index(vmx, msr);
a75beee6 1128 if (i >= 0)
a2fa3e9f 1129 return &vmx->guest_msrs[i];
8b6d44c7 1130 return NULL;
7725f0ba
AK		 1131}
1132
6aa8b732
AK		 1133static void vmcs_clear(struct vmcs *vmcs)
1134{
1135 u64 phys_addr = __pa(vmcs);
1136 u8 error;
1137
4ecac3fd 1138 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1139 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1140 : "cc", "memory");
1141 if (error)
1142 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143 vmcs, phys_addr);
1144}
1145
d462b819
NHE		 1146static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147{
1148 vmcs_clear(loaded_vmcs->vmcs);
1149 loaded_vmcs->cpu = -1;
1150 loaded_vmcs->launched = 0;
1151}
1152
7725b894
DX		 1153static void vmcs_load(struct vmcs *vmcs)
1154{
1155 u64 phys_addr = __pa(vmcs);
1156 u8 error;
1157
1158 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1159 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1160 : "cc", "memory");
1161 if (error)
2844d849 1162 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1163 vmcs, phys_addr);
1164}
1165
8f536b76
ZY		 1166#ifdef CONFIG_KEXEC
1167/*
1168 * This bitmap is used to indicate whether the vmclear
1169 * operation is enabled on all cpus. All disabled by
1170 * default.
1171 */
1172static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174static inline void crash_enable_local_vmclear(int cpu)
1175{
1176 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177}
1178
1179static inline void crash_disable_local_vmclear(int cpu)
1180{
1181 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182}
1183
1184static inline int crash_local_vmclear_enabled(int cpu)
1185{
1186 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187}
1188
1189static void crash_vmclear_local_loaded_vmcss(void)
1190{
1191 int cpu = raw_smp_processor_id();
1192 struct loaded_vmcs *v;
1193
1194 if (!crash_local_vmclear_enabled(cpu))
1195 return;
1196
1197 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198 loaded_vmcss_on_cpu_link)
1199 vmcs_clear(v->vmcs);
1200}
1201#else
1202static inline void crash_enable_local_vmclear(int cpu) { }
1203static inline void crash_disable_local_vmclear(int cpu) { }
1204#endif /* CONFIG_KEXEC */
1205
d462b819 1206static void __loaded_vmcs_clear(void *arg)
6aa8b732 1207{
d462b819 1208 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1209 int cpu = raw_smp_processor_id();
6aa8b732 1210
d462b819
NHE		 1211 if (loaded_vmcs->cpu != cpu)
1212 return; /* vcpu migration can race with cpu offline */
1213 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1214 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1215 crash_disable_local_vmclear(cpu);
d462b819 1216 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1217
1218 /*
1219 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220 * is before setting loaded_vmcs->vcpu to -1 which is done in
1221 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222 * then adds the vmcs into percpu list before it is deleted.
1223 */
1224 smp_wmb();
1225
d462b819 1226 loaded_vmcs_init(loaded_vmcs);
8f536b76 1227 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1228}
1229
d462b819 1230static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1231{
e6c7d321
XG		 1232 int cpu = loaded_vmcs->cpu;
1233
1234 if (cpu != -1)
1235 smp_call_function_single(cpu,
1236 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1237}
1238
1760dd49 1239static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1240{
1241 if (vmx->vpid == 0)
1242 return;
1243
518c8aee
GJ		 1244 if (cpu_has_vmx_invvpid_single())
1245 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1246}
1247
b9d762fa
GJ		 1248static inline void vpid_sync_vcpu_global(void)
1249{
1250 if (cpu_has_vmx_invvpid_global())
1251 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252}
1253
1254static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255{
1256 if (cpu_has_vmx_invvpid_single())
1760dd49 1257 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1258 else
1259 vpid_sync_vcpu_global();
1260}
1261
1439442c
SY		 1262static inline void ept_sync_global(void)
1263{
1264 if (cpu_has_vmx_invept_global())
1265 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266}
1267
1268static inline void ept_sync_context(u64 eptp)
1269{
089d034e 1270 if (enable_ept) {
1439442c
SY		 1271 if (cpu_has_vmx_invept_context())
1272 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273 else
1274 ept_sync_global();
1275 }
1276}
1277
96304217 1278static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1279{
5e520e62 1280 unsigned long value;
6aa8b732 1281
5e520e62
AK		 1282 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1284 return value;
1285}
1286
96304217 1287static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1288{
1289 return vmcs_readl(field);
1290}
1291
96304217 1292static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1293{
1294 return vmcs_readl(field);
1295}
1296
96304217 1297static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1298{
05b3e0c2 1299#ifdef CONFIG_X86_64
6aa8b732
AK		 1300 return vmcs_readl(field);
1301#else
1302 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303#endif
1304}
1305
e52de1b8
AK		 1306static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307{
1308 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310 dump_stack();
1311}
1312
6aa8b732
AK		 1313static void vmcs_writel(unsigned long field, unsigned long value)
1314{
1315 u8 error;
1316
4ecac3fd 1317 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1318 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1319 if (unlikely(error))
1320 vmwrite_error(field, value);
6aa8b732
AK		 1321}
1322
1323static void vmcs_write16(unsigned long field, u16 value)
1324{
1325 vmcs_writel(field, value);
1326}
1327
1328static void vmcs_write32(unsigned long field, u32 value)
1329{
1330 vmcs_writel(field, value);
1331}
1332
1333static void vmcs_write64(unsigned long field, u64 value)
1334{
6aa8b732 1335 vmcs_writel(field, value);
7682f2d0 1336#ifndef CONFIG_X86_64
6aa8b732
AK		 1337 asm volatile ("");
1338 vmcs_writel(field+1, value >> 32);
1339#endif
1340}
1341
2ab455cc
AL		 1342static void vmcs_clear_bits(unsigned long field, u32 mask)
1343{
1344 vmcs_writel(field, vmcs_readl(field) & ~mask);
1345}
1346
1347static void vmcs_set_bits(unsigned long field, u32 mask)
1348{
1349 vmcs_writel(field, vmcs_readl(field) | mask);
1350}
1351
2961e876
GN		 1352static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353{
1354 vmcs_write32(VM_ENTRY_CONTROLS, val);
1355 vmx->vm_entry_controls_shadow = val;
1356}
1357
1358static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359{
1360 if (vmx->vm_entry_controls_shadow != val)
1361 vm_entry_controls_init(vmx, val);
1362}
1363
1364static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365{
1366 return vmx->vm_entry_controls_shadow;
1367}
1368
1369
1370static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371{
1372 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373}
1374
1375static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376{
1377 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378}
1379
1380static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381{
1382 vmcs_write32(VM_EXIT_CONTROLS, val);
1383 vmx->vm_exit_controls_shadow = val;
1384}
1385
1386static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387{
1388 if (vmx->vm_exit_controls_shadow != val)
1389 vm_exit_controls_init(vmx, val);
1390}
1391
1392static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393{
1394 return vmx->vm_exit_controls_shadow;
1395}
1396
1397
1398static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399{
1400 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401}
1402
1403static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404{
1405 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406}
1407
2fb92db1
AK		 1408static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409{
1410 vmx->segment_cache.bitmask = 0;
1411}
1412
1413static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414 unsigned field)
1415{
1416 bool ret;
1417 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421 vmx->segment_cache.bitmask = 0;
1422 }
1423 ret = vmx->segment_cache.bitmask & mask;
1424 vmx->segment_cache.bitmask |= mask;
1425 return ret;
1426}
1427
1428static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429{
1430 u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434 return *p;
1435}
1436
1437static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438{
1439 ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443 return *p;
1444}
1445
1446static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447{
1448 u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452 return *p;
1453}
1454
1455static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456{
1457 u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461 return *p;
1462}
1463
abd3f2d6
AK		 1464static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465{
1466 u32 eb;
1467
fd7373cc
JK		 1468 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470 if ((vcpu->guest_debug &
1471 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473 eb |= 1u << BP_VECTOR;
7ffd92c5 1474 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1475 eb = ~0;
089d034e 1476 if (enable_ept)
1439442c 1477 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1478 if (vcpu->fpu_active)
1479 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1480
1481 /* When we are running a nested L2 guest and L1 specified for it a
1482 * certain exception bitmap, we must trap the same exceptions and pass
1483 * them to L1. When running L2, we will only handle the exceptions
1484 * specified above if L1 did not want them.
1485 */
1486 if (is_guest_mode(vcpu))
1487 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
abd3f2d6
AK		 1489 vmcs_write32(EXCEPTION_BITMAP, eb);
1490}
1491
2961e876
GN		 1492static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493 unsigned long entry, unsigned long exit)
8bf00a52 1494{
2961e876
GN		 1495 vm_entry_controls_clearbit(vmx, entry);
1496 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1497}
1498
61d2ef2c
AK		 1499static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500{
1501 unsigned i;
1502 struct msr_autoload *m = &vmx->msr_autoload;
1503
8bf00a52
GN		 1504 switch (msr) {
1505 case MSR_EFER:
1506 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1507 clear_atomic_switch_msr_special(vmx,
1508 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1509 VM_EXIT_LOAD_IA32_EFER);
1510 return;
1511 }
1512 break;
1513 case MSR_CORE_PERF_GLOBAL_CTRL:
1514 if (cpu_has_load_perf_global_ctrl) {
2961e876 1515 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1516 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518 return;
1519 }
1520 break;
110312c8
AK		 1521 }
1522
61d2ef2c
AK		 1523 for (i = 0; i < m->nr; ++i)
1524 if (m->guest[i].index == msr)
1525 break;
1526
1527 if (i == m->nr)
1528 return;
1529 --m->nr;
1530 m->guest[i] = m->guest[m->nr];
1531 m->host[i] = m->host[m->nr];
1532 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534}
1535
2961e876
GN		 1536static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537 unsigned long entry, unsigned long exit,
1538 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539 u64 guest_val, u64 host_val)
8bf00a52
GN		 1540{
1541 vmcs_write64(guest_val_vmcs, guest_val);
1542 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1543 vm_entry_controls_setbit(vmx, entry);
1544 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1545}
1546
61d2ef2c
AK		 1547static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548 u64 guest_val, u64 host_val)
1549{
1550 unsigned i;
1551 struct msr_autoload *m = &vmx->msr_autoload;
1552
8bf00a52
GN		 1553 switch (msr) {
1554 case MSR_EFER:
1555 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1556 add_atomic_switch_msr_special(vmx,
1557 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1558 VM_EXIT_LOAD_IA32_EFER,
1559 GUEST_IA32_EFER,
1560 HOST_IA32_EFER,
1561 guest_val, host_val);
1562 return;
1563 }
1564 break;
1565 case MSR_CORE_PERF_GLOBAL_CTRL:
1566 if (cpu_has_load_perf_global_ctrl) {
2961e876 1567 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1568 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570 GUEST_IA32_PERF_GLOBAL_CTRL,
1571 HOST_IA32_PERF_GLOBAL_CTRL,
1572 guest_val, host_val);
1573 return;
1574 }
1575 break;
110312c8
AK		 1576 }
1577
61d2ef2c
AK		 1578 for (i = 0; i < m->nr; ++i)
1579 if (m->guest[i].index == msr)
1580 break;
1581
e7fc6f93 1582 if (i == NR_AUTOLOAD_MSRS) {
60266204 1583 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1584 "Can't add msr %x\n", msr);
1585 return;
1586 } else if (i == m->nr) {
61d2ef2c
AK		 1587 ++m->nr;
1588 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590 }
1591
1592 m->guest[i].index = msr;
1593 m->guest[i].value = guest_val;
1594 m->host[i].index = msr;
1595 m->host[i].value = host_val;
1596}
1597
33ed6329
AK		 1598static void reload_tss(void)
1599{
33ed6329
AK		 1600 /*
1601 * VT restores TR but not its size. Useless.
1602 */
d359192f 1603 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1604 struct desc_struct *descs;
33ed6329 1605
d359192f 1606 descs = (void *)gdt->address;
33ed6329
AK		 1607 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608 load_TR_desc();
33ed6329
AK		 1609}
1610
92c0d900 1611static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1612{
3a34a881 1613 u64 guest_efer;
51c6cf66
AK		 1614 u64 ignore_bits;
1615
f6801dff 1616 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1617
51c6cf66 1618 /*
0fa06071 1619 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1620 * outside long mode
1621 */
1622 ignore_bits = EFER_NX | EFER_SCE;
1623#ifdef CONFIG_X86_64
1624 ignore_bits |= EFER_LMA | EFER_LME;
1625 /* SCE is meaningful only in long mode on Intel */
1626 if (guest_efer & EFER_LMA)
1627 ignore_bits &= ~(u64)EFER_SCE;
1628#endif
51c6cf66
AK		 1629 guest_efer &= ~ignore_bits;
1630 guest_efer |= host_efer & ignore_bits;
26bb0981 1631 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1632 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1633
1634 clear_atomic_switch_msr(vmx, MSR_EFER);
1635 /* On ept, can't emulate nx, and must switch nx atomically */
1636 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637 guest_efer = vmx->vcpu.arch.efer;
1638 if (!(guest_efer & EFER_LMA))
1639 guest_efer &= ~EFER_LME;
1640 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641 return false;
1642 }
1643
26bb0981 1644 return true;
51c6cf66
AK		 1645}
1646
2d49ec72
GN		 1647static unsigned long segment_base(u16 selector)
1648{
d359192f 1649 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1650 struct desc_struct *d;
1651 unsigned long table_base;
1652 unsigned long v;
1653
1654 if (!(selector & ~3))
1655 return 0;
1656
d359192f 1657 table_base = gdt->address;
2d49ec72
GN		 1658
1659 if (selector & 4) { /* from ldt */
1660 u16 ldt_selector = kvm_read_ldt();
1661
1662 if (!(ldt_selector & ~3))
1663 return 0;
1664
1665 table_base = segment_base(ldt_selector);
1666 }
1667 d = (struct desc_struct *)(table_base + (selector & ~7));
1668 v = get_desc_base(d);
1669#ifdef CONFIG_X86_64
1670 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672#endif
1673 return v;
1674}
1675
1676static inline unsigned long kvm_read_tr_base(void)
1677{
1678 u16 tr;
1679 asm("str %0" : "=g"(tr));
1680 return segment_base(tr);
1681}
1682
04d2cc77 1683static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1684{
04d2cc77 1685 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1686 int i;
04d2cc77 1687
a2fa3e9f 1688 if (vmx->host_state.loaded)
33ed6329
AK		 1689 return;
1690
a2fa3e9f 1691 vmx->host_state.loaded = 1;
33ed6329
AK		 1692 /*
1693 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1694 * allow segment selectors with cpl > 0 or ti == 1.
1695 */
d6e88aec 1696 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1697 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1698 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1699 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1700 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1701 vmx->host_state.fs_reload_needed = 0;
1702 } else {
33ed6329 1703 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1704 vmx->host_state.fs_reload_needed = 1;
33ed6329 1705 }
9581d442 1706 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1707 if (!(vmx->host_state.gs_sel & 7))
1708 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1709 else {
1710 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1711 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1712 }
1713
b2da15ac
AK		 1714#ifdef CONFIG_X86_64
1715 savesegment(ds, vmx->host_state.ds_sel);
1716 savesegment(es, vmx->host_state.es_sel);
1717#endif
1718
33ed6329
AK		 1719#ifdef CONFIG_X86_64
1720 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722#else
a2fa3e9f
GH		 1723 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1725#endif
707c0874
AK		 1726
1727#ifdef CONFIG_X86_64
c8770e7b
AK		 1728 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729 if (is_long_mode(&vmx->vcpu))
44ea2b17 1730 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1731#endif
da8999d3
LJ		 1732 if (boot_cpu_has(X86_FEATURE_MPX))
1733 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1734 for (i = 0; i < vmx->save_nmsrs; ++i)
1735 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1736 vmx->guest_msrs[i].data,
1737 vmx->guest_msrs[i].mask);
33ed6329
AK		 1738}
1739
a9b21b62 1740static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1741{
a2fa3e9f 1742 if (!vmx->host_state.loaded)
33ed6329
AK		 1743 return;
1744
e1beb1d3 1745 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1746 vmx->host_state.loaded = 0;
c8770e7b
AK		 1747#ifdef CONFIG_X86_64
1748 if (is_long_mode(&vmx->vcpu))
1749 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750#endif
152d3f2f 1751 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1752 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1753#ifdef CONFIG_X86_64
9581d442 1754 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1755#else
1756 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1757#endif
33ed6329 1758 }
0a77fe4c
AK		 1759 if (vmx->host_state.fs_reload_needed)
1760 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1761#ifdef CONFIG_X86_64
1762 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763 loadsegment(ds, vmx->host_state.ds_sel);
1764 loadsegment(es, vmx->host_state.es_sel);
1765 }
b2da15ac 1766#endif
152d3f2f 1767 reload_tss();
44ea2b17 1768#ifdef CONFIG_X86_64
c8770e7b 1769 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1770#endif
da8999d3
LJ		 1771 if (vmx->host_state.msr_host_bndcfgs)
1772 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1773 /*
1774 * If the FPU is not active (through the host task or
1775 * the guest vcpu), then restore the cr0.TS bit.
1776 */
1777 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778 stts();
3444d7da 1779 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1780}
1781
a9b21b62
AK		 1782static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783{
1784 preempt_disable();
1785 __vmx_load_host_state(vmx);
1786 preempt_enable();
1787}
1788
6aa8b732
AK		 1789/*
1790 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791 * vcpu mutex is already taken.
1792 */
15ad7146 1793static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1794{
a2fa3e9f 1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1796 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1797
4610c9cc
DX		 1798 if (!vmm_exclusive)
1799 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1800 else if (vmx->loaded_vmcs->cpu != cpu)
1801 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1802
d462b819
NHE		 1803 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1806 }
1807
d462b819 1808 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1809 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1810 unsigned long sysenter_esp;
1811
a8eeb04a 1812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1813 local_irq_disable();
8f536b76 1814 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1815
1816 /*
1817 * Read loaded_vmcs->cpu should be before fetching
1818 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819 * See the comments in __loaded_vmcs_clear().
1820 */
1821 smp_rmb();
1822
d462b819
NHE		 1823 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1825 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1826 local_irq_enable();
1827
6aa8b732
AK		 1828 /*
1829 * Linux uses per-cpu TSS and GDT, so set these when switching
1830 * processors.
1831 */
d6e88aec 1832 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1833 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1834
1835 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1837 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1838 }
6aa8b732
AK		 1839}
1840
1841static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842{
a9b21b62 1843 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1844 if (!vmm_exclusive) {
d462b819
NHE		 1845 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846 vcpu->cpu = -1;
4610c9cc
DX		 1847 kvm_cpu_vmxoff();
1848 }
6aa8b732
AK		 1849}
1850
5fd86fcf
AK		 1851static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852{
81231c69
AK		 1853 ulong cr0;
1854
5fd86fcf
AK		 1855 if (vcpu->fpu_active)
1856 return;
1857 vcpu->fpu_active = 1;
81231c69
AK		 1858 cr0 = vmcs_readl(GUEST_CR0);
1859 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1862 update_exception_bitmap(vcpu);
edcafe3c 1863 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1864 if (is_guest_mode(vcpu))
1865 vcpu->arch.cr0_guest_owned_bits &=
1866 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1867 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1868}
1869
edcafe3c
AK		 1870static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
fe3ef05c
NHE		 1872/*
1873 * Return the cr0 value that a nested guest would read. This is a combination
1874 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875 * its hypervisor (cr0_read_shadow).
1876 */
1877static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878{
1879 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881}
1882static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883{
1884 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886}
1887
5fd86fcf
AK		 1888static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889{
36cf24e0
NHE		 1890 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891 * set this *before* calling this function.
1892 */
edcafe3c 1893 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1894 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1895 update_exception_bitmap(vcpu);
edcafe3c
AK		 1896 vcpu->arch.cr0_guest_owned_bits = 0;
1897 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1898 if (is_guest_mode(vcpu)) {
1899 /*
1900 * L1's specified read shadow might not contain the TS bit,
1901 * so now that we turned on shadowing of this bit, we need to
1902 * set this bit of the shadow. Like in nested_vmx_run we need
1903 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904 * up-to-date here because we just decached cr0.TS (and we'll
1905 * only update vmcs12->guest_cr0 on nested exit).
1906 */
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909 (vcpu->arch.cr0 & X86_CR0_TS);
1910 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911 } else
1912 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1913}
1914
6aa8b732
AK		 1915static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916{
78ac8b47 1917 unsigned long rflags, save_rflags;
345dcaa8 1918
6de12732
AK		 1919 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921 rflags = vmcs_readl(GUEST_RFLAGS);
1922 if (to_vmx(vcpu)->rmode.vm86_active) {
1923 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926 }
1927 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1928 }
6de12732 1929 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1930}
1931
1932static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933{
6de12732
AK		 1934 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1936 if (to_vmx(vcpu)->rmode.vm86_active) {
1937 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1938 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1939 }
6aa8b732
AK		 1940 vmcs_writel(GUEST_RFLAGS, rflags);
1941}
1942
2809f5d2
GC		 1943static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944{
1945 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946 int ret = 0;
1947
1948 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1949 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1950 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1951 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1952
1953 return ret & mask;
1954}
1955
1956static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957{
1958 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959 u32 interruptibility = interruptibility_old;
1960
1961 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
48005f64 1963 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1964 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1965 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1966 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968 if ((interruptibility != interruptibility_old))
1969 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970}
1971
6aa8b732
AK		 1972static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973{
1974 unsigned long rip;
6aa8b732 1975
5fdbf976 1976 rip = kvm_rip_read(vcpu);
6aa8b732 1977 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1978 kvm_rip_write(vcpu, rip);
6aa8b732 1979
2809f5d2
GC		 1980 /* skipping an emulated instruction also counts */
1981 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1982}
1983
0b6ac343
NHE		 1984/*
1985 * KVM wants to inject page-faults which it got to the guest. This function
1986 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1987 */
e011c663 1988static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1989{
1990 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
e011c663 1992 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1993 return 0;
1994
533558bc
JK		 1995 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996 vmcs_read32(VM_EXIT_INTR_INFO),
1997 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1998 return 1;
1999}
2000
298101da 2001static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2002 bool has_error_code, u32 error_code,
2003 bool reinject)
298101da 2004{
77ab6db0 2005 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2006 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2007
e011c663
GN		 2008 if (!reinject && is_guest_mode(vcpu) &&
2009 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2010 return;
2011
8ab2d2e2 2012 if (has_error_code) {
77ab6db0 2013 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2014 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015 }
77ab6db0 2016
7ffd92c5 2017 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2018 int inc_eip = 0;
2019 if (kvm_exception_is_soft(nr))
2020 inc_eip = vcpu->arch.event_exit_inst_len;
2021 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2023 return;
2024 }
2025
66fd3f7f
GN		 2026 if (kvm_exception_is_soft(nr)) {
2027 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2029 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030 } else
2031 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2034}
2035
4e47c7a6
SY		 2036static bool vmx_rdtscp_supported(void)
2037{
2038 return cpu_has_vmx_rdtscp();
2039}
2040
ad756a16
MJ		 2041static bool vmx_invpcid_supported(void)
2042{
2043 return cpu_has_vmx_invpcid() && enable_ept;
2044}
2045
a75beee6
ED		 2046/*
2047 * Swap MSR entry in host/guest MSR entry array.
2048 */
8b9cf98c 2049static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2050{
26bb0981 2051 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2052
2053 tmp = vmx->guest_msrs[to];
2054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2056}
2057
8d14695f
YZ		 2058static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059{
2060 unsigned long *msr_bitmap;
2061
2062 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063 if (is_long_mode(vcpu))
2064 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065 else
2066 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067 } else {
2068 if (is_long_mode(vcpu))
2069 msr_bitmap = vmx_msr_bitmap_longmode;
2070 else
2071 msr_bitmap = vmx_msr_bitmap_legacy;
2072 }
2073
2074 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075}
2076
e38aea3e
AK		 2077/*
2078 * Set up the vmcs to automatically save and restore system
2079 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2080 * mode, as fiddling with msrs is very expensive.
2081 */
8b9cf98c 2082static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2083{
26bb0981 2084 int save_nmsrs, index;
e38aea3e 2085
a75beee6
ED		 2086 save_nmsrs = 0;
2087#ifdef CONFIG_X86_64
8b9cf98c 2088 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2089 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2090 if (index >= 0)
8b9cf98c
RR		 2091 move_msr_up(vmx, index, save_nmsrs++);
2092 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2093 if (index >= 0)
8b9cf98c
RR		 2094 move_msr_up(vmx, index, save_nmsrs++);
2095 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2096 if (index >= 0)
8b9cf98c 2097 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2098 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099 if (index >= 0 && vmx->rdtscp_enabled)
2100 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2101 /*
8c06585d 2102 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2103 * if efer.sce is enabled.
2104 */
8c06585d 2105 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2106 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2107 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2108 }
2109#endif
92c0d900
AK		 2110 index = __find_msr_index(vmx, MSR_EFER);
2111 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2112 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2113
26bb0981 2114 vmx->save_nmsrs = save_nmsrs;
5897297b 2115
8d14695f
YZ		 2116 if (cpu_has_vmx_msr_bitmap())
2117 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2118}
2119
6aa8b732
AK		 2120/*
2121 * reads and returns guest's timestamp counter "register"
2122 * guest_tsc = host_tsc + tsc_offset -- 21.3
2123 */
2124static u64 guest_read_tsc(void)
2125{
2126 u64 host_tsc, tsc_offset;
2127
2128 rdtscll(host_tsc);
2129 tsc_offset = vmcs_read64(TSC_OFFSET);
2130 return host_tsc + tsc_offset;
2131}
2132
d5c1785d
NHE		 2133/*
2134 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135 * counter, even if a nested guest (L2) is currently running.
2136 */
886b470c 2137u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2138{
886b470c 2139 u64 tsc_offset;
d5c1785d 2140
d5c1785d
NHE		 2141 tsc_offset = is_guest_mode(vcpu) ?
2142 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143 vmcs_read64(TSC_OFFSET);
2144 return host_tsc + tsc_offset;
2145}
2146
4051b188 2147/*
cc578287
ZA		 2148 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2149 * software catchup for faster rates on slower CPUs.
4051b188 2150 */
cc578287 2151static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2152{
cc578287
ZA		 2153 if (!scale)
2154 return;
2155
2156 if (user_tsc_khz > tsc_khz) {
2157 vcpu->arch.tsc_catchup = 1;
2158 vcpu->arch.tsc_always_catchup = 1;
2159 } else
2160 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2161}
2162
ba904635
WA		 2163static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164{
2165 return vmcs_read64(TSC_OFFSET);
2166}
2167
6aa8b732 2168/*
99e3e30a 2169 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2170 */
99e3e30a 2171static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2172{
27fc51b2 2173 if (is_guest_mode(vcpu)) {
7991825b 2174 /*
27fc51b2
NHE		 2175 * We're here if L1 chose not to trap WRMSR to TSC. According
2176 * to the spec, this should set L1's TSC; The offset that L1
2177 * set for L2 remains unchanged, and still needs to be added
2178 * to the newly set TSC to get L2's TSC.
7991825b 2179 */
27fc51b2
NHE		 2180 struct vmcs12 *vmcs12;
2181 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182 /* recalculate vmcs02.TSC_OFFSET: */
2183 vmcs12 = get_vmcs12(vcpu);
2184 vmcs_write64(TSC_OFFSET, offset +
2185 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186 vmcs12->tsc_offset : 0));
2187 } else {
489223ed
YY		 2188 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2190 vmcs_write64(TSC_OFFSET, offset);
2191 }
6aa8b732
AK		 2192}
2193
f1e2b260 2194static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2195{
2196 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2197
e48672fa 2198 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2199 if (is_guest_mode(vcpu)) {
2200 /* Even when running L2, the adjustment needs to apply to L1 */
2201 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2202 } else
2203 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204 offset + adjustment);
e48672fa
ZA		 2205}
2206
857e4099
JR		 2207static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208{
2209 return target_tsc - native_read_tsc();
2210}
2211
801d3424
NHE		 2212static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213{
2214 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216}
2217
2218/*
2219 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221 * all guests if the "nested" module option is off, and can also be disabled
2222 * for a single guest by disabling its VMX cpuid bit.
2223 */
2224static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225{
2226 return nested && guest_cpuid_has_vmx(vcpu);
2227}
2228
b87a51ae
NHE		 2229/*
2230 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231 * returned for the various VMX controls MSRs when nested VMX is enabled.
2232 * The same values should also be used to verify that vmcs12 control fields are
2233 * valid during nested entry from L1 to L2.
2234 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236 * bit in the high half is on if the corresponding bit in the control field
2237 * may be on. See also vmx_control_verify().
2238 * TODO: allow these variables to be modified (downgraded) by module options
2239 * or other means.
2240 */
2241static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2246static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2247static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2248static __init void nested_vmx_setup_ctls_msrs(void)
2249{
2250 /*
2251 * Note that as a general rule, the high half of the MSRs (bits in
2252 * the control fields which may be 1) should be initialized by the
2253 * intersection of the underlying hardware's MSR (i.e., features which
2254 * can be supported) and the list of features we want to expose -
2255 * because they are known to be properly supported in our code.
2256 * Also, usually, the low half of the MSRs (bits which must be 1) can
2257 * be set to 0, meaning that L1 may turn off any of these bits. The
2258 * reason is that if one of these bits is necessary, it will appear
2259 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260 * fields of vmcs01 and vmcs02, will turn these bits off - and
2261 * nested_vmx_exit_handled() will not pass related exits to L1.
2262 * These rules have exceptions below.
2263 */
2264
2265 /* pin-based controls */
eabeaacc
JK		 2266 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2268 /*
2269 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271 */
eabeaacc
JK		 2272 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2274 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2276 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2277
33fb20c3
JK		 2278 /*
2279 * Exit controls
2280 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281 * 17 must be 1.
2282 */
c0dfee58
ACL		 2283 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2285 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2286 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2287 nested_vmx_exit_ctls_high &=
b87a51ae 2288#ifdef CONFIG_X86_64
c0dfee58 2289 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2290#endif
f4124500
JK		 2291 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
7854cbca 2294 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
36be0b9d
PB		 2295 if (vmx_mpx_supported())
2296 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae
NHE		 2297
2298 /* entry controls */
2299 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2300 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2301 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2302 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2303 nested_vmx_entry_ctls_high &=
57435349
JK		 2304#ifdef CONFIG_X86_64
2305 VM_ENTRY_IA32E_MODE |
2306#endif
2307 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2308 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2309 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2310 if (vmx_mpx_supported())
2311 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2312
b87a51ae
NHE		 2313 /* cpu-based controls */
2314 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2315 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2316 nested_vmx_procbased_ctls_low = 0;
2317 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2318 CPU_BASED_VIRTUAL_INTR_PENDING |
2319 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2320 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2321 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2322 CPU_BASED_CR3_STORE_EXITING |
2323#ifdef CONFIG_X86_64
2324 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2325#endif
2326 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2327 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2328 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2329 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2330 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2331 /*
2332 * We can allow some features even when not supported by the
2333 * hardware. For example, L1 can specify an MSR bitmap - and we
2334 * can use it to avoid exits to L1 - even when L0 runs L2
2335 * without MSR bitmaps.
2336 */
2337 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2338
2339 /* secondary cpu-based controls */
2340 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2341 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2342 nested_vmx_secondary_ctls_low = 0;
2343 nested_vmx_secondary_ctls_high &=
d6851fbe 2344 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2345 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2346 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2347
afa61f75
NHE		 2348 if (enable_ept) {
2349 /* nested EPT: emulate EPT also to L1 */
2350 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2351 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2352 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2353 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2354 nested_vmx_ept_caps &= vmx_capability.ept;
2355 /*
4b855078
BD		 2356 * For nested guests, we don't do anything specific
2357 * for single context invalidation. Hence, only advertise
2358 * support for global context invalidation.
afa61f75 2359 */
4b855078 2360 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2361 } else
2362 nested_vmx_ept_caps = 0;
2363
c18911a2
JK		 2364 /* miscellaneous data */
2365 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2366 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2367 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2368 VMX_MISC_ACTIVITY_HLT;
c18911a2 2369 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2370}
2371
2372static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2373{
2374 /*
2375 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2376 */
2377 return ((control & high) | low) == control;
2378}
2379
2380static inline u64 vmx_control_msr(u32 low, u32 high)
2381{
2382 return low | ((u64)high << 32);
2383}
2384
cae50139 2385/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2386static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2387{
b87a51ae 2388 switch (msr_index) {
b87a51ae
NHE		 2389 case MSR_IA32_VMX_BASIC:
2390 /*
2391 * This MSR reports some information about VMX support. We
2392 * should return information about the VMX we emulate for the
2393 * guest, and the VMCS structure we give it - not about the
2394 * VMX support of the underlying hardware.
2395 */
2396 *pdata = VMCS12_REVISION |
2397 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2398 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2399 break;
2400 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2401 case MSR_IA32_VMX_PINBASED_CTLS:
2402 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2403 nested_vmx_pinbased_ctls_high);
2404 break;
2405 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2406 case MSR_IA32_VMX_PROCBASED_CTLS:
2407 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2408 nested_vmx_procbased_ctls_high);
2409 break;
2410 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2411 case MSR_IA32_VMX_EXIT_CTLS:
2412 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2413 nested_vmx_exit_ctls_high);
2414 break;
2415 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2416 case MSR_IA32_VMX_ENTRY_CTLS:
2417 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2418 nested_vmx_entry_ctls_high);
2419 break;
2420 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2421 *pdata = vmx_control_msr(nested_vmx_misc_low,
2422 nested_vmx_misc_high);
b87a51ae
NHE		 2423 break;
2424 /*
2425 * These MSRs specify bits which the guest must keep fixed (on or off)
2426 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2427 * We picked the standard core2 setting.
2428 */
2429#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2430#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2431 case MSR_IA32_VMX_CR0_FIXED0:
2432 *pdata = VMXON_CR0_ALWAYSON;
2433 break;
2434 case MSR_IA32_VMX_CR0_FIXED1:
2435 *pdata = -1ULL;
2436 break;
2437 case MSR_IA32_VMX_CR4_FIXED0:
2438 *pdata = VMXON_CR4_ALWAYSON;
2439 break;
2440 case MSR_IA32_VMX_CR4_FIXED1:
2441 *pdata = -1ULL;
2442 break;
2443 case MSR_IA32_VMX_VMCS_ENUM:
2444 *pdata = 0x1f;
2445 break;
2446 case MSR_IA32_VMX_PROCBASED_CTLS2:
2447 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2448 nested_vmx_secondary_ctls_high);
2449 break;
2450 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2451 /* Currently, no nested vpid support */
2452 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2453 break;
2454 default:
b87a51ae 2455 return 1;
b3897a49
NHE		 2456 }
2457
b87a51ae
NHE		 2458 return 0;
2459}
2460
6aa8b732
AK		 2461/*
2462 * Reads an msr value (of 'msr_index') into 'pdata'.
2463 * Returns 0 on success, non-0 otherwise.
2464 * Assumes vcpu_load() was already called.
2465 */
2466static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2467{
2468 u64 data;
26bb0981 2469 struct shared_msr_entry *msr;
6aa8b732
AK		 2470
2471 if (!pdata) {
2472 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2473 return -EINVAL;
2474 }
2475
2476 switch (msr_index) {
05b3e0c2 2477#ifdef CONFIG_X86_64
6aa8b732
AK		 2478 case MSR_FS_BASE:
2479 data = vmcs_readl(GUEST_FS_BASE);
2480 break;
2481 case MSR_GS_BASE:
2482 data = vmcs_readl(GUEST_GS_BASE);
2483 break;
44ea2b17
AK		 2484 case MSR_KERNEL_GS_BASE:
2485 vmx_load_host_state(to_vmx(vcpu));
2486 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2487 break;
26bb0981 2488#endif
6aa8b732 2489 case MSR_EFER:
3bab1f5d 2490 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2491 case MSR_IA32_TSC:
6aa8b732
AK		 2492 data = guest_read_tsc();
2493 break;
2494 case MSR_IA32_SYSENTER_CS:
2495 data = vmcs_read32(GUEST_SYSENTER_CS);
2496 break;
2497 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2498 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2499 break;
2500 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2501 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2502 break;
0dd376e7 2503 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2504 if (!vmx_mpx_supported())
2505 return 1;
0dd376e7
LJ		 2506 data = vmcs_read64(GUEST_BNDCFGS);
2507 break;
cae50139
JK		 2508 case MSR_IA32_FEATURE_CONTROL:
2509 if (!nested_vmx_allowed(vcpu))
2510 return 1;
2511 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2512 break;
2513 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2514 if (!nested_vmx_allowed(vcpu))
2515 return 1;
2516 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2517 case MSR_TSC_AUX:
2518 if (!to_vmx(vcpu)->rdtscp_enabled)
2519 return 1;
2520 /* Otherwise falls through */
6aa8b732 2521 default:
8b9cf98c 2522 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2523 if (msr) {
2524 data = msr->data;
2525 break;
6aa8b732 2526 }
3bab1f5d 2527 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2528 }
2529
2530 *pdata = data;
2531 return 0;
2532}
2533
cae50139
JK		 2534static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2535
6aa8b732
AK		 2536/*
2537 * Writes msr value into into the appropriate "register".
2538 * Returns 0 on success, non-0 otherwise.
2539 * Assumes vcpu_load() was already called.
2540 */
8fe8ab46 2541static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2542{
a2fa3e9f 2543 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2544 struct shared_msr_entry *msr;
2cc51560 2545 int ret = 0;
8fe8ab46
WA		 2546 u32 msr_index = msr_info->index;
2547 u64 data = msr_info->data;
2cc51560 2548
6aa8b732 2549 switch (msr_index) {
3bab1f5d 2550 case MSR_EFER:
8fe8ab46 2551 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2552 break;
16175a79 2553#ifdef CONFIG_X86_64
6aa8b732 2554 case MSR_FS_BASE:
2fb92db1 2555 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2556 vmcs_writel(GUEST_FS_BASE, data);
2557 break;
2558 case MSR_GS_BASE:
2fb92db1 2559 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2560 vmcs_writel(GUEST_GS_BASE, data);
2561 break;
44ea2b17
AK		 2562 case MSR_KERNEL_GS_BASE:
2563 vmx_load_host_state(vmx);
2564 vmx->msr_guest_kernel_gs_base = data;
2565 break;
6aa8b732
AK		 2566#endif
2567 case MSR_IA32_SYSENTER_CS:
2568 vmcs_write32(GUEST_SYSENTER_CS, data);
2569 break;
2570 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2571 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2572 break;
2573 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2574 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2575 break;
0dd376e7 2576 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2577 if (!vmx_mpx_supported())
2578 return 1;
0dd376e7
LJ		 2579 vmcs_write64(GUEST_BNDCFGS, data);
2580 break;
af24a4e4 2581 case MSR_IA32_TSC:
8fe8ab46 2582 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2583 break;
468d472f
SY		 2584 case MSR_IA32_CR_PAT:
2585 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2586 vmcs_write64(GUEST_IA32_PAT, data);
2587 vcpu->arch.pat = data;
2588 break;
2589 }
8fe8ab46 2590 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2591 break;
ba904635
WA		 2592 case MSR_IA32_TSC_ADJUST:
2593 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2594 break;
cae50139
JK		 2595 case MSR_IA32_FEATURE_CONTROL:
2596 if (!nested_vmx_allowed(vcpu) ||
2597 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2598 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2599 return 1;
2600 vmx->nested.msr_ia32_feature_control = data;
2601 if (msr_info->host_initiated && data == 0)
2602 vmx_leave_nested(vcpu);
2603 break;
2604 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2605 return 1; /* they are read-only */
4e47c7a6
SY		 2606 case MSR_TSC_AUX:
2607 if (!vmx->rdtscp_enabled)
2608 return 1;
2609 /* Check reserved bit, higher 32 bits should be zero */
2610 if ((data >> 32) != 0)
2611 return 1;
2612 /* Otherwise falls through */
6aa8b732 2613 default:
8b9cf98c 2614 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2615 if (msr) {
2616 msr->data = data;
2225fd56
AK		 2617 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2618 preempt_disable();
9ee73970
AK		 2619 kvm_set_shared_msr(msr->index, msr->data,
2620 msr->mask);
2225fd56
AK		 2621 preempt_enable();
2622 }
3bab1f5d 2623 break;
6aa8b732 2624 }
8fe8ab46 2625 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2626 }
2627
2cc51560 2628 return ret;
6aa8b732
AK		 2629}
2630
5fdbf976 2631static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2632{
5fdbf976
MT		 2633 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2634 switch (reg) {
2635 case VCPU_REGS_RSP:
2636 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2637 break;
2638 case VCPU_REGS_RIP:
2639 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2640 break;
6de4f3ad
AK		 2641 case VCPU_EXREG_PDPTR:
2642 if (enable_ept)
2643 ept_save_pdptrs(vcpu);
2644 break;
5fdbf976
MT		 2645 default:
2646 break;
2647 }
6aa8b732
AK		 2648}
2649
6aa8b732
AK		 2650static __init int cpu_has_kvm_support(void)
2651{
6210e37b 2652 return cpu_has_vmx();
6aa8b732
AK		 2653}
2654
2655static __init int vmx_disabled_by_bios(void)
2656{
2657 u64 msr;
2658
2659 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2660 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2661 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2662 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2663 && tboot_enabled())
2664 return 1;
23f3e991 2665 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2666 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2667 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2668 && !tboot_enabled()) {
2669 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2670 "activate TXT before enabling KVM\n");
cafd6659 2671 return 1;
f9335afe 2672 }
23f3e991
JC		 2673 /* launched w/o TXT and VMX disabled */
2674 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2675 && !tboot_enabled())
2676 return 1;
cafd6659
SW		 2677 }
2678
2679 return 0;
6aa8b732
AK		 2680}
2681
7725b894
DX		 2682static void kvm_cpu_vmxon(u64 addr)
2683{
2684 asm volatile (ASM_VMX_VMXON_RAX
2685 : : "a"(&addr), "m"(addr)
2686 : "memory", "cc");
2687}
2688
10474ae8 2689static int hardware_enable(void *garbage)
6aa8b732
AK		 2690{
2691 int cpu = raw_smp_processor_id();
2692 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2693 u64 old, test_bits;
6aa8b732 2694
10474ae8
AG		 2695 if (read_cr4() & X86_CR4_VMXE)
2696 return -EBUSY;
2697
d462b819 2698 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2699
2700 /*
2701 * Now we can enable the vmclear operation in kdump
2702 * since the loaded_vmcss_on_cpu list on this cpu
2703 * has been initialized.
2704 *
2705 * Though the cpu is not in VMX operation now, there
2706 * is no problem to enable the vmclear operation
2707 * for the loaded_vmcss_on_cpu list is empty!
2708 */
2709 crash_enable_local_vmclear(cpu);
2710
6aa8b732 2711 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2712
2713 test_bits = FEATURE_CONTROL_LOCKED;
2714 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2715 if (tboot_enabled())
2716 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2717
2718 if ((old & test_bits) != test_bits) {
6aa8b732 2719 /* enable and lock */
cafd6659
SW		 2720 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2721 }
66aee91a 2722 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2723
4610c9cc
DX		 2724 if (vmm_exclusive) {
2725 kvm_cpu_vmxon(phys_addr);
2726 ept_sync_global();
2727 }
10474ae8 2728
357d1226 2729 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2730
10474ae8 2731 return 0;
6aa8b732
AK		 2732}
2733
d462b819 2734static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2735{
2736 int cpu = raw_smp_processor_id();
d462b819 2737 struct loaded_vmcs *v, *n;
543e4243 2738
d462b819
NHE		 2739 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2740 loaded_vmcss_on_cpu_link)
2741 __loaded_vmcs_clear(v);
543e4243
AK		 2742}
2743
710ff4a8
EH		 2744
2745/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2746 * tricks.
2747 */
2748static void kvm_cpu_vmxoff(void)
6aa8b732 2749{
4ecac3fd 2750 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2751}
2752
710ff4a8
EH		 2753static void hardware_disable(void *garbage)
2754{
4610c9cc 2755 if (vmm_exclusive) {
d462b819 2756 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2757 kvm_cpu_vmxoff();
2758 }
7725b894 2759 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2760}
2761
1c3d14fe 2762static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2763 u32 msr, u32 *result)
1c3d14fe
YS		 2764{
2765 u32 vmx_msr_low, vmx_msr_high;
2766 u32 ctl = ctl_min | ctl_opt;
2767
2768 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2769
2770 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2771 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2772
2773 /* Ensure minimum (required) set of control bits are supported. */
2774 if (ctl_min & ~ctl)
002c7f7c 2775 return -EIO;
1c3d14fe
YS		 2776
2777 *result = ctl;
2778 return 0;
2779}
2780
110312c8
AK		 2781static __init bool allow_1_setting(u32 msr, u32 ctl)
2782{
2783 u32 vmx_msr_low, vmx_msr_high;
2784
2785 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2786 return vmx_msr_high & ctl;
2787}
2788
002c7f7c 2789static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2790{
2791 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2792 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2793 u32 _pin_based_exec_control = 0;
2794 u32 _cpu_based_exec_control = 0;
f78e0e2e 2795 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2796 u32 _vmexit_control = 0;
2797 u32 _vmentry_control = 0;
2798
10166744 2799 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2800#ifdef CONFIG_X86_64
2801 CPU_BASED_CR8_LOAD_EXITING |
2802 CPU_BASED_CR8_STORE_EXITING |
2803#endif
d56f546d
SY		 2804 CPU_BASED_CR3_LOAD_EXITING |
2805 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2806 CPU_BASED_USE_IO_BITMAPS |
2807 CPU_BASED_MOV_DR_EXITING |
a7052897 2808 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2809 CPU_BASED_MWAIT_EXITING |
2810 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2811 CPU_BASED_INVLPG_EXITING |
2812 CPU_BASED_RDPMC_EXITING;
443381a8 2813
f78e0e2e 2814 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2815 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2816 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2817 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2818 &_cpu_based_exec_control) < 0)
002c7f7c 2819 return -EIO;
6e5d865c
YS		 2820#ifdef CONFIG_X86_64
2821 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2822 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2823 ~CPU_BASED_CR8_STORE_EXITING;
2824#endif
f78e0e2e 2825 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2826 min2 = 0;
2827 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2828 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2829 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2830 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2831 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2832 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2833 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2834 SECONDARY_EXEC_RDTSCP |
83d4c286 2835 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2836 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2837 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2838 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2839 if (adjust_vmx_controls(min2, opt2,
2840 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2841 &_cpu_based_2nd_exec_control) < 0)
2842 return -EIO;
2843 }
2844#ifndef CONFIG_X86_64
2845 if (!(_cpu_based_2nd_exec_control &
2846 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2847 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2848#endif
83d4c286
YZ		 2849
2850 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2851 _cpu_based_2nd_exec_control &= ~(
8d14695f 2852 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2853 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2854 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2855
d56f546d 2856 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2857 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2858 enabled */
5fff7d27
GN		 2859 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2860 CPU_BASED_CR3_STORE_EXITING |
2861 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2862 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2863 vmx_capability.ept, vmx_capability.vpid);
2864 }
1c3d14fe 2865
81908bf4 2866 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2867#ifdef CONFIG_X86_64
2868 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2869#endif
a547c6db 2870 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2871 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2872 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2873 &_vmexit_control) < 0)
002c7f7c 2874 return -EIO;
1c3d14fe 2875
01e439be
YZ		 2876 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2877 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2878 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2879 &_pin_based_exec_control) < 0)
2880 return -EIO;
2881
2882 if (!(_cpu_based_2nd_exec_control &
2883 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2884 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2885 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2886
c845f9c6 2887 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2888 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2889 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2890 &_vmentry_control) < 0)
002c7f7c 2891 return -EIO;
6aa8b732 2892
c68876fd 2893 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2894
2895 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2896 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2897 return -EIO;
1c3d14fe
YS		 2898
2899#ifdef CONFIG_X86_64
2900 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2901 if (vmx_msr_high & (1u<<16))
002c7f7c 2902 return -EIO;
1c3d14fe
YS		 2903#endif
2904
2905 /* Require Write-Back (WB) memory type for VMCS accesses. */
2906 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2907 return -EIO;
1c3d14fe 2908
002c7f7c
YS		 2909 vmcs_conf->size = vmx_msr_high & 0x1fff;
2910 vmcs_conf->order = get_order(vmcs_config.size);
2911 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2912
002c7f7c
YS		 2913 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2914 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2915 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2916 vmcs_conf->vmexit_ctrl = _vmexit_control;
2917 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2918
110312c8
AK		 2919 cpu_has_load_ia32_efer =
2920 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2921 VM_ENTRY_LOAD_IA32_EFER)
2922 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2923 VM_EXIT_LOAD_IA32_EFER);
2924
8bf00a52
GN		 2925 cpu_has_load_perf_global_ctrl =
2926 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2927 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2928 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2929 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2930
2931 /*
2932 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2933 * but due to arrata below it can't be used. Workaround is to use
2934 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2935 *
2936 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2937 *
2938 * AAK155 (model 26)
2939 * AAP115 (model 30)
2940 * AAT100 (model 37)
2941 * BC86,AAY89,BD102 (model 44)
2942 * BA97 (model 46)
2943 *
2944 */
2945 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2946 switch (boot_cpu_data.x86_model) {
2947 case 26:
2948 case 30:
2949 case 37:
2950 case 44:
2951 case 46:
2952 cpu_has_load_perf_global_ctrl = false;
2953 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2954 "does not work properly. Using workaround\n");
2955 break;
2956 default:
2957 break;
2958 }
2959 }
2960
1c3d14fe 2961 return 0;
c68876fd 2962}
6aa8b732
AK		 2963
2964static struct vmcs *alloc_vmcs_cpu(int cpu)
2965{
2966 int node = cpu_to_node(cpu);
2967 struct page *pages;
2968 struct vmcs *vmcs;
2969
6484eb3e 2970 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2971 if (!pages)
2972 return NULL;
2973 vmcs = page_address(pages);
1c3d14fe
YS		 2974 memset(vmcs, 0, vmcs_config.size);
2975 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2976 return vmcs;
2977}
2978
2979static struct vmcs *alloc_vmcs(void)
2980{
d3b2c338 2981 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2982}
2983
2984static void free_vmcs(struct vmcs *vmcs)
2985{
1c3d14fe 2986 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2987}
2988
d462b819
NHE		 2989/*
2990 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2991 */
2992static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2993{
2994 if (!loaded_vmcs->vmcs)
2995 return;
2996 loaded_vmcs_clear(loaded_vmcs);
2997 free_vmcs(loaded_vmcs->vmcs);
2998 loaded_vmcs->vmcs = NULL;
2999}
3000
39959588 3001static void free_kvm_area(void)
6aa8b732
AK		 3002{
3003 int cpu;
3004
3230bb47 3005 for_each_possible_cpu(cpu) {
6aa8b732 3006 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3007 per_cpu(vmxarea, cpu) = NULL;
3008 }
6aa8b732
AK		 3009}
3010
6aa8b732
AK		 3011static __init int alloc_kvm_area(void)
3012{
3013 int cpu;
3014
3230bb47 3015 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3016 struct vmcs *vmcs;
3017
3018 vmcs = alloc_vmcs_cpu(cpu);
3019 if (!vmcs) {
3020 free_kvm_area();
3021 return -ENOMEM;
3022 }
3023
3024 per_cpu(vmxarea, cpu) = vmcs;
3025 }
3026 return 0;
3027}
3028
3029static __init int hardware_setup(void)
3030{
002c7f7c
YS		 3031 if (setup_vmcs_config(&vmcs_config) < 0)
3032 return -EIO;
50a37eb4
JR		 3033
3034 if (boot_cpu_has(X86_FEATURE_NX))
3035 kvm_enable_efer_bits(EFER_NX);
3036
93ba03c2
SY		 3037 if (!cpu_has_vmx_vpid())
3038 enable_vpid = 0;
abc4fc58
AG		 3039 if (!cpu_has_vmx_shadow_vmcs())
3040 enable_shadow_vmcs = 0;
93ba03c2 3041
4bc9b982
SY		 3042 if (!cpu_has_vmx_ept() ||
3043 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3044 enable_ept = 0;
3a624e29 3045 enable_unrestricted_guest = 0;
83c3a331 3046 enable_ept_ad_bits = 0;
3a624e29
NK		 3047 }
3048
83c3a331
XH		 3049 if (!cpu_has_vmx_ept_ad_bits())
3050 enable_ept_ad_bits = 0;
3051
3a624e29
NK		 3052 if (!cpu_has_vmx_unrestricted_guest())
3053 enable_unrestricted_guest = 0;
93ba03c2
SY		 3054
3055 if (!cpu_has_vmx_flexpriority())
3056 flexpriority_enabled = 0;
3057
95ba8273
GN		 3058 if (!cpu_has_vmx_tpr_shadow())
3059 kvm_x86_ops->update_cr8_intercept = NULL;
3060
54dee993
MT		 3061 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3062 kvm_disable_largepages();
3063
4b8d54f9
ZE		 3064 if (!cpu_has_vmx_ple())
3065 ple_gap = 0;
3066
01e439be
YZ		 3067 if (!cpu_has_vmx_apicv())
3068 enable_apicv = 0;
c7c9c56c 3069
01e439be 3070 if (enable_apicv)
c7c9c56c 3071 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3072 else {
c7c9c56c 3073 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3074 kvm_x86_ops->deliver_posted_interrupt = NULL;
3075 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3076 }
83d4c286 3077
b87a51ae
NHE		 3078 if (nested)
3079 nested_vmx_setup_ctls_msrs();
3080
6aa8b732
AK		 3081 return alloc_kvm_area();
3082}
3083
3084static __exit void hardware_unsetup(void)
3085{
3086 free_kvm_area();
3087}
3088
14168786
GN		 3089static bool emulation_required(struct kvm_vcpu *vcpu)
3090{
3091 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3092}
3093
91b0aa2c 3094static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3095 struct kvm_segment *save)
6aa8b732 3096{
d99e4152
GN		 3097 if (!emulate_invalid_guest_state) {
3098 /*
3099 * CS and SS RPL should be equal during guest entry according
3100 * to VMX spec, but in reality it is not always so. Since vcpu
3101 * is in the middle of the transition from real mode to
3102 * protected mode it is safe to assume that RPL 0 is a good
3103 * default value.
3104 */
3105 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3106 save->selector &= ~SELECTOR_RPL_MASK;
3107 save->dpl = save->selector & SELECTOR_RPL_MASK;
3108 save->s = 1;
6aa8b732 3109 }
d99e4152 3110 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3111}
3112
3113static void enter_pmode(struct kvm_vcpu *vcpu)
3114{
3115 unsigned long flags;
a89a8fb9 3116 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3117
d99e4152
GN		 3118 /*
3119 * Update real mode segment cache. It may be not up-to-date if sement
3120 * register was written while vcpu was in a guest mode.
3121 */
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3123 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3126 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3128
7ffd92c5 3129 vmx->rmode.vm86_active = 0;
6aa8b732 3130
2fb92db1
AK		 3131 vmx_segment_cache_clear(vmx);
3132
f5f7b2fe 3133 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3134
3135 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3136 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3137 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3138 vmcs_writel(GUEST_RFLAGS, flags);
3139
66aee91a
RR		 3140 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3141 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3142
3143 update_exception_bitmap(vcpu);
3144
91b0aa2c
GN		 3145 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3146 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3147 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3148 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3149 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3150 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3151
3152 /* CPL is always 0 when CPU enters protected mode */
3153 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3154 vmx->cpl = 0;
6aa8b732
AK		 3155}
3156
f5f7b2fe 3157static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3158{
772e0318 3159 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3160 struct kvm_segment var = *save;
3161
3162 var.dpl = 0x3;
3163 if (seg == VCPU_SREG_CS)
3164 var.type = 0x3;
3165
3166 if (!emulate_invalid_guest_state) {
3167 var.selector = var.base >> 4;
3168 var.base = var.base & 0xffff0;
3169 var.limit = 0xffff;
3170 var.g = 0;
3171 var.db = 0;
3172 var.present = 1;
3173 var.s = 1;
3174 var.l = 0;
3175 var.unusable = 0;
3176 var.type = 0x3;
3177 var.avl = 0;
3178 if (save->base & 0xf)
3179 printk_once(KERN_WARNING "kvm: segment base is not "
3180 "paragraph aligned when entering "
3181 "protected mode (seg=%d)", seg);
3182 }
6aa8b732 3183
d99e4152
GN		 3184 vmcs_write16(sf->selector, var.selector);
3185 vmcs_write32(sf->base, var.base);
3186 vmcs_write32(sf->limit, var.limit);
3187 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3188}
3189
3190static void enter_rmode(struct kvm_vcpu *vcpu)
3191{
3192 unsigned long flags;
a89a8fb9 3193 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3194
f5f7b2fe
AK		 3195 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3196 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3197 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3198 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3199 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3200 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3201 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3202
7ffd92c5 3203 vmx->rmode.vm86_active = 1;
6aa8b732 3204
776e58ea
GN		 3205 /*
3206 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3207 * vcpu. Warn the user that an update is overdue.
776e58ea 3208 */
4918c6ca 3209 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3210 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3211 "called before entering vcpu\n");
776e58ea 3212
2fb92db1
AK		 3213 vmx_segment_cache_clear(vmx);
3214
4918c6ca 3215 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3216 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3217 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3218
3219 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3220 vmx->rmode.save_rflags = flags;
6aa8b732 3221
053de044 3222 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3223
3224 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3225 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3226 update_exception_bitmap(vcpu);
3227
d99e4152
GN		 3228 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3229 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3230 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3231 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3232 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3233 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3234
8668a3c4 3235 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3236}
3237
401d10de
AS		 3238static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3239{
3240 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3241 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3242
3243 if (!msr)
3244 return;
401d10de 3245
44ea2b17
AK		 3246 /*
3247 * Force kernel_gs_base reloading before EFER changes, as control
3248 * of this msr depends on is_long_mode().
3249 */
3250 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3251 vcpu->arch.efer = efer;
401d10de 3252 if (efer & EFER_LMA) {
2961e876 3253 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3254 msr->data = efer;
3255 } else {
2961e876 3256 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3257
3258 msr->data = efer & ~EFER_LME;
3259 }
3260 setup_msrs(vmx);
3261}
3262
05b3e0c2 3263#ifdef CONFIG_X86_64
6aa8b732
AK		 3264
3265static void enter_lmode(struct kvm_vcpu *vcpu)
3266{
3267 u32 guest_tr_ar;
3268
2fb92db1
AK		 3269 vmx_segment_cache_clear(to_vmx(vcpu));
3270
6aa8b732
AK		 3271 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3272 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3273 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3274 __func__);
6aa8b732
AK		 3275 vmcs_write32(GUEST_TR_AR_BYTES,
3276 (guest_tr_ar & ~AR_TYPE_MASK)
3277 | AR_TYPE_BUSY_64_TSS);
3278 }
da38f438 3279 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3280}
3281
3282static void exit_lmode(struct kvm_vcpu *vcpu)
3283{
2961e876 3284 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3285 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3286}
3287
3288#endif
3289
2384d2b3
SY		 3290static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3291{
b9d762fa 3292 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3293 if (enable_ept) {
3294 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3295 return;
4e1096d2 3296 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3297 }
2384d2b3
SY		 3298}
3299
e8467fda
AK		 3300static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3301{
3302 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3303
3304 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3305 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3306}
3307
aff48baa
AK		 3308static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3309{
3310 if (enable_ept && is_paging(vcpu))
3311 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3312 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3313}
3314
25c4c276 3315static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3316{
fc78f519
AK		 3317 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3318
3319 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3320 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3321}
3322
1439442c
SY		 3323static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3324{
d0d538b9
GN		 3325 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3326
6de4f3ad
AK		 3327 if (!test_bit(VCPU_EXREG_PDPTR,
3328 (unsigned long *)&vcpu->arch.regs_dirty))
3329 return;
3330
1439442c 3331 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3332 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3333 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3334 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3335 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3336 }
3337}
3338
8f5d549f
AK		 3339static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3340{
d0d538b9
GN		 3341 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3342
8f5d549f 3343 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3344 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3345 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3346 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3347 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3348 }
6de4f3ad
AK		 3349
3350 __set_bit(VCPU_EXREG_PDPTR,
3351 (unsigned long *)&vcpu->arch.regs_avail);
3352 __set_bit(VCPU_EXREG_PDPTR,
3353 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3354}
3355
5e1746d6 3356static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3357
3358static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3359 unsigned long cr0,
3360 struct kvm_vcpu *vcpu)
3361{
5233dd51
MT		 3362 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3363 vmx_decache_cr3(vcpu);
1439442c
SY		 3364 if (!(cr0 & X86_CR0_PG)) {
3365 /* From paging/starting to nonpaging */
3366 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3367 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3368 (CPU_BASED_CR3_LOAD_EXITING |
3369 CPU_BASED_CR3_STORE_EXITING));
3370 vcpu->arch.cr0 = cr0;
fc78f519 3371 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3372 } else if (!is_paging(vcpu)) {
3373 /* From nonpaging to paging */
3374 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3375 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3376 ~(CPU_BASED_CR3_LOAD_EXITING |
3377 CPU_BASED_CR3_STORE_EXITING));
3378 vcpu->arch.cr0 = cr0;
fc78f519 3379 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3380 }
95eb84a7
SY		 3381
3382 if (!(cr0 & X86_CR0_WP))
3383 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3384}
3385
6aa8b732
AK		 3386static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3387{
7ffd92c5 3388 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3389 unsigned long hw_cr0;
3390
5037878e 3391 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3392 if (enable_unrestricted_guest)
5037878e 3393 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3394 else {
5037878e 3395 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3396
218e763f
GN		 3397 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3398 enter_pmode(vcpu);
6aa8b732 3399
218e763f
GN		 3400 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3401 enter_rmode(vcpu);
3402 }
6aa8b732 3403
05b3e0c2 3404#ifdef CONFIG_X86_64
f6801dff 3405 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3406 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3407 enter_lmode(vcpu);
707d92fa 3408 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3409 exit_lmode(vcpu);
3410 }
3411#endif
3412
089d034e 3413 if (enable_ept)
1439442c
SY		 3414 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3415
02daab21 3416 if (!vcpu->fpu_active)
81231c69 3417 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3418
6aa8b732 3419 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3420 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3421 vcpu->arch.cr0 = cr0;
14168786
GN		 3422
3423 /* depends on vcpu->arch.cr0 to be set to a new value */
3424 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3425}
3426
1439442c
SY		 3427static u64 construct_eptp(unsigned long root_hpa)
3428{
3429 u64 eptp;
3430
3431 /* TODO write the value reading from MSR */
3432 eptp = VMX_EPT_DEFAULT_MT |
3433 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3434 if (enable_ept_ad_bits)
3435 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3436 eptp |= (root_hpa & PAGE_MASK);
3437
3438 return eptp;
3439}
3440
6aa8b732
AK		 3441static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3442{
1439442c
SY		 3443 unsigned long guest_cr3;
3444 u64 eptp;
3445
3446 guest_cr3 = cr3;
089d034e 3447 if (enable_ept) {
1439442c
SY		 3448 eptp = construct_eptp(cr3);
3449 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3450 if (is_paging(vcpu) || is_guest_mode(vcpu))
3451 guest_cr3 = kvm_read_cr3(vcpu);
3452 else
3453 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3454 ept_load_pdptrs(vcpu);
1439442c
SY		 3455 }
3456
2384d2b3 3457 vmx_flush_tlb(vcpu);
1439442c 3458 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3459}
3460
5e1746d6 3461static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3462{
7ffd92c5 3463 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3464 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3465
5e1746d6
NHE		 3466 if (cr4 & X86_CR4_VMXE) {
3467 /*
3468 * To use VMXON (and later other VMX instructions), a guest
3469 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3470 * So basically the check on whether to allow nested VMX
3471 * is here.
3472 */
3473 if (!nested_vmx_allowed(vcpu))
3474 return 1;
1a0d74e6
JK		 3475 }
3476 if (to_vmx(vcpu)->nested.vmxon &&
3477 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3478 return 1;
3479
ad312c7c 3480 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3481 if (enable_ept) {
3482 if (!is_paging(vcpu)) {
3483 hw_cr4 &= ~X86_CR4_PAE;
3484 hw_cr4 |= X86_CR4_PSE;
c08800a5 3485 /*
e1e746b3
FW		 3486 * SMEP/SMAP is disabled if CPU is in non-paging mode
3487 * in hardware. However KVM always uses paging mode to
c08800a5 3488 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3489 * To emulate this behavior, SMEP/SMAP needs to be
3490 * manually disabled when guest switches to non-paging
3491 * mode.
c08800a5 3492 */
e1e746b3 3493 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3494 } else if (!(cr4 & X86_CR4_PAE)) {
3495 hw_cr4 &= ~X86_CR4_PAE;
3496 }
3497 }
1439442c
SY		 3498
3499 vmcs_writel(CR4_READ_SHADOW, cr4);
3500 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3501 return 0;
6aa8b732
AK		 3502}
3503
6aa8b732
AK		 3504static void vmx_get_segment(struct kvm_vcpu *vcpu,
3505 struct kvm_segment *var, int seg)
3506{
a9179499 3507 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3508 u32 ar;
3509
c6ad1153 3510 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3511 *var = vmx->rmode.segs[seg];
a9179499 3512 if (seg == VCPU_SREG_TR
2fb92db1 3513 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3514 return;
1390a28b
AK		 3515 var->base = vmx_read_guest_seg_base(vmx, seg);
3516 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3517 return;
a9179499 3518 }
2fb92db1
AK		 3519 var->base = vmx_read_guest_seg_base(vmx, seg);
3520 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3521 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3522 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3523 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3524 var->type = ar & 15;
3525 var->s = (ar >> 4) & 1;
3526 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3527 /*
3528 * Some userspaces do not preserve unusable property. Since usable
3529 * segment has to be present according to VMX spec we can use present
3530 * property to amend userspace bug by making unusable segment always
3531 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3532 * segment as unusable.
3533 */
3534 var->present = !var->unusable;
6aa8b732
AK		 3535 var->avl = (ar >> 12) & 1;
3536 var->l = (ar >> 13) & 1;
3537 var->db = (ar >> 14) & 1;
3538 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3539}
3540
a9179499
AK		 3541static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3542{
a9179499
AK		 3543 struct kvm_segment s;
3544
3545 if (to_vmx(vcpu)->rmode.vm86_active) {
3546 vmx_get_segment(vcpu, &s, seg);
3547 return s.base;
3548 }
2fb92db1 3549 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3550}
3551
b09408d0 3552static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3553{
b09408d0
MT		 3554 struct vcpu_vmx *vmx = to_vmx(vcpu);
3555
3eeb3288 3556 if (!is_protmode(vcpu))
2e4d2653
IE		 3557 return 0;
3558
f4c63e5d
AK		 3559 if (!is_long_mode(vcpu)
3560 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3561 return 3;
3562
69c73028
AK		 3563 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3564 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3565 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3566 }
d881e6f6
AK		 3567
3568 return vmx->cpl;
69c73028
AK		 3569}
3570
3571
653e3108 3572static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3573{
6aa8b732
AK		 3574 u32 ar;
3575
f0495f9b 3576 if (var->unusable || !var->present)
6aa8b732
AK		 3577 ar = 1 << 16;
3578 else {
3579 ar = var->type & 15;
3580 ar |= (var->s & 1) << 4;
3581 ar |= (var->dpl & 3) << 5;
3582 ar |= (var->present & 1) << 7;
3583 ar |= (var->avl & 1) << 12;
3584 ar |= (var->l & 1) << 13;
3585 ar |= (var->db & 1) << 14;
3586 ar |= (var->g & 1) << 15;
3587 }
653e3108
AK		 3588
3589 return ar;
3590}
3591
3592static void vmx_set_segment(struct kvm_vcpu *vcpu,
3593 struct kvm_segment *var, int seg)
3594{
7ffd92c5 3595 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3596 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3597
2fb92db1 3598 vmx_segment_cache_clear(vmx);
2f143240
GN		 3599 if (seg == VCPU_SREG_CS)
3600 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3601
1ecd50a9
GN		 3602 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3603 vmx->rmode.segs[seg] = *var;
3604 if (seg == VCPU_SREG_TR)
3605 vmcs_write16(sf->selector, var->selector);
3606 else if (var->s)
3607 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3608 goto out;
653e3108 3609 }
1ecd50a9 3610
653e3108
AK		 3611 vmcs_writel(sf->base, var->base);
3612 vmcs_write32(sf->limit, var->limit);
3613 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3614
3615 /*
3616 * Fix the "Accessed" bit in AR field of segment registers for older
3617 * qemu binaries.
3618 * IA32 arch specifies that at the time of processor reset the
3619 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3620 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3621 * state vmexit when "unrestricted guest" mode is turned on.
3622 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3623 * tree. Newer qemu binaries with that qemu fix would not need this
3624 * kvm hack.
3625 */
3626 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3627 var->type |= 0x1; /* Accessed */
3a624e29 3628
f924d66d 3629 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3630
3631out:
14168786 3632 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3633}
3634
6aa8b732
AK		 3635static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3636{
2fb92db1 3637 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3638
3639 *db = (ar >> 14) & 1;
3640 *l = (ar >> 13) & 1;
3641}
3642
89a27f4d 3643static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3644{
89a27f4d
GN		 3645 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3646 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3647}
3648
89a27f4d 3649static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3650{
89a27f4d
GN		 3651 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3652 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3653}
3654
89a27f4d 3655static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3656{
89a27f4d
GN		 3657 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3658 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3659}
3660
89a27f4d 3661static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3662{
89a27f4d
GN		 3663 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3664 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3665}
3666
648dfaa7
MG		 3667static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3668{
3669 struct kvm_segment var;
3670 u32 ar;
3671
3672 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3673 var.dpl = 0x3;
0647f4aa
GN		 3674 if (seg == VCPU_SREG_CS)
3675 var.type = 0x3;
648dfaa7
MG		 3676 ar = vmx_segment_access_rights(&var);
3677
3678 if (var.base != (var.selector << 4))
3679 return false;
89efbed0 3680 if (var.limit != 0xffff)
648dfaa7 3681 return false;
07f42f5f 3682 if (ar != 0xf3)
648dfaa7
MG		 3683 return false;
3684
3685 return true;
3686}
3687
3688static bool code_segment_valid(struct kvm_vcpu *vcpu)
3689{
3690 struct kvm_segment cs;
3691 unsigned int cs_rpl;
3692
3693 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3694 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3695
1872a3f4
AK		 3696 if (cs.unusable)
3697 return false;
648dfaa7
MG		 3698 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3699 return false;
3700 if (!cs.s)
3701 return false;
1872a3f4 3702 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3703 if (cs.dpl > cs_rpl)
3704 return false;
1872a3f4 3705 } else {
648dfaa7
MG		 3706 if (cs.dpl != cs_rpl)
3707 return false;
3708 }
3709 if (!cs.present)
3710 return false;
3711
3712 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3713 return true;
3714}
3715
3716static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3717{
3718 struct kvm_segment ss;
3719 unsigned int ss_rpl;
3720
3721 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3722 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3723
1872a3f4
AK		 3724 if (ss.unusable)
3725 return true;
3726 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3727 return false;
3728 if (!ss.s)
3729 return false;
3730 if (ss.dpl != ss_rpl) /* DPL != RPL */
3731 return false;
3732 if (!ss.present)
3733 return false;
3734
3735 return true;
3736}
3737
3738static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3739{
3740 struct kvm_segment var;
3741 unsigned int rpl;
3742
3743 vmx_get_segment(vcpu, &var, seg);
3744 rpl = var.selector & SELECTOR_RPL_MASK;
3745
1872a3f4
AK		 3746 if (var.unusable)
3747 return true;
648dfaa7
MG		 3748 if (!var.s)
3749 return false;
3750 if (!var.present)
3751 return false;
3752 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3753 if (var.dpl < rpl) /* DPL < RPL */
3754 return false;
3755 }
3756
3757 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3758 * rights flags
3759 */
3760 return true;
3761}
3762
3763static bool tr_valid(struct kvm_vcpu *vcpu)
3764{
3765 struct kvm_segment tr;
3766
3767 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3768
1872a3f4
AK		 3769 if (tr.unusable)
3770 return false;
648dfaa7
MG		 3771 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3772 return false;
1872a3f4 3773 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3774 return false;
3775 if (!tr.present)
3776 return false;
3777
3778 return true;
3779}
3780
3781static bool ldtr_valid(struct kvm_vcpu *vcpu)
3782{
3783 struct kvm_segment ldtr;
3784
3785 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3786
1872a3f4
AK		 3787 if (ldtr.unusable)
3788 return true;
648dfaa7
MG		 3789 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3790 return false;
3791 if (ldtr.type != 2)
3792 return false;
3793 if (!ldtr.present)
3794 return false;
3795
3796 return true;
3797}
3798
3799static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3800{
3801 struct kvm_segment cs, ss;
3802
3803 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3804 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3805
3806 return ((cs.selector & SELECTOR_RPL_MASK) ==
3807 (ss.selector & SELECTOR_RPL_MASK));
3808}
3809
3810/*
3811 * Check if guest state is valid. Returns true if valid, false if
3812 * not.
3813 * We assume that registers are always usable
3814 */
3815static bool guest_state_valid(struct kvm_vcpu *vcpu)
3816{
c5e97c80
GN		 3817 if (enable_unrestricted_guest)
3818 return true;
3819
648dfaa7 3820 /* real mode guest state checks */
f13882d8 3821 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3822 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3823 return false;
3824 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3825 return false;
3826 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3827 return false;
3828 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3829 return false;
3830 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3831 return false;
3832 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3833 return false;
3834 } else {
3835 /* protected mode guest state checks */
3836 if (!cs_ss_rpl_check(vcpu))
3837 return false;
3838 if (!code_segment_valid(vcpu))
3839 return false;
3840 if (!stack_segment_valid(vcpu))
3841 return false;
3842 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3843 return false;
3844 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3845 return false;
3846 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3847 return false;
3848 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3849 return false;
3850 if (!tr_valid(vcpu))
3851 return false;
3852 if (!ldtr_valid(vcpu))
3853 return false;
3854 }
3855 /* TODO:
3856 * - Add checks on RIP
3857 * - Add checks on RFLAGS
3858 */
3859
3860 return true;
3861}
3862
d77c26fc 3863static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3864{
40dcaa9f 3865 gfn_t fn;
195aefde 3866 u16 data = 0;
40dcaa9f 3867 int r, idx, ret = 0;
6aa8b732 3868
40dcaa9f 3869 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3870 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3871 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3872 if (r < 0)
10589a46 3873 goto out;
195aefde 3874 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3875 r = kvm_write_guest_page(kvm, fn++, &data,
3876 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3877 if (r < 0)
10589a46 3878 goto out;
195aefde
IE		 3879 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3880 if (r < 0)
10589a46 3881 goto out;
195aefde
IE		 3882 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3883 if (r < 0)
10589a46 3884 goto out;
195aefde 3885 data = ~0;
10589a46
MT		 3886 r = kvm_write_guest_page(kvm, fn, &data,
3887 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3888 sizeof(u8));
195aefde 3889 if (r < 0)
10589a46
MT		 3890 goto out;
3891
3892 ret = 1;
3893out:
40dcaa9f 3894 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3895 return ret;
6aa8b732
AK		 3896}
3897
b7ebfb05
SY		 3898static int init_rmode_identity_map(struct kvm *kvm)
3899{
40dcaa9f 3900 int i, idx, r, ret;
b7ebfb05
SY		 3901 pfn_t identity_map_pfn;
3902 u32 tmp;
3903
089d034e 3904 if (!enable_ept)
b7ebfb05
SY		 3905 return 1;
3906 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3907 printk(KERN_ERR "EPT: identity-mapping pagetable "
3908 "haven't been allocated!\n");
3909 return 0;
3910 }
3911 if (likely(kvm->arch.ept_identity_pagetable_done))
3912 return 1;
3913 ret = 0;
b927a3ce 3914 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3915 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3916 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3917 if (r < 0)
3918 goto out;
3919 /* Set up identity-mapping pagetable for EPT in real mode */
3920 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3921 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3922 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3923 r = kvm_write_guest_page(kvm, identity_map_pfn,
3924 &tmp, i * sizeof(tmp), sizeof(tmp));
3925 if (r < 0)
3926 goto out;
3927 }
3928 kvm->arch.ept_identity_pagetable_done = true;
3929 ret = 1;
3930out:
40dcaa9f 3931 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3932 return ret;
3933}
3934
6aa8b732
AK		 3935static void seg_setup(int seg)
3936{
772e0318 3937 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3938 unsigned int ar;
6aa8b732
AK		 3939
3940 vmcs_write16(sf->selector, 0);
3941 vmcs_writel(sf->base, 0);
3942 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3943 ar = 0x93;
3944 if (seg == VCPU_SREG_CS)
3945 ar |= 0x08; /* code segment */
3a624e29
NK		 3946
3947 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3948}
3949
f78e0e2e
SY		 3950static int alloc_apic_access_page(struct kvm *kvm)
3951{
4484141a 3952 struct page *page;
f78e0e2e
SY		 3953 struct kvm_userspace_memory_region kvm_userspace_mem;
3954 int r = 0;
3955
79fac95e 3956 mutex_lock(&kvm->slots_lock);
bfc6d222 3957 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3958 goto out;
3959 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3960 kvm_userspace_mem.flags = 0;
3961 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3962 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3963 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3964 if (r)
3965 goto out;
72dc67a6 3966
4484141a
XG		 3967 page = gfn_to_page(kvm, 0xfee00);
3968 if (is_error_page(page)) {
3969 r = -EFAULT;
3970 goto out;
3971 }
3972
3973 kvm->arch.apic_access_page = page;
f78e0e2e 3974out:
79fac95e 3975 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3976 return r;
3977}
3978
b7ebfb05
SY		 3979static int alloc_identity_pagetable(struct kvm *kvm)
3980{
4484141a 3981 struct page *page;
b7ebfb05
SY		 3982 struct kvm_userspace_memory_region kvm_userspace_mem;
3983 int r = 0;
3984
79fac95e 3985 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3986 if (kvm->arch.ept_identity_pagetable)
3987 goto out;
3988 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3989 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3990 kvm_userspace_mem.guest_phys_addr =
3991 kvm->arch.ept_identity_map_addr;
b7ebfb05 3992 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3993 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3994 if (r)
3995 goto out;
3996
4484141a
XG		 3997 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3998 if (is_error_page(page)) {
3999 r = -EFAULT;
4000 goto out;
4001 }
4002
4003 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4004out:
79fac95e 4005 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4006 return r;
4007}
4008
2384d2b3
SY		 4009static void allocate_vpid(struct vcpu_vmx *vmx)
4010{
4011 int vpid;
4012
4013 vmx->vpid = 0;
919818ab 4014 if (!enable_vpid)
2384d2b3
SY		 4015 return;
4016 spin_lock(&vmx_vpid_lock);
4017 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4018 if (vpid < VMX_NR_VPIDS) {
4019 vmx->vpid = vpid;
4020 __set_bit(vpid, vmx_vpid_bitmap);
4021 }
4022 spin_unlock(&vmx_vpid_lock);
4023}
4024
cdbecfc3
LJ		 4025static void free_vpid(struct vcpu_vmx *vmx)
4026{
4027 if (!enable_vpid)
4028 return;
4029 spin_lock(&vmx_vpid_lock);
4030 if (vmx->vpid != 0)
4031 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4032 spin_unlock(&vmx_vpid_lock);
4033}
4034
8d14695f
YZ		 4035#define MSR_TYPE_R 1
4036#define MSR_TYPE_W 2
4037static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4038 u32 msr, int type)
25c5f225 4039{
3e7c73e9 4040 int f = sizeof(unsigned long);
25c5f225
SY		 4041
4042 if (!cpu_has_vmx_msr_bitmap())
4043 return;
4044
4045 /*
4046 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4047 * have the write-low and read-high bitmap offsets the wrong way round.
4048 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4049 */
25c5f225 4050 if (msr <= 0x1fff) {
8d14695f
YZ		 4051 if (type & MSR_TYPE_R)
4052 /* read-low */
4053 __clear_bit(msr, msr_bitmap + 0x000 / f);
4054
4055 if (type & MSR_TYPE_W)
4056 /* write-low */
4057 __clear_bit(msr, msr_bitmap + 0x800 / f);
4058
25c5f225
SY		 4059 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4060 msr &= 0x1fff;
8d14695f
YZ		 4061 if (type & MSR_TYPE_R)
4062 /* read-high */
4063 __clear_bit(msr, msr_bitmap + 0x400 / f);
4064
4065 if (type & MSR_TYPE_W)
4066 /* write-high */
4067 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4068
4069 }
4070}
4071
4072static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4073 u32 msr, int type)
4074{
4075 int f = sizeof(unsigned long);
4076
4077 if (!cpu_has_vmx_msr_bitmap())
4078 return;
4079
4080 /*
4081 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4082 * have the write-low and read-high bitmap offsets the wrong way round.
4083 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4084 */
4085 if (msr <= 0x1fff) {
4086 if (type & MSR_TYPE_R)
4087 /* read-low */
4088 __set_bit(msr, msr_bitmap + 0x000 / f);
4089
4090 if (type & MSR_TYPE_W)
4091 /* write-low */
4092 __set_bit(msr, msr_bitmap + 0x800 / f);
4093
4094 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4095 msr &= 0x1fff;
4096 if (type & MSR_TYPE_R)
4097 /* read-high */
4098 __set_bit(msr, msr_bitmap + 0x400 / f);
4099
4100 if (type & MSR_TYPE_W)
4101 /* write-high */
4102 __set_bit(msr, msr_bitmap + 0xc00 / f);
4103
25c5f225 4104 }
25c5f225
SY		 4105}
4106
5897297b
AK		 4107static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4108{
4109 if (!longmode_only)
8d14695f
YZ		 4110 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4111 msr, MSR_TYPE_R | MSR_TYPE_W);
4112 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4113 msr, MSR_TYPE_R | MSR_TYPE_W);
4114}
4115
4116static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4117{
4118 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4119 msr, MSR_TYPE_R);
4120 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4121 msr, MSR_TYPE_R);
4122}
4123
4124static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4125{
4126 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4127 msr, MSR_TYPE_R);
4128 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4129 msr, MSR_TYPE_R);
4130}
4131
4132static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4133{
4134 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4135 msr, MSR_TYPE_W);
4136 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4137 msr, MSR_TYPE_W);
5897297b
AK		 4138}
4139
01e439be
YZ		 4140static int vmx_vm_has_apicv(struct kvm *kvm)
4141{
4142 return enable_apicv && irqchip_in_kernel(kvm);
4143}
4144
a20ed54d
YZ		 4145/*
4146 * Send interrupt to vcpu via posted interrupt way.
4147 * 1. If target vcpu is running(non-root mode), send posted interrupt
4148 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4149 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4150 * interrupt from PIR in next vmentry.
4151 */
4152static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4153{
4154 struct vcpu_vmx *vmx = to_vmx(vcpu);
4155 int r;
4156
4157 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4158 return;
4159
4160 r = pi_test_and_set_on(&vmx->pi_desc);
4161 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4162#ifdef CONFIG_SMP
a20ed54d
YZ		 4163 if (!r && (vcpu->mode == IN_GUEST_MODE))
4164 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4165 POSTED_INTR_VECTOR);
4166 else
6ffbbbba 4167#endif
a20ed54d
YZ		 4168 kvm_vcpu_kick(vcpu);
4169}
4170
4171static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4172{
4173 struct vcpu_vmx *vmx = to_vmx(vcpu);
4174
4175 if (!pi_test_and_clear_on(&vmx->pi_desc))
4176 return;
4177
4178 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4179}
4180
4181static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4182{
4183 return;
4184}
4185
a3a8ff8e
NHE		 4186/*
4187 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4188 * will not change in the lifetime of the guest.
4189 * Note that host-state that does change is set elsewhere. E.g., host-state
4190 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4191 */
a547c6db 4192static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4193{
4194 u32 low32, high32;
4195 unsigned long tmpl;
4196 struct desc_ptr dt;
4197
b1a74bf8 4198 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4199 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4200 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4201
4202 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4203#ifdef CONFIG_X86_64
4204 /*
4205 * Load null selectors, so we can avoid reloading them in
4206 * __vmx_load_host_state(), in case userspace uses the null selectors
4207 * too (the expected case).
4208 */
4209 vmcs_write16(HOST_DS_SELECTOR, 0);
4210 vmcs_write16(HOST_ES_SELECTOR, 0);
4211#else
a3a8ff8e
NHE		 4212 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4213 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4214#endif
a3a8ff8e
NHE		 4215 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4216 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4217
4218 native_store_idt(&dt);
4219 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4220 vmx->host_idt_base = dt.address;
a3a8ff8e 4221
83287ea4 4222 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4223
4224 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4225 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4226 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4227 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4228
4229 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4230 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4231 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4232 }
4233}
4234
bf8179a0
NHE		 4235static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4236{
4237 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4238 if (enable_ept)
4239 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4240 if (is_guest_mode(&vmx->vcpu))
4241 vmx->vcpu.arch.cr4_guest_owned_bits &=
4242 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4243 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4244}
4245
01e439be
YZ		 4246static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4247{
4248 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4249
4250 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4251 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4252 return pin_based_exec_ctrl;
4253}
4254
bf8179a0
NHE		 4255static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4256{
4257 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4258
4259 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4260 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4261
bf8179a0
NHE		 4262 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4263 exec_control &= ~CPU_BASED_TPR_SHADOW;
4264#ifdef CONFIG_X86_64
4265 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4266 CPU_BASED_CR8_LOAD_EXITING;
4267#endif
4268 }
4269 if (!enable_ept)
4270 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4271 CPU_BASED_CR3_LOAD_EXITING |
4272 CPU_BASED_INVLPG_EXITING;
4273 return exec_control;
4274}
4275
4276static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4277{
4278 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4279 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4280 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4281 if (vmx->vpid == 0)
4282 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4283 if (!enable_ept) {
4284 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4285 enable_unrestricted_guest = 0;
ad756a16
MJ		 4286 /* Enable INVPCID for non-ept guests may cause performance regression. */
4287 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4288 }
4289 if (!enable_unrestricted_guest)
4290 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4291 if (!ple_gap)
4292 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4293 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4294 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4295 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4296 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4297 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4298 (handle_vmptrld).
4299 We can NOT enable shadow_vmcs here because we don't have yet
4300 a current VMCS12
4301 */
4302 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4303 return exec_control;
4304}
4305
ce88decf
XG		 4306static void ept_set_mmio_spte_mask(void)
4307{
4308 /*
4309 * EPT Misconfigurations can be generated if the value of bits 2:0
4310 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4311 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4312 * spte.
4313 */
885032b9 4314 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4315}
4316
6aa8b732
AK		 4317/*
4318 * Sets up the vmcs for emulated real mode.
4319 */
8b9cf98c 4320static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4321{
2e4ce7f5 4322#ifdef CONFIG_X86_64
6aa8b732 4323 unsigned long a;
2e4ce7f5 4324#endif
6aa8b732 4325 int i;
6aa8b732 4326
6aa8b732 4327 /* I/O */
3e7c73e9
AK		 4328 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4329 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4330
4607c2d7
AG		 4331 if (enable_shadow_vmcs) {
4332 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4333 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4334 }
25c5f225 4335 if (cpu_has_vmx_msr_bitmap())
5897297b 4336 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4337
6aa8b732
AK		 4338 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4339
6aa8b732 4340 /* Control */
01e439be 4341 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4342
bf8179a0 4343 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4344
83ff3b9d 4345 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4346 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4347 vmx_secondary_exec_control(vmx));
83ff3b9d 4348 }
f78e0e2e 4349
01e439be 4350 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4351 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4352 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4353 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4354 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4355
4356 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4357
4358 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4359 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4360 }
4361
4b8d54f9
ZE		 4362 if (ple_gap) {
4363 vmcs_write32(PLE_GAP, ple_gap);
4364 vmcs_write32(PLE_WINDOW, ple_window);
4365 }
4366
c3707958
XG		 4367 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4368 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4369 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4370
9581d442
AK		 4371 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4372 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4373 vmx_set_constant_host_state(vmx);
05b3e0c2 4374#ifdef CONFIG_X86_64
6aa8b732
AK		 4375 rdmsrl(MSR_FS_BASE, a);
4376 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4377 rdmsrl(MSR_GS_BASE, a);
4378 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4379#else
4380 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4381 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4382#endif
4383
2cc51560
ED		 4384 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4385 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4386 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4387 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4388 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4389
468d472f 4390 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4391 u32 msr_low, msr_high;
4392 u64 host_pat;
468d472f
SY		 4393 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4394 host_pat = msr_low | ((u64) msr_high << 32);
4395 /* Write the default value follow host pat */
4396 vmcs_write64(GUEST_IA32_PAT, host_pat);
4397 /* Keep arch.pat sync with GUEST_IA32_PAT */
4398 vmx->vcpu.arch.pat = host_pat;
4399 }
4400
6aa8b732
AK		 4401 for (i = 0; i < NR_VMX_MSR; ++i) {
4402 u32 index = vmx_msr_index[i];
4403 u32 data_low, data_high;
a2fa3e9f 4404 int j = vmx->nmsrs;
6aa8b732
AK		 4405
4406 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4407 continue;
432bd6cb
AK		 4408 if (wrmsr_safe(index, data_low, data_high) < 0)
4409 continue;
26bb0981
AK		 4410 vmx->guest_msrs[j].index = i;
4411 vmx->guest_msrs[j].data = 0;
d5696725 4412 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4413 ++vmx->nmsrs;
6aa8b732 4414 }
6aa8b732 4415
2961e876
GN		 4416
4417 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4418
4419 /* 22.2.1, 20.8.1 */
2961e876 4420 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4421
e00c8cf2 4422 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4423 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4424
4425 return 0;
4426}
4427
57f252f2 4428static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4429{
4430 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4431 struct msr_data apic_base_msr;
e00c8cf2 4432
7ffd92c5 4433 vmx->rmode.vm86_active = 0;
e00c8cf2 4434
3b86cd99
JK		 4435 vmx->soft_vnmi_blocked = 0;
4436
ad312c7c 4437 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4438 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4439 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4440 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4441 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4442 apic_base_msr.host_initiated = true;
4443 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4444
2fb92db1
AK		 4445 vmx_segment_cache_clear(vmx);
4446
5706be0d 4447 seg_setup(VCPU_SREG_CS);
66450a21 4448 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4449 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4450
4451 seg_setup(VCPU_SREG_DS);
4452 seg_setup(VCPU_SREG_ES);
4453 seg_setup(VCPU_SREG_FS);
4454 seg_setup(VCPU_SREG_GS);
4455 seg_setup(VCPU_SREG_SS);
4456
4457 vmcs_write16(GUEST_TR_SELECTOR, 0);
4458 vmcs_writel(GUEST_TR_BASE, 0);
4459 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4460 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4461
4462 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4463 vmcs_writel(GUEST_LDTR_BASE, 0);
4464 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4465 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4466
4467 vmcs_write32(GUEST_SYSENTER_CS, 0);
4468 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4469 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4470
4471 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4472 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4473
e00c8cf2
AK		 4474 vmcs_writel(GUEST_GDTR_BASE, 0);
4475 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4476
4477 vmcs_writel(GUEST_IDTR_BASE, 0);
4478 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4479
443381a8 4480 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4481 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4482 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4483
e00c8cf2
AK		 4484 /* Special registers */
4485 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4486
4487 setup_msrs(vmx);
4488
6aa8b732
AK		 4489 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4490
f78e0e2e
SY		 4491 if (cpu_has_vmx_tpr_shadow()) {
4492 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4493 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4494 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4495 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4496 vmcs_write32(TPR_THRESHOLD, 0);
4497 }
4498
4499 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4500 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4501 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4502
01e439be
YZ		 4503 if (vmx_vm_has_apicv(vcpu->kvm))
4504 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4505
2384d2b3
SY		 4506 if (vmx->vpid != 0)
4507 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4508
fa40052c 4509 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4510 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4511 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4512 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4513 vmx_fpu_activate(&vmx->vcpu);
4514 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4515
b9d762fa 4516 vpid_sync_context(vmx);
6aa8b732
AK		 4517}
4518
b6f1250e
NHE		 4519/*
4520 * In nested virtualization, check if L1 asked to exit on external interrupts.
4521 * For most existing hypervisors, this will always return true.
4522 */
4523static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4524{
4525 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4526 PIN_BASED_EXT_INTR_MASK;
4527}
4528
ea8ceb83
JK		 4529static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4530{
4531 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4532 PIN_BASED_NMI_EXITING;
4533}
4534
c9a7953f 4535static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4536{
4537 u32 cpu_based_vm_exec_control;
730dca42 4538
3b86cd99
JK		 4539 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4540 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4542}
4543
c9a7953f 4544static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4545{
4546 u32 cpu_based_vm_exec_control;
4547
c9a7953f
JK		 4548 if (!cpu_has_virtual_nmis() ||
4549 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4550 enable_irq_window(vcpu);
4551 return;
4552 }
3b86cd99
JK		 4553
4554 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4555 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4556 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4557}
4558
66fd3f7f 4559static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4560{
9c8cba37 4561 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4562 uint32_t intr;
4563 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4564
229456fc 4565 trace_kvm_inj_virq(irq);
2714d1d3 4566
fa89a817 4567 ++vcpu->stat.irq_injections;
7ffd92c5 4568 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4569 int inc_eip = 0;
4570 if (vcpu->arch.interrupt.soft)
4571 inc_eip = vcpu->arch.event_exit_inst_len;
4572 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4573 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4574 return;
4575 }
66fd3f7f
GN		 4576 intr = irq | INTR_INFO_VALID_MASK;
4577 if (vcpu->arch.interrupt.soft) {
4578 intr |= INTR_TYPE_SOFT_INTR;
4579 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4580 vmx->vcpu.arch.event_exit_inst_len);
4581 } else
4582 intr |= INTR_TYPE_EXT_INTR;
4583 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4584}
4585
f08864b4
SY		 4586static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4587{
66a5a347
JK		 4588 struct vcpu_vmx *vmx = to_vmx(vcpu);
4589
0b6ac343
NHE		 4590 if (is_guest_mode(vcpu))
4591 return;
4592
3b86cd99
JK		 4593 if (!cpu_has_virtual_nmis()) {
4594 /*
4595 * Tracking the NMI-blocked state in software is built upon
4596 * finding the next open IRQ window. This, in turn, depends on
4597 * well-behaving guests: They have to keep IRQs disabled at
4598 * least as long as the NMI handler runs. Otherwise we may
4599 * cause NMI nesting, maybe breaking the guest. But as this is
4600 * highly unlikely, we can live with the residual risk.
4601 */
4602 vmx->soft_vnmi_blocked = 1;
4603 vmx->vnmi_blocked_time = 0;
4604 }
4605
487b391d 4606 ++vcpu->stat.nmi_injections;
9d58b931 4607 vmx->nmi_known_unmasked = false;
7ffd92c5 4608 if (vmx->rmode.vm86_active) {
71f9833b 4609 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4610 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4611 return;
4612 }
f08864b4
SY		 4613 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4614 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4615}
4616
3cfc3092
JK		 4617static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4618{
4619 if (!cpu_has_virtual_nmis())
4620 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4621 if (to_vmx(vcpu)->nmi_known_unmasked)
4622 return false;
c332c83a 4623 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4624}
4625
4626static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4627{
4628 struct vcpu_vmx *vmx = to_vmx(vcpu);
4629
4630 if (!cpu_has_virtual_nmis()) {
4631 if (vmx->soft_vnmi_blocked != masked) {
4632 vmx->soft_vnmi_blocked = masked;
4633 vmx->vnmi_blocked_time = 0;
4634 }
4635 } else {
9d58b931 4636 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4637 if (masked)
4638 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4639 GUEST_INTR_STATE_NMI);
4640 else
4641 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4642 GUEST_INTR_STATE_NMI);
4643 }
4644}
4645
2505dc9f
JK		 4646static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4647{
b6b8a145
JK		 4648 if (to_vmx(vcpu)->nested.nested_run_pending)
4649 return 0;
ea8ceb83 4650
2505dc9f
JK		 4651 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4652 return 0;
4653
4654 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4655 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4656 | GUEST_INTR_STATE_NMI));
4657}
4658
78646121
GN		 4659static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4660{
b6b8a145
JK		 4661 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4662 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4663 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4664 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4665}
4666
cbc94022
IE		 4667static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4668{
4669 int ret;
4670 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4671 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4672 .guest_phys_addr = addr,
4673 .memory_size = PAGE_SIZE * 3,
4674 .flags = 0,
4675 };
4676
47ae31e2 4677 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4678 if (ret)
4679 return ret;
bfc6d222 4680 kvm->arch.tss_addr = addr;
93ea5388
GN		 4681 if (!init_rmode_tss(kvm))
4682 return -ENOMEM;
4683
cbc94022
IE		 4684 return 0;
4685}
4686
0ca1b4f4 4687static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4688{
77ab6db0 4689 switch (vec) {
77ab6db0 4690 case BP_VECTOR:
c573cd22
JK		 4691 /*
4692 * Update instruction length as we may reinject the exception
4693 * from user space while in guest debugging mode.
4694 */
4695 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4696 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4697 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4698 return false;
4699 /* fall through */
4700 case DB_VECTOR:
4701 if (vcpu->guest_debug &
4702 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4703 return false;
d0bfb940
JK		 4704 /* fall through */
4705 case DE_VECTOR:
77ab6db0
JK		 4706 case OF_VECTOR:
4707 case BR_VECTOR:
4708 case UD_VECTOR:
4709 case DF_VECTOR:
4710 case SS_VECTOR:
4711 case GP_VECTOR:
4712 case MF_VECTOR:
0ca1b4f4
GN		 4713 return true;
4714 break;
77ab6db0 4715 }
0ca1b4f4
GN		 4716 return false;
4717}
4718
4719static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4720 int vec, u32 err_code)
4721{
4722 /*
4723 * Instruction with address size override prefix opcode 0x67
4724 * Cause the #SS fault with 0 error code in VM86 mode.
4725 */
4726 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4727 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4728 if (vcpu->arch.halt_request) {
4729 vcpu->arch.halt_request = 0;
4730 return kvm_emulate_halt(vcpu);
4731 }
4732 return 1;
4733 }
4734 return 0;
4735 }
4736
4737 /*
4738 * Forward all other exceptions that are valid in real mode.
4739 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4740 * the required debugging infrastructure rework.
4741 */
4742 kvm_queue_exception(vcpu, vec);
4743 return 1;
6aa8b732
AK		 4744}
4745
a0861c02
AK		 4746/*
4747 * Trigger machine check on the host. We assume all the MSRs are already set up
4748 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4749 * We pass a fake environment to the machine check handler because we want
4750 * the guest to be always treated like user space, no matter what context
4751 * it used internally.
4752 */
4753static void kvm_machine_check(void)
4754{
4755#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4756 struct pt_regs regs = {
4757 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4758 .flags = X86_EFLAGS_IF,
4759 };
4760
4761 do_machine_check(&regs, 0);
4762#endif
4763}
4764
851ba692 4765static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4766{
4767 /* already handled by vcpu_run */
4768 return 1;
4769}
4770
851ba692 4771static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4772{
1155f76a 4773 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4774 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4775 u32 intr_info, ex_no, error_code;
42dbaa5a 4776 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4777 u32 vect_info;
4778 enum emulation_result er;
4779
1155f76a 4780 vect_info = vmx->idt_vectoring_info;
88786475 4781 intr_info = vmx->exit_intr_info;
6aa8b732 4782
a0861c02 4783 if (is_machine_check(intr_info))
851ba692 4784 return handle_machine_check(vcpu);
a0861c02 4785
e4a41889 4786 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4787 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4788
4789 if (is_no_device(intr_info)) {
5fd86fcf 4790 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4791 return 1;
4792 }
4793
7aa81cc0 4794 if (is_invalid_opcode(intr_info)) {
51d8b661 4795 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4796 if (er != EMULATE_DONE)
7ee5d940 4797 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4798 return 1;
4799 }
4800
6aa8b732 4801 error_code = 0;
2e11384c 4802 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4803 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4804
4805 /*
4806 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4807 * MMIO, it is better to report an internal error.
4808 * See the comments in vmx_handle_exit.
4809 */
4810 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4811 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4812 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4813 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4814 vcpu->run->internal.ndata = 2;
4815 vcpu->run->internal.data[0] = vect_info;
4816 vcpu->run->internal.data[1] = intr_info;
4817 return 0;
4818 }
4819
6aa8b732 4820 if (is_page_fault(intr_info)) {
1439442c 4821 /* EPT won't cause page fault directly */
cf3ace79 4822 BUG_ON(enable_ept);
6aa8b732 4823 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4824 trace_kvm_page_fault(cr2, error_code);
4825
3298b75c 4826 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4827 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4828 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4829 }
4830
d0bfb940 4831 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4832
4833 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4834 return handle_rmode_exception(vcpu, ex_no, error_code);
4835
42dbaa5a
JK		 4836 switch (ex_no) {
4837 case DB_VECTOR:
4838 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4839 if (!(vcpu->guest_debug &
4840 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4841 vcpu->arch.dr6 &= ~15;
4842 vcpu->arch.dr6 |= dr6;
fd2a445a
HD		 4843 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4844 skip_emulated_instruction(vcpu);
4845
42dbaa5a
JK		 4846 kvm_queue_exception(vcpu, DB_VECTOR);
4847 return 1;
4848 }
4849 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4850 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4851 /* fall through */
4852 case BP_VECTOR:
c573cd22
JK		 4853 /*
4854 * Update instruction length as we may reinject #BP from
4855 * user space while in guest debugging mode. Reading it for
4856 * #DB as well causes no harm, it is not used in that case.
4857 */
4858 vmx->vcpu.arch.event_exit_inst_len =
4859 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4860 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4861 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4862 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4863 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4864 break;
4865 default:
d0bfb940
JK		 4866 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4867 kvm_run->ex.exception = ex_no;
4868 kvm_run->ex.error_code = error_code;
42dbaa5a 4869 break;
6aa8b732 4870 }
6aa8b732
AK		 4871 return 0;
4872}
4873
851ba692 4874static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4875{
1165f5fe 4876 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4877 return 1;
4878}
4879
851ba692 4880static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4881{
851ba692 4882 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4883 return 0;
4884}
6aa8b732 4885
851ba692 4886static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4887{
bfdaab09 4888 unsigned long exit_qualification;
34c33d16 4889 int size, in, string;
039576c0 4890 unsigned port;
6aa8b732 4891
bfdaab09 4892 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4893 string = (exit_qualification & 16) != 0;
cf8f70bf 4894 in = (exit_qualification & 8) != 0;
e70669ab 4895
cf8f70bf 4896 ++vcpu->stat.io_exits;
e70669ab 4897
cf8f70bf 4898 if (string || in)
51d8b661 4899 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4900
cf8f70bf
GN		 4901 port = exit_qualification >> 16;
4902 size = (exit_qualification & 7) + 1;
e93f36bc 4903 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4904
4905 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4906}
4907
102d8325
IM		 4908static void
4909vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4910{
4911 /*
4912 * Patch in the VMCALL instruction:
4913 */
4914 hypercall[0] = 0x0f;
4915 hypercall[1] = 0x01;
4916 hypercall[2] = 0xc1;
102d8325
IM		 4917}
4918
92fbc7b1
JK		 4919static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4920{
4921 unsigned long always_on = VMXON_CR0_ALWAYSON;
4922
4923 if (nested_vmx_secondary_ctls_high &
4924 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4925 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4926 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4927 return (val & always_on) == always_on;
4928}
4929
0fa06071 4930/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4931static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4932{
eeadf9e7 4933 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4934 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4935 unsigned long orig_val = val;
4936
eeadf9e7
NHE		 4937 /*
4938 * We get here when L2 changed cr0 in a way that did not change
4939 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4940 * but did change L0 shadowed bits. So we first calculate the
4941 * effective cr0 value that L1 would like to write into the
4942 * hardware. It consists of the L2-owned bits from the new
4943 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4944 */
1a0d74e6
JK		 4945 val = (val & ~vmcs12->cr0_guest_host_mask) |
4946 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4947
92fbc7b1 4948 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4949 return 1;
1a0d74e6
JK		 4950
4951 if (kvm_set_cr0(vcpu, val))
4952 return 1;
4953 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4954 return 0;
1a0d74e6
JK		 4955 } else {
4956 if (to_vmx(vcpu)->nested.vmxon &&
4957 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4958 return 1;
eeadf9e7 4959 return kvm_set_cr0(vcpu, val);
1a0d74e6 4960 }
eeadf9e7
NHE		 4961}
4962
4963static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4964{
4965 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4966 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4967 unsigned long orig_val = val;
4968
4969 /* analogously to handle_set_cr0 */
4970 val = (val & ~vmcs12->cr4_guest_host_mask) |
4971 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4972 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4973 return 1;
1a0d74e6 4974 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4975 return 0;
4976 } else
4977 return kvm_set_cr4(vcpu, val);
4978}
4979
4980/* called to set cr0 as approriate for clts instruction exit. */
4981static void handle_clts(struct kvm_vcpu *vcpu)
4982{
4983 if (is_guest_mode(vcpu)) {
4984 /*
4985 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4986 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4987 * just pretend it's off (also in arch.cr0 for fpu_activate).
4988 */
4989 vmcs_writel(CR0_READ_SHADOW,
4990 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4991 vcpu->arch.cr0 &= ~X86_CR0_TS;
4992 } else
4993 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4994}
4995
851ba692 4996static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4997{
229456fc 4998 unsigned long exit_qualification, val;
6aa8b732
AK		 4999 int cr;
5000 int reg;
49a9b07e 5001 int err;
6aa8b732 5002
bfdaab09 5003 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5004 cr = exit_qualification & 15;
5005 reg = (exit_qualification >> 8) & 15;
5006 switch ((exit_qualification >> 4) & 3) {
5007 case 0: /* mov to cr */
229456fc
MT		 5008 val = kvm_register_read(vcpu, reg);
5009 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5010 switch (cr) {
5011 case 0:
eeadf9e7 5012 err = handle_set_cr0(vcpu, val);
db8fcefa 5013 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5014 return 1;
5015 case 3:
2390218b 5016 err = kvm_set_cr3(vcpu, val);
db8fcefa 5017 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5018 return 1;
5019 case 4:
eeadf9e7 5020 err = handle_set_cr4(vcpu, val);
db8fcefa 5021 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5022 return 1;
0a5fff19
GN		 5023 case 8: {
5024 u8 cr8_prev = kvm_get_cr8(vcpu);
5025 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5026 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5027 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5028 if (irqchip_in_kernel(vcpu->kvm))
5029 return 1;
5030 if (cr8_prev <= cr8)
5031 return 1;
851ba692 5032 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5033 return 0;
5034 }
4b8073e4 5035 }
6aa8b732 5036 break;
25c4c276 5037 case 2: /* clts */
eeadf9e7 5038 handle_clts(vcpu);
4d4ec087 5039 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5040 skip_emulated_instruction(vcpu);
6b52d186 5041 vmx_fpu_activate(vcpu);
25c4c276 5042 return 1;
6aa8b732
AK		 5043 case 1: /*mov from cr*/
5044 switch (cr) {
5045 case 3:
9f8fe504
AK		 5046 val = kvm_read_cr3(vcpu);
5047 kvm_register_write(vcpu, reg, val);
5048 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5049 skip_emulated_instruction(vcpu);
5050 return 1;
5051 case 8:
229456fc
MT		 5052 val = kvm_get_cr8(vcpu);
5053 kvm_register_write(vcpu, reg, val);
5054 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5055 skip_emulated_instruction(vcpu);
5056 return 1;
5057 }
5058 break;
5059 case 3: /* lmsw */
a1f83a74 5060 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5061 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5062 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5063
5064 skip_emulated_instruction(vcpu);
5065 return 1;
5066 default:
5067 break;
5068 }
851ba692 5069 vcpu->run->exit_reason = 0;
a737f256 5070 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5071 (int)(exit_qualification >> 4) & 3, cr);
5072 return 0;
5073}
5074
851ba692 5075static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5076{
bfdaab09 5077 unsigned long exit_qualification;
6aa8b732
AK		 5078 int dr, reg;
5079
f2483415 5080 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5081 if (!kvm_require_cpl(vcpu, 0))
5082 return 1;
42dbaa5a
JK		 5083 dr = vmcs_readl(GUEST_DR7);
5084 if (dr & DR7_GD) {
5085 /*
5086 * As the vm-exit takes precedence over the debug trap, we
5087 * need to emulate the latter, either for the host or the
5088 * guest debugging itself.
5089 */
5090 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5091 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5092 vcpu->run->debug.arch.dr7 = dr;
5093 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5094 vmcs_readl(GUEST_CS_BASE) +
5095 vmcs_readl(GUEST_RIP);
851ba692
AK		 5096 vcpu->run->debug.arch.exception = DB_VECTOR;
5097 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5098 return 0;
5099 } else {
5100 vcpu->arch.dr7 &= ~DR7_GD;
5101 vcpu->arch.dr6 |= DR6_BD;
5102 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5103 kvm_queue_exception(vcpu, DB_VECTOR);
5104 return 1;
5105 }
5106 }
5107
81908bf4
PB		 5108 if (vcpu->guest_debug == 0) {
5109 u32 cpu_based_vm_exec_control;
5110
5111 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5112 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5113 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5114
5115 /*
5116 * No more DR vmexits; force a reload of the debug registers
5117 * and reenter on this instruction. The next vmexit will
5118 * retrieve the full state of the debug registers.
5119 */
5120 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5121 return 1;
5122 }
5123
bfdaab09 5124 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5125 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5126 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5127 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5128 unsigned long val;
4c4d563b
JK		 5129
5130 if (kvm_get_dr(vcpu, dr, &val))
5131 return 1;
5132 kvm_register_write(vcpu, reg, val);
020df079 5133 } else
4c4d563b
JK		 5134 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5135 return 1;
5136
6aa8b732
AK		 5137 skip_emulated_instruction(vcpu);
5138 return 1;
5139}
5140
73aaf249
JK		 5141static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5142{
5143 return vcpu->arch.dr6;
5144}
5145
5146static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5147{
5148}
5149
81908bf4
PB		 5150static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5151{
5152 u32 cpu_based_vm_exec_control;
5153
5154 get_debugreg(vcpu->arch.db[0], 0);
5155 get_debugreg(vcpu->arch.db[1], 1);
5156 get_debugreg(vcpu->arch.db[2], 2);
5157 get_debugreg(vcpu->arch.db[3], 3);
5158 get_debugreg(vcpu->arch.dr6, 6);
5159 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5160
5161 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5162
5163 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5164 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5165 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5166}
5167
020df079
GN		 5168static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5169{
5170 vmcs_writel(GUEST_DR7, val);
5171}
5172
851ba692 5173static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5174{
06465c5a
AK		 5175 kvm_emulate_cpuid(vcpu);
5176 return 1;
6aa8b732
AK		 5177}
5178
851ba692 5179static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5180{
ad312c7c 5181 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5182 u64 data;
5183
5184 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5185 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5186 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5187 return 1;
5188 }
5189
229456fc 5190 trace_kvm_msr_read(ecx, data);
2714d1d3 5191
6aa8b732 5192 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5193 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5194 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5195 skip_emulated_instruction(vcpu);
5196 return 1;
5197}
5198
851ba692 5199static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5200{
8fe8ab46 5201 struct msr_data msr;
ad312c7c
ZX		 5202 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5203 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5204 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5205
8fe8ab46
WA		 5206 msr.data = data;
5207 msr.index = ecx;
5208 msr.host_initiated = false;
5209 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5210 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5211 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5212 return 1;
5213 }
5214
59200273 5215 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5216 skip_emulated_instruction(vcpu);
5217 return 1;
5218}
5219
851ba692 5220static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5221{
3842d135 5222 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5223 return 1;
5224}
5225
851ba692 5226static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5227{
85f455f7
ED		 5228 u32 cpu_based_vm_exec_control;
5229
5230 /* clear pending irq */
5231 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5232 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5233 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5234
3842d135
AK		 5235 kvm_make_request(KVM_REQ_EVENT, vcpu);
5236
a26bf12a 5237 ++vcpu->stat.irq_window_exits;
2714d1d3 5238
c1150d8c
DL		 5239 /*
5240 * If the user space waits to inject interrupts, exit as soon as
5241 * possible
5242 */
8061823a 5243 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5244 vcpu->run->request_interrupt_window &&
8061823a 5245 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5246 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5247 return 0;
5248 }
6aa8b732
AK		 5249 return 1;
5250}
5251
851ba692 5252static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5253{
5254 skip_emulated_instruction(vcpu);
d3bef15f 5255 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5256}
5257
851ba692 5258static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5259{
510043da 5260 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5261 kvm_emulate_hypercall(vcpu);
5262 return 1;
c21415e8
IM		 5263}
5264
ec25d5e6
GN		 5265static int handle_invd(struct kvm_vcpu *vcpu)
5266{
51d8b661 5267 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5268}
5269
851ba692 5270static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5271{
f9c617f6 5272 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5273
5274 kvm_mmu_invlpg(vcpu, exit_qualification);
5275 skip_emulated_instruction(vcpu);
5276 return 1;
5277}
5278
fee84b07
AK		 5279static int handle_rdpmc(struct kvm_vcpu *vcpu)
5280{
5281 int err;
5282
5283 err = kvm_rdpmc(vcpu);
5284 kvm_complete_insn_gp(vcpu, err);
5285
5286 return 1;
5287}
5288
851ba692 5289static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5290{
5291 skip_emulated_instruction(vcpu);
f5f48ee1 5292 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5293 return 1;
5294}
5295
2acf923e
DC		 5296static int handle_xsetbv(struct kvm_vcpu *vcpu)
5297{
5298 u64 new_bv = kvm_read_edx_eax(vcpu);
5299 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5300
5301 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5302 skip_emulated_instruction(vcpu);
5303 return 1;
5304}
5305
851ba692 5306static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5307{
58fbbf26
KT		 5308 if (likely(fasteoi)) {
5309 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5310 int access_type, offset;
5311
5312 access_type = exit_qualification & APIC_ACCESS_TYPE;
5313 offset = exit_qualification & APIC_ACCESS_OFFSET;
5314 /*
5315 * Sane guest uses MOV to write EOI, with written value
5316 * not cared. So make a short-circuit here by avoiding
5317 * heavy instruction emulation.
5318 */
5319 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5320 (offset == APIC_EOI)) {
5321 kvm_lapic_set_eoi(vcpu);
5322 skip_emulated_instruction(vcpu);
5323 return 1;
5324 }
5325 }
51d8b661 5326 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5327}
5328
c7c9c56c
YZ		 5329static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5330{
5331 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5332 int vector = exit_qualification & 0xff;
5333
5334 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5335 kvm_apic_set_eoi_accelerated(vcpu, vector);
5336 return 1;
5337}
5338
83d4c286
YZ		 5339static int handle_apic_write(struct kvm_vcpu *vcpu)
5340{
5341 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5342 u32 offset = exit_qualification & 0xfff;
5343
5344 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5345 kvm_apic_write_nodecode(vcpu, offset);
5346 return 1;
5347}
5348
851ba692 5349static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5350{
60637aac 5351 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5352 unsigned long exit_qualification;
e269fb21
JK		 5353 bool has_error_code = false;
5354 u32 error_code = 0;
37817f29 5355 u16 tss_selector;
7f3d35fd 5356 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5357
5358 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5359 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5360 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5361
5362 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5363
5364 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5365 if (reason == TASK_SWITCH_GATE && idt_v) {
5366 switch (type) {
5367 case INTR_TYPE_NMI_INTR:
5368 vcpu->arch.nmi_injected = false;
654f06fc 5369 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5370 break;
5371 case INTR_TYPE_EXT_INTR:
66fd3f7f 5372 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5373 kvm_clear_interrupt_queue(vcpu);
5374 break;
5375 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5376 if (vmx->idt_vectoring_info &
5377 VECTORING_INFO_DELIVER_CODE_MASK) {
5378 has_error_code = true;
5379 error_code =
5380 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5381 }
5382 /* fall through */
64a7ec06
GN		 5383 case INTR_TYPE_SOFT_EXCEPTION:
5384 kvm_clear_exception_queue(vcpu);
5385 break;
5386 default:
5387 break;
5388 }
60637aac 5389 }
37817f29
IE		 5390 tss_selector = exit_qualification;
5391
64a7ec06
GN		 5392 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5393 type != INTR_TYPE_EXT_INTR &&
5394 type != INTR_TYPE_NMI_INTR))
5395 skip_emulated_instruction(vcpu);
5396
7f3d35fd
KW		 5397 if (kvm_task_switch(vcpu, tss_selector,
5398 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5399 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5400 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5401 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5402 vcpu->run->internal.ndata = 0;
42dbaa5a 5403 return 0;
acb54517 5404 }
42dbaa5a
JK		 5405
5406 /* clear all local breakpoint enable flags */
5407 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5408
5409 /*
5410 * TODO: What about debug traps on tss switch?
5411 * Are we supposed to inject them and update dr6?
5412 */
5413
5414 return 1;
37817f29
IE		 5415}
5416
851ba692 5417static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5418{
f9c617f6 5419 unsigned long exit_qualification;
1439442c 5420 gpa_t gpa;
4f5982a5 5421 u32 error_code;
1439442c 5422 int gla_validity;
1439442c 5423
f9c617f6 5424 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5425
1439442c
SY		 5426 gla_validity = (exit_qualification >> 7) & 0x3;
5427 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5428 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5429 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5430 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5431 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5432 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5433 (long unsigned int)exit_qualification);
851ba692
AK		 5434 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5435 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5436 return 0;
1439442c
SY		 5437 }
5438
0be9c7a8
GN		 5439 /*
5440 * EPT violation happened while executing iret from NMI,
5441 * "blocked by NMI" bit has to be set before next VM entry.
5442 * There are errata that may cause this bit to not be set:
5443 * AAK134, BY25.
5444 */
bcd1c294
GN		 5445 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5446 cpu_has_virtual_nmis() &&
5447 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5448 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5449
1439442c 5450 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5451 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5452
5453 /* It is a write fault? */
5454 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5455 /* It is a fetch fault? */
5456 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5457 /* ept page table is present? */
5458 error_code |= (exit_qualification >> 3) & 0x1;
5459
25d92081
YZ		 5460 vcpu->arch.exit_qualification = exit_qualification;
5461
4f5982a5 5462 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5463}
5464
68f89400
MT		 5465static u64 ept_rsvd_mask(u64 spte, int level)
5466{
5467 int i;
5468 u64 mask = 0;
5469
5470 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5471 mask |= (1ULL << i);
5472
5473 if (level > 2)
5474 /* bits 7:3 reserved */
5475 mask |= 0xf8;
5476 else if (level == 2) {
5477 if (spte & (1ULL << 7))
5478 /* 2MB ref, bits 20:12 reserved */
5479 mask |= 0x1ff000;
5480 else
5481 /* bits 6:3 reserved */
5482 mask |= 0x78;
5483 }
5484
5485 return mask;
5486}
5487
5488static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5489 int level)
5490{
5491 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5492
5493 /* 010b (write-only) */
5494 WARN_ON((spte & 0x7) == 0x2);
5495
5496 /* 110b (write/execute) */
5497 WARN_ON((spte & 0x7) == 0x6);
5498
5499 /* 100b (execute-only) and value not supported by logical processor */
5500 if (!cpu_has_vmx_ept_execute_only())
5501 WARN_ON((spte & 0x7) == 0x4);
5502
5503 /* not 000b */
5504 if ((spte & 0x7)) {
5505 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5506
5507 if (rsvd_bits != 0) {
5508 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5509 __func__, rsvd_bits);
5510 WARN_ON(1);
5511 }
5512
5513 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5514 u64 ept_mem_type = (spte & 0x38) >> 3;
5515
5516 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5517 ept_mem_type == 7) {
5518 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5519 __func__, ept_mem_type);
5520 WARN_ON(1);
5521 }
5522 }
5523 }
5524}
5525
851ba692 5526static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5527{
5528 u64 sptes[4];
ce88decf 5529 int nr_sptes, i, ret;
68f89400
MT		 5530 gpa_t gpa;
5531
5532 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5533 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5534 skip_emulated_instruction(vcpu);
5535 return 1;
5536 }
68f89400 5537
ce88decf 5538 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5539 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5540 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5541 EMULATE_DONE;
f8f55942
XG		 5542
5543 if (unlikely(ret == RET_MMIO_PF_INVALID))
5544 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5545
b37fbea6 5546 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5547 return 1;
5548
5549 /* It is the real ept misconfig */
68f89400
MT		 5550 printk(KERN_ERR "EPT: Misconfiguration.\n");
5551 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5552
5553 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5554
5555 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5556 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5557
851ba692
AK		 5558 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5559 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5560
5561 return 0;
5562}
5563
851ba692 5564static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5565{
5566 u32 cpu_based_vm_exec_control;
5567
5568 /* clear pending NMI */
5569 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5570 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5571 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5572 ++vcpu->stat.nmi_window_exits;
3842d135 5573 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5574
5575 return 1;
5576}
5577
80ced186 5578static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5579{
8b3079a5
AK		 5580 struct vcpu_vmx *vmx = to_vmx(vcpu);
5581 enum emulation_result err = EMULATE_DONE;
80ced186 5582 int ret = 1;
49e9d557
AK		 5583 u32 cpu_exec_ctrl;
5584 bool intr_window_requested;
b8405c18 5585 unsigned count = 130;
49e9d557
AK		 5586
5587 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5588 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5589
b8405c18 5590 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5591 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5592 return handle_interrupt_window(&vmx->vcpu);
5593
de87dcdd
AK		 5594 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5595 return 1;
5596
991eebf9 5597 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5598
ac0a48c3 5599 if (err == EMULATE_USER_EXIT) {
94452b9e 5600 ++vcpu->stat.mmio_exits;
80ced186
MG		 5601 ret = 0;
5602 goto out;
5603 }
1d5a4d9b 5604
de5f70e0
AK		 5605 if (err != EMULATE_DONE) {
5606 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5607 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5608 vcpu->run->internal.ndata = 0;
6d77dbfc 5609 return 0;
de5f70e0 5610 }
ea953ef0 5611
8d76c49e
GN		 5612 if (vcpu->arch.halt_request) {
5613 vcpu->arch.halt_request = 0;
5614 ret = kvm_emulate_halt(vcpu);
5615 goto out;
5616 }
5617
ea953ef0 5618 if (signal_pending(current))
80ced186 5619 goto out;
ea953ef0
MG		 5620 if (need_resched())
5621 schedule();
5622 }
5623
14168786 5624 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5625out:
5626 return ret;
ea953ef0
MG		 5627}
5628
4b8d54f9
ZE		 5629/*
5630 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5631 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5632 */
9fb41ba8 5633static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5634{
5635 skip_emulated_instruction(vcpu);
5636 kvm_vcpu_on_spin(vcpu);
5637
5638 return 1;
5639}
5640
59708670
SY		 5641static int handle_invalid_op(struct kvm_vcpu *vcpu)
5642{
5643 kvm_queue_exception(vcpu, UD_VECTOR);
5644 return 1;
5645}
5646
ff2f6fe9
NHE		 5647/*
5648 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5649 * We could reuse a single VMCS for all the L2 guests, but we also want the
5650 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5651 * allows keeping them loaded on the processor, and in the future will allow
5652 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5653 * every entry if they never change.
5654 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5655 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5656 *
5657 * The following functions allocate and free a vmcs02 in this pool.
5658 */
5659
5660/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5661static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5662{
5663 struct vmcs02_list *item;
5664 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5665 if (item->vmptr == vmx->nested.current_vmptr) {
5666 list_move(&item->list, &vmx->nested.vmcs02_pool);
5667 return &item->vmcs02;
5668 }
5669
5670 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5671 /* Recycle the least recently used VMCS. */
5672 item = list_entry(vmx->nested.vmcs02_pool.prev,
5673 struct vmcs02_list, list);
5674 item->vmptr = vmx->nested.current_vmptr;
5675 list_move(&item->list, &vmx->nested.vmcs02_pool);
5676 return &item->vmcs02;
5677 }
5678
5679 /* Create a new VMCS */
0fa24ce3 5680 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5681 if (!item)
5682 return NULL;
5683 item->vmcs02.vmcs = alloc_vmcs();
5684 if (!item->vmcs02.vmcs) {
5685 kfree(item);
5686 return NULL;
5687 }
5688 loaded_vmcs_init(&item->vmcs02);
5689 item->vmptr = vmx->nested.current_vmptr;
5690 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5691 vmx->nested.vmcs02_num++;
5692 return &item->vmcs02;
5693}
5694
5695/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5696static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5697{
5698 struct vmcs02_list *item;
5699 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5700 if (item->vmptr == vmptr) {
5701 free_loaded_vmcs(&item->vmcs02);
5702 list_del(&item->list);
5703 kfree(item);
5704 vmx->nested.vmcs02_num--;
5705 return;
5706 }
5707}
5708
5709/*
5710 * Free all VMCSs saved for this vcpu, except the one pointed by
5711 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5712 * currently used, if running L2), and vmcs01 when running L2.
5713 */
5714static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5715{
5716 struct vmcs02_list *item, *n;
5717 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5718 if (vmx->loaded_vmcs != &item->vmcs02)
5719 free_loaded_vmcs(&item->vmcs02);
5720 list_del(&item->list);
5721 kfree(item);
5722 }
5723 vmx->nested.vmcs02_num = 0;
5724
5725 if (vmx->loaded_vmcs != &vmx->vmcs01)
5726 free_loaded_vmcs(&vmx->vmcs01);
5727}
5728
0658fbaa
ACL		 5729/*
5730 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5731 * set the success or error code of an emulated VMX instruction, as specified
5732 * by Vol 2B, VMX Instruction Reference, "Conventions".
5733 */
5734static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5735{
5736 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5737 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5738 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5739}
5740
5741static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5742{
5743 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5744 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5745 X86_EFLAGS_SF | X86_EFLAGS_OF))
5746 | X86_EFLAGS_CF);
5747}
5748
145c28dd 5749static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5750 u32 vm_instruction_error)
5751{
5752 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5753 /*
5754 * failValid writes the error number to the current VMCS, which
5755 * can't be done there isn't a current VMCS.
5756 */
5757 nested_vmx_failInvalid(vcpu);
5758 return;
5759 }
5760 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5761 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5762 X86_EFLAGS_SF | X86_EFLAGS_OF))
5763 | X86_EFLAGS_ZF);
5764 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5765 /*
5766 * We don't need to force a shadow sync because
5767 * VM_INSTRUCTION_ERROR is not shadowed
5768 */
5769}
145c28dd 5770
f4124500
JK		 5771static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5772{
5773 struct vcpu_vmx *vmx =
5774 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5775
5776 vmx->nested.preemption_timer_expired = true;
5777 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5778 kvm_vcpu_kick(&vmx->vcpu);
5779
5780 return HRTIMER_NORESTART;
5781}
5782
ec378aee
NHE		 5783/*
5784 * Emulate the VMXON instruction.
5785 * Currently, we just remember that VMX is active, and do not save or even
5786 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5787 * do not currently need to store anything in that guest-allocated memory
5788 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5789 * argument is different from the VMXON pointer (which the spec says they do).
5790 */
5791static int handle_vmon(struct kvm_vcpu *vcpu)
5792{
5793 struct kvm_segment cs;
5794 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5795 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5796 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5797 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5798
5799 /* The Intel VMX Instruction Reference lists a bunch of bits that
5800 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5801 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5802 * Otherwise, we should fail with #UD. We test these now:
5803 */
5804 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5805 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5806 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5807 kvm_queue_exception(vcpu, UD_VECTOR);
5808 return 1;
5809 }
5810
5811 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5812 if (is_long_mode(vcpu) && !cs.l) {
5813 kvm_queue_exception(vcpu, UD_VECTOR);
5814 return 1;
5815 }
5816
5817 if (vmx_get_cpl(vcpu)) {
5818 kvm_inject_gp(vcpu, 0);
5819 return 1;
5820 }
145c28dd
AG		 5821 if (vmx->nested.vmxon) {
5822 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5823 skip_emulated_instruction(vcpu);
5824 return 1;
5825 }
b3897a49
NHE		 5826
5827 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5828 != VMXON_NEEDED_FEATURES) {
5829 kvm_inject_gp(vcpu, 0);
5830 return 1;
5831 }
5832
8de48833
AG		 5833 if (enable_shadow_vmcs) {
5834 shadow_vmcs = alloc_vmcs();
5835 if (!shadow_vmcs)
5836 return -ENOMEM;
5837 /* mark vmcs as shadow */
5838 shadow_vmcs->revision_id |= (1u << 31);
5839 /* init shadow vmcs */
5840 vmcs_clear(shadow_vmcs);
5841 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5842 }
ec378aee 5843
ff2f6fe9
NHE		 5844 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5845 vmx->nested.vmcs02_num = 0;
5846
f4124500
JK		 5847 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5848 HRTIMER_MODE_REL);
5849 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5850
ec378aee
NHE		 5851 vmx->nested.vmxon = true;
5852
5853 skip_emulated_instruction(vcpu);
a25eb114 5854 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5855 return 1;
5856}
5857
5858/*
5859 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5860 * for running VMX instructions (except VMXON, whose prerequisites are
5861 * slightly different). It also specifies what exception to inject otherwise.
5862 */
5863static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5864{
5865 struct kvm_segment cs;
5866 struct vcpu_vmx *vmx = to_vmx(vcpu);
5867
5868 if (!vmx->nested.vmxon) {
5869 kvm_queue_exception(vcpu, UD_VECTOR);
5870 return 0;
5871 }
5872
5873 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5874 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5875 (is_long_mode(vcpu) && !cs.l)) {
5876 kvm_queue_exception(vcpu, UD_VECTOR);
5877 return 0;
5878 }
5879
5880 if (vmx_get_cpl(vcpu)) {
5881 kvm_inject_gp(vcpu, 0);
5882 return 0;
5883 }
5884
5885 return 1;
5886}
5887
e7953d7f
AG		 5888static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5889{
8a1b9dd0 5890 u32 exec_control;
012f83cb
AG		 5891 if (enable_shadow_vmcs) {
5892 if (vmx->nested.current_vmcs12 != NULL) {
5893 /* copy to memory all shadowed fields in case
5894 they were modified */
5895 copy_shadow_to_vmcs12(vmx);
5896 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5897 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5898 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5899 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5900 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5901 }
5902 }
e7953d7f
AG		 5903 kunmap(vmx->nested.current_vmcs12_page);
5904 nested_release_page(vmx->nested.current_vmcs12_page);
5905}
5906
ec378aee
NHE		 5907/*
5908 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5909 * just stops using VMX.
5910 */
5911static void free_nested(struct vcpu_vmx *vmx)
5912{
5913 if (!vmx->nested.vmxon)
5914 return;
5915 vmx->nested.vmxon = false;
a9d30f33 5916 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5917 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5918 vmx->nested.current_vmptr = -1ull;
5919 vmx->nested.current_vmcs12 = NULL;
5920 }
e7953d7f
AG		 5921 if (enable_shadow_vmcs)
5922 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5923 /* Unpin physical memory we referred to in current vmcs02 */
5924 if (vmx->nested.apic_access_page) {
5925 nested_release_page(vmx->nested.apic_access_page);
5926 vmx->nested.apic_access_page = 0;
5927 }
ff2f6fe9
NHE		 5928
5929 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5930}
5931
5932/* Emulate the VMXOFF instruction */
5933static int handle_vmoff(struct kvm_vcpu *vcpu)
5934{
5935 if (!nested_vmx_check_permission(vcpu))
5936 return 1;
5937 free_nested(to_vmx(vcpu));
5938 skip_emulated_instruction(vcpu);
a25eb114 5939 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5940 return 1;
5941}
5942
064aea77
NHE		 5943/*
5944 * Decode the memory-address operand of a vmx instruction, as recorded on an
5945 * exit caused by such an instruction (run by a guest hypervisor).
5946 * On success, returns 0. When the operand is invalid, returns 1 and throws
5947 * #UD or #GP.
5948 */
5949static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5950 unsigned long exit_qualification,
5951 u32 vmx_instruction_info, gva_t *ret)
5952{
5953 /*
5954 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5955 * Execution", on an exit, vmx_instruction_info holds most of the
5956 * addressing components of the operand. Only the displacement part
5957 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5958 * For how an actual address is calculated from all these components,
5959 * refer to Vol. 1, "Operand Addressing".
5960 */
5961 int scaling = vmx_instruction_info & 3;
5962 int addr_size = (vmx_instruction_info >> 7) & 7;
5963 bool is_reg = vmx_instruction_info & (1u << 10);
5964 int seg_reg = (vmx_instruction_info >> 15) & 7;
5965 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5966 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5967 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5968 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5969
5970 if (is_reg) {
5971 kvm_queue_exception(vcpu, UD_VECTOR);
5972 return 1;
5973 }
5974
5975 /* Addr = segment_base + offset */
5976 /* offset = base + [index * scale] + displacement */
5977 *ret = vmx_get_segment_base(vcpu, seg_reg);
5978 if (base_is_valid)
5979 *ret += kvm_register_read(vcpu, base_reg);
5980 if (index_is_valid)
5981 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5982 *ret += exit_qualification; /* holds the displacement */
5983
5984 if (addr_size == 1) /* 32 bit */
5985 *ret &= 0xffffffff;
5986
5987 /*
5988 * TODO: throw #GP (and return 1) in various cases that the VM*
5989 * instructions require it - e.g., offset beyond segment limit,
5990 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5991 * address, and so on. Currently these are not checked.
5992 */
5993 return 0;
5994}
5995
27d6c865
NHE		 5996/* Emulate the VMCLEAR instruction */
5997static int handle_vmclear(struct kvm_vcpu *vcpu)
5998{
5999 struct vcpu_vmx *vmx = to_vmx(vcpu);
6000 gva_t gva;
6001 gpa_t vmptr;
6002 struct vmcs12 *vmcs12;
6003 struct page *page;
6004 struct x86_exception e;
6005
6006 if (!nested_vmx_check_permission(vcpu))
6007 return 1;
6008
6009 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6010 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6011 return 1;
6012
6013 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6014 sizeof(vmptr), &e)) {
6015 kvm_inject_page_fault(vcpu, &e);
6016 return 1;
6017 }
6018
6019 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6020 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6021 skip_emulated_instruction(vcpu);
6022 return 1;
6023 }
6024
6025 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6026 nested_release_vmcs12(vmx);
27d6c865
NHE		 6027 vmx->nested.current_vmptr = -1ull;
6028 vmx->nested.current_vmcs12 = NULL;
6029 }
6030
6031 page = nested_get_page(vcpu, vmptr);
6032 if (page == NULL) {
6033 /*
6034 * For accurate processor emulation, VMCLEAR beyond available
6035 * physical memory should do nothing at all. However, it is
6036 * possible that a nested vmx bug, not a guest hypervisor bug,
6037 * resulted in this case, so let's shut down before doing any
6038 * more damage:
6039 */
6040 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6041 return 1;
6042 }
6043 vmcs12 = kmap(page);
6044 vmcs12->launch_state = 0;
6045 kunmap(page);
6046 nested_release_page(page);
6047
6048 nested_free_vmcs02(vmx, vmptr);
6049
6050 skip_emulated_instruction(vcpu);
6051 nested_vmx_succeed(vcpu);
6052 return 1;
6053}
6054
cd232ad0
NHE		 6055static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6056
6057/* Emulate the VMLAUNCH instruction */
6058static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6059{
6060 return nested_vmx_run(vcpu, true);
6061}
6062
6063/* Emulate the VMRESUME instruction */
6064static int handle_vmresume(struct kvm_vcpu *vcpu)
6065{
6066
6067 return nested_vmx_run(vcpu, false);
6068}
6069
49f705c5
NHE		 6070enum vmcs_field_type {
6071 VMCS_FIELD_TYPE_U16 = 0,
6072 VMCS_FIELD_TYPE_U64 = 1,
6073 VMCS_FIELD_TYPE_U32 = 2,
6074 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6075};
6076
6077static inline int vmcs_field_type(unsigned long field)
6078{
6079 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6080 return VMCS_FIELD_TYPE_U32;
6081 return (field >> 13) & 0x3 ;
6082}
6083
6084static inline int vmcs_field_readonly(unsigned long field)
6085{
6086 return (((field >> 10) & 0x3) == 1);
6087}
6088
6089/*
6090 * Read a vmcs12 field. Since these can have varying lengths and we return
6091 * one type, we chose the biggest type (u64) and zero-extend the return value
6092 * to that size. Note that the caller, handle_vmread, might need to use only
6093 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6094 * 64-bit fields are to be returned).
6095 */
6096static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6097 unsigned long field, u64 *ret)
6098{
6099 short offset = vmcs_field_to_offset(field);
6100 char *p;
6101
6102 if (offset < 0)
6103 return 0;
6104
6105 p = ((char *)(get_vmcs12(vcpu))) + offset;
6106
6107 switch (vmcs_field_type(field)) {
6108 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6109 *ret = *((natural_width *)p);
6110 return 1;
6111 case VMCS_FIELD_TYPE_U16:
6112 *ret = *((u16 *)p);
6113 return 1;
6114 case VMCS_FIELD_TYPE_U32:
6115 *ret = *((u32 *)p);
6116 return 1;
6117 case VMCS_FIELD_TYPE_U64:
6118 *ret = *((u64 *)p);
6119 return 1;
6120 default:
6121 return 0; /* can never happen. */
6122 }
6123}
6124
20b97fea
AG		 6125
6126static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6127 unsigned long field, u64 field_value){
6128 short offset = vmcs_field_to_offset(field);
6129 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6130 if (offset < 0)
6131 return false;
6132
6133 switch (vmcs_field_type(field)) {
6134 case VMCS_FIELD_TYPE_U16:
6135 *(u16 *)p = field_value;
6136 return true;
6137 case VMCS_FIELD_TYPE_U32:
6138 *(u32 *)p = field_value;
6139 return true;
6140 case VMCS_FIELD_TYPE_U64:
6141 *(u64 *)p = field_value;
6142 return true;
6143 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6144 *(natural_width *)p = field_value;
6145 return true;
6146 default:
6147 return false; /* can never happen. */
6148 }
6149
6150}
6151
16f5b903
AG		 6152static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6153{
6154 int i;
6155 unsigned long field;
6156 u64 field_value;
6157 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6158 const unsigned long *fields = shadow_read_write_fields;
6159 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6160
6161 vmcs_load(shadow_vmcs);
6162
6163 for (i = 0; i < num_fields; i++) {
6164 field = fields[i];
6165 switch (vmcs_field_type(field)) {
6166 case VMCS_FIELD_TYPE_U16:
6167 field_value = vmcs_read16(field);
6168 break;
6169 case VMCS_FIELD_TYPE_U32:
6170 field_value = vmcs_read32(field);
6171 break;
6172 case VMCS_FIELD_TYPE_U64:
6173 field_value = vmcs_read64(field);
6174 break;
6175 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6176 field_value = vmcs_readl(field);
6177 break;
6178 }
6179 vmcs12_write_any(&vmx->vcpu, field, field_value);
6180 }
6181
6182 vmcs_clear(shadow_vmcs);
6183 vmcs_load(vmx->loaded_vmcs->vmcs);
6184}
6185
c3114420
AG		 6186static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6187{
c2bae893
MK		 6188 const unsigned long *fields[] = {
6189 shadow_read_write_fields,
6190 shadow_read_only_fields
c3114420 6191 };
c2bae893 6192 const int max_fields[] = {
c3114420
AG		 6193 max_shadow_read_write_fields,
6194 max_shadow_read_only_fields
6195 };
6196 int i, q;
6197 unsigned long field;
6198 u64 field_value = 0;
6199 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6200
6201 vmcs_load(shadow_vmcs);
6202
c2bae893 6203 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6204 for (i = 0; i < max_fields[q]; i++) {
6205 field = fields[q][i];
6206 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6207
6208 switch (vmcs_field_type(field)) {
6209 case VMCS_FIELD_TYPE_U16:
6210 vmcs_write16(field, (u16)field_value);
6211 break;
6212 case VMCS_FIELD_TYPE_U32:
6213 vmcs_write32(field, (u32)field_value);
6214 break;
6215 case VMCS_FIELD_TYPE_U64:
6216 vmcs_write64(field, (u64)field_value);
6217 break;
6218 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6219 vmcs_writel(field, (long)field_value);
6220 break;
6221 }
6222 }
6223 }
6224
6225 vmcs_clear(shadow_vmcs);
6226 vmcs_load(vmx->loaded_vmcs->vmcs);
6227}
6228
49f705c5
NHE		 6229/*
6230 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6231 * used before) all generate the same failure when it is missing.
6232 */
6233static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6234{
6235 struct vcpu_vmx *vmx = to_vmx(vcpu);
6236 if (vmx->nested.current_vmptr == -1ull) {
6237 nested_vmx_failInvalid(vcpu);
6238 skip_emulated_instruction(vcpu);
6239 return 0;
6240 }
6241 return 1;
6242}
6243
6244static int handle_vmread(struct kvm_vcpu *vcpu)
6245{
6246 unsigned long field;
6247 u64 field_value;
6248 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6249 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6250 gva_t gva = 0;
6251
6252 if (!nested_vmx_check_permission(vcpu) ||
6253 !nested_vmx_check_vmcs12(vcpu))
6254 return 1;
6255
6256 /* Decode instruction info and find the field to read */
6257 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6258 /* Read the field, zero-extended to a u64 field_value */
6259 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6260 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6261 skip_emulated_instruction(vcpu);
6262 return 1;
6263 }
6264 /*
6265 * Now copy part of this value to register or memory, as requested.
6266 * Note that the number of bits actually copied is 32 or 64 depending
6267 * on the guest's mode (32 or 64 bit), not on the given field's length.
6268 */
6269 if (vmx_instruction_info & (1u << 10)) {
6270 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6271 field_value);
6272 } else {
6273 if (get_vmx_mem_address(vcpu, exit_qualification,
6274 vmx_instruction_info, &gva))
6275 return 1;
6276 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6277 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6278 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6279 }
6280
6281 nested_vmx_succeed(vcpu);
6282 skip_emulated_instruction(vcpu);
6283 return 1;
6284}
6285
6286
6287static int handle_vmwrite(struct kvm_vcpu *vcpu)
6288{
6289 unsigned long field;
6290 gva_t gva;
6291 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6292 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6293 /* The value to write might be 32 or 64 bits, depending on L1's long
6294 * mode, and eventually we need to write that into a field of several
6295 * possible lengths. The code below first zero-extends the value to 64
6296 * bit (field_value), and then copies only the approriate number of
6297 * bits into the vmcs12 field.
6298 */
6299 u64 field_value = 0;
6300 struct x86_exception e;
6301
6302 if (!nested_vmx_check_permission(vcpu) ||
6303 !nested_vmx_check_vmcs12(vcpu))
6304 return 1;
6305
6306 if (vmx_instruction_info & (1u << 10))
6307 field_value = kvm_register_read(vcpu,
6308 (((vmx_instruction_info) >> 3) & 0xf));
6309 else {
6310 if (get_vmx_mem_address(vcpu, exit_qualification,
6311 vmx_instruction_info, &gva))
6312 return 1;
6313 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6314 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6315 kvm_inject_page_fault(vcpu, &e);
6316 return 1;
6317 }
6318 }
6319
6320
6321 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6322 if (vmcs_field_readonly(field)) {
6323 nested_vmx_failValid(vcpu,
6324 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6325 skip_emulated_instruction(vcpu);
6326 return 1;
6327 }
6328
20b97fea 6329 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6330 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6331 skip_emulated_instruction(vcpu);
6332 return 1;
6333 }
6334
6335 nested_vmx_succeed(vcpu);
6336 skip_emulated_instruction(vcpu);
6337 return 1;
6338}
6339
63846663
NHE		 6340/* Emulate the VMPTRLD instruction */
6341static int handle_vmptrld(struct kvm_vcpu *vcpu)
6342{
6343 struct vcpu_vmx *vmx = to_vmx(vcpu);
6344 gva_t gva;
6345 gpa_t vmptr;
6346 struct x86_exception e;
8a1b9dd0 6347 u32 exec_control;
63846663
NHE		 6348
6349 if (!nested_vmx_check_permission(vcpu))
6350 return 1;
6351
6352 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6353 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6354 return 1;
6355
6356 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6357 sizeof(vmptr), &e)) {
6358 kvm_inject_page_fault(vcpu, &e);
6359 return 1;
6360 }
6361
6362 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6363 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6364 skip_emulated_instruction(vcpu);
6365 return 1;
6366 }
6367
6368 if (vmx->nested.current_vmptr != vmptr) {
6369 struct vmcs12 *new_vmcs12;
6370 struct page *page;
6371 page = nested_get_page(vcpu, vmptr);
6372 if (page == NULL) {
6373 nested_vmx_failInvalid(vcpu);
6374 skip_emulated_instruction(vcpu);
6375 return 1;
6376 }
6377 new_vmcs12 = kmap(page);
6378 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6379 kunmap(page);
6380 nested_release_page_clean(page);
6381 nested_vmx_failValid(vcpu,
6382 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6383 skip_emulated_instruction(vcpu);
6384 return 1;
6385 }
e7953d7f
AG		 6386 if (vmx->nested.current_vmptr != -1ull)
6387 nested_release_vmcs12(vmx);
63846663
NHE		 6388
6389 vmx->nested.current_vmptr = vmptr;
6390 vmx->nested.current_vmcs12 = new_vmcs12;
6391 vmx->nested.current_vmcs12_page = page;
012f83cb 6392 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6393 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6394 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6395 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6396 vmcs_write64(VMCS_LINK_POINTER,
6397 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6398 vmx->nested.sync_shadow_vmcs = true;
6399 }
63846663
NHE		 6400 }
6401
6402 nested_vmx_succeed(vcpu);
6403 skip_emulated_instruction(vcpu);
6404 return 1;
6405}
6406
6a4d7550
NHE		 6407/* Emulate the VMPTRST instruction */
6408static int handle_vmptrst(struct kvm_vcpu *vcpu)
6409{
6410 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6411 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6412 gva_t vmcs_gva;
6413 struct x86_exception e;
6414
6415 if (!nested_vmx_check_permission(vcpu))
6416 return 1;
6417
6418 if (get_vmx_mem_address(vcpu, exit_qualification,
6419 vmx_instruction_info, &vmcs_gva))
6420 return 1;
6421 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6422 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6423 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6424 sizeof(u64), &e)) {
6425 kvm_inject_page_fault(vcpu, &e);
6426 return 1;
6427 }
6428 nested_vmx_succeed(vcpu);
6429 skip_emulated_instruction(vcpu);
6430 return 1;
6431}
6432
bfd0a56b
NHE		 6433/* Emulate the INVEPT instruction */
6434static int handle_invept(struct kvm_vcpu *vcpu)
6435{
6436 u32 vmx_instruction_info, types;
6437 unsigned long type;
6438 gva_t gva;
6439 struct x86_exception e;
6440 struct {
6441 u64 eptp, gpa;
6442 } operand;
bfd0a56b
NHE		 6443
6444 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6445 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6446 kvm_queue_exception(vcpu, UD_VECTOR);
6447 return 1;
6448 }
6449
6450 if (!nested_vmx_check_permission(vcpu))
6451 return 1;
6452
6453 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6454 kvm_queue_exception(vcpu, UD_VECTOR);
6455 return 1;
6456 }
6457
6458 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6459 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6460
6461 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6462
6463 if (!(types & (1UL << type))) {
6464 nested_vmx_failValid(vcpu,
6465 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6466 return 1;
6467 }
6468
6469 /* According to the Intel VMX instruction reference, the memory
6470 * operand is read even if it isn't needed (e.g., for type==global)
6471 */
6472 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6473 vmx_instruction_info, &gva))
6474 return 1;
6475 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6476 sizeof(operand), &e)) {
6477 kvm_inject_page_fault(vcpu, &e);
6478 return 1;
6479 }
6480
6481 switch (type) {
bfd0a56b
NHE		 6482 case VMX_EPT_EXTENT_GLOBAL:
6483 kvm_mmu_sync_roots(vcpu);
6484 kvm_mmu_flush_tlb(vcpu);
6485 nested_vmx_succeed(vcpu);
6486 break;
6487 default:
4b855078 6488 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6489 BUG_ON(1);
6490 break;
6491 }
6492
6493 skip_emulated_instruction(vcpu);
6494 return 1;
6495}
6496
6aa8b732
AK		 6497/*
6498 * The exit handlers return 1 if the exit was handled fully and guest execution
6499 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6500 * to be done to userspace and return 0.
6501 */
772e0318 6502static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6503 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6504 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6505 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6506 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6507 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6508 [EXIT_REASON_CR_ACCESS] = handle_cr,
6509 [EXIT_REASON_DR_ACCESS] = handle_dr,
6510 [EXIT_REASON_CPUID] = handle_cpuid,
6511 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6512 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6513 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6514 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6515 [EXIT_REASON_INVD] = handle_invd,
a7052897 6516 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6517 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6518 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6519 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6520 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6521 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6522 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6523 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6524 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6525 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6526 [EXIT_REASON_VMOFF] = handle_vmoff,
6527 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6528 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6529 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6530 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6531 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6532 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6533 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6534 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6535 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6536 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6537 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6538 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6539 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6540 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6541 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6542};
6543
6544static const int kvm_vmx_max_exit_handlers =
50a3485c 6545 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6546
908a7bdd
JK		 6547static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6548 struct vmcs12 *vmcs12)
6549{
6550 unsigned long exit_qualification;
6551 gpa_t bitmap, last_bitmap;
6552 unsigned int port;
6553 int size;
6554 u8 b;
6555
908a7bdd 6556 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6557 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6558
6559 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6560
6561 port = exit_qualification >> 16;
6562 size = (exit_qualification & 7) + 1;
6563
6564 last_bitmap = (gpa_t)-1;
6565 b = -1;
6566
6567 while (size > 0) {
6568 if (port < 0x8000)
6569 bitmap = vmcs12->io_bitmap_a;
6570 else if (port < 0x10000)
6571 bitmap = vmcs12->io_bitmap_b;
6572 else
6573 return 1;
6574 bitmap += (port & 0x7fff) / 8;
6575
6576 if (last_bitmap != bitmap)
6577 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6578 return 1;
6579 if (b & (1 << (port & 7)))
6580 return 1;
6581
6582 port++;
6583 size--;
6584 last_bitmap = bitmap;
6585 }
6586
6587 return 0;
6588}
6589
644d711a
NHE		 6590/*
6591 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6592 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6593 * disinterest in the current event (read or write a specific MSR) by using an
6594 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6595 */
6596static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6597 struct vmcs12 *vmcs12, u32 exit_reason)
6598{
6599 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6600 gpa_t bitmap;
6601
cbd29cb6 6602 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6603 return 1;
6604
6605 /*
6606 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6607 * for the four combinations of read/write and low/high MSR numbers.
6608 * First we need to figure out which of the four to use:
6609 */
6610 bitmap = vmcs12->msr_bitmap;
6611 if (exit_reason == EXIT_REASON_MSR_WRITE)
6612 bitmap += 2048;
6613 if (msr_index >= 0xc0000000) {
6614 msr_index -= 0xc0000000;
6615 bitmap += 1024;
6616 }
6617
6618 /* Then read the msr_index'th bit from this bitmap: */
6619 if (msr_index < 1024*8) {
6620 unsigned char b;
bd31a7f5
JK		 6621 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6622 return 1;
644d711a
NHE		 6623 return 1 & (b >> (msr_index & 7));
6624 } else
6625 return 1; /* let L1 handle the wrong parameter */
6626}
6627
6628/*
6629 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6630 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6631 * intercept (via guest_host_mask etc.) the current event.
6632 */
6633static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6634 struct vmcs12 *vmcs12)
6635{
6636 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6637 int cr = exit_qualification & 15;
6638 int reg = (exit_qualification >> 8) & 15;
6639 unsigned long val = kvm_register_read(vcpu, reg);
6640
6641 switch ((exit_qualification >> 4) & 3) {
6642 case 0: /* mov to cr */
6643 switch (cr) {
6644 case 0:
6645 if (vmcs12->cr0_guest_host_mask &
6646 (val ^ vmcs12->cr0_read_shadow))
6647 return 1;
6648 break;
6649 case 3:
6650 if ((vmcs12->cr3_target_count >= 1 &&
6651 vmcs12->cr3_target_value0 == val) ||
6652 (vmcs12->cr3_target_count >= 2 &&
6653 vmcs12->cr3_target_value1 == val) ||
6654 (vmcs12->cr3_target_count >= 3 &&
6655 vmcs12->cr3_target_value2 == val) ||
6656 (vmcs12->cr3_target_count >= 4 &&
6657 vmcs12->cr3_target_value3 == val))
6658 return 0;
6659 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6660 return 1;
6661 break;
6662 case 4:
6663 if (vmcs12->cr4_guest_host_mask &
6664 (vmcs12->cr4_read_shadow ^ val))
6665 return 1;
6666 break;
6667 case 8:
6668 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6669 return 1;
6670 break;
6671 }
6672 break;
6673 case 2: /* clts */
6674 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6675 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6676 return 1;
6677 break;
6678 case 1: /* mov from cr */
6679 switch (cr) {
6680 case 3:
6681 if (vmcs12->cpu_based_vm_exec_control &
6682 CPU_BASED_CR3_STORE_EXITING)
6683 return 1;
6684 break;
6685 case 8:
6686 if (vmcs12->cpu_based_vm_exec_control &
6687 CPU_BASED_CR8_STORE_EXITING)
6688 return 1;
6689 break;
6690 }
6691 break;
6692 case 3: /* lmsw */
6693 /*
6694 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6695 * cr0. Other attempted changes are ignored, with no exit.
6696 */
6697 if (vmcs12->cr0_guest_host_mask & 0xe &
6698 (val ^ vmcs12->cr0_read_shadow))
6699 return 1;
6700 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6701 !(vmcs12->cr0_read_shadow & 0x1) &&
6702 (val & 0x1))
6703 return 1;
6704 break;
6705 }
6706 return 0;
6707}
6708
6709/*
6710 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6711 * should handle it ourselves in L0 (and then continue L2). Only call this
6712 * when in is_guest_mode (L2).
6713 */
6714static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6715{
644d711a
NHE		 6716 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6717 struct vcpu_vmx *vmx = to_vmx(vcpu);
6718 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6719 u32 exit_reason = vmx->exit_reason;
644d711a 6720
542060ea
JK		 6721 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6722 vmcs_readl(EXIT_QUALIFICATION),
6723 vmx->idt_vectoring_info,
6724 intr_info,
6725 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6726 KVM_ISA_VMX);
6727
644d711a
NHE		 6728 if (vmx->nested.nested_run_pending)
6729 return 0;
6730
6731 if (unlikely(vmx->fail)) {
bd80158a
JK		 6732 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6733 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6734 return 1;
6735 }
6736
6737 switch (exit_reason) {
6738 case EXIT_REASON_EXCEPTION_NMI:
6739 if (!is_exception(intr_info))
6740 return 0;
6741 else if (is_page_fault(intr_info))
6742 return enable_ept;
e504c909 6743 else if (is_no_device(intr_info) &&
ccf9844e 6744 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6745 return 0;
644d711a
NHE		 6746 return vmcs12->exception_bitmap &
6747 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6748 case EXIT_REASON_EXTERNAL_INTERRUPT:
6749 return 0;
6750 case EXIT_REASON_TRIPLE_FAULT:
6751 return 1;
6752 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6753 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6754 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6755 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6756 case EXIT_REASON_TASK_SWITCH:
6757 return 1;
6758 case EXIT_REASON_CPUID:
6759 return 1;
6760 case EXIT_REASON_HLT:
6761 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6762 case EXIT_REASON_INVD:
6763 return 1;
6764 case EXIT_REASON_INVLPG:
6765 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6766 case EXIT_REASON_RDPMC:
6767 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6768 case EXIT_REASON_RDTSC:
6769 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6770 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6771 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6772 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6773 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6774 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6775 case EXIT_REASON_INVEPT:
644d711a
NHE		 6776 /*
6777 * VMX instructions trap unconditionally. This allows L1 to
6778 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6779 */
6780 return 1;
6781 case EXIT_REASON_CR_ACCESS:
6782 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6783 case EXIT_REASON_DR_ACCESS:
6784 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6785 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6786 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6787 case EXIT_REASON_MSR_READ:
6788 case EXIT_REASON_MSR_WRITE:
6789 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6790 case EXIT_REASON_INVALID_STATE:
6791 return 1;
6792 case EXIT_REASON_MWAIT_INSTRUCTION:
6793 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6794 case EXIT_REASON_MONITOR_INSTRUCTION:
6795 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6796 case EXIT_REASON_PAUSE_INSTRUCTION:
6797 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6798 nested_cpu_has2(vmcs12,
6799 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6800 case EXIT_REASON_MCE_DURING_VMENTRY:
6801 return 0;
6802 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6803 return 1;
6804 case EXIT_REASON_APIC_ACCESS:
6805 return nested_cpu_has2(vmcs12,
6806 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6807 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6808 /*
6809 * L0 always deals with the EPT violation. If nested EPT is
6810 * used, and the nested mmu code discovers that the address is
6811 * missing in the guest EPT table (EPT12), the EPT violation
6812 * will be injected with nested_ept_inject_page_fault()
6813 */
6814 return 0;
644d711a 6815 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6816 /*
6817 * L2 never uses directly L1's EPT, but rather L0's own EPT
6818 * table (shadow on EPT) or a merged EPT table that L0 built
6819 * (EPT on EPT). So any problems with the structure of the
6820 * table is L0's fault.
6821 */
644d711a
NHE		 6822 return 0;
6823 case EXIT_REASON_WBINVD:
6824 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6825 case EXIT_REASON_XSETBV:
6826 return 1;
6827 default:
6828 return 1;
6829 }
6830}
6831
586f9607
AK		 6832static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6833{
6834 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6835 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6836}
6837
6aa8b732
AK		 6838/*
6839 * The guest has exited. See if we can fix it or if we need userspace
6840 * assistance.
6841 */
851ba692 6842static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6843{
29bd8a78 6844 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6845 u32 exit_reason = vmx->exit_reason;
1155f76a 6846 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6847
80ced186 6848 /* If guest state is invalid, start emulating */
14168786 6849 if (vmx->emulation_required)
80ced186 6850 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6851
644d711a 6852 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6853 nested_vmx_vmexit(vcpu, exit_reason,
6854 vmcs_read32(VM_EXIT_INTR_INFO),
6855 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6856 return 1;
6857 }
6858
5120702e
MG		 6859 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6860 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6861 vcpu->run->fail_entry.hardware_entry_failure_reason
6862 = exit_reason;
6863 return 0;
6864 }
6865
29bd8a78 6866 if (unlikely(vmx->fail)) {
851ba692
AK		 6867 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6868 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6869 = vmcs_read32(VM_INSTRUCTION_ERROR);
6870 return 0;
6871 }
6aa8b732 6872
b9bf6882
XG		 6873 /*
6874 * Note:
6875 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6876 * delivery event since it indicates guest is accessing MMIO.
6877 * The vm-exit can be triggered again after return to guest that
6878 * will cause infinite loop.
6879 */
d77c26fc 6880 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6881 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6882 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6883 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6884 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6885 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6886 vcpu->run->internal.ndata = 2;
6887 vcpu->run->internal.data[0] = vectoring_info;
6888 vcpu->run->internal.data[1] = exit_reason;
6889 return 0;
6890 }
3b86cd99 6891
644d711a
NHE		 6892 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6893 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6894 get_vmcs12(vcpu))))) {
c4282df9 6895 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6896 vmx->soft_vnmi_blocked = 0;
3b86cd99 6897 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6898 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6899 /*
6900 * This CPU don't support us in finding the end of an
6901 * NMI-blocked window if the guest runs with IRQs
6902 * disabled. So we pull the trigger after 1 s of
6903 * futile waiting, but inform the user about this.
6904 */
6905 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6906 "state on VCPU %d after 1 s timeout\n",
6907 __func__, vcpu->vcpu_id);
6908 vmx->soft_vnmi_blocked = 0;
3b86cd99 6909 }
3b86cd99
JK		 6910 }
6911
6aa8b732
AK		 6912 if (exit_reason < kvm_vmx_max_exit_handlers
6913 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6914 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6915 else {
851ba692
AK		 6916 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6917 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6918 }
6919 return 0;
6920}
6921
95ba8273 6922static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6923{
95ba8273 6924 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6925 vmcs_write32(TPR_THRESHOLD, 0);
6926 return;
6927 }
6928
95ba8273 6929 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6930}
6931
8d14695f
YZ		 6932static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6933{
6934 u32 sec_exec_control;
6935
6936 /*
6937 * There is not point to enable virtualize x2apic without enable
6938 * apicv
6939 */
c7c9c56c
YZ		 6940 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6941 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6942 return;
6943
6944 if (!vm_need_tpr_shadow(vcpu->kvm))
6945 return;
6946
6947 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6948
6949 if (set) {
6950 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6951 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6952 } else {
6953 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6954 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6955 }
6956 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6957
6958 vmx_set_msr_bitmap(vcpu);
6959}
6960
c7c9c56c
YZ		 6961static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6962{
6963 u16 status;
6964 u8 old;
6965
6966 if (!vmx_vm_has_apicv(kvm))
6967 return;
6968
6969 if (isr == -1)
6970 isr = 0;
6971
6972 status = vmcs_read16(GUEST_INTR_STATUS);
6973 old = status >> 8;
6974 if (isr != old) {
6975 status &= 0xff;
6976 status |= isr << 8;
6977 vmcs_write16(GUEST_INTR_STATUS, status);
6978 }
6979}
6980
6981static void vmx_set_rvi(int vector)
6982{
6983 u16 status;
6984 u8 old;
6985
6986 status = vmcs_read16(GUEST_INTR_STATUS);
6987 old = (u8)status & 0xff;
6988 if ((u8)vector != old) {
6989 status &= ~0xff;
6990 status |= (u8)vector;
6991 vmcs_write16(GUEST_INTR_STATUS, status);
6992 }
6993}
6994
6995static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6996{
6997 if (max_irr == -1)
6998 return;
6999
7000 vmx_set_rvi(max_irr);
7001}
7002
7003static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7004{
3d81bc7e
YZ		 7005 if (!vmx_vm_has_apicv(vcpu->kvm))
7006 return;
7007
c7c9c56c
YZ		 7008 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7009 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7010 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7011 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7012}
7013
51aa01d1 7014static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7015{
00eba012
AK		 7016 u32 exit_intr_info;
7017
7018 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7019 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7020 return;
7021
c5ca8e57 7022 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7023 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7024
7025 /* Handle machine checks before interrupts are enabled */
00eba012 7026 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7027 kvm_machine_check();
7028
20f65983 7029 /* We need to handle NMIs before interrupts are enabled */
00eba012 7030 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7031 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7032 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7033 asm("int $2");
ff9d07a0
ZY		 7034 kvm_after_handle_nmi(&vmx->vcpu);
7035 }
51aa01d1 7036}
20f65983 7037
a547c6db
YZ		 7038static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7039{
7040 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7041
7042 /*
7043 * If external interrupt exists, IF bit is set in rflags/eflags on the
7044 * interrupt stack frame, and interrupt will be enabled on a return
7045 * from interrupt handler.
7046 */
7047 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7048 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7049 unsigned int vector;
7050 unsigned long entry;
7051 gate_desc *desc;
7052 struct vcpu_vmx *vmx = to_vmx(vcpu);
7053#ifdef CONFIG_X86_64
7054 unsigned long tmp;
7055#endif
7056
7057 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7058 desc = (gate_desc *)vmx->host_idt_base + vector;
7059 entry = gate_offset(*desc);
7060 asm volatile(
7061#ifdef CONFIG_X86_64
7062 "mov %%" _ASM_SP ", %[sp]\n\t"
7063 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7064 "push $%c[ss]\n\t"
7065 "push %[sp]\n\t"
7066#endif
7067 "pushf\n\t"
7068 "orl $0x200, (%%" _ASM_SP ")\n\t"
7069 __ASM_SIZE(push) " $%c[cs]\n\t"
7070 "call *%[entry]\n\t"
7071 :
7072#ifdef CONFIG_X86_64
7073 [sp]"=&r"(tmp)
7074#endif
7075 :
7076 [entry]"r"(entry),
7077 [ss]"i"(__KERNEL_DS),
7078 [cs]"i"(__KERNEL_CS)
7079 );
7080 } else
7081 local_irq_enable();
7082}
7083
da8999d3
LJ		 7084static bool vmx_mpx_supported(void)
7085{
7086 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7087 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7088}
7089
51aa01d1
AK		 7090static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7091{
c5ca8e57 7092 u32 exit_intr_info;
51aa01d1
AK		 7093 bool unblock_nmi;
7094 u8 vector;
7095 bool idtv_info_valid;
7096
7097 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7098
cf393f75 7099 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7100 if (vmx->nmi_known_unmasked)
7101 return;
c5ca8e57
AK		 7102 /*
7103 * Can't use vmx->exit_intr_info since we're not sure what
7104 * the exit reason is.
7105 */
7106 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7107 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7108 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7109 /*
7b4a25cb 7110 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7111 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7112 * a guest IRET fault.
7b4a25cb
GN		 7113 * SDM 3: 23.2.2 (September 2008)
7114 * Bit 12 is undefined in any of the following cases:
7115 * If the VM exit sets the valid bit in the IDT-vectoring
7116 * information field.
7117 * If the VM exit is due to a double fault.
cf393f75 7118 */
7b4a25cb
GN		 7119 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7120 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7121 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7122 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7123 else
7124 vmx->nmi_known_unmasked =
7125 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7126 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7127 } else if (unlikely(vmx->soft_vnmi_blocked))
7128 vmx->vnmi_blocked_time +=
7129 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7130}
7131
3ab66e8a 7132static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7133 u32 idt_vectoring_info,
7134 int instr_len_field,
7135 int error_code_field)
51aa01d1 7136{
51aa01d1
AK		 7137 u8 vector;
7138 int type;
7139 bool idtv_info_valid;
7140
7141 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7142
3ab66e8a
JK		 7143 vcpu->arch.nmi_injected = false;
7144 kvm_clear_exception_queue(vcpu);
7145 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7146
7147 if (!idtv_info_valid)
7148 return;
7149
3ab66e8a 7150 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7151
668f612f
AK		 7152 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7153 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7154
64a7ec06 7155 switch (type) {
37b96e98 7156 case INTR_TYPE_NMI_INTR:
3ab66e8a 7157 vcpu->arch.nmi_injected = true;
668f612f 7158 /*
7b4a25cb 7159 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7160 * Clear bit "block by NMI" before VM entry if a NMI
7161 * delivery faulted.
668f612f 7162 */
3ab66e8a 7163 vmx_set_nmi_mask(vcpu, false);
37b96e98 7164 break;
37b96e98 7165 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7166 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7167 /* fall through */
7168 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7169 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7170 u32 err = vmcs_read32(error_code_field);
851eb667 7171 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7172 } else
851eb667 7173 kvm_requeue_exception(vcpu, vector);
37b96e98 7174 break;
66fd3f7f 7175 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7176 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7177 /* fall through */
37b96e98 7178 case INTR_TYPE_EXT_INTR:
3ab66e8a 7179 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7180 break;
7181 default:
7182 break;
f7d9238f 7183 }
cf393f75
AK		 7184}
7185
83422e17
AK		 7186static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7187{
3ab66e8a 7188 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7189 VM_EXIT_INSTRUCTION_LEN,
7190 IDT_VECTORING_ERROR_CODE);
7191}
7192
b463a6f7
AK		 7193static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7194{
3ab66e8a 7195 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7196 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7197 VM_ENTRY_INSTRUCTION_LEN,
7198 VM_ENTRY_EXCEPTION_ERROR_CODE);
7199
7200 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7201}
7202
d7cd9796
GN		 7203static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7204{
7205 int i, nr_msrs;
7206 struct perf_guest_switch_msr *msrs;
7207
7208 msrs = perf_guest_get_msrs(&nr_msrs);
7209
7210 if (!msrs)
7211 return;
7212
7213 for (i = 0; i < nr_msrs; i++)
7214 if (msrs[i].host == msrs[i].guest)
7215 clear_atomic_switch_msr(vmx, msrs[i].msr);
7216 else
7217 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7218 msrs[i].host);
7219}
7220
a3b5ba49 7221static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7222{
a2fa3e9f 7223 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7224 unsigned long debugctlmsr;
104f226b
AK		 7225
7226 /* Record the guest's net vcpu time for enforced NMI injections. */
7227 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7228 vmx->entry_time = ktime_get();
7229
7230 /* Don't enter VMX if guest state is invalid, let the exit handler
7231 start emulation until we arrive back to a valid state */
14168786 7232 if (vmx->emulation_required)
104f226b
AK		 7233 return;
7234
012f83cb
AG		 7235 if (vmx->nested.sync_shadow_vmcs) {
7236 copy_vmcs12_to_shadow(vmx);
7237 vmx->nested.sync_shadow_vmcs = false;
7238 }
7239
104f226b
AK		 7240 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7241 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7242 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7243 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7244
7245 /* When single-stepping over STI and MOV SS, we must clear the
7246 * corresponding interruptibility bits in the guest state. Otherwise
7247 * vmentry fails as it then expects bit 14 (BS) in pending debug
7248 * exceptions being set, but that's not correct for the guest debugging
7249 * case. */
7250 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7251 vmx_set_interrupt_shadow(vcpu, 0);
7252
d7cd9796 7253 atomic_switch_perf_msrs(vmx);
2a7921b7 7254 debugctlmsr = get_debugctlmsr();
d7cd9796 7255
d462b819 7256 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7257 asm(
6aa8b732 7258 /* Store host registers */
b188c81f
AK		 7259 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7260 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7261 "push %%" _ASM_CX " \n\t"
7262 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7263 "je 1f \n\t"
b188c81f 7264 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7265 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7266 "1: \n\t"
d3edefc0 7267 /* Reload cr2 if changed */
b188c81f
AK		 7268 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7269 "mov %%cr2, %%" _ASM_DX " \n\t"
7270 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7271 "je 2f \n\t"
b188c81f 7272 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7273 "2: \n\t"
6aa8b732 7274 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7275 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7276 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7277 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7278 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7279 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7280 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7281 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7282 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7283#ifdef CONFIG_X86_64
e08aa78a
AK		 7284 "mov %c[r8](%0), %%r8 \n\t"
7285 "mov %c[r9](%0), %%r9 \n\t"
7286 "mov %c[r10](%0), %%r10 \n\t"
7287 "mov %c[r11](%0), %%r11 \n\t"
7288 "mov %c[r12](%0), %%r12 \n\t"
7289 "mov %c[r13](%0), %%r13 \n\t"
7290 "mov %c[r14](%0), %%r14 \n\t"
7291 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7292#endif
b188c81f 7293 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7294
6aa8b732 7295 /* Enter guest mode */
83287ea4 7296 "jne 1f \n\t"
4ecac3fd 7297 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7298 "jmp 2f \n\t"
7299 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7300 "2: "
6aa8b732 7301 /* Save guest registers, load host registers, keep flags */
b188c81f 7302 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7303 "pop %0 \n\t"
b188c81f
AK		 7304 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7305 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7306 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7307 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7308 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7309 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7310 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7311#ifdef CONFIG_X86_64
e08aa78a
AK		 7312 "mov %%r8, %c[r8](%0) \n\t"
7313 "mov %%r9, %c[r9](%0) \n\t"
7314 "mov %%r10, %c[r10](%0) \n\t"
7315 "mov %%r11, %c[r11](%0) \n\t"
7316 "mov %%r12, %c[r12](%0) \n\t"
7317 "mov %%r13, %c[r13](%0) \n\t"
7318 "mov %%r14, %c[r14](%0) \n\t"
7319 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7320#endif
b188c81f
AK		 7321 "mov %%cr2, %%" _ASM_AX " \n\t"
7322 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7323
b188c81f 7324 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7325 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7326 ".pushsection .rodata \n\t"
7327 ".global vmx_return \n\t"
7328 "vmx_return: " _ASM_PTR " 2b \n\t"
7329 ".popsection"
e08aa78a 7330 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7331 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7332 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7333 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7334 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7335 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7336 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7337 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7338 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7339 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7340 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7341#ifdef CONFIG_X86_64
ad312c7c
ZX		 7342 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7343 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7344 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7345 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7346 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7347 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7348 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7349 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7350#endif
40712fae
AK		 7351 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7352 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7353 : "cc", "memory"
7354#ifdef CONFIG_X86_64
b188c81f 7355 , "rax", "rbx", "rdi", "rsi"
c2036300 7356 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7357#else
7358 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7359#endif
7360 );
6aa8b732 7361
2a7921b7
GN		 7362 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7363 if (debugctlmsr)
7364 update_debugctlmsr(debugctlmsr);
7365
aa67f609
AK		 7366#ifndef CONFIG_X86_64
7367 /*
7368 * The sysexit path does not restore ds/es, so we must set them to
7369 * a reasonable value ourselves.
7370 *
7371 * We can't defer this to vmx_load_host_state() since that function
7372 * may be executed in interrupt context, which saves and restore segments
7373 * around it, nullifying its effect.
7374 */
7375 loadsegment(ds, __USER_DS);
7376 loadsegment(es, __USER_DS);
7377#endif
7378
6de4f3ad 7379 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7380 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7381 | (1 << VCPU_EXREG_CPL)
aff48baa 7382 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7383 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7384 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7385 vcpu->arch.regs_dirty = 0;
7386
1155f76a
AK		 7387 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7388
d462b819 7389 vmx->loaded_vmcs->launched = 1;
1b6269db 7390
51aa01d1 7391 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7392 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7393
e0b890d3
GN		 7394 /*
7395 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7396 * we did not inject a still-pending event to L1 now because of
7397 * nested_run_pending, we need to re-enable this bit.
7398 */
7399 if (vmx->nested.nested_run_pending)
7400 kvm_make_request(KVM_REQ_EVENT, vcpu);
7401
7402 vmx->nested.nested_run_pending = 0;
7403
51aa01d1
AK		 7404 vmx_complete_atomic_exit(vmx);
7405 vmx_recover_nmi_blocking(vmx);
cf393f75 7406 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7407}
7408
6aa8b732
AK		 7409static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7410{
fb3f0f51
RR		 7411 struct vcpu_vmx *vmx = to_vmx(vcpu);
7412
cdbecfc3 7413 free_vpid(vmx);
d462b819 7414 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7415 free_nested(vmx);
fb3f0f51
RR		 7416 kfree(vmx->guest_msrs);
7417 kvm_vcpu_uninit(vcpu);
a4770347 7418 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7419}
7420
fb3f0f51 7421static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7422{
fb3f0f51 7423 int err;
c16f862d 7424 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7425 int cpu;
6aa8b732 7426
a2fa3e9f 7427 if (!vmx)
fb3f0f51
RR		 7428 return ERR_PTR(-ENOMEM);
7429
2384d2b3
SY		 7430 allocate_vpid(vmx);
7431
fb3f0f51
RR		 7432 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7433 if (err)
7434 goto free_vcpu;
965b58a5 7435
a2fa3e9f 7436 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7437 err = -ENOMEM;
fb3f0f51 7438 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7439 goto uninit_vcpu;
7440 }
965b58a5 7441
d462b819
NHE		 7442 vmx->loaded_vmcs = &vmx->vmcs01;
7443 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7444 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7445 goto free_msrs;
d462b819
NHE		 7446 if (!vmm_exclusive)
7447 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7448 loaded_vmcs_init(vmx->loaded_vmcs);
7449 if (!vmm_exclusive)
7450 kvm_cpu_vmxoff();
a2fa3e9f 7451
15ad7146
AK		 7452 cpu = get_cpu();
7453 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7454 vmx->vcpu.cpu = cpu;
8b9cf98c 7455 err = vmx_vcpu_setup(vmx);
fb3f0f51 7456 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7457 put_cpu();
fb3f0f51
RR		 7458 if (err)
7459 goto free_vmcs;
a63cb560 7460 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7461 err = alloc_apic_access_page(kvm);
7462 if (err)
5e4a0b3c 7463 goto free_vmcs;
a63cb560 7464 }
fb3f0f51 7465
b927a3ce
SY		 7466 if (enable_ept) {
7467 if (!kvm->arch.ept_identity_map_addr)
7468 kvm->arch.ept_identity_map_addr =
7469 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7470 err = -ENOMEM;
b7ebfb05
SY		 7471 if (alloc_identity_pagetable(kvm) != 0)
7472 goto free_vmcs;
93ea5388
GN		 7473 if (!init_rmode_identity_map(kvm))
7474 goto free_vmcs;
b927a3ce 7475 }
b7ebfb05 7476
a9d30f33
NHE		 7477 vmx->nested.current_vmptr = -1ull;
7478 vmx->nested.current_vmcs12 = NULL;
7479
fb3f0f51
RR		 7480 return &vmx->vcpu;
7481
7482free_vmcs:
5f3fbc34 7483 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7484free_msrs:
fb3f0f51
RR		 7485 kfree(vmx->guest_msrs);
7486uninit_vcpu:
7487 kvm_vcpu_uninit(&vmx->vcpu);
7488free_vcpu:
cdbecfc3 7489 free_vpid(vmx);
a4770347 7490 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7491 return ERR_PTR(err);
6aa8b732
AK		 7492}
7493
002c7f7c
YS		 7494static void __init vmx_check_processor_compat(void *rtn)
7495{
7496 struct vmcs_config vmcs_conf;
7497
7498 *(int *)rtn = 0;
7499 if (setup_vmcs_config(&vmcs_conf) < 0)
7500 *(int *)rtn = -EIO;
7501 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7502 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7503 smp_processor_id());
7504 *(int *)rtn = -EIO;
7505 }
7506}
7507
67253af5
SY		 7508static int get_ept_level(void)
7509{
7510 return VMX_EPT_DEFAULT_GAW + 1;
7511}
7512
4b12f0de 7513static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7514{
4b12f0de
SY		 7515 u64 ret;
7516
522c68c4
SY		 7517 /* For VT-d and EPT combination
7518 * 1. MMIO: always map as UC
7519 * 2. EPT with VT-d:
7520 * a. VT-d without snooping control feature: can't guarantee the
7521 * result, try to trust guest.
7522 * b. VT-d with snooping control feature: snooping control feature of
7523 * VT-d engine can guarantee the cache correctness. Just set it
7524 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7525 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7526 * consistent with host MTRR
7527 */
4b12f0de
SY		 7528 if (is_mmio)
7529 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7530 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7531 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7532 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7533 else
522c68c4 7534 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7535 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7536
7537 return ret;
64d4d521
SY		 7538}
7539
17cc3935 7540static int vmx_get_lpage_level(void)
344f414f 7541{
878403b7
SY		 7542 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7543 return PT_DIRECTORY_LEVEL;
7544 else
7545 /* For shadow and EPT supported 1GB page */
7546 return PT_PDPE_LEVEL;
344f414f
JR		 7547}
7548
0e851880
SY		 7549static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7550{
4e47c7a6
SY		 7551 struct kvm_cpuid_entry2 *best;
7552 struct vcpu_vmx *vmx = to_vmx(vcpu);
7553 u32 exec_control;
7554
7555 vmx->rdtscp_enabled = false;
7556 if (vmx_rdtscp_supported()) {
7557 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7558 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7559 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7560 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7561 vmx->rdtscp_enabled = true;
7562 else {
7563 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7564 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7565 exec_control);
7566 }
7567 }
7568 }
ad756a16 7569
ad756a16
MJ		 7570 /* Exposing INVPCID only when PCID is exposed */
7571 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7572 if (vmx_invpcid_supported() &&
4f977045 7573 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7574 guest_cpuid_has_pcid(vcpu)) {
29282fde 7575 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7576 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7577 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7578 exec_control);
7579 } else {
29282fde
TI		 7580 if (cpu_has_secondary_exec_ctrls()) {
7581 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7582 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7583 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7584 exec_control);
7585 }
ad756a16 7586 if (best)
4f977045 7587 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7588 }
0e851880
SY		 7589}
7590
d4330ef2
JR		 7591static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7592{
7b8050f5
NHE		 7593 if (func == 1 && nested)
7594 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7595}
7596
25d92081
YZ		 7597static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7598 struct x86_exception *fault)
7599{
533558bc
JK		 7600 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7601 u32 exit_reason;
25d92081
YZ		 7602
7603 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7604 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7605 else
533558bc
JK		 7606 exit_reason = EXIT_REASON_EPT_VIOLATION;
7607 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7608 vmcs12->guest_physical_address = fault->address;
7609}
7610
155a97a3
NHE		 7611/* Callbacks for nested_ept_init_mmu_context: */
7612
7613static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7614{
7615 /* return the page table to be shadowed - in our case, EPT12 */
7616 return get_vmcs12(vcpu)->ept_pointer;
7617}
7618
8a3c1a33 7619static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7620{
8a3c1a33 7621 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7622 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7623
7624 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7625 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7626 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7627
7628 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7629}
7630
7631static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7632{
7633 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7634}
7635
feaf0c7d
GN		 7636static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7637 struct x86_exception *fault)
7638{
7639 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7640
7641 WARN_ON(!is_guest_mode(vcpu));
7642
7643 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7644 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7645 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7646 vmcs_read32(VM_EXIT_INTR_INFO),
7647 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7648 else
7649 kvm_inject_page_fault(vcpu, fault);
7650}
7651
f4124500
JK		 7652static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7653{
7654 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7655 struct vcpu_vmx *vmx = to_vmx(vcpu);
7656
7657 if (vcpu->arch.virtual_tsc_khz == 0)
7658 return;
7659
7660 /* Make sure short timeouts reliably trigger an immediate vmexit.
7661 * hrtimer_start does not guarantee this. */
7662 if (preemption_timeout <= 1) {
7663 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7664 return;
7665 }
7666
7667 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7668 preemption_timeout *= 1000000;
7669 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7670 hrtimer_start(&vmx->nested.preemption_timer,
7671 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7672}
7673
fe3ef05c
NHE		 7674/*
7675 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7676 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7677 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7678 * guest in a way that will both be appropriate to L1's requests, and our
7679 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7680 * function also has additional necessary side-effects, like setting various
7681 * vcpu->arch fields.
7682 */
7683static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7684{
7685 struct vcpu_vmx *vmx = to_vmx(vcpu);
7686 u32 exec_control;
7687
7688 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7689 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7690 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7691 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7692 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7693 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7694 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7695 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7696 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7697 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7698 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7699 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7700 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7701 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7702 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7703 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7704 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7705 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7706 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7707 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7708 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7709 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7710 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7711 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7712 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7713 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7714 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7715 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7716 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7717 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7718 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7719 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7720 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7721 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7722 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7723 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7724
7725 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7726 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7727 vmcs12->vm_entry_intr_info_field);
7728 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7729 vmcs12->vm_entry_exception_error_code);
7730 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7731 vmcs12->vm_entry_instruction_len);
7732 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7733 vmcs12->guest_interruptibility_info);
fe3ef05c 7734 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7735 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7736 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7737 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7738 vmcs12->guest_pending_dbg_exceptions);
7739 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7740 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7741
7742 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7743
f4124500
JK		 7744 exec_control = vmcs12->pin_based_vm_exec_control;
7745 exec_control |= vmcs_config.pin_based_exec_ctrl;
7746 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7747 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7748
f4124500
JK		 7749 vmx->nested.preemption_timer_expired = false;
7750 if (nested_cpu_has_preemption_timer(vmcs12))
7751 vmx_start_preemption_timer(vcpu);
0238ea91 7752
fe3ef05c
NHE		 7753 /*
7754 * Whether page-faults are trapped is determined by a combination of
7755 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7756 * If enable_ept, L0 doesn't care about page faults and we should
7757 * set all of these to L1's desires. However, if !enable_ept, L0 does
7758 * care about (at least some) page faults, and because it is not easy
7759 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7760 * to exit on each and every L2 page fault. This is done by setting
7761 * MASK=MATCH=0 and (see below) EB.PF=1.
7762 * Note that below we don't need special code to set EB.PF beyond the
7763 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7764 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7765 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7766 *
7767 * A problem with this approach (when !enable_ept) is that L1 may be
7768 * injected with more page faults than it asked for. This could have
7769 * caused problems, but in practice existing hypervisors don't care.
7770 * To fix this, we will need to emulate the PFEC checking (on the L1
7771 * page tables), using walk_addr(), when injecting PFs to L1.
7772 */
7773 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7774 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7775 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7776 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7777
7778 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7779 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7780 if (!vmx->rdtscp_enabled)
7781 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7782 /* Take the following fields only from vmcs12 */
7783 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7784 if (nested_cpu_has(vmcs12,
7785 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7786 exec_control |= vmcs12->secondary_vm_exec_control;
7787
7788 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7789 /*
7790 * Translate L1 physical address to host physical
7791 * address for vmcs02. Keep the page pinned, so this
7792 * physical address remains valid. We keep a reference
7793 * to it so we can release it later.
7794 */
7795 if (vmx->nested.apic_access_page) /* shouldn't happen */
7796 nested_release_page(vmx->nested.apic_access_page);
7797 vmx->nested.apic_access_page =
7798 nested_get_page(vcpu, vmcs12->apic_access_addr);
7799 /*
7800 * If translation failed, no matter: This feature asks
7801 * to exit when accessing the given address, and if it
7802 * can never be accessed, this feature won't do
7803 * anything anyway.
7804 */
7805 if (!vmx->nested.apic_access_page)
7806 exec_control &=
7807 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7808 else
7809 vmcs_write64(APIC_ACCESS_ADDR,
7810 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7811 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7812 exec_control |=
7813 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7814 vmcs_write64(APIC_ACCESS_ADDR,
7815 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7816 }
7817
7818 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7819 }
7820
7821
7822 /*
7823 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7824 * Some constant fields are set here by vmx_set_constant_host_state().
7825 * Other fields are different per CPU, and will be set later when
7826 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7827 */
a547c6db 7828 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7829
7830 /*
7831 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7832 * entry, but only if the current (host) sp changed from the value
7833 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7834 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7835 * here we just force the write to happen on entry.
7836 */
7837 vmx->host_rsp = 0;
7838
7839 exec_control = vmx_exec_control(vmx); /* L0's desires */
7840 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7841 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7842 exec_control &= ~CPU_BASED_TPR_SHADOW;
7843 exec_control |= vmcs12->cpu_based_vm_exec_control;
7844 /*
7845 * Merging of IO and MSR bitmaps not currently supported.
7846 * Rather, exit every time.
7847 */
7848 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7849 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7850 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7851
7852 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7853
7854 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7855 * bitwise-or of what L1 wants to trap for L2, and what we want to
7856 * trap. Note that CR0.TS also needs updating - we do this later.
7857 */
7858 update_exception_bitmap(vcpu);
7859 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7860 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7861
8049d651
NHE		 7862 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7863 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7864 * bits are further modified by vmx_set_efer() below.
7865 */
f4124500 7866 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7867
7868 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7869 * emulated by vmx_set_efer(), below.
7870 */
2961e876 7871 vm_entry_controls_init(vmx,
8049d651
NHE		 7872 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7873 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7874 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7875
44811c02 7876 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7877 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7878 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7879 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7880 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7881
7882
7883 set_cr4_guest_host_mask(vmx);
7884
36be0b9d
PB		 7885 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7886 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7887
27fc51b2
NHE		 7888 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7889 vmcs_write64(TSC_OFFSET,
7890 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7891 else
7892 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7893
7894 if (enable_vpid) {
7895 /*
7896 * Trivially support vpid by letting L2s share their parent
7897 * L1's vpid. TODO: move to a more elaborate solution, giving
7898 * each L2 its own vpid and exposing the vpid feature to L1.
7899 */
7900 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7901 vmx_flush_tlb(vcpu);
7902 }
7903
155a97a3
NHE		 7904 if (nested_cpu_has_ept(vmcs12)) {
7905 kvm_mmu_unload(vcpu);
7906 nested_ept_init_mmu_context(vcpu);
7907 }
7908
fe3ef05c
NHE		 7909 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7910 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7911 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7912 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7913 else
7914 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7915 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7916 vmx_set_efer(vcpu, vcpu->arch.efer);
7917
7918 /*
7919 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7920 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7921 * The CR0_READ_SHADOW is what L2 should have expected to read given
7922 * the specifications by L1; It's not enough to take
7923 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7924 * have more bits than L1 expected.
7925 */
7926 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7927 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7928
7929 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7930 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7931
7932 /* shadow page tables on either EPT or shadow page tables */
7933 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7934 kvm_mmu_reset_context(vcpu);
7935
feaf0c7d
GN		 7936 if (!enable_ept)
7937 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7938
3633cfc3
NHE		 7939 /*
7940 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7941 */
7942 if (enable_ept) {
7943 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7944 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7945 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7946 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7947 }
7948
fe3ef05c
NHE		 7949 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7950 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7951}
7952
cd232ad0
NHE		 7953/*
7954 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7955 * for running an L2 nested guest.
7956 */
7957static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7958{
7959 struct vmcs12 *vmcs12;
7960 struct vcpu_vmx *vmx = to_vmx(vcpu);
7961 int cpu;
7962 struct loaded_vmcs *vmcs02;
384bb783 7963 bool ia32e;
cd232ad0
NHE		 7964
7965 if (!nested_vmx_check_permission(vcpu) ||
7966 !nested_vmx_check_vmcs12(vcpu))
7967 return 1;
7968
7969 skip_emulated_instruction(vcpu);
7970 vmcs12 = get_vmcs12(vcpu);
7971
012f83cb
AG		 7972 if (enable_shadow_vmcs)
7973 copy_shadow_to_vmcs12(vmx);
7974
7c177938
NHE		 7975 /*
7976 * The nested entry process starts with enforcing various prerequisites
7977 * on vmcs12 as required by the Intel SDM, and act appropriately when
7978 * they fail: As the SDM explains, some conditions should cause the
7979 * instruction to fail, while others will cause the instruction to seem
7980 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7981 * To speed up the normal (success) code path, we should avoid checking
7982 * for misconfigurations which will anyway be caught by the processor
7983 * when using the merged vmcs02.
7984 */
7985 if (vmcs12->launch_state == launch) {
7986 nested_vmx_failValid(vcpu,
7987 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7988 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7989 return 1;
7990 }
7991
6dfacadd
JK		 7992 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7993 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7994 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7995 return 1;
7996 }
7997
7c177938
NHE		 7998 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7999 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8000 /*TODO: Also verify bits beyond physical address width are 0*/
8001 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8002 return 1;
8003 }
8004
8005 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8006 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8007 /*TODO: Also verify bits beyond physical address width are 0*/
8008 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8009 return 1;
8010 }
8011
8012 if (vmcs12->vm_entry_msr_load_count > 0 ||
8013 vmcs12->vm_exit_msr_load_count > 0 ||
8014 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8015 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8016 __func__);
7c177938
NHE		 8017 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8018 return 1;
8019 }
8020
8021 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8022 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8023 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8024 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8025 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8026 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8027 !vmx_control_verify(vmcs12->vm_exit_controls,
8028 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8029 !vmx_control_verify(vmcs12->vm_entry_controls,
8030 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8031 {
8032 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8033 return 1;
8034 }
8035
8036 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8037 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8038 nested_vmx_failValid(vcpu,
8039 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8040 return 1;
8041 }
8042
92fbc7b1 8043 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8044 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8045 nested_vmx_entry_failure(vcpu, vmcs12,
8046 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8047 return 1;
8048 }
8049 if (vmcs12->vmcs_link_pointer != -1ull) {
8050 nested_vmx_entry_failure(vcpu, vmcs12,
8051 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8052 return 1;
8053 }
8054
384bb783 8055 /*
cb0c8cda 8056 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8057 * are performed on the field for the IA32_EFER MSR:
8058 * - Bits reserved in the IA32_EFER MSR must be 0.
8059 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8060 * the IA-32e mode guest VM-exit control. It must also be identical
8061 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8062 * CR0.PG) is 1.
8063 */
8064 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8065 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8066 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8067 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8068 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8069 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8070 nested_vmx_entry_failure(vcpu, vmcs12,
8071 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8072 return 1;
8073 }
8074 }
8075
8076 /*
8077 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8078 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8079 * the values of the LMA and LME bits in the field must each be that of
8080 * the host address-space size VM-exit control.
8081 */
8082 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8083 ia32e = (vmcs12->vm_exit_controls &
8084 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8085 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8086 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8087 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8088 nested_vmx_entry_failure(vcpu, vmcs12,
8089 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8090 return 1;
8091 }
8092 }
8093
7c177938
NHE		 8094 /*
8095 * We're finally done with prerequisite checking, and can start with
8096 * the nested entry.
8097 */
8098
cd232ad0
NHE		 8099 vmcs02 = nested_get_current_vmcs02(vmx);
8100 if (!vmcs02)
8101 return -ENOMEM;
8102
8103 enter_guest_mode(vcpu);
8104
8105 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8106
8107 cpu = get_cpu();
8108 vmx->loaded_vmcs = vmcs02;
8109 vmx_vcpu_put(vcpu);
8110 vmx_vcpu_load(vcpu, cpu);
8111 vcpu->cpu = cpu;
8112 put_cpu();
8113
36c3cc42
JK		 8114 vmx_segment_cache_clear(vmx);
8115
cd232ad0
NHE		 8116 vmcs12->launch_state = 1;
8117
8118 prepare_vmcs02(vcpu, vmcs12);
8119
6dfacadd
JK		 8120 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8121 return kvm_emulate_halt(vcpu);
8122
7af40ad3
JK		 8123 vmx->nested.nested_run_pending = 1;
8124
cd232ad0
NHE		 8125 /*
8126 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8127 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8128 * returned as far as L1 is concerned. It will only return (and set
8129 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8130 */
8131 return 1;
8132}
8133
4704d0be
NHE		 8134/*
8135 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8136 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8137 * This function returns the new value we should put in vmcs12.guest_cr0.
8138 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8139 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8140 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8141 * didn't trap the bit, because if L1 did, so would L0).
8142 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8143 * been modified by L2, and L1 knows it. So just leave the old value of
8144 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8145 * isn't relevant, because if L0 traps this bit it can set it to anything.
8146 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8147 * changed these bits, and therefore they need to be updated, but L0
8148 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8149 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8150 */
8151static inline unsigned long
8152vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8153{
8154 return
8155 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8156 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8157 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8158 vcpu->arch.cr0_guest_owned_bits));
8159}
8160
8161static inline unsigned long
8162vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8163{
8164 return
8165 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8166 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8167 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8168 vcpu->arch.cr4_guest_owned_bits));
8169}
8170
5f3d5799
JK		 8171static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8172 struct vmcs12 *vmcs12)
8173{
8174 u32 idt_vectoring;
8175 unsigned int nr;
8176
851eb667 8177 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8178 nr = vcpu->arch.exception.nr;
8179 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8180
8181 if (kvm_exception_is_soft(nr)) {
8182 vmcs12->vm_exit_instruction_len =
8183 vcpu->arch.event_exit_inst_len;
8184 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8185 } else
8186 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8187
8188 if (vcpu->arch.exception.has_error_code) {
8189 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8190 vmcs12->idt_vectoring_error_code =
8191 vcpu->arch.exception.error_code;
8192 }
8193
8194 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8195 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8196 vmcs12->idt_vectoring_info_field =
8197 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8198 } else if (vcpu->arch.interrupt.pending) {
8199 nr = vcpu->arch.interrupt.nr;
8200 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8201
8202 if (vcpu->arch.interrupt.soft) {
8203 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8204 vmcs12->vm_entry_instruction_len =
8205 vcpu->arch.event_exit_inst_len;
8206 } else
8207 idt_vectoring |= INTR_TYPE_EXT_INTR;
8208
8209 vmcs12->idt_vectoring_info_field = idt_vectoring;
8210 }
8211}
8212
b6b8a145
JK		 8213static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8214{
8215 struct vcpu_vmx *vmx = to_vmx(vcpu);
8216
f4124500
JK		 8217 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8218 vmx->nested.preemption_timer_expired) {
8219 if (vmx->nested.nested_run_pending)
8220 return -EBUSY;
8221 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8222 return 0;
8223 }
8224
b6b8a145 8225 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8226 if (vmx->nested.nested_run_pending ||
8227 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8228 return -EBUSY;
8229 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8230 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8231 INTR_INFO_VALID_MASK, 0);
8232 /*
8233 * The NMI-triggered VM exit counts as injection:
8234 * clear this one and block further NMIs.
8235 */
8236 vcpu->arch.nmi_pending = 0;
8237 vmx_set_nmi_mask(vcpu, true);
8238 return 0;
8239 }
8240
8241 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8242 nested_exit_on_intr(vcpu)) {
8243 if (vmx->nested.nested_run_pending)
8244 return -EBUSY;
8245 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8246 }
8247
8248 return 0;
8249}
8250
f4124500
JK		 8251static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8252{
8253 ktime_t remaining =
8254 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8255 u64 value;
8256
8257 if (ktime_to_ns(remaining) <= 0)
8258 return 0;
8259
8260 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8261 do_div(value, 1000000);
8262 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8263}
8264
4704d0be
NHE		 8265/*
8266 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8267 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8268 * and this function updates it to reflect the changes to the guest state while
8269 * L2 was running (and perhaps made some exits which were handled directly by L0
8270 * without going back to L1), and to reflect the exit reason.
8271 * Note that we do not have to copy here all VMCS fields, just those that
8272 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8273 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8274 * which already writes to vmcs12 directly.
8275 */
533558bc
JK		 8276static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8277 u32 exit_reason, u32 exit_intr_info,
8278 unsigned long exit_qualification)
4704d0be
NHE		 8279{
8280 /* update guest state fields: */
8281 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8282 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8283
8284 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8285 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8286 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8287 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8288
8289 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8290 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8291 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8292 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8293 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8294 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8295 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8296 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8297 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8298 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8299 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8300 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8301 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8302 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8303 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8304 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8305 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8306 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8307 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8308 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8309 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8310 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8311 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8312 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8313 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8314 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8315 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8316 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8317 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8318 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8319 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8320 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8321 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8322 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8323 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8324 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8325
4704d0be
NHE		 8326 vmcs12->guest_interruptibility_info =
8327 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8328 vmcs12->guest_pending_dbg_exceptions =
8329 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8330 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8331 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8332 else
8333 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8334
f4124500
JK		 8335 if (nested_cpu_has_preemption_timer(vmcs12)) {
8336 if (vmcs12->vm_exit_controls &
8337 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8338 vmcs12->vmx_preemption_timer_value =
8339 vmx_get_preemption_timer_value(vcpu);
8340 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8341 }
7854cbca 8342
3633cfc3
NHE		 8343 /*
8344 * In some cases (usually, nested EPT), L2 is allowed to change its
8345 * own CR3 without exiting. If it has changed it, we must keep it.
8346 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8347 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8348 *
8349 * Additionally, restore L2's PDPTR to vmcs12.
8350 */
8351 if (enable_ept) {
8352 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8353 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8354 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8355 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8356 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8357 }
8358
c18911a2
JK		 8359 vmcs12->vm_entry_controls =
8360 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8361 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8362
4704d0be
NHE		 8363 /* TODO: These cannot have changed unless we have MSR bitmaps and
8364 * the relevant bit asks not to trap the change */
8365 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8366 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8367 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8368 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8369 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8370 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8371 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8372 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8373 if (vmx_mpx_supported())
8374 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8375
8376 /* update exit information fields: */
8377
533558bc
JK		 8378 vmcs12->vm_exit_reason = exit_reason;
8379 vmcs12->exit_qualification = exit_qualification;
4704d0be 8380
533558bc 8381 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8382 if ((vmcs12->vm_exit_intr_info &
8383 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8384 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8385 vmcs12->vm_exit_intr_error_code =
8386 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8387 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8388 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8389 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8390
5f3d5799
JK		 8391 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8392 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8393 * instead of reading the real value. */
4704d0be 8394 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8395
8396 /*
8397 * Transfer the event that L0 or L1 may wanted to inject into
8398 * L2 to IDT_VECTORING_INFO_FIELD.
8399 */
8400 vmcs12_save_pending_event(vcpu, vmcs12);
8401 }
8402
8403 /*
8404 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8405 * preserved above and would only end up incorrectly in L1.
8406 */
8407 vcpu->arch.nmi_injected = false;
8408 kvm_clear_exception_queue(vcpu);
8409 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8410}
8411
8412/*
8413 * A part of what we need to when the nested L2 guest exits and we want to
8414 * run its L1 parent, is to reset L1's guest state to the host state specified
8415 * in vmcs12.
8416 * This function is to be called not only on normal nested exit, but also on
8417 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8418 * Failures During or After Loading Guest State").
8419 * This function should be called when the active VMCS is L1's (vmcs01).
8420 */
733568f9
JK		 8421static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8422 struct vmcs12 *vmcs12)
4704d0be 8423{
21feb4eb
ACL		 8424 struct kvm_segment seg;
8425
4704d0be
NHE		 8426 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8427 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8428 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8429 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8430 else
8431 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8432 vmx_set_efer(vcpu, vcpu->arch.efer);
8433
8434 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8435 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8436 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8437 /*
8438 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8439 * actually changed, because it depends on the current state of
8440 * fpu_active (which may have changed).
8441 * Note that vmx_set_cr0 refers to efer set above.
8442 */
9e3e4dbf 8443 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8444 /*
8445 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8446 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8447 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8448 */
8449 update_exception_bitmap(vcpu);
8450 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8451 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8452
8453 /*
8454 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8455 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8456 */
8457 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8458 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8459
29bf08f1 8460 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8461
4704d0be
NHE		 8462 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8463 kvm_mmu_reset_context(vcpu);
8464
feaf0c7d
GN		 8465 if (!enable_ept)
8466 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8467
4704d0be
NHE		 8468 if (enable_vpid) {
8469 /*
8470 * Trivially support vpid by letting L2s share their parent
8471 * L1's vpid. TODO: move to a more elaborate solution, giving
8472 * each L2 its own vpid and exposing the vpid feature to L1.
8473 */
8474 vmx_flush_tlb(vcpu);
8475 }
8476
8477
8478 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8479 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8480 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8481 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8482 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8483
36be0b9d
PB		 8484 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8485 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8486 vmcs_write64(GUEST_BNDCFGS, 0);
8487
44811c02 8488 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8489 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8490 vcpu->arch.pat = vmcs12->host_ia32_pat;
8491 }
4704d0be
NHE		 8492 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8493 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8494 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8495
21feb4eb
ACL		 8496 /* Set L1 segment info according to Intel SDM
8497 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8498 seg = (struct kvm_segment) {
8499 .base = 0,
8500 .limit = 0xFFFFFFFF,
8501 .selector = vmcs12->host_cs_selector,
8502 .type = 11,
8503 .present = 1,
8504 .s = 1,
8505 .g = 1
8506 };
8507 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8508 seg.l = 1;
8509 else
8510 seg.db = 1;
8511 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8512 seg = (struct kvm_segment) {
8513 .base = 0,
8514 .limit = 0xFFFFFFFF,
8515 .type = 3,
8516 .present = 1,
8517 .s = 1,
8518 .db = 1,
8519 .g = 1
8520 };
8521 seg.selector = vmcs12->host_ds_selector;
8522 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8523 seg.selector = vmcs12->host_es_selector;
8524 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8525 seg.selector = vmcs12->host_ss_selector;
8526 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8527 seg.selector = vmcs12->host_fs_selector;
8528 seg.base = vmcs12->host_fs_base;
8529 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8530 seg.selector = vmcs12->host_gs_selector;
8531 seg.base = vmcs12->host_gs_base;
8532 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8533 seg = (struct kvm_segment) {
205befd9 8534 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8535 .limit = 0x67,
8536 .selector = vmcs12->host_tr_selector,
8537 .type = 11,
8538 .present = 1
8539 };
8540 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8541
503cd0c5
JK		 8542 kvm_set_dr(vcpu, 7, 0x400);
8543 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8544}
8545
8546/*
8547 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8548 * and modify vmcs12 to make it see what it would expect to see there if
8549 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8550 */
533558bc
JK		 8551static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8552 u32 exit_intr_info,
8553 unsigned long exit_qualification)
4704d0be
NHE		 8554{
8555 struct vcpu_vmx *vmx = to_vmx(vcpu);
8556 int cpu;
8557 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8558
5f3d5799
JK		 8559 /* trying to cancel vmlaunch/vmresume is a bug */
8560 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8561
4704d0be 8562 leave_guest_mode(vcpu);
533558bc
JK		 8563 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8564 exit_qualification);
4704d0be 8565
542060ea
JK		 8566 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8567 vmcs12->exit_qualification,
8568 vmcs12->idt_vectoring_info_field,
8569 vmcs12->vm_exit_intr_info,
8570 vmcs12->vm_exit_intr_error_code,
8571 KVM_ISA_VMX);
4704d0be
NHE		 8572
8573 cpu = get_cpu();
8574 vmx->loaded_vmcs = &vmx->vmcs01;
8575 vmx_vcpu_put(vcpu);
8576 vmx_vcpu_load(vcpu, cpu);
8577 vcpu->cpu = cpu;
8578 put_cpu();
8579
2961e876
GN		 8580 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8581 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8582 vmx_segment_cache_clear(vmx);
8583
4704d0be
NHE		 8584 /* if no vmcs02 cache requested, remove the one we used */
8585 if (VMCS02_POOL_SIZE == 0)
8586 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8587
8588 load_vmcs12_host_state(vcpu, vmcs12);
8589
27fc51b2 8590 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8591 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8592
8593 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8594 vmx->host_rsp = 0;
8595
8596 /* Unpin physical memory we referred to in vmcs02 */
8597 if (vmx->nested.apic_access_page) {
8598 nested_release_page(vmx->nested.apic_access_page);
8599 vmx->nested.apic_access_page = 0;
8600 }
8601
8602 /*
8603 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8604 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8605 * success or failure flag accordingly.
8606 */
8607 if (unlikely(vmx->fail)) {
8608 vmx->fail = 0;
8609 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8610 } else
8611 nested_vmx_succeed(vcpu);
012f83cb
AG		 8612 if (enable_shadow_vmcs)
8613 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8614
8615 /* in case we halted in L2 */
8616 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8617}
8618
42124925
JK		 8619/*
8620 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8621 */
8622static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8623{
8624 if (is_guest_mode(vcpu))
533558bc 8625 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8626 free_nested(to_vmx(vcpu));
8627}
8628
7c177938
NHE		 8629/*
8630 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8631 * 23.7 "VM-entry failures during or after loading guest state" (this also
8632 * lists the acceptable exit-reason and exit-qualification parameters).
8633 * It should only be called before L2 actually succeeded to run, and when
8634 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8635 */
8636static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8637 struct vmcs12 *vmcs12,
8638 u32 reason, unsigned long qualification)
8639{
8640 load_vmcs12_host_state(vcpu, vmcs12);
8641 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8642 vmcs12->exit_qualification = qualification;
8643 nested_vmx_succeed(vcpu);
012f83cb
AG		 8644 if (enable_shadow_vmcs)
8645 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8646}
8647
8a76d7f2
JR		 8648static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8649 struct x86_instruction_info *info,
8650 enum x86_intercept_stage stage)
8651{
8652 return X86EMUL_CONTINUE;
8653}
8654
cbdd1bea 8655static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8656 .cpu_has_kvm_support = cpu_has_kvm_support,
8657 .disabled_by_bios = vmx_disabled_by_bios,
8658 .hardware_setup = hardware_setup,
8659 .hardware_unsetup = hardware_unsetup,
002c7f7c 8660 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8661 .hardware_enable = hardware_enable,
8662 .hardware_disable = hardware_disable,
04547156 8663 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8664
8665 .vcpu_create = vmx_create_vcpu,
8666 .vcpu_free = vmx_free_vcpu,
04d2cc77 8667 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8668
04d2cc77 8669 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8670 .vcpu_load = vmx_vcpu_load,
8671 .vcpu_put = vmx_vcpu_put,
8672
c8639010 8673 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8674 .get_msr = vmx_get_msr,
8675 .set_msr = vmx_set_msr,
8676 .get_segment_base = vmx_get_segment_base,
8677 .get_segment = vmx_get_segment,
8678 .set_segment = vmx_set_segment,
2e4d2653 8679 .get_cpl = vmx_get_cpl,
6aa8b732 8680 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8681 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8682 .decache_cr3 = vmx_decache_cr3,
25c4c276 8683 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8684 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8685 .set_cr3 = vmx_set_cr3,
8686 .set_cr4 = vmx_set_cr4,
6aa8b732 8687 .set_efer = vmx_set_efer,
6aa8b732
AK		 8688 .get_idt = vmx_get_idt,
8689 .set_idt = vmx_set_idt,
8690 .get_gdt = vmx_get_gdt,
8691 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8692 .get_dr6 = vmx_get_dr6,
8693 .set_dr6 = vmx_set_dr6,
020df079 8694 .set_dr7 = vmx_set_dr7,
81908bf4 8695 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8696 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8697 .get_rflags = vmx_get_rflags,
8698 .set_rflags = vmx_set_rflags,
ebcbab4c 8699 .fpu_activate = vmx_fpu_activate,
02daab21 8700 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8701
8702 .tlb_flush = vmx_flush_tlb,
6aa8b732 8703
6aa8b732 8704 .run = vmx_vcpu_run,
6062d012 8705 .handle_exit = vmx_handle_exit,
6aa8b732 8706 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8707 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8708 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8709 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8710 .set_irq = vmx_inject_irq,
95ba8273 8711 .set_nmi = vmx_inject_nmi,
298101da 8712 .queue_exception = vmx_queue_exception,
b463a6f7 8713 .cancel_injection = vmx_cancel_injection,
78646121 8714 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8715 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8716 .get_nmi_mask = vmx_get_nmi_mask,
8717 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8718 .enable_nmi_window = enable_nmi_window,
8719 .enable_irq_window = enable_irq_window,
8720 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8721 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8722 .vm_has_apicv = vmx_vm_has_apicv,
8723 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8724 .hwapic_irr_update = vmx_hwapic_irr_update,
8725 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8726 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8727 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8728
cbc94022 8729 .set_tss_addr = vmx_set_tss_addr,
67253af5 8730 .get_tdp_level = get_ept_level,
4b12f0de 8731 .get_mt_mask = vmx_get_mt_mask,
229456fc 8732
586f9607 8733 .get_exit_info = vmx_get_exit_info,
586f9607 8734
17cc3935 8735 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8736
8737 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8738
8739 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8740 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8741
8742 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8743
8744 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8745
4051b188 8746 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8747 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8748 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8749 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8750 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8751 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8752
8753 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8754
8755 .check_intercept = vmx_check_intercept,
a547c6db 8756 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8757 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8758
8759 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8760};
8761
8762static int __init vmx_init(void)
8763{
8d14695f 8764 int r, i, msr;
26bb0981
AK		 8765
8766 rdmsrl_safe(MSR_EFER, &host_efer);
8767
8768 for (i = 0; i < NR_VMX_MSR; ++i)
8769 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8770
3e7c73e9 8771 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8772 if (!vmx_io_bitmap_a)
8773 return -ENOMEM;
8774
2106a548
GC		 8775 r = -ENOMEM;
8776
3e7c73e9 8777 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8778 if (!vmx_io_bitmap_b)
fdef3ad1 8779 goto out;
fdef3ad1 8780
5897297b 8781 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8782 if (!vmx_msr_bitmap_legacy)
25c5f225 8783 goto out1;
2106a548 8784
8d14695f
YZ		 8785 vmx_msr_bitmap_legacy_x2apic =
8786 (unsigned long *)__get_free_page(GFP_KERNEL);
8787 if (!vmx_msr_bitmap_legacy_x2apic)
8788 goto out2;
25c5f225 8789
5897297b 8790 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8791 if (!vmx_msr_bitmap_longmode)
8d14695f 8792 goto out3;
2106a548 8793
8d14695f
YZ		 8794 vmx_msr_bitmap_longmode_x2apic =
8795 (unsigned long *)__get_free_page(GFP_KERNEL);
8796 if (!vmx_msr_bitmap_longmode_x2apic)
8797 goto out4;
4607c2d7
AG		 8798 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8799 if (!vmx_vmread_bitmap)
8800 goto out5;
8801
8802 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8803 if (!vmx_vmwrite_bitmap)
8804 goto out6;
8805
8806 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8807 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8808 /* shadowed read/write fields */
8809 for (i = 0; i < max_shadow_read_write_fields; i++) {
8810 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8811 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8812 }
8813 /* shadowed read only fields */
8814 for (i = 0; i < max_shadow_read_only_fields; i++)
8815 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8816
fdef3ad1
HQ		 8817 /*
8818 * Allow direct access to the PC debug port (it is often used for I/O
8819 * delays, but the vmexits simply slow things down).
8820 */
3e7c73e9
AK		 8821 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8822 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8823
3e7c73e9 8824 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8825
5897297b
AK		 8826 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8827 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8828
2384d2b3
SY		 8829 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8830
0ee75bea
AK		 8831 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8832 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8833 if (r)
4607c2d7 8834 goto out7;
25c5f225 8835
8f536b76
ZY		 8836#ifdef CONFIG_KEXEC
8837 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8838 crash_vmclear_local_loaded_vmcss);
8839#endif
8840
5897297b
AK		 8841 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8842 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8843 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8844 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8845 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8846 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8847 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8848
8d14695f
YZ		 8849 memcpy(vmx_msr_bitmap_legacy_x2apic,
8850 vmx_msr_bitmap_legacy, PAGE_SIZE);
8851 memcpy(vmx_msr_bitmap_longmode_x2apic,
8852 vmx_msr_bitmap_longmode, PAGE_SIZE);
8853
01e439be 8854 if (enable_apicv) {
8d14695f
YZ		 8855 for (msr = 0x800; msr <= 0x8ff; msr++)
8856 vmx_disable_intercept_msr_read_x2apic(msr);
8857
8858 /* According SDM, in x2apic mode, the whole id reg is used.
8859 * But in KVM, it only use the highest eight bits. Need to
8860 * intercept it */
8861 vmx_enable_intercept_msr_read_x2apic(0x802);
8862 /* TMCCT */
8863 vmx_enable_intercept_msr_read_x2apic(0x839);
8864 /* TPR */
8865 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8866 /* EOI */
8867 vmx_disable_intercept_msr_write_x2apic(0x80b);
8868 /* SELF-IPI */
8869 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8870 }
fdef3ad1 8871
089d034e 8872 if (enable_ept) {
3f6d8c8a
XH		 8873 kvm_mmu_set_mask_ptes(0ull,
8874 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8875 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8876 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8877 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8878 kvm_enable_tdp();
8879 } else
8880 kvm_disable_tdp();
1439442c 8881
fdef3ad1
HQ		 8882 return 0;
8883
4607c2d7
AG		 8884out7:
8885 free_page((unsigned long)vmx_vmwrite_bitmap);
8886out6:
8887 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8888out5:
8889 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8890out4:
5897297b 8891 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8892out3:
8893 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8894out2:
5897297b 8895 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8896out1:
3e7c73e9 8897 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8898out:
3e7c73e9 8899 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8900 return r;
6aa8b732
AK		 8901}
8902
8903static void __exit vmx_exit(void)
8904{
8d14695f
YZ		 8905 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8906 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8907 free_page((unsigned long)vmx_msr_bitmap_legacy);
8908 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8909 free_page((unsigned long)vmx_io_bitmap_b);
8910 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8911 free_page((unsigned long)vmx_vmwrite_bitmap);
8912 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8913
8f536b76
ZY		 8914#ifdef CONFIG_KEXEC
8915 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8916 synchronize_rcu();
8917#endif
8918
cb498ea2 8919 kvm_exit();
6aa8b732
AK		 8920}
8921
8922module_init(vmx_init)
8923module_exit(vmx_exit)
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