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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
a9d30f33
NHE		 357
358 /* The guest-physical address of the current VMCS L1 keeps for L2 */
359 gpa_t current_vmptr;
360 /* The host-usable pointer to the above */
361 struct page *current_vmcs12_page;
362 struct vmcs12 *current_vmcs12;
8de48833 363 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 364 /*
365 * Indicates if the shadow vmcs must be updated with the
366 * data hold by vmcs12
367 */
368 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 369
370 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
371 struct list_head vmcs02_pool;
372 int vmcs02_num;
fe3ef05c 373 u64 vmcs01_tsc_offset;
644d711a
NHE		 374 /* L2 must run next, and mustn't decide to exit to L1. */
375 bool nested_run_pending;
fe3ef05c
NHE		 376 /*
377 * Guest pages referred to in vmcs02 with host-physical pointers, so
378 * we must keep them pinned while L2 runs.
379 */
380 struct page *apic_access_page;
b3897a49 381 u64 msr_ia32_feature_control;
f4124500
JK		 382
383 struct hrtimer preemption_timer;
384 bool preemption_timer_expired;
ec378aee
NHE		 385};
386
01e439be
YZ		 387#define POSTED_INTR_ON 0
388/* Posted-Interrupt Descriptor */
389struct pi_desc {
390 u32 pir[8]; /* Posted interrupt requested */
391 u32 control; /* bit 0 of control is outstanding notification bit */
392 u32 rsvd[7];
393} __aligned(64);
394
a20ed54d
YZ		 395static bool pi_test_and_set_on(struct pi_desc *pi_desc)
396{
397 return test_and_set_bit(POSTED_INTR_ON,
398 (unsigned long *)&pi_desc->control);
399}
400
401static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
402{
403 return test_and_clear_bit(POSTED_INTR_ON,
404 (unsigned long *)&pi_desc->control);
405}
406
407static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
408{
409 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
410}
411
a2fa3e9f 412struct vcpu_vmx {
fb3f0f51 413 struct kvm_vcpu vcpu;
313dbd49 414 unsigned long host_rsp;
29bd8a78 415 u8 fail;
69c73028 416 u8 cpl;
9d58b931 417 bool nmi_known_unmasked;
51aa01d1 418 u32 exit_intr_info;
1155f76a 419 u32 idt_vectoring_info;
6de12732 420 ulong rflags;
26bb0981 421 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 422 int nmsrs;
423 int save_nmsrs;
a547c6db 424 unsigned long host_idt_base;
a2fa3e9f 425#ifdef CONFIG_X86_64
44ea2b17
AK		 426 u64 msr_host_kernel_gs_base;
427 u64 msr_guest_kernel_gs_base;
a2fa3e9f 428#endif
2961e876
GN		 429 u32 vm_entry_controls_shadow;
430 u32 vm_exit_controls_shadow;
d462b819
NHE		 431 /*
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
435 */
436 struct loaded_vmcs vmcs01;
437 struct loaded_vmcs *loaded_vmcs;
438 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 439 struct msr_autoload {
440 unsigned nr;
441 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
442 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
443 } msr_autoload;
a2fa3e9f
GH		 444 struct {
445 int loaded;
446 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 447#ifdef CONFIG_X86_64
448 u16 ds_sel, es_sel;
449#endif
152d3f2f
LV		 450 int gs_ldt_reload_needed;
451 int fs_reload_needed;
da8999d3 452 u64 msr_host_bndcfgs;
d77c26fc 453 } host_state;
9c8cba37 454 struct {
7ffd92c5 455 int vm86_active;
78ac8b47 456 ulong save_rflags;
f5f7b2fe
AK		 457 struct kvm_segment segs[8];
458 } rmode;
459 struct {
460 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 461 struct kvm_save_segment {
462 u16 selector;
463 unsigned long base;
464 u32 limit;
465 u32 ar;
f5f7b2fe 466 } seg[8];
2fb92db1 467 } segment_cache;
2384d2b3 468 int vpid;
04fa4d32 469 bool emulation_required;
3b86cd99
JK		 470
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked;
473 ktime_t entry_time;
474 s64 vnmi_blocked_time;
a0861c02 475 u32 exit_reason;
4e47c7a6
SY		 476
477 bool rdtscp_enabled;
ec378aee 478
01e439be
YZ		 479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc;
481
ec378aee
NHE		 482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested;
a2fa3e9f
GH		 484};
485
2fb92db1
AK		 486enum segment_cache_field {
487 SEG_FIELD_SEL = 0,
488 SEG_FIELD_BASE = 1,
489 SEG_FIELD_LIMIT = 2,
490 SEG_FIELD_AR = 3,
491
492 SEG_FIELD_NR = 4
493};
494
a2fa3e9f
GH		 495static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
496{
fb3f0f51 497 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 498}
499
22bd0358
NHE		 500#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
504
4607c2d7 505
fe2b201b 506static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 507 /*
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
518 */
519 VM_EXIT_REASON,
520 VM_EXIT_INTR_INFO,
521 VM_EXIT_INSTRUCTION_LEN,
522 IDT_VECTORING_INFO_FIELD,
523 IDT_VECTORING_ERROR_CODE,
524 VM_EXIT_INTR_ERROR_CODE,
525 EXIT_QUALIFICATION,
526 GUEST_LINEAR_ADDRESS,
527 GUEST_PHYSICAL_ADDRESS
528};
fe2b201b 529static int max_shadow_read_only_fields =
4607c2d7
AG		 530 ARRAY_SIZE(shadow_read_only_fields);
531
fe2b201b 532static unsigned long shadow_read_write_fields[] = {
4607c2d7
AG		 533 GUEST_RIP,
534 GUEST_RSP,
535 GUEST_CR0,
536 GUEST_CR3,
537 GUEST_CR4,
538 GUEST_INTERRUPTIBILITY_INFO,
539 GUEST_RFLAGS,
540 GUEST_CS_SELECTOR,
541 GUEST_CS_AR_BYTES,
542 GUEST_CS_LIMIT,
543 GUEST_CS_BASE,
544 GUEST_ES_BASE,
36be0b9d 545 GUEST_BNDCFGS,
4607c2d7
AG		 546 CR0_GUEST_HOST_MASK,
547 CR0_READ_SHADOW,
548 CR4_READ_SHADOW,
549 TSC_OFFSET,
550 EXCEPTION_BITMAP,
551 CPU_BASED_VM_EXEC_CONTROL,
552 VM_ENTRY_EXCEPTION_ERROR_CODE,
553 VM_ENTRY_INTR_INFO_FIELD,
554 VM_ENTRY_INSTRUCTION_LEN,
555 VM_ENTRY_EXCEPTION_ERROR_CODE,
556 HOST_FS_BASE,
557 HOST_GS_BASE,
558 HOST_FS_SELECTOR,
559 HOST_GS_SELECTOR
560};
fe2b201b 561static int max_shadow_read_write_fields =
4607c2d7
AG		 562 ARRAY_SIZE(shadow_read_write_fields);
563
772e0318 564static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 565 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
566 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
567 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
568 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
569 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
570 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
571 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
572 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
573 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
574 FIELD(HOST_ES_SELECTOR, host_es_selector),
575 FIELD(HOST_CS_SELECTOR, host_cs_selector),
576 FIELD(HOST_SS_SELECTOR, host_ss_selector),
577 FIELD(HOST_DS_SELECTOR, host_ds_selector),
578 FIELD(HOST_FS_SELECTOR, host_fs_selector),
579 FIELD(HOST_GS_SELECTOR, host_gs_selector),
580 FIELD(HOST_TR_SELECTOR, host_tr_selector),
581 FIELD64(IO_BITMAP_A, io_bitmap_a),
582 FIELD64(IO_BITMAP_B, io_bitmap_b),
583 FIELD64(MSR_BITMAP, msr_bitmap),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
587 FIELD64(TSC_OFFSET, tsc_offset),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
589 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
590 FIELD64(EPT_POINTER, ept_pointer),
591 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
592 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
593 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
594 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
595 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
597 FIELD64(GUEST_PDPTR0, guest_pdptr0),
598 FIELD64(GUEST_PDPTR1, guest_pdptr1),
599 FIELD64(GUEST_PDPTR2, guest_pdptr2),
600 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 601 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 602 FIELD64(HOST_IA32_PAT, host_ia32_pat),
603 FIELD64(HOST_IA32_EFER, host_ia32_efer),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
607 FIELD(EXCEPTION_BITMAP, exception_bitmap),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
610 FIELD(CR3_TARGET_COUNT, cr3_target_count),
611 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
612 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
614 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
619 FIELD(TPR_THRESHOLD, tpr_threshold),
620 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
621 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
622 FIELD(VM_EXIT_REASON, vm_exit_reason),
623 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
624 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
625 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
626 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
627 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
628 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
629 FIELD(GUEST_ES_LIMIT, guest_es_limit),
630 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
631 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
632 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
633 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
634 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
635 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
636 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
637 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
638 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
639 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
640 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
641 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
642 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
643 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
644 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
645 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
646 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
648 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
649 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
650 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 651 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 652 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
653 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
654 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
655 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
656 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
657 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
658 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
659 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
660 FIELD(EXIT_QUALIFICATION, exit_qualification),
661 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
662 FIELD(GUEST_CR0, guest_cr0),
663 FIELD(GUEST_CR3, guest_cr3),
664 FIELD(GUEST_CR4, guest_cr4),
665 FIELD(GUEST_ES_BASE, guest_es_base),
666 FIELD(GUEST_CS_BASE, guest_cs_base),
667 FIELD(GUEST_SS_BASE, guest_ss_base),
668 FIELD(GUEST_DS_BASE, guest_ds_base),
669 FIELD(GUEST_FS_BASE, guest_fs_base),
670 FIELD(GUEST_GS_BASE, guest_gs_base),
671 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
672 FIELD(GUEST_TR_BASE, guest_tr_base),
673 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
674 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
675 FIELD(GUEST_DR7, guest_dr7),
676 FIELD(GUEST_RSP, guest_rsp),
677 FIELD(GUEST_RIP, guest_rip),
678 FIELD(GUEST_RFLAGS, guest_rflags),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
680 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
681 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
682 FIELD(HOST_CR0, host_cr0),
683 FIELD(HOST_CR3, host_cr3),
684 FIELD(HOST_CR4, host_cr4),
685 FIELD(HOST_FS_BASE, host_fs_base),
686 FIELD(HOST_GS_BASE, host_gs_base),
687 FIELD(HOST_TR_BASE, host_tr_base),
688 FIELD(HOST_GDTR_BASE, host_gdtr_base),
689 FIELD(HOST_IDTR_BASE, host_idtr_base),
690 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
691 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
692 FIELD(HOST_RSP, host_rsp),
693 FIELD(HOST_RIP, host_rip),
694};
695static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
696
697static inline short vmcs_field_to_offset(unsigned long field)
698{
699 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
700 return -1;
701 return vmcs_field_to_offset_table[field];
702}
703
a9d30f33
NHE		 704static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
705{
706 return to_vmx(vcpu)->nested.current_vmcs12;
707}
708
709static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
710{
711 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 712 if (is_error_page(page))
a9d30f33 713 return NULL;
32cad84f 714
a9d30f33
NHE		 715 return page;
716}
717
718static void nested_release_page(struct page *page)
719{
720 kvm_release_page_dirty(page);
721}
722
723static void nested_release_page_clean(struct page *page)
724{
725 kvm_release_page_clean(page);
726}
727
bfd0a56b 728static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 729static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 730static void kvm_cpu_vmxon(u64 addr);
731static void kvm_cpu_vmxoff(void);
93c4adc7 732static bool vmx_mpx_supported(void);
776e58ea 733static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 734static void vmx_set_segment(struct kvm_vcpu *vcpu,
735 struct kvm_segment *var, int seg);
736static void vmx_get_segment(struct kvm_vcpu *vcpu,
737 struct kvm_segment *var, int seg);
d99e4152
GN		 738static bool guest_state_valid(struct kvm_vcpu *vcpu);
739static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 740static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 741static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 742static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
36be0b9d 743static bool vmx_mpx_supported(void);
75880a01 744
6aa8b732
AK		 745static DEFINE_PER_CPU(struct vmcs *, vmxarea);
746static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 747/*
748 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
749 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
750 */
751static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 752static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 753
3e7c73e9
AK		 754static unsigned long *vmx_io_bitmap_a;
755static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 756static unsigned long *vmx_msr_bitmap_legacy;
757static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 758static unsigned long *vmx_msr_bitmap_legacy_x2apic;
759static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 760static unsigned long *vmx_vmread_bitmap;
761static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 762
110312c8 763static bool cpu_has_load_ia32_efer;
8bf00a52 764static bool cpu_has_load_perf_global_ctrl;
110312c8 765
2384d2b3
SY		 766static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
767static DEFINE_SPINLOCK(vmx_vpid_lock);
768
1c3d14fe 769static struct vmcs_config {
6aa8b732
AK		 770 int size;
771 int order;
772 u32 revision_id;
1c3d14fe
YS		 773 u32 pin_based_exec_ctrl;
774 u32 cpu_based_exec_ctrl;
f78e0e2e 775 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 776 u32 vmexit_ctrl;
777 u32 vmentry_ctrl;
778} vmcs_config;
6aa8b732 779
efff9e53 780static struct vmx_capability {
d56f546d
SY		 781 u32 ept;
782 u32 vpid;
783} vmx_capability;
784
6aa8b732
AK		 785#define VMX_SEGMENT_FIELD(seg) \
786 [VCPU_SREG_##seg] = { \
787 .selector = GUEST_##seg##_SELECTOR, \
788 .base = GUEST_##seg##_BASE, \
789 .limit = GUEST_##seg##_LIMIT, \
790 .ar_bytes = GUEST_##seg##_AR_BYTES, \
791 }
792
772e0318 793static const struct kvm_vmx_segment_field {
6aa8b732
AK		 794 unsigned selector;
795 unsigned base;
796 unsigned limit;
797 unsigned ar_bytes;
798} kvm_vmx_segment_fields[] = {
799 VMX_SEGMENT_FIELD(CS),
800 VMX_SEGMENT_FIELD(DS),
801 VMX_SEGMENT_FIELD(ES),
802 VMX_SEGMENT_FIELD(FS),
803 VMX_SEGMENT_FIELD(GS),
804 VMX_SEGMENT_FIELD(SS),
805 VMX_SEGMENT_FIELD(TR),
806 VMX_SEGMENT_FIELD(LDTR),
807};
808
26bb0981
AK		 809static u64 host_efer;
810
6de4f3ad
AK		 811static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
812
4d56c8a7 813/*
8c06585d 814 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 815 * away by decrementing the array size.
816 */
6aa8b732 817static const u32 vmx_msr_index[] = {
05b3e0c2 818#ifdef CONFIG_X86_64
44ea2b17 819 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 820#endif
8c06585d 821 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 822};
9d8f549d 823#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 824
31299944 825static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 826{
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
828 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 829 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 830}
831
31299944 832static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 833{
834 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
835 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 836 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 837}
838
31299944 839static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 843 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 844}
845
31299944 846static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 847{
848 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
849 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
850}
851
31299944 852static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 853{
854 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
855 INTR_INFO_VALID_MASK)) ==
856 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
857}
858
31299944 859static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 860{
04547156 861 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 862}
863
31299944 864static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 865{
04547156 866 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 867}
868
31299944 869static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 870{
04547156 871 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 872}
873
31299944 874static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 875{
04547156
SY		 876 return vmcs_config.cpu_based_exec_ctrl &
877 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 878}
879
774ead3a 880static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 881{
04547156
SY		 882 return vmcs_config.cpu_based_2nd_exec_ctrl &
883 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
884}
885
8d14695f
YZ		 886static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
887{
888 return vmcs_config.cpu_based_2nd_exec_ctrl &
889 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
890}
891
83d4c286
YZ		 892static inline bool cpu_has_vmx_apic_register_virt(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_APIC_REGISTER_VIRT;
896}
897
c7c9c56c
YZ		 898static inline bool cpu_has_vmx_virtual_intr_delivery(void)
899{
900 return vmcs_config.cpu_based_2nd_exec_ctrl &
901 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
902}
903
01e439be
YZ		 904static inline bool cpu_has_vmx_posted_intr(void)
905{
906 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
907}
908
909static inline bool cpu_has_vmx_apicv(void)
910{
911 return cpu_has_vmx_apic_register_virt() &&
912 cpu_has_vmx_virtual_intr_delivery() &&
913 cpu_has_vmx_posted_intr();
914}
915
04547156
SY		 916static inline bool cpu_has_vmx_flexpriority(void)
917{
918 return cpu_has_vmx_tpr_shadow() &&
919 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 920}
921
e799794e
MT		 922static inline bool cpu_has_vmx_ept_execute_only(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 925}
926
927static inline bool cpu_has_vmx_eptp_uncacheable(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 930}
931
932static inline bool cpu_has_vmx_eptp_writeback(void)
933{
31299944 934 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 935}
936
937static inline bool cpu_has_vmx_ept_2m_page(void)
938{
31299944 939 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 940}
941
878403b7
SY		 942static inline bool cpu_has_vmx_ept_1g_page(void)
943{
31299944 944 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 945}
946
4bc9b982
SY		 947static inline bool cpu_has_vmx_ept_4levels(void)
948{
949 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
950}
951
83c3a331
XH		 952static inline bool cpu_has_vmx_ept_ad_bits(void)
953{
954 return vmx_capability.ept & VMX_EPT_AD_BIT;
955}
956
31299944 957static inline bool cpu_has_vmx_invept_context(void)
d56f546d 958{
31299944 959 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 960}
961
31299944 962static inline bool cpu_has_vmx_invept_global(void)
d56f546d 963{
31299944 964 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 965}
966
518c8aee
GJ		 967static inline bool cpu_has_vmx_invvpid_single(void)
968{
969 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
970}
971
b9d762fa
GJ		 972static inline bool cpu_has_vmx_invvpid_global(void)
973{
974 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
975}
976
31299944 977static inline bool cpu_has_vmx_ept(void)
d56f546d 978{
04547156
SY		 979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 981}
982
31299944 983static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 984{
985 return vmcs_config.cpu_based_2nd_exec_ctrl &
986 SECONDARY_EXEC_UNRESTRICTED_GUEST;
987}
988
31299944 989static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 990{
991 return vmcs_config.cpu_based_2nd_exec_ctrl &
992 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
993}
994
31299944 995static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 996{
6d3e435e 997 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 998}
999
31299944 1000static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1001{
04547156
SY		 1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1004}
1005
31299944 1006static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1007{
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_RDTSCP;
1010}
1011
ad756a16
MJ		 1012static inline bool cpu_has_vmx_invpcid(void)
1013{
1014 return vmcs_config.cpu_based_2nd_exec_ctrl &
1015 SECONDARY_EXEC_ENABLE_INVPCID;
1016}
1017
31299944 1018static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1019{
1020 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021}
1022
f5f48ee1
SY		 1023static inline bool cpu_has_vmx_wbinvd_exit(void)
1024{
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_WBINVD_EXITING;
1027}
1028
abc4fc58
AG		 1029static inline bool cpu_has_vmx_shadow_vmcs(void)
1030{
1031 u64 vmx_msr;
1032 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033 /* check if the cpu supports writing r/o exit information fields */
1034 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035 return false;
1036
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_SHADOW_VMCS;
1039}
1040
04547156
SY		 1041static inline bool report_flexpriority(void)
1042{
1043 return flexpriority_enabled;
1044}
1045
fe3ef05c
NHE		 1046static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047{
1048 return vmcs12->cpu_based_vm_exec_control & bit;
1049}
1050
1051static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052{
1053 return (vmcs12->cpu_based_vm_exec_control &
1054 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055 (vmcs12->secondary_vm_exec_control & bit);
1056}
1057
f5c4368f 1058static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1059{
1060 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061}
1062
f4124500
JK		 1063static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064{
1065 return vmcs12->pin_based_vm_exec_control &
1066 PIN_BASED_VMX_PREEMPTION_TIMER;
1067}
1068
155a97a3
NHE		 1069static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070{
1071 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072}
1073
644d711a
NHE		 1074static inline bool is_exception(u32 intr_info)
1075{
1076 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078}
1079
533558bc
JK		 1080static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081 u32 exit_intr_info,
1082 unsigned long exit_qualification);
7c177938
NHE		 1083static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084 struct vmcs12 *vmcs12,
1085 u32 reason, unsigned long qualification);
1086
8b9cf98c 1087static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1088{
1089 int i;
1090
a2fa3e9f 1091 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1092 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1093 return i;
1094 return -1;
1095}
1096
2384d2b3
SY		 1097static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098{
1099 struct {
1100 u64 vpid : 16;
1101 u64 rsvd : 48;
1102 u64 gva;
1103 } operand = { vpid, 0, gva };
1104
4ecac3fd 1105 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1106 /* CF==1 or ZF==1 --> rc = -1 */
1107 "; ja 1f ; ud2 ; 1:"
1108 : : "a"(&operand), "c"(ext) : "cc", "memory");
1109}
1110
1439442c
SY		 1111static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112{
1113 struct {
1114 u64 eptp, gpa;
1115 } operand = {eptp, gpa};
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1118 /* CF==1 or ZF==1 --> rc = -1 */
1119 "; ja 1f ; ud2 ; 1:\n"
1120 : : "a" (&operand), "c" (ext) : "cc", "memory");
1121}
1122
26bb0981 1123static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1124{
1125 int i;
1126
8b9cf98c 1127 i = __find_msr_index(vmx, msr);
a75beee6 1128 if (i >= 0)
a2fa3e9f 1129 return &vmx->guest_msrs[i];
8b6d44c7 1130 return NULL;
7725f0ba
AK		 1131}
1132
6aa8b732
AK		 1133static void vmcs_clear(struct vmcs *vmcs)
1134{
1135 u64 phys_addr = __pa(vmcs);
1136 u8 error;
1137
4ecac3fd 1138 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1139 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1140 : "cc", "memory");
1141 if (error)
1142 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143 vmcs, phys_addr);
1144}
1145
d462b819
NHE		 1146static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147{
1148 vmcs_clear(loaded_vmcs->vmcs);
1149 loaded_vmcs->cpu = -1;
1150 loaded_vmcs->launched = 0;
1151}
1152
7725b894
DX		 1153static void vmcs_load(struct vmcs *vmcs)
1154{
1155 u64 phys_addr = __pa(vmcs);
1156 u8 error;
1157
1158 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1159 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1160 : "cc", "memory");
1161 if (error)
2844d849 1162 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1163 vmcs, phys_addr);
1164}
1165
8f536b76
ZY		 1166#ifdef CONFIG_KEXEC
1167/*
1168 * This bitmap is used to indicate whether the vmclear
1169 * operation is enabled on all cpus. All disabled by
1170 * default.
1171 */
1172static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174static inline void crash_enable_local_vmclear(int cpu)
1175{
1176 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177}
1178
1179static inline void crash_disable_local_vmclear(int cpu)
1180{
1181 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182}
1183
1184static inline int crash_local_vmclear_enabled(int cpu)
1185{
1186 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187}
1188
1189static void crash_vmclear_local_loaded_vmcss(void)
1190{
1191 int cpu = raw_smp_processor_id();
1192 struct loaded_vmcs *v;
1193
1194 if (!crash_local_vmclear_enabled(cpu))
1195 return;
1196
1197 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198 loaded_vmcss_on_cpu_link)
1199 vmcs_clear(v->vmcs);
1200}
1201#else
1202static inline void crash_enable_local_vmclear(int cpu) { }
1203static inline void crash_disable_local_vmclear(int cpu) { }
1204#endif /* CONFIG_KEXEC */
1205
d462b819 1206static void __loaded_vmcs_clear(void *arg)
6aa8b732 1207{
d462b819 1208 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1209 int cpu = raw_smp_processor_id();
6aa8b732 1210
d462b819
NHE		 1211 if (loaded_vmcs->cpu != cpu)
1212 return; /* vcpu migration can race with cpu offline */
1213 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1214 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1215 crash_disable_local_vmclear(cpu);
d462b819 1216 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1217
1218 /*
1219 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220 * is before setting loaded_vmcs->vcpu to -1 which is done in
1221 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222 * then adds the vmcs into percpu list before it is deleted.
1223 */
1224 smp_wmb();
1225
d462b819 1226 loaded_vmcs_init(loaded_vmcs);
8f536b76 1227 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1228}
1229
d462b819 1230static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1231{
e6c7d321
XG		 1232 int cpu = loaded_vmcs->cpu;
1233
1234 if (cpu != -1)
1235 smp_call_function_single(cpu,
1236 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1237}
1238
1760dd49 1239static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1240{
1241 if (vmx->vpid == 0)
1242 return;
1243
518c8aee
GJ		 1244 if (cpu_has_vmx_invvpid_single())
1245 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1246}
1247
b9d762fa
GJ		 1248static inline void vpid_sync_vcpu_global(void)
1249{
1250 if (cpu_has_vmx_invvpid_global())
1251 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252}
1253
1254static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255{
1256 if (cpu_has_vmx_invvpid_single())
1760dd49 1257 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1258 else
1259 vpid_sync_vcpu_global();
1260}
1261
1439442c
SY		 1262static inline void ept_sync_global(void)
1263{
1264 if (cpu_has_vmx_invept_global())
1265 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266}
1267
1268static inline void ept_sync_context(u64 eptp)
1269{
089d034e 1270 if (enable_ept) {
1439442c
SY		 1271 if (cpu_has_vmx_invept_context())
1272 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273 else
1274 ept_sync_global();
1275 }
1276}
1277
96304217 1278static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1279{
5e520e62 1280 unsigned long value;
6aa8b732 1281
5e520e62
AK		 1282 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1284 return value;
1285}
1286
96304217 1287static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1288{
1289 return vmcs_readl(field);
1290}
1291
96304217 1292static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1293{
1294 return vmcs_readl(field);
1295}
1296
96304217 1297static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1298{
05b3e0c2 1299#ifdef CONFIG_X86_64
6aa8b732
AK		 1300 return vmcs_readl(field);
1301#else
1302 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303#endif
1304}
1305
e52de1b8
AK		 1306static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307{
1308 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310 dump_stack();
1311}
1312
6aa8b732
AK		 1313static void vmcs_writel(unsigned long field, unsigned long value)
1314{
1315 u8 error;
1316
4ecac3fd 1317 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1318 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1319 if (unlikely(error))
1320 vmwrite_error(field, value);
6aa8b732
AK		 1321}
1322
1323static void vmcs_write16(unsigned long field, u16 value)
1324{
1325 vmcs_writel(field, value);
1326}
1327
1328static void vmcs_write32(unsigned long field, u32 value)
1329{
1330 vmcs_writel(field, value);
1331}
1332
1333static void vmcs_write64(unsigned long field, u64 value)
1334{
6aa8b732 1335 vmcs_writel(field, value);
7682f2d0 1336#ifndef CONFIG_X86_64
6aa8b732
AK		 1337 asm volatile ("");
1338 vmcs_writel(field+1, value >> 32);
1339#endif
1340}
1341
2ab455cc
AL		 1342static void vmcs_clear_bits(unsigned long field, u32 mask)
1343{
1344 vmcs_writel(field, vmcs_readl(field) & ~mask);
1345}
1346
1347static void vmcs_set_bits(unsigned long field, u32 mask)
1348{
1349 vmcs_writel(field, vmcs_readl(field) | mask);
1350}
1351
2961e876
GN		 1352static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353{
1354 vmcs_write32(VM_ENTRY_CONTROLS, val);
1355 vmx->vm_entry_controls_shadow = val;
1356}
1357
1358static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359{
1360 if (vmx->vm_entry_controls_shadow != val)
1361 vm_entry_controls_init(vmx, val);
1362}
1363
1364static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365{
1366 return vmx->vm_entry_controls_shadow;
1367}
1368
1369
1370static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371{
1372 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373}
1374
1375static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376{
1377 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378}
1379
1380static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381{
1382 vmcs_write32(VM_EXIT_CONTROLS, val);
1383 vmx->vm_exit_controls_shadow = val;
1384}
1385
1386static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387{
1388 if (vmx->vm_exit_controls_shadow != val)
1389 vm_exit_controls_init(vmx, val);
1390}
1391
1392static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393{
1394 return vmx->vm_exit_controls_shadow;
1395}
1396
1397
1398static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399{
1400 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401}
1402
1403static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404{
1405 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406}
1407
2fb92db1
AK		 1408static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409{
1410 vmx->segment_cache.bitmask = 0;
1411}
1412
1413static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414 unsigned field)
1415{
1416 bool ret;
1417 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421 vmx->segment_cache.bitmask = 0;
1422 }
1423 ret = vmx->segment_cache.bitmask & mask;
1424 vmx->segment_cache.bitmask |= mask;
1425 return ret;
1426}
1427
1428static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429{
1430 u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434 return *p;
1435}
1436
1437static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438{
1439 ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443 return *p;
1444}
1445
1446static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447{
1448 u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452 return *p;
1453}
1454
1455static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456{
1457 u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461 return *p;
1462}
1463
abd3f2d6
AK		 1464static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465{
1466 u32 eb;
1467
fd7373cc
JK		 1468 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470 if ((vcpu->guest_debug &
1471 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473 eb |= 1u << BP_VECTOR;
7ffd92c5 1474 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1475 eb = ~0;
089d034e 1476 if (enable_ept)
1439442c 1477 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1478 if (vcpu->fpu_active)
1479 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1480
1481 /* When we are running a nested L2 guest and L1 specified for it a
1482 * certain exception bitmap, we must trap the same exceptions and pass
1483 * them to L1. When running L2, we will only handle the exceptions
1484 * specified above if L1 did not want them.
1485 */
1486 if (is_guest_mode(vcpu))
1487 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
abd3f2d6
AK		 1489 vmcs_write32(EXCEPTION_BITMAP, eb);
1490}
1491
2961e876
GN		 1492static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493 unsigned long entry, unsigned long exit)
8bf00a52 1494{
2961e876
GN		 1495 vm_entry_controls_clearbit(vmx, entry);
1496 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1497}
1498
61d2ef2c
AK		 1499static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500{
1501 unsigned i;
1502 struct msr_autoload *m = &vmx->msr_autoload;
1503
8bf00a52
GN		 1504 switch (msr) {
1505 case MSR_EFER:
1506 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1507 clear_atomic_switch_msr_special(vmx,
1508 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1509 VM_EXIT_LOAD_IA32_EFER);
1510 return;
1511 }
1512 break;
1513 case MSR_CORE_PERF_GLOBAL_CTRL:
1514 if (cpu_has_load_perf_global_ctrl) {
2961e876 1515 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1516 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518 return;
1519 }
1520 break;
110312c8
AK		 1521 }
1522
61d2ef2c
AK		 1523 for (i = 0; i < m->nr; ++i)
1524 if (m->guest[i].index == msr)
1525 break;
1526
1527 if (i == m->nr)
1528 return;
1529 --m->nr;
1530 m->guest[i] = m->guest[m->nr];
1531 m->host[i] = m->host[m->nr];
1532 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534}
1535
2961e876
GN		 1536static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537 unsigned long entry, unsigned long exit,
1538 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539 u64 guest_val, u64 host_val)
8bf00a52
GN		 1540{
1541 vmcs_write64(guest_val_vmcs, guest_val);
1542 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1543 vm_entry_controls_setbit(vmx, entry);
1544 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1545}
1546
61d2ef2c
AK		 1547static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548 u64 guest_val, u64 host_val)
1549{
1550 unsigned i;
1551 struct msr_autoload *m = &vmx->msr_autoload;
1552
8bf00a52
GN		 1553 switch (msr) {
1554 case MSR_EFER:
1555 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1556 add_atomic_switch_msr_special(vmx,
1557 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1558 VM_EXIT_LOAD_IA32_EFER,
1559 GUEST_IA32_EFER,
1560 HOST_IA32_EFER,
1561 guest_val, host_val);
1562 return;
1563 }
1564 break;
1565 case MSR_CORE_PERF_GLOBAL_CTRL:
1566 if (cpu_has_load_perf_global_ctrl) {
2961e876 1567 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1568 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570 GUEST_IA32_PERF_GLOBAL_CTRL,
1571 HOST_IA32_PERF_GLOBAL_CTRL,
1572 guest_val, host_val);
1573 return;
1574 }
1575 break;
110312c8
AK		 1576 }
1577
61d2ef2c
AK		 1578 for (i = 0; i < m->nr; ++i)
1579 if (m->guest[i].index == msr)
1580 break;
1581
e7fc6f93 1582 if (i == NR_AUTOLOAD_MSRS) {
60266204 1583 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1584 "Can't add msr %x\n", msr);
1585 return;
1586 } else if (i == m->nr) {
61d2ef2c
AK		 1587 ++m->nr;
1588 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590 }
1591
1592 m->guest[i].index = msr;
1593 m->guest[i].value = guest_val;
1594 m->host[i].index = msr;
1595 m->host[i].value = host_val;
1596}
1597
33ed6329
AK		 1598static void reload_tss(void)
1599{
33ed6329
AK		 1600 /*
1601 * VT restores TR but not its size. Useless.
1602 */
d359192f 1603 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1604 struct desc_struct *descs;
33ed6329 1605
d359192f 1606 descs = (void *)gdt->address;
33ed6329
AK		 1607 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608 load_TR_desc();
33ed6329
AK		 1609}
1610
92c0d900 1611static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1612{
3a34a881 1613 u64 guest_efer;
51c6cf66
AK		 1614 u64 ignore_bits;
1615
f6801dff 1616 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1617
51c6cf66 1618 /*
0fa06071 1619 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1620 * outside long mode
1621 */
1622 ignore_bits = EFER_NX | EFER_SCE;
1623#ifdef CONFIG_X86_64
1624 ignore_bits |= EFER_LMA | EFER_LME;
1625 /* SCE is meaningful only in long mode on Intel */
1626 if (guest_efer & EFER_LMA)
1627 ignore_bits &= ~(u64)EFER_SCE;
1628#endif
51c6cf66
AK		 1629 guest_efer &= ~ignore_bits;
1630 guest_efer |= host_efer & ignore_bits;
26bb0981 1631 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1632 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1633
1634 clear_atomic_switch_msr(vmx, MSR_EFER);
1635 /* On ept, can't emulate nx, and must switch nx atomically */
1636 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637 guest_efer = vmx->vcpu.arch.efer;
1638 if (!(guest_efer & EFER_LMA))
1639 guest_efer &= ~EFER_LME;
1640 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641 return false;
1642 }
1643
26bb0981 1644 return true;
51c6cf66
AK		 1645}
1646
2d49ec72
GN		 1647static unsigned long segment_base(u16 selector)
1648{
d359192f 1649 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1650 struct desc_struct *d;
1651 unsigned long table_base;
1652 unsigned long v;
1653
1654 if (!(selector & ~3))
1655 return 0;
1656
d359192f 1657 table_base = gdt->address;
2d49ec72
GN		 1658
1659 if (selector & 4) { /* from ldt */
1660 u16 ldt_selector = kvm_read_ldt();
1661
1662 if (!(ldt_selector & ~3))
1663 return 0;
1664
1665 table_base = segment_base(ldt_selector);
1666 }
1667 d = (struct desc_struct *)(table_base + (selector & ~7));
1668 v = get_desc_base(d);
1669#ifdef CONFIG_X86_64
1670 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672#endif
1673 return v;
1674}
1675
1676static inline unsigned long kvm_read_tr_base(void)
1677{
1678 u16 tr;
1679 asm("str %0" : "=g"(tr));
1680 return segment_base(tr);
1681}
1682
04d2cc77 1683static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1684{
04d2cc77 1685 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1686 int i;
04d2cc77 1687
a2fa3e9f 1688 if (vmx->host_state.loaded)
33ed6329
AK		 1689 return;
1690
a2fa3e9f 1691 vmx->host_state.loaded = 1;
33ed6329
AK		 1692 /*
1693 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1694 * allow segment selectors with cpl > 0 or ti == 1.
1695 */
d6e88aec 1696 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1697 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1698 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1699 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1700 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1701 vmx->host_state.fs_reload_needed = 0;
1702 } else {
33ed6329 1703 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1704 vmx->host_state.fs_reload_needed = 1;
33ed6329 1705 }
9581d442 1706 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1707 if (!(vmx->host_state.gs_sel & 7))
1708 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1709 else {
1710 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1711 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1712 }
1713
b2da15ac
AK		 1714#ifdef CONFIG_X86_64
1715 savesegment(ds, vmx->host_state.ds_sel);
1716 savesegment(es, vmx->host_state.es_sel);
1717#endif
1718
33ed6329
AK		 1719#ifdef CONFIG_X86_64
1720 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722#else
a2fa3e9f
GH		 1723 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1725#endif
707c0874
AK		 1726
1727#ifdef CONFIG_X86_64
c8770e7b
AK		 1728 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729 if (is_long_mode(&vmx->vcpu))
44ea2b17 1730 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1731#endif
da8999d3
LJ		 1732 if (boot_cpu_has(X86_FEATURE_MPX))
1733 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1734 for (i = 0; i < vmx->save_nmsrs; ++i)
1735 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1736 vmx->guest_msrs[i].data,
1737 vmx->guest_msrs[i].mask);
33ed6329
AK		 1738}
1739
a9b21b62 1740static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1741{
a2fa3e9f 1742 if (!vmx->host_state.loaded)
33ed6329
AK		 1743 return;
1744
e1beb1d3 1745 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1746 vmx->host_state.loaded = 0;
c8770e7b
AK		 1747#ifdef CONFIG_X86_64
1748 if (is_long_mode(&vmx->vcpu))
1749 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750#endif
152d3f2f 1751 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1752 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1753#ifdef CONFIG_X86_64
9581d442 1754 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1755#else
1756 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1757#endif
33ed6329 1758 }
0a77fe4c
AK		 1759 if (vmx->host_state.fs_reload_needed)
1760 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1761#ifdef CONFIG_X86_64
1762 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763 loadsegment(ds, vmx->host_state.ds_sel);
1764 loadsegment(es, vmx->host_state.es_sel);
1765 }
b2da15ac 1766#endif
152d3f2f 1767 reload_tss();
44ea2b17 1768#ifdef CONFIG_X86_64
c8770e7b 1769 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1770#endif
da8999d3
LJ		 1771 if (vmx->host_state.msr_host_bndcfgs)
1772 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1773 /*
1774 * If the FPU is not active (through the host task or
1775 * the guest vcpu), then restore the cr0.TS bit.
1776 */
1777 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778 stts();
3444d7da 1779 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1780}
1781
a9b21b62
AK		 1782static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783{
1784 preempt_disable();
1785 __vmx_load_host_state(vmx);
1786 preempt_enable();
1787}
1788
6aa8b732
AK		 1789/*
1790 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791 * vcpu mutex is already taken.
1792 */
15ad7146 1793static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1794{
a2fa3e9f 1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1796 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1797
4610c9cc
DX		 1798 if (!vmm_exclusive)
1799 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1800 else if (vmx->loaded_vmcs->cpu != cpu)
1801 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1802
d462b819
NHE		 1803 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1806 }
1807
d462b819 1808 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1809 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1810 unsigned long sysenter_esp;
1811
a8eeb04a 1812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1813 local_irq_disable();
8f536b76 1814 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1815
1816 /*
1817 * Read loaded_vmcs->cpu should be before fetching
1818 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819 * See the comments in __loaded_vmcs_clear().
1820 */
1821 smp_rmb();
1822
d462b819
NHE		 1823 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1825 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1826 local_irq_enable();
1827
6aa8b732
AK		 1828 /*
1829 * Linux uses per-cpu TSS and GDT, so set these when switching
1830 * processors.
1831 */
d6e88aec 1832 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1833 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1834
1835 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1837 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1838 }
6aa8b732
AK		 1839}
1840
1841static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842{
a9b21b62 1843 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1844 if (!vmm_exclusive) {
d462b819
NHE		 1845 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846 vcpu->cpu = -1;
4610c9cc
DX		 1847 kvm_cpu_vmxoff();
1848 }
6aa8b732
AK		 1849}
1850
5fd86fcf
AK		 1851static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852{
81231c69
AK		 1853 ulong cr0;
1854
5fd86fcf
AK		 1855 if (vcpu->fpu_active)
1856 return;
1857 vcpu->fpu_active = 1;
81231c69
AK		 1858 cr0 = vmcs_readl(GUEST_CR0);
1859 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1862 update_exception_bitmap(vcpu);
edcafe3c 1863 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1864 if (is_guest_mode(vcpu))
1865 vcpu->arch.cr0_guest_owned_bits &=
1866 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1867 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1868}
1869
edcafe3c
AK		 1870static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
fe3ef05c
NHE		 1872/*
1873 * Return the cr0 value that a nested guest would read. This is a combination
1874 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875 * its hypervisor (cr0_read_shadow).
1876 */
1877static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878{
1879 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881}
1882static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883{
1884 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886}
1887
5fd86fcf
AK		 1888static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889{
36cf24e0
NHE		 1890 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891 * set this *before* calling this function.
1892 */
edcafe3c 1893 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1894 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1895 update_exception_bitmap(vcpu);
edcafe3c
AK		 1896 vcpu->arch.cr0_guest_owned_bits = 0;
1897 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1898 if (is_guest_mode(vcpu)) {
1899 /*
1900 * L1's specified read shadow might not contain the TS bit,
1901 * so now that we turned on shadowing of this bit, we need to
1902 * set this bit of the shadow. Like in nested_vmx_run we need
1903 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904 * up-to-date here because we just decached cr0.TS (and we'll
1905 * only update vmcs12->guest_cr0 on nested exit).
1906 */
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909 (vcpu->arch.cr0 & X86_CR0_TS);
1910 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911 } else
1912 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1913}
1914
6aa8b732
AK		 1915static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916{
78ac8b47 1917 unsigned long rflags, save_rflags;
345dcaa8 1918
6de12732
AK		 1919 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921 rflags = vmcs_readl(GUEST_RFLAGS);
1922 if (to_vmx(vcpu)->rmode.vm86_active) {
1923 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926 }
1927 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1928 }
6de12732 1929 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1930}
1931
1932static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933{
6de12732
AK		 1934 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1936 if (to_vmx(vcpu)->rmode.vm86_active) {
1937 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1938 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1939 }
6aa8b732
AK		 1940 vmcs_writel(GUEST_RFLAGS, rflags);
1941}
1942
2809f5d2
GC		 1943static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944{
1945 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946 int ret = 0;
1947
1948 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1949 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1950 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1951 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1952
1953 return ret & mask;
1954}
1955
1956static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957{
1958 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959 u32 interruptibility = interruptibility_old;
1960
1961 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
48005f64 1963 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1964 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1965 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1966 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968 if ((interruptibility != interruptibility_old))
1969 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970}
1971
6aa8b732
AK		 1972static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973{
1974 unsigned long rip;
6aa8b732 1975
5fdbf976 1976 rip = kvm_rip_read(vcpu);
6aa8b732 1977 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1978 kvm_rip_write(vcpu, rip);
6aa8b732 1979
2809f5d2
GC		 1980 /* skipping an emulated instruction also counts */
1981 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1982}
1983
0b6ac343
NHE		 1984/*
1985 * KVM wants to inject page-faults which it got to the guest. This function
1986 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1987 */
e011c663 1988static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1989{
1990 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
e011c663 1992 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1993 return 0;
1994
533558bc
JK		 1995 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996 vmcs_read32(VM_EXIT_INTR_INFO),
1997 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1998 return 1;
1999}
2000
298101da 2001static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2002 bool has_error_code, u32 error_code,
2003 bool reinject)
298101da 2004{
77ab6db0 2005 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2006 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2007
e011c663
GN		 2008 if (!reinject && is_guest_mode(vcpu) &&
2009 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2010 return;
2011
8ab2d2e2 2012 if (has_error_code) {
77ab6db0 2013 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2014 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015 }
77ab6db0 2016
7ffd92c5 2017 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2018 int inc_eip = 0;
2019 if (kvm_exception_is_soft(nr))
2020 inc_eip = vcpu->arch.event_exit_inst_len;
2021 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2023 return;
2024 }
2025
66fd3f7f
GN		 2026 if (kvm_exception_is_soft(nr)) {
2027 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2029 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030 } else
2031 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2034}
2035
4e47c7a6
SY		 2036static bool vmx_rdtscp_supported(void)
2037{
2038 return cpu_has_vmx_rdtscp();
2039}
2040
ad756a16
MJ		 2041static bool vmx_invpcid_supported(void)
2042{
2043 return cpu_has_vmx_invpcid() && enable_ept;
2044}
2045
a75beee6
ED		 2046/*
2047 * Swap MSR entry in host/guest MSR entry array.
2048 */
8b9cf98c 2049static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2050{
26bb0981 2051 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2052
2053 tmp = vmx->guest_msrs[to];
2054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2056}
2057
8d14695f
YZ		 2058static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059{
2060 unsigned long *msr_bitmap;
2061
2062 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063 if (is_long_mode(vcpu))
2064 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065 else
2066 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067 } else {
2068 if (is_long_mode(vcpu))
2069 msr_bitmap = vmx_msr_bitmap_longmode;
2070 else
2071 msr_bitmap = vmx_msr_bitmap_legacy;
2072 }
2073
2074 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075}
2076
e38aea3e
AK		 2077/*
2078 * Set up the vmcs to automatically save and restore system
2079 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2080 * mode, as fiddling with msrs is very expensive.
2081 */
8b9cf98c 2082static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2083{
26bb0981 2084 int save_nmsrs, index;
e38aea3e 2085
a75beee6
ED		 2086 save_nmsrs = 0;
2087#ifdef CONFIG_X86_64
8b9cf98c 2088 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2089 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2090 if (index >= 0)
8b9cf98c
RR		 2091 move_msr_up(vmx, index, save_nmsrs++);
2092 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2093 if (index >= 0)
8b9cf98c
RR		 2094 move_msr_up(vmx, index, save_nmsrs++);
2095 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2096 if (index >= 0)
8b9cf98c 2097 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2098 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099 if (index >= 0 && vmx->rdtscp_enabled)
2100 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2101 /*
8c06585d 2102 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2103 * if efer.sce is enabled.
2104 */
8c06585d 2105 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2106 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2107 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2108 }
2109#endif
92c0d900
AK		 2110 index = __find_msr_index(vmx, MSR_EFER);
2111 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2112 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2113
26bb0981 2114 vmx->save_nmsrs = save_nmsrs;
5897297b 2115
8d14695f
YZ		 2116 if (cpu_has_vmx_msr_bitmap())
2117 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2118}
2119
6aa8b732
AK		 2120/*
2121 * reads and returns guest's timestamp counter "register"
2122 * guest_tsc = host_tsc + tsc_offset -- 21.3
2123 */
2124static u64 guest_read_tsc(void)
2125{
2126 u64 host_tsc, tsc_offset;
2127
2128 rdtscll(host_tsc);
2129 tsc_offset = vmcs_read64(TSC_OFFSET);
2130 return host_tsc + tsc_offset;
2131}
2132
d5c1785d
NHE		 2133/*
2134 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135 * counter, even if a nested guest (L2) is currently running.
2136 */
886b470c 2137u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2138{
886b470c 2139 u64 tsc_offset;
d5c1785d 2140
d5c1785d
NHE		 2141 tsc_offset = is_guest_mode(vcpu) ?
2142 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143 vmcs_read64(TSC_OFFSET);
2144 return host_tsc + tsc_offset;
2145}
2146
4051b188 2147/*
cc578287
ZA		 2148 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2149 * software catchup for faster rates on slower CPUs.
4051b188 2150 */
cc578287 2151static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2152{
cc578287
ZA		 2153 if (!scale)
2154 return;
2155
2156 if (user_tsc_khz > tsc_khz) {
2157 vcpu->arch.tsc_catchup = 1;
2158 vcpu->arch.tsc_always_catchup = 1;
2159 } else
2160 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2161}
2162
ba904635
WA		 2163static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164{
2165 return vmcs_read64(TSC_OFFSET);
2166}
2167
6aa8b732 2168/*
99e3e30a 2169 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2170 */
99e3e30a 2171static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2172{
27fc51b2 2173 if (is_guest_mode(vcpu)) {
7991825b 2174 /*
27fc51b2
NHE		 2175 * We're here if L1 chose not to trap WRMSR to TSC. According
2176 * to the spec, this should set L1's TSC; The offset that L1
2177 * set for L2 remains unchanged, and still needs to be added
2178 * to the newly set TSC to get L2's TSC.
7991825b 2179 */
27fc51b2
NHE		 2180 struct vmcs12 *vmcs12;
2181 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182 /* recalculate vmcs02.TSC_OFFSET: */
2183 vmcs12 = get_vmcs12(vcpu);
2184 vmcs_write64(TSC_OFFSET, offset +
2185 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186 vmcs12->tsc_offset : 0));
2187 } else {
489223ed
YY		 2188 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2190 vmcs_write64(TSC_OFFSET, offset);
2191 }
6aa8b732
AK		 2192}
2193
f1e2b260 2194static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2195{
2196 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2197
e48672fa 2198 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2199 if (is_guest_mode(vcpu)) {
2200 /* Even when running L2, the adjustment needs to apply to L1 */
2201 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2202 } else
2203 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204 offset + adjustment);
e48672fa
ZA		 2205}
2206
857e4099
JR		 2207static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208{
2209 return target_tsc - native_read_tsc();
2210}
2211
801d3424
NHE		 2212static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213{
2214 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216}
2217
2218/*
2219 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221 * all guests if the "nested" module option is off, and can also be disabled
2222 * for a single guest by disabling its VMX cpuid bit.
2223 */
2224static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225{
2226 return nested && guest_cpuid_has_vmx(vcpu);
2227}
2228
b87a51ae
NHE		 2229/*
2230 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231 * returned for the various VMX controls MSRs when nested VMX is enabled.
2232 * The same values should also be used to verify that vmcs12 control fields are
2233 * valid during nested entry from L1 to L2.
2234 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236 * bit in the high half is on if the corresponding bit in the control field
2237 * may be on. See also vmx_control_verify().
2238 * TODO: allow these variables to be modified (downgraded) by module options
2239 * or other means.
2240 */
2241static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2242static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2243static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2244static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2245static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2246static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2247static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2248static __init void nested_vmx_setup_ctls_msrs(void)
2249{
2250 /*
2251 * Note that as a general rule, the high half of the MSRs (bits in
2252 * the control fields which may be 1) should be initialized by the
2253 * intersection of the underlying hardware's MSR (i.e., features which
2254 * can be supported) and the list of features we want to expose -
2255 * because they are known to be properly supported in our code.
2256 * Also, usually, the low half of the MSRs (bits which must be 1) can
2257 * be set to 0, meaning that L1 may turn off any of these bits. The
2258 * reason is that if one of these bits is necessary, it will appear
2259 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260 * fields of vmcs01 and vmcs02, will turn these bits off - and
2261 * nested_vmx_exit_handled() will not pass related exits to L1.
2262 * These rules have exceptions below.
2263 */
2264
2265 /* pin-based controls */
eabeaacc
JK		 2266 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2267 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2268 /*
2269 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2271 */
eabeaacc
JK		 2272 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2273 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2274 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2275 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2276 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2277
33fb20c3
JK		 2278 /*
2279 * Exit controls
2280 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2281 * 17 must be 1.
2282 */
c0dfee58
ACL		 2283 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2285 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2286 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2287 nested_vmx_exit_ctls_high &=
b87a51ae 2288#ifdef CONFIG_X86_64
c0dfee58 2289 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2290#endif
f4124500
JK		 2291 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
7854cbca 2294 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
36be0b9d
PB		 2295 if (vmx_mpx_supported())
2296 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae
NHE		 2297
2298 /* entry controls */
2299 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2300 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2301 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2302 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2303 nested_vmx_entry_ctls_high &=
57435349
JK		 2304#ifdef CONFIG_X86_64
2305 VM_ENTRY_IA32E_MODE |
2306#endif
2307 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2308 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2309 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2310 if (vmx_mpx_supported())
2311 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2312
b87a51ae
NHE		 2313 /* cpu-based controls */
2314 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2315 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2316 nested_vmx_procbased_ctls_low = 0;
2317 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2318 CPU_BASED_VIRTUAL_INTR_PENDING |
2319 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2320 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2321 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2322 CPU_BASED_CR3_STORE_EXITING |
2323#ifdef CONFIG_X86_64
2324 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2325#endif
2326 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2327 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2328 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2329 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2330 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2331 /*
2332 * We can allow some features even when not supported by the
2333 * hardware. For example, L1 can specify an MSR bitmap - and we
2334 * can use it to avoid exits to L1 - even when L0 runs L2
2335 * without MSR bitmaps.
2336 */
2337 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2338
2339 /* secondary cpu-based controls */
2340 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2341 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2342 nested_vmx_secondary_ctls_low = 0;
2343 nested_vmx_secondary_ctls_high &=
d6851fbe 2344 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2345 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2346 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2347
afa61f75
NHE		 2348 if (enable_ept) {
2349 /* nested EPT: emulate EPT also to L1 */
2350 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2351 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2352 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2353 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2354 nested_vmx_ept_caps &= vmx_capability.ept;
2355 /*
2356 * Since invept is completely emulated we support both global
2357 * and context invalidation independent of what host cpu
2358 * supports
2359 */
2360 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2361 VMX_EPT_EXTENT_CONTEXT_BIT;
2362 } else
2363 nested_vmx_ept_caps = 0;
2364
c18911a2
JK		 2365 /* miscellaneous data */
2366 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2367 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2368 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2369 VMX_MISC_ACTIVITY_HLT;
c18911a2 2370 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2371}
2372
2373static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2374{
2375 /*
2376 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2377 */
2378 return ((control & high) | low) == control;
2379}
2380
2381static inline u64 vmx_control_msr(u32 low, u32 high)
2382{
2383 return low | ((u64)high << 32);
2384}
2385
cae50139 2386/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2387static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2388{
b87a51ae 2389 switch (msr_index) {
b87a51ae
NHE		 2390 case MSR_IA32_VMX_BASIC:
2391 /*
2392 * This MSR reports some information about VMX support. We
2393 * should return information about the VMX we emulate for the
2394 * guest, and the VMCS structure we give it - not about the
2395 * VMX support of the underlying hardware.
2396 */
2397 *pdata = VMCS12_REVISION |
2398 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2399 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2400 break;
2401 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2402 case MSR_IA32_VMX_PINBASED_CTLS:
2403 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2404 nested_vmx_pinbased_ctls_high);
2405 break;
2406 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2407 case MSR_IA32_VMX_PROCBASED_CTLS:
2408 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409 nested_vmx_procbased_ctls_high);
2410 break;
2411 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412 case MSR_IA32_VMX_EXIT_CTLS:
2413 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414 nested_vmx_exit_ctls_high);
2415 break;
2416 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417 case MSR_IA32_VMX_ENTRY_CTLS:
2418 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419 nested_vmx_entry_ctls_high);
2420 break;
2421 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2422 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423 nested_vmx_misc_high);
b87a51ae
NHE		 2424 break;
2425 /*
2426 * These MSRs specify bits which the guest must keep fixed (on or off)
2427 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428 * We picked the standard core2 setting.
2429 */
2430#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2432 case MSR_IA32_VMX_CR0_FIXED0:
2433 *pdata = VMXON_CR0_ALWAYSON;
2434 break;
2435 case MSR_IA32_VMX_CR0_FIXED1:
2436 *pdata = -1ULL;
2437 break;
2438 case MSR_IA32_VMX_CR4_FIXED0:
2439 *pdata = VMXON_CR4_ALWAYSON;
2440 break;
2441 case MSR_IA32_VMX_CR4_FIXED1:
2442 *pdata = -1ULL;
2443 break;
2444 case MSR_IA32_VMX_VMCS_ENUM:
2445 *pdata = 0x1f;
2446 break;
2447 case MSR_IA32_VMX_PROCBASED_CTLS2:
2448 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449 nested_vmx_secondary_ctls_high);
2450 break;
2451 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2452 /* Currently, no nested vpid support */
2453 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2454 break;
2455 default:
b87a51ae 2456 return 1;
b3897a49
NHE		 2457 }
2458
b87a51ae
NHE		 2459 return 0;
2460}
2461
6aa8b732
AK		 2462/*
2463 * Reads an msr value (of 'msr_index') into 'pdata'.
2464 * Returns 0 on success, non-0 otherwise.
2465 * Assumes vcpu_load() was already called.
2466 */
2467static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2468{
2469 u64 data;
26bb0981 2470 struct shared_msr_entry *msr;
6aa8b732
AK		 2471
2472 if (!pdata) {
2473 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2474 return -EINVAL;
2475 }
2476
2477 switch (msr_index) {
05b3e0c2 2478#ifdef CONFIG_X86_64
6aa8b732
AK		 2479 case MSR_FS_BASE:
2480 data = vmcs_readl(GUEST_FS_BASE);
2481 break;
2482 case MSR_GS_BASE:
2483 data = vmcs_readl(GUEST_GS_BASE);
2484 break;
44ea2b17
AK		 2485 case MSR_KERNEL_GS_BASE:
2486 vmx_load_host_state(to_vmx(vcpu));
2487 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2488 break;
26bb0981 2489#endif
6aa8b732 2490 case MSR_EFER:
3bab1f5d 2491 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2492 case MSR_IA32_TSC:
6aa8b732
AK		 2493 data = guest_read_tsc();
2494 break;
2495 case MSR_IA32_SYSENTER_CS:
2496 data = vmcs_read32(GUEST_SYSENTER_CS);
2497 break;
2498 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2499 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2500 break;
2501 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2502 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2503 break;
0dd376e7 2504 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2505 if (!vmx_mpx_supported())
2506 return 1;
0dd376e7
LJ		 2507 data = vmcs_read64(GUEST_BNDCFGS);
2508 break;
cae50139
JK		 2509 case MSR_IA32_FEATURE_CONTROL:
2510 if (!nested_vmx_allowed(vcpu))
2511 return 1;
2512 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2513 break;
2514 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515 if (!nested_vmx_allowed(vcpu))
2516 return 1;
2517 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2518 case MSR_TSC_AUX:
2519 if (!to_vmx(vcpu)->rdtscp_enabled)
2520 return 1;
2521 /* Otherwise falls through */
6aa8b732 2522 default:
8b9cf98c 2523 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2524 if (msr) {
2525 data = msr->data;
2526 break;
6aa8b732 2527 }
3bab1f5d 2528 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2529 }
2530
2531 *pdata = data;
2532 return 0;
2533}
2534
cae50139
JK		 2535static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2536
6aa8b732
AK		 2537/*
2538 * Writes msr value into into the appropriate "register".
2539 * Returns 0 on success, non-0 otherwise.
2540 * Assumes vcpu_load() was already called.
2541 */
8fe8ab46 2542static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2543{
a2fa3e9f 2544 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2545 struct shared_msr_entry *msr;
2cc51560 2546 int ret = 0;
8fe8ab46
WA		 2547 u32 msr_index = msr_info->index;
2548 u64 data = msr_info->data;
2cc51560 2549
6aa8b732 2550 switch (msr_index) {
3bab1f5d 2551 case MSR_EFER:
8fe8ab46 2552 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2553 break;
16175a79 2554#ifdef CONFIG_X86_64
6aa8b732 2555 case MSR_FS_BASE:
2fb92db1 2556 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2557 vmcs_writel(GUEST_FS_BASE, data);
2558 break;
2559 case MSR_GS_BASE:
2fb92db1 2560 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2561 vmcs_writel(GUEST_GS_BASE, data);
2562 break;
44ea2b17
AK		 2563 case MSR_KERNEL_GS_BASE:
2564 vmx_load_host_state(vmx);
2565 vmx->msr_guest_kernel_gs_base = data;
2566 break;
6aa8b732
AK		 2567#endif
2568 case MSR_IA32_SYSENTER_CS:
2569 vmcs_write32(GUEST_SYSENTER_CS, data);
2570 break;
2571 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2572 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2573 break;
2574 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2575 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2576 break;
0dd376e7 2577 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2578 if (!vmx_mpx_supported())
2579 return 1;
0dd376e7
LJ		 2580 vmcs_write64(GUEST_BNDCFGS, data);
2581 break;
af24a4e4 2582 case MSR_IA32_TSC:
8fe8ab46 2583 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2584 break;
468d472f
SY		 2585 case MSR_IA32_CR_PAT:
2586 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587 vmcs_write64(GUEST_IA32_PAT, data);
2588 vcpu->arch.pat = data;
2589 break;
2590 }
8fe8ab46 2591 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2592 break;
ba904635
WA		 2593 case MSR_IA32_TSC_ADJUST:
2594 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2595 break;
cae50139
JK		 2596 case MSR_IA32_FEATURE_CONTROL:
2597 if (!nested_vmx_allowed(vcpu) ||
2598 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2600 return 1;
2601 vmx->nested.msr_ia32_feature_control = data;
2602 if (msr_info->host_initiated && data == 0)
2603 vmx_leave_nested(vcpu);
2604 break;
2605 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606 return 1; /* they are read-only */
4e47c7a6
SY		 2607 case MSR_TSC_AUX:
2608 if (!vmx->rdtscp_enabled)
2609 return 1;
2610 /* Check reserved bit, higher 32 bits should be zero */
2611 if ((data >> 32) != 0)
2612 return 1;
2613 /* Otherwise falls through */
6aa8b732 2614 default:
8b9cf98c 2615 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2616 if (msr) {
2617 msr->data = data;
2225fd56
AK		 2618 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2619 preempt_disable();
9ee73970
AK		 2620 kvm_set_shared_msr(msr->index, msr->data,
2621 msr->mask);
2225fd56
AK		 2622 preempt_enable();
2623 }
3bab1f5d 2624 break;
6aa8b732 2625 }
8fe8ab46 2626 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2627 }
2628
2cc51560 2629 return ret;
6aa8b732
AK		 2630}
2631
5fdbf976 2632static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2633{
5fdbf976
MT		 2634 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2635 switch (reg) {
2636 case VCPU_REGS_RSP:
2637 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2638 break;
2639 case VCPU_REGS_RIP:
2640 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2641 break;
6de4f3ad
AK		 2642 case VCPU_EXREG_PDPTR:
2643 if (enable_ept)
2644 ept_save_pdptrs(vcpu);
2645 break;
5fdbf976
MT		 2646 default:
2647 break;
2648 }
6aa8b732
AK		 2649}
2650
6aa8b732
AK		 2651static __init int cpu_has_kvm_support(void)
2652{
6210e37b 2653 return cpu_has_vmx();
6aa8b732
AK		 2654}
2655
2656static __init int vmx_disabled_by_bios(void)
2657{
2658 u64 msr;
2659
2660 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2661 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2662 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2663 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2664 && tboot_enabled())
2665 return 1;
23f3e991 2666 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2667 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2668 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2669 && !tboot_enabled()) {
2670 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2671 "activate TXT before enabling KVM\n");
cafd6659 2672 return 1;
f9335afe 2673 }
23f3e991
JC		 2674 /* launched w/o TXT and VMX disabled */
2675 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676 && !tboot_enabled())
2677 return 1;
cafd6659
SW		 2678 }
2679
2680 return 0;
6aa8b732
AK		 2681}
2682
7725b894
DX		 2683static void kvm_cpu_vmxon(u64 addr)
2684{
2685 asm volatile (ASM_VMX_VMXON_RAX
2686 : : "a"(&addr), "m"(addr)
2687 : "memory", "cc");
2688}
2689
10474ae8 2690static int hardware_enable(void *garbage)
6aa8b732
AK		 2691{
2692 int cpu = raw_smp_processor_id();
2693 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2694 u64 old, test_bits;
6aa8b732 2695
10474ae8
AG		 2696 if (read_cr4() & X86_CR4_VMXE)
2697 return -EBUSY;
2698
d462b819 2699 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2700
2701 /*
2702 * Now we can enable the vmclear operation in kdump
2703 * since the loaded_vmcss_on_cpu list on this cpu
2704 * has been initialized.
2705 *
2706 * Though the cpu is not in VMX operation now, there
2707 * is no problem to enable the vmclear operation
2708 * for the loaded_vmcss_on_cpu list is empty!
2709 */
2710 crash_enable_local_vmclear(cpu);
2711
6aa8b732 2712 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2713
2714 test_bits = FEATURE_CONTROL_LOCKED;
2715 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716 if (tboot_enabled())
2717 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2718
2719 if ((old & test_bits) != test_bits) {
6aa8b732 2720 /* enable and lock */
cafd6659
SW		 2721 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2722 }
66aee91a 2723 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2724
4610c9cc
DX		 2725 if (vmm_exclusive) {
2726 kvm_cpu_vmxon(phys_addr);
2727 ept_sync_global();
2728 }
10474ae8 2729
357d1226 2730 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2731
10474ae8 2732 return 0;
6aa8b732
AK		 2733}
2734
d462b819 2735static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2736{
2737 int cpu = raw_smp_processor_id();
d462b819 2738 struct loaded_vmcs *v, *n;
543e4243 2739
d462b819
NHE		 2740 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741 loaded_vmcss_on_cpu_link)
2742 __loaded_vmcs_clear(v);
543e4243
AK		 2743}
2744
710ff4a8
EH		 2745
2746/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2747 * tricks.
2748 */
2749static void kvm_cpu_vmxoff(void)
6aa8b732 2750{
4ecac3fd 2751 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2752}
2753
710ff4a8
EH		 2754static void hardware_disable(void *garbage)
2755{
4610c9cc 2756 if (vmm_exclusive) {
d462b819 2757 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2758 kvm_cpu_vmxoff();
2759 }
7725b894 2760 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2761}
2762
1c3d14fe 2763static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2764 u32 msr, u32 *result)
1c3d14fe
YS		 2765{
2766 u32 vmx_msr_low, vmx_msr_high;
2767 u32 ctl = ctl_min | ctl_opt;
2768
2769 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2770
2771 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2773
2774 /* Ensure minimum (required) set of control bits are supported. */
2775 if (ctl_min & ~ctl)
002c7f7c 2776 return -EIO;
1c3d14fe
YS		 2777
2778 *result = ctl;
2779 return 0;
2780}
2781
110312c8
AK		 2782static __init bool allow_1_setting(u32 msr, u32 ctl)
2783{
2784 u32 vmx_msr_low, vmx_msr_high;
2785
2786 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787 return vmx_msr_high & ctl;
2788}
2789
002c7f7c 2790static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2791{
2792 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2793 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2794 u32 _pin_based_exec_control = 0;
2795 u32 _cpu_based_exec_control = 0;
f78e0e2e 2796 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2797 u32 _vmexit_control = 0;
2798 u32 _vmentry_control = 0;
2799
10166744 2800 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2801#ifdef CONFIG_X86_64
2802 CPU_BASED_CR8_LOAD_EXITING |
2803 CPU_BASED_CR8_STORE_EXITING |
2804#endif
d56f546d
SY		 2805 CPU_BASED_CR3_LOAD_EXITING |
2806 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2807 CPU_BASED_USE_IO_BITMAPS |
2808 CPU_BASED_MOV_DR_EXITING |
a7052897 2809 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2810 CPU_BASED_MWAIT_EXITING |
2811 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2812 CPU_BASED_INVLPG_EXITING |
2813 CPU_BASED_RDPMC_EXITING;
443381a8 2814
f78e0e2e 2815 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2816 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2817 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2818 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819 &_cpu_based_exec_control) < 0)
002c7f7c 2820 return -EIO;
6e5d865c
YS		 2821#ifdef CONFIG_X86_64
2822 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824 ~CPU_BASED_CR8_STORE_EXITING;
2825#endif
f78e0e2e 2826 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2827 min2 = 0;
2828 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2829 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2830 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2831 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2832 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2833 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2834 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2835 SECONDARY_EXEC_RDTSCP |
83d4c286 2836 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2837 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2838 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2840 if (adjust_vmx_controls(min2, opt2,
2841 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2842 &_cpu_based_2nd_exec_control) < 0)
2843 return -EIO;
2844 }
2845#ifndef CONFIG_X86_64
2846 if (!(_cpu_based_2nd_exec_control &
2847 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2849#endif
83d4c286
YZ		 2850
2851 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852 _cpu_based_2nd_exec_control &= ~(
8d14695f 2853 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2854 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2856
d56f546d 2857 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2858 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2859 enabled */
5fff7d27
GN		 2860 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861 CPU_BASED_CR3_STORE_EXITING |
2862 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2863 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864 vmx_capability.ept, vmx_capability.vpid);
2865 }
1c3d14fe 2866
81908bf4 2867 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2868#ifdef CONFIG_X86_64
2869 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2870#endif
a547c6db 2871 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2872 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2873 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874 &_vmexit_control) < 0)
002c7f7c 2875 return -EIO;
1c3d14fe 2876
01e439be
YZ		 2877 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880 &_pin_based_exec_control) < 0)
2881 return -EIO;
2882
2883 if (!(_cpu_based_2nd_exec_control &
2884 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2887
c845f9c6 2888 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2889 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2890 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891 &_vmentry_control) < 0)
002c7f7c 2892 return -EIO;
6aa8b732 2893
c68876fd 2894 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2895
2896 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2898 return -EIO;
1c3d14fe
YS		 2899
2900#ifdef CONFIG_X86_64
2901 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902 if (vmx_msr_high & (1u<<16))
002c7f7c 2903 return -EIO;
1c3d14fe
YS		 2904#endif
2905
2906 /* Require Write-Back (WB) memory type for VMCS accesses. */
2907 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2908 return -EIO;
1c3d14fe 2909
002c7f7c
YS		 2910 vmcs_conf->size = vmx_msr_high & 0x1fff;
2911 vmcs_conf->order = get_order(vmcs_config.size);
2912 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2913
002c7f7c
YS		 2914 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2916 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2917 vmcs_conf->vmexit_ctrl = _vmexit_control;
2918 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2919
110312c8
AK		 2920 cpu_has_load_ia32_efer =
2921 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922 VM_ENTRY_LOAD_IA32_EFER)
2923 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924 VM_EXIT_LOAD_IA32_EFER);
2925
8bf00a52
GN		 2926 cpu_has_load_perf_global_ctrl =
2927 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2931
2932 /*
2933 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934 * but due to arrata below it can't be used. Workaround is to use
2935 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2936 *
2937 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2938 *
2939 * AAK155 (model 26)
2940 * AAP115 (model 30)
2941 * AAT100 (model 37)
2942 * BC86,AAY89,BD102 (model 44)
2943 * BA97 (model 46)
2944 *
2945 */
2946 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947 switch (boot_cpu_data.x86_model) {
2948 case 26:
2949 case 30:
2950 case 37:
2951 case 44:
2952 case 46:
2953 cpu_has_load_perf_global_ctrl = false;
2954 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955 "does not work properly. Using workaround\n");
2956 break;
2957 default:
2958 break;
2959 }
2960 }
2961
1c3d14fe 2962 return 0;
c68876fd 2963}
6aa8b732
AK		 2964
2965static struct vmcs *alloc_vmcs_cpu(int cpu)
2966{
2967 int node = cpu_to_node(cpu);
2968 struct page *pages;
2969 struct vmcs *vmcs;
2970
6484eb3e 2971 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2972 if (!pages)
2973 return NULL;
2974 vmcs = page_address(pages);
1c3d14fe
YS		 2975 memset(vmcs, 0, vmcs_config.size);
2976 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2977 return vmcs;
2978}
2979
2980static struct vmcs *alloc_vmcs(void)
2981{
d3b2c338 2982 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2983}
2984
2985static void free_vmcs(struct vmcs *vmcs)
2986{
1c3d14fe 2987 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2988}
2989
d462b819
NHE		 2990/*
2991 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2992 */
2993static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2994{
2995 if (!loaded_vmcs->vmcs)
2996 return;
2997 loaded_vmcs_clear(loaded_vmcs);
2998 free_vmcs(loaded_vmcs->vmcs);
2999 loaded_vmcs->vmcs = NULL;
3000}
3001
39959588 3002static void free_kvm_area(void)
6aa8b732
AK		 3003{
3004 int cpu;
3005
3230bb47 3006 for_each_possible_cpu(cpu) {
6aa8b732 3007 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3008 per_cpu(vmxarea, cpu) = NULL;
3009 }
6aa8b732
AK		 3010}
3011
fe2b201b
BD		 3012static void init_vmcs_shadow_fields(void)
3013{
3014 int i, j;
3015
3016 /* No checks for read only fields yet */
3017
3018 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3019 switch (shadow_read_write_fields[i]) {
3020 case GUEST_BNDCFGS:
3021 if (!vmx_mpx_supported())
3022 continue;
3023 break;
3024 default:
3025 break;
3026 }
3027
3028 if (j < i)
3029 shadow_read_write_fields[j] =
3030 shadow_read_write_fields[i];
3031 j++;
3032 }
3033 max_shadow_read_write_fields = j;
3034
3035 /* shadowed fields guest access without vmexit */
3036 for (i = 0; i < max_shadow_read_write_fields; i++) {
3037 clear_bit(shadow_read_write_fields[i],
3038 vmx_vmwrite_bitmap);
3039 clear_bit(shadow_read_write_fields[i],
3040 vmx_vmread_bitmap);
3041 }
3042 for (i = 0; i < max_shadow_read_only_fields; i++)
3043 clear_bit(shadow_read_only_fields[i],
3044 vmx_vmread_bitmap);
3045}
3046
6aa8b732
AK		 3047static __init int alloc_kvm_area(void)
3048{
3049 int cpu;
3050
3230bb47 3051 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3052 struct vmcs *vmcs;
3053
3054 vmcs = alloc_vmcs_cpu(cpu);
3055 if (!vmcs) {
3056 free_kvm_area();
3057 return -ENOMEM;
3058 }
3059
3060 per_cpu(vmxarea, cpu) = vmcs;
3061 }
3062 return 0;
3063}
3064
3065static __init int hardware_setup(void)
3066{
002c7f7c
YS		 3067 if (setup_vmcs_config(&vmcs_config) < 0)
3068 return -EIO;
50a37eb4
JR		 3069
3070 if (boot_cpu_has(X86_FEATURE_NX))
3071 kvm_enable_efer_bits(EFER_NX);
3072
93ba03c2
SY		 3073 if (!cpu_has_vmx_vpid())
3074 enable_vpid = 0;
abc4fc58
AG		 3075 if (!cpu_has_vmx_shadow_vmcs())
3076 enable_shadow_vmcs = 0;
fe2b201b
BD		 3077 if (enable_shadow_vmcs)
3078 init_vmcs_shadow_fields();
93ba03c2 3079
4bc9b982
SY		 3080 if (!cpu_has_vmx_ept() ||
3081 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3082 enable_ept = 0;
3a624e29 3083 enable_unrestricted_guest = 0;
83c3a331 3084 enable_ept_ad_bits = 0;
3a624e29
NK		 3085 }
3086
83c3a331
XH		 3087 if (!cpu_has_vmx_ept_ad_bits())
3088 enable_ept_ad_bits = 0;
3089
3a624e29
NK		 3090 if (!cpu_has_vmx_unrestricted_guest())
3091 enable_unrestricted_guest = 0;
93ba03c2
SY		 3092
3093 if (!cpu_has_vmx_flexpriority())
3094 flexpriority_enabled = 0;
3095
95ba8273
GN		 3096 if (!cpu_has_vmx_tpr_shadow())
3097 kvm_x86_ops->update_cr8_intercept = NULL;
3098
54dee993
MT		 3099 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3100 kvm_disable_largepages();
3101
4b8d54f9
ZE		 3102 if (!cpu_has_vmx_ple())
3103 ple_gap = 0;
3104
01e439be
YZ		 3105 if (!cpu_has_vmx_apicv())
3106 enable_apicv = 0;
c7c9c56c 3107
01e439be 3108 if (enable_apicv)
c7c9c56c 3109 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3110 else {
c7c9c56c 3111 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3112 kvm_x86_ops->deliver_posted_interrupt = NULL;
3113 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3114 }
83d4c286 3115
b87a51ae
NHE		 3116 if (nested)
3117 nested_vmx_setup_ctls_msrs();
3118
6aa8b732
AK		 3119 return alloc_kvm_area();
3120}
3121
3122static __exit void hardware_unsetup(void)
3123{
3124 free_kvm_area();
3125}
3126
14168786
GN		 3127static bool emulation_required(struct kvm_vcpu *vcpu)
3128{
3129 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3130}
3131
91b0aa2c 3132static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3133 struct kvm_segment *save)
6aa8b732 3134{
d99e4152
GN		 3135 if (!emulate_invalid_guest_state) {
3136 /*
3137 * CS and SS RPL should be equal during guest entry according
3138 * to VMX spec, but in reality it is not always so. Since vcpu
3139 * is in the middle of the transition from real mode to
3140 * protected mode it is safe to assume that RPL 0 is a good
3141 * default value.
3142 */
3143 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3144 save->selector &= ~SELECTOR_RPL_MASK;
3145 save->dpl = save->selector & SELECTOR_RPL_MASK;
3146 save->s = 1;
6aa8b732 3147 }
d99e4152 3148 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3149}
3150
3151static void enter_pmode(struct kvm_vcpu *vcpu)
3152{
3153 unsigned long flags;
a89a8fb9 3154 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3155
d99e4152
GN		 3156 /*
3157 * Update real mode segment cache. It may be not up-to-date if sement
3158 * register was written while vcpu was in a guest mode.
3159 */
3160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3161 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3162 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3163 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3164 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3165 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3166
7ffd92c5 3167 vmx->rmode.vm86_active = 0;
6aa8b732 3168
2fb92db1
AK		 3169 vmx_segment_cache_clear(vmx);
3170
f5f7b2fe 3171 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3172
3173 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3174 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3175 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3176 vmcs_writel(GUEST_RFLAGS, flags);
3177
66aee91a
RR		 3178 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3179 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3180
3181 update_exception_bitmap(vcpu);
3182
91b0aa2c
GN		 3183 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3184 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3185 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3186 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3187 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3188 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3189
3190 /* CPL is always 0 when CPU enters protected mode */
3191 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3192 vmx->cpl = 0;
6aa8b732
AK		 3193}
3194
f5f7b2fe 3195static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3196{
772e0318 3197 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3198 struct kvm_segment var = *save;
3199
3200 var.dpl = 0x3;
3201 if (seg == VCPU_SREG_CS)
3202 var.type = 0x3;
3203
3204 if (!emulate_invalid_guest_state) {
3205 var.selector = var.base >> 4;
3206 var.base = var.base & 0xffff0;
3207 var.limit = 0xffff;
3208 var.g = 0;
3209 var.db = 0;
3210 var.present = 1;
3211 var.s = 1;
3212 var.l = 0;
3213 var.unusable = 0;
3214 var.type = 0x3;
3215 var.avl = 0;
3216 if (save->base & 0xf)
3217 printk_once(KERN_WARNING "kvm: segment base is not "
3218 "paragraph aligned when entering "
3219 "protected mode (seg=%d)", seg);
3220 }
6aa8b732 3221
d99e4152
GN		 3222 vmcs_write16(sf->selector, var.selector);
3223 vmcs_write32(sf->base, var.base);
3224 vmcs_write32(sf->limit, var.limit);
3225 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3226}
3227
3228static void enter_rmode(struct kvm_vcpu *vcpu)
3229{
3230 unsigned long flags;
a89a8fb9 3231 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3232
f5f7b2fe
AK		 3233 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3234 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3235 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3236 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3237 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3238 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3239 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3240
7ffd92c5 3241 vmx->rmode.vm86_active = 1;
6aa8b732 3242
776e58ea
GN		 3243 /*
3244 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3245 * vcpu. Warn the user that an update is overdue.
776e58ea 3246 */
4918c6ca 3247 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3248 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3249 "called before entering vcpu\n");
776e58ea 3250
2fb92db1
AK		 3251 vmx_segment_cache_clear(vmx);
3252
4918c6ca 3253 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3254 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3255 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3256
3257 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3258 vmx->rmode.save_rflags = flags;
6aa8b732 3259
053de044 3260 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3261
3262 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3263 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3264 update_exception_bitmap(vcpu);
3265
d99e4152
GN		 3266 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3267 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3268 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3269 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3270 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3271 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3272
8668a3c4 3273 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3274}
3275
401d10de
AS		 3276static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3277{
3278 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3279 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3280
3281 if (!msr)
3282 return;
401d10de 3283
44ea2b17
AK		 3284 /*
3285 * Force kernel_gs_base reloading before EFER changes, as control
3286 * of this msr depends on is_long_mode().
3287 */
3288 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3289 vcpu->arch.efer = efer;
401d10de 3290 if (efer & EFER_LMA) {
2961e876 3291 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3292 msr->data = efer;
3293 } else {
2961e876 3294 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3295
3296 msr->data = efer & ~EFER_LME;
3297 }
3298 setup_msrs(vmx);
3299}
3300
05b3e0c2 3301#ifdef CONFIG_X86_64
6aa8b732
AK		 3302
3303static void enter_lmode(struct kvm_vcpu *vcpu)
3304{
3305 u32 guest_tr_ar;
3306
2fb92db1
AK		 3307 vmx_segment_cache_clear(to_vmx(vcpu));
3308
6aa8b732
AK		 3309 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3310 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3311 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3312 __func__);
6aa8b732
AK		 3313 vmcs_write32(GUEST_TR_AR_BYTES,
3314 (guest_tr_ar & ~AR_TYPE_MASK)
3315 | AR_TYPE_BUSY_64_TSS);
3316 }
da38f438 3317 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3318}
3319
3320static void exit_lmode(struct kvm_vcpu *vcpu)
3321{
2961e876 3322 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3323 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3324}
3325
3326#endif
3327
2384d2b3
SY		 3328static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3329{
b9d762fa 3330 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3331 if (enable_ept) {
3332 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3333 return;
4e1096d2 3334 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3335 }
2384d2b3
SY		 3336}
3337
e8467fda
AK		 3338static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3339{
3340 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3341
3342 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3343 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3344}
3345
aff48baa
AK		 3346static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3347{
3348 if (enable_ept && is_paging(vcpu))
3349 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3350 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3351}
3352
25c4c276 3353static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3354{
fc78f519
AK		 3355 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3356
3357 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3358 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3359}
3360
1439442c
SY		 3361static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3362{
d0d538b9
GN		 3363 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3364
6de4f3ad
AK		 3365 if (!test_bit(VCPU_EXREG_PDPTR,
3366 (unsigned long *)&vcpu->arch.regs_dirty))
3367 return;
3368
1439442c 3369 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3370 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3371 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3372 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3373 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3374 }
3375}
3376
8f5d549f
AK		 3377static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3378{
d0d538b9
GN		 3379 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3380
8f5d549f 3381 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3382 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3383 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3384 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3385 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3386 }
6de4f3ad
AK		 3387
3388 __set_bit(VCPU_EXREG_PDPTR,
3389 (unsigned long *)&vcpu->arch.regs_avail);
3390 __set_bit(VCPU_EXREG_PDPTR,
3391 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3392}
3393
5e1746d6 3394static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3395
3396static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3397 unsigned long cr0,
3398 struct kvm_vcpu *vcpu)
3399{
5233dd51
MT		 3400 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3401 vmx_decache_cr3(vcpu);
1439442c
SY		 3402 if (!(cr0 & X86_CR0_PG)) {
3403 /* From paging/starting to nonpaging */
3404 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3405 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3406 (CPU_BASED_CR3_LOAD_EXITING |
3407 CPU_BASED_CR3_STORE_EXITING));
3408 vcpu->arch.cr0 = cr0;
fc78f519 3409 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3410 } else if (!is_paging(vcpu)) {
3411 /* From nonpaging to paging */
3412 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3413 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3414 ~(CPU_BASED_CR3_LOAD_EXITING |
3415 CPU_BASED_CR3_STORE_EXITING));
3416 vcpu->arch.cr0 = cr0;
fc78f519 3417 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3418 }
95eb84a7
SY		 3419
3420 if (!(cr0 & X86_CR0_WP))
3421 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3422}
3423
6aa8b732
AK		 3424static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3425{
7ffd92c5 3426 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3427 unsigned long hw_cr0;
3428
5037878e 3429 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3430 if (enable_unrestricted_guest)
5037878e 3431 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3432 else {
5037878e 3433 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3434
218e763f
GN		 3435 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3436 enter_pmode(vcpu);
6aa8b732 3437
218e763f
GN		 3438 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3439 enter_rmode(vcpu);
3440 }
6aa8b732 3441
05b3e0c2 3442#ifdef CONFIG_X86_64
f6801dff 3443 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3444 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3445 enter_lmode(vcpu);
707d92fa 3446 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3447 exit_lmode(vcpu);
3448 }
3449#endif
3450
089d034e 3451 if (enable_ept)
1439442c
SY		 3452 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3453
02daab21 3454 if (!vcpu->fpu_active)
81231c69 3455 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3456
6aa8b732 3457 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3458 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3459 vcpu->arch.cr0 = cr0;
14168786
GN		 3460
3461 /* depends on vcpu->arch.cr0 to be set to a new value */
3462 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3463}
3464
1439442c
SY		 3465static u64 construct_eptp(unsigned long root_hpa)
3466{
3467 u64 eptp;
3468
3469 /* TODO write the value reading from MSR */
3470 eptp = VMX_EPT_DEFAULT_MT |
3471 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3472 if (enable_ept_ad_bits)
3473 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3474 eptp |= (root_hpa & PAGE_MASK);
3475
3476 return eptp;
3477}
3478
6aa8b732
AK		 3479static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3480{
1439442c
SY		 3481 unsigned long guest_cr3;
3482 u64 eptp;
3483
3484 guest_cr3 = cr3;
089d034e 3485 if (enable_ept) {
1439442c
SY		 3486 eptp = construct_eptp(cr3);
3487 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3488 if (is_paging(vcpu) || is_guest_mode(vcpu))
3489 guest_cr3 = kvm_read_cr3(vcpu);
3490 else
3491 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3492 ept_load_pdptrs(vcpu);
1439442c
SY		 3493 }
3494
2384d2b3 3495 vmx_flush_tlb(vcpu);
1439442c 3496 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3497}
3498
5e1746d6 3499static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3500{
7ffd92c5 3501 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3502 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3503
5e1746d6
NHE		 3504 if (cr4 & X86_CR4_VMXE) {
3505 /*
3506 * To use VMXON (and later other VMX instructions), a guest
3507 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3508 * So basically the check on whether to allow nested VMX
3509 * is here.
3510 */
3511 if (!nested_vmx_allowed(vcpu))
3512 return 1;
1a0d74e6
JK		 3513 }
3514 if (to_vmx(vcpu)->nested.vmxon &&
3515 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3516 return 1;
3517
ad312c7c 3518 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3519 if (enable_ept) {
3520 if (!is_paging(vcpu)) {
3521 hw_cr4 &= ~X86_CR4_PAE;
3522 hw_cr4 |= X86_CR4_PSE;
c08800a5 3523 /*
e1e746b3
FW		 3524 * SMEP/SMAP is disabled if CPU is in non-paging mode
3525 * in hardware. However KVM always uses paging mode to
c08800a5 3526 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3527 * To emulate this behavior, SMEP/SMAP needs to be
3528 * manually disabled when guest switches to non-paging
3529 * mode.
c08800a5 3530 */
e1e746b3 3531 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3532 } else if (!(cr4 & X86_CR4_PAE)) {
3533 hw_cr4 &= ~X86_CR4_PAE;
3534 }
3535 }
1439442c
SY		 3536
3537 vmcs_writel(CR4_READ_SHADOW, cr4);
3538 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3539 return 0;
6aa8b732
AK		 3540}
3541
6aa8b732
AK		 3542static void vmx_get_segment(struct kvm_vcpu *vcpu,
3543 struct kvm_segment *var, int seg)
3544{
a9179499 3545 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3546 u32 ar;
3547
c6ad1153 3548 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3549 *var = vmx->rmode.segs[seg];
a9179499 3550 if (seg == VCPU_SREG_TR
2fb92db1 3551 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3552 return;
1390a28b
AK		 3553 var->base = vmx_read_guest_seg_base(vmx, seg);
3554 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3555 return;
a9179499 3556 }
2fb92db1
AK		 3557 var->base = vmx_read_guest_seg_base(vmx, seg);
3558 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3559 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3560 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3561 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3562 var->type = ar & 15;
3563 var->s = (ar >> 4) & 1;
3564 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3565 /*
3566 * Some userspaces do not preserve unusable property. Since usable
3567 * segment has to be present according to VMX spec we can use present
3568 * property to amend userspace bug by making unusable segment always
3569 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3570 * segment as unusable.
3571 */
3572 var->present = !var->unusable;
6aa8b732
AK		 3573 var->avl = (ar >> 12) & 1;
3574 var->l = (ar >> 13) & 1;
3575 var->db = (ar >> 14) & 1;
3576 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3577}
3578
a9179499
AK		 3579static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3580{
a9179499
AK		 3581 struct kvm_segment s;
3582
3583 if (to_vmx(vcpu)->rmode.vm86_active) {
3584 vmx_get_segment(vcpu, &s, seg);
3585 return s.base;
3586 }
2fb92db1 3587 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3588}
3589
b09408d0 3590static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3591{
b09408d0
MT		 3592 struct vcpu_vmx *vmx = to_vmx(vcpu);
3593
3eeb3288 3594 if (!is_protmode(vcpu))
2e4d2653
IE		 3595 return 0;
3596
f4c63e5d
AK		 3597 if (!is_long_mode(vcpu)
3598 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3599 return 3;
3600
69c73028
AK		 3601 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3602 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3603 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3604 }
d881e6f6
AK		 3605
3606 return vmx->cpl;
69c73028
AK		 3607}
3608
3609
653e3108 3610static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3611{
6aa8b732
AK		 3612 u32 ar;
3613
f0495f9b 3614 if (var->unusable || !var->present)
6aa8b732
AK		 3615 ar = 1 << 16;
3616 else {
3617 ar = var->type & 15;
3618 ar |= (var->s & 1) << 4;
3619 ar |= (var->dpl & 3) << 5;
3620 ar |= (var->present & 1) << 7;
3621 ar |= (var->avl & 1) << 12;
3622 ar |= (var->l & 1) << 13;
3623 ar |= (var->db & 1) << 14;
3624 ar |= (var->g & 1) << 15;
3625 }
653e3108
AK		 3626
3627 return ar;
3628}
3629
3630static void vmx_set_segment(struct kvm_vcpu *vcpu,
3631 struct kvm_segment *var, int seg)
3632{
7ffd92c5 3633 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3634 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3635
2fb92db1 3636 vmx_segment_cache_clear(vmx);
2f143240
GN		 3637 if (seg == VCPU_SREG_CS)
3638 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3639
1ecd50a9
GN		 3640 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3641 vmx->rmode.segs[seg] = *var;
3642 if (seg == VCPU_SREG_TR)
3643 vmcs_write16(sf->selector, var->selector);
3644 else if (var->s)
3645 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3646 goto out;
653e3108 3647 }
1ecd50a9 3648
653e3108
AK		 3649 vmcs_writel(sf->base, var->base);
3650 vmcs_write32(sf->limit, var->limit);
3651 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3652
3653 /*
3654 * Fix the "Accessed" bit in AR field of segment registers for older
3655 * qemu binaries.
3656 * IA32 arch specifies that at the time of processor reset the
3657 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3658 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3659 * state vmexit when "unrestricted guest" mode is turned on.
3660 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3661 * tree. Newer qemu binaries with that qemu fix would not need this
3662 * kvm hack.
3663 */
3664 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3665 var->type |= 0x1; /* Accessed */
3a624e29 3666
f924d66d 3667 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3668
3669out:
14168786 3670 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3671}
3672
6aa8b732
AK		 3673static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3674{
2fb92db1 3675 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3676
3677 *db = (ar >> 14) & 1;
3678 *l = (ar >> 13) & 1;
3679}
3680
89a27f4d 3681static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3682{
89a27f4d
GN		 3683 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3684 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3685}
3686
89a27f4d 3687static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3688{
89a27f4d
GN		 3689 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3690 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3691}
3692
89a27f4d 3693static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3694{
89a27f4d
GN		 3695 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3696 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3697}
3698
89a27f4d 3699static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3700{
89a27f4d
GN		 3701 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3702 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3703}
3704
648dfaa7
MG		 3705static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3706{
3707 struct kvm_segment var;
3708 u32 ar;
3709
3710 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3711 var.dpl = 0x3;
0647f4aa
GN		 3712 if (seg == VCPU_SREG_CS)
3713 var.type = 0x3;
648dfaa7
MG		 3714 ar = vmx_segment_access_rights(&var);
3715
3716 if (var.base != (var.selector << 4))
3717 return false;
89efbed0 3718 if (var.limit != 0xffff)
648dfaa7 3719 return false;
07f42f5f 3720 if (ar != 0xf3)
648dfaa7
MG		 3721 return false;
3722
3723 return true;
3724}
3725
3726static bool code_segment_valid(struct kvm_vcpu *vcpu)
3727{
3728 struct kvm_segment cs;
3729 unsigned int cs_rpl;
3730
3731 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3732 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3733
1872a3f4
AK		 3734 if (cs.unusable)
3735 return false;
648dfaa7
MG		 3736 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3737 return false;
3738 if (!cs.s)
3739 return false;
1872a3f4 3740 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3741 if (cs.dpl > cs_rpl)
3742 return false;
1872a3f4 3743 } else {
648dfaa7
MG		 3744 if (cs.dpl != cs_rpl)
3745 return false;
3746 }
3747 if (!cs.present)
3748 return false;
3749
3750 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3751 return true;
3752}
3753
3754static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3755{
3756 struct kvm_segment ss;
3757 unsigned int ss_rpl;
3758
3759 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3760 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3761
1872a3f4
AK		 3762 if (ss.unusable)
3763 return true;
3764 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3765 return false;
3766 if (!ss.s)
3767 return false;
3768 if (ss.dpl != ss_rpl) /* DPL != RPL */
3769 return false;
3770 if (!ss.present)
3771 return false;
3772
3773 return true;
3774}
3775
3776static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3777{
3778 struct kvm_segment var;
3779 unsigned int rpl;
3780
3781 vmx_get_segment(vcpu, &var, seg);
3782 rpl = var.selector & SELECTOR_RPL_MASK;
3783
1872a3f4
AK		 3784 if (var.unusable)
3785 return true;
648dfaa7
MG		 3786 if (!var.s)
3787 return false;
3788 if (!var.present)
3789 return false;
3790 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3791 if (var.dpl < rpl) /* DPL < RPL */
3792 return false;
3793 }
3794
3795 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3796 * rights flags
3797 */
3798 return true;
3799}
3800
3801static bool tr_valid(struct kvm_vcpu *vcpu)
3802{
3803 struct kvm_segment tr;
3804
3805 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3806
1872a3f4
AK		 3807 if (tr.unusable)
3808 return false;
648dfaa7
MG		 3809 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3810 return false;
1872a3f4 3811 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3812 return false;
3813 if (!tr.present)
3814 return false;
3815
3816 return true;
3817}
3818
3819static bool ldtr_valid(struct kvm_vcpu *vcpu)
3820{
3821 struct kvm_segment ldtr;
3822
3823 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3824
1872a3f4
AK		 3825 if (ldtr.unusable)
3826 return true;
648dfaa7
MG		 3827 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3828 return false;
3829 if (ldtr.type != 2)
3830 return false;
3831 if (!ldtr.present)
3832 return false;
3833
3834 return true;
3835}
3836
3837static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3838{
3839 struct kvm_segment cs, ss;
3840
3841 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3842 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3843
3844 return ((cs.selector & SELECTOR_RPL_MASK) ==
3845 (ss.selector & SELECTOR_RPL_MASK));
3846}
3847
3848/*
3849 * Check if guest state is valid. Returns true if valid, false if
3850 * not.
3851 * We assume that registers are always usable
3852 */
3853static bool guest_state_valid(struct kvm_vcpu *vcpu)
3854{
c5e97c80
GN		 3855 if (enable_unrestricted_guest)
3856 return true;
3857
648dfaa7 3858 /* real mode guest state checks */
f13882d8 3859 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3860 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3861 return false;
3862 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3863 return false;
3864 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3865 return false;
3866 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3867 return false;
3868 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3869 return false;
3870 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3871 return false;
3872 } else {
3873 /* protected mode guest state checks */
3874 if (!cs_ss_rpl_check(vcpu))
3875 return false;
3876 if (!code_segment_valid(vcpu))
3877 return false;
3878 if (!stack_segment_valid(vcpu))
3879 return false;
3880 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3881 return false;
3882 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3883 return false;
3884 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3885 return false;
3886 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3887 return false;
3888 if (!tr_valid(vcpu))
3889 return false;
3890 if (!ldtr_valid(vcpu))
3891 return false;
3892 }
3893 /* TODO:
3894 * - Add checks on RIP
3895 * - Add checks on RFLAGS
3896 */
3897
3898 return true;
3899}
3900
d77c26fc 3901static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3902{
40dcaa9f 3903 gfn_t fn;
195aefde 3904 u16 data = 0;
40dcaa9f 3905 int r, idx, ret = 0;
6aa8b732 3906
40dcaa9f 3907 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3908 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3909 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3910 if (r < 0)
10589a46 3911 goto out;
195aefde 3912 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3913 r = kvm_write_guest_page(kvm, fn++, &data,
3914 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3915 if (r < 0)
10589a46 3916 goto out;
195aefde
IE		 3917 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3918 if (r < 0)
10589a46 3919 goto out;
195aefde
IE		 3920 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3921 if (r < 0)
10589a46 3922 goto out;
195aefde 3923 data = ~0;
10589a46
MT		 3924 r = kvm_write_guest_page(kvm, fn, &data,
3925 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3926 sizeof(u8));
195aefde 3927 if (r < 0)
10589a46
MT		 3928 goto out;
3929
3930 ret = 1;
3931out:
40dcaa9f 3932 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3933 return ret;
6aa8b732
AK		 3934}
3935
b7ebfb05
SY		 3936static int init_rmode_identity_map(struct kvm *kvm)
3937{
40dcaa9f 3938 int i, idx, r, ret;
b7ebfb05
SY		 3939 pfn_t identity_map_pfn;
3940 u32 tmp;
3941
089d034e 3942 if (!enable_ept)
b7ebfb05
SY		 3943 return 1;
3944 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3945 printk(KERN_ERR "EPT: identity-mapping pagetable "
3946 "haven't been allocated!\n");
3947 return 0;
3948 }
3949 if (likely(kvm->arch.ept_identity_pagetable_done))
3950 return 1;
3951 ret = 0;
b927a3ce 3952 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3953 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3954 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3955 if (r < 0)
3956 goto out;
3957 /* Set up identity-mapping pagetable for EPT in real mode */
3958 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3959 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3960 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3961 r = kvm_write_guest_page(kvm, identity_map_pfn,
3962 &tmp, i * sizeof(tmp), sizeof(tmp));
3963 if (r < 0)
3964 goto out;
3965 }
3966 kvm->arch.ept_identity_pagetable_done = true;
3967 ret = 1;
3968out:
40dcaa9f 3969 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3970 return ret;
3971}
3972
6aa8b732
AK		 3973static void seg_setup(int seg)
3974{
772e0318 3975 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3976 unsigned int ar;
6aa8b732
AK		 3977
3978 vmcs_write16(sf->selector, 0);
3979 vmcs_writel(sf->base, 0);
3980 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3981 ar = 0x93;
3982 if (seg == VCPU_SREG_CS)
3983 ar |= 0x08; /* code segment */
3a624e29
NK		 3984
3985 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3986}
3987
f78e0e2e
SY		 3988static int alloc_apic_access_page(struct kvm *kvm)
3989{
4484141a 3990 struct page *page;
f78e0e2e
SY		 3991 struct kvm_userspace_memory_region kvm_userspace_mem;
3992 int r = 0;
3993
79fac95e 3994 mutex_lock(&kvm->slots_lock);
bfc6d222 3995 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3996 goto out;
3997 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3998 kvm_userspace_mem.flags = 0;
3999 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4000 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4001 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4002 if (r)
4003 goto out;
72dc67a6 4004
4484141a
XG		 4005 page = gfn_to_page(kvm, 0xfee00);
4006 if (is_error_page(page)) {
4007 r = -EFAULT;
4008 goto out;
4009 }
4010
4011 kvm->arch.apic_access_page = page;
f78e0e2e 4012out:
79fac95e 4013 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4014 return r;
4015}
4016
b7ebfb05
SY		 4017static int alloc_identity_pagetable(struct kvm *kvm)
4018{
4484141a 4019 struct page *page;
b7ebfb05
SY		 4020 struct kvm_userspace_memory_region kvm_userspace_mem;
4021 int r = 0;
4022
79fac95e 4023 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 4024 if (kvm->arch.ept_identity_pagetable)
4025 goto out;
4026 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4027 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4028 kvm_userspace_mem.guest_phys_addr =
4029 kvm->arch.ept_identity_map_addr;
b7ebfb05 4030 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4031 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 4032 if (r)
4033 goto out;
4034
4484141a
XG		 4035 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4036 if (is_error_page(page)) {
4037 r = -EFAULT;
4038 goto out;
4039 }
4040
4041 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4042out:
79fac95e 4043 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4044 return r;
4045}
4046
2384d2b3
SY		 4047static void allocate_vpid(struct vcpu_vmx *vmx)
4048{
4049 int vpid;
4050
4051 vmx->vpid = 0;
919818ab 4052 if (!enable_vpid)
2384d2b3
SY		 4053 return;
4054 spin_lock(&vmx_vpid_lock);
4055 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4056 if (vpid < VMX_NR_VPIDS) {
4057 vmx->vpid = vpid;
4058 __set_bit(vpid, vmx_vpid_bitmap);
4059 }
4060 spin_unlock(&vmx_vpid_lock);
4061}
4062
cdbecfc3
LJ		 4063static void free_vpid(struct vcpu_vmx *vmx)
4064{
4065 if (!enable_vpid)
4066 return;
4067 spin_lock(&vmx_vpid_lock);
4068 if (vmx->vpid != 0)
4069 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4070 spin_unlock(&vmx_vpid_lock);
4071}
4072
8d14695f
YZ		 4073#define MSR_TYPE_R 1
4074#define MSR_TYPE_W 2
4075static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4076 u32 msr, int type)
25c5f225 4077{
3e7c73e9 4078 int f = sizeof(unsigned long);
25c5f225
SY		 4079
4080 if (!cpu_has_vmx_msr_bitmap())
4081 return;
4082
4083 /*
4084 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4085 * have the write-low and read-high bitmap offsets the wrong way round.
4086 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4087 */
25c5f225 4088 if (msr <= 0x1fff) {
8d14695f
YZ		 4089 if (type & MSR_TYPE_R)
4090 /* read-low */
4091 __clear_bit(msr, msr_bitmap + 0x000 / f);
4092
4093 if (type & MSR_TYPE_W)
4094 /* write-low */
4095 __clear_bit(msr, msr_bitmap + 0x800 / f);
4096
25c5f225
SY		 4097 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4098 msr &= 0x1fff;
8d14695f
YZ		 4099 if (type & MSR_TYPE_R)
4100 /* read-high */
4101 __clear_bit(msr, msr_bitmap + 0x400 / f);
4102
4103 if (type & MSR_TYPE_W)
4104 /* write-high */
4105 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4106
4107 }
4108}
4109
4110static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4111 u32 msr, int type)
4112{
4113 int f = sizeof(unsigned long);
4114
4115 if (!cpu_has_vmx_msr_bitmap())
4116 return;
4117
4118 /*
4119 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4120 * have the write-low and read-high bitmap offsets the wrong way round.
4121 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4122 */
4123 if (msr <= 0x1fff) {
4124 if (type & MSR_TYPE_R)
4125 /* read-low */
4126 __set_bit(msr, msr_bitmap + 0x000 / f);
4127
4128 if (type & MSR_TYPE_W)
4129 /* write-low */
4130 __set_bit(msr, msr_bitmap + 0x800 / f);
4131
4132 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4133 msr &= 0x1fff;
4134 if (type & MSR_TYPE_R)
4135 /* read-high */
4136 __set_bit(msr, msr_bitmap + 0x400 / f);
4137
4138 if (type & MSR_TYPE_W)
4139 /* write-high */
4140 __set_bit(msr, msr_bitmap + 0xc00 / f);
4141
25c5f225 4142 }
25c5f225
SY		 4143}
4144
5897297b
AK		 4145static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4146{
4147 if (!longmode_only)
8d14695f
YZ		 4148 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4149 msr, MSR_TYPE_R | MSR_TYPE_W);
4150 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4151 msr, MSR_TYPE_R | MSR_TYPE_W);
4152}
4153
4154static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4155{
4156 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4157 msr, MSR_TYPE_R);
4158 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4159 msr, MSR_TYPE_R);
4160}
4161
4162static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4163{
4164 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4165 msr, MSR_TYPE_R);
4166 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4167 msr, MSR_TYPE_R);
4168}
4169
4170static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4171{
4172 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4173 msr, MSR_TYPE_W);
4174 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4175 msr, MSR_TYPE_W);
5897297b
AK		 4176}
4177
01e439be
YZ		 4178static int vmx_vm_has_apicv(struct kvm *kvm)
4179{
4180 return enable_apicv && irqchip_in_kernel(kvm);
4181}
4182
a20ed54d
YZ		 4183/*
4184 * Send interrupt to vcpu via posted interrupt way.
4185 * 1. If target vcpu is running(non-root mode), send posted interrupt
4186 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4187 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4188 * interrupt from PIR in next vmentry.
4189 */
4190static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4191{
4192 struct vcpu_vmx *vmx = to_vmx(vcpu);
4193 int r;
4194
4195 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4196 return;
4197
4198 r = pi_test_and_set_on(&vmx->pi_desc);
4199 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4200#ifdef CONFIG_SMP
a20ed54d
YZ		 4201 if (!r && (vcpu->mode == IN_GUEST_MODE))
4202 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4203 POSTED_INTR_VECTOR);
4204 else
6ffbbbba 4205#endif
a20ed54d
YZ		 4206 kvm_vcpu_kick(vcpu);
4207}
4208
4209static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4210{
4211 struct vcpu_vmx *vmx = to_vmx(vcpu);
4212
4213 if (!pi_test_and_clear_on(&vmx->pi_desc))
4214 return;
4215
4216 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4217}
4218
4219static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4220{
4221 return;
4222}
4223
a3a8ff8e
NHE		 4224/*
4225 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4226 * will not change in the lifetime of the guest.
4227 * Note that host-state that does change is set elsewhere. E.g., host-state
4228 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4229 */
a547c6db 4230static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4231{
4232 u32 low32, high32;
4233 unsigned long tmpl;
4234 struct desc_ptr dt;
4235
b1a74bf8 4236 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4237 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4238 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4239
4240 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4241#ifdef CONFIG_X86_64
4242 /*
4243 * Load null selectors, so we can avoid reloading them in
4244 * __vmx_load_host_state(), in case userspace uses the null selectors
4245 * too (the expected case).
4246 */
4247 vmcs_write16(HOST_DS_SELECTOR, 0);
4248 vmcs_write16(HOST_ES_SELECTOR, 0);
4249#else
a3a8ff8e
NHE		 4250 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4251 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4252#endif
a3a8ff8e
NHE		 4253 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4254 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4255
4256 native_store_idt(&dt);
4257 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4258 vmx->host_idt_base = dt.address;
a3a8ff8e 4259
83287ea4 4260 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4261
4262 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4263 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4264 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4265 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4266
4267 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4268 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4269 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4270 }
4271}
4272
bf8179a0
NHE		 4273static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4274{
4275 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4276 if (enable_ept)
4277 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4278 if (is_guest_mode(&vmx->vcpu))
4279 vmx->vcpu.arch.cr4_guest_owned_bits &=
4280 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4281 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4282}
4283
01e439be
YZ		 4284static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4285{
4286 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4287
4288 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4289 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4290 return pin_based_exec_ctrl;
4291}
4292
bf8179a0
NHE		 4293static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4294{
4295 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4296
4297 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4298 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4299
bf8179a0
NHE		 4300 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4301 exec_control &= ~CPU_BASED_TPR_SHADOW;
4302#ifdef CONFIG_X86_64
4303 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4304 CPU_BASED_CR8_LOAD_EXITING;
4305#endif
4306 }
4307 if (!enable_ept)
4308 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4309 CPU_BASED_CR3_LOAD_EXITING |
4310 CPU_BASED_INVLPG_EXITING;
4311 return exec_control;
4312}
4313
4314static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4315{
4316 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4317 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4318 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4319 if (vmx->vpid == 0)
4320 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4321 if (!enable_ept) {
4322 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4323 enable_unrestricted_guest = 0;
ad756a16
MJ		 4324 /* Enable INVPCID for non-ept guests may cause performance regression. */
4325 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4326 }
4327 if (!enable_unrestricted_guest)
4328 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4329 if (!ple_gap)
4330 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4331 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4332 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4333 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4334 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4335 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4336 (handle_vmptrld).
4337 We can NOT enable shadow_vmcs here because we don't have yet
4338 a current VMCS12
4339 */
4340 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4341 return exec_control;
4342}
4343
ce88decf
XG		 4344static void ept_set_mmio_spte_mask(void)
4345{
4346 /*
4347 * EPT Misconfigurations can be generated if the value of bits 2:0
4348 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4349 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4350 * spte.
4351 */
885032b9 4352 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4353}
4354
6aa8b732
AK		 4355/*
4356 * Sets up the vmcs for emulated real mode.
4357 */
8b9cf98c 4358static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4359{
2e4ce7f5 4360#ifdef CONFIG_X86_64
6aa8b732 4361 unsigned long a;
2e4ce7f5 4362#endif
6aa8b732 4363 int i;
6aa8b732 4364
6aa8b732 4365 /* I/O */
3e7c73e9
AK		 4366 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4367 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4368
4607c2d7
AG		 4369 if (enable_shadow_vmcs) {
4370 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4371 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4372 }
25c5f225 4373 if (cpu_has_vmx_msr_bitmap())
5897297b 4374 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4375
6aa8b732
AK		 4376 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4377
6aa8b732 4378 /* Control */
01e439be 4379 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4380
bf8179a0 4381 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4382
83ff3b9d 4383 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4384 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4385 vmx_secondary_exec_control(vmx));
83ff3b9d 4386 }
f78e0e2e 4387
01e439be 4388 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4389 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4390 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4391 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4392 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4393
4394 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4395
4396 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4397 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4398 }
4399
4b8d54f9
ZE		 4400 if (ple_gap) {
4401 vmcs_write32(PLE_GAP, ple_gap);
4402 vmcs_write32(PLE_WINDOW, ple_window);
4403 }
4404
c3707958
XG		 4405 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4406 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4407 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4408
9581d442
AK		 4409 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4410 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4411 vmx_set_constant_host_state(vmx);
05b3e0c2 4412#ifdef CONFIG_X86_64
6aa8b732
AK		 4413 rdmsrl(MSR_FS_BASE, a);
4414 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4415 rdmsrl(MSR_GS_BASE, a);
4416 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4417#else
4418 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4419 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4420#endif
4421
2cc51560
ED		 4422 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4423 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4424 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4425 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4426 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4427
468d472f 4428 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4429 u32 msr_low, msr_high;
4430 u64 host_pat;
468d472f
SY		 4431 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4432 host_pat = msr_low | ((u64) msr_high << 32);
4433 /* Write the default value follow host pat */
4434 vmcs_write64(GUEST_IA32_PAT, host_pat);
4435 /* Keep arch.pat sync with GUEST_IA32_PAT */
4436 vmx->vcpu.arch.pat = host_pat;
4437 }
4438
6aa8b732
AK		 4439 for (i = 0; i < NR_VMX_MSR; ++i) {
4440 u32 index = vmx_msr_index[i];
4441 u32 data_low, data_high;
a2fa3e9f 4442 int j = vmx->nmsrs;
6aa8b732
AK		 4443
4444 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4445 continue;
432bd6cb
AK		 4446 if (wrmsr_safe(index, data_low, data_high) < 0)
4447 continue;
26bb0981
AK		 4448 vmx->guest_msrs[j].index = i;
4449 vmx->guest_msrs[j].data = 0;
d5696725 4450 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4451 ++vmx->nmsrs;
6aa8b732 4452 }
6aa8b732 4453
2961e876
GN		 4454
4455 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4456
4457 /* 22.2.1, 20.8.1 */
2961e876 4458 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4459
e00c8cf2 4460 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4461 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4462
4463 return 0;
4464}
4465
57f252f2 4466static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4467{
4468 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4469 struct msr_data apic_base_msr;
e00c8cf2 4470
7ffd92c5 4471 vmx->rmode.vm86_active = 0;
e00c8cf2 4472
3b86cd99
JK		 4473 vmx->soft_vnmi_blocked = 0;
4474
ad312c7c 4475 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4476 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4477 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4478 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4479 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4480 apic_base_msr.host_initiated = true;
4481 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4482
2fb92db1
AK		 4483 vmx_segment_cache_clear(vmx);
4484
5706be0d 4485 seg_setup(VCPU_SREG_CS);
66450a21 4486 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4487 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4488
4489 seg_setup(VCPU_SREG_DS);
4490 seg_setup(VCPU_SREG_ES);
4491 seg_setup(VCPU_SREG_FS);
4492 seg_setup(VCPU_SREG_GS);
4493 seg_setup(VCPU_SREG_SS);
4494
4495 vmcs_write16(GUEST_TR_SELECTOR, 0);
4496 vmcs_writel(GUEST_TR_BASE, 0);
4497 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4498 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4499
4500 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4501 vmcs_writel(GUEST_LDTR_BASE, 0);
4502 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4503 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4504
4505 vmcs_write32(GUEST_SYSENTER_CS, 0);
4506 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4507 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4508
4509 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4510 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4511
e00c8cf2
AK		 4512 vmcs_writel(GUEST_GDTR_BASE, 0);
4513 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4514
4515 vmcs_writel(GUEST_IDTR_BASE, 0);
4516 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4517
443381a8 4518 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4519 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4520 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4521
e00c8cf2
AK		 4522 /* Special registers */
4523 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4524
4525 setup_msrs(vmx);
4526
6aa8b732
AK		 4527 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4528
f78e0e2e
SY		 4529 if (cpu_has_vmx_tpr_shadow()) {
4530 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4531 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4532 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4533 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4534 vmcs_write32(TPR_THRESHOLD, 0);
4535 }
4536
4537 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4538 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4539 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4540
01e439be
YZ		 4541 if (vmx_vm_has_apicv(vcpu->kvm))
4542 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4543
2384d2b3
SY		 4544 if (vmx->vpid != 0)
4545 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4546
fa40052c 4547 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4548 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4549 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4550 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4551 vmx_fpu_activate(&vmx->vcpu);
4552 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4553
b9d762fa 4554 vpid_sync_context(vmx);
6aa8b732
AK		 4555}
4556
b6f1250e
NHE		 4557/*
4558 * In nested virtualization, check if L1 asked to exit on external interrupts.
4559 * For most existing hypervisors, this will always return true.
4560 */
4561static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4562{
4563 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4564 PIN_BASED_EXT_INTR_MASK;
4565}
4566
ea8ceb83
JK		 4567static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4568{
4569 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4570 PIN_BASED_NMI_EXITING;
4571}
4572
c9a7953f 4573static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4574{
4575 u32 cpu_based_vm_exec_control;
730dca42 4576
3b86cd99
JK		 4577 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4578 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4579 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4580}
4581
c9a7953f 4582static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4583{
4584 u32 cpu_based_vm_exec_control;
4585
c9a7953f
JK		 4586 if (!cpu_has_virtual_nmis() ||
4587 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4588 enable_irq_window(vcpu);
4589 return;
4590 }
3b86cd99
JK		 4591
4592 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4593 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4594 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4595}
4596
66fd3f7f 4597static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4598{
9c8cba37 4599 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4600 uint32_t intr;
4601 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4602
229456fc 4603 trace_kvm_inj_virq(irq);
2714d1d3 4604
fa89a817 4605 ++vcpu->stat.irq_injections;
7ffd92c5 4606 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4607 int inc_eip = 0;
4608 if (vcpu->arch.interrupt.soft)
4609 inc_eip = vcpu->arch.event_exit_inst_len;
4610 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4611 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4612 return;
4613 }
66fd3f7f
GN		 4614 intr = irq | INTR_INFO_VALID_MASK;
4615 if (vcpu->arch.interrupt.soft) {
4616 intr |= INTR_TYPE_SOFT_INTR;
4617 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4618 vmx->vcpu.arch.event_exit_inst_len);
4619 } else
4620 intr |= INTR_TYPE_EXT_INTR;
4621 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4622}
4623
f08864b4
SY		 4624static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4625{
66a5a347
JK		 4626 struct vcpu_vmx *vmx = to_vmx(vcpu);
4627
0b6ac343
NHE		 4628 if (is_guest_mode(vcpu))
4629 return;
4630
3b86cd99
JK		 4631 if (!cpu_has_virtual_nmis()) {
4632 /*
4633 * Tracking the NMI-blocked state in software is built upon
4634 * finding the next open IRQ window. This, in turn, depends on
4635 * well-behaving guests: They have to keep IRQs disabled at
4636 * least as long as the NMI handler runs. Otherwise we may
4637 * cause NMI nesting, maybe breaking the guest. But as this is
4638 * highly unlikely, we can live with the residual risk.
4639 */
4640 vmx->soft_vnmi_blocked = 1;
4641 vmx->vnmi_blocked_time = 0;
4642 }
4643
487b391d 4644 ++vcpu->stat.nmi_injections;
9d58b931 4645 vmx->nmi_known_unmasked = false;
7ffd92c5 4646 if (vmx->rmode.vm86_active) {
71f9833b 4647 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4648 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4649 return;
4650 }
f08864b4
SY		 4651 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4652 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4653}
4654
3cfc3092
JK		 4655static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4656{
4657 if (!cpu_has_virtual_nmis())
4658 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4659 if (to_vmx(vcpu)->nmi_known_unmasked)
4660 return false;
c332c83a 4661 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4662}
4663
4664static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4665{
4666 struct vcpu_vmx *vmx = to_vmx(vcpu);
4667
4668 if (!cpu_has_virtual_nmis()) {
4669 if (vmx->soft_vnmi_blocked != masked) {
4670 vmx->soft_vnmi_blocked = masked;
4671 vmx->vnmi_blocked_time = 0;
4672 }
4673 } else {
9d58b931 4674 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4675 if (masked)
4676 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4677 GUEST_INTR_STATE_NMI);
4678 else
4679 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4680 GUEST_INTR_STATE_NMI);
4681 }
4682}
4683
2505dc9f
JK		 4684static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4685{
b6b8a145
JK		 4686 if (to_vmx(vcpu)->nested.nested_run_pending)
4687 return 0;
ea8ceb83 4688
2505dc9f
JK		 4689 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4690 return 0;
4691
4692 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4693 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4694 | GUEST_INTR_STATE_NMI));
4695}
4696
78646121
GN		 4697static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4698{
b6b8a145
JK		 4699 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4700 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4701 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4702 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4703}
4704
cbc94022
IE		 4705static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4706{
4707 int ret;
4708 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4709 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4710 .guest_phys_addr = addr,
4711 .memory_size = PAGE_SIZE * 3,
4712 .flags = 0,
4713 };
4714
47ae31e2 4715 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4716 if (ret)
4717 return ret;
bfc6d222 4718 kvm->arch.tss_addr = addr;
93ea5388
GN		 4719 if (!init_rmode_tss(kvm))
4720 return -ENOMEM;
4721
cbc94022
IE		 4722 return 0;
4723}
4724
0ca1b4f4 4725static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4726{
77ab6db0 4727 switch (vec) {
77ab6db0 4728 case BP_VECTOR:
c573cd22
JK		 4729 /*
4730 * Update instruction length as we may reinject the exception
4731 * from user space while in guest debugging mode.
4732 */
4733 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4734 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4735 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4736 return false;
4737 /* fall through */
4738 case DB_VECTOR:
4739 if (vcpu->guest_debug &
4740 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4741 return false;
d0bfb940
JK		 4742 /* fall through */
4743 case DE_VECTOR:
77ab6db0
JK		 4744 case OF_VECTOR:
4745 case BR_VECTOR:
4746 case UD_VECTOR:
4747 case DF_VECTOR:
4748 case SS_VECTOR:
4749 case GP_VECTOR:
4750 case MF_VECTOR:
0ca1b4f4
GN		 4751 return true;
4752 break;
77ab6db0 4753 }
0ca1b4f4
GN		 4754 return false;
4755}
4756
4757static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4758 int vec, u32 err_code)
4759{
4760 /*
4761 * Instruction with address size override prefix opcode 0x67
4762 * Cause the #SS fault with 0 error code in VM86 mode.
4763 */
4764 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4765 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4766 if (vcpu->arch.halt_request) {
4767 vcpu->arch.halt_request = 0;
4768 return kvm_emulate_halt(vcpu);
4769 }
4770 return 1;
4771 }
4772 return 0;
4773 }
4774
4775 /*
4776 * Forward all other exceptions that are valid in real mode.
4777 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4778 * the required debugging infrastructure rework.
4779 */
4780 kvm_queue_exception(vcpu, vec);
4781 return 1;
6aa8b732
AK		 4782}
4783
a0861c02
AK		 4784/*
4785 * Trigger machine check on the host. We assume all the MSRs are already set up
4786 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4787 * We pass a fake environment to the machine check handler because we want
4788 * the guest to be always treated like user space, no matter what context
4789 * it used internally.
4790 */
4791static void kvm_machine_check(void)
4792{
4793#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4794 struct pt_regs regs = {
4795 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4796 .flags = X86_EFLAGS_IF,
4797 };
4798
4799 do_machine_check(&regs, 0);
4800#endif
4801}
4802
851ba692 4803static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4804{
4805 /* already handled by vcpu_run */
4806 return 1;
4807}
4808
851ba692 4809static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4810{
1155f76a 4811 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4812 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4813 u32 intr_info, ex_no, error_code;
42dbaa5a 4814 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4815 u32 vect_info;
4816 enum emulation_result er;
4817
1155f76a 4818 vect_info = vmx->idt_vectoring_info;
88786475 4819 intr_info = vmx->exit_intr_info;
6aa8b732 4820
a0861c02 4821 if (is_machine_check(intr_info))
851ba692 4822 return handle_machine_check(vcpu);
a0861c02 4823
e4a41889 4824 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4825 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4826
4827 if (is_no_device(intr_info)) {
5fd86fcf 4828 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4829 return 1;
4830 }
4831
7aa81cc0 4832 if (is_invalid_opcode(intr_info)) {
51d8b661 4833 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4834 if (er != EMULATE_DONE)
7ee5d940 4835 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4836 return 1;
4837 }
4838
6aa8b732 4839 error_code = 0;
2e11384c 4840 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4841 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4842
4843 /*
4844 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4845 * MMIO, it is better to report an internal error.
4846 * See the comments in vmx_handle_exit.
4847 */
4848 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4849 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4850 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4851 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4852 vcpu->run->internal.ndata = 2;
4853 vcpu->run->internal.data[0] = vect_info;
4854 vcpu->run->internal.data[1] = intr_info;
4855 return 0;
4856 }
4857
6aa8b732 4858 if (is_page_fault(intr_info)) {
1439442c 4859 /* EPT won't cause page fault directly */
cf3ace79 4860 BUG_ON(enable_ept);
6aa8b732 4861 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4862 trace_kvm_page_fault(cr2, error_code);
4863
3298b75c 4864 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4865 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4866 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4867 }
4868
d0bfb940 4869 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4870
4871 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4872 return handle_rmode_exception(vcpu, ex_no, error_code);
4873
42dbaa5a
JK		 4874 switch (ex_no) {
4875 case DB_VECTOR:
4876 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4877 if (!(vcpu->guest_debug &
4878 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4879 vcpu->arch.dr6 &= ~15;
4880 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4881 kvm_queue_exception(vcpu, DB_VECTOR);
4882 return 1;
4883 }
4884 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4885 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4886 /* fall through */
4887 case BP_VECTOR:
c573cd22
JK		 4888 /*
4889 * Update instruction length as we may reinject #BP from
4890 * user space while in guest debugging mode. Reading it for
4891 * #DB as well causes no harm, it is not used in that case.
4892 */
4893 vmx->vcpu.arch.event_exit_inst_len =
4894 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4895 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4896 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4897 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4898 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4899 break;
4900 default:
d0bfb940
JK		 4901 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4902 kvm_run->ex.exception = ex_no;
4903 kvm_run->ex.error_code = error_code;
42dbaa5a 4904 break;
6aa8b732 4905 }
6aa8b732
AK		 4906 return 0;
4907}
4908
851ba692 4909static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4910{
1165f5fe 4911 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4912 return 1;
4913}
4914
851ba692 4915static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4916{
851ba692 4917 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4918 return 0;
4919}
6aa8b732 4920
851ba692 4921static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4922{
bfdaab09 4923 unsigned long exit_qualification;
34c33d16 4924 int size, in, string;
039576c0 4925 unsigned port;
6aa8b732 4926
bfdaab09 4927 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4928 string = (exit_qualification & 16) != 0;
cf8f70bf 4929 in = (exit_qualification & 8) != 0;
e70669ab 4930
cf8f70bf 4931 ++vcpu->stat.io_exits;
e70669ab 4932
cf8f70bf 4933 if (string || in)
51d8b661 4934 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4935
cf8f70bf
GN		 4936 port = exit_qualification >> 16;
4937 size = (exit_qualification & 7) + 1;
e93f36bc 4938 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4939
4940 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4941}
4942
102d8325
IM		 4943static void
4944vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4945{
4946 /*
4947 * Patch in the VMCALL instruction:
4948 */
4949 hypercall[0] = 0x0f;
4950 hypercall[1] = 0x01;
4951 hypercall[2] = 0xc1;
102d8325
IM		 4952}
4953
92fbc7b1
JK		 4954static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4955{
4956 unsigned long always_on = VMXON_CR0_ALWAYSON;
4957
4958 if (nested_vmx_secondary_ctls_high &
4959 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4960 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4961 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4962 return (val & always_on) == always_on;
4963}
4964
0fa06071 4965/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4966static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4967{
eeadf9e7 4968 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4969 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4970 unsigned long orig_val = val;
4971
eeadf9e7
NHE		 4972 /*
4973 * We get here when L2 changed cr0 in a way that did not change
4974 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4975 * but did change L0 shadowed bits. So we first calculate the
4976 * effective cr0 value that L1 would like to write into the
4977 * hardware. It consists of the L2-owned bits from the new
4978 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4979 */
1a0d74e6
JK		 4980 val = (val & ~vmcs12->cr0_guest_host_mask) |
4981 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4982
92fbc7b1 4983 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4984 return 1;
1a0d74e6
JK		 4985
4986 if (kvm_set_cr0(vcpu, val))
4987 return 1;
4988 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4989 return 0;
1a0d74e6
JK		 4990 } else {
4991 if (to_vmx(vcpu)->nested.vmxon &&
4992 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4993 return 1;
eeadf9e7 4994 return kvm_set_cr0(vcpu, val);
1a0d74e6 4995 }
eeadf9e7
NHE		 4996}
4997
4998static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4999{
5000 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5001 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5002 unsigned long orig_val = val;
5003
5004 /* analogously to handle_set_cr0 */
5005 val = (val & ~vmcs12->cr4_guest_host_mask) |
5006 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5007 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5008 return 1;
1a0d74e6 5009 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5010 return 0;
5011 } else
5012 return kvm_set_cr4(vcpu, val);
5013}
5014
5015/* called to set cr0 as approriate for clts instruction exit. */
5016static void handle_clts(struct kvm_vcpu *vcpu)
5017{
5018 if (is_guest_mode(vcpu)) {
5019 /*
5020 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5021 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5022 * just pretend it's off (also in arch.cr0 for fpu_activate).
5023 */
5024 vmcs_writel(CR0_READ_SHADOW,
5025 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5026 vcpu->arch.cr0 &= ~X86_CR0_TS;
5027 } else
5028 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5029}
5030
851ba692 5031static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5032{
229456fc 5033 unsigned long exit_qualification, val;
6aa8b732
AK		 5034 int cr;
5035 int reg;
49a9b07e 5036 int err;
6aa8b732 5037
bfdaab09 5038 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5039 cr = exit_qualification & 15;
5040 reg = (exit_qualification >> 8) & 15;
5041 switch ((exit_qualification >> 4) & 3) {
5042 case 0: /* mov to cr */
229456fc
MT		 5043 val = kvm_register_read(vcpu, reg);
5044 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5045 switch (cr) {
5046 case 0:
eeadf9e7 5047 err = handle_set_cr0(vcpu, val);
db8fcefa 5048 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5049 return 1;
5050 case 3:
2390218b 5051 err = kvm_set_cr3(vcpu, val);
db8fcefa 5052 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5053 return 1;
5054 case 4:
eeadf9e7 5055 err = handle_set_cr4(vcpu, val);
db8fcefa 5056 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5057 return 1;
0a5fff19
GN		 5058 case 8: {
5059 u8 cr8_prev = kvm_get_cr8(vcpu);
5060 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5061 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5062 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5063 if (irqchip_in_kernel(vcpu->kvm))
5064 return 1;
5065 if (cr8_prev <= cr8)
5066 return 1;
851ba692 5067 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5068 return 0;
5069 }
4b8073e4 5070 }
6aa8b732 5071 break;
25c4c276 5072 case 2: /* clts */
eeadf9e7 5073 handle_clts(vcpu);
4d4ec087 5074 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5075 skip_emulated_instruction(vcpu);
6b52d186 5076 vmx_fpu_activate(vcpu);
25c4c276 5077 return 1;
6aa8b732
AK		 5078 case 1: /*mov from cr*/
5079 switch (cr) {
5080 case 3:
9f8fe504
AK		 5081 val = kvm_read_cr3(vcpu);
5082 kvm_register_write(vcpu, reg, val);
5083 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5084 skip_emulated_instruction(vcpu);
5085 return 1;
5086 case 8:
229456fc
MT		 5087 val = kvm_get_cr8(vcpu);
5088 kvm_register_write(vcpu, reg, val);
5089 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5090 skip_emulated_instruction(vcpu);
5091 return 1;
5092 }
5093 break;
5094 case 3: /* lmsw */
a1f83a74 5095 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5096 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5097 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5098
5099 skip_emulated_instruction(vcpu);
5100 return 1;
5101 default:
5102 break;
5103 }
851ba692 5104 vcpu->run->exit_reason = 0;
a737f256 5105 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5106 (int)(exit_qualification >> 4) & 3, cr);
5107 return 0;
5108}
5109
851ba692 5110static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5111{
bfdaab09 5112 unsigned long exit_qualification;
6aa8b732
AK		 5113 int dr, reg;
5114
f2483415 5115 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5116 if (!kvm_require_cpl(vcpu, 0))
5117 return 1;
42dbaa5a
JK		 5118 dr = vmcs_readl(GUEST_DR7);
5119 if (dr & DR7_GD) {
5120 /*
5121 * As the vm-exit takes precedence over the debug trap, we
5122 * need to emulate the latter, either for the host or the
5123 * guest debugging itself.
5124 */
5125 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5126 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5127 vcpu->run->debug.arch.dr7 = dr;
5128 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5129 vmcs_readl(GUEST_CS_BASE) +
5130 vmcs_readl(GUEST_RIP);
851ba692
AK		 5131 vcpu->run->debug.arch.exception = DB_VECTOR;
5132 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5133 return 0;
5134 } else {
5135 vcpu->arch.dr7 &= ~DR7_GD;
5136 vcpu->arch.dr6 |= DR6_BD;
5137 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5138 kvm_queue_exception(vcpu, DB_VECTOR);
5139 return 1;
5140 }
5141 }
5142
81908bf4
PB		 5143 if (vcpu->guest_debug == 0) {
5144 u32 cpu_based_vm_exec_control;
5145
5146 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5147 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5148 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5149
5150 /*
5151 * No more DR vmexits; force a reload of the debug registers
5152 * and reenter on this instruction. The next vmexit will
5153 * retrieve the full state of the debug registers.
5154 */
5155 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5156 return 1;
5157 }
5158
bfdaab09 5159 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5160 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5161 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5162 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5163 unsigned long val;
4c4d563b
JK		 5164
5165 if (kvm_get_dr(vcpu, dr, &val))
5166 return 1;
5167 kvm_register_write(vcpu, reg, val);
020df079 5168 } else
4c4d563b
JK		 5169 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5170 return 1;
5171
6aa8b732
AK		 5172 skip_emulated_instruction(vcpu);
5173 return 1;
5174}
5175
73aaf249
JK		 5176static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5177{
5178 return vcpu->arch.dr6;
5179}
5180
5181static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5182{
5183}
5184
81908bf4
PB		 5185static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5186{
5187 u32 cpu_based_vm_exec_control;
5188
5189 get_debugreg(vcpu->arch.db[0], 0);
5190 get_debugreg(vcpu->arch.db[1], 1);
5191 get_debugreg(vcpu->arch.db[2], 2);
5192 get_debugreg(vcpu->arch.db[3], 3);
5193 get_debugreg(vcpu->arch.dr6, 6);
5194 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5195
5196 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5197
5198 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5199 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5200 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5201}
5202
020df079
GN		 5203static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5204{
5205 vmcs_writel(GUEST_DR7, val);
5206}
5207
851ba692 5208static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5209{
06465c5a
AK		 5210 kvm_emulate_cpuid(vcpu);
5211 return 1;
6aa8b732
AK		 5212}
5213
851ba692 5214static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5215{
ad312c7c 5216 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5217 u64 data;
5218
5219 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5220 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5221 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5222 return 1;
5223 }
5224
229456fc 5225 trace_kvm_msr_read(ecx, data);
2714d1d3 5226
6aa8b732 5227 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5228 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5229 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5230 skip_emulated_instruction(vcpu);
5231 return 1;
5232}
5233
851ba692 5234static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5235{
8fe8ab46 5236 struct msr_data msr;
ad312c7c
ZX		 5237 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5238 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5239 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5240
8fe8ab46
WA		 5241 msr.data = data;
5242 msr.index = ecx;
5243 msr.host_initiated = false;
5244 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5245 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5246 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5247 return 1;
5248 }
5249
59200273 5250 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5251 skip_emulated_instruction(vcpu);
5252 return 1;
5253}
5254
851ba692 5255static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5256{
3842d135 5257 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5258 return 1;
5259}
5260
851ba692 5261static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5262{
85f455f7
ED		 5263 u32 cpu_based_vm_exec_control;
5264
5265 /* clear pending irq */
5266 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5267 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5268 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5269
3842d135
AK		 5270 kvm_make_request(KVM_REQ_EVENT, vcpu);
5271
a26bf12a 5272 ++vcpu->stat.irq_window_exits;
2714d1d3 5273
c1150d8c
DL		 5274 /*
5275 * If the user space waits to inject interrupts, exit as soon as
5276 * possible
5277 */
8061823a 5278 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5279 vcpu->run->request_interrupt_window &&
8061823a 5280 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5281 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5282 return 0;
5283 }
6aa8b732
AK		 5284 return 1;
5285}
5286
851ba692 5287static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5288{
5289 skip_emulated_instruction(vcpu);
d3bef15f 5290 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5291}
5292
851ba692 5293static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5294{
510043da 5295 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5296 kvm_emulate_hypercall(vcpu);
5297 return 1;
c21415e8
IM		 5298}
5299
ec25d5e6
GN		 5300static int handle_invd(struct kvm_vcpu *vcpu)
5301{
51d8b661 5302 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5303}
5304
851ba692 5305static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5306{
f9c617f6 5307 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5308
5309 kvm_mmu_invlpg(vcpu, exit_qualification);
5310 skip_emulated_instruction(vcpu);
5311 return 1;
5312}
5313
fee84b07
AK		 5314static int handle_rdpmc(struct kvm_vcpu *vcpu)
5315{
5316 int err;
5317
5318 err = kvm_rdpmc(vcpu);
5319 kvm_complete_insn_gp(vcpu, err);
5320
5321 return 1;
5322}
5323
851ba692 5324static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5325{
5326 skip_emulated_instruction(vcpu);
f5f48ee1 5327 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5328 return 1;
5329}
5330
2acf923e
DC		 5331static int handle_xsetbv(struct kvm_vcpu *vcpu)
5332{
5333 u64 new_bv = kvm_read_edx_eax(vcpu);
5334 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5335
5336 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5337 skip_emulated_instruction(vcpu);
5338 return 1;
5339}
5340
851ba692 5341static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5342{
58fbbf26
KT		 5343 if (likely(fasteoi)) {
5344 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5345 int access_type, offset;
5346
5347 access_type = exit_qualification & APIC_ACCESS_TYPE;
5348 offset = exit_qualification & APIC_ACCESS_OFFSET;
5349 /*
5350 * Sane guest uses MOV to write EOI, with written value
5351 * not cared. So make a short-circuit here by avoiding
5352 * heavy instruction emulation.
5353 */
5354 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5355 (offset == APIC_EOI)) {
5356 kvm_lapic_set_eoi(vcpu);
5357 skip_emulated_instruction(vcpu);
5358 return 1;
5359 }
5360 }
51d8b661 5361 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5362}
5363
c7c9c56c
YZ		 5364static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5365{
5366 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5367 int vector = exit_qualification & 0xff;
5368
5369 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5370 kvm_apic_set_eoi_accelerated(vcpu, vector);
5371 return 1;
5372}
5373
83d4c286
YZ		 5374static int handle_apic_write(struct kvm_vcpu *vcpu)
5375{
5376 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5377 u32 offset = exit_qualification & 0xfff;
5378
5379 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5380 kvm_apic_write_nodecode(vcpu, offset);
5381 return 1;
5382}
5383
851ba692 5384static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5385{
60637aac 5386 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5387 unsigned long exit_qualification;
e269fb21
JK		 5388 bool has_error_code = false;
5389 u32 error_code = 0;
37817f29 5390 u16 tss_selector;
7f3d35fd 5391 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5392
5393 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5394 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5395 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5396
5397 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5398
5399 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5400 if (reason == TASK_SWITCH_GATE && idt_v) {
5401 switch (type) {
5402 case INTR_TYPE_NMI_INTR:
5403 vcpu->arch.nmi_injected = false;
654f06fc 5404 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5405 break;
5406 case INTR_TYPE_EXT_INTR:
66fd3f7f 5407 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5408 kvm_clear_interrupt_queue(vcpu);
5409 break;
5410 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5411 if (vmx->idt_vectoring_info &
5412 VECTORING_INFO_DELIVER_CODE_MASK) {
5413 has_error_code = true;
5414 error_code =
5415 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5416 }
5417 /* fall through */
64a7ec06
GN		 5418 case INTR_TYPE_SOFT_EXCEPTION:
5419 kvm_clear_exception_queue(vcpu);
5420 break;
5421 default:
5422 break;
5423 }
60637aac 5424 }
37817f29
IE		 5425 tss_selector = exit_qualification;
5426
64a7ec06
GN		 5427 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5428 type != INTR_TYPE_EXT_INTR &&
5429 type != INTR_TYPE_NMI_INTR))
5430 skip_emulated_instruction(vcpu);
5431
7f3d35fd
KW		 5432 if (kvm_task_switch(vcpu, tss_selector,
5433 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5434 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5435 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5436 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5437 vcpu->run->internal.ndata = 0;
42dbaa5a 5438 return 0;
acb54517 5439 }
42dbaa5a
JK		 5440
5441 /* clear all local breakpoint enable flags */
5442 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5443
5444 /*
5445 * TODO: What about debug traps on tss switch?
5446 * Are we supposed to inject them and update dr6?
5447 */
5448
5449 return 1;
37817f29
IE		 5450}
5451
851ba692 5452static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5453{
f9c617f6 5454 unsigned long exit_qualification;
1439442c 5455 gpa_t gpa;
4f5982a5 5456 u32 error_code;
1439442c 5457 int gla_validity;
1439442c 5458
f9c617f6 5459 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5460
1439442c
SY		 5461 gla_validity = (exit_qualification >> 7) & 0x3;
5462 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5463 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5464 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5465 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5466 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5467 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5468 (long unsigned int)exit_qualification);
851ba692
AK		 5469 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5470 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5471 return 0;
1439442c
SY		 5472 }
5473
0be9c7a8
GN		 5474 /*
5475 * EPT violation happened while executing iret from NMI,
5476 * "blocked by NMI" bit has to be set before next VM entry.
5477 * There are errata that may cause this bit to not be set:
5478 * AAK134, BY25.
5479 */
bcd1c294
GN		 5480 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5481 cpu_has_virtual_nmis() &&
5482 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5483 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5484
1439442c 5485 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5486 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5487
5488 /* It is a write fault? */
5489 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5490 /* It is a fetch fault? */
5491 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5492 /* ept page table is present? */
5493 error_code |= (exit_qualification >> 3) & 0x1;
5494
25d92081
YZ		 5495 vcpu->arch.exit_qualification = exit_qualification;
5496
4f5982a5 5497 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5498}
5499
68f89400
MT		 5500static u64 ept_rsvd_mask(u64 spte, int level)
5501{
5502 int i;
5503 u64 mask = 0;
5504
5505 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5506 mask |= (1ULL << i);
5507
5508 if (level > 2)
5509 /* bits 7:3 reserved */
5510 mask |= 0xf8;
5511 else if (level == 2) {
5512 if (spte & (1ULL << 7))
5513 /* 2MB ref, bits 20:12 reserved */
5514 mask |= 0x1ff000;
5515 else
5516 /* bits 6:3 reserved */
5517 mask |= 0x78;
5518 }
5519
5520 return mask;
5521}
5522
5523static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5524 int level)
5525{
5526 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5527
5528 /* 010b (write-only) */
5529 WARN_ON((spte & 0x7) == 0x2);
5530
5531 /* 110b (write/execute) */
5532 WARN_ON((spte & 0x7) == 0x6);
5533
5534 /* 100b (execute-only) and value not supported by logical processor */
5535 if (!cpu_has_vmx_ept_execute_only())
5536 WARN_ON((spte & 0x7) == 0x4);
5537
5538 /* not 000b */
5539 if ((spte & 0x7)) {
5540 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5541
5542 if (rsvd_bits != 0) {
5543 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5544 __func__, rsvd_bits);
5545 WARN_ON(1);
5546 }
5547
5548 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5549 u64 ept_mem_type = (spte & 0x38) >> 3;
5550
5551 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5552 ept_mem_type == 7) {
5553 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5554 __func__, ept_mem_type);
5555 WARN_ON(1);
5556 }
5557 }
5558 }
5559}
5560
851ba692 5561static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5562{
5563 u64 sptes[4];
ce88decf 5564 int nr_sptes, i, ret;
68f89400
MT		 5565 gpa_t gpa;
5566
5567 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5568
ce88decf 5569 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5570 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5571 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5572 EMULATE_DONE;
f8f55942
XG		 5573
5574 if (unlikely(ret == RET_MMIO_PF_INVALID))
5575 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5576
b37fbea6 5577 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5578 return 1;
5579
5580 /* It is the real ept misconfig */
68f89400
MT		 5581 printk(KERN_ERR "EPT: Misconfiguration.\n");
5582 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5583
5584 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5585
5586 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5587 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5588
851ba692
AK		 5589 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5590 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5591
5592 return 0;
5593}
5594
851ba692 5595static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5596{
5597 u32 cpu_based_vm_exec_control;
5598
5599 /* clear pending NMI */
5600 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5601 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5602 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5603 ++vcpu->stat.nmi_window_exits;
3842d135 5604 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5605
5606 return 1;
5607}
5608
80ced186 5609static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5610{
8b3079a5
AK		 5611 struct vcpu_vmx *vmx = to_vmx(vcpu);
5612 enum emulation_result err = EMULATE_DONE;
80ced186 5613 int ret = 1;
49e9d557
AK		 5614 u32 cpu_exec_ctrl;
5615 bool intr_window_requested;
b8405c18 5616 unsigned count = 130;
49e9d557
AK		 5617
5618 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5619 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5620
b8405c18 5621 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5622 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5623 return handle_interrupt_window(&vmx->vcpu);
5624
de87dcdd
AK		 5625 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5626 return 1;
5627
991eebf9 5628 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5629
ac0a48c3 5630 if (err == EMULATE_USER_EXIT) {
94452b9e 5631 ++vcpu->stat.mmio_exits;
80ced186
MG		 5632 ret = 0;
5633 goto out;
5634 }
1d5a4d9b 5635
de5f70e0
AK		 5636 if (err != EMULATE_DONE) {
5637 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5638 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5639 vcpu->run->internal.ndata = 0;
6d77dbfc 5640 return 0;
de5f70e0 5641 }
ea953ef0 5642
8d76c49e
GN		 5643 if (vcpu->arch.halt_request) {
5644 vcpu->arch.halt_request = 0;
5645 ret = kvm_emulate_halt(vcpu);
5646 goto out;
5647 }
5648
ea953ef0 5649 if (signal_pending(current))
80ced186 5650 goto out;
ea953ef0
MG		 5651 if (need_resched())
5652 schedule();
5653 }
5654
14168786 5655 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5656out:
5657 return ret;
ea953ef0
MG		 5658}
5659
4b8d54f9
ZE		 5660/*
5661 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5662 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5663 */
9fb41ba8 5664static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5665{
5666 skip_emulated_instruction(vcpu);
5667 kvm_vcpu_on_spin(vcpu);
5668
5669 return 1;
5670}
5671
59708670
SY		 5672static int handle_invalid_op(struct kvm_vcpu *vcpu)
5673{
5674 kvm_queue_exception(vcpu, UD_VECTOR);
5675 return 1;
5676}
5677
ff2f6fe9
NHE		 5678/*
5679 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5680 * We could reuse a single VMCS for all the L2 guests, but we also want the
5681 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5682 * allows keeping them loaded on the processor, and in the future will allow
5683 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5684 * every entry if they never change.
5685 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5686 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5687 *
5688 * The following functions allocate and free a vmcs02 in this pool.
5689 */
5690
5691/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5692static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5693{
5694 struct vmcs02_list *item;
5695 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5696 if (item->vmptr == vmx->nested.current_vmptr) {
5697 list_move(&item->list, &vmx->nested.vmcs02_pool);
5698 return &item->vmcs02;
5699 }
5700
5701 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5702 /* Recycle the least recently used VMCS. */
5703 item = list_entry(vmx->nested.vmcs02_pool.prev,
5704 struct vmcs02_list, list);
5705 item->vmptr = vmx->nested.current_vmptr;
5706 list_move(&item->list, &vmx->nested.vmcs02_pool);
5707 return &item->vmcs02;
5708 }
5709
5710 /* Create a new VMCS */
0fa24ce3 5711 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5712 if (!item)
5713 return NULL;
5714 item->vmcs02.vmcs = alloc_vmcs();
5715 if (!item->vmcs02.vmcs) {
5716 kfree(item);
5717 return NULL;
5718 }
5719 loaded_vmcs_init(&item->vmcs02);
5720 item->vmptr = vmx->nested.current_vmptr;
5721 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5722 vmx->nested.vmcs02_num++;
5723 return &item->vmcs02;
5724}
5725
5726/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5727static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5728{
5729 struct vmcs02_list *item;
5730 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5731 if (item->vmptr == vmptr) {
5732 free_loaded_vmcs(&item->vmcs02);
5733 list_del(&item->list);
5734 kfree(item);
5735 vmx->nested.vmcs02_num--;
5736 return;
5737 }
5738}
5739
5740/*
5741 * Free all VMCSs saved for this vcpu, except the one pointed by
5742 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5743 * currently used, if running L2), and vmcs01 when running L2.
5744 */
5745static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5746{
5747 struct vmcs02_list *item, *n;
5748 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5749 if (vmx->loaded_vmcs != &item->vmcs02)
5750 free_loaded_vmcs(&item->vmcs02);
5751 list_del(&item->list);
5752 kfree(item);
5753 }
5754 vmx->nested.vmcs02_num = 0;
5755
5756 if (vmx->loaded_vmcs != &vmx->vmcs01)
5757 free_loaded_vmcs(&vmx->vmcs01);
5758}
5759
0658fbaa
ACL		 5760/*
5761 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5762 * set the success or error code of an emulated VMX instruction, as specified
5763 * by Vol 2B, VMX Instruction Reference, "Conventions".
5764 */
5765static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5766{
5767 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5768 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5769 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5770}
5771
5772static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5773{
5774 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5775 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5776 X86_EFLAGS_SF | X86_EFLAGS_OF))
5777 | X86_EFLAGS_CF);
5778}
5779
145c28dd 5780static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5781 u32 vm_instruction_error)
5782{
5783 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5784 /*
5785 * failValid writes the error number to the current VMCS, which
5786 * can't be done there isn't a current VMCS.
5787 */
5788 nested_vmx_failInvalid(vcpu);
5789 return;
5790 }
5791 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5792 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5793 X86_EFLAGS_SF | X86_EFLAGS_OF))
5794 | X86_EFLAGS_ZF);
5795 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5796 /*
5797 * We don't need to force a shadow sync because
5798 * VM_INSTRUCTION_ERROR is not shadowed
5799 */
5800}
145c28dd 5801
f4124500
JK		 5802static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5803{
5804 struct vcpu_vmx *vmx =
5805 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5806
5807 vmx->nested.preemption_timer_expired = true;
5808 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5809 kvm_vcpu_kick(&vmx->vcpu);
5810
5811 return HRTIMER_NORESTART;
5812}
5813
ec378aee
NHE		 5814/*
5815 * Emulate the VMXON instruction.
5816 * Currently, we just remember that VMX is active, and do not save or even
5817 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5818 * do not currently need to store anything in that guest-allocated memory
5819 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5820 * argument is different from the VMXON pointer (which the spec says they do).
5821 */
5822static int handle_vmon(struct kvm_vcpu *vcpu)
5823{
5824 struct kvm_segment cs;
5825 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5826 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5827 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5828 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5829
5830 /* The Intel VMX Instruction Reference lists a bunch of bits that
5831 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5832 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5833 * Otherwise, we should fail with #UD. We test these now:
5834 */
5835 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5836 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5837 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5838 kvm_queue_exception(vcpu, UD_VECTOR);
5839 return 1;
5840 }
5841
5842 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5843 if (is_long_mode(vcpu) && !cs.l) {
5844 kvm_queue_exception(vcpu, UD_VECTOR);
5845 return 1;
5846 }
5847
5848 if (vmx_get_cpl(vcpu)) {
5849 kvm_inject_gp(vcpu, 0);
5850 return 1;
5851 }
145c28dd
AG		 5852 if (vmx->nested.vmxon) {
5853 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5854 skip_emulated_instruction(vcpu);
5855 return 1;
5856 }
b3897a49
NHE		 5857
5858 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5859 != VMXON_NEEDED_FEATURES) {
5860 kvm_inject_gp(vcpu, 0);
5861 return 1;
5862 }
5863
8de48833
AG		 5864 if (enable_shadow_vmcs) {
5865 shadow_vmcs = alloc_vmcs();
5866 if (!shadow_vmcs)
5867 return -ENOMEM;
5868 /* mark vmcs as shadow */
5869 shadow_vmcs->revision_id |= (1u << 31);
5870 /* init shadow vmcs */
5871 vmcs_clear(shadow_vmcs);
5872 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5873 }
ec378aee 5874
ff2f6fe9
NHE		 5875 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5876 vmx->nested.vmcs02_num = 0;
5877
f4124500
JK		 5878 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5879 HRTIMER_MODE_REL);
5880 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5881
ec378aee
NHE		 5882 vmx->nested.vmxon = true;
5883
5884 skip_emulated_instruction(vcpu);
a25eb114 5885 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5886 return 1;
5887}
5888
5889/*
5890 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5891 * for running VMX instructions (except VMXON, whose prerequisites are
5892 * slightly different). It also specifies what exception to inject otherwise.
5893 */
5894static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5895{
5896 struct kvm_segment cs;
5897 struct vcpu_vmx *vmx = to_vmx(vcpu);
5898
5899 if (!vmx->nested.vmxon) {
5900 kvm_queue_exception(vcpu, UD_VECTOR);
5901 return 0;
5902 }
5903
5904 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5905 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5906 (is_long_mode(vcpu) && !cs.l)) {
5907 kvm_queue_exception(vcpu, UD_VECTOR);
5908 return 0;
5909 }
5910
5911 if (vmx_get_cpl(vcpu)) {
5912 kvm_inject_gp(vcpu, 0);
5913 return 0;
5914 }
5915
5916 return 1;
5917}
5918
e7953d7f
AG		 5919static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5920{
8a1b9dd0 5921 u32 exec_control;
012f83cb
AG		 5922 if (enable_shadow_vmcs) {
5923 if (vmx->nested.current_vmcs12 != NULL) {
5924 /* copy to memory all shadowed fields in case
5925 they were modified */
5926 copy_shadow_to_vmcs12(vmx);
5927 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5928 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5929 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5930 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5931 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5932 }
5933 }
e7953d7f
AG		 5934 kunmap(vmx->nested.current_vmcs12_page);
5935 nested_release_page(vmx->nested.current_vmcs12_page);
5936}
5937
ec378aee
NHE		 5938/*
5939 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5940 * just stops using VMX.
5941 */
5942static void free_nested(struct vcpu_vmx *vmx)
5943{
5944 if (!vmx->nested.vmxon)
5945 return;
5946 vmx->nested.vmxon = false;
a9d30f33 5947 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5948 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5949 vmx->nested.current_vmptr = -1ull;
5950 vmx->nested.current_vmcs12 = NULL;
5951 }
e7953d7f
AG		 5952 if (enable_shadow_vmcs)
5953 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5954 /* Unpin physical memory we referred to in current vmcs02 */
5955 if (vmx->nested.apic_access_page) {
5956 nested_release_page(vmx->nested.apic_access_page);
5957 vmx->nested.apic_access_page = 0;
5958 }
ff2f6fe9
NHE		 5959
5960 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5961}
5962
5963/* Emulate the VMXOFF instruction */
5964static int handle_vmoff(struct kvm_vcpu *vcpu)
5965{
5966 if (!nested_vmx_check_permission(vcpu))
5967 return 1;
5968 free_nested(to_vmx(vcpu));
5969 skip_emulated_instruction(vcpu);
a25eb114 5970 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5971 return 1;
5972}
5973
064aea77
NHE		 5974/*
5975 * Decode the memory-address operand of a vmx instruction, as recorded on an
5976 * exit caused by such an instruction (run by a guest hypervisor).
5977 * On success, returns 0. When the operand is invalid, returns 1 and throws
5978 * #UD or #GP.
5979 */
5980static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5981 unsigned long exit_qualification,
5982 u32 vmx_instruction_info, gva_t *ret)
5983{
5984 /*
5985 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5986 * Execution", on an exit, vmx_instruction_info holds most of the
5987 * addressing components of the operand. Only the displacement part
5988 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5989 * For how an actual address is calculated from all these components,
5990 * refer to Vol. 1, "Operand Addressing".
5991 */
5992 int scaling = vmx_instruction_info & 3;
5993 int addr_size = (vmx_instruction_info >> 7) & 7;
5994 bool is_reg = vmx_instruction_info & (1u << 10);
5995 int seg_reg = (vmx_instruction_info >> 15) & 7;
5996 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5997 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5998 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5999 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6000
6001 if (is_reg) {
6002 kvm_queue_exception(vcpu, UD_VECTOR);
6003 return 1;
6004 }
6005
6006 /* Addr = segment_base + offset */
6007 /* offset = base + [index * scale] + displacement */
6008 *ret = vmx_get_segment_base(vcpu, seg_reg);
6009 if (base_is_valid)
6010 *ret += kvm_register_read(vcpu, base_reg);
6011 if (index_is_valid)
6012 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6013 *ret += exit_qualification; /* holds the displacement */
6014
6015 if (addr_size == 1) /* 32 bit */
6016 *ret &= 0xffffffff;
6017
6018 /*
6019 * TODO: throw #GP (and return 1) in various cases that the VM*
6020 * instructions require it - e.g., offset beyond segment limit,
6021 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6022 * address, and so on. Currently these are not checked.
6023 */
6024 return 0;
6025}
6026
27d6c865
NHE		 6027/* Emulate the VMCLEAR instruction */
6028static int handle_vmclear(struct kvm_vcpu *vcpu)
6029{
6030 struct vcpu_vmx *vmx = to_vmx(vcpu);
6031 gva_t gva;
6032 gpa_t vmptr;
6033 struct vmcs12 *vmcs12;
6034 struct page *page;
6035 struct x86_exception e;
6036
6037 if (!nested_vmx_check_permission(vcpu))
6038 return 1;
6039
6040 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6041 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6042 return 1;
6043
6044 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6045 sizeof(vmptr), &e)) {
6046 kvm_inject_page_fault(vcpu, &e);
6047 return 1;
6048 }
6049
6050 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6051 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6052 skip_emulated_instruction(vcpu);
6053 return 1;
6054 }
6055
6056 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6057 nested_release_vmcs12(vmx);
27d6c865
NHE		 6058 vmx->nested.current_vmptr = -1ull;
6059 vmx->nested.current_vmcs12 = NULL;
6060 }
6061
6062 page = nested_get_page(vcpu, vmptr);
6063 if (page == NULL) {
6064 /*
6065 * For accurate processor emulation, VMCLEAR beyond available
6066 * physical memory should do nothing at all. However, it is
6067 * possible that a nested vmx bug, not a guest hypervisor bug,
6068 * resulted in this case, so let's shut down before doing any
6069 * more damage:
6070 */
6071 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6072 return 1;
6073 }
6074 vmcs12 = kmap(page);
6075 vmcs12->launch_state = 0;
6076 kunmap(page);
6077 nested_release_page(page);
6078
6079 nested_free_vmcs02(vmx, vmptr);
6080
6081 skip_emulated_instruction(vcpu);
6082 nested_vmx_succeed(vcpu);
6083 return 1;
6084}
6085
cd232ad0
NHE		 6086static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6087
6088/* Emulate the VMLAUNCH instruction */
6089static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6090{
6091 return nested_vmx_run(vcpu, true);
6092}
6093
6094/* Emulate the VMRESUME instruction */
6095static int handle_vmresume(struct kvm_vcpu *vcpu)
6096{
6097
6098 return nested_vmx_run(vcpu, false);
6099}
6100
49f705c5
NHE		 6101enum vmcs_field_type {
6102 VMCS_FIELD_TYPE_U16 = 0,
6103 VMCS_FIELD_TYPE_U64 = 1,
6104 VMCS_FIELD_TYPE_U32 = 2,
6105 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6106};
6107
6108static inline int vmcs_field_type(unsigned long field)
6109{
6110 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6111 return VMCS_FIELD_TYPE_U32;
6112 return (field >> 13) & 0x3 ;
6113}
6114
6115static inline int vmcs_field_readonly(unsigned long field)
6116{
6117 return (((field >> 10) & 0x3) == 1);
6118}
6119
6120/*
6121 * Read a vmcs12 field. Since these can have varying lengths and we return
6122 * one type, we chose the biggest type (u64) and zero-extend the return value
6123 * to that size. Note that the caller, handle_vmread, might need to use only
6124 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6125 * 64-bit fields are to be returned).
6126 */
6127static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6128 unsigned long field, u64 *ret)
6129{
6130 short offset = vmcs_field_to_offset(field);
6131 char *p;
6132
6133 if (offset < 0)
6134 return 0;
6135
6136 p = ((char *)(get_vmcs12(vcpu))) + offset;
6137
6138 switch (vmcs_field_type(field)) {
6139 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6140 *ret = *((natural_width *)p);
6141 return 1;
6142 case VMCS_FIELD_TYPE_U16:
6143 *ret = *((u16 *)p);
6144 return 1;
6145 case VMCS_FIELD_TYPE_U32:
6146 *ret = *((u32 *)p);
6147 return 1;
6148 case VMCS_FIELD_TYPE_U64:
6149 *ret = *((u64 *)p);
6150 return 1;
6151 default:
6152 return 0; /* can never happen. */
6153 }
6154}
6155
20b97fea
AG		 6156
6157static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6158 unsigned long field, u64 field_value){
6159 short offset = vmcs_field_to_offset(field);
6160 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6161 if (offset < 0)
6162 return false;
6163
6164 switch (vmcs_field_type(field)) {
6165 case VMCS_FIELD_TYPE_U16:
6166 *(u16 *)p = field_value;
6167 return true;
6168 case VMCS_FIELD_TYPE_U32:
6169 *(u32 *)p = field_value;
6170 return true;
6171 case VMCS_FIELD_TYPE_U64:
6172 *(u64 *)p = field_value;
6173 return true;
6174 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6175 *(natural_width *)p = field_value;
6176 return true;
6177 default:
6178 return false; /* can never happen. */
6179 }
6180
6181}
6182
16f5b903
AG		 6183static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6184{
6185 int i;
6186 unsigned long field;
6187 u64 field_value;
6188 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6189 const unsigned long *fields = shadow_read_write_fields;
6190 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6191
6192 vmcs_load(shadow_vmcs);
6193
6194 for (i = 0; i < num_fields; i++) {
6195 field = fields[i];
6196 switch (vmcs_field_type(field)) {
6197 case VMCS_FIELD_TYPE_U16:
6198 field_value = vmcs_read16(field);
6199 break;
6200 case VMCS_FIELD_TYPE_U32:
6201 field_value = vmcs_read32(field);
6202 break;
6203 case VMCS_FIELD_TYPE_U64:
6204 field_value = vmcs_read64(field);
6205 break;
6206 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6207 field_value = vmcs_readl(field);
6208 break;
6209 }
6210 vmcs12_write_any(&vmx->vcpu, field, field_value);
6211 }
6212
6213 vmcs_clear(shadow_vmcs);
6214 vmcs_load(vmx->loaded_vmcs->vmcs);
6215}
6216
c3114420
AG		 6217static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6218{
c2bae893
MK		 6219 const unsigned long *fields[] = {
6220 shadow_read_write_fields,
6221 shadow_read_only_fields
c3114420 6222 };
c2bae893 6223 const int max_fields[] = {
c3114420
AG		 6224 max_shadow_read_write_fields,
6225 max_shadow_read_only_fields
6226 };
6227 int i, q;
6228 unsigned long field;
6229 u64 field_value = 0;
6230 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6231
6232 vmcs_load(shadow_vmcs);
6233
c2bae893 6234 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6235 for (i = 0; i < max_fields[q]; i++) {
6236 field = fields[q][i];
6237 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6238
6239 switch (vmcs_field_type(field)) {
6240 case VMCS_FIELD_TYPE_U16:
6241 vmcs_write16(field, (u16)field_value);
6242 break;
6243 case VMCS_FIELD_TYPE_U32:
6244 vmcs_write32(field, (u32)field_value);
6245 break;
6246 case VMCS_FIELD_TYPE_U64:
6247 vmcs_write64(field, (u64)field_value);
6248 break;
6249 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6250 vmcs_writel(field, (long)field_value);
6251 break;
6252 }
6253 }
6254 }
6255
6256 vmcs_clear(shadow_vmcs);
6257 vmcs_load(vmx->loaded_vmcs->vmcs);
6258}
6259
49f705c5
NHE		 6260/*
6261 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6262 * used before) all generate the same failure when it is missing.
6263 */
6264static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6265{
6266 struct vcpu_vmx *vmx = to_vmx(vcpu);
6267 if (vmx->nested.current_vmptr == -1ull) {
6268 nested_vmx_failInvalid(vcpu);
6269 skip_emulated_instruction(vcpu);
6270 return 0;
6271 }
6272 return 1;
6273}
6274
6275static int handle_vmread(struct kvm_vcpu *vcpu)
6276{
6277 unsigned long field;
6278 u64 field_value;
6279 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6280 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6281 gva_t gva = 0;
6282
6283 if (!nested_vmx_check_permission(vcpu) ||
6284 !nested_vmx_check_vmcs12(vcpu))
6285 return 1;
6286
6287 /* Decode instruction info and find the field to read */
6288 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6289 /* Read the field, zero-extended to a u64 field_value */
6290 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6291 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6292 skip_emulated_instruction(vcpu);
6293 return 1;
6294 }
6295 /*
6296 * Now copy part of this value to register or memory, as requested.
6297 * Note that the number of bits actually copied is 32 or 64 depending
6298 * on the guest's mode (32 or 64 bit), not on the given field's length.
6299 */
6300 if (vmx_instruction_info & (1u << 10)) {
6301 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6302 field_value);
6303 } else {
6304 if (get_vmx_mem_address(vcpu, exit_qualification,
6305 vmx_instruction_info, &gva))
6306 return 1;
6307 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6308 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6309 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6310 }
6311
6312 nested_vmx_succeed(vcpu);
6313 skip_emulated_instruction(vcpu);
6314 return 1;
6315}
6316
6317
6318static int handle_vmwrite(struct kvm_vcpu *vcpu)
6319{
6320 unsigned long field;
6321 gva_t gva;
6322 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6323 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6324 /* The value to write might be 32 or 64 bits, depending on L1's long
6325 * mode, and eventually we need to write that into a field of several
6326 * possible lengths. The code below first zero-extends the value to 64
6327 * bit (field_value), and then copies only the approriate number of
6328 * bits into the vmcs12 field.
6329 */
6330 u64 field_value = 0;
6331 struct x86_exception e;
6332
6333 if (!nested_vmx_check_permission(vcpu) ||
6334 !nested_vmx_check_vmcs12(vcpu))
6335 return 1;
6336
6337 if (vmx_instruction_info & (1u << 10))
6338 field_value = kvm_register_read(vcpu,
6339 (((vmx_instruction_info) >> 3) & 0xf));
6340 else {
6341 if (get_vmx_mem_address(vcpu, exit_qualification,
6342 vmx_instruction_info, &gva))
6343 return 1;
6344 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6345 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6346 kvm_inject_page_fault(vcpu, &e);
6347 return 1;
6348 }
6349 }
6350
6351
6352 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6353 if (vmcs_field_readonly(field)) {
6354 nested_vmx_failValid(vcpu,
6355 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6356 skip_emulated_instruction(vcpu);
6357 return 1;
6358 }
6359
20b97fea 6360 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6361 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6362 skip_emulated_instruction(vcpu);
6363 return 1;
6364 }
6365
6366 nested_vmx_succeed(vcpu);
6367 skip_emulated_instruction(vcpu);
6368 return 1;
6369}
6370
63846663
NHE		 6371/* Emulate the VMPTRLD instruction */
6372static int handle_vmptrld(struct kvm_vcpu *vcpu)
6373{
6374 struct vcpu_vmx *vmx = to_vmx(vcpu);
6375 gva_t gva;
6376 gpa_t vmptr;
6377 struct x86_exception e;
8a1b9dd0 6378 u32 exec_control;
63846663
NHE		 6379
6380 if (!nested_vmx_check_permission(vcpu))
6381 return 1;
6382
6383 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6384 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6385 return 1;
6386
6387 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6388 sizeof(vmptr), &e)) {
6389 kvm_inject_page_fault(vcpu, &e);
6390 return 1;
6391 }
6392
6393 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6394 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6395 skip_emulated_instruction(vcpu);
6396 return 1;
6397 }
6398
6399 if (vmx->nested.current_vmptr != vmptr) {
6400 struct vmcs12 *new_vmcs12;
6401 struct page *page;
6402 page = nested_get_page(vcpu, vmptr);
6403 if (page == NULL) {
6404 nested_vmx_failInvalid(vcpu);
6405 skip_emulated_instruction(vcpu);
6406 return 1;
6407 }
6408 new_vmcs12 = kmap(page);
6409 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6410 kunmap(page);
6411 nested_release_page_clean(page);
6412 nested_vmx_failValid(vcpu,
6413 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6414 skip_emulated_instruction(vcpu);
6415 return 1;
6416 }
e7953d7f
AG		 6417 if (vmx->nested.current_vmptr != -1ull)
6418 nested_release_vmcs12(vmx);
63846663
NHE		 6419
6420 vmx->nested.current_vmptr = vmptr;
6421 vmx->nested.current_vmcs12 = new_vmcs12;
6422 vmx->nested.current_vmcs12_page = page;
012f83cb 6423 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6424 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6425 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6426 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6427 vmcs_write64(VMCS_LINK_POINTER,
6428 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6429 vmx->nested.sync_shadow_vmcs = true;
6430 }
63846663
NHE		 6431 }
6432
6433 nested_vmx_succeed(vcpu);
6434 skip_emulated_instruction(vcpu);
6435 return 1;
6436}
6437
6a4d7550
NHE		 6438/* Emulate the VMPTRST instruction */
6439static int handle_vmptrst(struct kvm_vcpu *vcpu)
6440{
6441 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6442 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6443 gva_t vmcs_gva;
6444 struct x86_exception e;
6445
6446 if (!nested_vmx_check_permission(vcpu))
6447 return 1;
6448
6449 if (get_vmx_mem_address(vcpu, exit_qualification,
6450 vmx_instruction_info, &vmcs_gva))
6451 return 1;
6452 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6453 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6454 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6455 sizeof(u64), &e)) {
6456 kvm_inject_page_fault(vcpu, &e);
6457 return 1;
6458 }
6459 nested_vmx_succeed(vcpu);
6460 skip_emulated_instruction(vcpu);
6461 return 1;
6462}
6463
bfd0a56b
NHE		 6464/* Emulate the INVEPT instruction */
6465static int handle_invept(struct kvm_vcpu *vcpu)
6466{
6467 u32 vmx_instruction_info, types;
6468 unsigned long type;
6469 gva_t gva;
6470 struct x86_exception e;
6471 struct {
6472 u64 eptp, gpa;
6473 } operand;
6474 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6475
6476 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6477 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6478 kvm_queue_exception(vcpu, UD_VECTOR);
6479 return 1;
6480 }
6481
6482 if (!nested_vmx_check_permission(vcpu))
6483 return 1;
6484
6485 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6486 kvm_queue_exception(vcpu, UD_VECTOR);
6487 return 1;
6488 }
6489
6490 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6491 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6492
6493 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6494
6495 if (!(types & (1UL << type))) {
6496 nested_vmx_failValid(vcpu,
6497 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6498 return 1;
6499 }
6500
6501 /* According to the Intel VMX instruction reference, the memory
6502 * operand is read even if it isn't needed (e.g., for type==global)
6503 */
6504 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6505 vmx_instruction_info, &gva))
6506 return 1;
6507 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6508 sizeof(operand), &e)) {
6509 kvm_inject_page_fault(vcpu, &e);
6510 return 1;
6511 }
6512
6513 switch (type) {
6514 case VMX_EPT_EXTENT_CONTEXT:
6515 if ((operand.eptp & eptp_mask) !=
6516 (nested_ept_get_cr3(vcpu) & eptp_mask))
6517 break;
6518 case VMX_EPT_EXTENT_GLOBAL:
6519 kvm_mmu_sync_roots(vcpu);
6520 kvm_mmu_flush_tlb(vcpu);
6521 nested_vmx_succeed(vcpu);
6522 break;
6523 default:
6524 BUG_ON(1);
6525 break;
6526 }
6527
6528 skip_emulated_instruction(vcpu);
6529 return 1;
6530}
6531
6aa8b732
AK		 6532/*
6533 * The exit handlers return 1 if the exit was handled fully and guest execution
6534 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6535 * to be done to userspace and return 0.
6536 */
772e0318 6537static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6538 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6539 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6540 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6541 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6542 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6543 [EXIT_REASON_CR_ACCESS] = handle_cr,
6544 [EXIT_REASON_DR_ACCESS] = handle_dr,
6545 [EXIT_REASON_CPUID] = handle_cpuid,
6546 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6547 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6548 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6549 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6550 [EXIT_REASON_INVD] = handle_invd,
a7052897 6551 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6552 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6553 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6554 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6555 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6556 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6557 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6558 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6559 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6560 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6561 [EXIT_REASON_VMOFF] = handle_vmoff,
6562 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6563 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6564 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6565 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6566 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6567 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6568 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6569 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6570 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6571 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6572 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6573 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6574 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6575 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6576 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6577};
6578
6579static const int kvm_vmx_max_exit_handlers =
50a3485c 6580 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6581
908a7bdd
JK		 6582static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6583 struct vmcs12 *vmcs12)
6584{
6585 unsigned long exit_qualification;
6586 gpa_t bitmap, last_bitmap;
6587 unsigned int port;
6588 int size;
6589 u8 b;
6590
908a7bdd 6591 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6592 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6593
6594 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6595
6596 port = exit_qualification >> 16;
6597 size = (exit_qualification & 7) + 1;
6598
6599 last_bitmap = (gpa_t)-1;
6600 b = -1;
6601
6602 while (size > 0) {
6603 if (port < 0x8000)
6604 bitmap = vmcs12->io_bitmap_a;
6605 else if (port < 0x10000)
6606 bitmap = vmcs12->io_bitmap_b;
6607 else
6608 return 1;
6609 bitmap += (port & 0x7fff) / 8;
6610
6611 if (last_bitmap != bitmap)
6612 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6613 return 1;
6614 if (b & (1 << (port & 7)))
6615 return 1;
6616
6617 port++;
6618 size--;
6619 last_bitmap = bitmap;
6620 }
6621
6622 return 0;
6623}
6624
644d711a
NHE		 6625/*
6626 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6627 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6628 * disinterest in the current event (read or write a specific MSR) by using an
6629 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6630 */
6631static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6632 struct vmcs12 *vmcs12, u32 exit_reason)
6633{
6634 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6635 gpa_t bitmap;
6636
cbd29cb6 6637 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6638 return 1;
6639
6640 /*
6641 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6642 * for the four combinations of read/write and low/high MSR numbers.
6643 * First we need to figure out which of the four to use:
6644 */
6645 bitmap = vmcs12->msr_bitmap;
6646 if (exit_reason == EXIT_REASON_MSR_WRITE)
6647 bitmap += 2048;
6648 if (msr_index >= 0xc0000000) {
6649 msr_index -= 0xc0000000;
6650 bitmap += 1024;
6651 }
6652
6653 /* Then read the msr_index'th bit from this bitmap: */
6654 if (msr_index < 1024*8) {
6655 unsigned char b;
bd31a7f5
JK		 6656 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6657 return 1;
644d711a
NHE		 6658 return 1 & (b >> (msr_index & 7));
6659 } else
6660 return 1; /* let L1 handle the wrong parameter */
6661}
6662
6663/*
6664 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6665 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6666 * intercept (via guest_host_mask etc.) the current event.
6667 */
6668static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6669 struct vmcs12 *vmcs12)
6670{
6671 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6672 int cr = exit_qualification & 15;
6673 int reg = (exit_qualification >> 8) & 15;
6674 unsigned long val = kvm_register_read(vcpu, reg);
6675
6676 switch ((exit_qualification >> 4) & 3) {
6677 case 0: /* mov to cr */
6678 switch (cr) {
6679 case 0:
6680 if (vmcs12->cr0_guest_host_mask &
6681 (val ^ vmcs12->cr0_read_shadow))
6682 return 1;
6683 break;
6684 case 3:
6685 if ((vmcs12->cr3_target_count >= 1 &&
6686 vmcs12->cr3_target_value0 == val) ||
6687 (vmcs12->cr3_target_count >= 2 &&
6688 vmcs12->cr3_target_value1 == val) ||
6689 (vmcs12->cr3_target_count >= 3 &&
6690 vmcs12->cr3_target_value2 == val) ||
6691 (vmcs12->cr3_target_count >= 4 &&
6692 vmcs12->cr3_target_value3 == val))
6693 return 0;
6694 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6695 return 1;
6696 break;
6697 case 4:
6698 if (vmcs12->cr4_guest_host_mask &
6699 (vmcs12->cr4_read_shadow ^ val))
6700 return 1;
6701 break;
6702 case 8:
6703 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6704 return 1;
6705 break;
6706 }
6707 break;
6708 case 2: /* clts */
6709 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6710 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6711 return 1;
6712 break;
6713 case 1: /* mov from cr */
6714 switch (cr) {
6715 case 3:
6716 if (vmcs12->cpu_based_vm_exec_control &
6717 CPU_BASED_CR3_STORE_EXITING)
6718 return 1;
6719 break;
6720 case 8:
6721 if (vmcs12->cpu_based_vm_exec_control &
6722 CPU_BASED_CR8_STORE_EXITING)
6723 return 1;
6724 break;
6725 }
6726 break;
6727 case 3: /* lmsw */
6728 /*
6729 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6730 * cr0. Other attempted changes are ignored, with no exit.
6731 */
6732 if (vmcs12->cr0_guest_host_mask & 0xe &
6733 (val ^ vmcs12->cr0_read_shadow))
6734 return 1;
6735 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6736 !(vmcs12->cr0_read_shadow & 0x1) &&
6737 (val & 0x1))
6738 return 1;
6739 break;
6740 }
6741 return 0;
6742}
6743
6744/*
6745 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6746 * should handle it ourselves in L0 (and then continue L2). Only call this
6747 * when in is_guest_mode (L2).
6748 */
6749static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6750{
644d711a
NHE		 6751 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6752 struct vcpu_vmx *vmx = to_vmx(vcpu);
6753 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6754 u32 exit_reason = vmx->exit_reason;
644d711a 6755
542060ea
JK		 6756 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6757 vmcs_readl(EXIT_QUALIFICATION),
6758 vmx->idt_vectoring_info,
6759 intr_info,
6760 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6761 KVM_ISA_VMX);
6762
644d711a
NHE		 6763 if (vmx->nested.nested_run_pending)
6764 return 0;
6765
6766 if (unlikely(vmx->fail)) {
bd80158a
JK		 6767 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6768 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6769 return 1;
6770 }
6771
6772 switch (exit_reason) {
6773 case EXIT_REASON_EXCEPTION_NMI:
6774 if (!is_exception(intr_info))
6775 return 0;
6776 else if (is_page_fault(intr_info))
6777 return enable_ept;
e504c909 6778 else if (is_no_device(intr_info) &&
ccf9844e 6779 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6780 return 0;
644d711a
NHE		 6781 return vmcs12->exception_bitmap &
6782 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6783 case EXIT_REASON_EXTERNAL_INTERRUPT:
6784 return 0;
6785 case EXIT_REASON_TRIPLE_FAULT:
6786 return 1;
6787 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6788 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6789 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6790 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6791 case EXIT_REASON_TASK_SWITCH:
6792 return 1;
6793 case EXIT_REASON_CPUID:
6794 return 1;
6795 case EXIT_REASON_HLT:
6796 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6797 case EXIT_REASON_INVD:
6798 return 1;
6799 case EXIT_REASON_INVLPG:
6800 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6801 case EXIT_REASON_RDPMC:
6802 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6803 case EXIT_REASON_RDTSC:
6804 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6805 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6806 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6807 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6808 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6809 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6810 case EXIT_REASON_INVEPT:
644d711a
NHE		 6811 /*
6812 * VMX instructions trap unconditionally. This allows L1 to
6813 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6814 */
6815 return 1;
6816 case EXIT_REASON_CR_ACCESS:
6817 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6818 case EXIT_REASON_DR_ACCESS:
6819 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6820 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6821 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6822 case EXIT_REASON_MSR_READ:
6823 case EXIT_REASON_MSR_WRITE:
6824 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6825 case EXIT_REASON_INVALID_STATE:
6826 return 1;
6827 case EXIT_REASON_MWAIT_INSTRUCTION:
6828 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6829 case EXIT_REASON_MONITOR_INSTRUCTION:
6830 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6831 case EXIT_REASON_PAUSE_INSTRUCTION:
6832 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6833 nested_cpu_has2(vmcs12,
6834 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6835 case EXIT_REASON_MCE_DURING_VMENTRY:
6836 return 0;
6837 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6838 return 1;
6839 case EXIT_REASON_APIC_ACCESS:
6840 return nested_cpu_has2(vmcs12,
6841 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6842 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6843 /*
6844 * L0 always deals with the EPT violation. If nested EPT is
6845 * used, and the nested mmu code discovers that the address is
6846 * missing in the guest EPT table (EPT12), the EPT violation
6847 * will be injected with nested_ept_inject_page_fault()
6848 */
6849 return 0;
644d711a 6850 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6851 /*
6852 * L2 never uses directly L1's EPT, but rather L0's own EPT
6853 * table (shadow on EPT) or a merged EPT table that L0 built
6854 * (EPT on EPT). So any problems with the structure of the
6855 * table is L0's fault.
6856 */
644d711a
NHE		 6857 return 0;
6858 case EXIT_REASON_WBINVD:
6859 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6860 case EXIT_REASON_XSETBV:
6861 return 1;
6862 default:
6863 return 1;
6864 }
6865}
6866
586f9607
AK		 6867static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6868{
6869 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6870 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6871}
6872
6aa8b732
AK		 6873/*
6874 * The guest has exited. See if we can fix it or if we need userspace
6875 * assistance.
6876 */
851ba692 6877static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6878{
29bd8a78 6879 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6880 u32 exit_reason = vmx->exit_reason;
1155f76a 6881 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6882
80ced186 6883 /* If guest state is invalid, start emulating */
14168786 6884 if (vmx->emulation_required)
80ced186 6885 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6886
644d711a 6887 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6888 nested_vmx_vmexit(vcpu, exit_reason,
6889 vmcs_read32(VM_EXIT_INTR_INFO),
6890 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6891 return 1;
6892 }
6893
5120702e
MG		 6894 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6895 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6896 vcpu->run->fail_entry.hardware_entry_failure_reason
6897 = exit_reason;
6898 return 0;
6899 }
6900
29bd8a78 6901 if (unlikely(vmx->fail)) {
851ba692
AK		 6902 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6903 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6904 = vmcs_read32(VM_INSTRUCTION_ERROR);
6905 return 0;
6906 }
6aa8b732 6907
b9bf6882
XG		 6908 /*
6909 * Note:
6910 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6911 * delivery event since it indicates guest is accessing MMIO.
6912 * The vm-exit can be triggered again after return to guest that
6913 * will cause infinite loop.
6914 */
d77c26fc 6915 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6916 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6917 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6918 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6919 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6920 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6921 vcpu->run->internal.ndata = 2;
6922 vcpu->run->internal.data[0] = vectoring_info;
6923 vcpu->run->internal.data[1] = exit_reason;
6924 return 0;
6925 }
3b86cd99 6926
644d711a
NHE		 6927 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6928 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6929 get_vmcs12(vcpu))))) {
c4282df9 6930 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6931 vmx->soft_vnmi_blocked = 0;
3b86cd99 6932 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6933 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6934 /*
6935 * This CPU don't support us in finding the end of an
6936 * NMI-blocked window if the guest runs with IRQs
6937 * disabled. So we pull the trigger after 1 s of
6938 * futile waiting, but inform the user about this.
6939 */
6940 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6941 "state on VCPU %d after 1 s timeout\n",
6942 __func__, vcpu->vcpu_id);
6943 vmx->soft_vnmi_blocked = 0;
3b86cd99 6944 }
3b86cd99
JK		 6945 }
6946
6aa8b732
AK		 6947 if (exit_reason < kvm_vmx_max_exit_handlers
6948 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6949 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6950 else {
851ba692
AK		 6951 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6952 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6953 }
6954 return 0;
6955}
6956
95ba8273 6957static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6958{
95ba8273 6959 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6960 vmcs_write32(TPR_THRESHOLD, 0);
6961 return;
6962 }
6963
95ba8273 6964 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6965}
6966
8d14695f
YZ		 6967static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6968{
6969 u32 sec_exec_control;
6970
6971 /*
6972 * There is not point to enable virtualize x2apic without enable
6973 * apicv
6974 */
c7c9c56c
YZ		 6975 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6976 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6977 return;
6978
6979 if (!vm_need_tpr_shadow(vcpu->kvm))
6980 return;
6981
6982 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6983
6984 if (set) {
6985 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6986 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6987 } else {
6988 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6989 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6990 }
6991 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6992
6993 vmx_set_msr_bitmap(vcpu);
6994}
6995
c7c9c56c
YZ		 6996static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6997{
6998 u16 status;
6999 u8 old;
7000
7001 if (!vmx_vm_has_apicv(kvm))
7002 return;
7003
7004 if (isr == -1)
7005 isr = 0;
7006
7007 status = vmcs_read16(GUEST_INTR_STATUS);
7008 old = status >> 8;
7009 if (isr != old) {
7010 status &= 0xff;
7011 status |= isr << 8;
7012 vmcs_write16(GUEST_INTR_STATUS, status);
7013 }
7014}
7015
7016static void vmx_set_rvi(int vector)
7017{
7018 u16 status;
7019 u8 old;
7020
7021 status = vmcs_read16(GUEST_INTR_STATUS);
7022 old = (u8)status & 0xff;
7023 if ((u8)vector != old) {
7024 status &= ~0xff;
7025 status |= (u8)vector;
7026 vmcs_write16(GUEST_INTR_STATUS, status);
7027 }
7028}
7029
7030static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7031{
7032 if (max_irr == -1)
7033 return;
7034
7035 vmx_set_rvi(max_irr);
7036}
7037
7038static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7039{
3d81bc7e
YZ		 7040 if (!vmx_vm_has_apicv(vcpu->kvm))
7041 return;
7042
c7c9c56c
YZ		 7043 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7044 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7045 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7046 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7047}
7048
51aa01d1 7049static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7050{
00eba012
AK		 7051 u32 exit_intr_info;
7052
7053 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7054 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7055 return;
7056
c5ca8e57 7057 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7058 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7059
7060 /* Handle machine checks before interrupts are enabled */
00eba012 7061 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7062 kvm_machine_check();
7063
20f65983 7064 /* We need to handle NMIs before interrupts are enabled */
00eba012 7065 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7066 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7067 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7068 asm("int $2");
ff9d07a0
ZY		 7069 kvm_after_handle_nmi(&vmx->vcpu);
7070 }
51aa01d1 7071}
20f65983 7072
a547c6db
YZ		 7073static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7074{
7075 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7076
7077 /*
7078 * If external interrupt exists, IF bit is set in rflags/eflags on the
7079 * interrupt stack frame, and interrupt will be enabled on a return
7080 * from interrupt handler.
7081 */
7082 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7083 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7084 unsigned int vector;
7085 unsigned long entry;
7086 gate_desc *desc;
7087 struct vcpu_vmx *vmx = to_vmx(vcpu);
7088#ifdef CONFIG_X86_64
7089 unsigned long tmp;
7090#endif
7091
7092 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7093 desc = (gate_desc *)vmx->host_idt_base + vector;
7094 entry = gate_offset(*desc);
7095 asm volatile(
7096#ifdef CONFIG_X86_64
7097 "mov %%" _ASM_SP ", %[sp]\n\t"
7098 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7099 "push $%c[ss]\n\t"
7100 "push %[sp]\n\t"
7101#endif
7102 "pushf\n\t"
7103 "orl $0x200, (%%" _ASM_SP ")\n\t"
7104 __ASM_SIZE(push) " $%c[cs]\n\t"
7105 "call *%[entry]\n\t"
7106 :
7107#ifdef CONFIG_X86_64
7108 [sp]"=&r"(tmp)
7109#endif
7110 :
7111 [entry]"r"(entry),
7112 [ss]"i"(__KERNEL_DS),
7113 [cs]"i"(__KERNEL_CS)
7114 );
7115 } else
7116 local_irq_enable();
7117}
7118
da8999d3
LJ		 7119static bool vmx_mpx_supported(void)
7120{
7121 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7122 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7123}
7124
51aa01d1
AK		 7125static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7126{
c5ca8e57 7127 u32 exit_intr_info;
51aa01d1
AK		 7128 bool unblock_nmi;
7129 u8 vector;
7130 bool idtv_info_valid;
7131
7132 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7133
cf393f75 7134 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7135 if (vmx->nmi_known_unmasked)
7136 return;
c5ca8e57
AK		 7137 /*
7138 * Can't use vmx->exit_intr_info since we're not sure what
7139 * the exit reason is.
7140 */
7141 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7142 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7143 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7144 /*
7b4a25cb 7145 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7146 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7147 * a guest IRET fault.
7b4a25cb
GN		 7148 * SDM 3: 23.2.2 (September 2008)
7149 * Bit 12 is undefined in any of the following cases:
7150 * If the VM exit sets the valid bit in the IDT-vectoring
7151 * information field.
7152 * If the VM exit is due to a double fault.
cf393f75 7153 */
7b4a25cb
GN		 7154 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7155 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7156 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7157 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7158 else
7159 vmx->nmi_known_unmasked =
7160 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7161 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7162 } else if (unlikely(vmx->soft_vnmi_blocked))
7163 vmx->vnmi_blocked_time +=
7164 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7165}
7166
3ab66e8a 7167static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7168 u32 idt_vectoring_info,
7169 int instr_len_field,
7170 int error_code_field)
51aa01d1 7171{
51aa01d1
AK		 7172 u8 vector;
7173 int type;
7174 bool idtv_info_valid;
7175
7176 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7177
3ab66e8a
JK		 7178 vcpu->arch.nmi_injected = false;
7179 kvm_clear_exception_queue(vcpu);
7180 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7181
7182 if (!idtv_info_valid)
7183 return;
7184
3ab66e8a 7185 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7186
668f612f
AK		 7187 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7188 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7189
64a7ec06 7190 switch (type) {
37b96e98 7191 case INTR_TYPE_NMI_INTR:
3ab66e8a 7192 vcpu->arch.nmi_injected = true;
668f612f 7193 /*
7b4a25cb 7194 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7195 * Clear bit "block by NMI" before VM entry if a NMI
7196 * delivery faulted.
668f612f 7197 */
3ab66e8a 7198 vmx_set_nmi_mask(vcpu, false);
37b96e98 7199 break;
37b96e98 7200 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7201 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7202 /* fall through */
7203 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7204 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7205 u32 err = vmcs_read32(error_code_field);
851eb667 7206 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7207 } else
851eb667 7208 kvm_requeue_exception(vcpu, vector);
37b96e98 7209 break;
66fd3f7f 7210 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7211 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7212 /* fall through */
37b96e98 7213 case INTR_TYPE_EXT_INTR:
3ab66e8a 7214 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7215 break;
7216 default:
7217 break;
f7d9238f 7218 }
cf393f75
AK		 7219}
7220
83422e17
AK		 7221static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7222{
3ab66e8a 7223 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7224 VM_EXIT_INSTRUCTION_LEN,
7225 IDT_VECTORING_ERROR_CODE);
7226}
7227
b463a6f7
AK		 7228static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7229{
3ab66e8a 7230 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7231 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7232 VM_ENTRY_INSTRUCTION_LEN,
7233 VM_ENTRY_EXCEPTION_ERROR_CODE);
7234
7235 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7236}
7237
d7cd9796
GN		 7238static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7239{
7240 int i, nr_msrs;
7241 struct perf_guest_switch_msr *msrs;
7242
7243 msrs = perf_guest_get_msrs(&nr_msrs);
7244
7245 if (!msrs)
7246 return;
7247
7248 for (i = 0; i < nr_msrs; i++)
7249 if (msrs[i].host == msrs[i].guest)
7250 clear_atomic_switch_msr(vmx, msrs[i].msr);
7251 else
7252 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7253 msrs[i].host);
7254}
7255
a3b5ba49 7256static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7257{
a2fa3e9f 7258 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7259 unsigned long debugctlmsr;
104f226b
AK		 7260
7261 /* Record the guest's net vcpu time for enforced NMI injections. */
7262 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7263 vmx->entry_time = ktime_get();
7264
7265 /* Don't enter VMX if guest state is invalid, let the exit handler
7266 start emulation until we arrive back to a valid state */
14168786 7267 if (vmx->emulation_required)
104f226b
AK		 7268 return;
7269
012f83cb
AG		 7270 if (vmx->nested.sync_shadow_vmcs) {
7271 copy_vmcs12_to_shadow(vmx);
7272 vmx->nested.sync_shadow_vmcs = false;
7273 }
7274
104f226b
AK		 7275 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7276 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7277 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7278 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7279
7280 /* When single-stepping over STI and MOV SS, we must clear the
7281 * corresponding interruptibility bits in the guest state. Otherwise
7282 * vmentry fails as it then expects bit 14 (BS) in pending debug
7283 * exceptions being set, but that's not correct for the guest debugging
7284 * case. */
7285 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7286 vmx_set_interrupt_shadow(vcpu, 0);
7287
d7cd9796 7288 atomic_switch_perf_msrs(vmx);
2a7921b7 7289 debugctlmsr = get_debugctlmsr();
d7cd9796 7290
d462b819 7291 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7292 asm(
6aa8b732 7293 /* Store host registers */
b188c81f
AK		 7294 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7295 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7296 "push %%" _ASM_CX " \n\t"
7297 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7298 "je 1f \n\t"
b188c81f 7299 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7300 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7301 "1: \n\t"
d3edefc0 7302 /* Reload cr2 if changed */
b188c81f
AK		 7303 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7304 "mov %%cr2, %%" _ASM_DX " \n\t"
7305 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7306 "je 2f \n\t"
b188c81f 7307 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7308 "2: \n\t"
6aa8b732 7309 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7310 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7311 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7312 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7313 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7314 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7315 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7316 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7317 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7318#ifdef CONFIG_X86_64
e08aa78a
AK		 7319 "mov %c[r8](%0), %%r8 \n\t"
7320 "mov %c[r9](%0), %%r9 \n\t"
7321 "mov %c[r10](%0), %%r10 \n\t"
7322 "mov %c[r11](%0), %%r11 \n\t"
7323 "mov %c[r12](%0), %%r12 \n\t"
7324 "mov %c[r13](%0), %%r13 \n\t"
7325 "mov %c[r14](%0), %%r14 \n\t"
7326 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7327#endif
b188c81f 7328 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7329
6aa8b732 7330 /* Enter guest mode */
83287ea4 7331 "jne 1f \n\t"
4ecac3fd 7332 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7333 "jmp 2f \n\t"
7334 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7335 "2: "
6aa8b732 7336 /* Save guest registers, load host registers, keep flags */
b188c81f 7337 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7338 "pop %0 \n\t"
b188c81f
AK		 7339 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7340 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7341 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7342 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7343 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7344 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7345 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7346#ifdef CONFIG_X86_64
e08aa78a
AK		 7347 "mov %%r8, %c[r8](%0) \n\t"
7348 "mov %%r9, %c[r9](%0) \n\t"
7349 "mov %%r10, %c[r10](%0) \n\t"
7350 "mov %%r11, %c[r11](%0) \n\t"
7351 "mov %%r12, %c[r12](%0) \n\t"
7352 "mov %%r13, %c[r13](%0) \n\t"
7353 "mov %%r14, %c[r14](%0) \n\t"
7354 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7355#endif
b188c81f
AK		 7356 "mov %%cr2, %%" _ASM_AX " \n\t"
7357 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7358
b188c81f 7359 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7360 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7361 ".pushsection .rodata \n\t"
7362 ".global vmx_return \n\t"
7363 "vmx_return: " _ASM_PTR " 2b \n\t"
7364 ".popsection"
e08aa78a 7365 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7366 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7367 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7368 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7369 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7370 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7371 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7372 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7373 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7374 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7375 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7376#ifdef CONFIG_X86_64
ad312c7c
ZX		 7377 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7378 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7379 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7380 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7381 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7382 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7383 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7384 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7385#endif
40712fae
AK		 7386 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7387 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7388 : "cc", "memory"
7389#ifdef CONFIG_X86_64
b188c81f 7390 , "rax", "rbx", "rdi", "rsi"
c2036300 7391 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7392#else
7393 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7394#endif
7395 );
6aa8b732 7396
2a7921b7
GN		 7397 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7398 if (debugctlmsr)
7399 update_debugctlmsr(debugctlmsr);
7400
aa67f609
AK		 7401#ifndef CONFIG_X86_64
7402 /*
7403 * The sysexit path does not restore ds/es, so we must set them to
7404 * a reasonable value ourselves.
7405 *
7406 * We can't defer this to vmx_load_host_state() since that function
7407 * may be executed in interrupt context, which saves and restore segments
7408 * around it, nullifying its effect.
7409 */
7410 loadsegment(ds, __USER_DS);
7411 loadsegment(es, __USER_DS);
7412#endif
7413
6de4f3ad 7414 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7415 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7416 | (1 << VCPU_EXREG_CPL)
aff48baa 7417 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7418 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7419 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7420 vcpu->arch.regs_dirty = 0;
7421
1155f76a
AK		 7422 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7423
d462b819 7424 vmx->loaded_vmcs->launched = 1;
1b6269db 7425
51aa01d1 7426 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7427 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7428
e0b890d3
GN		 7429 /*
7430 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7431 * we did not inject a still-pending event to L1 now because of
7432 * nested_run_pending, we need to re-enable this bit.
7433 */
7434 if (vmx->nested.nested_run_pending)
7435 kvm_make_request(KVM_REQ_EVENT, vcpu);
7436
7437 vmx->nested.nested_run_pending = 0;
7438
51aa01d1
AK		 7439 vmx_complete_atomic_exit(vmx);
7440 vmx_recover_nmi_blocking(vmx);
cf393f75 7441 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7442}
7443
6aa8b732
AK		 7444static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7445{
fb3f0f51
RR		 7446 struct vcpu_vmx *vmx = to_vmx(vcpu);
7447
cdbecfc3 7448 free_vpid(vmx);
d462b819 7449 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7450 free_nested(vmx);
fb3f0f51
RR		 7451 kfree(vmx->guest_msrs);
7452 kvm_vcpu_uninit(vcpu);
a4770347 7453 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7454}
7455
fb3f0f51 7456static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7457{
fb3f0f51 7458 int err;
c16f862d 7459 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7460 int cpu;
6aa8b732 7461
a2fa3e9f 7462 if (!vmx)
fb3f0f51
RR		 7463 return ERR_PTR(-ENOMEM);
7464
2384d2b3
SY		 7465 allocate_vpid(vmx);
7466
fb3f0f51
RR		 7467 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7468 if (err)
7469 goto free_vcpu;
965b58a5 7470
a2fa3e9f 7471 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7472 err = -ENOMEM;
fb3f0f51 7473 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7474 goto uninit_vcpu;
7475 }
965b58a5 7476
d462b819
NHE		 7477 vmx->loaded_vmcs = &vmx->vmcs01;
7478 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7479 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7480 goto free_msrs;
d462b819
NHE		 7481 if (!vmm_exclusive)
7482 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7483 loaded_vmcs_init(vmx->loaded_vmcs);
7484 if (!vmm_exclusive)
7485 kvm_cpu_vmxoff();
a2fa3e9f 7486
15ad7146
AK		 7487 cpu = get_cpu();
7488 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7489 vmx->vcpu.cpu = cpu;
8b9cf98c 7490 err = vmx_vcpu_setup(vmx);
fb3f0f51 7491 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7492 put_cpu();
fb3f0f51
RR		 7493 if (err)
7494 goto free_vmcs;
a63cb560 7495 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7496 err = alloc_apic_access_page(kvm);
7497 if (err)
5e4a0b3c 7498 goto free_vmcs;
a63cb560 7499 }
fb3f0f51 7500
b927a3ce
SY		 7501 if (enable_ept) {
7502 if (!kvm->arch.ept_identity_map_addr)
7503 kvm->arch.ept_identity_map_addr =
7504 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7505 err = -ENOMEM;
b7ebfb05
SY		 7506 if (alloc_identity_pagetable(kvm) != 0)
7507 goto free_vmcs;
93ea5388
GN		 7508 if (!init_rmode_identity_map(kvm))
7509 goto free_vmcs;
b927a3ce 7510 }
b7ebfb05 7511
a9d30f33
NHE		 7512 vmx->nested.current_vmptr = -1ull;
7513 vmx->nested.current_vmcs12 = NULL;
7514
fb3f0f51
RR		 7515 return &vmx->vcpu;
7516
7517free_vmcs:
5f3fbc34 7518 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7519free_msrs:
fb3f0f51
RR		 7520 kfree(vmx->guest_msrs);
7521uninit_vcpu:
7522 kvm_vcpu_uninit(&vmx->vcpu);
7523free_vcpu:
cdbecfc3 7524 free_vpid(vmx);
a4770347 7525 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7526 return ERR_PTR(err);
6aa8b732
AK		 7527}
7528
002c7f7c
YS		 7529static void __init vmx_check_processor_compat(void *rtn)
7530{
7531 struct vmcs_config vmcs_conf;
7532
7533 *(int *)rtn = 0;
7534 if (setup_vmcs_config(&vmcs_conf) < 0)
7535 *(int *)rtn = -EIO;
7536 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7537 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7538 smp_processor_id());
7539 *(int *)rtn = -EIO;
7540 }
7541}
7542
67253af5
SY		 7543static int get_ept_level(void)
7544{
7545 return VMX_EPT_DEFAULT_GAW + 1;
7546}
7547
4b12f0de 7548static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7549{
4b12f0de
SY		 7550 u64 ret;
7551
522c68c4
SY		 7552 /* For VT-d and EPT combination
7553 * 1. MMIO: always map as UC
7554 * 2. EPT with VT-d:
7555 * a. VT-d without snooping control feature: can't guarantee the
7556 * result, try to trust guest.
7557 * b. VT-d with snooping control feature: snooping control feature of
7558 * VT-d engine can guarantee the cache correctness. Just set it
7559 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7560 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7561 * consistent with host MTRR
7562 */
4b12f0de
SY		 7563 if (is_mmio)
7564 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7565 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7566 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7567 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7568 else
522c68c4 7569 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7570 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7571
7572 return ret;
64d4d521
SY		 7573}
7574
17cc3935 7575static int vmx_get_lpage_level(void)
344f414f 7576{
878403b7
SY		 7577 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7578 return PT_DIRECTORY_LEVEL;
7579 else
7580 /* For shadow and EPT supported 1GB page */
7581 return PT_PDPE_LEVEL;
344f414f
JR		 7582}
7583
0e851880
SY		 7584static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7585{
4e47c7a6
SY		 7586 struct kvm_cpuid_entry2 *best;
7587 struct vcpu_vmx *vmx = to_vmx(vcpu);
7588 u32 exec_control;
7589
7590 vmx->rdtscp_enabled = false;
7591 if (vmx_rdtscp_supported()) {
7592 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7593 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7594 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7595 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7596 vmx->rdtscp_enabled = true;
7597 else {
7598 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7599 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7600 exec_control);
7601 }
7602 }
7603 }
ad756a16 7604
ad756a16
MJ		 7605 /* Exposing INVPCID only when PCID is exposed */
7606 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7607 if (vmx_invpcid_supported() &&
4f977045 7608 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7609 guest_cpuid_has_pcid(vcpu)) {
29282fde 7610 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7611 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7612 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7613 exec_control);
7614 } else {
29282fde
TI		 7615 if (cpu_has_secondary_exec_ctrls()) {
7616 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7617 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7618 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7619 exec_control);
7620 }
ad756a16 7621 if (best)
4f977045 7622 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7623 }
0e851880
SY		 7624}
7625
d4330ef2
JR		 7626static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7627{
7b8050f5
NHE		 7628 if (func == 1 && nested)
7629 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7630}
7631
25d92081
YZ		 7632static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7633 struct x86_exception *fault)
7634{
533558bc
JK		 7635 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7636 u32 exit_reason;
25d92081
YZ		 7637
7638 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7639 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7640 else
533558bc
JK		 7641 exit_reason = EXIT_REASON_EPT_VIOLATION;
7642 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7643 vmcs12->guest_physical_address = fault->address;
7644}
7645
155a97a3
NHE		 7646/* Callbacks for nested_ept_init_mmu_context: */
7647
7648static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7649{
7650 /* return the page table to be shadowed - in our case, EPT12 */
7651 return get_vmcs12(vcpu)->ept_pointer;
7652}
7653
8a3c1a33 7654static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7655{
8a3c1a33 7656 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7657 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7658
7659 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7660 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7661 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7662
7663 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7664}
7665
7666static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7667{
7668 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7669}
7670
feaf0c7d
GN		 7671static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7672 struct x86_exception *fault)
7673{
7674 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7675
7676 WARN_ON(!is_guest_mode(vcpu));
7677
7678 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7679 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7680 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7681 vmcs_read32(VM_EXIT_INTR_INFO),
7682 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7683 else
7684 kvm_inject_page_fault(vcpu, fault);
7685}
7686
f4124500
JK		 7687static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7688{
7689 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7690 struct vcpu_vmx *vmx = to_vmx(vcpu);
7691
7692 if (vcpu->arch.virtual_tsc_khz == 0)
7693 return;
7694
7695 /* Make sure short timeouts reliably trigger an immediate vmexit.
7696 * hrtimer_start does not guarantee this. */
7697 if (preemption_timeout <= 1) {
7698 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7699 return;
7700 }
7701
7702 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7703 preemption_timeout *= 1000000;
7704 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7705 hrtimer_start(&vmx->nested.preemption_timer,
7706 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7707}
7708
fe3ef05c
NHE		 7709/*
7710 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7711 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7712 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7713 * guest in a way that will both be appropriate to L1's requests, and our
7714 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7715 * function also has additional necessary side-effects, like setting various
7716 * vcpu->arch fields.
7717 */
7718static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7719{
7720 struct vcpu_vmx *vmx = to_vmx(vcpu);
7721 u32 exec_control;
7722
7723 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7724 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7725 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7726 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7727 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7728 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7729 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7730 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7731 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7732 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7733 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7734 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7735 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7736 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7737 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7738 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7739 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7740 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7741 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7742 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7743 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7744 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7745 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7746 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7747 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7748 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7749 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7750 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7751 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7752 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7753 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7754 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7755 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7756 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7757 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7758 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7759
7760 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7761 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7762 vmcs12->vm_entry_intr_info_field);
7763 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7764 vmcs12->vm_entry_exception_error_code);
7765 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7766 vmcs12->vm_entry_instruction_len);
7767 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7768 vmcs12->guest_interruptibility_info);
fe3ef05c 7769 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7770 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7771 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7772 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7773 vmcs12->guest_pending_dbg_exceptions);
7774 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7775 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7776
7777 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7778
f4124500
JK		 7779 exec_control = vmcs12->pin_based_vm_exec_control;
7780 exec_control |= vmcs_config.pin_based_exec_ctrl;
7781 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7782 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7783
f4124500
JK		 7784 vmx->nested.preemption_timer_expired = false;
7785 if (nested_cpu_has_preemption_timer(vmcs12))
7786 vmx_start_preemption_timer(vcpu);
0238ea91 7787
fe3ef05c
NHE		 7788 /*
7789 * Whether page-faults are trapped is determined by a combination of
7790 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7791 * If enable_ept, L0 doesn't care about page faults and we should
7792 * set all of these to L1's desires. However, if !enable_ept, L0 does
7793 * care about (at least some) page faults, and because it is not easy
7794 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7795 * to exit on each and every L2 page fault. This is done by setting
7796 * MASK=MATCH=0 and (see below) EB.PF=1.
7797 * Note that below we don't need special code to set EB.PF beyond the
7798 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7799 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7800 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7801 *
7802 * A problem with this approach (when !enable_ept) is that L1 may be
7803 * injected with more page faults than it asked for. This could have
7804 * caused problems, but in practice existing hypervisors don't care.
7805 * To fix this, we will need to emulate the PFEC checking (on the L1
7806 * page tables), using walk_addr(), when injecting PFs to L1.
7807 */
7808 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7809 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7810 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7811 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7812
7813 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7814 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7815 if (!vmx->rdtscp_enabled)
7816 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7817 /* Take the following fields only from vmcs12 */
7818 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7819 if (nested_cpu_has(vmcs12,
7820 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7821 exec_control |= vmcs12->secondary_vm_exec_control;
7822
7823 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7824 /*
7825 * Translate L1 physical address to host physical
7826 * address for vmcs02. Keep the page pinned, so this
7827 * physical address remains valid. We keep a reference
7828 * to it so we can release it later.
7829 */
7830 if (vmx->nested.apic_access_page) /* shouldn't happen */
7831 nested_release_page(vmx->nested.apic_access_page);
7832 vmx->nested.apic_access_page =
7833 nested_get_page(vcpu, vmcs12->apic_access_addr);
7834 /*
7835 * If translation failed, no matter: This feature asks
7836 * to exit when accessing the given address, and if it
7837 * can never be accessed, this feature won't do
7838 * anything anyway.
7839 */
7840 if (!vmx->nested.apic_access_page)
7841 exec_control &=
7842 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7843 else
7844 vmcs_write64(APIC_ACCESS_ADDR,
7845 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7846 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7847 exec_control |=
7848 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7849 vmcs_write64(APIC_ACCESS_ADDR,
7850 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7851 }
7852
7853 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7854 }
7855
7856
7857 /*
7858 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7859 * Some constant fields are set here by vmx_set_constant_host_state().
7860 * Other fields are different per CPU, and will be set later when
7861 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7862 */
a547c6db 7863 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7864
7865 /*
7866 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7867 * entry, but only if the current (host) sp changed from the value
7868 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7869 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7870 * here we just force the write to happen on entry.
7871 */
7872 vmx->host_rsp = 0;
7873
7874 exec_control = vmx_exec_control(vmx); /* L0's desires */
7875 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7876 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7877 exec_control &= ~CPU_BASED_TPR_SHADOW;
7878 exec_control |= vmcs12->cpu_based_vm_exec_control;
7879 /*
7880 * Merging of IO and MSR bitmaps not currently supported.
7881 * Rather, exit every time.
7882 */
7883 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7884 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7885 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7886
7887 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7888
7889 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7890 * bitwise-or of what L1 wants to trap for L2, and what we want to
7891 * trap. Note that CR0.TS also needs updating - we do this later.
7892 */
7893 update_exception_bitmap(vcpu);
7894 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7895 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7896
8049d651
NHE		 7897 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7898 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7899 * bits are further modified by vmx_set_efer() below.
7900 */
f4124500 7901 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7902
7903 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7904 * emulated by vmx_set_efer(), below.
7905 */
2961e876 7906 vm_entry_controls_init(vmx,
8049d651
NHE		 7907 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7908 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7909 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7910
44811c02 7911 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7912 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7913 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7914 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7915 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7916
7917
7918 set_cr4_guest_host_mask(vmx);
7919
36be0b9d
PB		 7920 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7921 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7922
27fc51b2
NHE		 7923 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7924 vmcs_write64(TSC_OFFSET,
7925 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7926 else
7927 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7928
7929 if (enable_vpid) {
7930 /*
7931 * Trivially support vpid by letting L2s share their parent
7932 * L1's vpid. TODO: move to a more elaborate solution, giving
7933 * each L2 its own vpid and exposing the vpid feature to L1.
7934 */
7935 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7936 vmx_flush_tlb(vcpu);
7937 }
7938
155a97a3
NHE		 7939 if (nested_cpu_has_ept(vmcs12)) {
7940 kvm_mmu_unload(vcpu);
7941 nested_ept_init_mmu_context(vcpu);
7942 }
7943
fe3ef05c
NHE		 7944 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7945 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7946 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7947 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7948 else
7949 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7950 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7951 vmx_set_efer(vcpu, vcpu->arch.efer);
7952
7953 /*
7954 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7955 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7956 * The CR0_READ_SHADOW is what L2 should have expected to read given
7957 * the specifications by L1; It's not enough to take
7958 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7959 * have more bits than L1 expected.
7960 */
7961 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7962 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7963
7964 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7965 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7966
7967 /* shadow page tables on either EPT or shadow page tables */
7968 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7969 kvm_mmu_reset_context(vcpu);
7970
feaf0c7d
GN		 7971 if (!enable_ept)
7972 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7973
3633cfc3
NHE		 7974 /*
7975 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7976 */
7977 if (enable_ept) {
7978 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7979 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7980 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7981 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7982 }
7983
fe3ef05c
NHE		 7984 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7985 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7986}
7987
cd232ad0
NHE		 7988/*
7989 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7990 * for running an L2 nested guest.
7991 */
7992static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7993{
7994 struct vmcs12 *vmcs12;
7995 struct vcpu_vmx *vmx = to_vmx(vcpu);
7996 int cpu;
7997 struct loaded_vmcs *vmcs02;
384bb783 7998 bool ia32e;
cd232ad0
NHE		 7999
8000 if (!nested_vmx_check_permission(vcpu) ||
8001 !nested_vmx_check_vmcs12(vcpu))
8002 return 1;
8003
8004 skip_emulated_instruction(vcpu);
8005 vmcs12 = get_vmcs12(vcpu);
8006
012f83cb
AG		 8007 if (enable_shadow_vmcs)
8008 copy_shadow_to_vmcs12(vmx);
8009
7c177938
NHE		 8010 /*
8011 * The nested entry process starts with enforcing various prerequisites
8012 * on vmcs12 as required by the Intel SDM, and act appropriately when
8013 * they fail: As the SDM explains, some conditions should cause the
8014 * instruction to fail, while others will cause the instruction to seem
8015 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8016 * To speed up the normal (success) code path, we should avoid checking
8017 * for misconfigurations which will anyway be caught by the processor
8018 * when using the merged vmcs02.
8019 */
8020 if (vmcs12->launch_state == launch) {
8021 nested_vmx_failValid(vcpu,
8022 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8023 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8024 return 1;
8025 }
8026
6dfacadd
JK		 8027 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8028 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8029 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8030 return 1;
8031 }
8032
7c177938
NHE		 8033 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8034 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8035 /*TODO: Also verify bits beyond physical address width are 0*/
8036 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8037 return 1;
8038 }
8039
8040 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8041 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8042 /*TODO: Also verify bits beyond physical address width are 0*/
8043 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8044 return 1;
8045 }
8046
8047 if (vmcs12->vm_entry_msr_load_count > 0 ||
8048 vmcs12->vm_exit_msr_load_count > 0 ||
8049 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8050 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8051 __func__);
7c177938
NHE		 8052 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8053 return 1;
8054 }
8055
8056 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8057 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8058 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8059 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8060 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8061 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8062 !vmx_control_verify(vmcs12->vm_exit_controls,
8063 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8064 !vmx_control_verify(vmcs12->vm_entry_controls,
8065 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8066 {
8067 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8068 return 1;
8069 }
8070
8071 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8072 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8073 nested_vmx_failValid(vcpu,
8074 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8075 return 1;
8076 }
8077
92fbc7b1 8078 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8079 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8080 nested_vmx_entry_failure(vcpu, vmcs12,
8081 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8082 return 1;
8083 }
8084 if (vmcs12->vmcs_link_pointer != -1ull) {
8085 nested_vmx_entry_failure(vcpu, vmcs12,
8086 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8087 return 1;
8088 }
8089
384bb783 8090 /*
cb0c8cda 8091 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8092 * are performed on the field for the IA32_EFER MSR:
8093 * - Bits reserved in the IA32_EFER MSR must be 0.
8094 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8095 * the IA-32e mode guest VM-exit control. It must also be identical
8096 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8097 * CR0.PG) is 1.
8098 */
8099 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8100 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8101 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8102 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8103 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8104 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8105 nested_vmx_entry_failure(vcpu, vmcs12,
8106 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8107 return 1;
8108 }
8109 }
8110
8111 /*
8112 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8113 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8114 * the values of the LMA and LME bits in the field must each be that of
8115 * the host address-space size VM-exit control.
8116 */
8117 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8118 ia32e = (vmcs12->vm_exit_controls &
8119 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8120 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8121 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8122 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8123 nested_vmx_entry_failure(vcpu, vmcs12,
8124 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8125 return 1;
8126 }
8127 }
8128
7c177938
NHE		 8129 /*
8130 * We're finally done with prerequisite checking, and can start with
8131 * the nested entry.
8132 */
8133
cd232ad0
NHE		 8134 vmcs02 = nested_get_current_vmcs02(vmx);
8135 if (!vmcs02)
8136 return -ENOMEM;
8137
8138 enter_guest_mode(vcpu);
8139
8140 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8141
8142 cpu = get_cpu();
8143 vmx->loaded_vmcs = vmcs02;
8144 vmx_vcpu_put(vcpu);
8145 vmx_vcpu_load(vcpu, cpu);
8146 vcpu->cpu = cpu;
8147 put_cpu();
8148
36c3cc42
JK		 8149 vmx_segment_cache_clear(vmx);
8150
cd232ad0
NHE		 8151 vmcs12->launch_state = 1;
8152
8153 prepare_vmcs02(vcpu, vmcs12);
8154
6dfacadd
JK		 8155 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8156 return kvm_emulate_halt(vcpu);
8157
7af40ad3
JK		 8158 vmx->nested.nested_run_pending = 1;
8159
cd232ad0
NHE		 8160 /*
8161 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8162 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8163 * returned as far as L1 is concerned. It will only return (and set
8164 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8165 */
8166 return 1;
8167}
8168
4704d0be
NHE		 8169/*
8170 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8171 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8172 * This function returns the new value we should put in vmcs12.guest_cr0.
8173 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8174 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8175 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8176 * didn't trap the bit, because if L1 did, so would L0).
8177 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8178 * been modified by L2, and L1 knows it. So just leave the old value of
8179 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8180 * isn't relevant, because if L0 traps this bit it can set it to anything.
8181 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8182 * changed these bits, and therefore they need to be updated, but L0
8183 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8184 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8185 */
8186static inline unsigned long
8187vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8188{
8189 return
8190 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8191 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8192 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8193 vcpu->arch.cr0_guest_owned_bits));
8194}
8195
8196static inline unsigned long
8197vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8198{
8199 return
8200 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8201 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8202 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8203 vcpu->arch.cr4_guest_owned_bits));
8204}
8205
5f3d5799
JK		 8206static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8207 struct vmcs12 *vmcs12)
8208{
8209 u32 idt_vectoring;
8210 unsigned int nr;
8211
851eb667 8212 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8213 nr = vcpu->arch.exception.nr;
8214 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8215
8216 if (kvm_exception_is_soft(nr)) {
8217 vmcs12->vm_exit_instruction_len =
8218 vcpu->arch.event_exit_inst_len;
8219 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8220 } else
8221 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8222
8223 if (vcpu->arch.exception.has_error_code) {
8224 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8225 vmcs12->idt_vectoring_error_code =
8226 vcpu->arch.exception.error_code;
8227 }
8228
8229 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8230 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8231 vmcs12->idt_vectoring_info_field =
8232 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8233 } else if (vcpu->arch.interrupt.pending) {
8234 nr = vcpu->arch.interrupt.nr;
8235 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8236
8237 if (vcpu->arch.interrupt.soft) {
8238 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8239 vmcs12->vm_entry_instruction_len =
8240 vcpu->arch.event_exit_inst_len;
8241 } else
8242 idt_vectoring |= INTR_TYPE_EXT_INTR;
8243
8244 vmcs12->idt_vectoring_info_field = idt_vectoring;
8245 }
8246}
8247
b6b8a145
JK		 8248static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8249{
8250 struct vcpu_vmx *vmx = to_vmx(vcpu);
8251
f4124500
JK		 8252 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8253 vmx->nested.preemption_timer_expired) {
8254 if (vmx->nested.nested_run_pending)
8255 return -EBUSY;
8256 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8257 return 0;
8258 }
8259
b6b8a145 8260 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8261 if (vmx->nested.nested_run_pending ||
8262 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8263 return -EBUSY;
8264 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8265 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8266 INTR_INFO_VALID_MASK, 0);
8267 /*
8268 * The NMI-triggered VM exit counts as injection:
8269 * clear this one and block further NMIs.
8270 */
8271 vcpu->arch.nmi_pending = 0;
8272 vmx_set_nmi_mask(vcpu, true);
8273 return 0;
8274 }
8275
8276 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8277 nested_exit_on_intr(vcpu)) {
8278 if (vmx->nested.nested_run_pending)
8279 return -EBUSY;
8280 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8281 }
8282
8283 return 0;
8284}
8285
f4124500
JK		 8286static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8287{
8288 ktime_t remaining =
8289 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8290 u64 value;
8291
8292 if (ktime_to_ns(remaining) <= 0)
8293 return 0;
8294
8295 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8296 do_div(value, 1000000);
8297 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8298}
8299
4704d0be
NHE		 8300/*
8301 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8302 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8303 * and this function updates it to reflect the changes to the guest state while
8304 * L2 was running (and perhaps made some exits which were handled directly by L0
8305 * without going back to L1), and to reflect the exit reason.
8306 * Note that we do not have to copy here all VMCS fields, just those that
8307 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8308 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8309 * which already writes to vmcs12 directly.
8310 */
533558bc
JK		 8311static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8312 u32 exit_reason, u32 exit_intr_info,
8313 unsigned long exit_qualification)
4704d0be
NHE		 8314{
8315 /* update guest state fields: */
8316 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8317 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8318
8319 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8320 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8321 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8322 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8323
8324 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8325 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8326 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8327 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8328 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8329 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8330 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8331 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8332 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8333 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8334 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8335 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8336 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8337 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8338 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8339 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8340 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8341 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8342 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8343 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8344 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8345 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8346 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8347 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8348 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8349 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8350 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8351 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8352 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8353 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8354 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8355 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8356 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8357 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8358 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8359 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8360
4704d0be
NHE		 8361 vmcs12->guest_interruptibility_info =
8362 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8363 vmcs12->guest_pending_dbg_exceptions =
8364 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8365 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8366 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8367 else
8368 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8369
f4124500
JK		 8370 if (nested_cpu_has_preemption_timer(vmcs12)) {
8371 if (vmcs12->vm_exit_controls &
8372 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8373 vmcs12->vmx_preemption_timer_value =
8374 vmx_get_preemption_timer_value(vcpu);
8375 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8376 }
7854cbca 8377
3633cfc3
NHE		 8378 /*
8379 * In some cases (usually, nested EPT), L2 is allowed to change its
8380 * own CR3 without exiting. If it has changed it, we must keep it.
8381 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8382 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8383 *
8384 * Additionally, restore L2's PDPTR to vmcs12.
8385 */
8386 if (enable_ept) {
8387 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8388 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8389 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8390 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8391 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8392 }
8393
c18911a2
JK		 8394 vmcs12->vm_entry_controls =
8395 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8396 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8397
4704d0be
NHE		 8398 /* TODO: These cannot have changed unless we have MSR bitmaps and
8399 * the relevant bit asks not to trap the change */
8400 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8401 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8402 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8403 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8404 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8405 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8406 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8407 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8408 if (vmx_mpx_supported())
8409 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8410
8411 /* update exit information fields: */
8412
533558bc
JK		 8413 vmcs12->vm_exit_reason = exit_reason;
8414 vmcs12->exit_qualification = exit_qualification;
4704d0be 8415
533558bc 8416 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8417 if ((vmcs12->vm_exit_intr_info &
8418 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8419 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8420 vmcs12->vm_exit_intr_error_code =
8421 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8422 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8423 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8424 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8425
5f3d5799
JK		 8426 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8427 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8428 * instead of reading the real value. */
4704d0be 8429 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8430
8431 /*
8432 * Transfer the event that L0 or L1 may wanted to inject into
8433 * L2 to IDT_VECTORING_INFO_FIELD.
8434 */
8435 vmcs12_save_pending_event(vcpu, vmcs12);
8436 }
8437
8438 /*
8439 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8440 * preserved above and would only end up incorrectly in L1.
8441 */
8442 vcpu->arch.nmi_injected = false;
8443 kvm_clear_exception_queue(vcpu);
8444 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8445}
8446
8447/*
8448 * A part of what we need to when the nested L2 guest exits and we want to
8449 * run its L1 parent, is to reset L1's guest state to the host state specified
8450 * in vmcs12.
8451 * This function is to be called not only on normal nested exit, but also on
8452 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8453 * Failures During or After Loading Guest State").
8454 * This function should be called when the active VMCS is L1's (vmcs01).
8455 */
733568f9
JK		 8456static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8457 struct vmcs12 *vmcs12)
4704d0be 8458{
21feb4eb
ACL		 8459 struct kvm_segment seg;
8460
4704d0be
NHE		 8461 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8462 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8463 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8464 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8465 else
8466 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8467 vmx_set_efer(vcpu, vcpu->arch.efer);
8468
8469 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8470 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8471 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8472 /*
8473 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8474 * actually changed, because it depends on the current state of
8475 * fpu_active (which may have changed).
8476 * Note that vmx_set_cr0 refers to efer set above.
8477 */
9e3e4dbf 8478 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8479 /*
8480 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8481 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8482 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8483 */
8484 update_exception_bitmap(vcpu);
8485 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8486 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8487
8488 /*
8489 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8490 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8491 */
8492 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8493 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8494
29bf08f1 8495 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8496
4704d0be
NHE		 8497 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8498 kvm_mmu_reset_context(vcpu);
8499
feaf0c7d
GN		 8500 if (!enable_ept)
8501 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8502
4704d0be
NHE		 8503 if (enable_vpid) {
8504 /*
8505 * Trivially support vpid by letting L2s share their parent
8506 * L1's vpid. TODO: move to a more elaborate solution, giving
8507 * each L2 its own vpid and exposing the vpid feature to L1.
8508 */
8509 vmx_flush_tlb(vcpu);
8510 }
8511
8512
8513 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8514 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8515 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8516 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8517 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8518
36be0b9d
PB		 8519 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8520 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8521 vmcs_write64(GUEST_BNDCFGS, 0);
8522
44811c02 8523 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8524 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8525 vcpu->arch.pat = vmcs12->host_ia32_pat;
8526 }
4704d0be
NHE		 8527 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8528 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8529 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8530
21feb4eb
ACL		 8531 /* Set L1 segment info according to Intel SDM
8532 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8533 seg = (struct kvm_segment) {
8534 .base = 0,
8535 .limit = 0xFFFFFFFF,
8536 .selector = vmcs12->host_cs_selector,
8537 .type = 11,
8538 .present = 1,
8539 .s = 1,
8540 .g = 1
8541 };
8542 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8543 seg.l = 1;
8544 else
8545 seg.db = 1;
8546 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8547 seg = (struct kvm_segment) {
8548 .base = 0,
8549 .limit = 0xFFFFFFFF,
8550 .type = 3,
8551 .present = 1,
8552 .s = 1,
8553 .db = 1,
8554 .g = 1
8555 };
8556 seg.selector = vmcs12->host_ds_selector;
8557 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8558 seg.selector = vmcs12->host_es_selector;
8559 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8560 seg.selector = vmcs12->host_ss_selector;
8561 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8562 seg.selector = vmcs12->host_fs_selector;
8563 seg.base = vmcs12->host_fs_base;
8564 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8565 seg.selector = vmcs12->host_gs_selector;
8566 seg.base = vmcs12->host_gs_base;
8567 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8568 seg = (struct kvm_segment) {
205befd9 8569 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8570 .limit = 0x67,
8571 .selector = vmcs12->host_tr_selector,
8572 .type = 11,
8573 .present = 1
8574 };
8575 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8576
503cd0c5
JK		 8577 kvm_set_dr(vcpu, 7, 0x400);
8578 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8579}
8580
8581/*
8582 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8583 * and modify vmcs12 to make it see what it would expect to see there if
8584 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8585 */
533558bc
JK		 8586static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8587 u32 exit_intr_info,
8588 unsigned long exit_qualification)
4704d0be
NHE		 8589{
8590 struct vcpu_vmx *vmx = to_vmx(vcpu);
8591 int cpu;
8592 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8593
5f3d5799
JK		 8594 /* trying to cancel vmlaunch/vmresume is a bug */
8595 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8596
4704d0be 8597 leave_guest_mode(vcpu);
533558bc
JK		 8598 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8599 exit_qualification);
4704d0be 8600
542060ea
JK		 8601 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8602 vmcs12->exit_qualification,
8603 vmcs12->idt_vectoring_info_field,
8604 vmcs12->vm_exit_intr_info,
8605 vmcs12->vm_exit_intr_error_code,
8606 KVM_ISA_VMX);
4704d0be
NHE		 8607
8608 cpu = get_cpu();
8609 vmx->loaded_vmcs = &vmx->vmcs01;
8610 vmx_vcpu_put(vcpu);
8611 vmx_vcpu_load(vcpu, cpu);
8612 vcpu->cpu = cpu;
8613 put_cpu();
8614
2961e876
GN		 8615 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8616 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8617 vmx_segment_cache_clear(vmx);
8618
4704d0be
NHE		 8619 /* if no vmcs02 cache requested, remove the one we used */
8620 if (VMCS02_POOL_SIZE == 0)
8621 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8622
8623 load_vmcs12_host_state(vcpu, vmcs12);
8624
27fc51b2 8625 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8626 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8627
8628 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8629 vmx->host_rsp = 0;
8630
8631 /* Unpin physical memory we referred to in vmcs02 */
8632 if (vmx->nested.apic_access_page) {
8633 nested_release_page(vmx->nested.apic_access_page);
8634 vmx->nested.apic_access_page = 0;
8635 }
8636
8637 /*
8638 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8639 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8640 * success or failure flag accordingly.
8641 */
8642 if (unlikely(vmx->fail)) {
8643 vmx->fail = 0;
8644 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8645 } else
8646 nested_vmx_succeed(vcpu);
012f83cb
AG		 8647 if (enable_shadow_vmcs)
8648 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8649
8650 /* in case we halted in L2 */
8651 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8652}
8653
42124925
JK		 8654/*
8655 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8656 */
8657static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8658{
8659 if (is_guest_mode(vcpu))
533558bc 8660 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8661 free_nested(to_vmx(vcpu));
8662}
8663
7c177938
NHE		 8664/*
8665 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8666 * 23.7 "VM-entry failures during or after loading guest state" (this also
8667 * lists the acceptable exit-reason and exit-qualification parameters).
8668 * It should only be called before L2 actually succeeded to run, and when
8669 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8670 */
8671static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8672 struct vmcs12 *vmcs12,
8673 u32 reason, unsigned long qualification)
8674{
8675 load_vmcs12_host_state(vcpu, vmcs12);
8676 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8677 vmcs12->exit_qualification = qualification;
8678 nested_vmx_succeed(vcpu);
012f83cb
AG		 8679 if (enable_shadow_vmcs)
8680 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8681}
8682
8a76d7f2
JR		 8683static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8684 struct x86_instruction_info *info,
8685 enum x86_intercept_stage stage)
8686{
8687 return X86EMUL_CONTINUE;
8688}
8689
cbdd1bea 8690static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8691 .cpu_has_kvm_support = cpu_has_kvm_support,
8692 .disabled_by_bios = vmx_disabled_by_bios,
8693 .hardware_setup = hardware_setup,
8694 .hardware_unsetup = hardware_unsetup,
002c7f7c 8695 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8696 .hardware_enable = hardware_enable,
8697 .hardware_disable = hardware_disable,
04547156 8698 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8699
8700 .vcpu_create = vmx_create_vcpu,
8701 .vcpu_free = vmx_free_vcpu,
04d2cc77 8702 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8703
04d2cc77 8704 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8705 .vcpu_load = vmx_vcpu_load,
8706 .vcpu_put = vmx_vcpu_put,
8707
c8639010 8708 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8709 .get_msr = vmx_get_msr,
8710 .set_msr = vmx_set_msr,
8711 .get_segment_base = vmx_get_segment_base,
8712 .get_segment = vmx_get_segment,
8713 .set_segment = vmx_set_segment,
2e4d2653 8714 .get_cpl = vmx_get_cpl,
6aa8b732 8715 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8716 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8717 .decache_cr3 = vmx_decache_cr3,
25c4c276 8718 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8719 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8720 .set_cr3 = vmx_set_cr3,
8721 .set_cr4 = vmx_set_cr4,
6aa8b732 8722 .set_efer = vmx_set_efer,
6aa8b732
AK		 8723 .get_idt = vmx_get_idt,
8724 .set_idt = vmx_set_idt,
8725 .get_gdt = vmx_get_gdt,
8726 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8727 .get_dr6 = vmx_get_dr6,
8728 .set_dr6 = vmx_set_dr6,
020df079 8729 .set_dr7 = vmx_set_dr7,
81908bf4 8730 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8731 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8732 .get_rflags = vmx_get_rflags,
8733 .set_rflags = vmx_set_rflags,
ebcbab4c 8734 .fpu_activate = vmx_fpu_activate,
02daab21 8735 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8736
8737 .tlb_flush = vmx_flush_tlb,
6aa8b732 8738
6aa8b732 8739 .run = vmx_vcpu_run,
6062d012 8740 .handle_exit = vmx_handle_exit,
6aa8b732 8741 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8742 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8743 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8744 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8745 .set_irq = vmx_inject_irq,
95ba8273 8746 .set_nmi = vmx_inject_nmi,
298101da 8747 .queue_exception = vmx_queue_exception,
b463a6f7 8748 .cancel_injection = vmx_cancel_injection,
78646121 8749 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8750 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8751 .get_nmi_mask = vmx_get_nmi_mask,
8752 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8753 .enable_nmi_window = enable_nmi_window,
8754 .enable_irq_window = enable_irq_window,
8755 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8756 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8757 .vm_has_apicv = vmx_vm_has_apicv,
8758 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8759 .hwapic_irr_update = vmx_hwapic_irr_update,
8760 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8761 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8762 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8763
cbc94022 8764 .set_tss_addr = vmx_set_tss_addr,
67253af5 8765 .get_tdp_level = get_ept_level,
4b12f0de 8766 .get_mt_mask = vmx_get_mt_mask,
229456fc 8767
586f9607 8768 .get_exit_info = vmx_get_exit_info,
586f9607 8769
17cc3935 8770 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8771
8772 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8773
8774 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8775 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8776
8777 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8778
8779 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8780
4051b188 8781 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8782 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8783 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8784 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8785 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8786 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8787
8788 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8789
8790 .check_intercept = vmx_check_intercept,
a547c6db 8791 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8792 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8793
8794 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8795};
8796
8797static int __init vmx_init(void)
8798{
8d14695f 8799 int r, i, msr;
26bb0981
AK		 8800
8801 rdmsrl_safe(MSR_EFER, &host_efer);
8802
8803 for (i = 0; i < NR_VMX_MSR; ++i)
8804 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8805
3e7c73e9 8806 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8807 if (!vmx_io_bitmap_a)
8808 return -ENOMEM;
8809
2106a548
GC		 8810 r = -ENOMEM;
8811
3e7c73e9 8812 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8813 if (!vmx_io_bitmap_b)
fdef3ad1 8814 goto out;
fdef3ad1 8815
5897297b 8816 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8817 if (!vmx_msr_bitmap_legacy)
25c5f225 8818 goto out1;
2106a548 8819
8d14695f
YZ		 8820 vmx_msr_bitmap_legacy_x2apic =
8821 (unsigned long *)__get_free_page(GFP_KERNEL);
8822 if (!vmx_msr_bitmap_legacy_x2apic)
8823 goto out2;
25c5f225 8824
5897297b 8825 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8826 if (!vmx_msr_bitmap_longmode)
8d14695f 8827 goto out3;
2106a548 8828
8d14695f
YZ		 8829 vmx_msr_bitmap_longmode_x2apic =
8830 (unsigned long *)__get_free_page(GFP_KERNEL);
8831 if (!vmx_msr_bitmap_longmode_x2apic)
8832 goto out4;
4607c2d7
AG		 8833 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8834 if (!vmx_vmread_bitmap)
8835 goto out5;
8836
8837 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8838 if (!vmx_vmwrite_bitmap)
8839 goto out6;
8840
8841 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8842 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 8843
fdef3ad1
HQ		 8844 /*
8845 * Allow direct access to the PC debug port (it is often used for I/O
8846 * delays, but the vmexits simply slow things down).
8847 */
3e7c73e9
AK		 8848 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8849 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8850
3e7c73e9 8851 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8852
5897297b
AK		 8853 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8854 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8855
2384d2b3
SY		 8856 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8857
0ee75bea
AK		 8858 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8859 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8860 if (r)
4607c2d7 8861 goto out7;
25c5f225 8862
8f536b76
ZY		 8863#ifdef CONFIG_KEXEC
8864 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8865 crash_vmclear_local_loaded_vmcss);
8866#endif
8867
5897297b
AK		 8868 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8869 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8870 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8871 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8872 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8873 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8874 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8875
8d14695f
YZ		 8876 memcpy(vmx_msr_bitmap_legacy_x2apic,
8877 vmx_msr_bitmap_legacy, PAGE_SIZE);
8878 memcpy(vmx_msr_bitmap_longmode_x2apic,
8879 vmx_msr_bitmap_longmode, PAGE_SIZE);
8880
01e439be 8881 if (enable_apicv) {
8d14695f
YZ		 8882 for (msr = 0x800; msr <= 0x8ff; msr++)
8883 vmx_disable_intercept_msr_read_x2apic(msr);
8884
8885 /* According SDM, in x2apic mode, the whole id reg is used.
8886 * But in KVM, it only use the highest eight bits. Need to
8887 * intercept it */
8888 vmx_enable_intercept_msr_read_x2apic(0x802);
8889 /* TMCCT */
8890 vmx_enable_intercept_msr_read_x2apic(0x839);
8891 /* TPR */
8892 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8893 /* EOI */
8894 vmx_disable_intercept_msr_write_x2apic(0x80b);
8895 /* SELF-IPI */
8896 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8897 }
fdef3ad1 8898
089d034e 8899 if (enable_ept) {
3f6d8c8a
XH		 8900 kvm_mmu_set_mask_ptes(0ull,
8901 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8902 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8903 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8904 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8905 kvm_enable_tdp();
8906 } else
8907 kvm_disable_tdp();
1439442c 8908
fdef3ad1
HQ		 8909 return 0;
8910
4607c2d7
AG		 8911out7:
8912 free_page((unsigned long)vmx_vmwrite_bitmap);
8913out6:
8914 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8915out5:
8916 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8917out4:
5897297b 8918 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8919out3:
8920 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8921out2:
5897297b 8922 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8923out1:
3e7c73e9 8924 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8925out:
3e7c73e9 8926 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8927 return r;
6aa8b732
AK		 8928}
8929
8930static void __exit vmx_exit(void)
8931{
8d14695f
YZ		 8932 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8933 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8934 free_page((unsigned long)vmx_msr_bitmap_legacy);
8935 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8936 free_page((unsigned long)vmx_io_bitmap_b);
8937 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8938 free_page((unsigned long)vmx_vmwrite_bitmap);
8939 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8940
8f536b76
ZY		 8941#ifdef CONFIG_KEXEC
8942 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8943 synchronize_rcu();
8944#endif
8945
cb498ea2 8946 kvm_exit();
6aa8b732
AK		 8947}
8948
8949module_init(vmx_init)
8950module_exit(vmx_exit)
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