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kvm/x86: implement hv EOI assist
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
3573e22c 357 gpa_t vmxon_ptr;
a9d30f33
NHE		 358
359 /* The guest-physical address of the current VMCS L1 keeps for L2 */
360 gpa_t current_vmptr;
361 /* The host-usable pointer to the above */
362 struct page *current_vmcs12_page;
363 struct vmcs12 *current_vmcs12;
8de48833 364 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 365 /*
366 * Indicates if the shadow vmcs must be updated with the
367 * data hold by vmcs12
368 */
369 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 370
371 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
372 struct list_head vmcs02_pool;
373 int vmcs02_num;
fe3ef05c 374 u64 vmcs01_tsc_offset;
644d711a
NHE		 375 /* L2 must run next, and mustn't decide to exit to L1. */
376 bool nested_run_pending;
fe3ef05c
NHE		 377 /*
378 * Guest pages referred to in vmcs02 with host-physical pointers, so
379 * we must keep them pinned while L2 runs.
380 */
381 struct page *apic_access_page;
b3897a49 382 u64 msr_ia32_feature_control;
f4124500
JK		 383
384 struct hrtimer preemption_timer;
385 bool preemption_timer_expired;
ec378aee
NHE		 386};
387
01e439be
YZ		 388#define POSTED_INTR_ON 0
389/* Posted-Interrupt Descriptor */
390struct pi_desc {
391 u32 pir[8]; /* Posted interrupt requested */
392 u32 control; /* bit 0 of control is outstanding notification bit */
393 u32 rsvd[7];
394} __aligned(64);
395
a20ed54d
YZ		 396static bool pi_test_and_set_on(struct pi_desc *pi_desc)
397{
398 return test_and_set_bit(POSTED_INTR_ON,
399 (unsigned long *)&pi_desc->control);
400}
401
402static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
403{
404 return test_and_clear_bit(POSTED_INTR_ON,
405 (unsigned long *)&pi_desc->control);
406}
407
408static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
409{
410 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
411}
412
a2fa3e9f 413struct vcpu_vmx {
fb3f0f51 414 struct kvm_vcpu vcpu;
313dbd49 415 unsigned long host_rsp;
29bd8a78 416 u8 fail;
69c73028 417 u8 cpl;
9d58b931 418 bool nmi_known_unmasked;
51aa01d1 419 u32 exit_intr_info;
1155f76a 420 u32 idt_vectoring_info;
6de12732 421 ulong rflags;
26bb0981 422 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 423 int nmsrs;
424 int save_nmsrs;
a547c6db 425 unsigned long host_idt_base;
a2fa3e9f 426#ifdef CONFIG_X86_64
44ea2b17
AK		 427 u64 msr_host_kernel_gs_base;
428 u64 msr_guest_kernel_gs_base;
a2fa3e9f 429#endif
2961e876
GN		 430 u32 vm_entry_controls_shadow;
431 u32 vm_exit_controls_shadow;
d462b819
NHE		 432 /*
433 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
434 * non-nested (L1) guest, it always points to vmcs01. For a nested
435 * guest (L2), it points to a different VMCS.
436 */
437 struct loaded_vmcs vmcs01;
438 struct loaded_vmcs *loaded_vmcs;
439 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 440 struct msr_autoload {
441 unsigned nr;
442 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
443 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
444 } msr_autoload;
a2fa3e9f
GH		 445 struct {
446 int loaded;
447 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 448#ifdef CONFIG_X86_64
449 u16 ds_sel, es_sel;
450#endif
152d3f2f
LV		 451 int gs_ldt_reload_needed;
452 int fs_reload_needed;
da8999d3 453 u64 msr_host_bndcfgs;
d77c26fc 454 } host_state;
9c8cba37 455 struct {
7ffd92c5 456 int vm86_active;
78ac8b47 457 ulong save_rflags;
f5f7b2fe
AK		 458 struct kvm_segment segs[8];
459 } rmode;
460 struct {
461 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 462 struct kvm_save_segment {
463 u16 selector;
464 unsigned long base;
465 u32 limit;
466 u32 ar;
f5f7b2fe 467 } seg[8];
2fb92db1 468 } segment_cache;
2384d2b3 469 int vpid;
04fa4d32 470 bool emulation_required;
3b86cd99
JK		 471
472 /* Support for vnmi-less CPUs */
473 int soft_vnmi_blocked;
474 ktime_t entry_time;
475 s64 vnmi_blocked_time;
a0861c02 476 u32 exit_reason;
4e47c7a6
SY		 477
478 bool rdtscp_enabled;
ec378aee 479
01e439be
YZ		 480 /* Posted interrupt descriptor */
481 struct pi_desc pi_desc;
482
ec378aee
NHE		 483 /* Support for a guest hypervisor (nested VMX) */
484 struct nested_vmx nested;
a2fa3e9f
GH		 485};
486
2fb92db1
AK		 487enum segment_cache_field {
488 SEG_FIELD_SEL = 0,
489 SEG_FIELD_BASE = 1,
490 SEG_FIELD_LIMIT = 2,
491 SEG_FIELD_AR = 3,
492
493 SEG_FIELD_NR = 4
494};
495
a2fa3e9f
GH		 496static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
497{
fb3f0f51 498 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 499}
500
22bd0358
NHE		 501#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
502#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
503#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
504 [number##_HIGH] = VMCS12_OFFSET(name)+4
505
4607c2d7
AG		 506
507static const unsigned long shadow_read_only_fields[] = {
508 /*
509 * We do NOT shadow fields that are modified when L0
510 * traps and emulates any vmx instruction (e.g. VMPTRLD,
511 * VMXON...) executed by L1.
512 * For example, VM_INSTRUCTION_ERROR is read
513 * by L1 if a vmx instruction fails (part of the error path).
514 * Note the code assumes this logic. If for some reason
515 * we start shadowing these fields then we need to
516 * force a shadow sync when L0 emulates vmx instructions
517 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
518 * by nested_vmx_failValid)
519 */
520 VM_EXIT_REASON,
521 VM_EXIT_INTR_INFO,
522 VM_EXIT_INSTRUCTION_LEN,
523 IDT_VECTORING_INFO_FIELD,
524 IDT_VECTORING_ERROR_CODE,
525 VM_EXIT_INTR_ERROR_CODE,
526 EXIT_QUALIFICATION,
527 GUEST_LINEAR_ADDRESS,
528 GUEST_PHYSICAL_ADDRESS
529};
530static const int max_shadow_read_only_fields =
531 ARRAY_SIZE(shadow_read_only_fields);
532
533static const unsigned long shadow_read_write_fields[] = {
534 GUEST_RIP,
535 GUEST_RSP,
536 GUEST_CR0,
537 GUEST_CR3,
538 GUEST_CR4,
539 GUEST_INTERRUPTIBILITY_INFO,
540 GUEST_RFLAGS,
541 GUEST_CS_SELECTOR,
542 GUEST_CS_AR_BYTES,
543 GUEST_CS_LIMIT,
544 GUEST_CS_BASE,
545 GUEST_ES_BASE,
36be0b9d 546 GUEST_BNDCFGS,
4607c2d7
AG		 547 CR0_GUEST_HOST_MASK,
548 CR0_READ_SHADOW,
549 CR4_READ_SHADOW,
550 TSC_OFFSET,
551 EXCEPTION_BITMAP,
552 CPU_BASED_VM_EXEC_CONTROL,
553 VM_ENTRY_EXCEPTION_ERROR_CODE,
554 VM_ENTRY_INTR_INFO_FIELD,
555 VM_ENTRY_INSTRUCTION_LEN,
556 VM_ENTRY_EXCEPTION_ERROR_CODE,
557 HOST_FS_BASE,
558 HOST_GS_BASE,
559 HOST_FS_SELECTOR,
560 HOST_GS_SELECTOR
561};
562static const int max_shadow_read_write_fields =
563 ARRAY_SIZE(shadow_read_write_fields);
564
772e0318 565static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 566 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
567 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
568 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
569 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
570 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
571 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
572 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
573 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
574 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
575 FIELD(HOST_ES_SELECTOR, host_es_selector),
576 FIELD(HOST_CS_SELECTOR, host_cs_selector),
577 FIELD(HOST_SS_SELECTOR, host_ss_selector),
578 FIELD(HOST_DS_SELECTOR, host_ds_selector),
579 FIELD(HOST_FS_SELECTOR, host_fs_selector),
580 FIELD(HOST_GS_SELECTOR, host_gs_selector),
581 FIELD(HOST_TR_SELECTOR, host_tr_selector),
582 FIELD64(IO_BITMAP_A, io_bitmap_a),
583 FIELD64(IO_BITMAP_B, io_bitmap_b),
584 FIELD64(MSR_BITMAP, msr_bitmap),
585 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
586 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
587 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
588 FIELD64(TSC_OFFSET, tsc_offset),
589 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
590 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
591 FIELD64(EPT_POINTER, ept_pointer),
592 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
593 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
594 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
595 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
596 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
597 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
598 FIELD64(GUEST_PDPTR0, guest_pdptr0),
599 FIELD64(GUEST_PDPTR1, guest_pdptr1),
600 FIELD64(GUEST_PDPTR2, guest_pdptr2),
601 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 602 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 603 FIELD64(HOST_IA32_PAT, host_ia32_pat),
604 FIELD64(HOST_IA32_EFER, host_ia32_efer),
605 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
606 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
607 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
608 FIELD(EXCEPTION_BITMAP, exception_bitmap),
609 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
610 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
611 FIELD(CR3_TARGET_COUNT, cr3_target_count),
612 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
613 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
614 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
615 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
616 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
617 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
618 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
619 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
620 FIELD(TPR_THRESHOLD, tpr_threshold),
621 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
622 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
623 FIELD(VM_EXIT_REASON, vm_exit_reason),
624 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
625 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
626 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
627 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
628 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
629 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
630 FIELD(GUEST_ES_LIMIT, guest_es_limit),
631 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
632 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
633 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
634 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
635 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
636 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
637 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
638 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
639 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
640 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
641 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
642 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
643 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
644 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
645 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
646 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
647 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
648 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
649 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
650 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
651 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 652 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 653 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
654 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
655 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
656 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
657 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
658 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
659 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
660 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
661 FIELD(EXIT_QUALIFICATION, exit_qualification),
662 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
663 FIELD(GUEST_CR0, guest_cr0),
664 FIELD(GUEST_CR3, guest_cr3),
665 FIELD(GUEST_CR4, guest_cr4),
666 FIELD(GUEST_ES_BASE, guest_es_base),
667 FIELD(GUEST_CS_BASE, guest_cs_base),
668 FIELD(GUEST_SS_BASE, guest_ss_base),
669 FIELD(GUEST_DS_BASE, guest_ds_base),
670 FIELD(GUEST_FS_BASE, guest_fs_base),
671 FIELD(GUEST_GS_BASE, guest_gs_base),
672 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
673 FIELD(GUEST_TR_BASE, guest_tr_base),
674 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
675 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
676 FIELD(GUEST_DR7, guest_dr7),
677 FIELD(GUEST_RSP, guest_rsp),
678 FIELD(GUEST_RIP, guest_rip),
679 FIELD(GUEST_RFLAGS, guest_rflags),
680 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
681 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
682 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
683 FIELD(HOST_CR0, host_cr0),
684 FIELD(HOST_CR3, host_cr3),
685 FIELD(HOST_CR4, host_cr4),
686 FIELD(HOST_FS_BASE, host_fs_base),
687 FIELD(HOST_GS_BASE, host_gs_base),
688 FIELD(HOST_TR_BASE, host_tr_base),
689 FIELD(HOST_GDTR_BASE, host_gdtr_base),
690 FIELD(HOST_IDTR_BASE, host_idtr_base),
691 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
692 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
693 FIELD(HOST_RSP, host_rsp),
694 FIELD(HOST_RIP, host_rip),
695};
696static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
697
698static inline short vmcs_field_to_offset(unsigned long field)
699{
700 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
701 return -1;
702 return vmcs_field_to_offset_table[field];
703}
704
a9d30f33
NHE		 705static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
706{
707 return to_vmx(vcpu)->nested.current_vmcs12;
708}
709
710static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
711{
712 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 713 if (is_error_page(page))
a9d30f33 714 return NULL;
32cad84f 715
a9d30f33
NHE		 716 return page;
717}
718
719static void nested_release_page(struct page *page)
720{
721 kvm_release_page_dirty(page);
722}
723
724static void nested_release_page_clean(struct page *page)
725{
726 kvm_release_page_clean(page);
727}
728
bfd0a56b 729static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 730static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 731static void kvm_cpu_vmxon(u64 addr);
732static void kvm_cpu_vmxoff(void);
93c4adc7 733static bool vmx_mpx_supported(void);
776e58ea 734static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 735static void vmx_set_segment(struct kvm_vcpu *vcpu,
736 struct kvm_segment *var, int seg);
737static void vmx_get_segment(struct kvm_vcpu *vcpu,
738 struct kvm_segment *var, int seg);
d99e4152
GN		 739static bool guest_state_valid(struct kvm_vcpu *vcpu);
740static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 741static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 742static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 743static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
36be0b9d 744static bool vmx_mpx_supported(void);
75880a01 745
6aa8b732
AK		 746static DEFINE_PER_CPU(struct vmcs *, vmxarea);
747static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 748/*
749 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
750 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
751 */
752static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 753static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 754
3e7c73e9
AK		 755static unsigned long *vmx_io_bitmap_a;
756static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 757static unsigned long *vmx_msr_bitmap_legacy;
758static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 759static unsigned long *vmx_msr_bitmap_legacy_x2apic;
760static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 761static unsigned long *vmx_vmread_bitmap;
762static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 763
110312c8 764static bool cpu_has_load_ia32_efer;
8bf00a52 765static bool cpu_has_load_perf_global_ctrl;
110312c8 766
2384d2b3
SY		 767static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
768static DEFINE_SPINLOCK(vmx_vpid_lock);
769
1c3d14fe 770static struct vmcs_config {
6aa8b732
AK		 771 int size;
772 int order;
773 u32 revision_id;
1c3d14fe
YS		 774 u32 pin_based_exec_ctrl;
775 u32 cpu_based_exec_ctrl;
f78e0e2e 776 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 777 u32 vmexit_ctrl;
778 u32 vmentry_ctrl;
779} vmcs_config;
6aa8b732 780
efff9e53 781static struct vmx_capability {
d56f546d
SY		 782 u32 ept;
783 u32 vpid;
784} vmx_capability;
785
6aa8b732
AK		 786#define VMX_SEGMENT_FIELD(seg) \
787 [VCPU_SREG_##seg] = { \
788 .selector = GUEST_##seg##_SELECTOR, \
789 .base = GUEST_##seg##_BASE, \
790 .limit = GUEST_##seg##_LIMIT, \
791 .ar_bytes = GUEST_##seg##_AR_BYTES, \
792 }
793
772e0318 794static const struct kvm_vmx_segment_field {
6aa8b732
AK		 795 unsigned selector;
796 unsigned base;
797 unsigned limit;
798 unsigned ar_bytes;
799} kvm_vmx_segment_fields[] = {
800 VMX_SEGMENT_FIELD(CS),
801 VMX_SEGMENT_FIELD(DS),
802 VMX_SEGMENT_FIELD(ES),
803 VMX_SEGMENT_FIELD(FS),
804 VMX_SEGMENT_FIELD(GS),
805 VMX_SEGMENT_FIELD(SS),
806 VMX_SEGMENT_FIELD(TR),
807 VMX_SEGMENT_FIELD(LDTR),
808};
809
26bb0981
AK		 810static u64 host_efer;
811
6de4f3ad
AK		 812static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
813
4d56c8a7 814/*
8c06585d 815 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 816 * away by decrementing the array size.
817 */
6aa8b732 818static const u32 vmx_msr_index[] = {
05b3e0c2 819#ifdef CONFIG_X86_64
44ea2b17 820 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 821#endif
8c06585d 822 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 823};
9d8f549d 824#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 825
31299944 826static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 827{
828 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
829 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 830 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 831}
832
31299944 833static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 834{
835 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
836 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 837 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 838}
839
31299944 840static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 841{
842 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
843 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 844 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 845}
846
31299944 847static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 848{
849 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
850 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
851}
852
31299944 853static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 854{
855 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
856 INTR_INFO_VALID_MASK)) ==
857 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
858}
859
31299944 860static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 861{
04547156 862 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 863}
864
31299944 865static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 866{
04547156 867 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 868}
869
31299944 870static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 871{
04547156 872 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 873}
874
31299944 875static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 876{
04547156
SY		 877 return vmcs_config.cpu_based_exec_ctrl &
878 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 879}
880
774ead3a 881static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 882{
04547156
SY		 883 return vmcs_config.cpu_based_2nd_exec_ctrl &
884 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
885}
886
8d14695f
YZ		 887static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
888{
889 return vmcs_config.cpu_based_2nd_exec_ctrl &
890 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
891}
892
83d4c286
YZ		 893static inline bool cpu_has_vmx_apic_register_virt(void)
894{
895 return vmcs_config.cpu_based_2nd_exec_ctrl &
896 SECONDARY_EXEC_APIC_REGISTER_VIRT;
897}
898
c7c9c56c
YZ		 899static inline bool cpu_has_vmx_virtual_intr_delivery(void)
900{
901 return vmcs_config.cpu_based_2nd_exec_ctrl &
902 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
903}
904
01e439be
YZ		 905static inline bool cpu_has_vmx_posted_intr(void)
906{
907 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
908}
909
910static inline bool cpu_has_vmx_apicv(void)
911{
912 return cpu_has_vmx_apic_register_virt() &&
913 cpu_has_vmx_virtual_intr_delivery() &&
914 cpu_has_vmx_posted_intr();
915}
916
04547156
SY		 917static inline bool cpu_has_vmx_flexpriority(void)
918{
919 return cpu_has_vmx_tpr_shadow() &&
920 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 921}
922
e799794e
MT		 923static inline bool cpu_has_vmx_ept_execute_only(void)
924{
31299944 925 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 926}
927
928static inline bool cpu_has_vmx_eptp_uncacheable(void)
929{
31299944 930 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 931}
932
933static inline bool cpu_has_vmx_eptp_writeback(void)
934{
31299944 935 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 936}
937
938static inline bool cpu_has_vmx_ept_2m_page(void)
939{
31299944 940 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 941}
942
878403b7
SY		 943static inline bool cpu_has_vmx_ept_1g_page(void)
944{
31299944 945 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 946}
947
4bc9b982
SY		 948static inline bool cpu_has_vmx_ept_4levels(void)
949{
950 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
951}
952
83c3a331
XH		 953static inline bool cpu_has_vmx_ept_ad_bits(void)
954{
955 return vmx_capability.ept & VMX_EPT_AD_BIT;
956}
957
31299944 958static inline bool cpu_has_vmx_invept_context(void)
d56f546d 959{
31299944 960 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 961}
962
31299944 963static inline bool cpu_has_vmx_invept_global(void)
d56f546d 964{
31299944 965 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 966}
967
518c8aee
GJ		 968static inline bool cpu_has_vmx_invvpid_single(void)
969{
970 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
971}
972
b9d762fa
GJ		 973static inline bool cpu_has_vmx_invvpid_global(void)
974{
975 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
976}
977
31299944 978static inline bool cpu_has_vmx_ept(void)
d56f546d 979{
04547156
SY		 980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 982}
983
31299944 984static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 985{
986 return vmcs_config.cpu_based_2nd_exec_ctrl &
987 SECONDARY_EXEC_UNRESTRICTED_GUEST;
988}
989
31299944 990static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 991{
992 return vmcs_config.cpu_based_2nd_exec_ctrl &
993 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
994}
995
31299944 996static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 997{
6d3e435e 998 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 999}
1000
31299944 1001static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1002{
04547156
SY		 1003 return vmcs_config.cpu_based_2nd_exec_ctrl &
1004 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1005}
1006
31299944 1007static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1008{
1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_RDTSCP;
1011}
1012
ad756a16
MJ		 1013static inline bool cpu_has_vmx_invpcid(void)
1014{
1015 return vmcs_config.cpu_based_2nd_exec_ctrl &
1016 SECONDARY_EXEC_ENABLE_INVPCID;
1017}
1018
31299944 1019static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1020{
1021 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1022}
1023
f5f48ee1
SY		 1024static inline bool cpu_has_vmx_wbinvd_exit(void)
1025{
1026 return vmcs_config.cpu_based_2nd_exec_ctrl &
1027 SECONDARY_EXEC_WBINVD_EXITING;
1028}
1029
abc4fc58
AG		 1030static inline bool cpu_has_vmx_shadow_vmcs(void)
1031{
1032 u64 vmx_msr;
1033 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1034 /* check if the cpu supports writing r/o exit information fields */
1035 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1036 return false;
1037
1038 return vmcs_config.cpu_based_2nd_exec_ctrl &
1039 SECONDARY_EXEC_SHADOW_VMCS;
1040}
1041
04547156
SY		 1042static inline bool report_flexpriority(void)
1043{
1044 return flexpriority_enabled;
1045}
1046
fe3ef05c
NHE		 1047static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1048{
1049 return vmcs12->cpu_based_vm_exec_control & bit;
1050}
1051
1052static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1053{
1054 return (vmcs12->cpu_based_vm_exec_control &
1055 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1056 (vmcs12->secondary_vm_exec_control & bit);
1057}
1058
f5c4368f 1059static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1060{
1061 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1062}
1063
f4124500
JK		 1064static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1065{
1066 return vmcs12->pin_based_vm_exec_control &
1067 PIN_BASED_VMX_PREEMPTION_TIMER;
1068}
1069
155a97a3
NHE		 1070static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1071{
1072 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1073}
1074
644d711a
NHE		 1075static inline bool is_exception(u32 intr_info)
1076{
1077 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1078 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1079}
1080
533558bc
JK		 1081static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1082 u32 exit_intr_info,
1083 unsigned long exit_qualification);
7c177938
NHE		 1084static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1085 struct vmcs12 *vmcs12,
1086 u32 reason, unsigned long qualification);
1087
8b9cf98c 1088static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1089{
1090 int i;
1091
a2fa3e9f 1092 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1093 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1094 return i;
1095 return -1;
1096}
1097
2384d2b3
SY		 1098static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1099{
1100 struct {
1101 u64 vpid : 16;
1102 u64 rsvd : 48;
1103 u64 gva;
1104 } operand = { vpid, 0, gva };
1105
4ecac3fd 1106 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1107 /* CF==1 or ZF==1 --> rc = -1 */
1108 "; ja 1f ; ud2 ; 1:"
1109 : : "a"(&operand), "c"(ext) : "cc", "memory");
1110}
1111
1439442c
SY		 1112static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1113{
1114 struct {
1115 u64 eptp, gpa;
1116 } operand = {eptp, gpa};
1117
4ecac3fd 1118 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1119 /* CF==1 or ZF==1 --> rc = -1 */
1120 "; ja 1f ; ud2 ; 1:\n"
1121 : : "a" (&operand), "c" (ext) : "cc", "memory");
1122}
1123
26bb0981 1124static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1125{
1126 int i;
1127
8b9cf98c 1128 i = __find_msr_index(vmx, msr);
a75beee6 1129 if (i >= 0)
a2fa3e9f 1130 return &vmx->guest_msrs[i];
8b6d44c7 1131 return NULL;
7725f0ba
AK		 1132}
1133
6aa8b732
AK		 1134static void vmcs_clear(struct vmcs *vmcs)
1135{
1136 u64 phys_addr = __pa(vmcs);
1137 u8 error;
1138
4ecac3fd 1139 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1140 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1141 : "cc", "memory");
1142 if (error)
1143 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1144 vmcs, phys_addr);
1145}
1146
d462b819
NHE		 1147static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1148{
1149 vmcs_clear(loaded_vmcs->vmcs);
1150 loaded_vmcs->cpu = -1;
1151 loaded_vmcs->launched = 0;
1152}
1153
7725b894
DX		 1154static void vmcs_load(struct vmcs *vmcs)
1155{
1156 u64 phys_addr = __pa(vmcs);
1157 u8 error;
1158
1159 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1160 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1161 : "cc", "memory");
1162 if (error)
2844d849 1163 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1164 vmcs, phys_addr);
1165}
1166
8f536b76
ZY		 1167#ifdef CONFIG_KEXEC
1168/*
1169 * This bitmap is used to indicate whether the vmclear
1170 * operation is enabled on all cpus. All disabled by
1171 * default.
1172 */
1173static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1174
1175static inline void crash_enable_local_vmclear(int cpu)
1176{
1177 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1178}
1179
1180static inline void crash_disable_local_vmclear(int cpu)
1181{
1182 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1183}
1184
1185static inline int crash_local_vmclear_enabled(int cpu)
1186{
1187 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1188}
1189
1190static void crash_vmclear_local_loaded_vmcss(void)
1191{
1192 int cpu = raw_smp_processor_id();
1193 struct loaded_vmcs *v;
1194
1195 if (!crash_local_vmclear_enabled(cpu))
1196 return;
1197
1198 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1199 loaded_vmcss_on_cpu_link)
1200 vmcs_clear(v->vmcs);
1201}
1202#else
1203static inline void crash_enable_local_vmclear(int cpu) { }
1204static inline void crash_disable_local_vmclear(int cpu) { }
1205#endif /* CONFIG_KEXEC */
1206
d462b819 1207static void __loaded_vmcs_clear(void *arg)
6aa8b732 1208{
d462b819 1209 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1210 int cpu = raw_smp_processor_id();
6aa8b732 1211
d462b819
NHE		 1212 if (loaded_vmcs->cpu != cpu)
1213 return; /* vcpu migration can race with cpu offline */
1214 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1215 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1216 crash_disable_local_vmclear(cpu);
d462b819 1217 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1218
1219 /*
1220 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1221 * is before setting loaded_vmcs->vcpu to -1 which is done in
1222 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1223 * then adds the vmcs into percpu list before it is deleted.
1224 */
1225 smp_wmb();
1226
d462b819 1227 loaded_vmcs_init(loaded_vmcs);
8f536b76 1228 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1229}
1230
d462b819 1231static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1232{
e6c7d321
XG		 1233 int cpu = loaded_vmcs->cpu;
1234
1235 if (cpu != -1)
1236 smp_call_function_single(cpu,
1237 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1238}
1239
1760dd49 1240static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1241{
1242 if (vmx->vpid == 0)
1243 return;
1244
518c8aee
GJ		 1245 if (cpu_has_vmx_invvpid_single())
1246 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1247}
1248
b9d762fa
GJ		 1249static inline void vpid_sync_vcpu_global(void)
1250{
1251 if (cpu_has_vmx_invvpid_global())
1252 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1253}
1254
1255static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1256{
1257 if (cpu_has_vmx_invvpid_single())
1760dd49 1258 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1259 else
1260 vpid_sync_vcpu_global();
1261}
1262
1439442c
SY		 1263static inline void ept_sync_global(void)
1264{
1265 if (cpu_has_vmx_invept_global())
1266 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1267}
1268
1269static inline void ept_sync_context(u64 eptp)
1270{
089d034e 1271 if (enable_ept) {
1439442c
SY		 1272 if (cpu_has_vmx_invept_context())
1273 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1274 else
1275 ept_sync_global();
1276 }
1277}
1278
96304217 1279static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1280{
5e520e62 1281 unsigned long value;
6aa8b732 1282
5e520e62
AK		 1283 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1284 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1285 return value;
1286}
1287
96304217 1288static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1289{
1290 return vmcs_readl(field);
1291}
1292
96304217 1293static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1294{
1295 return vmcs_readl(field);
1296}
1297
96304217 1298static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1299{
05b3e0c2 1300#ifdef CONFIG_X86_64
6aa8b732
AK		 1301 return vmcs_readl(field);
1302#else
1303 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1304#endif
1305}
1306
e52de1b8
AK		 1307static noinline void vmwrite_error(unsigned long field, unsigned long value)
1308{
1309 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1310 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1311 dump_stack();
1312}
1313
6aa8b732
AK		 1314static void vmcs_writel(unsigned long field, unsigned long value)
1315{
1316 u8 error;
1317
4ecac3fd 1318 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1319 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1320 if (unlikely(error))
1321 vmwrite_error(field, value);
6aa8b732
AK		 1322}
1323
1324static void vmcs_write16(unsigned long field, u16 value)
1325{
1326 vmcs_writel(field, value);
1327}
1328
1329static void vmcs_write32(unsigned long field, u32 value)
1330{
1331 vmcs_writel(field, value);
1332}
1333
1334static void vmcs_write64(unsigned long field, u64 value)
1335{
6aa8b732 1336 vmcs_writel(field, value);
7682f2d0 1337#ifndef CONFIG_X86_64
6aa8b732
AK		 1338 asm volatile ("");
1339 vmcs_writel(field+1, value >> 32);
1340#endif
1341}
1342
2ab455cc
AL		 1343static void vmcs_clear_bits(unsigned long field, u32 mask)
1344{
1345 vmcs_writel(field, vmcs_readl(field) & ~mask);
1346}
1347
1348static void vmcs_set_bits(unsigned long field, u32 mask)
1349{
1350 vmcs_writel(field, vmcs_readl(field) | mask);
1351}
1352
2961e876
GN		 1353static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1354{
1355 vmcs_write32(VM_ENTRY_CONTROLS, val);
1356 vmx->vm_entry_controls_shadow = val;
1357}
1358
1359static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1360{
1361 if (vmx->vm_entry_controls_shadow != val)
1362 vm_entry_controls_init(vmx, val);
1363}
1364
1365static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1366{
1367 return vmx->vm_entry_controls_shadow;
1368}
1369
1370
1371static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1372{
1373 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1374}
1375
1376static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1377{
1378 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1379}
1380
1381static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1382{
1383 vmcs_write32(VM_EXIT_CONTROLS, val);
1384 vmx->vm_exit_controls_shadow = val;
1385}
1386
1387static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1388{
1389 if (vmx->vm_exit_controls_shadow != val)
1390 vm_exit_controls_init(vmx, val);
1391}
1392
1393static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1394{
1395 return vmx->vm_exit_controls_shadow;
1396}
1397
1398
1399static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1400{
1401 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1402}
1403
1404static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1405{
1406 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1407}
1408
2fb92db1
AK		 1409static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1410{
1411 vmx->segment_cache.bitmask = 0;
1412}
1413
1414static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1415 unsigned field)
1416{
1417 bool ret;
1418 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1419
1420 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1421 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1422 vmx->segment_cache.bitmask = 0;
1423 }
1424 ret = vmx->segment_cache.bitmask & mask;
1425 vmx->segment_cache.bitmask |= mask;
1426 return ret;
1427}
1428
1429static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1430{
1431 u16 *p = &vmx->segment_cache.seg[seg].selector;
1432
1433 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1434 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1435 return *p;
1436}
1437
1438static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1439{
1440 ulong *p = &vmx->segment_cache.seg[seg].base;
1441
1442 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1443 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1444 return *p;
1445}
1446
1447static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1448{
1449 u32 *p = &vmx->segment_cache.seg[seg].limit;
1450
1451 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1452 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1453 return *p;
1454}
1455
1456static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1457{
1458 u32 *p = &vmx->segment_cache.seg[seg].ar;
1459
1460 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1461 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1462 return *p;
1463}
1464
abd3f2d6
AK		 1465static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1466{
1467 u32 eb;
1468
fd7373cc
JK		 1469 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1470 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1471 if ((vcpu->guest_debug &
1472 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1473 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1474 eb |= 1u << BP_VECTOR;
7ffd92c5 1475 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1476 eb = ~0;
089d034e 1477 if (enable_ept)
1439442c 1478 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1479 if (vcpu->fpu_active)
1480 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1481
1482 /* When we are running a nested L2 guest and L1 specified for it a
1483 * certain exception bitmap, we must trap the same exceptions and pass
1484 * them to L1. When running L2, we will only handle the exceptions
1485 * specified above if L1 did not want them.
1486 */
1487 if (is_guest_mode(vcpu))
1488 eb |= get_vmcs12(vcpu)->exception_bitmap;
1489
abd3f2d6
AK		 1490 vmcs_write32(EXCEPTION_BITMAP, eb);
1491}
1492
2961e876
GN		 1493static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1494 unsigned long entry, unsigned long exit)
8bf00a52 1495{
2961e876
GN		 1496 vm_entry_controls_clearbit(vmx, entry);
1497 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1498}
1499
61d2ef2c
AK		 1500static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1501{
1502 unsigned i;
1503 struct msr_autoload *m = &vmx->msr_autoload;
1504
8bf00a52
GN		 1505 switch (msr) {
1506 case MSR_EFER:
1507 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1508 clear_atomic_switch_msr_special(vmx,
1509 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1510 VM_EXIT_LOAD_IA32_EFER);
1511 return;
1512 }
1513 break;
1514 case MSR_CORE_PERF_GLOBAL_CTRL:
1515 if (cpu_has_load_perf_global_ctrl) {
2961e876 1516 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1517 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1518 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1519 return;
1520 }
1521 break;
110312c8
AK		 1522 }
1523
61d2ef2c
AK		 1524 for (i = 0; i < m->nr; ++i)
1525 if (m->guest[i].index == msr)
1526 break;
1527
1528 if (i == m->nr)
1529 return;
1530 --m->nr;
1531 m->guest[i] = m->guest[m->nr];
1532 m->host[i] = m->host[m->nr];
1533 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1534 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1535}
1536
2961e876
GN		 1537static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1538 unsigned long entry, unsigned long exit,
1539 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1540 u64 guest_val, u64 host_val)
8bf00a52
GN		 1541{
1542 vmcs_write64(guest_val_vmcs, guest_val);
1543 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1544 vm_entry_controls_setbit(vmx, entry);
1545 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1546}
1547
61d2ef2c
AK		 1548static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1549 u64 guest_val, u64 host_val)
1550{
1551 unsigned i;
1552 struct msr_autoload *m = &vmx->msr_autoload;
1553
8bf00a52
GN		 1554 switch (msr) {
1555 case MSR_EFER:
1556 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1557 add_atomic_switch_msr_special(vmx,
1558 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1559 VM_EXIT_LOAD_IA32_EFER,
1560 GUEST_IA32_EFER,
1561 HOST_IA32_EFER,
1562 guest_val, host_val);
1563 return;
1564 }
1565 break;
1566 case MSR_CORE_PERF_GLOBAL_CTRL:
1567 if (cpu_has_load_perf_global_ctrl) {
2961e876 1568 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1569 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1570 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1571 GUEST_IA32_PERF_GLOBAL_CTRL,
1572 HOST_IA32_PERF_GLOBAL_CTRL,
1573 guest_val, host_val);
1574 return;
1575 }
1576 break;
110312c8
AK		 1577 }
1578
61d2ef2c
AK		 1579 for (i = 0; i < m->nr; ++i)
1580 if (m->guest[i].index == msr)
1581 break;
1582
e7fc6f93 1583 if (i == NR_AUTOLOAD_MSRS) {
60266204 1584 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1585 "Can't add msr %x\n", msr);
1586 return;
1587 } else if (i == m->nr) {
61d2ef2c
AK		 1588 ++m->nr;
1589 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1590 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1591 }
1592
1593 m->guest[i].index = msr;
1594 m->guest[i].value = guest_val;
1595 m->host[i].index = msr;
1596 m->host[i].value = host_val;
1597}
1598
33ed6329
AK		 1599static void reload_tss(void)
1600{
33ed6329
AK		 1601 /*
1602 * VT restores TR but not its size. Useless.
1603 */
d359192f 1604 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1605 struct desc_struct *descs;
33ed6329 1606
d359192f 1607 descs = (void *)gdt->address;
33ed6329
AK		 1608 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1609 load_TR_desc();
33ed6329
AK		 1610}
1611
92c0d900 1612static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1613{
3a34a881 1614 u64 guest_efer;
51c6cf66
AK		 1615 u64 ignore_bits;
1616
f6801dff 1617 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1618
51c6cf66 1619 /*
0fa06071 1620 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1621 * outside long mode
1622 */
1623 ignore_bits = EFER_NX | EFER_SCE;
1624#ifdef CONFIG_X86_64
1625 ignore_bits |= EFER_LMA | EFER_LME;
1626 /* SCE is meaningful only in long mode on Intel */
1627 if (guest_efer & EFER_LMA)
1628 ignore_bits &= ~(u64)EFER_SCE;
1629#endif
51c6cf66
AK		 1630 guest_efer &= ~ignore_bits;
1631 guest_efer |= host_efer & ignore_bits;
26bb0981 1632 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1633 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1634
1635 clear_atomic_switch_msr(vmx, MSR_EFER);
1636 /* On ept, can't emulate nx, and must switch nx atomically */
1637 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1638 guest_efer = vmx->vcpu.arch.efer;
1639 if (!(guest_efer & EFER_LMA))
1640 guest_efer &= ~EFER_LME;
1641 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1642 return false;
1643 }
1644
26bb0981 1645 return true;
51c6cf66
AK		 1646}
1647
2d49ec72
GN		 1648static unsigned long segment_base(u16 selector)
1649{
d359192f 1650 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1651 struct desc_struct *d;
1652 unsigned long table_base;
1653 unsigned long v;
1654
1655 if (!(selector & ~3))
1656 return 0;
1657
d359192f 1658 table_base = gdt->address;
2d49ec72
GN		 1659
1660 if (selector & 4) { /* from ldt */
1661 u16 ldt_selector = kvm_read_ldt();
1662
1663 if (!(ldt_selector & ~3))
1664 return 0;
1665
1666 table_base = segment_base(ldt_selector);
1667 }
1668 d = (struct desc_struct *)(table_base + (selector & ~7));
1669 v = get_desc_base(d);
1670#ifdef CONFIG_X86_64
1671 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1672 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1673#endif
1674 return v;
1675}
1676
1677static inline unsigned long kvm_read_tr_base(void)
1678{
1679 u16 tr;
1680 asm("str %0" : "=g"(tr));
1681 return segment_base(tr);
1682}
1683
04d2cc77 1684static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1685{
04d2cc77 1686 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1687 int i;
04d2cc77 1688
a2fa3e9f 1689 if (vmx->host_state.loaded)
33ed6329
AK		 1690 return;
1691
a2fa3e9f 1692 vmx->host_state.loaded = 1;
33ed6329
AK		 1693 /*
1694 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1695 * allow segment selectors with cpl > 0 or ti == 1.
1696 */
d6e88aec 1697 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1698 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1699 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1700 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1701 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1702 vmx->host_state.fs_reload_needed = 0;
1703 } else {
33ed6329 1704 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1705 vmx->host_state.fs_reload_needed = 1;
33ed6329 1706 }
9581d442 1707 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1708 if (!(vmx->host_state.gs_sel & 7))
1709 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1710 else {
1711 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1712 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1713 }
1714
b2da15ac
AK		 1715#ifdef CONFIG_X86_64
1716 savesegment(ds, vmx->host_state.ds_sel);
1717 savesegment(es, vmx->host_state.es_sel);
1718#endif
1719
33ed6329
AK		 1720#ifdef CONFIG_X86_64
1721 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1722 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1723#else
a2fa3e9f
GH		 1724 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1725 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1726#endif
707c0874
AK		 1727
1728#ifdef CONFIG_X86_64
c8770e7b
AK		 1729 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1730 if (is_long_mode(&vmx->vcpu))
44ea2b17 1731 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1732#endif
da8999d3
LJ		 1733 if (boot_cpu_has(X86_FEATURE_MPX))
1734 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1735 for (i = 0; i < vmx->save_nmsrs; ++i)
1736 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1737 vmx->guest_msrs[i].data,
1738 vmx->guest_msrs[i].mask);
33ed6329
AK		 1739}
1740
a9b21b62 1741static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1742{
a2fa3e9f 1743 if (!vmx->host_state.loaded)
33ed6329
AK		 1744 return;
1745
e1beb1d3 1746 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1747 vmx->host_state.loaded = 0;
c8770e7b
AK		 1748#ifdef CONFIG_X86_64
1749 if (is_long_mode(&vmx->vcpu))
1750 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1751#endif
152d3f2f 1752 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1753 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1754#ifdef CONFIG_X86_64
9581d442 1755 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1756#else
1757 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1758#endif
33ed6329 1759 }
0a77fe4c
AK		 1760 if (vmx->host_state.fs_reload_needed)
1761 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1762#ifdef CONFIG_X86_64
1763 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1764 loadsegment(ds, vmx->host_state.ds_sel);
1765 loadsegment(es, vmx->host_state.es_sel);
1766 }
b2da15ac 1767#endif
152d3f2f 1768 reload_tss();
44ea2b17 1769#ifdef CONFIG_X86_64
c8770e7b 1770 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1771#endif
da8999d3
LJ		 1772 if (vmx->host_state.msr_host_bndcfgs)
1773 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1774 /*
1775 * If the FPU is not active (through the host task or
1776 * the guest vcpu), then restore the cr0.TS bit.
1777 */
1778 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1779 stts();
3444d7da 1780 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1781}
1782
a9b21b62
AK		 1783static void vmx_load_host_state(struct vcpu_vmx *vmx)
1784{
1785 preempt_disable();
1786 __vmx_load_host_state(vmx);
1787 preempt_enable();
1788}
1789
6aa8b732
AK		 1790/*
1791 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1792 * vcpu mutex is already taken.
1793 */
15ad7146 1794static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1795{
a2fa3e9f 1796 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1797 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1798
4610c9cc
DX		 1799 if (!vmm_exclusive)
1800 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1801 else if (vmx->loaded_vmcs->cpu != cpu)
1802 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1803
d462b819
NHE		 1804 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1805 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1806 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1807 }
1808
d462b819 1809 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1810 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1811 unsigned long sysenter_esp;
1812
a8eeb04a 1813 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1814 local_irq_disable();
8f536b76 1815 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1816
1817 /*
1818 * Read loaded_vmcs->cpu should be before fetching
1819 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1820 * See the comments in __loaded_vmcs_clear().
1821 */
1822 smp_rmb();
1823
d462b819
NHE		 1824 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1825 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1826 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1827 local_irq_enable();
1828
6aa8b732
AK		 1829 /*
1830 * Linux uses per-cpu TSS and GDT, so set these when switching
1831 * processors.
1832 */
d6e88aec 1833 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1834 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1835
1836 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1837 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1838 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1839 }
6aa8b732
AK		 1840}
1841
1842static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1843{
a9b21b62 1844 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1845 if (!vmm_exclusive) {
d462b819
NHE		 1846 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1847 vcpu->cpu = -1;
4610c9cc
DX		 1848 kvm_cpu_vmxoff();
1849 }
6aa8b732
AK		 1850}
1851
5fd86fcf
AK		 1852static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1853{
81231c69
AK		 1854 ulong cr0;
1855
5fd86fcf
AK		 1856 if (vcpu->fpu_active)
1857 return;
1858 vcpu->fpu_active = 1;
81231c69
AK		 1859 cr0 = vmcs_readl(GUEST_CR0);
1860 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1861 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1862 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1863 update_exception_bitmap(vcpu);
edcafe3c 1864 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1865 if (is_guest_mode(vcpu))
1866 vcpu->arch.cr0_guest_owned_bits &=
1867 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1868 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1869}
1870
edcafe3c
AK		 1871static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1872
fe3ef05c
NHE		 1873/*
1874 * Return the cr0 value that a nested guest would read. This is a combination
1875 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1876 * its hypervisor (cr0_read_shadow).
1877 */
1878static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1879{
1880 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1881 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1882}
1883static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1884{
1885 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1886 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1887}
1888
5fd86fcf
AK		 1889static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1890{
36cf24e0
NHE		 1891 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1892 * set this *before* calling this function.
1893 */
edcafe3c 1894 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1895 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1896 update_exception_bitmap(vcpu);
edcafe3c
AK		 1897 vcpu->arch.cr0_guest_owned_bits = 0;
1898 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1899 if (is_guest_mode(vcpu)) {
1900 /*
1901 * L1's specified read shadow might not contain the TS bit,
1902 * so now that we turned on shadowing of this bit, we need to
1903 * set this bit of the shadow. Like in nested_vmx_run we need
1904 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1905 * up-to-date here because we just decached cr0.TS (and we'll
1906 * only update vmcs12->guest_cr0 on nested exit).
1907 */
1908 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1909 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1910 (vcpu->arch.cr0 & X86_CR0_TS);
1911 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1912 } else
1913 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1914}
1915
6aa8b732
AK		 1916static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1917{
78ac8b47 1918 unsigned long rflags, save_rflags;
345dcaa8 1919
6de12732
AK		 1920 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1921 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1922 rflags = vmcs_readl(GUEST_RFLAGS);
1923 if (to_vmx(vcpu)->rmode.vm86_active) {
1924 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1925 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1926 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1927 }
1928 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1929 }
6de12732 1930 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1931}
1932
1933static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1934{
6de12732
AK		 1935 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1936 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1937 if (to_vmx(vcpu)->rmode.vm86_active) {
1938 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1939 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1940 }
6aa8b732
AK		 1941 vmcs_writel(GUEST_RFLAGS, rflags);
1942}
1943
2809f5d2
GC		 1944static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1945{
1946 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1947 int ret = 0;
1948
1949 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1950 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1951 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1952 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1953
1954 return ret & mask;
1955}
1956
1957static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1958{
1959 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1960 u32 interruptibility = interruptibility_old;
1961
1962 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1963
48005f64 1964 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1965 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1966 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1967 interruptibility |= GUEST_INTR_STATE_STI;
1968
1969 if ((interruptibility != interruptibility_old))
1970 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1971}
1972
6aa8b732
AK		 1973static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1974{
1975 unsigned long rip;
6aa8b732 1976
5fdbf976 1977 rip = kvm_rip_read(vcpu);
6aa8b732 1978 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1979 kvm_rip_write(vcpu, rip);
6aa8b732 1980
2809f5d2
GC		 1981 /* skipping an emulated instruction also counts */
1982 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1983}
1984
0b6ac343
NHE		 1985/*
1986 * KVM wants to inject page-faults which it got to the guest. This function
1987 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1988 */
e011c663 1989static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1990{
1991 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1992
e011c663 1993 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1994 return 0;
1995
533558bc
JK		 1996 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1997 vmcs_read32(VM_EXIT_INTR_INFO),
1998 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1999 return 1;
2000}
2001
298101da 2002static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2003 bool has_error_code, u32 error_code,
2004 bool reinject)
298101da 2005{
77ab6db0 2006 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2007 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2008
e011c663
GN		 2009 if (!reinject && is_guest_mode(vcpu) &&
2010 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2011 return;
2012
8ab2d2e2 2013 if (has_error_code) {
77ab6db0 2014 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2015 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2016 }
77ab6db0 2017
7ffd92c5 2018 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2019 int inc_eip = 0;
2020 if (kvm_exception_is_soft(nr))
2021 inc_eip = vcpu->arch.event_exit_inst_len;
2022 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2023 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2024 return;
2025 }
2026
66fd3f7f
GN		 2027 if (kvm_exception_is_soft(nr)) {
2028 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2029 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2030 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2031 } else
2032 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2033
2034 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2035}
2036
4e47c7a6
SY		 2037static bool vmx_rdtscp_supported(void)
2038{
2039 return cpu_has_vmx_rdtscp();
2040}
2041
ad756a16
MJ		 2042static bool vmx_invpcid_supported(void)
2043{
2044 return cpu_has_vmx_invpcid() && enable_ept;
2045}
2046
a75beee6
ED		 2047/*
2048 * Swap MSR entry in host/guest MSR entry array.
2049 */
8b9cf98c 2050static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2051{
26bb0981 2052 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2053
2054 tmp = vmx->guest_msrs[to];
2055 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2056 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2057}
2058
8d14695f
YZ		 2059static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2060{
2061 unsigned long *msr_bitmap;
2062
2063 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2064 if (is_long_mode(vcpu))
2065 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2066 else
2067 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2068 } else {
2069 if (is_long_mode(vcpu))
2070 msr_bitmap = vmx_msr_bitmap_longmode;
2071 else
2072 msr_bitmap = vmx_msr_bitmap_legacy;
2073 }
2074
2075 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2076}
2077
e38aea3e
AK		 2078/*
2079 * Set up the vmcs to automatically save and restore system
2080 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2081 * mode, as fiddling with msrs is very expensive.
2082 */
8b9cf98c 2083static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2084{
26bb0981 2085 int save_nmsrs, index;
e38aea3e 2086
a75beee6
ED		 2087 save_nmsrs = 0;
2088#ifdef CONFIG_X86_64
8b9cf98c 2089 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2090 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2091 if (index >= 0)
8b9cf98c
RR		 2092 move_msr_up(vmx, index, save_nmsrs++);
2093 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2094 if (index >= 0)
8b9cf98c
RR		 2095 move_msr_up(vmx, index, save_nmsrs++);
2096 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2097 if (index >= 0)
8b9cf98c 2098 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2099 index = __find_msr_index(vmx, MSR_TSC_AUX);
2100 if (index >= 0 && vmx->rdtscp_enabled)
2101 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2102 /*
8c06585d 2103 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2104 * if efer.sce is enabled.
2105 */
8c06585d 2106 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2107 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2108 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2109 }
2110#endif
92c0d900
AK		 2111 index = __find_msr_index(vmx, MSR_EFER);
2112 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2113 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2114
26bb0981 2115 vmx->save_nmsrs = save_nmsrs;
5897297b 2116
8d14695f
YZ		 2117 if (cpu_has_vmx_msr_bitmap())
2118 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2119}
2120
6aa8b732
AK		 2121/*
2122 * reads and returns guest's timestamp counter "register"
2123 * guest_tsc = host_tsc + tsc_offset -- 21.3
2124 */
2125static u64 guest_read_tsc(void)
2126{
2127 u64 host_tsc, tsc_offset;
2128
2129 rdtscll(host_tsc);
2130 tsc_offset = vmcs_read64(TSC_OFFSET);
2131 return host_tsc + tsc_offset;
2132}
2133
d5c1785d
NHE		 2134/*
2135 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2136 * counter, even if a nested guest (L2) is currently running.
2137 */
886b470c 2138u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2139{
886b470c 2140 u64 tsc_offset;
d5c1785d 2141
d5c1785d
NHE		 2142 tsc_offset = is_guest_mode(vcpu) ?
2143 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2144 vmcs_read64(TSC_OFFSET);
2145 return host_tsc + tsc_offset;
2146}
2147
4051b188 2148/*
cc578287
ZA		 2149 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2150 * software catchup for faster rates on slower CPUs.
4051b188 2151 */
cc578287 2152static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2153{
cc578287
ZA		 2154 if (!scale)
2155 return;
2156
2157 if (user_tsc_khz > tsc_khz) {
2158 vcpu->arch.tsc_catchup = 1;
2159 vcpu->arch.tsc_always_catchup = 1;
2160 } else
2161 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2162}
2163
ba904635
WA		 2164static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2165{
2166 return vmcs_read64(TSC_OFFSET);
2167}
2168
6aa8b732 2169/*
99e3e30a 2170 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2171 */
99e3e30a 2172static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2173{
27fc51b2 2174 if (is_guest_mode(vcpu)) {
7991825b 2175 /*
27fc51b2
NHE		 2176 * We're here if L1 chose not to trap WRMSR to TSC. According
2177 * to the spec, this should set L1's TSC; The offset that L1
2178 * set for L2 remains unchanged, and still needs to be added
2179 * to the newly set TSC to get L2's TSC.
7991825b 2180 */
27fc51b2
NHE		 2181 struct vmcs12 *vmcs12;
2182 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2183 /* recalculate vmcs02.TSC_OFFSET: */
2184 vmcs12 = get_vmcs12(vcpu);
2185 vmcs_write64(TSC_OFFSET, offset +
2186 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2187 vmcs12->tsc_offset : 0));
2188 } else {
489223ed
YY		 2189 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2190 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2191 vmcs_write64(TSC_OFFSET, offset);
2192 }
6aa8b732
AK		 2193}
2194
f1e2b260 2195static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2196{
2197 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2198
e48672fa 2199 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2200 if (is_guest_mode(vcpu)) {
2201 /* Even when running L2, the adjustment needs to apply to L1 */
2202 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2203 } else
2204 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2205 offset + adjustment);
e48672fa
ZA		 2206}
2207
857e4099
JR		 2208static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2209{
2210 return target_tsc - native_read_tsc();
2211}
2212
801d3424
NHE		 2213static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2214{
2215 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2216 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2217}
2218
2219/*
2220 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2221 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2222 * all guests if the "nested" module option is off, and can also be disabled
2223 * for a single guest by disabling its VMX cpuid bit.
2224 */
2225static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2226{
2227 return nested && guest_cpuid_has_vmx(vcpu);
2228}
2229
b87a51ae
NHE		 2230/*
2231 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2232 * returned for the various VMX controls MSRs when nested VMX is enabled.
2233 * The same values should also be used to verify that vmcs12 control fields are
2234 * valid during nested entry from L1 to L2.
2235 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2236 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2237 * bit in the high half is on if the corresponding bit in the control field
2238 * may be on. See also vmx_control_verify().
2239 * TODO: allow these variables to be modified (downgraded) by module options
2240 * or other means.
2241 */
2242static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2243static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2244static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2245static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2246static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2247static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2248static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2249static __init void nested_vmx_setup_ctls_msrs(void)
2250{
2251 /*
2252 * Note that as a general rule, the high half of the MSRs (bits in
2253 * the control fields which may be 1) should be initialized by the
2254 * intersection of the underlying hardware's MSR (i.e., features which
2255 * can be supported) and the list of features we want to expose -
2256 * because they are known to be properly supported in our code.
2257 * Also, usually, the low half of the MSRs (bits which must be 1) can
2258 * be set to 0, meaning that L1 may turn off any of these bits. The
2259 * reason is that if one of these bits is necessary, it will appear
2260 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2261 * fields of vmcs01 and vmcs02, will turn these bits off - and
2262 * nested_vmx_exit_handled() will not pass related exits to L1.
2263 * These rules have exceptions below.
2264 */
2265
2266 /* pin-based controls */
eabeaacc
JK		 2267 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2268 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2269 /*
2270 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2271 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2272 */
eabeaacc
JK		 2273 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2274 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2275 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2276 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2277 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2278
33fb20c3
JK		 2279 /*
2280 * Exit controls
2281 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2282 * 17 must be 1.
2283 */
c0dfee58
ACL		 2284 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2285 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2286 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2287
c0dfee58 2288 nested_vmx_exit_ctls_high &=
b87a51ae 2289#ifdef CONFIG_X86_64
c0dfee58 2290 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2291#endif
f4124500
JK		 2292 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2293 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2294 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2295 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2296
36be0b9d
PB		 2297 if (vmx_mpx_supported())
2298 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae
NHE		 2299
2300 /* entry controls */
2301 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2302 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2303 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2304 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2305 nested_vmx_entry_ctls_high &=
57435349
JK		 2306#ifdef CONFIG_X86_64
2307 VM_ENTRY_IA32E_MODE |
2308#endif
2309 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2310 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2311 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2312 if (vmx_mpx_supported())
2313 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2314
b87a51ae
NHE		 2315 /* cpu-based controls */
2316 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2317 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2318 nested_vmx_procbased_ctls_low = 0;
2319 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2320 CPU_BASED_VIRTUAL_INTR_PENDING |
2321 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2322 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2323 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2324 CPU_BASED_CR3_STORE_EXITING |
2325#ifdef CONFIG_X86_64
2326 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2327#endif
2328 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2329 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2330 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2331 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2332 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2333 /*
2334 * We can allow some features even when not supported by the
2335 * hardware. For example, L1 can specify an MSR bitmap - and we
2336 * can use it to avoid exits to L1 - even when L0 runs L2
2337 * without MSR bitmaps.
2338 */
2339 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2340
2341 /* secondary cpu-based controls */
2342 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2343 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2344 nested_vmx_secondary_ctls_low = 0;
2345 nested_vmx_secondary_ctls_high &=
d6851fbe 2346 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2347 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2348 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2349
afa61f75
NHE		 2350 if (enable_ept) {
2351 /* nested EPT: emulate EPT also to L1 */
2352 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2353 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2354 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2355 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2356 nested_vmx_ept_caps &= vmx_capability.ept;
2357 /*
4b855078
BD		 2358 * For nested guests, we don't do anything specific
2359 * for single context invalidation. Hence, only advertise
2360 * support for global context invalidation.
afa61f75 2361 */
4b855078 2362 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2363 } else
2364 nested_vmx_ept_caps = 0;
2365
c18911a2
JK		 2366 /* miscellaneous data */
2367 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2368 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2369 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2370 VMX_MISC_ACTIVITY_HLT;
c18911a2 2371 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2372}
2373
2374static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2375{
2376 /*
2377 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2378 */
2379 return ((control & high) | low) == control;
2380}
2381
2382static inline u64 vmx_control_msr(u32 low, u32 high)
2383{
2384 return low | ((u64)high << 32);
2385}
2386
cae50139 2387/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2388static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2389{
b87a51ae 2390 switch (msr_index) {
b87a51ae
NHE		 2391 case MSR_IA32_VMX_BASIC:
2392 /*
2393 * This MSR reports some information about VMX support. We
2394 * should return information about the VMX we emulate for the
2395 * guest, and the VMCS structure we give it - not about the
2396 * VMX support of the underlying hardware.
2397 */
2398 *pdata = VMCS12_REVISION |
2399 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2400 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2401 break;
2402 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2403 case MSR_IA32_VMX_PINBASED_CTLS:
2404 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2405 nested_vmx_pinbased_ctls_high);
2406 break;
2407 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2408 case MSR_IA32_VMX_PROCBASED_CTLS:
2409 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2410 nested_vmx_procbased_ctls_high);
2411 break;
2412 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2413 case MSR_IA32_VMX_EXIT_CTLS:
2414 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2415 nested_vmx_exit_ctls_high);
2416 break;
2417 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2418 case MSR_IA32_VMX_ENTRY_CTLS:
2419 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2420 nested_vmx_entry_ctls_high);
2421 break;
2422 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2423 *pdata = vmx_control_msr(nested_vmx_misc_low,
2424 nested_vmx_misc_high);
b87a51ae
NHE		 2425 break;
2426 /*
2427 * These MSRs specify bits which the guest must keep fixed (on or off)
2428 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2429 * We picked the standard core2 setting.
2430 */
2431#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2432#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2433 case MSR_IA32_VMX_CR0_FIXED0:
2434 *pdata = VMXON_CR0_ALWAYSON;
2435 break;
2436 case MSR_IA32_VMX_CR0_FIXED1:
2437 *pdata = -1ULL;
2438 break;
2439 case MSR_IA32_VMX_CR4_FIXED0:
2440 *pdata = VMXON_CR4_ALWAYSON;
2441 break;
2442 case MSR_IA32_VMX_CR4_FIXED1:
2443 *pdata = -1ULL;
2444 break;
2445 case MSR_IA32_VMX_VMCS_ENUM:
2446 *pdata = 0x1f;
2447 break;
2448 case MSR_IA32_VMX_PROCBASED_CTLS2:
2449 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2450 nested_vmx_secondary_ctls_high);
2451 break;
2452 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2453 /* Currently, no nested vpid support */
2454 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2455 break;
2456 default:
b87a51ae 2457 return 1;
b3897a49
NHE		 2458 }
2459
b87a51ae
NHE		 2460 return 0;
2461}
2462
6aa8b732
AK		 2463/*
2464 * Reads an msr value (of 'msr_index') into 'pdata'.
2465 * Returns 0 on success, non-0 otherwise.
2466 * Assumes vcpu_load() was already called.
2467 */
2468static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2469{
2470 u64 data;
26bb0981 2471 struct shared_msr_entry *msr;
6aa8b732
AK		 2472
2473 if (!pdata) {
2474 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2475 return -EINVAL;
2476 }
2477
2478 switch (msr_index) {
05b3e0c2 2479#ifdef CONFIG_X86_64
6aa8b732
AK		 2480 case MSR_FS_BASE:
2481 data = vmcs_readl(GUEST_FS_BASE);
2482 break;
2483 case MSR_GS_BASE:
2484 data = vmcs_readl(GUEST_GS_BASE);
2485 break;
44ea2b17
AK		 2486 case MSR_KERNEL_GS_BASE:
2487 vmx_load_host_state(to_vmx(vcpu));
2488 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2489 break;
26bb0981 2490#endif
6aa8b732 2491 case MSR_EFER:
3bab1f5d 2492 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2493 case MSR_IA32_TSC:
6aa8b732
AK		 2494 data = guest_read_tsc();
2495 break;
2496 case MSR_IA32_SYSENTER_CS:
2497 data = vmcs_read32(GUEST_SYSENTER_CS);
2498 break;
2499 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2500 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2501 break;
2502 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2503 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2504 break;
0dd376e7 2505 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2506 if (!vmx_mpx_supported())
2507 return 1;
0dd376e7
LJ		 2508 data = vmcs_read64(GUEST_BNDCFGS);
2509 break;
cae50139
JK		 2510 case MSR_IA32_FEATURE_CONTROL:
2511 if (!nested_vmx_allowed(vcpu))
2512 return 1;
2513 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2514 break;
2515 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2516 if (!nested_vmx_allowed(vcpu))
2517 return 1;
2518 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2519 case MSR_TSC_AUX:
2520 if (!to_vmx(vcpu)->rdtscp_enabled)
2521 return 1;
2522 /* Otherwise falls through */
6aa8b732 2523 default:
8b9cf98c 2524 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2525 if (msr) {
2526 data = msr->data;
2527 break;
6aa8b732 2528 }
3bab1f5d 2529 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2530 }
2531
2532 *pdata = data;
2533 return 0;
2534}
2535
cae50139
JK		 2536static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2537
6aa8b732
AK		 2538/*
2539 * Writes msr value into into the appropriate "register".
2540 * Returns 0 on success, non-0 otherwise.
2541 * Assumes vcpu_load() was already called.
2542 */
8fe8ab46 2543static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2544{
a2fa3e9f 2545 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2546 struct shared_msr_entry *msr;
2cc51560 2547 int ret = 0;
8fe8ab46
WA		 2548 u32 msr_index = msr_info->index;
2549 u64 data = msr_info->data;
2cc51560 2550
6aa8b732 2551 switch (msr_index) {
3bab1f5d 2552 case MSR_EFER:
8fe8ab46 2553 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2554 break;
16175a79 2555#ifdef CONFIG_X86_64
6aa8b732 2556 case MSR_FS_BASE:
2fb92db1 2557 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2558 vmcs_writel(GUEST_FS_BASE, data);
2559 break;
2560 case MSR_GS_BASE:
2fb92db1 2561 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2562 vmcs_writel(GUEST_GS_BASE, data);
2563 break;
44ea2b17
AK		 2564 case MSR_KERNEL_GS_BASE:
2565 vmx_load_host_state(vmx);
2566 vmx->msr_guest_kernel_gs_base = data;
2567 break;
6aa8b732
AK		 2568#endif
2569 case MSR_IA32_SYSENTER_CS:
2570 vmcs_write32(GUEST_SYSENTER_CS, data);
2571 break;
2572 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2573 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2574 break;
2575 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2576 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2577 break;
0dd376e7 2578 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2579 if (!vmx_mpx_supported())
2580 return 1;
0dd376e7
LJ		 2581 vmcs_write64(GUEST_BNDCFGS, data);
2582 break;
af24a4e4 2583 case MSR_IA32_TSC:
8fe8ab46 2584 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2585 break;
468d472f
SY		 2586 case MSR_IA32_CR_PAT:
2587 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2588 vmcs_write64(GUEST_IA32_PAT, data);
2589 vcpu->arch.pat = data;
2590 break;
2591 }
8fe8ab46 2592 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2593 break;
ba904635
WA		 2594 case MSR_IA32_TSC_ADJUST:
2595 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2596 break;
cae50139
JK		 2597 case MSR_IA32_FEATURE_CONTROL:
2598 if (!nested_vmx_allowed(vcpu) ||
2599 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2600 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2601 return 1;
2602 vmx->nested.msr_ia32_feature_control = data;
2603 if (msr_info->host_initiated && data == 0)
2604 vmx_leave_nested(vcpu);
2605 break;
2606 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2607 return 1; /* they are read-only */
4e47c7a6
SY		 2608 case MSR_TSC_AUX:
2609 if (!vmx->rdtscp_enabled)
2610 return 1;
2611 /* Check reserved bit, higher 32 bits should be zero */
2612 if ((data >> 32) != 0)
2613 return 1;
2614 /* Otherwise falls through */
6aa8b732 2615 default:
8b9cf98c 2616 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2617 if (msr) {
2618 msr->data = data;
2225fd56
AK		 2619 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2620 preempt_disable();
9ee73970
AK		 2621 kvm_set_shared_msr(msr->index, msr->data,
2622 msr->mask);
2225fd56
AK		 2623 preempt_enable();
2624 }
3bab1f5d 2625 break;
6aa8b732 2626 }
8fe8ab46 2627 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2628 }
2629
2cc51560 2630 return ret;
6aa8b732
AK		 2631}
2632
5fdbf976 2633static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2634{
5fdbf976
MT		 2635 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2636 switch (reg) {
2637 case VCPU_REGS_RSP:
2638 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2639 break;
2640 case VCPU_REGS_RIP:
2641 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2642 break;
6de4f3ad
AK		 2643 case VCPU_EXREG_PDPTR:
2644 if (enable_ept)
2645 ept_save_pdptrs(vcpu);
2646 break;
5fdbf976
MT		 2647 default:
2648 break;
2649 }
6aa8b732
AK		 2650}
2651
6aa8b732
AK		 2652static __init int cpu_has_kvm_support(void)
2653{
6210e37b 2654 return cpu_has_vmx();
6aa8b732
AK		 2655}
2656
2657static __init int vmx_disabled_by_bios(void)
2658{
2659 u64 msr;
2660
2661 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2662 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2663 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2664 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2665 && tboot_enabled())
2666 return 1;
23f3e991 2667 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2668 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2669 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2670 && !tboot_enabled()) {
2671 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2672 "activate TXT before enabling KVM\n");
cafd6659 2673 return 1;
f9335afe 2674 }
23f3e991
JC		 2675 /* launched w/o TXT and VMX disabled */
2676 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2677 && !tboot_enabled())
2678 return 1;
cafd6659
SW		 2679 }
2680
2681 return 0;
6aa8b732
AK		 2682}
2683
7725b894
DX		 2684static void kvm_cpu_vmxon(u64 addr)
2685{
2686 asm volatile (ASM_VMX_VMXON_RAX
2687 : : "a"(&addr), "m"(addr)
2688 : "memory", "cc");
2689}
2690
10474ae8 2691static int hardware_enable(void *garbage)
6aa8b732
AK		 2692{
2693 int cpu = raw_smp_processor_id();
2694 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2695 u64 old, test_bits;
6aa8b732 2696
10474ae8
AG		 2697 if (read_cr4() & X86_CR4_VMXE)
2698 return -EBUSY;
2699
d462b819 2700 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2701
2702 /*
2703 * Now we can enable the vmclear operation in kdump
2704 * since the loaded_vmcss_on_cpu list on this cpu
2705 * has been initialized.
2706 *
2707 * Though the cpu is not in VMX operation now, there
2708 * is no problem to enable the vmclear operation
2709 * for the loaded_vmcss_on_cpu list is empty!
2710 */
2711 crash_enable_local_vmclear(cpu);
2712
6aa8b732 2713 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2714
2715 test_bits = FEATURE_CONTROL_LOCKED;
2716 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2717 if (tboot_enabled())
2718 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2719
2720 if ((old & test_bits) != test_bits) {
6aa8b732 2721 /* enable and lock */
cafd6659
SW		 2722 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2723 }
66aee91a 2724 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2725
4610c9cc
DX		 2726 if (vmm_exclusive) {
2727 kvm_cpu_vmxon(phys_addr);
2728 ept_sync_global();
2729 }
10474ae8 2730
357d1226 2731 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2732
10474ae8 2733 return 0;
6aa8b732
AK		 2734}
2735
d462b819 2736static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2737{
2738 int cpu = raw_smp_processor_id();
d462b819 2739 struct loaded_vmcs *v, *n;
543e4243 2740
d462b819
NHE		 2741 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2742 loaded_vmcss_on_cpu_link)
2743 __loaded_vmcs_clear(v);
543e4243
AK		 2744}
2745
710ff4a8
EH		 2746
2747/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2748 * tricks.
2749 */
2750static void kvm_cpu_vmxoff(void)
6aa8b732 2751{
4ecac3fd 2752 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2753}
2754
710ff4a8
EH		 2755static void hardware_disable(void *garbage)
2756{
4610c9cc 2757 if (vmm_exclusive) {
d462b819 2758 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2759 kvm_cpu_vmxoff();
2760 }
7725b894 2761 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2762}
2763
1c3d14fe 2764static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2765 u32 msr, u32 *result)
1c3d14fe
YS		 2766{
2767 u32 vmx_msr_low, vmx_msr_high;
2768 u32 ctl = ctl_min | ctl_opt;
2769
2770 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2771
2772 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2773 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2774
2775 /* Ensure minimum (required) set of control bits are supported. */
2776 if (ctl_min & ~ctl)
002c7f7c 2777 return -EIO;
1c3d14fe
YS		 2778
2779 *result = ctl;
2780 return 0;
2781}
2782
110312c8
AK		 2783static __init bool allow_1_setting(u32 msr, u32 ctl)
2784{
2785 u32 vmx_msr_low, vmx_msr_high;
2786
2787 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2788 return vmx_msr_high & ctl;
2789}
2790
002c7f7c 2791static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2792{
2793 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2794 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2795 u32 _pin_based_exec_control = 0;
2796 u32 _cpu_based_exec_control = 0;
f78e0e2e 2797 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2798 u32 _vmexit_control = 0;
2799 u32 _vmentry_control = 0;
2800
10166744 2801 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2802#ifdef CONFIG_X86_64
2803 CPU_BASED_CR8_LOAD_EXITING |
2804 CPU_BASED_CR8_STORE_EXITING |
2805#endif
d56f546d
SY		 2806 CPU_BASED_CR3_LOAD_EXITING |
2807 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2808 CPU_BASED_USE_IO_BITMAPS |
2809 CPU_BASED_MOV_DR_EXITING |
a7052897 2810 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2811 CPU_BASED_MWAIT_EXITING |
2812 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2813 CPU_BASED_INVLPG_EXITING |
2814 CPU_BASED_RDPMC_EXITING;
443381a8 2815
f78e0e2e 2816 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2817 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2818 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2819 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2820 &_cpu_based_exec_control) < 0)
002c7f7c 2821 return -EIO;
6e5d865c
YS		 2822#ifdef CONFIG_X86_64
2823 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2824 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2825 ~CPU_BASED_CR8_STORE_EXITING;
2826#endif
f78e0e2e 2827 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2828 min2 = 0;
2829 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2830 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2831 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2832 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2833 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2834 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2835 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2836 SECONDARY_EXEC_RDTSCP |
83d4c286 2837 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2838 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2839 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2840 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2841 if (adjust_vmx_controls(min2, opt2,
2842 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2843 &_cpu_based_2nd_exec_control) < 0)
2844 return -EIO;
2845 }
2846#ifndef CONFIG_X86_64
2847 if (!(_cpu_based_2nd_exec_control &
2848 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2849 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2850#endif
83d4c286
YZ		 2851
2852 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2853 _cpu_based_2nd_exec_control &= ~(
8d14695f 2854 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2855 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2856 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2857
d56f546d 2858 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2859 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2860 enabled */
5fff7d27
GN		 2861 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2862 CPU_BASED_CR3_STORE_EXITING |
2863 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2864 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2865 vmx_capability.ept, vmx_capability.vpid);
2866 }
1c3d14fe 2867
81908bf4 2868 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2869#ifdef CONFIG_X86_64
2870 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2871#endif
a547c6db 2872 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2873 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2874 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2875 &_vmexit_control) < 0)
002c7f7c 2876 return -EIO;
1c3d14fe 2877
01e439be
YZ		 2878 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2879 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2880 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2881 &_pin_based_exec_control) < 0)
2882 return -EIO;
2883
2884 if (!(_cpu_based_2nd_exec_control &
2885 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2886 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2887 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2888
c845f9c6 2889 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2890 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2891 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2892 &_vmentry_control) < 0)
002c7f7c 2893 return -EIO;
6aa8b732 2894
c68876fd 2895 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2896
2897 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2898 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2899 return -EIO;
1c3d14fe
YS		 2900
2901#ifdef CONFIG_X86_64
2902 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2903 if (vmx_msr_high & (1u<<16))
002c7f7c 2904 return -EIO;
1c3d14fe
YS		 2905#endif
2906
2907 /* Require Write-Back (WB) memory type for VMCS accesses. */
2908 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2909 return -EIO;
1c3d14fe 2910
002c7f7c
YS		 2911 vmcs_conf->size = vmx_msr_high & 0x1fff;
2912 vmcs_conf->order = get_order(vmcs_config.size);
2913 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2914
002c7f7c
YS		 2915 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2916 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2917 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2918 vmcs_conf->vmexit_ctrl = _vmexit_control;
2919 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2920
110312c8
AK		 2921 cpu_has_load_ia32_efer =
2922 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2923 VM_ENTRY_LOAD_IA32_EFER)
2924 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2925 VM_EXIT_LOAD_IA32_EFER);
2926
8bf00a52
GN		 2927 cpu_has_load_perf_global_ctrl =
2928 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2929 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2930 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2931 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2932
2933 /*
2934 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2935 * but due to arrata below it can't be used. Workaround is to use
2936 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2937 *
2938 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2939 *
2940 * AAK155 (model 26)
2941 * AAP115 (model 30)
2942 * AAT100 (model 37)
2943 * BC86,AAY89,BD102 (model 44)
2944 * BA97 (model 46)
2945 *
2946 */
2947 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2948 switch (boot_cpu_data.x86_model) {
2949 case 26:
2950 case 30:
2951 case 37:
2952 case 44:
2953 case 46:
2954 cpu_has_load_perf_global_ctrl = false;
2955 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2956 "does not work properly. Using workaround\n");
2957 break;
2958 default:
2959 break;
2960 }
2961 }
2962
1c3d14fe 2963 return 0;
c68876fd 2964}
6aa8b732
AK		 2965
2966static struct vmcs *alloc_vmcs_cpu(int cpu)
2967{
2968 int node = cpu_to_node(cpu);
2969 struct page *pages;
2970 struct vmcs *vmcs;
2971
6484eb3e 2972 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2973 if (!pages)
2974 return NULL;
2975 vmcs = page_address(pages);
1c3d14fe
YS		 2976 memset(vmcs, 0, vmcs_config.size);
2977 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2978 return vmcs;
2979}
2980
2981static struct vmcs *alloc_vmcs(void)
2982{
d3b2c338 2983 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2984}
2985
2986static void free_vmcs(struct vmcs *vmcs)
2987{
1c3d14fe 2988 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2989}
2990
d462b819
NHE		 2991/*
2992 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2993 */
2994static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2995{
2996 if (!loaded_vmcs->vmcs)
2997 return;
2998 loaded_vmcs_clear(loaded_vmcs);
2999 free_vmcs(loaded_vmcs->vmcs);
3000 loaded_vmcs->vmcs = NULL;
3001}
3002
39959588 3003static void free_kvm_area(void)
6aa8b732
AK		 3004{
3005 int cpu;
3006
3230bb47 3007 for_each_possible_cpu(cpu) {
6aa8b732 3008 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3009 per_cpu(vmxarea, cpu) = NULL;
3010 }
6aa8b732
AK		 3011}
3012
6aa8b732
AK		 3013static __init int alloc_kvm_area(void)
3014{
3015 int cpu;
3016
3230bb47 3017 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3018 struct vmcs *vmcs;
3019
3020 vmcs = alloc_vmcs_cpu(cpu);
3021 if (!vmcs) {
3022 free_kvm_area();
3023 return -ENOMEM;
3024 }
3025
3026 per_cpu(vmxarea, cpu) = vmcs;
3027 }
3028 return 0;
3029}
3030
3031static __init int hardware_setup(void)
3032{
002c7f7c
YS		 3033 if (setup_vmcs_config(&vmcs_config) < 0)
3034 return -EIO;
50a37eb4
JR		 3035
3036 if (boot_cpu_has(X86_FEATURE_NX))
3037 kvm_enable_efer_bits(EFER_NX);
3038
93ba03c2
SY		 3039 if (!cpu_has_vmx_vpid())
3040 enable_vpid = 0;
abc4fc58
AG		 3041 if (!cpu_has_vmx_shadow_vmcs())
3042 enable_shadow_vmcs = 0;
93ba03c2 3043
4bc9b982
SY		 3044 if (!cpu_has_vmx_ept() ||
3045 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3046 enable_ept = 0;
3a624e29 3047 enable_unrestricted_guest = 0;
83c3a331 3048 enable_ept_ad_bits = 0;
3a624e29
NK		 3049 }
3050
83c3a331
XH		 3051 if (!cpu_has_vmx_ept_ad_bits())
3052 enable_ept_ad_bits = 0;
3053
3a624e29
NK		 3054 if (!cpu_has_vmx_unrestricted_guest())
3055 enable_unrestricted_guest = 0;
93ba03c2
SY		 3056
3057 if (!cpu_has_vmx_flexpriority())
3058 flexpriority_enabled = 0;
3059
95ba8273
GN		 3060 if (!cpu_has_vmx_tpr_shadow())
3061 kvm_x86_ops->update_cr8_intercept = NULL;
3062
54dee993
MT		 3063 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3064 kvm_disable_largepages();
3065
4b8d54f9
ZE		 3066 if (!cpu_has_vmx_ple())
3067 ple_gap = 0;
3068
01e439be
YZ		 3069 if (!cpu_has_vmx_apicv())
3070 enable_apicv = 0;
c7c9c56c 3071
01e439be 3072 if (enable_apicv)
c7c9c56c 3073 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3074 else {
c7c9c56c 3075 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3076 kvm_x86_ops->deliver_posted_interrupt = NULL;
3077 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3078 }
83d4c286 3079
b87a51ae
NHE		 3080 if (nested)
3081 nested_vmx_setup_ctls_msrs();
3082
6aa8b732
AK		 3083 return alloc_kvm_area();
3084}
3085
3086static __exit void hardware_unsetup(void)
3087{
3088 free_kvm_area();
3089}
3090
14168786
GN		 3091static bool emulation_required(struct kvm_vcpu *vcpu)
3092{
3093 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3094}
3095
91b0aa2c 3096static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3097 struct kvm_segment *save)
6aa8b732 3098{
d99e4152
GN		 3099 if (!emulate_invalid_guest_state) {
3100 /*
3101 * CS and SS RPL should be equal during guest entry according
3102 * to VMX spec, but in reality it is not always so. Since vcpu
3103 * is in the middle of the transition from real mode to
3104 * protected mode it is safe to assume that RPL 0 is a good
3105 * default value.
3106 */
3107 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3108 save->selector &= ~SELECTOR_RPL_MASK;
3109 save->dpl = save->selector & SELECTOR_RPL_MASK;
3110 save->s = 1;
6aa8b732 3111 }
d99e4152 3112 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3113}
3114
3115static void enter_pmode(struct kvm_vcpu *vcpu)
3116{
3117 unsigned long flags;
a89a8fb9 3118 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3119
d99e4152
GN		 3120 /*
3121 * Update real mode segment cache. It may be not up-to-date if sement
3122 * register was written while vcpu was in a guest mode.
3123 */
3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3126 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3128 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3129 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3130
7ffd92c5 3131 vmx->rmode.vm86_active = 0;
6aa8b732 3132
2fb92db1
AK		 3133 vmx_segment_cache_clear(vmx);
3134
f5f7b2fe 3135 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3136
3137 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3138 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3139 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3140 vmcs_writel(GUEST_RFLAGS, flags);
3141
66aee91a
RR		 3142 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3143 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3144
3145 update_exception_bitmap(vcpu);
3146
91b0aa2c
GN		 3147 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3148 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3149 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3150 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3151 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3152 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3153
3154 /* CPL is always 0 when CPU enters protected mode */
3155 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3156 vmx->cpl = 0;
6aa8b732
AK		 3157}
3158
f5f7b2fe 3159static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3160{
772e0318 3161 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3162 struct kvm_segment var = *save;
3163
3164 var.dpl = 0x3;
3165 if (seg == VCPU_SREG_CS)
3166 var.type = 0x3;
3167
3168 if (!emulate_invalid_guest_state) {
3169 var.selector = var.base >> 4;
3170 var.base = var.base & 0xffff0;
3171 var.limit = 0xffff;
3172 var.g = 0;
3173 var.db = 0;
3174 var.present = 1;
3175 var.s = 1;
3176 var.l = 0;
3177 var.unusable = 0;
3178 var.type = 0x3;
3179 var.avl = 0;
3180 if (save->base & 0xf)
3181 printk_once(KERN_WARNING "kvm: segment base is not "
3182 "paragraph aligned when entering "
3183 "protected mode (seg=%d)", seg);
3184 }
6aa8b732 3185
d99e4152
GN		 3186 vmcs_write16(sf->selector, var.selector);
3187 vmcs_write32(sf->base, var.base);
3188 vmcs_write32(sf->limit, var.limit);
3189 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3190}
3191
3192static void enter_rmode(struct kvm_vcpu *vcpu)
3193{
3194 unsigned long flags;
a89a8fb9 3195 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3196
f5f7b2fe
AK		 3197 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3198 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3199 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3200 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3201 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3202 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3203 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3204
7ffd92c5 3205 vmx->rmode.vm86_active = 1;
6aa8b732 3206
776e58ea
GN		 3207 /*
3208 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3209 * vcpu. Warn the user that an update is overdue.
776e58ea 3210 */
4918c6ca 3211 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3212 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3213 "called before entering vcpu\n");
776e58ea 3214
2fb92db1
AK		 3215 vmx_segment_cache_clear(vmx);
3216
4918c6ca 3217 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3218 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3219 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3220
3221 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3222 vmx->rmode.save_rflags = flags;
6aa8b732 3223
053de044 3224 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3225
3226 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3227 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3228 update_exception_bitmap(vcpu);
3229
d99e4152
GN		 3230 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3231 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3232 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3233 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3234 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3235 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3236
8668a3c4 3237 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3238}
3239
401d10de
AS		 3240static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3241{
3242 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3243 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3244
3245 if (!msr)
3246 return;
401d10de 3247
44ea2b17
AK		 3248 /*
3249 * Force kernel_gs_base reloading before EFER changes, as control
3250 * of this msr depends on is_long_mode().
3251 */
3252 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3253 vcpu->arch.efer = efer;
401d10de 3254 if (efer & EFER_LMA) {
2961e876 3255 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3256 msr->data = efer;
3257 } else {
2961e876 3258 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3259
3260 msr->data = efer & ~EFER_LME;
3261 }
3262 setup_msrs(vmx);
3263}
3264
05b3e0c2 3265#ifdef CONFIG_X86_64
6aa8b732
AK		 3266
3267static void enter_lmode(struct kvm_vcpu *vcpu)
3268{
3269 u32 guest_tr_ar;
3270
2fb92db1
AK		 3271 vmx_segment_cache_clear(to_vmx(vcpu));
3272
6aa8b732
AK		 3273 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3274 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3275 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3276 __func__);
6aa8b732
AK		 3277 vmcs_write32(GUEST_TR_AR_BYTES,
3278 (guest_tr_ar & ~AR_TYPE_MASK)
3279 | AR_TYPE_BUSY_64_TSS);
3280 }
da38f438 3281 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3282}
3283
3284static void exit_lmode(struct kvm_vcpu *vcpu)
3285{
2961e876 3286 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3287 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3288}
3289
3290#endif
3291
2384d2b3
SY		 3292static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3293{
b9d762fa 3294 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3295 if (enable_ept) {
3296 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3297 return;
4e1096d2 3298 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3299 }
2384d2b3
SY		 3300}
3301
e8467fda
AK		 3302static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3303{
3304 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3305
3306 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3307 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3308}
3309
aff48baa
AK		 3310static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3311{
3312 if (enable_ept && is_paging(vcpu))
3313 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3314 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3315}
3316
25c4c276 3317static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3318{
fc78f519
AK		 3319 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3320
3321 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3322 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3323}
3324
1439442c
SY		 3325static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3326{
d0d538b9
GN		 3327 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3328
6de4f3ad
AK		 3329 if (!test_bit(VCPU_EXREG_PDPTR,
3330 (unsigned long *)&vcpu->arch.regs_dirty))
3331 return;
3332
1439442c 3333 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3334 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3335 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3336 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3337 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3338 }
3339}
3340
8f5d549f
AK		 3341static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3342{
d0d538b9
GN		 3343 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3344
8f5d549f 3345 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3346 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3347 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3348 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3349 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3350 }
6de4f3ad
AK		 3351
3352 __set_bit(VCPU_EXREG_PDPTR,
3353 (unsigned long *)&vcpu->arch.regs_avail);
3354 __set_bit(VCPU_EXREG_PDPTR,
3355 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3356}
3357
5e1746d6 3358static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3359
3360static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3361 unsigned long cr0,
3362 struct kvm_vcpu *vcpu)
3363{
5233dd51
MT		 3364 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3365 vmx_decache_cr3(vcpu);
1439442c
SY		 3366 if (!(cr0 & X86_CR0_PG)) {
3367 /* From paging/starting to nonpaging */
3368 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3369 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3370 (CPU_BASED_CR3_LOAD_EXITING |
3371 CPU_BASED_CR3_STORE_EXITING));
3372 vcpu->arch.cr0 = cr0;
fc78f519 3373 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3374 } else if (!is_paging(vcpu)) {
3375 /* From nonpaging to paging */
3376 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3377 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3378 ~(CPU_BASED_CR3_LOAD_EXITING |
3379 CPU_BASED_CR3_STORE_EXITING));
3380 vcpu->arch.cr0 = cr0;
fc78f519 3381 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3382 }
95eb84a7
SY		 3383
3384 if (!(cr0 & X86_CR0_WP))
3385 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3386}
3387
6aa8b732
AK		 3388static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3389{
7ffd92c5 3390 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3391 unsigned long hw_cr0;
3392
5037878e 3393 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3394 if (enable_unrestricted_guest)
5037878e 3395 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3396 else {
5037878e 3397 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3398
218e763f
GN		 3399 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3400 enter_pmode(vcpu);
6aa8b732 3401
218e763f
GN		 3402 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3403 enter_rmode(vcpu);
3404 }
6aa8b732 3405
05b3e0c2 3406#ifdef CONFIG_X86_64
f6801dff 3407 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3408 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3409 enter_lmode(vcpu);
707d92fa 3410 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3411 exit_lmode(vcpu);
3412 }
3413#endif
3414
089d034e 3415 if (enable_ept)
1439442c
SY		 3416 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3417
02daab21 3418 if (!vcpu->fpu_active)
81231c69 3419 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3420
6aa8b732 3421 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3422 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3423 vcpu->arch.cr0 = cr0;
14168786
GN		 3424
3425 /* depends on vcpu->arch.cr0 to be set to a new value */
3426 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3427}
3428
1439442c
SY		 3429static u64 construct_eptp(unsigned long root_hpa)
3430{
3431 u64 eptp;
3432
3433 /* TODO write the value reading from MSR */
3434 eptp = VMX_EPT_DEFAULT_MT |
3435 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3436 if (enable_ept_ad_bits)
3437 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3438 eptp |= (root_hpa & PAGE_MASK);
3439
3440 return eptp;
3441}
3442
6aa8b732
AK		 3443static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3444{
1439442c
SY		 3445 unsigned long guest_cr3;
3446 u64 eptp;
3447
3448 guest_cr3 = cr3;
089d034e 3449 if (enable_ept) {
1439442c
SY		 3450 eptp = construct_eptp(cr3);
3451 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3452 if (is_paging(vcpu) || is_guest_mode(vcpu))
3453 guest_cr3 = kvm_read_cr3(vcpu);
3454 else
3455 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3456 ept_load_pdptrs(vcpu);
1439442c
SY		 3457 }
3458
2384d2b3 3459 vmx_flush_tlb(vcpu);
1439442c 3460 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3461}
3462
5e1746d6 3463static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3464{
7ffd92c5 3465 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3466 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3467
5e1746d6
NHE		 3468 if (cr4 & X86_CR4_VMXE) {
3469 /*
3470 * To use VMXON (and later other VMX instructions), a guest
3471 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3472 * So basically the check on whether to allow nested VMX
3473 * is here.
3474 */
3475 if (!nested_vmx_allowed(vcpu))
3476 return 1;
1a0d74e6
JK		 3477 }
3478 if (to_vmx(vcpu)->nested.vmxon &&
3479 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3480 return 1;
3481
ad312c7c 3482 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3483 if (enable_ept) {
3484 if (!is_paging(vcpu)) {
3485 hw_cr4 &= ~X86_CR4_PAE;
3486 hw_cr4 |= X86_CR4_PSE;
c08800a5 3487 /*
e1e746b3
FW		 3488 * SMEP/SMAP is disabled if CPU is in non-paging mode
3489 * in hardware. However KVM always uses paging mode to
c08800a5 3490 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3491 * To emulate this behavior, SMEP/SMAP needs to be
3492 * manually disabled when guest switches to non-paging
3493 * mode.
c08800a5 3494 */
e1e746b3 3495 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3496 } else if (!(cr4 & X86_CR4_PAE)) {
3497 hw_cr4 &= ~X86_CR4_PAE;
3498 }
3499 }
1439442c
SY		 3500
3501 vmcs_writel(CR4_READ_SHADOW, cr4);
3502 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3503 return 0;
6aa8b732
AK		 3504}
3505
6aa8b732
AK		 3506static void vmx_get_segment(struct kvm_vcpu *vcpu,
3507 struct kvm_segment *var, int seg)
3508{
a9179499 3509 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3510 u32 ar;
3511
c6ad1153 3512 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3513 *var = vmx->rmode.segs[seg];
a9179499 3514 if (seg == VCPU_SREG_TR
2fb92db1 3515 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3516 return;
1390a28b
AK		 3517 var->base = vmx_read_guest_seg_base(vmx, seg);
3518 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3519 return;
a9179499 3520 }
2fb92db1
AK		 3521 var->base = vmx_read_guest_seg_base(vmx, seg);
3522 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3523 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3524 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3525 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3526 var->type = ar & 15;
3527 var->s = (ar >> 4) & 1;
3528 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3529 /*
3530 * Some userspaces do not preserve unusable property. Since usable
3531 * segment has to be present according to VMX spec we can use present
3532 * property to amend userspace bug by making unusable segment always
3533 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3534 * segment as unusable.
3535 */
3536 var->present = !var->unusable;
6aa8b732
AK		 3537 var->avl = (ar >> 12) & 1;
3538 var->l = (ar >> 13) & 1;
3539 var->db = (ar >> 14) & 1;
3540 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3541}
3542
a9179499
AK		 3543static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3544{
a9179499
AK		 3545 struct kvm_segment s;
3546
3547 if (to_vmx(vcpu)->rmode.vm86_active) {
3548 vmx_get_segment(vcpu, &s, seg);
3549 return s.base;
3550 }
2fb92db1 3551 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3552}
3553
b09408d0 3554static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3555{
b09408d0
MT		 3556 struct vcpu_vmx *vmx = to_vmx(vcpu);
3557
3eeb3288 3558 if (!is_protmode(vcpu))
2e4d2653
IE		 3559 return 0;
3560
f4c63e5d
AK		 3561 if (!is_long_mode(vcpu)
3562 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3563 return 3;
3564
69c73028
AK		 3565 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3566 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3567 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3568 }
d881e6f6
AK		 3569
3570 return vmx->cpl;
69c73028
AK		 3571}
3572
3573
653e3108 3574static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3575{
6aa8b732
AK		 3576 u32 ar;
3577
f0495f9b 3578 if (var->unusable || !var->present)
6aa8b732
AK		 3579 ar = 1 << 16;
3580 else {
3581 ar = var->type & 15;
3582 ar |= (var->s & 1) << 4;
3583 ar |= (var->dpl & 3) << 5;
3584 ar |= (var->present & 1) << 7;
3585 ar |= (var->avl & 1) << 12;
3586 ar |= (var->l & 1) << 13;
3587 ar |= (var->db & 1) << 14;
3588 ar |= (var->g & 1) << 15;
3589 }
653e3108
AK		 3590
3591 return ar;
3592}
3593
3594static void vmx_set_segment(struct kvm_vcpu *vcpu,
3595 struct kvm_segment *var, int seg)
3596{
7ffd92c5 3597 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3598 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3599
2fb92db1 3600 vmx_segment_cache_clear(vmx);
2f143240
GN		 3601 if (seg == VCPU_SREG_CS)
3602 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3603
1ecd50a9
GN		 3604 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3605 vmx->rmode.segs[seg] = *var;
3606 if (seg == VCPU_SREG_TR)
3607 vmcs_write16(sf->selector, var->selector);
3608 else if (var->s)
3609 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3610 goto out;
653e3108 3611 }
1ecd50a9 3612
653e3108
AK		 3613 vmcs_writel(sf->base, var->base);
3614 vmcs_write32(sf->limit, var->limit);
3615 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3616
3617 /*
3618 * Fix the "Accessed" bit in AR field of segment registers for older
3619 * qemu binaries.
3620 * IA32 arch specifies that at the time of processor reset the
3621 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3622 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3623 * state vmexit when "unrestricted guest" mode is turned on.
3624 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3625 * tree. Newer qemu binaries with that qemu fix would not need this
3626 * kvm hack.
3627 */
3628 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3629 var->type |= 0x1; /* Accessed */
3a624e29 3630
f924d66d 3631 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3632
3633out:
14168786 3634 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3635}
3636
6aa8b732
AK		 3637static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3638{
2fb92db1 3639 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3640
3641 *db = (ar >> 14) & 1;
3642 *l = (ar >> 13) & 1;
3643}
3644
89a27f4d 3645static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3646{
89a27f4d
GN		 3647 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3648 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3649}
3650
89a27f4d 3651static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3652{
89a27f4d
GN		 3653 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3654 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3655}
3656
89a27f4d 3657static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3658{
89a27f4d
GN		 3659 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3660 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3661}
3662
89a27f4d 3663static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3664{
89a27f4d
GN		 3665 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3666 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3667}
3668
648dfaa7
MG		 3669static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3670{
3671 struct kvm_segment var;
3672 u32 ar;
3673
3674 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3675 var.dpl = 0x3;
0647f4aa
GN		 3676 if (seg == VCPU_SREG_CS)
3677 var.type = 0x3;
648dfaa7
MG		 3678 ar = vmx_segment_access_rights(&var);
3679
3680 if (var.base != (var.selector << 4))
3681 return false;
89efbed0 3682 if (var.limit != 0xffff)
648dfaa7 3683 return false;
07f42f5f 3684 if (ar != 0xf3)
648dfaa7
MG		 3685 return false;
3686
3687 return true;
3688}
3689
3690static bool code_segment_valid(struct kvm_vcpu *vcpu)
3691{
3692 struct kvm_segment cs;
3693 unsigned int cs_rpl;
3694
3695 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3696 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3697
1872a3f4
AK		 3698 if (cs.unusable)
3699 return false;
648dfaa7
MG		 3700 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3701 return false;
3702 if (!cs.s)
3703 return false;
1872a3f4 3704 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3705 if (cs.dpl > cs_rpl)
3706 return false;
1872a3f4 3707 } else {
648dfaa7
MG		 3708 if (cs.dpl != cs_rpl)
3709 return false;
3710 }
3711 if (!cs.present)
3712 return false;
3713
3714 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3715 return true;
3716}
3717
3718static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3719{
3720 struct kvm_segment ss;
3721 unsigned int ss_rpl;
3722
3723 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3724 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3725
1872a3f4
AK		 3726 if (ss.unusable)
3727 return true;
3728 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3729 return false;
3730 if (!ss.s)
3731 return false;
3732 if (ss.dpl != ss_rpl) /* DPL != RPL */
3733 return false;
3734 if (!ss.present)
3735 return false;
3736
3737 return true;
3738}
3739
3740static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3741{
3742 struct kvm_segment var;
3743 unsigned int rpl;
3744
3745 vmx_get_segment(vcpu, &var, seg);
3746 rpl = var.selector & SELECTOR_RPL_MASK;
3747
1872a3f4
AK		 3748 if (var.unusable)
3749 return true;
648dfaa7
MG		 3750 if (!var.s)
3751 return false;
3752 if (!var.present)
3753 return false;
3754 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3755 if (var.dpl < rpl) /* DPL < RPL */
3756 return false;
3757 }
3758
3759 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3760 * rights flags
3761 */
3762 return true;
3763}
3764
3765static bool tr_valid(struct kvm_vcpu *vcpu)
3766{
3767 struct kvm_segment tr;
3768
3769 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3770
1872a3f4
AK		 3771 if (tr.unusable)
3772 return false;
648dfaa7
MG		 3773 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3774 return false;
1872a3f4 3775 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3776 return false;
3777 if (!tr.present)
3778 return false;
3779
3780 return true;
3781}
3782
3783static bool ldtr_valid(struct kvm_vcpu *vcpu)
3784{
3785 struct kvm_segment ldtr;
3786
3787 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3788
1872a3f4
AK		 3789 if (ldtr.unusable)
3790 return true;
648dfaa7
MG		 3791 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3792 return false;
3793 if (ldtr.type != 2)
3794 return false;
3795 if (!ldtr.present)
3796 return false;
3797
3798 return true;
3799}
3800
3801static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3802{
3803 struct kvm_segment cs, ss;
3804
3805 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3806 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3807
3808 return ((cs.selector & SELECTOR_RPL_MASK) ==
3809 (ss.selector & SELECTOR_RPL_MASK));
3810}
3811
3812/*
3813 * Check if guest state is valid. Returns true if valid, false if
3814 * not.
3815 * We assume that registers are always usable
3816 */
3817static bool guest_state_valid(struct kvm_vcpu *vcpu)
3818{
c5e97c80
GN		 3819 if (enable_unrestricted_guest)
3820 return true;
3821
648dfaa7 3822 /* real mode guest state checks */
f13882d8 3823 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3824 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3825 return false;
3826 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3827 return false;
3828 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3829 return false;
3830 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3831 return false;
3832 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3833 return false;
3834 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3835 return false;
3836 } else {
3837 /* protected mode guest state checks */
3838 if (!cs_ss_rpl_check(vcpu))
3839 return false;
3840 if (!code_segment_valid(vcpu))
3841 return false;
3842 if (!stack_segment_valid(vcpu))
3843 return false;
3844 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3845 return false;
3846 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3847 return false;
3848 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3849 return false;
3850 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3851 return false;
3852 if (!tr_valid(vcpu))
3853 return false;
3854 if (!ldtr_valid(vcpu))
3855 return false;
3856 }
3857 /* TODO:
3858 * - Add checks on RIP
3859 * - Add checks on RFLAGS
3860 */
3861
3862 return true;
3863}
3864
d77c26fc 3865static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3866{
40dcaa9f 3867 gfn_t fn;
195aefde 3868 u16 data = 0;
40dcaa9f 3869 int r, idx, ret = 0;
6aa8b732 3870
40dcaa9f 3871 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3872 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3873 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3874 if (r < 0)
10589a46 3875 goto out;
195aefde 3876 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3877 r = kvm_write_guest_page(kvm, fn++, &data,
3878 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3879 if (r < 0)
10589a46 3880 goto out;
195aefde
IE		 3881 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3882 if (r < 0)
10589a46 3883 goto out;
195aefde
IE		 3884 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3885 if (r < 0)
10589a46 3886 goto out;
195aefde 3887 data = ~0;
10589a46
MT		 3888 r = kvm_write_guest_page(kvm, fn, &data,
3889 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3890 sizeof(u8));
195aefde 3891 if (r < 0)
10589a46
MT		 3892 goto out;
3893
3894 ret = 1;
3895out:
40dcaa9f 3896 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3897 return ret;
6aa8b732
AK		 3898}
3899
b7ebfb05
SY		 3900static int init_rmode_identity_map(struct kvm *kvm)
3901{
40dcaa9f 3902 int i, idx, r, ret;
b7ebfb05
SY		 3903 pfn_t identity_map_pfn;
3904 u32 tmp;
3905
089d034e 3906 if (!enable_ept)
b7ebfb05
SY		 3907 return 1;
3908 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3909 printk(KERN_ERR "EPT: identity-mapping pagetable "
3910 "haven't been allocated!\n");
3911 return 0;
3912 }
3913 if (likely(kvm->arch.ept_identity_pagetable_done))
3914 return 1;
3915 ret = 0;
b927a3ce 3916 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3917 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3918 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3919 if (r < 0)
3920 goto out;
3921 /* Set up identity-mapping pagetable for EPT in real mode */
3922 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3923 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3924 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3925 r = kvm_write_guest_page(kvm, identity_map_pfn,
3926 &tmp, i * sizeof(tmp), sizeof(tmp));
3927 if (r < 0)
3928 goto out;
3929 }
3930 kvm->arch.ept_identity_pagetable_done = true;
3931 ret = 1;
3932out:
40dcaa9f 3933 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3934 return ret;
3935}
3936
6aa8b732
AK		 3937static void seg_setup(int seg)
3938{
772e0318 3939 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3940 unsigned int ar;
6aa8b732
AK		 3941
3942 vmcs_write16(sf->selector, 0);
3943 vmcs_writel(sf->base, 0);
3944 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3945 ar = 0x93;
3946 if (seg == VCPU_SREG_CS)
3947 ar |= 0x08; /* code segment */
3a624e29
NK		 3948
3949 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3950}
3951
f78e0e2e
SY		 3952static int alloc_apic_access_page(struct kvm *kvm)
3953{
4484141a 3954 struct page *page;
f78e0e2e
SY		 3955 struct kvm_userspace_memory_region kvm_userspace_mem;
3956 int r = 0;
3957
79fac95e 3958 mutex_lock(&kvm->slots_lock);
bfc6d222 3959 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3960 goto out;
3961 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3962 kvm_userspace_mem.flags = 0;
3963 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3964 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3965 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3966 if (r)
3967 goto out;
72dc67a6 3968
4484141a
XG		 3969 page = gfn_to_page(kvm, 0xfee00);
3970 if (is_error_page(page)) {
3971 r = -EFAULT;
3972 goto out;
3973 }
3974
3975 kvm->arch.apic_access_page = page;
f78e0e2e 3976out:
79fac95e 3977 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3978 return r;
3979}
3980
b7ebfb05
SY		 3981static int alloc_identity_pagetable(struct kvm *kvm)
3982{
4484141a 3983 struct page *page;
b7ebfb05
SY		 3984 struct kvm_userspace_memory_region kvm_userspace_mem;
3985 int r = 0;
3986
79fac95e 3987 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3988 if (kvm->arch.ept_identity_pagetable)
3989 goto out;
3990 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3991 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3992 kvm_userspace_mem.guest_phys_addr =
3993 kvm->arch.ept_identity_map_addr;
b7ebfb05 3994 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3995 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3996 if (r)
3997 goto out;
3998
4484141a
XG		 3999 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4000 if (is_error_page(page)) {
4001 r = -EFAULT;
4002 goto out;
4003 }
4004
4005 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4006out:
79fac95e 4007 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4008 return r;
4009}
4010
2384d2b3
SY		 4011static void allocate_vpid(struct vcpu_vmx *vmx)
4012{
4013 int vpid;
4014
4015 vmx->vpid = 0;
919818ab 4016 if (!enable_vpid)
2384d2b3
SY		 4017 return;
4018 spin_lock(&vmx_vpid_lock);
4019 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4020 if (vpid < VMX_NR_VPIDS) {
4021 vmx->vpid = vpid;
4022 __set_bit(vpid, vmx_vpid_bitmap);
4023 }
4024 spin_unlock(&vmx_vpid_lock);
4025}
4026
cdbecfc3
LJ		 4027static void free_vpid(struct vcpu_vmx *vmx)
4028{
4029 if (!enable_vpid)
4030 return;
4031 spin_lock(&vmx_vpid_lock);
4032 if (vmx->vpid != 0)
4033 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4034 spin_unlock(&vmx_vpid_lock);
4035}
4036
8d14695f
YZ		 4037#define MSR_TYPE_R 1
4038#define MSR_TYPE_W 2
4039static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4040 u32 msr, int type)
25c5f225 4041{
3e7c73e9 4042 int f = sizeof(unsigned long);
25c5f225
SY		 4043
4044 if (!cpu_has_vmx_msr_bitmap())
4045 return;
4046
4047 /*
4048 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4049 * have the write-low and read-high bitmap offsets the wrong way round.
4050 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4051 */
25c5f225 4052 if (msr <= 0x1fff) {
8d14695f
YZ		 4053 if (type & MSR_TYPE_R)
4054 /* read-low */
4055 __clear_bit(msr, msr_bitmap + 0x000 / f);
4056
4057 if (type & MSR_TYPE_W)
4058 /* write-low */
4059 __clear_bit(msr, msr_bitmap + 0x800 / f);
4060
25c5f225
SY		 4061 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4062 msr &= 0x1fff;
8d14695f
YZ		 4063 if (type & MSR_TYPE_R)
4064 /* read-high */
4065 __clear_bit(msr, msr_bitmap + 0x400 / f);
4066
4067 if (type & MSR_TYPE_W)
4068 /* write-high */
4069 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4070
4071 }
4072}
4073
4074static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4075 u32 msr, int type)
4076{
4077 int f = sizeof(unsigned long);
4078
4079 if (!cpu_has_vmx_msr_bitmap())
4080 return;
4081
4082 /*
4083 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4084 * have the write-low and read-high bitmap offsets the wrong way round.
4085 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4086 */
4087 if (msr <= 0x1fff) {
4088 if (type & MSR_TYPE_R)
4089 /* read-low */
4090 __set_bit(msr, msr_bitmap + 0x000 / f);
4091
4092 if (type & MSR_TYPE_W)
4093 /* write-low */
4094 __set_bit(msr, msr_bitmap + 0x800 / f);
4095
4096 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4097 msr &= 0x1fff;
4098 if (type & MSR_TYPE_R)
4099 /* read-high */
4100 __set_bit(msr, msr_bitmap + 0x400 / f);
4101
4102 if (type & MSR_TYPE_W)
4103 /* write-high */
4104 __set_bit(msr, msr_bitmap + 0xc00 / f);
4105
25c5f225 4106 }
25c5f225
SY		 4107}
4108
5897297b
AK		 4109static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4110{
4111 if (!longmode_only)
8d14695f
YZ		 4112 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4113 msr, MSR_TYPE_R | MSR_TYPE_W);
4114 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4115 msr, MSR_TYPE_R | MSR_TYPE_W);
4116}
4117
4118static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4119{
4120 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4121 msr, MSR_TYPE_R);
4122 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4123 msr, MSR_TYPE_R);
4124}
4125
4126static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4127{
4128 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4129 msr, MSR_TYPE_R);
4130 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4131 msr, MSR_TYPE_R);
4132}
4133
4134static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4135{
4136 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4137 msr, MSR_TYPE_W);
4138 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4139 msr, MSR_TYPE_W);
5897297b
AK		 4140}
4141
01e439be
YZ		 4142static int vmx_vm_has_apicv(struct kvm *kvm)
4143{
4144 return enable_apicv && irqchip_in_kernel(kvm);
4145}
4146
a20ed54d
YZ		 4147/*
4148 * Send interrupt to vcpu via posted interrupt way.
4149 * 1. If target vcpu is running(non-root mode), send posted interrupt
4150 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4151 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4152 * interrupt from PIR in next vmentry.
4153 */
4154static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4155{
4156 struct vcpu_vmx *vmx = to_vmx(vcpu);
4157 int r;
4158
4159 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4160 return;
4161
4162 r = pi_test_and_set_on(&vmx->pi_desc);
4163 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4164#ifdef CONFIG_SMP
a20ed54d
YZ		 4165 if (!r && (vcpu->mode == IN_GUEST_MODE))
4166 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4167 POSTED_INTR_VECTOR);
4168 else
6ffbbbba 4169#endif
a20ed54d
YZ		 4170 kvm_vcpu_kick(vcpu);
4171}
4172
4173static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4174{
4175 struct vcpu_vmx *vmx = to_vmx(vcpu);
4176
4177 if (!pi_test_and_clear_on(&vmx->pi_desc))
4178 return;
4179
4180 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4181}
4182
4183static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4184{
4185 return;
4186}
4187
a3a8ff8e
NHE		 4188/*
4189 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4190 * will not change in the lifetime of the guest.
4191 * Note that host-state that does change is set elsewhere. E.g., host-state
4192 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4193 */
a547c6db 4194static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4195{
4196 u32 low32, high32;
4197 unsigned long tmpl;
4198 struct desc_ptr dt;
4199
b1a74bf8 4200 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4201 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4202 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4203
4204 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4205#ifdef CONFIG_X86_64
4206 /*
4207 * Load null selectors, so we can avoid reloading them in
4208 * __vmx_load_host_state(), in case userspace uses the null selectors
4209 * too (the expected case).
4210 */
4211 vmcs_write16(HOST_DS_SELECTOR, 0);
4212 vmcs_write16(HOST_ES_SELECTOR, 0);
4213#else
a3a8ff8e
NHE		 4214 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4215 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4216#endif
a3a8ff8e
NHE		 4217 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4218 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4219
4220 native_store_idt(&dt);
4221 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4222 vmx->host_idt_base = dt.address;
a3a8ff8e 4223
83287ea4 4224 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4225
4226 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4227 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4228 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4229 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4230
4231 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4232 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4233 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4234 }
4235}
4236
bf8179a0
NHE		 4237static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4238{
4239 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4240 if (enable_ept)
4241 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4242 if (is_guest_mode(&vmx->vcpu))
4243 vmx->vcpu.arch.cr4_guest_owned_bits &=
4244 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4245 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4246}
4247
01e439be
YZ		 4248static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4249{
4250 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4251
4252 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4253 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4254 return pin_based_exec_ctrl;
4255}
4256
bf8179a0
NHE		 4257static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4258{
4259 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4260
4261 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4262 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4263
bf8179a0
NHE		 4264 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4265 exec_control &= ~CPU_BASED_TPR_SHADOW;
4266#ifdef CONFIG_X86_64
4267 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4268 CPU_BASED_CR8_LOAD_EXITING;
4269#endif
4270 }
4271 if (!enable_ept)
4272 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4273 CPU_BASED_CR3_LOAD_EXITING |
4274 CPU_BASED_INVLPG_EXITING;
4275 return exec_control;
4276}
4277
4278static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4279{
4280 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4281 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4282 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4283 if (vmx->vpid == 0)
4284 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4285 if (!enable_ept) {
4286 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4287 enable_unrestricted_guest = 0;
ad756a16
MJ		 4288 /* Enable INVPCID for non-ept guests may cause performance regression. */
4289 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4290 }
4291 if (!enable_unrestricted_guest)
4292 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4293 if (!ple_gap)
4294 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4295 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4296 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4297 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4298 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4299 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4300 (handle_vmptrld).
4301 We can NOT enable shadow_vmcs here because we don't have yet
4302 a current VMCS12
4303 */
4304 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4305 return exec_control;
4306}
4307
ce88decf
XG		 4308static void ept_set_mmio_spte_mask(void)
4309{
4310 /*
4311 * EPT Misconfigurations can be generated if the value of bits 2:0
4312 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4313 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4314 * spte.
4315 */
885032b9 4316 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4317}
4318
6aa8b732
AK		 4319/*
4320 * Sets up the vmcs for emulated real mode.
4321 */
8b9cf98c 4322static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4323{
2e4ce7f5 4324#ifdef CONFIG_X86_64
6aa8b732 4325 unsigned long a;
2e4ce7f5 4326#endif
6aa8b732 4327 int i;
6aa8b732 4328
6aa8b732 4329 /* I/O */
3e7c73e9
AK		 4330 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4331 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4332
4607c2d7
AG		 4333 if (enable_shadow_vmcs) {
4334 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4335 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4336 }
25c5f225 4337 if (cpu_has_vmx_msr_bitmap())
5897297b 4338 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4339
6aa8b732
AK		 4340 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4341
6aa8b732 4342 /* Control */
01e439be 4343 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4344
bf8179a0 4345 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4346
83ff3b9d 4347 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4348 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4349 vmx_secondary_exec_control(vmx));
83ff3b9d 4350 }
f78e0e2e 4351
01e439be 4352 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4353 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4354 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4355 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4356 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4357
4358 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4359
4360 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4361 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4362 }
4363
4b8d54f9
ZE		 4364 if (ple_gap) {
4365 vmcs_write32(PLE_GAP, ple_gap);
4366 vmcs_write32(PLE_WINDOW, ple_window);
4367 }
4368
c3707958
XG		 4369 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4370 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4371 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4372
9581d442
AK		 4373 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4374 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4375 vmx_set_constant_host_state(vmx);
05b3e0c2 4376#ifdef CONFIG_X86_64
6aa8b732
AK		 4377 rdmsrl(MSR_FS_BASE, a);
4378 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4379 rdmsrl(MSR_GS_BASE, a);
4380 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4381#else
4382 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4383 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4384#endif
4385
2cc51560
ED		 4386 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4387 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4388 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4389 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4390 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4391
468d472f 4392 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4393 u32 msr_low, msr_high;
4394 u64 host_pat;
468d472f
SY		 4395 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4396 host_pat = msr_low | ((u64) msr_high << 32);
4397 /* Write the default value follow host pat */
4398 vmcs_write64(GUEST_IA32_PAT, host_pat);
4399 /* Keep arch.pat sync with GUEST_IA32_PAT */
4400 vmx->vcpu.arch.pat = host_pat;
4401 }
4402
6aa8b732
AK		 4403 for (i = 0; i < NR_VMX_MSR; ++i) {
4404 u32 index = vmx_msr_index[i];
4405 u32 data_low, data_high;
a2fa3e9f 4406 int j = vmx->nmsrs;
6aa8b732
AK		 4407
4408 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4409 continue;
432bd6cb
AK		 4410 if (wrmsr_safe(index, data_low, data_high) < 0)
4411 continue;
26bb0981
AK		 4412 vmx->guest_msrs[j].index = i;
4413 vmx->guest_msrs[j].data = 0;
d5696725 4414 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4415 ++vmx->nmsrs;
6aa8b732 4416 }
6aa8b732 4417
2961e876
GN		 4418
4419 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4420
4421 /* 22.2.1, 20.8.1 */
2961e876 4422 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4423
e00c8cf2 4424 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4425 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4426
4427 return 0;
4428}
4429
57f252f2 4430static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4431{
4432 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4433 struct msr_data apic_base_msr;
e00c8cf2 4434
7ffd92c5 4435 vmx->rmode.vm86_active = 0;
e00c8cf2 4436
3b86cd99
JK		 4437 vmx->soft_vnmi_blocked = 0;
4438
ad312c7c 4439 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4440 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4441 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4442 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4443 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4444 apic_base_msr.host_initiated = true;
4445 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4446
2fb92db1
AK		 4447 vmx_segment_cache_clear(vmx);
4448
5706be0d 4449 seg_setup(VCPU_SREG_CS);
66450a21 4450 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4451 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4452
4453 seg_setup(VCPU_SREG_DS);
4454 seg_setup(VCPU_SREG_ES);
4455 seg_setup(VCPU_SREG_FS);
4456 seg_setup(VCPU_SREG_GS);
4457 seg_setup(VCPU_SREG_SS);
4458
4459 vmcs_write16(GUEST_TR_SELECTOR, 0);
4460 vmcs_writel(GUEST_TR_BASE, 0);
4461 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4462 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4463
4464 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4465 vmcs_writel(GUEST_LDTR_BASE, 0);
4466 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4467 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4468
4469 vmcs_write32(GUEST_SYSENTER_CS, 0);
4470 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4471 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4472
4473 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4474 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4475
e00c8cf2
AK		 4476 vmcs_writel(GUEST_GDTR_BASE, 0);
4477 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4478
4479 vmcs_writel(GUEST_IDTR_BASE, 0);
4480 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4481
443381a8 4482 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4483 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4484 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4485
e00c8cf2
AK		 4486 /* Special registers */
4487 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4488
4489 setup_msrs(vmx);
4490
6aa8b732
AK		 4491 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4492
f78e0e2e
SY		 4493 if (cpu_has_vmx_tpr_shadow()) {
4494 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4495 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4496 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4497 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4498 vmcs_write32(TPR_THRESHOLD, 0);
4499 }
4500
4501 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4502 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4503 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4504
01e439be
YZ		 4505 if (vmx_vm_has_apicv(vcpu->kvm))
4506 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4507
2384d2b3
SY		 4508 if (vmx->vpid != 0)
4509 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4510
fa40052c 4511 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4512 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4513 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4514 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4515 vmx_fpu_activate(&vmx->vcpu);
4516 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4517
b9d762fa 4518 vpid_sync_context(vmx);
6aa8b732
AK		 4519}
4520
b6f1250e
NHE		 4521/*
4522 * In nested virtualization, check if L1 asked to exit on external interrupts.
4523 * For most existing hypervisors, this will always return true.
4524 */
4525static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4526{
4527 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4528 PIN_BASED_EXT_INTR_MASK;
4529}
4530
77b0f5d6
BD		 4531/*
4532 * In nested virtualization, check if L1 has set
4533 * VM_EXIT_ACK_INTR_ON_EXIT
4534 */
4535static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4536{
4537 return get_vmcs12(vcpu)->vm_exit_controls &
4538 VM_EXIT_ACK_INTR_ON_EXIT;
4539}
4540
ea8ceb83
JK		 4541static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4542{
4543 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4544 PIN_BASED_NMI_EXITING;
4545}
4546
c9a7953f 4547static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4548{
4549 u32 cpu_based_vm_exec_control;
730dca42 4550
3b86cd99
JK		 4551 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4552 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4553 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4554}
4555
c9a7953f 4556static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4557{
4558 u32 cpu_based_vm_exec_control;
4559
c9a7953f
JK		 4560 if (!cpu_has_virtual_nmis() ||
4561 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4562 enable_irq_window(vcpu);
4563 return;
4564 }
3b86cd99
JK		 4565
4566 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4567 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4568 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4569}
4570
66fd3f7f 4571static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4572{
9c8cba37 4573 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4574 uint32_t intr;
4575 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4576
229456fc 4577 trace_kvm_inj_virq(irq);
2714d1d3 4578
fa89a817 4579 ++vcpu->stat.irq_injections;
7ffd92c5 4580 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4581 int inc_eip = 0;
4582 if (vcpu->arch.interrupt.soft)
4583 inc_eip = vcpu->arch.event_exit_inst_len;
4584 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4585 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4586 return;
4587 }
66fd3f7f
GN		 4588 intr = irq | INTR_INFO_VALID_MASK;
4589 if (vcpu->arch.interrupt.soft) {
4590 intr |= INTR_TYPE_SOFT_INTR;
4591 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4592 vmx->vcpu.arch.event_exit_inst_len);
4593 } else
4594 intr |= INTR_TYPE_EXT_INTR;
4595 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4596}
4597
f08864b4
SY		 4598static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4599{
66a5a347
JK		 4600 struct vcpu_vmx *vmx = to_vmx(vcpu);
4601
0b6ac343
NHE		 4602 if (is_guest_mode(vcpu))
4603 return;
4604
3b86cd99
JK		 4605 if (!cpu_has_virtual_nmis()) {
4606 /*
4607 * Tracking the NMI-blocked state in software is built upon
4608 * finding the next open IRQ window. This, in turn, depends on
4609 * well-behaving guests: They have to keep IRQs disabled at
4610 * least as long as the NMI handler runs. Otherwise we may
4611 * cause NMI nesting, maybe breaking the guest. But as this is
4612 * highly unlikely, we can live with the residual risk.
4613 */
4614 vmx->soft_vnmi_blocked = 1;
4615 vmx->vnmi_blocked_time = 0;
4616 }
4617
487b391d 4618 ++vcpu->stat.nmi_injections;
9d58b931 4619 vmx->nmi_known_unmasked = false;
7ffd92c5 4620 if (vmx->rmode.vm86_active) {
71f9833b 4621 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4622 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4623 return;
4624 }
f08864b4
SY		 4625 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4626 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4627}
4628
3cfc3092
JK		 4629static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4630{
4631 if (!cpu_has_virtual_nmis())
4632 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4633 if (to_vmx(vcpu)->nmi_known_unmasked)
4634 return false;
c332c83a 4635 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4636}
4637
4638static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4639{
4640 struct vcpu_vmx *vmx = to_vmx(vcpu);
4641
4642 if (!cpu_has_virtual_nmis()) {
4643 if (vmx->soft_vnmi_blocked != masked) {
4644 vmx->soft_vnmi_blocked = masked;
4645 vmx->vnmi_blocked_time = 0;
4646 }
4647 } else {
9d58b931 4648 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4649 if (masked)
4650 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4651 GUEST_INTR_STATE_NMI);
4652 else
4653 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4654 GUEST_INTR_STATE_NMI);
4655 }
4656}
4657
2505dc9f
JK		 4658static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4659{
b6b8a145
JK		 4660 if (to_vmx(vcpu)->nested.nested_run_pending)
4661 return 0;
ea8ceb83 4662
2505dc9f
JK		 4663 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4664 return 0;
4665
4666 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4667 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4668 | GUEST_INTR_STATE_NMI));
4669}
4670
78646121
GN		 4671static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4672{
b6b8a145
JK		 4673 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4674 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4675 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4676 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4677}
4678
cbc94022
IE		 4679static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4680{
4681 int ret;
4682 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4683 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4684 .guest_phys_addr = addr,
4685 .memory_size = PAGE_SIZE * 3,
4686 .flags = 0,
4687 };
4688
47ae31e2 4689 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4690 if (ret)
4691 return ret;
bfc6d222 4692 kvm->arch.tss_addr = addr;
93ea5388
GN		 4693 if (!init_rmode_tss(kvm))
4694 return -ENOMEM;
4695
cbc94022
IE		 4696 return 0;
4697}
4698
0ca1b4f4 4699static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4700{
77ab6db0 4701 switch (vec) {
77ab6db0 4702 case BP_VECTOR:
c573cd22
JK		 4703 /*
4704 * Update instruction length as we may reinject the exception
4705 * from user space while in guest debugging mode.
4706 */
4707 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4708 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4709 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4710 return false;
4711 /* fall through */
4712 case DB_VECTOR:
4713 if (vcpu->guest_debug &
4714 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4715 return false;
d0bfb940
JK		 4716 /* fall through */
4717 case DE_VECTOR:
77ab6db0
JK		 4718 case OF_VECTOR:
4719 case BR_VECTOR:
4720 case UD_VECTOR:
4721 case DF_VECTOR:
4722 case SS_VECTOR:
4723 case GP_VECTOR:
4724 case MF_VECTOR:
0ca1b4f4
GN		 4725 return true;
4726 break;
77ab6db0 4727 }
0ca1b4f4
GN		 4728 return false;
4729}
4730
4731static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4732 int vec, u32 err_code)
4733{
4734 /*
4735 * Instruction with address size override prefix opcode 0x67
4736 * Cause the #SS fault with 0 error code in VM86 mode.
4737 */
4738 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4739 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4740 if (vcpu->arch.halt_request) {
4741 vcpu->arch.halt_request = 0;
4742 return kvm_emulate_halt(vcpu);
4743 }
4744 return 1;
4745 }
4746 return 0;
4747 }
4748
4749 /*
4750 * Forward all other exceptions that are valid in real mode.
4751 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4752 * the required debugging infrastructure rework.
4753 */
4754 kvm_queue_exception(vcpu, vec);
4755 return 1;
6aa8b732
AK		 4756}
4757
a0861c02
AK		 4758/*
4759 * Trigger machine check on the host. We assume all the MSRs are already set up
4760 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4761 * We pass a fake environment to the machine check handler because we want
4762 * the guest to be always treated like user space, no matter what context
4763 * it used internally.
4764 */
4765static void kvm_machine_check(void)
4766{
4767#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4768 struct pt_regs regs = {
4769 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4770 .flags = X86_EFLAGS_IF,
4771 };
4772
4773 do_machine_check(&regs, 0);
4774#endif
4775}
4776
851ba692 4777static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4778{
4779 /* already handled by vcpu_run */
4780 return 1;
4781}
4782
851ba692 4783static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4784{
1155f76a 4785 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4786 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4787 u32 intr_info, ex_no, error_code;
42dbaa5a 4788 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4789 u32 vect_info;
4790 enum emulation_result er;
4791
1155f76a 4792 vect_info = vmx->idt_vectoring_info;
88786475 4793 intr_info = vmx->exit_intr_info;
6aa8b732 4794
a0861c02 4795 if (is_machine_check(intr_info))
851ba692 4796 return handle_machine_check(vcpu);
a0861c02 4797
e4a41889 4798 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4799 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4800
4801 if (is_no_device(intr_info)) {
5fd86fcf 4802 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4803 return 1;
4804 }
4805
7aa81cc0 4806 if (is_invalid_opcode(intr_info)) {
51d8b661 4807 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4808 if (er != EMULATE_DONE)
7ee5d940 4809 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4810 return 1;
4811 }
4812
6aa8b732 4813 error_code = 0;
2e11384c 4814 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4815 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4816
4817 /*
4818 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4819 * MMIO, it is better to report an internal error.
4820 * See the comments in vmx_handle_exit.
4821 */
4822 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4823 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4824 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4825 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4826 vcpu->run->internal.ndata = 2;
4827 vcpu->run->internal.data[0] = vect_info;
4828 vcpu->run->internal.data[1] = intr_info;
4829 return 0;
4830 }
4831
6aa8b732 4832 if (is_page_fault(intr_info)) {
1439442c 4833 /* EPT won't cause page fault directly */
cf3ace79 4834 BUG_ON(enable_ept);
6aa8b732 4835 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4836 trace_kvm_page_fault(cr2, error_code);
4837
3298b75c 4838 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4839 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4840 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4841 }
4842
d0bfb940 4843 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4844
4845 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4846 return handle_rmode_exception(vcpu, ex_no, error_code);
4847
42dbaa5a
JK		 4848 switch (ex_no) {
4849 case DB_VECTOR:
4850 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4851 if (!(vcpu->guest_debug &
4852 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4853 vcpu->arch.dr6 &= ~15;
4854 vcpu->arch.dr6 |= dr6;
fd2a445a
HD		 4855 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4856 skip_emulated_instruction(vcpu);
4857
42dbaa5a
JK		 4858 kvm_queue_exception(vcpu, DB_VECTOR);
4859 return 1;
4860 }
4861 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4862 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4863 /* fall through */
4864 case BP_VECTOR:
c573cd22
JK		 4865 /*
4866 * Update instruction length as we may reinject #BP from
4867 * user space while in guest debugging mode. Reading it for
4868 * #DB as well causes no harm, it is not used in that case.
4869 */
4870 vmx->vcpu.arch.event_exit_inst_len =
4871 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4872 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4873 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4874 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4875 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4876 break;
4877 default:
d0bfb940
JK		 4878 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4879 kvm_run->ex.exception = ex_no;
4880 kvm_run->ex.error_code = error_code;
42dbaa5a 4881 break;
6aa8b732 4882 }
6aa8b732
AK		 4883 return 0;
4884}
4885
851ba692 4886static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4887{
1165f5fe 4888 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4889 return 1;
4890}
4891
851ba692 4892static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4893{
851ba692 4894 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4895 return 0;
4896}
6aa8b732 4897
851ba692 4898static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4899{
bfdaab09 4900 unsigned long exit_qualification;
34c33d16 4901 int size, in, string;
039576c0 4902 unsigned port;
6aa8b732 4903
bfdaab09 4904 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4905 string = (exit_qualification & 16) != 0;
cf8f70bf 4906 in = (exit_qualification & 8) != 0;
e70669ab 4907
cf8f70bf 4908 ++vcpu->stat.io_exits;
e70669ab 4909
cf8f70bf 4910 if (string || in)
51d8b661 4911 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4912
cf8f70bf
GN		 4913 port = exit_qualification >> 16;
4914 size = (exit_qualification & 7) + 1;
e93f36bc 4915 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4916
4917 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4918}
4919
102d8325
IM		 4920static void
4921vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4922{
4923 /*
4924 * Patch in the VMCALL instruction:
4925 */
4926 hypercall[0] = 0x0f;
4927 hypercall[1] = 0x01;
4928 hypercall[2] = 0xc1;
102d8325
IM		 4929}
4930
92fbc7b1
JK		 4931static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4932{
4933 unsigned long always_on = VMXON_CR0_ALWAYSON;
4934
4935 if (nested_vmx_secondary_ctls_high &
4936 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4937 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4938 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4939 return (val & always_on) == always_on;
4940}
4941
0fa06071 4942/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4943static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4944{
eeadf9e7 4945 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4946 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4947 unsigned long orig_val = val;
4948
eeadf9e7
NHE		 4949 /*
4950 * We get here when L2 changed cr0 in a way that did not change
4951 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4952 * but did change L0 shadowed bits. So we first calculate the
4953 * effective cr0 value that L1 would like to write into the
4954 * hardware. It consists of the L2-owned bits from the new
4955 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4956 */
1a0d74e6
JK		 4957 val = (val & ~vmcs12->cr0_guest_host_mask) |
4958 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4959
92fbc7b1 4960 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4961 return 1;
1a0d74e6
JK		 4962
4963 if (kvm_set_cr0(vcpu, val))
4964 return 1;
4965 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4966 return 0;
1a0d74e6
JK		 4967 } else {
4968 if (to_vmx(vcpu)->nested.vmxon &&
4969 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4970 return 1;
eeadf9e7 4971 return kvm_set_cr0(vcpu, val);
1a0d74e6 4972 }
eeadf9e7
NHE		 4973}
4974
4975static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4976{
4977 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4978 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4979 unsigned long orig_val = val;
4980
4981 /* analogously to handle_set_cr0 */
4982 val = (val & ~vmcs12->cr4_guest_host_mask) |
4983 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4984 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4985 return 1;
1a0d74e6 4986 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4987 return 0;
4988 } else
4989 return kvm_set_cr4(vcpu, val);
4990}
4991
4992/* called to set cr0 as approriate for clts instruction exit. */
4993static void handle_clts(struct kvm_vcpu *vcpu)
4994{
4995 if (is_guest_mode(vcpu)) {
4996 /*
4997 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4998 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4999 * just pretend it's off (also in arch.cr0 for fpu_activate).
5000 */
5001 vmcs_writel(CR0_READ_SHADOW,
5002 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5003 vcpu->arch.cr0 &= ~X86_CR0_TS;
5004 } else
5005 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5006}
5007
851ba692 5008static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5009{
229456fc 5010 unsigned long exit_qualification, val;
6aa8b732
AK		 5011 int cr;
5012 int reg;
49a9b07e 5013 int err;
6aa8b732 5014
bfdaab09 5015 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5016 cr = exit_qualification & 15;
5017 reg = (exit_qualification >> 8) & 15;
5018 switch ((exit_qualification >> 4) & 3) {
5019 case 0: /* mov to cr */
229456fc
MT		 5020 val = kvm_register_read(vcpu, reg);
5021 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5022 switch (cr) {
5023 case 0:
eeadf9e7 5024 err = handle_set_cr0(vcpu, val);
db8fcefa 5025 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5026 return 1;
5027 case 3:
2390218b 5028 err = kvm_set_cr3(vcpu, val);
db8fcefa 5029 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5030 return 1;
5031 case 4:
eeadf9e7 5032 err = handle_set_cr4(vcpu, val);
db8fcefa 5033 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5034 return 1;
0a5fff19
GN		 5035 case 8: {
5036 u8 cr8_prev = kvm_get_cr8(vcpu);
5037 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5038 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5039 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5040 if (irqchip_in_kernel(vcpu->kvm))
5041 return 1;
5042 if (cr8_prev <= cr8)
5043 return 1;
851ba692 5044 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5045 return 0;
5046 }
4b8073e4 5047 }
6aa8b732 5048 break;
25c4c276 5049 case 2: /* clts */
eeadf9e7 5050 handle_clts(vcpu);
4d4ec087 5051 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5052 skip_emulated_instruction(vcpu);
6b52d186 5053 vmx_fpu_activate(vcpu);
25c4c276 5054 return 1;
6aa8b732
AK		 5055 case 1: /*mov from cr*/
5056 switch (cr) {
5057 case 3:
9f8fe504
AK		 5058 val = kvm_read_cr3(vcpu);
5059 kvm_register_write(vcpu, reg, val);
5060 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5061 skip_emulated_instruction(vcpu);
5062 return 1;
5063 case 8:
229456fc
MT		 5064 val = kvm_get_cr8(vcpu);
5065 kvm_register_write(vcpu, reg, val);
5066 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5067 skip_emulated_instruction(vcpu);
5068 return 1;
5069 }
5070 break;
5071 case 3: /* lmsw */
a1f83a74 5072 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5073 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5074 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5075
5076 skip_emulated_instruction(vcpu);
5077 return 1;
5078 default:
5079 break;
5080 }
851ba692 5081 vcpu->run->exit_reason = 0;
a737f256 5082 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5083 (int)(exit_qualification >> 4) & 3, cr);
5084 return 0;
5085}
5086
851ba692 5087static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5088{
bfdaab09 5089 unsigned long exit_qualification;
6aa8b732
AK		 5090 int dr, reg;
5091
f2483415 5092 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5093 if (!kvm_require_cpl(vcpu, 0))
5094 return 1;
42dbaa5a
JK		 5095 dr = vmcs_readl(GUEST_DR7);
5096 if (dr & DR7_GD) {
5097 /*
5098 * As the vm-exit takes precedence over the debug trap, we
5099 * need to emulate the latter, either for the host or the
5100 * guest debugging itself.
5101 */
5102 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5103 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5104 vcpu->run->debug.arch.dr7 = dr;
5105 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5106 vmcs_readl(GUEST_CS_BASE) +
5107 vmcs_readl(GUEST_RIP);
851ba692
AK		 5108 vcpu->run->debug.arch.exception = DB_VECTOR;
5109 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5110 return 0;
5111 } else {
5112 vcpu->arch.dr7 &= ~DR7_GD;
5113 vcpu->arch.dr6 |= DR6_BD;
5114 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5115 kvm_queue_exception(vcpu, DB_VECTOR);
5116 return 1;
5117 }
5118 }
5119
81908bf4
PB		 5120 if (vcpu->guest_debug == 0) {
5121 u32 cpu_based_vm_exec_control;
5122
5123 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5124 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5125 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5126
5127 /*
5128 * No more DR vmexits; force a reload of the debug registers
5129 * and reenter on this instruction. The next vmexit will
5130 * retrieve the full state of the debug registers.
5131 */
5132 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5133 return 1;
5134 }
5135
bfdaab09 5136 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5137 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5138 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5139 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5140 unsigned long val;
4c4d563b
JK		 5141
5142 if (kvm_get_dr(vcpu, dr, &val))
5143 return 1;
5144 kvm_register_write(vcpu, reg, val);
020df079 5145 } else
a4ab9d0c 5146 if (kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg)))
4c4d563b
JK		 5147 return 1;
5148
6aa8b732
AK		 5149 skip_emulated_instruction(vcpu);
5150 return 1;
5151}
5152
73aaf249
JK		 5153static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5154{
5155 return vcpu->arch.dr6;
5156}
5157
5158static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5159{
5160}
5161
81908bf4
PB		 5162static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5163{
5164 u32 cpu_based_vm_exec_control;
5165
5166 get_debugreg(vcpu->arch.db[0], 0);
5167 get_debugreg(vcpu->arch.db[1], 1);
5168 get_debugreg(vcpu->arch.db[2], 2);
5169 get_debugreg(vcpu->arch.db[3], 3);
5170 get_debugreg(vcpu->arch.dr6, 6);
5171 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5172
5173 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5174
5175 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5176 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5177 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5178}
5179
020df079
GN		 5180static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5181{
5182 vmcs_writel(GUEST_DR7, val);
5183}
5184
851ba692 5185static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5186{
06465c5a
AK		 5187 kvm_emulate_cpuid(vcpu);
5188 return 1;
6aa8b732
AK		 5189}
5190
851ba692 5191static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5192{
ad312c7c 5193 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5194 u64 data;
5195
5196 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5197 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5198 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5199 return 1;
5200 }
5201
229456fc 5202 trace_kvm_msr_read(ecx, data);
2714d1d3 5203
6aa8b732 5204 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5205 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5206 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5207 skip_emulated_instruction(vcpu);
5208 return 1;
5209}
5210
851ba692 5211static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5212{
8fe8ab46 5213 struct msr_data msr;
ad312c7c
ZX		 5214 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5215 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5216 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5217
8fe8ab46
WA		 5218 msr.data = data;
5219 msr.index = ecx;
5220 msr.host_initiated = false;
5221 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5222 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5223 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5224 return 1;
5225 }
5226
59200273 5227 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5228 skip_emulated_instruction(vcpu);
5229 return 1;
5230}
5231
851ba692 5232static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5233{
3842d135 5234 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5235 return 1;
5236}
5237
851ba692 5238static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5239{
85f455f7
ED		 5240 u32 cpu_based_vm_exec_control;
5241
5242 /* clear pending irq */
5243 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5244 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5245 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5246
3842d135
AK		 5247 kvm_make_request(KVM_REQ_EVENT, vcpu);
5248
a26bf12a 5249 ++vcpu->stat.irq_window_exits;
2714d1d3 5250
c1150d8c
DL		 5251 /*
5252 * If the user space waits to inject interrupts, exit as soon as
5253 * possible
5254 */
8061823a 5255 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5256 vcpu->run->request_interrupt_window &&
8061823a 5257 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5258 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5259 return 0;
5260 }
6aa8b732
AK		 5261 return 1;
5262}
5263
851ba692 5264static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5265{
5266 skip_emulated_instruction(vcpu);
d3bef15f 5267 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5268}
5269
851ba692 5270static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5271{
510043da 5272 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5273 kvm_emulate_hypercall(vcpu);
5274 return 1;
c21415e8
IM		 5275}
5276
ec25d5e6
GN		 5277static int handle_invd(struct kvm_vcpu *vcpu)
5278{
51d8b661 5279 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5280}
5281
851ba692 5282static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5283{
f9c617f6 5284 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5285
5286 kvm_mmu_invlpg(vcpu, exit_qualification);
5287 skip_emulated_instruction(vcpu);
5288 return 1;
5289}
5290
fee84b07
AK		 5291static int handle_rdpmc(struct kvm_vcpu *vcpu)
5292{
5293 int err;
5294
5295 err = kvm_rdpmc(vcpu);
5296 kvm_complete_insn_gp(vcpu, err);
5297
5298 return 1;
5299}
5300
851ba692 5301static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5302{
5303 skip_emulated_instruction(vcpu);
f5f48ee1 5304 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5305 return 1;
5306}
5307
2acf923e
DC		 5308static int handle_xsetbv(struct kvm_vcpu *vcpu)
5309{
5310 u64 new_bv = kvm_read_edx_eax(vcpu);
5311 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5312
5313 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5314 skip_emulated_instruction(vcpu);
5315 return 1;
5316}
5317
851ba692 5318static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5319{
58fbbf26
KT		 5320 if (likely(fasteoi)) {
5321 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5322 int access_type, offset;
5323
5324 access_type = exit_qualification & APIC_ACCESS_TYPE;
5325 offset = exit_qualification & APIC_ACCESS_OFFSET;
5326 /*
5327 * Sane guest uses MOV to write EOI, with written value
5328 * not cared. So make a short-circuit here by avoiding
5329 * heavy instruction emulation.
5330 */
5331 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5332 (offset == APIC_EOI)) {
5333 kvm_lapic_set_eoi(vcpu);
5334 skip_emulated_instruction(vcpu);
5335 return 1;
5336 }
5337 }
51d8b661 5338 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5339}
5340
c7c9c56c
YZ		 5341static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5342{
5343 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5344 int vector = exit_qualification & 0xff;
5345
5346 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5347 kvm_apic_set_eoi_accelerated(vcpu, vector);
5348 return 1;
5349}
5350
83d4c286
YZ		 5351static int handle_apic_write(struct kvm_vcpu *vcpu)
5352{
5353 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5354 u32 offset = exit_qualification & 0xfff;
5355
5356 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5357 kvm_apic_write_nodecode(vcpu, offset);
5358 return 1;
5359}
5360
851ba692 5361static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5362{
60637aac 5363 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5364 unsigned long exit_qualification;
e269fb21
JK		 5365 bool has_error_code = false;
5366 u32 error_code = 0;
37817f29 5367 u16 tss_selector;
7f3d35fd 5368 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5369
5370 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5371 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5372 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5373
5374 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5375
5376 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5377 if (reason == TASK_SWITCH_GATE && idt_v) {
5378 switch (type) {
5379 case INTR_TYPE_NMI_INTR:
5380 vcpu->arch.nmi_injected = false;
654f06fc 5381 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5382 break;
5383 case INTR_TYPE_EXT_INTR:
66fd3f7f 5384 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5385 kvm_clear_interrupt_queue(vcpu);
5386 break;
5387 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5388 if (vmx->idt_vectoring_info &
5389 VECTORING_INFO_DELIVER_CODE_MASK) {
5390 has_error_code = true;
5391 error_code =
5392 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5393 }
5394 /* fall through */
64a7ec06
GN		 5395 case INTR_TYPE_SOFT_EXCEPTION:
5396 kvm_clear_exception_queue(vcpu);
5397 break;
5398 default:
5399 break;
5400 }
60637aac 5401 }
37817f29
IE		 5402 tss_selector = exit_qualification;
5403
64a7ec06
GN		 5404 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5405 type != INTR_TYPE_EXT_INTR &&
5406 type != INTR_TYPE_NMI_INTR))
5407 skip_emulated_instruction(vcpu);
5408
7f3d35fd
KW		 5409 if (kvm_task_switch(vcpu, tss_selector,
5410 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5411 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5412 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5413 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5414 vcpu->run->internal.ndata = 0;
42dbaa5a 5415 return 0;
acb54517 5416 }
42dbaa5a
JK		 5417
5418 /* clear all local breakpoint enable flags */
5419 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5420
5421 /*
5422 * TODO: What about debug traps on tss switch?
5423 * Are we supposed to inject them and update dr6?
5424 */
5425
5426 return 1;
37817f29
IE		 5427}
5428
851ba692 5429static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5430{
f9c617f6 5431 unsigned long exit_qualification;
1439442c 5432 gpa_t gpa;
4f5982a5 5433 u32 error_code;
1439442c 5434 int gla_validity;
1439442c 5435
f9c617f6 5436 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5437
1439442c
SY		 5438 gla_validity = (exit_qualification >> 7) & 0x3;
5439 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5440 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5441 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5442 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5443 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5444 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5445 (long unsigned int)exit_qualification);
851ba692
AK		 5446 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5447 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5448 return 0;
1439442c
SY		 5449 }
5450
0be9c7a8
GN		 5451 /*
5452 * EPT violation happened while executing iret from NMI,
5453 * "blocked by NMI" bit has to be set before next VM entry.
5454 * There are errata that may cause this bit to not be set:
5455 * AAK134, BY25.
5456 */
bcd1c294
GN		 5457 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5458 cpu_has_virtual_nmis() &&
5459 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5460 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5461
1439442c 5462 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5463 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5464
5465 /* It is a write fault? */
5466 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5467 /* It is a fetch fault? */
5468 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5469 /* ept page table is present? */
5470 error_code |= (exit_qualification >> 3) & 0x1;
5471
25d92081
YZ		 5472 vcpu->arch.exit_qualification = exit_qualification;
5473
4f5982a5 5474 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5475}
5476
68f89400
MT		 5477static u64 ept_rsvd_mask(u64 spte, int level)
5478{
5479 int i;
5480 u64 mask = 0;
5481
5482 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5483 mask |= (1ULL << i);
5484
5485 if (level > 2)
5486 /* bits 7:3 reserved */
5487 mask |= 0xf8;
5488 else if (level == 2) {
5489 if (spte & (1ULL << 7))
5490 /* 2MB ref, bits 20:12 reserved */
5491 mask |= 0x1ff000;
5492 else
5493 /* bits 6:3 reserved */
5494 mask |= 0x78;
5495 }
5496
5497 return mask;
5498}
5499
5500static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5501 int level)
5502{
5503 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5504
5505 /* 010b (write-only) */
5506 WARN_ON((spte & 0x7) == 0x2);
5507
5508 /* 110b (write/execute) */
5509 WARN_ON((spte & 0x7) == 0x6);
5510
5511 /* 100b (execute-only) and value not supported by logical processor */
5512 if (!cpu_has_vmx_ept_execute_only())
5513 WARN_ON((spte & 0x7) == 0x4);
5514
5515 /* not 000b */
5516 if ((spte & 0x7)) {
5517 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5518
5519 if (rsvd_bits != 0) {
5520 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5521 __func__, rsvd_bits);
5522 WARN_ON(1);
5523 }
5524
5525 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5526 u64 ept_mem_type = (spte & 0x38) >> 3;
5527
5528 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5529 ept_mem_type == 7) {
5530 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5531 __func__, ept_mem_type);
5532 WARN_ON(1);
5533 }
5534 }
5535 }
5536}
5537
851ba692 5538static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5539{
5540 u64 sptes[4];
ce88decf 5541 int nr_sptes, i, ret;
68f89400
MT		 5542 gpa_t gpa;
5543
5544 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5545 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5546 skip_emulated_instruction(vcpu);
5547 return 1;
5548 }
68f89400 5549
ce88decf 5550 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5551 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5552 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5553 EMULATE_DONE;
f8f55942
XG		 5554
5555 if (unlikely(ret == RET_MMIO_PF_INVALID))
5556 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5557
b37fbea6 5558 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5559 return 1;
5560
5561 /* It is the real ept misconfig */
68f89400
MT		 5562 printk(KERN_ERR "EPT: Misconfiguration.\n");
5563 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5564
5565 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5566
5567 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5568 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5569
851ba692
AK		 5570 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5571 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5572
5573 return 0;
5574}
5575
851ba692 5576static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5577{
5578 u32 cpu_based_vm_exec_control;
5579
5580 /* clear pending NMI */
5581 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5582 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5583 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5584 ++vcpu->stat.nmi_window_exits;
3842d135 5585 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5586
5587 return 1;
5588}
5589
80ced186 5590static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5591{
8b3079a5
AK		 5592 struct vcpu_vmx *vmx = to_vmx(vcpu);
5593 enum emulation_result err = EMULATE_DONE;
80ced186 5594 int ret = 1;
49e9d557
AK		 5595 u32 cpu_exec_ctrl;
5596 bool intr_window_requested;
b8405c18 5597 unsigned count = 130;
49e9d557
AK		 5598
5599 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5600 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5601
b8405c18 5602 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5603 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5604 return handle_interrupt_window(&vmx->vcpu);
5605
de87dcdd
AK		 5606 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5607 return 1;
5608
991eebf9 5609 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5610
ac0a48c3 5611 if (err == EMULATE_USER_EXIT) {
94452b9e 5612 ++vcpu->stat.mmio_exits;
80ced186
MG		 5613 ret = 0;
5614 goto out;
5615 }
1d5a4d9b 5616
de5f70e0
AK		 5617 if (err != EMULATE_DONE) {
5618 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5619 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5620 vcpu->run->internal.ndata = 0;
6d77dbfc 5621 return 0;
de5f70e0 5622 }
ea953ef0 5623
8d76c49e
GN		 5624 if (vcpu->arch.halt_request) {
5625 vcpu->arch.halt_request = 0;
5626 ret = kvm_emulate_halt(vcpu);
5627 goto out;
5628 }
5629
ea953ef0 5630 if (signal_pending(current))
80ced186 5631 goto out;
ea953ef0
MG		 5632 if (need_resched())
5633 schedule();
5634 }
5635
14168786 5636 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5637out:
5638 return ret;
ea953ef0
MG		 5639}
5640
4b8d54f9
ZE		 5641/*
5642 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5643 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5644 */
9fb41ba8 5645static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5646{
5647 skip_emulated_instruction(vcpu);
5648 kvm_vcpu_on_spin(vcpu);
5649
5650 return 1;
5651}
5652
59708670
SY		 5653static int handle_invalid_op(struct kvm_vcpu *vcpu)
5654{
5655 kvm_queue_exception(vcpu, UD_VECTOR);
5656 return 1;
5657}
5658
ff2f6fe9
NHE		 5659/*
5660 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5661 * We could reuse a single VMCS for all the L2 guests, but we also want the
5662 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5663 * allows keeping them loaded on the processor, and in the future will allow
5664 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5665 * every entry if they never change.
5666 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5667 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5668 *
5669 * The following functions allocate and free a vmcs02 in this pool.
5670 */
5671
5672/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5673static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5674{
5675 struct vmcs02_list *item;
5676 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5677 if (item->vmptr == vmx->nested.current_vmptr) {
5678 list_move(&item->list, &vmx->nested.vmcs02_pool);
5679 return &item->vmcs02;
5680 }
5681
5682 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5683 /* Recycle the least recently used VMCS. */
5684 item = list_entry(vmx->nested.vmcs02_pool.prev,
5685 struct vmcs02_list, list);
5686 item->vmptr = vmx->nested.current_vmptr;
5687 list_move(&item->list, &vmx->nested.vmcs02_pool);
5688 return &item->vmcs02;
5689 }
5690
5691 /* Create a new VMCS */
0fa24ce3 5692 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5693 if (!item)
5694 return NULL;
5695 item->vmcs02.vmcs = alloc_vmcs();
5696 if (!item->vmcs02.vmcs) {
5697 kfree(item);
5698 return NULL;
5699 }
5700 loaded_vmcs_init(&item->vmcs02);
5701 item->vmptr = vmx->nested.current_vmptr;
5702 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5703 vmx->nested.vmcs02_num++;
5704 return &item->vmcs02;
5705}
5706
5707/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5708static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5709{
5710 struct vmcs02_list *item;
5711 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5712 if (item->vmptr == vmptr) {
5713 free_loaded_vmcs(&item->vmcs02);
5714 list_del(&item->list);
5715 kfree(item);
5716 vmx->nested.vmcs02_num--;
5717 return;
5718 }
5719}
5720
5721/*
5722 * Free all VMCSs saved for this vcpu, except the one pointed by
5723 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5724 * currently used, if running L2), and vmcs01 when running L2.
5725 */
5726static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5727{
5728 struct vmcs02_list *item, *n;
5729 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5730 if (vmx->loaded_vmcs != &item->vmcs02)
5731 free_loaded_vmcs(&item->vmcs02);
5732 list_del(&item->list);
5733 kfree(item);
5734 }
5735 vmx->nested.vmcs02_num = 0;
5736
5737 if (vmx->loaded_vmcs != &vmx->vmcs01)
5738 free_loaded_vmcs(&vmx->vmcs01);
5739}
5740
0658fbaa
ACL		 5741/*
5742 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5743 * set the success or error code of an emulated VMX instruction, as specified
5744 * by Vol 2B, VMX Instruction Reference, "Conventions".
5745 */
5746static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5747{
5748 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5749 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5750 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5751}
5752
5753static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5754{
5755 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5756 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5757 X86_EFLAGS_SF | X86_EFLAGS_OF))
5758 | X86_EFLAGS_CF);
5759}
5760
145c28dd 5761static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5762 u32 vm_instruction_error)
5763{
5764 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5765 /*
5766 * failValid writes the error number to the current VMCS, which
5767 * can't be done there isn't a current VMCS.
5768 */
5769 nested_vmx_failInvalid(vcpu);
5770 return;
5771 }
5772 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5773 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5774 X86_EFLAGS_SF | X86_EFLAGS_OF))
5775 | X86_EFLAGS_ZF);
5776 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5777 /*
5778 * We don't need to force a shadow sync because
5779 * VM_INSTRUCTION_ERROR is not shadowed
5780 */
5781}
145c28dd 5782
f4124500
JK		 5783static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5784{
5785 struct vcpu_vmx *vmx =
5786 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5787
5788 vmx->nested.preemption_timer_expired = true;
5789 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5790 kvm_vcpu_kick(&vmx->vcpu);
5791
5792 return HRTIMER_NORESTART;
5793}
5794
19677e32
BD		 5795/*
5796 * Decode the memory-address operand of a vmx instruction, as recorded on an
5797 * exit caused by such an instruction (run by a guest hypervisor).
5798 * On success, returns 0. When the operand is invalid, returns 1 and throws
5799 * #UD or #GP.
5800 */
5801static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5802 unsigned long exit_qualification,
5803 u32 vmx_instruction_info, gva_t *ret)
5804{
5805 /*
5806 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5807 * Execution", on an exit, vmx_instruction_info holds most of the
5808 * addressing components of the operand. Only the displacement part
5809 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5810 * For how an actual address is calculated from all these components,
5811 * refer to Vol. 1, "Operand Addressing".
5812 */
5813 int scaling = vmx_instruction_info & 3;
5814 int addr_size = (vmx_instruction_info >> 7) & 7;
5815 bool is_reg = vmx_instruction_info & (1u << 10);
5816 int seg_reg = (vmx_instruction_info >> 15) & 7;
5817 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5818 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5819 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5820 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5821
5822 if (is_reg) {
5823 kvm_queue_exception(vcpu, UD_VECTOR);
5824 return 1;
5825 }
5826
5827 /* Addr = segment_base + offset */
5828 /* offset = base + [index * scale] + displacement */
5829 *ret = vmx_get_segment_base(vcpu, seg_reg);
5830 if (base_is_valid)
5831 *ret += kvm_register_read(vcpu, base_reg);
5832 if (index_is_valid)
5833 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5834 *ret += exit_qualification; /* holds the displacement */
5835
5836 if (addr_size == 1) /* 32 bit */
5837 *ret &= 0xffffffff;
5838
5839 /*
5840 * TODO: throw #GP (and return 1) in various cases that the VM*
5841 * instructions require it - e.g., offset beyond segment limit,
5842 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5843 * address, and so on. Currently these are not checked.
5844 */
5845 return 0;
5846}
5847
3573e22c
BD		 5848/*
5849 * This function performs the various checks including
5850 * - if it's 4KB aligned
5851 * - No bits beyond the physical address width are set
5852 * - Returns 0 on success or else 1
4291b588 5853 * (Intel SDM Section 30.3)
3573e22c 5854 */
4291b588
BD		 5855static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
5856 gpa_t *vmpointer)
3573e22c
BD		 5857{
5858 gva_t gva;
5859 gpa_t vmptr;
5860 struct x86_exception e;
5861 struct page *page;
5862 struct vcpu_vmx *vmx = to_vmx(vcpu);
5863 int maxphyaddr = cpuid_maxphyaddr(vcpu);
5864
5865 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5866 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5867 return 1;
5868
5869 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5870 sizeof(vmptr), &e)) {
5871 kvm_inject_page_fault(vcpu, &e);
5872 return 1;
5873 }
5874
5875 switch (exit_reason) {
5876 case EXIT_REASON_VMON:
5877 /*
5878 * SDM 3: 24.11.5
5879 * The first 4 bytes of VMXON region contain the supported
5880 * VMCS revision identifier
5881 *
5882 * Note - IA32_VMX_BASIC[48] will never be 1
5883 * for the nested case;
5884 * which replaces physical address width with 32
5885 *
5886 */
5887 if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) {
5888 nested_vmx_failInvalid(vcpu);
5889 skip_emulated_instruction(vcpu);
5890 return 1;
5891 }
5892
5893 page = nested_get_page(vcpu, vmptr);
5894 if (page == NULL ||
5895 *(u32 *)kmap(page) != VMCS12_REVISION) {
5896 nested_vmx_failInvalid(vcpu);
5897 kunmap(page);
5898 skip_emulated_instruction(vcpu);
5899 return 1;
5900 }
5901 kunmap(page);
5902 vmx->nested.vmxon_ptr = vmptr;
5903 break;
4291b588
BD		 5904 case EXIT_REASON_VMCLEAR:
5905 if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) {
5906 nested_vmx_failValid(vcpu,
5907 VMXERR_VMCLEAR_INVALID_ADDRESS);
5908 skip_emulated_instruction(vcpu);
5909 return 1;
5910 }
5911
5912 if (vmptr == vmx->nested.vmxon_ptr) {
5913 nested_vmx_failValid(vcpu,
5914 VMXERR_VMCLEAR_VMXON_POINTER);
5915 skip_emulated_instruction(vcpu);
5916 return 1;
5917 }
5918 break;
5919 case EXIT_REASON_VMPTRLD:
5920 if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) {
5921 nested_vmx_failValid(vcpu,
5922 VMXERR_VMPTRLD_INVALID_ADDRESS);
5923 skip_emulated_instruction(vcpu);
5924 return 1;
5925 }
3573e22c 5926
4291b588
BD		 5927 if (vmptr == vmx->nested.vmxon_ptr) {
5928 nested_vmx_failValid(vcpu,
5929 VMXERR_VMCLEAR_VMXON_POINTER);
5930 skip_emulated_instruction(vcpu);
5931 return 1;
5932 }
5933 break;
3573e22c
BD		 5934 default:
5935 return 1; /* shouldn't happen */
5936 }
5937
4291b588
BD		 5938 if (vmpointer)
5939 *vmpointer = vmptr;
3573e22c
BD		 5940 return 0;
5941}
5942
ec378aee
NHE		 5943/*
5944 * Emulate the VMXON instruction.
5945 * Currently, we just remember that VMX is active, and do not save or even
5946 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5947 * do not currently need to store anything in that guest-allocated memory
5948 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5949 * argument is different from the VMXON pointer (which the spec says they do).
5950 */
5951static int handle_vmon(struct kvm_vcpu *vcpu)
5952{
5953 struct kvm_segment cs;
5954 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5955 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5956 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5957 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5958
5959 /* The Intel VMX Instruction Reference lists a bunch of bits that
5960 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5961 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5962 * Otherwise, we should fail with #UD. We test these now:
5963 */
5964 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5965 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5966 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5967 kvm_queue_exception(vcpu, UD_VECTOR);
5968 return 1;
5969 }
5970
5971 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5972 if (is_long_mode(vcpu) && !cs.l) {
5973 kvm_queue_exception(vcpu, UD_VECTOR);
5974 return 1;
5975 }
5976
5977 if (vmx_get_cpl(vcpu)) {
5978 kvm_inject_gp(vcpu, 0);
5979 return 1;
5980 }
3573e22c 5981
4291b588 5982 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 5983 return 1;
5984
145c28dd
AG		 5985 if (vmx->nested.vmxon) {
5986 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5987 skip_emulated_instruction(vcpu);
5988 return 1;
5989 }
b3897a49
NHE		 5990
5991 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5992 != VMXON_NEEDED_FEATURES) {
5993 kvm_inject_gp(vcpu, 0);
5994 return 1;
5995 }
5996
8de48833
AG		 5997 if (enable_shadow_vmcs) {
5998 shadow_vmcs = alloc_vmcs();
5999 if (!shadow_vmcs)
6000 return -ENOMEM;
6001 /* mark vmcs as shadow */
6002 shadow_vmcs->revision_id |= (1u << 31);
6003 /* init shadow vmcs */
6004 vmcs_clear(shadow_vmcs);
6005 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6006 }
ec378aee 6007
ff2f6fe9
NHE		 6008 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6009 vmx->nested.vmcs02_num = 0;
6010
f4124500
JK		 6011 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6012 HRTIMER_MODE_REL);
6013 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6014
ec378aee
NHE		 6015 vmx->nested.vmxon = true;
6016
6017 skip_emulated_instruction(vcpu);
a25eb114 6018 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6019 return 1;
6020}
6021
6022/*
6023 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6024 * for running VMX instructions (except VMXON, whose prerequisites are
6025 * slightly different). It also specifies what exception to inject otherwise.
6026 */
6027static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6028{
6029 struct kvm_segment cs;
6030 struct vcpu_vmx *vmx = to_vmx(vcpu);
6031
6032 if (!vmx->nested.vmxon) {
6033 kvm_queue_exception(vcpu, UD_VECTOR);
6034 return 0;
6035 }
6036
6037 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6038 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6039 (is_long_mode(vcpu) && !cs.l)) {
6040 kvm_queue_exception(vcpu, UD_VECTOR);
6041 return 0;
6042 }
6043
6044 if (vmx_get_cpl(vcpu)) {
6045 kvm_inject_gp(vcpu, 0);
6046 return 0;
6047 }
6048
6049 return 1;
6050}
6051
e7953d7f
AG		 6052static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6053{
8a1b9dd0 6054 u32 exec_control;
012f83cb
AG		 6055 if (enable_shadow_vmcs) {
6056 if (vmx->nested.current_vmcs12 != NULL) {
6057 /* copy to memory all shadowed fields in case
6058 they were modified */
6059 copy_shadow_to_vmcs12(vmx);
6060 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 6061 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6062 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6063 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6064 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 6065 }
6066 }
e7953d7f
AG		 6067 kunmap(vmx->nested.current_vmcs12_page);
6068 nested_release_page(vmx->nested.current_vmcs12_page);
6069}
6070
ec378aee
NHE		 6071/*
6072 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6073 * just stops using VMX.
6074 */
6075static void free_nested(struct vcpu_vmx *vmx)
6076{
6077 if (!vmx->nested.vmxon)
6078 return;
6079 vmx->nested.vmxon = false;
a9d30f33 6080 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 6081 nested_release_vmcs12(vmx);
a9d30f33
NHE		 6082 vmx->nested.current_vmptr = -1ull;
6083 vmx->nested.current_vmcs12 = NULL;
6084 }
e7953d7f
AG		 6085 if (enable_shadow_vmcs)
6086 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6087 /* Unpin physical memory we referred to in current vmcs02 */
6088 if (vmx->nested.apic_access_page) {
6089 nested_release_page(vmx->nested.apic_access_page);
6090 vmx->nested.apic_access_page = 0;
6091 }
ff2f6fe9
NHE		 6092
6093 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6094}
6095
6096/* Emulate the VMXOFF instruction */
6097static int handle_vmoff(struct kvm_vcpu *vcpu)
6098{
6099 if (!nested_vmx_check_permission(vcpu))
6100 return 1;
6101 free_nested(to_vmx(vcpu));
6102 skip_emulated_instruction(vcpu);
a25eb114 6103 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6104 return 1;
6105}
6106
27d6c865
NHE		 6107/* Emulate the VMCLEAR instruction */
6108static int handle_vmclear(struct kvm_vcpu *vcpu)
6109{
6110 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6111 gpa_t vmptr;
6112 struct vmcs12 *vmcs12;
6113 struct page *page;
27d6c865
NHE		 6114
6115 if (!nested_vmx_check_permission(vcpu))
6116 return 1;
6117
4291b588 6118 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865
NHE		 6119 return 1;
6120
27d6c865 6121 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6122 nested_release_vmcs12(vmx);
27d6c865
NHE		 6123 vmx->nested.current_vmptr = -1ull;
6124 vmx->nested.current_vmcs12 = NULL;
6125 }
6126
6127 page = nested_get_page(vcpu, vmptr);
6128 if (page == NULL) {
6129 /*
6130 * For accurate processor emulation, VMCLEAR beyond available
6131 * physical memory should do nothing at all. However, it is
6132 * possible that a nested vmx bug, not a guest hypervisor bug,
6133 * resulted in this case, so let's shut down before doing any
6134 * more damage:
6135 */
6136 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6137 return 1;
6138 }
6139 vmcs12 = kmap(page);
6140 vmcs12->launch_state = 0;
6141 kunmap(page);
6142 nested_release_page(page);
6143
6144 nested_free_vmcs02(vmx, vmptr);
6145
6146 skip_emulated_instruction(vcpu);
6147 nested_vmx_succeed(vcpu);
6148 return 1;
6149}
6150
cd232ad0
NHE		 6151static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6152
6153/* Emulate the VMLAUNCH instruction */
6154static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6155{
6156 return nested_vmx_run(vcpu, true);
6157}
6158
6159/* Emulate the VMRESUME instruction */
6160static int handle_vmresume(struct kvm_vcpu *vcpu)
6161{
6162
6163 return nested_vmx_run(vcpu, false);
6164}
6165
49f705c5
NHE		 6166enum vmcs_field_type {
6167 VMCS_FIELD_TYPE_U16 = 0,
6168 VMCS_FIELD_TYPE_U64 = 1,
6169 VMCS_FIELD_TYPE_U32 = 2,
6170 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6171};
6172
6173static inline int vmcs_field_type(unsigned long field)
6174{
6175 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6176 return VMCS_FIELD_TYPE_U32;
6177 return (field >> 13) & 0x3 ;
6178}
6179
6180static inline int vmcs_field_readonly(unsigned long field)
6181{
6182 return (((field >> 10) & 0x3) == 1);
6183}
6184
6185/*
6186 * Read a vmcs12 field. Since these can have varying lengths and we return
6187 * one type, we chose the biggest type (u64) and zero-extend the return value
6188 * to that size. Note that the caller, handle_vmread, might need to use only
6189 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6190 * 64-bit fields are to be returned).
6191 */
6192static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6193 unsigned long field, u64 *ret)
6194{
6195 short offset = vmcs_field_to_offset(field);
6196 char *p;
6197
6198 if (offset < 0)
6199 return 0;
6200
6201 p = ((char *)(get_vmcs12(vcpu))) + offset;
6202
6203 switch (vmcs_field_type(field)) {
6204 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6205 *ret = *((natural_width *)p);
6206 return 1;
6207 case VMCS_FIELD_TYPE_U16:
6208 *ret = *((u16 *)p);
6209 return 1;
6210 case VMCS_FIELD_TYPE_U32:
6211 *ret = *((u32 *)p);
6212 return 1;
6213 case VMCS_FIELD_TYPE_U64:
6214 *ret = *((u64 *)p);
6215 return 1;
6216 default:
6217 return 0; /* can never happen. */
6218 }
6219}
6220
20b97fea
AG		 6221
6222static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6223 unsigned long field, u64 field_value){
6224 short offset = vmcs_field_to_offset(field);
6225 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6226 if (offset < 0)
6227 return false;
6228
6229 switch (vmcs_field_type(field)) {
6230 case VMCS_FIELD_TYPE_U16:
6231 *(u16 *)p = field_value;
6232 return true;
6233 case VMCS_FIELD_TYPE_U32:
6234 *(u32 *)p = field_value;
6235 return true;
6236 case VMCS_FIELD_TYPE_U64:
6237 *(u64 *)p = field_value;
6238 return true;
6239 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6240 *(natural_width *)p = field_value;
6241 return true;
6242 default:
6243 return false; /* can never happen. */
6244 }
6245
6246}
6247
16f5b903
AG		 6248static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6249{
6250 int i;
6251 unsigned long field;
6252 u64 field_value;
6253 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6254 const unsigned long *fields = shadow_read_write_fields;
6255 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6256
6257 vmcs_load(shadow_vmcs);
6258
6259 for (i = 0; i < num_fields; i++) {
6260 field = fields[i];
6261 switch (vmcs_field_type(field)) {
6262 case VMCS_FIELD_TYPE_U16:
6263 field_value = vmcs_read16(field);
6264 break;
6265 case VMCS_FIELD_TYPE_U32:
6266 field_value = vmcs_read32(field);
6267 break;
6268 case VMCS_FIELD_TYPE_U64:
6269 field_value = vmcs_read64(field);
6270 break;
6271 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6272 field_value = vmcs_readl(field);
6273 break;
6274 }
6275 vmcs12_write_any(&vmx->vcpu, field, field_value);
6276 }
6277
6278 vmcs_clear(shadow_vmcs);
6279 vmcs_load(vmx->loaded_vmcs->vmcs);
6280}
6281
c3114420
AG		 6282static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6283{
c2bae893
MK		 6284 const unsigned long *fields[] = {
6285 shadow_read_write_fields,
6286 shadow_read_only_fields
c3114420 6287 };
c2bae893 6288 const int max_fields[] = {
c3114420
AG		 6289 max_shadow_read_write_fields,
6290 max_shadow_read_only_fields
6291 };
6292 int i, q;
6293 unsigned long field;
6294 u64 field_value = 0;
6295 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6296
6297 vmcs_load(shadow_vmcs);
6298
c2bae893 6299 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6300 for (i = 0; i < max_fields[q]; i++) {
6301 field = fields[q][i];
6302 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6303
6304 switch (vmcs_field_type(field)) {
6305 case VMCS_FIELD_TYPE_U16:
6306 vmcs_write16(field, (u16)field_value);
6307 break;
6308 case VMCS_FIELD_TYPE_U32:
6309 vmcs_write32(field, (u32)field_value);
6310 break;
6311 case VMCS_FIELD_TYPE_U64:
6312 vmcs_write64(field, (u64)field_value);
6313 break;
6314 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6315 vmcs_writel(field, (long)field_value);
6316 break;
6317 }
6318 }
6319 }
6320
6321 vmcs_clear(shadow_vmcs);
6322 vmcs_load(vmx->loaded_vmcs->vmcs);
6323}
6324
49f705c5
NHE		 6325/*
6326 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6327 * used before) all generate the same failure when it is missing.
6328 */
6329static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6330{
6331 struct vcpu_vmx *vmx = to_vmx(vcpu);
6332 if (vmx->nested.current_vmptr == -1ull) {
6333 nested_vmx_failInvalid(vcpu);
6334 skip_emulated_instruction(vcpu);
6335 return 0;
6336 }
6337 return 1;
6338}
6339
6340static int handle_vmread(struct kvm_vcpu *vcpu)
6341{
6342 unsigned long field;
6343 u64 field_value;
6344 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6345 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6346 gva_t gva = 0;
6347
6348 if (!nested_vmx_check_permission(vcpu) ||
6349 !nested_vmx_check_vmcs12(vcpu))
6350 return 1;
6351
6352 /* Decode instruction info and find the field to read */
6353 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6354 /* Read the field, zero-extended to a u64 field_value */
6355 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6356 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6357 skip_emulated_instruction(vcpu);
6358 return 1;
6359 }
6360 /*
6361 * Now copy part of this value to register or memory, as requested.
6362 * Note that the number of bits actually copied is 32 or 64 depending
6363 * on the guest's mode (32 or 64 bit), not on the given field's length.
6364 */
6365 if (vmx_instruction_info & (1u << 10)) {
6366 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6367 field_value);
6368 } else {
6369 if (get_vmx_mem_address(vcpu, exit_qualification,
6370 vmx_instruction_info, &gva))
6371 return 1;
6372 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6373 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6374 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6375 }
6376
6377 nested_vmx_succeed(vcpu);
6378 skip_emulated_instruction(vcpu);
6379 return 1;
6380}
6381
6382
6383static int handle_vmwrite(struct kvm_vcpu *vcpu)
6384{
6385 unsigned long field;
6386 gva_t gva;
6387 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6388 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6389 /* The value to write might be 32 or 64 bits, depending on L1's long
6390 * mode, and eventually we need to write that into a field of several
6391 * possible lengths. The code below first zero-extends the value to 64
6392 * bit (field_value), and then copies only the approriate number of
6393 * bits into the vmcs12 field.
6394 */
6395 u64 field_value = 0;
6396 struct x86_exception e;
6397
6398 if (!nested_vmx_check_permission(vcpu) ||
6399 !nested_vmx_check_vmcs12(vcpu))
6400 return 1;
6401
6402 if (vmx_instruction_info & (1u << 10))
6403 field_value = kvm_register_read(vcpu,
6404 (((vmx_instruction_info) >> 3) & 0xf));
6405 else {
6406 if (get_vmx_mem_address(vcpu, exit_qualification,
6407 vmx_instruction_info, &gva))
6408 return 1;
6409 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6410 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6411 kvm_inject_page_fault(vcpu, &e);
6412 return 1;
6413 }
6414 }
6415
6416
6417 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6418 if (vmcs_field_readonly(field)) {
6419 nested_vmx_failValid(vcpu,
6420 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6421 skip_emulated_instruction(vcpu);
6422 return 1;
6423 }
6424
20b97fea 6425 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6426 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6427 skip_emulated_instruction(vcpu);
6428 return 1;
6429 }
6430
6431 nested_vmx_succeed(vcpu);
6432 skip_emulated_instruction(vcpu);
6433 return 1;
6434}
6435
63846663
NHE		 6436/* Emulate the VMPTRLD instruction */
6437static int handle_vmptrld(struct kvm_vcpu *vcpu)
6438{
6439 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6440 gpa_t vmptr;
8a1b9dd0 6441 u32 exec_control;
63846663
NHE		 6442
6443 if (!nested_vmx_check_permission(vcpu))
6444 return 1;
6445
4291b588 6446 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6447 return 1;
96ec1463 6448
63846663
NHE		 6449 if (vmx->nested.current_vmptr != vmptr) {
6450 struct vmcs12 *new_vmcs12;
6451 struct page *page;
6452 page = nested_get_page(vcpu, vmptr);
6453 if (page == NULL) {
6454 nested_vmx_failInvalid(vcpu);
6455 skip_emulated_instruction(vcpu);
6456 return 1;
6457 }
6458 new_vmcs12 = kmap(page);
6459 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6460 kunmap(page);
6461 nested_release_page_clean(page);
6462 nested_vmx_failValid(vcpu,
6463 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6464 skip_emulated_instruction(vcpu);
6465 return 1;
6466 }
e7953d7f
AG		 6467 if (vmx->nested.current_vmptr != -1ull)
6468 nested_release_vmcs12(vmx);
63846663
NHE		 6469
6470 vmx->nested.current_vmptr = vmptr;
6471 vmx->nested.current_vmcs12 = new_vmcs12;
6472 vmx->nested.current_vmcs12_page = page;
012f83cb 6473 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6474 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6475 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6476 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6477 vmcs_write64(VMCS_LINK_POINTER,
6478 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6479 vmx->nested.sync_shadow_vmcs = true;
6480 }
63846663
NHE		 6481 }
6482
6483 nested_vmx_succeed(vcpu);
6484 skip_emulated_instruction(vcpu);
6485 return 1;
6486}
6487
6a4d7550
NHE		 6488/* Emulate the VMPTRST instruction */
6489static int handle_vmptrst(struct kvm_vcpu *vcpu)
6490{
6491 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6492 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6493 gva_t vmcs_gva;
6494 struct x86_exception e;
6495
6496 if (!nested_vmx_check_permission(vcpu))
6497 return 1;
6498
6499 if (get_vmx_mem_address(vcpu, exit_qualification,
6500 vmx_instruction_info, &vmcs_gva))
6501 return 1;
6502 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6503 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6504 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6505 sizeof(u64), &e)) {
6506 kvm_inject_page_fault(vcpu, &e);
6507 return 1;
6508 }
6509 nested_vmx_succeed(vcpu);
6510 skip_emulated_instruction(vcpu);
6511 return 1;
6512}
6513
bfd0a56b
NHE		 6514/* Emulate the INVEPT instruction */
6515static int handle_invept(struct kvm_vcpu *vcpu)
6516{
6517 u32 vmx_instruction_info, types;
6518 unsigned long type;
6519 gva_t gva;
6520 struct x86_exception e;
6521 struct {
6522 u64 eptp, gpa;
6523 } operand;
bfd0a56b
NHE		 6524
6525 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6526 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6527 kvm_queue_exception(vcpu, UD_VECTOR);
6528 return 1;
6529 }
6530
6531 if (!nested_vmx_check_permission(vcpu))
6532 return 1;
6533
6534 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6535 kvm_queue_exception(vcpu, UD_VECTOR);
6536 return 1;
6537 }
6538
6539 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6540 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6541
6542 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6543
6544 if (!(types & (1UL << type))) {
6545 nested_vmx_failValid(vcpu,
6546 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6547 return 1;
6548 }
6549
6550 /* According to the Intel VMX instruction reference, the memory
6551 * operand is read even if it isn't needed (e.g., for type==global)
6552 */
6553 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6554 vmx_instruction_info, &gva))
6555 return 1;
6556 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6557 sizeof(operand), &e)) {
6558 kvm_inject_page_fault(vcpu, &e);
6559 return 1;
6560 }
6561
6562 switch (type) {
bfd0a56b
NHE		 6563 case VMX_EPT_EXTENT_GLOBAL:
6564 kvm_mmu_sync_roots(vcpu);
6565 kvm_mmu_flush_tlb(vcpu);
6566 nested_vmx_succeed(vcpu);
6567 break;
6568 default:
4b855078 6569 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6570 BUG_ON(1);
6571 break;
6572 }
6573
6574 skip_emulated_instruction(vcpu);
6575 return 1;
6576}
6577
6aa8b732
AK		 6578/*
6579 * The exit handlers return 1 if the exit was handled fully and guest execution
6580 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6581 * to be done to userspace and return 0.
6582 */
772e0318 6583static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6584 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6585 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6586 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6587 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6588 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6589 [EXIT_REASON_CR_ACCESS] = handle_cr,
6590 [EXIT_REASON_DR_ACCESS] = handle_dr,
6591 [EXIT_REASON_CPUID] = handle_cpuid,
6592 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6593 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6594 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6595 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6596 [EXIT_REASON_INVD] = handle_invd,
a7052897 6597 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6598 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6599 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6600 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6601 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6602 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6603 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6604 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6605 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6606 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6607 [EXIT_REASON_VMOFF] = handle_vmoff,
6608 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6609 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6610 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6611 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6612 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6613 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6614 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6615 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6616 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6617 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6618 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6619 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6620 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6621 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6622 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6623};
6624
6625static const int kvm_vmx_max_exit_handlers =
50a3485c 6626 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6627
908a7bdd
JK		 6628static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6629 struct vmcs12 *vmcs12)
6630{
6631 unsigned long exit_qualification;
6632 gpa_t bitmap, last_bitmap;
6633 unsigned int port;
6634 int size;
6635 u8 b;
6636
908a7bdd 6637 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6638 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6639
6640 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6641
6642 port = exit_qualification >> 16;
6643 size = (exit_qualification & 7) + 1;
6644
6645 last_bitmap = (gpa_t)-1;
6646 b = -1;
6647
6648 while (size > 0) {
6649 if (port < 0x8000)
6650 bitmap = vmcs12->io_bitmap_a;
6651 else if (port < 0x10000)
6652 bitmap = vmcs12->io_bitmap_b;
6653 else
6654 return 1;
6655 bitmap += (port & 0x7fff) / 8;
6656
6657 if (last_bitmap != bitmap)
6658 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6659 return 1;
6660 if (b & (1 << (port & 7)))
6661 return 1;
6662
6663 port++;
6664 size--;
6665 last_bitmap = bitmap;
6666 }
6667
6668 return 0;
6669}
6670
644d711a
NHE		 6671/*
6672 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6673 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6674 * disinterest in the current event (read or write a specific MSR) by using an
6675 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6676 */
6677static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6678 struct vmcs12 *vmcs12, u32 exit_reason)
6679{
6680 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6681 gpa_t bitmap;
6682
cbd29cb6 6683 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6684 return 1;
6685
6686 /*
6687 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6688 * for the four combinations of read/write and low/high MSR numbers.
6689 * First we need to figure out which of the four to use:
6690 */
6691 bitmap = vmcs12->msr_bitmap;
6692 if (exit_reason == EXIT_REASON_MSR_WRITE)
6693 bitmap += 2048;
6694 if (msr_index >= 0xc0000000) {
6695 msr_index -= 0xc0000000;
6696 bitmap += 1024;
6697 }
6698
6699 /* Then read the msr_index'th bit from this bitmap: */
6700 if (msr_index < 1024*8) {
6701 unsigned char b;
bd31a7f5
JK		 6702 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6703 return 1;
644d711a
NHE		 6704 return 1 & (b >> (msr_index & 7));
6705 } else
6706 return 1; /* let L1 handle the wrong parameter */
6707}
6708
6709/*
6710 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6711 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6712 * intercept (via guest_host_mask etc.) the current event.
6713 */
6714static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6715 struct vmcs12 *vmcs12)
6716{
6717 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6718 int cr = exit_qualification & 15;
6719 int reg = (exit_qualification >> 8) & 15;
6720 unsigned long val = kvm_register_read(vcpu, reg);
6721
6722 switch ((exit_qualification >> 4) & 3) {
6723 case 0: /* mov to cr */
6724 switch (cr) {
6725 case 0:
6726 if (vmcs12->cr0_guest_host_mask &
6727 (val ^ vmcs12->cr0_read_shadow))
6728 return 1;
6729 break;
6730 case 3:
6731 if ((vmcs12->cr3_target_count >= 1 &&
6732 vmcs12->cr3_target_value0 == val) ||
6733 (vmcs12->cr3_target_count >= 2 &&
6734 vmcs12->cr3_target_value1 == val) ||
6735 (vmcs12->cr3_target_count >= 3 &&
6736 vmcs12->cr3_target_value2 == val) ||
6737 (vmcs12->cr3_target_count >= 4 &&
6738 vmcs12->cr3_target_value3 == val))
6739 return 0;
6740 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6741 return 1;
6742 break;
6743 case 4:
6744 if (vmcs12->cr4_guest_host_mask &
6745 (vmcs12->cr4_read_shadow ^ val))
6746 return 1;
6747 break;
6748 case 8:
6749 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6750 return 1;
6751 break;
6752 }
6753 break;
6754 case 2: /* clts */
6755 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6756 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6757 return 1;
6758 break;
6759 case 1: /* mov from cr */
6760 switch (cr) {
6761 case 3:
6762 if (vmcs12->cpu_based_vm_exec_control &
6763 CPU_BASED_CR3_STORE_EXITING)
6764 return 1;
6765 break;
6766 case 8:
6767 if (vmcs12->cpu_based_vm_exec_control &
6768 CPU_BASED_CR8_STORE_EXITING)
6769 return 1;
6770 break;
6771 }
6772 break;
6773 case 3: /* lmsw */
6774 /*
6775 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6776 * cr0. Other attempted changes are ignored, with no exit.
6777 */
6778 if (vmcs12->cr0_guest_host_mask & 0xe &
6779 (val ^ vmcs12->cr0_read_shadow))
6780 return 1;
6781 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6782 !(vmcs12->cr0_read_shadow & 0x1) &&
6783 (val & 0x1))
6784 return 1;
6785 break;
6786 }
6787 return 0;
6788}
6789
6790/*
6791 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6792 * should handle it ourselves in L0 (and then continue L2). Only call this
6793 * when in is_guest_mode (L2).
6794 */
6795static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6796{
644d711a
NHE		 6797 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6798 struct vcpu_vmx *vmx = to_vmx(vcpu);
6799 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6800 u32 exit_reason = vmx->exit_reason;
644d711a 6801
542060ea
JK		 6802 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6803 vmcs_readl(EXIT_QUALIFICATION),
6804 vmx->idt_vectoring_info,
6805 intr_info,
6806 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6807 KVM_ISA_VMX);
6808
644d711a
NHE		 6809 if (vmx->nested.nested_run_pending)
6810 return 0;
6811
6812 if (unlikely(vmx->fail)) {
bd80158a
JK		 6813 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6814 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6815 return 1;
6816 }
6817
6818 switch (exit_reason) {
6819 case EXIT_REASON_EXCEPTION_NMI:
6820 if (!is_exception(intr_info))
6821 return 0;
6822 else if (is_page_fault(intr_info))
6823 return enable_ept;
e504c909 6824 else if (is_no_device(intr_info) &&
ccf9844e 6825 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6826 return 0;
644d711a
NHE		 6827 return vmcs12->exception_bitmap &
6828 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6829 case EXIT_REASON_EXTERNAL_INTERRUPT:
6830 return 0;
6831 case EXIT_REASON_TRIPLE_FAULT:
6832 return 1;
6833 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6834 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6835 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6836 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6837 case EXIT_REASON_TASK_SWITCH:
6838 return 1;
6839 case EXIT_REASON_CPUID:
6840 return 1;
6841 case EXIT_REASON_HLT:
6842 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6843 case EXIT_REASON_INVD:
6844 return 1;
6845 case EXIT_REASON_INVLPG:
6846 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6847 case EXIT_REASON_RDPMC:
6848 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6849 case EXIT_REASON_RDTSC:
6850 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6851 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6852 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6853 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6854 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6855 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6856 case EXIT_REASON_INVEPT:
644d711a
NHE		 6857 /*
6858 * VMX instructions trap unconditionally. This allows L1 to
6859 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6860 */
6861 return 1;
6862 case EXIT_REASON_CR_ACCESS:
6863 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6864 case EXIT_REASON_DR_ACCESS:
6865 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6866 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6867 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6868 case EXIT_REASON_MSR_READ:
6869 case EXIT_REASON_MSR_WRITE:
6870 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6871 case EXIT_REASON_INVALID_STATE:
6872 return 1;
6873 case EXIT_REASON_MWAIT_INSTRUCTION:
6874 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6875 case EXIT_REASON_MONITOR_INSTRUCTION:
6876 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6877 case EXIT_REASON_PAUSE_INSTRUCTION:
6878 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6879 nested_cpu_has2(vmcs12,
6880 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6881 case EXIT_REASON_MCE_DURING_VMENTRY:
6882 return 0;
6883 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6884 return 1;
6885 case EXIT_REASON_APIC_ACCESS:
6886 return nested_cpu_has2(vmcs12,
6887 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6888 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6889 /*
6890 * L0 always deals with the EPT violation. If nested EPT is
6891 * used, and the nested mmu code discovers that the address is
6892 * missing in the guest EPT table (EPT12), the EPT violation
6893 * will be injected with nested_ept_inject_page_fault()
6894 */
6895 return 0;
644d711a 6896 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6897 /*
6898 * L2 never uses directly L1's EPT, but rather L0's own EPT
6899 * table (shadow on EPT) or a merged EPT table that L0 built
6900 * (EPT on EPT). So any problems with the structure of the
6901 * table is L0's fault.
6902 */
644d711a
NHE		 6903 return 0;
6904 case EXIT_REASON_WBINVD:
6905 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6906 case EXIT_REASON_XSETBV:
6907 return 1;
6908 default:
6909 return 1;
6910 }
6911}
6912
586f9607
AK		 6913static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6914{
6915 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6916 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6917}
6918
6aa8b732
AK		 6919/*
6920 * The guest has exited. See if we can fix it or if we need userspace
6921 * assistance.
6922 */
851ba692 6923static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6924{
29bd8a78 6925 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6926 u32 exit_reason = vmx->exit_reason;
1155f76a 6927 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6928
80ced186 6929 /* If guest state is invalid, start emulating */
14168786 6930 if (vmx->emulation_required)
80ced186 6931 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6932
644d711a 6933 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6934 nested_vmx_vmexit(vcpu, exit_reason,
6935 vmcs_read32(VM_EXIT_INTR_INFO),
6936 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6937 return 1;
6938 }
6939
5120702e
MG		 6940 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6941 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6942 vcpu->run->fail_entry.hardware_entry_failure_reason
6943 = exit_reason;
6944 return 0;
6945 }
6946
29bd8a78 6947 if (unlikely(vmx->fail)) {
851ba692
AK		 6948 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6949 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6950 = vmcs_read32(VM_INSTRUCTION_ERROR);
6951 return 0;
6952 }
6aa8b732 6953
b9bf6882
XG		 6954 /*
6955 * Note:
6956 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6957 * delivery event since it indicates guest is accessing MMIO.
6958 * The vm-exit can be triggered again after return to guest that
6959 * will cause infinite loop.
6960 */
d77c26fc 6961 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6962 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6963 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6964 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6965 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6966 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6967 vcpu->run->internal.ndata = 2;
6968 vcpu->run->internal.data[0] = vectoring_info;
6969 vcpu->run->internal.data[1] = exit_reason;
6970 return 0;
6971 }
3b86cd99 6972
644d711a
NHE		 6973 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6974 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6975 get_vmcs12(vcpu))))) {
c4282df9 6976 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6977 vmx->soft_vnmi_blocked = 0;
3b86cd99 6978 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6979 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6980 /*
6981 * This CPU don't support us in finding the end of an
6982 * NMI-blocked window if the guest runs with IRQs
6983 * disabled. So we pull the trigger after 1 s of
6984 * futile waiting, but inform the user about this.
6985 */
6986 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6987 "state on VCPU %d after 1 s timeout\n",
6988 __func__, vcpu->vcpu_id);
6989 vmx->soft_vnmi_blocked = 0;
3b86cd99 6990 }
3b86cd99
JK		 6991 }
6992
6aa8b732
AK		 6993 if (exit_reason < kvm_vmx_max_exit_handlers
6994 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6995 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6996 else {
851ba692
AK		 6997 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6998 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6999 }
7000 return 0;
7001}
7002
95ba8273 7003static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7004{
95ba8273 7005 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7006 vmcs_write32(TPR_THRESHOLD, 0);
7007 return;
7008 }
7009
95ba8273 7010 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7011}
7012
8d14695f
YZ		 7013static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7014{
7015 u32 sec_exec_control;
7016
7017 /*
7018 * There is not point to enable virtualize x2apic without enable
7019 * apicv
7020 */
c7c9c56c
YZ		 7021 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7022 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7023 return;
7024
7025 if (!vm_need_tpr_shadow(vcpu->kvm))
7026 return;
7027
7028 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7029
7030 if (set) {
7031 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7032 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7033 } else {
7034 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7035 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7036 }
7037 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7038
7039 vmx_set_msr_bitmap(vcpu);
7040}
7041
c7c9c56c
YZ		 7042static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7043{
7044 u16 status;
7045 u8 old;
7046
7047 if (!vmx_vm_has_apicv(kvm))
7048 return;
7049
7050 if (isr == -1)
7051 isr = 0;
7052
7053 status = vmcs_read16(GUEST_INTR_STATUS);
7054 old = status >> 8;
7055 if (isr != old) {
7056 status &= 0xff;
7057 status |= isr << 8;
7058 vmcs_write16(GUEST_INTR_STATUS, status);
7059 }
7060}
7061
7062static void vmx_set_rvi(int vector)
7063{
7064 u16 status;
7065 u8 old;
7066
7067 status = vmcs_read16(GUEST_INTR_STATUS);
7068 old = (u8)status & 0xff;
7069 if ((u8)vector != old) {
7070 status &= ~0xff;
7071 status |= (u8)vector;
7072 vmcs_write16(GUEST_INTR_STATUS, status);
7073 }
7074}
7075
7076static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7077{
7078 if (max_irr == -1)
7079 return;
7080
7081 vmx_set_rvi(max_irr);
7082}
7083
7084static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7085{
3d81bc7e
YZ		 7086 if (!vmx_vm_has_apicv(vcpu->kvm))
7087 return;
7088
c7c9c56c
YZ		 7089 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7090 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7091 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7092 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7093}
7094
51aa01d1 7095static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7096{
00eba012
AK		 7097 u32 exit_intr_info;
7098
7099 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7100 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7101 return;
7102
c5ca8e57 7103 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7104 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7105
7106 /* Handle machine checks before interrupts are enabled */
00eba012 7107 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7108 kvm_machine_check();
7109
20f65983 7110 /* We need to handle NMIs before interrupts are enabled */
00eba012 7111 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7112 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7113 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7114 asm("int $2");
ff9d07a0
ZY		 7115 kvm_after_handle_nmi(&vmx->vcpu);
7116 }
51aa01d1 7117}
20f65983 7118
a547c6db
YZ		 7119static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7120{
7121 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7122
7123 /*
7124 * If external interrupt exists, IF bit is set in rflags/eflags on the
7125 * interrupt stack frame, and interrupt will be enabled on a return
7126 * from interrupt handler.
7127 */
7128 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7129 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7130 unsigned int vector;
7131 unsigned long entry;
7132 gate_desc *desc;
7133 struct vcpu_vmx *vmx = to_vmx(vcpu);
7134#ifdef CONFIG_X86_64
7135 unsigned long tmp;
7136#endif
7137
7138 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7139 desc = (gate_desc *)vmx->host_idt_base + vector;
7140 entry = gate_offset(*desc);
7141 asm volatile(
7142#ifdef CONFIG_X86_64
7143 "mov %%" _ASM_SP ", %[sp]\n\t"
7144 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7145 "push $%c[ss]\n\t"
7146 "push %[sp]\n\t"
7147#endif
7148 "pushf\n\t"
7149 "orl $0x200, (%%" _ASM_SP ")\n\t"
7150 __ASM_SIZE(push) " $%c[cs]\n\t"
7151 "call *%[entry]\n\t"
7152 :
7153#ifdef CONFIG_X86_64
7154 [sp]"=&r"(tmp)
7155#endif
7156 :
7157 [entry]"r"(entry),
7158 [ss]"i"(__KERNEL_DS),
7159 [cs]"i"(__KERNEL_CS)
7160 );
7161 } else
7162 local_irq_enable();
7163}
7164
da8999d3
LJ		 7165static bool vmx_mpx_supported(void)
7166{
7167 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7168 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7169}
7170
51aa01d1
AK		 7171static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7172{
c5ca8e57 7173 u32 exit_intr_info;
51aa01d1
AK		 7174 bool unblock_nmi;
7175 u8 vector;
7176 bool idtv_info_valid;
7177
7178 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7179
cf393f75 7180 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7181 if (vmx->nmi_known_unmasked)
7182 return;
c5ca8e57
AK		 7183 /*
7184 * Can't use vmx->exit_intr_info since we're not sure what
7185 * the exit reason is.
7186 */
7187 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7188 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7189 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7190 /*
7b4a25cb 7191 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7192 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7193 * a guest IRET fault.
7b4a25cb
GN		 7194 * SDM 3: 23.2.2 (September 2008)
7195 * Bit 12 is undefined in any of the following cases:
7196 * If the VM exit sets the valid bit in the IDT-vectoring
7197 * information field.
7198 * If the VM exit is due to a double fault.
cf393f75 7199 */
7b4a25cb
GN		 7200 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7201 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7202 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7203 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7204 else
7205 vmx->nmi_known_unmasked =
7206 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7207 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7208 } else if (unlikely(vmx->soft_vnmi_blocked))
7209 vmx->vnmi_blocked_time +=
7210 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7211}
7212
3ab66e8a 7213static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7214 u32 idt_vectoring_info,
7215 int instr_len_field,
7216 int error_code_field)
51aa01d1 7217{
51aa01d1
AK		 7218 u8 vector;
7219 int type;
7220 bool idtv_info_valid;
7221
7222 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7223
3ab66e8a
JK		 7224 vcpu->arch.nmi_injected = false;
7225 kvm_clear_exception_queue(vcpu);
7226 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7227
7228 if (!idtv_info_valid)
7229 return;
7230
3ab66e8a 7231 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7232
668f612f
AK		 7233 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7234 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7235
64a7ec06 7236 switch (type) {
37b96e98 7237 case INTR_TYPE_NMI_INTR:
3ab66e8a 7238 vcpu->arch.nmi_injected = true;
668f612f 7239 /*
7b4a25cb 7240 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7241 * Clear bit "block by NMI" before VM entry if a NMI
7242 * delivery faulted.
668f612f 7243 */
3ab66e8a 7244 vmx_set_nmi_mask(vcpu, false);
37b96e98 7245 break;
37b96e98 7246 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7247 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7248 /* fall through */
7249 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7250 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7251 u32 err = vmcs_read32(error_code_field);
851eb667 7252 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7253 } else
851eb667 7254 kvm_requeue_exception(vcpu, vector);
37b96e98 7255 break;
66fd3f7f 7256 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7257 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7258 /* fall through */
37b96e98 7259 case INTR_TYPE_EXT_INTR:
3ab66e8a 7260 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7261 break;
7262 default:
7263 break;
f7d9238f 7264 }
cf393f75
AK		 7265}
7266
83422e17
AK		 7267static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7268{
3ab66e8a 7269 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7270 VM_EXIT_INSTRUCTION_LEN,
7271 IDT_VECTORING_ERROR_CODE);
7272}
7273
b463a6f7
AK		 7274static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7275{
3ab66e8a 7276 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7277 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7278 VM_ENTRY_INSTRUCTION_LEN,
7279 VM_ENTRY_EXCEPTION_ERROR_CODE);
7280
7281 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7282}
7283
d7cd9796
GN		 7284static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7285{
7286 int i, nr_msrs;
7287 struct perf_guest_switch_msr *msrs;
7288
7289 msrs = perf_guest_get_msrs(&nr_msrs);
7290
7291 if (!msrs)
7292 return;
7293
7294 for (i = 0; i < nr_msrs; i++)
7295 if (msrs[i].host == msrs[i].guest)
7296 clear_atomic_switch_msr(vmx, msrs[i].msr);
7297 else
7298 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7299 msrs[i].host);
7300}
7301
a3b5ba49 7302static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7303{
a2fa3e9f 7304 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7305 unsigned long debugctlmsr;
104f226b
AK		 7306
7307 /* Record the guest's net vcpu time for enforced NMI injections. */
7308 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7309 vmx->entry_time = ktime_get();
7310
7311 /* Don't enter VMX if guest state is invalid, let the exit handler
7312 start emulation until we arrive back to a valid state */
14168786 7313 if (vmx->emulation_required)
104f226b
AK		 7314 return;
7315
012f83cb
AG		 7316 if (vmx->nested.sync_shadow_vmcs) {
7317 copy_vmcs12_to_shadow(vmx);
7318 vmx->nested.sync_shadow_vmcs = false;
7319 }
7320
104f226b
AK		 7321 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7322 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7323 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7324 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7325
7326 /* When single-stepping over STI and MOV SS, we must clear the
7327 * corresponding interruptibility bits in the guest state. Otherwise
7328 * vmentry fails as it then expects bit 14 (BS) in pending debug
7329 * exceptions being set, but that's not correct for the guest debugging
7330 * case. */
7331 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7332 vmx_set_interrupt_shadow(vcpu, 0);
7333
d7cd9796 7334 atomic_switch_perf_msrs(vmx);
2a7921b7 7335 debugctlmsr = get_debugctlmsr();
d7cd9796 7336
d462b819 7337 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7338 asm(
6aa8b732 7339 /* Store host registers */
b188c81f
AK		 7340 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7341 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7342 "push %%" _ASM_CX " \n\t"
7343 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7344 "je 1f \n\t"
b188c81f 7345 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7346 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7347 "1: \n\t"
d3edefc0 7348 /* Reload cr2 if changed */
b188c81f
AK		 7349 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7350 "mov %%cr2, %%" _ASM_DX " \n\t"
7351 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7352 "je 2f \n\t"
b188c81f 7353 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7354 "2: \n\t"
6aa8b732 7355 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7356 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7357 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7358 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7359 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7360 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7361 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7362 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7363 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7364#ifdef CONFIG_X86_64
e08aa78a
AK		 7365 "mov %c[r8](%0), %%r8 \n\t"
7366 "mov %c[r9](%0), %%r9 \n\t"
7367 "mov %c[r10](%0), %%r10 \n\t"
7368 "mov %c[r11](%0), %%r11 \n\t"
7369 "mov %c[r12](%0), %%r12 \n\t"
7370 "mov %c[r13](%0), %%r13 \n\t"
7371 "mov %c[r14](%0), %%r14 \n\t"
7372 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7373#endif
b188c81f 7374 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7375
6aa8b732 7376 /* Enter guest mode */
83287ea4 7377 "jne 1f \n\t"
4ecac3fd 7378 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7379 "jmp 2f \n\t"
7380 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7381 "2: "
6aa8b732 7382 /* Save guest registers, load host registers, keep flags */
b188c81f 7383 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7384 "pop %0 \n\t"
b188c81f
AK		 7385 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7386 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7387 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7388 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7389 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7390 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7391 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7392#ifdef CONFIG_X86_64
e08aa78a
AK		 7393 "mov %%r8, %c[r8](%0) \n\t"
7394 "mov %%r9, %c[r9](%0) \n\t"
7395 "mov %%r10, %c[r10](%0) \n\t"
7396 "mov %%r11, %c[r11](%0) \n\t"
7397 "mov %%r12, %c[r12](%0) \n\t"
7398 "mov %%r13, %c[r13](%0) \n\t"
7399 "mov %%r14, %c[r14](%0) \n\t"
7400 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7401#endif
b188c81f
AK		 7402 "mov %%cr2, %%" _ASM_AX " \n\t"
7403 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7404
b188c81f 7405 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7406 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7407 ".pushsection .rodata \n\t"
7408 ".global vmx_return \n\t"
7409 "vmx_return: " _ASM_PTR " 2b \n\t"
7410 ".popsection"
e08aa78a 7411 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7412 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7413 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7414 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7415 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7416 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7417 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7418 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7419 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7420 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7421 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7422#ifdef CONFIG_X86_64
ad312c7c
ZX		 7423 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7424 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7425 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7426 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7427 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7428 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7429 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7430 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7431#endif
40712fae
AK		 7432 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7433 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7434 : "cc", "memory"
7435#ifdef CONFIG_X86_64
b188c81f 7436 , "rax", "rbx", "rdi", "rsi"
c2036300 7437 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7438#else
7439 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7440#endif
7441 );
6aa8b732 7442
2a7921b7
GN		 7443 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7444 if (debugctlmsr)
7445 update_debugctlmsr(debugctlmsr);
7446
aa67f609
AK		 7447#ifndef CONFIG_X86_64
7448 /*
7449 * The sysexit path does not restore ds/es, so we must set them to
7450 * a reasonable value ourselves.
7451 *
7452 * We can't defer this to vmx_load_host_state() since that function
7453 * may be executed in interrupt context, which saves and restore segments
7454 * around it, nullifying its effect.
7455 */
7456 loadsegment(ds, __USER_DS);
7457 loadsegment(es, __USER_DS);
7458#endif
7459
6de4f3ad 7460 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7461 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7462 | (1 << VCPU_EXREG_CPL)
aff48baa 7463 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7464 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7465 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7466 vcpu->arch.regs_dirty = 0;
7467
1155f76a
AK		 7468 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7469
d462b819 7470 vmx->loaded_vmcs->launched = 1;
1b6269db 7471
51aa01d1 7472 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7473 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7474
e0b890d3
GN		 7475 /*
7476 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7477 * we did not inject a still-pending event to L1 now because of
7478 * nested_run_pending, we need to re-enable this bit.
7479 */
7480 if (vmx->nested.nested_run_pending)
7481 kvm_make_request(KVM_REQ_EVENT, vcpu);
7482
7483 vmx->nested.nested_run_pending = 0;
7484
51aa01d1
AK		 7485 vmx_complete_atomic_exit(vmx);
7486 vmx_recover_nmi_blocking(vmx);
cf393f75 7487 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7488}
7489
6aa8b732
AK		 7490static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7491{
fb3f0f51
RR		 7492 struct vcpu_vmx *vmx = to_vmx(vcpu);
7493
cdbecfc3 7494 free_vpid(vmx);
d462b819 7495 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7496 free_nested(vmx);
fb3f0f51
RR		 7497 kfree(vmx->guest_msrs);
7498 kvm_vcpu_uninit(vcpu);
a4770347 7499 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7500}
7501
fb3f0f51 7502static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7503{
fb3f0f51 7504 int err;
c16f862d 7505 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7506 int cpu;
6aa8b732 7507
a2fa3e9f 7508 if (!vmx)
fb3f0f51
RR		 7509 return ERR_PTR(-ENOMEM);
7510
2384d2b3
SY		 7511 allocate_vpid(vmx);
7512
fb3f0f51
RR		 7513 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7514 if (err)
7515 goto free_vcpu;
965b58a5 7516
a2fa3e9f 7517 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7518 err = -ENOMEM;
fb3f0f51 7519 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7520 goto uninit_vcpu;
7521 }
965b58a5 7522
d462b819
NHE		 7523 vmx->loaded_vmcs = &vmx->vmcs01;
7524 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7525 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7526 goto free_msrs;
d462b819
NHE		 7527 if (!vmm_exclusive)
7528 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7529 loaded_vmcs_init(vmx->loaded_vmcs);
7530 if (!vmm_exclusive)
7531 kvm_cpu_vmxoff();
a2fa3e9f 7532
15ad7146
AK		 7533 cpu = get_cpu();
7534 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7535 vmx->vcpu.cpu = cpu;
8b9cf98c 7536 err = vmx_vcpu_setup(vmx);
fb3f0f51 7537 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7538 put_cpu();
fb3f0f51
RR		 7539 if (err)
7540 goto free_vmcs;
a63cb560 7541 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7542 err = alloc_apic_access_page(kvm);
7543 if (err)
5e4a0b3c 7544 goto free_vmcs;
a63cb560 7545 }
fb3f0f51 7546
b927a3ce
SY		 7547 if (enable_ept) {
7548 if (!kvm->arch.ept_identity_map_addr)
7549 kvm->arch.ept_identity_map_addr =
7550 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7551 err = -ENOMEM;
b7ebfb05
SY		 7552 if (alloc_identity_pagetable(kvm) != 0)
7553 goto free_vmcs;
93ea5388
GN		 7554 if (!init_rmode_identity_map(kvm))
7555 goto free_vmcs;
b927a3ce 7556 }
b7ebfb05 7557
a9d30f33
NHE		 7558 vmx->nested.current_vmptr = -1ull;
7559 vmx->nested.current_vmcs12 = NULL;
7560
fb3f0f51
RR		 7561 return &vmx->vcpu;
7562
7563free_vmcs:
5f3fbc34 7564 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7565free_msrs:
fb3f0f51
RR		 7566 kfree(vmx->guest_msrs);
7567uninit_vcpu:
7568 kvm_vcpu_uninit(&vmx->vcpu);
7569free_vcpu:
cdbecfc3 7570 free_vpid(vmx);
a4770347 7571 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7572 return ERR_PTR(err);
6aa8b732
AK		 7573}
7574
002c7f7c
YS		 7575static void __init vmx_check_processor_compat(void *rtn)
7576{
7577 struct vmcs_config vmcs_conf;
7578
7579 *(int *)rtn = 0;
7580 if (setup_vmcs_config(&vmcs_conf) < 0)
7581 *(int *)rtn = -EIO;
7582 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7583 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7584 smp_processor_id());
7585 *(int *)rtn = -EIO;
7586 }
7587}
7588
67253af5
SY		 7589static int get_ept_level(void)
7590{
7591 return VMX_EPT_DEFAULT_GAW + 1;
7592}
7593
4b12f0de 7594static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7595{
4b12f0de
SY		 7596 u64 ret;
7597
522c68c4
SY		 7598 /* For VT-d and EPT combination
7599 * 1. MMIO: always map as UC
7600 * 2. EPT with VT-d:
7601 * a. VT-d without snooping control feature: can't guarantee the
7602 * result, try to trust guest.
7603 * b. VT-d with snooping control feature: snooping control feature of
7604 * VT-d engine can guarantee the cache correctness. Just set it
7605 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7606 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7607 * consistent with host MTRR
7608 */
4b12f0de
SY		 7609 if (is_mmio)
7610 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7611 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7612 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7613 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7614 else
522c68c4 7615 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7616 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7617
7618 return ret;
64d4d521
SY		 7619}
7620
17cc3935 7621static int vmx_get_lpage_level(void)
344f414f 7622{
878403b7
SY		 7623 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7624 return PT_DIRECTORY_LEVEL;
7625 else
7626 /* For shadow and EPT supported 1GB page */
7627 return PT_PDPE_LEVEL;
344f414f
JR		 7628}
7629
0e851880
SY		 7630static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7631{
4e47c7a6
SY		 7632 struct kvm_cpuid_entry2 *best;
7633 struct vcpu_vmx *vmx = to_vmx(vcpu);
7634 u32 exec_control;
7635
7636 vmx->rdtscp_enabled = false;
7637 if (vmx_rdtscp_supported()) {
7638 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7639 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7640 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7641 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7642 vmx->rdtscp_enabled = true;
7643 else {
7644 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7645 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7646 exec_control);
7647 }
7648 }
7649 }
ad756a16 7650
ad756a16
MJ		 7651 /* Exposing INVPCID only when PCID is exposed */
7652 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7653 if (vmx_invpcid_supported() &&
4f977045 7654 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7655 guest_cpuid_has_pcid(vcpu)) {
29282fde 7656 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7657 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7658 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7659 exec_control);
7660 } else {
29282fde
TI		 7661 if (cpu_has_secondary_exec_ctrls()) {
7662 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7663 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7664 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7665 exec_control);
7666 }
ad756a16 7667 if (best)
4f977045 7668 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7669 }
0e851880
SY		 7670}
7671
d4330ef2
JR		 7672static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7673{
7b8050f5
NHE		 7674 if (func == 1 && nested)
7675 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7676}
7677
25d92081
YZ		 7678static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7679 struct x86_exception *fault)
7680{
533558bc
JK		 7681 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7682 u32 exit_reason;
25d92081
YZ		 7683
7684 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7685 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7686 else
533558bc
JK		 7687 exit_reason = EXIT_REASON_EPT_VIOLATION;
7688 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7689 vmcs12->guest_physical_address = fault->address;
7690}
7691
155a97a3
NHE		 7692/* Callbacks for nested_ept_init_mmu_context: */
7693
7694static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7695{
7696 /* return the page table to be shadowed - in our case, EPT12 */
7697 return get_vmcs12(vcpu)->ept_pointer;
7698}
7699
8a3c1a33 7700static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7701{
8a3c1a33 7702 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7703 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7704
7705 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7706 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7707 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7708
7709 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7710}
7711
7712static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7713{
7714 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7715}
7716
feaf0c7d
GN		 7717static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7718 struct x86_exception *fault)
7719{
7720 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7721
7722 WARN_ON(!is_guest_mode(vcpu));
7723
7724 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7725 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7726 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7727 vmcs_read32(VM_EXIT_INTR_INFO),
7728 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7729 else
7730 kvm_inject_page_fault(vcpu, fault);
7731}
7732
f4124500
JK		 7733static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7734{
7735 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7736 struct vcpu_vmx *vmx = to_vmx(vcpu);
7737
7738 if (vcpu->arch.virtual_tsc_khz == 0)
7739 return;
7740
7741 /* Make sure short timeouts reliably trigger an immediate vmexit.
7742 * hrtimer_start does not guarantee this. */
7743 if (preemption_timeout <= 1) {
7744 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7745 return;
7746 }
7747
7748 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7749 preemption_timeout *= 1000000;
7750 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7751 hrtimer_start(&vmx->nested.preemption_timer,
7752 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7753}
7754
fe3ef05c
NHE		 7755/*
7756 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7757 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7758 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7759 * guest in a way that will both be appropriate to L1's requests, and our
7760 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7761 * function also has additional necessary side-effects, like setting various
7762 * vcpu->arch fields.
7763 */
7764static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7765{
7766 struct vcpu_vmx *vmx = to_vmx(vcpu);
7767 u32 exec_control;
7768
7769 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7770 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7771 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7772 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7773 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7774 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7775 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7776 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7777 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7778 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7779 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7780 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7781 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7782 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7783 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7784 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7785 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7786 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7787 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7788 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7789 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7790 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7791 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7792 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7793 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7794 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7795 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7796 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7797 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7798 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7799 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7800 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7801 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7802 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7803 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7804 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7805
7806 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7807 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7808 vmcs12->vm_entry_intr_info_field);
7809 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7810 vmcs12->vm_entry_exception_error_code);
7811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7812 vmcs12->vm_entry_instruction_len);
7813 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7814 vmcs12->guest_interruptibility_info);
fe3ef05c 7815 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7816 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7817 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7818 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7819 vmcs12->guest_pending_dbg_exceptions);
7820 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7821 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7822
7823 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7824
f4124500
JK		 7825 exec_control = vmcs12->pin_based_vm_exec_control;
7826 exec_control |= vmcs_config.pin_based_exec_ctrl;
7827 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7828 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7829
f4124500
JK		 7830 vmx->nested.preemption_timer_expired = false;
7831 if (nested_cpu_has_preemption_timer(vmcs12))
7832 vmx_start_preemption_timer(vcpu);
0238ea91 7833
fe3ef05c
NHE		 7834 /*
7835 * Whether page-faults are trapped is determined by a combination of
7836 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7837 * If enable_ept, L0 doesn't care about page faults and we should
7838 * set all of these to L1's desires. However, if !enable_ept, L0 does
7839 * care about (at least some) page faults, and because it is not easy
7840 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7841 * to exit on each and every L2 page fault. This is done by setting
7842 * MASK=MATCH=0 and (see below) EB.PF=1.
7843 * Note that below we don't need special code to set EB.PF beyond the
7844 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7845 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7846 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7847 *
7848 * A problem with this approach (when !enable_ept) is that L1 may be
7849 * injected with more page faults than it asked for. This could have
7850 * caused problems, but in practice existing hypervisors don't care.
7851 * To fix this, we will need to emulate the PFEC checking (on the L1
7852 * page tables), using walk_addr(), when injecting PFs to L1.
7853 */
7854 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7855 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7856 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7857 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7858
7859 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7860 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7861 if (!vmx->rdtscp_enabled)
7862 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7863 /* Take the following fields only from vmcs12 */
7864 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7865 if (nested_cpu_has(vmcs12,
7866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7867 exec_control |= vmcs12->secondary_vm_exec_control;
7868
7869 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7870 /*
7871 * Translate L1 physical address to host physical
7872 * address for vmcs02. Keep the page pinned, so this
7873 * physical address remains valid. We keep a reference
7874 * to it so we can release it later.
7875 */
7876 if (vmx->nested.apic_access_page) /* shouldn't happen */
7877 nested_release_page(vmx->nested.apic_access_page);
7878 vmx->nested.apic_access_page =
7879 nested_get_page(vcpu, vmcs12->apic_access_addr);
7880 /*
7881 * If translation failed, no matter: This feature asks
7882 * to exit when accessing the given address, and if it
7883 * can never be accessed, this feature won't do
7884 * anything anyway.
7885 */
7886 if (!vmx->nested.apic_access_page)
7887 exec_control &=
7888 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7889 else
7890 vmcs_write64(APIC_ACCESS_ADDR,
7891 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7892 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7893 exec_control |=
7894 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7895 vmcs_write64(APIC_ACCESS_ADDR,
7896 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7897 }
7898
7899 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7900 }
7901
7902
7903 /*
7904 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7905 * Some constant fields are set here by vmx_set_constant_host_state().
7906 * Other fields are different per CPU, and will be set later when
7907 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7908 */
a547c6db 7909 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7910
7911 /*
7912 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7913 * entry, but only if the current (host) sp changed from the value
7914 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7915 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7916 * here we just force the write to happen on entry.
7917 */
7918 vmx->host_rsp = 0;
7919
7920 exec_control = vmx_exec_control(vmx); /* L0's desires */
7921 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7922 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7923 exec_control &= ~CPU_BASED_TPR_SHADOW;
7924 exec_control |= vmcs12->cpu_based_vm_exec_control;
7925 /*
7926 * Merging of IO and MSR bitmaps not currently supported.
7927 * Rather, exit every time.
7928 */
7929 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7930 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7931 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7932
7933 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7934
7935 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7936 * bitwise-or of what L1 wants to trap for L2, and what we want to
7937 * trap. Note that CR0.TS also needs updating - we do this later.
7938 */
7939 update_exception_bitmap(vcpu);
7940 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7941 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7942
8049d651
NHE		 7943 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7944 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7945 * bits are further modified by vmx_set_efer() below.
7946 */
f4124500 7947 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7948
7949 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7950 * emulated by vmx_set_efer(), below.
7951 */
2961e876 7952 vm_entry_controls_init(vmx,
8049d651
NHE		 7953 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7954 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7955 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7956
44811c02 7957 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7958 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7959 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7960 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7961 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7962
7963
7964 set_cr4_guest_host_mask(vmx);
7965
36be0b9d
PB		 7966 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
7967 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
7968
27fc51b2
NHE		 7969 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7970 vmcs_write64(TSC_OFFSET,
7971 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7972 else
7973 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7974
7975 if (enable_vpid) {
7976 /*
7977 * Trivially support vpid by letting L2s share their parent
7978 * L1's vpid. TODO: move to a more elaborate solution, giving
7979 * each L2 its own vpid and exposing the vpid feature to L1.
7980 */
7981 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7982 vmx_flush_tlb(vcpu);
7983 }
7984
155a97a3
NHE		 7985 if (nested_cpu_has_ept(vmcs12)) {
7986 kvm_mmu_unload(vcpu);
7987 nested_ept_init_mmu_context(vcpu);
7988 }
7989
fe3ef05c
NHE		 7990 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7991 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7992 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7993 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7994 else
7995 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7996 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7997 vmx_set_efer(vcpu, vcpu->arch.efer);
7998
7999 /*
8000 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8001 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8002 * The CR0_READ_SHADOW is what L2 should have expected to read given
8003 * the specifications by L1; It's not enough to take
8004 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8005 * have more bits than L1 expected.
8006 */
8007 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8008 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8009
8010 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8011 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8012
8013 /* shadow page tables on either EPT or shadow page tables */
8014 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8015 kvm_mmu_reset_context(vcpu);
8016
feaf0c7d
GN		 8017 if (!enable_ept)
8018 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8019
3633cfc3
NHE		 8020 /*
8021 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8022 */
8023 if (enable_ept) {
8024 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8025 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8026 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8027 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8028 }
8029
fe3ef05c
NHE		 8030 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8031 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8032}
8033
cd232ad0
NHE		 8034/*
8035 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8036 * for running an L2 nested guest.
8037 */
8038static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8039{
8040 struct vmcs12 *vmcs12;
8041 struct vcpu_vmx *vmx = to_vmx(vcpu);
8042 int cpu;
8043 struct loaded_vmcs *vmcs02;
384bb783 8044 bool ia32e;
cd232ad0
NHE		 8045
8046 if (!nested_vmx_check_permission(vcpu) ||
8047 !nested_vmx_check_vmcs12(vcpu))
8048 return 1;
8049
8050 skip_emulated_instruction(vcpu);
8051 vmcs12 = get_vmcs12(vcpu);
8052
012f83cb
AG		 8053 if (enable_shadow_vmcs)
8054 copy_shadow_to_vmcs12(vmx);
8055
7c177938
NHE		 8056 /*
8057 * The nested entry process starts with enforcing various prerequisites
8058 * on vmcs12 as required by the Intel SDM, and act appropriately when
8059 * they fail: As the SDM explains, some conditions should cause the
8060 * instruction to fail, while others will cause the instruction to seem
8061 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8062 * To speed up the normal (success) code path, we should avoid checking
8063 * for misconfigurations which will anyway be caught by the processor
8064 * when using the merged vmcs02.
8065 */
8066 if (vmcs12->launch_state == launch) {
8067 nested_vmx_failValid(vcpu,
8068 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8069 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8070 return 1;
8071 }
8072
6dfacadd
JK		 8073 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8074 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8075 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8076 return 1;
8077 }
8078
7c177938
NHE		 8079 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
8080 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
8081 /*TODO: Also verify bits beyond physical address width are 0*/
8082 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8083 return 1;
8084 }
8085
8086 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
8087 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
8088 /*TODO: Also verify bits beyond physical address width are 0*/
8089 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8090 return 1;
8091 }
8092
8093 if (vmcs12->vm_entry_msr_load_count > 0 ||
8094 vmcs12->vm_exit_msr_load_count > 0 ||
8095 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8096 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8097 __func__);
7c177938
NHE		 8098 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8099 return 1;
8100 }
8101
8102 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8103 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8104 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8105 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8106 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8107 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8108 !vmx_control_verify(vmcs12->vm_exit_controls,
8109 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8110 !vmx_control_verify(vmcs12->vm_entry_controls,
8111 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8112 {
8113 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8114 return 1;
8115 }
8116
8117 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8118 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8119 nested_vmx_failValid(vcpu,
8120 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8121 return 1;
8122 }
8123
92fbc7b1 8124 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8125 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8126 nested_vmx_entry_failure(vcpu, vmcs12,
8127 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8128 return 1;
8129 }
8130 if (vmcs12->vmcs_link_pointer != -1ull) {
8131 nested_vmx_entry_failure(vcpu, vmcs12,
8132 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8133 return 1;
8134 }
8135
384bb783 8136 /*
cb0c8cda 8137 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8138 * are performed on the field for the IA32_EFER MSR:
8139 * - Bits reserved in the IA32_EFER MSR must be 0.
8140 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8141 * the IA-32e mode guest VM-exit control. It must also be identical
8142 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8143 * CR0.PG) is 1.
8144 */
8145 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8146 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8147 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8148 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8149 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8150 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8151 nested_vmx_entry_failure(vcpu, vmcs12,
8152 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8153 return 1;
8154 }
8155 }
8156
8157 /*
8158 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8159 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8160 * the values of the LMA and LME bits in the field must each be that of
8161 * the host address-space size VM-exit control.
8162 */
8163 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8164 ia32e = (vmcs12->vm_exit_controls &
8165 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8166 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8167 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8168 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8169 nested_vmx_entry_failure(vcpu, vmcs12,
8170 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8171 return 1;
8172 }
8173 }
8174
7c177938
NHE		 8175 /*
8176 * We're finally done with prerequisite checking, and can start with
8177 * the nested entry.
8178 */
8179
cd232ad0
NHE		 8180 vmcs02 = nested_get_current_vmcs02(vmx);
8181 if (!vmcs02)
8182 return -ENOMEM;
8183
8184 enter_guest_mode(vcpu);
8185
8186 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8187
8188 cpu = get_cpu();
8189 vmx->loaded_vmcs = vmcs02;
8190 vmx_vcpu_put(vcpu);
8191 vmx_vcpu_load(vcpu, cpu);
8192 vcpu->cpu = cpu;
8193 put_cpu();
8194
36c3cc42
JK		 8195 vmx_segment_cache_clear(vmx);
8196
cd232ad0
NHE		 8197 vmcs12->launch_state = 1;
8198
8199 prepare_vmcs02(vcpu, vmcs12);
8200
6dfacadd
JK		 8201 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8202 return kvm_emulate_halt(vcpu);
8203
7af40ad3
JK		 8204 vmx->nested.nested_run_pending = 1;
8205
cd232ad0
NHE		 8206 /*
8207 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8208 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8209 * returned as far as L1 is concerned. It will only return (and set
8210 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8211 */
8212 return 1;
8213}
8214
4704d0be
NHE		 8215/*
8216 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8217 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8218 * This function returns the new value we should put in vmcs12.guest_cr0.
8219 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8220 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8221 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8222 * didn't trap the bit, because if L1 did, so would L0).
8223 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8224 * been modified by L2, and L1 knows it. So just leave the old value of
8225 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8226 * isn't relevant, because if L0 traps this bit it can set it to anything.
8227 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8228 * changed these bits, and therefore they need to be updated, but L0
8229 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8230 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8231 */
8232static inline unsigned long
8233vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8234{
8235 return
8236 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8237 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8238 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8239 vcpu->arch.cr0_guest_owned_bits));
8240}
8241
8242static inline unsigned long
8243vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8244{
8245 return
8246 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8247 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8248 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8249 vcpu->arch.cr4_guest_owned_bits));
8250}
8251
5f3d5799
JK		 8252static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8253 struct vmcs12 *vmcs12)
8254{
8255 u32 idt_vectoring;
8256 unsigned int nr;
8257
851eb667 8258 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8259 nr = vcpu->arch.exception.nr;
8260 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8261
8262 if (kvm_exception_is_soft(nr)) {
8263 vmcs12->vm_exit_instruction_len =
8264 vcpu->arch.event_exit_inst_len;
8265 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8266 } else
8267 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8268
8269 if (vcpu->arch.exception.has_error_code) {
8270 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8271 vmcs12->idt_vectoring_error_code =
8272 vcpu->arch.exception.error_code;
8273 }
8274
8275 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8276 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8277 vmcs12->idt_vectoring_info_field =
8278 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8279 } else if (vcpu->arch.interrupt.pending) {
8280 nr = vcpu->arch.interrupt.nr;
8281 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8282
8283 if (vcpu->arch.interrupt.soft) {
8284 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8285 vmcs12->vm_entry_instruction_len =
8286 vcpu->arch.event_exit_inst_len;
8287 } else
8288 idt_vectoring |= INTR_TYPE_EXT_INTR;
8289
8290 vmcs12->idt_vectoring_info_field = idt_vectoring;
8291 }
8292}
8293
b6b8a145
JK		 8294static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8295{
8296 struct vcpu_vmx *vmx = to_vmx(vcpu);
8297
f4124500
JK		 8298 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8299 vmx->nested.preemption_timer_expired) {
8300 if (vmx->nested.nested_run_pending)
8301 return -EBUSY;
8302 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8303 return 0;
8304 }
8305
b6b8a145 8306 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8307 if (vmx->nested.nested_run_pending ||
8308 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8309 return -EBUSY;
8310 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8311 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8312 INTR_INFO_VALID_MASK, 0);
8313 /*
8314 * The NMI-triggered VM exit counts as injection:
8315 * clear this one and block further NMIs.
8316 */
8317 vcpu->arch.nmi_pending = 0;
8318 vmx_set_nmi_mask(vcpu, true);
8319 return 0;
8320 }
8321
8322 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8323 nested_exit_on_intr(vcpu)) {
8324 if (vmx->nested.nested_run_pending)
8325 return -EBUSY;
8326 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8327 }
8328
8329 return 0;
8330}
8331
f4124500
JK		 8332static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8333{
8334 ktime_t remaining =
8335 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8336 u64 value;
8337
8338 if (ktime_to_ns(remaining) <= 0)
8339 return 0;
8340
8341 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8342 do_div(value, 1000000);
8343 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8344}
8345
4704d0be
NHE		 8346/*
8347 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8348 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8349 * and this function updates it to reflect the changes to the guest state while
8350 * L2 was running (and perhaps made some exits which were handled directly by L0
8351 * without going back to L1), and to reflect the exit reason.
8352 * Note that we do not have to copy here all VMCS fields, just those that
8353 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8354 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8355 * which already writes to vmcs12 directly.
8356 */
533558bc
JK		 8357static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8358 u32 exit_reason, u32 exit_intr_info,
8359 unsigned long exit_qualification)
4704d0be
NHE		 8360{
8361 /* update guest state fields: */
8362 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8363 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8364
8365 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8366 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8367 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8368 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8369
8370 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8371 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8372 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8373 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8374 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8375 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8376 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8377 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8378 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8379 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8380 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8381 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8382 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8383 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8384 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8385 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8386 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8387 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8388 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8389 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8390 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8391 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8392 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8393 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8394 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8395 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8396 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8397 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8398 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8399 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8400 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8401 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8402 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8403 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8404 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8405 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8406
4704d0be
NHE		 8407 vmcs12->guest_interruptibility_info =
8408 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8409 vmcs12->guest_pending_dbg_exceptions =
8410 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8411 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8412 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8413 else
8414 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8415
f4124500
JK		 8416 if (nested_cpu_has_preemption_timer(vmcs12)) {
8417 if (vmcs12->vm_exit_controls &
8418 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8419 vmcs12->vmx_preemption_timer_value =
8420 vmx_get_preemption_timer_value(vcpu);
8421 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8422 }
7854cbca 8423
3633cfc3
NHE		 8424 /*
8425 * In some cases (usually, nested EPT), L2 is allowed to change its
8426 * own CR3 without exiting. If it has changed it, we must keep it.
8427 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8428 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8429 *
8430 * Additionally, restore L2's PDPTR to vmcs12.
8431 */
8432 if (enable_ept) {
8433 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8434 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8435 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8436 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8437 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8438 }
8439
c18911a2
JK		 8440 vmcs12->vm_entry_controls =
8441 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8442 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8443
4704d0be
NHE		 8444 /* TODO: These cannot have changed unless we have MSR bitmaps and
8445 * the relevant bit asks not to trap the change */
8446 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8447 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8448 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8449 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8450 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8451 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8452 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8453 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8454 if (vmx_mpx_supported())
8455 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8456
8457 /* update exit information fields: */
8458
533558bc
JK		 8459 vmcs12->vm_exit_reason = exit_reason;
8460 vmcs12->exit_qualification = exit_qualification;
4704d0be 8461
533558bc 8462 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8463 if ((vmcs12->vm_exit_intr_info &
8464 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8465 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8466 vmcs12->vm_exit_intr_error_code =
8467 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8468 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8469 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8470 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8471
5f3d5799
JK		 8472 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8473 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8474 * instead of reading the real value. */
4704d0be 8475 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8476
8477 /*
8478 * Transfer the event that L0 or L1 may wanted to inject into
8479 * L2 to IDT_VECTORING_INFO_FIELD.
8480 */
8481 vmcs12_save_pending_event(vcpu, vmcs12);
8482 }
8483
8484 /*
8485 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8486 * preserved above and would only end up incorrectly in L1.
8487 */
8488 vcpu->arch.nmi_injected = false;
8489 kvm_clear_exception_queue(vcpu);
8490 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8491}
8492
8493/*
8494 * A part of what we need to when the nested L2 guest exits and we want to
8495 * run its L1 parent, is to reset L1's guest state to the host state specified
8496 * in vmcs12.
8497 * This function is to be called not only on normal nested exit, but also on
8498 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8499 * Failures During or After Loading Guest State").
8500 * This function should be called when the active VMCS is L1's (vmcs01).
8501 */
733568f9
JK		 8502static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8503 struct vmcs12 *vmcs12)
4704d0be 8504{
21feb4eb
ACL		 8505 struct kvm_segment seg;
8506
4704d0be
NHE		 8507 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8508 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8509 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8510 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8511 else
8512 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8513 vmx_set_efer(vcpu, vcpu->arch.efer);
8514
8515 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8516 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8517 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8518 /*
8519 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8520 * actually changed, because it depends on the current state of
8521 * fpu_active (which may have changed).
8522 * Note that vmx_set_cr0 refers to efer set above.
8523 */
9e3e4dbf 8524 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8525 /*
8526 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8527 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8528 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8529 */
8530 update_exception_bitmap(vcpu);
8531 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8532 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8533
8534 /*
8535 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8536 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8537 */
8538 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8539 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8540
29bf08f1 8541 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8542
4704d0be
NHE		 8543 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8544 kvm_mmu_reset_context(vcpu);
8545
feaf0c7d
GN		 8546 if (!enable_ept)
8547 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8548
4704d0be
NHE		 8549 if (enable_vpid) {
8550 /*
8551 * Trivially support vpid by letting L2s share their parent
8552 * L1's vpid. TODO: move to a more elaborate solution, giving
8553 * each L2 its own vpid and exposing the vpid feature to L1.
8554 */
8555 vmx_flush_tlb(vcpu);
8556 }
8557
8558
8559 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8560 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8561 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8562 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8563 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8564
36be0b9d
PB		 8565 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8566 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8567 vmcs_write64(GUEST_BNDCFGS, 0);
8568
44811c02 8569 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8570 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8571 vcpu->arch.pat = vmcs12->host_ia32_pat;
8572 }
4704d0be
NHE		 8573 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8574 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8575 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8576
21feb4eb
ACL		 8577 /* Set L1 segment info according to Intel SDM
8578 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8579 seg = (struct kvm_segment) {
8580 .base = 0,
8581 .limit = 0xFFFFFFFF,
8582 .selector = vmcs12->host_cs_selector,
8583 .type = 11,
8584 .present = 1,
8585 .s = 1,
8586 .g = 1
8587 };
8588 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8589 seg.l = 1;
8590 else
8591 seg.db = 1;
8592 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8593 seg = (struct kvm_segment) {
8594 .base = 0,
8595 .limit = 0xFFFFFFFF,
8596 .type = 3,
8597 .present = 1,
8598 .s = 1,
8599 .db = 1,
8600 .g = 1
8601 };
8602 seg.selector = vmcs12->host_ds_selector;
8603 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8604 seg.selector = vmcs12->host_es_selector;
8605 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8606 seg.selector = vmcs12->host_ss_selector;
8607 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8608 seg.selector = vmcs12->host_fs_selector;
8609 seg.base = vmcs12->host_fs_base;
8610 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8611 seg.selector = vmcs12->host_gs_selector;
8612 seg.base = vmcs12->host_gs_base;
8613 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8614 seg = (struct kvm_segment) {
205befd9 8615 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8616 .limit = 0x67,
8617 .selector = vmcs12->host_tr_selector,
8618 .type = 11,
8619 .present = 1
8620 };
8621 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8622
503cd0c5
JK		 8623 kvm_set_dr(vcpu, 7, 0x400);
8624 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8625}
8626
8627/*
8628 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8629 * and modify vmcs12 to make it see what it would expect to see there if
8630 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8631 */
533558bc
JK		 8632static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8633 u32 exit_intr_info,
8634 unsigned long exit_qualification)
4704d0be
NHE		 8635{
8636 struct vcpu_vmx *vmx = to_vmx(vcpu);
8637 int cpu;
8638 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8639
5f3d5799
JK		 8640 /* trying to cancel vmlaunch/vmresume is a bug */
8641 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8642
4704d0be 8643 leave_guest_mode(vcpu);
533558bc
JK		 8644 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8645 exit_qualification);
4704d0be 8646
77b0f5d6
BD		 8647 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8648 && nested_exit_intr_ack_set(vcpu)) {
8649 int irq = kvm_cpu_get_interrupt(vcpu);
8650 WARN_ON(irq < 0);
8651 vmcs12->vm_exit_intr_info = irq |
8652 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8653 }
8654
542060ea
JK		 8655 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8656 vmcs12->exit_qualification,
8657 vmcs12->idt_vectoring_info_field,
8658 vmcs12->vm_exit_intr_info,
8659 vmcs12->vm_exit_intr_error_code,
8660 KVM_ISA_VMX);
4704d0be
NHE		 8661
8662 cpu = get_cpu();
8663 vmx->loaded_vmcs = &vmx->vmcs01;
8664 vmx_vcpu_put(vcpu);
8665 vmx_vcpu_load(vcpu, cpu);
8666 vcpu->cpu = cpu;
8667 put_cpu();
8668
2961e876
GN		 8669 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8670 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8671 vmx_segment_cache_clear(vmx);
8672
4704d0be
NHE		 8673 /* if no vmcs02 cache requested, remove the one we used */
8674 if (VMCS02_POOL_SIZE == 0)
8675 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8676
8677 load_vmcs12_host_state(vcpu, vmcs12);
8678
27fc51b2 8679 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8680 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8681
8682 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8683 vmx->host_rsp = 0;
8684
8685 /* Unpin physical memory we referred to in vmcs02 */
8686 if (vmx->nested.apic_access_page) {
8687 nested_release_page(vmx->nested.apic_access_page);
8688 vmx->nested.apic_access_page = 0;
8689 }
8690
8691 /*
8692 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8693 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8694 * success or failure flag accordingly.
8695 */
8696 if (unlikely(vmx->fail)) {
8697 vmx->fail = 0;
8698 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8699 } else
8700 nested_vmx_succeed(vcpu);
012f83cb
AG		 8701 if (enable_shadow_vmcs)
8702 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8703
8704 /* in case we halted in L2 */
8705 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8706}
8707
42124925
JK		 8708/*
8709 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8710 */
8711static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8712{
8713 if (is_guest_mode(vcpu))
533558bc 8714 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8715 free_nested(to_vmx(vcpu));
8716}
8717
7c177938
NHE		 8718/*
8719 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8720 * 23.7 "VM-entry failures during or after loading guest state" (this also
8721 * lists the acceptable exit-reason and exit-qualification parameters).
8722 * It should only be called before L2 actually succeeded to run, and when
8723 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8724 */
8725static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8726 struct vmcs12 *vmcs12,
8727 u32 reason, unsigned long qualification)
8728{
8729 load_vmcs12_host_state(vcpu, vmcs12);
8730 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8731 vmcs12->exit_qualification = qualification;
8732 nested_vmx_succeed(vcpu);
012f83cb
AG		 8733 if (enable_shadow_vmcs)
8734 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8735}
8736
8a76d7f2
JR		 8737static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8738 struct x86_instruction_info *info,
8739 enum x86_intercept_stage stage)
8740{
8741 return X86EMUL_CONTINUE;
8742}
8743
cbdd1bea 8744static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8745 .cpu_has_kvm_support = cpu_has_kvm_support,
8746 .disabled_by_bios = vmx_disabled_by_bios,
8747 .hardware_setup = hardware_setup,
8748 .hardware_unsetup = hardware_unsetup,
002c7f7c 8749 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8750 .hardware_enable = hardware_enable,
8751 .hardware_disable = hardware_disable,
04547156 8752 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8753
8754 .vcpu_create = vmx_create_vcpu,
8755 .vcpu_free = vmx_free_vcpu,
04d2cc77 8756 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8757
04d2cc77 8758 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8759 .vcpu_load = vmx_vcpu_load,
8760 .vcpu_put = vmx_vcpu_put,
8761
c8639010 8762 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8763 .get_msr = vmx_get_msr,
8764 .set_msr = vmx_set_msr,
8765 .get_segment_base = vmx_get_segment_base,
8766 .get_segment = vmx_get_segment,
8767 .set_segment = vmx_set_segment,
2e4d2653 8768 .get_cpl = vmx_get_cpl,
6aa8b732 8769 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8770 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8771 .decache_cr3 = vmx_decache_cr3,
25c4c276 8772 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8773 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8774 .set_cr3 = vmx_set_cr3,
8775 .set_cr4 = vmx_set_cr4,
6aa8b732 8776 .set_efer = vmx_set_efer,
6aa8b732
AK		 8777 .get_idt = vmx_get_idt,
8778 .set_idt = vmx_set_idt,
8779 .get_gdt = vmx_get_gdt,
8780 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8781 .get_dr6 = vmx_get_dr6,
8782 .set_dr6 = vmx_set_dr6,
020df079 8783 .set_dr7 = vmx_set_dr7,
81908bf4 8784 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8785 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8786 .get_rflags = vmx_get_rflags,
8787 .set_rflags = vmx_set_rflags,
ebcbab4c 8788 .fpu_activate = vmx_fpu_activate,
02daab21 8789 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8790
8791 .tlb_flush = vmx_flush_tlb,
6aa8b732 8792
6aa8b732 8793 .run = vmx_vcpu_run,
6062d012 8794 .handle_exit = vmx_handle_exit,
6aa8b732 8795 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8796 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8797 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8798 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8799 .set_irq = vmx_inject_irq,
95ba8273 8800 .set_nmi = vmx_inject_nmi,
298101da 8801 .queue_exception = vmx_queue_exception,
b463a6f7 8802 .cancel_injection = vmx_cancel_injection,
78646121 8803 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8804 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8805 .get_nmi_mask = vmx_get_nmi_mask,
8806 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8807 .enable_nmi_window = enable_nmi_window,
8808 .enable_irq_window = enable_irq_window,
8809 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8810 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8811 .vm_has_apicv = vmx_vm_has_apicv,
8812 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8813 .hwapic_irr_update = vmx_hwapic_irr_update,
8814 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8815 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8816 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8817
cbc94022 8818 .set_tss_addr = vmx_set_tss_addr,
67253af5 8819 .get_tdp_level = get_ept_level,
4b12f0de 8820 .get_mt_mask = vmx_get_mt_mask,
229456fc 8821
586f9607 8822 .get_exit_info = vmx_get_exit_info,
586f9607 8823
17cc3935 8824 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8825
8826 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8827
8828 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8829 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8830
8831 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8832
8833 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8834
4051b188 8835 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8836 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8837 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8838 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8839 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8840 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8841
8842 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8843
8844 .check_intercept = vmx_check_intercept,
a547c6db 8845 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8846 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8847
8848 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8849};
8850
8851static int __init vmx_init(void)
8852{
8d14695f 8853 int r, i, msr;
26bb0981
AK		 8854
8855 rdmsrl_safe(MSR_EFER, &host_efer);
8856
8857 for (i = 0; i < NR_VMX_MSR; ++i)
8858 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8859
3e7c73e9 8860 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8861 if (!vmx_io_bitmap_a)
8862 return -ENOMEM;
8863
2106a548
GC		 8864 r = -ENOMEM;
8865
3e7c73e9 8866 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8867 if (!vmx_io_bitmap_b)
fdef3ad1 8868 goto out;
fdef3ad1 8869
5897297b 8870 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8871 if (!vmx_msr_bitmap_legacy)
25c5f225 8872 goto out1;
2106a548 8873
8d14695f
YZ		 8874 vmx_msr_bitmap_legacy_x2apic =
8875 (unsigned long *)__get_free_page(GFP_KERNEL);
8876 if (!vmx_msr_bitmap_legacy_x2apic)
8877 goto out2;
25c5f225 8878
5897297b 8879 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8880 if (!vmx_msr_bitmap_longmode)
8d14695f 8881 goto out3;
2106a548 8882
8d14695f
YZ		 8883 vmx_msr_bitmap_longmode_x2apic =
8884 (unsigned long *)__get_free_page(GFP_KERNEL);
8885 if (!vmx_msr_bitmap_longmode_x2apic)
8886 goto out4;
4607c2d7
AG		 8887 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8888 if (!vmx_vmread_bitmap)
8889 goto out5;
8890
8891 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8892 if (!vmx_vmwrite_bitmap)
8893 goto out6;
8894
8895 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8896 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8897 /* shadowed read/write fields */
8898 for (i = 0; i < max_shadow_read_write_fields; i++) {
8899 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8900 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8901 }
8902 /* shadowed read only fields */
8903 for (i = 0; i < max_shadow_read_only_fields; i++)
8904 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8905
fdef3ad1
HQ		 8906 /*
8907 * Allow direct access to the PC debug port (it is often used for I/O
8908 * delays, but the vmexits simply slow things down).
8909 */
3e7c73e9
AK		 8910 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8911 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8912
3e7c73e9 8913 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8914
5897297b
AK		 8915 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8916 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8917
2384d2b3
SY		 8918 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8919
0ee75bea
AK		 8920 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8921 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8922 if (r)
4607c2d7 8923 goto out7;
25c5f225 8924
8f536b76
ZY		 8925#ifdef CONFIG_KEXEC
8926 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8927 crash_vmclear_local_loaded_vmcss);
8928#endif
8929
5897297b
AK		 8930 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8931 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8932 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8933 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8934 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8935 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8936 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8937
8d14695f
YZ		 8938 memcpy(vmx_msr_bitmap_legacy_x2apic,
8939 vmx_msr_bitmap_legacy, PAGE_SIZE);
8940 memcpy(vmx_msr_bitmap_longmode_x2apic,
8941 vmx_msr_bitmap_longmode, PAGE_SIZE);
8942
01e439be 8943 if (enable_apicv) {
8d14695f
YZ		 8944 for (msr = 0x800; msr <= 0x8ff; msr++)
8945 vmx_disable_intercept_msr_read_x2apic(msr);
8946
8947 /* According SDM, in x2apic mode, the whole id reg is used.
8948 * But in KVM, it only use the highest eight bits. Need to
8949 * intercept it */
8950 vmx_enable_intercept_msr_read_x2apic(0x802);
8951 /* TMCCT */
8952 vmx_enable_intercept_msr_read_x2apic(0x839);
8953 /* TPR */
8954 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8955 /* EOI */
8956 vmx_disable_intercept_msr_write_x2apic(0x80b);
8957 /* SELF-IPI */
8958 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8959 }
fdef3ad1 8960
089d034e 8961 if (enable_ept) {
3f6d8c8a
XH		 8962 kvm_mmu_set_mask_ptes(0ull,
8963 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8964 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8965 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8966 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8967 kvm_enable_tdp();
8968 } else
8969 kvm_disable_tdp();
1439442c 8970
fdef3ad1
HQ		 8971 return 0;
8972
4607c2d7
AG		 8973out7:
8974 free_page((unsigned long)vmx_vmwrite_bitmap);
8975out6:
8976 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8977out5:
8978 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8979out4:
5897297b 8980 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8981out3:
8982 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8983out2:
5897297b 8984 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8985out1:
3e7c73e9 8986 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8987out:
3e7c73e9 8988 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8989 return r;
6aa8b732
AK		 8990}
8991
8992static void __exit vmx_exit(void)
8993{
8d14695f
YZ		 8994 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8995 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8996 free_page((unsigned long)vmx_msr_bitmap_legacy);
8997 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8998 free_page((unsigned long)vmx_io_bitmap_b);
8999 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9000 free_page((unsigned long)vmx_vmwrite_bitmap);
9001 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9002
8f536b76
ZY		 9003#ifdef CONFIG_KEXEC
9004 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
9005 synchronize_rcu();
9006#endif
9007
cb498ea2 9008 kvm_exit();
6aa8b732
AK		 9009}
9010
9011module_init(vmx_init)
9012module_exit(vmx_exit)
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