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vl: Add another sanity check to smp_parse() function
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
d49b6836 29#include "qemu/error-report.h"
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
2001d0cd 48#include "exec/address-spaces.h"
0d09e41a 49#include "hw/xen/xen.h"
0d09e41a 50#include "hw/i386/apic_internal.h"
bdeec802
IM		 51#endif
52
5e891bf8
EH		 53
54/* Cache topology CPUID constants: */
55
56/* CPUID Leaf 2 Descriptors */
57
58#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
59#define CPUID_2_L1I_32KB_8WAY_64B 0x30
60#define CPUID_2_L2_2MB_8WAY_64B 0x7d
61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
135/* No L3 cache: */
136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
140
141/* TLB definitions: */
142
143#define L1_DTLB_2M_ASSOC 1
144#define L1_DTLB_2M_ENTRIES 255
145#define L1_DTLB_4K_ASSOC 1
146#define L1_DTLB_4K_ENTRIES 255
147
148#define L1_ITLB_2M_ASSOC 1
149#define L1_ITLB_2M_ENTRIES 255
150#define L1_ITLB_4K_ASSOC 1
151#define L1_ITLB_4K_ENTRIES 255
152
153#define L2_DTLB_2M_ASSOC 0 /* disabled */
154#define L2_DTLB_2M_ENTRIES 0 /* disabled */
155#define L2_DTLB_4K_ASSOC 4
156#define L2_DTLB_4K_ENTRIES 512
157
158#define L2_ITLB_2M_ASSOC 0 /* disabled */
159#define L2_ITLB_2M_ENTRIES 0 /* disabled */
160#define L2_ITLB_4K_ASSOC 4
161#define L2_ITLB_4K_ENTRIES 512
162
163
164
99b88a17
IM		 165static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
166 uint32_t vendor2, uint32_t vendor3)
167{
168 int i;
169 for (i = 0; i < 4; i++) {
170 dst[i] = vendor1 >> (8 * i);
171 dst[i + 4] = vendor2 >> (8 * i);
172 dst[i + 8] = vendor3 >> (8 * i);
173 }
174 dst[CPUID_VENDOR_SZ] = '\0';
175}
176
c6dc6f63
AP		 177/* feature flags taken from "Intel Processor Identification and the CPUID
178 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
179 * between feature naming conventions, aliases may be added.
180 */
181static const char *feature_name[] = {
182 "fpu", "vme", "de", "pse",
183 "tsc", "msr", "pae", "mce",
184 "cx8", "apic", NULL, "sep",
185 "mtrr", "pge", "mca", "cmov",
186 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
187 NULL, "ds" /* Intel dts */, "acpi", "mmx",
188 "fxsr", "sse", "sse2", "ss",
189 "ht" /* Intel htt */, "tm", "ia64", "pbe",
190};
191static const char *ext_feature_name[] = {
f370be3c 192 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 193 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 194 "tm2", "ssse3", "cid", NULL,
e117f772 195 "fma", "cx16", "xtpr", "pdcm",
434acb81 196 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 197 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 198 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 199 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 200};
3b671a40
EH		 201/* Feature names that are already defined on feature_name[] but are set on
202 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
203 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
204 * if and only if CPU vendor is AMD.
205 */
c6dc6f63 206static const char *ext2_feature_name[] = {
3b671a40
EH		 207 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
208 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
209 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
210 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
211 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
212 "nx|xd", NULL, "mmxext", NULL /* mmx */,
213 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 214 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 215};
216static const char *ext3_feature_name[] = {
217 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
218 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 219 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 220 "skinit", "wdt", NULL, "lwp",
221 "fma4", "tce", NULL, "nodeid_msr",
222 NULL, "tbm", "topoext", "perfctr_core",
223 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 224 NULL, NULL, NULL, NULL,
225};
226
89e49c8b
EH		 227static const char *ext4_feature_name[] = {
228 NULL, NULL, "xstore", "xstore-en",
229 NULL, NULL, "xcrypt", "xcrypt-en",
230 "ace2", "ace2-en", "phe", "phe-en",
231 "pmm", "pmm-en", NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235 NULL, NULL, NULL, NULL,
236};
237
c6dc6f63 238static const char *kvm_feature_name[] = {
c3d39807 239 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 240 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
8248c36a 245 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 246 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 247};
248
296acb64
JR		 249static const char *svm_feature_name[] = {
250 "npt", "lbrv", "svm_lock", "nrip_save",
251 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
252 NULL, NULL, "pause_filter", NULL,
253 "pfthreshold", NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257 NULL, NULL, NULL, NULL,
258};
259
a9321a4d 260static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 261 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 262 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 263 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
264 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 265};
266
303752a9
MT		 267static const char *cpuid_apm_edx_feature_name[] = {
268 NULL, NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 "invtsc", NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275 NULL, NULL, NULL, NULL,
276};
277
0bb0b2d2
PB		 278static const char *cpuid_xsave_feature_name[] = {
279 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286 NULL, NULL, NULL, NULL,
287};
288
28b8e4d0
JK		 289static const char *cpuid_6_feature_name[] = {
290 NULL, NULL, "arat", NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296 NULL, NULL, NULL, NULL,
297 NULL, NULL, NULL, NULL,
298};
299
621626ce
EH		 300#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
301#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
302 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
303#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
304 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
305 CPUID_PSE36 | CPUID_FXSR)
306#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
307#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
308 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
309 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
310 CPUID_PAE | CPUID_SEP | CPUID_APIC)
311
312#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
313 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
314 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
315 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
316 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
317 /* partly implemented:
318 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
319 /* missing:
320 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
321#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
322 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
323 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
324 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
325 /* missing:
326 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
327 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
328 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
329 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
330 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
331 CPUID_EXT_RDRAND */
332
333#ifdef TARGET_X86_64
334#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
335#else
336#define TCG_EXT2_X86_64_FEATURES 0
337#endif
338
339#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
340 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
341 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
342 TCG_EXT2_X86_64_FEATURES)
343#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
344 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
345#define TCG_EXT4_FEATURES 0
346#define TCG_SVM_FEATURES 0
347#define TCG_KVM_FEATURES 0
348#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
349 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
350 /* missing:
351 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
352 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
353 CPUID_7_0_EBX_RDSEED */
303752a9 354#define TCG_APM_FEATURES 0
28b8e4d0 355#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
621626ce
EH		 356
357
5ef57876
EH		 358typedef struct FeatureWordInfo {
359 const char **feat_names;
04d104b6
EH		 360 uint32_t cpuid_eax; /* Input EAX for CPUID */
361 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
362 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
363 int cpuid_reg; /* output register (R_* constant) */
37ce3522 364 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 365 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 366} FeatureWordInfo;
367
368static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 369 [FEAT_1_EDX] = {
370 .feat_names = feature_name,
371 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 372 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 373 },
374 [FEAT_1_ECX] = {
375 .feat_names = ext_feature_name,
376 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 377 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 378 },
379 [FEAT_8000_0001_EDX] = {
380 .feat_names = ext2_feature_name,
381 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 382 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 383 },
384 [FEAT_8000_0001_ECX] = {
385 .feat_names = ext3_feature_name,
386 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 387 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 388 },
89e49c8b
EH		 389 [FEAT_C000_0001_EDX] = {
390 .feat_names = ext4_feature_name,
391 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 392 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 393 },
bffd67b0
EH		 394 [FEAT_KVM] = {
395 .feat_names = kvm_feature_name,
396 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 397 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 398 },
399 [FEAT_SVM] = {
400 .feat_names = svm_feature_name,
401 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 402 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 403 },
404 [FEAT_7_0_EBX] = {
405 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 406 .cpuid_eax = 7,
407 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
408 .cpuid_reg = R_EBX,
37ce3522 409 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 410 },
303752a9
MT		 411 [FEAT_8000_0007_EDX] = {
412 .feat_names = cpuid_apm_edx_feature_name,
413 .cpuid_eax = 0x80000007,
414 .cpuid_reg = R_EDX,
415 .tcg_features = TCG_APM_FEATURES,
416 .unmigratable_flags = CPUID_APM_INVTSC,
417 },
0bb0b2d2
PB		 418 [FEAT_XSAVE] = {
419 .feat_names = cpuid_xsave_feature_name,
420 .cpuid_eax = 0xd,
421 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
422 .cpuid_reg = R_EAX,
423 .tcg_features = 0,
0bb0b2d2 424 },
28b8e4d0
JK		 425 [FEAT_6_EAX] = {
426 .feat_names = cpuid_6_feature_name,
427 .cpuid_eax = 6, .cpuid_reg = R_EAX,
428 .tcg_features = TCG_6_EAX_FEATURES,
429 },
5ef57876
EH		 430};
431
8e8aba50
EH		 432typedef struct X86RegisterInfo32 {
433 /* Name of register */
434 const char *name;
435 /* QAPI enum value register */
436 X86CPURegister32 qapi_enum;
437} X86RegisterInfo32;
438
439#define REGISTER(reg) \
5d371f41 440 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 441static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 442 REGISTER(EAX),
443 REGISTER(ECX),
444 REGISTER(EDX),
445 REGISTER(EBX),
446 REGISTER(ESP),
447 REGISTER(EBP),
448 REGISTER(ESI),
449 REGISTER(EDI),
450};
451#undef REGISTER
452
2560f19f
PB		 453typedef struct ExtSaveArea {
454 uint32_t feature, bits;
455 uint32_t offset, size;
456} ExtSaveArea;
457
458static const ExtSaveArea ext_save_areas[] = {
459 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 460 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 461 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
462 .offset = 0x3c0, .size = 0x40 },
463 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 464 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 465 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
466 .offset = 0x440, .size = 0x40 },
467 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
468 .offset = 0x480, .size = 0x200 },
469 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
470 .offset = 0x680, .size = 0x400 },
2560f19f 471};
8e8aba50 472
8b4beddc
EH		 473const char *get_register_name_32(unsigned int reg)
474{
31ccdde2 475 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 476 return NULL;
477 }
8e8aba50 478 return x86_reg_info_32[reg].name;
8b4beddc
EH		 479}
480
5fcca9ff
EH		 481/* KVM-specific features that are automatically added to all CPU models
482 * when KVM is enabled.
483 */
484static uint32_t kvm_default_features[FEATURE_WORDS] = {
485 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
dc59944b 486 (1 << KVM_FEATURE_NOP_IO_DELAY) |
dc59944b
MT		 487 (1 << KVM_FEATURE_CLOCKSOURCE2) |
488 (1 << KVM_FEATURE_ASYNC_PF) |
489 (1 << KVM_FEATURE_STEAL_TIME) |
29694758 490 (1 << KVM_FEATURE_PV_EOI) |
5fcca9ff 491 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
ef02ef5f 492 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
5fcca9ff 493};
dc59944b 494
136a7e9a
EH		 495/* Features that are not added by default to any CPU model when KVM is enabled.
496 */
497static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
864867b9 498 [FEAT_1_EDX] = CPUID_ACPI,
136a7e9a 499 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
75d373ef 500 [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM,
136a7e9a
EH		 501};
502
1cadaa94 503void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features)
dc59944b 504{
8fb4f821 505 kvm_default_features[w] &= ~features;
dc59944b
MT		 506}
507
75d373ef
EH		 508void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features)
509{
510 kvm_default_unset_features[w] &= ~features;
511}
512
84f1b92f
EH		 513/*
514 * Returns the set of feature flags that are supported and migratable by
515 * QEMU, for a given FeatureWord.
516 */
517static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
518{
519 FeatureWordInfo *wi = &feature_word_info[w];
520 uint32_t r = 0;
521 int i;
522
523 for (i = 0; i < 32; i++) {
524 uint32_t f = 1U << i;
525 /* If the feature name is unknown, it is not supported by QEMU yet */
526 if (!wi->feat_names[i]) {
527 continue;
528 }
529 /* Skip features known to QEMU, but explicitly marked as unmigratable */
530 if (wi->unmigratable_flags & f) {
531 continue;
532 }
533 r |= f;
534 }
535 return r;
536}
537
bb44e0d1
JK		 538void host_cpuid(uint32_t function, uint32_t count,
539 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 540{
a1fd24af
AL		 541 uint32_t vec[4];
542
543#ifdef __x86_64__
544 asm volatile("cpuid"
545 : "=a"(vec[0]), "=b"(vec[1]),
546 "=c"(vec[2]), "=d"(vec[3])
547 : "0"(function), "c"(count) : "cc");
c1f41226 548#elif defined(__i386__)
a1fd24af
AL		 549 asm volatile("pusha \n\t"
550 "cpuid \n\t"
551 "mov %%eax, 0(%2) \n\t"
552 "mov %%ebx, 4(%2) \n\t"
553 "mov %%ecx, 8(%2) \n\t"
554 "mov %%edx, 12(%2) \n\t"
555 "popa"
556 : : "a"(function), "c"(count), "S"(vec)
557 : "memory", "cc");
c1f41226
EH		 558#else
559 abort();
a1fd24af
AL		 560#endif
561
bdde476a 562 if (eax)
a1fd24af 563 *eax = vec[0];
bdde476a 564 if (ebx)
a1fd24af 565 *ebx = vec[1];
bdde476a 566 if (ecx)
a1fd24af 567 *ecx = vec[2];
bdde476a 568 if (edx)
a1fd24af 569 *edx = vec[3];
bdde476a 570}
c6dc6f63
AP		 571
572#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
573
574/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
575 * a substring. ex if !NULL points to the first char after a substring,
576 * otherwise the string is assumed to sized by a terminating nul.
577 * Return lexical ordering of *s1:*s2.
578 */
8f9d989c
CF		 579static int sstrcmp(const char *s1, const char *e1,
580 const char *s2, const char *e2)
c6dc6f63
AP		 581{
582 for (;;) {
583 if (!*s1 || !*s2 || *s1 != *s2)
584 return (*s1 - *s2);
585 ++s1, ++s2;
586 if (s1 == e1 && s2 == e2)
587 return (0);
588 else if (s1 == e1)
589 return (*s2);
590 else if (s2 == e2)
591 return (*s1);
592 }
593}
594
595/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
596 * '|' delimited (possibly empty) strings in which case search for a match
597 * within the alternatives proceeds left to right. Return 0 for success,
598 * non-zero otherwise.
599 */
600static int altcmp(const char *s, const char *e, const char *altstr)
601{
602 const char *p, *q;
603
604 for (q = p = altstr; ; ) {
605 while (*p && *p != '|')
606 ++p;
607 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
608 return (0);
609 if (!*p)
610 return (1);
611 else
612 q = ++p;
613 }
614}
615
616/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 617 * *pval and return true, otherwise return false
c6dc6f63 618 */
e41e0fc6
JK		 619static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
620 const char **featureset)
c6dc6f63
AP		 621{
622 uint32_t mask;
623 const char **ppc;
e41e0fc6 624 bool found = false;
c6dc6f63 625
e41e0fc6 626 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 627 if (*ppc && !altcmp(s, e, *ppc)) {
628 *pval |= mask;
e41e0fc6 629 found = true;
c6dc6f63 630 }
e41e0fc6
JK		 631 }
632 return found;
c6dc6f63
AP		 633}
634
5ef57876 635static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 636 FeatureWordArray words,
637 Error **errp)
c6dc6f63 638{
5ef57876
EH		 639 FeatureWord w;
640 for (w = 0; w < FEATURE_WORDS; w++) {
641 FeatureWordInfo *wi = &feature_word_info[w];
642 if (wi->feat_names &&
643 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
644 break;
645 }
646 }
647 if (w == FEATURE_WORDS) {
c00c94ab 648 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 649 }
c6dc6f63
AP		 650}
651
d940ee9b
EH		 652/* CPU class name definitions: */
653
654#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
655#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
656
657/* Return type name for a given CPU model name
658 * Caller is responsible for freeing the returned string.
659 */
660static char *x86_cpu_type_name(const char *model_name)
661{
662 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
663}
664
500050d1
AF		 665static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
666{
d940ee9b
EH		 667 ObjectClass *oc;
668 char *typename;
669
500050d1
AF		 670 if (cpu_model == NULL) {
671 return NULL;
672 }
673
d940ee9b
EH		 674 typename = x86_cpu_type_name(cpu_model);
675 oc = object_class_by_name(typename);
676 g_free(typename);
677 return oc;
500050d1
AF		 678}
679
d940ee9b 680struct X86CPUDefinition {
c6dc6f63
AP		 681 const char *name;
682 uint32_t level;
90e4b0c3
EH		 683 uint32_t xlevel;
684 uint32_t xlevel2;
99b88a17
IM		 685 /* vendor is zero-terminated, 12 character ASCII string */
686 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 687 int family;
688 int model;
689 int stepping;
0514ef2f 690 FeatureWordArray features;
c6dc6f63 691 char model_id[48];
787aaf57 692 bool cache_info_passthrough;
d940ee9b 693};
c6dc6f63 694
9576de75 695static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 696 {
697 .name = "qemu64",
3046bb5d 698 .level = 0xd,
99b88a17 699 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 700 .family = 6,
f8e6a11a 701 .model = 6,
c6dc6f63 702 .stepping = 3,
0514ef2f 703 .features[FEAT_1_EDX] =
27861ecc 704 PPRO_FEATURES |
c6dc6f63 705 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 706 CPUID_PSE36,
0514ef2f 707 .features[FEAT_1_ECX] =
27861ecc 708 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 709 .features[FEAT_8000_0001_EDX] =
c6dc6f63 710 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 711 .features[FEAT_8000_0001_ECX] =
27861ecc 712 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 713 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
714 .xlevel = 0x8000000A,
c6dc6f63
AP		 715 },
716 {
717 .name = "phenom",
718 .level = 5,
99b88a17 719 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 720 .family = 16,
721 .model = 2,
722 .stepping = 3,
b9fc20bc 723 /* Missing: CPUID_HT */
0514ef2f 724 .features[FEAT_1_EDX] =
27861ecc 725 PPRO_FEATURES |
c6dc6f63 726 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 727 CPUID_PSE36 | CPUID_VME,
0514ef2f 728 .features[FEAT_1_ECX] =
27861ecc 729 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 730 CPUID_EXT_POPCNT,
0514ef2f 731 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 732 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
733 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 734 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 735 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
736 CPUID_EXT3_CR8LEG,
737 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
738 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 739 .features[FEAT_8000_0001_ECX] =
27861ecc 740 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 741 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 742 /* Missing: CPUID_SVM_LBRV */
0514ef2f 743 .features[FEAT_SVM] =
b9fc20bc 744 CPUID_SVM_NPT,
c6dc6f63
AP		 745 .xlevel = 0x8000001A,
746 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
747 },
748 {
749 .name = "core2duo",
750 .level = 10,
99b88a17 751 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 752 .family = 6,
753 .model = 15,
754 .stepping = 11,
b9fc20bc 755 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 756 .features[FEAT_1_EDX] =
27861ecc 757 PPRO_FEATURES |
c6dc6f63 758 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 759 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
760 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 761 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 762 .features[FEAT_1_ECX] =
27861ecc 763 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 764 CPUID_EXT_CX16,
0514ef2f 765 .features[FEAT_8000_0001_EDX] =
27861ecc 766 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 767 .features[FEAT_8000_0001_ECX] =
27861ecc 768 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 769 .xlevel = 0x80000008,
770 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
771 },
772 {
773 .name = "kvm64",
3046bb5d 774 .level = 0xd,
99b88a17 775 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 776 .family = 15,
777 .model = 6,
778 .stepping = 1,
b3a4f0b1 779 /* Missing: CPUID_HT */
0514ef2f 780 .features[FEAT_1_EDX] =
b3a4f0b1 781 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 782 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
783 CPUID_PSE36,
784 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 785 .features[FEAT_1_ECX] =
27861ecc 786 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 787 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 788 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 789 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
790 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
791 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
792 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
793 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 794 .features[FEAT_8000_0001_ECX] =
27861ecc 795 0,
c6dc6f63
AP		 796 .xlevel = 0x80000008,
797 .model_id = "Common KVM processor"
798 },
c6dc6f63
AP		 799 {
800 .name = "qemu32",
801 .level = 4,
99b88a17 802 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 803 .family = 6,
f8e6a11a 804 .model = 6,
c6dc6f63 805 .stepping = 3,
0514ef2f 806 .features[FEAT_1_EDX] =
27861ecc 807 PPRO_FEATURES,
0514ef2f 808 .features[FEAT_1_ECX] =
27861ecc 809 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 810 .xlevel = 0x80000004,
c6dc6f63 811 },
eafaf1e5
AP		 812 {
813 .name = "kvm32",
814 .level = 5,
99b88a17 815 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 816 .family = 15,
817 .model = 6,
818 .stepping = 1,
0514ef2f 819 .features[FEAT_1_EDX] =
b3a4f0b1 820 PPRO_FEATURES | CPUID_VME |
eafaf1e5 821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 822 .features[FEAT_1_ECX] =
27861ecc 823 CPUID_EXT_SSE3,
0514ef2f 824 .features[FEAT_8000_0001_ECX] =
27861ecc 825 0,
eafaf1e5
AP		 826 .xlevel = 0x80000008,
827 .model_id = "Common 32-bit KVM processor"
828 },
c6dc6f63
AP		 829 {
830 .name = "coreduo",
831 .level = 10,
99b88a17 832 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 833 .family = 6,
834 .model = 14,
835 .stepping = 8,
b9fc20bc 836 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 837 .features[FEAT_1_EDX] =
27861ecc 838 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 839 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
840 CPUID_SS,
841 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 842 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 843 .features[FEAT_1_ECX] =
e93abc14 844 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 845 .features[FEAT_8000_0001_EDX] =
27861ecc 846 CPUID_EXT2_NX,
c6dc6f63
AP		 847 .xlevel = 0x80000008,
848 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
849 },
850 {
851 .name = "486",
58012d66 852 .level = 1,
99b88a17 853 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 854 .family = 4,
b2a856d9 855 .model = 8,
c6dc6f63 856 .stepping = 0,
0514ef2f 857 .features[FEAT_1_EDX] =
27861ecc 858 I486_FEATURES,
c6dc6f63
AP		 859 .xlevel = 0,
860 },
861 {
862 .name = "pentium",
863 .level = 1,
99b88a17 864 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 865 .family = 5,
866 .model = 4,
867 .stepping = 3,
0514ef2f 868 .features[FEAT_1_EDX] =
27861ecc 869 PENTIUM_FEATURES,
c6dc6f63
AP		 870 .xlevel = 0,
871 },
872 {
873 .name = "pentium2",
874 .level = 2,
99b88a17 875 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 876 .family = 6,
877 .model = 5,
878 .stepping = 2,
0514ef2f 879 .features[FEAT_1_EDX] =
27861ecc 880 PENTIUM2_FEATURES,
c6dc6f63
AP		 881 .xlevel = 0,
882 },
883 {
884 .name = "pentium3",
3046bb5d 885 .level = 3,
99b88a17 886 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 887 .family = 6,
888 .model = 7,
889 .stepping = 3,
0514ef2f 890 .features[FEAT_1_EDX] =
27861ecc 891 PENTIUM3_FEATURES,
c6dc6f63
AP		 892 .xlevel = 0,
893 },
894 {
895 .name = "athlon",
896 .level = 2,
99b88a17 897 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 898 .family = 6,
899 .model = 2,
900 .stepping = 3,
0514ef2f 901 .features[FEAT_1_EDX] =
27861ecc 902 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 903 CPUID_MCA,
0514ef2f 904 .features[FEAT_8000_0001_EDX] =
60032ac0 905 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 906 .xlevel = 0x80000008,
c6dc6f63
AP		 907 },
908 {
909 .name = "n270",
3046bb5d 910 .level = 10,
99b88a17 911 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 912 .family = 6,
913 .model = 28,
914 .stepping = 2,
b9fc20bc 915 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 916 .features[FEAT_1_EDX] =
27861ecc 917 PPRO_FEATURES |
b9fc20bc
EH		 918 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
919 CPUID_ACPI | CPUID_SS,
c6dc6f63 920 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 921 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
922 * CPUID_EXT_XTPR */
0514ef2f 923 .features[FEAT_1_ECX] =
27861ecc 924 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 925 CPUID_EXT_MOVBE,
0514ef2f 926 .features[FEAT_8000_0001_EDX] =
60032ac0 927 CPUID_EXT2_NX,
0514ef2f 928 .features[FEAT_8000_0001_ECX] =
27861ecc 929 CPUID_EXT3_LAHF_LM,
3046bb5d 930 .xlevel = 0x80000008,
c6dc6f63
AP		 931 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
932 },
3eca4642
EH		 933 {
934 .name = "Conroe",
3046bb5d 935 .level = 10,
99b88a17 936 .vendor = CPUID_VENDOR_INTEL,
3eca4642 937 .family = 6,
ffce9ebb 938 .model = 15,
3eca4642 939 .stepping = 3,
0514ef2f 940 .features[FEAT_1_EDX] =
b3a4f0b1 941 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 942 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
943 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
944 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
945 CPUID_DE | CPUID_FP87,
0514ef2f 946 .features[FEAT_1_ECX] =
27861ecc 947 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 948 .features[FEAT_8000_0001_EDX] =
27861ecc 949 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 950 .features[FEAT_8000_0001_ECX] =
27861ecc 951 CPUID_EXT3_LAHF_LM,
3046bb5d 952 .xlevel = 0x80000008,
3eca4642
EH		 953 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
954 },
955 {
956 .name = "Penryn",
3046bb5d 957 .level = 10,
99b88a17 958 .vendor = CPUID_VENDOR_INTEL,
3eca4642 959 .family = 6,
ffce9ebb 960 .model = 23,
3eca4642 961 .stepping = 3,
0514ef2f 962 .features[FEAT_1_EDX] =
b3a4f0b1 963 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 964 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
965 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
966 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
967 CPUID_DE | CPUID_FP87,
0514ef2f 968 .features[FEAT_1_ECX] =
27861ecc 969 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 970 CPUID_EXT_SSE3,
0514ef2f 971 .features[FEAT_8000_0001_EDX] =
27861ecc 972 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 973 .features[FEAT_8000_0001_ECX] =
27861ecc 974 CPUID_EXT3_LAHF_LM,
3046bb5d 975 .xlevel = 0x80000008,
3eca4642
EH		 976 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
977 },
978 {
979 .name = "Nehalem",
3046bb5d 980 .level = 11,
99b88a17 981 .vendor = CPUID_VENDOR_INTEL,
3eca4642 982 .family = 6,
ffce9ebb 983 .model = 26,
3eca4642 984 .stepping = 3,
0514ef2f 985 .features[FEAT_1_EDX] =
b3a4f0b1 986 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 987 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
988 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
989 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
990 CPUID_DE | CPUID_FP87,
0514ef2f 991 .features[FEAT_1_ECX] =
27861ecc 992 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 993 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 994 .features[FEAT_8000_0001_EDX] =
27861ecc 995 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 996 .features[FEAT_8000_0001_ECX] =
27861ecc 997 CPUID_EXT3_LAHF_LM,
3046bb5d 998 .xlevel = 0x80000008,
3eca4642
EH		 999 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1000 },
1001 {
1002 .name = "Westmere",
1003 .level = 11,
99b88a17 1004 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1005 .family = 6,
1006 .model = 44,
1007 .stepping = 1,
0514ef2f 1008 .features[FEAT_1_EDX] =
b3a4f0b1 1009 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1013 CPUID_DE | CPUID_FP87,
0514ef2f 1014 .features[FEAT_1_ECX] =
27861ecc 1015 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1016 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1017 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1018 .features[FEAT_8000_0001_EDX] =
27861ecc 1019 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1020 .features[FEAT_8000_0001_ECX] =
27861ecc 1021 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1022 .features[FEAT_6_EAX] =
1023 CPUID_6_EAX_ARAT,
3046bb5d 1024 .xlevel = 0x80000008,
3eca4642
EH		 1025 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1026 },
1027 {
1028 .name = "SandyBridge",
1029 .level = 0xd,
99b88a17 1030 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1031 .family = 6,
1032 .model = 42,
1033 .stepping = 1,
0514ef2f 1034 .features[FEAT_1_EDX] =
b3a4f0b1 1035 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1036 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1037 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1038 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1039 CPUID_DE | CPUID_FP87,
0514ef2f 1040 .features[FEAT_1_ECX] =
27861ecc 1041 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1042 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1043 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1044 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1045 CPUID_EXT_SSE3,
0514ef2f 1046 .features[FEAT_8000_0001_EDX] =
27861ecc 1047 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1048 CPUID_EXT2_SYSCALL,
0514ef2f 1049 .features[FEAT_8000_0001_ECX] =
27861ecc 1050 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1051 .features[FEAT_XSAVE] =
1052 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1053 .features[FEAT_6_EAX] =
1054 CPUID_6_EAX_ARAT,
3046bb5d 1055 .xlevel = 0x80000008,
3eca4642
EH		 1056 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1057 },
2f9ac42a
PB		 1058 {
1059 .name = "IvyBridge",
1060 .level = 0xd,
1061 .vendor = CPUID_VENDOR_INTEL,
1062 .family = 6,
1063 .model = 58,
1064 .stepping = 9,
1065 .features[FEAT_1_EDX] =
1066 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1067 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1068 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1069 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1070 CPUID_DE | CPUID_FP87,
1071 .features[FEAT_1_ECX] =
1072 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1073 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1074 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1075 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1076 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1077 .features[FEAT_7_0_EBX] =
1078 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1079 CPUID_7_0_EBX_ERMS,
1080 .features[FEAT_8000_0001_EDX] =
1081 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1082 CPUID_EXT2_SYSCALL,
1083 .features[FEAT_8000_0001_ECX] =
1084 CPUID_EXT3_LAHF_LM,
1085 .features[FEAT_XSAVE] =
1086 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1087 .features[FEAT_6_EAX] =
1088 CPUID_6_EAX_ARAT,
3046bb5d 1089 .xlevel = 0x80000008,
2f9ac42a
PB		 1090 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1091 },
37507094 1092 {
a356850b
EH		 1093 .name = "Haswell-noTSX",
1094 .level = 0xd,
1095 .vendor = CPUID_VENDOR_INTEL,
1096 .family = 6,
1097 .model = 60,
1098 .stepping = 1,
1099 .features[FEAT_1_EDX] =
1100 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1101 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1102 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1103 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1104 CPUID_DE | CPUID_FP87,
1105 .features[FEAT_1_ECX] =
1106 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1107 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1108 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1109 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1110 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1111 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1112 .features[FEAT_8000_0001_EDX] =
1113 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1114 CPUID_EXT2_SYSCALL,
1115 .features[FEAT_8000_0001_ECX] =
1116 CPUID_EXT3_LAHF_LM,
1117 .features[FEAT_7_0_EBX] =
1118 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1119 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1120 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1121 .features[FEAT_XSAVE] =
1122 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1123 .features[FEAT_6_EAX] =
1124 CPUID_6_EAX_ARAT,
3046bb5d 1125 .xlevel = 0x80000008,
a356850b
EH		 1126 .model_id = "Intel Core Processor (Haswell, no TSX)",
1127 }, {
37507094
EH		 1128 .name = "Haswell",
1129 .level = 0xd,
99b88a17 1130 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1131 .family = 6,
1132 .model = 60,
1133 .stepping = 1,
0514ef2f 1134 .features[FEAT_1_EDX] =
b3a4f0b1 1135 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1136 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1137 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1138 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1139 CPUID_DE | CPUID_FP87,
0514ef2f 1140 .features[FEAT_1_ECX] =
27861ecc 1141 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1142 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1143 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1144 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1145 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1146 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1147 .features[FEAT_8000_0001_EDX] =
27861ecc 1148 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1149 CPUID_EXT2_SYSCALL,
0514ef2f 1150 .features[FEAT_8000_0001_ECX] =
27861ecc 1151 CPUID_EXT3_LAHF_LM,
0514ef2f 1152 .features[FEAT_7_0_EBX] =
27861ecc 1153 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1154 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1155 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1156 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1157 .features[FEAT_XSAVE] =
1158 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1159 .features[FEAT_6_EAX] =
1160 CPUID_6_EAX_ARAT,
3046bb5d 1161 .xlevel = 0x80000008,
37507094
EH		 1162 .model_id = "Intel Core Processor (Haswell)",
1163 },
a356850b
EH		 1164 {
1165 .name = "Broadwell-noTSX",
1166 .level = 0xd,
1167 .vendor = CPUID_VENDOR_INTEL,
1168 .family = 6,
1169 .model = 61,
1170 .stepping = 2,
1171 .features[FEAT_1_EDX] =
1172 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1173 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1174 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1175 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1176 CPUID_DE | CPUID_FP87,
1177 .features[FEAT_1_ECX] =
1178 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1179 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1180 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1181 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1182 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1183 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1184 .features[FEAT_8000_0001_EDX] =
1185 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1186 CPUID_EXT2_SYSCALL,
1187 .features[FEAT_8000_0001_ECX] =
1188 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1189 .features[FEAT_7_0_EBX] =
1190 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1191 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1192 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1193 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1194 CPUID_7_0_EBX_SMAP,
1195 .features[FEAT_XSAVE] =
1196 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1197 .features[FEAT_6_EAX] =
1198 CPUID_6_EAX_ARAT,
3046bb5d 1199 .xlevel = 0x80000008,
a356850b
EH		 1200 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1201 },
ece01354
EH		 1202 {
1203 .name = "Broadwell",
1204 .level = 0xd,
1205 .vendor = CPUID_VENDOR_INTEL,
1206 .family = 6,
1207 .model = 61,
1208 .stepping = 2,
1209 .features[FEAT_1_EDX] =
b3a4f0b1 1210 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1211 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1212 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1213 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1214 CPUID_DE | CPUID_FP87,
1215 .features[FEAT_1_ECX] =
1216 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1217 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1218 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1219 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1220 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1221 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1222 .features[FEAT_8000_0001_EDX] =
1223 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1224 CPUID_EXT2_SYSCALL,
1225 .features[FEAT_8000_0001_ECX] =
1226 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1227 .features[FEAT_7_0_EBX] =
1228 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1229 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1230 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1231 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1232 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1233 .features[FEAT_XSAVE] =
1234 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1235 .features[FEAT_6_EAX] =
1236 CPUID_6_EAX_ARAT,
3046bb5d 1237 .xlevel = 0x80000008,
ece01354
EH		 1238 .model_id = "Intel Core Processor (Broadwell)",
1239 },
3eca4642
EH		 1240 {
1241 .name = "Opteron_G1",
1242 .level = 5,
99b88a17 1243 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1244 .family = 15,
1245 .model = 6,
1246 .stepping = 1,
0514ef2f 1247 .features[FEAT_1_EDX] =
b3a4f0b1 1248 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1249 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1250 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1251 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1252 CPUID_DE | CPUID_FP87,
0514ef2f 1253 .features[FEAT_1_ECX] =
27861ecc 1254 CPUID_EXT_SSE3,
0514ef2f 1255 .features[FEAT_8000_0001_EDX] =
27861ecc 1256 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1257 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1258 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1259 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1260 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1261 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1262 .xlevel = 0x80000008,
1263 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1264 },
1265 {
1266 .name = "Opteron_G2",
1267 .level = 5,
99b88a17 1268 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1269 .family = 15,
1270 .model = 6,
1271 .stepping = 1,
0514ef2f 1272 .features[FEAT_1_EDX] =
b3a4f0b1 1273 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1274 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1275 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1276 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1277 CPUID_DE | CPUID_FP87,
0514ef2f 1278 .features[FEAT_1_ECX] =
27861ecc 1279 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1280 .features[FEAT_8000_0001_EDX] =
27861ecc 1281 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1282 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1283 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1284 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1285 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1286 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1287 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1288 .features[FEAT_8000_0001_ECX] =
27861ecc 1289 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1290 .xlevel = 0x80000008,
1291 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1292 },
1293 {
1294 .name = "Opteron_G3",
1295 .level = 5,
99b88a17 1296 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1297 .family = 15,
1298 .model = 6,
1299 .stepping = 1,
0514ef2f 1300 .features[FEAT_1_EDX] =
b3a4f0b1 1301 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1302 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1303 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1304 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1305 CPUID_DE | CPUID_FP87,
0514ef2f 1306 .features[FEAT_1_ECX] =
27861ecc 1307 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1308 CPUID_EXT_SSE3,
0514ef2f 1309 .features[FEAT_8000_0001_EDX] =
27861ecc 1310 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1311 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1312 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1313 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1314 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1315 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1316 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1317 .features[FEAT_8000_0001_ECX] =
27861ecc 1318 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1319 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1320 .xlevel = 0x80000008,
1321 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1322 },
1323 {
1324 .name = "Opteron_G4",
1325 .level = 0xd,
99b88a17 1326 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1327 .family = 21,
1328 .model = 1,
1329 .stepping = 2,
0514ef2f 1330 .features[FEAT_1_EDX] =
b3a4f0b1 1331 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1332 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1333 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1334 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1335 CPUID_DE | CPUID_FP87,
0514ef2f 1336 .features[FEAT_1_ECX] =
27861ecc 1337 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1338 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1339 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1340 CPUID_EXT_SSE3,
0514ef2f 1341 .features[FEAT_8000_0001_EDX] =
27861ecc 1342 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1343 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1344 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1345 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1346 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1347 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1348 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1349 .features[FEAT_8000_0001_ECX] =
27861ecc 1350 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1351 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1352 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1353 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1354 /* no xsaveopt! */
3eca4642
EH		 1355 .xlevel = 0x8000001A,
1356 .model_id = "AMD Opteron 62xx class CPU",
1357 },
021941b9
AP		 1358 {
1359 .name = "Opteron_G5",
1360 .level = 0xd,
99b88a17 1361 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1362 .family = 21,
1363 .model = 2,
1364 .stepping = 0,
0514ef2f 1365 .features[FEAT_1_EDX] =
b3a4f0b1 1366 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1367 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1368 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1369 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1370 CPUID_DE | CPUID_FP87,
0514ef2f 1371 .features[FEAT_1_ECX] =
27861ecc 1372 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1373 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1374 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1375 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1376 .features[FEAT_8000_0001_EDX] =
27861ecc 1377 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1378 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1379 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1380 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1381 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1382 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1383 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1384 .features[FEAT_8000_0001_ECX] =
27861ecc 1385 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1386 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1387 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1388 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1389 /* no xsaveopt! */
021941b9
AP		 1390 .xlevel = 0x8000001A,
1391 .model_id = "AMD Opteron 63xx class CPU",
1392 },
c6dc6f63
AP		 1393};
1394
4d1b279b
EH		 1395static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1396 bool migratable_only);
1397
d940ee9b
EH		 1398#ifdef CONFIG_KVM
1399
c6dc6f63
AP		 1400static int cpu_x86_fill_model_id(char *str)
1401{
1402 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1403 int i;
1404
1405 for (i = 0; i < 3; i++) {
1406 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1407 memcpy(str + i * 16 + 0, &eax, 4);
1408 memcpy(str + i * 16 + 4, &ebx, 4);
1409 memcpy(str + i * 16 + 8, &ecx, 4);
1410 memcpy(str + i * 16 + 12, &edx, 4);
1411 }
1412 return 0;
1413}
1414
d940ee9b
EH		 1415static X86CPUDefinition host_cpudef;
1416
84f1b92f 1417static Property host_x86_cpu_properties[] = {
120eee7d 1418 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1419 DEFINE_PROP_END_OF_LIST()
1420};
1421
d940ee9b 1422/* class_init for the "host" CPU model
6e746f30 1423 *
d940ee9b 1424 * This function may be called before KVM is initialized.
6e746f30 1425 */
d940ee9b 1426static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1427{
84f1b92f 1428 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1429 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1430 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1431
d940ee9b 1432 xcc->kvm_required = true;
6e746f30 1433
c6dc6f63 1434 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1435 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1436
1437 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1438 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1439 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1440 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1441
d940ee9b 1442 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1443
d940ee9b
EH		 1444 xcc->cpu_def = &host_cpudef;
1445 host_cpudef.cache_info_passthrough = true;
1446
1447 /* level, xlevel, xlevel2, and the feature words are initialized on
1448 * instance_init, because they require KVM to be initialized.
1449 */
84f1b92f
EH		 1450
1451 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1452}
1453
1454static void host_x86_cpu_initfn(Object *obj)
1455{
1456 X86CPU *cpu = X86_CPU(obj);
1457 CPUX86State *env = &cpu->env;
1458 KVMState *s = kvm_state;
d940ee9b
EH		 1459
1460 assert(kvm_enabled());
1461
4d1b279b
EH		 1462 /* We can't fill the features array here because we don't know yet if
1463 * "migratable" is true or false.
1464 */
1465 cpu->host_features = true;
1466
d940ee9b
EH		 1467 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1468 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1469 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1470
d940ee9b 1471 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1472}
1473
d940ee9b
EH		 1474static const TypeInfo host_x86_cpu_type_info = {
1475 .name = X86_CPU_TYPE_NAME("host"),
1476 .parent = TYPE_X86_CPU,
1477 .instance_init = host_x86_cpu_initfn,
1478 .class_init = host_x86_cpu_class_init,
1479};
1480
1481#endif
1482
8459e396 1483static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1484{
8459e396 1485 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1486 int i;
1487
857aee33 1488 for (i = 0; i < 32; ++i) {
c6dc6f63 1489 if (1 << i & mask) {
bffd67b0 1490 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1491 assert(reg);
fefb41bf 1492 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1493 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1494 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1495 f->cpuid_eax, reg,
1496 f->feat_names[i] ? "." : "",
1497 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1498 }
857aee33 1499 }
c6dc6f63
AP		 1500}
1501
95b8519d
AF		 1502static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1503 const char *name, Error **errp)
1504{
1505 X86CPU *cpu = X86_CPU(obj);
1506 CPUX86State *env = &cpu->env;
1507 int64_t value;
1508
1509 value = (env->cpuid_version >> 8) & 0xf;
1510 if (value == 0xf) {
1511 value += (env->cpuid_version >> 20) & 0xff;
1512 }
1513 visit_type_int(v, &value, name, errp);
1514}
1515
71ad61d3
AF		 1516static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1517 const char *name, Error **errp)
ed5e1ec3 1518{
71ad61d3
AF		 1519 X86CPU *cpu = X86_CPU(obj);
1520 CPUX86State *env = &cpu->env;
1521 const int64_t min = 0;
1522 const int64_t max = 0xff + 0xf;
65cd9064 1523 Error *local_err = NULL;
71ad61d3
AF		 1524 int64_t value;
1525
65cd9064
MA		 1526 visit_type_int(v, &value, name, &local_err);
1527 if (local_err) {
1528 error_propagate(errp, local_err);
71ad61d3
AF		 1529 return;
1530 }
1531 if (value < min || value > max) {
c6bd8c70
MA		 1532 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1533 name ? name : "null", value, min, max);
71ad61d3
AF		 1534 return;
1535 }
1536
ed5e1ec3 1537 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1538 if (value > 0x0f) {
1539 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1540 } else {
71ad61d3 1541 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1542 }
1543}
1544
67e30c83
AF		 1545static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1546 const char *name, Error **errp)
1547{
1548 X86CPU *cpu = X86_CPU(obj);
1549 CPUX86State *env = &cpu->env;
1550 int64_t value;
1551
1552 value = (env->cpuid_version >> 4) & 0xf;
1553 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1554 visit_type_int(v, &value, name, errp);
1555}
1556
c5291a4f
AF		 1557static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1558 const char *name, Error **errp)
b0704cbd 1559{
c5291a4f
AF		 1560 X86CPU *cpu = X86_CPU(obj);
1561 CPUX86State *env = &cpu->env;
1562 const int64_t min = 0;
1563 const int64_t max = 0xff;
65cd9064 1564 Error *local_err = NULL;
c5291a4f
AF		 1565 int64_t value;
1566
65cd9064
MA		 1567 visit_type_int(v, &value, name, &local_err);
1568 if (local_err) {
1569 error_propagate(errp, local_err);
c5291a4f
AF		 1570 return;
1571 }
1572 if (value < min || value > max) {
c6bd8c70
MA		 1573 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1574 name ? name : "null", value, min, max);
c5291a4f
AF		 1575 return;
1576 }
1577
b0704cbd 1578 env->cpuid_version &= ~0xf00f0;
c5291a4f 1579 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1580}
1581
35112e41
AF		 1582static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1583 void *opaque, const char *name,
1584 Error **errp)
1585{
1586 X86CPU *cpu = X86_CPU(obj);
1587 CPUX86State *env = &cpu->env;
1588 int64_t value;
1589
1590 value = env->cpuid_version & 0xf;
1591 visit_type_int(v, &value, name, errp);
1592}
1593
036e2222
AF		 1594static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1595 void *opaque, const char *name,
1596 Error **errp)
38c3dc46 1597{
036e2222
AF		 1598 X86CPU *cpu = X86_CPU(obj);
1599 CPUX86State *env = &cpu->env;
1600 const int64_t min = 0;
1601 const int64_t max = 0xf;
65cd9064 1602 Error *local_err = NULL;
036e2222
AF		 1603 int64_t value;
1604
65cd9064
MA		 1605 visit_type_int(v, &value, name, &local_err);
1606 if (local_err) {
1607 error_propagate(errp, local_err);
036e2222
AF		 1608 return;
1609 }
1610 if (value < min || value > max) {
c6bd8c70
MA		 1611 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1612 name ? name : "null", value, min, max);
036e2222
AF		 1613 return;
1614 }
1615
38c3dc46 1616 env->cpuid_version &= ~0xf;
036e2222 1617 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1618}
1619
d480e1af
AF		 1620static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1621{
1622 X86CPU *cpu = X86_CPU(obj);
1623 CPUX86State *env = &cpu->env;
1624 char *value;
d480e1af 1625
e42a92ae 1626 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1627 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1628 env->cpuid_vendor3);
d480e1af
AF		 1629 return value;
1630}
1631
1632static void x86_cpuid_set_vendor(Object *obj, const char *value,
1633 Error **errp)
1634{
1635 X86CPU *cpu = X86_CPU(obj);
1636 CPUX86State *env = &cpu->env;
1637 int i;
1638
9df694ee 1639 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1640 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1641 return;
1642 }
1643
1644 env->cpuid_vendor1 = 0;
1645 env->cpuid_vendor2 = 0;
1646 env->cpuid_vendor3 = 0;
1647 for (i = 0; i < 4; i++) {
1648 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1649 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1650 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1651 }
d480e1af
AF		 1652}
1653
63e886eb
AF		 1654static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1655{
1656 X86CPU *cpu = X86_CPU(obj);
1657 CPUX86State *env = &cpu->env;
1658 char *value;
1659 int i;
1660
1661 value = g_malloc(48 + 1);
1662 for (i = 0; i < 48; i++) {
1663 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1664 }
1665 value[48] = '\0';
1666 return value;
1667}
1668
938d4c25
AF		 1669static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1670 Error **errp)
dcce6675 1671{
938d4c25
AF		 1672 X86CPU *cpu = X86_CPU(obj);
1673 CPUX86State *env = &cpu->env;
dcce6675
AF		 1674 int c, len, i;
1675
1676 if (model_id == NULL) {
1677 model_id = "";
1678 }
1679 len = strlen(model_id);
d0a6acf4 1680 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1681 for (i = 0; i < 48; i++) {
1682 if (i >= len) {
1683 c = '\0';
1684 } else {
1685 c = (uint8_t)model_id[i];
1686 }
1687 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1688 }
1689}
1690
89e48965
AF		 1691static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1692 const char *name, Error **errp)
1693{
1694 X86CPU *cpu = X86_CPU(obj);
1695 int64_t value;
1696
1697 value = cpu->env.tsc_khz * 1000;
1698 visit_type_int(v, &value, name, errp);
1699}
1700
1701static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1702 const char *name, Error **errp)
1703{
1704 X86CPU *cpu = X86_CPU(obj);
1705 const int64_t min = 0;
2e84849a 1706 const int64_t max = INT64_MAX;
65cd9064 1707 Error *local_err = NULL;
89e48965
AF		 1708 int64_t value;
1709
65cd9064
MA		 1710 visit_type_int(v, &value, name, &local_err);
1711 if (local_err) {
1712 error_propagate(errp, local_err);
89e48965
AF		 1713 return;
1714 }
1715 if (value < min || value > max) {
c6bd8c70
MA		 1716 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1717 name ? name : "null", value, min, max);
89e48965
AF		 1718 return;
1719 }
1720
1721 cpu->env.tsc_khz = value / 1000;
1722}
1723
31050930
IM		 1724static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1725 const char *name, Error **errp)
1726{
1727 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1728 int64_t value = cpu->apic_id;
31050930
IM		 1729
1730 visit_type_int(v, &value, name, errp);
1731}
1732
1733static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1734 const char *name, Error **errp)
1735{
1736 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1737 DeviceState *dev = DEVICE(obj);
31050930
IM		 1738 const int64_t min = 0;
1739 const int64_t max = UINT32_MAX;
1740 Error *error = NULL;
1741 int64_t value;
1742
8d6d4980
IM		 1743 if (dev->realized) {
1744 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1745 "it was realized", name, object_get_typename(obj));
1746 return;
1747 }
1748
31050930
IM		 1749 visit_type_int(v, &value, name, &error);
1750 if (error) {
1751 error_propagate(errp, error);
1752 return;
1753 }
1754 if (value < min || value > max) {
1755 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1756 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1757 object_get_typename(obj), name, value, min, max);
1758 return;
1759 }
1760
7e72a45c 1761 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1762 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1763 return;
1764 }
7e72a45c 1765 cpu->apic_id = value;
31050930
IM		 1766}
1767
7e5292b5 1768/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1769static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1770 const char *name, Error **errp)
1771{
7e5292b5 1772 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1773 FeatureWord w;
1774 Error *err = NULL;
1775 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1776 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1777 X86CPUFeatureWordInfoList *list = NULL;
1778
1779 for (w = 0; w < FEATURE_WORDS; w++) {
1780 FeatureWordInfo *wi = &feature_word_info[w];
1781 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1782 qwi->cpuid_input_eax = wi->cpuid_eax;
1783 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1784 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1785 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1786 qwi->features = array[w];
8e8aba50
EH		 1787
1788 /* List will be in reverse order, but order shouldn't matter */
1789 list_entries[w].next = list;
1790 list_entries[w].value = &word_infos[w];
1791 list = &list_entries[w];
1792 }
1793
1794 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1795 error_propagate(errp, err);
1796}
1797
c8f0f88e
IM		 1798static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1799 const char *name, Error **errp)
1800{
1801 X86CPU *cpu = X86_CPU(obj);
1802 int64_t value = cpu->hyperv_spinlock_attempts;
1803
1804 visit_type_int(v, &value, name, errp);
1805}
1806
1807static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1808 const char *name, Error **errp)
1809{
1810 const int64_t min = 0xFFF;
1811 const int64_t max = UINT_MAX;
1812 X86CPU *cpu = X86_CPU(obj);
1813 Error *err = NULL;
1814 int64_t value;
1815
1816 visit_type_int(v, &value, name, &err);
1817 if (err) {
1818 error_propagate(errp, err);
1819 return;
1820 }
1821
1822 if (value < min || value > max) {
1823 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1824 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1825 object_get_typename(obj), name ? name : "null",
1826 value, min, max);
c8f0f88e
IM		 1827 return;
1828 }
1829 cpu->hyperv_spinlock_attempts = value;
1830}
1831
1832static PropertyInfo qdev_prop_spinlocks = {
1833 .name = "int",
1834 .get = x86_get_hv_spinlocks,
1835 .set = x86_set_hv_spinlocks,
1836};
1837
72ac2e87
IM		 1838/* Convert all '_' in a feature string option name to '-', to make feature
1839 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1840 */
1841static inline void feat2prop(char *s)
1842{
1843 while ((s = strchr(s, '_'))) {
1844 *s = '-';
1845 }
1846}
1847
8f961357
EH		 1848/* Parse "+feature,-feature,feature=foo" CPU feature string
1849 */
94a444b2
AF		 1850static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1851 Error **errp)
8f961357 1852{
94a444b2 1853 X86CPU *cpu = X86_CPU(cs);
8f961357 1854 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1855 FeatureWord w;
8f961357 1856 /* Features to be added */
077c68c3 1857 FeatureWordArray plus_features = { 0 };
8f961357 1858 /* Features to be removed */
5ef57876 1859 FeatureWordArray minus_features = { 0 };
8f961357 1860 uint32_t numvalue;
a91987c2 1861 CPUX86State *env = &cpu->env;
94a444b2 1862 Error *local_err = NULL;
8f961357 1863
8f961357 1864 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1865
1866 while (featurestr) {
1867 char *val;
1868 if (featurestr[0] == '+') {
c00c94ab 1869 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1870 } else if (featurestr[0] == '-') {
c00c94ab 1871 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1872 } else if ((val = strchr(featurestr, '='))) {
1873 *val = 0; val++;
72ac2e87 1874 feat2prop(featurestr);
d024d209 1875 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1876 char *err;
a91987c2
IM		 1877 char num[32];
1878
c6dc6f63
AP		 1879 numvalue = strtoul(val, &err, 0);
1880 if (!*val || *err) {
6b1dd54b
PB		 1881 error_setg(errp, "bad numerical value %s", val);
1882 return;
c6dc6f63
AP		 1883 }
1884 if (numvalue < 0x80000000) {
94a444b2
AF		 1885 error_report("xlevel value shall always be >= 0x80000000"
1886 ", fixup will be removed in future versions");
2f7a21c4 1887 numvalue += 0x80000000;
c6dc6f63 1888 }
a91987c2 1889 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1890 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1891 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1892 int64_t tsc_freq;
1893 char *err;
a91987c2 1894 char num[32];
b862d1fe 1895
4677bb40
MAL		 1896 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1897 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1898 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1899 error_setg(errp, "bad numerical value %s", val);
1900 return;
b862d1fe 1901 }
a91987c2 1902 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1903 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1904 &local_err);
72ac2e87 1905 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1906 char *err;
92067bf4 1907 const int min = 0xFFF;
c8f0f88e 1908 char num[32];
28f52cc0
VR		 1909 numvalue = strtoul(val, &err, 0);
1910 if (!*val || *err) {
6b1dd54b
PB		 1911 error_setg(errp, "bad numerical value %s", val);
1912 return;
28f52cc0 1913 }
92067bf4 1914 if (numvalue < min) {
94a444b2 1915 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1916 ", fixup will be removed in future versions",
1917 min);
92067bf4
IM		 1918 numvalue = min;
1919 }
c8f0f88e 1920 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1921 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1922 } else {
94a444b2 1923 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1924 }
c6dc6f63 1925 } else {
258f5abe 1926 feat2prop(featurestr);
94a444b2 1927 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1928 }
94a444b2
AF		 1929 if (local_err) {
1930 error_propagate(errp, local_err);
6b1dd54b 1931 return;
c6dc6f63
AP		 1932 }
1933 featurestr = strtok(NULL, ",");
1934 }
e1c224b4 1935
4d1b279b
EH		 1936 if (cpu->host_features) {
1937 for (w = 0; w < FEATURE_WORDS; w++) {
1938 env->features[w] =
1939 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1940 }
1941 }
1942
e1c224b4
EH		 1943 for (w = 0; w < FEATURE_WORDS; w++) {
1944 env->features[w] |= plus_features[w];
1945 env->features[w] &= ~minus_features[w];
1946 }
c6dc6f63
AP		 1947}
1948
8c3329e5 1949/* Print all cpuid feature names in featureset
c6dc6f63 1950 */
8c3329e5 1951static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1952{
8c3329e5
EH		 1953 int bit;
1954 bool first = true;
1955
1956 for (bit = 0; bit < 32; bit++) {
1957 if (featureset[bit]) {
1958 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1959 first = false;
c6dc6f63 1960 }
8c3329e5 1961 }
c6dc6f63
AP		 1962}
1963
e916cbf8
PM		 1964/* generate CPU information. */
1965void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1966{
9576de75 1967 X86CPUDefinition *def;
c6dc6f63 1968 char buf[256];
7fc9b714 1969 int i;
c6dc6f63 1970
7fc9b714
AF		 1971 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1972 def = &builtin_x86_defs[i];
c04321b3 1973 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1974 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1975 }
21ad7789
JK		 1976#ifdef CONFIG_KVM
1977 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1978 "KVM processor with all supported host features "
1979 "(only available in KVM mode)");
1980#endif
1981
6cdf8854 1982 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1983 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1984 FeatureWordInfo *fw = &feature_word_info[i];
1985
8c3329e5
EH		 1986 (*cpu_fprintf)(f, " ");
1987 listflags(f, cpu_fprintf, fw->feat_names);
1988 (*cpu_fprintf)(f, "\n");
3af60be2 1989 }
c6dc6f63
AP		 1990}
1991
76b64a7a 1992CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1993{
1994 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 1995 X86CPUDefinition *def;
7fc9b714 1996 int i;
e3966126 1997
7fc9b714 1998 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 1999 CpuDefinitionInfoList *entry;
2000 CpuDefinitionInfo *info;
2001
7fc9b714 2002 def = &builtin_x86_defs[i];
e3966126
AL		 2003 info = g_malloc0(sizeof(*info));
2004 info->name = g_strdup(def->name);
2005
2006 entry = g_malloc0(sizeof(*entry));
2007 entry->value = info;
2008 entry->next = cpu_list;
2009 cpu_list = entry;
2010 }
2011
2012 return cpu_list;
2013}
2014
84f1b92f
EH		 2015static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2016 bool migratable_only)
27418adf
EH		 2017{
2018 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2019 uint32_t r;
27418adf 2020
fefb41bf 2021 if (kvm_enabled()) {
84f1b92f
EH		 2022 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2023 wi->cpuid_ecx,
2024 wi->cpuid_reg);
fefb41bf 2025 } else if (tcg_enabled()) {
84f1b92f 2026 r = wi->tcg_features;
fefb41bf
EH		 2027 } else {
2028 return ~0;
2029 }
84f1b92f
EH		 2030 if (migratable_only) {
2031 r &= x86_cpu_get_migratable_flags(w);
2032 }
2033 return r;
27418adf
EH		 2034}
2035
51f63aed
EH		 2036/*
2037 * Filters CPU feature words based on host availability of each feature.
2038 *
51f63aed
EH		 2039 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2040 */
27418adf 2041static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2042{
2043 CPUX86State *env = &cpu->env;
bd87d2a2 2044 FeatureWord w;
51f63aed
EH		 2045 int rv = 0;
2046
bd87d2a2 2047 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2048 uint32_t host_feat =
2049 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2050 uint32_t requested_features = env->features[w];
2051 env->features[w] &= host_feat;
2052 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2053 if (cpu->filtered_features[w]) {
2054 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2055 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2056 }
2057 rv = 1;
2058 }
bd87d2a2 2059 }
51f63aed
EH		 2060
2061 return rv;
bc74b7db 2062}
bc74b7db 2063
d940ee9b 2064/* Load data from X86CPUDefinition
c080e30e 2065 */
d940ee9b 2066static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2067{
61dcd775 2068 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2069 const char *vendor;
2070 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2071 FeatureWord w;
c6dc6f63 2072
2d64255b
AF		 2073 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2074 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2075 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2076 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2077 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2078 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
787aaf57 2079 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2080 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2081 for (w = 0; w < FEATURE_WORDS; w++) {
2082 env->features[w] = def->features[w];
2083 }
82beb536 2084
9576de75 2085 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2086 if (kvm_enabled()) {
5fcca9ff
EH		 2087 FeatureWord w;
2088 for (w = 0; w < FEATURE_WORDS; w++) {
2089 env->features[w] |= kvm_default_features[w];
136a7e9a 2090 env->features[w] &= ~kvm_default_unset_features[w];
5fcca9ff 2091 }
82beb536 2092 }
5fcca9ff 2093
82beb536 2094 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2095
2096 /* sysenter isn't supported in compatibility mode on AMD,
2097 * syscall isn't supported in compatibility mode on Intel.
2098 * Normally we advertise the actual CPU vendor, but you can
2099 * override this using the 'vendor' property if you want to use
2100 * KVM's sysenter/syscall emulation in compatibility mode and
2101 * when doing cross vendor migration
2102 */
74f54bc4 2103 vendor = def->vendor;
7c08db30
EH		 2104 if (kvm_enabled()) {
2105 uint32_t ebx = 0, ecx = 0, edx = 0;
2106 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2107 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2108 vendor = host_vendor;
2109 }
2110
2111 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2112
c6dc6f63
AP		 2113}
2114
e1570d00 2115X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2116{
2d64255b 2117 X86CPU *cpu = NULL;
d940ee9b 2118 X86CPUClass *xcc;
500050d1 2119 ObjectClass *oc;
2d64255b
AF		 2120 gchar **model_pieces;
2121 char *name, *features;
5c3c6a68
AF		 2122 Error *error = NULL;
2123
2d64255b
AF		 2124 model_pieces = g_strsplit(cpu_model, ",", 2);
2125 if (!model_pieces[0]) {
2126 error_setg(&error, "Invalid/empty CPU model name");
2127 goto out;
2128 }
2129 name = model_pieces[0];
2130 features = model_pieces[1];
2131
500050d1
AF		 2132 oc = x86_cpu_class_by_name(name);
2133 if (oc == NULL) {
2134 error_setg(&error, "Unable to find CPU definition: %s", name);
2135 goto out;
2136 }
d940ee9b
EH		 2137 xcc = X86_CPU_CLASS(oc);
2138
2139 if (xcc->kvm_required && !kvm_enabled()) {
2140 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2141 goto out;
2142 }
2143
d940ee9b
EH		 2144 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2145
94a444b2 2146 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2147 if (error) {
2148 goto out;
5c3c6a68
AF		 2149 }
2150
7f833247 2151out:
cd7b87ff
AF		 2152 if (error != NULL) {
2153 error_propagate(errp, error);
500050d1
AF		 2154 if (cpu) {
2155 object_unref(OBJECT(cpu));
2156 cpu = NULL;
2157 }
cd7b87ff 2158 }
7f833247
IM		 2159 g_strfreev(model_pieces);
2160 return cpu;
2161}
2162
0856579c 2163X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2164{
2165 Error *error = NULL;
2166 X86CPU *cpu;
2167
e1570d00 2168 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2169 if (error) {
0856579c 2170 goto out;
9c235e83 2171 }
7f833247 2172
7f833247 2173 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2174
0856579c
PM		 2175out:
2176 if (error) {
2177 error_report_err(error);
2178 if (cpu != NULL) {
2179 object_unref(OBJECT(cpu));
2180 cpu = NULL;
2181 }
18b0e4e7 2182 }
0856579c 2183 return cpu;
5c3c6a68
AF		 2184}
2185
d940ee9b
EH		 2186static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2187{
2188 X86CPUDefinition *cpudef = data;
2189 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2190
2191 xcc->cpu_def = cpudef;
2192}
2193
2194static void x86_register_cpudef_type(X86CPUDefinition *def)
2195{
2196 char *typename = x86_cpu_type_name(def->name);
2197 TypeInfo ti = {
2198 .name = typename,
2199 .parent = TYPE_X86_CPU,
2200 .class_init = x86_cpu_cpudef_class_init,
2201 .class_data = def,
2202 };
2203
2204 type_register(&ti);
2205 g_free(typename);
2206}
2207
c6dc6f63 2208#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2209
0e26b7b8
BS		 2210void cpu_clear_apic_feature(CPUX86State *env)
2211{
0514ef2f 2212 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2213}
2214
c6dc6f63
AP		 2215#endif /* !CONFIG_USER_ONLY */
2216
c04321b3 2217/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2218 */
2219void x86_cpudef_setup(void)
2220{
93bfef4c
CV		 2221 int i, j;
2222 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2223
2224 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2225 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2226
2227 /* Look for specific "cpudef" models that */
09faecf2 2228 /* have the QEMU version in .model_id */
93bfef4c 2229 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2230 if (strcmp(model_with_versions[j], def->name) == 0) {
2231 pstrcpy(def->model_id, sizeof(def->model_id),
2232 "QEMU Virtual CPU version ");
2233 pstrcat(def->model_id, sizeof(def->model_id),
2234 qemu_get_version());
93bfef4c
CV		 2235 break;
2236 }
2237 }
c6dc6f63 2238 }
c6dc6f63
AP		 2239}
2240
c6dc6f63
AP		 2241void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2242 uint32_t *eax, uint32_t *ebx,
2243 uint32_t *ecx, uint32_t *edx)
2244{
a60f24b5
AF		 2245 X86CPU *cpu = x86_env_get_cpu(env);
2246 CPUState *cs = CPU(cpu);
2247
c6dc6f63
AP		 2248 /* test if maximum index reached */
2249 if (index & 0x80000000) {
b3baa152
BW		 2250 if (index > env->cpuid_xlevel) {
2251 if (env->cpuid_xlevel2 > 0) {
2252 /* Handle the Centaur's CPUID instruction. */
2253 if (index > env->cpuid_xlevel2) {
2254 index = env->cpuid_xlevel2;
2255 } else if (index < 0xC0000000) {
2256 index = env->cpuid_xlevel;
2257 }
2258 } else {
57f26ae7
EH		 2259 /* Intel documentation states that invalid EAX input will
2260 * return the same information as EAX=cpuid_level
2261 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2262 */
2263 index = env->cpuid_level;
b3baa152
BW		 2264 }
2265 }
c6dc6f63
AP		 2266 } else {
2267 if (index > env->cpuid_level)
2268 index = env->cpuid_level;
2269 }
2270
2271 switch(index) {
2272 case 0:
2273 *eax = env->cpuid_level;
5eb2f7a4
EH		 2274 *ebx = env->cpuid_vendor1;
2275 *edx = env->cpuid_vendor2;
2276 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2277 break;
2278 case 1:
2279 *eax = env->cpuid_version;
7e72a45c
EH		 2280 *ebx = (cpu->apic_id << 24) |
2281 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2282 *ecx = env->features[FEAT_1_ECX];
2283 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2284 if (cs->nr_cores * cs->nr_threads > 1) {
2285 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2286 *edx |= 1 << 28; /* HTT bit */
2287 }
2288 break;
2289 case 2:
2290 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2291 if (cpu->cache_info_passthrough) {
2292 host_cpuid(index, 0, eax, ebx, ecx, edx);
2293 break;
2294 }
5e891bf8 2295 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2296 *ebx = 0;
2297 *ecx = 0;
5e891bf8
EH		 2298 *edx = (L1D_DESCRIPTOR << 16) | \
2299 (L1I_DESCRIPTOR << 8) | \
2300 (L2_DESCRIPTOR);
c6dc6f63
AP		 2301 break;
2302 case 4:
2303 /* cache info: needed for Core compatibility */
787aaf57
BC		 2304 if (cpu->cache_info_passthrough) {
2305 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2306 *eax &= ~0xFC000000;
c6dc6f63 2307 } else {
2f7a21c4 2308 *eax = 0;
76c2975a 2309 switch (count) {
c6dc6f63 2310 case 0: /* L1 dcache info */
5e891bf8
EH		 2311 *eax |= CPUID_4_TYPE_DCACHE | \
2312 CPUID_4_LEVEL(1) | \
2313 CPUID_4_SELF_INIT_LEVEL;
2314 *ebx = (L1D_LINE_SIZE - 1) | \
2315 ((L1D_PARTITIONS - 1) << 12) | \
2316 ((L1D_ASSOCIATIVITY - 1) << 22);
2317 *ecx = L1D_SETS - 1;
2318 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2319 break;
2320 case 1: /* L1 icache info */
5e891bf8
EH		 2321 *eax |= CPUID_4_TYPE_ICACHE | \
2322 CPUID_4_LEVEL(1) | \
2323 CPUID_4_SELF_INIT_LEVEL;
2324 *ebx = (L1I_LINE_SIZE - 1) | \
2325 ((L1I_PARTITIONS - 1) << 12) | \
2326 ((L1I_ASSOCIATIVITY - 1) << 22);
2327 *ecx = L1I_SETS - 1;
2328 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2329 break;
2330 case 2: /* L2 cache info */
5e891bf8
EH		 2331 *eax |= CPUID_4_TYPE_UNIFIED | \
2332 CPUID_4_LEVEL(2) | \
2333 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2334 if (cs->nr_threads > 1) {
2335 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2336 }
5e891bf8
EH		 2337 *ebx = (L2_LINE_SIZE - 1) | \
2338 ((L2_PARTITIONS - 1) << 12) | \
2339 ((L2_ASSOCIATIVITY - 1) << 22);
2340 *ecx = L2_SETS - 1;
2341 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2342 break;
2343 default: /* end of info */
2344 *eax = 0;
2345 *ebx = 0;
2346 *ecx = 0;
2347 *edx = 0;
2348 break;
76c2975a
PB		 2349 }
2350 }
2351
2352 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2353 if ((*eax & 31) && cs->nr_cores > 1) {
2354 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2355 }
2356 break;
2357 case 5:
2358 /* mwait info: needed for Core compatibility */
2359 *eax = 0; /* Smallest monitor-line size in bytes */
2360 *ebx = 0; /* Largest monitor-line size in bytes */
2361 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2362 *edx = 0;
2363 break;
2364 case 6:
2365 /* Thermal and Power Leaf */
28b8e4d0 2366 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2367 *ebx = 0;
2368 *ecx = 0;
2369 *edx = 0;
2370 break;
f7911686 2371 case 7:
13526728
EH		 2372 /* Structured Extended Feature Flags Enumeration Leaf */
2373 if (count == 0) {
2374 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2375 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2376 *ecx = 0; /* Reserved */
2377 *edx = 0; /* Reserved */
f7911686
YW		 2378 } else {
2379 *eax = 0;
2380 *ebx = 0;
2381 *ecx = 0;
2382 *edx = 0;
2383 }
2384 break;
c6dc6f63
AP		 2385 case 9:
2386 /* Direct Cache Access Information Leaf */
2387 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2388 *ebx = 0;
2389 *ecx = 0;
2390 *edx = 0;
2391 break;
2392 case 0xA:
2393 /* Architectural Performance Monitoring Leaf */
9337e3b6 2394 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2395 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2396
2397 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2398 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2399 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2400 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2401 } else {
2402 *eax = 0;
2403 *ebx = 0;
2404 *ecx = 0;
2405 *edx = 0;
2406 }
c6dc6f63 2407 break;
2560f19f
PB		 2408 case 0xD: {
2409 KVMState *s = cs->kvm_state;
2410 uint64_t kvm_mask;
2411 int i;
2412
51e49430 2413 /* Processor Extended State */
2560f19f
PB		 2414 *eax = 0;
2415 *ebx = 0;
2416 *ecx = 0;
2417 *edx = 0;
2418 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2419 break;
2420 }
2560f19f
PB		 2421 kvm_mask =
2422 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2423 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2424
2560f19f
PB		 2425 if (count == 0) {
2426 *ecx = 0x240;
2427 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2428 const ExtSaveArea *esa = &ext_save_areas[i];
2429 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2430 (kvm_mask & (1 << i)) != 0) {
2431 if (i < 32) {
2432 *eax |= 1 << i;
2433 } else {
2434 *edx |= 1 << (i - 32);
2435 }
2436 *ecx = MAX(*ecx, esa->offset + esa->size);
2437 }
2438 }
2439 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2440 *ebx = *ecx;
2441 } else if (count == 1) {
0bb0b2d2 2442 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2443 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2444 const ExtSaveArea *esa = &ext_save_areas[count];
2445 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2446 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2447 *eax = esa->size;
2448 *ebx = esa->offset;
2560f19f 2449 }
51e49430
SY		 2450 }
2451 break;
2560f19f 2452 }
c6dc6f63
AP		 2453 case 0x80000000:
2454 *eax = env->cpuid_xlevel;
2455 *ebx = env->cpuid_vendor1;
2456 *edx = env->cpuid_vendor2;
2457 *ecx = env->cpuid_vendor3;
2458 break;
2459 case 0x80000001:
2460 *eax = env->cpuid_version;
2461 *ebx = 0;
0514ef2f
EH		 2462 *ecx = env->features[FEAT_8000_0001_ECX];
2463 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2464
2465 /* The Linux kernel checks for the CMPLegacy bit and
2466 * discards multiple thread information if it is set.
2467 * So dont set it here for Intel to make Linux guests happy.
2468 */
ce3960eb 2469 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2470 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2471 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2472 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2473 *ecx |= 1 << 1; /* CmpLegacy bit */
2474 }
2475 }
c6dc6f63
AP		 2476 break;
2477 case 0x80000002:
2478 case 0x80000003:
2479 case 0x80000004:
2480 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2481 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2482 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2483 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2484 break;
2485 case 0x80000005:
2486 /* cache info (L1 cache) */
787aaf57
BC		 2487 if (cpu->cache_info_passthrough) {
2488 host_cpuid(index, 0, eax, ebx, ecx, edx);
2489 break;
2490 }
5e891bf8
EH		 2491 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2492 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2493 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2494 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2495 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2496 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2497 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2498 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2499 break;
2500 case 0x80000006:
2501 /* cache info (L2 cache) */
787aaf57
BC		 2502 if (cpu->cache_info_passthrough) {
2503 host_cpuid(index, 0, eax, ebx, ecx, edx);
2504 break;
2505 }
5e891bf8
EH		 2506 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2507 (L2_DTLB_2M_ENTRIES << 16) | \
2508 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2509 (L2_ITLB_2M_ENTRIES);
2510 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2511 (L2_DTLB_4K_ENTRIES << 16) | \
2512 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2513 (L2_ITLB_4K_ENTRIES);
2514 *ecx = (L2_SIZE_KB_AMD << 16) | \
2515 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2516 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2517 *edx = ((L3_SIZE_KB/512) << 18) | \
2518 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2519 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2520 break;
303752a9
MT		 2521 case 0x80000007:
2522 *eax = 0;
2523 *ebx = 0;
2524 *ecx = 0;
2525 *edx = env->features[FEAT_8000_0007_EDX];
2526 break;
c6dc6f63
AP		 2527 case 0x80000008:
2528 /* virtual & phys address size in low 2 bytes. */
2529/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2530 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2531 /* 64 bit processor */
2532/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2533 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2534 } else {
0514ef2f 2535 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2536 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2537 } else {
c6dc6f63 2538 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2539 }
c6dc6f63
AP		 2540 }
2541 *ebx = 0;
2542 *ecx = 0;
2543 *edx = 0;
ce3960eb
AF		 2544 if (cs->nr_cores * cs->nr_threads > 1) {
2545 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2546 }
2547 break;
2548 case 0x8000000A:
0514ef2f 2549 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2550 *eax = 0x00000001; /* SVM Revision */
2551 *ebx = 0x00000010; /* nr of ASIDs */
2552 *ecx = 0;
0514ef2f 2553 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2554 } else {
2555 *eax = 0;
2556 *ebx = 0;
2557 *ecx = 0;
2558 *edx = 0;
2559 }
c6dc6f63 2560 break;
b3baa152
BW		 2561 case 0xC0000000:
2562 *eax = env->cpuid_xlevel2;
2563 *ebx = 0;
2564 *ecx = 0;
2565 *edx = 0;
2566 break;
2567 case 0xC0000001:
2568 /* Support for VIA CPU's CPUID instruction */
2569 *eax = env->cpuid_version;
2570 *ebx = 0;
2571 *ecx = 0;
0514ef2f 2572 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2573 break;
2574 case 0xC0000002:
2575 case 0xC0000003:
2576 case 0xC0000004:
2577 /* Reserved for the future, and now filled with zero */
2578 *eax = 0;
2579 *ebx = 0;
2580 *ecx = 0;
2581 *edx = 0;
2582 break;
c6dc6f63
AP		 2583 default:
2584 /* reserved values: zero */
2585 *eax = 0;
2586 *ebx = 0;
2587 *ecx = 0;
2588 *edx = 0;
2589 break;
2590 }
2591}
5fd2087a
AF		 2592
2593/* CPUClass::reset() */
2594static void x86_cpu_reset(CPUState *s)
2595{
2596 X86CPU *cpu = X86_CPU(s);
2597 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2598 CPUX86State *env = &cpu->env;
c1958aea
AF		 2599 int i;
2600
5fd2087a
AF		 2601 xcc->parent_reset(s);
2602
43175fa9 2603 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2604
00c8cb0a 2605 tlb_flush(s, 1);
c1958aea
AF		 2606
2607 env->old_exception = -1;
2608
2609 /* init to reset state */
2610
2611#ifdef CONFIG_SOFTMMU
2612 env->hflags |= HF_SOFTMMU_MASK;
2613#endif
2614 env->hflags2 |= HF2_GIF_MASK;
2615
2616 cpu_x86_update_cr0(env, 0x60000010);
2617 env->a20_mask = ~0x0;
2618 env->smbase = 0x30000;
2619
2620 env->idt.limit = 0xffff;
2621 env->gdt.limit = 0xffff;
2622 env->ldt.limit = 0xffff;
2623 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2624 env->tr.limit = 0xffff;
2625 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2626
2627 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2628 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2629 DESC_R_MASK | DESC_A_MASK);
2630 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2631 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2632 DESC_A_MASK);
2633 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2634 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2635 DESC_A_MASK);
2636 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2637 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2638 DESC_A_MASK);
2639 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2640 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2641 DESC_A_MASK);
2642 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2643 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2644 DESC_A_MASK);
2645
2646 env->eip = 0xfff0;
2647 env->regs[R_EDX] = env->cpuid_version;
2648
2649 env->eflags = 0x2;
2650
2651 /* FPU init */
2652 for (i = 0; i < 8; i++) {
2653 env->fptags[i] = 1;
2654 }
5bde1407 2655 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2656
2657 env->mxcsr = 0x1f80;
c74f41bb 2658 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2659
2660 env->pat = 0x0007040600070406ULL;
2661 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2662
2663 memset(env->dr, 0, sizeof(env->dr));
2664 env->dr[6] = DR6_FIXED_1;
2665 env->dr[7] = DR7_FIXED_1;
b3310ab3 2666 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2667 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2668
05e7e819 2669 env->xcr0 = 1;
0522604b 2670
9db2efd9
AW		 2671 /*
2672 * SDM 11.11.5 requires:
2673 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2674 * - IA32_MTRR_PHYSMASKn.V = 0
2675 * All other bits are undefined. For simplification, zero it all.
2676 */
2677 env->mtrr_deftype = 0;
2678 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2679 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2680
dd673288
IM		 2681#if !defined(CONFIG_USER_ONLY)
2682 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2683 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2684
259186a7 2685 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2686
2687 if (kvm_enabled()) {
2688 kvm_arch_reset_vcpu(cpu);
2689 }
dd673288 2690#endif
5fd2087a
AF		 2691}
2692
dd673288
IM		 2693#ifndef CONFIG_USER_ONLY
2694bool cpu_is_bsp(X86CPU *cpu)
2695{
02e51483 2696 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2697}
65dee380
IM		 2698
2699/* TODO: remove me, when reset over QOM tree is implemented */
2700static void x86_cpu_machine_reset_cb(void *opaque)
2701{
2702 X86CPU *cpu = opaque;
2703 cpu_reset(CPU(cpu));
2704}
dd673288
IM		 2705#endif
2706
de024815
AF		 2707static void mce_init(X86CPU *cpu)
2708{
2709 CPUX86State *cenv = &cpu->env;
2710 unsigned int bank;
2711
2712 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2713 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2714 (CPUID_MCE | CPUID_MCA)) {
2715 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2716 cenv->mcg_ctl = ~(uint64_t)0;
2717 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2718 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2719 }
2720 }
2721}
2722
bdeec802 2723#ifndef CONFIG_USER_ONLY
d3c64d6a 2724static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2725{
53a89e26 2726 DeviceState *dev = DEVICE(cpu);
449994eb 2727 APICCommonState *apic;
bdeec802
IM		 2728 const char *apic_type = "apic";
2729
2730 if (kvm_irqchip_in_kernel()) {
2731 apic_type = "kvm-apic";
2732 } else if (xen_enabled()) {
2733 apic_type = "xen-apic";
2734 }
2735
02e51483
CF		 2736 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2737 if (cpu->apic_state == NULL) {
bdeec802
IM		 2738 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2739 return;
2740 }
2741
2742 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2743 OBJECT(cpu->apic_state), NULL);
7e72a45c 2744 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2745 /* TODO: convert to link<> */
02e51483 2746 apic = APIC_COMMON(cpu->apic_state);
60671e58 2747 apic->cpu = cpu;
d3c64d6a
IM		 2748}
2749
2750static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2751{
02e51483 2752 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2753 return;
2754 }
6e8e2651
MA		 2755 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2756 errp);
bdeec802 2757}
f809c605
PB		 2758
2759static void x86_cpu_machine_done(Notifier *n, void *unused)
2760{
2761 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2762 MemoryRegion *smram =
2763 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2764
2765 if (smram) {
2766 cpu->smram = g_new(MemoryRegion, 1);
2767 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2768 smram, 0, 1ull << 32);
2769 memory_region_set_enabled(cpu->smram, false);
2770 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2771 }
2772}
d3c64d6a
IM		 2773#else
2774static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2775{
2776}
bdeec802
IM		 2777#endif
2778
e48638fd
WH		 2779
2780#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2781 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2782 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2783#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2784 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2785 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2786static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2787{
14a10fc3 2788 CPUState *cs = CPU(dev);
2b6f294c
AF		 2789 X86CPU *cpu = X86_CPU(dev);
2790 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2791 CPUX86State *env = &cpu->env;
2b6f294c 2792 Error *local_err = NULL;
e48638fd 2793 static bool ht_warned;
b34d12d1 2794
9886e834
EH		 2795 if (cpu->apic_id < 0) {
2796 error_setg(errp, "apic-id property was not initialized properly");
2797 return;
2798 }
2799
0514ef2f 2800 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2801 env->cpuid_level = 7;
2802 }
7a059953 2803
9b15cd9e
IM		 2804 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2805 * CPUID[1].EDX.
2806 */
e48638fd 2807 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2808 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2809 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2810 & CPUID_EXT2_AMD_ALIASES);
2811 }
2812
fefb41bf
EH		 2813
2814 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2815 error_setg(&local_err,
2816 kvm_enabled() ?
2817 "Host doesn't support requested features" :
2818 "TCG doesn't support requested features");
2819 goto out;
4586f157
IM		 2820 }
2821
65dee380
IM		 2822#ifndef CONFIG_USER_ONLY
2823 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2824
0514ef2f 2825 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2826 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2827 if (local_err != NULL) {
4dc1f449 2828 goto out;
bdeec802
IM		 2829 }
2830 }
65dee380
IM		 2831#endif
2832
7a059953 2833 mce_init(cpu);
2001d0cd
PB		 2834
2835#ifndef CONFIG_USER_ONLY
2836 if (tcg_enabled()) {
f809c605 2837 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd
PB		 2838 cpu->cpu_as_root = g_new(MemoryRegion, 1);
2839 cs->as = g_new(AddressSpace, 1);
f809c605
PB		 2840
2841 /* Outer container... */
2842 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2843 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2844
2845 /* ... with two regions inside: normal system memory with low
2846 * priority, and...
2847 */
2848 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2849 get_system_memory(), 0, ~0ull);
2850 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2851 memory_region_set_enabled(cpu->cpu_as_mem, true);
2001d0cd 2852 address_space_init(cs->as, cpu->cpu_as_root, "CPU");
f809c605
PB		 2853
2854 /* ... SMRAM with higher priority, linked from /machine/smram. */
2855 cpu->machine_done.notify = x86_cpu_machine_done;
2856 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2857 }
2858#endif
2859
14a10fc3 2860 qemu_init_vcpu(cs);
d3c64d6a 2861
e48638fd
WH		 2862 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2863 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2864 * based on inputs (sockets,cores,threads), it is still better to gives
2865 * users a warning.
2866 *
2867 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2868 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2869 */
2870 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2871 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2872 " -smp options properly.");
2873 ht_warned = true;
2874 }
2875
d3c64d6a
IM		 2876 x86_cpu_apic_realize(cpu, &local_err);
2877 if (local_err != NULL) {
2878 goto out;
2879 }
14a10fc3 2880 cpu_reset(cs);
2b6f294c 2881
4dc1f449 2882 xcc->parent_realize(dev, &local_err);
2001d0cd 2883
4dc1f449
IM		 2884out:
2885 if (local_err != NULL) {
2886 error_propagate(errp, local_err);
2887 return;
2888 }
7a059953
AF		 2889}
2890
38e5c119
EH		 2891typedef struct BitProperty {
2892 uint32_t *ptr;
2893 uint32_t mask;
2894} BitProperty;
2895
2896static void x86_cpu_get_bit_prop(Object *obj,
2897 struct Visitor *v,
2898 void *opaque,
2899 const char *name,
2900 Error **errp)
2901{
2902 BitProperty *fp = opaque;
2903 bool value = (*fp->ptr & fp->mask) == fp->mask;
2904 visit_type_bool(v, &value, name, errp);
2905}
2906
2907static void x86_cpu_set_bit_prop(Object *obj,
2908 struct Visitor *v,
2909 void *opaque,
2910 const char *name,
2911 Error **errp)
2912{
2913 DeviceState *dev = DEVICE(obj);
2914 BitProperty *fp = opaque;
2915 Error *local_err = NULL;
2916 bool value;
2917
2918 if (dev->realized) {
2919 qdev_prop_set_after_realize(dev, name, errp);
2920 return;
2921 }
2922
2923 visit_type_bool(v, &value, name, &local_err);
2924 if (local_err) {
2925 error_propagate(errp, local_err);
2926 return;
2927 }
2928
2929 if (value) {
2930 *fp->ptr |= fp->mask;
2931 } else {
2932 *fp->ptr &= ~fp->mask;
2933 }
2934}
2935
2936static void x86_cpu_release_bit_prop(Object *obj, const char *name,
2937 void *opaque)
2938{
2939 BitProperty *prop = opaque;
2940 g_free(prop);
2941}
2942
2943/* Register a boolean property to get/set a single bit in a uint32_t field.
2944 *
2945 * The same property name can be registered multiple times to make it affect
2946 * multiple bits in the same FeatureWord. In that case, the getter will return
2947 * true only if all bits are set.
2948 */
2949static void x86_cpu_register_bit_prop(X86CPU *cpu,
2950 const char *prop_name,
2951 uint32_t *field,
2952 int bitnr)
2953{
2954 BitProperty *fp;
2955 ObjectProperty *op;
2956 uint32_t mask = (1UL << bitnr);
2957
2958 op = object_property_find(OBJECT(cpu), prop_name, NULL);
2959 if (op) {
2960 fp = op->opaque;
2961 assert(fp->ptr == field);
2962 fp->mask |= mask;
2963 } else {
2964 fp = g_new0(BitProperty, 1);
2965 fp->ptr = field;
2966 fp->mask = mask;
2967 object_property_add(OBJECT(cpu), prop_name, "bool",
2968 x86_cpu_get_bit_prop,
2969 x86_cpu_set_bit_prop,
2970 x86_cpu_release_bit_prop, fp, &error_abort);
2971 }
2972}
2973
2974static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
2975 FeatureWord w,
2976 int bitnr)
2977{
2978 Object *obj = OBJECT(cpu);
2979 int i;
2980 char **names;
2981 FeatureWordInfo *fi = &feature_word_info[w];
2982
2983 if (!fi->feat_names) {
2984 return;
2985 }
2986 if (!fi->feat_names[bitnr]) {
2987 return;
2988 }
2989
2990 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
2991
2992 feat2prop(names[0]);
2993 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
2994
2995 for (i = 1; names[i]; i++) {
2996 feat2prop(names[i]);
d461a44c 2997 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 2998 &error_abort);
2999 }
3000
3001 g_strfreev(names);
3002}
3003
de024815
AF		 3004static void x86_cpu_initfn(Object *obj)
3005{
55e5c285 3006 CPUState *cs = CPU(obj);
de024815 3007 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3008 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3009 CPUX86State *env = &cpu->env;
38e5c119 3010 FeatureWord w;
d65e9815 3011 static int inited;
de024815 3012
c05efcb1 3013 cs->env_ptr = env;
4bad9e39 3014 cpu_exec_init(cs, &error_abort);
71ad61d3
AF		 3015
3016 object_property_add(obj, "family", "int",
95b8519d 3017 x86_cpuid_version_get_family,
71ad61d3 3018 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3019 object_property_add(obj, "model", "int",
67e30c83 3020 x86_cpuid_version_get_model,
c5291a4f 3021 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3022 object_property_add(obj, "stepping", "int",
35112e41 3023 x86_cpuid_version_get_stepping,
036e2222 3024 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3025 object_property_add_str(obj, "vendor",
3026 x86_cpuid_get_vendor,
3027 x86_cpuid_set_vendor, NULL);
938d4c25 3028 object_property_add_str(obj, "model-id",
63e886eb 3029 x86_cpuid_get_model_id,
938d4c25 3030 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3031 object_property_add(obj, "tsc-frequency", "int",
3032 x86_cpuid_get_tsc_freq,
3033 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3034 object_property_add(obj, "apic-id", "int",
3035 x86_cpuid_get_apic_id,
3036 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3037 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3038 x86_cpu_get_feature_words,
7e5292b5
EH		 3039 NULL, NULL, (void *)env->features, NULL);
3040 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3041 x86_cpu_get_feature_words,
3042 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3043
92067bf4 3044 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3045
9886e834
EH		 3046#ifndef CONFIG_USER_ONLY
3047 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3048 cpu->apic_id = -1;
3049#endif
3050
38e5c119
EH		 3051 for (w = 0; w < FEATURE_WORDS; w++) {
3052 int bitnr;
3053
3054 for (bitnr = 0; bitnr < 32; bitnr++) {
3055 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3056 }
3057 }
3058
d940ee9b
EH		 3059 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3060
d65e9815
IM		 3061 /* init various static tables used in TCG mode */
3062 if (tcg_enabled() && !inited) {
3063 inited = 1;
3064 optimize_flags_init();
d65e9815 3065 }
de024815
AF		 3066}
3067
997395d3
IM		 3068static int64_t x86_cpu_get_arch_id(CPUState *cs)
3069{
3070 X86CPU *cpu = X86_CPU(cs);
997395d3 3071
7e72a45c 3072 return cpu->apic_id;
997395d3
IM		 3073}
3074
444d5590
AF		 3075static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3076{
3077 X86CPU *cpu = X86_CPU(cs);
3078
3079 return cpu->env.cr[0] & CR0_PG_MASK;
3080}
3081
f45748f1
AF		 3082static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3083{
3084 X86CPU *cpu = X86_CPU(cs);
3085
3086 cpu->env.eip = value;
3087}
3088
bdf7ae5b
AF		 3089static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3090{
3091 X86CPU *cpu = X86_CPU(cs);
3092
3093 cpu->env.eip = tb->pc - tb->cs_base;
3094}
3095
8c2e1b00
AF		 3096static bool x86_cpu_has_work(CPUState *cs)
3097{
3098 X86CPU *cpu = X86_CPU(cs);
3099 CPUX86State *env = &cpu->env;
3100
6220e900
PD		 3101 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3102 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3103 (env->eflags & IF_MASK)) ||
3104 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3105 CPU_INTERRUPT_INIT |
3106 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3107 CPU_INTERRUPT_MCE)) ||
3108 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3109 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3110}
3111
9337e3b6
EH		 3112static Property x86_cpu_properties[] = {
3113 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3114 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3115 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3116 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3117 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3118 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
912ffc47
IM		 3119 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
3120 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3121 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3122 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3123 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3124 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
9337e3b6
EH		 3125 DEFINE_PROP_END_OF_LIST()
3126};
3127
5fd2087a
AF		 3128static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3129{
3130 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3131 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3132 DeviceClass *dc = DEVICE_CLASS(oc);
3133
3134 xcc->parent_realize = dc->realize;
3135 dc->realize = x86_cpu_realizefn;
62fc403f 3136 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 3137 dc->props = x86_cpu_properties;
5fd2087a
AF		 3138
3139 xcc->parent_reset = cc->reset;
3140 cc->reset = x86_cpu_reset;
91b1df8c 3141 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3142
500050d1 3143 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3144 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3145 cc->has_work = x86_cpu_has_work;
97a8ea5a 3146 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3147 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3148 cc->dump_state = x86_cpu_dump_state;
f45748f1 3149 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3150 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3151 cc->gdb_read_register = x86_cpu_gdb_read_register;
3152 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3153 cc->get_arch_id = x86_cpu_get_arch_id;
3154 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3155#ifdef CONFIG_USER_ONLY
3156 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3157#else
a23bbfda 3158 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3159 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3160 cc->write_elf64_note = x86_cpu_write_elf64_note;
3161 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3162 cc->write_elf32_note = x86_cpu_write_elf32_note;
3163 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3164 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3165#endif
a0e372f0 3166 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3167#ifndef CONFIG_USER_ONLY
3168 cc->debug_excp_handler = breakpoint_handler;
3169#endif
374e0cd4
RH		 3170 cc->cpu_exec_enter = x86_cpu_exec_enter;
3171 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 3172}
3173
3174static const TypeInfo x86_cpu_type_info = {
3175 .name = TYPE_X86_CPU,
3176 .parent = TYPE_CPU,
3177 .instance_size = sizeof(X86CPU),
de024815 3178 .instance_init = x86_cpu_initfn,
d940ee9b 3179 .abstract = true,
5fd2087a
AF		 3180 .class_size = sizeof(X86CPUClass),
3181 .class_init = x86_cpu_common_class_init,
3182};
3183
3184static void x86_cpu_register_types(void)
3185{
d940ee9b
EH		 3186 int i;
3187
5fd2087a 3188 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3189 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3190 x86_register_cpudef_type(&builtin_x86_defs[i]);
3191 }
3192#ifdef CONFIG_KVM
3193 type_register_static(&host_x86_cpu_type_info);
3194#endif
5fd2087a
AF		 3195}
3196
3197type_init(x86_cpu_register_types)
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