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Correctly re-init EFER state during INIT IPI
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
d49b6836 29#include "qemu/error-report.h"
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
62fc403f 46#include "hw/cpu/icc_bus.h"
bdeec802 47#ifndef CONFIG_USER_ONLY
2001d0cd 48#include "exec/address-spaces.h"
0d09e41a 49#include "hw/xen/xen.h"
0d09e41a 50#include "hw/i386/apic_internal.h"
bdeec802
IM		 51#endif
52
5e891bf8
EH		 53
54/* Cache topology CPUID constants: */
55
56/* CPUID Leaf 2 Descriptors */
57
58#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
59#define CPUID_2_L1I_32KB_8WAY_64B 0x30
60#define CPUID_2_L2_2MB_8WAY_64B 0x7d
61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
135/* No L3 cache: */
136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
140
141/* TLB definitions: */
142
143#define L1_DTLB_2M_ASSOC 1
144#define L1_DTLB_2M_ENTRIES 255
145#define L1_DTLB_4K_ASSOC 1
146#define L1_DTLB_4K_ENTRIES 255
147
148#define L1_ITLB_2M_ASSOC 1
149#define L1_ITLB_2M_ENTRIES 255
150#define L1_ITLB_4K_ASSOC 1
151#define L1_ITLB_4K_ENTRIES 255
152
153#define L2_DTLB_2M_ASSOC 0 /* disabled */
154#define L2_DTLB_2M_ENTRIES 0 /* disabled */
155#define L2_DTLB_4K_ASSOC 4
156#define L2_DTLB_4K_ENTRIES 512
157
158#define L2_ITLB_2M_ASSOC 0 /* disabled */
159#define L2_ITLB_2M_ENTRIES 0 /* disabled */
160#define L2_ITLB_4K_ASSOC 4
161#define L2_ITLB_4K_ENTRIES 512
162
163
164
99b88a17
IM		 165static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
166 uint32_t vendor2, uint32_t vendor3)
167{
168 int i;
169 for (i = 0; i < 4; i++) {
170 dst[i] = vendor1 >> (8 * i);
171 dst[i + 4] = vendor2 >> (8 * i);
172 dst[i + 8] = vendor3 >> (8 * i);
173 }
174 dst[CPUID_VENDOR_SZ] = '\0';
175}
176
c6dc6f63
AP		 177/* feature flags taken from "Intel Processor Identification and the CPUID
178 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
179 * between feature naming conventions, aliases may be added.
180 */
181static const char *feature_name[] = {
182 "fpu", "vme", "de", "pse",
183 "tsc", "msr", "pae", "mce",
184 "cx8", "apic", NULL, "sep",
185 "mtrr", "pge", "mca", "cmov",
186 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
187 NULL, "ds" /* Intel dts */, "acpi", "mmx",
188 "fxsr", "sse", "sse2", "ss",
189 "ht" /* Intel htt */, "tm", "ia64", "pbe",
190};
191static const char *ext_feature_name[] = {
f370be3c 192 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 193 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 194 "tm2", "ssse3", "cid", NULL,
e117f772 195 "fma", "cx16", "xtpr", "pdcm",
434acb81 196 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 197 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 198 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 199 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 200};
3b671a40
EH		 201/* Feature names that are already defined on feature_name[] but are set on
202 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
203 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
204 * if and only if CPU vendor is AMD.
205 */
c6dc6f63 206static const char *ext2_feature_name[] = {
3b671a40
EH		 207 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
208 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
209 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
210 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
211 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
212 "nx|xd", NULL, "mmxext", NULL /* mmx */,
213 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 214 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 215};
216static const char *ext3_feature_name[] = {
217 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
218 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 219 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 220 "skinit", "wdt", NULL, "lwp",
221 "fma4", "tce", NULL, "nodeid_msr",
222 NULL, "tbm", "topoext", "perfctr_core",
223 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 224 NULL, NULL, NULL, NULL,
225};
226
89e49c8b
EH		 227static const char *ext4_feature_name[] = {
228 NULL, NULL, "xstore", "xstore-en",
229 NULL, NULL, "xcrypt", "xcrypt-en",
230 "ace2", "ace2-en", "phe", "phe-en",
231 "pmm", "pmm-en", NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235 NULL, NULL, NULL, NULL,
236};
237
c6dc6f63 238static const char *kvm_feature_name[] = {
c3d39807 239 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 240 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
8248c36a 245 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 246 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 247};
248
296acb64
JR		 249static const char *svm_feature_name[] = {
250 "npt", "lbrv", "svm_lock", "nrip_save",
251 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
252 NULL, NULL, "pause_filter", NULL,
253 "pfthreshold", NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257 NULL, NULL, NULL, NULL,
258};
259
a9321a4d 260static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 261 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 262 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
9aecd6f8
CP		 263 "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
264 NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 265};
266
303752a9
MT		 267static const char *cpuid_apm_edx_feature_name[] = {
268 NULL, NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 "invtsc", NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275 NULL, NULL, NULL, NULL,
276};
277
0bb0b2d2
PB		 278static const char *cpuid_xsave_feature_name[] = {
279 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286 NULL, NULL, NULL, NULL,
287};
288
28b8e4d0
JK		 289static const char *cpuid_6_feature_name[] = {
290 NULL, NULL, "arat", NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296 NULL, NULL, NULL, NULL,
297 NULL, NULL, NULL, NULL,
298};
299
621626ce
EH		 300#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
301#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
302 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
303#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
304 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
305 CPUID_PSE36 | CPUID_FXSR)
306#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
307#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
308 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
309 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
310 CPUID_PAE | CPUID_SEP | CPUID_APIC)
311
312#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
313 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
314 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
315 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
316 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
317 /* partly implemented:
318 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
319 /* missing:
320 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
321#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
322 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
323 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
324 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
325 /* missing:
326 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
327 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
328 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
329 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
330 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
331 CPUID_EXT_RDRAND */
332
333#ifdef TARGET_X86_64
334#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
335#else
336#define TCG_EXT2_X86_64_FEATURES 0
337#endif
338
339#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
340 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
341 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
342 TCG_EXT2_X86_64_FEATURES)
343#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
344 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
345#define TCG_EXT4_FEATURES 0
346#define TCG_SVM_FEATURES 0
347#define TCG_KVM_FEATURES 0
348#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
349 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
350 /* missing:
351 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
352 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
353 CPUID_7_0_EBX_RDSEED */
303752a9 354#define TCG_APM_FEATURES 0
28b8e4d0 355#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
621626ce
EH		 356
357
5ef57876
EH		 358typedef struct FeatureWordInfo {
359 const char **feat_names;
04d104b6
EH		 360 uint32_t cpuid_eax; /* Input EAX for CPUID */
361 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
362 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
363 int cpuid_reg; /* output register (R_* constant) */
37ce3522 364 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 365 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 366} FeatureWordInfo;
367
368static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 369 [FEAT_1_EDX] = {
370 .feat_names = feature_name,
371 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 372 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 373 },
374 [FEAT_1_ECX] = {
375 .feat_names = ext_feature_name,
376 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 377 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 378 },
379 [FEAT_8000_0001_EDX] = {
380 .feat_names = ext2_feature_name,
381 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 382 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 383 },
384 [FEAT_8000_0001_ECX] = {
385 .feat_names = ext3_feature_name,
386 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 387 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 388 },
89e49c8b
EH		 389 [FEAT_C000_0001_EDX] = {
390 .feat_names = ext4_feature_name,
391 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 392 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 393 },
bffd67b0
EH		 394 [FEAT_KVM] = {
395 .feat_names = kvm_feature_name,
396 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 397 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 398 },
399 [FEAT_SVM] = {
400 .feat_names = svm_feature_name,
401 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 402 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 403 },
404 [FEAT_7_0_EBX] = {
405 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 406 .cpuid_eax = 7,
407 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
408 .cpuid_reg = R_EBX,
37ce3522 409 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 410 },
303752a9
MT		 411 [FEAT_8000_0007_EDX] = {
412 .feat_names = cpuid_apm_edx_feature_name,
413 .cpuid_eax = 0x80000007,
414 .cpuid_reg = R_EDX,
415 .tcg_features = TCG_APM_FEATURES,
416 .unmigratable_flags = CPUID_APM_INVTSC,
417 },
0bb0b2d2
PB		 418 [FEAT_XSAVE] = {
419 .feat_names = cpuid_xsave_feature_name,
420 .cpuid_eax = 0xd,
421 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
422 .cpuid_reg = R_EAX,
423 .tcg_features = 0,
0bb0b2d2 424 },
28b8e4d0
JK		 425 [FEAT_6_EAX] = {
426 .feat_names = cpuid_6_feature_name,
427 .cpuid_eax = 6, .cpuid_reg = R_EAX,
428 .tcg_features = TCG_6_EAX_FEATURES,
429 },
5ef57876
EH		 430};
431
8e8aba50
EH		 432typedef struct X86RegisterInfo32 {
433 /* Name of register */
434 const char *name;
435 /* QAPI enum value register */
436 X86CPURegister32 qapi_enum;
437} X86RegisterInfo32;
438
439#define REGISTER(reg) \
5d371f41 440 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 441static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 442 REGISTER(EAX),
443 REGISTER(ECX),
444 REGISTER(EDX),
445 REGISTER(EBX),
446 REGISTER(ESP),
447 REGISTER(EBP),
448 REGISTER(ESI),
449 REGISTER(EDI),
450};
451#undef REGISTER
452
2560f19f
PB		 453typedef struct ExtSaveArea {
454 uint32_t feature, bits;
455 uint32_t offset, size;
456} ExtSaveArea;
457
458static const ExtSaveArea ext_save_areas[] = {
459 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 460 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 461 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
462 .offset = 0x3c0, .size = 0x40 },
463 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 464 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 465 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
466 .offset = 0x440, .size = 0x40 },
467 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
468 .offset = 0x480, .size = 0x200 },
469 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
470 .offset = 0x680, .size = 0x400 },
2560f19f 471};
8e8aba50 472
8b4beddc
EH		 473const char *get_register_name_32(unsigned int reg)
474{
31ccdde2 475 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 476 return NULL;
477 }
8e8aba50 478 return x86_reg_info_32[reg].name;
8b4beddc
EH		 479}
480
84f1b92f
EH		 481/*
482 * Returns the set of feature flags that are supported and migratable by
483 * QEMU, for a given FeatureWord.
484 */
485static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
486{
487 FeatureWordInfo *wi = &feature_word_info[w];
488 uint32_t r = 0;
489 int i;
490
491 for (i = 0; i < 32; i++) {
492 uint32_t f = 1U << i;
493 /* If the feature name is unknown, it is not supported by QEMU yet */
494 if (!wi->feat_names[i]) {
495 continue;
496 }
497 /* Skip features known to QEMU, but explicitly marked as unmigratable */
498 if (wi->unmigratable_flags & f) {
499 continue;
500 }
501 r |= f;
502 }
503 return r;
504}
505
bb44e0d1
JK		 506void host_cpuid(uint32_t function, uint32_t count,
507 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 508{
a1fd24af
AL		 509 uint32_t vec[4];
510
511#ifdef __x86_64__
512 asm volatile("cpuid"
513 : "=a"(vec[0]), "=b"(vec[1]),
514 "=c"(vec[2]), "=d"(vec[3])
515 : "0"(function), "c"(count) : "cc");
c1f41226 516#elif defined(__i386__)
a1fd24af
AL		 517 asm volatile("pusha \n\t"
518 "cpuid \n\t"
519 "mov %%eax, 0(%2) \n\t"
520 "mov %%ebx, 4(%2) \n\t"
521 "mov %%ecx, 8(%2) \n\t"
522 "mov %%edx, 12(%2) \n\t"
523 "popa"
524 : : "a"(function), "c"(count), "S"(vec)
525 : "memory", "cc");
c1f41226
EH		 526#else
527 abort();
a1fd24af
AL		 528#endif
529
bdde476a 530 if (eax)
a1fd24af 531 *eax = vec[0];
bdde476a 532 if (ebx)
a1fd24af 533 *ebx = vec[1];
bdde476a 534 if (ecx)
a1fd24af 535 *ecx = vec[2];
bdde476a 536 if (edx)
a1fd24af 537 *edx = vec[3];
bdde476a 538}
c6dc6f63
AP		 539
540#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
541
542/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
543 * a substring. ex if !NULL points to the first char after a substring,
544 * otherwise the string is assumed to sized by a terminating nul.
545 * Return lexical ordering of *s1:*s2.
546 */
8f9d989c
CF		 547static int sstrcmp(const char *s1, const char *e1,
548 const char *s2, const char *e2)
c6dc6f63
AP		 549{
550 for (;;) {
551 if (!*s1 || !*s2 || *s1 != *s2)
552 return (*s1 - *s2);
553 ++s1, ++s2;
554 if (s1 == e1 && s2 == e2)
555 return (0);
556 else if (s1 == e1)
557 return (*s2);
558 else if (s2 == e2)
559 return (*s1);
560 }
561}
562
563/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
564 * '|' delimited (possibly empty) strings in which case search for a match
565 * within the alternatives proceeds left to right. Return 0 for success,
566 * non-zero otherwise.
567 */
568static int altcmp(const char *s, const char *e, const char *altstr)
569{
570 const char *p, *q;
571
572 for (q = p = altstr; ; ) {
573 while (*p && *p != '|')
574 ++p;
575 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
576 return (0);
577 if (!*p)
578 return (1);
579 else
580 q = ++p;
581 }
582}
583
584/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 585 * *pval and return true, otherwise return false
c6dc6f63 586 */
e41e0fc6
JK		 587static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
588 const char **featureset)
c6dc6f63
AP		 589{
590 uint32_t mask;
591 const char **ppc;
e41e0fc6 592 bool found = false;
c6dc6f63 593
e41e0fc6 594 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 595 if (*ppc && !altcmp(s, e, *ppc)) {
596 *pval |= mask;
e41e0fc6 597 found = true;
c6dc6f63 598 }
e41e0fc6
JK		 599 }
600 return found;
c6dc6f63
AP		 601}
602
5ef57876 603static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 604 FeatureWordArray words,
605 Error **errp)
c6dc6f63 606{
5ef57876
EH		 607 FeatureWord w;
608 for (w = 0; w < FEATURE_WORDS; w++) {
609 FeatureWordInfo *wi = &feature_word_info[w];
610 if (wi->feat_names &&
611 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
612 break;
613 }
614 }
615 if (w == FEATURE_WORDS) {
c00c94ab 616 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 617 }
c6dc6f63
AP		 618}
619
d940ee9b
EH		 620/* CPU class name definitions: */
621
622#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
623#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
624
625/* Return type name for a given CPU model name
626 * Caller is responsible for freeing the returned string.
627 */
628static char *x86_cpu_type_name(const char *model_name)
629{
630 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
631}
632
500050d1
AF		 633static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
634{
d940ee9b
EH		 635 ObjectClass *oc;
636 char *typename;
637
500050d1
AF		 638 if (cpu_model == NULL) {
639 return NULL;
640 }
641
d940ee9b
EH		 642 typename = x86_cpu_type_name(cpu_model);
643 oc = object_class_by_name(typename);
644 g_free(typename);
645 return oc;
500050d1
AF		 646}
647
d940ee9b 648struct X86CPUDefinition {
c6dc6f63
AP		 649 const char *name;
650 uint32_t level;
90e4b0c3
EH		 651 uint32_t xlevel;
652 uint32_t xlevel2;
99b88a17
IM		 653 /* vendor is zero-terminated, 12 character ASCII string */
654 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 655 int family;
656 int model;
657 int stepping;
0514ef2f 658 FeatureWordArray features;
c6dc6f63 659 char model_id[48];
787aaf57 660 bool cache_info_passthrough;
d940ee9b 661};
c6dc6f63 662
9576de75 663static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 664 {
665 .name = "qemu64",
3046bb5d 666 .level = 0xd,
99b88a17 667 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 668 .family = 6,
f8e6a11a 669 .model = 6,
c6dc6f63 670 .stepping = 3,
0514ef2f 671 .features[FEAT_1_EDX] =
27861ecc 672 PPRO_FEATURES |
c6dc6f63 673 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 674 CPUID_PSE36,
0514ef2f 675 .features[FEAT_1_ECX] =
27861ecc 676 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
0514ef2f 677 .features[FEAT_8000_0001_EDX] =
c6dc6f63 678 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 679 .features[FEAT_8000_0001_ECX] =
27861ecc 680 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63
AP		 681 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
682 .xlevel = 0x8000000A,
c6dc6f63
AP		 683 },
684 {
685 .name = "phenom",
686 .level = 5,
99b88a17 687 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 688 .family = 16,
689 .model = 2,
690 .stepping = 3,
b9fc20bc 691 /* Missing: CPUID_HT */
0514ef2f 692 .features[FEAT_1_EDX] =
27861ecc 693 PPRO_FEATURES |
c6dc6f63 694 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 695 CPUID_PSE36 | CPUID_VME,
0514ef2f 696 .features[FEAT_1_ECX] =
27861ecc 697 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 698 CPUID_EXT_POPCNT,
0514ef2f 699 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 700 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
701 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 702 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 703 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
704 CPUID_EXT3_CR8LEG,
705 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
706 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 707 .features[FEAT_8000_0001_ECX] =
27861ecc 708 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 709 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 710 /* Missing: CPUID_SVM_LBRV */
0514ef2f 711 .features[FEAT_SVM] =
b9fc20bc 712 CPUID_SVM_NPT,
c6dc6f63
AP		 713 .xlevel = 0x8000001A,
714 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
715 },
716 {
717 .name = "core2duo",
718 .level = 10,
99b88a17 719 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 720 .family = 6,
721 .model = 15,
722 .stepping = 11,
b9fc20bc 723 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 724 .features[FEAT_1_EDX] =
27861ecc 725 PPRO_FEATURES |
c6dc6f63 726 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 727 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
728 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 729 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 730 .features[FEAT_1_ECX] =
27861ecc 731 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 732 CPUID_EXT_CX16,
0514ef2f 733 .features[FEAT_8000_0001_EDX] =
27861ecc 734 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 735 .features[FEAT_8000_0001_ECX] =
27861ecc 736 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 737 .xlevel = 0x80000008,
738 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
739 },
740 {
741 .name = "kvm64",
3046bb5d 742 .level = 0xd,
99b88a17 743 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 744 .family = 15,
745 .model = 6,
746 .stepping = 1,
b3a4f0b1 747 /* Missing: CPUID_HT */
0514ef2f 748 .features[FEAT_1_EDX] =
b3a4f0b1 749 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 750 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
751 CPUID_PSE36,
752 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 753 .features[FEAT_1_ECX] =
27861ecc 754 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 755 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 756 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 757 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
758 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
759 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
760 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
761 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 762 .features[FEAT_8000_0001_ECX] =
27861ecc 763 0,
c6dc6f63
AP		 764 .xlevel = 0x80000008,
765 .model_id = "Common KVM processor"
766 },
c6dc6f63
AP		 767 {
768 .name = "qemu32",
769 .level = 4,
99b88a17 770 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 771 .family = 6,
f8e6a11a 772 .model = 6,
c6dc6f63 773 .stepping = 3,
0514ef2f 774 .features[FEAT_1_EDX] =
27861ecc 775 PPRO_FEATURES,
0514ef2f 776 .features[FEAT_1_ECX] =
27861ecc 777 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 778 .xlevel = 0x80000004,
c6dc6f63 779 },
eafaf1e5
AP		 780 {
781 .name = "kvm32",
782 .level = 5,
99b88a17 783 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 784 .family = 15,
785 .model = 6,
786 .stepping = 1,
0514ef2f 787 .features[FEAT_1_EDX] =
b3a4f0b1 788 PPRO_FEATURES | CPUID_VME |
eafaf1e5 789 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 790 .features[FEAT_1_ECX] =
27861ecc 791 CPUID_EXT_SSE3,
0514ef2f 792 .features[FEAT_8000_0001_ECX] =
27861ecc 793 0,
eafaf1e5
AP		 794 .xlevel = 0x80000008,
795 .model_id = "Common 32-bit KVM processor"
796 },
c6dc6f63
AP		 797 {
798 .name = "coreduo",
799 .level = 10,
99b88a17 800 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 801 .family = 6,
802 .model = 14,
803 .stepping = 8,
b9fc20bc 804 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 805 .features[FEAT_1_EDX] =
27861ecc 806 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 807 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
808 CPUID_SS,
809 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 810 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 811 .features[FEAT_1_ECX] =
e93abc14 812 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 813 .features[FEAT_8000_0001_EDX] =
27861ecc 814 CPUID_EXT2_NX,
c6dc6f63
AP		 815 .xlevel = 0x80000008,
816 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
817 },
818 {
819 .name = "486",
58012d66 820 .level = 1,
99b88a17 821 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 822 .family = 4,
b2a856d9 823 .model = 8,
c6dc6f63 824 .stepping = 0,
0514ef2f 825 .features[FEAT_1_EDX] =
27861ecc 826 I486_FEATURES,
c6dc6f63
AP		 827 .xlevel = 0,
828 },
829 {
830 .name = "pentium",
831 .level = 1,
99b88a17 832 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 833 .family = 5,
834 .model = 4,
835 .stepping = 3,
0514ef2f 836 .features[FEAT_1_EDX] =
27861ecc 837 PENTIUM_FEATURES,
c6dc6f63
AP		 838 .xlevel = 0,
839 },
840 {
841 .name = "pentium2",
842 .level = 2,
99b88a17 843 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 844 .family = 6,
845 .model = 5,
846 .stepping = 2,
0514ef2f 847 .features[FEAT_1_EDX] =
27861ecc 848 PENTIUM2_FEATURES,
c6dc6f63
AP		 849 .xlevel = 0,
850 },
851 {
852 .name = "pentium3",
3046bb5d 853 .level = 3,
99b88a17 854 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 855 .family = 6,
856 .model = 7,
857 .stepping = 3,
0514ef2f 858 .features[FEAT_1_EDX] =
27861ecc 859 PENTIUM3_FEATURES,
c6dc6f63
AP		 860 .xlevel = 0,
861 },
862 {
863 .name = "athlon",
864 .level = 2,
99b88a17 865 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 866 .family = 6,
867 .model = 2,
868 .stepping = 3,
0514ef2f 869 .features[FEAT_1_EDX] =
27861ecc 870 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 871 CPUID_MCA,
0514ef2f 872 .features[FEAT_8000_0001_EDX] =
60032ac0 873 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 874 .xlevel = 0x80000008,
c6dc6f63
AP		 875 },
876 {
877 .name = "n270",
3046bb5d 878 .level = 10,
99b88a17 879 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 880 .family = 6,
881 .model = 28,
882 .stepping = 2,
b9fc20bc 883 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 884 .features[FEAT_1_EDX] =
27861ecc 885 PPRO_FEATURES |
b9fc20bc
EH		 886 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
887 CPUID_ACPI | CPUID_SS,
c6dc6f63 888 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 889 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
890 * CPUID_EXT_XTPR */
0514ef2f 891 .features[FEAT_1_ECX] =
27861ecc 892 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 893 CPUID_EXT_MOVBE,
0514ef2f 894 .features[FEAT_8000_0001_EDX] =
60032ac0 895 CPUID_EXT2_NX,
0514ef2f 896 .features[FEAT_8000_0001_ECX] =
27861ecc 897 CPUID_EXT3_LAHF_LM,
3046bb5d 898 .xlevel = 0x80000008,
c6dc6f63
AP		 899 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
900 },
3eca4642
EH		 901 {
902 .name = "Conroe",
3046bb5d 903 .level = 10,
99b88a17 904 .vendor = CPUID_VENDOR_INTEL,
3eca4642 905 .family = 6,
ffce9ebb 906 .model = 15,
3eca4642 907 .stepping = 3,
0514ef2f 908 .features[FEAT_1_EDX] =
b3a4f0b1 909 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 910 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
911 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
912 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
913 CPUID_DE | CPUID_FP87,
0514ef2f 914 .features[FEAT_1_ECX] =
27861ecc 915 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 916 .features[FEAT_8000_0001_EDX] =
27861ecc 917 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 918 .features[FEAT_8000_0001_ECX] =
27861ecc 919 CPUID_EXT3_LAHF_LM,
3046bb5d 920 .xlevel = 0x80000008,
3eca4642
EH		 921 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
922 },
923 {
924 .name = "Penryn",
3046bb5d 925 .level = 10,
99b88a17 926 .vendor = CPUID_VENDOR_INTEL,
3eca4642 927 .family = 6,
ffce9ebb 928 .model = 23,
3eca4642 929 .stepping = 3,
0514ef2f 930 .features[FEAT_1_EDX] =
b3a4f0b1 931 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 932 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
933 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
934 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
935 CPUID_DE | CPUID_FP87,
0514ef2f 936 .features[FEAT_1_ECX] =
27861ecc 937 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 938 CPUID_EXT_SSE3,
0514ef2f 939 .features[FEAT_8000_0001_EDX] =
27861ecc 940 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 941 .features[FEAT_8000_0001_ECX] =
27861ecc 942 CPUID_EXT3_LAHF_LM,
3046bb5d 943 .xlevel = 0x80000008,
3eca4642
EH		 944 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
945 },
946 {
947 .name = "Nehalem",
3046bb5d 948 .level = 11,
99b88a17 949 .vendor = CPUID_VENDOR_INTEL,
3eca4642 950 .family = 6,
ffce9ebb 951 .model = 26,
3eca4642 952 .stepping = 3,
0514ef2f 953 .features[FEAT_1_EDX] =
b3a4f0b1 954 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 955 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
956 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
957 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
958 CPUID_DE | CPUID_FP87,
0514ef2f 959 .features[FEAT_1_ECX] =
27861ecc 960 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 961 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 962 .features[FEAT_8000_0001_EDX] =
27861ecc 963 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 964 .features[FEAT_8000_0001_ECX] =
27861ecc 965 CPUID_EXT3_LAHF_LM,
3046bb5d 966 .xlevel = 0x80000008,
3eca4642
EH		 967 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
968 },
969 {
970 .name = "Westmere",
971 .level = 11,
99b88a17 972 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 973 .family = 6,
974 .model = 44,
975 .stepping = 1,
0514ef2f 976 .features[FEAT_1_EDX] =
b3a4f0b1 977 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 978 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
979 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
980 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
981 CPUID_DE | CPUID_FP87,
0514ef2f 982 .features[FEAT_1_ECX] =
27861ecc 983 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 984 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
985 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 986 .features[FEAT_8000_0001_EDX] =
27861ecc 987 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 988 .features[FEAT_8000_0001_ECX] =
27861ecc 989 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 990 .features[FEAT_6_EAX] =
991 CPUID_6_EAX_ARAT,
3046bb5d 992 .xlevel = 0x80000008,
3eca4642
EH		 993 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
994 },
995 {
996 .name = "SandyBridge",
997 .level = 0xd,
99b88a17 998 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 999 .family = 6,
1000 .model = 42,
1001 .stepping = 1,
0514ef2f 1002 .features[FEAT_1_EDX] =
b3a4f0b1 1003 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1007 CPUID_DE | CPUID_FP87,
0514ef2f 1008 .features[FEAT_1_ECX] =
27861ecc 1009 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1010 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1011 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1012 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1013 CPUID_EXT_SSE3,
0514ef2f 1014 .features[FEAT_8000_0001_EDX] =
27861ecc 1015 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1016 CPUID_EXT2_SYSCALL,
0514ef2f 1017 .features[FEAT_8000_0001_ECX] =
27861ecc 1018 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1019 .features[FEAT_XSAVE] =
1020 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1021 .features[FEAT_6_EAX] =
1022 CPUID_6_EAX_ARAT,
3046bb5d 1023 .xlevel = 0x80000008,
3eca4642
EH		 1024 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1025 },
2f9ac42a
PB		 1026 {
1027 .name = "IvyBridge",
1028 .level = 0xd,
1029 .vendor = CPUID_VENDOR_INTEL,
1030 .family = 6,
1031 .model = 58,
1032 .stepping = 9,
1033 .features[FEAT_1_EDX] =
1034 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1038 CPUID_DE | CPUID_FP87,
1039 .features[FEAT_1_ECX] =
1040 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1041 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1042 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1043 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1044 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1045 .features[FEAT_7_0_EBX] =
1046 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1047 CPUID_7_0_EBX_ERMS,
1048 .features[FEAT_8000_0001_EDX] =
1049 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1050 CPUID_EXT2_SYSCALL,
1051 .features[FEAT_8000_0001_ECX] =
1052 CPUID_EXT3_LAHF_LM,
1053 .features[FEAT_XSAVE] =
1054 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1055 .features[FEAT_6_EAX] =
1056 CPUID_6_EAX_ARAT,
3046bb5d 1057 .xlevel = 0x80000008,
2f9ac42a
PB		 1058 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1059 },
37507094 1060 {
a356850b
EH		 1061 .name = "Haswell-noTSX",
1062 .level = 0xd,
1063 .vendor = CPUID_VENDOR_INTEL,
1064 .family = 6,
1065 .model = 60,
1066 .stepping = 1,
1067 .features[FEAT_1_EDX] =
1068 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1069 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1070 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1071 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1072 CPUID_DE | CPUID_FP87,
1073 .features[FEAT_1_ECX] =
1074 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1075 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1076 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1077 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1078 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1079 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1080 .features[FEAT_8000_0001_EDX] =
1081 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1082 CPUID_EXT2_SYSCALL,
1083 .features[FEAT_8000_0001_ECX] =
becb6667 1084 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1085 .features[FEAT_7_0_EBX] =
1086 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1087 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1088 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1089 .features[FEAT_XSAVE] =
1090 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1091 .features[FEAT_6_EAX] =
1092 CPUID_6_EAX_ARAT,
3046bb5d 1093 .xlevel = 0x80000008,
a356850b
EH		 1094 .model_id = "Intel Core Processor (Haswell, no TSX)",
1095 }, {
37507094
EH		 1096 .name = "Haswell",
1097 .level = 0xd,
99b88a17 1098 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1099 .family = 6,
1100 .model = 60,
1101 .stepping = 1,
0514ef2f 1102 .features[FEAT_1_EDX] =
b3a4f0b1 1103 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1104 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1105 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1106 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1107 CPUID_DE | CPUID_FP87,
0514ef2f 1108 .features[FEAT_1_ECX] =
27861ecc 1109 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1110 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1111 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1112 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1113 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1114 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1115 .features[FEAT_8000_0001_EDX] =
27861ecc 1116 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1117 CPUID_EXT2_SYSCALL,
0514ef2f 1118 .features[FEAT_8000_0001_ECX] =
becb6667 1119 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1120 .features[FEAT_7_0_EBX] =
27861ecc 1121 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1122 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1123 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1124 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1125 .features[FEAT_XSAVE] =
1126 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1127 .features[FEAT_6_EAX] =
1128 CPUID_6_EAX_ARAT,
3046bb5d 1129 .xlevel = 0x80000008,
37507094
EH		 1130 .model_id = "Intel Core Processor (Haswell)",
1131 },
a356850b
EH		 1132 {
1133 .name = "Broadwell-noTSX",
1134 .level = 0xd,
1135 .vendor = CPUID_VENDOR_INTEL,
1136 .family = 6,
1137 .model = 61,
1138 .stepping = 2,
1139 .features[FEAT_1_EDX] =
1140 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1141 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1142 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1143 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1144 CPUID_DE | CPUID_FP87,
1145 .features[FEAT_1_ECX] =
1146 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1147 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1148 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1149 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1150 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1151 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1152 .features[FEAT_8000_0001_EDX] =
1153 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1154 CPUID_EXT2_SYSCALL,
1155 .features[FEAT_8000_0001_ECX] =
becb6667 1156 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1157 .features[FEAT_7_0_EBX] =
1158 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1159 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1160 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1161 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1162 CPUID_7_0_EBX_SMAP,
1163 .features[FEAT_XSAVE] =
1164 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1165 .features[FEAT_6_EAX] =
1166 CPUID_6_EAX_ARAT,
3046bb5d 1167 .xlevel = 0x80000008,
a356850b
EH		 1168 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1169 },
ece01354
EH		 1170 {
1171 .name = "Broadwell",
1172 .level = 0xd,
1173 .vendor = CPUID_VENDOR_INTEL,
1174 .family = 6,
1175 .model = 61,
1176 .stepping = 2,
1177 .features[FEAT_1_EDX] =
b3a4f0b1 1178 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1179 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1180 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1181 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1182 CPUID_DE | CPUID_FP87,
1183 .features[FEAT_1_ECX] =
1184 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1185 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1186 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1187 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1188 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1189 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1190 .features[FEAT_8000_0001_EDX] =
1191 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1192 CPUID_EXT2_SYSCALL,
1193 .features[FEAT_8000_0001_ECX] =
becb6667 1194 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1195 .features[FEAT_7_0_EBX] =
1196 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1197 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1198 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1199 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1200 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1201 .features[FEAT_XSAVE] =
1202 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1203 .features[FEAT_6_EAX] =
1204 CPUID_6_EAX_ARAT,
3046bb5d 1205 .xlevel = 0x80000008,
ece01354
EH		 1206 .model_id = "Intel Core Processor (Broadwell)",
1207 },
3eca4642
EH		 1208 {
1209 .name = "Opteron_G1",
1210 .level = 5,
99b88a17 1211 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1212 .family = 15,
1213 .model = 6,
1214 .stepping = 1,
0514ef2f 1215 .features[FEAT_1_EDX] =
b3a4f0b1 1216 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1217 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1218 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1219 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1220 CPUID_DE | CPUID_FP87,
0514ef2f 1221 .features[FEAT_1_ECX] =
27861ecc 1222 CPUID_EXT_SSE3,
0514ef2f 1223 .features[FEAT_8000_0001_EDX] =
27861ecc 1224 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1225 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1226 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1227 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1228 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1229 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1230 .xlevel = 0x80000008,
1231 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1232 },
1233 {
1234 .name = "Opteron_G2",
1235 .level = 5,
99b88a17 1236 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1237 .family = 15,
1238 .model = 6,
1239 .stepping = 1,
0514ef2f 1240 .features[FEAT_1_EDX] =
b3a4f0b1 1241 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1242 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1243 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1244 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1245 CPUID_DE | CPUID_FP87,
0514ef2f 1246 .features[FEAT_1_ECX] =
27861ecc 1247 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 1248 .features[FEAT_8000_0001_EDX] =
27861ecc 1249 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1250 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1251 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1252 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1253 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1254 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1255 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1256 .features[FEAT_8000_0001_ECX] =
27861ecc 1257 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1258 .xlevel = 0x80000008,
1259 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1260 },
1261 {
1262 .name = "Opteron_G3",
1263 .level = 5,
99b88a17 1264 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1265 .family = 15,
1266 .model = 6,
1267 .stepping = 1,
0514ef2f 1268 .features[FEAT_1_EDX] =
b3a4f0b1 1269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1273 CPUID_DE | CPUID_FP87,
0514ef2f 1274 .features[FEAT_1_ECX] =
27861ecc 1275 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1276 CPUID_EXT_SSE3,
0514ef2f 1277 .features[FEAT_8000_0001_EDX] =
27861ecc 1278 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1279 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1280 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1281 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1282 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1283 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1284 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1285 .features[FEAT_8000_0001_ECX] =
27861ecc 1286 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1287 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1288 .xlevel = 0x80000008,
1289 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1290 },
1291 {
1292 .name = "Opteron_G4",
1293 .level = 0xd,
99b88a17 1294 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1295 .family = 21,
1296 .model = 1,
1297 .stepping = 2,
0514ef2f 1298 .features[FEAT_1_EDX] =
b3a4f0b1 1299 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1300 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1301 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1302 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1303 CPUID_DE | CPUID_FP87,
0514ef2f 1304 .features[FEAT_1_ECX] =
27861ecc 1305 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1306 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1307 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1308 CPUID_EXT_SSE3,
0514ef2f 1309 .features[FEAT_8000_0001_EDX] =
27861ecc 1310 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1311 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1312 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1313 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1314 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1315 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1316 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1317 .features[FEAT_8000_0001_ECX] =
27861ecc 1318 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1319 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1320 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1321 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1322 /* no xsaveopt! */
3eca4642
EH		 1323 .xlevel = 0x8000001A,
1324 .model_id = "AMD Opteron 62xx class CPU",
1325 },
021941b9
AP		 1326 {
1327 .name = "Opteron_G5",
1328 .level = 0xd,
99b88a17 1329 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1330 .family = 21,
1331 .model = 2,
1332 .stepping = 0,
0514ef2f 1333 .features[FEAT_1_EDX] =
b3a4f0b1 1334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1338 CPUID_DE | CPUID_FP87,
0514ef2f 1339 .features[FEAT_1_ECX] =
27861ecc 1340 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1341 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1342 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1343 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1344 .features[FEAT_8000_0001_EDX] =
27861ecc 1345 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
b3fb3a20
EH		 1346 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1347 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1348 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1349 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1350 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1351 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1352 .features[FEAT_8000_0001_ECX] =
27861ecc 1353 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1354 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1355 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1356 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1357 /* no xsaveopt! */
021941b9
AP		 1358 .xlevel = 0x8000001A,
1359 .model_id = "AMD Opteron 63xx class CPU",
1360 },
c6dc6f63
AP		 1361};
1362
5114e842
EH		 1363typedef struct PropValue {
1364 const char *prop, *value;
1365} PropValue;
1366
1367/* KVM-specific features that are automatically added/removed
1368 * from all CPU models when KVM is enabled.
1369 */
1370static PropValue kvm_default_props[] = {
1371 { "kvmclock", "on" },
1372 { "kvm-nopiodelay", "on" },
1373 { "kvm-asyncpf", "on" },
1374 { "kvm-steal-time", "on" },
1375 { "kvm-pv-eoi", "on" },
1376 { "kvmclock-stable-bit", "on" },
1377 { "x2apic", "on" },
1378 { "acpi", "off" },
1379 { "monitor", "off" },
1380 { "svm", "off" },
1381 { NULL, NULL },
1382};
1383
1384void x86_cpu_change_kvm_default(const char *prop, const char *value)
1385{
1386 PropValue *pv;
1387 for (pv = kvm_default_props; pv->prop; pv++) {
1388 if (!strcmp(pv->prop, prop)) {
1389 pv->value = value;
1390 break;
1391 }
1392 }
1393
1394 /* It is valid to call this function only for properties that
1395 * are already present in the kvm_default_props table.
1396 */
1397 assert(pv->prop);
1398}
1399
4d1b279b
EH		 1400static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1401 bool migratable_only);
1402
d940ee9b
EH		 1403#ifdef CONFIG_KVM
1404
c6dc6f63
AP		 1405static int cpu_x86_fill_model_id(char *str)
1406{
1407 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1408 int i;
1409
1410 for (i = 0; i < 3; i++) {
1411 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1412 memcpy(str + i * 16 + 0, &eax, 4);
1413 memcpy(str + i * 16 + 4, &ebx, 4);
1414 memcpy(str + i * 16 + 8, &ecx, 4);
1415 memcpy(str + i * 16 + 12, &edx, 4);
1416 }
1417 return 0;
1418}
1419
d940ee9b
EH		 1420static X86CPUDefinition host_cpudef;
1421
84f1b92f 1422static Property host_x86_cpu_properties[] = {
120eee7d 1423 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
84f1b92f
EH		 1424 DEFINE_PROP_END_OF_LIST()
1425};
1426
d940ee9b 1427/* class_init for the "host" CPU model
6e746f30 1428 *
d940ee9b 1429 * This function may be called before KVM is initialized.
6e746f30 1430 */
d940ee9b 1431static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1432{
84f1b92f 1433 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1434 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1435 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1436
d940ee9b 1437 xcc->kvm_required = true;
6e746f30 1438
c6dc6f63 1439 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1440 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1441
1442 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1443 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1444 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1445 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1446
d940ee9b 1447 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1448
d940ee9b
EH		 1449 xcc->cpu_def = &host_cpudef;
1450 host_cpudef.cache_info_passthrough = true;
1451
1452 /* level, xlevel, xlevel2, and the feature words are initialized on
1453 * instance_init, because they require KVM to be initialized.
1454 */
84f1b92f
EH		 1455
1456 dc->props = host_x86_cpu_properties;
d940ee9b
EH		 1457}
1458
1459static void host_x86_cpu_initfn(Object *obj)
1460{
1461 X86CPU *cpu = X86_CPU(obj);
1462 CPUX86State *env = &cpu->env;
1463 KVMState *s = kvm_state;
d940ee9b
EH		 1464
1465 assert(kvm_enabled());
1466
4d1b279b
EH		 1467 /* We can't fill the features array here because we don't know yet if
1468 * "migratable" is true or false.
1469 */
1470 cpu->host_features = true;
1471
d940ee9b
EH		 1472 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1473 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1474 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1475
d940ee9b 1476 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1477}
1478
d940ee9b
EH		 1479static const TypeInfo host_x86_cpu_type_info = {
1480 .name = X86_CPU_TYPE_NAME("host"),
1481 .parent = TYPE_X86_CPU,
1482 .instance_init = host_x86_cpu_initfn,
1483 .class_init = host_x86_cpu_class_init,
1484};
1485
1486#endif
1487
8459e396 1488static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1489{
8459e396 1490 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1491 int i;
1492
857aee33 1493 for (i = 0; i < 32; ++i) {
c6dc6f63 1494 if (1 << i & mask) {
bffd67b0 1495 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1496 assert(reg);
fefb41bf 1497 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1498 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1499 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1500 f->cpuid_eax, reg,
1501 f->feat_names[i] ? "." : "",
1502 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1503 }
857aee33 1504 }
c6dc6f63
AP		 1505}
1506
95b8519d
AF		 1507static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1508 const char *name, Error **errp)
1509{
1510 X86CPU *cpu = X86_CPU(obj);
1511 CPUX86State *env = &cpu->env;
1512 int64_t value;
1513
1514 value = (env->cpuid_version >> 8) & 0xf;
1515 if (value == 0xf) {
1516 value += (env->cpuid_version >> 20) & 0xff;
1517 }
1518 visit_type_int(v, &value, name, errp);
1519}
1520
71ad61d3
AF		 1521static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1522 const char *name, Error **errp)
ed5e1ec3 1523{
71ad61d3
AF		 1524 X86CPU *cpu = X86_CPU(obj);
1525 CPUX86State *env = &cpu->env;
1526 const int64_t min = 0;
1527 const int64_t max = 0xff + 0xf;
65cd9064 1528 Error *local_err = NULL;
71ad61d3
AF		 1529 int64_t value;
1530
65cd9064
MA		 1531 visit_type_int(v, &value, name, &local_err);
1532 if (local_err) {
1533 error_propagate(errp, local_err);
71ad61d3
AF		 1534 return;
1535 }
1536 if (value < min || value > max) {
c6bd8c70
MA		 1537 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1538 name ? name : "null", value, min, max);
71ad61d3
AF		 1539 return;
1540 }
1541
ed5e1ec3 1542 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1543 if (value > 0x0f) {
1544 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1545 } else {
71ad61d3 1546 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1547 }
1548}
1549
67e30c83
AF		 1550static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1551 const char *name, Error **errp)
1552{
1553 X86CPU *cpu = X86_CPU(obj);
1554 CPUX86State *env = &cpu->env;
1555 int64_t value;
1556
1557 value = (env->cpuid_version >> 4) & 0xf;
1558 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1559 visit_type_int(v, &value, name, errp);
1560}
1561
c5291a4f
AF		 1562static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1563 const char *name, Error **errp)
b0704cbd 1564{
c5291a4f
AF		 1565 X86CPU *cpu = X86_CPU(obj);
1566 CPUX86State *env = &cpu->env;
1567 const int64_t min = 0;
1568 const int64_t max = 0xff;
65cd9064 1569 Error *local_err = NULL;
c5291a4f
AF		 1570 int64_t value;
1571
65cd9064
MA		 1572 visit_type_int(v, &value, name, &local_err);
1573 if (local_err) {
1574 error_propagate(errp, local_err);
c5291a4f
AF		 1575 return;
1576 }
1577 if (value < min || value > max) {
c6bd8c70
MA		 1578 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1579 name ? name : "null", value, min, max);
c5291a4f
AF		 1580 return;
1581 }
1582
b0704cbd 1583 env->cpuid_version &= ~0xf00f0;
c5291a4f 1584 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1585}
1586
35112e41
AF		 1587static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1588 void *opaque, const char *name,
1589 Error **errp)
1590{
1591 X86CPU *cpu = X86_CPU(obj);
1592 CPUX86State *env = &cpu->env;
1593 int64_t value;
1594
1595 value = env->cpuid_version & 0xf;
1596 visit_type_int(v, &value, name, errp);
1597}
1598
036e2222
AF		 1599static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1600 void *opaque, const char *name,
1601 Error **errp)
38c3dc46 1602{
036e2222
AF		 1603 X86CPU *cpu = X86_CPU(obj);
1604 CPUX86State *env = &cpu->env;
1605 const int64_t min = 0;
1606 const int64_t max = 0xf;
65cd9064 1607 Error *local_err = NULL;
036e2222
AF		 1608 int64_t value;
1609
65cd9064
MA		 1610 visit_type_int(v, &value, name, &local_err);
1611 if (local_err) {
1612 error_propagate(errp, local_err);
036e2222
AF		 1613 return;
1614 }
1615 if (value < min || value > max) {
c6bd8c70
MA		 1616 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1617 name ? name : "null", value, min, max);
036e2222
AF		 1618 return;
1619 }
1620
38c3dc46 1621 env->cpuid_version &= ~0xf;
036e2222 1622 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1623}
1624
d480e1af
AF		 1625static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1626{
1627 X86CPU *cpu = X86_CPU(obj);
1628 CPUX86State *env = &cpu->env;
1629 char *value;
d480e1af 1630
e42a92ae 1631 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1632 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1633 env->cpuid_vendor3);
d480e1af
AF		 1634 return value;
1635}
1636
1637static void x86_cpuid_set_vendor(Object *obj, const char *value,
1638 Error **errp)
1639{
1640 X86CPU *cpu = X86_CPU(obj);
1641 CPUX86State *env = &cpu->env;
1642 int i;
1643
9df694ee 1644 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1645 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1646 return;
1647 }
1648
1649 env->cpuid_vendor1 = 0;
1650 env->cpuid_vendor2 = 0;
1651 env->cpuid_vendor3 = 0;
1652 for (i = 0; i < 4; i++) {
1653 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1654 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1655 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1656 }
d480e1af
AF		 1657}
1658
63e886eb
AF		 1659static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1660{
1661 X86CPU *cpu = X86_CPU(obj);
1662 CPUX86State *env = &cpu->env;
1663 char *value;
1664 int i;
1665
1666 value = g_malloc(48 + 1);
1667 for (i = 0; i < 48; i++) {
1668 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1669 }
1670 value[48] = '\0';
1671 return value;
1672}
1673
938d4c25
AF		 1674static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1675 Error **errp)
dcce6675 1676{
938d4c25
AF		 1677 X86CPU *cpu = X86_CPU(obj);
1678 CPUX86State *env = &cpu->env;
dcce6675
AF		 1679 int c, len, i;
1680
1681 if (model_id == NULL) {
1682 model_id = "";
1683 }
1684 len = strlen(model_id);
d0a6acf4 1685 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1686 for (i = 0; i < 48; i++) {
1687 if (i >= len) {
1688 c = '\0';
1689 } else {
1690 c = (uint8_t)model_id[i];
1691 }
1692 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1693 }
1694}
1695
89e48965
AF		 1696static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1697 const char *name, Error **errp)
1698{
1699 X86CPU *cpu = X86_CPU(obj);
1700 int64_t value;
1701
1702 value = cpu->env.tsc_khz * 1000;
1703 visit_type_int(v, &value, name, errp);
1704}
1705
1706static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1707 const char *name, Error **errp)
1708{
1709 X86CPU *cpu = X86_CPU(obj);
1710 const int64_t min = 0;
2e84849a 1711 const int64_t max = INT64_MAX;
65cd9064 1712 Error *local_err = NULL;
89e48965
AF		 1713 int64_t value;
1714
65cd9064
MA		 1715 visit_type_int(v, &value, name, &local_err);
1716 if (local_err) {
1717 error_propagate(errp, local_err);
89e48965
AF		 1718 return;
1719 }
1720 if (value < min || value > max) {
c6bd8c70
MA		 1721 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1722 name ? name : "null", value, min, max);
89e48965
AF		 1723 return;
1724 }
1725
1726 cpu->env.tsc_khz = value / 1000;
1727}
1728
31050930
IM		 1729static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1730 const char *name, Error **errp)
1731{
1732 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1733 int64_t value = cpu->apic_id;
31050930
IM		 1734
1735 visit_type_int(v, &value, name, errp);
1736}
1737
1738static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1739 const char *name, Error **errp)
1740{
1741 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1742 DeviceState *dev = DEVICE(obj);
31050930
IM		 1743 const int64_t min = 0;
1744 const int64_t max = UINT32_MAX;
1745 Error *error = NULL;
1746 int64_t value;
1747
8d6d4980
IM		 1748 if (dev->realized) {
1749 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1750 "it was realized", name, object_get_typename(obj));
1751 return;
1752 }
1753
31050930
IM		 1754 visit_type_int(v, &value, name, &error);
1755 if (error) {
1756 error_propagate(errp, error);
1757 return;
1758 }
1759 if (value < min || value > max) {
1760 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1761 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1762 object_get_typename(obj), name, value, min, max);
1763 return;
1764 }
1765
7e72a45c 1766 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1767 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1768 return;
1769 }
7e72a45c 1770 cpu->apic_id = value;
31050930
IM		 1771}
1772
7e5292b5 1773/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1774static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1775 const char *name, Error **errp)
1776{
7e5292b5 1777 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1778 FeatureWord w;
1779 Error *err = NULL;
1780 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1781 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1782 X86CPUFeatureWordInfoList *list = NULL;
1783
1784 for (w = 0; w < FEATURE_WORDS; w++) {
1785 FeatureWordInfo *wi = &feature_word_info[w];
1786 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1787 qwi->cpuid_input_eax = wi->cpuid_eax;
1788 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1789 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1790 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1791 qwi->features = array[w];
8e8aba50
EH		 1792
1793 /* List will be in reverse order, but order shouldn't matter */
1794 list_entries[w].next = list;
1795 list_entries[w].value = &word_infos[w];
1796 list = &list_entries[w];
1797 }
1798
1799 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1800 error_propagate(errp, err);
1801}
1802
c8f0f88e
IM		 1803static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1804 const char *name, Error **errp)
1805{
1806 X86CPU *cpu = X86_CPU(obj);
1807 int64_t value = cpu->hyperv_spinlock_attempts;
1808
1809 visit_type_int(v, &value, name, errp);
1810}
1811
1812static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1813 const char *name, Error **errp)
1814{
1815 const int64_t min = 0xFFF;
1816 const int64_t max = UINT_MAX;
1817 X86CPU *cpu = X86_CPU(obj);
1818 Error *err = NULL;
1819 int64_t value;
1820
1821 visit_type_int(v, &value, name, &err);
1822 if (err) {
1823 error_propagate(errp, err);
1824 return;
1825 }
1826
1827 if (value < min || value > max) {
1828 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1829 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1830 object_get_typename(obj), name ? name : "null",
1831 value, min, max);
c8f0f88e
IM		 1832 return;
1833 }
1834 cpu->hyperv_spinlock_attempts = value;
1835}
1836
1837static PropertyInfo qdev_prop_spinlocks = {
1838 .name = "int",
1839 .get = x86_get_hv_spinlocks,
1840 .set = x86_set_hv_spinlocks,
1841};
1842
72ac2e87
IM		 1843/* Convert all '_' in a feature string option name to '-', to make feature
1844 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1845 */
1846static inline void feat2prop(char *s)
1847{
1848 while ((s = strchr(s, '_'))) {
1849 *s = '-';
1850 }
1851}
1852
8f961357
EH		 1853/* Parse "+feature,-feature,feature=foo" CPU feature string
1854 */
94a444b2
AF		 1855static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1856 Error **errp)
8f961357 1857{
94a444b2 1858 X86CPU *cpu = X86_CPU(cs);
8f961357 1859 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1860 FeatureWord w;
8f961357 1861 /* Features to be added */
077c68c3 1862 FeatureWordArray plus_features = { 0 };
8f961357 1863 /* Features to be removed */
5ef57876 1864 FeatureWordArray minus_features = { 0 };
8f961357 1865 uint32_t numvalue;
a91987c2 1866 CPUX86State *env = &cpu->env;
94a444b2 1867 Error *local_err = NULL;
8f961357 1868
8f961357 1869 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1870
1871 while (featurestr) {
1872 char *val;
1873 if (featurestr[0] == '+') {
c00c94ab 1874 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1875 } else if (featurestr[0] == '-') {
c00c94ab 1876 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1877 } else if ((val = strchr(featurestr, '='))) {
1878 *val = 0; val++;
72ac2e87 1879 feat2prop(featurestr);
d024d209 1880 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1881 char *err;
a91987c2
IM		 1882 char num[32];
1883
c6dc6f63
AP		 1884 numvalue = strtoul(val, &err, 0);
1885 if (!*val || *err) {
6b1dd54b
PB		 1886 error_setg(errp, "bad numerical value %s", val);
1887 return;
c6dc6f63
AP		 1888 }
1889 if (numvalue < 0x80000000) {
94a444b2
AF		 1890 error_report("xlevel value shall always be >= 0x80000000"
1891 ", fixup will be removed in future versions");
2f7a21c4 1892 numvalue += 0x80000000;
c6dc6f63 1893 }
a91987c2 1894 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1895 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1896 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1897 int64_t tsc_freq;
1898 char *err;
a91987c2 1899 char num[32];
b862d1fe 1900
4677bb40
MAL		 1901 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1902 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1903 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1904 error_setg(errp, "bad numerical value %s", val);
1905 return;
b862d1fe 1906 }
a91987c2 1907 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1908 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1909 &local_err);
72ac2e87 1910 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1911 char *err;
92067bf4 1912 const int min = 0xFFF;
c8f0f88e 1913 char num[32];
28f52cc0
VR		 1914 numvalue = strtoul(val, &err, 0);
1915 if (!*val || *err) {
6b1dd54b
PB		 1916 error_setg(errp, "bad numerical value %s", val);
1917 return;
28f52cc0 1918 }
92067bf4 1919 if (numvalue < min) {
94a444b2 1920 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1921 ", fixup will be removed in future versions",
1922 min);
92067bf4
IM		 1923 numvalue = min;
1924 }
c8f0f88e 1925 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1926 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1927 } else {
94a444b2 1928 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1929 }
c6dc6f63 1930 } else {
258f5abe 1931 feat2prop(featurestr);
94a444b2 1932 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1933 }
94a444b2
AF		 1934 if (local_err) {
1935 error_propagate(errp, local_err);
6b1dd54b 1936 return;
c6dc6f63
AP		 1937 }
1938 featurestr = strtok(NULL, ",");
1939 }
e1c224b4 1940
4d1b279b
EH		 1941 if (cpu->host_features) {
1942 for (w = 0; w < FEATURE_WORDS; w++) {
1943 env->features[w] =
1944 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1945 }
1946 }
1947
e1c224b4
EH		 1948 for (w = 0; w < FEATURE_WORDS; w++) {
1949 env->features[w] |= plus_features[w];
1950 env->features[w] &= ~minus_features[w];
1951 }
c6dc6f63
AP		 1952}
1953
8c3329e5 1954/* Print all cpuid feature names in featureset
c6dc6f63 1955 */
8c3329e5 1956static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1957{
8c3329e5
EH		 1958 int bit;
1959 bool first = true;
1960
1961 for (bit = 0; bit < 32; bit++) {
1962 if (featureset[bit]) {
1963 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1964 first = false;
c6dc6f63 1965 }
8c3329e5 1966 }
c6dc6f63
AP		 1967}
1968
e916cbf8
PM		 1969/* generate CPU information. */
1970void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1971{
9576de75 1972 X86CPUDefinition *def;
c6dc6f63 1973 char buf[256];
7fc9b714 1974 int i;
c6dc6f63 1975
7fc9b714
AF		 1976 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1977 def = &builtin_x86_defs[i];
c04321b3 1978 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 1979 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 1980 }
21ad7789
JK		 1981#ifdef CONFIG_KVM
1982 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1983 "KVM processor with all supported host features "
1984 "(only available in KVM mode)");
1985#endif
1986
6cdf8854 1987 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 1988 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1989 FeatureWordInfo *fw = &feature_word_info[i];
1990
8c3329e5
EH		 1991 (*cpu_fprintf)(f, " ");
1992 listflags(f, cpu_fprintf, fw->feat_names);
1993 (*cpu_fprintf)(f, "\n");
3af60be2 1994 }
c6dc6f63
AP		 1995}
1996
76b64a7a 1997CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 1998{
1999 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2000 X86CPUDefinition *def;
7fc9b714 2001 int i;
e3966126 2002
7fc9b714 2003 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2004 CpuDefinitionInfoList *entry;
2005 CpuDefinitionInfo *info;
2006
7fc9b714 2007 def = &builtin_x86_defs[i];
e3966126
AL		 2008 info = g_malloc0(sizeof(*info));
2009 info->name = g_strdup(def->name);
2010
2011 entry = g_malloc0(sizeof(*entry));
2012 entry->value = info;
2013 entry->next = cpu_list;
2014 cpu_list = entry;
2015 }
2016
2017 return cpu_list;
2018}
2019
84f1b92f
EH		 2020static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2021 bool migratable_only)
27418adf
EH		 2022{
2023 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2024 uint32_t r;
27418adf 2025
fefb41bf 2026 if (kvm_enabled()) {
84f1b92f
EH		 2027 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2028 wi->cpuid_ecx,
2029 wi->cpuid_reg);
fefb41bf 2030 } else if (tcg_enabled()) {
84f1b92f 2031 r = wi->tcg_features;
fefb41bf
EH		 2032 } else {
2033 return ~0;
2034 }
84f1b92f
EH		 2035 if (migratable_only) {
2036 r &= x86_cpu_get_migratable_flags(w);
2037 }
2038 return r;
27418adf
EH		 2039}
2040
51f63aed
EH		 2041/*
2042 * Filters CPU feature words based on host availability of each feature.
2043 *
51f63aed
EH		 2044 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2045 */
27418adf 2046static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2047{
2048 CPUX86State *env = &cpu->env;
bd87d2a2 2049 FeatureWord w;
51f63aed
EH		 2050 int rv = 0;
2051
bd87d2a2 2052 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2053 uint32_t host_feat =
2054 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2055 uint32_t requested_features = env->features[w];
2056 env->features[w] &= host_feat;
2057 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2058 if (cpu->filtered_features[w]) {
2059 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2060 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2061 }
2062 rv = 1;
2063 }
bd87d2a2 2064 }
51f63aed
EH		 2065
2066 return rv;
bc74b7db 2067}
bc74b7db 2068
5114e842
EH		 2069static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2070{
2071 PropValue *pv;
2072 for (pv = props; pv->prop; pv++) {
2073 if (!pv->value) {
2074 continue;
2075 }
2076 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2077 &error_abort);
2078 }
2079}
2080
d940ee9b 2081/* Load data from X86CPUDefinition
c080e30e 2082 */
d940ee9b 2083static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2084{
61dcd775 2085 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2086 const char *vendor;
2087 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2088 FeatureWord w;
c6dc6f63 2089
2d64255b
AF		 2090 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2091 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2092 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2093 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2094 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2095 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
787aaf57 2096 cpu->cache_info_passthrough = def->cache_info_passthrough;
2d64255b 2097 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2098 for (w = 0; w < FEATURE_WORDS; w++) {
2099 env->features[w] = def->features[w];
2100 }
82beb536 2101
9576de75 2102 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2103 if (kvm_enabled()) {
5114e842 2104 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2105 }
5fcca9ff 2106
82beb536 2107 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2108
2109 /* sysenter isn't supported in compatibility mode on AMD,
2110 * syscall isn't supported in compatibility mode on Intel.
2111 * Normally we advertise the actual CPU vendor, but you can
2112 * override this using the 'vendor' property if you want to use
2113 * KVM's sysenter/syscall emulation in compatibility mode and
2114 * when doing cross vendor migration
2115 */
74f54bc4 2116 vendor = def->vendor;
7c08db30
EH		 2117 if (kvm_enabled()) {
2118 uint32_t ebx = 0, ecx = 0, edx = 0;
2119 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2120 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2121 vendor = host_vendor;
2122 }
2123
2124 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2125
c6dc6f63
AP		 2126}
2127
e1570d00 2128X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2129{
2d64255b 2130 X86CPU *cpu = NULL;
d940ee9b 2131 X86CPUClass *xcc;
500050d1 2132 ObjectClass *oc;
2d64255b
AF		 2133 gchar **model_pieces;
2134 char *name, *features;
5c3c6a68
AF		 2135 Error *error = NULL;
2136
2d64255b
AF		 2137 model_pieces = g_strsplit(cpu_model, ",", 2);
2138 if (!model_pieces[0]) {
2139 error_setg(&error, "Invalid/empty CPU model name");
2140 goto out;
2141 }
2142 name = model_pieces[0];
2143 features = model_pieces[1];
2144
500050d1
AF		 2145 oc = x86_cpu_class_by_name(name);
2146 if (oc == NULL) {
2147 error_setg(&error, "Unable to find CPU definition: %s", name);
2148 goto out;
2149 }
d940ee9b
EH		 2150 xcc = X86_CPU_CLASS(oc);
2151
2152 if (xcc->kvm_required && !kvm_enabled()) {
2153 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2154 goto out;
2155 }
2156
d940ee9b
EH		 2157 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2158
94a444b2 2159 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2160 if (error) {
2161 goto out;
5c3c6a68
AF		 2162 }
2163
7f833247 2164out:
cd7b87ff
AF		 2165 if (error != NULL) {
2166 error_propagate(errp, error);
500050d1
AF		 2167 if (cpu) {
2168 object_unref(OBJECT(cpu));
2169 cpu = NULL;
2170 }
cd7b87ff 2171 }
7f833247
IM		 2172 g_strfreev(model_pieces);
2173 return cpu;
2174}
2175
0856579c 2176X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2177{
2178 Error *error = NULL;
2179 X86CPU *cpu;
2180
e1570d00 2181 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2182 if (error) {
0856579c 2183 goto out;
9c235e83 2184 }
7f833247 2185
7f833247 2186 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2187
0856579c
PM		 2188out:
2189 if (error) {
2190 error_report_err(error);
2191 if (cpu != NULL) {
2192 object_unref(OBJECT(cpu));
2193 cpu = NULL;
2194 }
18b0e4e7 2195 }
0856579c 2196 return cpu;
5c3c6a68
AF		 2197}
2198
d940ee9b
EH		 2199static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2200{
2201 X86CPUDefinition *cpudef = data;
2202 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2203
2204 xcc->cpu_def = cpudef;
2205}
2206
2207static void x86_register_cpudef_type(X86CPUDefinition *def)
2208{
2209 char *typename = x86_cpu_type_name(def->name);
2210 TypeInfo ti = {
2211 .name = typename,
2212 .parent = TYPE_X86_CPU,
2213 .class_init = x86_cpu_cpudef_class_init,
2214 .class_data = def,
2215 };
2216
2217 type_register(&ti);
2218 g_free(typename);
2219}
2220
c6dc6f63 2221#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2222
0e26b7b8
BS		 2223void cpu_clear_apic_feature(CPUX86State *env)
2224{
0514ef2f 2225 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2226}
2227
c6dc6f63
AP		 2228#endif /* !CONFIG_USER_ONLY */
2229
c04321b3 2230/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2231 */
2232void x86_cpudef_setup(void)
2233{
93bfef4c
CV		 2234 int i, j;
2235 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2236
2237 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2238 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2239
2240 /* Look for specific "cpudef" models that */
09faecf2 2241 /* have the QEMU version in .model_id */
93bfef4c 2242 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2243 if (strcmp(model_with_versions[j], def->name) == 0) {
2244 pstrcpy(def->model_id, sizeof(def->model_id),
2245 "QEMU Virtual CPU version ");
2246 pstrcat(def->model_id, sizeof(def->model_id),
2247 qemu_get_version());
93bfef4c
CV		 2248 break;
2249 }
2250 }
c6dc6f63 2251 }
c6dc6f63
AP		 2252}
2253
c6dc6f63
AP		 2254void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2255 uint32_t *eax, uint32_t *ebx,
2256 uint32_t *ecx, uint32_t *edx)
2257{
a60f24b5
AF		 2258 X86CPU *cpu = x86_env_get_cpu(env);
2259 CPUState *cs = CPU(cpu);
2260
c6dc6f63
AP		 2261 /* test if maximum index reached */
2262 if (index & 0x80000000) {
b3baa152
BW		 2263 if (index > env->cpuid_xlevel) {
2264 if (env->cpuid_xlevel2 > 0) {
2265 /* Handle the Centaur's CPUID instruction. */
2266 if (index > env->cpuid_xlevel2) {
2267 index = env->cpuid_xlevel2;
2268 } else if (index < 0xC0000000) {
2269 index = env->cpuid_xlevel;
2270 }
2271 } else {
57f26ae7
EH		 2272 /* Intel documentation states that invalid EAX input will
2273 * return the same information as EAX=cpuid_level
2274 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2275 */
2276 index = env->cpuid_level;
b3baa152
BW		 2277 }
2278 }
c6dc6f63
AP		 2279 } else {
2280 if (index > env->cpuid_level)
2281 index = env->cpuid_level;
2282 }
2283
2284 switch(index) {
2285 case 0:
2286 *eax = env->cpuid_level;
5eb2f7a4
EH		 2287 *ebx = env->cpuid_vendor1;
2288 *edx = env->cpuid_vendor2;
2289 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2290 break;
2291 case 1:
2292 *eax = env->cpuid_version;
7e72a45c
EH		 2293 *ebx = (cpu->apic_id << 24) |
2294 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2295 *ecx = env->features[FEAT_1_ECX];
2296 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2297 if (cs->nr_cores * cs->nr_threads > 1) {
2298 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2299 *edx |= 1 << 28; /* HTT bit */
2300 }
2301 break;
2302 case 2:
2303 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2304 if (cpu->cache_info_passthrough) {
2305 host_cpuid(index, 0, eax, ebx, ecx, edx);
2306 break;
2307 }
5e891bf8 2308 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2309 *ebx = 0;
2310 *ecx = 0;
5e891bf8
EH		 2311 *edx = (L1D_DESCRIPTOR << 16) | \
2312 (L1I_DESCRIPTOR << 8) | \
2313 (L2_DESCRIPTOR);
c6dc6f63
AP		 2314 break;
2315 case 4:
2316 /* cache info: needed for Core compatibility */
787aaf57
BC		 2317 if (cpu->cache_info_passthrough) {
2318 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2319 *eax &= ~0xFC000000;
c6dc6f63 2320 } else {
2f7a21c4 2321 *eax = 0;
76c2975a 2322 switch (count) {
c6dc6f63 2323 case 0: /* L1 dcache info */
5e891bf8
EH		 2324 *eax |= CPUID_4_TYPE_DCACHE | \
2325 CPUID_4_LEVEL(1) | \
2326 CPUID_4_SELF_INIT_LEVEL;
2327 *ebx = (L1D_LINE_SIZE - 1) | \
2328 ((L1D_PARTITIONS - 1) << 12) | \
2329 ((L1D_ASSOCIATIVITY - 1) << 22);
2330 *ecx = L1D_SETS - 1;
2331 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2332 break;
2333 case 1: /* L1 icache info */
5e891bf8
EH		 2334 *eax |= CPUID_4_TYPE_ICACHE | \
2335 CPUID_4_LEVEL(1) | \
2336 CPUID_4_SELF_INIT_LEVEL;
2337 *ebx = (L1I_LINE_SIZE - 1) | \
2338 ((L1I_PARTITIONS - 1) << 12) | \
2339 ((L1I_ASSOCIATIVITY - 1) << 22);
2340 *ecx = L1I_SETS - 1;
2341 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2342 break;
2343 case 2: /* L2 cache info */
5e891bf8
EH		 2344 *eax |= CPUID_4_TYPE_UNIFIED | \
2345 CPUID_4_LEVEL(2) | \
2346 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2347 if (cs->nr_threads > 1) {
2348 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2349 }
5e891bf8
EH		 2350 *ebx = (L2_LINE_SIZE - 1) | \
2351 ((L2_PARTITIONS - 1) << 12) | \
2352 ((L2_ASSOCIATIVITY - 1) << 22);
2353 *ecx = L2_SETS - 1;
2354 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2355 break;
2356 default: /* end of info */
2357 *eax = 0;
2358 *ebx = 0;
2359 *ecx = 0;
2360 *edx = 0;
2361 break;
76c2975a
PB		 2362 }
2363 }
2364
2365 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2366 if ((*eax & 31) && cs->nr_cores > 1) {
2367 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2368 }
2369 break;
2370 case 5:
2371 /* mwait info: needed for Core compatibility */
2372 *eax = 0; /* Smallest monitor-line size in bytes */
2373 *ebx = 0; /* Largest monitor-line size in bytes */
2374 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2375 *edx = 0;
2376 break;
2377 case 6:
2378 /* Thermal and Power Leaf */
28b8e4d0 2379 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2380 *ebx = 0;
2381 *ecx = 0;
2382 *edx = 0;
2383 break;
f7911686 2384 case 7:
13526728
EH		 2385 /* Structured Extended Feature Flags Enumeration Leaf */
2386 if (count == 0) {
2387 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2388 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
13526728
EH		 2389 *ecx = 0; /* Reserved */
2390 *edx = 0; /* Reserved */
f7911686
YW		 2391 } else {
2392 *eax = 0;
2393 *ebx = 0;
2394 *ecx = 0;
2395 *edx = 0;
2396 }
2397 break;
c6dc6f63
AP		 2398 case 9:
2399 /* Direct Cache Access Information Leaf */
2400 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2401 *ebx = 0;
2402 *ecx = 0;
2403 *edx = 0;
2404 break;
2405 case 0xA:
2406 /* Architectural Performance Monitoring Leaf */
9337e3b6 2407 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2408 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2409
2410 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2411 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2412 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2413 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2414 } else {
2415 *eax = 0;
2416 *ebx = 0;
2417 *ecx = 0;
2418 *edx = 0;
2419 }
c6dc6f63 2420 break;
2560f19f
PB		 2421 case 0xD: {
2422 KVMState *s = cs->kvm_state;
2423 uint64_t kvm_mask;
2424 int i;
2425
51e49430 2426 /* Processor Extended State */
2560f19f
PB		 2427 *eax = 0;
2428 *ebx = 0;
2429 *ecx = 0;
2430 *edx = 0;
2431 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2432 break;
2433 }
2560f19f
PB		 2434 kvm_mask =
2435 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2436 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2437
2560f19f
PB		 2438 if (count == 0) {
2439 *ecx = 0x240;
2440 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2441 const ExtSaveArea *esa = &ext_save_areas[i];
2442 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2443 (kvm_mask & (1 << i)) != 0) {
2444 if (i < 32) {
2445 *eax |= 1 << i;
2446 } else {
2447 *edx |= 1 << (i - 32);
2448 }
2449 *ecx = MAX(*ecx, esa->offset + esa->size);
2450 }
2451 }
2452 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2453 *ebx = *ecx;
2454 } else if (count == 1) {
0bb0b2d2 2455 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2456 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2457 const ExtSaveArea *esa = &ext_save_areas[count];
2458 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2459 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2460 *eax = esa->size;
2461 *ebx = esa->offset;
2560f19f 2462 }
51e49430
SY		 2463 }
2464 break;
2560f19f 2465 }
c6dc6f63
AP		 2466 case 0x80000000:
2467 *eax = env->cpuid_xlevel;
2468 *ebx = env->cpuid_vendor1;
2469 *edx = env->cpuid_vendor2;
2470 *ecx = env->cpuid_vendor3;
2471 break;
2472 case 0x80000001:
2473 *eax = env->cpuid_version;
2474 *ebx = 0;
0514ef2f
EH		 2475 *ecx = env->features[FEAT_8000_0001_ECX];
2476 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2477
2478 /* The Linux kernel checks for the CMPLegacy bit and
2479 * discards multiple thread information if it is set.
2480 * So dont set it here for Intel to make Linux guests happy.
2481 */
ce3960eb 2482 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2483 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2484 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2485 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2486 *ecx |= 1 << 1; /* CmpLegacy bit */
2487 }
2488 }
c6dc6f63
AP		 2489 break;
2490 case 0x80000002:
2491 case 0x80000003:
2492 case 0x80000004:
2493 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2494 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2495 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2496 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2497 break;
2498 case 0x80000005:
2499 /* cache info (L1 cache) */
787aaf57
BC		 2500 if (cpu->cache_info_passthrough) {
2501 host_cpuid(index, 0, eax, ebx, ecx, edx);
2502 break;
2503 }
5e891bf8
EH		 2504 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2505 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2506 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2507 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2508 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2509 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2510 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2511 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2512 break;
2513 case 0x80000006:
2514 /* cache info (L2 cache) */
787aaf57
BC		 2515 if (cpu->cache_info_passthrough) {
2516 host_cpuid(index, 0, eax, ebx, ecx, edx);
2517 break;
2518 }
5e891bf8
EH		 2519 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2520 (L2_DTLB_2M_ENTRIES << 16) | \
2521 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2522 (L2_ITLB_2M_ENTRIES);
2523 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2524 (L2_DTLB_4K_ENTRIES << 16) | \
2525 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2526 (L2_ITLB_4K_ENTRIES);
2527 *ecx = (L2_SIZE_KB_AMD << 16) | \
2528 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2529 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2530 *edx = ((L3_SIZE_KB/512) << 18) | \
2531 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2532 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2533 break;
303752a9
MT		 2534 case 0x80000007:
2535 *eax = 0;
2536 *ebx = 0;
2537 *ecx = 0;
2538 *edx = env->features[FEAT_8000_0007_EDX];
2539 break;
c6dc6f63
AP		 2540 case 0x80000008:
2541 /* virtual & phys address size in low 2 bytes. */
2542/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2543 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2544 /* 64 bit processor */
2545/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2546 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2547 } else {
0514ef2f 2548 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2549 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2550 } else {
c6dc6f63 2551 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2552 }
c6dc6f63
AP		 2553 }
2554 *ebx = 0;
2555 *ecx = 0;
2556 *edx = 0;
ce3960eb
AF		 2557 if (cs->nr_cores * cs->nr_threads > 1) {
2558 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2559 }
2560 break;
2561 case 0x8000000A:
0514ef2f 2562 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2563 *eax = 0x00000001; /* SVM Revision */
2564 *ebx = 0x00000010; /* nr of ASIDs */
2565 *ecx = 0;
0514ef2f 2566 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2567 } else {
2568 *eax = 0;
2569 *ebx = 0;
2570 *ecx = 0;
2571 *edx = 0;
2572 }
c6dc6f63 2573 break;
b3baa152
BW		 2574 case 0xC0000000:
2575 *eax = env->cpuid_xlevel2;
2576 *ebx = 0;
2577 *ecx = 0;
2578 *edx = 0;
2579 break;
2580 case 0xC0000001:
2581 /* Support for VIA CPU's CPUID instruction */
2582 *eax = env->cpuid_version;
2583 *ebx = 0;
2584 *ecx = 0;
0514ef2f 2585 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2586 break;
2587 case 0xC0000002:
2588 case 0xC0000003:
2589 case 0xC0000004:
2590 /* Reserved for the future, and now filled with zero */
2591 *eax = 0;
2592 *ebx = 0;
2593 *ecx = 0;
2594 *edx = 0;
2595 break;
c6dc6f63
AP		 2596 default:
2597 /* reserved values: zero */
2598 *eax = 0;
2599 *ebx = 0;
2600 *ecx = 0;
2601 *edx = 0;
2602 break;
2603 }
2604}
5fd2087a
AF		 2605
2606/* CPUClass::reset() */
2607static void x86_cpu_reset(CPUState *s)
2608{
2609 X86CPU *cpu = X86_CPU(s);
2610 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2611 CPUX86State *env = &cpu->env;
c1958aea
AF		 2612 int i;
2613
5fd2087a
AF		 2614 xcc->parent_reset(s);
2615
43175fa9 2616 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2617
00c8cb0a 2618 tlb_flush(s, 1);
c1958aea
AF		 2619
2620 env->old_exception = -1;
2621
2622 /* init to reset state */
2623
2624#ifdef CONFIG_SOFTMMU
2625 env->hflags |= HF_SOFTMMU_MASK;
2626#endif
2627 env->hflags2 |= HF2_GIF_MASK;
2628
2629 cpu_x86_update_cr0(env, 0x60000010);
2630 env->a20_mask = ~0x0;
2631 env->smbase = 0x30000;
2632
2633 env->idt.limit = 0xffff;
2634 env->gdt.limit = 0xffff;
2635 env->ldt.limit = 0xffff;
2636 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2637 env->tr.limit = 0xffff;
2638 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2639
2640 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2641 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2642 DESC_R_MASK | DESC_A_MASK);
2643 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2644 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2645 DESC_A_MASK);
2646 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2647 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2648 DESC_A_MASK);
2649 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2650 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2651 DESC_A_MASK);
2652 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2653 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2654 DESC_A_MASK);
2655 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2656 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2657 DESC_A_MASK);
2658
2659 env->eip = 0xfff0;
2660 env->regs[R_EDX] = env->cpuid_version;
2661
2662 env->eflags = 0x2;
2663
2664 /* FPU init */
2665 for (i = 0; i < 8; i++) {
2666 env->fptags[i] = 1;
2667 }
5bde1407 2668 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2669
2670 env->mxcsr = 0x1f80;
c74f41bb 2671 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2672
2673 env->pat = 0x0007040600070406ULL;
2674 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2675
2676 memset(env->dr, 0, sizeof(env->dr));
2677 env->dr[6] = DR6_FIXED_1;
2678 env->dr[7] = DR7_FIXED_1;
b3310ab3 2679 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2680 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2681
05e7e819 2682 env->xcr0 = 1;
0522604b 2683
9db2efd9
AW		 2684 /*
2685 * SDM 11.11.5 requires:
2686 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2687 * - IA32_MTRR_PHYSMASKn.V = 0
2688 * All other bits are undefined. For simplification, zero it all.
2689 */
2690 env->mtrr_deftype = 0;
2691 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2692 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2693
dd673288
IM		 2694#if !defined(CONFIG_USER_ONLY)
2695 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2696 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2697
259186a7 2698 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2699
2700 if (kvm_enabled()) {
2701 kvm_arch_reset_vcpu(cpu);
2702 }
dd673288 2703#endif
5fd2087a
AF		 2704}
2705
dd673288
IM		 2706#ifndef CONFIG_USER_ONLY
2707bool cpu_is_bsp(X86CPU *cpu)
2708{
02e51483 2709 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2710}
65dee380
IM		 2711
2712/* TODO: remove me, when reset over QOM tree is implemented */
2713static void x86_cpu_machine_reset_cb(void *opaque)
2714{
2715 X86CPU *cpu = opaque;
2716 cpu_reset(CPU(cpu));
2717}
dd673288
IM		 2718#endif
2719
de024815
AF		 2720static void mce_init(X86CPU *cpu)
2721{
2722 CPUX86State *cenv = &cpu->env;
2723 unsigned int bank;
2724
2725 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2726 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2727 (CPUID_MCE | CPUID_MCA)) {
2728 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2729 cenv->mcg_ctl = ~(uint64_t)0;
2730 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2731 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2732 }
2733 }
2734}
2735
bdeec802 2736#ifndef CONFIG_USER_ONLY
d3c64d6a 2737static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2738{
53a89e26 2739 DeviceState *dev = DEVICE(cpu);
449994eb 2740 APICCommonState *apic;
bdeec802
IM		 2741 const char *apic_type = "apic";
2742
2743 if (kvm_irqchip_in_kernel()) {
2744 apic_type = "kvm-apic";
2745 } else if (xen_enabled()) {
2746 apic_type = "xen-apic";
2747 }
2748
02e51483
CF		 2749 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2750 if (cpu->apic_state == NULL) {
bdeec802
IM		 2751 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2752 return;
2753 }
2754
2755 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2756 OBJECT(cpu->apic_state), NULL);
7e72a45c 2757 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2758 /* TODO: convert to link<> */
02e51483 2759 apic = APIC_COMMON(cpu->apic_state);
60671e58 2760 apic->cpu = cpu;
d3c64d6a
IM		 2761}
2762
2763static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2764{
02e51483 2765 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2766 return;
2767 }
6e8e2651
MA		 2768 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2769 errp);
bdeec802 2770}
f809c605
PB		 2771
2772static void x86_cpu_machine_done(Notifier *n, void *unused)
2773{
2774 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2775 MemoryRegion *smram =
2776 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2777
2778 if (smram) {
2779 cpu->smram = g_new(MemoryRegion, 1);
2780 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2781 smram, 0, 1ull << 32);
2782 memory_region_set_enabled(cpu->smram, false);
2783 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2784 }
2785}
d3c64d6a
IM		 2786#else
2787static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2788{
2789}
bdeec802
IM		 2790#endif
2791
e48638fd
WH		 2792
2793#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2794 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2795 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2796#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2797 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2798 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2799static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2800{
14a10fc3 2801 CPUState *cs = CPU(dev);
2b6f294c
AF		 2802 X86CPU *cpu = X86_CPU(dev);
2803 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2804 CPUX86State *env = &cpu->env;
2b6f294c 2805 Error *local_err = NULL;
e48638fd 2806 static bool ht_warned;
b34d12d1 2807
9886e834
EH		 2808 if (cpu->apic_id < 0) {
2809 error_setg(errp, "apic-id property was not initialized properly");
2810 return;
2811 }
2812
0514ef2f 2813 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2814 env->cpuid_level = 7;
2815 }
7a059953 2816
9b15cd9e
IM		 2817 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2818 * CPUID[1].EDX.
2819 */
e48638fd 2820 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2821 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2822 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2823 & CPUID_EXT2_AMD_ALIASES);
2824 }
2825
fefb41bf
EH		 2826
2827 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2828 error_setg(&local_err,
2829 kvm_enabled() ?
2830 "Host doesn't support requested features" :
2831 "TCG doesn't support requested features");
2832 goto out;
4586f157
IM		 2833 }
2834
65dee380
IM		 2835#ifndef CONFIG_USER_ONLY
2836 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2837
0514ef2f 2838 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2839 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2840 if (local_err != NULL) {
4dc1f449 2841 goto out;
bdeec802
IM		 2842 }
2843 }
65dee380
IM		 2844#endif
2845
7a059953 2846 mce_init(cpu);
2001d0cd
PB		 2847
2848#ifndef CONFIG_USER_ONLY
2849 if (tcg_enabled()) {
f809c605 2850 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd
PB		 2851 cpu->cpu_as_root = g_new(MemoryRegion, 1);
2852 cs->as = g_new(AddressSpace, 1);
f809c605
PB		 2853
2854 /* Outer container... */
2855 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2856 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2857
2858 /* ... with two regions inside: normal system memory with low
2859 * priority, and...
2860 */
2861 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2862 get_system_memory(), 0, ~0ull);
2863 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2864 memory_region_set_enabled(cpu->cpu_as_mem, true);
2001d0cd 2865 address_space_init(cs->as, cpu->cpu_as_root, "CPU");
f809c605
PB		 2866
2867 /* ... SMRAM with higher priority, linked from /machine/smram. */
2868 cpu->machine_done.notify = x86_cpu_machine_done;
2869 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2870 }
2871#endif
2872
14a10fc3 2873 qemu_init_vcpu(cs);
d3c64d6a 2874
e48638fd
WH		 2875 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2876 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2877 * based on inputs (sockets,cores,threads), it is still better to gives
2878 * users a warning.
2879 *
2880 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2881 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2882 */
2883 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2884 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2885 " -smp options properly.");
2886 ht_warned = true;
2887 }
2888
d3c64d6a
IM		 2889 x86_cpu_apic_realize(cpu, &local_err);
2890 if (local_err != NULL) {
2891 goto out;
2892 }
14a10fc3 2893 cpu_reset(cs);
2b6f294c 2894
4dc1f449 2895 xcc->parent_realize(dev, &local_err);
2001d0cd 2896
4dc1f449
IM		 2897out:
2898 if (local_err != NULL) {
2899 error_propagate(errp, local_err);
2900 return;
2901 }
7a059953
AF		 2902}
2903
38e5c119
EH		 2904typedef struct BitProperty {
2905 uint32_t *ptr;
2906 uint32_t mask;
2907} BitProperty;
2908
2909static void x86_cpu_get_bit_prop(Object *obj,
2910 struct Visitor *v,
2911 void *opaque,
2912 const char *name,
2913 Error **errp)
2914{
2915 BitProperty *fp = opaque;
2916 bool value = (*fp->ptr & fp->mask) == fp->mask;
2917 visit_type_bool(v, &value, name, errp);
2918}
2919
2920static void x86_cpu_set_bit_prop(Object *obj,
2921 struct Visitor *v,
2922 void *opaque,
2923 const char *name,
2924 Error **errp)
2925{
2926 DeviceState *dev = DEVICE(obj);
2927 BitProperty *fp = opaque;
2928 Error *local_err = NULL;
2929 bool value;
2930
2931 if (dev->realized) {
2932 qdev_prop_set_after_realize(dev, name, errp);
2933 return;
2934 }
2935
2936 visit_type_bool(v, &value, name, &local_err);
2937 if (local_err) {
2938 error_propagate(errp, local_err);
2939 return;
2940 }
2941
2942 if (value) {
2943 *fp->ptr |= fp->mask;
2944 } else {
2945 *fp->ptr &= ~fp->mask;
2946 }
2947}
2948
2949static void x86_cpu_release_bit_prop(Object *obj, const char *name,
2950 void *opaque)
2951{
2952 BitProperty *prop = opaque;
2953 g_free(prop);
2954}
2955
2956/* Register a boolean property to get/set a single bit in a uint32_t field.
2957 *
2958 * The same property name can be registered multiple times to make it affect
2959 * multiple bits in the same FeatureWord. In that case, the getter will return
2960 * true only if all bits are set.
2961 */
2962static void x86_cpu_register_bit_prop(X86CPU *cpu,
2963 const char *prop_name,
2964 uint32_t *field,
2965 int bitnr)
2966{
2967 BitProperty *fp;
2968 ObjectProperty *op;
2969 uint32_t mask = (1UL << bitnr);
2970
2971 op = object_property_find(OBJECT(cpu), prop_name, NULL);
2972 if (op) {
2973 fp = op->opaque;
2974 assert(fp->ptr == field);
2975 fp->mask |= mask;
2976 } else {
2977 fp = g_new0(BitProperty, 1);
2978 fp->ptr = field;
2979 fp->mask = mask;
2980 object_property_add(OBJECT(cpu), prop_name, "bool",
2981 x86_cpu_get_bit_prop,
2982 x86_cpu_set_bit_prop,
2983 x86_cpu_release_bit_prop, fp, &error_abort);
2984 }
2985}
2986
2987static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
2988 FeatureWord w,
2989 int bitnr)
2990{
2991 Object *obj = OBJECT(cpu);
2992 int i;
2993 char **names;
2994 FeatureWordInfo *fi = &feature_word_info[w];
2995
2996 if (!fi->feat_names) {
2997 return;
2998 }
2999 if (!fi->feat_names[bitnr]) {
3000 return;
3001 }
3002
3003 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3004
3005 feat2prop(names[0]);
3006 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3007
3008 for (i = 1; names[i]; i++) {
3009 feat2prop(names[i]);
d461a44c 3010 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3011 &error_abort);
3012 }
3013
3014 g_strfreev(names);
3015}
3016
de024815
AF		 3017static void x86_cpu_initfn(Object *obj)
3018{
55e5c285 3019 CPUState *cs = CPU(obj);
de024815 3020 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3021 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3022 CPUX86State *env = &cpu->env;
38e5c119 3023 FeatureWord w;
d65e9815 3024 static int inited;
de024815 3025
c05efcb1 3026 cs->env_ptr = env;
4bad9e39 3027 cpu_exec_init(cs, &error_abort);
71ad61d3
AF		 3028
3029 object_property_add(obj, "family", "int",
95b8519d 3030 x86_cpuid_version_get_family,
71ad61d3 3031 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3032 object_property_add(obj, "model", "int",
67e30c83 3033 x86_cpuid_version_get_model,
c5291a4f 3034 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3035 object_property_add(obj, "stepping", "int",
35112e41 3036 x86_cpuid_version_get_stepping,
036e2222 3037 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3038 object_property_add_str(obj, "vendor",
3039 x86_cpuid_get_vendor,
3040 x86_cpuid_set_vendor, NULL);
938d4c25 3041 object_property_add_str(obj, "model-id",
63e886eb 3042 x86_cpuid_get_model_id,
938d4c25 3043 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3044 object_property_add(obj, "tsc-frequency", "int",
3045 x86_cpuid_get_tsc_freq,
3046 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3047 object_property_add(obj, "apic-id", "int",
3048 x86_cpuid_get_apic_id,
3049 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3050 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3051 x86_cpu_get_feature_words,
7e5292b5
EH		 3052 NULL, NULL, (void *)env->features, NULL);
3053 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3054 x86_cpu_get_feature_words,
3055 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3056
92067bf4 3057 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3058
9886e834
EH		 3059#ifndef CONFIG_USER_ONLY
3060 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3061 cpu->apic_id = -1;
3062#endif
3063
38e5c119
EH		 3064 for (w = 0; w < FEATURE_WORDS; w++) {
3065 int bitnr;
3066
3067 for (bitnr = 0; bitnr < 32; bitnr++) {
3068 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3069 }
3070 }
3071
d940ee9b
EH		 3072 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3073
d65e9815
IM		 3074 /* init various static tables used in TCG mode */
3075 if (tcg_enabled() && !inited) {
3076 inited = 1;
3077 optimize_flags_init();
d65e9815 3078 }
de024815
AF		 3079}
3080
997395d3
IM		 3081static int64_t x86_cpu_get_arch_id(CPUState *cs)
3082{
3083 X86CPU *cpu = X86_CPU(cs);
997395d3 3084
7e72a45c 3085 return cpu->apic_id;
997395d3
IM		 3086}
3087
444d5590
AF		 3088static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3089{
3090 X86CPU *cpu = X86_CPU(cs);
3091
3092 return cpu->env.cr[0] & CR0_PG_MASK;
3093}
3094
f45748f1
AF		 3095static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3096{
3097 X86CPU *cpu = X86_CPU(cs);
3098
3099 cpu->env.eip = value;
3100}
3101
bdf7ae5b
AF		 3102static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3103{
3104 X86CPU *cpu = X86_CPU(cs);
3105
3106 cpu->env.eip = tb->pc - tb->cs_base;
3107}
3108
8c2e1b00
AF		 3109static bool x86_cpu_has_work(CPUState *cs)
3110{
3111 X86CPU *cpu = X86_CPU(cs);
3112 CPUX86State *env = &cpu->env;
3113
6220e900
PD		 3114 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3115 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3116 (env->eflags & IF_MASK)) ||
3117 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3118 CPU_INTERRUPT_INIT |
3119 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3120 CPU_INTERRUPT_MCE)) ||
3121 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3122 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3123}
3124
9337e3b6
EH		 3125static Property x86_cpu_properties[] = {
3126 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3127 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3128 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3129 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3130 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3131 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
912ffc47
IM		 3132 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
3133 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3134 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3135 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3136 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3137 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
9337e3b6
EH		 3138 DEFINE_PROP_END_OF_LIST()
3139};
3140
5fd2087a
AF		 3141static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3142{
3143 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3144 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3145 DeviceClass *dc = DEVICE_CLASS(oc);
3146
3147 xcc->parent_realize = dc->realize;
3148 dc->realize = x86_cpu_realizefn;
62fc403f 3149 dc->bus_type = TYPE_ICC_BUS;
9337e3b6 3150 dc->props = x86_cpu_properties;
5fd2087a
AF		 3151
3152 xcc->parent_reset = cc->reset;
3153 cc->reset = x86_cpu_reset;
91b1df8c 3154 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3155
500050d1 3156 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3157 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3158 cc->has_work = x86_cpu_has_work;
97a8ea5a 3159 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3160 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3161 cc->dump_state = x86_cpu_dump_state;
f45748f1 3162 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3163 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3164 cc->gdb_read_register = x86_cpu_gdb_read_register;
3165 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3166 cc->get_arch_id = x86_cpu_get_arch_id;
3167 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3168#ifdef CONFIG_USER_ONLY
3169 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3170#else
a23bbfda 3171 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3172 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3173 cc->write_elf64_note = x86_cpu_write_elf64_note;
3174 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3175 cc->write_elf32_note = x86_cpu_write_elf32_note;
3176 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3177 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3178#endif
a0e372f0 3179 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3180#ifndef CONFIG_USER_ONLY
3181 cc->debug_excp_handler = breakpoint_handler;
3182#endif
374e0cd4
RH		 3183 cc->cpu_exec_enter = x86_cpu_exec_enter;
3184 cc->cpu_exec_exit = x86_cpu_exec_exit;
5fd2087a
AF		 3185}
3186
3187static const TypeInfo x86_cpu_type_info = {
3188 .name = TYPE_X86_CPU,
3189 .parent = TYPE_CPU,
3190 .instance_size = sizeof(X86CPU),
de024815 3191 .instance_init = x86_cpu_initfn,
d940ee9b 3192 .abstract = true,
5fd2087a
AF		 3193 .class_size = sizeof(X86CPUClass),
3194 .class_init = x86_cpu_common_class_init,
3195};
3196
3197static void x86_cpu_register_types(void)
3198{
d940ee9b
EH		 3199 int i;
3200
5fd2087a 3201 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3202 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3203 x86_register_cpudef_type(&builtin_x86_defs[i]);
3204 }
3205#ifdef CONFIG_KVM
3206 type_register_static(&host_x86_cpu_type_info);
3207#endif
5fd2087a
AF		 3208}
3209
3210type_init(x86_cpu_register_types)
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