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qapi: Swap visit_* arguments for consistent 'name' placement
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
9c17d615 25#include "sysemu/kvm.h"
8932cfdf 26#include "sysemu/cpus.h"
50a2c6e5 27#include "kvm_i386.h"
c6dc6f63 28
d49b6836 29#include "qemu/error-report.h"
1de7afc9
PB		 30#include "qemu/option.h"
31#include "qemu/config-file.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
c6dc6f63 33
8e8aba50
EH		 34#include "qapi-types.h"
35#include "qapi-visit.h"
7b1b5d19 36#include "qapi/visitor.h"
9c17d615 37#include "sysemu/arch_init.h"
71ad61d3 38
65dee380 39#include "hw/hw.h"
b834b508 40#if defined(CONFIG_KVM)
ef8621b1 41#include <linux/kvm_para.h>
b834b508 42#endif
65dee380 43
9c17d615 44#include "sysemu/sysemu.h"
53a89e26 45#include "hw/qdev-properties.h"
bdeec802 46#ifndef CONFIG_USER_ONLY
2001d0cd 47#include "exec/address-spaces.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 260 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
f7fda280
XG		 262 "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
263 "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 264};
265
f74eefe0
HH		 266static const char *cpuid_7_0_ecx_feature_name[] = {
267 NULL, NULL, NULL, "pku",
268 "ospke", NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275};
276
303752a9
MT		 277static const char *cpuid_apm_edx_feature_name[] = {
278 NULL, NULL, NULL, NULL,
279 NULL, NULL, NULL, NULL,
280 "invtsc", NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286};
287
0bb0b2d2
PB		 288static const char *cpuid_xsave_feature_name[] = {
289 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
290 NULL, NULL, NULL, NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296 NULL, NULL, NULL, NULL,
297};
298
28b8e4d0
JK		 299static const char *cpuid_6_feature_name[] = {
300 NULL, NULL, "arat", NULL,
301 NULL, NULL, NULL, NULL,
302 NULL, NULL, NULL, NULL,
303 NULL, NULL, NULL, NULL,
304 NULL, NULL, NULL, NULL,
305 NULL, NULL, NULL, NULL,
306 NULL, NULL, NULL, NULL,
307 NULL, NULL, NULL, NULL,
308};
309
621626ce
EH		 310#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
311#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
312 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
313#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
314 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
315 CPUID_PSE36 | CPUID_FXSR)
316#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
317#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
318 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
319 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
320 CPUID_PAE | CPUID_SEP | CPUID_APIC)
321
322#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
323 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
324 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
325 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 326 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 327 /* partly implemented:
328 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
329 /* missing:
330 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
331#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
332 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
333 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
334 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
335 /* missing:
336 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
337 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
338 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
339 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
340 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
341 CPUID_EXT_RDRAND */
342
343#ifdef TARGET_X86_64
344#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
345#else
346#define TCG_EXT2_X86_64_FEATURES 0
347#endif
348
349#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
350 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
351 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
352 TCG_EXT2_X86_64_FEATURES)
353#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
354 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
355#define TCG_EXT4_FEATURES 0
356#define TCG_SVM_FEATURES 0
357#define TCG_KVM_FEATURES 0
358#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 359 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
360 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
361 CPUID_7_0_EBX_CLWB)
621626ce
EH		 362 /* missing:
363 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
364 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
365 CPUID_7_0_EBX_RDSEED */
f74eefe0 366#define TCG_7_0_ECX_FEATURES 0
303752a9 367#define TCG_APM_FEATURES 0
28b8e4d0 368#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
621626ce
EH		 369
370
5ef57876
EH		 371typedef struct FeatureWordInfo {
372 const char **feat_names;
04d104b6
EH		 373 uint32_t cpuid_eax; /* Input EAX for CPUID */
374 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
375 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
376 int cpuid_reg; /* output register (R_* constant) */
37ce3522 377 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 378 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 379} FeatureWordInfo;
380
381static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 382 [FEAT_1_EDX] = {
383 .feat_names = feature_name,
384 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 385 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 386 },
387 [FEAT_1_ECX] = {
388 .feat_names = ext_feature_name,
389 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 390 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 391 },
392 [FEAT_8000_0001_EDX] = {
393 .feat_names = ext2_feature_name,
394 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 395 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 396 },
397 [FEAT_8000_0001_ECX] = {
398 .feat_names = ext3_feature_name,
399 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 400 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 401 },
89e49c8b
EH		 402 [FEAT_C000_0001_EDX] = {
403 .feat_names = ext4_feature_name,
404 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 405 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 406 },
bffd67b0
EH		 407 [FEAT_KVM] = {
408 .feat_names = kvm_feature_name,
409 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 410 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 411 },
412 [FEAT_SVM] = {
413 .feat_names = svm_feature_name,
414 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 415 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 416 },
417 [FEAT_7_0_EBX] = {
418 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 419 .cpuid_eax = 7,
420 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
421 .cpuid_reg = R_EBX,
37ce3522 422 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 423 },
f74eefe0
HH		 424 [FEAT_7_0_ECX] = {
425 .feat_names = cpuid_7_0_ecx_feature_name,
426 .cpuid_eax = 7,
427 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
428 .cpuid_reg = R_ECX,
429 .tcg_features = TCG_7_0_ECX_FEATURES,
430 },
303752a9
MT		 431 [FEAT_8000_0007_EDX] = {
432 .feat_names = cpuid_apm_edx_feature_name,
433 .cpuid_eax = 0x80000007,
434 .cpuid_reg = R_EDX,
435 .tcg_features = TCG_APM_FEATURES,
436 .unmigratable_flags = CPUID_APM_INVTSC,
437 },
0bb0b2d2
PB		 438 [FEAT_XSAVE] = {
439 .feat_names = cpuid_xsave_feature_name,
440 .cpuid_eax = 0xd,
441 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
442 .cpuid_reg = R_EAX,
443 .tcg_features = 0,
0bb0b2d2 444 },
28b8e4d0
JK		 445 [FEAT_6_EAX] = {
446 .feat_names = cpuid_6_feature_name,
447 .cpuid_eax = 6, .cpuid_reg = R_EAX,
448 .tcg_features = TCG_6_EAX_FEATURES,
449 },
5ef57876
EH		 450};
451
8e8aba50
EH		 452typedef struct X86RegisterInfo32 {
453 /* Name of register */
454 const char *name;
455 /* QAPI enum value register */
456 X86CPURegister32 qapi_enum;
457} X86RegisterInfo32;
458
459#define REGISTER(reg) \
5d371f41 460 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 461static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 462 REGISTER(EAX),
463 REGISTER(ECX),
464 REGISTER(EDX),
465 REGISTER(EBX),
466 REGISTER(ESP),
467 REGISTER(EBP),
468 REGISTER(ESI),
469 REGISTER(EDI),
470};
471#undef REGISTER
472
2560f19f
PB		 473typedef struct ExtSaveArea {
474 uint32_t feature, bits;
475 uint32_t offset, size;
476} ExtSaveArea;
477
478static const ExtSaveArea ext_save_areas[] = {
479 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 480 .offset = 0x240, .size = 0x100 },
79e9ebeb
LJ		 481 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
482 .offset = 0x3c0, .size = 0x40 },
483 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 484 .offset = 0x400, .size = 0x40 },
9aecd6f8
CP		 485 [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
486 .offset = 0x440, .size = 0x40 },
487 [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
488 .offset = 0x480, .size = 0x200 },
489 [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
490 .offset = 0x680, .size = 0x400 },
f74eefe0
HH		 491 [9] = { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
492 .offset = 0xA80, .size = 0x8 },
2560f19f 493};
8e8aba50 494
8b4beddc
EH		 495const char *get_register_name_32(unsigned int reg)
496{
31ccdde2 497 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 498 return NULL;
499 }
8e8aba50 500 return x86_reg_info_32[reg].name;
8b4beddc
EH		 501}
502
84f1b92f
EH		 503/*
504 * Returns the set of feature flags that are supported and migratable by
505 * QEMU, for a given FeatureWord.
506 */
507static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
508{
509 FeatureWordInfo *wi = &feature_word_info[w];
510 uint32_t r = 0;
511 int i;
512
513 for (i = 0; i < 32; i++) {
514 uint32_t f = 1U << i;
515 /* If the feature name is unknown, it is not supported by QEMU yet */
516 if (!wi->feat_names[i]) {
517 continue;
518 }
519 /* Skip features known to QEMU, but explicitly marked as unmigratable */
520 if (wi->unmigratable_flags & f) {
521 continue;
522 }
523 r |= f;
524 }
525 return r;
526}
527
bb44e0d1
JK		 528void host_cpuid(uint32_t function, uint32_t count,
529 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 530{
a1fd24af
AL		 531 uint32_t vec[4];
532
533#ifdef __x86_64__
534 asm volatile("cpuid"
535 : "=a"(vec[0]), "=b"(vec[1]),
536 "=c"(vec[2]), "=d"(vec[3])
537 : "0"(function), "c"(count) : "cc");
c1f41226 538#elif defined(__i386__)
a1fd24af
AL		 539 asm volatile("pusha \n\t"
540 "cpuid \n\t"
541 "mov %%eax, 0(%2) \n\t"
542 "mov %%ebx, 4(%2) \n\t"
543 "mov %%ecx, 8(%2) \n\t"
544 "mov %%edx, 12(%2) \n\t"
545 "popa"
546 : : "a"(function), "c"(count), "S"(vec)
547 : "memory", "cc");
c1f41226
EH		 548#else
549 abort();
a1fd24af
AL		 550#endif
551
bdde476a 552 if (eax)
a1fd24af 553 *eax = vec[0];
bdde476a 554 if (ebx)
a1fd24af 555 *ebx = vec[1];
bdde476a 556 if (ecx)
a1fd24af 557 *ecx = vec[2];
bdde476a 558 if (edx)
a1fd24af 559 *edx = vec[3];
bdde476a 560}
c6dc6f63
AP		 561
562#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
563
564/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
565 * a substring. ex if !NULL points to the first char after a substring,
566 * otherwise the string is assumed to sized by a terminating nul.
567 * Return lexical ordering of *s1:*s2.
568 */
8f9d989c
CF		 569static int sstrcmp(const char *s1, const char *e1,
570 const char *s2, const char *e2)
c6dc6f63
AP		 571{
572 for (;;) {
573 if (!*s1 || !*s2 || *s1 != *s2)
574 return (*s1 - *s2);
575 ++s1, ++s2;
576 if (s1 == e1 && s2 == e2)
577 return (0);
578 else if (s1 == e1)
579 return (*s2);
580 else if (s2 == e2)
581 return (*s1);
582 }
583}
584
585/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
586 * '|' delimited (possibly empty) strings in which case search for a match
587 * within the alternatives proceeds left to right. Return 0 for success,
588 * non-zero otherwise.
589 */
590static int altcmp(const char *s, const char *e, const char *altstr)
591{
592 const char *p, *q;
593
594 for (q = p = altstr; ; ) {
595 while (*p && *p != '|')
596 ++p;
597 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
598 return (0);
599 if (!*p)
600 return (1);
601 else
602 q = ++p;
603 }
604}
605
606/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 607 * *pval and return true, otherwise return false
c6dc6f63 608 */
e41e0fc6
JK		 609static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
610 const char **featureset)
c6dc6f63
AP		 611{
612 uint32_t mask;
613 const char **ppc;
e41e0fc6 614 bool found = false;
c6dc6f63 615
e41e0fc6 616 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 617 if (*ppc && !altcmp(s, e, *ppc)) {
618 *pval |= mask;
e41e0fc6 619 found = true;
c6dc6f63 620 }
e41e0fc6
JK		 621 }
622 return found;
c6dc6f63
AP		 623}
624
5ef57876 625static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 626 FeatureWordArray words,
627 Error **errp)
c6dc6f63 628{
5ef57876
EH		 629 FeatureWord w;
630 for (w = 0; w < FEATURE_WORDS; w++) {
631 FeatureWordInfo *wi = &feature_word_info[w];
632 if (wi->feat_names &&
633 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
634 break;
635 }
636 }
637 if (w == FEATURE_WORDS) {
c00c94ab 638 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 639 }
c6dc6f63
AP		 640}
641
d940ee9b
EH		 642/* CPU class name definitions: */
643
644#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
645#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
646
647/* Return type name for a given CPU model name
648 * Caller is responsible for freeing the returned string.
649 */
650static char *x86_cpu_type_name(const char *model_name)
651{
652 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
653}
654
500050d1
AF		 655static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
656{
d940ee9b
EH		 657 ObjectClass *oc;
658 char *typename;
659
500050d1
AF		 660 if (cpu_model == NULL) {
661 return NULL;
662 }
663
d940ee9b
EH		 664 typename = x86_cpu_type_name(cpu_model);
665 oc = object_class_by_name(typename);
666 g_free(typename);
667 return oc;
500050d1
AF		 668}
669
d940ee9b 670struct X86CPUDefinition {
c6dc6f63
AP		 671 const char *name;
672 uint32_t level;
90e4b0c3
EH		 673 uint32_t xlevel;
674 uint32_t xlevel2;
99b88a17
IM		 675 /* vendor is zero-terminated, 12 character ASCII string */
676 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 677 int family;
678 int model;
679 int stepping;
0514ef2f 680 FeatureWordArray features;
c6dc6f63 681 char model_id[48];
d940ee9b 682};
c6dc6f63 683
9576de75 684static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 685 {
686 .name = "qemu64",
3046bb5d 687 .level = 0xd,
99b88a17 688 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 689 .family = 6,
f8e6a11a 690 .model = 6,
c6dc6f63 691 .stepping = 3,
0514ef2f 692 .features[FEAT_1_EDX] =
27861ecc 693 PPRO_FEATURES |
c6dc6f63 694 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 695 CPUID_PSE36,
0514ef2f 696 .features[FEAT_1_ECX] =
6aa91e4a 697 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 698 .features[FEAT_8000_0001_EDX] =
c6dc6f63 699 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 700 .features[FEAT_8000_0001_ECX] =
71195672 701 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 702 .xlevel = 0x8000000A,
c6dc6f63
AP		 703 },
704 {
705 .name = "phenom",
706 .level = 5,
99b88a17 707 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 708 .family = 16,
709 .model = 2,
710 .stepping = 3,
b9fc20bc 711 /* Missing: CPUID_HT */
0514ef2f 712 .features[FEAT_1_EDX] =
27861ecc 713 PPRO_FEATURES |
c6dc6f63 714 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 715 CPUID_PSE36 | CPUID_VME,
0514ef2f 716 .features[FEAT_1_ECX] =
27861ecc 717 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 718 CPUID_EXT_POPCNT,
0514ef2f 719 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 720 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
721 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 722 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 723 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
724 CPUID_EXT3_CR8LEG,
725 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
726 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 727 .features[FEAT_8000_0001_ECX] =
27861ecc 728 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 729 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 730 /* Missing: CPUID_SVM_LBRV */
0514ef2f 731 .features[FEAT_SVM] =
b9fc20bc 732 CPUID_SVM_NPT,
c6dc6f63
AP		 733 .xlevel = 0x8000001A,
734 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
735 },
736 {
737 .name = "core2duo",
738 .level = 10,
99b88a17 739 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 740 .family = 6,
741 .model = 15,
742 .stepping = 11,
b9fc20bc 743 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 744 .features[FEAT_1_EDX] =
27861ecc 745 PPRO_FEATURES |
c6dc6f63 746 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 747 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
748 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 749 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 750 .features[FEAT_1_ECX] =
27861ecc 751 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 752 CPUID_EXT_CX16,
0514ef2f 753 .features[FEAT_8000_0001_EDX] =
27861ecc 754 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 755 .features[FEAT_8000_0001_ECX] =
27861ecc 756 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 757 .xlevel = 0x80000008,
758 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
759 },
760 {
761 .name = "kvm64",
3046bb5d 762 .level = 0xd,
99b88a17 763 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 764 .family = 15,
765 .model = 6,
766 .stepping = 1,
b3a4f0b1 767 /* Missing: CPUID_HT */
0514ef2f 768 .features[FEAT_1_EDX] =
b3a4f0b1 769 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 770 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
771 CPUID_PSE36,
772 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 773 .features[FEAT_1_ECX] =
27861ecc 774 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 775 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 776 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 777 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
778 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
779 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
780 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
781 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 782 .features[FEAT_8000_0001_ECX] =
27861ecc 783 0,
c6dc6f63
AP		 784 .xlevel = 0x80000008,
785 .model_id = "Common KVM processor"
786 },
c6dc6f63
AP		 787 {
788 .name = "qemu32",
789 .level = 4,
99b88a17 790 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 791 .family = 6,
f8e6a11a 792 .model = 6,
c6dc6f63 793 .stepping = 3,
0514ef2f 794 .features[FEAT_1_EDX] =
27861ecc 795 PPRO_FEATURES,
0514ef2f 796 .features[FEAT_1_ECX] =
6aa91e4a 797 CPUID_EXT_SSE3,
58012d66 798 .xlevel = 0x80000004,
c6dc6f63 799 },
eafaf1e5
AP		 800 {
801 .name = "kvm32",
802 .level = 5,
99b88a17 803 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 804 .family = 15,
805 .model = 6,
806 .stepping = 1,
0514ef2f 807 .features[FEAT_1_EDX] =
b3a4f0b1 808 PPRO_FEATURES | CPUID_VME |
eafaf1e5 809 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 810 .features[FEAT_1_ECX] =
27861ecc 811 CPUID_EXT_SSE3,
0514ef2f 812 .features[FEAT_8000_0001_ECX] =
27861ecc 813 0,
eafaf1e5
AP		 814 .xlevel = 0x80000008,
815 .model_id = "Common 32-bit KVM processor"
816 },
c6dc6f63
AP		 817 {
818 .name = "coreduo",
819 .level = 10,
99b88a17 820 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 821 .family = 6,
822 .model = 14,
823 .stepping = 8,
b9fc20bc 824 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 825 .features[FEAT_1_EDX] =
27861ecc 826 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 827 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
828 CPUID_SS,
829 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 830 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 831 .features[FEAT_1_ECX] =
e93abc14 832 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 833 .features[FEAT_8000_0001_EDX] =
27861ecc 834 CPUID_EXT2_NX,
c6dc6f63
AP		 835 .xlevel = 0x80000008,
836 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
837 },
838 {
839 .name = "486",
58012d66 840 .level = 1,
99b88a17 841 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 842 .family = 4,
b2a856d9 843 .model = 8,
c6dc6f63 844 .stepping = 0,
0514ef2f 845 .features[FEAT_1_EDX] =
27861ecc 846 I486_FEATURES,
c6dc6f63
AP		 847 .xlevel = 0,
848 },
849 {
850 .name = "pentium",
851 .level = 1,
99b88a17 852 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 853 .family = 5,
854 .model = 4,
855 .stepping = 3,
0514ef2f 856 .features[FEAT_1_EDX] =
27861ecc 857 PENTIUM_FEATURES,
c6dc6f63
AP		 858 .xlevel = 0,
859 },
860 {
861 .name = "pentium2",
862 .level = 2,
99b88a17 863 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 864 .family = 6,
865 .model = 5,
866 .stepping = 2,
0514ef2f 867 .features[FEAT_1_EDX] =
27861ecc 868 PENTIUM2_FEATURES,
c6dc6f63
AP		 869 .xlevel = 0,
870 },
871 {
872 .name = "pentium3",
3046bb5d 873 .level = 3,
99b88a17 874 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 875 .family = 6,
876 .model = 7,
877 .stepping = 3,
0514ef2f 878 .features[FEAT_1_EDX] =
27861ecc 879 PENTIUM3_FEATURES,
c6dc6f63
AP		 880 .xlevel = 0,
881 },
882 {
883 .name = "athlon",
884 .level = 2,
99b88a17 885 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 886 .family = 6,
887 .model = 2,
888 .stepping = 3,
0514ef2f 889 .features[FEAT_1_EDX] =
27861ecc 890 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 891 CPUID_MCA,
0514ef2f 892 .features[FEAT_8000_0001_EDX] =
60032ac0 893 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 894 .xlevel = 0x80000008,
c6dc6f63
AP		 895 },
896 {
897 .name = "n270",
3046bb5d 898 .level = 10,
99b88a17 899 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 900 .family = 6,
901 .model = 28,
902 .stepping = 2,
b9fc20bc 903 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 904 .features[FEAT_1_EDX] =
27861ecc 905 PPRO_FEATURES |
b9fc20bc
EH		 906 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
907 CPUID_ACPI | CPUID_SS,
c6dc6f63 908 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 909 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
910 * CPUID_EXT_XTPR */
0514ef2f 911 .features[FEAT_1_ECX] =
27861ecc 912 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 913 CPUID_EXT_MOVBE,
0514ef2f 914 .features[FEAT_8000_0001_EDX] =
60032ac0 915 CPUID_EXT2_NX,
0514ef2f 916 .features[FEAT_8000_0001_ECX] =
27861ecc 917 CPUID_EXT3_LAHF_LM,
3046bb5d 918 .xlevel = 0x80000008,
c6dc6f63
AP		 919 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
920 },
3eca4642
EH		 921 {
922 .name = "Conroe",
3046bb5d 923 .level = 10,
99b88a17 924 .vendor = CPUID_VENDOR_INTEL,
3eca4642 925 .family = 6,
ffce9ebb 926 .model = 15,
3eca4642 927 .stepping = 3,
0514ef2f 928 .features[FEAT_1_EDX] =
b3a4f0b1 929 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 930 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
931 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
932 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
933 CPUID_DE | CPUID_FP87,
0514ef2f 934 .features[FEAT_1_ECX] =
27861ecc 935 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 936 .features[FEAT_8000_0001_EDX] =
27861ecc 937 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 938 .features[FEAT_8000_0001_ECX] =
27861ecc 939 CPUID_EXT3_LAHF_LM,
3046bb5d 940 .xlevel = 0x80000008,
3eca4642
EH		 941 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
942 },
943 {
944 .name = "Penryn",
3046bb5d 945 .level = 10,
99b88a17 946 .vendor = CPUID_VENDOR_INTEL,
3eca4642 947 .family = 6,
ffce9ebb 948 .model = 23,
3eca4642 949 .stepping = 3,
0514ef2f 950 .features[FEAT_1_EDX] =
b3a4f0b1 951 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
955 CPUID_DE | CPUID_FP87,
0514ef2f 956 .features[FEAT_1_ECX] =
27861ecc 957 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 958 CPUID_EXT_SSE3,
0514ef2f 959 .features[FEAT_8000_0001_EDX] =
27861ecc 960 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 961 .features[FEAT_8000_0001_ECX] =
27861ecc 962 CPUID_EXT3_LAHF_LM,
3046bb5d 963 .xlevel = 0x80000008,
3eca4642
EH		 964 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
965 },
966 {
967 .name = "Nehalem",
3046bb5d 968 .level = 11,
99b88a17 969 .vendor = CPUID_VENDOR_INTEL,
3eca4642 970 .family = 6,
ffce9ebb 971 .model = 26,
3eca4642 972 .stepping = 3,
0514ef2f 973 .features[FEAT_1_EDX] =
b3a4f0b1 974 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 975 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
976 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
977 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
978 CPUID_DE | CPUID_FP87,
0514ef2f 979 .features[FEAT_1_ECX] =
27861ecc 980 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 981 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 982 .features[FEAT_8000_0001_EDX] =
27861ecc 983 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 984 .features[FEAT_8000_0001_ECX] =
27861ecc 985 CPUID_EXT3_LAHF_LM,
3046bb5d 986 .xlevel = 0x80000008,
3eca4642
EH		 987 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
988 },
989 {
990 .name = "Westmere",
991 .level = 11,
99b88a17 992 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 993 .family = 6,
994 .model = 44,
995 .stepping = 1,
0514ef2f 996 .features[FEAT_1_EDX] =
b3a4f0b1 997 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 998 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
999 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1000 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1001 CPUID_DE | CPUID_FP87,
0514ef2f 1002 .features[FEAT_1_ECX] =
27861ecc 1003 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1004 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1005 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1006 .features[FEAT_8000_0001_EDX] =
27861ecc 1007 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1008 .features[FEAT_8000_0001_ECX] =
27861ecc 1009 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1010 .features[FEAT_6_EAX] =
1011 CPUID_6_EAX_ARAT,
3046bb5d 1012 .xlevel = 0x80000008,
3eca4642
EH		 1013 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1014 },
1015 {
1016 .name = "SandyBridge",
1017 .level = 0xd,
99b88a17 1018 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1019 .family = 6,
1020 .model = 42,
1021 .stepping = 1,
0514ef2f 1022 .features[FEAT_1_EDX] =
b3a4f0b1 1023 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1024 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1025 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1026 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1027 CPUID_DE | CPUID_FP87,
0514ef2f 1028 .features[FEAT_1_ECX] =
27861ecc 1029 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1030 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1031 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1032 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1033 CPUID_EXT_SSE3,
0514ef2f 1034 .features[FEAT_8000_0001_EDX] =
27861ecc 1035 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1036 CPUID_EXT2_SYSCALL,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1039 .features[FEAT_XSAVE] =
1040 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1041 .features[FEAT_6_EAX] =
1042 CPUID_6_EAX_ARAT,
3046bb5d 1043 .xlevel = 0x80000008,
3eca4642
EH		 1044 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1045 },
2f9ac42a
PB		 1046 {
1047 .name = "IvyBridge",
1048 .level = 0xd,
1049 .vendor = CPUID_VENDOR_INTEL,
1050 .family = 6,
1051 .model = 58,
1052 .stepping = 9,
1053 .features[FEAT_1_EDX] =
1054 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1055 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1056 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1057 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1058 CPUID_DE | CPUID_FP87,
1059 .features[FEAT_1_ECX] =
1060 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1062 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1063 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1064 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1065 .features[FEAT_7_0_EBX] =
1066 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1067 CPUID_7_0_EBX_ERMS,
1068 .features[FEAT_8000_0001_EDX] =
1069 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1070 CPUID_EXT2_SYSCALL,
1071 .features[FEAT_8000_0001_ECX] =
1072 CPUID_EXT3_LAHF_LM,
1073 .features[FEAT_XSAVE] =
1074 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1075 .features[FEAT_6_EAX] =
1076 CPUID_6_EAX_ARAT,
3046bb5d 1077 .xlevel = 0x80000008,
2f9ac42a
PB		 1078 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1079 },
37507094 1080 {
a356850b
EH		 1081 .name = "Haswell-noTSX",
1082 .level = 0xd,
1083 .vendor = CPUID_VENDOR_INTEL,
1084 .family = 6,
1085 .model = 60,
1086 .stepping = 1,
1087 .features[FEAT_1_EDX] =
1088 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1089 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1090 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1091 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1092 CPUID_DE | CPUID_FP87,
1093 .features[FEAT_1_ECX] =
1094 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1095 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1096 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1097 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1098 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1099 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1100 .features[FEAT_8000_0001_EDX] =
1101 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1102 CPUID_EXT2_SYSCALL,
1103 .features[FEAT_8000_0001_ECX] =
becb6667 1104 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1105 .features[FEAT_7_0_EBX] =
1106 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1107 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1108 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1109 .features[FEAT_XSAVE] =
1110 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1111 .features[FEAT_6_EAX] =
1112 CPUID_6_EAX_ARAT,
3046bb5d 1113 .xlevel = 0x80000008,
a356850b
EH		 1114 .model_id = "Intel Core Processor (Haswell, no TSX)",
1115 }, {
37507094
EH		 1116 .name = "Haswell",
1117 .level = 0xd,
99b88a17 1118 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1119 .family = 6,
1120 .model = 60,
1121 .stepping = 1,
0514ef2f 1122 .features[FEAT_1_EDX] =
b3a4f0b1 1123 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1124 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1125 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1126 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1127 CPUID_DE | CPUID_FP87,
0514ef2f 1128 .features[FEAT_1_ECX] =
27861ecc 1129 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1130 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1131 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1132 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1133 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1134 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1135 .features[FEAT_8000_0001_EDX] =
27861ecc 1136 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1137 CPUID_EXT2_SYSCALL,
0514ef2f 1138 .features[FEAT_8000_0001_ECX] =
becb6667 1139 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1140 .features[FEAT_7_0_EBX] =
27861ecc 1141 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1142 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1143 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1144 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1145 .features[FEAT_XSAVE] =
1146 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1147 .features[FEAT_6_EAX] =
1148 CPUID_6_EAX_ARAT,
3046bb5d 1149 .xlevel = 0x80000008,
37507094
EH		 1150 .model_id = "Intel Core Processor (Haswell)",
1151 },
a356850b
EH		 1152 {
1153 .name = "Broadwell-noTSX",
1154 .level = 0xd,
1155 .vendor = CPUID_VENDOR_INTEL,
1156 .family = 6,
1157 .model = 61,
1158 .stepping = 2,
1159 .features[FEAT_1_EDX] =
1160 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1161 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1162 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1163 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1164 CPUID_DE | CPUID_FP87,
1165 .features[FEAT_1_ECX] =
1166 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1167 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1168 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1169 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1170 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1171 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1172 .features[FEAT_8000_0001_EDX] =
1173 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1174 CPUID_EXT2_SYSCALL,
1175 .features[FEAT_8000_0001_ECX] =
becb6667 1176 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1177 .features[FEAT_7_0_EBX] =
1178 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1179 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1180 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1181 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1182 CPUID_7_0_EBX_SMAP,
1183 .features[FEAT_XSAVE] =
1184 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1185 .features[FEAT_6_EAX] =
1186 CPUID_6_EAX_ARAT,
3046bb5d 1187 .xlevel = 0x80000008,
a356850b
EH		 1188 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1189 },
ece01354
EH		 1190 {
1191 .name = "Broadwell",
1192 .level = 0xd,
1193 .vendor = CPUID_VENDOR_INTEL,
1194 .family = 6,
1195 .model = 61,
1196 .stepping = 2,
1197 .features[FEAT_1_EDX] =
b3a4f0b1 1198 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1199 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1200 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1201 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1202 CPUID_DE | CPUID_FP87,
1203 .features[FEAT_1_ECX] =
1204 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1205 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1206 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1207 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1208 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1209 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1210 .features[FEAT_8000_0001_EDX] =
1211 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1212 CPUID_EXT2_SYSCALL,
1213 .features[FEAT_8000_0001_ECX] =
becb6667 1214 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1215 .features[FEAT_7_0_EBX] =
1216 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1217 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1218 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1219 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1220 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1221 .features[FEAT_XSAVE] =
1222 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1223 .features[FEAT_6_EAX] =
1224 CPUID_6_EAX_ARAT,
3046bb5d 1225 .xlevel = 0x80000008,
ece01354
EH		 1226 .model_id = "Intel Core Processor (Broadwell)",
1227 },
3eca4642
EH		 1228 {
1229 .name = "Opteron_G1",
1230 .level = 5,
99b88a17 1231 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1232 .family = 15,
1233 .model = 6,
1234 .stepping = 1,
0514ef2f 1235 .features[FEAT_1_EDX] =
b3a4f0b1 1236 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1237 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1238 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1239 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1240 CPUID_DE | CPUID_FP87,
0514ef2f 1241 .features[FEAT_1_ECX] =
27861ecc 1242 CPUID_EXT_SSE3,
0514ef2f 1243 .features[FEAT_8000_0001_EDX] =
27861ecc 1244 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1245 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1246 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1247 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1248 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1249 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1250 .xlevel = 0x80000008,
1251 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1252 },
1253 {
1254 .name = "Opteron_G2",
1255 .level = 5,
99b88a17 1256 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1257 .family = 15,
1258 .model = 6,
1259 .stepping = 1,
0514ef2f 1260 .features[FEAT_1_EDX] =
b3a4f0b1 1261 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1262 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1263 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1264 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1265 CPUID_DE | CPUID_FP87,
0514ef2f 1266 .features[FEAT_1_ECX] =
27861ecc 1267 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1268 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1269 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1270 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1271 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1272 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1273 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1274 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1275 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1276 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1277 .features[FEAT_8000_0001_ECX] =
27861ecc 1278 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1279 .xlevel = 0x80000008,
1280 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1281 },
1282 {
1283 .name = "Opteron_G3",
1284 .level = 5,
99b88a17 1285 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1286 .family = 15,
1287 .model = 6,
1288 .stepping = 1,
0514ef2f 1289 .features[FEAT_1_EDX] =
b3a4f0b1 1290 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1291 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1292 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1293 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1294 CPUID_DE | CPUID_FP87,
0514ef2f 1295 .features[FEAT_1_ECX] =
27861ecc 1296 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1297 CPUID_EXT_SSE3,
33b5e8c0 1298 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1299 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1300 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1301 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1302 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1303 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1304 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1305 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1306 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1307 .features[FEAT_8000_0001_ECX] =
27861ecc 1308 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1309 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1310 .xlevel = 0x80000008,
1311 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1312 },
1313 {
1314 .name = "Opteron_G4",
1315 .level = 0xd,
99b88a17 1316 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1317 .family = 21,
1318 .model = 1,
1319 .stepping = 2,
0514ef2f 1320 .features[FEAT_1_EDX] =
b3a4f0b1 1321 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1322 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1323 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1324 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1325 CPUID_DE | CPUID_FP87,
0514ef2f 1326 .features[FEAT_1_ECX] =
27861ecc 1327 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1328 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1329 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1330 CPUID_EXT_SSE3,
33b5e8c0 1331 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1332 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1333 CPUID_EXT2_LM |
b3fb3a20
EH		 1334 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1335 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1336 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1337 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1338 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1339 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1340 .features[FEAT_8000_0001_ECX] =
27861ecc 1341 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1342 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1343 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1344 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1345 /* no xsaveopt! */
3eca4642
EH		 1346 .xlevel = 0x8000001A,
1347 .model_id = "AMD Opteron 62xx class CPU",
1348 },
021941b9
AP		 1349 {
1350 .name = "Opteron_G5",
1351 .level = 0xd,
99b88a17 1352 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1353 .family = 21,
1354 .model = 2,
1355 .stepping = 0,
0514ef2f 1356 .features[FEAT_1_EDX] =
b3a4f0b1 1357 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1358 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1359 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1360 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1361 CPUID_DE | CPUID_FP87,
0514ef2f 1362 .features[FEAT_1_ECX] =
27861ecc 1363 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1364 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1365 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1366 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1367 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1368 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1369 CPUID_EXT2_LM |
b3fb3a20
EH		 1370 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1371 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1372 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1373 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1374 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1375 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1376 .features[FEAT_8000_0001_ECX] =
27861ecc 1377 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1378 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1379 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1380 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1381 /* no xsaveopt! */
021941b9
AP		 1382 .xlevel = 0x8000001A,
1383 .model_id = "AMD Opteron 63xx class CPU",
1384 },
c6dc6f63
AP		 1385};
1386
5114e842
EH		 1387typedef struct PropValue {
1388 const char *prop, *value;
1389} PropValue;
1390
1391/* KVM-specific features that are automatically added/removed
1392 * from all CPU models when KVM is enabled.
1393 */
1394static PropValue kvm_default_props[] = {
1395 { "kvmclock", "on" },
1396 { "kvm-nopiodelay", "on" },
1397 { "kvm-asyncpf", "on" },
1398 { "kvm-steal-time", "on" },
1399 { "kvm-pv-eoi", "on" },
1400 { "kvmclock-stable-bit", "on" },
1401 { "x2apic", "on" },
1402 { "acpi", "off" },
1403 { "monitor", "off" },
1404 { "svm", "off" },
1405 { NULL, NULL },
1406};
1407
1408void x86_cpu_change_kvm_default(const char *prop, const char *value)
1409{
1410 PropValue *pv;
1411 for (pv = kvm_default_props; pv->prop; pv++) {
1412 if (!strcmp(pv->prop, prop)) {
1413 pv->value = value;
1414 break;
1415 }
1416 }
1417
1418 /* It is valid to call this function only for properties that
1419 * are already present in the kvm_default_props table.
1420 */
1421 assert(pv->prop);
1422}
1423
4d1b279b
EH		 1424static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1425 bool migratable_only);
1426
d940ee9b
EH		 1427#ifdef CONFIG_KVM
1428
c6dc6f63
AP		 1429static int cpu_x86_fill_model_id(char *str)
1430{
1431 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1432 int i;
1433
1434 for (i = 0; i < 3; i++) {
1435 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1436 memcpy(str + i * 16 + 0, &eax, 4);
1437 memcpy(str + i * 16 + 4, &ebx, 4);
1438 memcpy(str + i * 16 + 8, &ecx, 4);
1439 memcpy(str + i * 16 + 12, &edx, 4);
1440 }
1441 return 0;
1442}
1443
d940ee9b
EH		 1444static X86CPUDefinition host_cpudef;
1445
84f1b92f 1446static Property host_x86_cpu_properties[] = {
120eee7d 1447 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1448 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1449 DEFINE_PROP_END_OF_LIST()
1450};
1451
d940ee9b 1452/* class_init for the "host" CPU model
6e746f30 1453 *
d940ee9b 1454 * This function may be called before KVM is initialized.
6e746f30 1455 */
d940ee9b 1456static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1457{
84f1b92f 1458 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1459 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1460 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1461
d940ee9b 1462 xcc->kvm_required = true;
6e746f30 1463
c6dc6f63 1464 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1465 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1466
1467 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1468 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1469 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1470 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1471
d940ee9b 1472 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1473
d940ee9b 1474 xcc->cpu_def = &host_cpudef;
d940ee9b
EH		 1475
1476 /* level, xlevel, xlevel2, and the feature words are initialized on
1477 * instance_init, because they require KVM to be initialized.
1478 */
84f1b92f
EH		 1479
1480 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1481 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1482 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1483}
1484
1485static void host_x86_cpu_initfn(Object *obj)
1486{
1487 X86CPU *cpu = X86_CPU(obj);
1488 CPUX86State *env = &cpu->env;
1489 KVMState *s = kvm_state;
d940ee9b
EH		 1490
1491 assert(kvm_enabled());
1492
4d1b279b
EH		 1493 /* We can't fill the features array here because we don't know yet if
1494 * "migratable" is true or false.
1495 */
1496 cpu->host_features = true;
1497
d940ee9b
EH		 1498 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1499 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1500 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1501
d940ee9b 1502 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1503}
1504
d940ee9b
EH		 1505static const TypeInfo host_x86_cpu_type_info = {
1506 .name = X86_CPU_TYPE_NAME("host"),
1507 .parent = TYPE_X86_CPU,
1508 .instance_init = host_x86_cpu_initfn,
1509 .class_init = host_x86_cpu_class_init,
1510};
1511
1512#endif
1513
8459e396 1514static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1515{
8459e396 1516 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1517 int i;
1518
857aee33 1519 for (i = 0; i < 32; ++i) {
72370dc1 1520 if ((1UL << i) & mask) {
bffd67b0 1521 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1522 assert(reg);
fefb41bf 1523 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1524 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1525 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1526 f->cpuid_eax, reg,
1527 f->feat_names[i] ? "." : "",
1528 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1529 }
857aee33 1530 }
c6dc6f63
AP		 1531}
1532
95b8519d
AF		 1533static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1534 const char *name, Error **errp)
1535{
1536 X86CPU *cpu = X86_CPU(obj);
1537 CPUX86State *env = &cpu->env;
1538 int64_t value;
1539
1540 value = (env->cpuid_version >> 8) & 0xf;
1541 if (value == 0xf) {
1542 value += (env->cpuid_version >> 20) & 0xff;
1543 }
51e72bc1 1544 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1545}
1546
71ad61d3
AF		 1547static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1548 const char *name, Error **errp)
ed5e1ec3 1549{
71ad61d3
AF		 1550 X86CPU *cpu = X86_CPU(obj);
1551 CPUX86State *env = &cpu->env;
1552 const int64_t min = 0;
1553 const int64_t max = 0xff + 0xf;
65cd9064 1554 Error *local_err = NULL;
71ad61d3
AF		 1555 int64_t value;
1556
51e72bc1 1557 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1558 if (local_err) {
1559 error_propagate(errp, local_err);
71ad61d3
AF		 1560 return;
1561 }
1562 if (value < min || value > max) {
c6bd8c70
MA		 1563 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1564 name ? name : "null", value, min, max);
71ad61d3
AF		 1565 return;
1566 }
1567
ed5e1ec3 1568 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1569 if (value > 0x0f) {
1570 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1571 } else {
71ad61d3 1572 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1573 }
1574}
1575
67e30c83
AF		 1576static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1577 const char *name, Error **errp)
1578{
1579 X86CPU *cpu = X86_CPU(obj);
1580 CPUX86State *env = &cpu->env;
1581 int64_t value;
1582
1583 value = (env->cpuid_version >> 4) & 0xf;
1584 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1585 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1586}
1587
c5291a4f
AF		 1588static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1589 const char *name, Error **errp)
b0704cbd 1590{
c5291a4f
AF		 1591 X86CPU *cpu = X86_CPU(obj);
1592 CPUX86State *env = &cpu->env;
1593 const int64_t min = 0;
1594 const int64_t max = 0xff;
65cd9064 1595 Error *local_err = NULL;
c5291a4f
AF		 1596 int64_t value;
1597
51e72bc1 1598 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1599 if (local_err) {
1600 error_propagate(errp, local_err);
c5291a4f
AF		 1601 return;
1602 }
1603 if (value < min || value > max) {
c6bd8c70
MA		 1604 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1605 name ? name : "null", value, min, max);
c5291a4f
AF		 1606 return;
1607 }
1608
b0704cbd 1609 env->cpuid_version &= ~0xf00f0;
c5291a4f 1610 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1611}
1612
35112e41
AF		 1613static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1614 void *opaque, const char *name,
1615 Error **errp)
1616{
1617 X86CPU *cpu = X86_CPU(obj);
1618 CPUX86State *env = &cpu->env;
1619 int64_t value;
1620
1621 value = env->cpuid_version & 0xf;
51e72bc1 1622 visit_type_int(v, name, &value, errp);
35112e41
AF		 1623}
1624
036e2222
AF		 1625static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1626 void *opaque, const char *name,
1627 Error **errp)
38c3dc46 1628{
036e2222
AF		 1629 X86CPU *cpu = X86_CPU(obj);
1630 CPUX86State *env = &cpu->env;
1631 const int64_t min = 0;
1632 const int64_t max = 0xf;
65cd9064 1633 Error *local_err = NULL;
036e2222
AF		 1634 int64_t value;
1635
51e72bc1 1636 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1637 if (local_err) {
1638 error_propagate(errp, local_err);
036e2222
AF		 1639 return;
1640 }
1641 if (value < min || value > max) {
c6bd8c70
MA		 1642 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1643 name ? name : "null", value, min, max);
036e2222
AF		 1644 return;
1645 }
1646
38c3dc46 1647 env->cpuid_version &= ~0xf;
036e2222 1648 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1649}
1650
d480e1af
AF		 1651static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1652{
1653 X86CPU *cpu = X86_CPU(obj);
1654 CPUX86State *env = &cpu->env;
1655 char *value;
d480e1af 1656
e42a92ae 1657 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1658 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1659 env->cpuid_vendor3);
d480e1af
AF		 1660 return value;
1661}
1662
1663static void x86_cpuid_set_vendor(Object *obj, const char *value,
1664 Error **errp)
1665{
1666 X86CPU *cpu = X86_CPU(obj);
1667 CPUX86State *env = &cpu->env;
1668 int i;
1669
9df694ee 1670 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1671 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1672 return;
1673 }
1674
1675 env->cpuid_vendor1 = 0;
1676 env->cpuid_vendor2 = 0;
1677 env->cpuid_vendor3 = 0;
1678 for (i = 0; i < 4; i++) {
1679 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1680 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1681 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1682 }
d480e1af
AF		 1683}
1684
63e886eb
AF		 1685static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1686{
1687 X86CPU *cpu = X86_CPU(obj);
1688 CPUX86State *env = &cpu->env;
1689 char *value;
1690 int i;
1691
1692 value = g_malloc(48 + 1);
1693 for (i = 0; i < 48; i++) {
1694 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1695 }
1696 value[48] = '\0';
1697 return value;
1698}
1699
938d4c25
AF		 1700static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1701 Error **errp)
dcce6675 1702{
938d4c25
AF		 1703 X86CPU *cpu = X86_CPU(obj);
1704 CPUX86State *env = &cpu->env;
dcce6675
AF		 1705 int c, len, i;
1706
1707 if (model_id == NULL) {
1708 model_id = "";
1709 }
1710 len = strlen(model_id);
d0a6acf4 1711 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1712 for (i = 0; i < 48; i++) {
1713 if (i >= len) {
1714 c = '\0';
1715 } else {
1716 c = (uint8_t)model_id[i];
1717 }
1718 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1719 }
1720}
1721
89e48965
AF		 1722static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1723 const char *name, Error **errp)
1724{
1725 X86CPU *cpu = X86_CPU(obj);
1726 int64_t value;
1727
1728 value = cpu->env.tsc_khz * 1000;
51e72bc1 1729 visit_type_int(v, name, &value, errp);
89e48965
AF		 1730}
1731
1732static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1733 const char *name, Error **errp)
1734{
1735 X86CPU *cpu = X86_CPU(obj);
1736 const int64_t min = 0;
2e84849a 1737 const int64_t max = INT64_MAX;
65cd9064 1738 Error *local_err = NULL;
89e48965
AF		 1739 int64_t value;
1740
51e72bc1 1741 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1742 if (local_err) {
1743 error_propagate(errp, local_err);
89e48965
AF		 1744 return;
1745 }
1746 if (value < min || value > max) {
c6bd8c70
MA		 1747 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1748 name ? name : "null", value, min, max);
89e48965
AF		 1749 return;
1750 }
1751
36f96c4b 1752 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1753}
1754
31050930
IM		 1755static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1756 const char *name, Error **errp)
1757{
1758 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1759 int64_t value = cpu->apic_id;
31050930 1760
51e72bc1 1761 visit_type_int(v, name, &value, errp);
31050930
IM		 1762}
1763
1764static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1765 const char *name, Error **errp)
1766{
1767 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1768 DeviceState *dev = DEVICE(obj);
31050930
IM		 1769 const int64_t min = 0;
1770 const int64_t max = UINT32_MAX;
1771 Error *error = NULL;
1772 int64_t value;
1773
8d6d4980
IM		 1774 if (dev->realized) {
1775 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1776 "it was realized", name, object_get_typename(obj));
1777 return;
1778 }
1779
51e72bc1 1780 visit_type_int(v, name, &value, &error);
31050930
IM		 1781 if (error) {
1782 error_propagate(errp, error);
1783 return;
1784 }
1785 if (value < min || value > max) {
1786 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1787 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1788 object_get_typename(obj), name, value, min, max);
1789 return;
1790 }
1791
7e72a45c 1792 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1793 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1794 return;
1795 }
7e72a45c 1796 cpu->apic_id = value;
31050930
IM		 1797}
1798
7e5292b5 1799/* Generic getter for "feature-words" and "filtered-features" properties */
8e8aba50
EH		 1800static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1801 const char *name, Error **errp)
1802{
7e5292b5 1803 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1804 FeatureWord w;
1805 Error *err = NULL;
1806 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1807 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1808 X86CPUFeatureWordInfoList *list = NULL;
1809
1810 for (w = 0; w < FEATURE_WORDS; w++) {
1811 FeatureWordInfo *wi = &feature_word_info[w];
1812 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1813 qwi->cpuid_input_eax = wi->cpuid_eax;
1814 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1815 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1816 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1817 qwi->features = array[w];
8e8aba50
EH		 1818
1819 /* List will be in reverse order, but order shouldn't matter */
1820 list_entries[w].next = list;
1821 list_entries[w].value = &word_infos[w];
1822 list = &list_entries[w];
1823 }
1824
51e72bc1 1825 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, &err);
8e8aba50
EH		 1826 error_propagate(errp, err);
1827}
1828
c8f0f88e
IM		 1829static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1830 const char *name, Error **errp)
1831{
1832 X86CPU *cpu = X86_CPU(obj);
1833 int64_t value = cpu->hyperv_spinlock_attempts;
1834
51e72bc1 1835 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1836}
1837
1838static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1839 const char *name, Error **errp)
1840{
1841 const int64_t min = 0xFFF;
1842 const int64_t max = UINT_MAX;
1843 X86CPU *cpu = X86_CPU(obj);
1844 Error *err = NULL;
1845 int64_t value;
1846
51e72bc1 1847 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1848 if (err) {
1849 error_propagate(errp, err);
1850 return;
1851 }
1852
1853 if (value < min || value > max) {
1854 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1855 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1856 object_get_typename(obj), name ? name : "null",
1857 value, min, max);
c8f0f88e
IM		 1858 return;
1859 }
1860 cpu->hyperv_spinlock_attempts = value;
1861}
1862
1863static PropertyInfo qdev_prop_spinlocks = {
1864 .name = "int",
1865 .get = x86_get_hv_spinlocks,
1866 .set = x86_set_hv_spinlocks,
1867};
1868
72ac2e87
IM		 1869/* Convert all '_' in a feature string option name to '-', to make feature
1870 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1871 */
1872static inline void feat2prop(char *s)
1873{
1874 while ((s = strchr(s, '_'))) {
1875 *s = '-';
1876 }
1877}
1878
8f961357
EH		 1879/* Parse "+feature,-feature,feature=foo" CPU feature string
1880 */
94a444b2
AF		 1881static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1882 Error **errp)
8f961357 1883{
94a444b2 1884 X86CPU *cpu = X86_CPU(cs);
8f961357 1885 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1886 FeatureWord w;
8f961357 1887 /* Features to be added */
077c68c3 1888 FeatureWordArray plus_features = { 0 };
8f961357 1889 /* Features to be removed */
5ef57876 1890 FeatureWordArray minus_features = { 0 };
8f961357 1891 uint32_t numvalue;
a91987c2 1892 CPUX86State *env = &cpu->env;
94a444b2 1893 Error *local_err = NULL;
8f961357 1894
8f961357 1895 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1896
1897 while (featurestr) {
1898 char *val;
1899 if (featurestr[0] == '+') {
c00c94ab 1900 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1901 } else if (featurestr[0] == '-') {
c00c94ab 1902 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1903 } else if ((val = strchr(featurestr, '='))) {
1904 *val = 0; val++;
72ac2e87 1905 feat2prop(featurestr);
d024d209 1906 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1907 char *err;
a91987c2
IM		 1908 char num[32];
1909
c6dc6f63
AP		 1910 numvalue = strtoul(val, &err, 0);
1911 if (!*val || *err) {
6b1dd54b
PB		 1912 error_setg(errp, "bad numerical value %s", val);
1913 return;
c6dc6f63
AP		 1914 }
1915 if (numvalue < 0x80000000) {
94a444b2
AF		 1916 error_report("xlevel value shall always be >= 0x80000000"
1917 ", fixup will be removed in future versions");
2f7a21c4 1918 numvalue += 0x80000000;
c6dc6f63 1919 }
a91987c2 1920 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1921 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1922 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1923 int64_t tsc_freq;
1924 char *err;
a91987c2 1925 char num[32];
b862d1fe 1926
4677bb40
MAL		 1927 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1928 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1929 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1930 error_setg(errp, "bad numerical value %s", val);
1931 return;
b862d1fe 1932 }
a91987c2 1933 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1934 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1935 &local_err);
72ac2e87 1936 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1937 char *err;
92067bf4 1938 const int min = 0xFFF;
c8f0f88e 1939 char num[32];
28f52cc0
VR		 1940 numvalue = strtoul(val, &err, 0);
1941 if (!*val || *err) {
6b1dd54b
PB		 1942 error_setg(errp, "bad numerical value %s", val);
1943 return;
28f52cc0 1944 }
92067bf4 1945 if (numvalue < min) {
94a444b2 1946 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1947 ", fixup will be removed in future versions",
1948 min);
92067bf4
IM		 1949 numvalue = min;
1950 }
c8f0f88e 1951 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1952 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1953 } else {
94a444b2 1954 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1955 }
c6dc6f63 1956 } else {
258f5abe 1957 feat2prop(featurestr);
94a444b2 1958 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1959 }
94a444b2
AF		 1960 if (local_err) {
1961 error_propagate(errp, local_err);
6b1dd54b 1962 return;
c6dc6f63
AP		 1963 }
1964 featurestr = strtok(NULL, ",");
1965 }
e1c224b4 1966
4d1b279b
EH		 1967 if (cpu->host_features) {
1968 for (w = 0; w < FEATURE_WORDS; w++) {
1969 env->features[w] =
1970 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1971 }
1972 }
1973
e1c224b4
EH		 1974 for (w = 0; w < FEATURE_WORDS; w++) {
1975 env->features[w] |= plus_features[w];
1976 env->features[w] &= ~minus_features[w];
1977 }
c6dc6f63
AP		 1978}
1979
8c3329e5 1980/* Print all cpuid feature names in featureset
c6dc6f63 1981 */
8c3329e5 1982static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1983{
8c3329e5
EH		 1984 int bit;
1985 bool first = true;
1986
1987 for (bit = 0; bit < 32; bit++) {
1988 if (featureset[bit]) {
1989 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1990 first = false;
c6dc6f63 1991 }
8c3329e5 1992 }
c6dc6f63
AP		 1993}
1994
e916cbf8
PM		 1995/* generate CPU information. */
1996void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 1997{
9576de75 1998 X86CPUDefinition *def;
c6dc6f63 1999 char buf[256];
7fc9b714 2000 int i;
c6dc6f63 2001
7fc9b714
AF		 2002 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2003 def = &builtin_x86_defs[i];
c04321b3 2004 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2005 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2006 }
21ad7789
JK		 2007#ifdef CONFIG_KVM
2008 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2009 "KVM processor with all supported host features "
2010 "(only available in KVM mode)");
2011#endif
2012
6cdf8854 2013 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2014 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2015 FeatureWordInfo *fw = &feature_word_info[i];
2016
8c3329e5
EH		 2017 (*cpu_fprintf)(f, " ");
2018 listflags(f, cpu_fprintf, fw->feat_names);
2019 (*cpu_fprintf)(f, "\n");
3af60be2 2020 }
c6dc6f63
AP		 2021}
2022
76b64a7a 2023CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2024{
2025 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2026 X86CPUDefinition *def;
7fc9b714 2027 int i;
e3966126 2028
7fc9b714 2029 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2030 CpuDefinitionInfoList *entry;
2031 CpuDefinitionInfo *info;
2032
7fc9b714 2033 def = &builtin_x86_defs[i];
e3966126
AL		 2034 info = g_malloc0(sizeof(*info));
2035 info->name = g_strdup(def->name);
2036
2037 entry = g_malloc0(sizeof(*entry));
2038 entry->value = info;
2039 entry->next = cpu_list;
2040 cpu_list = entry;
2041 }
2042
2043 return cpu_list;
2044}
2045
84f1b92f
EH		 2046static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2047 bool migratable_only)
27418adf
EH		 2048{
2049 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2050 uint32_t r;
27418adf 2051
fefb41bf 2052 if (kvm_enabled()) {
84f1b92f
EH		 2053 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2054 wi->cpuid_ecx,
2055 wi->cpuid_reg);
fefb41bf 2056 } else if (tcg_enabled()) {
84f1b92f 2057 r = wi->tcg_features;
fefb41bf
EH		 2058 } else {
2059 return ~0;
2060 }
84f1b92f
EH		 2061 if (migratable_only) {
2062 r &= x86_cpu_get_migratable_flags(w);
2063 }
2064 return r;
27418adf
EH		 2065}
2066
51f63aed
EH		 2067/*
2068 * Filters CPU feature words based on host availability of each feature.
2069 *
51f63aed
EH		 2070 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2071 */
27418adf 2072static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2073{
2074 CPUX86State *env = &cpu->env;
bd87d2a2 2075 FeatureWord w;
51f63aed
EH		 2076 int rv = 0;
2077
bd87d2a2 2078 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2079 uint32_t host_feat =
2080 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2081 uint32_t requested_features = env->features[w];
2082 env->features[w] &= host_feat;
2083 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2084 if (cpu->filtered_features[w]) {
2085 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2086 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2087 }
2088 rv = 1;
2089 }
bd87d2a2 2090 }
51f63aed
EH		 2091
2092 return rv;
bc74b7db 2093}
bc74b7db 2094
5114e842
EH		 2095static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2096{
2097 PropValue *pv;
2098 for (pv = props; pv->prop; pv++) {
2099 if (!pv->value) {
2100 continue;
2101 }
2102 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2103 &error_abort);
2104 }
2105}
2106
d940ee9b 2107/* Load data from X86CPUDefinition
c080e30e 2108 */
d940ee9b 2109static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2110{
61dcd775 2111 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2112 const char *vendor;
2113 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2114 FeatureWord w;
c6dc6f63 2115
2d64255b
AF		 2116 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2117 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2118 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2119 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2120 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2121 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2d64255b 2122 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2123 for (w = 0; w < FEATURE_WORDS; w++) {
2124 env->features[w] = def->features[w];
2125 }
82beb536 2126
9576de75 2127 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2128 if (kvm_enabled()) {
5114e842 2129 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2130 }
5fcca9ff 2131
82beb536 2132 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2133
2134 /* sysenter isn't supported in compatibility mode on AMD,
2135 * syscall isn't supported in compatibility mode on Intel.
2136 * Normally we advertise the actual CPU vendor, but you can
2137 * override this using the 'vendor' property if you want to use
2138 * KVM's sysenter/syscall emulation in compatibility mode and
2139 * when doing cross vendor migration
2140 */
74f54bc4 2141 vendor = def->vendor;
7c08db30
EH		 2142 if (kvm_enabled()) {
2143 uint32_t ebx = 0, ecx = 0, edx = 0;
2144 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2145 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2146 vendor = host_vendor;
2147 }
2148
2149 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2150
c6dc6f63
AP		 2151}
2152
e1570d00 2153X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2154{
2d64255b 2155 X86CPU *cpu = NULL;
d940ee9b 2156 X86CPUClass *xcc;
500050d1 2157 ObjectClass *oc;
2d64255b
AF		 2158 gchar **model_pieces;
2159 char *name, *features;
5c3c6a68
AF		 2160 Error *error = NULL;
2161
2d64255b
AF		 2162 model_pieces = g_strsplit(cpu_model, ",", 2);
2163 if (!model_pieces[0]) {
2164 error_setg(&error, "Invalid/empty CPU model name");
2165 goto out;
2166 }
2167 name = model_pieces[0];
2168 features = model_pieces[1];
2169
500050d1
AF		 2170 oc = x86_cpu_class_by_name(name);
2171 if (oc == NULL) {
2172 error_setg(&error, "Unable to find CPU definition: %s", name);
2173 goto out;
2174 }
d940ee9b
EH		 2175 xcc = X86_CPU_CLASS(oc);
2176
2177 if (xcc->kvm_required && !kvm_enabled()) {
2178 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2179 goto out;
2180 }
2181
d940ee9b
EH		 2182 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2183
94a444b2 2184 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2185 if (error) {
2186 goto out;
5c3c6a68
AF		 2187 }
2188
7f833247 2189out:
cd7b87ff
AF		 2190 if (error != NULL) {
2191 error_propagate(errp, error);
500050d1
AF		 2192 if (cpu) {
2193 object_unref(OBJECT(cpu));
2194 cpu = NULL;
2195 }
cd7b87ff 2196 }
7f833247
IM		 2197 g_strfreev(model_pieces);
2198 return cpu;
2199}
2200
0856579c 2201X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2202{
2203 Error *error = NULL;
2204 X86CPU *cpu;
2205
e1570d00 2206 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2207 if (error) {
0856579c 2208 goto out;
9c235e83 2209 }
7f833247 2210
7f833247 2211 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2212
0856579c
PM		 2213out:
2214 if (error) {
2215 error_report_err(error);
2216 if (cpu != NULL) {
2217 object_unref(OBJECT(cpu));
2218 cpu = NULL;
2219 }
18b0e4e7 2220 }
0856579c 2221 return cpu;
5c3c6a68
AF		 2222}
2223
d940ee9b
EH		 2224static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2225{
2226 X86CPUDefinition *cpudef = data;
2227 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2228
2229 xcc->cpu_def = cpudef;
2230}
2231
2232static void x86_register_cpudef_type(X86CPUDefinition *def)
2233{
2234 char *typename = x86_cpu_type_name(def->name);
2235 TypeInfo ti = {
2236 .name = typename,
2237 .parent = TYPE_X86_CPU,
2238 .class_init = x86_cpu_cpudef_class_init,
2239 .class_data = def,
2240 };
2241
2242 type_register(&ti);
2243 g_free(typename);
2244}
2245
c6dc6f63 2246#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2247
0e26b7b8
BS		 2248void cpu_clear_apic_feature(CPUX86State *env)
2249{
0514ef2f 2250 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2251}
2252
c6dc6f63
AP		 2253#endif /* !CONFIG_USER_ONLY */
2254
c04321b3 2255/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2256 */
2257void x86_cpudef_setup(void)
2258{
93bfef4c
CV		 2259 int i, j;
2260 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2261
2262 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2263 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2264
2265 /* Look for specific "cpudef" models that */
09faecf2 2266 /* have the QEMU version in .model_id */
93bfef4c 2267 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2268 if (strcmp(model_with_versions[j], def->name) == 0) {
2269 pstrcpy(def->model_id, sizeof(def->model_id),
2270 "QEMU Virtual CPU version ");
2271 pstrcat(def->model_id, sizeof(def->model_id),
35c2c8dc 2272 qemu_hw_version());
93bfef4c
CV		 2273 break;
2274 }
2275 }
c6dc6f63 2276 }
c6dc6f63
AP		 2277}
2278
c6dc6f63
AP		 2279void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2280 uint32_t *eax, uint32_t *ebx,
2281 uint32_t *ecx, uint32_t *edx)
2282{
a60f24b5
AF		 2283 X86CPU *cpu = x86_env_get_cpu(env);
2284 CPUState *cs = CPU(cpu);
2285
c6dc6f63
AP		 2286 /* test if maximum index reached */
2287 if (index & 0x80000000) {
b3baa152
BW		 2288 if (index > env->cpuid_xlevel) {
2289 if (env->cpuid_xlevel2 > 0) {
2290 /* Handle the Centaur's CPUID instruction. */
2291 if (index > env->cpuid_xlevel2) {
2292 index = env->cpuid_xlevel2;
2293 } else if (index < 0xC0000000) {
2294 index = env->cpuid_xlevel;
2295 }
2296 } else {
57f26ae7
EH		 2297 /* Intel documentation states that invalid EAX input will
2298 * return the same information as EAX=cpuid_level
2299 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2300 */
2301 index = env->cpuid_level;
b3baa152
BW		 2302 }
2303 }
c6dc6f63
AP		 2304 } else {
2305 if (index > env->cpuid_level)
2306 index = env->cpuid_level;
2307 }
2308
2309 switch(index) {
2310 case 0:
2311 *eax = env->cpuid_level;
5eb2f7a4
EH		 2312 *ebx = env->cpuid_vendor1;
2313 *edx = env->cpuid_vendor2;
2314 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2315 break;
2316 case 1:
2317 *eax = env->cpuid_version;
7e72a45c
EH		 2318 *ebx = (cpu->apic_id << 24) |
2319 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f
EH		 2320 *ecx = env->features[FEAT_1_ECX];
2321 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2322 if (cs->nr_cores * cs->nr_threads > 1) {
2323 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
c6dc6f63
AP		 2324 *edx |= 1 << 28; /* HTT bit */
2325 }
2326 break;
2327 case 2:
2328 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2329 if (cpu->cache_info_passthrough) {
2330 host_cpuid(index, 0, eax, ebx, ecx, edx);
2331 break;
2332 }
5e891bf8 2333 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2334 *ebx = 0;
2335 *ecx = 0;
5e891bf8
EH		 2336 *edx = (L1D_DESCRIPTOR << 16) | \
2337 (L1I_DESCRIPTOR << 8) | \
2338 (L2_DESCRIPTOR);
c6dc6f63
AP		 2339 break;
2340 case 4:
2341 /* cache info: needed for Core compatibility */
787aaf57
BC		 2342 if (cpu->cache_info_passthrough) {
2343 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2344 *eax &= ~0xFC000000;
c6dc6f63 2345 } else {
2f7a21c4 2346 *eax = 0;
76c2975a 2347 switch (count) {
c6dc6f63 2348 case 0: /* L1 dcache info */
5e891bf8
EH		 2349 *eax |= CPUID_4_TYPE_DCACHE | \
2350 CPUID_4_LEVEL(1) | \
2351 CPUID_4_SELF_INIT_LEVEL;
2352 *ebx = (L1D_LINE_SIZE - 1) | \
2353 ((L1D_PARTITIONS - 1) << 12) | \
2354 ((L1D_ASSOCIATIVITY - 1) << 22);
2355 *ecx = L1D_SETS - 1;
2356 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2357 break;
2358 case 1: /* L1 icache info */
5e891bf8
EH		 2359 *eax |= CPUID_4_TYPE_ICACHE | \
2360 CPUID_4_LEVEL(1) | \
2361 CPUID_4_SELF_INIT_LEVEL;
2362 *ebx = (L1I_LINE_SIZE - 1) | \
2363 ((L1I_PARTITIONS - 1) << 12) | \
2364 ((L1I_ASSOCIATIVITY - 1) << 22);
2365 *ecx = L1I_SETS - 1;
2366 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2367 break;
2368 case 2: /* L2 cache info */
5e891bf8
EH		 2369 *eax |= CPUID_4_TYPE_UNIFIED | \
2370 CPUID_4_LEVEL(2) | \
2371 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2372 if (cs->nr_threads > 1) {
2373 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2374 }
5e891bf8
EH		 2375 *ebx = (L2_LINE_SIZE - 1) | \
2376 ((L2_PARTITIONS - 1) << 12) | \
2377 ((L2_ASSOCIATIVITY - 1) << 22);
2378 *ecx = L2_SETS - 1;
2379 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2380 break;
2381 default: /* end of info */
2382 *eax = 0;
2383 *ebx = 0;
2384 *ecx = 0;
2385 *edx = 0;
2386 break;
76c2975a
PB		 2387 }
2388 }
2389
2390 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2391 if ((*eax & 31) && cs->nr_cores > 1) {
2392 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2393 }
2394 break;
2395 case 5:
2396 /* mwait info: needed for Core compatibility */
2397 *eax = 0; /* Smallest monitor-line size in bytes */
2398 *ebx = 0; /* Largest monitor-line size in bytes */
2399 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2400 *edx = 0;
2401 break;
2402 case 6:
2403 /* Thermal and Power Leaf */
28b8e4d0 2404 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2405 *ebx = 0;
2406 *ecx = 0;
2407 *edx = 0;
2408 break;
f7911686 2409 case 7:
13526728
EH		 2410 /* Structured Extended Feature Flags Enumeration Leaf */
2411 if (count == 0) {
2412 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2413 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2414 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
13526728 2415 *edx = 0; /* Reserved */
f7911686
YW		 2416 } else {
2417 *eax = 0;
2418 *ebx = 0;
2419 *ecx = 0;
2420 *edx = 0;
2421 }
2422 break;
c6dc6f63
AP		 2423 case 9:
2424 /* Direct Cache Access Information Leaf */
2425 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2426 *ebx = 0;
2427 *ecx = 0;
2428 *edx = 0;
2429 break;
2430 case 0xA:
2431 /* Architectural Performance Monitoring Leaf */
9337e3b6 2432 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2433 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2434
2435 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2436 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2437 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2438 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2439 } else {
2440 *eax = 0;
2441 *ebx = 0;
2442 *ecx = 0;
2443 *edx = 0;
2444 }
c6dc6f63 2445 break;
2560f19f
PB		 2446 case 0xD: {
2447 KVMState *s = cs->kvm_state;
2448 uint64_t kvm_mask;
2449 int i;
2450
51e49430 2451 /* Processor Extended State */
2560f19f
PB		 2452 *eax = 0;
2453 *ebx = 0;
2454 *ecx = 0;
2455 *edx = 0;
2456 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
51e49430
SY		 2457 break;
2458 }
2560f19f
PB		 2459 kvm_mask =
2460 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2461 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
ba9bc59e 2462
2560f19f
PB		 2463 if (count == 0) {
2464 *ecx = 0x240;
2465 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2466 const ExtSaveArea *esa = &ext_save_areas[i];
2467 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2468 (kvm_mask & (1 << i)) != 0) {
2469 if (i < 32) {
2470 *eax |= 1 << i;
2471 } else {
2472 *edx |= 1 << (i - 32);
2473 }
2474 *ecx = MAX(*ecx, esa->offset + esa->size);
2475 }
2476 }
2477 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2478 *ebx = *ecx;
2479 } else if (count == 1) {
0bb0b2d2 2480 *eax = env->features[FEAT_XSAVE];
2560f19f
PB		 2481 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2482 const ExtSaveArea *esa = &ext_save_areas[count];
2483 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2484 (kvm_mask & (1 << count)) != 0) {
33f373d7
LJ		 2485 *eax = esa->size;
2486 *ebx = esa->offset;
2560f19f 2487 }
51e49430
SY		 2488 }
2489 break;
2560f19f 2490 }
c6dc6f63
AP		 2491 case 0x80000000:
2492 *eax = env->cpuid_xlevel;
2493 *ebx = env->cpuid_vendor1;
2494 *edx = env->cpuid_vendor2;
2495 *ecx = env->cpuid_vendor3;
2496 break;
2497 case 0x80000001:
2498 *eax = env->cpuid_version;
2499 *ebx = 0;
0514ef2f
EH		 2500 *ecx = env->features[FEAT_8000_0001_ECX];
2501 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2502
2503 /* The Linux kernel checks for the CMPLegacy bit and
2504 * discards multiple thread information if it is set.
2505 * So dont set it here for Intel to make Linux guests happy.
2506 */
ce3960eb 2507 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2508 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2509 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2510 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2511 *ecx |= 1 << 1; /* CmpLegacy bit */
2512 }
2513 }
c6dc6f63
AP		 2514 break;
2515 case 0x80000002:
2516 case 0x80000003:
2517 case 0x80000004:
2518 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2519 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2520 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2521 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2522 break;
2523 case 0x80000005:
2524 /* cache info (L1 cache) */
787aaf57
BC		 2525 if (cpu->cache_info_passthrough) {
2526 host_cpuid(index, 0, eax, ebx, ecx, edx);
2527 break;
2528 }
5e891bf8
EH		 2529 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2530 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2531 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2532 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2533 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2534 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2535 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2536 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2537 break;
2538 case 0x80000006:
2539 /* cache info (L2 cache) */
787aaf57
BC		 2540 if (cpu->cache_info_passthrough) {
2541 host_cpuid(index, 0, eax, ebx, ecx, edx);
2542 break;
2543 }
5e891bf8
EH		 2544 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2545 (L2_DTLB_2M_ENTRIES << 16) | \
2546 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2547 (L2_ITLB_2M_ENTRIES);
2548 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2549 (L2_DTLB_4K_ENTRIES << 16) | \
2550 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2551 (L2_ITLB_4K_ENTRIES);
2552 *ecx = (L2_SIZE_KB_AMD << 16) | \
2553 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2554 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2555 *edx = ((L3_SIZE_KB/512) << 18) | \
2556 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2557 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2558 break;
303752a9
MT		 2559 case 0x80000007:
2560 *eax = 0;
2561 *ebx = 0;
2562 *ecx = 0;
2563 *edx = env->features[FEAT_8000_0007_EDX];
2564 break;
c6dc6f63
AP		 2565 case 0x80000008:
2566 /* virtual & phys address size in low 2 bytes. */
2567/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2568 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2569 /* 64 bit processor */
2570/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2571 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2572 } else {
0514ef2f 2573 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2574 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2575 } else {
c6dc6f63 2576 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2577 }
c6dc6f63
AP		 2578 }
2579 *ebx = 0;
2580 *ecx = 0;
2581 *edx = 0;
ce3960eb
AF		 2582 if (cs->nr_cores * cs->nr_threads > 1) {
2583 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2584 }
2585 break;
2586 case 0x8000000A:
0514ef2f 2587 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2588 *eax = 0x00000001; /* SVM Revision */
2589 *ebx = 0x00000010; /* nr of ASIDs */
2590 *ecx = 0;
0514ef2f 2591 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2592 } else {
2593 *eax = 0;
2594 *ebx = 0;
2595 *ecx = 0;
2596 *edx = 0;
2597 }
c6dc6f63 2598 break;
b3baa152
BW		 2599 case 0xC0000000:
2600 *eax = env->cpuid_xlevel2;
2601 *ebx = 0;
2602 *ecx = 0;
2603 *edx = 0;
2604 break;
2605 case 0xC0000001:
2606 /* Support for VIA CPU's CPUID instruction */
2607 *eax = env->cpuid_version;
2608 *ebx = 0;
2609 *ecx = 0;
0514ef2f 2610 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2611 break;
2612 case 0xC0000002:
2613 case 0xC0000003:
2614 case 0xC0000004:
2615 /* Reserved for the future, and now filled with zero */
2616 *eax = 0;
2617 *ebx = 0;
2618 *ecx = 0;
2619 *edx = 0;
2620 break;
c6dc6f63
AP		 2621 default:
2622 /* reserved values: zero */
2623 *eax = 0;
2624 *ebx = 0;
2625 *ecx = 0;
2626 *edx = 0;
2627 break;
2628 }
2629}
5fd2087a
AF		 2630
2631/* CPUClass::reset() */
2632static void x86_cpu_reset(CPUState *s)
2633{
2634 X86CPU *cpu = X86_CPU(s);
2635 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2636 CPUX86State *env = &cpu->env;
c1958aea
AF		 2637 int i;
2638
5fd2087a
AF		 2639 xcc->parent_reset(s);
2640
43175fa9 2641 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2642
00c8cb0a 2643 tlb_flush(s, 1);
c1958aea
AF		 2644
2645 env->old_exception = -1;
2646
2647 /* init to reset state */
2648
2649#ifdef CONFIG_SOFTMMU
2650 env->hflags |= HF_SOFTMMU_MASK;
2651#endif
2652 env->hflags2 |= HF2_GIF_MASK;
2653
2654 cpu_x86_update_cr0(env, 0x60000010);
2655 env->a20_mask = ~0x0;
2656 env->smbase = 0x30000;
2657
2658 env->idt.limit = 0xffff;
2659 env->gdt.limit = 0xffff;
2660 env->ldt.limit = 0xffff;
2661 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2662 env->tr.limit = 0xffff;
2663 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2664
2665 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2666 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2667 DESC_R_MASK | DESC_A_MASK);
2668 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2669 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2670 DESC_A_MASK);
2671 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2672 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2673 DESC_A_MASK);
2674 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2675 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2676 DESC_A_MASK);
2677 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2678 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2679 DESC_A_MASK);
2680 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2681 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2682 DESC_A_MASK);
2683
2684 env->eip = 0xfff0;
2685 env->regs[R_EDX] = env->cpuid_version;
2686
2687 env->eflags = 0x2;
2688
2689 /* FPU init */
2690 for (i = 0; i < 8; i++) {
2691 env->fptags[i] = 1;
2692 }
5bde1407 2693 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2694
2695 env->mxcsr = 0x1f80;
c74f41bb 2696 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
c1958aea
AF		 2697
2698 env->pat = 0x0007040600070406ULL;
2699 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2700
2701 memset(env->dr, 0, sizeof(env->dr));
2702 env->dr[6] = DR6_FIXED_1;
2703 env->dr[7] = DR7_FIXED_1;
b3310ab3 2704 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2705 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2706
05e7e819 2707 env->xcr0 = 1;
0522604b 2708
9db2efd9
AW		 2709 /*
2710 * SDM 11.11.5 requires:
2711 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2712 * - IA32_MTRR_PHYSMASKn.V = 0
2713 * All other bits are undefined. For simplification, zero it all.
2714 */
2715 env->mtrr_deftype = 0;
2716 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2717 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2718
dd673288
IM		 2719#if !defined(CONFIG_USER_ONLY)
2720 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2721 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2722
259186a7 2723 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2724
2725 if (kvm_enabled()) {
2726 kvm_arch_reset_vcpu(cpu);
2727 }
dd673288 2728#endif
5fd2087a
AF		 2729}
2730
dd673288
IM		 2731#ifndef CONFIG_USER_ONLY
2732bool cpu_is_bsp(X86CPU *cpu)
2733{
02e51483 2734 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2735}
65dee380
IM		 2736
2737/* TODO: remove me, when reset over QOM tree is implemented */
2738static void x86_cpu_machine_reset_cb(void *opaque)
2739{
2740 X86CPU *cpu = opaque;
2741 cpu_reset(CPU(cpu));
2742}
dd673288
IM		 2743#endif
2744
de024815
AF		 2745static void mce_init(X86CPU *cpu)
2746{
2747 CPUX86State *cenv = &cpu->env;
2748 unsigned int bank;
2749
2750 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2751 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2752 (CPUID_MCE | CPUID_MCA)) {
2753 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2754 cenv->mcg_ctl = ~(uint64_t)0;
2755 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2756 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2757 }
2758 }
2759}
2760
bdeec802 2761#ifndef CONFIG_USER_ONLY
d3c64d6a 2762static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2763{
449994eb 2764 APICCommonState *apic;
bdeec802
IM		 2765 const char *apic_type = "apic";
2766
15eafc2e 2767 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2768 apic_type = "kvm-apic";
2769 } else if (xen_enabled()) {
2770 apic_type = "xen-apic";
2771 }
2772
46232aaa 2773 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802
IM		 2774
2775 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2776 OBJECT(cpu->apic_state), NULL);
7e72a45c 2777 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2778 /* TODO: convert to link<> */
02e51483 2779 apic = APIC_COMMON(cpu->apic_state);
60671e58 2780 apic->cpu = cpu;
8d42d2d3 2781 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2782}
2783
2784static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2785{
8d42d2d3
CF		 2786 APICCommonState *apic;
2787 static bool apic_mmio_map_once;
2788
02e51483 2789 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2790 return;
2791 }
6e8e2651
MA		 2792 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2793 errp);
8d42d2d3
CF		 2794
2795 /* Map APIC MMIO area */
2796 apic = APIC_COMMON(cpu->apic_state);
2797 if (!apic_mmio_map_once) {
2798 memory_region_add_subregion_overlap(get_system_memory(),
2799 apic->apicbase &
2800 MSR_IA32_APICBASE_BASE,
2801 &apic->io_memory,
2802 0x1000);
2803 apic_mmio_map_once = true;
2804 }
bdeec802 2805}
f809c605
PB		 2806
2807static void x86_cpu_machine_done(Notifier *n, void *unused)
2808{
2809 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2810 MemoryRegion *smram =
2811 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2812
2813 if (smram) {
2814 cpu->smram = g_new(MemoryRegion, 1);
2815 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2816 smram, 0, 1ull << 32);
2817 memory_region_set_enabled(cpu->smram, false);
2818 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2819 }
2820}
d3c64d6a
IM		 2821#else
2822static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2823{
2824}
bdeec802
IM		 2825#endif
2826
e48638fd
WH		 2827
2828#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2829 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2830 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2831#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2832 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2833 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2834static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2835{
14a10fc3 2836 CPUState *cs = CPU(dev);
2b6f294c
AF		 2837 X86CPU *cpu = X86_CPU(dev);
2838 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2839 CPUX86State *env = &cpu->env;
2b6f294c 2840 Error *local_err = NULL;
e48638fd 2841 static bool ht_warned;
b34d12d1 2842
9886e834
EH		 2843 if (cpu->apic_id < 0) {
2844 error_setg(errp, "apic-id property was not initialized properly");
2845 return;
2846 }
2847
0514ef2f 2848 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2849 env->cpuid_level = 7;
2850 }
7a059953 2851
9b15cd9e
IM		 2852 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2853 * CPUID[1].EDX.
2854 */
e48638fd 2855 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2856 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2857 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2858 & CPUID_EXT2_AMD_ALIASES);
2859 }
2860
fefb41bf
EH		 2861
2862 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2863 error_setg(&local_err,
2864 kvm_enabled() ?
2865 "Host doesn't support requested features" :
2866 "TCG doesn't support requested features");
2867 goto out;
4586f157
IM		 2868 }
2869
65dee380
IM		 2870#ifndef CONFIG_USER_ONLY
2871 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2872
0514ef2f 2873 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2874 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2875 if (local_err != NULL) {
4dc1f449 2876 goto out;
bdeec802
IM		 2877 }
2878 }
65dee380
IM		 2879#endif
2880
7a059953 2881 mce_init(cpu);
2001d0cd
PB		 2882
2883#ifndef CONFIG_USER_ONLY
2884 if (tcg_enabled()) {
56943e8c
PM		 2885 AddressSpace *newas = g_new(AddressSpace, 1);
2886
f809c605 2887 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 2888 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 2889
2890 /* Outer container... */
2891 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2892 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2893
2894 /* ... with two regions inside: normal system memory with low
2895 * priority, and...
2896 */
2897 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2898 get_system_memory(), 0, ~0ull);
2899 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2900 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 2901 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 2902 cs->num_ases = 1;
56943e8c 2903 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 2904
2905 /* ... SMRAM with higher priority, linked from /machine/smram. */
2906 cpu->machine_done.notify = x86_cpu_machine_done;
2907 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2908 }
2909#endif
2910
14a10fc3 2911 qemu_init_vcpu(cs);
d3c64d6a 2912
e48638fd
WH		 2913 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2914 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2915 * based on inputs (sockets,cores,threads), it is still better to gives
2916 * users a warning.
2917 *
2918 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2919 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2920 */
2921 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2922 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2923 " -smp options properly.");
2924 ht_warned = true;
2925 }
2926
d3c64d6a
IM		 2927 x86_cpu_apic_realize(cpu, &local_err);
2928 if (local_err != NULL) {
2929 goto out;
2930 }
14a10fc3 2931 cpu_reset(cs);
2b6f294c 2932
4dc1f449 2933 xcc->parent_realize(dev, &local_err);
2001d0cd 2934
4dc1f449
IM		 2935out:
2936 if (local_err != NULL) {
2937 error_propagate(errp, local_err);
2938 return;
2939 }
7a059953
AF		 2940}
2941
38e5c119
EH		 2942typedef struct BitProperty {
2943 uint32_t *ptr;
2944 uint32_t mask;
2945} BitProperty;
2946
2947static void x86_cpu_get_bit_prop(Object *obj,
4fa45492 2948 Visitor *v,
38e5c119
EH		 2949 void *opaque,
2950 const char *name,
2951 Error **errp)
2952{
2953 BitProperty *fp = opaque;
2954 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 2955 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 2956}
2957
2958static void x86_cpu_set_bit_prop(Object *obj,
4fa45492 2959 Visitor *v,
38e5c119
EH		 2960 void *opaque,
2961 const char *name,
2962 Error **errp)
2963{
2964 DeviceState *dev = DEVICE(obj);
2965 BitProperty *fp = opaque;
2966 Error *local_err = NULL;
2967 bool value;
2968
2969 if (dev->realized) {
2970 qdev_prop_set_after_realize(dev, name, errp);
2971 return;
2972 }
2973
51e72bc1 2974 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 2975 if (local_err) {
2976 error_propagate(errp, local_err);
2977 return;
2978 }
2979
2980 if (value) {
2981 *fp->ptr |= fp->mask;
2982 } else {
2983 *fp->ptr &= ~fp->mask;
2984 }
2985}
2986
2987static void x86_cpu_release_bit_prop(Object *obj, const char *name,
2988 void *opaque)
2989{
2990 BitProperty *prop = opaque;
2991 g_free(prop);
2992}
2993
2994/* Register a boolean property to get/set a single bit in a uint32_t field.
2995 *
2996 * The same property name can be registered multiple times to make it affect
2997 * multiple bits in the same FeatureWord. In that case, the getter will return
2998 * true only if all bits are set.
2999 */
3000static void x86_cpu_register_bit_prop(X86CPU *cpu,
3001 const char *prop_name,
3002 uint32_t *field,
3003 int bitnr)
3004{
3005 BitProperty *fp;
3006 ObjectProperty *op;
3007 uint32_t mask = (1UL << bitnr);
3008
3009 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3010 if (op) {
3011 fp = op->opaque;
3012 assert(fp->ptr == field);
3013 fp->mask |= mask;
3014 } else {
3015 fp = g_new0(BitProperty, 1);
3016 fp->ptr = field;
3017 fp->mask = mask;
3018 object_property_add(OBJECT(cpu), prop_name, "bool",
3019 x86_cpu_get_bit_prop,
3020 x86_cpu_set_bit_prop,
3021 x86_cpu_release_bit_prop, fp, &error_abort);
3022 }
3023}
3024
3025static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3026 FeatureWord w,
3027 int bitnr)
3028{
3029 Object *obj = OBJECT(cpu);
3030 int i;
3031 char **names;
3032 FeatureWordInfo *fi = &feature_word_info[w];
3033
3034 if (!fi->feat_names) {
3035 return;
3036 }
3037 if (!fi->feat_names[bitnr]) {
3038 return;
3039 }
3040
3041 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3042
3043 feat2prop(names[0]);
3044 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3045
3046 for (i = 1; names[i]; i++) {
3047 feat2prop(names[i]);
d461a44c 3048 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3049 &error_abort);
3050 }
3051
3052 g_strfreev(names);
3053}
3054
de024815
AF		 3055static void x86_cpu_initfn(Object *obj)
3056{
55e5c285 3057 CPUState *cs = CPU(obj);
de024815 3058 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3059 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3060 CPUX86State *env = &cpu->env;
38e5c119 3061 FeatureWord w;
d65e9815 3062 static int inited;
de024815 3063
c05efcb1 3064 cs->env_ptr = env;
4bad9e39 3065 cpu_exec_init(cs, &error_abort);
71ad61d3
AF		 3066
3067 object_property_add(obj, "family", "int",
95b8519d 3068 x86_cpuid_version_get_family,
71ad61d3 3069 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3070 object_property_add(obj, "model", "int",
67e30c83 3071 x86_cpuid_version_get_model,
c5291a4f 3072 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3073 object_property_add(obj, "stepping", "int",
35112e41 3074 x86_cpuid_version_get_stepping,
036e2222 3075 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3076 object_property_add_str(obj, "vendor",
3077 x86_cpuid_get_vendor,
3078 x86_cpuid_set_vendor, NULL);
938d4c25 3079 object_property_add_str(obj, "model-id",
63e886eb 3080 x86_cpuid_get_model_id,
938d4c25 3081 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3082 object_property_add(obj, "tsc-frequency", "int",
3083 x86_cpuid_get_tsc_freq,
3084 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3085 object_property_add(obj, "apic-id", "int",
3086 x86_cpuid_get_apic_id,
3087 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3088 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3089 x86_cpu_get_feature_words,
7e5292b5
EH		 3090 NULL, NULL, (void *)env->features, NULL);
3091 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3092 x86_cpu_get_feature_words,
3093 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3094
92067bf4 3095 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3096
9886e834
EH		 3097#ifndef CONFIG_USER_ONLY
3098 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3099 cpu->apic_id = -1;
3100#endif
3101
38e5c119
EH		 3102 for (w = 0; w < FEATURE_WORDS; w++) {
3103 int bitnr;
3104
3105 for (bitnr = 0; bitnr < 32; bitnr++) {
3106 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3107 }
3108 }
3109
d940ee9b
EH		 3110 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3111
d65e9815
IM		 3112 /* init various static tables used in TCG mode */
3113 if (tcg_enabled() && !inited) {
3114 inited = 1;
63618b4e 3115 tcg_x86_init();
d65e9815 3116 }
de024815
AF		 3117}
3118
997395d3
IM		 3119static int64_t x86_cpu_get_arch_id(CPUState *cs)
3120{
3121 X86CPU *cpu = X86_CPU(cs);
997395d3 3122
7e72a45c 3123 return cpu->apic_id;
997395d3
IM		 3124}
3125
444d5590
AF		 3126static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3127{
3128 X86CPU *cpu = X86_CPU(cs);
3129
3130 return cpu->env.cr[0] & CR0_PG_MASK;
3131}
3132
f45748f1
AF		 3133static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3134{
3135 X86CPU *cpu = X86_CPU(cs);
3136
3137 cpu->env.eip = value;
3138}
3139
bdf7ae5b
AF		 3140static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3141{
3142 X86CPU *cpu = X86_CPU(cs);
3143
3144 cpu->env.eip = tb->pc - tb->cs_base;
3145}
3146
8c2e1b00
AF		 3147static bool x86_cpu_has_work(CPUState *cs)
3148{
3149 X86CPU *cpu = X86_CPU(cs);
3150 CPUX86State *env = &cpu->env;
3151
6220e900
PD		 3152 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3153 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3154 (env->eflags & IF_MASK)) ||
3155 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3156 CPU_INTERRUPT_INIT |
3157 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3158 CPU_INTERRUPT_MCE)) ||
3159 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3160 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3161}
3162
9337e3b6
EH		 3163static Property x86_cpu_properties[] = {
3164 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3165 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3166 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3167 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3168 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3169 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3170 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3171 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3172 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3173 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3174 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3175 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3176 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3177 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3178 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3179 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3180 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
1c4a55db 3181 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
9337e3b6
EH		 3182 DEFINE_PROP_END_OF_LIST()
3183};
3184
5fd2087a
AF		 3185static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3186{
3187 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3188 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3189 DeviceClass *dc = DEVICE_CLASS(oc);
3190
3191 xcc->parent_realize = dc->realize;
3192 dc->realize = x86_cpu_realizefn;
9337e3b6 3193 dc->props = x86_cpu_properties;
5fd2087a
AF		 3194
3195 xcc->parent_reset = cc->reset;
3196 cc->reset = x86_cpu_reset;
91b1df8c 3197 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3198
500050d1 3199 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3200 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3201 cc->has_work = x86_cpu_has_work;
97a8ea5a 3202 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3203 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3204 cc->dump_state = x86_cpu_dump_state;
f45748f1 3205 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3206 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3207 cc->gdb_read_register = x86_cpu_gdb_read_register;
3208 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3209 cc->get_arch_id = x86_cpu_get_arch_id;
3210 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3211#ifdef CONFIG_USER_ONLY
3212 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3213#else
a23bbfda 3214 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3215 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3216 cc->write_elf64_note = x86_cpu_write_elf64_note;
3217 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3218 cc->write_elf32_note = x86_cpu_write_elf32_note;
3219 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3220 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3221#endif
a0e372f0 3222 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3223#ifndef CONFIG_USER_ONLY
3224 cc->debug_excp_handler = breakpoint_handler;
3225#endif
374e0cd4
RH		 3226 cc->cpu_exec_enter = x86_cpu_exec_enter;
3227 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27
MA		 3228
3229 /*
3230 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3231 * object in cpus -> dangling pointer after final object_unref().
3232 */
3233 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3234}
3235
3236static const TypeInfo x86_cpu_type_info = {
3237 .name = TYPE_X86_CPU,
3238 .parent = TYPE_CPU,
3239 .instance_size = sizeof(X86CPU),
de024815 3240 .instance_init = x86_cpu_initfn,
d940ee9b 3241 .abstract = true,
5fd2087a
AF		 3242 .class_size = sizeof(X86CPUClass),
3243 .class_init = x86_cpu_common_class_init,
3244};
3245
3246static void x86_cpu_register_types(void)
3247{
d940ee9b
EH		 3248 int i;
3249
5fd2087a 3250 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3251 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3252 x86_register_cpudef_type(&builtin_x86_defs[i]);
3253 }
3254#ifdef CONFIG_KVM
3255 type_register_static(&host_x86_cpu_type_info);
3256#endif
5fd2087a
AF		 3257}
3258
3259type_init(x86_cpu_register_types)
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