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KVM: nVMX: nested TPR shadow/threshold emulation
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d77c26fc 475 } host_state;
9c8cba37 476 struct {
7ffd92c5 477 int vm86_active;
78ac8b47 478 ulong save_rflags;
f5f7b2fe
AK		 479 struct kvm_segment segs[8];
480 } rmode;
481 struct {
482 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 483 struct kvm_save_segment {
484 u16 selector;
485 unsigned long base;
486 u32 limit;
487 u32 ar;
f5f7b2fe 488 } seg[8];
2fb92db1 489 } segment_cache;
2384d2b3 490 int vpid;
04fa4d32 491 bool emulation_required;
3b86cd99
JK		 492
493 /* Support for vnmi-less CPUs */
494 int soft_vnmi_blocked;
495 ktime_t entry_time;
496 s64 vnmi_blocked_time;
a0861c02 497 u32 exit_reason;
4e47c7a6
SY		 498
499 bool rdtscp_enabled;
ec378aee 500
01e439be
YZ		 501 /* Posted interrupt descriptor */
502 struct pi_desc pi_desc;
503
ec378aee
NHE		 504 /* Support for a guest hypervisor (nested VMX) */
505 struct nested_vmx nested;
a7653ecd
RK		 506
507 /* Dynamic PLE window. */
508 int ple_window;
509 bool ple_window_dirty;
a2fa3e9f
GH		 510};
511
2fb92db1
AK		 512enum segment_cache_field {
513 SEG_FIELD_SEL = 0,
514 SEG_FIELD_BASE = 1,
515 SEG_FIELD_LIMIT = 2,
516 SEG_FIELD_AR = 3,
517
518 SEG_FIELD_NR = 4
519};
520
a2fa3e9f
GH		 521static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
522{
fb3f0f51 523 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 524}
525
22bd0358
NHE		 526#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
527#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
528#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
529 [number##_HIGH] = VMCS12_OFFSET(name)+4
530
4607c2d7 531
fe2b201b 532static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 533 /*
534 * We do NOT shadow fields that are modified when L0
535 * traps and emulates any vmx instruction (e.g. VMPTRLD,
536 * VMXON...) executed by L1.
537 * For example, VM_INSTRUCTION_ERROR is read
538 * by L1 if a vmx instruction fails (part of the error path).
539 * Note the code assumes this logic. If for some reason
540 * we start shadowing these fields then we need to
541 * force a shadow sync when L0 emulates vmx instructions
542 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
543 * by nested_vmx_failValid)
544 */
545 VM_EXIT_REASON,
546 VM_EXIT_INTR_INFO,
547 VM_EXIT_INSTRUCTION_LEN,
548 IDT_VECTORING_INFO_FIELD,
549 IDT_VECTORING_ERROR_CODE,
550 VM_EXIT_INTR_ERROR_CODE,
551 EXIT_QUALIFICATION,
552 GUEST_LINEAR_ADDRESS,
553 GUEST_PHYSICAL_ADDRESS
554};
fe2b201b 555static int max_shadow_read_only_fields =
4607c2d7
AG		 556 ARRAY_SIZE(shadow_read_only_fields);
557
fe2b201b 558static unsigned long shadow_read_write_fields[] = {
a7c0b07d 559 TPR_THRESHOLD,
4607c2d7
AG		 560 GUEST_RIP,
561 GUEST_RSP,
562 GUEST_CR0,
563 GUEST_CR3,
564 GUEST_CR4,
565 GUEST_INTERRUPTIBILITY_INFO,
566 GUEST_RFLAGS,
567 GUEST_CS_SELECTOR,
568 GUEST_CS_AR_BYTES,
569 GUEST_CS_LIMIT,
570 GUEST_CS_BASE,
571 GUEST_ES_BASE,
36be0b9d 572 GUEST_BNDCFGS,
4607c2d7
AG		 573 CR0_GUEST_HOST_MASK,
574 CR0_READ_SHADOW,
575 CR4_READ_SHADOW,
576 TSC_OFFSET,
577 EXCEPTION_BITMAP,
578 CPU_BASED_VM_EXEC_CONTROL,
579 VM_ENTRY_EXCEPTION_ERROR_CODE,
580 VM_ENTRY_INTR_INFO_FIELD,
581 VM_ENTRY_INSTRUCTION_LEN,
582 VM_ENTRY_EXCEPTION_ERROR_CODE,
583 HOST_FS_BASE,
584 HOST_GS_BASE,
585 HOST_FS_SELECTOR,
586 HOST_GS_SELECTOR
587};
fe2b201b 588static int max_shadow_read_write_fields =
4607c2d7
AG		 589 ARRAY_SIZE(shadow_read_write_fields);
590
772e0318 591static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 592 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
593 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
594 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
595 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
596 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
597 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
598 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
599 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
600 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
601 FIELD(HOST_ES_SELECTOR, host_es_selector),
602 FIELD(HOST_CS_SELECTOR, host_cs_selector),
603 FIELD(HOST_SS_SELECTOR, host_ss_selector),
604 FIELD(HOST_DS_SELECTOR, host_ds_selector),
605 FIELD(HOST_FS_SELECTOR, host_fs_selector),
606 FIELD(HOST_GS_SELECTOR, host_gs_selector),
607 FIELD(HOST_TR_SELECTOR, host_tr_selector),
608 FIELD64(IO_BITMAP_A, io_bitmap_a),
609 FIELD64(IO_BITMAP_B, io_bitmap_b),
610 FIELD64(MSR_BITMAP, msr_bitmap),
611 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
612 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
613 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
614 FIELD64(TSC_OFFSET, tsc_offset),
615 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
616 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
617 FIELD64(EPT_POINTER, ept_pointer),
618 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
619 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
620 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
621 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
622 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
623 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
624 FIELD64(GUEST_PDPTR0, guest_pdptr0),
625 FIELD64(GUEST_PDPTR1, guest_pdptr1),
626 FIELD64(GUEST_PDPTR2, guest_pdptr2),
627 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 628 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 629 FIELD64(HOST_IA32_PAT, host_ia32_pat),
630 FIELD64(HOST_IA32_EFER, host_ia32_efer),
631 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
632 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
633 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
634 FIELD(EXCEPTION_BITMAP, exception_bitmap),
635 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
636 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
637 FIELD(CR3_TARGET_COUNT, cr3_target_count),
638 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
639 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
640 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
641 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
642 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
643 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
644 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
645 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
646 FIELD(TPR_THRESHOLD, tpr_threshold),
647 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
648 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
649 FIELD(VM_EXIT_REASON, vm_exit_reason),
650 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
651 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
652 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
653 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
654 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
655 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
656 FIELD(GUEST_ES_LIMIT, guest_es_limit),
657 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
658 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
659 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
660 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
661 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
662 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
663 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
664 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
665 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
666 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
667 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
668 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
669 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
670 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
671 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
672 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
673 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
674 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
675 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
676 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
677 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 678 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 679 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
680 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
681 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
682 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
683 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
684 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
685 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
686 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
687 FIELD(EXIT_QUALIFICATION, exit_qualification),
688 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
689 FIELD(GUEST_CR0, guest_cr0),
690 FIELD(GUEST_CR3, guest_cr3),
691 FIELD(GUEST_CR4, guest_cr4),
692 FIELD(GUEST_ES_BASE, guest_es_base),
693 FIELD(GUEST_CS_BASE, guest_cs_base),
694 FIELD(GUEST_SS_BASE, guest_ss_base),
695 FIELD(GUEST_DS_BASE, guest_ds_base),
696 FIELD(GUEST_FS_BASE, guest_fs_base),
697 FIELD(GUEST_GS_BASE, guest_gs_base),
698 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
699 FIELD(GUEST_TR_BASE, guest_tr_base),
700 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
701 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
702 FIELD(GUEST_DR7, guest_dr7),
703 FIELD(GUEST_RSP, guest_rsp),
704 FIELD(GUEST_RIP, guest_rip),
705 FIELD(GUEST_RFLAGS, guest_rflags),
706 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
707 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
708 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
709 FIELD(HOST_CR0, host_cr0),
710 FIELD(HOST_CR3, host_cr3),
711 FIELD(HOST_CR4, host_cr4),
712 FIELD(HOST_FS_BASE, host_fs_base),
713 FIELD(HOST_GS_BASE, host_gs_base),
714 FIELD(HOST_TR_BASE, host_tr_base),
715 FIELD(HOST_GDTR_BASE, host_gdtr_base),
716 FIELD(HOST_IDTR_BASE, host_idtr_base),
717 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
718 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
719 FIELD(HOST_RSP, host_rsp),
720 FIELD(HOST_RIP, host_rip),
721};
722static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
723
724static inline short vmcs_field_to_offset(unsigned long field)
725{
726 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
727 return -1;
728 return vmcs_field_to_offset_table[field];
729}
730
a9d30f33
NHE		 731static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
732{
733 return to_vmx(vcpu)->nested.current_vmcs12;
734}
735
736static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
737{
738 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 739 if (is_error_page(page))
a9d30f33 740 return NULL;
32cad84f 741
a9d30f33
NHE		 742 return page;
743}
744
745static void nested_release_page(struct page *page)
746{
747 kvm_release_page_dirty(page);
748}
749
750static void nested_release_page_clean(struct page *page)
751{
752 kvm_release_page_clean(page);
753}
754
bfd0a56b 755static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 756static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 757static void kvm_cpu_vmxon(u64 addr);
758static void kvm_cpu_vmxoff(void);
93c4adc7 759static bool vmx_mpx_supported(void);
776e58ea 760static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 761static void vmx_set_segment(struct kvm_vcpu *vcpu,
762 struct kvm_segment *var, int seg);
763static void vmx_get_segment(struct kvm_vcpu *vcpu,
764 struct kvm_segment *var, int seg);
d99e4152
GN		 765static bool guest_state_valid(struct kvm_vcpu *vcpu);
766static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 767static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 768static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 769static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 770
6aa8b732
AK		 771static DEFINE_PER_CPU(struct vmcs *, vmxarea);
772static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 773/*
774 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
775 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
776 */
777static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 778static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 779
3e7c73e9
AK		 780static unsigned long *vmx_io_bitmap_a;
781static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 782static unsigned long *vmx_msr_bitmap_legacy;
783static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 784static unsigned long *vmx_msr_bitmap_legacy_x2apic;
785static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 786static unsigned long *vmx_vmread_bitmap;
787static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 788
110312c8 789static bool cpu_has_load_ia32_efer;
8bf00a52 790static bool cpu_has_load_perf_global_ctrl;
110312c8 791
2384d2b3
SY		 792static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
793static DEFINE_SPINLOCK(vmx_vpid_lock);
794
1c3d14fe 795static struct vmcs_config {
6aa8b732
AK		 796 int size;
797 int order;
798 u32 revision_id;
1c3d14fe
YS		 799 u32 pin_based_exec_ctrl;
800 u32 cpu_based_exec_ctrl;
f78e0e2e 801 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 802 u32 vmexit_ctrl;
803 u32 vmentry_ctrl;
804} vmcs_config;
6aa8b732 805
efff9e53 806static struct vmx_capability {
d56f546d
SY		 807 u32 ept;
808 u32 vpid;
809} vmx_capability;
810
6aa8b732
AK		 811#define VMX_SEGMENT_FIELD(seg) \
812 [VCPU_SREG_##seg] = { \
813 .selector = GUEST_##seg##_SELECTOR, \
814 .base = GUEST_##seg##_BASE, \
815 .limit = GUEST_##seg##_LIMIT, \
816 .ar_bytes = GUEST_##seg##_AR_BYTES, \
817 }
818
772e0318 819static const struct kvm_vmx_segment_field {
6aa8b732
AK		 820 unsigned selector;
821 unsigned base;
822 unsigned limit;
823 unsigned ar_bytes;
824} kvm_vmx_segment_fields[] = {
825 VMX_SEGMENT_FIELD(CS),
826 VMX_SEGMENT_FIELD(DS),
827 VMX_SEGMENT_FIELD(ES),
828 VMX_SEGMENT_FIELD(FS),
829 VMX_SEGMENT_FIELD(GS),
830 VMX_SEGMENT_FIELD(SS),
831 VMX_SEGMENT_FIELD(TR),
832 VMX_SEGMENT_FIELD(LDTR),
833};
834
26bb0981
AK		 835static u64 host_efer;
836
6de4f3ad
AK		 837static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
838
4d56c8a7 839/*
8c06585d 840 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 841 * away by decrementing the array size.
842 */
6aa8b732 843static const u32 vmx_msr_index[] = {
05b3e0c2 844#ifdef CONFIG_X86_64
44ea2b17 845 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 846#endif
8c06585d 847 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 848};
6aa8b732 849
31299944 850static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 851{
852 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
853 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 854 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 855}
856
31299944 857static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 858{
859 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
860 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 861 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 862}
863
31299944 864static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 865{
866 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
867 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 868 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 869}
870
31299944 871static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 872{
873 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
874 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
875}
876
31299944 877static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 878{
879 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
880 INTR_INFO_VALID_MASK)) ==
881 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
882}
883
31299944 884static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 885{
04547156 886 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 887}
888
31299944 889static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 890{
04547156 891 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 892}
893
31299944 894static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 895{
04547156 896 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 897}
898
31299944 899static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 900{
04547156
SY		 901 return vmcs_config.cpu_based_exec_ctrl &
902 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 903}
904
774ead3a 905static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 906{
04547156
SY		 907 return vmcs_config.cpu_based_2nd_exec_ctrl &
908 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
909}
910
8d14695f
YZ		 911static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
912{
913 return vmcs_config.cpu_based_2nd_exec_ctrl &
914 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
915}
916
83d4c286
YZ		 917static inline bool cpu_has_vmx_apic_register_virt(void)
918{
919 return vmcs_config.cpu_based_2nd_exec_ctrl &
920 SECONDARY_EXEC_APIC_REGISTER_VIRT;
921}
922
c7c9c56c
YZ		 923static inline bool cpu_has_vmx_virtual_intr_delivery(void)
924{
925 return vmcs_config.cpu_based_2nd_exec_ctrl &
926 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
927}
928
01e439be
YZ		 929static inline bool cpu_has_vmx_posted_intr(void)
930{
931 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
932}
933
934static inline bool cpu_has_vmx_apicv(void)
935{
936 return cpu_has_vmx_apic_register_virt() &&
937 cpu_has_vmx_virtual_intr_delivery() &&
938 cpu_has_vmx_posted_intr();
939}
940
04547156
SY		 941static inline bool cpu_has_vmx_flexpriority(void)
942{
943 return cpu_has_vmx_tpr_shadow() &&
944 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 945}
946
e799794e
MT		 947static inline bool cpu_has_vmx_ept_execute_only(void)
948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 950}
951
952static inline bool cpu_has_vmx_eptp_uncacheable(void)
953{
31299944 954 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 955}
956
957static inline bool cpu_has_vmx_eptp_writeback(void)
958{
31299944 959 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 960}
961
962static inline bool cpu_has_vmx_ept_2m_page(void)
963{
31299944 964 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 965}
966
878403b7
SY		 967static inline bool cpu_has_vmx_ept_1g_page(void)
968{
31299944 969 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 970}
971
4bc9b982
SY		 972static inline bool cpu_has_vmx_ept_4levels(void)
973{
974 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
975}
976
83c3a331
XH		 977static inline bool cpu_has_vmx_ept_ad_bits(void)
978{
979 return vmx_capability.ept & VMX_EPT_AD_BIT;
980}
981
31299944 982static inline bool cpu_has_vmx_invept_context(void)
d56f546d 983{
31299944 984 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 985}
986
31299944 987static inline bool cpu_has_vmx_invept_global(void)
d56f546d 988{
31299944 989 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 990}
991
518c8aee
GJ		 992static inline bool cpu_has_vmx_invvpid_single(void)
993{
994 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
995}
996
b9d762fa
GJ		 997static inline bool cpu_has_vmx_invvpid_global(void)
998{
999 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1000}
1001
31299944 1002static inline bool cpu_has_vmx_ept(void)
d56f546d 1003{
04547156
SY		 1004 return vmcs_config.cpu_based_2nd_exec_ctrl &
1005 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1006}
1007
31299944 1008static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1012}
1013
31299944 1014static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1015{
1016 return vmcs_config.cpu_based_2nd_exec_ctrl &
1017 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1018}
1019
31299944 1020static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1021{
6d3e435e 1022 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1023}
1024
31299944 1025static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1026{
04547156
SY		 1027 return vmcs_config.cpu_based_2nd_exec_ctrl &
1028 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1029}
1030
31299944 1031static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1032{
1033 return vmcs_config.cpu_based_2nd_exec_ctrl &
1034 SECONDARY_EXEC_RDTSCP;
1035}
1036
ad756a16
MJ		 1037static inline bool cpu_has_vmx_invpcid(void)
1038{
1039 return vmcs_config.cpu_based_2nd_exec_ctrl &
1040 SECONDARY_EXEC_ENABLE_INVPCID;
1041}
1042
31299944 1043static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1044{
1045 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
f5f48ee1
SY		 1048static inline bool cpu_has_vmx_wbinvd_exit(void)
1049{
1050 return vmcs_config.cpu_based_2nd_exec_ctrl &
1051 SECONDARY_EXEC_WBINVD_EXITING;
1052}
1053
abc4fc58
AG		 1054static inline bool cpu_has_vmx_shadow_vmcs(void)
1055{
1056 u64 vmx_msr;
1057 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1058 /* check if the cpu supports writing r/o exit information fields */
1059 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1060 return false;
1061
1062 return vmcs_config.cpu_based_2nd_exec_ctrl &
1063 SECONDARY_EXEC_SHADOW_VMCS;
1064}
1065
04547156
SY		 1066static inline bool report_flexpriority(void)
1067{
1068 return flexpriority_enabled;
1069}
1070
fe3ef05c
NHE		 1071static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1072{
1073 return vmcs12->cpu_based_vm_exec_control & bit;
1074}
1075
1076static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1077{
1078 return (vmcs12->cpu_based_vm_exec_control &
1079 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1080 (vmcs12->secondary_vm_exec_control & bit);
1081}
1082
f5c4368f 1083static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1084{
1085 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1086}
1087
f4124500
JK		 1088static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1089{
1090 return vmcs12->pin_based_vm_exec_control &
1091 PIN_BASED_VMX_PREEMPTION_TIMER;
1092}
1093
155a97a3
NHE		 1094static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1095{
1096 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1097}
1098
644d711a
NHE		 1099static inline bool is_exception(u32 intr_info)
1100{
1101 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1102 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1103}
1104
533558bc
JK		 1105static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1106 u32 exit_intr_info,
1107 unsigned long exit_qualification);
7c177938
NHE		 1108static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1109 struct vmcs12 *vmcs12,
1110 u32 reason, unsigned long qualification);
1111
8b9cf98c 1112static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1113{
1114 int i;
1115
a2fa3e9f 1116 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1117 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1118 return i;
1119 return -1;
1120}
1121
2384d2b3
SY		 1122static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1123{
1124 struct {
1125 u64 vpid : 16;
1126 u64 rsvd : 48;
1127 u64 gva;
1128 } operand = { vpid, 0, gva };
1129
4ecac3fd 1130 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1131 /* CF==1 or ZF==1 --> rc = -1 */
1132 "; ja 1f ; ud2 ; 1:"
1133 : : "a"(&operand), "c"(ext) : "cc", "memory");
1134}
1135
1439442c
SY		 1136static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1137{
1138 struct {
1139 u64 eptp, gpa;
1140 } operand = {eptp, gpa};
1141
4ecac3fd 1142 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1143 /* CF==1 or ZF==1 --> rc = -1 */
1144 "; ja 1f ; ud2 ; 1:\n"
1145 : : "a" (&operand), "c" (ext) : "cc", "memory");
1146}
1147
26bb0981 1148static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1149{
1150 int i;
1151
8b9cf98c 1152 i = __find_msr_index(vmx, msr);
a75beee6 1153 if (i >= 0)
a2fa3e9f 1154 return &vmx->guest_msrs[i];
8b6d44c7 1155 return NULL;
7725f0ba
AK		 1156}
1157
6aa8b732
AK		 1158static void vmcs_clear(struct vmcs *vmcs)
1159{
1160 u64 phys_addr = __pa(vmcs);
1161 u8 error;
1162
4ecac3fd 1163 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1164 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1165 : "cc", "memory");
1166 if (error)
1167 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1168 vmcs, phys_addr);
1169}
1170
d462b819
NHE		 1171static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1172{
1173 vmcs_clear(loaded_vmcs->vmcs);
1174 loaded_vmcs->cpu = -1;
1175 loaded_vmcs->launched = 0;
1176}
1177
7725b894
DX		 1178static void vmcs_load(struct vmcs *vmcs)
1179{
1180 u64 phys_addr = __pa(vmcs);
1181 u8 error;
1182
1183 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1184 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1185 : "cc", "memory");
1186 if (error)
2844d849 1187 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1188 vmcs, phys_addr);
1189}
1190
8f536b76
ZY		 1191#ifdef CONFIG_KEXEC
1192/*
1193 * This bitmap is used to indicate whether the vmclear
1194 * operation is enabled on all cpus. All disabled by
1195 * default.
1196 */
1197static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1198
1199static inline void crash_enable_local_vmclear(int cpu)
1200{
1201 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1202}
1203
1204static inline void crash_disable_local_vmclear(int cpu)
1205{
1206 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1207}
1208
1209static inline int crash_local_vmclear_enabled(int cpu)
1210{
1211 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1212}
1213
1214static void crash_vmclear_local_loaded_vmcss(void)
1215{
1216 int cpu = raw_smp_processor_id();
1217 struct loaded_vmcs *v;
1218
1219 if (!crash_local_vmclear_enabled(cpu))
1220 return;
1221
1222 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1223 loaded_vmcss_on_cpu_link)
1224 vmcs_clear(v->vmcs);
1225}
1226#else
1227static inline void crash_enable_local_vmclear(int cpu) { }
1228static inline void crash_disable_local_vmclear(int cpu) { }
1229#endif /* CONFIG_KEXEC */
1230
d462b819 1231static void __loaded_vmcs_clear(void *arg)
6aa8b732 1232{
d462b819 1233 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1234 int cpu = raw_smp_processor_id();
6aa8b732 1235
d462b819
NHE		 1236 if (loaded_vmcs->cpu != cpu)
1237 return; /* vcpu migration can race with cpu offline */
1238 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1239 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1240 crash_disable_local_vmclear(cpu);
d462b819 1241 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1242
1243 /*
1244 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1245 * is before setting loaded_vmcs->vcpu to -1 which is done in
1246 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1247 * then adds the vmcs into percpu list before it is deleted.
1248 */
1249 smp_wmb();
1250
d462b819 1251 loaded_vmcs_init(loaded_vmcs);
8f536b76 1252 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1253}
1254
d462b819 1255static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1256{
e6c7d321
XG		 1257 int cpu = loaded_vmcs->cpu;
1258
1259 if (cpu != -1)
1260 smp_call_function_single(cpu,
1261 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1262}
1263
1760dd49 1264static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1265{
1266 if (vmx->vpid == 0)
1267 return;
1268
518c8aee
GJ		 1269 if (cpu_has_vmx_invvpid_single())
1270 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1271}
1272
b9d762fa
GJ		 1273static inline void vpid_sync_vcpu_global(void)
1274{
1275 if (cpu_has_vmx_invvpid_global())
1276 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1277}
1278
1279static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1280{
1281 if (cpu_has_vmx_invvpid_single())
1760dd49 1282 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1283 else
1284 vpid_sync_vcpu_global();
1285}
1286
1439442c
SY		 1287static inline void ept_sync_global(void)
1288{
1289 if (cpu_has_vmx_invept_global())
1290 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1291}
1292
1293static inline void ept_sync_context(u64 eptp)
1294{
089d034e 1295 if (enable_ept) {
1439442c
SY		 1296 if (cpu_has_vmx_invept_context())
1297 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1298 else
1299 ept_sync_global();
1300 }
1301}
1302
96304217 1303static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1304{
5e520e62 1305 unsigned long value;
6aa8b732 1306
5e520e62
AK		 1307 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1308 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1309 return value;
1310}
1311
96304217 1312static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1313{
1314 return vmcs_readl(field);
1315}
1316
96304217 1317static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1318{
1319 return vmcs_readl(field);
1320}
1321
96304217 1322static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1323{
05b3e0c2 1324#ifdef CONFIG_X86_64
6aa8b732
AK		 1325 return vmcs_readl(field);
1326#else
1327 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1328#endif
1329}
1330
e52de1b8
AK		 1331static noinline void vmwrite_error(unsigned long field, unsigned long value)
1332{
1333 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1334 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1335 dump_stack();
1336}
1337
6aa8b732
AK		 1338static void vmcs_writel(unsigned long field, unsigned long value)
1339{
1340 u8 error;
1341
4ecac3fd 1342 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1343 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1344 if (unlikely(error))
1345 vmwrite_error(field, value);
6aa8b732
AK		 1346}
1347
1348static void vmcs_write16(unsigned long field, u16 value)
1349{
1350 vmcs_writel(field, value);
1351}
1352
1353static void vmcs_write32(unsigned long field, u32 value)
1354{
1355 vmcs_writel(field, value);
1356}
1357
1358static void vmcs_write64(unsigned long field, u64 value)
1359{
6aa8b732 1360 vmcs_writel(field, value);
7682f2d0 1361#ifndef CONFIG_X86_64
6aa8b732
AK		 1362 asm volatile ("");
1363 vmcs_writel(field+1, value >> 32);
1364#endif
1365}
1366
2ab455cc
AL		 1367static void vmcs_clear_bits(unsigned long field, u32 mask)
1368{
1369 vmcs_writel(field, vmcs_readl(field) & ~mask);
1370}
1371
1372static void vmcs_set_bits(unsigned long field, u32 mask)
1373{
1374 vmcs_writel(field, vmcs_readl(field) | mask);
1375}
1376
2961e876
GN		 1377static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1378{
1379 vmcs_write32(VM_ENTRY_CONTROLS, val);
1380 vmx->vm_entry_controls_shadow = val;
1381}
1382
1383static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1384{
1385 if (vmx->vm_entry_controls_shadow != val)
1386 vm_entry_controls_init(vmx, val);
1387}
1388
1389static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1390{
1391 return vmx->vm_entry_controls_shadow;
1392}
1393
1394
1395static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1396{
1397 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1398}
1399
1400static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1401{
1402 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1403}
1404
1405static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1406{
1407 vmcs_write32(VM_EXIT_CONTROLS, val);
1408 vmx->vm_exit_controls_shadow = val;
1409}
1410
1411static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1412{
1413 if (vmx->vm_exit_controls_shadow != val)
1414 vm_exit_controls_init(vmx, val);
1415}
1416
1417static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1418{
1419 return vmx->vm_exit_controls_shadow;
1420}
1421
1422
1423static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1424{
1425 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1426}
1427
1428static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1429{
1430 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1431}
1432
2fb92db1
AK		 1433static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1434{
1435 vmx->segment_cache.bitmask = 0;
1436}
1437
1438static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1439 unsigned field)
1440{
1441 bool ret;
1442 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1443
1444 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1445 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1446 vmx->segment_cache.bitmask = 0;
1447 }
1448 ret = vmx->segment_cache.bitmask & mask;
1449 vmx->segment_cache.bitmask |= mask;
1450 return ret;
1451}
1452
1453static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1454{
1455 u16 *p = &vmx->segment_cache.seg[seg].selector;
1456
1457 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1458 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1459 return *p;
1460}
1461
1462static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1463{
1464 ulong *p = &vmx->segment_cache.seg[seg].base;
1465
1466 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1467 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1468 return *p;
1469}
1470
1471static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1472{
1473 u32 *p = &vmx->segment_cache.seg[seg].limit;
1474
1475 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1476 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1477 return *p;
1478}
1479
1480static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1481{
1482 u32 *p = &vmx->segment_cache.seg[seg].ar;
1483
1484 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1485 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1486 return *p;
1487}
1488
abd3f2d6
AK		 1489static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1490{
1491 u32 eb;
1492
fd7373cc
JK		 1493 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1494 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1495 if ((vcpu->guest_debug &
1496 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1497 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1498 eb |= 1u << BP_VECTOR;
7ffd92c5 1499 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1500 eb = ~0;
089d034e 1501 if (enable_ept)
1439442c 1502 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1503 if (vcpu->fpu_active)
1504 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1505
1506 /* When we are running a nested L2 guest and L1 specified for it a
1507 * certain exception bitmap, we must trap the same exceptions and pass
1508 * them to L1. When running L2, we will only handle the exceptions
1509 * specified above if L1 did not want them.
1510 */
1511 if (is_guest_mode(vcpu))
1512 eb |= get_vmcs12(vcpu)->exception_bitmap;
1513
abd3f2d6
AK		 1514 vmcs_write32(EXCEPTION_BITMAP, eb);
1515}
1516
2961e876
GN		 1517static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1518 unsigned long entry, unsigned long exit)
8bf00a52 1519{
2961e876
GN		 1520 vm_entry_controls_clearbit(vmx, entry);
1521 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1522}
1523
61d2ef2c
AK		 1524static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1525{
1526 unsigned i;
1527 struct msr_autoload *m = &vmx->msr_autoload;
1528
8bf00a52
GN		 1529 switch (msr) {
1530 case MSR_EFER:
1531 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1532 clear_atomic_switch_msr_special(vmx,
1533 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1534 VM_EXIT_LOAD_IA32_EFER);
1535 return;
1536 }
1537 break;
1538 case MSR_CORE_PERF_GLOBAL_CTRL:
1539 if (cpu_has_load_perf_global_ctrl) {
2961e876 1540 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1541 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1542 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1543 return;
1544 }
1545 break;
110312c8
AK		 1546 }
1547
61d2ef2c
AK		 1548 for (i = 0; i < m->nr; ++i)
1549 if (m->guest[i].index == msr)
1550 break;
1551
1552 if (i == m->nr)
1553 return;
1554 --m->nr;
1555 m->guest[i] = m->guest[m->nr];
1556 m->host[i] = m->host[m->nr];
1557 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1558 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1559}
1560
2961e876
GN		 1561static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1562 unsigned long entry, unsigned long exit,
1563 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1564 u64 guest_val, u64 host_val)
8bf00a52
GN		 1565{
1566 vmcs_write64(guest_val_vmcs, guest_val);
1567 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1568 vm_entry_controls_setbit(vmx, entry);
1569 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1570}
1571
61d2ef2c
AK		 1572static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1573 u64 guest_val, u64 host_val)
1574{
1575 unsigned i;
1576 struct msr_autoload *m = &vmx->msr_autoload;
1577
8bf00a52
GN		 1578 switch (msr) {
1579 case MSR_EFER:
1580 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1581 add_atomic_switch_msr_special(vmx,
1582 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1583 VM_EXIT_LOAD_IA32_EFER,
1584 GUEST_IA32_EFER,
1585 HOST_IA32_EFER,
1586 guest_val, host_val);
1587 return;
1588 }
1589 break;
1590 case MSR_CORE_PERF_GLOBAL_CTRL:
1591 if (cpu_has_load_perf_global_ctrl) {
2961e876 1592 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1593 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1594 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1595 GUEST_IA32_PERF_GLOBAL_CTRL,
1596 HOST_IA32_PERF_GLOBAL_CTRL,
1597 guest_val, host_val);
1598 return;
1599 }
1600 break;
110312c8
AK		 1601 }
1602
61d2ef2c
AK		 1603 for (i = 0; i < m->nr; ++i)
1604 if (m->guest[i].index == msr)
1605 break;
1606
e7fc6f93 1607 if (i == NR_AUTOLOAD_MSRS) {
60266204 1608 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1609 "Can't add msr %x\n", msr);
1610 return;
1611 } else if (i == m->nr) {
61d2ef2c
AK		 1612 ++m->nr;
1613 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1614 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1615 }
1616
1617 m->guest[i].index = msr;
1618 m->guest[i].value = guest_val;
1619 m->host[i].index = msr;
1620 m->host[i].value = host_val;
1621}
1622
33ed6329
AK		 1623static void reload_tss(void)
1624{
33ed6329
AK		 1625 /*
1626 * VT restores TR but not its size. Useless.
1627 */
d359192f 1628 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1629 struct desc_struct *descs;
33ed6329 1630
d359192f 1631 descs = (void *)gdt->address;
33ed6329
AK		 1632 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1633 load_TR_desc();
33ed6329
AK		 1634}
1635
92c0d900 1636static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1637{
3a34a881 1638 u64 guest_efer;
51c6cf66
AK		 1639 u64 ignore_bits;
1640
f6801dff 1641 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1642
51c6cf66 1643 /*
0fa06071 1644 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1645 * outside long mode
1646 */
1647 ignore_bits = EFER_NX | EFER_SCE;
1648#ifdef CONFIG_X86_64
1649 ignore_bits |= EFER_LMA | EFER_LME;
1650 /* SCE is meaningful only in long mode on Intel */
1651 if (guest_efer & EFER_LMA)
1652 ignore_bits &= ~(u64)EFER_SCE;
1653#endif
51c6cf66
AK		 1654 guest_efer &= ~ignore_bits;
1655 guest_efer |= host_efer & ignore_bits;
26bb0981 1656 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1657 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1658
1659 clear_atomic_switch_msr(vmx, MSR_EFER);
1660 /* On ept, can't emulate nx, and must switch nx atomically */
1661 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1662 guest_efer = vmx->vcpu.arch.efer;
1663 if (!(guest_efer & EFER_LMA))
1664 guest_efer &= ~EFER_LME;
1665 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1666 return false;
1667 }
1668
26bb0981 1669 return true;
51c6cf66
AK		 1670}
1671
2d49ec72
GN		 1672static unsigned long segment_base(u16 selector)
1673{
d359192f 1674 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1675 struct desc_struct *d;
1676 unsigned long table_base;
1677 unsigned long v;
1678
1679 if (!(selector & ~3))
1680 return 0;
1681
d359192f 1682 table_base = gdt->address;
2d49ec72
GN		 1683
1684 if (selector & 4) { /* from ldt */
1685 u16 ldt_selector = kvm_read_ldt();
1686
1687 if (!(ldt_selector & ~3))
1688 return 0;
1689
1690 table_base = segment_base(ldt_selector);
1691 }
1692 d = (struct desc_struct *)(table_base + (selector & ~7));
1693 v = get_desc_base(d);
1694#ifdef CONFIG_X86_64
1695 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1696 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1697#endif
1698 return v;
1699}
1700
1701static inline unsigned long kvm_read_tr_base(void)
1702{
1703 u16 tr;
1704 asm("str %0" : "=g"(tr));
1705 return segment_base(tr);
1706}
1707
04d2cc77 1708static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1709{
04d2cc77 1710 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1711 int i;
04d2cc77 1712
a2fa3e9f 1713 if (vmx->host_state.loaded)
33ed6329
AK		 1714 return;
1715
a2fa3e9f 1716 vmx->host_state.loaded = 1;
33ed6329
AK		 1717 /*
1718 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1719 * allow segment selectors with cpl > 0 or ti == 1.
1720 */
d6e88aec 1721 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1722 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1723 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1724 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1725 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1726 vmx->host_state.fs_reload_needed = 0;
1727 } else {
33ed6329 1728 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1729 vmx->host_state.fs_reload_needed = 1;
33ed6329 1730 }
9581d442 1731 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1732 if (!(vmx->host_state.gs_sel & 7))
1733 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1734 else {
1735 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1736 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1737 }
1738
b2da15ac
AK		 1739#ifdef CONFIG_X86_64
1740 savesegment(ds, vmx->host_state.ds_sel);
1741 savesegment(es, vmx->host_state.es_sel);
1742#endif
1743
33ed6329
AK		 1744#ifdef CONFIG_X86_64
1745 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1746 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1747#else
a2fa3e9f
GH		 1748 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1749 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1750#endif
707c0874
AK		 1751
1752#ifdef CONFIG_X86_64
c8770e7b
AK		 1753 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1754 if (is_long_mode(&vmx->vcpu))
44ea2b17 1755 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1756#endif
da8999d3
LJ		 1757 if (boot_cpu_has(X86_FEATURE_MPX))
1758 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1759 for (i = 0; i < vmx->save_nmsrs; ++i)
1760 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1761 vmx->guest_msrs[i].data,
1762 vmx->guest_msrs[i].mask);
33ed6329
AK		 1763}
1764
a9b21b62 1765static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1766{
a2fa3e9f 1767 if (!vmx->host_state.loaded)
33ed6329
AK		 1768 return;
1769
e1beb1d3 1770 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1771 vmx->host_state.loaded = 0;
c8770e7b
AK		 1772#ifdef CONFIG_X86_64
1773 if (is_long_mode(&vmx->vcpu))
1774 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1775#endif
152d3f2f 1776 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1777 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1778#ifdef CONFIG_X86_64
9581d442 1779 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1780#else
1781 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1782#endif
33ed6329 1783 }
0a77fe4c
AK		 1784 if (vmx->host_state.fs_reload_needed)
1785 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1786#ifdef CONFIG_X86_64
1787 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1788 loadsegment(ds, vmx->host_state.ds_sel);
1789 loadsegment(es, vmx->host_state.es_sel);
1790 }
b2da15ac 1791#endif
152d3f2f 1792 reload_tss();
44ea2b17 1793#ifdef CONFIG_X86_64
c8770e7b 1794 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1795#endif
da8999d3
LJ		 1796 if (vmx->host_state.msr_host_bndcfgs)
1797 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1798 /*
1799 * If the FPU is not active (through the host task or
1800 * the guest vcpu), then restore the cr0.TS bit.
1801 */
1802 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1803 stts();
3444d7da 1804 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1805}
1806
a9b21b62
AK		 1807static void vmx_load_host_state(struct vcpu_vmx *vmx)
1808{
1809 preempt_disable();
1810 __vmx_load_host_state(vmx);
1811 preempt_enable();
1812}
1813
6aa8b732
AK		 1814/*
1815 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1816 * vcpu mutex is already taken.
1817 */
15ad7146 1818static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1819{
a2fa3e9f 1820 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1821 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1822
4610c9cc
DX		 1823 if (!vmm_exclusive)
1824 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1825 else if (vmx->loaded_vmcs->cpu != cpu)
1826 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1827
d462b819
NHE		 1828 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1829 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1830 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1831 }
1832
d462b819 1833 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1834 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1835 unsigned long sysenter_esp;
1836
a8eeb04a 1837 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1838 local_irq_disable();
8f536b76 1839 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1840
1841 /*
1842 * Read loaded_vmcs->cpu should be before fetching
1843 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1844 * See the comments in __loaded_vmcs_clear().
1845 */
1846 smp_rmb();
1847
d462b819
NHE		 1848 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1849 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1850 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1851 local_irq_enable();
1852
6aa8b732
AK		 1853 /*
1854 * Linux uses per-cpu TSS and GDT, so set these when switching
1855 * processors.
1856 */
d6e88aec 1857 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1858 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1859
1860 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1861 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1862 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1863 }
6aa8b732
AK		 1864}
1865
1866static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1867{
a9b21b62 1868 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1869 if (!vmm_exclusive) {
d462b819
NHE		 1870 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1871 vcpu->cpu = -1;
4610c9cc
DX		 1872 kvm_cpu_vmxoff();
1873 }
6aa8b732
AK		 1874}
1875
5fd86fcf
AK		 1876static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1877{
81231c69
AK		 1878 ulong cr0;
1879
5fd86fcf
AK		 1880 if (vcpu->fpu_active)
1881 return;
1882 vcpu->fpu_active = 1;
81231c69
AK		 1883 cr0 = vmcs_readl(GUEST_CR0);
1884 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1885 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1886 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1887 update_exception_bitmap(vcpu);
edcafe3c 1888 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1889 if (is_guest_mode(vcpu))
1890 vcpu->arch.cr0_guest_owned_bits &=
1891 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1892 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1893}
1894
edcafe3c
AK		 1895static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1896
fe3ef05c
NHE		 1897/*
1898 * Return the cr0 value that a nested guest would read. This is a combination
1899 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1900 * its hypervisor (cr0_read_shadow).
1901 */
1902static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1903{
1904 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1905 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1906}
1907static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1908{
1909 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1910 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1911}
1912
5fd86fcf
AK		 1913static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1914{
36cf24e0
NHE		 1915 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1916 * set this *before* calling this function.
1917 */
edcafe3c 1918 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1919 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1920 update_exception_bitmap(vcpu);
edcafe3c
AK		 1921 vcpu->arch.cr0_guest_owned_bits = 0;
1922 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1923 if (is_guest_mode(vcpu)) {
1924 /*
1925 * L1's specified read shadow might not contain the TS bit,
1926 * so now that we turned on shadowing of this bit, we need to
1927 * set this bit of the shadow. Like in nested_vmx_run we need
1928 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1929 * up-to-date here because we just decached cr0.TS (and we'll
1930 * only update vmcs12->guest_cr0 on nested exit).
1931 */
1932 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1933 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1934 (vcpu->arch.cr0 & X86_CR0_TS);
1935 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1936 } else
1937 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1938}
1939
6aa8b732
AK		 1940static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1941{
78ac8b47 1942 unsigned long rflags, save_rflags;
345dcaa8 1943
6de12732
AK		 1944 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1945 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1946 rflags = vmcs_readl(GUEST_RFLAGS);
1947 if (to_vmx(vcpu)->rmode.vm86_active) {
1948 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1949 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1950 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1951 }
1952 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1953 }
6de12732 1954 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1955}
1956
1957static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1958{
6de12732
AK		 1959 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1960 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1961 if (to_vmx(vcpu)->rmode.vm86_active) {
1962 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1963 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1964 }
6aa8b732
AK		 1965 vmcs_writel(GUEST_RFLAGS, rflags);
1966}
1967
37ccdcbe 1968static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1969{
1970 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1971 int ret = 0;
1972
1973 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1974 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1975 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1976 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1977
37ccdcbe 1978 return ret;
2809f5d2
GC		 1979}
1980
1981static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1982{
1983 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1984 u32 interruptibility = interruptibility_old;
1985
1986 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1987
48005f64 1988 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1989 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1990 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1991 interruptibility |= GUEST_INTR_STATE_STI;
1992
1993 if ((interruptibility != interruptibility_old))
1994 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1995}
1996
6aa8b732
AK		 1997static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1998{
1999 unsigned long rip;
6aa8b732 2000
5fdbf976 2001 rip = kvm_rip_read(vcpu);
6aa8b732 2002 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2003 kvm_rip_write(vcpu, rip);
6aa8b732 2004
2809f5d2
GC		 2005 /* skipping an emulated instruction also counts */
2006 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2007}
2008
0b6ac343
NHE		 2009/*
2010 * KVM wants to inject page-faults which it got to the guest. This function
2011 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2012 */
e011c663 2013static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2014{
2015 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2016
e011c663 2017 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2018 return 0;
2019
533558bc
JK		 2020 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2021 vmcs_read32(VM_EXIT_INTR_INFO),
2022 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2023 return 1;
2024}
2025
298101da 2026static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2027 bool has_error_code, u32 error_code,
2028 bool reinject)
298101da 2029{
77ab6db0 2030 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2031 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2032
e011c663
GN		 2033 if (!reinject && is_guest_mode(vcpu) &&
2034 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2035 return;
2036
8ab2d2e2 2037 if (has_error_code) {
77ab6db0 2038 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2039 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2040 }
77ab6db0 2041
7ffd92c5 2042 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2043 int inc_eip = 0;
2044 if (kvm_exception_is_soft(nr))
2045 inc_eip = vcpu->arch.event_exit_inst_len;
2046 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2047 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2048 return;
2049 }
2050
66fd3f7f
GN		 2051 if (kvm_exception_is_soft(nr)) {
2052 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2053 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2054 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2055 } else
2056 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2057
2058 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2059}
2060
4e47c7a6
SY		 2061static bool vmx_rdtscp_supported(void)
2062{
2063 return cpu_has_vmx_rdtscp();
2064}
2065
ad756a16
MJ		 2066static bool vmx_invpcid_supported(void)
2067{
2068 return cpu_has_vmx_invpcid() && enable_ept;
2069}
2070
a75beee6
ED		 2071/*
2072 * Swap MSR entry in host/guest MSR entry array.
2073 */
8b9cf98c 2074static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2075{
26bb0981 2076 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2077
2078 tmp = vmx->guest_msrs[to];
2079 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2080 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2081}
2082
8d14695f
YZ		 2083static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2084{
2085 unsigned long *msr_bitmap;
2086
2087 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2088 if (is_long_mode(vcpu))
2089 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2090 else
2091 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2092 } else {
2093 if (is_long_mode(vcpu))
2094 msr_bitmap = vmx_msr_bitmap_longmode;
2095 else
2096 msr_bitmap = vmx_msr_bitmap_legacy;
2097 }
2098
2099 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2100}
2101
e38aea3e
AK		 2102/*
2103 * Set up the vmcs to automatically save and restore system
2104 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2105 * mode, as fiddling with msrs is very expensive.
2106 */
8b9cf98c 2107static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2108{
26bb0981 2109 int save_nmsrs, index;
e38aea3e 2110
a75beee6
ED		 2111 save_nmsrs = 0;
2112#ifdef CONFIG_X86_64
8b9cf98c 2113 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2114 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2115 if (index >= 0)
8b9cf98c
RR		 2116 move_msr_up(vmx, index, save_nmsrs++);
2117 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2118 if (index >= 0)
8b9cf98c
RR		 2119 move_msr_up(vmx, index, save_nmsrs++);
2120 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2121 if (index >= 0)
8b9cf98c 2122 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2123 index = __find_msr_index(vmx, MSR_TSC_AUX);
2124 if (index >= 0 && vmx->rdtscp_enabled)
2125 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2126 /*
8c06585d 2127 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2128 * if efer.sce is enabled.
2129 */
8c06585d 2130 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2131 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2132 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2133 }
2134#endif
92c0d900
AK		 2135 index = __find_msr_index(vmx, MSR_EFER);
2136 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2137 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2138
26bb0981 2139 vmx->save_nmsrs = save_nmsrs;
5897297b 2140
8d14695f
YZ		 2141 if (cpu_has_vmx_msr_bitmap())
2142 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2143}
2144
6aa8b732
AK		 2145/*
2146 * reads and returns guest's timestamp counter "register"
2147 * guest_tsc = host_tsc + tsc_offset -- 21.3
2148 */
2149static u64 guest_read_tsc(void)
2150{
2151 u64 host_tsc, tsc_offset;
2152
2153 rdtscll(host_tsc);
2154 tsc_offset = vmcs_read64(TSC_OFFSET);
2155 return host_tsc + tsc_offset;
2156}
2157
d5c1785d
NHE		 2158/*
2159 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2160 * counter, even if a nested guest (L2) is currently running.
2161 */
886b470c 2162u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2163{
886b470c 2164 u64 tsc_offset;
d5c1785d 2165
d5c1785d
NHE		 2166 tsc_offset = is_guest_mode(vcpu) ?
2167 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2168 vmcs_read64(TSC_OFFSET);
2169 return host_tsc + tsc_offset;
2170}
2171
4051b188 2172/*
cc578287
ZA		 2173 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2174 * software catchup for faster rates on slower CPUs.
4051b188 2175 */
cc578287 2176static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2177{
cc578287
ZA		 2178 if (!scale)
2179 return;
2180
2181 if (user_tsc_khz > tsc_khz) {
2182 vcpu->arch.tsc_catchup = 1;
2183 vcpu->arch.tsc_always_catchup = 1;
2184 } else
2185 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2186}
2187
ba904635
WA		 2188static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2189{
2190 return vmcs_read64(TSC_OFFSET);
2191}
2192
6aa8b732 2193/*
99e3e30a 2194 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2195 */
99e3e30a 2196static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2197{
27fc51b2 2198 if (is_guest_mode(vcpu)) {
7991825b 2199 /*
27fc51b2
NHE		 2200 * We're here if L1 chose not to trap WRMSR to TSC. According
2201 * to the spec, this should set L1's TSC; The offset that L1
2202 * set for L2 remains unchanged, and still needs to be added
2203 * to the newly set TSC to get L2's TSC.
7991825b 2204 */
27fc51b2
NHE		 2205 struct vmcs12 *vmcs12;
2206 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2207 /* recalculate vmcs02.TSC_OFFSET: */
2208 vmcs12 = get_vmcs12(vcpu);
2209 vmcs_write64(TSC_OFFSET, offset +
2210 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2211 vmcs12->tsc_offset : 0));
2212 } else {
489223ed
YY		 2213 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2214 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2215 vmcs_write64(TSC_OFFSET, offset);
2216 }
6aa8b732
AK		 2217}
2218
f1e2b260 2219static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2220{
2221 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2222
e48672fa 2223 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2224 if (is_guest_mode(vcpu)) {
2225 /* Even when running L2, the adjustment needs to apply to L1 */
2226 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2227 } else
2228 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2229 offset + adjustment);
e48672fa
ZA		 2230}
2231
857e4099
JR		 2232static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2233{
2234 return target_tsc - native_read_tsc();
2235}
2236
801d3424
NHE		 2237static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2238{
2239 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2240 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2241}
2242
2243/*
2244 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2245 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2246 * all guests if the "nested" module option is off, and can also be disabled
2247 * for a single guest by disabling its VMX cpuid bit.
2248 */
2249static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2250{
2251 return nested && guest_cpuid_has_vmx(vcpu);
2252}
2253
b87a51ae
NHE		 2254/*
2255 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2256 * returned for the various VMX controls MSRs when nested VMX is enabled.
2257 * The same values should also be used to verify that vmcs12 control fields are
2258 * valid during nested entry from L1 to L2.
2259 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2260 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2261 * bit in the high half is on if the corresponding bit in the control field
2262 * may be on. See also vmx_control_verify().
2263 * TODO: allow these variables to be modified (downgraded) by module options
2264 * or other means.
2265 */
2266static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2267static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2268static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2269static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2270static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2271static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2272static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2273static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2274static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2275static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2276static __init void nested_vmx_setup_ctls_msrs(void)
2277{
2278 /*
2279 * Note that as a general rule, the high half of the MSRs (bits in
2280 * the control fields which may be 1) should be initialized by the
2281 * intersection of the underlying hardware's MSR (i.e., features which
2282 * can be supported) and the list of features we want to expose -
2283 * because they are known to be properly supported in our code.
2284 * Also, usually, the low half of the MSRs (bits which must be 1) can
2285 * be set to 0, meaning that L1 may turn off any of these bits. The
2286 * reason is that if one of these bits is necessary, it will appear
2287 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2288 * fields of vmcs01 and vmcs02, will turn these bits off - and
2289 * nested_vmx_exit_handled() will not pass related exits to L1.
2290 * These rules have exceptions below.
2291 */
2292
2293 /* pin-based controls */
eabeaacc
JK		 2294 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2295 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2296 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2297 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2298 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2299 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2300 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2301
3dbcd8da 2302 /* exit controls */
c0dfee58
ACL		 2303 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2304 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2305 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2306
c0dfee58 2307 nested_vmx_exit_ctls_high &=
b87a51ae 2308#ifdef CONFIG_X86_64
c0dfee58 2309 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2310#endif
f4124500
JK		 2311 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2312 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2313 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2314 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2315
36be0b9d
PB		 2316 if (vmx_mpx_supported())
2317 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2318
2996fca0
JK		 2319 /* We support free control of debug control saving. */
2320 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2321 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2322
b87a51ae
NHE		 2323 /* entry controls */
2324 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2325 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2326 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2327 nested_vmx_entry_ctls_high &=
57435349
JK		 2328#ifdef CONFIG_X86_64
2329 VM_ENTRY_IA32E_MODE |
2330#endif
2331 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2332 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2333 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2334 if (vmx_mpx_supported())
2335 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2336
2996fca0
JK		 2337 /* We support free control of debug control loading. */
2338 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2339 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2340
b87a51ae
NHE		 2341 /* cpu-based controls */
2342 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2343 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2344 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2345 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2346 CPU_BASED_VIRTUAL_INTR_PENDING |
2347 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2348 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2349 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2350 CPU_BASED_CR3_STORE_EXITING |
2351#ifdef CONFIG_X86_64
2352 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2353#endif
2354 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2355 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2356 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2357 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2358 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2359 /*
2360 * We can allow some features even when not supported by the
2361 * hardware. For example, L1 can specify an MSR bitmap - and we
2362 * can use it to avoid exits to L1 - even when L0 runs L2
2363 * without MSR bitmaps.
2364 */
560b7ee1
JK		 2365 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2366 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2367
3dcdf3ec
JK		 2368 /* We support free control of CR3 access interception. */
2369 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2370 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2371
b87a51ae
NHE		 2372 /* secondary cpu-based controls */
2373 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2374 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2375 nested_vmx_secondary_ctls_low = 0;
2376 nested_vmx_secondary_ctls_high &=
d6851fbe 2377 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2378 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2379 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2380
afa61f75
NHE		 2381 if (enable_ept) {
2382 /* nested EPT: emulate EPT also to L1 */
2383 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2384 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2385 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2386 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2387 nested_vmx_ept_caps &= vmx_capability.ept;
2388 /*
4b855078
BD		 2389 * For nested guests, we don't do anything specific
2390 * for single context invalidation. Hence, only advertise
2391 * support for global context invalidation.
afa61f75 2392 */
4b855078 2393 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2394 } else
2395 nested_vmx_ept_caps = 0;
2396
c18911a2
JK		 2397 /* miscellaneous data */
2398 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2399 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2400 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2401 VMX_MISC_ACTIVITY_HLT;
c18911a2 2402 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2403}
2404
2405static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2406{
2407 /*
2408 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2409 */
2410 return ((control & high) | low) == control;
2411}
2412
2413static inline u64 vmx_control_msr(u32 low, u32 high)
2414{
2415 return low | ((u64)high << 32);
2416}
2417
cae50139 2418/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2419static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2420{
b87a51ae 2421 switch (msr_index) {
b87a51ae
NHE		 2422 case MSR_IA32_VMX_BASIC:
2423 /*
2424 * This MSR reports some information about VMX support. We
2425 * should return information about the VMX we emulate for the
2426 * guest, and the VMCS structure we give it - not about the
2427 * VMX support of the underlying hardware.
2428 */
3dbcd8da 2429 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2430 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2431 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2432 break;
2433 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2434 case MSR_IA32_VMX_PINBASED_CTLS:
2435 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2436 nested_vmx_pinbased_ctls_high);
2437 break;
2438 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2439 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2440 nested_vmx_procbased_ctls_high);
2441 break;
b87a51ae
NHE		 2442 case MSR_IA32_VMX_PROCBASED_CTLS:
2443 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2444 nested_vmx_procbased_ctls_high);
2445 break;
2446 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2447 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2448 nested_vmx_exit_ctls_high);
2449 break;
b87a51ae
NHE		 2450 case MSR_IA32_VMX_EXIT_CTLS:
2451 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2452 nested_vmx_exit_ctls_high);
2453 break;
2454 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2455 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2456 nested_vmx_entry_ctls_high);
2457 break;
b87a51ae
NHE		 2458 case MSR_IA32_VMX_ENTRY_CTLS:
2459 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2460 nested_vmx_entry_ctls_high);
2461 break;
2462 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2463 *pdata = vmx_control_msr(nested_vmx_misc_low,
2464 nested_vmx_misc_high);
b87a51ae
NHE		 2465 break;
2466 /*
2467 * These MSRs specify bits which the guest must keep fixed (on or off)
2468 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2469 * We picked the standard core2 setting.
2470 */
2471#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2472#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2473 case MSR_IA32_VMX_CR0_FIXED0:
2474 *pdata = VMXON_CR0_ALWAYSON;
2475 break;
2476 case MSR_IA32_VMX_CR0_FIXED1:
2477 *pdata = -1ULL;
2478 break;
2479 case MSR_IA32_VMX_CR4_FIXED0:
2480 *pdata = VMXON_CR4_ALWAYSON;
2481 break;
2482 case MSR_IA32_VMX_CR4_FIXED1:
2483 *pdata = -1ULL;
2484 break;
2485 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2486 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2487 break;
2488 case MSR_IA32_VMX_PROCBASED_CTLS2:
2489 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2490 nested_vmx_secondary_ctls_high);
2491 break;
2492 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2493 /* Currently, no nested vpid support */
2494 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2495 break;
2496 default:
b87a51ae 2497 return 1;
b3897a49
NHE		 2498 }
2499
b87a51ae
NHE		 2500 return 0;
2501}
2502
6aa8b732
AK		 2503/*
2504 * Reads an msr value (of 'msr_index') into 'pdata'.
2505 * Returns 0 on success, non-0 otherwise.
2506 * Assumes vcpu_load() was already called.
2507 */
2508static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2509{
2510 u64 data;
26bb0981 2511 struct shared_msr_entry *msr;
6aa8b732
AK		 2512
2513 if (!pdata) {
2514 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2515 return -EINVAL;
2516 }
2517
2518 switch (msr_index) {
05b3e0c2 2519#ifdef CONFIG_X86_64
6aa8b732
AK		 2520 case MSR_FS_BASE:
2521 data = vmcs_readl(GUEST_FS_BASE);
2522 break;
2523 case MSR_GS_BASE:
2524 data = vmcs_readl(GUEST_GS_BASE);
2525 break;
44ea2b17
AK		 2526 case MSR_KERNEL_GS_BASE:
2527 vmx_load_host_state(to_vmx(vcpu));
2528 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2529 break;
26bb0981 2530#endif
6aa8b732 2531 case MSR_EFER:
3bab1f5d 2532 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2533 case MSR_IA32_TSC:
6aa8b732
AK		 2534 data = guest_read_tsc();
2535 break;
2536 case MSR_IA32_SYSENTER_CS:
2537 data = vmcs_read32(GUEST_SYSENTER_CS);
2538 break;
2539 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2540 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2541 break;
2542 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2543 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2544 break;
0dd376e7 2545 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2546 if (!vmx_mpx_supported())
2547 return 1;
0dd376e7
LJ		 2548 data = vmcs_read64(GUEST_BNDCFGS);
2549 break;
cae50139
JK		 2550 case MSR_IA32_FEATURE_CONTROL:
2551 if (!nested_vmx_allowed(vcpu))
2552 return 1;
2553 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2554 break;
2555 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2556 if (!nested_vmx_allowed(vcpu))
2557 return 1;
2558 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2559 case MSR_TSC_AUX:
2560 if (!to_vmx(vcpu)->rdtscp_enabled)
2561 return 1;
2562 /* Otherwise falls through */
6aa8b732 2563 default:
8b9cf98c 2564 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2565 if (msr) {
2566 data = msr->data;
2567 break;
6aa8b732 2568 }
3bab1f5d 2569 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2570 }
2571
2572 *pdata = data;
2573 return 0;
2574}
2575
cae50139
JK		 2576static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2577
6aa8b732
AK		 2578/*
2579 * Writes msr value into into the appropriate "register".
2580 * Returns 0 on success, non-0 otherwise.
2581 * Assumes vcpu_load() was already called.
2582 */
8fe8ab46 2583static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2584{
a2fa3e9f 2585 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2586 struct shared_msr_entry *msr;
2cc51560 2587 int ret = 0;
8fe8ab46
WA		 2588 u32 msr_index = msr_info->index;
2589 u64 data = msr_info->data;
2cc51560 2590
6aa8b732 2591 switch (msr_index) {
3bab1f5d 2592 case MSR_EFER:
8fe8ab46 2593 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2594 break;
16175a79 2595#ifdef CONFIG_X86_64
6aa8b732 2596 case MSR_FS_BASE:
2fb92db1 2597 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2598 vmcs_writel(GUEST_FS_BASE, data);
2599 break;
2600 case MSR_GS_BASE:
2fb92db1 2601 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2602 vmcs_writel(GUEST_GS_BASE, data);
2603 break;
44ea2b17
AK		 2604 case MSR_KERNEL_GS_BASE:
2605 vmx_load_host_state(vmx);
2606 vmx->msr_guest_kernel_gs_base = data;
2607 break;
6aa8b732
AK		 2608#endif
2609 case MSR_IA32_SYSENTER_CS:
2610 vmcs_write32(GUEST_SYSENTER_CS, data);
2611 break;
2612 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2613 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2614 break;
2615 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2616 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2617 break;
0dd376e7 2618 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2619 if (!vmx_mpx_supported())
2620 return 1;
0dd376e7
LJ		 2621 vmcs_write64(GUEST_BNDCFGS, data);
2622 break;
af24a4e4 2623 case MSR_IA32_TSC:
8fe8ab46 2624 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2625 break;
468d472f
SY		 2626 case MSR_IA32_CR_PAT:
2627 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2628 vmcs_write64(GUEST_IA32_PAT, data);
2629 vcpu->arch.pat = data;
2630 break;
2631 }
8fe8ab46 2632 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2633 break;
ba904635
WA		 2634 case MSR_IA32_TSC_ADJUST:
2635 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2636 break;
cae50139
JK		 2637 case MSR_IA32_FEATURE_CONTROL:
2638 if (!nested_vmx_allowed(vcpu) ||
2639 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2640 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2641 return 1;
2642 vmx->nested.msr_ia32_feature_control = data;
2643 if (msr_info->host_initiated && data == 0)
2644 vmx_leave_nested(vcpu);
2645 break;
2646 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2647 return 1; /* they are read-only */
4e47c7a6
SY		 2648 case MSR_TSC_AUX:
2649 if (!vmx->rdtscp_enabled)
2650 return 1;
2651 /* Check reserved bit, higher 32 bits should be zero */
2652 if ((data >> 32) != 0)
2653 return 1;
2654 /* Otherwise falls through */
6aa8b732 2655 default:
8b9cf98c 2656 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2657 if (msr) {
2658 msr->data = data;
2225fd56
AK		 2659 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2660 preempt_disable();
9ee73970
AK		 2661 kvm_set_shared_msr(msr->index, msr->data,
2662 msr->mask);
2225fd56
AK		 2663 preempt_enable();
2664 }
3bab1f5d 2665 break;
6aa8b732 2666 }
8fe8ab46 2667 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2668 }
2669
2cc51560 2670 return ret;
6aa8b732
AK		 2671}
2672
5fdbf976 2673static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2674{
5fdbf976
MT		 2675 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2676 switch (reg) {
2677 case VCPU_REGS_RSP:
2678 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2679 break;
2680 case VCPU_REGS_RIP:
2681 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2682 break;
6de4f3ad
AK		 2683 case VCPU_EXREG_PDPTR:
2684 if (enable_ept)
2685 ept_save_pdptrs(vcpu);
2686 break;
5fdbf976
MT		 2687 default:
2688 break;
2689 }
6aa8b732
AK		 2690}
2691
6aa8b732
AK		 2692static __init int cpu_has_kvm_support(void)
2693{
6210e37b 2694 return cpu_has_vmx();
6aa8b732
AK		 2695}
2696
2697static __init int vmx_disabled_by_bios(void)
2698{
2699 u64 msr;
2700
2701 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2702 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2703 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2704 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2705 && tboot_enabled())
2706 return 1;
23f3e991 2707 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2708 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2709 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2710 && !tboot_enabled()) {
2711 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2712 "activate TXT before enabling KVM\n");
cafd6659 2713 return 1;
f9335afe 2714 }
23f3e991
JC		 2715 /* launched w/o TXT and VMX disabled */
2716 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2717 && !tboot_enabled())
2718 return 1;
cafd6659
SW		 2719 }
2720
2721 return 0;
6aa8b732
AK		 2722}
2723
7725b894
DX		 2724static void kvm_cpu_vmxon(u64 addr)
2725{
2726 asm volatile (ASM_VMX_VMXON_RAX
2727 : : "a"(&addr), "m"(addr)
2728 : "memory", "cc");
2729}
2730
10474ae8 2731static int hardware_enable(void *garbage)
6aa8b732
AK		 2732{
2733 int cpu = raw_smp_processor_id();
2734 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2735 u64 old, test_bits;
6aa8b732 2736
10474ae8
AG		 2737 if (read_cr4() & X86_CR4_VMXE)
2738 return -EBUSY;
2739
d462b819 2740 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2741
2742 /*
2743 * Now we can enable the vmclear operation in kdump
2744 * since the loaded_vmcss_on_cpu list on this cpu
2745 * has been initialized.
2746 *
2747 * Though the cpu is not in VMX operation now, there
2748 * is no problem to enable the vmclear operation
2749 * for the loaded_vmcss_on_cpu list is empty!
2750 */
2751 crash_enable_local_vmclear(cpu);
2752
6aa8b732 2753 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2754
2755 test_bits = FEATURE_CONTROL_LOCKED;
2756 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2757 if (tboot_enabled())
2758 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2759
2760 if ((old & test_bits) != test_bits) {
6aa8b732 2761 /* enable and lock */
cafd6659
SW		 2762 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2763 }
66aee91a 2764 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2765
4610c9cc
DX		 2766 if (vmm_exclusive) {
2767 kvm_cpu_vmxon(phys_addr);
2768 ept_sync_global();
2769 }
10474ae8 2770
357d1226 2771 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2772
10474ae8 2773 return 0;
6aa8b732
AK		 2774}
2775
d462b819 2776static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2777{
2778 int cpu = raw_smp_processor_id();
d462b819 2779 struct loaded_vmcs *v, *n;
543e4243 2780
d462b819
NHE		 2781 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2782 loaded_vmcss_on_cpu_link)
2783 __loaded_vmcs_clear(v);
543e4243
AK		 2784}
2785
710ff4a8
EH		 2786
2787/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2788 * tricks.
2789 */
2790static void kvm_cpu_vmxoff(void)
6aa8b732 2791{
4ecac3fd 2792 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2793}
2794
710ff4a8
EH		 2795static void hardware_disable(void *garbage)
2796{
4610c9cc 2797 if (vmm_exclusive) {
d462b819 2798 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2799 kvm_cpu_vmxoff();
2800 }
7725b894 2801 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2802}
2803
1c3d14fe 2804static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2805 u32 msr, u32 *result)
1c3d14fe
YS		 2806{
2807 u32 vmx_msr_low, vmx_msr_high;
2808 u32 ctl = ctl_min | ctl_opt;
2809
2810 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2811
2812 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2813 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2814
2815 /* Ensure minimum (required) set of control bits are supported. */
2816 if (ctl_min & ~ctl)
002c7f7c 2817 return -EIO;
1c3d14fe
YS		 2818
2819 *result = ctl;
2820 return 0;
2821}
2822
110312c8
AK		 2823static __init bool allow_1_setting(u32 msr, u32 ctl)
2824{
2825 u32 vmx_msr_low, vmx_msr_high;
2826
2827 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2828 return vmx_msr_high & ctl;
2829}
2830
002c7f7c 2831static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2832{
2833 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2834 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2835 u32 _pin_based_exec_control = 0;
2836 u32 _cpu_based_exec_control = 0;
f78e0e2e 2837 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2838 u32 _vmexit_control = 0;
2839 u32 _vmentry_control = 0;
2840
10166744 2841 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2842#ifdef CONFIG_X86_64
2843 CPU_BASED_CR8_LOAD_EXITING |
2844 CPU_BASED_CR8_STORE_EXITING |
2845#endif
d56f546d
SY		 2846 CPU_BASED_CR3_LOAD_EXITING |
2847 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2848 CPU_BASED_USE_IO_BITMAPS |
2849 CPU_BASED_MOV_DR_EXITING |
a7052897 2850 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2851 CPU_BASED_MWAIT_EXITING |
2852 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2853 CPU_BASED_INVLPG_EXITING |
2854 CPU_BASED_RDPMC_EXITING;
443381a8 2855
f78e0e2e 2856 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2857 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2858 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2859 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2860 &_cpu_based_exec_control) < 0)
002c7f7c 2861 return -EIO;
6e5d865c
YS		 2862#ifdef CONFIG_X86_64
2863 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2864 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2865 ~CPU_BASED_CR8_STORE_EXITING;
2866#endif
f78e0e2e 2867 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2868 min2 = 0;
2869 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2870 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2871 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2872 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2873 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2874 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2875 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2876 SECONDARY_EXEC_RDTSCP |
83d4c286 2877 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2878 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2879 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2880 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2881 if (adjust_vmx_controls(min2, opt2,
2882 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2883 &_cpu_based_2nd_exec_control) < 0)
2884 return -EIO;
2885 }
2886#ifndef CONFIG_X86_64
2887 if (!(_cpu_based_2nd_exec_control &
2888 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2889 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2890#endif
83d4c286
YZ		 2891
2892 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2893 _cpu_based_2nd_exec_control &= ~(
8d14695f 2894 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2895 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2896 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2897
d56f546d 2898 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2899 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2900 enabled */
5fff7d27
GN		 2901 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2902 CPU_BASED_CR3_STORE_EXITING |
2903 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2904 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2905 vmx_capability.ept, vmx_capability.vpid);
2906 }
1c3d14fe 2907
81908bf4 2908 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2909#ifdef CONFIG_X86_64
2910 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2911#endif
a547c6db 2912 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2913 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2914 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2915 &_vmexit_control) < 0)
002c7f7c 2916 return -EIO;
1c3d14fe 2917
01e439be
YZ		 2918 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2919 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2920 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2921 &_pin_based_exec_control) < 0)
2922 return -EIO;
2923
2924 if (!(_cpu_based_2nd_exec_control &
2925 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2926 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2927 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2928
c845f9c6 2929 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2930 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2931 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2932 &_vmentry_control) < 0)
002c7f7c 2933 return -EIO;
6aa8b732 2934
c68876fd 2935 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2936
2937 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2938 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2939 return -EIO;
1c3d14fe
YS		 2940
2941#ifdef CONFIG_X86_64
2942 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2943 if (vmx_msr_high & (1u<<16))
002c7f7c 2944 return -EIO;
1c3d14fe
YS		 2945#endif
2946
2947 /* Require Write-Back (WB) memory type for VMCS accesses. */
2948 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2949 return -EIO;
1c3d14fe 2950
002c7f7c
YS		 2951 vmcs_conf->size = vmx_msr_high & 0x1fff;
2952 vmcs_conf->order = get_order(vmcs_config.size);
2953 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2954
002c7f7c
YS		 2955 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2956 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2957 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2958 vmcs_conf->vmexit_ctrl = _vmexit_control;
2959 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2960
110312c8
AK		 2961 cpu_has_load_ia32_efer =
2962 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2963 VM_ENTRY_LOAD_IA32_EFER)
2964 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2965 VM_EXIT_LOAD_IA32_EFER);
2966
8bf00a52
GN		 2967 cpu_has_load_perf_global_ctrl =
2968 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2969 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2970 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2971 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2972
2973 /*
2974 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2975 * but due to arrata below it can't be used. Workaround is to use
2976 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2977 *
2978 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2979 *
2980 * AAK155 (model 26)
2981 * AAP115 (model 30)
2982 * AAT100 (model 37)
2983 * BC86,AAY89,BD102 (model 44)
2984 * BA97 (model 46)
2985 *
2986 */
2987 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2988 switch (boot_cpu_data.x86_model) {
2989 case 26:
2990 case 30:
2991 case 37:
2992 case 44:
2993 case 46:
2994 cpu_has_load_perf_global_ctrl = false;
2995 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2996 "does not work properly. Using workaround\n");
2997 break;
2998 default:
2999 break;
3000 }
3001 }
3002
1c3d14fe 3003 return 0;
c68876fd 3004}
6aa8b732
AK		 3005
3006static struct vmcs *alloc_vmcs_cpu(int cpu)
3007{
3008 int node = cpu_to_node(cpu);
3009 struct page *pages;
3010 struct vmcs *vmcs;
3011
6484eb3e 3012 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3013 if (!pages)
3014 return NULL;
3015 vmcs = page_address(pages);
1c3d14fe
YS		 3016 memset(vmcs, 0, vmcs_config.size);
3017 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3018 return vmcs;
3019}
3020
3021static struct vmcs *alloc_vmcs(void)
3022{
d3b2c338 3023 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3024}
3025
3026static void free_vmcs(struct vmcs *vmcs)
3027{
1c3d14fe 3028 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3029}
3030
d462b819
NHE		 3031/*
3032 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3033 */
3034static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3035{
3036 if (!loaded_vmcs->vmcs)
3037 return;
3038 loaded_vmcs_clear(loaded_vmcs);
3039 free_vmcs(loaded_vmcs->vmcs);
3040 loaded_vmcs->vmcs = NULL;
3041}
3042
39959588 3043static void free_kvm_area(void)
6aa8b732
AK		 3044{
3045 int cpu;
3046
3230bb47 3047 for_each_possible_cpu(cpu) {
6aa8b732 3048 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3049 per_cpu(vmxarea, cpu) = NULL;
3050 }
6aa8b732
AK		 3051}
3052
fe2b201b
BD		 3053static void init_vmcs_shadow_fields(void)
3054{
3055 int i, j;
3056
3057 /* No checks for read only fields yet */
3058
3059 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3060 switch (shadow_read_write_fields[i]) {
3061 case GUEST_BNDCFGS:
3062 if (!vmx_mpx_supported())
3063 continue;
3064 break;
3065 default:
3066 break;
3067 }
3068
3069 if (j < i)
3070 shadow_read_write_fields[j] =
3071 shadow_read_write_fields[i];
3072 j++;
3073 }
3074 max_shadow_read_write_fields = j;
3075
3076 /* shadowed fields guest access without vmexit */
3077 for (i = 0; i < max_shadow_read_write_fields; i++) {
3078 clear_bit(shadow_read_write_fields[i],
3079 vmx_vmwrite_bitmap);
3080 clear_bit(shadow_read_write_fields[i],
3081 vmx_vmread_bitmap);
3082 }
3083 for (i = 0; i < max_shadow_read_only_fields; i++)
3084 clear_bit(shadow_read_only_fields[i],
3085 vmx_vmread_bitmap);
3086}
3087
6aa8b732
AK		 3088static __init int alloc_kvm_area(void)
3089{
3090 int cpu;
3091
3230bb47 3092 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3093 struct vmcs *vmcs;
3094
3095 vmcs = alloc_vmcs_cpu(cpu);
3096 if (!vmcs) {
3097 free_kvm_area();
3098 return -ENOMEM;
3099 }
3100
3101 per_cpu(vmxarea, cpu) = vmcs;
3102 }
3103 return 0;
3104}
3105
3106static __init int hardware_setup(void)
3107{
002c7f7c
YS		 3108 if (setup_vmcs_config(&vmcs_config) < 0)
3109 return -EIO;
50a37eb4
JR		 3110
3111 if (boot_cpu_has(X86_FEATURE_NX))
3112 kvm_enable_efer_bits(EFER_NX);
3113
93ba03c2
SY		 3114 if (!cpu_has_vmx_vpid())
3115 enable_vpid = 0;
abc4fc58
AG		 3116 if (!cpu_has_vmx_shadow_vmcs())
3117 enable_shadow_vmcs = 0;
fe2b201b
BD		 3118 if (enable_shadow_vmcs)
3119 init_vmcs_shadow_fields();
93ba03c2 3120
4bc9b982
SY		 3121 if (!cpu_has_vmx_ept() ||
3122 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3123 enable_ept = 0;
3a624e29 3124 enable_unrestricted_guest = 0;
83c3a331 3125 enable_ept_ad_bits = 0;
3a624e29
NK		 3126 }
3127
83c3a331
XH		 3128 if (!cpu_has_vmx_ept_ad_bits())
3129 enable_ept_ad_bits = 0;
3130
3a624e29
NK		 3131 if (!cpu_has_vmx_unrestricted_guest())
3132 enable_unrestricted_guest = 0;
93ba03c2
SY		 3133
3134 if (!cpu_has_vmx_flexpriority())
3135 flexpriority_enabled = 0;
3136
95ba8273
GN		 3137 if (!cpu_has_vmx_tpr_shadow())
3138 kvm_x86_ops->update_cr8_intercept = NULL;
3139
54dee993
MT		 3140 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3141 kvm_disable_largepages();
3142
4b8d54f9
ZE		 3143 if (!cpu_has_vmx_ple())
3144 ple_gap = 0;
3145
01e439be
YZ		 3146 if (!cpu_has_vmx_apicv())
3147 enable_apicv = 0;
c7c9c56c 3148
01e439be 3149 if (enable_apicv)
c7c9c56c 3150 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3151 else {
c7c9c56c 3152 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3153 kvm_x86_ops->deliver_posted_interrupt = NULL;
3154 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3155 }
83d4c286 3156
b87a51ae
NHE		 3157 if (nested)
3158 nested_vmx_setup_ctls_msrs();
3159
6aa8b732
AK		 3160 return alloc_kvm_area();
3161}
3162
3163static __exit void hardware_unsetup(void)
3164{
3165 free_kvm_area();
3166}
3167
14168786
GN		 3168static bool emulation_required(struct kvm_vcpu *vcpu)
3169{
3170 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3171}
3172
91b0aa2c 3173static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3174 struct kvm_segment *save)
6aa8b732 3175{
d99e4152
GN		 3176 if (!emulate_invalid_guest_state) {
3177 /*
3178 * CS and SS RPL should be equal during guest entry according
3179 * to VMX spec, but in reality it is not always so. Since vcpu
3180 * is in the middle of the transition from real mode to
3181 * protected mode it is safe to assume that RPL 0 is a good
3182 * default value.
3183 */
3184 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3185 save->selector &= ~SELECTOR_RPL_MASK;
3186 save->dpl = save->selector & SELECTOR_RPL_MASK;
3187 save->s = 1;
6aa8b732 3188 }
d99e4152 3189 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3190}
3191
3192static void enter_pmode(struct kvm_vcpu *vcpu)
3193{
3194 unsigned long flags;
a89a8fb9 3195 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3196
d99e4152
GN		 3197 /*
3198 * Update real mode segment cache. It may be not up-to-date if sement
3199 * register was written while vcpu was in a guest mode.
3200 */
3201 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3202 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3203 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3204 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3205 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3206 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3207
7ffd92c5 3208 vmx->rmode.vm86_active = 0;
6aa8b732 3209
2fb92db1
AK		 3210 vmx_segment_cache_clear(vmx);
3211
f5f7b2fe 3212 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3213
3214 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3215 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3216 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3217 vmcs_writel(GUEST_RFLAGS, flags);
3218
66aee91a
RR		 3219 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3220 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3221
3222 update_exception_bitmap(vcpu);
3223
91b0aa2c
GN		 3224 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3225 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3226 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3227 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3228 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3229 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3230}
3231
f5f7b2fe 3232static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3233{
772e0318 3234 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3235 struct kvm_segment var = *save;
3236
3237 var.dpl = 0x3;
3238 if (seg == VCPU_SREG_CS)
3239 var.type = 0x3;
3240
3241 if (!emulate_invalid_guest_state) {
3242 var.selector = var.base >> 4;
3243 var.base = var.base & 0xffff0;
3244 var.limit = 0xffff;
3245 var.g = 0;
3246 var.db = 0;
3247 var.present = 1;
3248 var.s = 1;
3249 var.l = 0;
3250 var.unusable = 0;
3251 var.type = 0x3;
3252 var.avl = 0;
3253 if (save->base & 0xf)
3254 printk_once(KERN_WARNING "kvm: segment base is not "
3255 "paragraph aligned when entering "
3256 "protected mode (seg=%d)", seg);
3257 }
6aa8b732 3258
d99e4152
GN		 3259 vmcs_write16(sf->selector, var.selector);
3260 vmcs_write32(sf->base, var.base);
3261 vmcs_write32(sf->limit, var.limit);
3262 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3263}
3264
3265static void enter_rmode(struct kvm_vcpu *vcpu)
3266{
3267 unsigned long flags;
a89a8fb9 3268 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3269
f5f7b2fe
AK		 3270 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3271 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3272 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3273 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3274 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3275 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3276 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3277
7ffd92c5 3278 vmx->rmode.vm86_active = 1;
6aa8b732 3279
776e58ea
GN		 3280 /*
3281 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3282 * vcpu. Warn the user that an update is overdue.
776e58ea 3283 */
4918c6ca 3284 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3285 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3286 "called before entering vcpu\n");
776e58ea 3287
2fb92db1
AK		 3288 vmx_segment_cache_clear(vmx);
3289
4918c6ca 3290 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3291 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3292 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3293
3294 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3295 vmx->rmode.save_rflags = flags;
6aa8b732 3296
053de044 3297 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3298
3299 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3300 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3301 update_exception_bitmap(vcpu);
3302
d99e4152
GN		 3303 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3304 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3305 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3306 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3307 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3308 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3309
8668a3c4 3310 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3311}
3312
401d10de
AS		 3313static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3314{
3315 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3316 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3317
3318 if (!msr)
3319 return;
401d10de 3320
44ea2b17
AK		 3321 /*
3322 * Force kernel_gs_base reloading before EFER changes, as control
3323 * of this msr depends on is_long_mode().
3324 */
3325 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3326 vcpu->arch.efer = efer;
401d10de 3327 if (efer & EFER_LMA) {
2961e876 3328 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3329 msr->data = efer;
3330 } else {
2961e876 3331 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3332
3333 msr->data = efer & ~EFER_LME;
3334 }
3335 setup_msrs(vmx);
3336}
3337
05b3e0c2 3338#ifdef CONFIG_X86_64
6aa8b732
AK		 3339
3340static void enter_lmode(struct kvm_vcpu *vcpu)
3341{
3342 u32 guest_tr_ar;
3343
2fb92db1
AK		 3344 vmx_segment_cache_clear(to_vmx(vcpu));
3345
6aa8b732
AK		 3346 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3347 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3348 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3349 __func__);
6aa8b732
AK		 3350 vmcs_write32(GUEST_TR_AR_BYTES,
3351 (guest_tr_ar & ~AR_TYPE_MASK)
3352 | AR_TYPE_BUSY_64_TSS);
3353 }
da38f438 3354 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3355}
3356
3357static void exit_lmode(struct kvm_vcpu *vcpu)
3358{
2961e876 3359 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3360 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3361}
3362
3363#endif
3364
2384d2b3
SY		 3365static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3366{
b9d762fa 3367 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3368 if (enable_ept) {
3369 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3370 return;
4e1096d2 3371 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3372 }
2384d2b3
SY		 3373}
3374
e8467fda
AK		 3375static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3376{
3377 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3378
3379 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3380 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3381}
3382
aff48baa
AK		 3383static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3384{
3385 if (enable_ept && is_paging(vcpu))
3386 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3387 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3388}
3389
25c4c276 3390static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3391{
fc78f519
AK		 3392 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3393
3394 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3395 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3396}
3397
1439442c
SY		 3398static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3399{
d0d538b9
GN		 3400 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3401
6de4f3ad
AK		 3402 if (!test_bit(VCPU_EXREG_PDPTR,
3403 (unsigned long *)&vcpu->arch.regs_dirty))
3404 return;
3405
1439442c 3406 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3407 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3408 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3409 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3410 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3411 }
3412}
3413
8f5d549f
AK		 3414static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3415{
d0d538b9
GN		 3416 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3417
8f5d549f 3418 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3419 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3420 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3421 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3422 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3423 }
6de4f3ad
AK		 3424
3425 __set_bit(VCPU_EXREG_PDPTR,
3426 (unsigned long *)&vcpu->arch.regs_avail);
3427 __set_bit(VCPU_EXREG_PDPTR,
3428 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3429}
3430
5e1746d6 3431static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3432
3433static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3434 unsigned long cr0,
3435 struct kvm_vcpu *vcpu)
3436{
5233dd51
MT		 3437 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3438 vmx_decache_cr3(vcpu);
1439442c
SY		 3439 if (!(cr0 & X86_CR0_PG)) {
3440 /* From paging/starting to nonpaging */
3441 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3442 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3443 (CPU_BASED_CR3_LOAD_EXITING |
3444 CPU_BASED_CR3_STORE_EXITING));
3445 vcpu->arch.cr0 = cr0;
fc78f519 3446 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3447 } else if (!is_paging(vcpu)) {
3448 /* From nonpaging to paging */
3449 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3450 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3451 ~(CPU_BASED_CR3_LOAD_EXITING |
3452 CPU_BASED_CR3_STORE_EXITING));
3453 vcpu->arch.cr0 = cr0;
fc78f519 3454 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3455 }
95eb84a7
SY		 3456
3457 if (!(cr0 & X86_CR0_WP))
3458 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3459}
3460
6aa8b732
AK		 3461static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3462{
7ffd92c5 3463 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3464 unsigned long hw_cr0;
3465
5037878e 3466 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3467 if (enable_unrestricted_guest)
5037878e 3468 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3469 else {
5037878e 3470 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3471
218e763f
GN		 3472 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3473 enter_pmode(vcpu);
6aa8b732 3474
218e763f
GN		 3475 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3476 enter_rmode(vcpu);
3477 }
6aa8b732 3478
05b3e0c2 3479#ifdef CONFIG_X86_64
f6801dff 3480 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3481 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3482 enter_lmode(vcpu);
707d92fa 3483 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3484 exit_lmode(vcpu);
3485 }
3486#endif
3487
089d034e 3488 if (enable_ept)
1439442c
SY		 3489 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3490
02daab21 3491 if (!vcpu->fpu_active)
81231c69 3492 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3493
6aa8b732 3494 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3495 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3496 vcpu->arch.cr0 = cr0;
14168786
GN		 3497
3498 /* depends on vcpu->arch.cr0 to be set to a new value */
3499 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3500}
3501
1439442c
SY		 3502static u64 construct_eptp(unsigned long root_hpa)
3503{
3504 u64 eptp;
3505
3506 /* TODO write the value reading from MSR */
3507 eptp = VMX_EPT_DEFAULT_MT |
3508 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3509 if (enable_ept_ad_bits)
3510 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3511 eptp |= (root_hpa & PAGE_MASK);
3512
3513 return eptp;
3514}
3515
6aa8b732
AK		 3516static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3517{
1439442c
SY		 3518 unsigned long guest_cr3;
3519 u64 eptp;
3520
3521 guest_cr3 = cr3;
089d034e 3522 if (enable_ept) {
1439442c
SY		 3523 eptp = construct_eptp(cr3);
3524 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3525 if (is_paging(vcpu) || is_guest_mode(vcpu))
3526 guest_cr3 = kvm_read_cr3(vcpu);
3527 else
3528 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3529 ept_load_pdptrs(vcpu);
1439442c
SY		 3530 }
3531
2384d2b3 3532 vmx_flush_tlb(vcpu);
1439442c 3533 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3534}
3535
5e1746d6 3536static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3537{
7ffd92c5 3538 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3539 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3540
5e1746d6
NHE		 3541 if (cr4 & X86_CR4_VMXE) {
3542 /*
3543 * To use VMXON (and later other VMX instructions), a guest
3544 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3545 * So basically the check on whether to allow nested VMX
3546 * is here.
3547 */
3548 if (!nested_vmx_allowed(vcpu))
3549 return 1;
1a0d74e6
JK		 3550 }
3551 if (to_vmx(vcpu)->nested.vmxon &&
3552 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3553 return 1;
3554
ad312c7c 3555 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3556 if (enable_ept) {
3557 if (!is_paging(vcpu)) {
3558 hw_cr4 &= ~X86_CR4_PAE;
3559 hw_cr4 |= X86_CR4_PSE;
c08800a5 3560 /*
e1e746b3
FW		 3561 * SMEP/SMAP is disabled if CPU is in non-paging mode
3562 * in hardware. However KVM always uses paging mode to
c08800a5 3563 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3564 * To emulate this behavior, SMEP/SMAP needs to be
3565 * manually disabled when guest switches to non-paging
3566 * mode.
c08800a5 3567 */
e1e746b3 3568 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3569 } else if (!(cr4 & X86_CR4_PAE)) {
3570 hw_cr4 &= ~X86_CR4_PAE;
3571 }
3572 }
1439442c
SY		 3573
3574 vmcs_writel(CR4_READ_SHADOW, cr4);
3575 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3576 return 0;
6aa8b732
AK		 3577}
3578
6aa8b732
AK		 3579static void vmx_get_segment(struct kvm_vcpu *vcpu,
3580 struct kvm_segment *var, int seg)
3581{
a9179499 3582 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3583 u32 ar;
3584
c6ad1153 3585 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3586 *var = vmx->rmode.segs[seg];
a9179499 3587 if (seg == VCPU_SREG_TR
2fb92db1 3588 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3589 return;
1390a28b
AK		 3590 var->base = vmx_read_guest_seg_base(vmx, seg);
3591 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3592 return;
a9179499 3593 }
2fb92db1
AK		 3594 var->base = vmx_read_guest_seg_base(vmx, seg);
3595 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3596 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3597 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3598 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3599 var->type = ar & 15;
3600 var->s = (ar >> 4) & 1;
3601 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3602 /*
3603 * Some userspaces do not preserve unusable property. Since usable
3604 * segment has to be present according to VMX spec we can use present
3605 * property to amend userspace bug by making unusable segment always
3606 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3607 * segment as unusable.
3608 */
3609 var->present = !var->unusable;
6aa8b732
AK		 3610 var->avl = (ar >> 12) & 1;
3611 var->l = (ar >> 13) & 1;
3612 var->db = (ar >> 14) & 1;
3613 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3614}
3615
a9179499
AK		 3616static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3617{
a9179499
AK		 3618 struct kvm_segment s;
3619
3620 if (to_vmx(vcpu)->rmode.vm86_active) {
3621 vmx_get_segment(vcpu, &s, seg);
3622 return s.base;
3623 }
2fb92db1 3624 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3625}
3626
b09408d0 3627static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3628{
b09408d0
MT		 3629 struct vcpu_vmx *vmx = to_vmx(vcpu);
3630
ae9fedc7 3631 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3632 return 0;
ae9fedc7
PB		 3633 else {
3634 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3635 return AR_DPL(ar);
69c73028 3636 }
69c73028
AK		 3637}
3638
653e3108 3639static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3640{
6aa8b732
AK		 3641 u32 ar;
3642
f0495f9b 3643 if (var->unusable || !var->present)
6aa8b732
AK		 3644 ar = 1 << 16;
3645 else {
3646 ar = var->type & 15;
3647 ar |= (var->s & 1) << 4;
3648 ar |= (var->dpl & 3) << 5;
3649 ar |= (var->present & 1) << 7;
3650 ar |= (var->avl & 1) << 12;
3651 ar |= (var->l & 1) << 13;
3652 ar |= (var->db & 1) << 14;
3653 ar |= (var->g & 1) << 15;
3654 }
653e3108
AK		 3655
3656 return ar;
3657}
3658
3659static void vmx_set_segment(struct kvm_vcpu *vcpu,
3660 struct kvm_segment *var, int seg)
3661{
7ffd92c5 3662 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3663 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3664
2fb92db1
AK		 3665 vmx_segment_cache_clear(vmx);
3666
1ecd50a9
GN		 3667 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3668 vmx->rmode.segs[seg] = *var;
3669 if (seg == VCPU_SREG_TR)
3670 vmcs_write16(sf->selector, var->selector);
3671 else if (var->s)
3672 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3673 goto out;
653e3108 3674 }
1ecd50a9 3675
653e3108
AK		 3676 vmcs_writel(sf->base, var->base);
3677 vmcs_write32(sf->limit, var->limit);
3678 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3679
3680 /*
3681 * Fix the "Accessed" bit in AR field of segment registers for older
3682 * qemu binaries.
3683 * IA32 arch specifies that at the time of processor reset the
3684 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3685 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3686 * state vmexit when "unrestricted guest" mode is turned on.
3687 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3688 * tree. Newer qemu binaries with that qemu fix would not need this
3689 * kvm hack.
3690 */
3691 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3692 var->type |= 0x1; /* Accessed */
3a624e29 3693
f924d66d 3694 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3695
3696out:
98eb2f8b 3697 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3698}
3699
6aa8b732
AK		 3700static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3701{
2fb92db1 3702 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3703
3704 *db = (ar >> 14) & 1;
3705 *l = (ar >> 13) & 1;
3706}
3707
89a27f4d 3708static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3709{
89a27f4d
GN		 3710 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3711 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3712}
3713
89a27f4d 3714static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3715{
89a27f4d
GN		 3716 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3717 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3718}
3719
89a27f4d 3720static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3721{
89a27f4d
GN		 3722 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3723 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3724}
3725
89a27f4d 3726static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3727{
89a27f4d
GN		 3728 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3729 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3730}
3731
648dfaa7
MG		 3732static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3733{
3734 struct kvm_segment var;
3735 u32 ar;
3736
3737 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3738 var.dpl = 0x3;
0647f4aa
GN		 3739 if (seg == VCPU_SREG_CS)
3740 var.type = 0x3;
648dfaa7
MG		 3741 ar = vmx_segment_access_rights(&var);
3742
3743 if (var.base != (var.selector << 4))
3744 return false;
89efbed0 3745 if (var.limit != 0xffff)
648dfaa7 3746 return false;
07f42f5f 3747 if (ar != 0xf3)
648dfaa7
MG		 3748 return false;
3749
3750 return true;
3751}
3752
3753static bool code_segment_valid(struct kvm_vcpu *vcpu)
3754{
3755 struct kvm_segment cs;
3756 unsigned int cs_rpl;
3757
3758 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3759 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3760
1872a3f4
AK		 3761 if (cs.unusable)
3762 return false;
648dfaa7
MG		 3763 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3764 return false;
3765 if (!cs.s)
3766 return false;
1872a3f4 3767 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3768 if (cs.dpl > cs_rpl)
3769 return false;
1872a3f4 3770 } else {
648dfaa7
MG		 3771 if (cs.dpl != cs_rpl)
3772 return false;
3773 }
3774 if (!cs.present)
3775 return false;
3776
3777 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3778 return true;
3779}
3780
3781static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3782{
3783 struct kvm_segment ss;
3784 unsigned int ss_rpl;
3785
3786 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3787 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3788
1872a3f4
AK		 3789 if (ss.unusable)
3790 return true;
3791 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3792 return false;
3793 if (!ss.s)
3794 return false;
3795 if (ss.dpl != ss_rpl) /* DPL != RPL */
3796 return false;
3797 if (!ss.present)
3798 return false;
3799
3800 return true;
3801}
3802
3803static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3804{
3805 struct kvm_segment var;
3806 unsigned int rpl;
3807
3808 vmx_get_segment(vcpu, &var, seg);
3809 rpl = var.selector & SELECTOR_RPL_MASK;
3810
1872a3f4
AK		 3811 if (var.unusable)
3812 return true;
648dfaa7
MG		 3813 if (!var.s)
3814 return false;
3815 if (!var.present)
3816 return false;
3817 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3818 if (var.dpl < rpl) /* DPL < RPL */
3819 return false;
3820 }
3821
3822 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3823 * rights flags
3824 */
3825 return true;
3826}
3827
3828static bool tr_valid(struct kvm_vcpu *vcpu)
3829{
3830 struct kvm_segment tr;
3831
3832 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3833
1872a3f4
AK		 3834 if (tr.unusable)
3835 return false;
648dfaa7
MG		 3836 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3837 return false;
1872a3f4 3838 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3839 return false;
3840 if (!tr.present)
3841 return false;
3842
3843 return true;
3844}
3845
3846static bool ldtr_valid(struct kvm_vcpu *vcpu)
3847{
3848 struct kvm_segment ldtr;
3849
3850 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3851
1872a3f4
AK		 3852 if (ldtr.unusable)
3853 return true;
648dfaa7
MG		 3854 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3855 return false;
3856 if (ldtr.type != 2)
3857 return false;
3858 if (!ldtr.present)
3859 return false;
3860
3861 return true;
3862}
3863
3864static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3865{
3866 struct kvm_segment cs, ss;
3867
3868 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3869 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3870
3871 return ((cs.selector & SELECTOR_RPL_MASK) ==
3872 (ss.selector & SELECTOR_RPL_MASK));
3873}
3874
3875/*
3876 * Check if guest state is valid. Returns true if valid, false if
3877 * not.
3878 * We assume that registers are always usable
3879 */
3880static bool guest_state_valid(struct kvm_vcpu *vcpu)
3881{
c5e97c80
GN		 3882 if (enable_unrestricted_guest)
3883 return true;
3884
648dfaa7 3885 /* real mode guest state checks */
f13882d8 3886 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3887 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3888 return false;
3889 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3890 return false;
3891 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3892 return false;
3893 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3894 return false;
3895 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3896 return false;
3897 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3898 return false;
3899 } else {
3900 /* protected mode guest state checks */
3901 if (!cs_ss_rpl_check(vcpu))
3902 return false;
3903 if (!code_segment_valid(vcpu))
3904 return false;
3905 if (!stack_segment_valid(vcpu))
3906 return false;
3907 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3908 return false;
3909 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3910 return false;
3911 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3912 return false;
3913 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3914 return false;
3915 if (!tr_valid(vcpu))
3916 return false;
3917 if (!ldtr_valid(vcpu))
3918 return false;
3919 }
3920 /* TODO:
3921 * - Add checks on RIP
3922 * - Add checks on RFLAGS
3923 */
3924
3925 return true;
3926}
3927
d77c26fc 3928static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3929{
40dcaa9f 3930 gfn_t fn;
195aefde 3931 u16 data = 0;
40dcaa9f 3932 int r, idx, ret = 0;
6aa8b732 3933
40dcaa9f 3934 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3935 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3936 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3937 if (r < 0)
10589a46 3938 goto out;
195aefde 3939 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3940 r = kvm_write_guest_page(kvm, fn++, &data,
3941 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3942 if (r < 0)
10589a46 3943 goto out;
195aefde
IE		 3944 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3945 if (r < 0)
10589a46 3946 goto out;
195aefde
IE		 3947 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3948 if (r < 0)
10589a46 3949 goto out;
195aefde 3950 data = ~0;
10589a46
MT		 3951 r = kvm_write_guest_page(kvm, fn, &data,
3952 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3953 sizeof(u8));
195aefde 3954 if (r < 0)
10589a46
MT		 3955 goto out;
3956
3957 ret = 1;
3958out:
40dcaa9f 3959 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3960 return ret;
6aa8b732
AK		 3961}
3962
b7ebfb05
SY		 3963static int init_rmode_identity_map(struct kvm *kvm)
3964{
40dcaa9f 3965 int i, idx, r, ret;
b7ebfb05
SY		 3966 pfn_t identity_map_pfn;
3967 u32 tmp;
3968
089d034e 3969 if (!enable_ept)
b7ebfb05
SY		 3970 return 1;
3971 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3972 printk(KERN_ERR "EPT: identity-mapping pagetable "
3973 "haven't been allocated!\n");
3974 return 0;
3975 }
3976 if (likely(kvm->arch.ept_identity_pagetable_done))
3977 return 1;
3978 ret = 0;
b927a3ce 3979 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3980 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3981 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3982 if (r < 0)
3983 goto out;
3984 /* Set up identity-mapping pagetable for EPT in real mode */
3985 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3986 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3987 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3988 r = kvm_write_guest_page(kvm, identity_map_pfn,
3989 &tmp, i * sizeof(tmp), sizeof(tmp));
3990 if (r < 0)
3991 goto out;
3992 }
3993 kvm->arch.ept_identity_pagetable_done = true;
3994 ret = 1;
3995out:
40dcaa9f 3996 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3997 return ret;
3998}
3999
6aa8b732
AK		 4000static void seg_setup(int seg)
4001{
772e0318 4002 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4003 unsigned int ar;
6aa8b732
AK		 4004
4005 vmcs_write16(sf->selector, 0);
4006 vmcs_writel(sf->base, 0);
4007 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4008 ar = 0x93;
4009 if (seg == VCPU_SREG_CS)
4010 ar |= 0x08; /* code segment */
3a624e29
NK		 4011
4012 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4013}
4014
f78e0e2e
SY		 4015static int alloc_apic_access_page(struct kvm *kvm)
4016{
4484141a 4017 struct page *page;
f78e0e2e
SY		 4018 struct kvm_userspace_memory_region kvm_userspace_mem;
4019 int r = 0;
4020
79fac95e 4021 mutex_lock(&kvm->slots_lock);
bfc6d222 4022 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 4023 goto out;
4024 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4025 kvm_userspace_mem.flags = 0;
4026 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4027 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4028 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4029 if (r)
4030 goto out;
72dc67a6 4031
4484141a
XG		 4032 page = gfn_to_page(kvm, 0xfee00);
4033 if (is_error_page(page)) {
4034 r = -EFAULT;
4035 goto out;
4036 }
4037
4038 kvm->arch.apic_access_page = page;
f78e0e2e 4039out:
79fac95e 4040 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4041 return r;
4042}
4043
b7ebfb05
SY		 4044static int alloc_identity_pagetable(struct kvm *kvm)
4045{
4484141a 4046 struct page *page;
b7ebfb05
SY		 4047 struct kvm_userspace_memory_region kvm_userspace_mem;
4048 int r = 0;
4049
79fac95e 4050 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 4051 if (kvm->arch.ept_identity_pagetable)
4052 goto out;
4053 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4054 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4055 kvm_userspace_mem.guest_phys_addr =
4056 kvm->arch.ept_identity_map_addr;
b7ebfb05 4057 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4058 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 4059 if (r)
4060 goto out;
4061
4484141a
XG		 4062 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4063 if (is_error_page(page)) {
4064 r = -EFAULT;
4065 goto out;
4066 }
4067
4068 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4069out:
79fac95e 4070 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4071 return r;
4072}
4073
2384d2b3
SY		 4074static void allocate_vpid(struct vcpu_vmx *vmx)
4075{
4076 int vpid;
4077
4078 vmx->vpid = 0;
919818ab 4079 if (!enable_vpid)
2384d2b3
SY		 4080 return;
4081 spin_lock(&vmx_vpid_lock);
4082 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4083 if (vpid < VMX_NR_VPIDS) {
4084 vmx->vpid = vpid;
4085 __set_bit(vpid, vmx_vpid_bitmap);
4086 }
4087 spin_unlock(&vmx_vpid_lock);
4088}
4089
cdbecfc3
LJ		 4090static void free_vpid(struct vcpu_vmx *vmx)
4091{
4092 if (!enable_vpid)
4093 return;
4094 spin_lock(&vmx_vpid_lock);
4095 if (vmx->vpid != 0)
4096 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4097 spin_unlock(&vmx_vpid_lock);
4098}
4099
8d14695f
YZ		 4100#define MSR_TYPE_R 1
4101#define MSR_TYPE_W 2
4102static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4103 u32 msr, int type)
25c5f225 4104{
3e7c73e9 4105 int f = sizeof(unsigned long);
25c5f225
SY		 4106
4107 if (!cpu_has_vmx_msr_bitmap())
4108 return;
4109
4110 /*
4111 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4112 * have the write-low and read-high bitmap offsets the wrong way round.
4113 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4114 */
25c5f225 4115 if (msr <= 0x1fff) {
8d14695f
YZ		 4116 if (type & MSR_TYPE_R)
4117 /* read-low */
4118 __clear_bit(msr, msr_bitmap + 0x000 / f);
4119
4120 if (type & MSR_TYPE_W)
4121 /* write-low */
4122 __clear_bit(msr, msr_bitmap + 0x800 / f);
4123
25c5f225
SY		 4124 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4125 msr &= 0x1fff;
8d14695f
YZ		 4126 if (type & MSR_TYPE_R)
4127 /* read-high */
4128 __clear_bit(msr, msr_bitmap + 0x400 / f);
4129
4130 if (type & MSR_TYPE_W)
4131 /* write-high */
4132 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4133
4134 }
4135}
4136
4137static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4138 u32 msr, int type)
4139{
4140 int f = sizeof(unsigned long);
4141
4142 if (!cpu_has_vmx_msr_bitmap())
4143 return;
4144
4145 /*
4146 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4147 * have the write-low and read-high bitmap offsets the wrong way round.
4148 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4149 */
4150 if (msr <= 0x1fff) {
4151 if (type & MSR_TYPE_R)
4152 /* read-low */
4153 __set_bit(msr, msr_bitmap + 0x000 / f);
4154
4155 if (type & MSR_TYPE_W)
4156 /* write-low */
4157 __set_bit(msr, msr_bitmap + 0x800 / f);
4158
4159 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4160 msr &= 0x1fff;
4161 if (type & MSR_TYPE_R)
4162 /* read-high */
4163 __set_bit(msr, msr_bitmap + 0x400 / f);
4164
4165 if (type & MSR_TYPE_W)
4166 /* write-high */
4167 __set_bit(msr, msr_bitmap + 0xc00 / f);
4168
25c5f225 4169 }
25c5f225
SY		 4170}
4171
5897297b
AK		 4172static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4173{
4174 if (!longmode_only)
8d14695f
YZ		 4175 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4176 msr, MSR_TYPE_R | MSR_TYPE_W);
4177 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4178 msr, MSR_TYPE_R | MSR_TYPE_W);
4179}
4180
4181static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4182{
4183 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4184 msr, MSR_TYPE_R);
4185 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4186 msr, MSR_TYPE_R);
4187}
4188
4189static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4190{
4191 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4192 msr, MSR_TYPE_R);
4193 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4194 msr, MSR_TYPE_R);
4195}
4196
4197static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4198{
4199 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4200 msr, MSR_TYPE_W);
4201 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4202 msr, MSR_TYPE_W);
5897297b
AK		 4203}
4204
01e439be
YZ		 4205static int vmx_vm_has_apicv(struct kvm *kvm)
4206{
4207 return enable_apicv && irqchip_in_kernel(kvm);
4208}
4209
a20ed54d
YZ		 4210/*
4211 * Send interrupt to vcpu via posted interrupt way.
4212 * 1. If target vcpu is running(non-root mode), send posted interrupt
4213 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4214 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4215 * interrupt from PIR in next vmentry.
4216 */
4217static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4218{
4219 struct vcpu_vmx *vmx = to_vmx(vcpu);
4220 int r;
4221
4222 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4223 return;
4224
4225 r = pi_test_and_set_on(&vmx->pi_desc);
4226 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4227#ifdef CONFIG_SMP
a20ed54d
YZ		 4228 if (!r && (vcpu->mode == IN_GUEST_MODE))
4229 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4230 POSTED_INTR_VECTOR);
4231 else
6ffbbbba 4232#endif
a20ed54d
YZ		 4233 kvm_vcpu_kick(vcpu);
4234}
4235
4236static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4237{
4238 struct vcpu_vmx *vmx = to_vmx(vcpu);
4239
4240 if (!pi_test_and_clear_on(&vmx->pi_desc))
4241 return;
4242
4243 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4244}
4245
4246static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4247{
4248 return;
4249}
4250
a3a8ff8e
NHE		 4251/*
4252 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4253 * will not change in the lifetime of the guest.
4254 * Note that host-state that does change is set elsewhere. E.g., host-state
4255 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4256 */
a547c6db 4257static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4258{
4259 u32 low32, high32;
4260 unsigned long tmpl;
4261 struct desc_ptr dt;
4262
b1a74bf8 4263 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4264 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4265 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4266
4267 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4268#ifdef CONFIG_X86_64
4269 /*
4270 * Load null selectors, so we can avoid reloading them in
4271 * __vmx_load_host_state(), in case userspace uses the null selectors
4272 * too (the expected case).
4273 */
4274 vmcs_write16(HOST_DS_SELECTOR, 0);
4275 vmcs_write16(HOST_ES_SELECTOR, 0);
4276#else
a3a8ff8e
NHE		 4277 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4278 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4279#endif
a3a8ff8e
NHE		 4280 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4281 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4282
4283 native_store_idt(&dt);
4284 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4285 vmx->host_idt_base = dt.address;
a3a8ff8e 4286
83287ea4 4287 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4288
4289 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4290 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4291 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4292 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4293
4294 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4295 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4296 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4297 }
4298}
4299
bf8179a0
NHE		 4300static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4301{
4302 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4303 if (enable_ept)
4304 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4305 if (is_guest_mode(&vmx->vcpu))
4306 vmx->vcpu.arch.cr4_guest_owned_bits &=
4307 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4308 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4309}
4310
01e439be
YZ		 4311static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4312{
4313 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4314
4315 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4316 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4317 return pin_based_exec_ctrl;
4318}
4319
bf8179a0
NHE		 4320static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4321{
4322 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4323
4324 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4325 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4326
bf8179a0
NHE		 4327 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4328 exec_control &= ~CPU_BASED_TPR_SHADOW;
4329#ifdef CONFIG_X86_64
4330 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4331 CPU_BASED_CR8_LOAD_EXITING;
4332#endif
4333 }
4334 if (!enable_ept)
4335 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4336 CPU_BASED_CR3_LOAD_EXITING |
4337 CPU_BASED_INVLPG_EXITING;
4338 return exec_control;
4339}
4340
4341static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4342{
4343 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4344 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4345 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4346 if (vmx->vpid == 0)
4347 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4348 if (!enable_ept) {
4349 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4350 enable_unrestricted_guest = 0;
ad756a16
MJ		 4351 /* Enable INVPCID for non-ept guests may cause performance regression. */
4352 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4353 }
4354 if (!enable_unrestricted_guest)
4355 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4356 if (!ple_gap)
4357 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4358 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4359 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4360 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4361 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4362 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4363 (handle_vmptrld).
4364 We can NOT enable shadow_vmcs here because we don't have yet
4365 a current VMCS12
4366 */
4367 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4368 return exec_control;
4369}
4370
ce88decf
XG		 4371static void ept_set_mmio_spte_mask(void)
4372{
4373 /*
4374 * EPT Misconfigurations can be generated if the value of bits 2:0
4375 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4376 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4377 * spte.
4378 */
885032b9 4379 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4380}
4381
6aa8b732
AK		 4382/*
4383 * Sets up the vmcs for emulated real mode.
4384 */
8b9cf98c 4385static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4386{
2e4ce7f5 4387#ifdef CONFIG_X86_64
6aa8b732 4388 unsigned long a;
2e4ce7f5 4389#endif
6aa8b732 4390 int i;
6aa8b732 4391
6aa8b732 4392 /* I/O */
3e7c73e9
AK		 4393 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4394 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4395
4607c2d7
AG		 4396 if (enable_shadow_vmcs) {
4397 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4398 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4399 }
25c5f225 4400 if (cpu_has_vmx_msr_bitmap())
5897297b 4401 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4402
6aa8b732
AK		 4403 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4404
6aa8b732 4405 /* Control */
01e439be 4406 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4407
bf8179a0 4408 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4409
83ff3b9d 4410 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4411 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4412 vmx_secondary_exec_control(vmx));
83ff3b9d 4413 }
f78e0e2e 4414
01e439be 4415 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4416 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4417 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4418 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4419 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4420
4421 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4422
4423 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4424 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4425 }
4426
4b8d54f9
ZE		 4427 if (ple_gap) {
4428 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4429 vmx->ple_window = ple_window;
4430 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4431 }
4432
c3707958
XG		 4433 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4434 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4435 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4436
9581d442
AK		 4437 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4438 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4439 vmx_set_constant_host_state(vmx);
05b3e0c2 4440#ifdef CONFIG_X86_64
6aa8b732
AK		 4441 rdmsrl(MSR_FS_BASE, a);
4442 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4443 rdmsrl(MSR_GS_BASE, a);
4444 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4445#else
4446 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4447 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4448#endif
4449
2cc51560
ED		 4450 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4451 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4452 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4453 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4454 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4455
468d472f 4456 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4457 u32 msr_low, msr_high;
4458 u64 host_pat;
468d472f
SY		 4459 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4460 host_pat = msr_low | ((u64) msr_high << 32);
4461 /* Write the default value follow host pat */
4462 vmcs_write64(GUEST_IA32_PAT, host_pat);
4463 /* Keep arch.pat sync with GUEST_IA32_PAT */
4464 vmx->vcpu.arch.pat = host_pat;
4465 }
4466
03916db9 4467 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4468 u32 index = vmx_msr_index[i];
4469 u32 data_low, data_high;
a2fa3e9f 4470 int j = vmx->nmsrs;
6aa8b732
AK		 4471
4472 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4473 continue;
432bd6cb
AK		 4474 if (wrmsr_safe(index, data_low, data_high) < 0)
4475 continue;
26bb0981
AK		 4476 vmx->guest_msrs[j].index = i;
4477 vmx->guest_msrs[j].data = 0;
d5696725 4478 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4479 ++vmx->nmsrs;
6aa8b732 4480 }
6aa8b732 4481
2961e876
GN		 4482
4483 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4484
4485 /* 22.2.1, 20.8.1 */
2961e876 4486 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4487
e00c8cf2 4488 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4489 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4490
4491 return 0;
4492}
4493
57f252f2 4494static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4495{
4496 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4497 struct msr_data apic_base_msr;
e00c8cf2 4498
7ffd92c5 4499 vmx->rmode.vm86_active = 0;
e00c8cf2 4500
3b86cd99
JK		 4501 vmx->soft_vnmi_blocked = 0;
4502
ad312c7c 4503 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4504 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4505 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4506 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4507 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4508 apic_base_msr.host_initiated = true;
4509 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4510
2fb92db1
AK		 4511 vmx_segment_cache_clear(vmx);
4512
5706be0d 4513 seg_setup(VCPU_SREG_CS);
66450a21 4514 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4515 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4516
4517 seg_setup(VCPU_SREG_DS);
4518 seg_setup(VCPU_SREG_ES);
4519 seg_setup(VCPU_SREG_FS);
4520 seg_setup(VCPU_SREG_GS);
4521 seg_setup(VCPU_SREG_SS);
4522
4523 vmcs_write16(GUEST_TR_SELECTOR, 0);
4524 vmcs_writel(GUEST_TR_BASE, 0);
4525 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4526 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4527
4528 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4529 vmcs_writel(GUEST_LDTR_BASE, 0);
4530 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4531 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4532
4533 vmcs_write32(GUEST_SYSENTER_CS, 0);
4534 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4535 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4536
4537 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4538 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4539
e00c8cf2
AK		 4540 vmcs_writel(GUEST_GDTR_BASE, 0);
4541 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4542
4543 vmcs_writel(GUEST_IDTR_BASE, 0);
4544 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4545
443381a8 4546 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4547 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4548 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4549
e00c8cf2
AK		 4550 /* Special registers */
4551 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4552
4553 setup_msrs(vmx);
4554
6aa8b732
AK		 4555 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4556
f78e0e2e
SY		 4557 if (cpu_has_vmx_tpr_shadow()) {
4558 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4559 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4560 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4561 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4562 vmcs_write32(TPR_THRESHOLD, 0);
4563 }
4564
4565 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4566 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4567 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4568
01e439be
YZ		 4569 if (vmx_vm_has_apicv(vcpu->kvm))
4570 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4571
2384d2b3
SY		 4572 if (vmx->vpid != 0)
4573 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4574
fa40052c 4575 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4576 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4577 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4578 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4579 vmx_fpu_activate(&vmx->vcpu);
4580 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4581
b9d762fa 4582 vpid_sync_context(vmx);
6aa8b732
AK		 4583}
4584
b6f1250e
NHE		 4585/*
4586 * In nested virtualization, check if L1 asked to exit on external interrupts.
4587 * For most existing hypervisors, this will always return true.
4588 */
4589static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4590{
4591 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4592 PIN_BASED_EXT_INTR_MASK;
4593}
4594
77b0f5d6
BD		 4595/*
4596 * In nested virtualization, check if L1 has set
4597 * VM_EXIT_ACK_INTR_ON_EXIT
4598 */
4599static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4600{
4601 return get_vmcs12(vcpu)->vm_exit_controls &
4602 VM_EXIT_ACK_INTR_ON_EXIT;
4603}
4604
ea8ceb83
JK		 4605static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4606{
4607 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4608 PIN_BASED_NMI_EXITING;
4609}
4610
c9a7953f 4611static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4612{
4613 u32 cpu_based_vm_exec_control;
730dca42 4614
3b86cd99
JK		 4615 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4616 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4617 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4618}
4619
c9a7953f 4620static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4621{
4622 u32 cpu_based_vm_exec_control;
4623
c9a7953f
JK		 4624 if (!cpu_has_virtual_nmis() ||
4625 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4626 enable_irq_window(vcpu);
4627 return;
4628 }
3b86cd99
JK		 4629
4630 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4631 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4632 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4633}
4634
66fd3f7f 4635static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4636{
9c8cba37 4637 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4638 uint32_t intr;
4639 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4640
229456fc 4641 trace_kvm_inj_virq(irq);
2714d1d3 4642
fa89a817 4643 ++vcpu->stat.irq_injections;
7ffd92c5 4644 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4645 int inc_eip = 0;
4646 if (vcpu->arch.interrupt.soft)
4647 inc_eip = vcpu->arch.event_exit_inst_len;
4648 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4649 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4650 return;
4651 }
66fd3f7f
GN		 4652 intr = irq | INTR_INFO_VALID_MASK;
4653 if (vcpu->arch.interrupt.soft) {
4654 intr |= INTR_TYPE_SOFT_INTR;
4655 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4656 vmx->vcpu.arch.event_exit_inst_len);
4657 } else
4658 intr |= INTR_TYPE_EXT_INTR;
4659 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4660}
4661
f08864b4
SY		 4662static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4663{
66a5a347
JK		 4664 struct vcpu_vmx *vmx = to_vmx(vcpu);
4665
0b6ac343
NHE		 4666 if (is_guest_mode(vcpu))
4667 return;
4668
3b86cd99
JK		 4669 if (!cpu_has_virtual_nmis()) {
4670 /*
4671 * Tracking the NMI-blocked state in software is built upon
4672 * finding the next open IRQ window. This, in turn, depends on
4673 * well-behaving guests: They have to keep IRQs disabled at
4674 * least as long as the NMI handler runs. Otherwise we may
4675 * cause NMI nesting, maybe breaking the guest. But as this is
4676 * highly unlikely, we can live with the residual risk.
4677 */
4678 vmx->soft_vnmi_blocked = 1;
4679 vmx->vnmi_blocked_time = 0;
4680 }
4681
487b391d 4682 ++vcpu->stat.nmi_injections;
9d58b931 4683 vmx->nmi_known_unmasked = false;
7ffd92c5 4684 if (vmx->rmode.vm86_active) {
71f9833b 4685 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4686 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4687 return;
4688 }
f08864b4
SY		 4689 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4690 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4691}
4692
3cfc3092
JK		 4693static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4694{
4695 if (!cpu_has_virtual_nmis())
4696 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4697 if (to_vmx(vcpu)->nmi_known_unmasked)
4698 return false;
c332c83a 4699 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4700}
4701
4702static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4703{
4704 struct vcpu_vmx *vmx = to_vmx(vcpu);
4705
4706 if (!cpu_has_virtual_nmis()) {
4707 if (vmx->soft_vnmi_blocked != masked) {
4708 vmx->soft_vnmi_blocked = masked;
4709 vmx->vnmi_blocked_time = 0;
4710 }
4711 } else {
9d58b931 4712 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4713 if (masked)
4714 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4715 GUEST_INTR_STATE_NMI);
4716 else
4717 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4718 GUEST_INTR_STATE_NMI);
4719 }
4720}
4721
2505dc9f
JK		 4722static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4723{
b6b8a145
JK		 4724 if (to_vmx(vcpu)->nested.nested_run_pending)
4725 return 0;
ea8ceb83 4726
2505dc9f
JK		 4727 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4728 return 0;
4729
4730 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4731 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4732 | GUEST_INTR_STATE_NMI));
4733}
4734
78646121
GN		 4735static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4736{
b6b8a145
JK		 4737 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4738 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4739 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4740 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4741}
4742
cbc94022
IE		 4743static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4744{
4745 int ret;
4746 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4747 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4748 .guest_phys_addr = addr,
4749 .memory_size = PAGE_SIZE * 3,
4750 .flags = 0,
4751 };
4752
47ae31e2 4753 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4754 if (ret)
4755 return ret;
bfc6d222 4756 kvm->arch.tss_addr = addr;
93ea5388
GN		 4757 if (!init_rmode_tss(kvm))
4758 return -ENOMEM;
4759
cbc94022
IE		 4760 return 0;
4761}
4762
0ca1b4f4 4763static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4764{
77ab6db0 4765 switch (vec) {
77ab6db0 4766 case BP_VECTOR:
c573cd22
JK		 4767 /*
4768 * Update instruction length as we may reinject the exception
4769 * from user space while in guest debugging mode.
4770 */
4771 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4772 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4773 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4774 return false;
4775 /* fall through */
4776 case DB_VECTOR:
4777 if (vcpu->guest_debug &
4778 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4779 return false;
d0bfb940
JK		 4780 /* fall through */
4781 case DE_VECTOR:
77ab6db0
JK		 4782 case OF_VECTOR:
4783 case BR_VECTOR:
4784 case UD_VECTOR:
4785 case DF_VECTOR:
4786 case SS_VECTOR:
4787 case GP_VECTOR:
4788 case MF_VECTOR:
0ca1b4f4
GN		 4789 return true;
4790 break;
77ab6db0 4791 }
0ca1b4f4
GN		 4792 return false;
4793}
4794
4795static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4796 int vec, u32 err_code)
4797{
4798 /*
4799 * Instruction with address size override prefix opcode 0x67
4800 * Cause the #SS fault with 0 error code in VM86 mode.
4801 */
4802 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4803 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4804 if (vcpu->arch.halt_request) {
4805 vcpu->arch.halt_request = 0;
4806 return kvm_emulate_halt(vcpu);
4807 }
4808 return 1;
4809 }
4810 return 0;
4811 }
4812
4813 /*
4814 * Forward all other exceptions that are valid in real mode.
4815 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4816 * the required debugging infrastructure rework.
4817 */
4818 kvm_queue_exception(vcpu, vec);
4819 return 1;
6aa8b732
AK		 4820}
4821
a0861c02
AK		 4822/*
4823 * Trigger machine check on the host. We assume all the MSRs are already set up
4824 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4825 * We pass a fake environment to the machine check handler because we want
4826 * the guest to be always treated like user space, no matter what context
4827 * it used internally.
4828 */
4829static void kvm_machine_check(void)
4830{
4831#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4832 struct pt_regs regs = {
4833 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4834 .flags = X86_EFLAGS_IF,
4835 };
4836
4837 do_machine_check(&regs, 0);
4838#endif
4839}
4840
851ba692 4841static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4842{
4843 /* already handled by vcpu_run */
4844 return 1;
4845}
4846
851ba692 4847static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4848{
1155f76a 4849 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4850 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4851 u32 intr_info, ex_no, error_code;
42dbaa5a 4852 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4853 u32 vect_info;
4854 enum emulation_result er;
4855
1155f76a 4856 vect_info = vmx->idt_vectoring_info;
88786475 4857 intr_info = vmx->exit_intr_info;
6aa8b732 4858
a0861c02 4859 if (is_machine_check(intr_info))
851ba692 4860 return handle_machine_check(vcpu);
a0861c02 4861
e4a41889 4862 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4863 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4864
4865 if (is_no_device(intr_info)) {
5fd86fcf 4866 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4867 return 1;
4868 }
4869
7aa81cc0 4870 if (is_invalid_opcode(intr_info)) {
51d8b661 4871 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4872 if (er != EMULATE_DONE)
7ee5d940 4873 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4874 return 1;
4875 }
4876
6aa8b732 4877 error_code = 0;
2e11384c 4878 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4879 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4880
4881 /*
4882 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4883 * MMIO, it is better to report an internal error.
4884 * See the comments in vmx_handle_exit.
4885 */
4886 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4887 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4888 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4889 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4890 vcpu->run->internal.ndata = 2;
4891 vcpu->run->internal.data[0] = vect_info;
4892 vcpu->run->internal.data[1] = intr_info;
4893 return 0;
4894 }
4895
6aa8b732 4896 if (is_page_fault(intr_info)) {
1439442c 4897 /* EPT won't cause page fault directly */
cf3ace79 4898 BUG_ON(enable_ept);
6aa8b732 4899 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4900 trace_kvm_page_fault(cr2, error_code);
4901
3298b75c 4902 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4903 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4904 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4905 }
4906
d0bfb940 4907 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4908
4909 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4910 return handle_rmode_exception(vcpu, ex_no, error_code);
4911
42dbaa5a
JK		 4912 switch (ex_no) {
4913 case DB_VECTOR:
4914 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4915 if (!(vcpu->guest_debug &
4916 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4917 vcpu->arch.dr6 &= ~15;
6f43ed01 4918 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4919 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4920 skip_emulated_instruction(vcpu);
4921
42dbaa5a
JK		 4922 kvm_queue_exception(vcpu, DB_VECTOR);
4923 return 1;
4924 }
4925 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4926 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4927 /* fall through */
4928 case BP_VECTOR:
c573cd22
JK		 4929 /*
4930 * Update instruction length as we may reinject #BP from
4931 * user space while in guest debugging mode. Reading it for
4932 * #DB as well causes no harm, it is not used in that case.
4933 */
4934 vmx->vcpu.arch.event_exit_inst_len =
4935 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4936 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4937 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4938 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4939 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4940 break;
4941 default:
d0bfb940
JK		 4942 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4943 kvm_run->ex.exception = ex_no;
4944 kvm_run->ex.error_code = error_code;
42dbaa5a 4945 break;
6aa8b732 4946 }
6aa8b732
AK		 4947 return 0;
4948}
4949
851ba692 4950static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4951{
1165f5fe 4952 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4953 return 1;
4954}
4955
851ba692 4956static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4957{
851ba692 4958 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4959 return 0;
4960}
6aa8b732 4961
851ba692 4962static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4963{
bfdaab09 4964 unsigned long exit_qualification;
34c33d16 4965 int size, in, string;
039576c0 4966 unsigned port;
6aa8b732 4967
bfdaab09 4968 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4969 string = (exit_qualification & 16) != 0;
cf8f70bf 4970 in = (exit_qualification & 8) != 0;
e70669ab 4971
cf8f70bf 4972 ++vcpu->stat.io_exits;
e70669ab 4973
cf8f70bf 4974 if (string || in)
51d8b661 4975 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4976
cf8f70bf
GN		 4977 port = exit_qualification >> 16;
4978 size = (exit_qualification & 7) + 1;
e93f36bc 4979 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4980
4981 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4982}
4983
102d8325
IM		 4984static void
4985vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4986{
4987 /*
4988 * Patch in the VMCALL instruction:
4989 */
4990 hypercall[0] = 0x0f;
4991 hypercall[1] = 0x01;
4992 hypercall[2] = 0xc1;
102d8325
IM		 4993}
4994
92fbc7b1
JK		 4995static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4996{
4997 unsigned long always_on = VMXON_CR0_ALWAYSON;
4998
4999 if (nested_vmx_secondary_ctls_high &
5000 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5001 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5002 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5003 return (val & always_on) == always_on;
5004}
5005
0fa06071 5006/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5007static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5008{
eeadf9e7 5009 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5010 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5011 unsigned long orig_val = val;
5012
eeadf9e7
NHE		 5013 /*
5014 * We get here when L2 changed cr0 in a way that did not change
5015 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5016 * but did change L0 shadowed bits. So we first calculate the
5017 * effective cr0 value that L1 would like to write into the
5018 * hardware. It consists of the L2-owned bits from the new
5019 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5020 */
1a0d74e6
JK		 5021 val = (val & ~vmcs12->cr0_guest_host_mask) |
5022 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5023
92fbc7b1 5024 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5025 return 1;
1a0d74e6
JK		 5026
5027 if (kvm_set_cr0(vcpu, val))
5028 return 1;
5029 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5030 return 0;
1a0d74e6
JK		 5031 } else {
5032 if (to_vmx(vcpu)->nested.vmxon &&
5033 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5034 return 1;
eeadf9e7 5035 return kvm_set_cr0(vcpu, val);
1a0d74e6 5036 }
eeadf9e7
NHE		 5037}
5038
5039static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5040{
5041 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5042 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5043 unsigned long orig_val = val;
5044
5045 /* analogously to handle_set_cr0 */
5046 val = (val & ~vmcs12->cr4_guest_host_mask) |
5047 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5048 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5049 return 1;
1a0d74e6 5050 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5051 return 0;
5052 } else
5053 return kvm_set_cr4(vcpu, val);
5054}
5055
5056/* called to set cr0 as approriate for clts instruction exit. */
5057static void handle_clts(struct kvm_vcpu *vcpu)
5058{
5059 if (is_guest_mode(vcpu)) {
5060 /*
5061 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5062 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5063 * just pretend it's off (also in arch.cr0 for fpu_activate).
5064 */
5065 vmcs_writel(CR0_READ_SHADOW,
5066 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5067 vcpu->arch.cr0 &= ~X86_CR0_TS;
5068 } else
5069 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5070}
5071
851ba692 5072static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5073{
229456fc 5074 unsigned long exit_qualification, val;
6aa8b732
AK		 5075 int cr;
5076 int reg;
49a9b07e 5077 int err;
6aa8b732 5078
bfdaab09 5079 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5080 cr = exit_qualification & 15;
5081 reg = (exit_qualification >> 8) & 15;
5082 switch ((exit_qualification >> 4) & 3) {
5083 case 0: /* mov to cr */
1e32c079 5084 val = kvm_register_readl(vcpu, reg);
229456fc 5085 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5086 switch (cr) {
5087 case 0:
eeadf9e7 5088 err = handle_set_cr0(vcpu, val);
db8fcefa 5089 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5090 return 1;
5091 case 3:
2390218b 5092 err = kvm_set_cr3(vcpu, val);
db8fcefa 5093 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5094 return 1;
5095 case 4:
eeadf9e7 5096 err = handle_set_cr4(vcpu, val);
db8fcefa 5097 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5098 return 1;
0a5fff19
GN		 5099 case 8: {
5100 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5101 u8 cr8 = (u8)val;
eea1cff9 5102 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5103 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5104 if (irqchip_in_kernel(vcpu->kvm))
5105 return 1;
5106 if (cr8_prev <= cr8)
5107 return 1;
851ba692 5108 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5109 return 0;
5110 }
4b8073e4 5111 }
6aa8b732 5112 break;
25c4c276 5113 case 2: /* clts */
eeadf9e7 5114 handle_clts(vcpu);
4d4ec087 5115 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5116 skip_emulated_instruction(vcpu);
6b52d186 5117 vmx_fpu_activate(vcpu);
25c4c276 5118 return 1;
6aa8b732
AK		 5119 case 1: /*mov from cr*/
5120 switch (cr) {
5121 case 3:
9f8fe504
AK		 5122 val = kvm_read_cr3(vcpu);
5123 kvm_register_write(vcpu, reg, val);
5124 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5125 skip_emulated_instruction(vcpu);
5126 return 1;
5127 case 8:
229456fc
MT		 5128 val = kvm_get_cr8(vcpu);
5129 kvm_register_write(vcpu, reg, val);
5130 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5131 skip_emulated_instruction(vcpu);
5132 return 1;
5133 }
5134 break;
5135 case 3: /* lmsw */
a1f83a74 5136 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5137 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5138 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5139
5140 skip_emulated_instruction(vcpu);
5141 return 1;
5142 default:
5143 break;
5144 }
851ba692 5145 vcpu->run->exit_reason = 0;
a737f256 5146 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5147 (int)(exit_qualification >> 4) & 3, cr);
5148 return 0;
5149}
5150
851ba692 5151static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5152{
bfdaab09 5153 unsigned long exit_qualification;
6aa8b732
AK		 5154 int dr, reg;
5155
f2483415 5156 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5157 if (!kvm_require_cpl(vcpu, 0))
5158 return 1;
42dbaa5a
JK		 5159 dr = vmcs_readl(GUEST_DR7);
5160 if (dr & DR7_GD) {
5161 /*
5162 * As the vm-exit takes precedence over the debug trap, we
5163 * need to emulate the latter, either for the host or the
5164 * guest debugging itself.
5165 */
5166 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5167 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5168 vcpu->run->debug.arch.dr7 = dr;
5169 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5170 vmcs_readl(GUEST_CS_BASE) +
5171 vmcs_readl(GUEST_RIP);
851ba692
AK		 5172 vcpu->run->debug.arch.exception = DB_VECTOR;
5173 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5174 return 0;
5175 } else {
5176 vcpu->arch.dr7 &= ~DR7_GD;
6f43ed01 5177 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5178 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5179 kvm_queue_exception(vcpu, DB_VECTOR);
5180 return 1;
5181 }
5182 }
5183
81908bf4
PB		 5184 if (vcpu->guest_debug == 0) {
5185 u32 cpu_based_vm_exec_control;
5186
5187 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5188 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5189 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5190
5191 /*
5192 * No more DR vmexits; force a reload of the debug registers
5193 * and reenter on this instruction. The next vmexit will
5194 * retrieve the full state of the debug registers.
5195 */
5196 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5197 return 1;
5198 }
5199
bfdaab09 5200 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5201 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5202 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5203 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5204 unsigned long val;
4c4d563b
JK		 5205
5206 if (kvm_get_dr(vcpu, dr, &val))
5207 return 1;
5208 kvm_register_write(vcpu, reg, val);
020df079 5209 } else
5777392e 5210 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5211 return 1;
5212
6aa8b732
AK		 5213 skip_emulated_instruction(vcpu);
5214 return 1;
5215}
5216
73aaf249
JK		 5217static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5218{
5219 return vcpu->arch.dr6;
5220}
5221
5222static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5223{
5224}
5225
81908bf4
PB		 5226static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5227{
5228 u32 cpu_based_vm_exec_control;
5229
5230 get_debugreg(vcpu->arch.db[0], 0);
5231 get_debugreg(vcpu->arch.db[1], 1);
5232 get_debugreg(vcpu->arch.db[2], 2);
5233 get_debugreg(vcpu->arch.db[3], 3);
5234 get_debugreg(vcpu->arch.dr6, 6);
5235 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5236
5237 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5238
5239 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5240 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5241 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5242}
5243
020df079
GN		 5244static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5245{
5246 vmcs_writel(GUEST_DR7, val);
5247}
5248
851ba692 5249static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5250{
06465c5a
AK		 5251 kvm_emulate_cpuid(vcpu);
5252 return 1;
6aa8b732
AK		 5253}
5254
851ba692 5255static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5256{
ad312c7c 5257 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5258 u64 data;
5259
5260 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5261 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5262 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5263 return 1;
5264 }
5265
229456fc 5266 trace_kvm_msr_read(ecx, data);
2714d1d3 5267
6aa8b732 5268 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5269 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5270 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5271 skip_emulated_instruction(vcpu);
5272 return 1;
5273}
5274
851ba692 5275static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5276{
8fe8ab46 5277 struct msr_data msr;
ad312c7c
ZX		 5278 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5279 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5280 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5281
8fe8ab46
WA		 5282 msr.data = data;
5283 msr.index = ecx;
5284 msr.host_initiated = false;
5285 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5286 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5287 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5288 return 1;
5289 }
5290
59200273 5291 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5292 skip_emulated_instruction(vcpu);
5293 return 1;
5294}
5295
851ba692 5296static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5297{
3842d135 5298 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5299 return 1;
5300}
5301
851ba692 5302static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5303{
85f455f7
ED		 5304 u32 cpu_based_vm_exec_control;
5305
5306 /* clear pending irq */
5307 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5308 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5309 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5310
3842d135
AK		 5311 kvm_make_request(KVM_REQ_EVENT, vcpu);
5312
a26bf12a 5313 ++vcpu->stat.irq_window_exits;
2714d1d3 5314
c1150d8c
DL		 5315 /*
5316 * If the user space waits to inject interrupts, exit as soon as
5317 * possible
5318 */
8061823a 5319 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5320 vcpu->run->request_interrupt_window &&
8061823a 5321 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5322 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5323 return 0;
5324 }
6aa8b732
AK		 5325 return 1;
5326}
5327
851ba692 5328static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5329{
5330 skip_emulated_instruction(vcpu);
d3bef15f 5331 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5332}
5333
851ba692 5334static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5335{
510043da 5336 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5337 kvm_emulate_hypercall(vcpu);
5338 return 1;
c21415e8
IM		 5339}
5340
ec25d5e6
GN		 5341static int handle_invd(struct kvm_vcpu *vcpu)
5342{
51d8b661 5343 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5344}
5345
851ba692 5346static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5347{
f9c617f6 5348 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5349
5350 kvm_mmu_invlpg(vcpu, exit_qualification);
5351 skip_emulated_instruction(vcpu);
5352 return 1;
5353}
5354
fee84b07
AK		 5355static int handle_rdpmc(struct kvm_vcpu *vcpu)
5356{
5357 int err;
5358
5359 err = kvm_rdpmc(vcpu);
5360 kvm_complete_insn_gp(vcpu, err);
5361
5362 return 1;
5363}
5364
851ba692 5365static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5366{
5367 skip_emulated_instruction(vcpu);
f5f48ee1 5368 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5369 return 1;
5370}
5371
2acf923e
DC		 5372static int handle_xsetbv(struct kvm_vcpu *vcpu)
5373{
5374 u64 new_bv = kvm_read_edx_eax(vcpu);
5375 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5376
5377 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5378 skip_emulated_instruction(vcpu);
5379 return 1;
5380}
5381
851ba692 5382static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5383{
58fbbf26
KT		 5384 if (likely(fasteoi)) {
5385 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5386 int access_type, offset;
5387
5388 access_type = exit_qualification & APIC_ACCESS_TYPE;
5389 offset = exit_qualification & APIC_ACCESS_OFFSET;
5390 /*
5391 * Sane guest uses MOV to write EOI, with written value
5392 * not cared. So make a short-circuit here by avoiding
5393 * heavy instruction emulation.
5394 */
5395 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5396 (offset == APIC_EOI)) {
5397 kvm_lapic_set_eoi(vcpu);
5398 skip_emulated_instruction(vcpu);
5399 return 1;
5400 }
5401 }
51d8b661 5402 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5403}
5404
c7c9c56c
YZ		 5405static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5406{
5407 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5408 int vector = exit_qualification & 0xff;
5409
5410 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5411 kvm_apic_set_eoi_accelerated(vcpu, vector);
5412 return 1;
5413}
5414
83d4c286
YZ		 5415static int handle_apic_write(struct kvm_vcpu *vcpu)
5416{
5417 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5418 u32 offset = exit_qualification & 0xfff;
5419
5420 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5421 kvm_apic_write_nodecode(vcpu, offset);
5422 return 1;
5423}
5424
851ba692 5425static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5426{
60637aac 5427 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5428 unsigned long exit_qualification;
e269fb21
JK		 5429 bool has_error_code = false;
5430 u32 error_code = 0;
37817f29 5431 u16 tss_selector;
7f3d35fd 5432 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5433
5434 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5435 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5436 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5437
5438 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5439
5440 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5441 if (reason == TASK_SWITCH_GATE && idt_v) {
5442 switch (type) {
5443 case INTR_TYPE_NMI_INTR:
5444 vcpu->arch.nmi_injected = false;
654f06fc 5445 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5446 break;
5447 case INTR_TYPE_EXT_INTR:
66fd3f7f 5448 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5449 kvm_clear_interrupt_queue(vcpu);
5450 break;
5451 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5452 if (vmx->idt_vectoring_info &
5453 VECTORING_INFO_DELIVER_CODE_MASK) {
5454 has_error_code = true;
5455 error_code =
5456 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5457 }
5458 /* fall through */
64a7ec06
GN		 5459 case INTR_TYPE_SOFT_EXCEPTION:
5460 kvm_clear_exception_queue(vcpu);
5461 break;
5462 default:
5463 break;
5464 }
60637aac 5465 }
37817f29
IE		 5466 tss_selector = exit_qualification;
5467
64a7ec06
GN		 5468 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5469 type != INTR_TYPE_EXT_INTR &&
5470 type != INTR_TYPE_NMI_INTR))
5471 skip_emulated_instruction(vcpu);
5472
7f3d35fd
KW		 5473 if (kvm_task_switch(vcpu, tss_selector,
5474 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5475 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5476 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5477 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5478 vcpu->run->internal.ndata = 0;
42dbaa5a 5479 return 0;
acb54517 5480 }
42dbaa5a
JK		 5481
5482 /* clear all local breakpoint enable flags */
1f854112 5483 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5484
5485 /*
5486 * TODO: What about debug traps on tss switch?
5487 * Are we supposed to inject them and update dr6?
5488 */
5489
5490 return 1;
37817f29
IE		 5491}
5492
851ba692 5493static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5494{
f9c617f6 5495 unsigned long exit_qualification;
1439442c 5496 gpa_t gpa;
4f5982a5 5497 u32 error_code;
1439442c 5498 int gla_validity;
1439442c 5499
f9c617f6 5500 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5501
1439442c
SY		 5502 gla_validity = (exit_qualification >> 7) & 0x3;
5503 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5504 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5505 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5506 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5507 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5508 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5509 (long unsigned int)exit_qualification);
851ba692
AK		 5510 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5511 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5512 return 0;
1439442c
SY		 5513 }
5514
0be9c7a8
GN		 5515 /*
5516 * EPT violation happened while executing iret from NMI,
5517 * "blocked by NMI" bit has to be set before next VM entry.
5518 * There are errata that may cause this bit to not be set:
5519 * AAK134, BY25.
5520 */
bcd1c294
GN		 5521 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5522 cpu_has_virtual_nmis() &&
5523 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5524 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5525
1439442c 5526 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5527 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5528
5529 /* It is a write fault? */
5530 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5531 /* It is a fetch fault? */
5532 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5533 /* ept page table is present? */
5534 error_code |= (exit_qualification >> 3) & 0x1;
5535
25d92081
YZ		 5536 vcpu->arch.exit_qualification = exit_qualification;
5537
4f5982a5 5538 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5539}
5540
68f89400
MT		 5541static u64 ept_rsvd_mask(u64 spte, int level)
5542{
5543 int i;
5544 u64 mask = 0;
5545
5546 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5547 mask |= (1ULL << i);
5548
a32e8459 5549 if (level == 4)
68f89400
MT		 5550 /* bits 7:3 reserved */
5551 mask |= 0xf8;
a32e8459
WL		 5552 else if (spte & (1ULL << 7))
5553 /*
5554 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5555 * level == 1 if the hypervisor is using the ignored bit 7.
5556 */
5557 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5558 else if (level > 1)
5559 /* bits 6:3 reserved */
5560 mask |= 0x78;
68f89400
MT		 5561
5562 return mask;
5563}
5564
5565static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5566 int level)
5567{
5568 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5569
5570 /* 010b (write-only) */
5571 WARN_ON((spte & 0x7) == 0x2);
5572
5573 /* 110b (write/execute) */
5574 WARN_ON((spte & 0x7) == 0x6);
5575
5576 /* 100b (execute-only) and value not supported by logical processor */
5577 if (!cpu_has_vmx_ept_execute_only())
5578 WARN_ON((spte & 0x7) == 0x4);
5579
5580 /* not 000b */
5581 if ((spte & 0x7)) {
5582 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5583
5584 if (rsvd_bits != 0) {
5585 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5586 __func__, rsvd_bits);
5587 WARN_ON(1);
5588 }
5589
a32e8459
WL		 5590 /* bits 5:3 are _not_ reserved for large page or leaf page */
5591 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5592 u64 ept_mem_type = (spte & 0x38) >> 3;
5593
5594 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5595 ept_mem_type == 7) {
5596 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5597 __func__, ept_mem_type);
5598 WARN_ON(1);
5599 }
5600 }
5601 }
5602}
5603
851ba692 5604static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5605{
5606 u64 sptes[4];
ce88decf 5607 int nr_sptes, i, ret;
68f89400
MT		 5608 gpa_t gpa;
5609
5610 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5611 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5612 skip_emulated_instruction(vcpu);
5613 return 1;
5614 }
68f89400 5615
ce88decf 5616 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5617 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5618 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5619 EMULATE_DONE;
f8f55942
XG		 5620
5621 if (unlikely(ret == RET_MMIO_PF_INVALID))
5622 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5623
b37fbea6 5624 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5625 return 1;
5626
5627 /* It is the real ept misconfig */
68f89400
MT		 5628 printk(KERN_ERR "EPT: Misconfiguration.\n");
5629 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5630
5631 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5632
5633 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5634 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5635
851ba692
AK		 5636 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5637 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5638
5639 return 0;
5640}
5641
851ba692 5642static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5643{
5644 u32 cpu_based_vm_exec_control;
5645
5646 /* clear pending NMI */
5647 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5648 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5649 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5650 ++vcpu->stat.nmi_window_exits;
3842d135 5651 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5652
5653 return 1;
5654}
5655
80ced186 5656static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5657{
8b3079a5
AK		 5658 struct vcpu_vmx *vmx = to_vmx(vcpu);
5659 enum emulation_result err = EMULATE_DONE;
80ced186 5660 int ret = 1;
49e9d557
AK		 5661 u32 cpu_exec_ctrl;
5662 bool intr_window_requested;
b8405c18 5663 unsigned count = 130;
49e9d557
AK		 5664
5665 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5666 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5667
98eb2f8b 5668 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5669 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5670 return handle_interrupt_window(&vmx->vcpu);
5671
de87dcdd
AK		 5672 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5673 return 1;
5674
991eebf9 5675 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5676
ac0a48c3 5677 if (err == EMULATE_USER_EXIT) {
94452b9e 5678 ++vcpu->stat.mmio_exits;
80ced186
MG		 5679 ret = 0;
5680 goto out;
5681 }
1d5a4d9b 5682
de5f70e0
AK		 5683 if (err != EMULATE_DONE) {
5684 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5685 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5686 vcpu->run->internal.ndata = 0;
6d77dbfc 5687 return 0;
de5f70e0 5688 }
ea953ef0 5689
8d76c49e
GN		 5690 if (vcpu->arch.halt_request) {
5691 vcpu->arch.halt_request = 0;
5692 ret = kvm_emulate_halt(vcpu);
5693 goto out;
5694 }
5695
ea953ef0 5696 if (signal_pending(current))
80ced186 5697 goto out;
ea953ef0
MG		 5698 if (need_resched())
5699 schedule();
5700 }
5701
80ced186
MG		 5702out:
5703 return ret;
ea953ef0
MG		 5704}
5705
b4a2d31d
RK		 5706static int __grow_ple_window(int val)
5707{
5708 if (ple_window_grow < 1)
5709 return ple_window;
5710
5711 val = min(val, ple_window_actual_max);
5712
5713 if (ple_window_grow < ple_window)
5714 val *= ple_window_grow;
5715 else
5716 val += ple_window_grow;
5717
5718 return val;
5719}
5720
5721static int __shrink_ple_window(int val, int modifier, int minimum)
5722{
5723 if (modifier < 1)
5724 return ple_window;
5725
5726 if (modifier < ple_window)
5727 val /= modifier;
5728 else
5729 val -= modifier;
5730
5731 return max(val, minimum);
5732}
5733
5734static void grow_ple_window(struct kvm_vcpu *vcpu)
5735{
5736 struct vcpu_vmx *vmx = to_vmx(vcpu);
5737 int old = vmx->ple_window;
5738
5739 vmx->ple_window = __grow_ple_window(old);
5740
5741 if (vmx->ple_window != old)
5742 vmx->ple_window_dirty = true;
7b46268d
RK		 5743
5744 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5745}
5746
5747static void shrink_ple_window(struct kvm_vcpu *vcpu)
5748{
5749 struct vcpu_vmx *vmx = to_vmx(vcpu);
5750 int old = vmx->ple_window;
5751
5752 vmx->ple_window = __shrink_ple_window(old,
5753 ple_window_shrink, ple_window);
5754
5755 if (vmx->ple_window != old)
5756 vmx->ple_window_dirty = true;
7b46268d
RK		 5757
5758 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5759}
5760
5761/*
5762 * ple_window_actual_max is computed to be one grow_ple_window() below
5763 * ple_window_max. (See __grow_ple_window for the reason.)
5764 * This prevents overflows, because ple_window_max is int.
5765 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5766 * this process.
5767 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5768 */
5769static void update_ple_window_actual_max(void)
5770{
5771 ple_window_actual_max =
5772 __shrink_ple_window(max(ple_window_max, ple_window),
5773 ple_window_grow, INT_MIN);
5774}
5775
4b8d54f9
ZE		 5776/*
5777 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5778 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5779 */
9fb41ba8 5780static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5781{
b4a2d31d
RK		 5782 if (ple_gap)
5783 grow_ple_window(vcpu);
5784
4b8d54f9
ZE		 5785 skip_emulated_instruction(vcpu);
5786 kvm_vcpu_on_spin(vcpu);
5787
5788 return 1;
5789}
5790
87c00572 5791static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5792{
87c00572 5793 skip_emulated_instruction(vcpu);
59708670
SY		 5794 return 1;
5795}
5796
87c00572
GS		 5797static int handle_mwait(struct kvm_vcpu *vcpu)
5798{
5799 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5800 return handle_nop(vcpu);
5801}
5802
5803static int handle_monitor(struct kvm_vcpu *vcpu)
5804{
5805 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5806 return handle_nop(vcpu);
5807}
5808
ff2f6fe9
NHE		 5809/*
5810 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5811 * We could reuse a single VMCS for all the L2 guests, but we also want the
5812 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5813 * allows keeping them loaded on the processor, and in the future will allow
5814 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5815 * every entry if they never change.
5816 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5817 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5818 *
5819 * The following functions allocate and free a vmcs02 in this pool.
5820 */
5821
5822/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5823static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5824{
5825 struct vmcs02_list *item;
5826 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5827 if (item->vmptr == vmx->nested.current_vmptr) {
5828 list_move(&item->list, &vmx->nested.vmcs02_pool);
5829 return &item->vmcs02;
5830 }
5831
5832 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5833 /* Recycle the least recently used VMCS. */
5834 item = list_entry(vmx->nested.vmcs02_pool.prev,
5835 struct vmcs02_list, list);
5836 item->vmptr = vmx->nested.current_vmptr;
5837 list_move(&item->list, &vmx->nested.vmcs02_pool);
5838 return &item->vmcs02;
5839 }
5840
5841 /* Create a new VMCS */
0fa24ce3 5842 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5843 if (!item)
5844 return NULL;
5845 item->vmcs02.vmcs = alloc_vmcs();
5846 if (!item->vmcs02.vmcs) {
5847 kfree(item);
5848 return NULL;
5849 }
5850 loaded_vmcs_init(&item->vmcs02);
5851 item->vmptr = vmx->nested.current_vmptr;
5852 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5853 vmx->nested.vmcs02_num++;
5854 return &item->vmcs02;
5855}
5856
5857/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5858static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5859{
5860 struct vmcs02_list *item;
5861 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5862 if (item->vmptr == vmptr) {
5863 free_loaded_vmcs(&item->vmcs02);
5864 list_del(&item->list);
5865 kfree(item);
5866 vmx->nested.vmcs02_num--;
5867 return;
5868 }
5869}
5870
5871/*
5872 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 5873 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5874 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 5875 */
5876static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5877{
5878 struct vmcs02_list *item, *n;
4fa7734c
PB		 5879
5880 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 5881 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 5882 /*
5883 * Something will leak if the above WARN triggers. Better than
5884 * a use-after-free.
5885 */
5886 if (vmx->loaded_vmcs == &item->vmcs02)
5887 continue;
5888
5889 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 5890 list_del(&item->list);
5891 kfree(item);
4fa7734c 5892 vmx->nested.vmcs02_num--;
ff2f6fe9 5893 }
ff2f6fe9
NHE		 5894}
5895
0658fbaa
ACL		 5896/*
5897 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5898 * set the success or error code of an emulated VMX instruction, as specified
5899 * by Vol 2B, VMX Instruction Reference, "Conventions".
5900 */
5901static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5902{
5903 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5904 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5905 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5906}
5907
5908static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5909{
5910 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5911 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5912 X86_EFLAGS_SF | X86_EFLAGS_OF))
5913 | X86_EFLAGS_CF);
5914}
5915
145c28dd 5916static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5917 u32 vm_instruction_error)
5918{
5919 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5920 /*
5921 * failValid writes the error number to the current VMCS, which
5922 * can't be done there isn't a current VMCS.
5923 */
5924 nested_vmx_failInvalid(vcpu);
5925 return;
5926 }
5927 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5928 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5929 X86_EFLAGS_SF | X86_EFLAGS_OF))
5930 | X86_EFLAGS_ZF);
5931 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5932 /*
5933 * We don't need to force a shadow sync because
5934 * VM_INSTRUCTION_ERROR is not shadowed
5935 */
5936}
145c28dd 5937
f4124500
JK		 5938static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5939{
5940 struct vcpu_vmx *vmx =
5941 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5942
5943 vmx->nested.preemption_timer_expired = true;
5944 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5945 kvm_vcpu_kick(&vmx->vcpu);
5946
5947 return HRTIMER_NORESTART;
5948}
5949
19677e32
BD		 5950/*
5951 * Decode the memory-address operand of a vmx instruction, as recorded on an
5952 * exit caused by such an instruction (run by a guest hypervisor).
5953 * On success, returns 0. When the operand is invalid, returns 1 and throws
5954 * #UD or #GP.
5955 */
5956static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5957 unsigned long exit_qualification,
5958 u32 vmx_instruction_info, gva_t *ret)
5959{
5960 /*
5961 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5962 * Execution", on an exit, vmx_instruction_info holds most of the
5963 * addressing components of the operand. Only the displacement part
5964 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5965 * For how an actual address is calculated from all these components,
5966 * refer to Vol. 1, "Operand Addressing".
5967 */
5968 int scaling = vmx_instruction_info & 3;
5969 int addr_size = (vmx_instruction_info >> 7) & 7;
5970 bool is_reg = vmx_instruction_info & (1u << 10);
5971 int seg_reg = (vmx_instruction_info >> 15) & 7;
5972 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5973 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5974 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5975 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5976
5977 if (is_reg) {
5978 kvm_queue_exception(vcpu, UD_VECTOR);
5979 return 1;
5980 }
5981
5982 /* Addr = segment_base + offset */
5983 /* offset = base + [index * scale] + displacement */
5984 *ret = vmx_get_segment_base(vcpu, seg_reg);
5985 if (base_is_valid)
5986 *ret += kvm_register_read(vcpu, base_reg);
5987 if (index_is_valid)
5988 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5989 *ret += exit_qualification; /* holds the displacement */
5990
5991 if (addr_size == 1) /* 32 bit */
5992 *ret &= 0xffffffff;
5993
5994 /*
5995 * TODO: throw #GP (and return 1) in various cases that the VM*
5996 * instructions require it - e.g., offset beyond segment limit,
5997 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5998 * address, and so on. Currently these are not checked.
5999 */
6000 return 0;
6001}
6002
3573e22c
BD		 6003/*
6004 * This function performs the various checks including
6005 * - if it's 4KB aligned
6006 * - No bits beyond the physical address width are set
6007 * - Returns 0 on success or else 1
4291b588 6008 * (Intel SDM Section 30.3)
3573e22c 6009 */
4291b588
BD		 6010static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6011 gpa_t *vmpointer)
3573e22c
BD		 6012{
6013 gva_t gva;
6014 gpa_t vmptr;
6015 struct x86_exception e;
6016 struct page *page;
6017 struct vcpu_vmx *vmx = to_vmx(vcpu);
6018 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6019
6020 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6021 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6022 return 1;
6023
6024 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6025 sizeof(vmptr), &e)) {
6026 kvm_inject_page_fault(vcpu, &e);
6027 return 1;
6028 }
6029
6030 switch (exit_reason) {
6031 case EXIT_REASON_VMON:
6032 /*
6033 * SDM 3: 24.11.5
6034 * The first 4 bytes of VMXON region contain the supported
6035 * VMCS revision identifier
6036 *
6037 * Note - IA32_VMX_BASIC[48] will never be 1
6038 * for the nested case;
6039 * which replaces physical address width with 32
6040 *
6041 */
bc39c4db 6042 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6043 nested_vmx_failInvalid(vcpu);
6044 skip_emulated_instruction(vcpu);
6045 return 1;
6046 }
6047
6048 page = nested_get_page(vcpu, vmptr);
6049 if (page == NULL ||
6050 *(u32 *)kmap(page) != VMCS12_REVISION) {
6051 nested_vmx_failInvalid(vcpu);
6052 kunmap(page);
6053 skip_emulated_instruction(vcpu);
6054 return 1;
6055 }
6056 kunmap(page);
6057 vmx->nested.vmxon_ptr = vmptr;
6058 break;
4291b588 6059 case EXIT_REASON_VMCLEAR:
bc39c4db 6060 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6061 nested_vmx_failValid(vcpu,
6062 VMXERR_VMCLEAR_INVALID_ADDRESS);
6063 skip_emulated_instruction(vcpu);
6064 return 1;
6065 }
6066
6067 if (vmptr == vmx->nested.vmxon_ptr) {
6068 nested_vmx_failValid(vcpu,
6069 VMXERR_VMCLEAR_VMXON_POINTER);
6070 skip_emulated_instruction(vcpu);
6071 return 1;
6072 }
6073 break;
6074 case EXIT_REASON_VMPTRLD:
bc39c4db 6075 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6076 nested_vmx_failValid(vcpu,
6077 VMXERR_VMPTRLD_INVALID_ADDRESS);
6078 skip_emulated_instruction(vcpu);
6079 return 1;
6080 }
3573e22c 6081
4291b588
BD		 6082 if (vmptr == vmx->nested.vmxon_ptr) {
6083 nested_vmx_failValid(vcpu,
6084 VMXERR_VMCLEAR_VMXON_POINTER);
6085 skip_emulated_instruction(vcpu);
6086 return 1;
6087 }
6088 break;
3573e22c
BD		 6089 default:
6090 return 1; /* shouldn't happen */
6091 }
6092
4291b588
BD		 6093 if (vmpointer)
6094 *vmpointer = vmptr;
3573e22c
BD		 6095 return 0;
6096}
6097
ec378aee
NHE		 6098/*
6099 * Emulate the VMXON instruction.
6100 * Currently, we just remember that VMX is active, and do not save or even
6101 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6102 * do not currently need to store anything in that guest-allocated memory
6103 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6104 * argument is different from the VMXON pointer (which the spec says they do).
6105 */
6106static int handle_vmon(struct kvm_vcpu *vcpu)
6107{
6108 struct kvm_segment cs;
6109 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6110 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6111 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6112 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6113
6114 /* The Intel VMX Instruction Reference lists a bunch of bits that
6115 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6116 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6117 * Otherwise, we should fail with #UD. We test these now:
6118 */
6119 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6120 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6121 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6122 kvm_queue_exception(vcpu, UD_VECTOR);
6123 return 1;
6124 }
6125
6126 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6127 if (is_long_mode(vcpu) && !cs.l) {
6128 kvm_queue_exception(vcpu, UD_VECTOR);
6129 return 1;
6130 }
6131
6132 if (vmx_get_cpl(vcpu)) {
6133 kvm_inject_gp(vcpu, 0);
6134 return 1;
6135 }
3573e22c 6136
4291b588 6137 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6138 return 1;
6139
145c28dd
AG		 6140 if (vmx->nested.vmxon) {
6141 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6142 skip_emulated_instruction(vcpu);
6143 return 1;
6144 }
b3897a49
NHE		 6145
6146 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6147 != VMXON_NEEDED_FEATURES) {
6148 kvm_inject_gp(vcpu, 0);
6149 return 1;
6150 }
6151
8de48833
AG		 6152 if (enable_shadow_vmcs) {
6153 shadow_vmcs = alloc_vmcs();
6154 if (!shadow_vmcs)
6155 return -ENOMEM;
6156 /* mark vmcs as shadow */
6157 shadow_vmcs->revision_id |= (1u << 31);
6158 /* init shadow vmcs */
6159 vmcs_clear(shadow_vmcs);
6160 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6161 }
ec378aee 6162
ff2f6fe9
NHE		 6163 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6164 vmx->nested.vmcs02_num = 0;
6165
f4124500
JK		 6166 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6167 HRTIMER_MODE_REL);
6168 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6169
ec378aee
NHE		 6170 vmx->nested.vmxon = true;
6171
6172 skip_emulated_instruction(vcpu);
a25eb114 6173 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6174 return 1;
6175}
6176
6177/*
6178 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6179 * for running VMX instructions (except VMXON, whose prerequisites are
6180 * slightly different). It also specifies what exception to inject otherwise.
6181 */
6182static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6183{
6184 struct kvm_segment cs;
6185 struct vcpu_vmx *vmx = to_vmx(vcpu);
6186
6187 if (!vmx->nested.vmxon) {
6188 kvm_queue_exception(vcpu, UD_VECTOR);
6189 return 0;
6190 }
6191
6192 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6193 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6194 (is_long_mode(vcpu) && !cs.l)) {
6195 kvm_queue_exception(vcpu, UD_VECTOR);
6196 return 0;
6197 }
6198
6199 if (vmx_get_cpl(vcpu)) {
6200 kvm_inject_gp(vcpu, 0);
6201 return 0;
6202 }
6203
6204 return 1;
6205}
6206
e7953d7f
AG		 6207static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6208{
8a1b9dd0 6209 u32 exec_control;
9a2a05b9
PB		 6210 if (vmx->nested.current_vmptr == -1ull)
6211 return;
6212
6213 /* current_vmptr and current_vmcs12 are always set/reset together */
6214 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6215 return;
6216
012f83cb 6217 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6218 /* copy to memory all shadowed fields in case
6219 they were modified */
6220 copy_shadow_to_vmcs12(vmx);
6221 vmx->nested.sync_shadow_vmcs = false;
6222 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6223 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6224 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6225 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6226 }
e7953d7f
AG		 6227 kunmap(vmx->nested.current_vmcs12_page);
6228 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6229 vmx->nested.current_vmptr = -1ull;
6230 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6231}
6232
ec378aee
NHE		 6233/*
6234 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6235 * just stops using VMX.
6236 */
6237static void free_nested(struct vcpu_vmx *vmx)
6238{
6239 if (!vmx->nested.vmxon)
6240 return;
9a2a05b9 6241
ec378aee 6242 vmx->nested.vmxon = false;
9a2a05b9 6243 nested_release_vmcs12(vmx);
e7953d7f
AG		 6244 if (enable_shadow_vmcs)
6245 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6246 /* Unpin physical memory we referred to in current vmcs02 */
6247 if (vmx->nested.apic_access_page) {
6248 nested_release_page(vmx->nested.apic_access_page);
6249 vmx->nested.apic_access_page = 0;
6250 }
a7c0b07d
WL		 6251 if (vmx->nested.virtual_apic_page) {
6252 nested_release_page(vmx->nested.virtual_apic_page);
6253 vmx->nested.virtual_apic_page = 0;
6254 }
ff2f6fe9
NHE		 6255
6256 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6257}
6258
6259/* Emulate the VMXOFF instruction */
6260static int handle_vmoff(struct kvm_vcpu *vcpu)
6261{
6262 if (!nested_vmx_check_permission(vcpu))
6263 return 1;
6264 free_nested(to_vmx(vcpu));
6265 skip_emulated_instruction(vcpu);
a25eb114 6266 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6267 return 1;
6268}
6269
27d6c865
NHE		 6270/* Emulate the VMCLEAR instruction */
6271static int handle_vmclear(struct kvm_vcpu *vcpu)
6272{
6273 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6274 gpa_t vmptr;
6275 struct vmcs12 *vmcs12;
6276 struct page *page;
27d6c865
NHE		 6277
6278 if (!nested_vmx_check_permission(vcpu))
6279 return 1;
6280
4291b588 6281 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6282 return 1;
27d6c865 6283
9a2a05b9 6284 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6285 nested_release_vmcs12(vmx);
27d6c865
NHE		 6286
6287 page = nested_get_page(vcpu, vmptr);
6288 if (page == NULL) {
6289 /*
6290 * For accurate processor emulation, VMCLEAR beyond available
6291 * physical memory should do nothing at all. However, it is
6292 * possible that a nested vmx bug, not a guest hypervisor bug,
6293 * resulted in this case, so let's shut down before doing any
6294 * more damage:
6295 */
6296 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6297 return 1;
6298 }
6299 vmcs12 = kmap(page);
6300 vmcs12->launch_state = 0;
6301 kunmap(page);
6302 nested_release_page(page);
6303
6304 nested_free_vmcs02(vmx, vmptr);
6305
6306 skip_emulated_instruction(vcpu);
6307 nested_vmx_succeed(vcpu);
6308 return 1;
6309}
6310
cd232ad0
NHE		 6311static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6312
6313/* Emulate the VMLAUNCH instruction */
6314static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6315{
6316 return nested_vmx_run(vcpu, true);
6317}
6318
6319/* Emulate the VMRESUME instruction */
6320static int handle_vmresume(struct kvm_vcpu *vcpu)
6321{
6322
6323 return nested_vmx_run(vcpu, false);
6324}
6325
49f705c5
NHE		 6326enum vmcs_field_type {
6327 VMCS_FIELD_TYPE_U16 = 0,
6328 VMCS_FIELD_TYPE_U64 = 1,
6329 VMCS_FIELD_TYPE_U32 = 2,
6330 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6331};
6332
6333static inline int vmcs_field_type(unsigned long field)
6334{
6335 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6336 return VMCS_FIELD_TYPE_U32;
6337 return (field >> 13) & 0x3 ;
6338}
6339
6340static inline int vmcs_field_readonly(unsigned long field)
6341{
6342 return (((field >> 10) & 0x3) == 1);
6343}
6344
6345/*
6346 * Read a vmcs12 field. Since these can have varying lengths and we return
6347 * one type, we chose the biggest type (u64) and zero-extend the return value
6348 * to that size. Note that the caller, handle_vmread, might need to use only
6349 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6350 * 64-bit fields are to be returned).
6351 */
6352static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6353 unsigned long field, u64 *ret)
6354{
6355 short offset = vmcs_field_to_offset(field);
6356 char *p;
6357
6358 if (offset < 0)
6359 return 0;
6360
6361 p = ((char *)(get_vmcs12(vcpu))) + offset;
6362
6363 switch (vmcs_field_type(field)) {
6364 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6365 *ret = *((natural_width *)p);
6366 return 1;
6367 case VMCS_FIELD_TYPE_U16:
6368 *ret = *((u16 *)p);
6369 return 1;
6370 case VMCS_FIELD_TYPE_U32:
6371 *ret = *((u32 *)p);
6372 return 1;
6373 case VMCS_FIELD_TYPE_U64:
6374 *ret = *((u64 *)p);
6375 return 1;
6376 default:
6377 return 0; /* can never happen. */
6378 }
6379}
6380
20b97fea
AG		 6381
6382static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6383 unsigned long field, u64 field_value){
6384 short offset = vmcs_field_to_offset(field);
6385 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6386 if (offset < 0)
6387 return false;
6388
6389 switch (vmcs_field_type(field)) {
6390 case VMCS_FIELD_TYPE_U16:
6391 *(u16 *)p = field_value;
6392 return true;
6393 case VMCS_FIELD_TYPE_U32:
6394 *(u32 *)p = field_value;
6395 return true;
6396 case VMCS_FIELD_TYPE_U64:
6397 *(u64 *)p = field_value;
6398 return true;
6399 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6400 *(natural_width *)p = field_value;
6401 return true;
6402 default:
6403 return false; /* can never happen. */
6404 }
6405
6406}
6407
16f5b903
AG		 6408static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6409{
6410 int i;
6411 unsigned long field;
6412 u64 field_value;
6413 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6414 const unsigned long *fields = shadow_read_write_fields;
6415 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6416
6417 vmcs_load(shadow_vmcs);
6418
6419 for (i = 0; i < num_fields; i++) {
6420 field = fields[i];
6421 switch (vmcs_field_type(field)) {
6422 case VMCS_FIELD_TYPE_U16:
6423 field_value = vmcs_read16(field);
6424 break;
6425 case VMCS_FIELD_TYPE_U32:
6426 field_value = vmcs_read32(field);
6427 break;
6428 case VMCS_FIELD_TYPE_U64:
6429 field_value = vmcs_read64(field);
6430 break;
6431 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6432 field_value = vmcs_readl(field);
6433 break;
6434 }
6435 vmcs12_write_any(&vmx->vcpu, field, field_value);
6436 }
6437
6438 vmcs_clear(shadow_vmcs);
6439 vmcs_load(vmx->loaded_vmcs->vmcs);
6440}
6441
c3114420
AG		 6442static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6443{
c2bae893
MK		 6444 const unsigned long *fields[] = {
6445 shadow_read_write_fields,
6446 shadow_read_only_fields
c3114420 6447 };
c2bae893 6448 const int max_fields[] = {
c3114420
AG		 6449 max_shadow_read_write_fields,
6450 max_shadow_read_only_fields
6451 };
6452 int i, q;
6453 unsigned long field;
6454 u64 field_value = 0;
6455 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6456
6457 vmcs_load(shadow_vmcs);
6458
c2bae893 6459 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6460 for (i = 0; i < max_fields[q]; i++) {
6461 field = fields[q][i];
6462 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6463
6464 switch (vmcs_field_type(field)) {
6465 case VMCS_FIELD_TYPE_U16:
6466 vmcs_write16(field, (u16)field_value);
6467 break;
6468 case VMCS_FIELD_TYPE_U32:
6469 vmcs_write32(field, (u32)field_value);
6470 break;
6471 case VMCS_FIELD_TYPE_U64:
6472 vmcs_write64(field, (u64)field_value);
6473 break;
6474 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6475 vmcs_writel(field, (long)field_value);
6476 break;
6477 }
6478 }
6479 }
6480
6481 vmcs_clear(shadow_vmcs);
6482 vmcs_load(vmx->loaded_vmcs->vmcs);
6483}
6484
49f705c5
NHE		 6485/*
6486 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6487 * used before) all generate the same failure when it is missing.
6488 */
6489static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6490{
6491 struct vcpu_vmx *vmx = to_vmx(vcpu);
6492 if (vmx->nested.current_vmptr == -1ull) {
6493 nested_vmx_failInvalid(vcpu);
6494 skip_emulated_instruction(vcpu);
6495 return 0;
6496 }
6497 return 1;
6498}
6499
6500static int handle_vmread(struct kvm_vcpu *vcpu)
6501{
6502 unsigned long field;
6503 u64 field_value;
6504 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6505 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6506 gva_t gva = 0;
6507
6508 if (!nested_vmx_check_permission(vcpu) ||
6509 !nested_vmx_check_vmcs12(vcpu))
6510 return 1;
6511
6512 /* Decode instruction info and find the field to read */
27e6fb5d 6513 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6514 /* Read the field, zero-extended to a u64 field_value */
6515 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6516 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6517 skip_emulated_instruction(vcpu);
6518 return 1;
6519 }
6520 /*
6521 * Now copy part of this value to register or memory, as requested.
6522 * Note that the number of bits actually copied is 32 or 64 depending
6523 * on the guest's mode (32 or 64 bit), not on the given field's length.
6524 */
6525 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6526 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6527 field_value);
6528 } else {
6529 if (get_vmx_mem_address(vcpu, exit_qualification,
6530 vmx_instruction_info, &gva))
6531 return 1;
6532 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6533 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6534 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6535 }
6536
6537 nested_vmx_succeed(vcpu);
6538 skip_emulated_instruction(vcpu);
6539 return 1;
6540}
6541
6542
6543static int handle_vmwrite(struct kvm_vcpu *vcpu)
6544{
6545 unsigned long field;
6546 gva_t gva;
6547 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6548 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6549 /* The value to write might be 32 or 64 bits, depending on L1's long
6550 * mode, and eventually we need to write that into a field of several
6551 * possible lengths. The code below first zero-extends the value to 64
6552 * bit (field_value), and then copies only the approriate number of
6553 * bits into the vmcs12 field.
6554 */
6555 u64 field_value = 0;
6556 struct x86_exception e;
6557
6558 if (!nested_vmx_check_permission(vcpu) ||
6559 !nested_vmx_check_vmcs12(vcpu))
6560 return 1;
6561
6562 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6563 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6564 (((vmx_instruction_info) >> 3) & 0xf));
6565 else {
6566 if (get_vmx_mem_address(vcpu, exit_qualification,
6567 vmx_instruction_info, &gva))
6568 return 1;
6569 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6570 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6571 kvm_inject_page_fault(vcpu, &e);
6572 return 1;
6573 }
6574 }
6575
6576
27e6fb5d 6577 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6578 if (vmcs_field_readonly(field)) {
6579 nested_vmx_failValid(vcpu,
6580 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6581 skip_emulated_instruction(vcpu);
6582 return 1;
6583 }
6584
20b97fea 6585 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6586 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6587 skip_emulated_instruction(vcpu);
6588 return 1;
6589 }
6590
6591 nested_vmx_succeed(vcpu);
6592 skip_emulated_instruction(vcpu);
6593 return 1;
6594}
6595
63846663
NHE		 6596/* Emulate the VMPTRLD instruction */
6597static int handle_vmptrld(struct kvm_vcpu *vcpu)
6598{
6599 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6600 gpa_t vmptr;
8a1b9dd0 6601 u32 exec_control;
63846663
NHE		 6602
6603 if (!nested_vmx_check_permission(vcpu))
6604 return 1;
6605
4291b588 6606 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6607 return 1;
63846663
NHE		 6608
6609 if (vmx->nested.current_vmptr != vmptr) {
6610 struct vmcs12 *new_vmcs12;
6611 struct page *page;
6612 page = nested_get_page(vcpu, vmptr);
6613 if (page == NULL) {
6614 nested_vmx_failInvalid(vcpu);
6615 skip_emulated_instruction(vcpu);
6616 return 1;
6617 }
6618 new_vmcs12 = kmap(page);
6619 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6620 kunmap(page);
6621 nested_release_page_clean(page);
6622 nested_vmx_failValid(vcpu,
6623 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6624 skip_emulated_instruction(vcpu);
6625 return 1;
6626 }
63846663 6627
9a2a05b9 6628 nested_release_vmcs12(vmx);
63846663
NHE		 6629 vmx->nested.current_vmptr = vmptr;
6630 vmx->nested.current_vmcs12 = new_vmcs12;
6631 vmx->nested.current_vmcs12_page = page;
012f83cb 6632 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6633 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6634 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6635 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6636 vmcs_write64(VMCS_LINK_POINTER,
6637 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6638 vmx->nested.sync_shadow_vmcs = true;
6639 }
63846663
NHE		 6640 }
6641
6642 nested_vmx_succeed(vcpu);
6643 skip_emulated_instruction(vcpu);
6644 return 1;
6645}
6646
6a4d7550
NHE		 6647/* Emulate the VMPTRST instruction */
6648static int handle_vmptrst(struct kvm_vcpu *vcpu)
6649{
6650 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6651 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6652 gva_t vmcs_gva;
6653 struct x86_exception e;
6654
6655 if (!nested_vmx_check_permission(vcpu))
6656 return 1;
6657
6658 if (get_vmx_mem_address(vcpu, exit_qualification,
6659 vmx_instruction_info, &vmcs_gva))
6660 return 1;
6661 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6662 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6663 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6664 sizeof(u64), &e)) {
6665 kvm_inject_page_fault(vcpu, &e);
6666 return 1;
6667 }
6668 nested_vmx_succeed(vcpu);
6669 skip_emulated_instruction(vcpu);
6670 return 1;
6671}
6672
bfd0a56b
NHE		 6673/* Emulate the INVEPT instruction */
6674static int handle_invept(struct kvm_vcpu *vcpu)
6675{
6676 u32 vmx_instruction_info, types;
6677 unsigned long type;
6678 gva_t gva;
6679 struct x86_exception e;
6680 struct {
6681 u64 eptp, gpa;
6682 } operand;
bfd0a56b
NHE		 6683
6684 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6685 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6686 kvm_queue_exception(vcpu, UD_VECTOR);
6687 return 1;
6688 }
6689
6690 if (!nested_vmx_check_permission(vcpu))
6691 return 1;
6692
6693 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6694 kvm_queue_exception(vcpu, UD_VECTOR);
6695 return 1;
6696 }
6697
6698 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6699 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6700
6701 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6702
6703 if (!(types & (1UL << type))) {
6704 nested_vmx_failValid(vcpu,
6705 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6706 return 1;
6707 }
6708
6709 /* According to the Intel VMX instruction reference, the memory
6710 * operand is read even if it isn't needed (e.g., for type==global)
6711 */
6712 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6713 vmx_instruction_info, &gva))
6714 return 1;
6715 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6716 sizeof(operand), &e)) {
6717 kvm_inject_page_fault(vcpu, &e);
6718 return 1;
6719 }
6720
6721 switch (type) {
bfd0a56b
NHE		 6722 case VMX_EPT_EXTENT_GLOBAL:
6723 kvm_mmu_sync_roots(vcpu);
6724 kvm_mmu_flush_tlb(vcpu);
6725 nested_vmx_succeed(vcpu);
6726 break;
6727 default:
4b855078 6728 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6729 BUG_ON(1);
6730 break;
6731 }
6732
6733 skip_emulated_instruction(vcpu);
6734 return 1;
6735}
6736
6aa8b732
AK		 6737/*
6738 * The exit handlers return 1 if the exit was handled fully and guest execution
6739 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6740 * to be done to userspace and return 0.
6741 */
772e0318 6742static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6743 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6744 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6745 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6746 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6747 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6748 [EXIT_REASON_CR_ACCESS] = handle_cr,
6749 [EXIT_REASON_DR_ACCESS] = handle_dr,
6750 [EXIT_REASON_CPUID] = handle_cpuid,
6751 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6752 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6753 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6754 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6755 [EXIT_REASON_INVD] = handle_invd,
a7052897 6756 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6757 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6758 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6759 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6760 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6761 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6762 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6763 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6764 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6765 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6766 [EXIT_REASON_VMOFF] = handle_vmoff,
6767 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6768 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6769 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6770 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6771 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6772 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6773 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6774 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6775 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6776 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6777 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6778 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6779 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6780 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6781 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6782};
6783
6784static const int kvm_vmx_max_exit_handlers =
50a3485c 6785 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6786
908a7bdd
JK		 6787static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6788 struct vmcs12 *vmcs12)
6789{
6790 unsigned long exit_qualification;
6791 gpa_t bitmap, last_bitmap;
6792 unsigned int port;
6793 int size;
6794 u8 b;
6795
908a7bdd 6796 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6797 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6798
6799 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6800
6801 port = exit_qualification >> 16;
6802 size = (exit_qualification & 7) + 1;
6803
6804 last_bitmap = (gpa_t)-1;
6805 b = -1;
6806
6807 while (size > 0) {
6808 if (port < 0x8000)
6809 bitmap = vmcs12->io_bitmap_a;
6810 else if (port < 0x10000)
6811 bitmap = vmcs12->io_bitmap_b;
6812 else
6813 return 1;
6814 bitmap += (port & 0x7fff) / 8;
6815
6816 if (last_bitmap != bitmap)
6817 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6818 return 1;
6819 if (b & (1 << (port & 7)))
6820 return 1;
6821
6822 port++;
6823 size--;
6824 last_bitmap = bitmap;
6825 }
6826
6827 return 0;
6828}
6829
644d711a
NHE		 6830/*
6831 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6832 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6833 * disinterest in the current event (read or write a specific MSR) by using an
6834 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6835 */
6836static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6837 struct vmcs12 *vmcs12, u32 exit_reason)
6838{
6839 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6840 gpa_t bitmap;
6841
cbd29cb6 6842 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6843 return 1;
6844
6845 /*
6846 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6847 * for the four combinations of read/write and low/high MSR numbers.
6848 * First we need to figure out which of the four to use:
6849 */
6850 bitmap = vmcs12->msr_bitmap;
6851 if (exit_reason == EXIT_REASON_MSR_WRITE)
6852 bitmap += 2048;
6853 if (msr_index >= 0xc0000000) {
6854 msr_index -= 0xc0000000;
6855 bitmap += 1024;
6856 }
6857
6858 /* Then read the msr_index'th bit from this bitmap: */
6859 if (msr_index < 1024*8) {
6860 unsigned char b;
bd31a7f5
JK		 6861 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6862 return 1;
644d711a
NHE		 6863 return 1 & (b >> (msr_index & 7));
6864 } else
6865 return 1; /* let L1 handle the wrong parameter */
6866}
6867
6868/*
6869 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6870 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6871 * intercept (via guest_host_mask etc.) the current event.
6872 */
6873static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6874 struct vmcs12 *vmcs12)
6875{
6876 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6877 int cr = exit_qualification & 15;
6878 int reg = (exit_qualification >> 8) & 15;
1e32c079 6879 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 6880
6881 switch ((exit_qualification >> 4) & 3) {
6882 case 0: /* mov to cr */
6883 switch (cr) {
6884 case 0:
6885 if (vmcs12->cr0_guest_host_mask &
6886 (val ^ vmcs12->cr0_read_shadow))
6887 return 1;
6888 break;
6889 case 3:
6890 if ((vmcs12->cr3_target_count >= 1 &&
6891 vmcs12->cr3_target_value0 == val) ||
6892 (vmcs12->cr3_target_count >= 2 &&
6893 vmcs12->cr3_target_value1 == val) ||
6894 (vmcs12->cr3_target_count >= 3 &&
6895 vmcs12->cr3_target_value2 == val) ||
6896 (vmcs12->cr3_target_count >= 4 &&
6897 vmcs12->cr3_target_value3 == val))
6898 return 0;
6899 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6900 return 1;
6901 break;
6902 case 4:
6903 if (vmcs12->cr4_guest_host_mask &
6904 (vmcs12->cr4_read_shadow ^ val))
6905 return 1;
6906 break;
6907 case 8:
6908 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6909 return 1;
6910 break;
6911 }
6912 break;
6913 case 2: /* clts */
6914 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6915 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6916 return 1;
6917 break;
6918 case 1: /* mov from cr */
6919 switch (cr) {
6920 case 3:
6921 if (vmcs12->cpu_based_vm_exec_control &
6922 CPU_BASED_CR3_STORE_EXITING)
6923 return 1;
6924 break;
6925 case 8:
6926 if (vmcs12->cpu_based_vm_exec_control &
6927 CPU_BASED_CR8_STORE_EXITING)
6928 return 1;
6929 break;
6930 }
6931 break;
6932 case 3: /* lmsw */
6933 /*
6934 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6935 * cr0. Other attempted changes are ignored, with no exit.
6936 */
6937 if (vmcs12->cr0_guest_host_mask & 0xe &
6938 (val ^ vmcs12->cr0_read_shadow))
6939 return 1;
6940 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6941 !(vmcs12->cr0_read_shadow & 0x1) &&
6942 (val & 0x1))
6943 return 1;
6944 break;
6945 }
6946 return 0;
6947}
6948
6949/*
6950 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6951 * should handle it ourselves in L0 (and then continue L2). Only call this
6952 * when in is_guest_mode (L2).
6953 */
6954static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6955{
644d711a
NHE		 6956 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6957 struct vcpu_vmx *vmx = to_vmx(vcpu);
6958 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6959 u32 exit_reason = vmx->exit_reason;
644d711a 6960
542060ea
JK		 6961 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6962 vmcs_readl(EXIT_QUALIFICATION),
6963 vmx->idt_vectoring_info,
6964 intr_info,
6965 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6966 KVM_ISA_VMX);
6967
644d711a
NHE		 6968 if (vmx->nested.nested_run_pending)
6969 return 0;
6970
6971 if (unlikely(vmx->fail)) {
bd80158a
JK		 6972 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6973 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6974 return 1;
6975 }
6976
6977 switch (exit_reason) {
6978 case EXIT_REASON_EXCEPTION_NMI:
6979 if (!is_exception(intr_info))
6980 return 0;
6981 else if (is_page_fault(intr_info))
6982 return enable_ept;
e504c909 6983 else if (is_no_device(intr_info) &&
ccf9844e 6984 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6985 return 0;
644d711a
NHE		 6986 return vmcs12->exception_bitmap &
6987 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6988 case EXIT_REASON_EXTERNAL_INTERRUPT:
6989 return 0;
6990 case EXIT_REASON_TRIPLE_FAULT:
6991 return 1;
6992 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6993 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6994 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6995 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6996 case EXIT_REASON_TASK_SWITCH:
6997 return 1;
6998 case EXIT_REASON_CPUID:
6999 return 1;
7000 case EXIT_REASON_HLT:
7001 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7002 case EXIT_REASON_INVD:
7003 return 1;
7004 case EXIT_REASON_INVLPG:
7005 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7006 case EXIT_REASON_RDPMC:
7007 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7008 case EXIT_REASON_RDTSC:
7009 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7010 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7011 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7012 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7013 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7014 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 7015 case EXIT_REASON_INVEPT:
644d711a
NHE		 7016 /*
7017 * VMX instructions trap unconditionally. This allows L1 to
7018 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7019 */
7020 return 1;
7021 case EXIT_REASON_CR_ACCESS:
7022 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7023 case EXIT_REASON_DR_ACCESS:
7024 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7025 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7026 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7027 case EXIT_REASON_MSR_READ:
7028 case EXIT_REASON_MSR_WRITE:
7029 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7030 case EXIT_REASON_INVALID_STATE:
7031 return 1;
7032 case EXIT_REASON_MWAIT_INSTRUCTION:
7033 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7034 case EXIT_REASON_MONITOR_INSTRUCTION:
7035 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7036 case EXIT_REASON_PAUSE_INSTRUCTION:
7037 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7038 nested_cpu_has2(vmcs12,
7039 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7040 case EXIT_REASON_MCE_DURING_VMENTRY:
7041 return 0;
7042 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7043 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7044 case EXIT_REASON_APIC_ACCESS:
7045 return nested_cpu_has2(vmcs12,
7046 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7047 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7048 /*
7049 * L0 always deals with the EPT violation. If nested EPT is
7050 * used, and the nested mmu code discovers that the address is
7051 * missing in the guest EPT table (EPT12), the EPT violation
7052 * will be injected with nested_ept_inject_page_fault()
7053 */
7054 return 0;
644d711a 7055 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7056 /*
7057 * L2 never uses directly L1's EPT, but rather L0's own EPT
7058 * table (shadow on EPT) or a merged EPT table that L0 built
7059 * (EPT on EPT). So any problems with the structure of the
7060 * table is L0's fault.
7061 */
644d711a
NHE		 7062 return 0;
7063 case EXIT_REASON_WBINVD:
7064 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7065 case EXIT_REASON_XSETBV:
7066 return 1;
7067 default:
7068 return 1;
7069 }
7070}
7071
586f9607
AK		 7072static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7073{
7074 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7075 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7076}
7077
6aa8b732
AK		 7078/*
7079 * The guest has exited. See if we can fix it or if we need userspace
7080 * assistance.
7081 */
851ba692 7082static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7083{
29bd8a78 7084 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7085 u32 exit_reason = vmx->exit_reason;
1155f76a 7086 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7087
80ced186 7088 /* If guest state is invalid, start emulating */
14168786 7089 if (vmx->emulation_required)
80ced186 7090 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7091
644d711a 7092 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7093 nested_vmx_vmexit(vcpu, exit_reason,
7094 vmcs_read32(VM_EXIT_INTR_INFO),
7095 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7096 return 1;
7097 }
7098
5120702e
MG		 7099 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7100 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7101 vcpu->run->fail_entry.hardware_entry_failure_reason
7102 = exit_reason;
7103 return 0;
7104 }
7105
29bd8a78 7106 if (unlikely(vmx->fail)) {
851ba692
AK		 7107 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7108 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7109 = vmcs_read32(VM_INSTRUCTION_ERROR);
7110 return 0;
7111 }
6aa8b732 7112
b9bf6882
XG		 7113 /*
7114 * Note:
7115 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7116 * delivery event since it indicates guest is accessing MMIO.
7117 * The vm-exit can be triggered again after return to guest that
7118 * will cause infinite loop.
7119 */
d77c26fc 7120 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7121 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7122 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7123 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7124 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7125 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7126 vcpu->run->internal.ndata = 2;
7127 vcpu->run->internal.data[0] = vectoring_info;
7128 vcpu->run->internal.data[1] = exit_reason;
7129 return 0;
7130 }
3b86cd99 7131
644d711a
NHE		 7132 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7133 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7134 get_vmcs12(vcpu))))) {
c4282df9 7135 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7136 vmx->soft_vnmi_blocked = 0;
3b86cd99 7137 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7138 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7139 /*
7140 * This CPU don't support us in finding the end of an
7141 * NMI-blocked window if the guest runs with IRQs
7142 * disabled. So we pull the trigger after 1 s of
7143 * futile waiting, but inform the user about this.
7144 */
7145 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7146 "state on VCPU %d after 1 s timeout\n",
7147 __func__, vcpu->vcpu_id);
7148 vmx->soft_vnmi_blocked = 0;
3b86cd99 7149 }
3b86cd99
JK		 7150 }
7151
6aa8b732
AK		 7152 if (exit_reason < kvm_vmx_max_exit_handlers
7153 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7154 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7155 else {
851ba692
AK		 7156 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7157 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7158 }
7159 return 0;
7160}
7161
95ba8273 7162static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7163{
a7c0b07d
WL		 7164 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7165
7166 if (is_guest_mode(vcpu) &&
7167 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7168 return;
7169
95ba8273 7170 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7171 vmcs_write32(TPR_THRESHOLD, 0);
7172 return;
7173 }
7174
95ba8273 7175 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7176}
7177
8d14695f
YZ		 7178static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7179{
7180 u32 sec_exec_control;
7181
7182 /*
7183 * There is not point to enable virtualize x2apic without enable
7184 * apicv
7185 */
c7c9c56c
YZ		 7186 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7187 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7188 return;
7189
7190 if (!vm_need_tpr_shadow(vcpu->kvm))
7191 return;
7192
7193 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7194
7195 if (set) {
7196 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7197 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7198 } else {
7199 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7200 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7201 }
7202 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7203
7204 vmx_set_msr_bitmap(vcpu);
7205}
7206
c7c9c56c
YZ		 7207static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7208{
7209 u16 status;
7210 u8 old;
7211
7212 if (!vmx_vm_has_apicv(kvm))
7213 return;
7214
7215 if (isr == -1)
7216 isr = 0;
7217
7218 status = vmcs_read16(GUEST_INTR_STATUS);
7219 old = status >> 8;
7220 if (isr != old) {
7221 status &= 0xff;
7222 status |= isr << 8;
7223 vmcs_write16(GUEST_INTR_STATUS, status);
7224 }
7225}
7226
7227static void vmx_set_rvi(int vector)
7228{
7229 u16 status;
7230 u8 old;
7231
7232 status = vmcs_read16(GUEST_INTR_STATUS);
7233 old = (u8)status & 0xff;
7234 if ((u8)vector != old) {
7235 status &= ~0xff;
7236 status |= (u8)vector;
7237 vmcs_write16(GUEST_INTR_STATUS, status);
7238 }
7239}
7240
7241static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7242{
7243 if (max_irr == -1)
7244 return;
7245
963fee16
WL		 7246 /*
7247 * If a vmexit is needed, vmx_check_nested_events handles it.
7248 */
7249 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7250 return;
7251
7252 if (!is_guest_mode(vcpu)) {
7253 vmx_set_rvi(max_irr);
7254 return;
7255 }
7256
7257 /*
7258 * Fall back to pre-APICv interrupt injection since L2
7259 * is run without virtual interrupt delivery.
7260 */
7261 if (!kvm_event_needs_reinjection(vcpu) &&
7262 vmx_interrupt_allowed(vcpu)) {
7263 kvm_queue_interrupt(vcpu, max_irr, false);
7264 vmx_inject_irq(vcpu);
7265 }
c7c9c56c
YZ		 7266}
7267
7268static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7269{
3d81bc7e
YZ		 7270 if (!vmx_vm_has_apicv(vcpu->kvm))
7271 return;
7272
c7c9c56c
YZ		 7273 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7274 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7275 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7276 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7277}
7278
51aa01d1 7279static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7280{
00eba012
AK		 7281 u32 exit_intr_info;
7282
7283 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7284 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7285 return;
7286
c5ca8e57 7287 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7288 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7289
7290 /* Handle machine checks before interrupts are enabled */
00eba012 7291 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7292 kvm_machine_check();
7293
20f65983 7294 /* We need to handle NMIs before interrupts are enabled */
00eba012 7295 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7296 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7297 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7298 asm("int $2");
ff9d07a0
ZY		 7299 kvm_after_handle_nmi(&vmx->vcpu);
7300 }
51aa01d1 7301}
20f65983 7302
a547c6db
YZ		 7303static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7304{
7305 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7306
7307 /*
7308 * If external interrupt exists, IF bit is set in rflags/eflags on the
7309 * interrupt stack frame, and interrupt will be enabled on a return
7310 * from interrupt handler.
7311 */
7312 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7313 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7314 unsigned int vector;
7315 unsigned long entry;
7316 gate_desc *desc;
7317 struct vcpu_vmx *vmx = to_vmx(vcpu);
7318#ifdef CONFIG_X86_64
7319 unsigned long tmp;
7320#endif
7321
7322 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7323 desc = (gate_desc *)vmx->host_idt_base + vector;
7324 entry = gate_offset(*desc);
7325 asm volatile(
7326#ifdef CONFIG_X86_64
7327 "mov %%" _ASM_SP ", %[sp]\n\t"
7328 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7329 "push $%c[ss]\n\t"
7330 "push %[sp]\n\t"
7331#endif
7332 "pushf\n\t"
7333 "orl $0x200, (%%" _ASM_SP ")\n\t"
7334 __ASM_SIZE(push) " $%c[cs]\n\t"
7335 "call *%[entry]\n\t"
7336 :
7337#ifdef CONFIG_X86_64
7338 [sp]"=&r"(tmp)
7339#endif
7340 :
7341 [entry]"r"(entry),
7342 [ss]"i"(__KERNEL_DS),
7343 [cs]"i"(__KERNEL_CS)
7344 );
7345 } else
7346 local_irq_enable();
7347}
7348
da8999d3
LJ		 7349static bool vmx_mpx_supported(void)
7350{
7351 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7352 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7353}
7354
51aa01d1
AK		 7355static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7356{
c5ca8e57 7357 u32 exit_intr_info;
51aa01d1
AK		 7358 bool unblock_nmi;
7359 u8 vector;
7360 bool idtv_info_valid;
7361
7362 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7363
cf393f75 7364 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7365 if (vmx->nmi_known_unmasked)
7366 return;
c5ca8e57
AK		 7367 /*
7368 * Can't use vmx->exit_intr_info since we're not sure what
7369 * the exit reason is.
7370 */
7371 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7372 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7373 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7374 /*
7b4a25cb 7375 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7376 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7377 * a guest IRET fault.
7b4a25cb
GN		 7378 * SDM 3: 23.2.2 (September 2008)
7379 * Bit 12 is undefined in any of the following cases:
7380 * If the VM exit sets the valid bit in the IDT-vectoring
7381 * information field.
7382 * If the VM exit is due to a double fault.
cf393f75 7383 */
7b4a25cb
GN		 7384 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7385 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7386 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7387 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7388 else
7389 vmx->nmi_known_unmasked =
7390 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7391 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7392 } else if (unlikely(vmx->soft_vnmi_blocked))
7393 vmx->vnmi_blocked_time +=
7394 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7395}
7396
3ab66e8a 7397static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7398 u32 idt_vectoring_info,
7399 int instr_len_field,
7400 int error_code_field)
51aa01d1 7401{
51aa01d1
AK		 7402 u8 vector;
7403 int type;
7404 bool idtv_info_valid;
7405
7406 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7407
3ab66e8a
JK		 7408 vcpu->arch.nmi_injected = false;
7409 kvm_clear_exception_queue(vcpu);
7410 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7411
7412 if (!idtv_info_valid)
7413 return;
7414
3ab66e8a 7415 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7416
668f612f
AK		 7417 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7418 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7419
64a7ec06 7420 switch (type) {
37b96e98 7421 case INTR_TYPE_NMI_INTR:
3ab66e8a 7422 vcpu->arch.nmi_injected = true;
668f612f 7423 /*
7b4a25cb 7424 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7425 * Clear bit "block by NMI" before VM entry if a NMI
7426 * delivery faulted.
668f612f 7427 */
3ab66e8a 7428 vmx_set_nmi_mask(vcpu, false);
37b96e98 7429 break;
37b96e98 7430 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7431 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7432 /* fall through */
7433 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7434 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7435 u32 err = vmcs_read32(error_code_field);
851eb667 7436 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7437 } else
851eb667 7438 kvm_requeue_exception(vcpu, vector);
37b96e98 7439 break;
66fd3f7f 7440 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7441 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7442 /* fall through */
37b96e98 7443 case INTR_TYPE_EXT_INTR:
3ab66e8a 7444 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7445 break;
7446 default:
7447 break;
f7d9238f 7448 }
cf393f75
AK		 7449}
7450
83422e17
AK		 7451static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7452{
3ab66e8a 7453 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7454 VM_EXIT_INSTRUCTION_LEN,
7455 IDT_VECTORING_ERROR_CODE);
7456}
7457
b463a6f7
AK		 7458static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7459{
3ab66e8a 7460 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7461 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7462 VM_ENTRY_INSTRUCTION_LEN,
7463 VM_ENTRY_EXCEPTION_ERROR_CODE);
7464
7465 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7466}
7467
d7cd9796
GN		 7468static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7469{
7470 int i, nr_msrs;
7471 struct perf_guest_switch_msr *msrs;
7472
7473 msrs = perf_guest_get_msrs(&nr_msrs);
7474
7475 if (!msrs)
7476 return;
7477
7478 for (i = 0; i < nr_msrs; i++)
7479 if (msrs[i].host == msrs[i].guest)
7480 clear_atomic_switch_msr(vmx, msrs[i].msr);
7481 else
7482 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7483 msrs[i].host);
7484}
7485
a3b5ba49 7486static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7487{
a2fa3e9f 7488 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7489 unsigned long debugctlmsr;
104f226b
AK		 7490
7491 /* Record the guest's net vcpu time for enforced NMI injections. */
7492 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7493 vmx->entry_time = ktime_get();
7494
7495 /* Don't enter VMX if guest state is invalid, let the exit handler
7496 start emulation until we arrive back to a valid state */
14168786 7497 if (vmx->emulation_required)
104f226b
AK		 7498 return;
7499
a7653ecd
RK		 7500 if (vmx->ple_window_dirty) {
7501 vmx->ple_window_dirty = false;
7502 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7503 }
7504
012f83cb
AG		 7505 if (vmx->nested.sync_shadow_vmcs) {
7506 copy_vmcs12_to_shadow(vmx);
7507 vmx->nested.sync_shadow_vmcs = false;
7508 }
7509
104f226b
AK		 7510 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7511 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7512 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7513 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7514
7515 /* When single-stepping over STI and MOV SS, we must clear the
7516 * corresponding interruptibility bits in the guest state. Otherwise
7517 * vmentry fails as it then expects bit 14 (BS) in pending debug
7518 * exceptions being set, but that's not correct for the guest debugging
7519 * case. */
7520 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7521 vmx_set_interrupt_shadow(vcpu, 0);
7522
d7cd9796 7523 atomic_switch_perf_msrs(vmx);
2a7921b7 7524 debugctlmsr = get_debugctlmsr();
d7cd9796 7525
d462b819 7526 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7527 asm(
6aa8b732 7528 /* Store host registers */
b188c81f
AK		 7529 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7530 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7531 "push %%" _ASM_CX " \n\t"
7532 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7533 "je 1f \n\t"
b188c81f 7534 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7535 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7536 "1: \n\t"
d3edefc0 7537 /* Reload cr2 if changed */
b188c81f
AK		 7538 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7539 "mov %%cr2, %%" _ASM_DX " \n\t"
7540 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7541 "je 2f \n\t"
b188c81f 7542 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7543 "2: \n\t"
6aa8b732 7544 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7545 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7546 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7547 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7548 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7549 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7550 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7551 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7552 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7553#ifdef CONFIG_X86_64
e08aa78a
AK		 7554 "mov %c[r8](%0), %%r8 \n\t"
7555 "mov %c[r9](%0), %%r9 \n\t"
7556 "mov %c[r10](%0), %%r10 \n\t"
7557 "mov %c[r11](%0), %%r11 \n\t"
7558 "mov %c[r12](%0), %%r12 \n\t"
7559 "mov %c[r13](%0), %%r13 \n\t"
7560 "mov %c[r14](%0), %%r14 \n\t"
7561 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7562#endif
b188c81f 7563 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7564
6aa8b732 7565 /* Enter guest mode */
83287ea4 7566 "jne 1f \n\t"
4ecac3fd 7567 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7568 "jmp 2f \n\t"
7569 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7570 "2: "
6aa8b732 7571 /* Save guest registers, load host registers, keep flags */
b188c81f 7572 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7573 "pop %0 \n\t"
b188c81f
AK		 7574 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7575 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7576 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7577 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7578 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7579 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7580 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7581#ifdef CONFIG_X86_64
e08aa78a
AK		 7582 "mov %%r8, %c[r8](%0) \n\t"
7583 "mov %%r9, %c[r9](%0) \n\t"
7584 "mov %%r10, %c[r10](%0) \n\t"
7585 "mov %%r11, %c[r11](%0) \n\t"
7586 "mov %%r12, %c[r12](%0) \n\t"
7587 "mov %%r13, %c[r13](%0) \n\t"
7588 "mov %%r14, %c[r14](%0) \n\t"
7589 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7590#endif
b188c81f
AK		 7591 "mov %%cr2, %%" _ASM_AX " \n\t"
7592 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7593
b188c81f 7594 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7595 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7596 ".pushsection .rodata \n\t"
7597 ".global vmx_return \n\t"
7598 "vmx_return: " _ASM_PTR " 2b \n\t"
7599 ".popsection"
e08aa78a 7600 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7601 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7602 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7603 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7604 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7605 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7606 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7607 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7608 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7609 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7610 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7611#ifdef CONFIG_X86_64
ad312c7c
ZX		 7612 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7613 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7614 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7615 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7616 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7617 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7618 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7619 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7620#endif
40712fae
AK		 7621 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7622 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7623 : "cc", "memory"
7624#ifdef CONFIG_X86_64
b188c81f 7625 , "rax", "rbx", "rdi", "rsi"
c2036300 7626 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7627#else
7628 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7629#endif
7630 );
6aa8b732 7631
2a7921b7
GN		 7632 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7633 if (debugctlmsr)
7634 update_debugctlmsr(debugctlmsr);
7635
aa67f609
AK		 7636#ifndef CONFIG_X86_64
7637 /*
7638 * The sysexit path does not restore ds/es, so we must set them to
7639 * a reasonable value ourselves.
7640 *
7641 * We can't defer this to vmx_load_host_state() since that function
7642 * may be executed in interrupt context, which saves and restore segments
7643 * around it, nullifying its effect.
7644 */
7645 loadsegment(ds, __USER_DS);
7646 loadsegment(es, __USER_DS);
7647#endif
7648
6de4f3ad 7649 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7650 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7651 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7652 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7653 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7654 vcpu->arch.regs_dirty = 0;
7655
1155f76a
AK		 7656 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7657
d462b819 7658 vmx->loaded_vmcs->launched = 1;
1b6269db 7659
51aa01d1 7660 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7661 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7662
e0b890d3
GN		 7663 /*
7664 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7665 * we did not inject a still-pending event to L1 now because of
7666 * nested_run_pending, we need to re-enable this bit.
7667 */
7668 if (vmx->nested.nested_run_pending)
7669 kvm_make_request(KVM_REQ_EVENT, vcpu);
7670
7671 vmx->nested.nested_run_pending = 0;
7672
51aa01d1
AK		 7673 vmx_complete_atomic_exit(vmx);
7674 vmx_recover_nmi_blocking(vmx);
cf393f75 7675 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7676}
7677
4fa7734c
PB		 7678static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7679{
7680 struct vcpu_vmx *vmx = to_vmx(vcpu);
7681 int cpu;
7682
7683 if (vmx->loaded_vmcs == &vmx->vmcs01)
7684 return;
7685
7686 cpu = get_cpu();
7687 vmx->loaded_vmcs = &vmx->vmcs01;
7688 vmx_vcpu_put(vcpu);
7689 vmx_vcpu_load(vcpu, cpu);
7690 vcpu->cpu = cpu;
7691 put_cpu();
7692}
7693
6aa8b732
AK		 7694static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7695{
fb3f0f51
RR		 7696 struct vcpu_vmx *vmx = to_vmx(vcpu);
7697
cdbecfc3 7698 free_vpid(vmx);
4fa7734c
PB		 7699 leave_guest_mode(vcpu);
7700 vmx_load_vmcs01(vcpu);
26a865f4 7701 free_nested(vmx);
4fa7734c 7702 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7703 kfree(vmx->guest_msrs);
7704 kvm_vcpu_uninit(vcpu);
a4770347 7705 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7706}
7707
fb3f0f51 7708static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7709{
fb3f0f51 7710 int err;
c16f862d 7711 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7712 int cpu;
6aa8b732 7713
a2fa3e9f 7714 if (!vmx)
fb3f0f51
RR		 7715 return ERR_PTR(-ENOMEM);
7716
2384d2b3
SY		 7717 allocate_vpid(vmx);
7718
fb3f0f51
RR		 7719 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7720 if (err)
7721 goto free_vcpu;
965b58a5 7722
a2fa3e9f 7723 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7724 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7725 > PAGE_SIZE);
0123be42 7726
be6d05cf 7727 err = -ENOMEM;
fb3f0f51 7728 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7729 goto uninit_vcpu;
7730 }
965b58a5 7731
d462b819
NHE		 7732 vmx->loaded_vmcs = &vmx->vmcs01;
7733 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7734 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7735 goto free_msrs;
d462b819
NHE		 7736 if (!vmm_exclusive)
7737 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7738 loaded_vmcs_init(vmx->loaded_vmcs);
7739 if (!vmm_exclusive)
7740 kvm_cpu_vmxoff();
a2fa3e9f 7741
15ad7146
AK		 7742 cpu = get_cpu();
7743 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7744 vmx->vcpu.cpu = cpu;
8b9cf98c 7745 err = vmx_vcpu_setup(vmx);
fb3f0f51 7746 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7747 put_cpu();
fb3f0f51
RR		 7748 if (err)
7749 goto free_vmcs;
a63cb560 7750 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7751 err = alloc_apic_access_page(kvm);
7752 if (err)
5e4a0b3c 7753 goto free_vmcs;
a63cb560 7754 }
fb3f0f51 7755
b927a3ce
SY		 7756 if (enable_ept) {
7757 if (!kvm->arch.ept_identity_map_addr)
7758 kvm->arch.ept_identity_map_addr =
7759 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7760 err = -ENOMEM;
b7ebfb05
SY		 7761 if (alloc_identity_pagetable(kvm) != 0)
7762 goto free_vmcs;
93ea5388
GN		 7763 if (!init_rmode_identity_map(kvm))
7764 goto free_vmcs;
b927a3ce 7765 }
b7ebfb05 7766
a9d30f33
NHE		 7767 vmx->nested.current_vmptr = -1ull;
7768 vmx->nested.current_vmcs12 = NULL;
7769
fb3f0f51
RR		 7770 return &vmx->vcpu;
7771
7772free_vmcs:
5f3fbc34 7773 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7774free_msrs:
fb3f0f51
RR		 7775 kfree(vmx->guest_msrs);
7776uninit_vcpu:
7777 kvm_vcpu_uninit(&vmx->vcpu);
7778free_vcpu:
cdbecfc3 7779 free_vpid(vmx);
a4770347 7780 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7781 return ERR_PTR(err);
6aa8b732
AK		 7782}
7783
002c7f7c
YS		 7784static void __init vmx_check_processor_compat(void *rtn)
7785{
7786 struct vmcs_config vmcs_conf;
7787
7788 *(int *)rtn = 0;
7789 if (setup_vmcs_config(&vmcs_conf) < 0)
7790 *(int *)rtn = -EIO;
7791 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7792 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7793 smp_processor_id());
7794 *(int *)rtn = -EIO;
7795 }
7796}
7797
67253af5
SY		 7798static int get_ept_level(void)
7799{
7800 return VMX_EPT_DEFAULT_GAW + 1;
7801}
7802
4b12f0de 7803static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7804{
4b12f0de
SY		 7805 u64 ret;
7806
522c68c4
SY		 7807 /* For VT-d and EPT combination
7808 * 1. MMIO: always map as UC
7809 * 2. EPT with VT-d:
7810 * a. VT-d without snooping control feature: can't guarantee the
7811 * result, try to trust guest.
7812 * b. VT-d with snooping control feature: snooping control feature of
7813 * VT-d engine can guarantee the cache correctness. Just set it
7814 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7815 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7816 * consistent with host MTRR
7817 */
4b12f0de
SY		 7818 if (is_mmio)
7819 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7820 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7821 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7822 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7823 else
522c68c4 7824 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7825 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7826
7827 return ret;
64d4d521
SY		 7828}
7829
17cc3935 7830static int vmx_get_lpage_level(void)
344f414f 7831{
878403b7
SY		 7832 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7833 return PT_DIRECTORY_LEVEL;
7834 else
7835 /* For shadow and EPT supported 1GB page */
7836 return PT_PDPE_LEVEL;
344f414f
JR		 7837}
7838
0e851880
SY		 7839static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7840{
4e47c7a6
SY		 7841 struct kvm_cpuid_entry2 *best;
7842 struct vcpu_vmx *vmx = to_vmx(vcpu);
7843 u32 exec_control;
7844
7845 vmx->rdtscp_enabled = false;
7846 if (vmx_rdtscp_supported()) {
7847 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7848 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7849 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7850 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7851 vmx->rdtscp_enabled = true;
7852 else {
7853 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7854 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7855 exec_control);
7856 }
7857 }
7858 }
ad756a16 7859
ad756a16
MJ		 7860 /* Exposing INVPCID only when PCID is exposed */
7861 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7862 if (vmx_invpcid_supported() &&
4f977045 7863 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7864 guest_cpuid_has_pcid(vcpu)) {
29282fde 7865 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7866 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7867 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7868 exec_control);
7869 } else {
29282fde
TI		 7870 if (cpu_has_secondary_exec_ctrls()) {
7871 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7872 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7873 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7874 exec_control);
7875 }
ad756a16 7876 if (best)
4f977045 7877 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7878 }
0e851880
SY		 7879}
7880
d4330ef2
JR		 7881static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7882{
7b8050f5
NHE		 7883 if (func == 1 && nested)
7884 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7885}
7886
25d92081
YZ		 7887static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7888 struct x86_exception *fault)
7889{
533558bc
JK		 7890 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7891 u32 exit_reason;
25d92081
YZ		 7892
7893 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7894 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7895 else
533558bc
JK		 7896 exit_reason = EXIT_REASON_EPT_VIOLATION;
7897 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7898 vmcs12->guest_physical_address = fault->address;
7899}
7900
155a97a3
NHE		 7901/* Callbacks for nested_ept_init_mmu_context: */
7902
7903static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7904{
7905 /* return the page table to be shadowed - in our case, EPT12 */
7906 return get_vmcs12(vcpu)->ept_pointer;
7907}
7908
8a3c1a33 7909static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7910{
8a3c1a33 7911 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7912 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7913
7914 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7915 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7916 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7917
7918 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7919}
7920
7921static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7922{
7923 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7924}
7925
feaf0c7d
GN		 7926static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7927 struct x86_exception *fault)
7928{
7929 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7930
7931 WARN_ON(!is_guest_mode(vcpu));
7932
7933 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7934 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7935 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7936 vmcs_read32(VM_EXIT_INTR_INFO),
7937 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7938 else
7939 kvm_inject_page_fault(vcpu, fault);
7940}
7941
a2bcba50
WL		 7942static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
7943 struct vmcs12 *vmcs12)
7944{
7945 struct vcpu_vmx *vmx = to_vmx(vcpu);
7946
7947 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 7948 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 7949 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 7950 return false;
7951
7952 /*
7953 * Translate L1 physical address to host physical
7954 * address for vmcs02. Keep the page pinned, so this
7955 * physical address remains valid. We keep a reference
7956 * to it so we can release it later.
7957 */
7958 if (vmx->nested.apic_access_page) /* shouldn't happen */
7959 nested_release_page(vmx->nested.apic_access_page);
7960 vmx->nested.apic_access_page =
7961 nested_get_page(vcpu, vmcs12->apic_access_addr);
7962 }
a7c0b07d
WL		 7963
7964 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
7965 /* TODO: Also verify bits beyond physical address width are 0 */
7966 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
7967 return false;
7968
7969 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
7970 nested_release_page(vmx->nested.virtual_apic_page);
7971 vmx->nested.virtual_apic_page =
7972 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
7973
7974 /*
7975 * Failing the vm entry is _not_ what the processor does
7976 * but it's basically the only possibility we have.
7977 * We could still enter the guest if CR8 load exits are
7978 * enabled, CR8 store exits are enabled, and virtualize APIC
7979 * access is disabled; in this case the processor would never
7980 * use the TPR shadow and we could simply clear the bit from
7981 * the execution control. But such a configuration is useless,
7982 * so let's keep the code simple.
7983 */
7984 if (!vmx->nested.virtual_apic_page)
7985 return false;
7986 }
7987
a2bcba50
WL		 7988 return true;
7989}
7990
f4124500
JK		 7991static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7992{
7993 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7994 struct vcpu_vmx *vmx = to_vmx(vcpu);
7995
7996 if (vcpu->arch.virtual_tsc_khz == 0)
7997 return;
7998
7999 /* Make sure short timeouts reliably trigger an immediate vmexit.
8000 * hrtimer_start does not guarantee this. */
8001 if (preemption_timeout <= 1) {
8002 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8003 return;
8004 }
8005
8006 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8007 preemption_timeout *= 1000000;
8008 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8009 hrtimer_start(&vmx->nested.preemption_timer,
8010 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8011}
8012
fe3ef05c
NHE		 8013/*
8014 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8015 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8016 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
8017 * guest in a way that will both be appropriate to L1's requests, and our
8018 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8019 * function also has additional necessary side-effects, like setting various
8020 * vcpu->arch fields.
8021 */
8022static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8023{
8024 struct vcpu_vmx *vmx = to_vmx(vcpu);
8025 u32 exec_control;
8026
8027 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8028 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8029 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8030 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8031 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8032 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8033 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8034 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8035 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8036 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8037 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8038 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8039 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8040 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8041 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8042 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8043 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8044 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8045 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8046 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8047 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8048 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8049 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8050 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8051 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8052 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8053 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8054 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8055 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8056 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8057 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8058 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8059 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8060 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8061 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8062 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8063
2996fca0
JK		 8064 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8065 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8066 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8067 } else {
8068 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8069 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8070 }
fe3ef05c
NHE		 8071 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8072 vmcs12->vm_entry_intr_info_field);
8073 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8074 vmcs12->vm_entry_exception_error_code);
8075 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8076 vmcs12->vm_entry_instruction_len);
8077 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8078 vmcs12->guest_interruptibility_info);
fe3ef05c 8079 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8080 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8081 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8082 vmcs12->guest_pending_dbg_exceptions);
8083 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8084 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8085
8086 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8087
f4124500
JK		 8088 exec_control = vmcs12->pin_based_vm_exec_control;
8089 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8090 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8091 PIN_BASED_POSTED_INTR);
f4124500 8092 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8093
f4124500
JK		 8094 vmx->nested.preemption_timer_expired = false;
8095 if (nested_cpu_has_preemption_timer(vmcs12))
8096 vmx_start_preemption_timer(vcpu);
0238ea91 8097
fe3ef05c
NHE		 8098 /*
8099 * Whether page-faults are trapped is determined by a combination of
8100 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8101 * If enable_ept, L0 doesn't care about page faults and we should
8102 * set all of these to L1's desires. However, if !enable_ept, L0 does
8103 * care about (at least some) page faults, and because it is not easy
8104 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8105 * to exit on each and every L2 page fault. This is done by setting
8106 * MASK=MATCH=0 and (see below) EB.PF=1.
8107 * Note that below we don't need special code to set EB.PF beyond the
8108 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8109 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8110 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8111 *
8112 * A problem with this approach (when !enable_ept) is that L1 may be
8113 * injected with more page faults than it asked for. This could have
8114 * caused problems, but in practice existing hypervisors don't care.
8115 * To fix this, we will need to emulate the PFEC checking (on the L1
8116 * page tables), using walk_addr(), when injecting PFs to L1.
8117 */
8118 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8119 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8120 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8121 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8122
8123 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8124 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8125 if (!vmx->rdtscp_enabled)
8126 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8127 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8128 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8129 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8130 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8131 if (nested_cpu_has(vmcs12,
8132 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8133 exec_control |= vmcs12->secondary_vm_exec_control;
8134
8135 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8136 /*
8137 * If translation failed, no matter: This feature asks
8138 * to exit when accessing the given address, and if it
8139 * can never be accessed, this feature won't do
8140 * anything anyway.
8141 */
8142 if (!vmx->nested.apic_access_page)
8143 exec_control &=
8144 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8145 else
8146 vmcs_write64(APIC_ACCESS_ADDR,
8147 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8148 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8149 exec_control |=
8150 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8151 vmcs_write64(APIC_ACCESS_ADDR,
8152 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 8153 }
8154
8155 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8156 }
8157
8158
8159 /*
8160 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8161 * Some constant fields are set here by vmx_set_constant_host_state().
8162 * Other fields are different per CPU, and will be set later when
8163 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8164 */
a547c6db 8165 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8166
8167 /*
8168 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8169 * entry, but only if the current (host) sp changed from the value
8170 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8171 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8172 * here we just force the write to happen on entry.
8173 */
8174 vmx->host_rsp = 0;
8175
8176 exec_control = vmx_exec_control(vmx); /* L0's desires */
8177 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8178 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8179 exec_control &= ~CPU_BASED_TPR_SHADOW;
8180 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8181
8182 if (exec_control & CPU_BASED_TPR_SHADOW) {
8183 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8184 page_to_phys(vmx->nested.virtual_apic_page));
8185 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8186 }
8187
fe3ef05c
NHE		 8188 /*
8189 * Merging of IO and MSR bitmaps not currently supported.
8190 * Rather, exit every time.
8191 */
8192 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8193 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8194 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8195
8196 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8197
8198 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8199 * bitwise-or of what L1 wants to trap for L2, and what we want to
8200 * trap. Note that CR0.TS also needs updating - we do this later.
8201 */
8202 update_exception_bitmap(vcpu);
8203 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8204 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8205
8049d651
NHE		 8206 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8207 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8208 * bits are further modified by vmx_set_efer() below.
8209 */
f4124500 8210 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8211
8212 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8213 * emulated by vmx_set_efer(), below.
8214 */
2961e876 8215 vm_entry_controls_init(vmx,
8049d651
NHE		 8216 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8217 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8218 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8219
44811c02 8220 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8221 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8222 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8223 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8224 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8225
8226
8227 set_cr4_guest_host_mask(vmx);
8228
36be0b9d
PB		 8229 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8230 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8231
27fc51b2
NHE		 8232 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8233 vmcs_write64(TSC_OFFSET,
8234 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8235 else
8236 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8237
8238 if (enable_vpid) {
8239 /*
8240 * Trivially support vpid by letting L2s share their parent
8241 * L1's vpid. TODO: move to a more elaborate solution, giving
8242 * each L2 its own vpid and exposing the vpid feature to L1.
8243 */
8244 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8245 vmx_flush_tlb(vcpu);
8246 }
8247
155a97a3
NHE		 8248 if (nested_cpu_has_ept(vmcs12)) {
8249 kvm_mmu_unload(vcpu);
8250 nested_ept_init_mmu_context(vcpu);
8251 }
8252
fe3ef05c
NHE		 8253 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8254 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8255 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8256 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8257 else
8258 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8259 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8260 vmx_set_efer(vcpu, vcpu->arch.efer);
8261
8262 /*
8263 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8264 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8265 * The CR0_READ_SHADOW is what L2 should have expected to read given
8266 * the specifications by L1; It's not enough to take
8267 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8268 * have more bits than L1 expected.
8269 */
8270 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8271 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8272
8273 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8274 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8275
8276 /* shadow page tables on either EPT or shadow page tables */
8277 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8278 kvm_mmu_reset_context(vcpu);
8279
feaf0c7d
GN		 8280 if (!enable_ept)
8281 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8282
3633cfc3
NHE		 8283 /*
8284 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8285 */
8286 if (enable_ept) {
8287 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8288 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8289 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8290 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8291 }
8292
fe3ef05c
NHE		 8293 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8294 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8295}
8296
cd232ad0
NHE		 8297/*
8298 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8299 * for running an L2 nested guest.
8300 */
8301static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8302{
8303 struct vmcs12 *vmcs12;
8304 struct vcpu_vmx *vmx = to_vmx(vcpu);
8305 int cpu;
8306 struct loaded_vmcs *vmcs02;
384bb783 8307 bool ia32e;
cd232ad0
NHE		 8308
8309 if (!nested_vmx_check_permission(vcpu) ||
8310 !nested_vmx_check_vmcs12(vcpu))
8311 return 1;
8312
8313 skip_emulated_instruction(vcpu);
8314 vmcs12 = get_vmcs12(vcpu);
8315
012f83cb
AG		 8316 if (enable_shadow_vmcs)
8317 copy_shadow_to_vmcs12(vmx);
8318
7c177938
NHE		 8319 /*
8320 * The nested entry process starts with enforcing various prerequisites
8321 * on vmcs12 as required by the Intel SDM, and act appropriately when
8322 * they fail: As the SDM explains, some conditions should cause the
8323 * instruction to fail, while others will cause the instruction to seem
8324 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8325 * To speed up the normal (success) code path, we should avoid checking
8326 * for misconfigurations which will anyway be caught by the processor
8327 * when using the merged vmcs02.
8328 */
8329 if (vmcs12->launch_state == launch) {
8330 nested_vmx_failValid(vcpu,
8331 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8332 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8333 return 1;
8334 }
8335
6dfacadd
JK		 8336 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8337 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8338 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8339 return 1;
8340 }
8341
7c177938 8342 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8343 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8344 /*TODO: Also verify bits beyond physical address width are 0*/
8345 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8346 return 1;
8347 }
8348
a2bcba50 8349 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8350 /*TODO: Also verify bits beyond physical address width are 0*/
8351 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8352 return 1;
8353 }
8354
8355 if (vmcs12->vm_entry_msr_load_count > 0 ||
8356 vmcs12->vm_exit_msr_load_count > 0 ||
8357 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8358 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8359 __func__);
7c177938
NHE		 8360 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8361 return 1;
8362 }
8363
8364 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8365 nested_vmx_true_procbased_ctls_low,
8366 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8367 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8368 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8369 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8370 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8371 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8372 nested_vmx_true_exit_ctls_low,
8373 nested_vmx_exit_ctls_high) ||
7c177938 8374 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8375 nested_vmx_true_entry_ctls_low,
8376 nested_vmx_entry_ctls_high))
7c177938
NHE		 8377 {
8378 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8379 return 1;
8380 }
8381
8382 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8383 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8384 nested_vmx_failValid(vcpu,
8385 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8386 return 1;
8387 }
8388
92fbc7b1 8389 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8390 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8391 nested_vmx_entry_failure(vcpu, vmcs12,
8392 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8393 return 1;
8394 }
8395 if (vmcs12->vmcs_link_pointer != -1ull) {
8396 nested_vmx_entry_failure(vcpu, vmcs12,
8397 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8398 return 1;
8399 }
8400
384bb783 8401 /*
cb0c8cda 8402 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8403 * are performed on the field for the IA32_EFER MSR:
8404 * - Bits reserved in the IA32_EFER MSR must be 0.
8405 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8406 * the IA-32e mode guest VM-exit control. It must also be identical
8407 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8408 * CR0.PG) is 1.
8409 */
8410 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8411 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8412 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8413 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8414 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8415 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8416 nested_vmx_entry_failure(vcpu, vmcs12,
8417 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8418 return 1;
8419 }
8420 }
8421
8422 /*
8423 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8424 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8425 * the values of the LMA and LME bits in the field must each be that of
8426 * the host address-space size VM-exit control.
8427 */
8428 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8429 ia32e = (vmcs12->vm_exit_controls &
8430 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8431 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8432 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8433 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8434 nested_vmx_entry_failure(vcpu, vmcs12,
8435 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8436 return 1;
8437 }
8438 }
8439
7c177938
NHE		 8440 /*
8441 * We're finally done with prerequisite checking, and can start with
8442 * the nested entry.
8443 */
8444
cd232ad0
NHE		 8445 vmcs02 = nested_get_current_vmcs02(vmx);
8446 if (!vmcs02)
8447 return -ENOMEM;
8448
8449 enter_guest_mode(vcpu);
8450
8451 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8452
2996fca0
JK		 8453 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8454 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8455
cd232ad0
NHE		 8456 cpu = get_cpu();
8457 vmx->loaded_vmcs = vmcs02;
8458 vmx_vcpu_put(vcpu);
8459 vmx_vcpu_load(vcpu, cpu);
8460 vcpu->cpu = cpu;
8461 put_cpu();
8462
36c3cc42
JK		 8463 vmx_segment_cache_clear(vmx);
8464
cd232ad0
NHE		 8465 vmcs12->launch_state = 1;
8466
8467 prepare_vmcs02(vcpu, vmcs12);
8468
6dfacadd
JK		 8469 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8470 return kvm_emulate_halt(vcpu);
8471
7af40ad3
JK		 8472 vmx->nested.nested_run_pending = 1;
8473
cd232ad0
NHE		 8474 /*
8475 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8476 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8477 * returned as far as L1 is concerned. It will only return (and set
8478 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8479 */
8480 return 1;
8481}
8482
4704d0be
NHE		 8483/*
8484 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8485 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8486 * This function returns the new value we should put in vmcs12.guest_cr0.
8487 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8488 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8489 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8490 * didn't trap the bit, because if L1 did, so would L0).
8491 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8492 * been modified by L2, and L1 knows it. So just leave the old value of
8493 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8494 * isn't relevant, because if L0 traps this bit it can set it to anything.
8495 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8496 * changed these bits, and therefore they need to be updated, but L0
8497 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8498 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8499 */
8500static inline unsigned long
8501vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8502{
8503 return
8504 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8505 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8506 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8507 vcpu->arch.cr0_guest_owned_bits));
8508}
8509
8510static inline unsigned long
8511vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8512{
8513 return
8514 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8515 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8516 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8517 vcpu->arch.cr4_guest_owned_bits));
8518}
8519
5f3d5799
JK		 8520static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8521 struct vmcs12 *vmcs12)
8522{
8523 u32 idt_vectoring;
8524 unsigned int nr;
8525
851eb667 8526 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8527 nr = vcpu->arch.exception.nr;
8528 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8529
8530 if (kvm_exception_is_soft(nr)) {
8531 vmcs12->vm_exit_instruction_len =
8532 vcpu->arch.event_exit_inst_len;
8533 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8534 } else
8535 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8536
8537 if (vcpu->arch.exception.has_error_code) {
8538 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8539 vmcs12->idt_vectoring_error_code =
8540 vcpu->arch.exception.error_code;
8541 }
8542
8543 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8544 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8545 vmcs12->idt_vectoring_info_field =
8546 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8547 } else if (vcpu->arch.interrupt.pending) {
8548 nr = vcpu->arch.interrupt.nr;
8549 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8550
8551 if (vcpu->arch.interrupt.soft) {
8552 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8553 vmcs12->vm_entry_instruction_len =
8554 vcpu->arch.event_exit_inst_len;
8555 } else
8556 idt_vectoring |= INTR_TYPE_EXT_INTR;
8557
8558 vmcs12->idt_vectoring_info_field = idt_vectoring;
8559 }
8560}
8561
b6b8a145
JK		 8562static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8563{
8564 struct vcpu_vmx *vmx = to_vmx(vcpu);
8565
f4124500
JK		 8566 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8567 vmx->nested.preemption_timer_expired) {
8568 if (vmx->nested.nested_run_pending)
8569 return -EBUSY;
8570 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8571 return 0;
8572 }
8573
b6b8a145 8574 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8575 if (vmx->nested.nested_run_pending ||
8576 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8577 return -EBUSY;
8578 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8579 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8580 INTR_INFO_VALID_MASK, 0);
8581 /*
8582 * The NMI-triggered VM exit counts as injection:
8583 * clear this one and block further NMIs.
8584 */
8585 vcpu->arch.nmi_pending = 0;
8586 vmx_set_nmi_mask(vcpu, true);
8587 return 0;
8588 }
8589
8590 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8591 nested_exit_on_intr(vcpu)) {
8592 if (vmx->nested.nested_run_pending)
8593 return -EBUSY;
8594 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8595 }
8596
8597 return 0;
8598}
8599
f4124500
JK		 8600static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8601{
8602 ktime_t remaining =
8603 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8604 u64 value;
8605
8606 if (ktime_to_ns(remaining) <= 0)
8607 return 0;
8608
8609 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8610 do_div(value, 1000000);
8611 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8612}
8613
4704d0be
NHE		 8614/*
8615 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8616 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8617 * and this function updates it to reflect the changes to the guest state while
8618 * L2 was running (and perhaps made some exits which were handled directly by L0
8619 * without going back to L1), and to reflect the exit reason.
8620 * Note that we do not have to copy here all VMCS fields, just those that
8621 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8622 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8623 * which already writes to vmcs12 directly.
8624 */
533558bc
JK		 8625static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8626 u32 exit_reason, u32 exit_intr_info,
8627 unsigned long exit_qualification)
4704d0be
NHE		 8628{
8629 /* update guest state fields: */
8630 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8631 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8632
4704d0be
NHE		 8633 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8634 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8635 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8636
8637 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8638 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8639 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8640 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8641 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8642 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8643 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8644 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8645 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8646 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8647 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8648 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8649 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8650 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8651 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8652 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8653 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8654 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8655 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8656 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8657 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8658 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8659 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8660 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8661 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8662 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8663 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8664 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8665 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8666 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8667 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8668 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8669 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8670 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8671 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8672 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8673
4704d0be
NHE		 8674 vmcs12->guest_interruptibility_info =
8675 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8676 vmcs12->guest_pending_dbg_exceptions =
8677 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8678 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8679 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8680 else
8681 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8682
f4124500
JK		 8683 if (nested_cpu_has_preemption_timer(vmcs12)) {
8684 if (vmcs12->vm_exit_controls &
8685 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8686 vmcs12->vmx_preemption_timer_value =
8687 vmx_get_preemption_timer_value(vcpu);
8688 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8689 }
7854cbca 8690
3633cfc3
NHE		 8691 /*
8692 * In some cases (usually, nested EPT), L2 is allowed to change its
8693 * own CR3 without exiting. If it has changed it, we must keep it.
8694 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8695 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8696 *
8697 * Additionally, restore L2's PDPTR to vmcs12.
8698 */
8699 if (enable_ept) {
8700 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8701 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8702 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8703 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8704 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8705 }
8706
c18911a2
JK		 8707 vmcs12->vm_entry_controls =
8708 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8709 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8710
2996fca0
JK		 8711 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8712 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8713 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8714 }
8715
4704d0be
NHE		 8716 /* TODO: These cannot have changed unless we have MSR bitmaps and
8717 * the relevant bit asks not to trap the change */
b8c07d55 8718 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8719 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8720 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8721 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8722 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8723 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8724 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8725 if (vmx_mpx_supported())
8726 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8727
8728 /* update exit information fields: */
8729
533558bc
JK		 8730 vmcs12->vm_exit_reason = exit_reason;
8731 vmcs12->exit_qualification = exit_qualification;
4704d0be 8732
533558bc 8733 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8734 if ((vmcs12->vm_exit_intr_info &
8735 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8736 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8737 vmcs12->vm_exit_intr_error_code =
8738 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8739 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8740 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8741 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8742
5f3d5799
JK		 8743 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8744 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8745 * instead of reading the real value. */
4704d0be 8746 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8747
8748 /*
8749 * Transfer the event that L0 or L1 may wanted to inject into
8750 * L2 to IDT_VECTORING_INFO_FIELD.
8751 */
8752 vmcs12_save_pending_event(vcpu, vmcs12);
8753 }
8754
8755 /*
8756 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8757 * preserved above and would only end up incorrectly in L1.
8758 */
8759 vcpu->arch.nmi_injected = false;
8760 kvm_clear_exception_queue(vcpu);
8761 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8762}
8763
8764/*
8765 * A part of what we need to when the nested L2 guest exits and we want to
8766 * run its L1 parent, is to reset L1's guest state to the host state specified
8767 * in vmcs12.
8768 * This function is to be called not only on normal nested exit, but also on
8769 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8770 * Failures During or After Loading Guest State").
8771 * This function should be called when the active VMCS is L1's (vmcs01).
8772 */
733568f9
JK		 8773static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8774 struct vmcs12 *vmcs12)
4704d0be 8775{
21feb4eb
ACL		 8776 struct kvm_segment seg;
8777
4704d0be
NHE		 8778 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8779 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8780 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8781 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8782 else
8783 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8784 vmx_set_efer(vcpu, vcpu->arch.efer);
8785
8786 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8787 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8788 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8789 /*
8790 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8791 * actually changed, because it depends on the current state of
8792 * fpu_active (which may have changed).
8793 * Note that vmx_set_cr0 refers to efer set above.
8794 */
9e3e4dbf 8795 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8796 /*
8797 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8798 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8799 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8800 */
8801 update_exception_bitmap(vcpu);
8802 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8803 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8804
8805 /*
8806 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8807 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8808 */
8809 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8810 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8811
29bf08f1 8812 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8813
4704d0be
NHE		 8814 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8815 kvm_mmu_reset_context(vcpu);
8816
feaf0c7d
GN		 8817 if (!enable_ept)
8818 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8819
4704d0be
NHE		 8820 if (enable_vpid) {
8821 /*
8822 * Trivially support vpid by letting L2s share their parent
8823 * L1's vpid. TODO: move to a more elaborate solution, giving
8824 * each L2 its own vpid and exposing the vpid feature to L1.
8825 */
8826 vmx_flush_tlb(vcpu);
8827 }
8828
8829
8830 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8831 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8832 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8833 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8834 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8835
36be0b9d
PB		 8836 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8837 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8838 vmcs_write64(GUEST_BNDCFGS, 0);
8839
44811c02 8840 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8841 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8842 vcpu->arch.pat = vmcs12->host_ia32_pat;
8843 }
4704d0be
NHE		 8844 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8845 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8846 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8847
21feb4eb
ACL		 8848 /* Set L1 segment info according to Intel SDM
8849 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8850 seg = (struct kvm_segment) {
8851 .base = 0,
8852 .limit = 0xFFFFFFFF,
8853 .selector = vmcs12->host_cs_selector,
8854 .type = 11,
8855 .present = 1,
8856 .s = 1,
8857 .g = 1
8858 };
8859 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8860 seg.l = 1;
8861 else
8862 seg.db = 1;
8863 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8864 seg = (struct kvm_segment) {
8865 .base = 0,
8866 .limit = 0xFFFFFFFF,
8867 .type = 3,
8868 .present = 1,
8869 .s = 1,
8870 .db = 1,
8871 .g = 1
8872 };
8873 seg.selector = vmcs12->host_ds_selector;
8874 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8875 seg.selector = vmcs12->host_es_selector;
8876 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8877 seg.selector = vmcs12->host_ss_selector;
8878 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8879 seg.selector = vmcs12->host_fs_selector;
8880 seg.base = vmcs12->host_fs_base;
8881 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8882 seg.selector = vmcs12->host_gs_selector;
8883 seg.base = vmcs12->host_gs_base;
8884 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8885 seg = (struct kvm_segment) {
205befd9 8886 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8887 .limit = 0x67,
8888 .selector = vmcs12->host_tr_selector,
8889 .type = 11,
8890 .present = 1
8891 };
8892 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8893
503cd0c5
JK		 8894 kvm_set_dr(vcpu, 7, 0x400);
8895 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8896}
8897
8898/*
8899 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8900 * and modify vmcs12 to make it see what it would expect to see there if
8901 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8902 */
533558bc
JK		 8903static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8904 u32 exit_intr_info,
8905 unsigned long exit_qualification)
4704d0be
NHE		 8906{
8907 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 8908 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8909
5f3d5799
JK		 8910 /* trying to cancel vmlaunch/vmresume is a bug */
8911 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8912
4704d0be 8913 leave_guest_mode(vcpu);
533558bc
JK		 8914 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8915 exit_qualification);
4704d0be 8916
f3380ca5
WL		 8917 vmx_load_vmcs01(vcpu);
8918
77b0f5d6
BD		 8919 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8920 && nested_exit_intr_ack_set(vcpu)) {
8921 int irq = kvm_cpu_get_interrupt(vcpu);
8922 WARN_ON(irq < 0);
8923 vmcs12->vm_exit_intr_info = irq |
8924 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8925 }
8926
542060ea
JK		 8927 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8928 vmcs12->exit_qualification,
8929 vmcs12->idt_vectoring_info_field,
8930 vmcs12->vm_exit_intr_info,
8931 vmcs12->vm_exit_intr_error_code,
8932 KVM_ISA_VMX);
4704d0be 8933
2961e876
GN		 8934 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8935 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8936 vmx_segment_cache_clear(vmx);
8937
4704d0be
NHE		 8938 /* if no vmcs02 cache requested, remove the one we used */
8939 if (VMCS02_POOL_SIZE == 0)
8940 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8941
8942 load_vmcs12_host_state(vcpu, vmcs12);
8943
27fc51b2 8944 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8945 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8946
8947 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8948 vmx->host_rsp = 0;
8949
8950 /* Unpin physical memory we referred to in vmcs02 */
8951 if (vmx->nested.apic_access_page) {
8952 nested_release_page(vmx->nested.apic_access_page);
8953 vmx->nested.apic_access_page = 0;
8954 }
a7c0b07d
WL		 8955 if (vmx->nested.virtual_apic_page) {
8956 nested_release_page(vmx->nested.virtual_apic_page);
8957 vmx->nested.virtual_apic_page = 0;
8958 }
4704d0be
NHE		 8959
8960 /*
8961 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8962 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8963 * success or failure flag accordingly.
8964 */
8965 if (unlikely(vmx->fail)) {
8966 vmx->fail = 0;
8967 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8968 } else
8969 nested_vmx_succeed(vcpu);
012f83cb
AG		 8970 if (enable_shadow_vmcs)
8971 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8972
8973 /* in case we halted in L2 */
8974 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8975}
8976
42124925
JK		 8977/*
8978 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8979 */
8980static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8981{
8982 if (is_guest_mode(vcpu))
533558bc 8983 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8984 free_nested(to_vmx(vcpu));
8985}
8986
7c177938
NHE		 8987/*
8988 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8989 * 23.7 "VM-entry failures during or after loading guest state" (this also
8990 * lists the acceptable exit-reason and exit-qualification parameters).
8991 * It should only be called before L2 actually succeeded to run, and when
8992 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8993 */
8994static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8995 struct vmcs12 *vmcs12,
8996 u32 reason, unsigned long qualification)
8997{
8998 load_vmcs12_host_state(vcpu, vmcs12);
8999 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9000 vmcs12->exit_qualification = qualification;
9001 nested_vmx_succeed(vcpu);
012f83cb
AG		 9002 if (enable_shadow_vmcs)
9003 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9004}
9005
8a76d7f2
JR		 9006static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9007 struct x86_instruction_info *info,
9008 enum x86_intercept_stage stage)
9009{
9010 return X86EMUL_CONTINUE;
9011}
9012
ae97a3b8
RK		 9013void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
9014{
b4a2d31d
RK		 9015 if (ple_gap)
9016 shrink_ple_window(vcpu);
ae97a3b8
RK		 9017}
9018
cbdd1bea 9019static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9020 .cpu_has_kvm_support = cpu_has_kvm_support,
9021 .disabled_by_bios = vmx_disabled_by_bios,
9022 .hardware_setup = hardware_setup,
9023 .hardware_unsetup = hardware_unsetup,
002c7f7c 9024 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9025 .hardware_enable = hardware_enable,
9026 .hardware_disable = hardware_disable,
04547156 9027 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9028
9029 .vcpu_create = vmx_create_vcpu,
9030 .vcpu_free = vmx_free_vcpu,
04d2cc77 9031 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9032
04d2cc77 9033 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9034 .vcpu_load = vmx_vcpu_load,
9035 .vcpu_put = vmx_vcpu_put,
9036
c8639010 9037 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9038 .get_msr = vmx_get_msr,
9039 .set_msr = vmx_set_msr,
9040 .get_segment_base = vmx_get_segment_base,
9041 .get_segment = vmx_get_segment,
9042 .set_segment = vmx_set_segment,
2e4d2653 9043 .get_cpl = vmx_get_cpl,
6aa8b732 9044 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9045 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9046 .decache_cr3 = vmx_decache_cr3,
25c4c276 9047 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9048 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9049 .set_cr3 = vmx_set_cr3,
9050 .set_cr4 = vmx_set_cr4,
6aa8b732 9051 .set_efer = vmx_set_efer,
6aa8b732
AK		 9052 .get_idt = vmx_get_idt,
9053 .set_idt = vmx_set_idt,
9054 .get_gdt = vmx_get_gdt,
9055 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9056 .get_dr6 = vmx_get_dr6,
9057 .set_dr6 = vmx_set_dr6,
020df079 9058 .set_dr7 = vmx_set_dr7,
81908bf4 9059 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9060 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9061 .get_rflags = vmx_get_rflags,
9062 .set_rflags = vmx_set_rflags,
02daab21 9063 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9064
9065 .tlb_flush = vmx_flush_tlb,
6aa8b732 9066
6aa8b732 9067 .run = vmx_vcpu_run,
6062d012 9068 .handle_exit = vmx_handle_exit,
6aa8b732 9069 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9070 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9071 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9072 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9073 .set_irq = vmx_inject_irq,
95ba8273 9074 .set_nmi = vmx_inject_nmi,
298101da 9075 .queue_exception = vmx_queue_exception,
b463a6f7 9076 .cancel_injection = vmx_cancel_injection,
78646121 9077 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9078 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9079 .get_nmi_mask = vmx_get_nmi_mask,
9080 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9081 .enable_nmi_window = enable_nmi_window,
9082 .enable_irq_window = enable_irq_window,
9083 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9084 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 9085 .vm_has_apicv = vmx_vm_has_apicv,
9086 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9087 .hwapic_irr_update = vmx_hwapic_irr_update,
9088 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9089 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9090 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9091
cbc94022 9092 .set_tss_addr = vmx_set_tss_addr,
67253af5 9093 .get_tdp_level = get_ept_level,
4b12f0de 9094 .get_mt_mask = vmx_get_mt_mask,
229456fc 9095
586f9607 9096 .get_exit_info = vmx_get_exit_info,
586f9607 9097
17cc3935 9098 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9099
9100 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9101
9102 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9103 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9104
9105 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9106
9107 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9108
4051b188 9109 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9110 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9111 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9112 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9113 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9114 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9115
9116 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9117
9118 .check_intercept = vmx_check_intercept,
a547c6db 9119 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9120 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9121
9122 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9123
9124 .sched_in = vmx_sched_in,
6aa8b732
AK		 9125};
9126
9127static int __init vmx_init(void)
9128{
8d14695f 9129 int r, i, msr;
26bb0981
AK		 9130
9131 rdmsrl_safe(MSR_EFER, &host_efer);
9132
03916db9 9133 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
26bb0981 9134 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 9135
3e7c73e9 9136 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 9137 if (!vmx_io_bitmap_a)
9138 return -ENOMEM;
9139
2106a548
GC		 9140 r = -ENOMEM;
9141
3e7c73e9 9142 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9143 if (!vmx_io_bitmap_b)
fdef3ad1 9144 goto out;
fdef3ad1 9145
5897297b 9146 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9147 if (!vmx_msr_bitmap_legacy)
25c5f225 9148 goto out1;
2106a548 9149
8d14695f
YZ		 9150 vmx_msr_bitmap_legacy_x2apic =
9151 (unsigned long *)__get_free_page(GFP_KERNEL);
9152 if (!vmx_msr_bitmap_legacy_x2apic)
9153 goto out2;
25c5f225 9154
5897297b 9155 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9156 if (!vmx_msr_bitmap_longmode)
8d14695f 9157 goto out3;
2106a548 9158
8d14695f
YZ		 9159 vmx_msr_bitmap_longmode_x2apic =
9160 (unsigned long *)__get_free_page(GFP_KERNEL);
9161 if (!vmx_msr_bitmap_longmode_x2apic)
9162 goto out4;
4607c2d7
AG		 9163 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9164 if (!vmx_vmread_bitmap)
9165 goto out5;
9166
9167 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9168 if (!vmx_vmwrite_bitmap)
9169 goto out6;
9170
9171 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9172 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 9173
fdef3ad1
HQ		 9174 /*
9175 * Allow direct access to the PC debug port (it is often used for I/O
9176 * delays, but the vmexits simply slow things down).
9177 */
3e7c73e9
AK		 9178 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9179 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 9180
3e7c73e9 9181 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 9182
5897297b
AK		 9183 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9184 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 9185
2384d2b3
SY		 9186 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9187
0ee75bea
AK		 9188 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9189 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9190 if (r)
4607c2d7 9191 goto out7;
25c5f225 9192
8f536b76
ZY		 9193#ifdef CONFIG_KEXEC
9194 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9195 crash_vmclear_local_loaded_vmcss);
9196#endif
9197
5897297b
AK		 9198 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9199 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9200 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9201 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9202 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9203 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 9204 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9205
8d14695f
YZ		 9206 memcpy(vmx_msr_bitmap_legacy_x2apic,
9207 vmx_msr_bitmap_legacy, PAGE_SIZE);
9208 memcpy(vmx_msr_bitmap_longmode_x2apic,
9209 vmx_msr_bitmap_longmode, PAGE_SIZE);
9210
01e439be 9211 if (enable_apicv) {
8d14695f
YZ		 9212 for (msr = 0x800; msr <= 0x8ff; msr++)
9213 vmx_disable_intercept_msr_read_x2apic(msr);
9214
9215 /* According SDM, in x2apic mode, the whole id reg is used.
9216 * But in KVM, it only use the highest eight bits. Need to
9217 * intercept it */
9218 vmx_enable_intercept_msr_read_x2apic(0x802);
9219 /* TMCCT */
9220 vmx_enable_intercept_msr_read_x2apic(0x839);
9221 /* TPR */
9222 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9223 /* EOI */
9224 vmx_disable_intercept_msr_write_x2apic(0x80b);
9225 /* SELF-IPI */
9226 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9227 }
fdef3ad1 9228
089d034e 9229 if (enable_ept) {
3f6d8c8a
XH		 9230 kvm_mmu_set_mask_ptes(0ull,
9231 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9232 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9233 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9234 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9235 kvm_enable_tdp();
9236 } else
9237 kvm_disable_tdp();
1439442c 9238
b4a2d31d
RK		 9239 update_ple_window_actual_max();
9240
fdef3ad1
HQ		 9241 return 0;
9242
4607c2d7
AG		 9243out7:
9244 free_page((unsigned long)vmx_vmwrite_bitmap);
9245out6:
9246 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9247out5:
9248 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9249out4:
5897297b 9250 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9251out3:
9252 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9253out2:
5897297b 9254 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9255out1:
3e7c73e9 9256 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9257out:
3e7c73e9 9258 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9259 return r;
6aa8b732
AK		 9260}
9261
9262static void __exit vmx_exit(void)
9263{
8d14695f
YZ		 9264 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9265 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9266 free_page((unsigned long)vmx_msr_bitmap_legacy);
9267 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9268 free_page((unsigned long)vmx_io_bitmap_b);
9269 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9270 free_page((unsigned long)vmx_vmwrite_bitmap);
9271 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9272
8f536b76 9273#ifdef CONFIG_KEXEC
3b63a43f 9274 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9275 synchronize_rcu();
9276#endif
9277
cb498ea2 9278 kvm_exit();
6aa8b732
AK		 9279}
9280
9281module_init(vmx_init)
9282module_exit(vmx_exit)
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