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target-i386: Define structs for layout of xsave area
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
bdeec802 44#ifndef CONFIG_USER_ONLY
2001d0cd 45#include "exec/address-spaces.h"
741da0d3 46#include "hw/hw.h"
0d09e41a 47#include "hw/xen/xen.h"
0d09e41a 48#include "hw/i386/apic_internal.h"
bdeec802
IM		 49#endif
50
5e891bf8
EH		 51
52/* Cache topology CPUID constants: */
53
54/* CPUID Leaf 2 Descriptors */
55
56#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57#define CPUID_2_L1I_32KB_8WAY_64B 0x30
58#define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61/* CPUID Leaf 4 constants: */
62
63/* EAX: */
64#define CPUID_4_TYPE_DCACHE 1
65#define CPUID_4_TYPE_ICACHE 2
66#define CPUID_4_TYPE_UNIFIED 3
67
68#define CPUID_4_LEVEL(l) ((l) << 5)
69
70#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71#define CPUID_4_FULLY_ASSOC (1 << 9)
72
73/* EDX: */
74#define CPUID_4_NO_INVD_SHARING (1 << 0)
75#define CPUID_4_INCLUSIVE (1 << 1)
76#define CPUID_4_COMPLEX_IDX (1 << 2)
77
78#define ASSOC_FULL 0xFF
79
80/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95/* Definitions of the hardcoded cache entries we expose: */
96
97/* L1 data cache: */
98#define L1D_LINE_SIZE 64
99#define L1D_ASSOCIATIVITY 8
100#define L1D_SETS 64
101#define L1D_PARTITIONS 1
102/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105#define L1D_LINES_PER_TAG 1
106#define L1D_SIZE_KB_AMD 64
107#define L1D_ASSOCIATIVITY_AMD 2
108
109/* L1 instruction cache: */
110#define L1I_LINE_SIZE 64
111#define L1I_ASSOCIATIVITY 8
112#define L1I_SETS 64
113#define L1I_PARTITIONS 1
114/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117#define L1I_LINES_PER_TAG 1
118#define L1I_SIZE_KB_AMD 64
119#define L1I_ASSOCIATIVITY_AMD 2
120
121/* Level 2 unified cache: */
122#define L2_LINE_SIZE 64
123#define L2_ASSOCIATIVITY 16
124#define L2_SETS 4096
125#define L2_PARTITIONS 1
126/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130#define L2_LINES_PER_TAG 1
131#define L2_SIZE_KB_AMD 512
132
133/* No L3 cache: */
134#define L3_SIZE_KB 0 /* disabled */
135#define L3_ASSOCIATIVITY 0 /* disabled */
136#define L3_LINES_PER_TAG 0 /* disabled */
137#define L3_LINE_SIZE 0 /* disabled */
138
139/* TLB definitions: */
140
141#define L1_DTLB_2M_ASSOC 1
142#define L1_DTLB_2M_ENTRIES 255
143#define L1_DTLB_4K_ASSOC 1
144#define L1_DTLB_4K_ENTRIES 255
145
146#define L1_ITLB_2M_ASSOC 1
147#define L1_ITLB_2M_ENTRIES 255
148#define L1_ITLB_4K_ASSOC 1
149#define L1_ITLB_4K_ENTRIES 255
150
151#define L2_DTLB_2M_ASSOC 0 /* disabled */
152#define L2_DTLB_2M_ENTRIES 0 /* disabled */
153#define L2_DTLB_4K_ASSOC 4
154#define L2_DTLB_4K_ENTRIES 512
155
156#define L2_ITLB_2M_ASSOC 0 /* disabled */
157#define L2_ITLB_2M_ENTRIES 0 /* disabled */
158#define L2_ITLB_4K_ASSOC 4
159#define L2_ITLB_4K_ENTRIES 512
160
161
162
99b88a17
IM		 163static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165{
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173}
174
c6dc6f63
AP		 175/* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188};
189static const char *ext_feature_name[] = {
f370be3c 190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 191 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 192 "tm2", "ssse3", "cid", NULL,
e117f772 193 "fma", "cx16", "xtpr", "pdcm",
434acb81 194 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 196 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 197 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 198};
3b671a40
EH		 199/* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
c6dc6f63 204static const char *ext2_feature_name[] = {
3b671a40
EH		 205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 212 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 213};
214static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 217 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 222 NULL, NULL, NULL, NULL,
223};
224
89e49c8b
EH		 225static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234};
235
c6dc6f63 236static const char *kvm_feature_name[] = {
c3d39807 237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
8248c36a 243 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 244 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 245};
246
296acb64
JR		 247static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256};
257
a9321a4d 258static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 259 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
f7fda280
XG		 261 "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
262 "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 263};
264
f74eefe0
HH		 265static const char *cpuid_7_0_ecx_feature_name[] = {
266 NULL, NULL, NULL, "pku",
267 "ospke", NULL, NULL, NULL,
268 NULL, NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274};
275
303752a9
MT		 276static const char *cpuid_apm_edx_feature_name[] = {
277 NULL, NULL, NULL, NULL,
278 NULL, NULL, NULL, NULL,
279 "invtsc", NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285};
286
0bb0b2d2
PB		 287static const char *cpuid_xsave_feature_name[] = {
288 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
289 NULL, NULL, NULL, NULL,
290 NULL, NULL, NULL, NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296};
297
28b8e4d0
JK		 298static const char *cpuid_6_feature_name[] = {
299 NULL, NULL, "arat", NULL,
300 NULL, NULL, NULL, NULL,
301 NULL, NULL, NULL, NULL,
302 NULL, NULL, NULL, NULL,
303 NULL, NULL, NULL, NULL,
304 NULL, NULL, NULL, NULL,
305 NULL, NULL, NULL, NULL,
306 NULL, NULL, NULL, NULL,
307};
308
621626ce
EH		 309#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
310#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
311 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
312#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
313 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
314 CPUID_PSE36 | CPUID_FXSR)
315#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
316#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
317 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
318 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
319 CPUID_PAE | CPUID_SEP | CPUID_APIC)
320
321#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
322 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
323 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
324 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 325 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 326 /* partly implemented:
327 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
328 /* missing:
329 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
330#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
331 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
332 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 333 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 334 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
335 /* missing:
336 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
337 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
338 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 339 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
340 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 341
342#ifdef TARGET_X86_64
343#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
344#else
345#define TCG_EXT2_X86_64_FEATURES 0
346#endif
347
348#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
349 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
350 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
351 TCG_EXT2_X86_64_FEATURES)
352#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
353 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
354#define TCG_EXT4_FEATURES 0
355#define TCG_SVM_FEATURES 0
356#define TCG_KVM_FEATURES 0
357#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 358 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
359 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
07929f2a 360 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE)
621626ce 361 /* missing:
07929f2a 362 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
621626ce
EH		 363 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
364 CPUID_7_0_EBX_RDSEED */
0f70ed47 365#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 366#define TCG_APM_FEATURES 0
28b8e4d0 367#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 368#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
369 /* missing:
370 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 371
5ef57876
EH		 372typedef struct FeatureWordInfo {
373 const char **feat_names;
04d104b6
EH		 374 uint32_t cpuid_eax; /* Input EAX for CPUID */
375 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
376 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
377 int cpuid_reg; /* output register (R_* constant) */
37ce3522 378 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 379 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 380} FeatureWordInfo;
381
382static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 383 [FEAT_1_EDX] = {
384 .feat_names = feature_name,
385 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 386 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 387 },
388 [FEAT_1_ECX] = {
389 .feat_names = ext_feature_name,
390 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 391 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 392 },
393 [FEAT_8000_0001_EDX] = {
394 .feat_names = ext2_feature_name,
395 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 396 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 397 },
398 [FEAT_8000_0001_ECX] = {
399 .feat_names = ext3_feature_name,
400 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 401 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 402 },
89e49c8b
EH		 403 [FEAT_C000_0001_EDX] = {
404 .feat_names = ext4_feature_name,
405 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 406 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 407 },
bffd67b0
EH		 408 [FEAT_KVM] = {
409 .feat_names = kvm_feature_name,
410 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 411 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 412 },
413 [FEAT_SVM] = {
414 .feat_names = svm_feature_name,
415 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 416 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 417 },
418 [FEAT_7_0_EBX] = {
419 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 420 .cpuid_eax = 7,
421 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
422 .cpuid_reg = R_EBX,
37ce3522 423 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 424 },
f74eefe0
HH		 425 [FEAT_7_0_ECX] = {
426 .feat_names = cpuid_7_0_ecx_feature_name,
427 .cpuid_eax = 7,
428 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
429 .cpuid_reg = R_ECX,
430 .tcg_features = TCG_7_0_ECX_FEATURES,
431 },
303752a9
MT		 432 [FEAT_8000_0007_EDX] = {
433 .feat_names = cpuid_apm_edx_feature_name,
434 .cpuid_eax = 0x80000007,
435 .cpuid_reg = R_EDX,
436 .tcg_features = TCG_APM_FEATURES,
437 .unmigratable_flags = CPUID_APM_INVTSC,
438 },
0bb0b2d2
PB		 439 [FEAT_XSAVE] = {
440 .feat_names = cpuid_xsave_feature_name,
441 .cpuid_eax = 0xd,
442 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
443 .cpuid_reg = R_EAX,
c9cfe8f9 444 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 445 },
28b8e4d0
JK		 446 [FEAT_6_EAX] = {
447 .feat_names = cpuid_6_feature_name,
448 .cpuid_eax = 6, .cpuid_reg = R_EAX,
449 .tcg_features = TCG_6_EAX_FEATURES,
450 },
5ef57876
EH		 451};
452
8e8aba50
EH		 453typedef struct X86RegisterInfo32 {
454 /* Name of register */
455 const char *name;
456 /* QAPI enum value register */
457 X86CPURegister32 qapi_enum;
458} X86RegisterInfo32;
459
460#define REGISTER(reg) \
5d371f41 461 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 462static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 463 REGISTER(EAX),
464 REGISTER(ECX),
465 REGISTER(EDX),
466 REGISTER(EBX),
467 REGISTER(ESP),
468 REGISTER(EBP),
469 REGISTER(ESI),
470 REGISTER(EDI),
471};
472#undef REGISTER
473
f4f1110e 474const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB		 475 [XSTATE_YMM_BIT] =
476 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
33f373d7 477 .offset = 0x240, .size = 0x100 },
cfc3b074
PB		 478 [XSTATE_BNDREGS_BIT] =
479 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
79e9ebeb 480 .offset = 0x3c0, .size = 0x40 },
cfc3b074
PB		 481 [XSTATE_BNDCSR_BIT] =
482 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
b0f15a5d 483 .offset = 0x400, .size = 0x40 },
cfc3b074
PB		 484 [XSTATE_OPMASK_BIT] =
485 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
9aecd6f8 486 .offset = 0x440, .size = 0x40 },
cfc3b074
PB		 487 [XSTATE_ZMM_Hi256_BIT] =
488 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
9aecd6f8 489 .offset = 0x480, .size = 0x200 },
cfc3b074
PB		 490 [XSTATE_Hi16_ZMM_BIT] =
491 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
9aecd6f8 492 .offset = 0x680, .size = 0x400 },
cfc3b074
PB		 493 [XSTATE_PKRU_BIT] =
494 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
f74eefe0 495 .offset = 0xA80, .size = 0x8 },
2560f19f 496};
8e8aba50 497
8b4beddc
EH		 498const char *get_register_name_32(unsigned int reg)
499{
31ccdde2 500 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 501 return NULL;
502 }
8e8aba50 503 return x86_reg_info_32[reg].name;
8b4beddc
EH		 504}
505
84f1b92f
EH		 506/*
507 * Returns the set of feature flags that are supported and migratable by
508 * QEMU, for a given FeatureWord.
509 */
510static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
511{
512 FeatureWordInfo *wi = &feature_word_info[w];
513 uint32_t r = 0;
514 int i;
515
516 for (i = 0; i < 32; i++) {
517 uint32_t f = 1U << i;
518 /* If the feature name is unknown, it is not supported by QEMU yet */
519 if (!wi->feat_names[i]) {
520 continue;
521 }
522 /* Skip features known to QEMU, but explicitly marked as unmigratable */
523 if (wi->unmigratable_flags & f) {
524 continue;
525 }
526 r |= f;
527 }
528 return r;
529}
530
bb44e0d1
JK		 531void host_cpuid(uint32_t function, uint32_t count,
532 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 533{
a1fd24af
AL		 534 uint32_t vec[4];
535
536#ifdef __x86_64__
537 asm volatile("cpuid"
538 : "=a"(vec[0]), "=b"(vec[1]),
539 "=c"(vec[2]), "=d"(vec[3])
540 : "0"(function), "c"(count) : "cc");
c1f41226 541#elif defined(__i386__)
a1fd24af
AL		 542 asm volatile("pusha \n\t"
543 "cpuid \n\t"
544 "mov %%eax, 0(%2) \n\t"
545 "mov %%ebx, 4(%2) \n\t"
546 "mov %%ecx, 8(%2) \n\t"
547 "mov %%edx, 12(%2) \n\t"
548 "popa"
549 : : "a"(function), "c"(count), "S"(vec)
550 : "memory", "cc");
c1f41226
EH		 551#else
552 abort();
a1fd24af
AL		 553#endif
554
bdde476a 555 if (eax)
a1fd24af 556 *eax = vec[0];
bdde476a 557 if (ebx)
a1fd24af 558 *ebx = vec[1];
bdde476a 559 if (ecx)
a1fd24af 560 *ecx = vec[2];
bdde476a 561 if (edx)
a1fd24af 562 *edx = vec[3];
bdde476a 563}
c6dc6f63
AP		 564
565#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
566
567/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
568 * a substring. ex if !NULL points to the first char after a substring,
569 * otherwise the string is assumed to sized by a terminating nul.
570 * Return lexical ordering of *s1:*s2.
571 */
8f9d989c
CF		 572static int sstrcmp(const char *s1, const char *e1,
573 const char *s2, const char *e2)
c6dc6f63
AP		 574{
575 for (;;) {
576 if (!*s1 || !*s2 || *s1 != *s2)
577 return (*s1 - *s2);
578 ++s1, ++s2;
579 if (s1 == e1 && s2 == e2)
580 return (0);
581 else if (s1 == e1)
582 return (*s2);
583 else if (s2 == e2)
584 return (*s1);
585 }
586}
587
588/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
589 * '|' delimited (possibly empty) strings in which case search for a match
590 * within the alternatives proceeds left to right. Return 0 for success,
591 * non-zero otherwise.
592 */
593static int altcmp(const char *s, const char *e, const char *altstr)
594{
595 const char *p, *q;
596
597 for (q = p = altstr; ; ) {
598 while (*p && *p != '|')
599 ++p;
600 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
601 return (0);
602 if (!*p)
603 return (1);
604 else
605 q = ++p;
606 }
607}
608
609/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 610 * *pval and return true, otherwise return false
c6dc6f63 611 */
e41e0fc6
JK		 612static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
613 const char **featureset)
c6dc6f63
AP		 614{
615 uint32_t mask;
616 const char **ppc;
e41e0fc6 617 bool found = false;
c6dc6f63 618
e41e0fc6 619 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 620 if (*ppc && !altcmp(s, e, *ppc)) {
621 *pval |= mask;
e41e0fc6 622 found = true;
c6dc6f63 623 }
e41e0fc6
JK		 624 }
625 return found;
c6dc6f63
AP		 626}
627
5ef57876 628static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 629 FeatureWordArray words,
630 Error **errp)
c6dc6f63 631{
5ef57876
EH		 632 FeatureWord w;
633 for (w = 0; w < FEATURE_WORDS; w++) {
634 FeatureWordInfo *wi = &feature_word_info[w];
635 if (wi->feat_names &&
636 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
637 break;
638 }
639 }
640 if (w == FEATURE_WORDS) {
c00c94ab 641 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 642 }
c6dc6f63
AP		 643}
644
d940ee9b
EH		 645/* CPU class name definitions: */
646
647#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
648#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
649
650/* Return type name for a given CPU model name
651 * Caller is responsible for freeing the returned string.
652 */
653static char *x86_cpu_type_name(const char *model_name)
654{
655 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
656}
657
500050d1
AF		 658static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
659{
d940ee9b
EH		 660 ObjectClass *oc;
661 char *typename;
662
500050d1
AF		 663 if (cpu_model == NULL) {
664 return NULL;
665 }
666
d940ee9b
EH		 667 typename = x86_cpu_type_name(cpu_model);
668 oc = object_class_by_name(typename);
669 g_free(typename);
670 return oc;
500050d1
AF		 671}
672
d940ee9b 673struct X86CPUDefinition {
c6dc6f63
AP		 674 const char *name;
675 uint32_t level;
90e4b0c3
EH		 676 uint32_t xlevel;
677 uint32_t xlevel2;
99b88a17
IM		 678 /* vendor is zero-terminated, 12 character ASCII string */
679 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 680 int family;
681 int model;
682 int stepping;
0514ef2f 683 FeatureWordArray features;
c6dc6f63 684 char model_id[48];
d940ee9b 685};
c6dc6f63 686
9576de75 687static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 688 {
689 .name = "qemu64",
3046bb5d 690 .level = 0xd,
99b88a17 691 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 692 .family = 6,
f8e6a11a 693 .model = 6,
c6dc6f63 694 .stepping = 3,
0514ef2f 695 .features[FEAT_1_EDX] =
27861ecc 696 PPRO_FEATURES |
c6dc6f63 697 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 698 CPUID_PSE36,
0514ef2f 699 .features[FEAT_1_ECX] =
6aa91e4a 700 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 701 .features[FEAT_8000_0001_EDX] =
c6dc6f63 702 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 703 .features[FEAT_8000_0001_ECX] =
71195672 704 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 705 .xlevel = 0x8000000A,
c6dc6f63
AP		 706 },
707 {
708 .name = "phenom",
709 .level = 5,
99b88a17 710 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 711 .family = 16,
712 .model = 2,
713 .stepping = 3,
b9fc20bc 714 /* Missing: CPUID_HT */
0514ef2f 715 .features[FEAT_1_EDX] =
27861ecc 716 PPRO_FEATURES |
c6dc6f63 717 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 718 CPUID_PSE36 | CPUID_VME,
0514ef2f 719 .features[FEAT_1_ECX] =
27861ecc 720 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 721 CPUID_EXT_POPCNT,
0514ef2f 722 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 723 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
724 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 725 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 726 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
727 CPUID_EXT3_CR8LEG,
728 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
729 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 730 .features[FEAT_8000_0001_ECX] =
27861ecc 731 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 732 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 733 /* Missing: CPUID_SVM_LBRV */
0514ef2f 734 .features[FEAT_SVM] =
b9fc20bc 735 CPUID_SVM_NPT,
c6dc6f63
AP		 736 .xlevel = 0x8000001A,
737 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
738 },
739 {
740 .name = "core2duo",
741 .level = 10,
99b88a17 742 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 743 .family = 6,
744 .model = 15,
745 .stepping = 11,
b9fc20bc 746 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 747 .features[FEAT_1_EDX] =
27861ecc 748 PPRO_FEATURES |
c6dc6f63 749 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 750 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
751 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 752 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 753 .features[FEAT_1_ECX] =
27861ecc 754 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 755 CPUID_EXT_CX16,
0514ef2f 756 .features[FEAT_8000_0001_EDX] =
27861ecc 757 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 758 .features[FEAT_8000_0001_ECX] =
27861ecc 759 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 760 .xlevel = 0x80000008,
761 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
762 },
763 {
764 .name = "kvm64",
3046bb5d 765 .level = 0xd,
99b88a17 766 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 767 .family = 15,
768 .model = 6,
769 .stepping = 1,
b3a4f0b1 770 /* Missing: CPUID_HT */
0514ef2f 771 .features[FEAT_1_EDX] =
b3a4f0b1 772 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 773 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
774 CPUID_PSE36,
775 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 776 .features[FEAT_1_ECX] =
27861ecc 777 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 778 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 779 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 780 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
781 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
782 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
783 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
784 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 785 .features[FEAT_8000_0001_ECX] =
27861ecc 786 0,
c6dc6f63
AP		 787 .xlevel = 0x80000008,
788 .model_id = "Common KVM processor"
789 },
c6dc6f63
AP		 790 {
791 .name = "qemu32",
792 .level = 4,
99b88a17 793 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 794 .family = 6,
f8e6a11a 795 .model = 6,
c6dc6f63 796 .stepping = 3,
0514ef2f 797 .features[FEAT_1_EDX] =
27861ecc 798 PPRO_FEATURES,
0514ef2f 799 .features[FEAT_1_ECX] =
6aa91e4a 800 CPUID_EXT_SSE3,
58012d66 801 .xlevel = 0x80000004,
c6dc6f63 802 },
eafaf1e5
AP		 803 {
804 .name = "kvm32",
805 .level = 5,
99b88a17 806 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 807 .family = 15,
808 .model = 6,
809 .stepping = 1,
0514ef2f 810 .features[FEAT_1_EDX] =
b3a4f0b1 811 PPRO_FEATURES | CPUID_VME |
eafaf1e5 812 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 813 .features[FEAT_1_ECX] =
27861ecc 814 CPUID_EXT_SSE3,
0514ef2f 815 .features[FEAT_8000_0001_ECX] =
27861ecc 816 0,
eafaf1e5
AP		 817 .xlevel = 0x80000008,
818 .model_id = "Common 32-bit KVM processor"
819 },
c6dc6f63
AP		 820 {
821 .name = "coreduo",
822 .level = 10,
99b88a17 823 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 824 .family = 6,
825 .model = 14,
826 .stepping = 8,
b9fc20bc 827 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 828 .features[FEAT_1_EDX] =
27861ecc 829 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 830 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
831 CPUID_SS,
832 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 833 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 834 .features[FEAT_1_ECX] =
e93abc14 835 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 836 .features[FEAT_8000_0001_EDX] =
27861ecc 837 CPUID_EXT2_NX,
c6dc6f63
AP		 838 .xlevel = 0x80000008,
839 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
840 },
841 {
842 .name = "486",
58012d66 843 .level = 1,
99b88a17 844 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 845 .family = 4,
b2a856d9 846 .model = 8,
c6dc6f63 847 .stepping = 0,
0514ef2f 848 .features[FEAT_1_EDX] =
27861ecc 849 I486_FEATURES,
c6dc6f63
AP		 850 .xlevel = 0,
851 },
852 {
853 .name = "pentium",
854 .level = 1,
99b88a17 855 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 856 .family = 5,
857 .model = 4,
858 .stepping = 3,
0514ef2f 859 .features[FEAT_1_EDX] =
27861ecc 860 PENTIUM_FEATURES,
c6dc6f63
AP		 861 .xlevel = 0,
862 },
863 {
864 .name = "pentium2",
865 .level = 2,
99b88a17 866 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 867 .family = 6,
868 .model = 5,
869 .stepping = 2,
0514ef2f 870 .features[FEAT_1_EDX] =
27861ecc 871 PENTIUM2_FEATURES,
c6dc6f63
AP		 872 .xlevel = 0,
873 },
874 {
875 .name = "pentium3",
3046bb5d 876 .level = 3,
99b88a17 877 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 878 .family = 6,
879 .model = 7,
880 .stepping = 3,
0514ef2f 881 .features[FEAT_1_EDX] =
27861ecc 882 PENTIUM3_FEATURES,
c6dc6f63
AP		 883 .xlevel = 0,
884 },
885 {
886 .name = "athlon",
887 .level = 2,
99b88a17 888 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 889 .family = 6,
890 .model = 2,
891 .stepping = 3,
0514ef2f 892 .features[FEAT_1_EDX] =
27861ecc 893 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 894 CPUID_MCA,
0514ef2f 895 .features[FEAT_8000_0001_EDX] =
60032ac0 896 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 897 .xlevel = 0x80000008,
c6dc6f63
AP		 898 },
899 {
900 .name = "n270",
3046bb5d 901 .level = 10,
99b88a17 902 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 903 .family = 6,
904 .model = 28,
905 .stepping = 2,
b9fc20bc 906 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 907 .features[FEAT_1_EDX] =
27861ecc 908 PPRO_FEATURES |
b9fc20bc
EH		 909 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
910 CPUID_ACPI | CPUID_SS,
c6dc6f63 911 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 912 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
913 * CPUID_EXT_XTPR */
0514ef2f 914 .features[FEAT_1_ECX] =
27861ecc 915 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 916 CPUID_EXT_MOVBE,
0514ef2f 917 .features[FEAT_8000_0001_EDX] =
60032ac0 918 CPUID_EXT2_NX,
0514ef2f 919 .features[FEAT_8000_0001_ECX] =
27861ecc 920 CPUID_EXT3_LAHF_LM,
3046bb5d 921 .xlevel = 0x80000008,
c6dc6f63
AP		 922 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
923 },
3eca4642
EH		 924 {
925 .name = "Conroe",
3046bb5d 926 .level = 10,
99b88a17 927 .vendor = CPUID_VENDOR_INTEL,
3eca4642 928 .family = 6,
ffce9ebb 929 .model = 15,
3eca4642 930 .stepping = 3,
0514ef2f 931 .features[FEAT_1_EDX] =
b3a4f0b1 932 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 933 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
934 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
935 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
936 CPUID_DE | CPUID_FP87,
0514ef2f 937 .features[FEAT_1_ECX] =
27861ecc 938 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 939 .features[FEAT_8000_0001_EDX] =
27861ecc 940 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 941 .features[FEAT_8000_0001_ECX] =
27861ecc 942 CPUID_EXT3_LAHF_LM,
3046bb5d 943 .xlevel = 0x80000008,
3eca4642
EH		 944 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
945 },
946 {
947 .name = "Penryn",
3046bb5d 948 .level = 10,
99b88a17 949 .vendor = CPUID_VENDOR_INTEL,
3eca4642 950 .family = 6,
ffce9ebb 951 .model = 23,
3eca4642 952 .stepping = 3,
0514ef2f 953 .features[FEAT_1_EDX] =
b3a4f0b1 954 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 955 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
956 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
957 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
958 CPUID_DE | CPUID_FP87,
0514ef2f 959 .features[FEAT_1_ECX] =
27861ecc 960 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 961 CPUID_EXT_SSE3,
0514ef2f 962 .features[FEAT_8000_0001_EDX] =
27861ecc 963 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 964 .features[FEAT_8000_0001_ECX] =
27861ecc 965 CPUID_EXT3_LAHF_LM,
3046bb5d 966 .xlevel = 0x80000008,
3eca4642
EH		 967 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
968 },
969 {
970 .name = "Nehalem",
3046bb5d 971 .level = 11,
99b88a17 972 .vendor = CPUID_VENDOR_INTEL,
3eca4642 973 .family = 6,
ffce9ebb 974 .model = 26,
3eca4642 975 .stepping = 3,
0514ef2f 976 .features[FEAT_1_EDX] =
b3a4f0b1 977 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 978 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
979 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
980 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
981 CPUID_DE | CPUID_FP87,
0514ef2f 982 .features[FEAT_1_ECX] =
27861ecc 983 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 984 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 985 .features[FEAT_8000_0001_EDX] =
27861ecc 986 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 987 .features[FEAT_8000_0001_ECX] =
27861ecc 988 CPUID_EXT3_LAHF_LM,
3046bb5d 989 .xlevel = 0x80000008,
3eca4642
EH		 990 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
991 },
992 {
993 .name = "Westmere",
994 .level = 11,
99b88a17 995 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 996 .family = 6,
997 .model = 44,
998 .stepping = 1,
0514ef2f 999 .features[FEAT_1_EDX] =
b3a4f0b1 1000 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1001 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1002 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1003 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1004 CPUID_DE | CPUID_FP87,
0514ef2f 1005 .features[FEAT_1_ECX] =
27861ecc 1006 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1007 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1008 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1009 .features[FEAT_8000_0001_EDX] =
27861ecc 1010 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1011 .features[FEAT_8000_0001_ECX] =
27861ecc 1012 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1013 .features[FEAT_6_EAX] =
1014 CPUID_6_EAX_ARAT,
3046bb5d 1015 .xlevel = 0x80000008,
3eca4642
EH		 1016 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1017 },
1018 {
1019 .name = "SandyBridge",
1020 .level = 0xd,
99b88a17 1021 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1022 .family = 6,
1023 .model = 42,
1024 .stepping = 1,
0514ef2f 1025 .features[FEAT_1_EDX] =
b3a4f0b1 1026 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1027 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1028 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1029 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1030 CPUID_DE | CPUID_FP87,
0514ef2f 1031 .features[FEAT_1_ECX] =
27861ecc 1032 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1033 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1034 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1035 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1036 CPUID_EXT_SSE3,
0514ef2f 1037 .features[FEAT_8000_0001_EDX] =
27861ecc 1038 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1039 CPUID_EXT2_SYSCALL,
0514ef2f 1040 .features[FEAT_8000_0001_ECX] =
27861ecc 1041 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1042 .features[FEAT_XSAVE] =
1043 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1044 .features[FEAT_6_EAX] =
1045 CPUID_6_EAX_ARAT,
3046bb5d 1046 .xlevel = 0x80000008,
3eca4642
EH		 1047 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1048 },
2f9ac42a
PB		 1049 {
1050 .name = "IvyBridge",
1051 .level = 0xd,
1052 .vendor = CPUID_VENDOR_INTEL,
1053 .family = 6,
1054 .model = 58,
1055 .stepping = 9,
1056 .features[FEAT_1_EDX] =
1057 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1058 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1059 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1060 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1061 CPUID_DE | CPUID_FP87,
1062 .features[FEAT_1_ECX] =
1063 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1064 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1065 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1066 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1067 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1068 .features[FEAT_7_0_EBX] =
1069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1070 CPUID_7_0_EBX_ERMS,
1071 .features[FEAT_8000_0001_EDX] =
1072 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1073 CPUID_EXT2_SYSCALL,
1074 .features[FEAT_8000_0001_ECX] =
1075 CPUID_EXT3_LAHF_LM,
1076 .features[FEAT_XSAVE] =
1077 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1078 .features[FEAT_6_EAX] =
1079 CPUID_6_EAX_ARAT,
3046bb5d 1080 .xlevel = 0x80000008,
2f9ac42a
PB		 1081 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1082 },
37507094 1083 {
a356850b
EH		 1084 .name = "Haswell-noTSX",
1085 .level = 0xd,
1086 .vendor = CPUID_VENDOR_INTEL,
1087 .family = 6,
1088 .model = 60,
1089 .stepping = 1,
1090 .features[FEAT_1_EDX] =
1091 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1092 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1093 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1094 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1095 CPUID_DE | CPUID_FP87,
1096 .features[FEAT_1_ECX] =
1097 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1098 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1099 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1100 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1101 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1102 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1103 .features[FEAT_8000_0001_EDX] =
1104 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1105 CPUID_EXT2_SYSCALL,
1106 .features[FEAT_8000_0001_ECX] =
becb6667 1107 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1108 .features[FEAT_7_0_EBX] =
1109 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1110 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1111 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1112 .features[FEAT_XSAVE] =
1113 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1114 .features[FEAT_6_EAX] =
1115 CPUID_6_EAX_ARAT,
3046bb5d 1116 .xlevel = 0x80000008,
a356850b
EH		 1117 .model_id = "Intel Core Processor (Haswell, no TSX)",
1118 }, {
37507094
EH		 1119 .name = "Haswell",
1120 .level = 0xd,
99b88a17 1121 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1122 .family = 6,
1123 .model = 60,
1124 .stepping = 1,
0514ef2f 1125 .features[FEAT_1_EDX] =
b3a4f0b1 1126 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1127 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1128 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1129 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1130 CPUID_DE | CPUID_FP87,
0514ef2f 1131 .features[FEAT_1_ECX] =
27861ecc 1132 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1133 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1134 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1135 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1136 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1137 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1138 .features[FEAT_8000_0001_EDX] =
27861ecc 1139 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1140 CPUID_EXT2_SYSCALL,
0514ef2f 1141 .features[FEAT_8000_0001_ECX] =
becb6667 1142 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1143 .features[FEAT_7_0_EBX] =
27861ecc 1144 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1145 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1146 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1147 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1148 .features[FEAT_XSAVE] =
1149 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1150 .features[FEAT_6_EAX] =
1151 CPUID_6_EAX_ARAT,
3046bb5d 1152 .xlevel = 0x80000008,
37507094
EH		 1153 .model_id = "Intel Core Processor (Haswell)",
1154 },
a356850b
EH		 1155 {
1156 .name = "Broadwell-noTSX",
1157 .level = 0xd,
1158 .vendor = CPUID_VENDOR_INTEL,
1159 .family = 6,
1160 .model = 61,
1161 .stepping = 2,
1162 .features[FEAT_1_EDX] =
1163 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1164 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1165 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1166 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1167 CPUID_DE | CPUID_FP87,
1168 .features[FEAT_1_ECX] =
1169 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1170 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1171 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1172 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1173 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1174 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1175 .features[FEAT_8000_0001_EDX] =
1176 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1177 CPUID_EXT2_SYSCALL,
1178 .features[FEAT_8000_0001_ECX] =
becb6667 1179 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1180 .features[FEAT_7_0_EBX] =
1181 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1182 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1183 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1184 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1185 CPUID_7_0_EBX_SMAP,
1186 .features[FEAT_XSAVE] =
1187 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1188 .features[FEAT_6_EAX] =
1189 CPUID_6_EAX_ARAT,
3046bb5d 1190 .xlevel = 0x80000008,
a356850b
EH		 1191 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1192 },
ece01354
EH		 1193 {
1194 .name = "Broadwell",
1195 .level = 0xd,
1196 .vendor = CPUID_VENDOR_INTEL,
1197 .family = 6,
1198 .model = 61,
1199 .stepping = 2,
1200 .features[FEAT_1_EDX] =
b3a4f0b1 1201 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1202 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1203 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1204 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1205 CPUID_DE | CPUID_FP87,
1206 .features[FEAT_1_ECX] =
1207 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1208 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1209 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1210 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1211 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1212 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1213 .features[FEAT_8000_0001_EDX] =
1214 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1215 CPUID_EXT2_SYSCALL,
1216 .features[FEAT_8000_0001_ECX] =
becb6667 1217 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1218 .features[FEAT_7_0_EBX] =
1219 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1220 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1221 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1222 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1223 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1224 .features[FEAT_XSAVE] =
1225 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1226 .features[FEAT_6_EAX] =
1227 CPUID_6_EAX_ARAT,
3046bb5d 1228 .xlevel = 0x80000008,
ece01354
EH		 1229 .model_id = "Intel Core Processor (Broadwell)",
1230 },
3eca4642
EH		 1231 {
1232 .name = "Opteron_G1",
1233 .level = 5,
99b88a17 1234 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1235 .family = 15,
1236 .model = 6,
1237 .stepping = 1,
0514ef2f 1238 .features[FEAT_1_EDX] =
b3a4f0b1 1239 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1240 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1241 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1242 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1243 CPUID_DE | CPUID_FP87,
0514ef2f 1244 .features[FEAT_1_ECX] =
27861ecc 1245 CPUID_EXT_SSE3,
0514ef2f 1246 .features[FEAT_8000_0001_EDX] =
27861ecc 1247 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1248 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1249 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1250 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1251 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1252 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1253 .xlevel = 0x80000008,
1254 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1255 },
1256 {
1257 .name = "Opteron_G2",
1258 .level = 5,
99b88a17 1259 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1260 .family = 15,
1261 .model = 6,
1262 .stepping = 1,
0514ef2f 1263 .features[FEAT_1_EDX] =
b3a4f0b1 1264 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1265 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1266 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1267 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1268 CPUID_DE | CPUID_FP87,
0514ef2f 1269 .features[FEAT_1_ECX] =
27861ecc 1270 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1271 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1272 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1273 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1274 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1275 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1276 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1277 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1278 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1279 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1280 .features[FEAT_8000_0001_ECX] =
27861ecc 1281 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1282 .xlevel = 0x80000008,
1283 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1284 },
1285 {
1286 .name = "Opteron_G3",
1287 .level = 5,
99b88a17 1288 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1289 .family = 15,
1290 .model = 6,
1291 .stepping = 1,
0514ef2f 1292 .features[FEAT_1_EDX] =
b3a4f0b1 1293 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1294 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1295 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1296 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1297 CPUID_DE | CPUID_FP87,
0514ef2f 1298 .features[FEAT_1_ECX] =
27861ecc 1299 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1300 CPUID_EXT_SSE3,
33b5e8c0 1301 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1302 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1303 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1304 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1305 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1306 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1307 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1308 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1309 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1310 .features[FEAT_8000_0001_ECX] =
27861ecc 1311 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1312 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1313 .xlevel = 0x80000008,
1314 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1315 },
1316 {
1317 .name = "Opteron_G4",
1318 .level = 0xd,
99b88a17 1319 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1320 .family = 21,
1321 .model = 1,
1322 .stepping = 2,
0514ef2f 1323 .features[FEAT_1_EDX] =
b3a4f0b1 1324 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1325 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1326 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1327 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1328 CPUID_DE | CPUID_FP87,
0514ef2f 1329 .features[FEAT_1_ECX] =
27861ecc 1330 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1331 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1332 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1333 CPUID_EXT_SSE3,
33b5e8c0 1334 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1335 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1336 CPUID_EXT2_LM |
b3fb3a20
EH		 1337 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1338 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1339 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1340 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1341 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1342 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1343 .features[FEAT_8000_0001_ECX] =
27861ecc 1344 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1345 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1346 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1347 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1348 /* no xsaveopt! */
3eca4642
EH		 1349 .xlevel = 0x8000001A,
1350 .model_id = "AMD Opteron 62xx class CPU",
1351 },
021941b9
AP		 1352 {
1353 .name = "Opteron_G5",
1354 .level = 0xd,
99b88a17 1355 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1356 .family = 21,
1357 .model = 2,
1358 .stepping = 0,
0514ef2f 1359 .features[FEAT_1_EDX] =
b3a4f0b1 1360 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1361 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1362 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1363 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1364 CPUID_DE | CPUID_FP87,
0514ef2f 1365 .features[FEAT_1_ECX] =
27861ecc 1366 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1367 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1368 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1369 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1370 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1371 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1372 CPUID_EXT2_LM |
b3fb3a20
EH		 1373 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1374 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1375 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1376 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1377 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1378 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1379 .features[FEAT_8000_0001_ECX] =
27861ecc 1380 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1381 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1382 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1383 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1384 /* no xsaveopt! */
021941b9
AP		 1385 .xlevel = 0x8000001A,
1386 .model_id = "AMD Opteron 63xx class CPU",
1387 },
c6dc6f63
AP		 1388};
1389
5114e842
EH		 1390typedef struct PropValue {
1391 const char *prop, *value;
1392} PropValue;
1393
1394/* KVM-specific features that are automatically added/removed
1395 * from all CPU models when KVM is enabled.
1396 */
1397static PropValue kvm_default_props[] = {
1398 { "kvmclock", "on" },
1399 { "kvm-nopiodelay", "on" },
1400 { "kvm-asyncpf", "on" },
1401 { "kvm-steal-time", "on" },
1402 { "kvm-pv-eoi", "on" },
1403 { "kvmclock-stable-bit", "on" },
1404 { "x2apic", "on" },
1405 { "acpi", "off" },
1406 { "monitor", "off" },
1407 { "svm", "off" },
1408 { NULL, NULL },
1409};
1410
1411void x86_cpu_change_kvm_default(const char *prop, const char *value)
1412{
1413 PropValue *pv;
1414 for (pv = kvm_default_props; pv->prop; pv++) {
1415 if (!strcmp(pv->prop, prop)) {
1416 pv->value = value;
1417 break;
1418 }
1419 }
1420
1421 /* It is valid to call this function only for properties that
1422 * are already present in the kvm_default_props table.
1423 */
1424 assert(pv->prop);
1425}
1426
4d1b279b
EH		 1427static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1428 bool migratable_only);
1429
d940ee9b
EH		 1430#ifdef CONFIG_KVM
1431
c6dc6f63
AP		 1432static int cpu_x86_fill_model_id(char *str)
1433{
1434 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1435 int i;
1436
1437 for (i = 0; i < 3; i++) {
1438 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1439 memcpy(str + i * 16 + 0, &eax, 4);
1440 memcpy(str + i * 16 + 4, &ebx, 4);
1441 memcpy(str + i * 16 + 8, &ecx, 4);
1442 memcpy(str + i * 16 + 12, &edx, 4);
1443 }
1444 return 0;
1445}
1446
d940ee9b
EH		 1447static X86CPUDefinition host_cpudef;
1448
84f1b92f 1449static Property host_x86_cpu_properties[] = {
120eee7d 1450 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1451 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1452 DEFINE_PROP_END_OF_LIST()
1453};
1454
d940ee9b 1455/* class_init for the "host" CPU model
6e746f30 1456 *
d940ee9b 1457 * This function may be called before KVM is initialized.
6e746f30 1458 */
d940ee9b 1459static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1460{
84f1b92f 1461 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1462 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1463 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1464
d940ee9b 1465 xcc->kvm_required = true;
6e746f30 1466
c6dc6f63 1467 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1468 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1469
1470 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1471 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1472 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1473 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1474
d940ee9b 1475 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1476
d940ee9b 1477 xcc->cpu_def = &host_cpudef;
d940ee9b
EH		 1478
1479 /* level, xlevel, xlevel2, and the feature words are initialized on
1480 * instance_init, because they require KVM to be initialized.
1481 */
84f1b92f
EH		 1482
1483 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1484 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1485 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1486}
1487
1488static void host_x86_cpu_initfn(Object *obj)
1489{
1490 X86CPU *cpu = X86_CPU(obj);
1491 CPUX86State *env = &cpu->env;
1492 KVMState *s = kvm_state;
d940ee9b
EH		 1493
1494 assert(kvm_enabled());
1495
4d1b279b
EH		 1496 /* We can't fill the features array here because we don't know yet if
1497 * "migratable" is true or false.
1498 */
1499 cpu->host_features = true;
1500
d940ee9b
EH		 1501 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1502 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1503 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2a573259 1504
d940ee9b 1505 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1506}
1507
d940ee9b
EH		 1508static const TypeInfo host_x86_cpu_type_info = {
1509 .name = X86_CPU_TYPE_NAME("host"),
1510 .parent = TYPE_X86_CPU,
1511 .instance_init = host_x86_cpu_initfn,
1512 .class_init = host_x86_cpu_class_init,
1513};
1514
1515#endif
1516
8459e396 1517static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1518{
8459e396 1519 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1520 int i;
1521
857aee33 1522 for (i = 0; i < 32; ++i) {
72370dc1 1523 if ((1UL << i) & mask) {
bffd67b0 1524 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1525 assert(reg);
fefb41bf 1526 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1527 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1528 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1529 f->cpuid_eax, reg,
1530 f->feat_names[i] ? "." : "",
1531 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1532 }
857aee33 1533 }
c6dc6f63
AP		 1534}
1535
d7bce999
EB		 1536static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1537 const char *name, void *opaque,
1538 Error **errp)
95b8519d
AF		 1539{
1540 X86CPU *cpu = X86_CPU(obj);
1541 CPUX86State *env = &cpu->env;
1542 int64_t value;
1543
1544 value = (env->cpuid_version >> 8) & 0xf;
1545 if (value == 0xf) {
1546 value += (env->cpuid_version >> 20) & 0xff;
1547 }
51e72bc1 1548 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1549}
1550
d7bce999
EB		 1551static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1552 const char *name, void *opaque,
1553 Error **errp)
ed5e1ec3 1554{
71ad61d3
AF		 1555 X86CPU *cpu = X86_CPU(obj);
1556 CPUX86State *env = &cpu->env;
1557 const int64_t min = 0;
1558 const int64_t max = 0xff + 0xf;
65cd9064 1559 Error *local_err = NULL;
71ad61d3
AF		 1560 int64_t value;
1561
51e72bc1 1562 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1563 if (local_err) {
1564 error_propagate(errp, local_err);
71ad61d3
AF		 1565 return;
1566 }
1567 if (value < min || value > max) {
c6bd8c70
MA		 1568 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1569 name ? name : "null", value, min, max);
71ad61d3
AF		 1570 return;
1571 }
1572
ed5e1ec3 1573 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1574 if (value > 0x0f) {
1575 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1576 } else {
71ad61d3 1577 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1578 }
1579}
1580
d7bce999
EB		 1581static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1582 const char *name, void *opaque,
1583 Error **errp)
67e30c83
AF		 1584{
1585 X86CPU *cpu = X86_CPU(obj);
1586 CPUX86State *env = &cpu->env;
1587 int64_t value;
1588
1589 value = (env->cpuid_version >> 4) & 0xf;
1590 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1591 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1592}
1593
d7bce999
EB		 1594static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1595 const char *name, void *opaque,
1596 Error **errp)
b0704cbd 1597{
c5291a4f
AF		 1598 X86CPU *cpu = X86_CPU(obj);
1599 CPUX86State *env = &cpu->env;
1600 const int64_t min = 0;
1601 const int64_t max = 0xff;
65cd9064 1602 Error *local_err = NULL;
c5291a4f
AF		 1603 int64_t value;
1604
51e72bc1 1605 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1606 if (local_err) {
1607 error_propagate(errp, local_err);
c5291a4f
AF		 1608 return;
1609 }
1610 if (value < min || value > max) {
c6bd8c70
MA		 1611 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1612 name ? name : "null", value, min, max);
c5291a4f
AF		 1613 return;
1614 }
1615
b0704cbd 1616 env->cpuid_version &= ~0xf00f0;
c5291a4f 1617 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1618}
1619
35112e41 1620static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1621 const char *name, void *opaque,
35112e41
AF		 1622 Error **errp)
1623{
1624 X86CPU *cpu = X86_CPU(obj);
1625 CPUX86State *env = &cpu->env;
1626 int64_t value;
1627
1628 value = env->cpuid_version & 0xf;
51e72bc1 1629 visit_type_int(v, name, &value, errp);
35112e41
AF		 1630}
1631
036e2222 1632static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1633 const char *name, void *opaque,
036e2222 1634 Error **errp)
38c3dc46 1635{
036e2222
AF		 1636 X86CPU *cpu = X86_CPU(obj);
1637 CPUX86State *env = &cpu->env;
1638 const int64_t min = 0;
1639 const int64_t max = 0xf;
65cd9064 1640 Error *local_err = NULL;
036e2222
AF		 1641 int64_t value;
1642
51e72bc1 1643 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1644 if (local_err) {
1645 error_propagate(errp, local_err);
036e2222
AF		 1646 return;
1647 }
1648 if (value < min || value > max) {
c6bd8c70
MA		 1649 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1650 name ? name : "null", value, min, max);
036e2222
AF		 1651 return;
1652 }
1653
38c3dc46 1654 env->cpuid_version &= ~0xf;
036e2222 1655 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1656}
1657
d480e1af
AF		 1658static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1659{
1660 X86CPU *cpu = X86_CPU(obj);
1661 CPUX86State *env = &cpu->env;
1662 char *value;
d480e1af 1663
e42a92ae 1664 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1665 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1666 env->cpuid_vendor3);
d480e1af
AF		 1667 return value;
1668}
1669
1670static void x86_cpuid_set_vendor(Object *obj, const char *value,
1671 Error **errp)
1672{
1673 X86CPU *cpu = X86_CPU(obj);
1674 CPUX86State *env = &cpu->env;
1675 int i;
1676
9df694ee 1677 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1678 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1679 return;
1680 }
1681
1682 env->cpuid_vendor1 = 0;
1683 env->cpuid_vendor2 = 0;
1684 env->cpuid_vendor3 = 0;
1685 for (i = 0; i < 4; i++) {
1686 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1687 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1688 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1689 }
d480e1af
AF		 1690}
1691
63e886eb
AF		 1692static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1693{
1694 X86CPU *cpu = X86_CPU(obj);
1695 CPUX86State *env = &cpu->env;
1696 char *value;
1697 int i;
1698
1699 value = g_malloc(48 + 1);
1700 for (i = 0; i < 48; i++) {
1701 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1702 }
1703 value[48] = '\0';
1704 return value;
1705}
1706
938d4c25
AF		 1707static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1708 Error **errp)
dcce6675 1709{
938d4c25
AF		 1710 X86CPU *cpu = X86_CPU(obj);
1711 CPUX86State *env = &cpu->env;
dcce6675
AF		 1712 int c, len, i;
1713
1714 if (model_id == NULL) {
1715 model_id = "";
1716 }
1717 len = strlen(model_id);
d0a6acf4 1718 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1719 for (i = 0; i < 48; i++) {
1720 if (i >= len) {
1721 c = '\0';
1722 } else {
1723 c = (uint8_t)model_id[i];
1724 }
1725 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1726 }
1727}
1728
d7bce999
EB		 1729static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1730 void *opaque, Error **errp)
89e48965
AF		 1731{
1732 X86CPU *cpu = X86_CPU(obj);
1733 int64_t value;
1734
1735 value = cpu->env.tsc_khz * 1000;
51e72bc1 1736 visit_type_int(v, name, &value, errp);
89e48965
AF		 1737}
1738
d7bce999
EB		 1739static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1740 void *opaque, Error **errp)
89e48965
AF		 1741{
1742 X86CPU *cpu = X86_CPU(obj);
1743 const int64_t min = 0;
2e84849a 1744 const int64_t max = INT64_MAX;
65cd9064 1745 Error *local_err = NULL;
89e48965
AF		 1746 int64_t value;
1747
51e72bc1 1748 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1749 if (local_err) {
1750 error_propagate(errp, local_err);
89e48965
AF		 1751 return;
1752 }
1753 if (value < min || value > max) {
c6bd8c70
MA		 1754 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1755 name ? name : "null", value, min, max);
89e48965
AF		 1756 return;
1757 }
1758
36f96c4b 1759 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1760}
1761
d7bce999
EB		 1762static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, const char *name,
1763 void *opaque, Error **errp)
31050930
IM		 1764{
1765 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1766 int64_t value = cpu->apic_id;
31050930 1767
51e72bc1 1768 visit_type_int(v, name, &value, errp);
31050930
IM		 1769}
1770
d7bce999
EB		 1771static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, const char *name,
1772 void *opaque, Error **errp)
31050930
IM		 1773{
1774 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1775 DeviceState *dev = DEVICE(obj);
31050930
IM		 1776 const int64_t min = 0;
1777 const int64_t max = UINT32_MAX;
1778 Error *error = NULL;
1779 int64_t value;
1780
8d6d4980
IM		 1781 if (dev->realized) {
1782 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1783 "it was realized", name, object_get_typename(obj));
1784 return;
1785 }
1786
51e72bc1 1787 visit_type_int(v, name, &value, &error);
31050930
IM		 1788 if (error) {
1789 error_propagate(errp, error);
1790 return;
1791 }
1792 if (value < min || value > max) {
1793 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1794 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1795 object_get_typename(obj), name, value, min, max);
1796 return;
1797 }
1798
7e72a45c 1799 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1800 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1801 return;
1802 }
7e72a45c 1803 cpu->apic_id = value;
31050930
IM		 1804}
1805
7e5292b5 1806/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1807static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1808 const char *name, void *opaque,
1809 Error **errp)
8e8aba50 1810{
7e5292b5 1811 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1812 FeatureWord w;
1813 Error *err = NULL;
1814 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1815 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1816 X86CPUFeatureWordInfoList *list = NULL;
1817
1818 for (w = 0; w < FEATURE_WORDS; w++) {
1819 FeatureWordInfo *wi = &feature_word_info[w];
1820 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1821 qwi->cpuid_input_eax = wi->cpuid_eax;
1822 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1823 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1824 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1825 qwi->features = array[w];
8e8aba50
EH		 1826
1827 /* List will be in reverse order, but order shouldn't matter */
1828 list_entries[w].next = list;
1829 list_entries[w].value = &word_infos[w];
1830 list = &list_entries[w];
1831 }
1832
51e72bc1 1833 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, &err);
8e8aba50
EH		 1834 error_propagate(errp, err);
1835}
1836
d7bce999
EB		 1837static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1838 void *opaque, Error **errp)
c8f0f88e
IM		 1839{
1840 X86CPU *cpu = X86_CPU(obj);
1841 int64_t value = cpu->hyperv_spinlock_attempts;
1842
51e72bc1 1843 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1844}
1845
d7bce999
EB		 1846static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1847 void *opaque, Error **errp)
c8f0f88e
IM		 1848{
1849 const int64_t min = 0xFFF;
1850 const int64_t max = UINT_MAX;
1851 X86CPU *cpu = X86_CPU(obj);
1852 Error *err = NULL;
1853 int64_t value;
1854
51e72bc1 1855 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1856 if (err) {
1857 error_propagate(errp, err);
1858 return;
1859 }
1860
1861 if (value < min || value > max) {
1862 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1863 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1864 object_get_typename(obj), name ? name : "null",
1865 value, min, max);
c8f0f88e
IM		 1866 return;
1867 }
1868 cpu->hyperv_spinlock_attempts = value;
1869}
1870
1871static PropertyInfo qdev_prop_spinlocks = {
1872 .name = "int",
1873 .get = x86_get_hv_spinlocks,
1874 .set = x86_set_hv_spinlocks,
1875};
1876
72ac2e87
IM		 1877/* Convert all '_' in a feature string option name to '-', to make feature
1878 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1879 */
1880static inline void feat2prop(char *s)
1881{
1882 while ((s = strchr(s, '_'))) {
1883 *s = '-';
1884 }
1885}
1886
8f961357
EH		 1887/* Parse "+feature,-feature,feature=foo" CPU feature string
1888 */
94a444b2
AF		 1889static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1890 Error **errp)
8f961357 1891{
94a444b2 1892 X86CPU *cpu = X86_CPU(cs);
8f961357 1893 char *featurestr; /* Single 'key=value" string being parsed */
e1c224b4 1894 FeatureWord w;
8f961357 1895 /* Features to be added */
077c68c3 1896 FeatureWordArray plus_features = { 0 };
8f961357 1897 /* Features to be removed */
5ef57876 1898 FeatureWordArray minus_features = { 0 };
8f961357 1899 uint32_t numvalue;
a91987c2 1900 CPUX86State *env = &cpu->env;
94a444b2 1901 Error *local_err = NULL;
8f961357 1902
8f961357 1903 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1904
1905 while (featurestr) {
1906 char *val;
1907 if (featurestr[0] == '+') {
c00c94ab 1908 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1909 } else if (featurestr[0] == '-') {
c00c94ab 1910 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1911 } else if ((val = strchr(featurestr, '='))) {
1912 *val = 0; val++;
72ac2e87 1913 feat2prop(featurestr);
d024d209 1914 if (!strcmp(featurestr, "xlevel")) {
c6dc6f63 1915 char *err;
a91987c2
IM		 1916 char num[32];
1917
c6dc6f63
AP		 1918 numvalue = strtoul(val, &err, 0);
1919 if (!*val || *err) {
6b1dd54b
PB		 1920 error_setg(errp, "bad numerical value %s", val);
1921 return;
c6dc6f63
AP		 1922 }
1923 if (numvalue < 0x80000000) {
94a444b2
AF		 1924 error_report("xlevel value shall always be >= 0x80000000"
1925 ", fixup will be removed in future versions");
2f7a21c4 1926 numvalue += 0x80000000;
c6dc6f63 1927 }
a91987c2 1928 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
94a444b2 1929 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
72ac2e87 1930 } else if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1931 int64_t tsc_freq;
1932 char *err;
a91987c2 1933 char num[32];
b862d1fe 1934
4677bb40
MAL		 1935 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1936 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1937 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1938 error_setg(errp, "bad numerical value %s", val);
1939 return;
b862d1fe 1940 }
a91987c2 1941 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1942 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1943 &local_err);
72ac2e87 1944 } else if (!strcmp(featurestr, "hv-spinlocks")) {
28f52cc0 1945 char *err;
92067bf4 1946 const int min = 0xFFF;
c8f0f88e 1947 char num[32];
28f52cc0
VR		 1948 numvalue = strtoul(val, &err, 0);
1949 if (!*val || *err) {
6b1dd54b
PB		 1950 error_setg(errp, "bad numerical value %s", val);
1951 return;
28f52cc0 1952 }
92067bf4 1953 if (numvalue < min) {
94a444b2 1954 error_report("hv-spinlocks value shall always be >= 0x%x"
5bb4c35d 1955 ", fixup will be removed in future versions",
1956 min);
92067bf4
IM		 1957 numvalue = min;
1958 }
c8f0f88e 1959 snprintf(num, sizeof(num), "%" PRId32, numvalue);
94a444b2 1960 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
c6dc6f63 1961 } else {
94a444b2 1962 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1963 }
c6dc6f63 1964 } else {
258f5abe 1965 feat2prop(featurestr);
94a444b2 1966 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 1967 }
94a444b2
AF		 1968 if (local_err) {
1969 error_propagate(errp, local_err);
6b1dd54b 1970 return;
c6dc6f63
AP		 1971 }
1972 featurestr = strtok(NULL, ",");
1973 }
e1c224b4 1974
4d1b279b
EH		 1975 if (cpu->host_features) {
1976 for (w = 0; w < FEATURE_WORDS; w++) {
1977 env->features[w] =
1978 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1979 }
1980 }
1981
e1c224b4
EH		 1982 for (w = 0; w < FEATURE_WORDS; w++) {
1983 env->features[w] |= plus_features[w];
1984 env->features[w] &= ~minus_features[w];
1985 }
c6dc6f63
AP		 1986}
1987
8c3329e5 1988/* Print all cpuid feature names in featureset
c6dc6f63 1989 */
8c3329e5 1990static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 1991{
8c3329e5
EH		 1992 int bit;
1993 bool first = true;
1994
1995 for (bit = 0; bit < 32; bit++) {
1996 if (featureset[bit]) {
1997 print(f, "%s%s", first ? "" : " ", featureset[bit]);
1998 first = false;
c6dc6f63 1999 }
8c3329e5 2000 }
c6dc6f63
AP		 2001}
2002
e916cbf8
PM		 2003/* generate CPU information. */
2004void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2005{
9576de75 2006 X86CPUDefinition *def;
c6dc6f63 2007 char buf[256];
7fc9b714 2008 int i;
c6dc6f63 2009
7fc9b714
AF		 2010 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2011 def = &builtin_x86_defs[i];
c04321b3 2012 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2013 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2014 }
21ad7789
JK		 2015#ifdef CONFIG_KVM
2016 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2017 "KVM processor with all supported host features "
2018 "(only available in KVM mode)");
2019#endif
2020
6cdf8854 2021 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2022 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2023 FeatureWordInfo *fw = &feature_word_info[i];
2024
8c3329e5
EH		 2025 (*cpu_fprintf)(f, " ");
2026 listflags(f, cpu_fprintf, fw->feat_names);
2027 (*cpu_fprintf)(f, "\n");
3af60be2 2028 }
c6dc6f63
AP		 2029}
2030
76b64a7a 2031CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2032{
2033 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2034 X86CPUDefinition *def;
7fc9b714 2035 int i;
e3966126 2036
7fc9b714 2037 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2038 CpuDefinitionInfoList *entry;
2039 CpuDefinitionInfo *info;
2040
7fc9b714 2041 def = &builtin_x86_defs[i];
e3966126
AL		 2042 info = g_malloc0(sizeof(*info));
2043 info->name = g_strdup(def->name);
2044
2045 entry = g_malloc0(sizeof(*entry));
2046 entry->value = info;
2047 entry->next = cpu_list;
2048 cpu_list = entry;
2049 }
2050
2051 return cpu_list;
2052}
2053
84f1b92f
EH		 2054static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2055 bool migratable_only)
27418adf
EH		 2056{
2057 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2058 uint32_t r;
27418adf 2059
fefb41bf 2060 if (kvm_enabled()) {
84f1b92f
EH		 2061 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2062 wi->cpuid_ecx,
2063 wi->cpuid_reg);
fefb41bf 2064 } else if (tcg_enabled()) {
84f1b92f 2065 r = wi->tcg_features;
fefb41bf
EH		 2066 } else {
2067 return ~0;
2068 }
84f1b92f
EH		 2069 if (migratable_only) {
2070 r &= x86_cpu_get_migratable_flags(w);
2071 }
2072 return r;
27418adf
EH		 2073}
2074
51f63aed
EH		 2075/*
2076 * Filters CPU feature words based on host availability of each feature.
2077 *
51f63aed
EH		 2078 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2079 */
27418adf 2080static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2081{
2082 CPUX86State *env = &cpu->env;
bd87d2a2 2083 FeatureWord w;
51f63aed
EH		 2084 int rv = 0;
2085
bd87d2a2 2086 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2087 uint32_t host_feat =
2088 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2089 uint32_t requested_features = env->features[w];
2090 env->features[w] &= host_feat;
2091 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2092 if (cpu->filtered_features[w]) {
2093 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2094 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2095 }
2096 rv = 1;
2097 }
bd87d2a2 2098 }
51f63aed
EH		 2099
2100 return rv;
bc74b7db 2101}
bc74b7db 2102
5114e842
EH		 2103static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2104{
2105 PropValue *pv;
2106 for (pv = props; pv->prop; pv++) {
2107 if (!pv->value) {
2108 continue;
2109 }
2110 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2111 &error_abort);
2112 }
2113}
2114
d940ee9b 2115/* Load data from X86CPUDefinition
c080e30e 2116 */
d940ee9b 2117static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2118{
61dcd775 2119 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2120 const char *vendor;
2121 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2122 FeatureWord w;
c6dc6f63 2123
2d64255b
AF		 2124 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2125 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2126 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2127 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2128 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2129 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2d64255b 2130 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2131 for (w = 0; w < FEATURE_WORDS; w++) {
2132 env->features[w] = def->features[w];
2133 }
82beb536 2134
9576de75 2135 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2136 if (kvm_enabled()) {
492a4c94
LT		 2137 if (!kvm_irqchip_in_kernel()) {
2138 x86_cpu_change_kvm_default("x2apic", "off");
2139 }
2140
5114e842 2141 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2142 }
5fcca9ff 2143
82beb536 2144 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2145
2146 /* sysenter isn't supported in compatibility mode on AMD,
2147 * syscall isn't supported in compatibility mode on Intel.
2148 * Normally we advertise the actual CPU vendor, but you can
2149 * override this using the 'vendor' property if you want to use
2150 * KVM's sysenter/syscall emulation in compatibility mode and
2151 * when doing cross vendor migration
2152 */
74f54bc4 2153 vendor = def->vendor;
7c08db30
EH		 2154 if (kvm_enabled()) {
2155 uint32_t ebx = 0, ecx = 0, edx = 0;
2156 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2157 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2158 vendor = host_vendor;
2159 }
2160
2161 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2162
c6dc6f63
AP		 2163}
2164
e1570d00 2165X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2166{
2d64255b 2167 X86CPU *cpu = NULL;
d940ee9b 2168 X86CPUClass *xcc;
500050d1 2169 ObjectClass *oc;
2d64255b
AF		 2170 gchar **model_pieces;
2171 char *name, *features;
5c3c6a68
AF		 2172 Error *error = NULL;
2173
2d64255b
AF		 2174 model_pieces = g_strsplit(cpu_model, ",", 2);
2175 if (!model_pieces[0]) {
2176 error_setg(&error, "Invalid/empty CPU model name");
2177 goto out;
2178 }
2179 name = model_pieces[0];
2180 features = model_pieces[1];
2181
500050d1
AF		 2182 oc = x86_cpu_class_by_name(name);
2183 if (oc == NULL) {
2184 error_setg(&error, "Unable to find CPU definition: %s", name);
2185 goto out;
2186 }
d940ee9b
EH		 2187 xcc = X86_CPU_CLASS(oc);
2188
2189 if (xcc->kvm_required && !kvm_enabled()) {
2190 error_setg(&error, "CPU model '%s' requires KVM", name);
285f025d
EH		 2191 goto out;
2192 }
2193
d940ee9b
EH		 2194 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2195
94a444b2 2196 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2197 if (error) {
2198 goto out;
5c3c6a68
AF		 2199 }
2200
7f833247 2201out:
cd7b87ff
AF		 2202 if (error != NULL) {
2203 error_propagate(errp, error);
500050d1
AF		 2204 if (cpu) {
2205 object_unref(OBJECT(cpu));
2206 cpu = NULL;
2207 }
cd7b87ff 2208 }
7f833247
IM		 2209 g_strfreev(model_pieces);
2210 return cpu;
2211}
2212
0856579c 2213X86CPU *cpu_x86_init(const char *cpu_model)
7f833247
IM		 2214{
2215 Error *error = NULL;
2216 X86CPU *cpu;
2217
e1570d00 2218 cpu = cpu_x86_create(cpu_model, &error);
5c3c6a68 2219 if (error) {
0856579c 2220 goto out;
9c235e83 2221 }
7f833247 2222
7f833247 2223 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
18b0e4e7 2224
0856579c
PM		 2225out:
2226 if (error) {
2227 error_report_err(error);
2228 if (cpu != NULL) {
2229 object_unref(OBJECT(cpu));
2230 cpu = NULL;
2231 }
18b0e4e7 2232 }
0856579c 2233 return cpu;
5c3c6a68
AF		 2234}
2235
d940ee9b
EH		 2236static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2237{
2238 X86CPUDefinition *cpudef = data;
2239 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2240
2241 xcc->cpu_def = cpudef;
2242}
2243
2244static void x86_register_cpudef_type(X86CPUDefinition *def)
2245{
2246 char *typename = x86_cpu_type_name(def->name);
2247 TypeInfo ti = {
2248 .name = typename,
2249 .parent = TYPE_X86_CPU,
2250 .class_init = x86_cpu_cpudef_class_init,
2251 .class_data = def,
2252 };
2253
2254 type_register(&ti);
2255 g_free(typename);
2256}
2257
c6dc6f63 2258#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2259
0e26b7b8
BS		 2260void cpu_clear_apic_feature(CPUX86State *env)
2261{
0514ef2f 2262 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2263}
2264
c6dc6f63
AP		 2265#endif /* !CONFIG_USER_ONLY */
2266
c04321b3 2267/* Initialize list of CPU models, filling some non-static fields if necessary
c6dc6f63
AP		 2268 */
2269void x86_cpudef_setup(void)
2270{
93bfef4c
CV		 2271 int i, j;
2272 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 2273
2274 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
9576de75 2275 X86CPUDefinition *def = &builtin_x86_defs[i];
93bfef4c
CV		 2276
2277 /* Look for specific "cpudef" models that */
09faecf2 2278 /* have the QEMU version in .model_id */
93bfef4c 2279 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
bc3e1291
EH		 2280 if (strcmp(model_with_versions[j], def->name) == 0) {
2281 pstrcpy(def->model_id, sizeof(def->model_id),
2282 "QEMU Virtual CPU version ");
2283 pstrcat(def->model_id, sizeof(def->model_id),
35c2c8dc 2284 qemu_hw_version());
93bfef4c
CV		 2285 break;
2286 }
2287 }
c6dc6f63 2288 }
c6dc6f63
AP		 2289}
2290
c6dc6f63
AP		 2291void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2292 uint32_t *eax, uint32_t *ebx,
2293 uint32_t *ecx, uint32_t *edx)
2294{
a60f24b5
AF		 2295 X86CPU *cpu = x86_env_get_cpu(env);
2296 CPUState *cs = CPU(cpu);
2297
c6dc6f63
AP		 2298 /* test if maximum index reached */
2299 if (index & 0x80000000) {
b3baa152
BW		 2300 if (index > env->cpuid_xlevel) {
2301 if (env->cpuid_xlevel2 > 0) {
2302 /* Handle the Centaur's CPUID instruction. */
2303 if (index > env->cpuid_xlevel2) {
2304 index = env->cpuid_xlevel2;
2305 } else if (index < 0xC0000000) {
2306 index = env->cpuid_xlevel;
2307 }
2308 } else {
57f26ae7
EH		 2309 /* Intel documentation states that invalid EAX input will
2310 * return the same information as EAX=cpuid_level
2311 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2312 */
2313 index = env->cpuid_level;
b3baa152
BW		 2314 }
2315 }
c6dc6f63
AP		 2316 } else {
2317 if (index > env->cpuid_level)
2318 index = env->cpuid_level;
2319 }
2320
2321 switch(index) {
2322 case 0:
2323 *eax = env->cpuid_level;
5eb2f7a4
EH		 2324 *ebx = env->cpuid_vendor1;
2325 *edx = env->cpuid_vendor2;
2326 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2327 break;
2328 case 1:
2329 *eax = env->cpuid_version;
7e72a45c
EH		 2330 *ebx = (cpu->apic_id << 24) |
2331 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2332 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2333 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2334 *ecx |= CPUID_EXT_OSXSAVE;
2335 }
0514ef2f 2336 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2337 if (cs->nr_cores * cs->nr_threads > 1) {
2338 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2339 *edx |= CPUID_HT;
c6dc6f63
AP		 2340 }
2341 break;
2342 case 2:
2343 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2344 if (cpu->cache_info_passthrough) {
2345 host_cpuid(index, 0, eax, ebx, ecx, edx);
2346 break;
2347 }
5e891bf8 2348 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2349 *ebx = 0;
2350 *ecx = 0;
5e891bf8
EH		 2351 *edx = (L1D_DESCRIPTOR << 16) | \
2352 (L1I_DESCRIPTOR << 8) | \
2353 (L2_DESCRIPTOR);
c6dc6f63
AP		 2354 break;
2355 case 4:
2356 /* cache info: needed for Core compatibility */
787aaf57
BC		 2357 if (cpu->cache_info_passthrough) {
2358 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2359 *eax &= ~0xFC000000;
c6dc6f63 2360 } else {
2f7a21c4 2361 *eax = 0;
76c2975a 2362 switch (count) {
c6dc6f63 2363 case 0: /* L1 dcache info */
5e891bf8
EH		 2364 *eax |= CPUID_4_TYPE_DCACHE | \
2365 CPUID_4_LEVEL(1) | \
2366 CPUID_4_SELF_INIT_LEVEL;
2367 *ebx = (L1D_LINE_SIZE - 1) | \
2368 ((L1D_PARTITIONS - 1) << 12) | \
2369 ((L1D_ASSOCIATIVITY - 1) << 22);
2370 *ecx = L1D_SETS - 1;
2371 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2372 break;
2373 case 1: /* L1 icache info */
5e891bf8
EH		 2374 *eax |= CPUID_4_TYPE_ICACHE | \
2375 CPUID_4_LEVEL(1) | \
2376 CPUID_4_SELF_INIT_LEVEL;
2377 *ebx = (L1I_LINE_SIZE - 1) | \
2378 ((L1I_PARTITIONS - 1) << 12) | \
2379 ((L1I_ASSOCIATIVITY - 1) << 22);
2380 *ecx = L1I_SETS - 1;
2381 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2382 break;
2383 case 2: /* L2 cache info */
5e891bf8
EH		 2384 *eax |= CPUID_4_TYPE_UNIFIED | \
2385 CPUID_4_LEVEL(2) | \
2386 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2387 if (cs->nr_threads > 1) {
2388 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2389 }
5e891bf8
EH		 2390 *ebx = (L2_LINE_SIZE - 1) | \
2391 ((L2_PARTITIONS - 1) << 12) | \
2392 ((L2_ASSOCIATIVITY - 1) << 22);
2393 *ecx = L2_SETS - 1;
2394 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2395 break;
2396 default: /* end of info */
2397 *eax = 0;
2398 *ebx = 0;
2399 *ecx = 0;
2400 *edx = 0;
2401 break;
76c2975a
PB		 2402 }
2403 }
2404
2405 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2406 if ((*eax & 31) && cs->nr_cores > 1) {
2407 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2408 }
2409 break;
2410 case 5:
2411 /* mwait info: needed for Core compatibility */
2412 *eax = 0; /* Smallest monitor-line size in bytes */
2413 *ebx = 0; /* Largest monitor-line size in bytes */
2414 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2415 *edx = 0;
2416 break;
2417 case 6:
2418 /* Thermal and Power Leaf */
28b8e4d0 2419 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2420 *ebx = 0;
2421 *ecx = 0;
2422 *edx = 0;
2423 break;
f7911686 2424 case 7:
13526728
EH		 2425 /* Structured Extended Feature Flags Enumeration Leaf */
2426 if (count == 0) {
2427 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2428 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2429 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2430 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2431 *ecx |= CPUID_7_0_ECX_OSPKE;
2432 }
13526728 2433 *edx = 0; /* Reserved */
f7911686
YW		 2434 } else {
2435 *eax = 0;
2436 *ebx = 0;
2437 *ecx = 0;
2438 *edx = 0;
2439 }
2440 break;
c6dc6f63
AP		 2441 case 9:
2442 /* Direct Cache Access Information Leaf */
2443 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2444 *ebx = 0;
2445 *ecx = 0;
2446 *edx = 0;
2447 break;
2448 case 0xA:
2449 /* Architectural Performance Monitoring Leaf */
9337e3b6 2450 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2451 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2452
2453 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2454 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2455 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2456 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2457 } else {
2458 *eax = 0;
2459 *ebx = 0;
2460 *ecx = 0;
2461 *edx = 0;
2462 }
c6dc6f63 2463 break;
2560f19f
PB		 2464 case 0xD: {
2465 KVMState *s = cs->kvm_state;
19dc85db 2466 uint64_t ena_mask;
2560f19f
PB		 2467 int i;
2468
51e49430 2469 /* Processor Extended State */
2560f19f
PB		 2470 *eax = 0;
2471 *ebx = 0;
2472 *ecx = 0;
2473 *edx = 0;
19dc85db 2474 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2475 break;
2476 }
19dc85db
RH		 2477 if (kvm_enabled()) {
2478 ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2479 ena_mask <<= 32;
2480 ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2481 } else {
2482 ena_mask = -1;
2483 }
ba9bc59e 2484
2560f19f
PB		 2485 if (count == 0) {
2486 *ecx = 0x240;
f4f1110e
RH		 2487 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2488 const ExtSaveArea *esa = &x86_ext_save_areas[i];
19dc85db
RH		 2489 if ((env->features[esa->feature] & esa->bits) == esa->bits
2490 && ((ena_mask >> i) & 1) != 0) {
2560f19f 2491 if (i < 32) {
19dc85db 2492 *eax |= 1u << i;
2560f19f 2493 } else {
19dc85db 2494 *edx |= 1u << (i - 32);
2560f19f
PB		 2495 }
2496 *ecx = MAX(*ecx, esa->offset + esa->size);
2497 }
2498 }
cfc3b074 2499 *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2560f19f
PB		 2500 *ebx = *ecx;
2501 } else if (count == 1) {
0bb0b2d2 2502 *eax = env->features[FEAT_XSAVE];
f4f1110e
RH		 2503 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2504 const ExtSaveArea *esa = &x86_ext_save_areas[count];
19dc85db
RH		 2505 if ((env->features[esa->feature] & esa->bits) == esa->bits
2506 && ((ena_mask >> count) & 1) != 0) {
33f373d7
LJ		 2507 *eax = esa->size;
2508 *ebx = esa->offset;
2560f19f 2509 }
51e49430
SY		 2510 }
2511 break;
2560f19f 2512 }
c6dc6f63
AP		 2513 case 0x80000000:
2514 *eax = env->cpuid_xlevel;
2515 *ebx = env->cpuid_vendor1;
2516 *edx = env->cpuid_vendor2;
2517 *ecx = env->cpuid_vendor3;
2518 break;
2519 case 0x80000001:
2520 *eax = env->cpuid_version;
2521 *ebx = 0;
0514ef2f
EH		 2522 *ecx = env->features[FEAT_8000_0001_ECX];
2523 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2524
2525 /* The Linux kernel checks for the CMPLegacy bit and
2526 * discards multiple thread information if it is set.
cb8d4c8f 2527 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2528 */
ce3960eb 2529 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2530 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2531 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2532 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2533 *ecx |= 1 << 1; /* CmpLegacy bit */
2534 }
2535 }
c6dc6f63
AP		 2536 break;
2537 case 0x80000002:
2538 case 0x80000003:
2539 case 0x80000004:
2540 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2541 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2542 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2543 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2544 break;
2545 case 0x80000005:
2546 /* cache info (L1 cache) */
787aaf57
BC		 2547 if (cpu->cache_info_passthrough) {
2548 host_cpuid(index, 0, eax, ebx, ecx, edx);
2549 break;
2550 }
5e891bf8
EH		 2551 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2552 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2553 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2554 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2555 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2556 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2557 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2558 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2559 break;
2560 case 0x80000006:
2561 /* cache info (L2 cache) */
787aaf57
BC		 2562 if (cpu->cache_info_passthrough) {
2563 host_cpuid(index, 0, eax, ebx, ecx, edx);
2564 break;
2565 }
5e891bf8
EH		 2566 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2567 (L2_DTLB_2M_ENTRIES << 16) | \
2568 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2569 (L2_ITLB_2M_ENTRIES);
2570 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2571 (L2_DTLB_4K_ENTRIES << 16) | \
2572 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2573 (L2_ITLB_4K_ENTRIES);
2574 *ecx = (L2_SIZE_KB_AMD << 16) | \
2575 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2576 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2577 *edx = ((L3_SIZE_KB/512) << 18) | \
2578 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2579 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2580 break;
303752a9
MT		 2581 case 0x80000007:
2582 *eax = 0;
2583 *ebx = 0;
2584 *ecx = 0;
2585 *edx = env->features[FEAT_8000_0007_EDX];
2586 break;
c6dc6f63
AP		 2587 case 0x80000008:
2588 /* virtual & phys address size in low 2 bytes. */
2589/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2590 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2591 /* 64 bit processor */
2592/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2593 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2594 } else {
0514ef2f 2595 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2596 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2597 } else {
c6dc6f63 2598 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2599 }
c6dc6f63
AP		 2600 }
2601 *ebx = 0;
2602 *ecx = 0;
2603 *edx = 0;
ce3960eb
AF		 2604 if (cs->nr_cores * cs->nr_threads > 1) {
2605 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2606 }
2607 break;
2608 case 0x8000000A:
0514ef2f 2609 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2610 *eax = 0x00000001; /* SVM Revision */
2611 *ebx = 0x00000010; /* nr of ASIDs */
2612 *ecx = 0;
0514ef2f 2613 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2614 } else {
2615 *eax = 0;
2616 *ebx = 0;
2617 *ecx = 0;
2618 *edx = 0;
2619 }
c6dc6f63 2620 break;
b3baa152
BW		 2621 case 0xC0000000:
2622 *eax = env->cpuid_xlevel2;
2623 *ebx = 0;
2624 *ecx = 0;
2625 *edx = 0;
2626 break;
2627 case 0xC0000001:
2628 /* Support for VIA CPU's CPUID instruction */
2629 *eax = env->cpuid_version;
2630 *ebx = 0;
2631 *ecx = 0;
0514ef2f 2632 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2633 break;
2634 case 0xC0000002:
2635 case 0xC0000003:
2636 case 0xC0000004:
2637 /* Reserved for the future, and now filled with zero */
2638 *eax = 0;
2639 *ebx = 0;
2640 *ecx = 0;
2641 *edx = 0;
2642 break;
c6dc6f63
AP		 2643 default:
2644 /* reserved values: zero */
2645 *eax = 0;
2646 *ebx = 0;
2647 *ecx = 0;
2648 *edx = 0;
2649 break;
2650 }
2651}
5fd2087a
AF		 2652
2653/* CPUClass::reset() */
2654static void x86_cpu_reset(CPUState *s)
2655{
2656 X86CPU *cpu = X86_CPU(s);
2657 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2658 CPUX86State *env = &cpu->env;
a114d25d
RH		 2659 target_ulong cr4;
2660 uint64_t xcr0;
c1958aea
AF		 2661 int i;
2662
5fd2087a
AF		 2663 xcc->parent_reset(s);
2664
43175fa9 2665 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2666
00c8cb0a 2667 tlb_flush(s, 1);
c1958aea
AF		 2668
2669 env->old_exception = -1;
2670
2671 /* init to reset state */
2672
2673#ifdef CONFIG_SOFTMMU
2674 env->hflags |= HF_SOFTMMU_MASK;
2675#endif
2676 env->hflags2 |= HF2_GIF_MASK;
2677
2678 cpu_x86_update_cr0(env, 0x60000010);
2679 env->a20_mask = ~0x0;
2680 env->smbase = 0x30000;
2681
2682 env->idt.limit = 0xffff;
2683 env->gdt.limit = 0xffff;
2684 env->ldt.limit = 0xffff;
2685 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2686 env->tr.limit = 0xffff;
2687 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2688
2689 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2690 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2691 DESC_R_MASK | DESC_A_MASK);
2692 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2693 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2694 DESC_A_MASK);
2695 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2696 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2697 DESC_A_MASK);
2698 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2699 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2700 DESC_A_MASK);
2701 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2702 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2703 DESC_A_MASK);
2704 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2705 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2706 DESC_A_MASK);
2707
2708 env->eip = 0xfff0;
2709 env->regs[R_EDX] = env->cpuid_version;
2710
2711 env->eflags = 0x2;
2712
2713 /* FPU init */
2714 for (i = 0; i < 8; i++) {
2715 env->fptags[i] = 1;
2716 }
5bde1407 2717 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2718
2719 env->mxcsr = 0x1f80;
a114d25d
RH		 2720 /* All units are in INIT state. */
2721 env->xstate_bv = 0;
c1958aea
AF		 2722
2723 env->pat = 0x0007040600070406ULL;
2724 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2725
2726 memset(env->dr, 0, sizeof(env->dr));
2727 env->dr[6] = DR6_FIXED_1;
2728 env->dr[7] = DR7_FIXED_1;
b3310ab3 2729 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2730 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2731
a114d25d 2732 cr4 = 0;
cfc3b074 2733 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2734
2735#ifdef CONFIG_USER_ONLY
2736 /* Enable all the features for user-mode. */
2737 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2738 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2739 }
0f70ed47
PB		 2740 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2741 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2742 if ((env->features[esa->feature] & esa->bits) == esa->bits) {
2743 xcr0 |= 1ull << i;
2744 }
a114d25d 2745 }
0f70ed47 2746
a114d25d
RH		 2747 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2748 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2749 }
07929f2a
RH		 2750 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2751 cr4 |= CR4_FSGSBASE_MASK;
2752 }
a114d25d
RH		 2753#endif
2754
2755 env->xcr0 = xcr0;
2756 cpu_x86_update_cr4(env, cr4);
0522604b 2757
9db2efd9
AW		 2758 /*
2759 * SDM 11.11.5 requires:
2760 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2761 * - IA32_MTRR_PHYSMASKn.V = 0
2762 * All other bits are undefined. For simplification, zero it all.
2763 */
2764 env->mtrr_deftype = 0;
2765 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2766 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2767
dd673288
IM		 2768#if !defined(CONFIG_USER_ONLY)
2769 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2770 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2771
259186a7 2772 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2773
2774 if (kvm_enabled()) {
2775 kvm_arch_reset_vcpu(cpu);
2776 }
dd673288 2777#endif
5fd2087a
AF		 2778}
2779
dd673288
IM		 2780#ifndef CONFIG_USER_ONLY
2781bool cpu_is_bsp(X86CPU *cpu)
2782{
02e51483 2783 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2784}
65dee380
IM		 2785
2786/* TODO: remove me, when reset over QOM tree is implemented */
2787static void x86_cpu_machine_reset_cb(void *opaque)
2788{
2789 X86CPU *cpu = opaque;
2790 cpu_reset(CPU(cpu));
2791}
dd673288
IM		 2792#endif
2793
de024815
AF		 2794static void mce_init(X86CPU *cpu)
2795{
2796 CPUX86State *cenv = &cpu->env;
2797 unsigned int bank;
2798
2799 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2800 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2801 (CPUID_MCE | CPUID_MCA)) {
2802 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2803 cenv->mcg_ctl = ~(uint64_t)0;
2804 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2805 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2806 }
2807 }
2808}
2809
bdeec802 2810#ifndef CONFIG_USER_ONLY
d3c64d6a 2811static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2812{
449994eb 2813 APICCommonState *apic;
bdeec802
IM		 2814 const char *apic_type = "apic";
2815
15eafc2e 2816 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2817 apic_type = "kvm-apic";
2818 } else if (xen_enabled()) {
2819 apic_type = "xen-apic";
2820 }
2821
46232aaa 2822 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802
IM		 2823
2824 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2825 OBJECT(cpu->apic_state), NULL);
7e72a45c 2826 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2827 /* TODO: convert to link<> */
02e51483 2828 apic = APIC_COMMON(cpu->apic_state);
60671e58 2829 apic->cpu = cpu;
8d42d2d3 2830 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2831}
2832
2833static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2834{
8d42d2d3
CF		 2835 APICCommonState *apic;
2836 static bool apic_mmio_map_once;
2837
02e51483 2838 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2839 return;
2840 }
6e8e2651
MA		 2841 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2842 errp);
8d42d2d3
CF		 2843
2844 /* Map APIC MMIO area */
2845 apic = APIC_COMMON(cpu->apic_state);
2846 if (!apic_mmio_map_once) {
2847 memory_region_add_subregion_overlap(get_system_memory(),
2848 apic->apicbase &
2849 MSR_IA32_APICBASE_BASE,
2850 &apic->io_memory,
2851 0x1000);
2852 apic_mmio_map_once = true;
2853 }
bdeec802 2854}
f809c605
PB		 2855
2856static void x86_cpu_machine_done(Notifier *n, void *unused)
2857{
2858 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2859 MemoryRegion *smram =
2860 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2861
2862 if (smram) {
2863 cpu->smram = g_new(MemoryRegion, 1);
2864 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2865 smram, 0, 1ull << 32);
2866 memory_region_set_enabled(cpu->smram, false);
2867 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2868 }
2869}
d3c64d6a
IM		 2870#else
2871static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2872{
2873}
bdeec802
IM		 2874#endif
2875
e48638fd
WH		 2876
2877#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2878 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2879 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2880#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2881 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2882 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2883static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2884{
14a10fc3 2885 CPUState *cs = CPU(dev);
2b6f294c
AF		 2886 X86CPU *cpu = X86_CPU(dev);
2887 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2888 CPUX86State *env = &cpu->env;
2b6f294c 2889 Error *local_err = NULL;
e48638fd 2890 static bool ht_warned;
b34d12d1 2891
9886e834
EH		 2892 if (cpu->apic_id < 0) {
2893 error_setg(errp, "apic-id property was not initialized properly");
2894 return;
2895 }
2896
0514ef2f 2897 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2898 env->cpuid_level = 7;
2899 }
7a059953 2900
9997cf7b
EH		 2901 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2902 error_setg(&local_err,
2903 kvm_enabled() ?
2904 "Host doesn't support requested features" :
2905 "TCG doesn't support requested features");
2906 goto out;
2907 }
2908
9b15cd9e
IM		 2909 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2910 * CPUID[1].EDX.
2911 */
e48638fd 2912 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2913 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2914 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2915 & CPUID_EXT2_AMD_ALIASES);
2916 }
2917
fefb41bf 2918
65dee380
IM		 2919#ifndef CONFIG_USER_ONLY
2920 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2921
0514ef2f 2922 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2923 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2924 if (local_err != NULL) {
4dc1f449 2925 goto out;
bdeec802
IM		 2926 }
2927 }
65dee380
IM		 2928#endif
2929
7a059953 2930 mce_init(cpu);
2001d0cd
PB		 2931
2932#ifndef CONFIG_USER_ONLY
2933 if (tcg_enabled()) {
56943e8c
PM		 2934 AddressSpace *newas = g_new(AddressSpace, 1);
2935
f809c605 2936 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 2937 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 2938
2939 /* Outer container... */
2940 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2941 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2942
2943 /* ... with two regions inside: normal system memory with low
2944 * priority, and...
2945 */
2946 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2947 get_system_memory(), 0, ~0ull);
2948 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2949 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 2950 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 2951 cs->num_ases = 1;
56943e8c 2952 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 2953
2954 /* ... SMRAM with higher priority, linked from /machine/smram. */
2955 cpu->machine_done.notify = x86_cpu_machine_done;
2956 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2957 }
2958#endif
2959
14a10fc3 2960 qemu_init_vcpu(cs);
d3c64d6a 2961
e48638fd
WH		 2962 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2963 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2964 * based on inputs (sockets,cores,threads), it is still better to gives
2965 * users a warning.
2966 *
2967 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
2968 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
2969 */
2970 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
2971 error_report("AMD CPU doesn't support hyperthreading. Please configure"
2972 " -smp options properly.");
2973 ht_warned = true;
2974 }
2975
d3c64d6a
IM		 2976 x86_cpu_apic_realize(cpu, &local_err);
2977 if (local_err != NULL) {
2978 goto out;
2979 }
14a10fc3 2980 cpu_reset(cs);
2b6f294c 2981
4dc1f449 2982 xcc->parent_realize(dev, &local_err);
2001d0cd 2983
4dc1f449
IM		 2984out:
2985 if (local_err != NULL) {
2986 error_propagate(errp, local_err);
2987 return;
2988 }
7a059953
AF		 2989}
2990
38e5c119
EH		 2991typedef struct BitProperty {
2992 uint32_t *ptr;
2993 uint32_t mask;
2994} BitProperty;
2995
d7bce999
EB		 2996static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
2997 void *opaque, Error **errp)
38e5c119
EH		 2998{
2999 BitProperty *fp = opaque;
3000 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3001 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3002}
3003
d7bce999
EB		 3004static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3005 void *opaque, Error **errp)
38e5c119
EH		 3006{
3007 DeviceState *dev = DEVICE(obj);
3008 BitProperty *fp = opaque;
3009 Error *local_err = NULL;
3010 bool value;
3011
3012 if (dev->realized) {
3013 qdev_prop_set_after_realize(dev, name, errp);
3014 return;
3015 }
3016
51e72bc1 3017 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3018 if (local_err) {
3019 error_propagate(errp, local_err);
3020 return;
3021 }
3022
3023 if (value) {
3024 *fp->ptr |= fp->mask;
3025 } else {
3026 *fp->ptr &= ~fp->mask;
3027 }
3028}
3029
3030static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3031 void *opaque)
3032{
3033 BitProperty *prop = opaque;
3034 g_free(prop);
3035}
3036
3037/* Register a boolean property to get/set a single bit in a uint32_t field.
3038 *
3039 * The same property name can be registered multiple times to make it affect
3040 * multiple bits in the same FeatureWord. In that case, the getter will return
3041 * true only if all bits are set.
3042 */
3043static void x86_cpu_register_bit_prop(X86CPU *cpu,
3044 const char *prop_name,
3045 uint32_t *field,
3046 int bitnr)
3047{
3048 BitProperty *fp;
3049 ObjectProperty *op;
3050 uint32_t mask = (1UL << bitnr);
3051
3052 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3053 if (op) {
3054 fp = op->opaque;
3055 assert(fp->ptr == field);
3056 fp->mask |= mask;
3057 } else {
3058 fp = g_new0(BitProperty, 1);
3059 fp->ptr = field;
3060 fp->mask = mask;
3061 object_property_add(OBJECT(cpu), prop_name, "bool",
3062 x86_cpu_get_bit_prop,
3063 x86_cpu_set_bit_prop,
3064 x86_cpu_release_bit_prop, fp, &error_abort);
3065 }
3066}
3067
3068static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3069 FeatureWord w,
3070 int bitnr)
3071{
3072 Object *obj = OBJECT(cpu);
3073 int i;
3074 char **names;
3075 FeatureWordInfo *fi = &feature_word_info[w];
3076
3077 if (!fi->feat_names) {
3078 return;
3079 }
3080 if (!fi->feat_names[bitnr]) {
3081 return;
3082 }
3083
3084 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3085
3086 feat2prop(names[0]);
3087 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3088
3089 for (i = 1; names[i]; i++) {
3090 feat2prop(names[i]);
d461a44c 3091 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3092 &error_abort);
3093 }
3094
3095 g_strfreev(names);
3096}
3097
de024815
AF		 3098static void x86_cpu_initfn(Object *obj)
3099{
55e5c285 3100 CPUState *cs = CPU(obj);
de024815 3101 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3102 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3103 CPUX86State *env = &cpu->env;
38e5c119 3104 FeatureWord w;
d65e9815 3105 static int inited;
de024815 3106
c05efcb1 3107 cs->env_ptr = env;
4bad9e39 3108 cpu_exec_init(cs, &error_abort);
71ad61d3
AF		 3109
3110 object_property_add(obj, "family", "int",
95b8519d 3111 x86_cpuid_version_get_family,
71ad61d3 3112 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3113 object_property_add(obj, "model", "int",
67e30c83 3114 x86_cpuid_version_get_model,
c5291a4f 3115 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3116 object_property_add(obj, "stepping", "int",
35112e41 3117 x86_cpuid_version_get_stepping,
036e2222 3118 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3119 object_property_add_str(obj, "vendor",
3120 x86_cpuid_get_vendor,
3121 x86_cpuid_set_vendor, NULL);
938d4c25 3122 object_property_add_str(obj, "model-id",
63e886eb 3123 x86_cpuid_get_model_id,
938d4c25 3124 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3125 object_property_add(obj, "tsc-frequency", "int",
3126 x86_cpuid_get_tsc_freq,
3127 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3128 object_property_add(obj, "apic-id", "int",
3129 x86_cpuid_get_apic_id,
3130 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3131 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3132 x86_cpu_get_feature_words,
7e5292b5
EH		 3133 NULL, NULL, (void *)env->features, NULL);
3134 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3135 x86_cpu_get_feature_words,
3136 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3137
92067bf4 3138 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3139
9886e834
EH		 3140#ifndef CONFIG_USER_ONLY
3141 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3142 cpu->apic_id = -1;
3143#endif
3144
38e5c119
EH		 3145 for (w = 0; w < FEATURE_WORDS; w++) {
3146 int bitnr;
3147
3148 for (bitnr = 0; bitnr < 32; bitnr++) {
3149 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3150 }
3151 }
3152
d940ee9b
EH		 3153 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3154
d65e9815
IM		 3155 /* init various static tables used in TCG mode */
3156 if (tcg_enabled() && !inited) {
3157 inited = 1;
63618b4e 3158 tcg_x86_init();
d65e9815 3159 }
de024815
AF		 3160}
3161
997395d3
IM		 3162static int64_t x86_cpu_get_arch_id(CPUState *cs)
3163{
3164 X86CPU *cpu = X86_CPU(cs);
997395d3 3165
7e72a45c 3166 return cpu->apic_id;
997395d3
IM		 3167}
3168
444d5590
AF		 3169static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3170{
3171 X86CPU *cpu = X86_CPU(cs);
3172
3173 return cpu->env.cr[0] & CR0_PG_MASK;
3174}
3175
f45748f1
AF		 3176static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3177{
3178 X86CPU *cpu = X86_CPU(cs);
3179
3180 cpu->env.eip = value;
3181}
3182
bdf7ae5b
AF		 3183static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3184{
3185 X86CPU *cpu = X86_CPU(cs);
3186
3187 cpu->env.eip = tb->pc - tb->cs_base;
3188}
3189
8c2e1b00
AF		 3190static bool x86_cpu_has_work(CPUState *cs)
3191{
3192 X86CPU *cpu = X86_CPU(cs);
3193 CPUX86State *env = &cpu->env;
3194
6220e900
PD		 3195 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3196 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3197 (env->eflags & IF_MASK)) ||
3198 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3199 CPU_INTERRUPT_INIT |
3200 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3201 CPU_INTERRUPT_MCE)) ||
3202 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3203 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3204}
3205
9337e3b6
EH		 3206static Property x86_cpu_properties[] = {
3207 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3208 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3209 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3210 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3211 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3212 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3213 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3214 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3215 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3216 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3217 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3218 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3219 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3220 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3221 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3222 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3223 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
1c4a55db 3224 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
9337e3b6
EH		 3225 DEFINE_PROP_END_OF_LIST()
3226};
3227
5fd2087a
AF		 3228static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3229{
3230 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3231 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3232 DeviceClass *dc = DEVICE_CLASS(oc);
3233
3234 xcc->parent_realize = dc->realize;
3235 dc->realize = x86_cpu_realizefn;
9337e3b6 3236 dc->props = x86_cpu_properties;
5fd2087a
AF		 3237
3238 xcc->parent_reset = cc->reset;
3239 cc->reset = x86_cpu_reset;
91b1df8c 3240 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3241
500050d1 3242 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3243 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3244 cc->has_work = x86_cpu_has_work;
97a8ea5a 3245 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3246 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3247 cc->dump_state = x86_cpu_dump_state;
f45748f1 3248 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3249 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3250 cc->gdb_read_register = x86_cpu_gdb_read_register;
3251 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3252 cc->get_arch_id = x86_cpu_get_arch_id;
3253 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3254#ifdef CONFIG_USER_ONLY
3255 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3256#else
a23bbfda 3257 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3258 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3259 cc->write_elf64_note = x86_cpu_write_elf64_note;
3260 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3261 cc->write_elf32_note = x86_cpu_write_elf32_note;
3262 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3263 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3264#endif
a0e372f0 3265 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3266#ifndef CONFIG_USER_ONLY
3267 cc->debug_excp_handler = breakpoint_handler;
3268#endif
374e0cd4
RH		 3269 cc->cpu_exec_enter = x86_cpu_exec_enter;
3270 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27
MA		 3271
3272 /*
3273 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3274 * object in cpus -> dangling pointer after final object_unref().
3275 */
3276 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3277}
3278
3279static const TypeInfo x86_cpu_type_info = {
3280 .name = TYPE_X86_CPU,
3281 .parent = TYPE_CPU,
3282 .instance_size = sizeof(X86CPU),
de024815 3283 .instance_init = x86_cpu_initfn,
d940ee9b 3284 .abstract = true,
5fd2087a
AF		 3285 .class_size = sizeof(X86CPUClass),
3286 .class_init = x86_cpu_common_class_init,
3287};
3288
3289static void x86_cpu_register_types(void)
3290{
d940ee9b
EH		 3291 int i;
3292
5fd2087a 3293 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3294 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3295 x86_register_cpudef_type(&builtin_x86_defs[i]);
3296 }
3297#ifdef CONFIG_KVM
3298 type_register_static(&host_x86_cpu_type_info);
3299#endif
5fd2087a
AF		 3300}
3301
3302type_init(x86_cpu_register_types)
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