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KVM: vmx: Inject #GP on invalid PAT CR
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d77c26fc 475 } host_state;
9c8cba37 476 struct {
7ffd92c5 477 int vm86_active;
78ac8b47 478 ulong save_rflags;
f5f7b2fe
AK		 479 struct kvm_segment segs[8];
480 } rmode;
481 struct {
482 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 483 struct kvm_save_segment {
484 u16 selector;
485 unsigned long base;
486 u32 limit;
487 u32 ar;
f5f7b2fe 488 } seg[8];
2fb92db1 489 } segment_cache;
2384d2b3 490 int vpid;
04fa4d32 491 bool emulation_required;
3b86cd99
JK		 492
493 /* Support for vnmi-less CPUs */
494 int soft_vnmi_blocked;
495 ktime_t entry_time;
496 s64 vnmi_blocked_time;
a0861c02 497 u32 exit_reason;
4e47c7a6
SY		 498
499 bool rdtscp_enabled;
ec378aee 500
01e439be
YZ		 501 /* Posted interrupt descriptor */
502 struct pi_desc pi_desc;
503
ec378aee
NHE		 504 /* Support for a guest hypervisor (nested VMX) */
505 struct nested_vmx nested;
a7653ecd
RK		 506
507 /* Dynamic PLE window. */
508 int ple_window;
509 bool ple_window_dirty;
a2fa3e9f
GH		 510};
511
2fb92db1
AK		 512enum segment_cache_field {
513 SEG_FIELD_SEL = 0,
514 SEG_FIELD_BASE = 1,
515 SEG_FIELD_LIMIT = 2,
516 SEG_FIELD_AR = 3,
517
518 SEG_FIELD_NR = 4
519};
520
a2fa3e9f
GH		 521static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
522{
fb3f0f51 523 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 524}
525
22bd0358
NHE		 526#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
527#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
528#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
529 [number##_HIGH] = VMCS12_OFFSET(name)+4
530
4607c2d7 531
fe2b201b 532static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 533 /*
534 * We do NOT shadow fields that are modified when L0
535 * traps and emulates any vmx instruction (e.g. VMPTRLD,
536 * VMXON...) executed by L1.
537 * For example, VM_INSTRUCTION_ERROR is read
538 * by L1 if a vmx instruction fails (part of the error path).
539 * Note the code assumes this logic. If for some reason
540 * we start shadowing these fields then we need to
541 * force a shadow sync when L0 emulates vmx instructions
542 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
543 * by nested_vmx_failValid)
544 */
545 VM_EXIT_REASON,
546 VM_EXIT_INTR_INFO,
547 VM_EXIT_INSTRUCTION_LEN,
548 IDT_VECTORING_INFO_FIELD,
549 IDT_VECTORING_ERROR_CODE,
550 VM_EXIT_INTR_ERROR_CODE,
551 EXIT_QUALIFICATION,
552 GUEST_LINEAR_ADDRESS,
553 GUEST_PHYSICAL_ADDRESS
554};
fe2b201b 555static int max_shadow_read_only_fields =
4607c2d7
AG		 556 ARRAY_SIZE(shadow_read_only_fields);
557
fe2b201b 558static unsigned long shadow_read_write_fields[] = {
a7c0b07d 559 TPR_THRESHOLD,
4607c2d7
AG		 560 GUEST_RIP,
561 GUEST_RSP,
562 GUEST_CR0,
563 GUEST_CR3,
564 GUEST_CR4,
565 GUEST_INTERRUPTIBILITY_INFO,
566 GUEST_RFLAGS,
567 GUEST_CS_SELECTOR,
568 GUEST_CS_AR_BYTES,
569 GUEST_CS_LIMIT,
570 GUEST_CS_BASE,
571 GUEST_ES_BASE,
36be0b9d 572 GUEST_BNDCFGS,
4607c2d7
AG		 573 CR0_GUEST_HOST_MASK,
574 CR0_READ_SHADOW,
575 CR4_READ_SHADOW,
576 TSC_OFFSET,
577 EXCEPTION_BITMAP,
578 CPU_BASED_VM_EXEC_CONTROL,
579 VM_ENTRY_EXCEPTION_ERROR_CODE,
580 VM_ENTRY_INTR_INFO_FIELD,
581 VM_ENTRY_INSTRUCTION_LEN,
582 VM_ENTRY_EXCEPTION_ERROR_CODE,
583 HOST_FS_BASE,
584 HOST_GS_BASE,
585 HOST_FS_SELECTOR,
586 HOST_GS_SELECTOR
587};
fe2b201b 588static int max_shadow_read_write_fields =
4607c2d7
AG		 589 ARRAY_SIZE(shadow_read_write_fields);
590
772e0318 591static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 592 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
593 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
594 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
595 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
596 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
597 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
598 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
599 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
600 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
601 FIELD(HOST_ES_SELECTOR, host_es_selector),
602 FIELD(HOST_CS_SELECTOR, host_cs_selector),
603 FIELD(HOST_SS_SELECTOR, host_ss_selector),
604 FIELD(HOST_DS_SELECTOR, host_ds_selector),
605 FIELD(HOST_FS_SELECTOR, host_fs_selector),
606 FIELD(HOST_GS_SELECTOR, host_gs_selector),
607 FIELD(HOST_TR_SELECTOR, host_tr_selector),
608 FIELD64(IO_BITMAP_A, io_bitmap_a),
609 FIELD64(IO_BITMAP_B, io_bitmap_b),
610 FIELD64(MSR_BITMAP, msr_bitmap),
611 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
612 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
613 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
614 FIELD64(TSC_OFFSET, tsc_offset),
615 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
616 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
617 FIELD64(EPT_POINTER, ept_pointer),
618 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
619 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
620 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
621 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
622 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
623 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
624 FIELD64(GUEST_PDPTR0, guest_pdptr0),
625 FIELD64(GUEST_PDPTR1, guest_pdptr1),
626 FIELD64(GUEST_PDPTR2, guest_pdptr2),
627 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 628 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 629 FIELD64(HOST_IA32_PAT, host_ia32_pat),
630 FIELD64(HOST_IA32_EFER, host_ia32_efer),
631 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
632 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
633 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
634 FIELD(EXCEPTION_BITMAP, exception_bitmap),
635 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
636 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
637 FIELD(CR3_TARGET_COUNT, cr3_target_count),
638 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
639 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
640 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
641 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
642 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
643 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
644 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
645 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
646 FIELD(TPR_THRESHOLD, tpr_threshold),
647 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
648 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
649 FIELD(VM_EXIT_REASON, vm_exit_reason),
650 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
651 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
652 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
653 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
654 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
655 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
656 FIELD(GUEST_ES_LIMIT, guest_es_limit),
657 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
658 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
659 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
660 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
661 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
662 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
663 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
664 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
665 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
666 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
667 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
668 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
669 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
670 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
671 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
672 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
673 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
674 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
675 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
676 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
677 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 678 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 679 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
680 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
681 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
682 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
683 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
684 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
685 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
686 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
687 FIELD(EXIT_QUALIFICATION, exit_qualification),
688 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
689 FIELD(GUEST_CR0, guest_cr0),
690 FIELD(GUEST_CR3, guest_cr3),
691 FIELD(GUEST_CR4, guest_cr4),
692 FIELD(GUEST_ES_BASE, guest_es_base),
693 FIELD(GUEST_CS_BASE, guest_cs_base),
694 FIELD(GUEST_SS_BASE, guest_ss_base),
695 FIELD(GUEST_DS_BASE, guest_ds_base),
696 FIELD(GUEST_FS_BASE, guest_fs_base),
697 FIELD(GUEST_GS_BASE, guest_gs_base),
698 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
699 FIELD(GUEST_TR_BASE, guest_tr_base),
700 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
701 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
702 FIELD(GUEST_DR7, guest_dr7),
703 FIELD(GUEST_RSP, guest_rsp),
704 FIELD(GUEST_RIP, guest_rip),
705 FIELD(GUEST_RFLAGS, guest_rflags),
706 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
707 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
708 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
709 FIELD(HOST_CR0, host_cr0),
710 FIELD(HOST_CR3, host_cr3),
711 FIELD(HOST_CR4, host_cr4),
712 FIELD(HOST_FS_BASE, host_fs_base),
713 FIELD(HOST_GS_BASE, host_gs_base),
714 FIELD(HOST_TR_BASE, host_tr_base),
715 FIELD(HOST_GDTR_BASE, host_gdtr_base),
716 FIELD(HOST_IDTR_BASE, host_idtr_base),
717 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
718 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
719 FIELD(HOST_RSP, host_rsp),
720 FIELD(HOST_RIP, host_rip),
721};
722static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
723
724static inline short vmcs_field_to_offset(unsigned long field)
725{
726 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
727 return -1;
728 return vmcs_field_to_offset_table[field];
729}
730
a9d30f33
NHE		 731static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
732{
733 return to_vmx(vcpu)->nested.current_vmcs12;
734}
735
736static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
737{
738 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 739 if (is_error_page(page))
a9d30f33 740 return NULL;
32cad84f 741
a9d30f33
NHE		 742 return page;
743}
744
745static void nested_release_page(struct page *page)
746{
747 kvm_release_page_dirty(page);
748}
749
750static void nested_release_page_clean(struct page *page)
751{
752 kvm_release_page_clean(page);
753}
754
bfd0a56b 755static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 756static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 757static void kvm_cpu_vmxon(u64 addr);
758static void kvm_cpu_vmxoff(void);
93c4adc7 759static bool vmx_mpx_supported(void);
776e58ea 760static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 761static void vmx_set_segment(struct kvm_vcpu *vcpu,
762 struct kvm_segment *var, int seg);
763static void vmx_get_segment(struct kvm_vcpu *vcpu,
764 struct kvm_segment *var, int seg);
d99e4152
GN		 765static bool guest_state_valid(struct kvm_vcpu *vcpu);
766static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 767static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 768static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 769static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 770static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 771
6aa8b732
AK		 772static DEFINE_PER_CPU(struct vmcs *, vmxarea);
773static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 774/*
775 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
776 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
777 */
778static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 779static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 780
3e7c73e9
AK		 781static unsigned long *vmx_io_bitmap_a;
782static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 783static unsigned long *vmx_msr_bitmap_legacy;
784static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 785static unsigned long *vmx_msr_bitmap_legacy_x2apic;
786static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 787static unsigned long *vmx_vmread_bitmap;
788static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 789
110312c8 790static bool cpu_has_load_ia32_efer;
8bf00a52 791static bool cpu_has_load_perf_global_ctrl;
110312c8 792
2384d2b3
SY		 793static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
794static DEFINE_SPINLOCK(vmx_vpid_lock);
795
1c3d14fe 796static struct vmcs_config {
6aa8b732
AK		 797 int size;
798 int order;
799 u32 revision_id;
1c3d14fe
YS		 800 u32 pin_based_exec_ctrl;
801 u32 cpu_based_exec_ctrl;
f78e0e2e 802 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 803 u32 vmexit_ctrl;
804 u32 vmentry_ctrl;
805} vmcs_config;
6aa8b732 806
efff9e53 807static struct vmx_capability {
d56f546d
SY		 808 u32 ept;
809 u32 vpid;
810} vmx_capability;
811
6aa8b732
AK		 812#define VMX_SEGMENT_FIELD(seg) \
813 [VCPU_SREG_##seg] = { \
814 .selector = GUEST_##seg##_SELECTOR, \
815 .base = GUEST_##seg##_BASE, \
816 .limit = GUEST_##seg##_LIMIT, \
817 .ar_bytes = GUEST_##seg##_AR_BYTES, \
818 }
819
772e0318 820static const struct kvm_vmx_segment_field {
6aa8b732
AK		 821 unsigned selector;
822 unsigned base;
823 unsigned limit;
824 unsigned ar_bytes;
825} kvm_vmx_segment_fields[] = {
826 VMX_SEGMENT_FIELD(CS),
827 VMX_SEGMENT_FIELD(DS),
828 VMX_SEGMENT_FIELD(ES),
829 VMX_SEGMENT_FIELD(FS),
830 VMX_SEGMENT_FIELD(GS),
831 VMX_SEGMENT_FIELD(SS),
832 VMX_SEGMENT_FIELD(TR),
833 VMX_SEGMENT_FIELD(LDTR),
834};
835
26bb0981
AK		 836static u64 host_efer;
837
6de4f3ad
AK		 838static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
839
4d56c8a7 840/*
8c06585d 841 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 842 * away by decrementing the array size.
843 */
6aa8b732 844static const u32 vmx_msr_index[] = {
05b3e0c2 845#ifdef CONFIG_X86_64
44ea2b17 846 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 847#endif
8c06585d 848 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 849};
6aa8b732 850
31299944 851static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 852{
853 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
854 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 855 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 856}
857
31299944 858static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 859{
860 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
861 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 862 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 863}
864
31299944 865static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 866{
867 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
868 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 869 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 870}
871
31299944 872static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 873{
874 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
875 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
876}
877
31299944 878static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 879{
880 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
881 INTR_INFO_VALID_MASK)) ==
882 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
883}
884
31299944 885static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 886{
04547156 887 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 888}
889
31299944 890static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 891{
04547156 892 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 893}
894
31299944 895static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 896{
04547156 897 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 898}
899
31299944 900static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 901{
04547156
SY		 902 return vmcs_config.cpu_based_exec_ctrl &
903 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 904}
905
774ead3a 906static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 907{
04547156
SY		 908 return vmcs_config.cpu_based_2nd_exec_ctrl &
909 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
910}
911
8d14695f
YZ		 912static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
913{
914 return vmcs_config.cpu_based_2nd_exec_ctrl &
915 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
916}
917
83d4c286
YZ		 918static inline bool cpu_has_vmx_apic_register_virt(void)
919{
920 return vmcs_config.cpu_based_2nd_exec_ctrl &
921 SECONDARY_EXEC_APIC_REGISTER_VIRT;
922}
923
c7c9c56c
YZ		 924static inline bool cpu_has_vmx_virtual_intr_delivery(void)
925{
926 return vmcs_config.cpu_based_2nd_exec_ctrl &
927 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
928}
929
01e439be
YZ		 930static inline bool cpu_has_vmx_posted_intr(void)
931{
932 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
933}
934
935static inline bool cpu_has_vmx_apicv(void)
936{
937 return cpu_has_vmx_apic_register_virt() &&
938 cpu_has_vmx_virtual_intr_delivery() &&
939 cpu_has_vmx_posted_intr();
940}
941
04547156
SY		 942static inline bool cpu_has_vmx_flexpriority(void)
943{
944 return cpu_has_vmx_tpr_shadow() &&
945 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 946}
947
e799794e
MT		 948static inline bool cpu_has_vmx_ept_execute_only(void)
949{
31299944 950 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 951}
952
953static inline bool cpu_has_vmx_eptp_uncacheable(void)
954{
31299944 955 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 956}
957
958static inline bool cpu_has_vmx_eptp_writeback(void)
959{
31299944 960 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 961}
962
963static inline bool cpu_has_vmx_ept_2m_page(void)
964{
31299944 965 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 966}
967
878403b7
SY		 968static inline bool cpu_has_vmx_ept_1g_page(void)
969{
31299944 970 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 971}
972
4bc9b982
SY		 973static inline bool cpu_has_vmx_ept_4levels(void)
974{
975 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
976}
977
83c3a331
XH		 978static inline bool cpu_has_vmx_ept_ad_bits(void)
979{
980 return vmx_capability.ept & VMX_EPT_AD_BIT;
981}
982
31299944 983static inline bool cpu_has_vmx_invept_context(void)
d56f546d 984{
31299944 985 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 986}
987
31299944 988static inline bool cpu_has_vmx_invept_global(void)
d56f546d 989{
31299944 990 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 991}
992
518c8aee
GJ		 993static inline bool cpu_has_vmx_invvpid_single(void)
994{
995 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
996}
997
b9d762fa
GJ		 998static inline bool cpu_has_vmx_invvpid_global(void)
999{
1000 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1001}
1002
31299944 1003static inline bool cpu_has_vmx_ept(void)
d56f546d 1004{
04547156
SY		 1005 return vmcs_config.cpu_based_2nd_exec_ctrl &
1006 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1007}
1008
31299944 1009static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1010{
1011 return vmcs_config.cpu_based_2nd_exec_ctrl &
1012 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1013}
1014
31299944 1015static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1016{
1017 return vmcs_config.cpu_based_2nd_exec_ctrl &
1018 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1019}
1020
31299944 1021static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1022{
6d3e435e 1023 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1024}
1025
31299944 1026static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1027{
04547156
SY		 1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1033{
1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_RDTSCP;
1036}
1037
ad756a16
MJ		 1038static inline bool cpu_has_vmx_invpcid(void)
1039{
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_ENABLE_INVPCID;
1042}
1043
31299944 1044static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1045{
1046 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1047}
1048
f5f48ee1
SY		 1049static inline bool cpu_has_vmx_wbinvd_exit(void)
1050{
1051 return vmcs_config.cpu_based_2nd_exec_ctrl &
1052 SECONDARY_EXEC_WBINVD_EXITING;
1053}
1054
abc4fc58
AG		 1055static inline bool cpu_has_vmx_shadow_vmcs(void)
1056{
1057 u64 vmx_msr;
1058 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1059 /* check if the cpu supports writing r/o exit information fields */
1060 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1061 return false;
1062
1063 return vmcs_config.cpu_based_2nd_exec_ctrl &
1064 SECONDARY_EXEC_SHADOW_VMCS;
1065}
1066
04547156
SY		 1067static inline bool report_flexpriority(void)
1068{
1069 return flexpriority_enabled;
1070}
1071
fe3ef05c
NHE		 1072static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1073{
1074 return vmcs12->cpu_based_vm_exec_control & bit;
1075}
1076
1077static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1078{
1079 return (vmcs12->cpu_based_vm_exec_control &
1080 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1081 (vmcs12->secondary_vm_exec_control & bit);
1082}
1083
f5c4368f 1084static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1085{
1086 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1087}
1088
f4124500
JK		 1089static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1090{
1091 return vmcs12->pin_based_vm_exec_control &
1092 PIN_BASED_VMX_PREEMPTION_TIMER;
1093}
1094
155a97a3
NHE		 1095static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1096{
1097 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1098}
1099
644d711a
NHE		 1100static inline bool is_exception(u32 intr_info)
1101{
1102 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1103 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1104}
1105
533558bc
JK		 1106static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1107 u32 exit_intr_info,
1108 unsigned long exit_qualification);
7c177938
NHE		 1109static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1110 struct vmcs12 *vmcs12,
1111 u32 reason, unsigned long qualification);
1112
8b9cf98c 1113static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1114{
1115 int i;
1116
a2fa3e9f 1117 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1118 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1119 return i;
1120 return -1;
1121}
1122
2384d2b3
SY		 1123static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1124{
1125 struct {
1126 u64 vpid : 16;
1127 u64 rsvd : 48;
1128 u64 gva;
1129 } operand = { vpid, 0, gva };
1130
4ecac3fd 1131 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1132 /* CF==1 or ZF==1 --> rc = -1 */
1133 "; ja 1f ; ud2 ; 1:"
1134 : : "a"(&operand), "c"(ext) : "cc", "memory");
1135}
1136
1439442c
SY		 1137static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1138{
1139 struct {
1140 u64 eptp, gpa;
1141 } operand = {eptp, gpa};
1142
4ecac3fd 1143 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1144 /* CF==1 or ZF==1 --> rc = -1 */
1145 "; ja 1f ; ud2 ; 1:\n"
1146 : : "a" (&operand), "c" (ext) : "cc", "memory");
1147}
1148
26bb0981 1149static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1150{
1151 int i;
1152
8b9cf98c 1153 i = __find_msr_index(vmx, msr);
a75beee6 1154 if (i >= 0)
a2fa3e9f 1155 return &vmx->guest_msrs[i];
8b6d44c7 1156 return NULL;
7725f0ba
AK		 1157}
1158
6aa8b732
AK		 1159static void vmcs_clear(struct vmcs *vmcs)
1160{
1161 u64 phys_addr = __pa(vmcs);
1162 u8 error;
1163
4ecac3fd 1164 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1165 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1166 : "cc", "memory");
1167 if (error)
1168 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1169 vmcs, phys_addr);
1170}
1171
d462b819
NHE		 1172static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1173{
1174 vmcs_clear(loaded_vmcs->vmcs);
1175 loaded_vmcs->cpu = -1;
1176 loaded_vmcs->launched = 0;
1177}
1178
7725b894
DX		 1179static void vmcs_load(struct vmcs *vmcs)
1180{
1181 u64 phys_addr = __pa(vmcs);
1182 u8 error;
1183
1184 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1185 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1186 : "cc", "memory");
1187 if (error)
2844d849 1188 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1189 vmcs, phys_addr);
1190}
1191
8f536b76
ZY		 1192#ifdef CONFIG_KEXEC
1193/*
1194 * This bitmap is used to indicate whether the vmclear
1195 * operation is enabled on all cpus. All disabled by
1196 * default.
1197 */
1198static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1199
1200static inline void crash_enable_local_vmclear(int cpu)
1201{
1202 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1203}
1204
1205static inline void crash_disable_local_vmclear(int cpu)
1206{
1207 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1208}
1209
1210static inline int crash_local_vmclear_enabled(int cpu)
1211{
1212 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1213}
1214
1215static void crash_vmclear_local_loaded_vmcss(void)
1216{
1217 int cpu = raw_smp_processor_id();
1218 struct loaded_vmcs *v;
1219
1220 if (!crash_local_vmclear_enabled(cpu))
1221 return;
1222
1223 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1224 loaded_vmcss_on_cpu_link)
1225 vmcs_clear(v->vmcs);
1226}
1227#else
1228static inline void crash_enable_local_vmclear(int cpu) { }
1229static inline void crash_disable_local_vmclear(int cpu) { }
1230#endif /* CONFIG_KEXEC */
1231
d462b819 1232static void __loaded_vmcs_clear(void *arg)
6aa8b732 1233{
d462b819 1234 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1235 int cpu = raw_smp_processor_id();
6aa8b732 1236
d462b819
NHE		 1237 if (loaded_vmcs->cpu != cpu)
1238 return; /* vcpu migration can race with cpu offline */
1239 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1240 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1241 crash_disable_local_vmclear(cpu);
d462b819 1242 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1243
1244 /*
1245 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1246 * is before setting loaded_vmcs->vcpu to -1 which is done in
1247 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1248 * then adds the vmcs into percpu list before it is deleted.
1249 */
1250 smp_wmb();
1251
d462b819 1252 loaded_vmcs_init(loaded_vmcs);
8f536b76 1253 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1254}
1255
d462b819 1256static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1257{
e6c7d321
XG		 1258 int cpu = loaded_vmcs->cpu;
1259
1260 if (cpu != -1)
1261 smp_call_function_single(cpu,
1262 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1263}
1264
1760dd49 1265static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1266{
1267 if (vmx->vpid == 0)
1268 return;
1269
518c8aee
GJ		 1270 if (cpu_has_vmx_invvpid_single())
1271 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1272}
1273
b9d762fa
GJ		 1274static inline void vpid_sync_vcpu_global(void)
1275{
1276 if (cpu_has_vmx_invvpid_global())
1277 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1278}
1279
1280static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1281{
1282 if (cpu_has_vmx_invvpid_single())
1760dd49 1283 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1284 else
1285 vpid_sync_vcpu_global();
1286}
1287
1439442c
SY		 1288static inline void ept_sync_global(void)
1289{
1290 if (cpu_has_vmx_invept_global())
1291 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1292}
1293
1294static inline void ept_sync_context(u64 eptp)
1295{
089d034e 1296 if (enable_ept) {
1439442c
SY		 1297 if (cpu_has_vmx_invept_context())
1298 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1299 else
1300 ept_sync_global();
1301 }
1302}
1303
96304217 1304static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1305{
5e520e62 1306 unsigned long value;
6aa8b732 1307
5e520e62
AK		 1308 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1309 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1310 return value;
1311}
1312
96304217 1313static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1314{
1315 return vmcs_readl(field);
1316}
1317
96304217 1318static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1319{
1320 return vmcs_readl(field);
1321}
1322
96304217 1323static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1324{
05b3e0c2 1325#ifdef CONFIG_X86_64
6aa8b732
AK		 1326 return vmcs_readl(field);
1327#else
1328 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1329#endif
1330}
1331
e52de1b8
AK		 1332static noinline void vmwrite_error(unsigned long field, unsigned long value)
1333{
1334 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1335 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1336 dump_stack();
1337}
1338
6aa8b732
AK		 1339static void vmcs_writel(unsigned long field, unsigned long value)
1340{
1341 u8 error;
1342
4ecac3fd 1343 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1344 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1345 if (unlikely(error))
1346 vmwrite_error(field, value);
6aa8b732
AK		 1347}
1348
1349static void vmcs_write16(unsigned long field, u16 value)
1350{
1351 vmcs_writel(field, value);
1352}
1353
1354static void vmcs_write32(unsigned long field, u32 value)
1355{
1356 vmcs_writel(field, value);
1357}
1358
1359static void vmcs_write64(unsigned long field, u64 value)
1360{
6aa8b732 1361 vmcs_writel(field, value);
7682f2d0 1362#ifndef CONFIG_X86_64
6aa8b732
AK		 1363 asm volatile ("");
1364 vmcs_writel(field+1, value >> 32);
1365#endif
1366}
1367
2ab455cc
AL		 1368static void vmcs_clear_bits(unsigned long field, u32 mask)
1369{
1370 vmcs_writel(field, vmcs_readl(field) & ~mask);
1371}
1372
1373static void vmcs_set_bits(unsigned long field, u32 mask)
1374{
1375 vmcs_writel(field, vmcs_readl(field) | mask);
1376}
1377
2961e876
GN		 1378static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1379{
1380 vmcs_write32(VM_ENTRY_CONTROLS, val);
1381 vmx->vm_entry_controls_shadow = val;
1382}
1383
1384static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1385{
1386 if (vmx->vm_entry_controls_shadow != val)
1387 vm_entry_controls_init(vmx, val);
1388}
1389
1390static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1391{
1392 return vmx->vm_entry_controls_shadow;
1393}
1394
1395
1396static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1397{
1398 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1399}
1400
1401static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1402{
1403 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1404}
1405
1406static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1407{
1408 vmcs_write32(VM_EXIT_CONTROLS, val);
1409 vmx->vm_exit_controls_shadow = val;
1410}
1411
1412static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1413{
1414 if (vmx->vm_exit_controls_shadow != val)
1415 vm_exit_controls_init(vmx, val);
1416}
1417
1418static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1419{
1420 return vmx->vm_exit_controls_shadow;
1421}
1422
1423
1424static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1425{
1426 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1427}
1428
1429static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1430{
1431 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1432}
1433
2fb92db1
AK		 1434static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1435{
1436 vmx->segment_cache.bitmask = 0;
1437}
1438
1439static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1440 unsigned field)
1441{
1442 bool ret;
1443 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1444
1445 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1446 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1447 vmx->segment_cache.bitmask = 0;
1448 }
1449 ret = vmx->segment_cache.bitmask & mask;
1450 vmx->segment_cache.bitmask |= mask;
1451 return ret;
1452}
1453
1454static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1455{
1456 u16 *p = &vmx->segment_cache.seg[seg].selector;
1457
1458 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1459 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1460 return *p;
1461}
1462
1463static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1464{
1465 ulong *p = &vmx->segment_cache.seg[seg].base;
1466
1467 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1468 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1469 return *p;
1470}
1471
1472static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1473{
1474 u32 *p = &vmx->segment_cache.seg[seg].limit;
1475
1476 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1477 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1478 return *p;
1479}
1480
1481static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1482{
1483 u32 *p = &vmx->segment_cache.seg[seg].ar;
1484
1485 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1486 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1487 return *p;
1488}
1489
abd3f2d6
AK		 1490static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1491{
1492 u32 eb;
1493
fd7373cc
JK		 1494 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1495 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1496 if ((vcpu->guest_debug &
1497 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1498 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1499 eb |= 1u << BP_VECTOR;
7ffd92c5 1500 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1501 eb = ~0;
089d034e 1502 if (enable_ept)
1439442c 1503 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1504 if (vcpu->fpu_active)
1505 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1506
1507 /* When we are running a nested L2 guest and L1 specified for it a
1508 * certain exception bitmap, we must trap the same exceptions and pass
1509 * them to L1. When running L2, we will only handle the exceptions
1510 * specified above if L1 did not want them.
1511 */
1512 if (is_guest_mode(vcpu))
1513 eb |= get_vmcs12(vcpu)->exception_bitmap;
1514
abd3f2d6
AK		 1515 vmcs_write32(EXCEPTION_BITMAP, eb);
1516}
1517
2961e876
GN		 1518static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1519 unsigned long entry, unsigned long exit)
8bf00a52 1520{
2961e876
GN		 1521 vm_entry_controls_clearbit(vmx, entry);
1522 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1523}
1524
61d2ef2c
AK		 1525static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1526{
1527 unsigned i;
1528 struct msr_autoload *m = &vmx->msr_autoload;
1529
8bf00a52
GN		 1530 switch (msr) {
1531 case MSR_EFER:
1532 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1533 clear_atomic_switch_msr_special(vmx,
1534 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1535 VM_EXIT_LOAD_IA32_EFER);
1536 return;
1537 }
1538 break;
1539 case MSR_CORE_PERF_GLOBAL_CTRL:
1540 if (cpu_has_load_perf_global_ctrl) {
2961e876 1541 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1542 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1543 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1544 return;
1545 }
1546 break;
110312c8
AK		 1547 }
1548
61d2ef2c
AK		 1549 for (i = 0; i < m->nr; ++i)
1550 if (m->guest[i].index == msr)
1551 break;
1552
1553 if (i == m->nr)
1554 return;
1555 --m->nr;
1556 m->guest[i] = m->guest[m->nr];
1557 m->host[i] = m->host[m->nr];
1558 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1559 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1560}
1561
2961e876
GN		 1562static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1563 unsigned long entry, unsigned long exit,
1564 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1565 u64 guest_val, u64 host_val)
8bf00a52
GN		 1566{
1567 vmcs_write64(guest_val_vmcs, guest_val);
1568 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1569 vm_entry_controls_setbit(vmx, entry);
1570 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1571}
1572
61d2ef2c
AK		 1573static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1574 u64 guest_val, u64 host_val)
1575{
1576 unsigned i;
1577 struct msr_autoload *m = &vmx->msr_autoload;
1578
8bf00a52
GN		 1579 switch (msr) {
1580 case MSR_EFER:
1581 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1582 add_atomic_switch_msr_special(vmx,
1583 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1584 VM_EXIT_LOAD_IA32_EFER,
1585 GUEST_IA32_EFER,
1586 HOST_IA32_EFER,
1587 guest_val, host_val);
1588 return;
1589 }
1590 break;
1591 case MSR_CORE_PERF_GLOBAL_CTRL:
1592 if (cpu_has_load_perf_global_ctrl) {
2961e876 1593 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1594 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1595 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1596 GUEST_IA32_PERF_GLOBAL_CTRL,
1597 HOST_IA32_PERF_GLOBAL_CTRL,
1598 guest_val, host_val);
1599 return;
1600 }
1601 break;
110312c8
AK		 1602 }
1603
61d2ef2c
AK		 1604 for (i = 0; i < m->nr; ++i)
1605 if (m->guest[i].index == msr)
1606 break;
1607
e7fc6f93 1608 if (i == NR_AUTOLOAD_MSRS) {
60266204 1609 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1610 "Can't add msr %x\n", msr);
1611 return;
1612 } else if (i == m->nr) {
61d2ef2c
AK		 1613 ++m->nr;
1614 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1615 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1616 }
1617
1618 m->guest[i].index = msr;
1619 m->guest[i].value = guest_val;
1620 m->host[i].index = msr;
1621 m->host[i].value = host_val;
1622}
1623
33ed6329
AK		 1624static void reload_tss(void)
1625{
33ed6329
AK		 1626 /*
1627 * VT restores TR but not its size. Useless.
1628 */
d359192f 1629 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1630 struct desc_struct *descs;
33ed6329 1631
d359192f 1632 descs = (void *)gdt->address;
33ed6329
AK		 1633 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1634 load_TR_desc();
33ed6329
AK		 1635}
1636
92c0d900 1637static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1638{
3a34a881 1639 u64 guest_efer;
51c6cf66
AK		 1640 u64 ignore_bits;
1641
f6801dff 1642 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1643
51c6cf66 1644 /*
0fa06071 1645 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1646 * outside long mode
1647 */
1648 ignore_bits = EFER_NX | EFER_SCE;
1649#ifdef CONFIG_X86_64
1650 ignore_bits |= EFER_LMA | EFER_LME;
1651 /* SCE is meaningful only in long mode on Intel */
1652 if (guest_efer & EFER_LMA)
1653 ignore_bits &= ~(u64)EFER_SCE;
1654#endif
51c6cf66
AK		 1655 guest_efer &= ~ignore_bits;
1656 guest_efer |= host_efer & ignore_bits;
26bb0981 1657 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1658 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1659
1660 clear_atomic_switch_msr(vmx, MSR_EFER);
1661 /* On ept, can't emulate nx, and must switch nx atomically */
1662 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1663 guest_efer = vmx->vcpu.arch.efer;
1664 if (!(guest_efer & EFER_LMA))
1665 guest_efer &= ~EFER_LME;
1666 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1667 return false;
1668 }
1669
26bb0981 1670 return true;
51c6cf66
AK		 1671}
1672
2d49ec72
GN		 1673static unsigned long segment_base(u16 selector)
1674{
d359192f 1675 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1676 struct desc_struct *d;
1677 unsigned long table_base;
1678 unsigned long v;
1679
1680 if (!(selector & ~3))
1681 return 0;
1682
d359192f 1683 table_base = gdt->address;
2d49ec72
GN		 1684
1685 if (selector & 4) { /* from ldt */
1686 u16 ldt_selector = kvm_read_ldt();
1687
1688 if (!(ldt_selector & ~3))
1689 return 0;
1690
1691 table_base = segment_base(ldt_selector);
1692 }
1693 d = (struct desc_struct *)(table_base + (selector & ~7));
1694 v = get_desc_base(d);
1695#ifdef CONFIG_X86_64
1696 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1697 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1698#endif
1699 return v;
1700}
1701
1702static inline unsigned long kvm_read_tr_base(void)
1703{
1704 u16 tr;
1705 asm("str %0" : "=g"(tr));
1706 return segment_base(tr);
1707}
1708
04d2cc77 1709static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1710{
04d2cc77 1711 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1712 int i;
04d2cc77 1713
a2fa3e9f 1714 if (vmx->host_state.loaded)
33ed6329
AK		 1715 return;
1716
a2fa3e9f 1717 vmx->host_state.loaded = 1;
33ed6329
AK		 1718 /*
1719 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1720 * allow segment selectors with cpl > 0 or ti == 1.
1721 */
d6e88aec 1722 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1723 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1724 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1725 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1726 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1727 vmx->host_state.fs_reload_needed = 0;
1728 } else {
33ed6329 1729 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1730 vmx->host_state.fs_reload_needed = 1;
33ed6329 1731 }
9581d442 1732 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1733 if (!(vmx->host_state.gs_sel & 7))
1734 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1735 else {
1736 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1737 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1738 }
1739
b2da15ac
AK		 1740#ifdef CONFIG_X86_64
1741 savesegment(ds, vmx->host_state.ds_sel);
1742 savesegment(es, vmx->host_state.es_sel);
1743#endif
1744
33ed6329
AK		 1745#ifdef CONFIG_X86_64
1746 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1747 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1748#else
a2fa3e9f
GH		 1749 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1750 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1751#endif
707c0874
AK		 1752
1753#ifdef CONFIG_X86_64
c8770e7b
AK		 1754 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1755 if (is_long_mode(&vmx->vcpu))
44ea2b17 1756 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1757#endif
da8999d3
LJ		 1758 if (boot_cpu_has(X86_FEATURE_MPX))
1759 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1760 for (i = 0; i < vmx->save_nmsrs; ++i)
1761 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1762 vmx->guest_msrs[i].data,
1763 vmx->guest_msrs[i].mask);
33ed6329
AK		 1764}
1765
a9b21b62 1766static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1767{
a2fa3e9f 1768 if (!vmx->host_state.loaded)
33ed6329
AK		 1769 return;
1770
e1beb1d3 1771 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1772 vmx->host_state.loaded = 0;
c8770e7b
AK		 1773#ifdef CONFIG_X86_64
1774 if (is_long_mode(&vmx->vcpu))
1775 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1776#endif
152d3f2f 1777 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1778 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1779#ifdef CONFIG_X86_64
9581d442 1780 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1781#else
1782 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1783#endif
33ed6329 1784 }
0a77fe4c
AK		 1785 if (vmx->host_state.fs_reload_needed)
1786 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1787#ifdef CONFIG_X86_64
1788 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1789 loadsegment(ds, vmx->host_state.ds_sel);
1790 loadsegment(es, vmx->host_state.es_sel);
1791 }
b2da15ac 1792#endif
152d3f2f 1793 reload_tss();
44ea2b17 1794#ifdef CONFIG_X86_64
c8770e7b 1795 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1796#endif
da8999d3
LJ		 1797 if (vmx->host_state.msr_host_bndcfgs)
1798 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1799 /*
1800 * If the FPU is not active (through the host task or
1801 * the guest vcpu), then restore the cr0.TS bit.
1802 */
1803 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1804 stts();
3444d7da 1805 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1806}
1807
a9b21b62
AK		 1808static void vmx_load_host_state(struct vcpu_vmx *vmx)
1809{
1810 preempt_disable();
1811 __vmx_load_host_state(vmx);
1812 preempt_enable();
1813}
1814
6aa8b732
AK		 1815/*
1816 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1817 * vcpu mutex is already taken.
1818 */
15ad7146 1819static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1820{
a2fa3e9f 1821 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1822 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1823
4610c9cc
DX		 1824 if (!vmm_exclusive)
1825 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1826 else if (vmx->loaded_vmcs->cpu != cpu)
1827 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1828
d462b819
NHE		 1829 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1830 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1831 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1832 }
1833
d462b819 1834 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1835 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1836 unsigned long sysenter_esp;
1837
a8eeb04a 1838 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1839 local_irq_disable();
8f536b76 1840 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1841
1842 /*
1843 * Read loaded_vmcs->cpu should be before fetching
1844 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1845 * See the comments in __loaded_vmcs_clear().
1846 */
1847 smp_rmb();
1848
d462b819
NHE		 1849 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1850 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1851 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1852 local_irq_enable();
1853
6aa8b732
AK		 1854 /*
1855 * Linux uses per-cpu TSS and GDT, so set these when switching
1856 * processors.
1857 */
d6e88aec 1858 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1859 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1860
1861 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1862 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1863 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1864 }
6aa8b732
AK		 1865}
1866
1867static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1868{
a9b21b62 1869 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1870 if (!vmm_exclusive) {
d462b819
NHE		 1871 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1872 vcpu->cpu = -1;
4610c9cc
DX		 1873 kvm_cpu_vmxoff();
1874 }
6aa8b732
AK		 1875}
1876
5fd86fcf
AK		 1877static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1878{
81231c69
AK		 1879 ulong cr0;
1880
5fd86fcf
AK		 1881 if (vcpu->fpu_active)
1882 return;
1883 vcpu->fpu_active = 1;
81231c69
AK		 1884 cr0 = vmcs_readl(GUEST_CR0);
1885 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1886 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1887 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1888 update_exception_bitmap(vcpu);
edcafe3c 1889 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1890 if (is_guest_mode(vcpu))
1891 vcpu->arch.cr0_guest_owned_bits &=
1892 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1893 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1894}
1895
edcafe3c
AK		 1896static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1897
fe3ef05c
NHE		 1898/*
1899 * Return the cr0 value that a nested guest would read. This is a combination
1900 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1901 * its hypervisor (cr0_read_shadow).
1902 */
1903static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1904{
1905 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1906 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1907}
1908static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1909{
1910 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1911 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1912}
1913
5fd86fcf
AK		 1914static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1915{
36cf24e0
NHE		 1916 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1917 * set this *before* calling this function.
1918 */
edcafe3c 1919 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1920 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1921 update_exception_bitmap(vcpu);
edcafe3c
AK		 1922 vcpu->arch.cr0_guest_owned_bits = 0;
1923 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1924 if (is_guest_mode(vcpu)) {
1925 /*
1926 * L1's specified read shadow might not contain the TS bit,
1927 * so now that we turned on shadowing of this bit, we need to
1928 * set this bit of the shadow. Like in nested_vmx_run we need
1929 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1930 * up-to-date here because we just decached cr0.TS (and we'll
1931 * only update vmcs12->guest_cr0 on nested exit).
1932 */
1933 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1934 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1935 (vcpu->arch.cr0 & X86_CR0_TS);
1936 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1937 } else
1938 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1939}
1940
6aa8b732
AK		 1941static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1942{
78ac8b47 1943 unsigned long rflags, save_rflags;
345dcaa8 1944
6de12732
AK		 1945 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1946 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1947 rflags = vmcs_readl(GUEST_RFLAGS);
1948 if (to_vmx(vcpu)->rmode.vm86_active) {
1949 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1950 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1951 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1952 }
1953 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1954 }
6de12732 1955 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1956}
1957
1958static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1959{
6de12732
AK		 1960 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1961 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1962 if (to_vmx(vcpu)->rmode.vm86_active) {
1963 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1964 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1965 }
6aa8b732
AK		 1966 vmcs_writel(GUEST_RFLAGS, rflags);
1967}
1968
37ccdcbe 1969static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1970{
1971 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1972 int ret = 0;
1973
1974 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1975 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1976 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1977 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1978
37ccdcbe 1979 return ret;
2809f5d2
GC		 1980}
1981
1982static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1983{
1984 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1985 u32 interruptibility = interruptibility_old;
1986
1987 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1988
48005f64 1989 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1990 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1991 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1992 interruptibility |= GUEST_INTR_STATE_STI;
1993
1994 if ((interruptibility != interruptibility_old))
1995 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1996}
1997
6aa8b732
AK		 1998static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1999{
2000 unsigned long rip;
6aa8b732 2001
5fdbf976 2002 rip = kvm_rip_read(vcpu);
6aa8b732 2003 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2004 kvm_rip_write(vcpu, rip);
6aa8b732 2005
2809f5d2
GC		 2006 /* skipping an emulated instruction also counts */
2007 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2008}
2009
0b6ac343
NHE		 2010/*
2011 * KVM wants to inject page-faults which it got to the guest. This function
2012 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2013 */
e011c663 2014static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2015{
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017
e011c663 2018 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2019 return 0;
2020
533558bc
JK		 2021 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2022 vmcs_read32(VM_EXIT_INTR_INFO),
2023 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2024 return 1;
2025}
2026
298101da 2027static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2028 bool has_error_code, u32 error_code,
2029 bool reinject)
298101da 2030{
77ab6db0 2031 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2032 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2033
e011c663
GN		 2034 if (!reinject && is_guest_mode(vcpu) &&
2035 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2036 return;
2037
8ab2d2e2 2038 if (has_error_code) {
77ab6db0 2039 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2040 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2041 }
77ab6db0 2042
7ffd92c5 2043 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2044 int inc_eip = 0;
2045 if (kvm_exception_is_soft(nr))
2046 inc_eip = vcpu->arch.event_exit_inst_len;
2047 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2048 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2049 return;
2050 }
2051
66fd3f7f
GN		 2052 if (kvm_exception_is_soft(nr)) {
2053 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2054 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2055 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2056 } else
2057 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2058
2059 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2060}
2061
4e47c7a6
SY		 2062static bool vmx_rdtscp_supported(void)
2063{
2064 return cpu_has_vmx_rdtscp();
2065}
2066
ad756a16
MJ		 2067static bool vmx_invpcid_supported(void)
2068{
2069 return cpu_has_vmx_invpcid() && enable_ept;
2070}
2071
a75beee6
ED		 2072/*
2073 * Swap MSR entry in host/guest MSR entry array.
2074 */
8b9cf98c 2075static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2076{
26bb0981 2077 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2078
2079 tmp = vmx->guest_msrs[to];
2080 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2081 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2082}
2083
8d14695f
YZ		 2084static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2085{
2086 unsigned long *msr_bitmap;
2087
2088 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2089 if (is_long_mode(vcpu))
2090 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2091 else
2092 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2093 } else {
2094 if (is_long_mode(vcpu))
2095 msr_bitmap = vmx_msr_bitmap_longmode;
2096 else
2097 msr_bitmap = vmx_msr_bitmap_legacy;
2098 }
2099
2100 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2101}
2102
e38aea3e
AK		 2103/*
2104 * Set up the vmcs to automatically save and restore system
2105 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2106 * mode, as fiddling with msrs is very expensive.
2107 */
8b9cf98c 2108static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2109{
26bb0981 2110 int save_nmsrs, index;
e38aea3e 2111
a75beee6
ED		 2112 save_nmsrs = 0;
2113#ifdef CONFIG_X86_64
8b9cf98c 2114 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2115 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2116 if (index >= 0)
8b9cf98c
RR		 2117 move_msr_up(vmx, index, save_nmsrs++);
2118 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2119 if (index >= 0)
8b9cf98c
RR		 2120 move_msr_up(vmx, index, save_nmsrs++);
2121 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2122 if (index >= 0)
8b9cf98c 2123 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2124 index = __find_msr_index(vmx, MSR_TSC_AUX);
2125 if (index >= 0 && vmx->rdtscp_enabled)
2126 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2127 /*
8c06585d 2128 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2129 * if efer.sce is enabled.
2130 */
8c06585d 2131 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2132 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2133 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2134 }
2135#endif
92c0d900
AK		 2136 index = __find_msr_index(vmx, MSR_EFER);
2137 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2138 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2139
26bb0981 2140 vmx->save_nmsrs = save_nmsrs;
5897297b 2141
8d14695f
YZ		 2142 if (cpu_has_vmx_msr_bitmap())
2143 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2144}
2145
6aa8b732
AK		 2146/*
2147 * reads and returns guest's timestamp counter "register"
2148 * guest_tsc = host_tsc + tsc_offset -- 21.3
2149 */
2150static u64 guest_read_tsc(void)
2151{
2152 u64 host_tsc, tsc_offset;
2153
2154 rdtscll(host_tsc);
2155 tsc_offset = vmcs_read64(TSC_OFFSET);
2156 return host_tsc + tsc_offset;
2157}
2158
d5c1785d
NHE		 2159/*
2160 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2161 * counter, even if a nested guest (L2) is currently running.
2162 */
48d89b92 2163static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2164{
886b470c 2165 u64 tsc_offset;
d5c1785d 2166
d5c1785d
NHE		 2167 tsc_offset = is_guest_mode(vcpu) ?
2168 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2169 vmcs_read64(TSC_OFFSET);
2170 return host_tsc + tsc_offset;
2171}
2172
4051b188 2173/*
cc578287
ZA		 2174 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2175 * software catchup for faster rates on slower CPUs.
4051b188 2176 */
cc578287 2177static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2178{
cc578287
ZA		 2179 if (!scale)
2180 return;
2181
2182 if (user_tsc_khz > tsc_khz) {
2183 vcpu->arch.tsc_catchup = 1;
2184 vcpu->arch.tsc_always_catchup = 1;
2185 } else
2186 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2187}
2188
ba904635
WA		 2189static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2190{
2191 return vmcs_read64(TSC_OFFSET);
2192}
2193
6aa8b732 2194/*
99e3e30a 2195 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2196 */
99e3e30a 2197static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2198{
27fc51b2 2199 if (is_guest_mode(vcpu)) {
7991825b 2200 /*
27fc51b2
NHE		 2201 * We're here if L1 chose not to trap WRMSR to TSC. According
2202 * to the spec, this should set L1's TSC; The offset that L1
2203 * set for L2 remains unchanged, and still needs to be added
2204 * to the newly set TSC to get L2's TSC.
7991825b 2205 */
27fc51b2
NHE		 2206 struct vmcs12 *vmcs12;
2207 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2208 /* recalculate vmcs02.TSC_OFFSET: */
2209 vmcs12 = get_vmcs12(vcpu);
2210 vmcs_write64(TSC_OFFSET, offset +
2211 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2212 vmcs12->tsc_offset : 0));
2213 } else {
489223ed
YY		 2214 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2215 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2216 vmcs_write64(TSC_OFFSET, offset);
2217 }
6aa8b732
AK		 2218}
2219
f1e2b260 2220static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2221{
2222 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2223
e48672fa 2224 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2225 if (is_guest_mode(vcpu)) {
2226 /* Even when running L2, the adjustment needs to apply to L1 */
2227 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2228 } else
2229 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2230 offset + adjustment);
e48672fa
ZA		 2231}
2232
857e4099
JR		 2233static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2234{
2235 return target_tsc - native_read_tsc();
2236}
2237
801d3424
NHE		 2238static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2239{
2240 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2241 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2242}
2243
2244/*
2245 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2246 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2247 * all guests if the "nested" module option is off, and can also be disabled
2248 * for a single guest by disabling its VMX cpuid bit.
2249 */
2250static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2251{
2252 return nested && guest_cpuid_has_vmx(vcpu);
2253}
2254
b87a51ae
NHE		 2255/*
2256 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2257 * returned for the various VMX controls MSRs when nested VMX is enabled.
2258 * The same values should also be used to verify that vmcs12 control fields are
2259 * valid during nested entry from L1 to L2.
2260 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2261 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2262 * bit in the high half is on if the corresponding bit in the control field
2263 * may be on. See also vmx_control_verify().
2264 * TODO: allow these variables to be modified (downgraded) by module options
2265 * or other means.
2266 */
2267static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2268static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2269static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2270static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2271static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2272static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2273static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2274static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2275static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2276static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2277static __init void nested_vmx_setup_ctls_msrs(void)
2278{
2279 /*
2280 * Note that as a general rule, the high half of the MSRs (bits in
2281 * the control fields which may be 1) should be initialized by the
2282 * intersection of the underlying hardware's MSR (i.e., features which
2283 * can be supported) and the list of features we want to expose -
2284 * because they are known to be properly supported in our code.
2285 * Also, usually, the low half of the MSRs (bits which must be 1) can
2286 * be set to 0, meaning that L1 may turn off any of these bits. The
2287 * reason is that if one of these bits is necessary, it will appear
2288 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2289 * fields of vmcs01 and vmcs02, will turn these bits off - and
2290 * nested_vmx_exit_handled() will not pass related exits to L1.
2291 * These rules have exceptions below.
2292 */
2293
2294 /* pin-based controls */
eabeaacc
JK		 2295 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2296 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2297 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2298 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2299 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2300 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2301 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2302
3dbcd8da 2303 /* exit controls */
c0dfee58
ACL		 2304 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2305 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2306 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2307
c0dfee58 2308 nested_vmx_exit_ctls_high &=
b87a51ae 2309#ifdef CONFIG_X86_64
c0dfee58 2310 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2311#endif
f4124500
JK		 2312 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2313 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2314 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2315 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2316
36be0b9d
PB		 2317 if (vmx_mpx_supported())
2318 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2319
2996fca0
JK		 2320 /* We support free control of debug control saving. */
2321 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2322 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2323
b87a51ae
NHE		 2324 /* entry controls */
2325 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2326 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2327 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2328 nested_vmx_entry_ctls_high &=
57435349
JK		 2329#ifdef CONFIG_X86_64
2330 VM_ENTRY_IA32E_MODE |
2331#endif
2332 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2333 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2334 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2335 if (vmx_mpx_supported())
2336 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2337
2996fca0
JK		 2338 /* We support free control of debug control loading. */
2339 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2340 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2341
b87a51ae
NHE		 2342 /* cpu-based controls */
2343 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2344 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2345 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2346 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2347 CPU_BASED_VIRTUAL_INTR_PENDING |
2348 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2349 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2350 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2351 CPU_BASED_CR3_STORE_EXITING |
2352#ifdef CONFIG_X86_64
2353 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2354#endif
2355 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2356 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2357 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2358 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2359 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2360 /*
2361 * We can allow some features even when not supported by the
2362 * hardware. For example, L1 can specify an MSR bitmap - and we
2363 * can use it to avoid exits to L1 - even when L0 runs L2
2364 * without MSR bitmaps.
2365 */
560b7ee1
JK		 2366 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2367 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2368
3dcdf3ec
JK		 2369 /* We support free control of CR3 access interception. */
2370 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2371 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2372
b87a51ae
NHE		 2373 /* secondary cpu-based controls */
2374 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2375 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2376 nested_vmx_secondary_ctls_low = 0;
2377 nested_vmx_secondary_ctls_high &=
d6851fbe 2378 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2379 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2380 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2381
afa61f75
NHE		 2382 if (enable_ept) {
2383 /* nested EPT: emulate EPT also to L1 */
2384 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2385 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2386 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2387 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2388 nested_vmx_ept_caps &= vmx_capability.ept;
2389 /*
4b855078
BD		 2390 * For nested guests, we don't do anything specific
2391 * for single context invalidation. Hence, only advertise
2392 * support for global context invalidation.
afa61f75 2393 */
4b855078 2394 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2395 } else
2396 nested_vmx_ept_caps = 0;
2397
c18911a2
JK		 2398 /* miscellaneous data */
2399 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2400 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2401 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2402 VMX_MISC_ACTIVITY_HLT;
c18911a2 2403 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2404}
2405
2406static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2407{
2408 /*
2409 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2410 */
2411 return ((control & high) | low) == control;
2412}
2413
2414static inline u64 vmx_control_msr(u32 low, u32 high)
2415{
2416 return low | ((u64)high << 32);
2417}
2418
cae50139 2419/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2420static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2421{
b87a51ae 2422 switch (msr_index) {
b87a51ae
NHE		 2423 case MSR_IA32_VMX_BASIC:
2424 /*
2425 * This MSR reports some information about VMX support. We
2426 * should return information about the VMX we emulate for the
2427 * guest, and the VMCS structure we give it - not about the
2428 * VMX support of the underlying hardware.
2429 */
3dbcd8da 2430 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2431 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2432 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2433 break;
2434 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2435 case MSR_IA32_VMX_PINBASED_CTLS:
2436 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2437 nested_vmx_pinbased_ctls_high);
2438 break;
2439 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2440 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2441 nested_vmx_procbased_ctls_high);
2442 break;
b87a51ae
NHE		 2443 case MSR_IA32_VMX_PROCBASED_CTLS:
2444 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2445 nested_vmx_procbased_ctls_high);
2446 break;
2447 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2448 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2449 nested_vmx_exit_ctls_high);
2450 break;
b87a51ae
NHE		 2451 case MSR_IA32_VMX_EXIT_CTLS:
2452 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2453 nested_vmx_exit_ctls_high);
2454 break;
2455 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2456 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2457 nested_vmx_entry_ctls_high);
2458 break;
b87a51ae
NHE		 2459 case MSR_IA32_VMX_ENTRY_CTLS:
2460 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2461 nested_vmx_entry_ctls_high);
2462 break;
2463 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2464 *pdata = vmx_control_msr(nested_vmx_misc_low,
2465 nested_vmx_misc_high);
b87a51ae
NHE		 2466 break;
2467 /*
2468 * These MSRs specify bits which the guest must keep fixed (on or off)
2469 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2470 * We picked the standard core2 setting.
2471 */
2472#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2473#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2474 case MSR_IA32_VMX_CR0_FIXED0:
2475 *pdata = VMXON_CR0_ALWAYSON;
2476 break;
2477 case MSR_IA32_VMX_CR0_FIXED1:
2478 *pdata = -1ULL;
2479 break;
2480 case MSR_IA32_VMX_CR4_FIXED0:
2481 *pdata = VMXON_CR4_ALWAYSON;
2482 break;
2483 case MSR_IA32_VMX_CR4_FIXED1:
2484 *pdata = -1ULL;
2485 break;
2486 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2487 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2488 break;
2489 case MSR_IA32_VMX_PROCBASED_CTLS2:
2490 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2491 nested_vmx_secondary_ctls_high);
2492 break;
2493 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2494 /* Currently, no nested vpid support */
2495 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2496 break;
2497 default:
b87a51ae 2498 return 1;
b3897a49
NHE		 2499 }
2500
b87a51ae
NHE		 2501 return 0;
2502}
2503
6aa8b732
AK		 2504/*
2505 * Reads an msr value (of 'msr_index') into 'pdata'.
2506 * Returns 0 on success, non-0 otherwise.
2507 * Assumes vcpu_load() was already called.
2508 */
2509static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2510{
2511 u64 data;
26bb0981 2512 struct shared_msr_entry *msr;
6aa8b732
AK		 2513
2514 if (!pdata) {
2515 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2516 return -EINVAL;
2517 }
2518
2519 switch (msr_index) {
05b3e0c2 2520#ifdef CONFIG_X86_64
6aa8b732
AK		 2521 case MSR_FS_BASE:
2522 data = vmcs_readl(GUEST_FS_BASE);
2523 break;
2524 case MSR_GS_BASE:
2525 data = vmcs_readl(GUEST_GS_BASE);
2526 break;
44ea2b17
AK		 2527 case MSR_KERNEL_GS_BASE:
2528 vmx_load_host_state(to_vmx(vcpu));
2529 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2530 break;
26bb0981 2531#endif
6aa8b732 2532 case MSR_EFER:
3bab1f5d 2533 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2534 case MSR_IA32_TSC:
6aa8b732
AK		 2535 data = guest_read_tsc();
2536 break;
2537 case MSR_IA32_SYSENTER_CS:
2538 data = vmcs_read32(GUEST_SYSENTER_CS);
2539 break;
2540 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2541 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2542 break;
2543 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2544 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2545 break;
0dd376e7 2546 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2547 if (!vmx_mpx_supported())
2548 return 1;
0dd376e7
LJ		 2549 data = vmcs_read64(GUEST_BNDCFGS);
2550 break;
cae50139
JK		 2551 case MSR_IA32_FEATURE_CONTROL:
2552 if (!nested_vmx_allowed(vcpu))
2553 return 1;
2554 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2555 break;
2556 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2557 if (!nested_vmx_allowed(vcpu))
2558 return 1;
2559 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2560 case MSR_TSC_AUX:
2561 if (!to_vmx(vcpu)->rdtscp_enabled)
2562 return 1;
2563 /* Otherwise falls through */
6aa8b732 2564 default:
8b9cf98c 2565 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2566 if (msr) {
2567 data = msr->data;
2568 break;
6aa8b732 2569 }
3bab1f5d 2570 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2571 }
2572
2573 *pdata = data;
2574 return 0;
2575}
2576
cae50139
JK		 2577static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2578
6aa8b732
AK		 2579/*
2580 * Writes msr value into into the appropriate "register".
2581 * Returns 0 on success, non-0 otherwise.
2582 * Assumes vcpu_load() was already called.
2583 */
8fe8ab46 2584static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2585{
a2fa3e9f 2586 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2587 struct shared_msr_entry *msr;
2cc51560 2588 int ret = 0;
8fe8ab46
WA		 2589 u32 msr_index = msr_info->index;
2590 u64 data = msr_info->data;
2cc51560 2591
6aa8b732 2592 switch (msr_index) {
3bab1f5d 2593 case MSR_EFER:
8fe8ab46 2594 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2595 break;
16175a79 2596#ifdef CONFIG_X86_64
6aa8b732 2597 case MSR_FS_BASE:
2fb92db1 2598 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2599 vmcs_writel(GUEST_FS_BASE, data);
2600 break;
2601 case MSR_GS_BASE:
2fb92db1 2602 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2603 vmcs_writel(GUEST_GS_BASE, data);
2604 break;
44ea2b17
AK		 2605 case MSR_KERNEL_GS_BASE:
2606 vmx_load_host_state(vmx);
2607 vmx->msr_guest_kernel_gs_base = data;
2608 break;
6aa8b732
AK		 2609#endif
2610 case MSR_IA32_SYSENTER_CS:
2611 vmcs_write32(GUEST_SYSENTER_CS, data);
2612 break;
2613 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2614 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2615 break;
2616 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2617 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2618 break;
0dd376e7 2619 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2620 if (!vmx_mpx_supported())
2621 return 1;
0dd376e7
LJ		 2622 vmcs_write64(GUEST_BNDCFGS, data);
2623 break;
af24a4e4 2624 case MSR_IA32_TSC:
8fe8ab46 2625 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2626 break;
468d472f
SY		 2627 case MSR_IA32_CR_PAT:
2628 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2629 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2630 return 1;
468d472f
SY		 2631 vmcs_write64(GUEST_IA32_PAT, data);
2632 vcpu->arch.pat = data;
2633 break;
2634 }
8fe8ab46 2635 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2636 break;
ba904635
WA		 2637 case MSR_IA32_TSC_ADJUST:
2638 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2639 break;
cae50139
JK		 2640 case MSR_IA32_FEATURE_CONTROL:
2641 if (!nested_vmx_allowed(vcpu) ||
2642 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2643 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2644 return 1;
2645 vmx->nested.msr_ia32_feature_control = data;
2646 if (msr_info->host_initiated && data == 0)
2647 vmx_leave_nested(vcpu);
2648 break;
2649 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2650 return 1; /* they are read-only */
4e47c7a6
SY		 2651 case MSR_TSC_AUX:
2652 if (!vmx->rdtscp_enabled)
2653 return 1;
2654 /* Check reserved bit, higher 32 bits should be zero */
2655 if ((data >> 32) != 0)
2656 return 1;
2657 /* Otherwise falls through */
6aa8b732 2658 default:
8b9cf98c 2659 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2660 if (msr) {
2661 msr->data = data;
2225fd56
AK		 2662 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2663 preempt_disable();
9ee73970
AK		 2664 kvm_set_shared_msr(msr->index, msr->data,
2665 msr->mask);
2225fd56
AK		 2666 preempt_enable();
2667 }
3bab1f5d 2668 break;
6aa8b732 2669 }
8fe8ab46 2670 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2671 }
2672
2cc51560 2673 return ret;
6aa8b732
AK		 2674}
2675
5fdbf976 2676static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2677{
5fdbf976
MT		 2678 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2679 switch (reg) {
2680 case VCPU_REGS_RSP:
2681 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2682 break;
2683 case VCPU_REGS_RIP:
2684 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2685 break;
6de4f3ad
AK		 2686 case VCPU_EXREG_PDPTR:
2687 if (enable_ept)
2688 ept_save_pdptrs(vcpu);
2689 break;
5fdbf976
MT		 2690 default:
2691 break;
2692 }
6aa8b732
AK		 2693}
2694
6aa8b732
AK		 2695static __init int cpu_has_kvm_support(void)
2696{
6210e37b 2697 return cpu_has_vmx();
6aa8b732
AK		 2698}
2699
2700static __init int vmx_disabled_by_bios(void)
2701{
2702 u64 msr;
2703
2704 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2705 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2706 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2707 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2708 && tboot_enabled())
2709 return 1;
23f3e991 2710 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2711 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2712 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2713 && !tboot_enabled()) {
2714 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2715 "activate TXT before enabling KVM\n");
cafd6659 2716 return 1;
f9335afe 2717 }
23f3e991
JC		 2718 /* launched w/o TXT and VMX disabled */
2719 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2720 && !tboot_enabled())
2721 return 1;
cafd6659
SW		 2722 }
2723
2724 return 0;
6aa8b732
AK		 2725}
2726
7725b894
DX		 2727static void kvm_cpu_vmxon(u64 addr)
2728{
2729 asm volatile (ASM_VMX_VMXON_RAX
2730 : : "a"(&addr), "m"(addr)
2731 : "memory", "cc");
2732}
2733
13a34e06 2734static int hardware_enable(void)
6aa8b732
AK		 2735{
2736 int cpu = raw_smp_processor_id();
2737 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2738 u64 old, test_bits;
6aa8b732 2739
10474ae8
AG		 2740 if (read_cr4() & X86_CR4_VMXE)
2741 return -EBUSY;
2742
d462b819 2743 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2744
2745 /*
2746 * Now we can enable the vmclear operation in kdump
2747 * since the loaded_vmcss_on_cpu list on this cpu
2748 * has been initialized.
2749 *
2750 * Though the cpu is not in VMX operation now, there
2751 * is no problem to enable the vmclear operation
2752 * for the loaded_vmcss_on_cpu list is empty!
2753 */
2754 crash_enable_local_vmclear(cpu);
2755
6aa8b732 2756 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2757
2758 test_bits = FEATURE_CONTROL_LOCKED;
2759 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2760 if (tboot_enabled())
2761 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2762
2763 if ((old & test_bits) != test_bits) {
6aa8b732 2764 /* enable and lock */
cafd6659
SW		 2765 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2766 }
66aee91a 2767 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2768
4610c9cc
DX		 2769 if (vmm_exclusive) {
2770 kvm_cpu_vmxon(phys_addr);
2771 ept_sync_global();
2772 }
10474ae8 2773
357d1226 2774 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2775
10474ae8 2776 return 0;
6aa8b732
AK		 2777}
2778
d462b819 2779static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2780{
2781 int cpu = raw_smp_processor_id();
d462b819 2782 struct loaded_vmcs *v, *n;
543e4243 2783
d462b819
NHE		 2784 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2785 loaded_vmcss_on_cpu_link)
2786 __loaded_vmcs_clear(v);
543e4243
AK		 2787}
2788
710ff4a8
EH		 2789
2790/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2791 * tricks.
2792 */
2793static void kvm_cpu_vmxoff(void)
6aa8b732 2794{
4ecac3fd 2795 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2796}
2797
13a34e06 2798static void hardware_disable(void)
710ff4a8 2799{
4610c9cc 2800 if (vmm_exclusive) {
d462b819 2801 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2802 kvm_cpu_vmxoff();
2803 }
7725b894 2804 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2805}
2806
1c3d14fe 2807static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2808 u32 msr, u32 *result)
1c3d14fe
YS		 2809{
2810 u32 vmx_msr_low, vmx_msr_high;
2811 u32 ctl = ctl_min | ctl_opt;
2812
2813 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2814
2815 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2816 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2817
2818 /* Ensure minimum (required) set of control bits are supported. */
2819 if (ctl_min & ~ctl)
002c7f7c 2820 return -EIO;
1c3d14fe
YS		 2821
2822 *result = ctl;
2823 return 0;
2824}
2825
110312c8
AK		 2826static __init bool allow_1_setting(u32 msr, u32 ctl)
2827{
2828 u32 vmx_msr_low, vmx_msr_high;
2829
2830 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2831 return vmx_msr_high & ctl;
2832}
2833
002c7f7c 2834static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2835{
2836 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2837 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2838 u32 _pin_based_exec_control = 0;
2839 u32 _cpu_based_exec_control = 0;
f78e0e2e 2840 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2841 u32 _vmexit_control = 0;
2842 u32 _vmentry_control = 0;
2843
10166744 2844 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2845#ifdef CONFIG_X86_64
2846 CPU_BASED_CR8_LOAD_EXITING |
2847 CPU_BASED_CR8_STORE_EXITING |
2848#endif
d56f546d
SY		 2849 CPU_BASED_CR3_LOAD_EXITING |
2850 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2851 CPU_BASED_USE_IO_BITMAPS |
2852 CPU_BASED_MOV_DR_EXITING |
a7052897 2853 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2854 CPU_BASED_MWAIT_EXITING |
2855 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2856 CPU_BASED_INVLPG_EXITING |
2857 CPU_BASED_RDPMC_EXITING;
443381a8 2858
f78e0e2e 2859 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2860 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2861 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2862 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2863 &_cpu_based_exec_control) < 0)
002c7f7c 2864 return -EIO;
6e5d865c
YS		 2865#ifdef CONFIG_X86_64
2866 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2867 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2868 ~CPU_BASED_CR8_STORE_EXITING;
2869#endif
f78e0e2e 2870 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2871 min2 = 0;
2872 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2873 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2874 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2875 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2876 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2877 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2878 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2879 SECONDARY_EXEC_RDTSCP |
83d4c286 2880 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2881 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2882 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2883 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2884 if (adjust_vmx_controls(min2, opt2,
2885 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2886 &_cpu_based_2nd_exec_control) < 0)
2887 return -EIO;
2888 }
2889#ifndef CONFIG_X86_64
2890 if (!(_cpu_based_2nd_exec_control &
2891 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2892 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2893#endif
83d4c286
YZ		 2894
2895 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2896 _cpu_based_2nd_exec_control &= ~(
8d14695f 2897 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2898 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2899 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2900
d56f546d 2901 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2902 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2903 enabled */
5fff7d27
GN		 2904 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2905 CPU_BASED_CR3_STORE_EXITING |
2906 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2907 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2908 vmx_capability.ept, vmx_capability.vpid);
2909 }
1c3d14fe 2910
81908bf4 2911 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2912#ifdef CONFIG_X86_64
2913 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2914#endif
a547c6db 2915 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2916 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2917 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2918 &_vmexit_control) < 0)
002c7f7c 2919 return -EIO;
1c3d14fe 2920
01e439be
YZ		 2921 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2922 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2923 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2924 &_pin_based_exec_control) < 0)
2925 return -EIO;
2926
2927 if (!(_cpu_based_2nd_exec_control &
2928 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2929 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2930 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2931
c845f9c6 2932 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2933 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2934 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2935 &_vmentry_control) < 0)
002c7f7c 2936 return -EIO;
6aa8b732 2937
c68876fd 2938 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2939
2940 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2941 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2942 return -EIO;
1c3d14fe
YS		 2943
2944#ifdef CONFIG_X86_64
2945 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2946 if (vmx_msr_high & (1u<<16))
002c7f7c 2947 return -EIO;
1c3d14fe
YS		 2948#endif
2949
2950 /* Require Write-Back (WB) memory type for VMCS accesses. */
2951 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2952 return -EIO;
1c3d14fe 2953
002c7f7c
YS		 2954 vmcs_conf->size = vmx_msr_high & 0x1fff;
2955 vmcs_conf->order = get_order(vmcs_config.size);
2956 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2957
002c7f7c
YS		 2958 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2959 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2960 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2961 vmcs_conf->vmexit_ctrl = _vmexit_control;
2962 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2963
110312c8
AK		 2964 cpu_has_load_ia32_efer =
2965 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2966 VM_ENTRY_LOAD_IA32_EFER)
2967 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2968 VM_EXIT_LOAD_IA32_EFER);
2969
8bf00a52
GN		 2970 cpu_has_load_perf_global_ctrl =
2971 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2972 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2973 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2974 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2975
2976 /*
2977 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2978 * but due to arrata below it can't be used. Workaround is to use
2979 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2980 *
2981 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2982 *
2983 * AAK155 (model 26)
2984 * AAP115 (model 30)
2985 * AAT100 (model 37)
2986 * BC86,AAY89,BD102 (model 44)
2987 * BA97 (model 46)
2988 *
2989 */
2990 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2991 switch (boot_cpu_data.x86_model) {
2992 case 26:
2993 case 30:
2994 case 37:
2995 case 44:
2996 case 46:
2997 cpu_has_load_perf_global_ctrl = false;
2998 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2999 "does not work properly. Using workaround\n");
3000 break;
3001 default:
3002 break;
3003 }
3004 }
3005
1c3d14fe 3006 return 0;
c68876fd 3007}
6aa8b732
AK		 3008
3009static struct vmcs *alloc_vmcs_cpu(int cpu)
3010{
3011 int node = cpu_to_node(cpu);
3012 struct page *pages;
3013 struct vmcs *vmcs;
3014
6484eb3e 3015 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3016 if (!pages)
3017 return NULL;
3018 vmcs = page_address(pages);
1c3d14fe
YS		 3019 memset(vmcs, 0, vmcs_config.size);
3020 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3021 return vmcs;
3022}
3023
3024static struct vmcs *alloc_vmcs(void)
3025{
d3b2c338 3026 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3027}
3028
3029static void free_vmcs(struct vmcs *vmcs)
3030{
1c3d14fe 3031 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3032}
3033
d462b819
NHE		 3034/*
3035 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3036 */
3037static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3038{
3039 if (!loaded_vmcs->vmcs)
3040 return;
3041 loaded_vmcs_clear(loaded_vmcs);
3042 free_vmcs(loaded_vmcs->vmcs);
3043 loaded_vmcs->vmcs = NULL;
3044}
3045
39959588 3046static void free_kvm_area(void)
6aa8b732
AK		 3047{
3048 int cpu;
3049
3230bb47 3050 for_each_possible_cpu(cpu) {
6aa8b732 3051 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3052 per_cpu(vmxarea, cpu) = NULL;
3053 }
6aa8b732
AK		 3054}
3055
fe2b201b
BD		 3056static void init_vmcs_shadow_fields(void)
3057{
3058 int i, j;
3059
3060 /* No checks for read only fields yet */
3061
3062 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3063 switch (shadow_read_write_fields[i]) {
3064 case GUEST_BNDCFGS:
3065 if (!vmx_mpx_supported())
3066 continue;
3067 break;
3068 default:
3069 break;
3070 }
3071
3072 if (j < i)
3073 shadow_read_write_fields[j] =
3074 shadow_read_write_fields[i];
3075 j++;
3076 }
3077 max_shadow_read_write_fields = j;
3078
3079 /* shadowed fields guest access without vmexit */
3080 for (i = 0; i < max_shadow_read_write_fields; i++) {
3081 clear_bit(shadow_read_write_fields[i],
3082 vmx_vmwrite_bitmap);
3083 clear_bit(shadow_read_write_fields[i],
3084 vmx_vmread_bitmap);
3085 }
3086 for (i = 0; i < max_shadow_read_only_fields; i++)
3087 clear_bit(shadow_read_only_fields[i],
3088 vmx_vmread_bitmap);
3089}
3090
6aa8b732
AK		 3091static __init int alloc_kvm_area(void)
3092{
3093 int cpu;
3094
3230bb47 3095 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3096 struct vmcs *vmcs;
3097
3098 vmcs = alloc_vmcs_cpu(cpu);
3099 if (!vmcs) {
3100 free_kvm_area();
3101 return -ENOMEM;
3102 }
3103
3104 per_cpu(vmxarea, cpu) = vmcs;
3105 }
3106 return 0;
3107}
3108
3109static __init int hardware_setup(void)
3110{
002c7f7c
YS		 3111 if (setup_vmcs_config(&vmcs_config) < 0)
3112 return -EIO;
50a37eb4
JR		 3113
3114 if (boot_cpu_has(X86_FEATURE_NX))
3115 kvm_enable_efer_bits(EFER_NX);
3116
93ba03c2
SY		 3117 if (!cpu_has_vmx_vpid())
3118 enable_vpid = 0;
abc4fc58
AG		 3119 if (!cpu_has_vmx_shadow_vmcs())
3120 enable_shadow_vmcs = 0;
fe2b201b
BD		 3121 if (enable_shadow_vmcs)
3122 init_vmcs_shadow_fields();
93ba03c2 3123
4bc9b982
SY		 3124 if (!cpu_has_vmx_ept() ||
3125 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3126 enable_ept = 0;
3a624e29 3127 enable_unrestricted_guest = 0;
83c3a331 3128 enable_ept_ad_bits = 0;
3a624e29
NK		 3129 }
3130
83c3a331
XH		 3131 if (!cpu_has_vmx_ept_ad_bits())
3132 enable_ept_ad_bits = 0;
3133
3a624e29
NK		 3134 if (!cpu_has_vmx_unrestricted_guest())
3135 enable_unrestricted_guest = 0;
93ba03c2
SY		 3136
3137 if (!cpu_has_vmx_flexpriority())
3138 flexpriority_enabled = 0;
3139
95ba8273
GN		 3140 if (!cpu_has_vmx_tpr_shadow())
3141 kvm_x86_ops->update_cr8_intercept = NULL;
3142
54dee993
MT		 3143 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3144 kvm_disable_largepages();
3145
4b8d54f9
ZE		 3146 if (!cpu_has_vmx_ple())
3147 ple_gap = 0;
3148
01e439be
YZ		 3149 if (!cpu_has_vmx_apicv())
3150 enable_apicv = 0;
c7c9c56c 3151
01e439be 3152 if (enable_apicv)
c7c9c56c 3153 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3154 else {
c7c9c56c 3155 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3156 kvm_x86_ops->deliver_posted_interrupt = NULL;
3157 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3158 }
83d4c286 3159
b87a51ae
NHE		 3160 if (nested)
3161 nested_vmx_setup_ctls_msrs();
3162
6aa8b732
AK		 3163 return alloc_kvm_area();
3164}
3165
3166static __exit void hardware_unsetup(void)
3167{
3168 free_kvm_area();
3169}
3170
14168786
GN		 3171static bool emulation_required(struct kvm_vcpu *vcpu)
3172{
3173 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3174}
3175
91b0aa2c 3176static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3177 struct kvm_segment *save)
6aa8b732 3178{
d99e4152
GN		 3179 if (!emulate_invalid_guest_state) {
3180 /*
3181 * CS and SS RPL should be equal during guest entry according
3182 * to VMX spec, but in reality it is not always so. Since vcpu
3183 * is in the middle of the transition from real mode to
3184 * protected mode it is safe to assume that RPL 0 is a good
3185 * default value.
3186 */
3187 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3188 save->selector &= ~SELECTOR_RPL_MASK;
3189 save->dpl = save->selector & SELECTOR_RPL_MASK;
3190 save->s = 1;
6aa8b732 3191 }
d99e4152 3192 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3193}
3194
3195static void enter_pmode(struct kvm_vcpu *vcpu)
3196{
3197 unsigned long flags;
a89a8fb9 3198 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3199
d99e4152
GN		 3200 /*
3201 * Update real mode segment cache. It may be not up-to-date if sement
3202 * register was written while vcpu was in a guest mode.
3203 */
3204 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3205 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3206 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3207 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3208 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3209 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3210
7ffd92c5 3211 vmx->rmode.vm86_active = 0;
6aa8b732 3212
2fb92db1
AK		 3213 vmx_segment_cache_clear(vmx);
3214
f5f7b2fe 3215 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3216
3217 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3218 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3219 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3220 vmcs_writel(GUEST_RFLAGS, flags);
3221
66aee91a
RR		 3222 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3223 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3224
3225 update_exception_bitmap(vcpu);
3226
91b0aa2c
GN		 3227 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3228 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3229 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3230 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3231 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3232 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3233}
3234
f5f7b2fe 3235static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3236{
772e0318 3237 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3238 struct kvm_segment var = *save;
3239
3240 var.dpl = 0x3;
3241 if (seg == VCPU_SREG_CS)
3242 var.type = 0x3;
3243
3244 if (!emulate_invalid_guest_state) {
3245 var.selector = var.base >> 4;
3246 var.base = var.base & 0xffff0;
3247 var.limit = 0xffff;
3248 var.g = 0;
3249 var.db = 0;
3250 var.present = 1;
3251 var.s = 1;
3252 var.l = 0;
3253 var.unusable = 0;
3254 var.type = 0x3;
3255 var.avl = 0;
3256 if (save->base & 0xf)
3257 printk_once(KERN_WARNING "kvm: segment base is not "
3258 "paragraph aligned when entering "
3259 "protected mode (seg=%d)", seg);
3260 }
6aa8b732 3261
d99e4152
GN		 3262 vmcs_write16(sf->selector, var.selector);
3263 vmcs_write32(sf->base, var.base);
3264 vmcs_write32(sf->limit, var.limit);
3265 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3266}
3267
3268static void enter_rmode(struct kvm_vcpu *vcpu)
3269{
3270 unsigned long flags;
a89a8fb9 3271 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3272
f5f7b2fe
AK		 3273 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3274 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3275 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3276 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3277 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3278 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3279 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3280
7ffd92c5 3281 vmx->rmode.vm86_active = 1;
6aa8b732 3282
776e58ea
GN		 3283 /*
3284 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3285 * vcpu. Warn the user that an update is overdue.
776e58ea 3286 */
4918c6ca 3287 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3288 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3289 "called before entering vcpu\n");
776e58ea 3290
2fb92db1
AK		 3291 vmx_segment_cache_clear(vmx);
3292
4918c6ca 3293 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3294 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3295 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3296
3297 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3298 vmx->rmode.save_rflags = flags;
6aa8b732 3299
053de044 3300 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3301
3302 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3303 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3304 update_exception_bitmap(vcpu);
3305
d99e4152
GN		 3306 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3307 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3308 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3309 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3310 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3311 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3312
8668a3c4 3313 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3314}
3315
401d10de
AS		 3316static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3317{
3318 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3319 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3320
3321 if (!msr)
3322 return;
401d10de 3323
44ea2b17
AK		 3324 /*
3325 * Force kernel_gs_base reloading before EFER changes, as control
3326 * of this msr depends on is_long_mode().
3327 */
3328 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3329 vcpu->arch.efer = efer;
401d10de 3330 if (efer & EFER_LMA) {
2961e876 3331 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3332 msr->data = efer;
3333 } else {
2961e876 3334 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3335
3336 msr->data = efer & ~EFER_LME;
3337 }
3338 setup_msrs(vmx);
3339}
3340
05b3e0c2 3341#ifdef CONFIG_X86_64
6aa8b732
AK		 3342
3343static void enter_lmode(struct kvm_vcpu *vcpu)
3344{
3345 u32 guest_tr_ar;
3346
2fb92db1
AK		 3347 vmx_segment_cache_clear(to_vmx(vcpu));
3348
6aa8b732
AK		 3349 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3350 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3351 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3352 __func__);
6aa8b732
AK		 3353 vmcs_write32(GUEST_TR_AR_BYTES,
3354 (guest_tr_ar & ~AR_TYPE_MASK)
3355 | AR_TYPE_BUSY_64_TSS);
3356 }
da38f438 3357 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3358}
3359
3360static void exit_lmode(struct kvm_vcpu *vcpu)
3361{
2961e876 3362 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3363 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3364}
3365
3366#endif
3367
2384d2b3
SY		 3368static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3369{
b9d762fa 3370 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3371 if (enable_ept) {
3372 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3373 return;
4e1096d2 3374 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3375 }
2384d2b3
SY		 3376}
3377
e8467fda
AK		 3378static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3379{
3380 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3381
3382 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3383 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3384}
3385
aff48baa
AK		 3386static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3387{
3388 if (enable_ept && is_paging(vcpu))
3389 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3390 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3391}
3392
25c4c276 3393static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3394{
fc78f519
AK		 3395 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3396
3397 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3398 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3399}
3400
1439442c
SY		 3401static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3402{
d0d538b9
GN		 3403 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3404
6de4f3ad
AK		 3405 if (!test_bit(VCPU_EXREG_PDPTR,
3406 (unsigned long *)&vcpu->arch.regs_dirty))
3407 return;
3408
1439442c 3409 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3410 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3411 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3412 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3413 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3414 }
3415}
3416
8f5d549f
AK		 3417static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3418{
d0d538b9
GN		 3419 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3420
8f5d549f 3421 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3422 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3423 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3424 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3425 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3426 }
6de4f3ad
AK		 3427
3428 __set_bit(VCPU_EXREG_PDPTR,
3429 (unsigned long *)&vcpu->arch.regs_avail);
3430 __set_bit(VCPU_EXREG_PDPTR,
3431 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3432}
3433
5e1746d6 3434static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3435
3436static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3437 unsigned long cr0,
3438 struct kvm_vcpu *vcpu)
3439{
5233dd51
MT		 3440 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3441 vmx_decache_cr3(vcpu);
1439442c
SY		 3442 if (!(cr0 & X86_CR0_PG)) {
3443 /* From paging/starting to nonpaging */
3444 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3445 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3446 (CPU_BASED_CR3_LOAD_EXITING |
3447 CPU_BASED_CR3_STORE_EXITING));
3448 vcpu->arch.cr0 = cr0;
fc78f519 3449 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3450 } else if (!is_paging(vcpu)) {
3451 /* From nonpaging to paging */
3452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3453 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3454 ~(CPU_BASED_CR3_LOAD_EXITING |
3455 CPU_BASED_CR3_STORE_EXITING));
3456 vcpu->arch.cr0 = cr0;
fc78f519 3457 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3458 }
95eb84a7
SY		 3459
3460 if (!(cr0 & X86_CR0_WP))
3461 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3462}
3463
6aa8b732
AK		 3464static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3465{
7ffd92c5 3466 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3467 unsigned long hw_cr0;
3468
5037878e 3469 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3470 if (enable_unrestricted_guest)
5037878e 3471 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3472 else {
5037878e 3473 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3474
218e763f
GN		 3475 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3476 enter_pmode(vcpu);
6aa8b732 3477
218e763f
GN		 3478 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3479 enter_rmode(vcpu);
3480 }
6aa8b732 3481
05b3e0c2 3482#ifdef CONFIG_X86_64
f6801dff 3483 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3484 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3485 enter_lmode(vcpu);
707d92fa 3486 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3487 exit_lmode(vcpu);
3488 }
3489#endif
3490
089d034e 3491 if (enable_ept)
1439442c
SY		 3492 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3493
02daab21 3494 if (!vcpu->fpu_active)
81231c69 3495 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3496
6aa8b732 3497 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3498 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3499 vcpu->arch.cr0 = cr0;
14168786
GN		 3500
3501 /* depends on vcpu->arch.cr0 to be set to a new value */
3502 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3503}
3504
1439442c
SY		 3505static u64 construct_eptp(unsigned long root_hpa)
3506{
3507 u64 eptp;
3508
3509 /* TODO write the value reading from MSR */
3510 eptp = VMX_EPT_DEFAULT_MT |
3511 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3512 if (enable_ept_ad_bits)
3513 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3514 eptp |= (root_hpa & PAGE_MASK);
3515
3516 return eptp;
3517}
3518
6aa8b732
AK		 3519static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3520{
1439442c
SY		 3521 unsigned long guest_cr3;
3522 u64 eptp;
3523
3524 guest_cr3 = cr3;
089d034e 3525 if (enable_ept) {
1439442c
SY		 3526 eptp = construct_eptp(cr3);
3527 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3528 if (is_paging(vcpu) || is_guest_mode(vcpu))
3529 guest_cr3 = kvm_read_cr3(vcpu);
3530 else
3531 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3532 ept_load_pdptrs(vcpu);
1439442c
SY		 3533 }
3534
2384d2b3 3535 vmx_flush_tlb(vcpu);
1439442c 3536 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3537}
3538
5e1746d6 3539static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3540{
7ffd92c5 3541 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3542 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3543
5e1746d6
NHE		 3544 if (cr4 & X86_CR4_VMXE) {
3545 /*
3546 * To use VMXON (and later other VMX instructions), a guest
3547 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3548 * So basically the check on whether to allow nested VMX
3549 * is here.
3550 */
3551 if (!nested_vmx_allowed(vcpu))
3552 return 1;
1a0d74e6
JK		 3553 }
3554 if (to_vmx(vcpu)->nested.vmxon &&
3555 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3556 return 1;
3557
ad312c7c 3558 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3559 if (enable_ept) {
3560 if (!is_paging(vcpu)) {
3561 hw_cr4 &= ~X86_CR4_PAE;
3562 hw_cr4 |= X86_CR4_PSE;
c08800a5 3563 /*
e1e746b3
FW		 3564 * SMEP/SMAP is disabled if CPU is in non-paging mode
3565 * in hardware. However KVM always uses paging mode to
c08800a5 3566 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3567 * To emulate this behavior, SMEP/SMAP needs to be
3568 * manually disabled when guest switches to non-paging
3569 * mode.
c08800a5 3570 */
e1e746b3 3571 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3572 } else if (!(cr4 & X86_CR4_PAE)) {
3573 hw_cr4 &= ~X86_CR4_PAE;
3574 }
3575 }
1439442c
SY		 3576
3577 vmcs_writel(CR4_READ_SHADOW, cr4);
3578 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3579 return 0;
6aa8b732
AK		 3580}
3581
6aa8b732
AK		 3582static void vmx_get_segment(struct kvm_vcpu *vcpu,
3583 struct kvm_segment *var, int seg)
3584{
a9179499 3585 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3586 u32 ar;
3587
c6ad1153 3588 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3589 *var = vmx->rmode.segs[seg];
a9179499 3590 if (seg == VCPU_SREG_TR
2fb92db1 3591 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3592 return;
1390a28b
AK		 3593 var->base = vmx_read_guest_seg_base(vmx, seg);
3594 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3595 return;
a9179499 3596 }
2fb92db1
AK		 3597 var->base = vmx_read_guest_seg_base(vmx, seg);
3598 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3599 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3600 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3601 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3602 var->type = ar & 15;
3603 var->s = (ar >> 4) & 1;
3604 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3605 /*
3606 * Some userspaces do not preserve unusable property. Since usable
3607 * segment has to be present according to VMX spec we can use present
3608 * property to amend userspace bug by making unusable segment always
3609 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3610 * segment as unusable.
3611 */
3612 var->present = !var->unusable;
6aa8b732
AK		 3613 var->avl = (ar >> 12) & 1;
3614 var->l = (ar >> 13) & 1;
3615 var->db = (ar >> 14) & 1;
3616 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3617}
3618
a9179499
AK		 3619static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3620{
a9179499
AK		 3621 struct kvm_segment s;
3622
3623 if (to_vmx(vcpu)->rmode.vm86_active) {
3624 vmx_get_segment(vcpu, &s, seg);
3625 return s.base;
3626 }
2fb92db1 3627 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3628}
3629
b09408d0 3630static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3631{
b09408d0
MT		 3632 struct vcpu_vmx *vmx = to_vmx(vcpu);
3633
ae9fedc7 3634 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3635 return 0;
ae9fedc7
PB		 3636 else {
3637 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3638 return AR_DPL(ar);
69c73028 3639 }
69c73028
AK		 3640}
3641
653e3108 3642static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3643{
6aa8b732
AK		 3644 u32 ar;
3645
f0495f9b 3646 if (var->unusable || !var->present)
6aa8b732
AK		 3647 ar = 1 << 16;
3648 else {
3649 ar = var->type & 15;
3650 ar |= (var->s & 1) << 4;
3651 ar |= (var->dpl & 3) << 5;
3652 ar |= (var->present & 1) << 7;
3653 ar |= (var->avl & 1) << 12;
3654 ar |= (var->l & 1) << 13;
3655 ar |= (var->db & 1) << 14;
3656 ar |= (var->g & 1) << 15;
3657 }
653e3108
AK		 3658
3659 return ar;
3660}
3661
3662static void vmx_set_segment(struct kvm_vcpu *vcpu,
3663 struct kvm_segment *var, int seg)
3664{
7ffd92c5 3665 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3666 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3667
2fb92db1
AK		 3668 vmx_segment_cache_clear(vmx);
3669
1ecd50a9
GN		 3670 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3671 vmx->rmode.segs[seg] = *var;
3672 if (seg == VCPU_SREG_TR)
3673 vmcs_write16(sf->selector, var->selector);
3674 else if (var->s)
3675 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3676 goto out;
653e3108 3677 }
1ecd50a9 3678
653e3108
AK		 3679 vmcs_writel(sf->base, var->base);
3680 vmcs_write32(sf->limit, var->limit);
3681 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3682
3683 /*
3684 * Fix the "Accessed" bit in AR field of segment registers for older
3685 * qemu binaries.
3686 * IA32 arch specifies that at the time of processor reset the
3687 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3688 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3689 * state vmexit when "unrestricted guest" mode is turned on.
3690 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3691 * tree. Newer qemu binaries with that qemu fix would not need this
3692 * kvm hack.
3693 */
3694 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3695 var->type |= 0x1; /* Accessed */
3a624e29 3696
f924d66d 3697 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3698
3699out:
98eb2f8b 3700 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3701}
3702
6aa8b732
AK		 3703static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3704{
2fb92db1 3705 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3706
3707 *db = (ar >> 14) & 1;
3708 *l = (ar >> 13) & 1;
3709}
3710
89a27f4d 3711static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3712{
89a27f4d
GN		 3713 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3714 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3715}
3716
89a27f4d 3717static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3718{
89a27f4d
GN		 3719 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3720 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3721}
3722
89a27f4d 3723static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3724{
89a27f4d
GN		 3725 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3726 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3727}
3728
89a27f4d 3729static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3730{
89a27f4d
GN		 3731 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3732 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3733}
3734
648dfaa7
MG		 3735static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3736{
3737 struct kvm_segment var;
3738 u32 ar;
3739
3740 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3741 var.dpl = 0x3;
0647f4aa
GN		 3742 if (seg == VCPU_SREG_CS)
3743 var.type = 0x3;
648dfaa7
MG		 3744 ar = vmx_segment_access_rights(&var);
3745
3746 if (var.base != (var.selector << 4))
3747 return false;
89efbed0 3748 if (var.limit != 0xffff)
648dfaa7 3749 return false;
07f42f5f 3750 if (ar != 0xf3)
648dfaa7
MG		 3751 return false;
3752
3753 return true;
3754}
3755
3756static bool code_segment_valid(struct kvm_vcpu *vcpu)
3757{
3758 struct kvm_segment cs;
3759 unsigned int cs_rpl;
3760
3761 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3762 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3763
1872a3f4
AK		 3764 if (cs.unusable)
3765 return false;
648dfaa7
MG		 3766 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3767 return false;
3768 if (!cs.s)
3769 return false;
1872a3f4 3770 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3771 if (cs.dpl > cs_rpl)
3772 return false;
1872a3f4 3773 } else {
648dfaa7
MG		 3774 if (cs.dpl != cs_rpl)
3775 return false;
3776 }
3777 if (!cs.present)
3778 return false;
3779
3780 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3781 return true;
3782}
3783
3784static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3785{
3786 struct kvm_segment ss;
3787 unsigned int ss_rpl;
3788
3789 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3790 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3791
1872a3f4
AK		 3792 if (ss.unusable)
3793 return true;
3794 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3795 return false;
3796 if (!ss.s)
3797 return false;
3798 if (ss.dpl != ss_rpl) /* DPL != RPL */
3799 return false;
3800 if (!ss.present)
3801 return false;
3802
3803 return true;
3804}
3805
3806static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3807{
3808 struct kvm_segment var;
3809 unsigned int rpl;
3810
3811 vmx_get_segment(vcpu, &var, seg);
3812 rpl = var.selector & SELECTOR_RPL_MASK;
3813
1872a3f4
AK		 3814 if (var.unusable)
3815 return true;
648dfaa7
MG		 3816 if (!var.s)
3817 return false;
3818 if (!var.present)
3819 return false;
3820 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3821 if (var.dpl < rpl) /* DPL < RPL */
3822 return false;
3823 }
3824
3825 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3826 * rights flags
3827 */
3828 return true;
3829}
3830
3831static bool tr_valid(struct kvm_vcpu *vcpu)
3832{
3833 struct kvm_segment tr;
3834
3835 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3836
1872a3f4
AK		 3837 if (tr.unusable)
3838 return false;
648dfaa7
MG		 3839 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3840 return false;
1872a3f4 3841 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3842 return false;
3843 if (!tr.present)
3844 return false;
3845
3846 return true;
3847}
3848
3849static bool ldtr_valid(struct kvm_vcpu *vcpu)
3850{
3851 struct kvm_segment ldtr;
3852
3853 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3854
1872a3f4
AK		 3855 if (ldtr.unusable)
3856 return true;
648dfaa7
MG		 3857 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3858 return false;
3859 if (ldtr.type != 2)
3860 return false;
3861 if (!ldtr.present)
3862 return false;
3863
3864 return true;
3865}
3866
3867static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3868{
3869 struct kvm_segment cs, ss;
3870
3871 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3872 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3873
3874 return ((cs.selector & SELECTOR_RPL_MASK) ==
3875 (ss.selector & SELECTOR_RPL_MASK));
3876}
3877
3878/*
3879 * Check if guest state is valid. Returns true if valid, false if
3880 * not.
3881 * We assume that registers are always usable
3882 */
3883static bool guest_state_valid(struct kvm_vcpu *vcpu)
3884{
c5e97c80
GN		 3885 if (enable_unrestricted_guest)
3886 return true;
3887
648dfaa7 3888 /* real mode guest state checks */
f13882d8 3889 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3890 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3891 return false;
3892 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3893 return false;
3894 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3895 return false;
3896 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3897 return false;
3898 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3899 return false;
3900 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3901 return false;
3902 } else {
3903 /* protected mode guest state checks */
3904 if (!cs_ss_rpl_check(vcpu))
3905 return false;
3906 if (!code_segment_valid(vcpu))
3907 return false;
3908 if (!stack_segment_valid(vcpu))
3909 return false;
3910 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3911 return false;
3912 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3913 return false;
3914 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3915 return false;
3916 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3917 return false;
3918 if (!tr_valid(vcpu))
3919 return false;
3920 if (!ldtr_valid(vcpu))
3921 return false;
3922 }
3923 /* TODO:
3924 * - Add checks on RIP
3925 * - Add checks on RFLAGS
3926 */
3927
3928 return true;
3929}
3930
d77c26fc 3931static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3932{
40dcaa9f 3933 gfn_t fn;
195aefde 3934 u16 data = 0;
1f755a82 3935 int idx, r;
6aa8b732 3936
40dcaa9f 3937 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3938 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3939 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3940 if (r < 0)
10589a46 3941 goto out;
195aefde 3942 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3943 r = kvm_write_guest_page(kvm, fn++, &data,
3944 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3945 if (r < 0)
10589a46 3946 goto out;
195aefde
IE		 3947 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3948 if (r < 0)
10589a46 3949 goto out;
195aefde
IE		 3950 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3951 if (r < 0)
10589a46 3952 goto out;
195aefde 3953 data = ~0;
10589a46
MT		 3954 r = kvm_write_guest_page(kvm, fn, &data,
3955 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3956 sizeof(u8));
10589a46 3957out:
40dcaa9f 3958 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3959 return r;
6aa8b732
AK		 3960}
3961
b7ebfb05
SY		 3962static int init_rmode_identity_map(struct kvm *kvm)
3963{
f51770ed 3964 int i, idx, r = 0;
b7ebfb05
SY		 3965 pfn_t identity_map_pfn;
3966 u32 tmp;
3967
089d034e 3968 if (!enable_ept)
f51770ed 3969 return 0;
a255d479
TC		 3970
3971 /* Protect kvm->arch.ept_identity_pagetable_done. */
3972 mutex_lock(&kvm->slots_lock);
3973
f51770ed 3974 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3975 goto out2;
a255d479 3976
b927a3ce 3977 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3978
3979 r = alloc_identity_pagetable(kvm);
f51770ed 3980 if (r < 0)
a255d479
TC		 3981 goto out2;
3982
40dcaa9f 3983 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3984 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3985 if (r < 0)
3986 goto out;
3987 /* Set up identity-mapping pagetable for EPT in real mode */
3988 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3989 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3990 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3991 r = kvm_write_guest_page(kvm, identity_map_pfn,
3992 &tmp, i * sizeof(tmp), sizeof(tmp));
3993 if (r < 0)
3994 goto out;
3995 }
3996 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3997
b7ebfb05 3998out:
40dcaa9f 3999 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4000
4001out2:
4002 mutex_unlock(&kvm->slots_lock);
f51770ed 4003 return r;
b7ebfb05
SY		 4004}
4005
6aa8b732
AK		 4006static void seg_setup(int seg)
4007{
772e0318 4008 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4009 unsigned int ar;
6aa8b732
AK		 4010
4011 vmcs_write16(sf->selector, 0);
4012 vmcs_writel(sf->base, 0);
4013 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4014 ar = 0x93;
4015 if (seg == VCPU_SREG_CS)
4016 ar |= 0x08; /* code segment */
3a624e29
NK		 4017
4018 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4019}
4020
f78e0e2e
SY		 4021static int alloc_apic_access_page(struct kvm *kvm)
4022{
4484141a 4023 struct page *page;
f78e0e2e
SY		 4024 struct kvm_userspace_memory_region kvm_userspace_mem;
4025 int r = 0;
4026
79fac95e 4027 mutex_lock(&kvm->slots_lock);
bfc6d222 4028 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 4029 goto out;
4030 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4031 kvm_userspace_mem.flags = 0;
73a6d941 4032 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4033 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4034 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4035 if (r)
4036 goto out;
72dc67a6 4037
73a6d941 4038 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4039 if (is_error_page(page)) {
4040 r = -EFAULT;
4041 goto out;
4042 }
4043
4044 kvm->arch.apic_access_page = page;
f78e0e2e 4045out:
79fac95e 4046 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4047 return r;
4048}
4049
b7ebfb05
SY		 4050static int alloc_identity_pagetable(struct kvm *kvm)
4051{
a255d479
TC		 4052 /* Called with kvm->slots_lock held. */
4053
b7ebfb05
SY		 4054 struct kvm_userspace_memory_region kvm_userspace_mem;
4055 int r = 0;
4056
a255d479
TC		 4057 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4058
b7ebfb05
SY		 4059 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4060 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4061 kvm_userspace_mem.guest_phys_addr =
4062 kvm->arch.ept_identity_map_addr;
b7ebfb05 4063 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4064 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4065
b7ebfb05
SY		 4066 return r;
4067}
4068
2384d2b3
SY		 4069static void allocate_vpid(struct vcpu_vmx *vmx)
4070{
4071 int vpid;
4072
4073 vmx->vpid = 0;
919818ab 4074 if (!enable_vpid)
2384d2b3
SY		 4075 return;
4076 spin_lock(&vmx_vpid_lock);
4077 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4078 if (vpid < VMX_NR_VPIDS) {
4079 vmx->vpid = vpid;
4080 __set_bit(vpid, vmx_vpid_bitmap);
4081 }
4082 spin_unlock(&vmx_vpid_lock);
4083}
4084
cdbecfc3
LJ		 4085static void free_vpid(struct vcpu_vmx *vmx)
4086{
4087 if (!enable_vpid)
4088 return;
4089 spin_lock(&vmx_vpid_lock);
4090 if (vmx->vpid != 0)
4091 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4092 spin_unlock(&vmx_vpid_lock);
4093}
4094
8d14695f
YZ		 4095#define MSR_TYPE_R 1
4096#define MSR_TYPE_W 2
4097static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4098 u32 msr, int type)
25c5f225 4099{
3e7c73e9 4100 int f = sizeof(unsigned long);
25c5f225
SY		 4101
4102 if (!cpu_has_vmx_msr_bitmap())
4103 return;
4104
4105 /*
4106 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4107 * have the write-low and read-high bitmap offsets the wrong way round.
4108 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4109 */
25c5f225 4110 if (msr <= 0x1fff) {
8d14695f
YZ		 4111 if (type & MSR_TYPE_R)
4112 /* read-low */
4113 __clear_bit(msr, msr_bitmap + 0x000 / f);
4114
4115 if (type & MSR_TYPE_W)
4116 /* write-low */
4117 __clear_bit(msr, msr_bitmap + 0x800 / f);
4118
25c5f225
SY		 4119 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4120 msr &= 0x1fff;
8d14695f
YZ		 4121 if (type & MSR_TYPE_R)
4122 /* read-high */
4123 __clear_bit(msr, msr_bitmap + 0x400 / f);
4124
4125 if (type & MSR_TYPE_W)
4126 /* write-high */
4127 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4128
4129 }
4130}
4131
4132static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4133 u32 msr, int type)
4134{
4135 int f = sizeof(unsigned long);
4136
4137 if (!cpu_has_vmx_msr_bitmap())
4138 return;
4139
4140 /*
4141 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4142 * have the write-low and read-high bitmap offsets the wrong way round.
4143 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4144 */
4145 if (msr <= 0x1fff) {
4146 if (type & MSR_TYPE_R)
4147 /* read-low */
4148 __set_bit(msr, msr_bitmap + 0x000 / f);
4149
4150 if (type & MSR_TYPE_W)
4151 /* write-low */
4152 __set_bit(msr, msr_bitmap + 0x800 / f);
4153
4154 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4155 msr &= 0x1fff;
4156 if (type & MSR_TYPE_R)
4157 /* read-high */
4158 __set_bit(msr, msr_bitmap + 0x400 / f);
4159
4160 if (type & MSR_TYPE_W)
4161 /* write-high */
4162 __set_bit(msr, msr_bitmap + 0xc00 / f);
4163
25c5f225 4164 }
25c5f225
SY		 4165}
4166
5897297b
AK		 4167static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4168{
4169 if (!longmode_only)
8d14695f
YZ		 4170 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4171 msr, MSR_TYPE_R | MSR_TYPE_W);
4172 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4173 msr, MSR_TYPE_R | MSR_TYPE_W);
4174}
4175
4176static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4177{
4178 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4179 msr, MSR_TYPE_R);
4180 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4181 msr, MSR_TYPE_R);
4182}
4183
4184static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4185{
4186 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4187 msr, MSR_TYPE_R);
4188 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4189 msr, MSR_TYPE_R);
4190}
4191
4192static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4193{
4194 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4195 msr, MSR_TYPE_W);
4196 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4197 msr, MSR_TYPE_W);
5897297b
AK		 4198}
4199
01e439be
YZ		 4200static int vmx_vm_has_apicv(struct kvm *kvm)
4201{
4202 return enable_apicv && irqchip_in_kernel(kvm);
4203}
4204
a20ed54d
YZ		 4205/*
4206 * Send interrupt to vcpu via posted interrupt way.
4207 * 1. If target vcpu is running(non-root mode), send posted interrupt
4208 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4209 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4210 * interrupt from PIR in next vmentry.
4211 */
4212static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4213{
4214 struct vcpu_vmx *vmx = to_vmx(vcpu);
4215 int r;
4216
4217 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4218 return;
4219
4220 r = pi_test_and_set_on(&vmx->pi_desc);
4221 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4222#ifdef CONFIG_SMP
a20ed54d
YZ		 4223 if (!r && (vcpu->mode == IN_GUEST_MODE))
4224 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4225 POSTED_INTR_VECTOR);
4226 else
6ffbbbba 4227#endif
a20ed54d
YZ		 4228 kvm_vcpu_kick(vcpu);
4229}
4230
4231static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4232{
4233 struct vcpu_vmx *vmx = to_vmx(vcpu);
4234
4235 if (!pi_test_and_clear_on(&vmx->pi_desc))
4236 return;
4237
4238 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4239}
4240
4241static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4242{
4243 return;
4244}
4245
a3a8ff8e
NHE		 4246/*
4247 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4248 * will not change in the lifetime of the guest.
4249 * Note that host-state that does change is set elsewhere. E.g., host-state
4250 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4251 */
a547c6db 4252static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4253{
4254 u32 low32, high32;
4255 unsigned long tmpl;
4256 struct desc_ptr dt;
4257
b1a74bf8 4258 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4259 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4260 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4261
4262 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4263#ifdef CONFIG_X86_64
4264 /*
4265 * Load null selectors, so we can avoid reloading them in
4266 * __vmx_load_host_state(), in case userspace uses the null selectors
4267 * too (the expected case).
4268 */
4269 vmcs_write16(HOST_DS_SELECTOR, 0);
4270 vmcs_write16(HOST_ES_SELECTOR, 0);
4271#else
a3a8ff8e
NHE		 4272 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4273 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4274#endif
a3a8ff8e
NHE		 4275 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4276 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4277
4278 native_store_idt(&dt);
4279 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4280 vmx->host_idt_base = dt.address;
a3a8ff8e 4281
83287ea4 4282 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4283
4284 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4285 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4286 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4287 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4288
4289 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4290 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4291 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4292 }
4293}
4294
bf8179a0
NHE		 4295static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4296{
4297 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4298 if (enable_ept)
4299 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4300 if (is_guest_mode(&vmx->vcpu))
4301 vmx->vcpu.arch.cr4_guest_owned_bits &=
4302 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4303 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4304}
4305
01e439be
YZ		 4306static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4307{
4308 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4309
4310 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4311 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4312 return pin_based_exec_ctrl;
4313}
4314
bf8179a0
NHE		 4315static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4316{
4317 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4318
4319 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4320 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4321
bf8179a0
NHE		 4322 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4323 exec_control &= ~CPU_BASED_TPR_SHADOW;
4324#ifdef CONFIG_X86_64
4325 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4326 CPU_BASED_CR8_LOAD_EXITING;
4327#endif
4328 }
4329 if (!enable_ept)
4330 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4331 CPU_BASED_CR3_LOAD_EXITING |
4332 CPU_BASED_INVLPG_EXITING;
4333 return exec_control;
4334}
4335
4336static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4337{
4338 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4339 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4340 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4341 if (vmx->vpid == 0)
4342 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4343 if (!enable_ept) {
4344 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4345 enable_unrestricted_guest = 0;
ad756a16
MJ		 4346 /* Enable INVPCID for non-ept guests may cause performance regression. */
4347 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4348 }
4349 if (!enable_unrestricted_guest)
4350 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4351 if (!ple_gap)
4352 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4353 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4354 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4355 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4356 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4357 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4358 (handle_vmptrld).
4359 We can NOT enable shadow_vmcs here because we don't have yet
4360 a current VMCS12
4361 */
4362 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4363 return exec_control;
4364}
4365
ce88decf
XG		 4366static void ept_set_mmio_spte_mask(void)
4367{
4368 /*
4369 * EPT Misconfigurations can be generated if the value of bits 2:0
4370 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4371 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4372 * spte.
4373 */
885032b9 4374 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4375}
4376
6aa8b732
AK		 4377/*
4378 * Sets up the vmcs for emulated real mode.
4379 */
8b9cf98c 4380static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4381{
2e4ce7f5 4382#ifdef CONFIG_X86_64
6aa8b732 4383 unsigned long a;
2e4ce7f5 4384#endif
6aa8b732 4385 int i;
6aa8b732 4386
6aa8b732 4387 /* I/O */
3e7c73e9
AK		 4388 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4389 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4390
4607c2d7
AG		 4391 if (enable_shadow_vmcs) {
4392 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4393 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4394 }
25c5f225 4395 if (cpu_has_vmx_msr_bitmap())
5897297b 4396 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4397
6aa8b732
AK		 4398 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4399
6aa8b732 4400 /* Control */
01e439be 4401 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4402
bf8179a0 4403 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4404
83ff3b9d 4405 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4406 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4407 vmx_secondary_exec_control(vmx));
83ff3b9d 4408 }
f78e0e2e 4409
01e439be 4410 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4411 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4412 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4413 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4414 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4415
4416 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4417
4418 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4419 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4420 }
4421
4b8d54f9
ZE		 4422 if (ple_gap) {
4423 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4424 vmx->ple_window = ple_window;
4425 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4426 }
4427
c3707958
XG		 4428 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4429 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4430 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4431
9581d442
AK		 4432 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4433 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4434 vmx_set_constant_host_state(vmx);
05b3e0c2 4435#ifdef CONFIG_X86_64
6aa8b732
AK		 4436 rdmsrl(MSR_FS_BASE, a);
4437 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4438 rdmsrl(MSR_GS_BASE, a);
4439 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4440#else
4441 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4442 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4443#endif
4444
2cc51560
ED		 4445 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4446 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4447 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4448 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4449 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4450
468d472f 4451 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4452 u32 msr_low, msr_high;
4453 u64 host_pat;
468d472f
SY		 4454 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4455 host_pat = msr_low | ((u64) msr_high << 32);
4456 /* Write the default value follow host pat */
4457 vmcs_write64(GUEST_IA32_PAT, host_pat);
4458 /* Keep arch.pat sync with GUEST_IA32_PAT */
4459 vmx->vcpu.arch.pat = host_pat;
4460 }
4461
03916db9 4462 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4463 u32 index = vmx_msr_index[i];
4464 u32 data_low, data_high;
a2fa3e9f 4465 int j = vmx->nmsrs;
6aa8b732
AK		 4466
4467 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4468 continue;
432bd6cb
AK		 4469 if (wrmsr_safe(index, data_low, data_high) < 0)
4470 continue;
26bb0981
AK		 4471 vmx->guest_msrs[j].index = i;
4472 vmx->guest_msrs[j].data = 0;
d5696725 4473 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4474 ++vmx->nmsrs;
6aa8b732 4475 }
6aa8b732 4476
2961e876
GN		 4477
4478 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4479
4480 /* 22.2.1, 20.8.1 */
2961e876 4481 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4482
e00c8cf2 4483 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4484 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4485
4486 return 0;
4487}
4488
57f252f2 4489static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4490{
4491 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4492 struct msr_data apic_base_msr;
e00c8cf2 4493
7ffd92c5 4494 vmx->rmode.vm86_active = 0;
e00c8cf2 4495
3b86cd99
JK		 4496 vmx->soft_vnmi_blocked = 0;
4497
ad312c7c 4498 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4499 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4500 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4501 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4502 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4503 apic_base_msr.host_initiated = true;
4504 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4505
2fb92db1
AK		 4506 vmx_segment_cache_clear(vmx);
4507
5706be0d 4508 seg_setup(VCPU_SREG_CS);
66450a21 4509 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4510 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4511
4512 seg_setup(VCPU_SREG_DS);
4513 seg_setup(VCPU_SREG_ES);
4514 seg_setup(VCPU_SREG_FS);
4515 seg_setup(VCPU_SREG_GS);
4516 seg_setup(VCPU_SREG_SS);
4517
4518 vmcs_write16(GUEST_TR_SELECTOR, 0);
4519 vmcs_writel(GUEST_TR_BASE, 0);
4520 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4521 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4522
4523 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4524 vmcs_writel(GUEST_LDTR_BASE, 0);
4525 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4526 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4527
4528 vmcs_write32(GUEST_SYSENTER_CS, 0);
4529 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4530 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4531
4532 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4533 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4534
e00c8cf2
AK		 4535 vmcs_writel(GUEST_GDTR_BASE, 0);
4536 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4537
4538 vmcs_writel(GUEST_IDTR_BASE, 0);
4539 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4540
443381a8 4541 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4542 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4543 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4544
e00c8cf2
AK		 4545 /* Special registers */
4546 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4547
4548 setup_msrs(vmx);
4549
6aa8b732
AK		 4550 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4551
f78e0e2e
SY		 4552 if (cpu_has_vmx_tpr_shadow()) {
4553 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4554 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4555 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4556 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4557 vmcs_write32(TPR_THRESHOLD, 0);
4558 }
4559
4560 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4561 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4562 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4563
01e439be
YZ		 4564 if (vmx_vm_has_apicv(vcpu->kvm))
4565 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4566
2384d2b3
SY		 4567 if (vmx->vpid != 0)
4568 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4569
fa40052c 4570 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4571 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4572 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4573 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4574 vmx_fpu_activate(&vmx->vcpu);
4575 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4576
b9d762fa 4577 vpid_sync_context(vmx);
6aa8b732
AK		 4578}
4579
b6f1250e
NHE		 4580/*
4581 * In nested virtualization, check if L1 asked to exit on external interrupts.
4582 * For most existing hypervisors, this will always return true.
4583 */
4584static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4585{
4586 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4587 PIN_BASED_EXT_INTR_MASK;
4588}
4589
77b0f5d6
BD		 4590/*
4591 * In nested virtualization, check if L1 has set
4592 * VM_EXIT_ACK_INTR_ON_EXIT
4593 */
4594static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4595{
4596 return get_vmcs12(vcpu)->vm_exit_controls &
4597 VM_EXIT_ACK_INTR_ON_EXIT;
4598}
4599
ea8ceb83
JK		 4600static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4601{
4602 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4603 PIN_BASED_NMI_EXITING;
4604}
4605
c9a7953f 4606static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4607{
4608 u32 cpu_based_vm_exec_control;
730dca42 4609
3b86cd99
JK		 4610 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4611 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4612 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4613}
4614
c9a7953f 4615static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4616{
4617 u32 cpu_based_vm_exec_control;
4618
c9a7953f
JK		 4619 if (!cpu_has_virtual_nmis() ||
4620 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4621 enable_irq_window(vcpu);
4622 return;
4623 }
3b86cd99
JK		 4624
4625 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4626 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4627 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4628}
4629
66fd3f7f 4630static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4631{
9c8cba37 4632 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4633 uint32_t intr;
4634 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4635
229456fc 4636 trace_kvm_inj_virq(irq);
2714d1d3 4637
fa89a817 4638 ++vcpu->stat.irq_injections;
7ffd92c5 4639 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4640 int inc_eip = 0;
4641 if (vcpu->arch.interrupt.soft)
4642 inc_eip = vcpu->arch.event_exit_inst_len;
4643 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4644 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4645 return;
4646 }
66fd3f7f
GN		 4647 intr = irq | INTR_INFO_VALID_MASK;
4648 if (vcpu->arch.interrupt.soft) {
4649 intr |= INTR_TYPE_SOFT_INTR;
4650 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4651 vmx->vcpu.arch.event_exit_inst_len);
4652 } else
4653 intr |= INTR_TYPE_EXT_INTR;
4654 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4655}
4656
f08864b4
SY		 4657static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4658{
66a5a347
JK		 4659 struct vcpu_vmx *vmx = to_vmx(vcpu);
4660
0b6ac343
NHE		 4661 if (is_guest_mode(vcpu))
4662 return;
4663
3b86cd99
JK		 4664 if (!cpu_has_virtual_nmis()) {
4665 /*
4666 * Tracking the NMI-blocked state in software is built upon
4667 * finding the next open IRQ window. This, in turn, depends on
4668 * well-behaving guests: They have to keep IRQs disabled at
4669 * least as long as the NMI handler runs. Otherwise we may
4670 * cause NMI nesting, maybe breaking the guest. But as this is
4671 * highly unlikely, we can live with the residual risk.
4672 */
4673 vmx->soft_vnmi_blocked = 1;
4674 vmx->vnmi_blocked_time = 0;
4675 }
4676
487b391d 4677 ++vcpu->stat.nmi_injections;
9d58b931 4678 vmx->nmi_known_unmasked = false;
7ffd92c5 4679 if (vmx->rmode.vm86_active) {
71f9833b 4680 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4681 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4682 return;
4683 }
f08864b4
SY		 4684 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4685 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4686}
4687
3cfc3092
JK		 4688static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4689{
4690 if (!cpu_has_virtual_nmis())
4691 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4692 if (to_vmx(vcpu)->nmi_known_unmasked)
4693 return false;
c332c83a 4694 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4695}
4696
4697static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4698{
4699 struct vcpu_vmx *vmx = to_vmx(vcpu);
4700
4701 if (!cpu_has_virtual_nmis()) {
4702 if (vmx->soft_vnmi_blocked != masked) {
4703 vmx->soft_vnmi_blocked = masked;
4704 vmx->vnmi_blocked_time = 0;
4705 }
4706 } else {
9d58b931 4707 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4708 if (masked)
4709 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4710 GUEST_INTR_STATE_NMI);
4711 else
4712 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4713 GUEST_INTR_STATE_NMI);
4714 }
4715}
4716
2505dc9f
JK		 4717static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4718{
b6b8a145
JK		 4719 if (to_vmx(vcpu)->nested.nested_run_pending)
4720 return 0;
ea8ceb83 4721
2505dc9f
JK		 4722 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4723 return 0;
4724
4725 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4726 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4727 | GUEST_INTR_STATE_NMI));
4728}
4729
78646121
GN		 4730static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4731{
b6b8a145
JK		 4732 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4733 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4734 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4735 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4736}
4737
cbc94022
IE		 4738static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4739{
4740 int ret;
4741 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4742 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4743 .guest_phys_addr = addr,
4744 .memory_size = PAGE_SIZE * 3,
4745 .flags = 0,
4746 };
4747
47ae31e2 4748 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4749 if (ret)
4750 return ret;
bfc6d222 4751 kvm->arch.tss_addr = addr;
1f755a82 4752 return init_rmode_tss(kvm);
cbc94022
IE		 4753}
4754
0ca1b4f4 4755static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4756{
77ab6db0 4757 switch (vec) {
77ab6db0 4758 case BP_VECTOR:
c573cd22
JK		 4759 /*
4760 * Update instruction length as we may reinject the exception
4761 * from user space while in guest debugging mode.
4762 */
4763 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4764 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4765 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4766 return false;
4767 /* fall through */
4768 case DB_VECTOR:
4769 if (vcpu->guest_debug &
4770 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4771 return false;
d0bfb940
JK		 4772 /* fall through */
4773 case DE_VECTOR:
77ab6db0
JK		 4774 case OF_VECTOR:
4775 case BR_VECTOR:
4776 case UD_VECTOR:
4777 case DF_VECTOR:
4778 case SS_VECTOR:
4779 case GP_VECTOR:
4780 case MF_VECTOR:
0ca1b4f4
GN		 4781 return true;
4782 break;
77ab6db0 4783 }
0ca1b4f4
GN		 4784 return false;
4785}
4786
4787static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4788 int vec, u32 err_code)
4789{
4790 /*
4791 * Instruction with address size override prefix opcode 0x67
4792 * Cause the #SS fault with 0 error code in VM86 mode.
4793 */
4794 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4795 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4796 if (vcpu->arch.halt_request) {
4797 vcpu->arch.halt_request = 0;
4798 return kvm_emulate_halt(vcpu);
4799 }
4800 return 1;
4801 }
4802 return 0;
4803 }
4804
4805 /*
4806 * Forward all other exceptions that are valid in real mode.
4807 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4808 * the required debugging infrastructure rework.
4809 */
4810 kvm_queue_exception(vcpu, vec);
4811 return 1;
6aa8b732
AK		 4812}
4813
a0861c02
AK		 4814/*
4815 * Trigger machine check on the host. We assume all the MSRs are already set up
4816 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4817 * We pass a fake environment to the machine check handler because we want
4818 * the guest to be always treated like user space, no matter what context
4819 * it used internally.
4820 */
4821static void kvm_machine_check(void)
4822{
4823#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4824 struct pt_regs regs = {
4825 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4826 .flags = X86_EFLAGS_IF,
4827 };
4828
4829 do_machine_check(&regs, 0);
4830#endif
4831}
4832
851ba692 4833static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4834{
4835 /* already handled by vcpu_run */
4836 return 1;
4837}
4838
851ba692 4839static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4840{
1155f76a 4841 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4842 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4843 u32 intr_info, ex_no, error_code;
42dbaa5a 4844 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4845 u32 vect_info;
4846 enum emulation_result er;
4847
1155f76a 4848 vect_info = vmx->idt_vectoring_info;
88786475 4849 intr_info = vmx->exit_intr_info;
6aa8b732 4850
a0861c02 4851 if (is_machine_check(intr_info))
851ba692 4852 return handle_machine_check(vcpu);
a0861c02 4853
e4a41889 4854 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4855 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4856
4857 if (is_no_device(intr_info)) {
5fd86fcf 4858 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4859 return 1;
4860 }
4861
7aa81cc0 4862 if (is_invalid_opcode(intr_info)) {
51d8b661 4863 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4864 if (er != EMULATE_DONE)
7ee5d940 4865 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4866 return 1;
4867 }
4868
6aa8b732 4869 error_code = 0;
2e11384c 4870 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4871 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4872
4873 /*
4874 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4875 * MMIO, it is better to report an internal error.
4876 * See the comments in vmx_handle_exit.
4877 */
4878 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4879 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4880 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4881 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4882 vcpu->run->internal.ndata = 2;
4883 vcpu->run->internal.data[0] = vect_info;
4884 vcpu->run->internal.data[1] = intr_info;
4885 return 0;
4886 }
4887
6aa8b732 4888 if (is_page_fault(intr_info)) {
1439442c 4889 /* EPT won't cause page fault directly */
cf3ace79 4890 BUG_ON(enable_ept);
6aa8b732 4891 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4892 trace_kvm_page_fault(cr2, error_code);
4893
3298b75c 4894 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4895 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4896 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4897 }
4898
d0bfb940 4899 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4900
4901 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4902 return handle_rmode_exception(vcpu, ex_no, error_code);
4903
42dbaa5a
JK		 4904 switch (ex_no) {
4905 case DB_VECTOR:
4906 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4907 if (!(vcpu->guest_debug &
4908 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4909 vcpu->arch.dr6 &= ~15;
6f43ed01 4910 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4911 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4912 skip_emulated_instruction(vcpu);
4913
42dbaa5a
JK		 4914 kvm_queue_exception(vcpu, DB_VECTOR);
4915 return 1;
4916 }
4917 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4918 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4919 /* fall through */
4920 case BP_VECTOR:
c573cd22
JK		 4921 /*
4922 * Update instruction length as we may reinject #BP from
4923 * user space while in guest debugging mode. Reading it for
4924 * #DB as well causes no harm, it is not used in that case.
4925 */
4926 vmx->vcpu.arch.event_exit_inst_len =
4927 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4928 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4929 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4930 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4931 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4932 break;
4933 default:
d0bfb940
JK		 4934 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4935 kvm_run->ex.exception = ex_no;
4936 kvm_run->ex.error_code = error_code;
42dbaa5a 4937 break;
6aa8b732 4938 }
6aa8b732
AK		 4939 return 0;
4940}
4941
851ba692 4942static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4943{
1165f5fe 4944 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4945 return 1;
4946}
4947
851ba692 4948static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4949{
851ba692 4950 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4951 return 0;
4952}
6aa8b732 4953
851ba692 4954static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4955{
bfdaab09 4956 unsigned long exit_qualification;
34c33d16 4957 int size, in, string;
039576c0 4958 unsigned port;
6aa8b732 4959
bfdaab09 4960 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4961 string = (exit_qualification & 16) != 0;
cf8f70bf 4962 in = (exit_qualification & 8) != 0;
e70669ab 4963
cf8f70bf 4964 ++vcpu->stat.io_exits;
e70669ab 4965
cf8f70bf 4966 if (string || in)
51d8b661 4967 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4968
cf8f70bf
GN		 4969 port = exit_qualification >> 16;
4970 size = (exit_qualification & 7) + 1;
e93f36bc 4971 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4972
4973 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4974}
4975
102d8325
IM		 4976static void
4977vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4978{
4979 /*
4980 * Patch in the VMCALL instruction:
4981 */
4982 hypercall[0] = 0x0f;
4983 hypercall[1] = 0x01;
4984 hypercall[2] = 0xc1;
102d8325
IM		 4985}
4986
92fbc7b1
JK		 4987static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4988{
4989 unsigned long always_on = VMXON_CR0_ALWAYSON;
4990
4991 if (nested_vmx_secondary_ctls_high &
4992 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4993 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4994 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4995 return (val & always_on) == always_on;
4996}
4997
0fa06071 4998/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4999static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5000{
eeadf9e7 5001 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5002 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5003 unsigned long orig_val = val;
5004
eeadf9e7
NHE		 5005 /*
5006 * We get here when L2 changed cr0 in a way that did not change
5007 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5008 * but did change L0 shadowed bits. So we first calculate the
5009 * effective cr0 value that L1 would like to write into the
5010 * hardware. It consists of the L2-owned bits from the new
5011 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5012 */
1a0d74e6
JK		 5013 val = (val & ~vmcs12->cr0_guest_host_mask) |
5014 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5015
92fbc7b1 5016 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5017 return 1;
1a0d74e6
JK		 5018
5019 if (kvm_set_cr0(vcpu, val))
5020 return 1;
5021 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5022 return 0;
1a0d74e6
JK		 5023 } else {
5024 if (to_vmx(vcpu)->nested.vmxon &&
5025 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5026 return 1;
eeadf9e7 5027 return kvm_set_cr0(vcpu, val);
1a0d74e6 5028 }
eeadf9e7
NHE		 5029}
5030
5031static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5032{
5033 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5034 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5035 unsigned long orig_val = val;
5036
5037 /* analogously to handle_set_cr0 */
5038 val = (val & ~vmcs12->cr4_guest_host_mask) |
5039 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5040 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5041 return 1;
1a0d74e6 5042 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5043 return 0;
5044 } else
5045 return kvm_set_cr4(vcpu, val);
5046}
5047
5048/* called to set cr0 as approriate for clts instruction exit. */
5049static void handle_clts(struct kvm_vcpu *vcpu)
5050{
5051 if (is_guest_mode(vcpu)) {
5052 /*
5053 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5054 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5055 * just pretend it's off (also in arch.cr0 for fpu_activate).
5056 */
5057 vmcs_writel(CR0_READ_SHADOW,
5058 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5059 vcpu->arch.cr0 &= ~X86_CR0_TS;
5060 } else
5061 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5062}
5063
851ba692 5064static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5065{
229456fc 5066 unsigned long exit_qualification, val;
6aa8b732
AK		 5067 int cr;
5068 int reg;
49a9b07e 5069 int err;
6aa8b732 5070
bfdaab09 5071 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5072 cr = exit_qualification & 15;
5073 reg = (exit_qualification >> 8) & 15;
5074 switch ((exit_qualification >> 4) & 3) {
5075 case 0: /* mov to cr */
1e32c079 5076 val = kvm_register_readl(vcpu, reg);
229456fc 5077 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5078 switch (cr) {
5079 case 0:
eeadf9e7 5080 err = handle_set_cr0(vcpu, val);
db8fcefa 5081 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5082 return 1;
5083 case 3:
2390218b 5084 err = kvm_set_cr3(vcpu, val);
db8fcefa 5085 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5086 return 1;
5087 case 4:
eeadf9e7 5088 err = handle_set_cr4(vcpu, val);
db8fcefa 5089 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5090 return 1;
0a5fff19
GN		 5091 case 8: {
5092 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5093 u8 cr8 = (u8)val;
eea1cff9 5094 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5095 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5096 if (irqchip_in_kernel(vcpu->kvm))
5097 return 1;
5098 if (cr8_prev <= cr8)
5099 return 1;
851ba692 5100 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5101 return 0;
5102 }
4b8073e4 5103 }
6aa8b732 5104 break;
25c4c276 5105 case 2: /* clts */
eeadf9e7 5106 handle_clts(vcpu);
4d4ec087 5107 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5108 skip_emulated_instruction(vcpu);
6b52d186 5109 vmx_fpu_activate(vcpu);
25c4c276 5110 return 1;
6aa8b732
AK		 5111 case 1: /*mov from cr*/
5112 switch (cr) {
5113 case 3:
9f8fe504
AK		 5114 val = kvm_read_cr3(vcpu);
5115 kvm_register_write(vcpu, reg, val);
5116 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5117 skip_emulated_instruction(vcpu);
5118 return 1;
5119 case 8:
229456fc
MT		 5120 val = kvm_get_cr8(vcpu);
5121 kvm_register_write(vcpu, reg, val);
5122 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5123 skip_emulated_instruction(vcpu);
5124 return 1;
5125 }
5126 break;
5127 case 3: /* lmsw */
a1f83a74 5128 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5129 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5130 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5131
5132 skip_emulated_instruction(vcpu);
5133 return 1;
5134 default:
5135 break;
5136 }
851ba692 5137 vcpu->run->exit_reason = 0;
a737f256 5138 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5139 (int)(exit_qualification >> 4) & 3, cr);
5140 return 0;
5141}
5142
851ba692 5143static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5144{
bfdaab09 5145 unsigned long exit_qualification;
6aa8b732
AK		 5146 int dr, reg;
5147
f2483415 5148 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5149 if (!kvm_require_cpl(vcpu, 0))
5150 return 1;
42dbaa5a
JK		 5151 dr = vmcs_readl(GUEST_DR7);
5152 if (dr & DR7_GD) {
5153 /*
5154 * As the vm-exit takes precedence over the debug trap, we
5155 * need to emulate the latter, either for the host or the
5156 * guest debugging itself.
5157 */
5158 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5159 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5160 vcpu->run->debug.arch.dr7 = dr;
5161 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5162 vmcs_readl(GUEST_CS_BASE) +
5163 vmcs_readl(GUEST_RIP);
851ba692
AK		 5164 vcpu->run->debug.arch.exception = DB_VECTOR;
5165 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5166 return 0;
5167 } else {
5168 vcpu->arch.dr7 &= ~DR7_GD;
6f43ed01 5169 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5170 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5171 kvm_queue_exception(vcpu, DB_VECTOR);
5172 return 1;
5173 }
5174 }
5175
81908bf4
PB		 5176 if (vcpu->guest_debug == 0) {
5177 u32 cpu_based_vm_exec_control;
5178
5179 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5180 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5181 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5182
5183 /*
5184 * No more DR vmexits; force a reload of the debug registers
5185 * and reenter on this instruction. The next vmexit will
5186 * retrieve the full state of the debug registers.
5187 */
5188 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5189 return 1;
5190 }
5191
bfdaab09 5192 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5193 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5194 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5195 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5196 unsigned long val;
4c4d563b
JK		 5197
5198 if (kvm_get_dr(vcpu, dr, &val))
5199 return 1;
5200 kvm_register_write(vcpu, reg, val);
020df079 5201 } else
5777392e 5202 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5203 return 1;
5204
6aa8b732
AK		 5205 skip_emulated_instruction(vcpu);
5206 return 1;
5207}
5208
73aaf249
JK		 5209static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5210{
5211 return vcpu->arch.dr6;
5212}
5213
5214static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5215{
5216}
5217
81908bf4
PB		 5218static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5219{
5220 u32 cpu_based_vm_exec_control;
5221
5222 get_debugreg(vcpu->arch.db[0], 0);
5223 get_debugreg(vcpu->arch.db[1], 1);
5224 get_debugreg(vcpu->arch.db[2], 2);
5225 get_debugreg(vcpu->arch.db[3], 3);
5226 get_debugreg(vcpu->arch.dr6, 6);
5227 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5228
5229 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5230
5231 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5232 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5233 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5234}
5235
020df079
GN		 5236static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5237{
5238 vmcs_writel(GUEST_DR7, val);
5239}
5240
851ba692 5241static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5242{
06465c5a
AK		 5243 kvm_emulate_cpuid(vcpu);
5244 return 1;
6aa8b732
AK		 5245}
5246
851ba692 5247static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5248{
ad312c7c 5249 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5250 u64 data;
5251
5252 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5253 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5254 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5255 return 1;
5256 }
5257
229456fc 5258 trace_kvm_msr_read(ecx, data);
2714d1d3 5259
6aa8b732 5260 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5261 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5262 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5263 skip_emulated_instruction(vcpu);
5264 return 1;
5265}
5266
851ba692 5267static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5268{
8fe8ab46 5269 struct msr_data msr;
ad312c7c
ZX		 5270 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5271 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5272 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5273
8fe8ab46
WA		 5274 msr.data = data;
5275 msr.index = ecx;
5276 msr.host_initiated = false;
5277 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5278 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5279 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5280 return 1;
5281 }
5282
59200273 5283 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5284 skip_emulated_instruction(vcpu);
5285 return 1;
5286}
5287
851ba692 5288static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5289{
3842d135 5290 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5291 return 1;
5292}
5293
851ba692 5294static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5295{
85f455f7
ED		 5296 u32 cpu_based_vm_exec_control;
5297
5298 /* clear pending irq */
5299 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5300 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5301 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5302
3842d135
AK		 5303 kvm_make_request(KVM_REQ_EVENT, vcpu);
5304
a26bf12a 5305 ++vcpu->stat.irq_window_exits;
2714d1d3 5306
c1150d8c
DL		 5307 /*
5308 * If the user space waits to inject interrupts, exit as soon as
5309 * possible
5310 */
8061823a 5311 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5312 vcpu->run->request_interrupt_window &&
8061823a 5313 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5314 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5315 return 0;
5316 }
6aa8b732
AK		 5317 return 1;
5318}
5319
851ba692 5320static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5321{
5322 skip_emulated_instruction(vcpu);
d3bef15f 5323 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5324}
5325
851ba692 5326static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5327{
510043da 5328 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5329 kvm_emulate_hypercall(vcpu);
5330 return 1;
c21415e8
IM		 5331}
5332
ec25d5e6
GN		 5333static int handle_invd(struct kvm_vcpu *vcpu)
5334{
51d8b661 5335 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5336}
5337
851ba692 5338static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5339{
f9c617f6 5340 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5341
5342 kvm_mmu_invlpg(vcpu, exit_qualification);
5343 skip_emulated_instruction(vcpu);
5344 return 1;
5345}
5346
fee84b07
AK		 5347static int handle_rdpmc(struct kvm_vcpu *vcpu)
5348{
5349 int err;
5350
5351 err = kvm_rdpmc(vcpu);
5352 kvm_complete_insn_gp(vcpu, err);
5353
5354 return 1;
5355}
5356
851ba692 5357static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5358{
5359 skip_emulated_instruction(vcpu);
f5f48ee1 5360 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5361 return 1;
5362}
5363
2acf923e
DC		 5364static int handle_xsetbv(struct kvm_vcpu *vcpu)
5365{
5366 u64 new_bv = kvm_read_edx_eax(vcpu);
5367 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5368
5369 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5370 skip_emulated_instruction(vcpu);
5371 return 1;
5372}
5373
851ba692 5374static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5375{
58fbbf26
KT		 5376 if (likely(fasteoi)) {
5377 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5378 int access_type, offset;
5379
5380 access_type = exit_qualification & APIC_ACCESS_TYPE;
5381 offset = exit_qualification & APIC_ACCESS_OFFSET;
5382 /*
5383 * Sane guest uses MOV to write EOI, with written value
5384 * not cared. So make a short-circuit here by avoiding
5385 * heavy instruction emulation.
5386 */
5387 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5388 (offset == APIC_EOI)) {
5389 kvm_lapic_set_eoi(vcpu);
5390 skip_emulated_instruction(vcpu);
5391 return 1;
5392 }
5393 }
51d8b661 5394 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5395}
5396
c7c9c56c
YZ		 5397static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5398{
5399 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5400 int vector = exit_qualification & 0xff;
5401
5402 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5403 kvm_apic_set_eoi_accelerated(vcpu, vector);
5404 return 1;
5405}
5406
83d4c286
YZ		 5407static int handle_apic_write(struct kvm_vcpu *vcpu)
5408{
5409 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5410 u32 offset = exit_qualification & 0xfff;
5411
5412 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5413 kvm_apic_write_nodecode(vcpu, offset);
5414 return 1;
5415}
5416
851ba692 5417static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5418{
60637aac 5419 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5420 unsigned long exit_qualification;
e269fb21
JK		 5421 bool has_error_code = false;
5422 u32 error_code = 0;
37817f29 5423 u16 tss_selector;
7f3d35fd 5424 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5425
5426 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5427 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5428 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5429
5430 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5431
5432 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5433 if (reason == TASK_SWITCH_GATE && idt_v) {
5434 switch (type) {
5435 case INTR_TYPE_NMI_INTR:
5436 vcpu->arch.nmi_injected = false;
654f06fc 5437 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5438 break;
5439 case INTR_TYPE_EXT_INTR:
66fd3f7f 5440 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5441 kvm_clear_interrupt_queue(vcpu);
5442 break;
5443 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5444 if (vmx->idt_vectoring_info &
5445 VECTORING_INFO_DELIVER_CODE_MASK) {
5446 has_error_code = true;
5447 error_code =
5448 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5449 }
5450 /* fall through */
64a7ec06
GN		 5451 case INTR_TYPE_SOFT_EXCEPTION:
5452 kvm_clear_exception_queue(vcpu);
5453 break;
5454 default:
5455 break;
5456 }
60637aac 5457 }
37817f29
IE		 5458 tss_selector = exit_qualification;
5459
64a7ec06
GN		 5460 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5461 type != INTR_TYPE_EXT_INTR &&
5462 type != INTR_TYPE_NMI_INTR))
5463 skip_emulated_instruction(vcpu);
5464
7f3d35fd
KW		 5465 if (kvm_task_switch(vcpu, tss_selector,
5466 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5467 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5468 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5469 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5470 vcpu->run->internal.ndata = 0;
42dbaa5a 5471 return 0;
acb54517 5472 }
42dbaa5a
JK		 5473
5474 /* clear all local breakpoint enable flags */
1f854112 5475 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5476
5477 /*
5478 * TODO: What about debug traps on tss switch?
5479 * Are we supposed to inject them and update dr6?
5480 */
5481
5482 return 1;
37817f29
IE		 5483}
5484
851ba692 5485static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5486{
f9c617f6 5487 unsigned long exit_qualification;
1439442c 5488 gpa_t gpa;
4f5982a5 5489 u32 error_code;
1439442c 5490 int gla_validity;
1439442c 5491
f9c617f6 5492 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5493
1439442c
SY		 5494 gla_validity = (exit_qualification >> 7) & 0x3;
5495 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5496 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5497 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5498 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5499 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5500 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5501 (long unsigned int)exit_qualification);
851ba692
AK		 5502 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5503 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5504 return 0;
1439442c
SY		 5505 }
5506
0be9c7a8
GN		 5507 /*
5508 * EPT violation happened while executing iret from NMI,
5509 * "blocked by NMI" bit has to be set before next VM entry.
5510 * There are errata that may cause this bit to not be set:
5511 * AAK134, BY25.
5512 */
bcd1c294
GN		 5513 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5514 cpu_has_virtual_nmis() &&
5515 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5516 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5517
1439442c 5518 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5519 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5520
5521 /* It is a write fault? */
5522 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5523 /* It is a fetch fault? */
5524 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5525 /* ept page table is present? */
5526 error_code |= (exit_qualification >> 3) & 0x1;
5527
25d92081
YZ		 5528 vcpu->arch.exit_qualification = exit_qualification;
5529
4f5982a5 5530 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5531}
5532
68f89400
MT		 5533static u64 ept_rsvd_mask(u64 spte, int level)
5534{
5535 int i;
5536 u64 mask = 0;
5537
5538 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5539 mask |= (1ULL << i);
5540
a32e8459 5541 if (level == 4)
68f89400
MT		 5542 /* bits 7:3 reserved */
5543 mask |= 0xf8;
a32e8459
WL		 5544 else if (spte & (1ULL << 7))
5545 /*
5546 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5547 * level == 1 if the hypervisor is using the ignored bit 7.
5548 */
5549 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5550 else if (level > 1)
5551 /* bits 6:3 reserved */
5552 mask |= 0x78;
68f89400
MT		 5553
5554 return mask;
5555}
5556
5557static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5558 int level)
5559{
5560 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5561
5562 /* 010b (write-only) */
5563 WARN_ON((spte & 0x7) == 0x2);
5564
5565 /* 110b (write/execute) */
5566 WARN_ON((spte & 0x7) == 0x6);
5567
5568 /* 100b (execute-only) and value not supported by logical processor */
5569 if (!cpu_has_vmx_ept_execute_only())
5570 WARN_ON((spte & 0x7) == 0x4);
5571
5572 /* not 000b */
5573 if ((spte & 0x7)) {
5574 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5575
5576 if (rsvd_bits != 0) {
5577 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5578 __func__, rsvd_bits);
5579 WARN_ON(1);
5580 }
5581
a32e8459
WL		 5582 /* bits 5:3 are _not_ reserved for large page or leaf page */
5583 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5584 u64 ept_mem_type = (spte & 0x38) >> 3;
5585
5586 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5587 ept_mem_type == 7) {
5588 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5589 __func__, ept_mem_type);
5590 WARN_ON(1);
5591 }
5592 }
5593 }
5594}
5595
851ba692 5596static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5597{
5598 u64 sptes[4];
ce88decf 5599 int nr_sptes, i, ret;
68f89400
MT		 5600 gpa_t gpa;
5601
5602 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5603 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5604 skip_emulated_instruction(vcpu);
5605 return 1;
5606 }
68f89400 5607
ce88decf 5608 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5609 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5610 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5611 EMULATE_DONE;
f8f55942
XG		 5612
5613 if (unlikely(ret == RET_MMIO_PF_INVALID))
5614 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5615
b37fbea6 5616 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5617 return 1;
5618
5619 /* It is the real ept misconfig */
68f89400
MT		 5620 printk(KERN_ERR "EPT: Misconfiguration.\n");
5621 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5622
5623 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5624
5625 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5626 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5627
851ba692
AK		 5628 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5629 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5630
5631 return 0;
5632}
5633
851ba692 5634static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5635{
5636 u32 cpu_based_vm_exec_control;
5637
5638 /* clear pending NMI */
5639 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5640 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5641 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5642 ++vcpu->stat.nmi_window_exits;
3842d135 5643 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5644
5645 return 1;
5646}
5647
80ced186 5648static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5649{
8b3079a5
AK		 5650 struct vcpu_vmx *vmx = to_vmx(vcpu);
5651 enum emulation_result err = EMULATE_DONE;
80ced186 5652 int ret = 1;
49e9d557
AK		 5653 u32 cpu_exec_ctrl;
5654 bool intr_window_requested;
b8405c18 5655 unsigned count = 130;
49e9d557
AK		 5656
5657 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5658 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5659
98eb2f8b 5660 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5661 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5662 return handle_interrupt_window(&vmx->vcpu);
5663
de87dcdd
AK		 5664 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5665 return 1;
5666
991eebf9 5667 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5668
ac0a48c3 5669 if (err == EMULATE_USER_EXIT) {
94452b9e 5670 ++vcpu->stat.mmio_exits;
80ced186
MG		 5671 ret = 0;
5672 goto out;
5673 }
1d5a4d9b 5674
de5f70e0
AK		 5675 if (err != EMULATE_DONE) {
5676 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5677 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5678 vcpu->run->internal.ndata = 0;
6d77dbfc 5679 return 0;
de5f70e0 5680 }
ea953ef0 5681
8d76c49e
GN		 5682 if (vcpu->arch.halt_request) {
5683 vcpu->arch.halt_request = 0;
5684 ret = kvm_emulate_halt(vcpu);
5685 goto out;
5686 }
5687
ea953ef0 5688 if (signal_pending(current))
80ced186 5689 goto out;
ea953ef0
MG		 5690 if (need_resched())
5691 schedule();
5692 }
5693
80ced186
MG		 5694out:
5695 return ret;
ea953ef0
MG		 5696}
5697
b4a2d31d
RK		 5698static int __grow_ple_window(int val)
5699{
5700 if (ple_window_grow < 1)
5701 return ple_window;
5702
5703 val = min(val, ple_window_actual_max);
5704
5705 if (ple_window_grow < ple_window)
5706 val *= ple_window_grow;
5707 else
5708 val += ple_window_grow;
5709
5710 return val;
5711}
5712
5713static int __shrink_ple_window(int val, int modifier, int minimum)
5714{
5715 if (modifier < 1)
5716 return ple_window;
5717
5718 if (modifier < ple_window)
5719 val /= modifier;
5720 else
5721 val -= modifier;
5722
5723 return max(val, minimum);
5724}
5725
5726static void grow_ple_window(struct kvm_vcpu *vcpu)
5727{
5728 struct vcpu_vmx *vmx = to_vmx(vcpu);
5729 int old = vmx->ple_window;
5730
5731 vmx->ple_window = __grow_ple_window(old);
5732
5733 if (vmx->ple_window != old)
5734 vmx->ple_window_dirty = true;
7b46268d
RK		 5735
5736 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5737}
5738
5739static void shrink_ple_window(struct kvm_vcpu *vcpu)
5740{
5741 struct vcpu_vmx *vmx = to_vmx(vcpu);
5742 int old = vmx->ple_window;
5743
5744 vmx->ple_window = __shrink_ple_window(old,
5745 ple_window_shrink, ple_window);
5746
5747 if (vmx->ple_window != old)
5748 vmx->ple_window_dirty = true;
7b46268d
RK		 5749
5750 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5751}
5752
5753/*
5754 * ple_window_actual_max is computed to be one grow_ple_window() below
5755 * ple_window_max. (See __grow_ple_window for the reason.)
5756 * This prevents overflows, because ple_window_max is int.
5757 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5758 * this process.
5759 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5760 */
5761static void update_ple_window_actual_max(void)
5762{
5763 ple_window_actual_max =
5764 __shrink_ple_window(max(ple_window_max, ple_window),
5765 ple_window_grow, INT_MIN);
5766}
5767
4b8d54f9
ZE		 5768/*
5769 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5770 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5771 */
9fb41ba8 5772static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5773{
b4a2d31d
RK		 5774 if (ple_gap)
5775 grow_ple_window(vcpu);
5776
4b8d54f9
ZE		 5777 skip_emulated_instruction(vcpu);
5778 kvm_vcpu_on_spin(vcpu);
5779
5780 return 1;
5781}
5782
87c00572 5783static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5784{
87c00572 5785 skip_emulated_instruction(vcpu);
59708670
SY		 5786 return 1;
5787}
5788
87c00572
GS		 5789static int handle_mwait(struct kvm_vcpu *vcpu)
5790{
5791 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5792 return handle_nop(vcpu);
5793}
5794
5795static int handle_monitor(struct kvm_vcpu *vcpu)
5796{
5797 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5798 return handle_nop(vcpu);
5799}
5800
ff2f6fe9
NHE		 5801/*
5802 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5803 * We could reuse a single VMCS for all the L2 guests, but we also want the
5804 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5805 * allows keeping them loaded on the processor, and in the future will allow
5806 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5807 * every entry if they never change.
5808 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5809 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5810 *
5811 * The following functions allocate and free a vmcs02 in this pool.
5812 */
5813
5814/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5815static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5816{
5817 struct vmcs02_list *item;
5818 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5819 if (item->vmptr == vmx->nested.current_vmptr) {
5820 list_move(&item->list, &vmx->nested.vmcs02_pool);
5821 return &item->vmcs02;
5822 }
5823
5824 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5825 /* Recycle the least recently used VMCS. */
5826 item = list_entry(vmx->nested.vmcs02_pool.prev,
5827 struct vmcs02_list, list);
5828 item->vmptr = vmx->nested.current_vmptr;
5829 list_move(&item->list, &vmx->nested.vmcs02_pool);
5830 return &item->vmcs02;
5831 }
5832
5833 /* Create a new VMCS */
0fa24ce3 5834 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5835 if (!item)
5836 return NULL;
5837 item->vmcs02.vmcs = alloc_vmcs();
5838 if (!item->vmcs02.vmcs) {
5839 kfree(item);
5840 return NULL;
5841 }
5842 loaded_vmcs_init(&item->vmcs02);
5843 item->vmptr = vmx->nested.current_vmptr;
5844 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5845 vmx->nested.vmcs02_num++;
5846 return &item->vmcs02;
5847}
5848
5849/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5850static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5851{
5852 struct vmcs02_list *item;
5853 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5854 if (item->vmptr == vmptr) {
5855 free_loaded_vmcs(&item->vmcs02);
5856 list_del(&item->list);
5857 kfree(item);
5858 vmx->nested.vmcs02_num--;
5859 return;
5860 }
5861}
5862
5863/*
5864 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 5865 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5866 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 5867 */
5868static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5869{
5870 struct vmcs02_list *item, *n;
4fa7734c
PB		 5871
5872 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 5873 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 5874 /*
5875 * Something will leak if the above WARN triggers. Better than
5876 * a use-after-free.
5877 */
5878 if (vmx->loaded_vmcs == &item->vmcs02)
5879 continue;
5880
5881 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 5882 list_del(&item->list);
5883 kfree(item);
4fa7734c 5884 vmx->nested.vmcs02_num--;
ff2f6fe9 5885 }
ff2f6fe9
NHE		 5886}
5887
0658fbaa
ACL		 5888/*
5889 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5890 * set the success or error code of an emulated VMX instruction, as specified
5891 * by Vol 2B, VMX Instruction Reference, "Conventions".
5892 */
5893static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5894{
5895 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5896 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5897 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5898}
5899
5900static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5901{
5902 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5903 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5904 X86_EFLAGS_SF | X86_EFLAGS_OF))
5905 | X86_EFLAGS_CF);
5906}
5907
145c28dd 5908static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5909 u32 vm_instruction_error)
5910{
5911 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5912 /*
5913 * failValid writes the error number to the current VMCS, which
5914 * can't be done there isn't a current VMCS.
5915 */
5916 nested_vmx_failInvalid(vcpu);
5917 return;
5918 }
5919 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5920 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5921 X86_EFLAGS_SF | X86_EFLAGS_OF))
5922 | X86_EFLAGS_ZF);
5923 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5924 /*
5925 * We don't need to force a shadow sync because
5926 * VM_INSTRUCTION_ERROR is not shadowed
5927 */
5928}
145c28dd 5929
f4124500
JK		 5930static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5931{
5932 struct vcpu_vmx *vmx =
5933 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5934
5935 vmx->nested.preemption_timer_expired = true;
5936 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5937 kvm_vcpu_kick(&vmx->vcpu);
5938
5939 return HRTIMER_NORESTART;
5940}
5941
19677e32
BD		 5942/*
5943 * Decode the memory-address operand of a vmx instruction, as recorded on an
5944 * exit caused by such an instruction (run by a guest hypervisor).
5945 * On success, returns 0. When the operand is invalid, returns 1 and throws
5946 * #UD or #GP.
5947 */
5948static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5949 unsigned long exit_qualification,
5950 u32 vmx_instruction_info, gva_t *ret)
5951{
5952 /*
5953 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5954 * Execution", on an exit, vmx_instruction_info holds most of the
5955 * addressing components of the operand. Only the displacement part
5956 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5957 * For how an actual address is calculated from all these components,
5958 * refer to Vol. 1, "Operand Addressing".
5959 */
5960 int scaling = vmx_instruction_info & 3;
5961 int addr_size = (vmx_instruction_info >> 7) & 7;
5962 bool is_reg = vmx_instruction_info & (1u << 10);
5963 int seg_reg = (vmx_instruction_info >> 15) & 7;
5964 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5965 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5966 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5967 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5968
5969 if (is_reg) {
5970 kvm_queue_exception(vcpu, UD_VECTOR);
5971 return 1;
5972 }
5973
5974 /* Addr = segment_base + offset */
5975 /* offset = base + [index * scale] + displacement */
5976 *ret = vmx_get_segment_base(vcpu, seg_reg);
5977 if (base_is_valid)
5978 *ret += kvm_register_read(vcpu, base_reg);
5979 if (index_is_valid)
5980 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5981 *ret += exit_qualification; /* holds the displacement */
5982
5983 if (addr_size == 1) /* 32 bit */
5984 *ret &= 0xffffffff;
5985
5986 /*
5987 * TODO: throw #GP (and return 1) in various cases that the VM*
5988 * instructions require it - e.g., offset beyond segment limit,
5989 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5990 * address, and so on. Currently these are not checked.
5991 */
5992 return 0;
5993}
5994
3573e22c
BD		 5995/*
5996 * This function performs the various checks including
5997 * - if it's 4KB aligned
5998 * - No bits beyond the physical address width are set
5999 * - Returns 0 on success or else 1
4291b588 6000 * (Intel SDM Section 30.3)
3573e22c 6001 */
4291b588
BD		 6002static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6003 gpa_t *vmpointer)
3573e22c
BD		 6004{
6005 gva_t gva;
6006 gpa_t vmptr;
6007 struct x86_exception e;
6008 struct page *page;
6009 struct vcpu_vmx *vmx = to_vmx(vcpu);
6010 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6011
6012 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6013 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6014 return 1;
6015
6016 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6017 sizeof(vmptr), &e)) {
6018 kvm_inject_page_fault(vcpu, &e);
6019 return 1;
6020 }
6021
6022 switch (exit_reason) {
6023 case EXIT_REASON_VMON:
6024 /*
6025 * SDM 3: 24.11.5
6026 * The first 4 bytes of VMXON region contain the supported
6027 * VMCS revision identifier
6028 *
6029 * Note - IA32_VMX_BASIC[48] will never be 1
6030 * for the nested case;
6031 * which replaces physical address width with 32
6032 *
6033 */
bc39c4db 6034 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6035 nested_vmx_failInvalid(vcpu);
6036 skip_emulated_instruction(vcpu);
6037 return 1;
6038 }
6039
6040 page = nested_get_page(vcpu, vmptr);
6041 if (page == NULL ||
6042 *(u32 *)kmap(page) != VMCS12_REVISION) {
6043 nested_vmx_failInvalid(vcpu);
6044 kunmap(page);
6045 skip_emulated_instruction(vcpu);
6046 return 1;
6047 }
6048 kunmap(page);
6049 vmx->nested.vmxon_ptr = vmptr;
6050 break;
4291b588 6051 case EXIT_REASON_VMCLEAR:
bc39c4db 6052 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6053 nested_vmx_failValid(vcpu,
6054 VMXERR_VMCLEAR_INVALID_ADDRESS);
6055 skip_emulated_instruction(vcpu);
6056 return 1;
6057 }
6058
6059 if (vmptr == vmx->nested.vmxon_ptr) {
6060 nested_vmx_failValid(vcpu,
6061 VMXERR_VMCLEAR_VMXON_POINTER);
6062 skip_emulated_instruction(vcpu);
6063 return 1;
6064 }
6065 break;
6066 case EXIT_REASON_VMPTRLD:
bc39c4db 6067 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6068 nested_vmx_failValid(vcpu,
6069 VMXERR_VMPTRLD_INVALID_ADDRESS);
6070 skip_emulated_instruction(vcpu);
6071 return 1;
6072 }
3573e22c 6073
4291b588
BD		 6074 if (vmptr == vmx->nested.vmxon_ptr) {
6075 nested_vmx_failValid(vcpu,
6076 VMXERR_VMCLEAR_VMXON_POINTER);
6077 skip_emulated_instruction(vcpu);
6078 return 1;
6079 }
6080 break;
3573e22c
BD		 6081 default:
6082 return 1; /* shouldn't happen */
6083 }
6084
4291b588
BD		 6085 if (vmpointer)
6086 *vmpointer = vmptr;
3573e22c
BD		 6087 return 0;
6088}
6089
ec378aee
NHE		 6090/*
6091 * Emulate the VMXON instruction.
6092 * Currently, we just remember that VMX is active, and do not save or even
6093 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6094 * do not currently need to store anything in that guest-allocated memory
6095 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6096 * argument is different from the VMXON pointer (which the spec says they do).
6097 */
6098static int handle_vmon(struct kvm_vcpu *vcpu)
6099{
6100 struct kvm_segment cs;
6101 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6102 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6103 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6104 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6105
6106 /* The Intel VMX Instruction Reference lists a bunch of bits that
6107 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6108 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6109 * Otherwise, we should fail with #UD. We test these now:
6110 */
6111 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6112 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6113 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6114 kvm_queue_exception(vcpu, UD_VECTOR);
6115 return 1;
6116 }
6117
6118 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6119 if (is_long_mode(vcpu) && !cs.l) {
6120 kvm_queue_exception(vcpu, UD_VECTOR);
6121 return 1;
6122 }
6123
6124 if (vmx_get_cpl(vcpu)) {
6125 kvm_inject_gp(vcpu, 0);
6126 return 1;
6127 }
3573e22c 6128
4291b588 6129 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6130 return 1;
6131
145c28dd
AG		 6132 if (vmx->nested.vmxon) {
6133 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6134 skip_emulated_instruction(vcpu);
6135 return 1;
6136 }
b3897a49
NHE		 6137
6138 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6139 != VMXON_NEEDED_FEATURES) {
6140 kvm_inject_gp(vcpu, 0);
6141 return 1;
6142 }
6143
8de48833
AG		 6144 if (enable_shadow_vmcs) {
6145 shadow_vmcs = alloc_vmcs();
6146 if (!shadow_vmcs)
6147 return -ENOMEM;
6148 /* mark vmcs as shadow */
6149 shadow_vmcs->revision_id |= (1u << 31);
6150 /* init shadow vmcs */
6151 vmcs_clear(shadow_vmcs);
6152 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6153 }
ec378aee 6154
ff2f6fe9
NHE		 6155 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6156 vmx->nested.vmcs02_num = 0;
6157
f4124500
JK		 6158 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6159 HRTIMER_MODE_REL);
6160 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6161
ec378aee
NHE		 6162 vmx->nested.vmxon = true;
6163
6164 skip_emulated_instruction(vcpu);
a25eb114 6165 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6166 return 1;
6167}
6168
6169/*
6170 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6171 * for running VMX instructions (except VMXON, whose prerequisites are
6172 * slightly different). It also specifies what exception to inject otherwise.
6173 */
6174static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6175{
6176 struct kvm_segment cs;
6177 struct vcpu_vmx *vmx = to_vmx(vcpu);
6178
6179 if (!vmx->nested.vmxon) {
6180 kvm_queue_exception(vcpu, UD_VECTOR);
6181 return 0;
6182 }
6183
6184 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6185 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6186 (is_long_mode(vcpu) && !cs.l)) {
6187 kvm_queue_exception(vcpu, UD_VECTOR);
6188 return 0;
6189 }
6190
6191 if (vmx_get_cpl(vcpu)) {
6192 kvm_inject_gp(vcpu, 0);
6193 return 0;
6194 }
6195
6196 return 1;
6197}
6198
e7953d7f
AG		 6199static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6200{
8a1b9dd0 6201 u32 exec_control;
9a2a05b9
PB		 6202 if (vmx->nested.current_vmptr == -1ull)
6203 return;
6204
6205 /* current_vmptr and current_vmcs12 are always set/reset together */
6206 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6207 return;
6208
012f83cb 6209 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6210 /* copy to memory all shadowed fields in case
6211 they were modified */
6212 copy_shadow_to_vmcs12(vmx);
6213 vmx->nested.sync_shadow_vmcs = false;
6214 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6215 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6216 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6217 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6218 }
e7953d7f
AG		 6219 kunmap(vmx->nested.current_vmcs12_page);
6220 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6221 vmx->nested.current_vmptr = -1ull;
6222 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6223}
6224
ec378aee
NHE		 6225/*
6226 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6227 * just stops using VMX.
6228 */
6229static void free_nested(struct vcpu_vmx *vmx)
6230{
6231 if (!vmx->nested.vmxon)
6232 return;
9a2a05b9 6233
ec378aee 6234 vmx->nested.vmxon = false;
9a2a05b9 6235 nested_release_vmcs12(vmx);
e7953d7f
AG		 6236 if (enable_shadow_vmcs)
6237 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6238 /* Unpin physical memory we referred to in current vmcs02 */
6239 if (vmx->nested.apic_access_page) {
6240 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6241 vmx->nested.apic_access_page = NULL;
fe3ef05c 6242 }
a7c0b07d
WL		 6243 if (vmx->nested.virtual_apic_page) {
6244 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6245 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6246 }
ff2f6fe9
NHE		 6247
6248 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6249}
6250
6251/* Emulate the VMXOFF instruction */
6252static int handle_vmoff(struct kvm_vcpu *vcpu)
6253{
6254 if (!nested_vmx_check_permission(vcpu))
6255 return 1;
6256 free_nested(to_vmx(vcpu));
6257 skip_emulated_instruction(vcpu);
a25eb114 6258 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6259 return 1;
6260}
6261
27d6c865
NHE		 6262/* Emulate the VMCLEAR instruction */
6263static int handle_vmclear(struct kvm_vcpu *vcpu)
6264{
6265 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6266 gpa_t vmptr;
6267 struct vmcs12 *vmcs12;
6268 struct page *page;
27d6c865
NHE		 6269
6270 if (!nested_vmx_check_permission(vcpu))
6271 return 1;
6272
4291b588 6273 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6274 return 1;
27d6c865 6275
9a2a05b9 6276 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6277 nested_release_vmcs12(vmx);
27d6c865
NHE		 6278
6279 page = nested_get_page(vcpu, vmptr);
6280 if (page == NULL) {
6281 /*
6282 * For accurate processor emulation, VMCLEAR beyond available
6283 * physical memory should do nothing at all. However, it is
6284 * possible that a nested vmx bug, not a guest hypervisor bug,
6285 * resulted in this case, so let's shut down before doing any
6286 * more damage:
6287 */
6288 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6289 return 1;
6290 }
6291 vmcs12 = kmap(page);
6292 vmcs12->launch_state = 0;
6293 kunmap(page);
6294 nested_release_page(page);
6295
6296 nested_free_vmcs02(vmx, vmptr);
6297
6298 skip_emulated_instruction(vcpu);
6299 nested_vmx_succeed(vcpu);
6300 return 1;
6301}
6302
cd232ad0
NHE		 6303static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6304
6305/* Emulate the VMLAUNCH instruction */
6306static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6307{
6308 return nested_vmx_run(vcpu, true);
6309}
6310
6311/* Emulate the VMRESUME instruction */
6312static int handle_vmresume(struct kvm_vcpu *vcpu)
6313{
6314
6315 return nested_vmx_run(vcpu, false);
6316}
6317
49f705c5
NHE		 6318enum vmcs_field_type {
6319 VMCS_FIELD_TYPE_U16 = 0,
6320 VMCS_FIELD_TYPE_U64 = 1,
6321 VMCS_FIELD_TYPE_U32 = 2,
6322 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6323};
6324
6325static inline int vmcs_field_type(unsigned long field)
6326{
6327 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6328 return VMCS_FIELD_TYPE_U32;
6329 return (field >> 13) & 0x3 ;
6330}
6331
6332static inline int vmcs_field_readonly(unsigned long field)
6333{
6334 return (((field >> 10) & 0x3) == 1);
6335}
6336
6337/*
6338 * Read a vmcs12 field. Since these can have varying lengths and we return
6339 * one type, we chose the biggest type (u64) and zero-extend the return value
6340 * to that size. Note that the caller, handle_vmread, might need to use only
6341 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6342 * 64-bit fields are to be returned).
6343 */
6344static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6345 unsigned long field, u64 *ret)
6346{
6347 short offset = vmcs_field_to_offset(field);
6348 char *p;
6349
6350 if (offset < 0)
6351 return 0;
6352
6353 p = ((char *)(get_vmcs12(vcpu))) + offset;
6354
6355 switch (vmcs_field_type(field)) {
6356 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6357 *ret = *((natural_width *)p);
6358 return 1;
6359 case VMCS_FIELD_TYPE_U16:
6360 *ret = *((u16 *)p);
6361 return 1;
6362 case VMCS_FIELD_TYPE_U32:
6363 *ret = *((u32 *)p);
6364 return 1;
6365 case VMCS_FIELD_TYPE_U64:
6366 *ret = *((u64 *)p);
6367 return 1;
6368 default:
6369 return 0; /* can never happen. */
6370 }
6371}
6372
20b97fea
AG		 6373
6374static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6375 unsigned long field, u64 field_value){
6376 short offset = vmcs_field_to_offset(field);
6377 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6378 if (offset < 0)
6379 return false;
6380
6381 switch (vmcs_field_type(field)) {
6382 case VMCS_FIELD_TYPE_U16:
6383 *(u16 *)p = field_value;
6384 return true;
6385 case VMCS_FIELD_TYPE_U32:
6386 *(u32 *)p = field_value;
6387 return true;
6388 case VMCS_FIELD_TYPE_U64:
6389 *(u64 *)p = field_value;
6390 return true;
6391 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6392 *(natural_width *)p = field_value;
6393 return true;
6394 default:
6395 return false; /* can never happen. */
6396 }
6397
6398}
6399
16f5b903
AG		 6400static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6401{
6402 int i;
6403 unsigned long field;
6404 u64 field_value;
6405 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6406 const unsigned long *fields = shadow_read_write_fields;
6407 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6408
6409 vmcs_load(shadow_vmcs);
6410
6411 for (i = 0; i < num_fields; i++) {
6412 field = fields[i];
6413 switch (vmcs_field_type(field)) {
6414 case VMCS_FIELD_TYPE_U16:
6415 field_value = vmcs_read16(field);
6416 break;
6417 case VMCS_FIELD_TYPE_U32:
6418 field_value = vmcs_read32(field);
6419 break;
6420 case VMCS_FIELD_TYPE_U64:
6421 field_value = vmcs_read64(field);
6422 break;
6423 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6424 field_value = vmcs_readl(field);
6425 break;
6426 }
6427 vmcs12_write_any(&vmx->vcpu, field, field_value);
6428 }
6429
6430 vmcs_clear(shadow_vmcs);
6431 vmcs_load(vmx->loaded_vmcs->vmcs);
6432}
6433
c3114420
AG		 6434static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6435{
c2bae893
MK		 6436 const unsigned long *fields[] = {
6437 shadow_read_write_fields,
6438 shadow_read_only_fields
c3114420 6439 };
c2bae893 6440 const int max_fields[] = {
c3114420
AG		 6441 max_shadow_read_write_fields,
6442 max_shadow_read_only_fields
6443 };
6444 int i, q;
6445 unsigned long field;
6446 u64 field_value = 0;
6447 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6448
6449 vmcs_load(shadow_vmcs);
6450
c2bae893 6451 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6452 for (i = 0; i < max_fields[q]; i++) {
6453 field = fields[q][i];
6454 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6455
6456 switch (vmcs_field_type(field)) {
6457 case VMCS_FIELD_TYPE_U16:
6458 vmcs_write16(field, (u16)field_value);
6459 break;
6460 case VMCS_FIELD_TYPE_U32:
6461 vmcs_write32(field, (u32)field_value);
6462 break;
6463 case VMCS_FIELD_TYPE_U64:
6464 vmcs_write64(field, (u64)field_value);
6465 break;
6466 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6467 vmcs_writel(field, (long)field_value);
6468 break;
6469 }
6470 }
6471 }
6472
6473 vmcs_clear(shadow_vmcs);
6474 vmcs_load(vmx->loaded_vmcs->vmcs);
6475}
6476
49f705c5
NHE		 6477/*
6478 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6479 * used before) all generate the same failure when it is missing.
6480 */
6481static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6482{
6483 struct vcpu_vmx *vmx = to_vmx(vcpu);
6484 if (vmx->nested.current_vmptr == -1ull) {
6485 nested_vmx_failInvalid(vcpu);
6486 skip_emulated_instruction(vcpu);
6487 return 0;
6488 }
6489 return 1;
6490}
6491
6492static int handle_vmread(struct kvm_vcpu *vcpu)
6493{
6494 unsigned long field;
6495 u64 field_value;
6496 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6497 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6498 gva_t gva = 0;
6499
6500 if (!nested_vmx_check_permission(vcpu) ||
6501 !nested_vmx_check_vmcs12(vcpu))
6502 return 1;
6503
6504 /* Decode instruction info and find the field to read */
27e6fb5d 6505 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6506 /* Read the field, zero-extended to a u64 field_value */
6507 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6508 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6509 skip_emulated_instruction(vcpu);
6510 return 1;
6511 }
6512 /*
6513 * Now copy part of this value to register or memory, as requested.
6514 * Note that the number of bits actually copied is 32 or 64 depending
6515 * on the guest's mode (32 or 64 bit), not on the given field's length.
6516 */
6517 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6518 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6519 field_value);
6520 } else {
6521 if (get_vmx_mem_address(vcpu, exit_qualification,
6522 vmx_instruction_info, &gva))
6523 return 1;
6524 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6525 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6526 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6527 }
6528
6529 nested_vmx_succeed(vcpu);
6530 skip_emulated_instruction(vcpu);
6531 return 1;
6532}
6533
6534
6535static int handle_vmwrite(struct kvm_vcpu *vcpu)
6536{
6537 unsigned long field;
6538 gva_t gva;
6539 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6540 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6541 /* The value to write might be 32 or 64 bits, depending on L1's long
6542 * mode, and eventually we need to write that into a field of several
6543 * possible lengths. The code below first zero-extends the value to 64
6544 * bit (field_value), and then copies only the approriate number of
6545 * bits into the vmcs12 field.
6546 */
6547 u64 field_value = 0;
6548 struct x86_exception e;
6549
6550 if (!nested_vmx_check_permission(vcpu) ||
6551 !nested_vmx_check_vmcs12(vcpu))
6552 return 1;
6553
6554 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6555 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6556 (((vmx_instruction_info) >> 3) & 0xf));
6557 else {
6558 if (get_vmx_mem_address(vcpu, exit_qualification,
6559 vmx_instruction_info, &gva))
6560 return 1;
6561 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6562 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6563 kvm_inject_page_fault(vcpu, &e);
6564 return 1;
6565 }
6566 }
6567
6568
27e6fb5d 6569 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6570 if (vmcs_field_readonly(field)) {
6571 nested_vmx_failValid(vcpu,
6572 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6573 skip_emulated_instruction(vcpu);
6574 return 1;
6575 }
6576
20b97fea 6577 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6578 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6579 skip_emulated_instruction(vcpu);
6580 return 1;
6581 }
6582
6583 nested_vmx_succeed(vcpu);
6584 skip_emulated_instruction(vcpu);
6585 return 1;
6586}
6587
63846663
NHE		 6588/* Emulate the VMPTRLD instruction */
6589static int handle_vmptrld(struct kvm_vcpu *vcpu)
6590{
6591 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6592 gpa_t vmptr;
8a1b9dd0 6593 u32 exec_control;
63846663
NHE		 6594
6595 if (!nested_vmx_check_permission(vcpu))
6596 return 1;
6597
4291b588 6598 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6599 return 1;
63846663
NHE		 6600
6601 if (vmx->nested.current_vmptr != vmptr) {
6602 struct vmcs12 *new_vmcs12;
6603 struct page *page;
6604 page = nested_get_page(vcpu, vmptr);
6605 if (page == NULL) {
6606 nested_vmx_failInvalid(vcpu);
6607 skip_emulated_instruction(vcpu);
6608 return 1;
6609 }
6610 new_vmcs12 = kmap(page);
6611 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6612 kunmap(page);
6613 nested_release_page_clean(page);
6614 nested_vmx_failValid(vcpu,
6615 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6616 skip_emulated_instruction(vcpu);
6617 return 1;
6618 }
63846663 6619
9a2a05b9 6620 nested_release_vmcs12(vmx);
63846663
NHE		 6621 vmx->nested.current_vmptr = vmptr;
6622 vmx->nested.current_vmcs12 = new_vmcs12;
6623 vmx->nested.current_vmcs12_page = page;
012f83cb 6624 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6625 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6626 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6627 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6628 vmcs_write64(VMCS_LINK_POINTER,
6629 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6630 vmx->nested.sync_shadow_vmcs = true;
6631 }
63846663
NHE		 6632 }
6633
6634 nested_vmx_succeed(vcpu);
6635 skip_emulated_instruction(vcpu);
6636 return 1;
6637}
6638
6a4d7550
NHE		 6639/* Emulate the VMPTRST instruction */
6640static int handle_vmptrst(struct kvm_vcpu *vcpu)
6641{
6642 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6643 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6644 gva_t vmcs_gva;
6645 struct x86_exception e;
6646
6647 if (!nested_vmx_check_permission(vcpu))
6648 return 1;
6649
6650 if (get_vmx_mem_address(vcpu, exit_qualification,
6651 vmx_instruction_info, &vmcs_gva))
6652 return 1;
6653 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6654 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6655 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6656 sizeof(u64), &e)) {
6657 kvm_inject_page_fault(vcpu, &e);
6658 return 1;
6659 }
6660 nested_vmx_succeed(vcpu);
6661 skip_emulated_instruction(vcpu);
6662 return 1;
6663}
6664
bfd0a56b
NHE		 6665/* Emulate the INVEPT instruction */
6666static int handle_invept(struct kvm_vcpu *vcpu)
6667{
6668 u32 vmx_instruction_info, types;
6669 unsigned long type;
6670 gva_t gva;
6671 struct x86_exception e;
6672 struct {
6673 u64 eptp, gpa;
6674 } operand;
bfd0a56b
NHE		 6675
6676 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6677 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6678 kvm_queue_exception(vcpu, UD_VECTOR);
6679 return 1;
6680 }
6681
6682 if (!nested_vmx_check_permission(vcpu))
6683 return 1;
6684
6685 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6686 kvm_queue_exception(vcpu, UD_VECTOR);
6687 return 1;
6688 }
6689
6690 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6691 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6692
6693 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6694
6695 if (!(types & (1UL << type))) {
6696 nested_vmx_failValid(vcpu,
6697 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6698 return 1;
6699 }
6700
6701 /* According to the Intel VMX instruction reference, the memory
6702 * operand is read even if it isn't needed (e.g., for type==global)
6703 */
6704 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6705 vmx_instruction_info, &gva))
6706 return 1;
6707 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6708 sizeof(operand), &e)) {
6709 kvm_inject_page_fault(vcpu, &e);
6710 return 1;
6711 }
6712
6713 switch (type) {
bfd0a56b
NHE		 6714 case VMX_EPT_EXTENT_GLOBAL:
6715 kvm_mmu_sync_roots(vcpu);
77c3913b 6716 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6717 nested_vmx_succeed(vcpu);
6718 break;
6719 default:
4b855078 6720 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6721 BUG_ON(1);
6722 break;
6723 }
6724
6725 skip_emulated_instruction(vcpu);
6726 return 1;
6727}
6728
6aa8b732
AK		 6729/*
6730 * The exit handlers return 1 if the exit was handled fully and guest execution
6731 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6732 * to be done to userspace and return 0.
6733 */
772e0318 6734static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6735 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6736 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6737 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6738 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6739 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6740 [EXIT_REASON_CR_ACCESS] = handle_cr,
6741 [EXIT_REASON_DR_ACCESS] = handle_dr,
6742 [EXIT_REASON_CPUID] = handle_cpuid,
6743 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6744 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6745 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6746 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6747 [EXIT_REASON_INVD] = handle_invd,
a7052897 6748 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6749 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6750 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6751 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6752 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6753 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6754 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6755 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6756 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6757 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6758 [EXIT_REASON_VMOFF] = handle_vmoff,
6759 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6760 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6761 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6762 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6763 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6764 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6765 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6766 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6767 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6768 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6769 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6770 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6771 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6772 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6773 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6774};
6775
6776static const int kvm_vmx_max_exit_handlers =
50a3485c 6777 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6778
908a7bdd
JK		 6779static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6780 struct vmcs12 *vmcs12)
6781{
6782 unsigned long exit_qualification;
6783 gpa_t bitmap, last_bitmap;
6784 unsigned int port;
6785 int size;
6786 u8 b;
6787
908a7bdd 6788 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6789 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6790
6791 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6792
6793 port = exit_qualification >> 16;
6794 size = (exit_qualification & 7) + 1;
6795
6796 last_bitmap = (gpa_t)-1;
6797 b = -1;
6798
6799 while (size > 0) {
6800 if (port < 0x8000)
6801 bitmap = vmcs12->io_bitmap_a;
6802 else if (port < 0x10000)
6803 bitmap = vmcs12->io_bitmap_b;
6804 else
6805 return 1;
6806 bitmap += (port & 0x7fff) / 8;
6807
6808 if (last_bitmap != bitmap)
6809 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6810 return 1;
6811 if (b & (1 << (port & 7)))
6812 return 1;
6813
6814 port++;
6815 size--;
6816 last_bitmap = bitmap;
6817 }
6818
6819 return 0;
6820}
6821
644d711a
NHE		 6822/*
6823 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6824 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6825 * disinterest in the current event (read or write a specific MSR) by using an
6826 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6827 */
6828static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6829 struct vmcs12 *vmcs12, u32 exit_reason)
6830{
6831 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6832 gpa_t bitmap;
6833
cbd29cb6 6834 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6835 return 1;
6836
6837 /*
6838 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6839 * for the four combinations of read/write and low/high MSR numbers.
6840 * First we need to figure out which of the four to use:
6841 */
6842 bitmap = vmcs12->msr_bitmap;
6843 if (exit_reason == EXIT_REASON_MSR_WRITE)
6844 bitmap += 2048;
6845 if (msr_index >= 0xc0000000) {
6846 msr_index -= 0xc0000000;
6847 bitmap += 1024;
6848 }
6849
6850 /* Then read the msr_index'th bit from this bitmap: */
6851 if (msr_index < 1024*8) {
6852 unsigned char b;
bd31a7f5
JK		 6853 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6854 return 1;
644d711a
NHE		 6855 return 1 & (b >> (msr_index & 7));
6856 } else
6857 return 1; /* let L1 handle the wrong parameter */
6858}
6859
6860/*
6861 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6862 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6863 * intercept (via guest_host_mask etc.) the current event.
6864 */
6865static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6866 struct vmcs12 *vmcs12)
6867{
6868 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6869 int cr = exit_qualification & 15;
6870 int reg = (exit_qualification >> 8) & 15;
1e32c079 6871 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 6872
6873 switch ((exit_qualification >> 4) & 3) {
6874 case 0: /* mov to cr */
6875 switch (cr) {
6876 case 0:
6877 if (vmcs12->cr0_guest_host_mask &
6878 (val ^ vmcs12->cr0_read_shadow))
6879 return 1;
6880 break;
6881 case 3:
6882 if ((vmcs12->cr3_target_count >= 1 &&
6883 vmcs12->cr3_target_value0 == val) ||
6884 (vmcs12->cr3_target_count >= 2 &&
6885 vmcs12->cr3_target_value1 == val) ||
6886 (vmcs12->cr3_target_count >= 3 &&
6887 vmcs12->cr3_target_value2 == val) ||
6888 (vmcs12->cr3_target_count >= 4 &&
6889 vmcs12->cr3_target_value3 == val))
6890 return 0;
6891 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6892 return 1;
6893 break;
6894 case 4:
6895 if (vmcs12->cr4_guest_host_mask &
6896 (vmcs12->cr4_read_shadow ^ val))
6897 return 1;
6898 break;
6899 case 8:
6900 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6901 return 1;
6902 break;
6903 }
6904 break;
6905 case 2: /* clts */
6906 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6907 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6908 return 1;
6909 break;
6910 case 1: /* mov from cr */
6911 switch (cr) {
6912 case 3:
6913 if (vmcs12->cpu_based_vm_exec_control &
6914 CPU_BASED_CR3_STORE_EXITING)
6915 return 1;
6916 break;
6917 case 8:
6918 if (vmcs12->cpu_based_vm_exec_control &
6919 CPU_BASED_CR8_STORE_EXITING)
6920 return 1;
6921 break;
6922 }
6923 break;
6924 case 3: /* lmsw */
6925 /*
6926 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6927 * cr0. Other attempted changes are ignored, with no exit.
6928 */
6929 if (vmcs12->cr0_guest_host_mask & 0xe &
6930 (val ^ vmcs12->cr0_read_shadow))
6931 return 1;
6932 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6933 !(vmcs12->cr0_read_shadow & 0x1) &&
6934 (val & 0x1))
6935 return 1;
6936 break;
6937 }
6938 return 0;
6939}
6940
6941/*
6942 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6943 * should handle it ourselves in L0 (and then continue L2). Only call this
6944 * when in is_guest_mode (L2).
6945 */
6946static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6947{
644d711a
NHE		 6948 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6949 struct vcpu_vmx *vmx = to_vmx(vcpu);
6950 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6951 u32 exit_reason = vmx->exit_reason;
644d711a 6952
542060ea
JK		 6953 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6954 vmcs_readl(EXIT_QUALIFICATION),
6955 vmx->idt_vectoring_info,
6956 intr_info,
6957 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6958 KVM_ISA_VMX);
6959
644d711a
NHE		 6960 if (vmx->nested.nested_run_pending)
6961 return 0;
6962
6963 if (unlikely(vmx->fail)) {
bd80158a
JK		 6964 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6965 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6966 return 1;
6967 }
6968
6969 switch (exit_reason) {
6970 case EXIT_REASON_EXCEPTION_NMI:
6971 if (!is_exception(intr_info))
6972 return 0;
6973 else if (is_page_fault(intr_info))
6974 return enable_ept;
e504c909 6975 else if (is_no_device(intr_info) &&
ccf9844e 6976 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6977 return 0;
644d711a
NHE		 6978 return vmcs12->exception_bitmap &
6979 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6980 case EXIT_REASON_EXTERNAL_INTERRUPT:
6981 return 0;
6982 case EXIT_REASON_TRIPLE_FAULT:
6983 return 1;
6984 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6985 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6986 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6987 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6988 case EXIT_REASON_TASK_SWITCH:
6989 return 1;
6990 case EXIT_REASON_CPUID:
bc613494
MT		 6991 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
6992 return 0;
644d711a
NHE		 6993 return 1;
6994 case EXIT_REASON_HLT:
6995 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6996 case EXIT_REASON_INVD:
6997 return 1;
6998 case EXIT_REASON_INVLPG:
6999 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7000 case EXIT_REASON_RDPMC:
7001 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7002 case EXIT_REASON_RDTSC:
7003 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7004 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7005 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7006 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7007 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7008 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 7009 case EXIT_REASON_INVEPT:
644d711a
NHE		 7010 /*
7011 * VMX instructions trap unconditionally. This allows L1 to
7012 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7013 */
7014 return 1;
7015 case EXIT_REASON_CR_ACCESS:
7016 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7017 case EXIT_REASON_DR_ACCESS:
7018 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7019 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7020 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7021 case EXIT_REASON_MSR_READ:
7022 case EXIT_REASON_MSR_WRITE:
7023 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7024 case EXIT_REASON_INVALID_STATE:
7025 return 1;
7026 case EXIT_REASON_MWAIT_INSTRUCTION:
7027 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7028 case EXIT_REASON_MONITOR_INSTRUCTION:
7029 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7030 case EXIT_REASON_PAUSE_INSTRUCTION:
7031 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7032 nested_cpu_has2(vmcs12,
7033 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7034 case EXIT_REASON_MCE_DURING_VMENTRY:
7035 return 0;
7036 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7037 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7038 case EXIT_REASON_APIC_ACCESS:
7039 return nested_cpu_has2(vmcs12,
7040 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7041 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7042 /*
7043 * L0 always deals with the EPT violation. If nested EPT is
7044 * used, and the nested mmu code discovers that the address is
7045 * missing in the guest EPT table (EPT12), the EPT violation
7046 * will be injected with nested_ept_inject_page_fault()
7047 */
7048 return 0;
644d711a 7049 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7050 /*
7051 * L2 never uses directly L1's EPT, but rather L0's own EPT
7052 * table (shadow on EPT) or a merged EPT table that L0 built
7053 * (EPT on EPT). So any problems with the structure of the
7054 * table is L0's fault.
7055 */
644d711a
NHE		 7056 return 0;
7057 case EXIT_REASON_WBINVD:
7058 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7059 case EXIT_REASON_XSETBV:
7060 return 1;
7061 default:
7062 return 1;
7063 }
7064}
7065
586f9607
AK		 7066static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7067{
7068 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7069 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7070}
7071
6aa8b732
AK		 7072/*
7073 * The guest has exited. See if we can fix it or if we need userspace
7074 * assistance.
7075 */
851ba692 7076static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7077{
29bd8a78 7078 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7079 u32 exit_reason = vmx->exit_reason;
1155f76a 7080 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7081
80ced186 7082 /* If guest state is invalid, start emulating */
14168786 7083 if (vmx->emulation_required)
80ced186 7084 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7085
644d711a 7086 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7087 nested_vmx_vmexit(vcpu, exit_reason,
7088 vmcs_read32(VM_EXIT_INTR_INFO),
7089 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7090 return 1;
7091 }
7092
5120702e
MG		 7093 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7094 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7095 vcpu->run->fail_entry.hardware_entry_failure_reason
7096 = exit_reason;
7097 return 0;
7098 }
7099
29bd8a78 7100 if (unlikely(vmx->fail)) {
851ba692
AK		 7101 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7102 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7103 = vmcs_read32(VM_INSTRUCTION_ERROR);
7104 return 0;
7105 }
6aa8b732 7106
b9bf6882
XG		 7107 /*
7108 * Note:
7109 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7110 * delivery event since it indicates guest is accessing MMIO.
7111 * The vm-exit can be triggered again after return to guest that
7112 * will cause infinite loop.
7113 */
d77c26fc 7114 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7115 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7116 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7117 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7118 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7119 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7120 vcpu->run->internal.ndata = 2;
7121 vcpu->run->internal.data[0] = vectoring_info;
7122 vcpu->run->internal.data[1] = exit_reason;
7123 return 0;
7124 }
3b86cd99 7125
644d711a
NHE		 7126 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7127 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7128 get_vmcs12(vcpu))))) {
c4282df9 7129 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7130 vmx->soft_vnmi_blocked = 0;
3b86cd99 7131 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7132 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7133 /*
7134 * This CPU don't support us in finding the end of an
7135 * NMI-blocked window if the guest runs with IRQs
7136 * disabled. So we pull the trigger after 1 s of
7137 * futile waiting, but inform the user about this.
7138 */
7139 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7140 "state on VCPU %d after 1 s timeout\n",
7141 __func__, vcpu->vcpu_id);
7142 vmx->soft_vnmi_blocked = 0;
3b86cd99 7143 }
3b86cd99
JK		 7144 }
7145
6aa8b732
AK		 7146 if (exit_reason < kvm_vmx_max_exit_handlers
7147 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7148 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7149 else {
851ba692
AK		 7150 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7151 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7152 }
7153 return 0;
7154}
7155
95ba8273 7156static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7157{
a7c0b07d
WL		 7158 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7159
7160 if (is_guest_mode(vcpu) &&
7161 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7162 return;
7163
95ba8273 7164 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7165 vmcs_write32(TPR_THRESHOLD, 0);
7166 return;
7167 }
7168
95ba8273 7169 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7170}
7171
8d14695f
YZ		 7172static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7173{
7174 u32 sec_exec_control;
7175
7176 /*
7177 * There is not point to enable virtualize x2apic without enable
7178 * apicv
7179 */
c7c9c56c
YZ		 7180 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7181 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7182 return;
7183
7184 if (!vm_need_tpr_shadow(vcpu->kvm))
7185 return;
7186
7187 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7188
7189 if (set) {
7190 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7191 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7192 } else {
7193 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7194 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7195 }
7196 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7197
7198 vmx_set_msr_bitmap(vcpu);
7199}
7200
c7c9c56c
YZ		 7201static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7202{
7203 u16 status;
7204 u8 old;
7205
7206 if (!vmx_vm_has_apicv(kvm))
7207 return;
7208
7209 if (isr == -1)
7210 isr = 0;
7211
7212 status = vmcs_read16(GUEST_INTR_STATUS);
7213 old = status >> 8;
7214 if (isr != old) {
7215 status &= 0xff;
7216 status |= isr << 8;
7217 vmcs_write16(GUEST_INTR_STATUS, status);
7218 }
7219}
7220
7221static void vmx_set_rvi(int vector)
7222{
7223 u16 status;
7224 u8 old;
7225
7226 status = vmcs_read16(GUEST_INTR_STATUS);
7227 old = (u8)status & 0xff;
7228 if ((u8)vector != old) {
7229 status &= ~0xff;
7230 status |= (u8)vector;
7231 vmcs_write16(GUEST_INTR_STATUS, status);
7232 }
7233}
7234
7235static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7236{
7237 if (max_irr == -1)
7238 return;
7239
963fee16
WL		 7240 /*
7241 * If a vmexit is needed, vmx_check_nested_events handles it.
7242 */
7243 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7244 return;
7245
7246 if (!is_guest_mode(vcpu)) {
7247 vmx_set_rvi(max_irr);
7248 return;
7249 }
7250
7251 /*
7252 * Fall back to pre-APICv interrupt injection since L2
7253 * is run without virtual interrupt delivery.
7254 */
7255 if (!kvm_event_needs_reinjection(vcpu) &&
7256 vmx_interrupt_allowed(vcpu)) {
7257 kvm_queue_interrupt(vcpu, max_irr, false);
7258 vmx_inject_irq(vcpu);
7259 }
c7c9c56c
YZ		 7260}
7261
7262static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7263{
3d81bc7e
YZ		 7264 if (!vmx_vm_has_apicv(vcpu->kvm))
7265 return;
7266
c7c9c56c
YZ		 7267 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7268 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7269 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7270 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7271}
7272
51aa01d1 7273static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7274{
00eba012
AK		 7275 u32 exit_intr_info;
7276
7277 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7278 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7279 return;
7280
c5ca8e57 7281 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7282 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7283
7284 /* Handle machine checks before interrupts are enabled */
00eba012 7285 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7286 kvm_machine_check();
7287
20f65983 7288 /* We need to handle NMIs before interrupts are enabled */
00eba012 7289 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7290 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7291 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7292 asm("int $2");
ff9d07a0
ZY		 7293 kvm_after_handle_nmi(&vmx->vcpu);
7294 }
51aa01d1 7295}
20f65983 7296
a547c6db
YZ		 7297static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7298{
7299 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7300
7301 /*
7302 * If external interrupt exists, IF bit is set in rflags/eflags on the
7303 * interrupt stack frame, and interrupt will be enabled on a return
7304 * from interrupt handler.
7305 */
7306 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7307 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7308 unsigned int vector;
7309 unsigned long entry;
7310 gate_desc *desc;
7311 struct vcpu_vmx *vmx = to_vmx(vcpu);
7312#ifdef CONFIG_X86_64
7313 unsigned long tmp;
7314#endif
7315
7316 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7317 desc = (gate_desc *)vmx->host_idt_base + vector;
7318 entry = gate_offset(*desc);
7319 asm volatile(
7320#ifdef CONFIG_X86_64
7321 "mov %%" _ASM_SP ", %[sp]\n\t"
7322 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7323 "push $%c[ss]\n\t"
7324 "push %[sp]\n\t"
7325#endif
7326 "pushf\n\t"
7327 "orl $0x200, (%%" _ASM_SP ")\n\t"
7328 __ASM_SIZE(push) " $%c[cs]\n\t"
7329 "call *%[entry]\n\t"
7330 :
7331#ifdef CONFIG_X86_64
7332 [sp]"=&r"(tmp)
7333#endif
7334 :
7335 [entry]"r"(entry),
7336 [ss]"i"(__KERNEL_DS),
7337 [cs]"i"(__KERNEL_CS)
7338 );
7339 } else
7340 local_irq_enable();
7341}
7342
da8999d3
LJ		 7343static bool vmx_mpx_supported(void)
7344{
7345 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7346 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7347}
7348
51aa01d1
AK		 7349static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7350{
c5ca8e57 7351 u32 exit_intr_info;
51aa01d1
AK		 7352 bool unblock_nmi;
7353 u8 vector;
7354 bool idtv_info_valid;
7355
7356 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7357
cf393f75 7358 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7359 if (vmx->nmi_known_unmasked)
7360 return;
c5ca8e57
AK		 7361 /*
7362 * Can't use vmx->exit_intr_info since we're not sure what
7363 * the exit reason is.
7364 */
7365 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7366 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7367 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7368 /*
7b4a25cb 7369 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7370 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7371 * a guest IRET fault.
7b4a25cb
GN		 7372 * SDM 3: 23.2.2 (September 2008)
7373 * Bit 12 is undefined in any of the following cases:
7374 * If the VM exit sets the valid bit in the IDT-vectoring
7375 * information field.
7376 * If the VM exit is due to a double fault.
cf393f75 7377 */
7b4a25cb
GN		 7378 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7379 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7380 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7381 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7382 else
7383 vmx->nmi_known_unmasked =
7384 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7385 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7386 } else if (unlikely(vmx->soft_vnmi_blocked))
7387 vmx->vnmi_blocked_time +=
7388 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7389}
7390
3ab66e8a 7391static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7392 u32 idt_vectoring_info,
7393 int instr_len_field,
7394 int error_code_field)
51aa01d1 7395{
51aa01d1
AK		 7396 u8 vector;
7397 int type;
7398 bool idtv_info_valid;
7399
7400 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7401
3ab66e8a
JK		 7402 vcpu->arch.nmi_injected = false;
7403 kvm_clear_exception_queue(vcpu);
7404 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7405
7406 if (!idtv_info_valid)
7407 return;
7408
3ab66e8a 7409 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7410
668f612f
AK		 7411 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7412 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7413
64a7ec06 7414 switch (type) {
37b96e98 7415 case INTR_TYPE_NMI_INTR:
3ab66e8a 7416 vcpu->arch.nmi_injected = true;
668f612f 7417 /*
7b4a25cb 7418 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7419 * Clear bit "block by NMI" before VM entry if a NMI
7420 * delivery faulted.
668f612f 7421 */
3ab66e8a 7422 vmx_set_nmi_mask(vcpu, false);
37b96e98 7423 break;
37b96e98 7424 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7425 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7426 /* fall through */
7427 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7428 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7429 u32 err = vmcs_read32(error_code_field);
851eb667 7430 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7431 } else
851eb667 7432 kvm_requeue_exception(vcpu, vector);
37b96e98 7433 break;
66fd3f7f 7434 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7435 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7436 /* fall through */
37b96e98 7437 case INTR_TYPE_EXT_INTR:
3ab66e8a 7438 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7439 break;
7440 default:
7441 break;
f7d9238f 7442 }
cf393f75
AK		 7443}
7444
83422e17
AK		 7445static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7446{
3ab66e8a 7447 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7448 VM_EXIT_INSTRUCTION_LEN,
7449 IDT_VECTORING_ERROR_CODE);
7450}
7451
b463a6f7
AK		 7452static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7453{
3ab66e8a 7454 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7455 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7456 VM_ENTRY_INSTRUCTION_LEN,
7457 VM_ENTRY_EXCEPTION_ERROR_CODE);
7458
7459 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7460}
7461
d7cd9796
GN		 7462static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7463{
7464 int i, nr_msrs;
7465 struct perf_guest_switch_msr *msrs;
7466
7467 msrs = perf_guest_get_msrs(&nr_msrs);
7468
7469 if (!msrs)
7470 return;
7471
7472 for (i = 0; i < nr_msrs; i++)
7473 if (msrs[i].host == msrs[i].guest)
7474 clear_atomic_switch_msr(vmx, msrs[i].msr);
7475 else
7476 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7477 msrs[i].host);
7478}
7479
a3b5ba49 7480static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7481{
a2fa3e9f 7482 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7483 unsigned long debugctlmsr;
104f226b
AK		 7484
7485 /* Record the guest's net vcpu time for enforced NMI injections. */
7486 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7487 vmx->entry_time = ktime_get();
7488
7489 /* Don't enter VMX if guest state is invalid, let the exit handler
7490 start emulation until we arrive back to a valid state */
14168786 7491 if (vmx->emulation_required)
104f226b
AK		 7492 return;
7493
a7653ecd
RK		 7494 if (vmx->ple_window_dirty) {
7495 vmx->ple_window_dirty = false;
7496 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7497 }
7498
012f83cb
AG		 7499 if (vmx->nested.sync_shadow_vmcs) {
7500 copy_vmcs12_to_shadow(vmx);
7501 vmx->nested.sync_shadow_vmcs = false;
7502 }
7503
104f226b
AK		 7504 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7505 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7506 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7507 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7508
7509 /* When single-stepping over STI and MOV SS, we must clear the
7510 * corresponding interruptibility bits in the guest state. Otherwise
7511 * vmentry fails as it then expects bit 14 (BS) in pending debug
7512 * exceptions being set, but that's not correct for the guest debugging
7513 * case. */
7514 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7515 vmx_set_interrupt_shadow(vcpu, 0);
7516
d7cd9796 7517 atomic_switch_perf_msrs(vmx);
2a7921b7 7518 debugctlmsr = get_debugctlmsr();
d7cd9796 7519
d462b819 7520 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7521 asm(
6aa8b732 7522 /* Store host registers */
b188c81f
AK		 7523 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7524 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7525 "push %%" _ASM_CX " \n\t"
7526 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7527 "je 1f \n\t"
b188c81f 7528 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7529 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7530 "1: \n\t"
d3edefc0 7531 /* Reload cr2 if changed */
b188c81f
AK		 7532 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7533 "mov %%cr2, %%" _ASM_DX " \n\t"
7534 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7535 "je 2f \n\t"
b188c81f 7536 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7537 "2: \n\t"
6aa8b732 7538 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7539 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7540 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7541 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7542 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7543 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7544 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7545 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7546 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7547#ifdef CONFIG_X86_64
e08aa78a
AK		 7548 "mov %c[r8](%0), %%r8 \n\t"
7549 "mov %c[r9](%0), %%r9 \n\t"
7550 "mov %c[r10](%0), %%r10 \n\t"
7551 "mov %c[r11](%0), %%r11 \n\t"
7552 "mov %c[r12](%0), %%r12 \n\t"
7553 "mov %c[r13](%0), %%r13 \n\t"
7554 "mov %c[r14](%0), %%r14 \n\t"
7555 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7556#endif
b188c81f 7557 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7558
6aa8b732 7559 /* Enter guest mode */
83287ea4 7560 "jne 1f \n\t"
4ecac3fd 7561 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7562 "jmp 2f \n\t"
7563 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7564 "2: "
6aa8b732 7565 /* Save guest registers, load host registers, keep flags */
b188c81f 7566 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7567 "pop %0 \n\t"
b188c81f
AK		 7568 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7569 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7570 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7571 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7572 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7573 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7574 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7575#ifdef CONFIG_X86_64
e08aa78a
AK		 7576 "mov %%r8, %c[r8](%0) \n\t"
7577 "mov %%r9, %c[r9](%0) \n\t"
7578 "mov %%r10, %c[r10](%0) \n\t"
7579 "mov %%r11, %c[r11](%0) \n\t"
7580 "mov %%r12, %c[r12](%0) \n\t"
7581 "mov %%r13, %c[r13](%0) \n\t"
7582 "mov %%r14, %c[r14](%0) \n\t"
7583 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7584#endif
b188c81f
AK		 7585 "mov %%cr2, %%" _ASM_AX " \n\t"
7586 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7587
b188c81f 7588 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7589 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7590 ".pushsection .rodata \n\t"
7591 ".global vmx_return \n\t"
7592 "vmx_return: " _ASM_PTR " 2b \n\t"
7593 ".popsection"
e08aa78a 7594 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7595 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7596 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7597 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7598 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7599 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7600 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7601 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7602 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7603 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7604 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7605#ifdef CONFIG_X86_64
ad312c7c
ZX		 7606 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7607 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7608 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7609 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7610 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7611 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7612 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7613 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7614#endif
40712fae
AK		 7615 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7616 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7617 : "cc", "memory"
7618#ifdef CONFIG_X86_64
b188c81f 7619 , "rax", "rbx", "rdi", "rsi"
c2036300 7620 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7621#else
7622 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7623#endif
7624 );
6aa8b732 7625
2a7921b7
GN		 7626 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7627 if (debugctlmsr)
7628 update_debugctlmsr(debugctlmsr);
7629
aa67f609
AK		 7630#ifndef CONFIG_X86_64
7631 /*
7632 * The sysexit path does not restore ds/es, so we must set them to
7633 * a reasonable value ourselves.
7634 *
7635 * We can't defer this to vmx_load_host_state() since that function
7636 * may be executed in interrupt context, which saves and restore segments
7637 * around it, nullifying its effect.
7638 */
7639 loadsegment(ds, __USER_DS);
7640 loadsegment(es, __USER_DS);
7641#endif
7642
6de4f3ad 7643 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7644 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7645 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7646 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7647 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7648 vcpu->arch.regs_dirty = 0;
7649
1155f76a
AK		 7650 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7651
d462b819 7652 vmx->loaded_vmcs->launched = 1;
1b6269db 7653
51aa01d1 7654 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7655 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7656
e0b890d3
GN		 7657 /*
7658 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7659 * we did not inject a still-pending event to L1 now because of
7660 * nested_run_pending, we need to re-enable this bit.
7661 */
7662 if (vmx->nested.nested_run_pending)
7663 kvm_make_request(KVM_REQ_EVENT, vcpu);
7664
7665 vmx->nested.nested_run_pending = 0;
7666
51aa01d1
AK		 7667 vmx_complete_atomic_exit(vmx);
7668 vmx_recover_nmi_blocking(vmx);
cf393f75 7669 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7670}
7671
4fa7734c
PB		 7672static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7673{
7674 struct vcpu_vmx *vmx = to_vmx(vcpu);
7675 int cpu;
7676
7677 if (vmx->loaded_vmcs == &vmx->vmcs01)
7678 return;
7679
7680 cpu = get_cpu();
7681 vmx->loaded_vmcs = &vmx->vmcs01;
7682 vmx_vcpu_put(vcpu);
7683 vmx_vcpu_load(vcpu, cpu);
7684 vcpu->cpu = cpu;
7685 put_cpu();
7686}
7687
6aa8b732
AK		 7688static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7689{
fb3f0f51
RR		 7690 struct vcpu_vmx *vmx = to_vmx(vcpu);
7691
cdbecfc3 7692 free_vpid(vmx);
4fa7734c
PB		 7693 leave_guest_mode(vcpu);
7694 vmx_load_vmcs01(vcpu);
26a865f4 7695 free_nested(vmx);
4fa7734c 7696 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7697 kfree(vmx->guest_msrs);
7698 kvm_vcpu_uninit(vcpu);
a4770347 7699 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7700}
7701
fb3f0f51 7702static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7703{
fb3f0f51 7704 int err;
c16f862d 7705 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7706 int cpu;
6aa8b732 7707
a2fa3e9f 7708 if (!vmx)
fb3f0f51
RR		 7709 return ERR_PTR(-ENOMEM);
7710
2384d2b3
SY		 7711 allocate_vpid(vmx);
7712
fb3f0f51
RR		 7713 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7714 if (err)
7715 goto free_vcpu;
965b58a5 7716
a2fa3e9f 7717 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7718 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7719 > PAGE_SIZE);
0123be42 7720
be6d05cf 7721 err = -ENOMEM;
fb3f0f51 7722 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7723 goto uninit_vcpu;
7724 }
965b58a5 7725
d462b819
NHE		 7726 vmx->loaded_vmcs = &vmx->vmcs01;
7727 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7728 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7729 goto free_msrs;
d462b819
NHE		 7730 if (!vmm_exclusive)
7731 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7732 loaded_vmcs_init(vmx->loaded_vmcs);
7733 if (!vmm_exclusive)
7734 kvm_cpu_vmxoff();
a2fa3e9f 7735
15ad7146
AK		 7736 cpu = get_cpu();
7737 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7738 vmx->vcpu.cpu = cpu;
8b9cf98c 7739 err = vmx_vcpu_setup(vmx);
fb3f0f51 7740 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7741 put_cpu();
fb3f0f51
RR		 7742 if (err)
7743 goto free_vmcs;
a63cb560 7744 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7745 err = alloc_apic_access_page(kvm);
7746 if (err)
5e4a0b3c 7747 goto free_vmcs;
a63cb560 7748 }
fb3f0f51 7749
b927a3ce
SY		 7750 if (enable_ept) {
7751 if (!kvm->arch.ept_identity_map_addr)
7752 kvm->arch.ept_identity_map_addr =
7753 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7754 err = init_rmode_identity_map(kvm);
7755 if (err)
93ea5388 7756 goto free_vmcs;
b927a3ce 7757 }
b7ebfb05 7758
a9d30f33
NHE		 7759 vmx->nested.current_vmptr = -1ull;
7760 vmx->nested.current_vmcs12 = NULL;
7761
fb3f0f51
RR		 7762 return &vmx->vcpu;
7763
7764free_vmcs:
5f3fbc34 7765 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7766free_msrs:
fb3f0f51
RR		 7767 kfree(vmx->guest_msrs);
7768uninit_vcpu:
7769 kvm_vcpu_uninit(&vmx->vcpu);
7770free_vcpu:
cdbecfc3 7771 free_vpid(vmx);
a4770347 7772 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7773 return ERR_PTR(err);
6aa8b732
AK		 7774}
7775
002c7f7c
YS		 7776static void __init vmx_check_processor_compat(void *rtn)
7777{
7778 struct vmcs_config vmcs_conf;
7779
7780 *(int *)rtn = 0;
7781 if (setup_vmcs_config(&vmcs_conf) < 0)
7782 *(int *)rtn = -EIO;
7783 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7784 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7785 smp_processor_id());
7786 *(int *)rtn = -EIO;
7787 }
7788}
7789
67253af5
SY		 7790static int get_ept_level(void)
7791{
7792 return VMX_EPT_DEFAULT_GAW + 1;
7793}
7794
4b12f0de 7795static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7796{
4b12f0de
SY		 7797 u64 ret;
7798
522c68c4
SY		 7799 /* For VT-d and EPT combination
7800 * 1. MMIO: always map as UC
7801 * 2. EPT with VT-d:
7802 * a. VT-d without snooping control feature: can't guarantee the
7803 * result, try to trust guest.
7804 * b. VT-d with snooping control feature: snooping control feature of
7805 * VT-d engine can guarantee the cache correctness. Just set it
7806 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7807 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7808 * consistent with host MTRR
7809 */
4b12f0de
SY		 7810 if (is_mmio)
7811 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7812 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7813 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7814 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7815 else
522c68c4 7816 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7817 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7818
7819 return ret;
64d4d521
SY		 7820}
7821
17cc3935 7822static int vmx_get_lpage_level(void)
344f414f 7823{
878403b7
SY		 7824 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7825 return PT_DIRECTORY_LEVEL;
7826 else
7827 /* For shadow and EPT supported 1GB page */
7828 return PT_PDPE_LEVEL;
344f414f
JR		 7829}
7830
0e851880
SY		 7831static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7832{
4e47c7a6
SY		 7833 struct kvm_cpuid_entry2 *best;
7834 struct vcpu_vmx *vmx = to_vmx(vcpu);
7835 u32 exec_control;
7836
7837 vmx->rdtscp_enabled = false;
7838 if (vmx_rdtscp_supported()) {
7839 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7840 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7841 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7842 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7843 vmx->rdtscp_enabled = true;
7844 else {
7845 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7846 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7847 exec_control);
7848 }
7849 }
7850 }
ad756a16 7851
ad756a16
MJ		 7852 /* Exposing INVPCID only when PCID is exposed */
7853 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7854 if (vmx_invpcid_supported() &&
4f977045 7855 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7856 guest_cpuid_has_pcid(vcpu)) {
29282fde 7857 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7858 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7859 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7860 exec_control);
7861 } else {
29282fde
TI		 7862 if (cpu_has_secondary_exec_ctrls()) {
7863 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7864 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7865 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7866 exec_control);
7867 }
ad756a16 7868 if (best)
4f977045 7869 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7870 }
0e851880
SY		 7871}
7872
d4330ef2
JR		 7873static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7874{
7b8050f5
NHE		 7875 if (func == 1 && nested)
7876 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7877}
7878
25d92081
YZ		 7879static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7880 struct x86_exception *fault)
7881{
533558bc
JK		 7882 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7883 u32 exit_reason;
25d92081
YZ		 7884
7885 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7886 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7887 else
533558bc
JK		 7888 exit_reason = EXIT_REASON_EPT_VIOLATION;
7889 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7890 vmcs12->guest_physical_address = fault->address;
7891}
7892
155a97a3
NHE		 7893/* Callbacks for nested_ept_init_mmu_context: */
7894
7895static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7896{
7897 /* return the page table to be shadowed - in our case, EPT12 */
7898 return get_vmcs12(vcpu)->ept_pointer;
7899}
7900
8a3c1a33 7901static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7902{
8a3c1a33 7903 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7904 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7905
7906 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7907 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7908 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7909
7910 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7911}
7912
7913static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7914{
7915 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7916}
7917
feaf0c7d
GN		 7918static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7919 struct x86_exception *fault)
7920{
7921 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7922
7923 WARN_ON(!is_guest_mode(vcpu));
7924
7925 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7926 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7927 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7928 vmcs_read32(VM_EXIT_INTR_INFO),
7929 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7930 else
7931 kvm_inject_page_fault(vcpu, fault);
7932}
7933
a2bcba50
WL		 7934static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
7935 struct vmcs12 *vmcs12)
7936{
7937 struct vcpu_vmx *vmx = to_vmx(vcpu);
7938
7939 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 7940 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 7941 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 7942 return false;
7943
7944 /*
7945 * Translate L1 physical address to host physical
7946 * address for vmcs02. Keep the page pinned, so this
7947 * physical address remains valid. We keep a reference
7948 * to it so we can release it later.
7949 */
7950 if (vmx->nested.apic_access_page) /* shouldn't happen */
7951 nested_release_page(vmx->nested.apic_access_page);
7952 vmx->nested.apic_access_page =
7953 nested_get_page(vcpu, vmcs12->apic_access_addr);
7954 }
a7c0b07d
WL		 7955
7956 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
7957 /* TODO: Also verify bits beyond physical address width are 0 */
7958 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
7959 return false;
7960
7961 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
7962 nested_release_page(vmx->nested.virtual_apic_page);
7963 vmx->nested.virtual_apic_page =
7964 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
7965
7966 /*
7967 * Failing the vm entry is _not_ what the processor does
7968 * but it's basically the only possibility we have.
7969 * We could still enter the guest if CR8 load exits are
7970 * enabled, CR8 store exits are enabled, and virtualize APIC
7971 * access is disabled; in this case the processor would never
7972 * use the TPR shadow and we could simply clear the bit from
7973 * the execution control. But such a configuration is useless,
7974 * so let's keep the code simple.
7975 */
7976 if (!vmx->nested.virtual_apic_page)
7977 return false;
7978 }
7979
a2bcba50
WL		 7980 return true;
7981}
7982
f4124500
JK		 7983static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7984{
7985 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7986 struct vcpu_vmx *vmx = to_vmx(vcpu);
7987
7988 if (vcpu->arch.virtual_tsc_khz == 0)
7989 return;
7990
7991 /* Make sure short timeouts reliably trigger an immediate vmexit.
7992 * hrtimer_start does not guarantee this. */
7993 if (preemption_timeout <= 1) {
7994 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7995 return;
7996 }
7997
7998 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7999 preemption_timeout *= 1000000;
8000 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8001 hrtimer_start(&vmx->nested.preemption_timer,
8002 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8003}
8004
fe3ef05c
NHE		 8005/*
8006 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8007 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
8008 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
8009 * guest in a way that will both be appropriate to L1's requests, and our
8010 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8011 * function also has additional necessary side-effects, like setting various
8012 * vcpu->arch fields.
8013 */
8014static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8015{
8016 struct vcpu_vmx *vmx = to_vmx(vcpu);
8017 u32 exec_control;
8018
8019 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8020 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8021 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8022 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8023 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8024 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8025 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8026 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8027 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8028 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8029 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8030 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8031 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8032 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8033 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8034 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8035 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8036 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8037 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8038 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8039 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8040 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8041 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8042 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8043 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8044 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8045 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8046 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8047 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8048 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8049 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8050 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8051 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8052 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8053 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8054 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8055
2996fca0
JK		 8056 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8057 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8058 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8059 } else {
8060 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8061 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8062 }
fe3ef05c
NHE		 8063 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8064 vmcs12->vm_entry_intr_info_field);
8065 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8066 vmcs12->vm_entry_exception_error_code);
8067 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8068 vmcs12->vm_entry_instruction_len);
8069 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8070 vmcs12->guest_interruptibility_info);
fe3ef05c 8071 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8072 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8073 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8074 vmcs12->guest_pending_dbg_exceptions);
8075 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8076 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8077
8078 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8079
f4124500
JK		 8080 exec_control = vmcs12->pin_based_vm_exec_control;
8081 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8082 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8083 PIN_BASED_POSTED_INTR);
f4124500 8084 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8085
f4124500
JK		 8086 vmx->nested.preemption_timer_expired = false;
8087 if (nested_cpu_has_preemption_timer(vmcs12))
8088 vmx_start_preemption_timer(vcpu);
0238ea91 8089
fe3ef05c
NHE		 8090 /*
8091 * Whether page-faults are trapped is determined by a combination of
8092 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8093 * If enable_ept, L0 doesn't care about page faults and we should
8094 * set all of these to L1's desires. However, if !enable_ept, L0 does
8095 * care about (at least some) page faults, and because it is not easy
8096 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8097 * to exit on each and every L2 page fault. This is done by setting
8098 * MASK=MATCH=0 and (see below) EB.PF=1.
8099 * Note that below we don't need special code to set EB.PF beyond the
8100 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8101 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8102 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8103 *
8104 * A problem with this approach (when !enable_ept) is that L1 may be
8105 * injected with more page faults than it asked for. This could have
8106 * caused problems, but in practice existing hypervisors don't care.
8107 * To fix this, we will need to emulate the PFEC checking (on the L1
8108 * page tables), using walk_addr(), when injecting PFs to L1.
8109 */
8110 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8111 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8112 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8113 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8114
8115 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8116 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8117 if (!vmx->rdtscp_enabled)
8118 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8119 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8120 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8121 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8122 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8123 if (nested_cpu_has(vmcs12,
8124 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8125 exec_control |= vmcs12->secondary_vm_exec_control;
8126
8127 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8128 /*
8129 * If translation failed, no matter: This feature asks
8130 * to exit when accessing the given address, and if it
8131 * can never be accessed, this feature won't do
8132 * anything anyway.
8133 */
8134 if (!vmx->nested.apic_access_page)
8135 exec_control &=
8136 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8137 else
8138 vmcs_write64(APIC_ACCESS_ADDR,
8139 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8140 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8141 exec_control |=
8142 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8143 vmcs_write64(APIC_ACCESS_ADDR,
8144 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 8145 }
8146
8147 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8148 }
8149
8150
8151 /*
8152 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8153 * Some constant fields are set here by vmx_set_constant_host_state().
8154 * Other fields are different per CPU, and will be set later when
8155 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8156 */
a547c6db 8157 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8158
8159 /*
8160 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8161 * entry, but only if the current (host) sp changed from the value
8162 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8163 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8164 * here we just force the write to happen on entry.
8165 */
8166 vmx->host_rsp = 0;
8167
8168 exec_control = vmx_exec_control(vmx); /* L0's desires */
8169 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8170 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8171 exec_control &= ~CPU_BASED_TPR_SHADOW;
8172 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8173
8174 if (exec_control & CPU_BASED_TPR_SHADOW) {
8175 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8176 page_to_phys(vmx->nested.virtual_apic_page));
8177 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8178 }
8179
fe3ef05c
NHE		 8180 /*
8181 * Merging of IO and MSR bitmaps not currently supported.
8182 * Rather, exit every time.
8183 */
8184 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8185 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8186 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8187
8188 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8189
8190 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8191 * bitwise-or of what L1 wants to trap for L2, and what we want to
8192 * trap. Note that CR0.TS also needs updating - we do this later.
8193 */
8194 update_exception_bitmap(vcpu);
8195 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8196 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8197
8049d651
NHE		 8198 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8199 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8200 * bits are further modified by vmx_set_efer() below.
8201 */
f4124500 8202 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8203
8204 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8205 * emulated by vmx_set_efer(), below.
8206 */
2961e876 8207 vm_entry_controls_init(vmx,
8049d651
NHE		 8208 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8209 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8210 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8211
44811c02 8212 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8213 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8214 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8215 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8216 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8217
8218
8219 set_cr4_guest_host_mask(vmx);
8220
36be0b9d
PB		 8221 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8222 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8223
27fc51b2
NHE		 8224 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8225 vmcs_write64(TSC_OFFSET,
8226 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8227 else
8228 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8229
8230 if (enable_vpid) {
8231 /*
8232 * Trivially support vpid by letting L2s share their parent
8233 * L1's vpid. TODO: move to a more elaborate solution, giving
8234 * each L2 its own vpid and exposing the vpid feature to L1.
8235 */
8236 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8237 vmx_flush_tlb(vcpu);
8238 }
8239
155a97a3
NHE		 8240 if (nested_cpu_has_ept(vmcs12)) {
8241 kvm_mmu_unload(vcpu);
8242 nested_ept_init_mmu_context(vcpu);
8243 }
8244
fe3ef05c
NHE		 8245 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8246 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8247 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8248 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8249 else
8250 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8251 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8252 vmx_set_efer(vcpu, vcpu->arch.efer);
8253
8254 /*
8255 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8256 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8257 * The CR0_READ_SHADOW is what L2 should have expected to read given
8258 * the specifications by L1; It's not enough to take
8259 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8260 * have more bits than L1 expected.
8261 */
8262 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8263 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8264
8265 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8266 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8267
8268 /* shadow page tables on either EPT or shadow page tables */
8269 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8270 kvm_mmu_reset_context(vcpu);
8271
feaf0c7d
GN		 8272 if (!enable_ept)
8273 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8274
3633cfc3
NHE		 8275 /*
8276 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8277 */
8278 if (enable_ept) {
8279 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8280 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8281 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8282 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8283 }
8284
fe3ef05c
NHE		 8285 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8286 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8287}
8288
cd232ad0
NHE		 8289/*
8290 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8291 * for running an L2 nested guest.
8292 */
8293static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8294{
8295 struct vmcs12 *vmcs12;
8296 struct vcpu_vmx *vmx = to_vmx(vcpu);
8297 int cpu;
8298 struct loaded_vmcs *vmcs02;
384bb783 8299 bool ia32e;
cd232ad0
NHE		 8300
8301 if (!nested_vmx_check_permission(vcpu) ||
8302 !nested_vmx_check_vmcs12(vcpu))
8303 return 1;
8304
8305 skip_emulated_instruction(vcpu);
8306 vmcs12 = get_vmcs12(vcpu);
8307
012f83cb
AG		 8308 if (enable_shadow_vmcs)
8309 copy_shadow_to_vmcs12(vmx);
8310
7c177938
NHE		 8311 /*
8312 * The nested entry process starts with enforcing various prerequisites
8313 * on vmcs12 as required by the Intel SDM, and act appropriately when
8314 * they fail: As the SDM explains, some conditions should cause the
8315 * instruction to fail, while others will cause the instruction to seem
8316 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8317 * To speed up the normal (success) code path, we should avoid checking
8318 * for misconfigurations which will anyway be caught by the processor
8319 * when using the merged vmcs02.
8320 */
8321 if (vmcs12->launch_state == launch) {
8322 nested_vmx_failValid(vcpu,
8323 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8324 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8325 return 1;
8326 }
8327
6dfacadd
JK		 8328 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8329 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8330 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8331 return 1;
8332 }
8333
7c177938 8334 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8335 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8336 /*TODO: Also verify bits beyond physical address width are 0*/
8337 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8338 return 1;
8339 }
8340
a2bcba50 8341 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8342 /*TODO: Also verify bits beyond physical address width are 0*/
8343 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8344 return 1;
8345 }
8346
8347 if (vmcs12->vm_entry_msr_load_count > 0 ||
8348 vmcs12->vm_exit_msr_load_count > 0 ||
8349 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8350 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8351 __func__);
7c177938
NHE		 8352 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8353 return 1;
8354 }
8355
8356 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8357 nested_vmx_true_procbased_ctls_low,
8358 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8359 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8360 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8361 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8362 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8363 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8364 nested_vmx_true_exit_ctls_low,
8365 nested_vmx_exit_ctls_high) ||
7c177938 8366 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8367 nested_vmx_true_entry_ctls_low,
8368 nested_vmx_entry_ctls_high))
7c177938
NHE		 8369 {
8370 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8371 return 1;
8372 }
8373
8374 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8375 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8376 nested_vmx_failValid(vcpu,
8377 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8378 return 1;
8379 }
8380
92fbc7b1 8381 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8382 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8383 nested_vmx_entry_failure(vcpu, vmcs12,
8384 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8385 return 1;
8386 }
8387 if (vmcs12->vmcs_link_pointer != -1ull) {
8388 nested_vmx_entry_failure(vcpu, vmcs12,
8389 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8390 return 1;
8391 }
8392
384bb783 8393 /*
cb0c8cda 8394 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8395 * are performed on the field for the IA32_EFER MSR:
8396 * - Bits reserved in the IA32_EFER MSR must be 0.
8397 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8398 * the IA-32e mode guest VM-exit control. It must also be identical
8399 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8400 * CR0.PG) is 1.
8401 */
8402 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8403 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8404 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8405 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8406 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8407 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8408 nested_vmx_entry_failure(vcpu, vmcs12,
8409 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8410 return 1;
8411 }
8412 }
8413
8414 /*
8415 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8416 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8417 * the values of the LMA and LME bits in the field must each be that of
8418 * the host address-space size VM-exit control.
8419 */
8420 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8421 ia32e = (vmcs12->vm_exit_controls &
8422 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8423 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8424 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8425 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8426 nested_vmx_entry_failure(vcpu, vmcs12,
8427 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8428 return 1;
8429 }
8430 }
8431
7c177938
NHE		 8432 /*
8433 * We're finally done with prerequisite checking, and can start with
8434 * the nested entry.
8435 */
8436
cd232ad0
NHE		 8437 vmcs02 = nested_get_current_vmcs02(vmx);
8438 if (!vmcs02)
8439 return -ENOMEM;
8440
8441 enter_guest_mode(vcpu);
8442
8443 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8444
2996fca0
JK		 8445 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8446 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8447
cd232ad0
NHE		 8448 cpu = get_cpu();
8449 vmx->loaded_vmcs = vmcs02;
8450 vmx_vcpu_put(vcpu);
8451 vmx_vcpu_load(vcpu, cpu);
8452 vcpu->cpu = cpu;
8453 put_cpu();
8454
36c3cc42
JK		 8455 vmx_segment_cache_clear(vmx);
8456
cd232ad0
NHE		 8457 vmcs12->launch_state = 1;
8458
8459 prepare_vmcs02(vcpu, vmcs12);
8460
6dfacadd
JK		 8461 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8462 return kvm_emulate_halt(vcpu);
8463
7af40ad3
JK		 8464 vmx->nested.nested_run_pending = 1;
8465
cd232ad0
NHE		 8466 /*
8467 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8468 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8469 * returned as far as L1 is concerned. It will only return (and set
8470 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8471 */
8472 return 1;
8473}
8474
4704d0be
NHE		 8475/*
8476 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8477 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8478 * This function returns the new value we should put in vmcs12.guest_cr0.
8479 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8480 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8481 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8482 * didn't trap the bit, because if L1 did, so would L0).
8483 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8484 * been modified by L2, and L1 knows it. So just leave the old value of
8485 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8486 * isn't relevant, because if L0 traps this bit it can set it to anything.
8487 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8488 * changed these bits, and therefore they need to be updated, but L0
8489 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8490 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8491 */
8492static inline unsigned long
8493vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8494{
8495 return
8496 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8497 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8498 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8499 vcpu->arch.cr0_guest_owned_bits));
8500}
8501
8502static inline unsigned long
8503vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8504{
8505 return
8506 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8507 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8508 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8509 vcpu->arch.cr4_guest_owned_bits));
8510}
8511
5f3d5799
JK		 8512static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8513 struct vmcs12 *vmcs12)
8514{
8515 u32 idt_vectoring;
8516 unsigned int nr;
8517
851eb667 8518 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8519 nr = vcpu->arch.exception.nr;
8520 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8521
8522 if (kvm_exception_is_soft(nr)) {
8523 vmcs12->vm_exit_instruction_len =
8524 vcpu->arch.event_exit_inst_len;
8525 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8526 } else
8527 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8528
8529 if (vcpu->arch.exception.has_error_code) {
8530 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8531 vmcs12->idt_vectoring_error_code =
8532 vcpu->arch.exception.error_code;
8533 }
8534
8535 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8536 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8537 vmcs12->idt_vectoring_info_field =
8538 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8539 } else if (vcpu->arch.interrupt.pending) {
8540 nr = vcpu->arch.interrupt.nr;
8541 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8542
8543 if (vcpu->arch.interrupt.soft) {
8544 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8545 vmcs12->vm_entry_instruction_len =
8546 vcpu->arch.event_exit_inst_len;
8547 } else
8548 idt_vectoring |= INTR_TYPE_EXT_INTR;
8549
8550 vmcs12->idt_vectoring_info_field = idt_vectoring;
8551 }
8552}
8553
b6b8a145
JK		 8554static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8555{
8556 struct vcpu_vmx *vmx = to_vmx(vcpu);
8557
f4124500
JK		 8558 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8559 vmx->nested.preemption_timer_expired) {
8560 if (vmx->nested.nested_run_pending)
8561 return -EBUSY;
8562 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8563 return 0;
8564 }
8565
b6b8a145 8566 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8567 if (vmx->nested.nested_run_pending ||
8568 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8569 return -EBUSY;
8570 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8571 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8572 INTR_INFO_VALID_MASK, 0);
8573 /*
8574 * The NMI-triggered VM exit counts as injection:
8575 * clear this one and block further NMIs.
8576 */
8577 vcpu->arch.nmi_pending = 0;
8578 vmx_set_nmi_mask(vcpu, true);
8579 return 0;
8580 }
8581
8582 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8583 nested_exit_on_intr(vcpu)) {
8584 if (vmx->nested.nested_run_pending)
8585 return -EBUSY;
8586 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8587 }
8588
8589 return 0;
8590}
8591
f4124500
JK		 8592static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8593{
8594 ktime_t remaining =
8595 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8596 u64 value;
8597
8598 if (ktime_to_ns(remaining) <= 0)
8599 return 0;
8600
8601 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8602 do_div(value, 1000000);
8603 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8604}
8605
4704d0be
NHE		 8606/*
8607 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8608 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8609 * and this function updates it to reflect the changes to the guest state while
8610 * L2 was running (and perhaps made some exits which were handled directly by L0
8611 * without going back to L1), and to reflect the exit reason.
8612 * Note that we do not have to copy here all VMCS fields, just those that
8613 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8614 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8615 * which already writes to vmcs12 directly.
8616 */
533558bc
JK		 8617static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8618 u32 exit_reason, u32 exit_intr_info,
8619 unsigned long exit_qualification)
4704d0be
NHE		 8620{
8621 /* update guest state fields: */
8622 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8623 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8624
4704d0be
NHE		 8625 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8626 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8627 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8628
8629 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8630 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8631 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8632 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8633 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8634 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8635 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8636 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8637 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8638 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8639 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8640 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8641 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8642 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8643 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8644 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8645 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8646 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8647 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8648 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8649 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8650 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8651 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8652 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8653 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8654 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8655 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8656 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8657 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8658 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8659 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8660 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8661 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8662 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8663 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8664 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8665
4704d0be
NHE		 8666 vmcs12->guest_interruptibility_info =
8667 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8668 vmcs12->guest_pending_dbg_exceptions =
8669 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8670 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8671 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8672 else
8673 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8674
f4124500
JK		 8675 if (nested_cpu_has_preemption_timer(vmcs12)) {
8676 if (vmcs12->vm_exit_controls &
8677 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8678 vmcs12->vmx_preemption_timer_value =
8679 vmx_get_preemption_timer_value(vcpu);
8680 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8681 }
7854cbca 8682
3633cfc3
NHE		 8683 /*
8684 * In some cases (usually, nested EPT), L2 is allowed to change its
8685 * own CR3 without exiting. If it has changed it, we must keep it.
8686 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8687 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8688 *
8689 * Additionally, restore L2's PDPTR to vmcs12.
8690 */
8691 if (enable_ept) {
8692 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8693 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8694 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8695 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8696 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8697 }
8698
c18911a2
JK		 8699 vmcs12->vm_entry_controls =
8700 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8701 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8702
2996fca0
JK		 8703 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8704 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8705 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8706 }
8707
4704d0be
NHE		 8708 /* TODO: These cannot have changed unless we have MSR bitmaps and
8709 * the relevant bit asks not to trap the change */
b8c07d55 8710 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8711 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8712 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8713 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8714 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8715 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8716 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8717 if (vmx_mpx_supported())
8718 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8719
8720 /* update exit information fields: */
8721
533558bc
JK		 8722 vmcs12->vm_exit_reason = exit_reason;
8723 vmcs12->exit_qualification = exit_qualification;
4704d0be 8724
533558bc 8725 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8726 if ((vmcs12->vm_exit_intr_info &
8727 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8728 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8729 vmcs12->vm_exit_intr_error_code =
8730 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8731 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8732 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8733 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8734
5f3d5799
JK		 8735 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8736 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8737 * instead of reading the real value. */
4704d0be 8738 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8739
8740 /*
8741 * Transfer the event that L0 or L1 may wanted to inject into
8742 * L2 to IDT_VECTORING_INFO_FIELD.
8743 */
8744 vmcs12_save_pending_event(vcpu, vmcs12);
8745 }
8746
8747 /*
8748 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8749 * preserved above and would only end up incorrectly in L1.
8750 */
8751 vcpu->arch.nmi_injected = false;
8752 kvm_clear_exception_queue(vcpu);
8753 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8754}
8755
8756/*
8757 * A part of what we need to when the nested L2 guest exits and we want to
8758 * run its L1 parent, is to reset L1's guest state to the host state specified
8759 * in vmcs12.
8760 * This function is to be called not only on normal nested exit, but also on
8761 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8762 * Failures During or After Loading Guest State").
8763 * This function should be called when the active VMCS is L1's (vmcs01).
8764 */
733568f9
JK		 8765static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8766 struct vmcs12 *vmcs12)
4704d0be 8767{
21feb4eb
ACL		 8768 struct kvm_segment seg;
8769
4704d0be
NHE		 8770 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8771 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8772 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8773 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8774 else
8775 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8776 vmx_set_efer(vcpu, vcpu->arch.efer);
8777
8778 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8779 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8780 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8781 /*
8782 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8783 * actually changed, because it depends on the current state of
8784 * fpu_active (which may have changed).
8785 * Note that vmx_set_cr0 refers to efer set above.
8786 */
9e3e4dbf 8787 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8788 /*
8789 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8790 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8791 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8792 */
8793 update_exception_bitmap(vcpu);
8794 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8795 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8796
8797 /*
8798 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8799 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8800 */
8801 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8802 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8803
29bf08f1 8804 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8805
4704d0be
NHE		 8806 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8807 kvm_mmu_reset_context(vcpu);
8808
feaf0c7d
GN		 8809 if (!enable_ept)
8810 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8811
4704d0be
NHE		 8812 if (enable_vpid) {
8813 /*
8814 * Trivially support vpid by letting L2s share their parent
8815 * L1's vpid. TODO: move to a more elaborate solution, giving
8816 * each L2 its own vpid and exposing the vpid feature to L1.
8817 */
8818 vmx_flush_tlb(vcpu);
8819 }
8820
8821
8822 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8823 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8824 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8825 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8826 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8827
36be0b9d
PB		 8828 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8829 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8830 vmcs_write64(GUEST_BNDCFGS, 0);
8831
44811c02 8832 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8833 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8834 vcpu->arch.pat = vmcs12->host_ia32_pat;
8835 }
4704d0be
NHE		 8836 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8837 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8838 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8839
21feb4eb
ACL		 8840 /* Set L1 segment info according to Intel SDM
8841 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8842 seg = (struct kvm_segment) {
8843 .base = 0,
8844 .limit = 0xFFFFFFFF,
8845 .selector = vmcs12->host_cs_selector,
8846 .type = 11,
8847 .present = 1,
8848 .s = 1,
8849 .g = 1
8850 };
8851 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8852 seg.l = 1;
8853 else
8854 seg.db = 1;
8855 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8856 seg = (struct kvm_segment) {
8857 .base = 0,
8858 .limit = 0xFFFFFFFF,
8859 .type = 3,
8860 .present = 1,
8861 .s = 1,
8862 .db = 1,
8863 .g = 1
8864 };
8865 seg.selector = vmcs12->host_ds_selector;
8866 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8867 seg.selector = vmcs12->host_es_selector;
8868 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8869 seg.selector = vmcs12->host_ss_selector;
8870 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8871 seg.selector = vmcs12->host_fs_selector;
8872 seg.base = vmcs12->host_fs_base;
8873 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8874 seg.selector = vmcs12->host_gs_selector;
8875 seg.base = vmcs12->host_gs_base;
8876 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8877 seg = (struct kvm_segment) {
205befd9 8878 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8879 .limit = 0x67,
8880 .selector = vmcs12->host_tr_selector,
8881 .type = 11,
8882 .present = 1
8883 };
8884 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8885
503cd0c5
JK		 8886 kvm_set_dr(vcpu, 7, 0x400);
8887 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8888}
8889
8890/*
8891 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8892 * and modify vmcs12 to make it see what it would expect to see there if
8893 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8894 */
533558bc
JK		 8895static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8896 u32 exit_intr_info,
8897 unsigned long exit_qualification)
4704d0be
NHE		 8898{
8899 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 8900 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8901
5f3d5799
JK		 8902 /* trying to cancel vmlaunch/vmresume is a bug */
8903 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8904
4704d0be 8905 leave_guest_mode(vcpu);
533558bc
JK		 8906 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8907 exit_qualification);
4704d0be 8908
f3380ca5
WL		 8909 vmx_load_vmcs01(vcpu);
8910
77b0f5d6
BD		 8911 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8912 && nested_exit_intr_ack_set(vcpu)) {
8913 int irq = kvm_cpu_get_interrupt(vcpu);
8914 WARN_ON(irq < 0);
8915 vmcs12->vm_exit_intr_info = irq |
8916 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8917 }
8918
542060ea
JK		 8919 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8920 vmcs12->exit_qualification,
8921 vmcs12->idt_vectoring_info_field,
8922 vmcs12->vm_exit_intr_info,
8923 vmcs12->vm_exit_intr_error_code,
8924 KVM_ISA_VMX);
4704d0be 8925
2961e876
GN		 8926 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8927 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8928 vmx_segment_cache_clear(vmx);
8929
4704d0be
NHE		 8930 /* if no vmcs02 cache requested, remove the one we used */
8931 if (VMCS02_POOL_SIZE == 0)
8932 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8933
8934 load_vmcs12_host_state(vcpu, vmcs12);
8935
27fc51b2 8936 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8937 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8938
8939 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8940 vmx->host_rsp = 0;
8941
8942 /* Unpin physical memory we referred to in vmcs02 */
8943 if (vmx->nested.apic_access_page) {
8944 nested_release_page(vmx->nested.apic_access_page);
48d89b92 8945 vmx->nested.apic_access_page = NULL;
4704d0be 8946 }
a7c0b07d
WL		 8947 if (vmx->nested.virtual_apic_page) {
8948 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 8949 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 8950 }
4704d0be
NHE		 8951
8952 /*
8953 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8954 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8955 * success or failure flag accordingly.
8956 */
8957 if (unlikely(vmx->fail)) {
8958 vmx->fail = 0;
8959 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8960 } else
8961 nested_vmx_succeed(vcpu);
012f83cb
AG		 8962 if (enable_shadow_vmcs)
8963 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8964
8965 /* in case we halted in L2 */
8966 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8967}
8968
42124925
JK		 8969/*
8970 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8971 */
8972static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8973{
8974 if (is_guest_mode(vcpu))
533558bc 8975 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8976 free_nested(to_vmx(vcpu));
8977}
8978
7c177938
NHE		 8979/*
8980 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8981 * 23.7 "VM-entry failures during or after loading guest state" (this also
8982 * lists the acceptable exit-reason and exit-qualification parameters).
8983 * It should only be called before L2 actually succeeded to run, and when
8984 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8985 */
8986static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8987 struct vmcs12 *vmcs12,
8988 u32 reason, unsigned long qualification)
8989{
8990 load_vmcs12_host_state(vcpu, vmcs12);
8991 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8992 vmcs12->exit_qualification = qualification;
8993 nested_vmx_succeed(vcpu);
012f83cb
AG		 8994 if (enable_shadow_vmcs)
8995 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8996}
8997
8a76d7f2
JR		 8998static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8999 struct x86_instruction_info *info,
9000 enum x86_intercept_stage stage)
9001{
9002 return X86EMUL_CONTINUE;
9003}
9004
48d89b92 9005static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9006{
b4a2d31d
RK		 9007 if (ple_gap)
9008 shrink_ple_window(vcpu);
ae97a3b8
RK		 9009}
9010
cbdd1bea 9011static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9012 .cpu_has_kvm_support = cpu_has_kvm_support,
9013 .disabled_by_bios = vmx_disabled_by_bios,
9014 .hardware_setup = hardware_setup,
9015 .hardware_unsetup = hardware_unsetup,
002c7f7c 9016 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9017 .hardware_enable = hardware_enable,
9018 .hardware_disable = hardware_disable,
04547156 9019 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9020
9021 .vcpu_create = vmx_create_vcpu,
9022 .vcpu_free = vmx_free_vcpu,
04d2cc77 9023 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9024
04d2cc77 9025 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9026 .vcpu_load = vmx_vcpu_load,
9027 .vcpu_put = vmx_vcpu_put,
9028
c8639010 9029 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9030 .get_msr = vmx_get_msr,
9031 .set_msr = vmx_set_msr,
9032 .get_segment_base = vmx_get_segment_base,
9033 .get_segment = vmx_get_segment,
9034 .set_segment = vmx_set_segment,
2e4d2653 9035 .get_cpl = vmx_get_cpl,
6aa8b732 9036 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9037 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9038 .decache_cr3 = vmx_decache_cr3,
25c4c276 9039 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9040 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9041 .set_cr3 = vmx_set_cr3,
9042 .set_cr4 = vmx_set_cr4,
6aa8b732 9043 .set_efer = vmx_set_efer,
6aa8b732
AK		 9044 .get_idt = vmx_get_idt,
9045 .set_idt = vmx_set_idt,
9046 .get_gdt = vmx_get_gdt,
9047 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9048 .get_dr6 = vmx_get_dr6,
9049 .set_dr6 = vmx_set_dr6,
020df079 9050 .set_dr7 = vmx_set_dr7,
81908bf4 9051 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9052 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9053 .get_rflags = vmx_get_rflags,
9054 .set_rflags = vmx_set_rflags,
02daab21 9055 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9056
9057 .tlb_flush = vmx_flush_tlb,
6aa8b732 9058
6aa8b732 9059 .run = vmx_vcpu_run,
6062d012 9060 .handle_exit = vmx_handle_exit,
6aa8b732 9061 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9062 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9063 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9064 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9065 .set_irq = vmx_inject_irq,
95ba8273 9066 .set_nmi = vmx_inject_nmi,
298101da 9067 .queue_exception = vmx_queue_exception,
b463a6f7 9068 .cancel_injection = vmx_cancel_injection,
78646121 9069 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9070 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9071 .get_nmi_mask = vmx_get_nmi_mask,
9072 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9073 .enable_nmi_window = enable_nmi_window,
9074 .enable_irq_window = enable_irq_window,
9075 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9076 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 9077 .vm_has_apicv = vmx_vm_has_apicv,
9078 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9079 .hwapic_irr_update = vmx_hwapic_irr_update,
9080 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9081 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9082 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9083
cbc94022 9084 .set_tss_addr = vmx_set_tss_addr,
67253af5 9085 .get_tdp_level = get_ept_level,
4b12f0de 9086 .get_mt_mask = vmx_get_mt_mask,
229456fc 9087
586f9607 9088 .get_exit_info = vmx_get_exit_info,
586f9607 9089
17cc3935 9090 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9091
9092 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9093
9094 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9095 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9096
9097 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9098
9099 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9100
4051b188 9101 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9102 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9103 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9104 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9105 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9106 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9107
9108 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9109
9110 .check_intercept = vmx_check_intercept,
a547c6db 9111 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9112 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9113
9114 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9115
9116 .sched_in = vmx_sched_in,
6aa8b732
AK		 9117};
9118
9119static int __init vmx_init(void)
9120{
8d14695f 9121 int r, i, msr;
26bb0981
AK		 9122
9123 rdmsrl_safe(MSR_EFER, &host_efer);
9124
03916db9 9125 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
26bb0981 9126 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 9127
3e7c73e9 9128 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 9129 if (!vmx_io_bitmap_a)
9130 return -ENOMEM;
9131
2106a548
GC		 9132 r = -ENOMEM;
9133
3e7c73e9 9134 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9135 if (!vmx_io_bitmap_b)
fdef3ad1 9136 goto out;
fdef3ad1 9137
5897297b 9138 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9139 if (!vmx_msr_bitmap_legacy)
25c5f225 9140 goto out1;
2106a548 9141
8d14695f
YZ		 9142 vmx_msr_bitmap_legacy_x2apic =
9143 (unsigned long *)__get_free_page(GFP_KERNEL);
9144 if (!vmx_msr_bitmap_legacy_x2apic)
9145 goto out2;
25c5f225 9146
5897297b 9147 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9148 if (!vmx_msr_bitmap_longmode)
8d14695f 9149 goto out3;
2106a548 9150
8d14695f
YZ		 9151 vmx_msr_bitmap_longmode_x2apic =
9152 (unsigned long *)__get_free_page(GFP_KERNEL);
9153 if (!vmx_msr_bitmap_longmode_x2apic)
9154 goto out4;
4607c2d7
AG		 9155 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9156 if (!vmx_vmread_bitmap)
9157 goto out5;
9158
9159 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9160 if (!vmx_vmwrite_bitmap)
9161 goto out6;
9162
9163 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9164 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 9165
fdef3ad1
HQ		 9166 /*
9167 * Allow direct access to the PC debug port (it is often used for I/O
9168 * delays, but the vmexits simply slow things down).
9169 */
3e7c73e9
AK		 9170 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9171 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 9172
3e7c73e9 9173 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 9174
5897297b
AK		 9175 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9176 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 9177
2384d2b3
SY		 9178 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9179
0ee75bea
AK		 9180 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9181 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9182 if (r)
4607c2d7 9183 goto out7;
25c5f225 9184
8f536b76
ZY		 9185#ifdef CONFIG_KEXEC
9186 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9187 crash_vmclear_local_loaded_vmcss);
9188#endif
9189
5897297b
AK		 9190 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9191 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9192 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9193 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9194 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9195 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 9196 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9197
8d14695f
YZ		 9198 memcpy(vmx_msr_bitmap_legacy_x2apic,
9199 vmx_msr_bitmap_legacy, PAGE_SIZE);
9200 memcpy(vmx_msr_bitmap_longmode_x2apic,
9201 vmx_msr_bitmap_longmode, PAGE_SIZE);
9202
01e439be 9203 if (enable_apicv) {
8d14695f
YZ		 9204 for (msr = 0x800; msr <= 0x8ff; msr++)
9205 vmx_disable_intercept_msr_read_x2apic(msr);
9206
9207 /* According SDM, in x2apic mode, the whole id reg is used.
9208 * But in KVM, it only use the highest eight bits. Need to
9209 * intercept it */
9210 vmx_enable_intercept_msr_read_x2apic(0x802);
9211 /* TMCCT */
9212 vmx_enable_intercept_msr_read_x2apic(0x839);
9213 /* TPR */
9214 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9215 /* EOI */
9216 vmx_disable_intercept_msr_write_x2apic(0x80b);
9217 /* SELF-IPI */
9218 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9219 }
fdef3ad1 9220
089d034e 9221 if (enable_ept) {
3f6d8c8a
XH		 9222 kvm_mmu_set_mask_ptes(0ull,
9223 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9224 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9225 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9226 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9227 kvm_enable_tdp();
9228 } else
9229 kvm_disable_tdp();
1439442c 9230
b4a2d31d
RK		 9231 update_ple_window_actual_max();
9232
fdef3ad1
HQ		 9233 return 0;
9234
4607c2d7
AG		 9235out7:
9236 free_page((unsigned long)vmx_vmwrite_bitmap);
9237out6:
9238 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9239out5:
9240 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9241out4:
5897297b 9242 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9243out3:
9244 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9245out2:
5897297b 9246 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9247out1:
3e7c73e9 9248 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9249out:
3e7c73e9 9250 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9251 return r;
6aa8b732
AK		 9252}
9253
9254static void __exit vmx_exit(void)
9255{
8d14695f
YZ		 9256 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9257 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9258 free_page((unsigned long)vmx_msr_bitmap_legacy);
9259 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9260 free_page((unsigned long)vmx_io_bitmap_b);
9261 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9262 free_page((unsigned long)vmx_vmwrite_bitmap);
9263 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9264
8f536b76 9265#ifdef CONFIG_KEXEC
3b63a43f 9266 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9267 synchronize_rcu();
9268#endif
9269
cb498ea2 9270 kvm_exit();
6aa8b732
AK		 9271}
9272
9273module_init(vmx_init)
9274module_exit(vmx_exit)
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