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KVM: x86: revert "add method to test PIR bitmap vector"
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
20300099
WL		 102static u64 __read_mostly host_xss;
103
843e4330
KH		 104static bool __read_mostly enable_pml = 1;
105module_param_named(pml, enable_pml, bool, S_IRUGO);
106
5037878e
GN		 107#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
108#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 109#define KVM_VM_CR0_ALWAYS_ON \
110 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 111#define KVM_CR4_GUEST_OWNED_BITS \
112 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 113 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 114
cdc0e244
AK		 115#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
116#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
117
78ac8b47
AK		 118#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
119
f4124500
JK		 120#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
121
4b8d54f9
ZE		 122/*
123 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
124 * ple_gap: upper bound on the amount of time between two successive
125 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 126 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 127 * ple_window: upper bound on the amount of time a guest is allowed to execute
128 * in a PAUSE loop. Tests indicate that most spinlocks are held for
129 * less than 2^12 cycles
130 * Time is measured based on a counter that runs at the same rate as the TSC,
131 * refer SDM volume 3b section 21.6.13 & 22.1.3.
132 */
b4a2d31d
RK		 133#define KVM_VMX_DEFAULT_PLE_GAP 128
134#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
135#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
136#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
137#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
138 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
139
4b8d54f9
ZE		 140static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
141module_param(ple_gap, int, S_IRUGO);
142
143static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
144module_param(ple_window, int, S_IRUGO);
145
b4a2d31d
RK		 146/* Default doubles per-vcpu window every exit. */
147static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
148module_param(ple_window_grow, int, S_IRUGO);
149
150/* Default resets per-vcpu window every exit to ple_window. */
151static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
152module_param(ple_window_shrink, int, S_IRUGO);
153
154/* Default is to compute the maximum so we can never overflow. */
155static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
156static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157module_param(ple_window_max, int, S_IRUGO);
158
83287ea4
AK		 159extern const ulong vmx_return;
160
8bf00a52 161#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 162#define VMCS02_POOL_SIZE 1
61d2ef2c 163
a2fa3e9f
GH		 164struct vmcs {
165 u32 revision_id;
166 u32 abort;
167 char data[0];
168};
169
d462b819
NHE		 170/*
171 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
172 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
173 * loaded on this CPU (so we can clear them if the CPU goes down).
174 */
175struct loaded_vmcs {
176 struct vmcs *vmcs;
177 int cpu;
178 int launched;
179 struct list_head loaded_vmcss_on_cpu_link;
180};
181
26bb0981
AK		 182struct shared_msr_entry {
183 unsigned index;
184 u64 data;
d5696725 185 u64 mask;
26bb0981
AK		 186};
187
a9d30f33
NHE		 188/*
189 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
190 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
191 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
192 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
193 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
194 * More than one of these structures may exist, if L1 runs multiple L2 guests.
195 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
196 * underlying hardware which will be used to run L2.
197 * This structure is packed to ensure that its layout is identical across
198 * machines (necessary for live migration).
199 * If there are changes in this struct, VMCS12_REVISION must be changed.
200 */
22bd0358 201typedef u64 natural_width;
a9d30f33
NHE		 202struct __packed vmcs12 {
203 /* According to the Intel spec, a VMCS region must start with the
204 * following two fields. Then follow implementation-specific data.
205 */
206 u32 revision_id;
207 u32 abort;
22bd0358 208
27d6c865
NHE		 209 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
210 u32 padding[7]; /* room for future expansion */
211
22bd0358
NHE		 212 u64 io_bitmap_a;
213 u64 io_bitmap_b;
214 u64 msr_bitmap;
215 u64 vm_exit_msr_store_addr;
216 u64 vm_exit_msr_load_addr;
217 u64 vm_entry_msr_load_addr;
218 u64 tsc_offset;
219 u64 virtual_apic_page_addr;
220 u64 apic_access_addr;
221 u64 ept_pointer;
81dc01f7 222 u64 xss_exit_bitmap;
22bd0358
NHE		 223 u64 guest_physical_address;
224 u64 vmcs_link_pointer;
225 u64 guest_ia32_debugctl;
226 u64 guest_ia32_pat;
227 u64 guest_ia32_efer;
228 u64 guest_ia32_perf_global_ctrl;
229 u64 guest_pdptr0;
230 u64 guest_pdptr1;
231 u64 guest_pdptr2;
232 u64 guest_pdptr3;
36be0b9d 233 u64 guest_bndcfgs;
22bd0358
NHE		 234 u64 host_ia32_pat;
235 u64 host_ia32_efer;
236 u64 host_ia32_perf_global_ctrl;
237 u64 padding64[8]; /* room for future expansion */
238 /*
239 * To allow migration of L1 (complete with its L2 guests) between
240 * machines of different natural widths (32 or 64 bit), we cannot have
241 * unsigned long fields with no explict size. We use u64 (aliased
242 * natural_width) instead. Luckily, x86 is little-endian.
243 */
244 natural_width cr0_guest_host_mask;
245 natural_width cr4_guest_host_mask;
246 natural_width cr0_read_shadow;
247 natural_width cr4_read_shadow;
248 natural_width cr3_target_value0;
249 natural_width cr3_target_value1;
250 natural_width cr3_target_value2;
251 natural_width cr3_target_value3;
252 natural_width exit_qualification;
253 natural_width guest_linear_address;
254 natural_width guest_cr0;
255 natural_width guest_cr3;
256 natural_width guest_cr4;
257 natural_width guest_es_base;
258 natural_width guest_cs_base;
259 natural_width guest_ss_base;
260 natural_width guest_ds_base;
261 natural_width guest_fs_base;
262 natural_width guest_gs_base;
263 natural_width guest_ldtr_base;
264 natural_width guest_tr_base;
265 natural_width guest_gdtr_base;
266 natural_width guest_idtr_base;
267 natural_width guest_dr7;
268 natural_width guest_rsp;
269 natural_width guest_rip;
270 natural_width guest_rflags;
271 natural_width guest_pending_dbg_exceptions;
272 natural_width guest_sysenter_esp;
273 natural_width guest_sysenter_eip;
274 natural_width host_cr0;
275 natural_width host_cr3;
276 natural_width host_cr4;
277 natural_width host_fs_base;
278 natural_width host_gs_base;
279 natural_width host_tr_base;
280 natural_width host_gdtr_base;
281 natural_width host_idtr_base;
282 natural_width host_ia32_sysenter_esp;
283 natural_width host_ia32_sysenter_eip;
284 natural_width host_rsp;
285 natural_width host_rip;
286 natural_width paddingl[8]; /* room for future expansion */
287 u32 pin_based_vm_exec_control;
288 u32 cpu_based_vm_exec_control;
289 u32 exception_bitmap;
290 u32 page_fault_error_code_mask;
291 u32 page_fault_error_code_match;
292 u32 cr3_target_count;
293 u32 vm_exit_controls;
294 u32 vm_exit_msr_store_count;
295 u32 vm_exit_msr_load_count;
296 u32 vm_entry_controls;
297 u32 vm_entry_msr_load_count;
298 u32 vm_entry_intr_info_field;
299 u32 vm_entry_exception_error_code;
300 u32 vm_entry_instruction_len;
301 u32 tpr_threshold;
302 u32 secondary_vm_exec_control;
303 u32 vm_instruction_error;
304 u32 vm_exit_reason;
305 u32 vm_exit_intr_info;
306 u32 vm_exit_intr_error_code;
307 u32 idt_vectoring_info_field;
308 u32 idt_vectoring_error_code;
309 u32 vm_exit_instruction_len;
310 u32 vmx_instruction_info;
311 u32 guest_es_limit;
312 u32 guest_cs_limit;
313 u32 guest_ss_limit;
314 u32 guest_ds_limit;
315 u32 guest_fs_limit;
316 u32 guest_gs_limit;
317 u32 guest_ldtr_limit;
318 u32 guest_tr_limit;
319 u32 guest_gdtr_limit;
320 u32 guest_idtr_limit;
321 u32 guest_es_ar_bytes;
322 u32 guest_cs_ar_bytes;
323 u32 guest_ss_ar_bytes;
324 u32 guest_ds_ar_bytes;
325 u32 guest_fs_ar_bytes;
326 u32 guest_gs_ar_bytes;
327 u32 guest_ldtr_ar_bytes;
328 u32 guest_tr_ar_bytes;
329 u32 guest_interruptibility_info;
330 u32 guest_activity_state;
331 u32 guest_sysenter_cs;
332 u32 host_ia32_sysenter_cs;
0238ea91
JK		 333 u32 vmx_preemption_timer_value;
334 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 335 u16 virtual_processor_id;
336 u16 guest_es_selector;
337 u16 guest_cs_selector;
338 u16 guest_ss_selector;
339 u16 guest_ds_selector;
340 u16 guest_fs_selector;
341 u16 guest_gs_selector;
342 u16 guest_ldtr_selector;
343 u16 guest_tr_selector;
344 u16 host_es_selector;
345 u16 host_cs_selector;
346 u16 host_ss_selector;
347 u16 host_ds_selector;
348 u16 host_fs_selector;
349 u16 host_gs_selector;
350 u16 host_tr_selector;
a9d30f33
NHE		 351};
352
353/*
354 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
355 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
356 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
357 */
358#define VMCS12_REVISION 0x11e57ed0
359
360/*
361 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
362 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
363 * current implementation, 4K are reserved to avoid future complications.
364 */
365#define VMCS12_SIZE 0x1000
366
ff2f6fe9
NHE		 367/* Used to remember the last vmcs02 used for some recently used vmcs12s */
368struct vmcs02_list {
369 struct list_head list;
370 gpa_t vmptr;
371 struct loaded_vmcs vmcs02;
372};
373
ec378aee
NHE		 374/*
375 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
376 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
377 */
378struct nested_vmx {
379 /* Has the level1 guest done vmxon? */
380 bool vmxon;
3573e22c 381 gpa_t vmxon_ptr;
a9d30f33
NHE		 382
383 /* The guest-physical address of the current VMCS L1 keeps for L2 */
384 gpa_t current_vmptr;
385 /* The host-usable pointer to the above */
386 struct page *current_vmcs12_page;
387 struct vmcs12 *current_vmcs12;
8de48833 388 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 389 /*
390 * Indicates if the shadow vmcs must be updated with the
391 * data hold by vmcs12
392 */
393 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 394
395 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
396 struct list_head vmcs02_pool;
397 int vmcs02_num;
fe3ef05c 398 u64 vmcs01_tsc_offset;
644d711a
NHE		 399 /* L2 must run next, and mustn't decide to exit to L1. */
400 bool nested_run_pending;
fe3ef05c
NHE		 401 /*
402 * Guest pages referred to in vmcs02 with host-physical pointers, so
403 * we must keep them pinned while L2 runs.
404 */
405 struct page *apic_access_page;
a7c0b07d 406 struct page *virtual_apic_page;
b3897a49 407 u64 msr_ia32_feature_control;
f4124500
JK		 408
409 struct hrtimer preemption_timer;
410 bool preemption_timer_expired;
2996fca0
JK		 411
412 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
413 u64 vmcs01_debugctl;
ec378aee
NHE		 414};
415
01e439be
YZ		 416#define POSTED_INTR_ON 0
417/* Posted-Interrupt Descriptor */
418struct pi_desc {
419 u32 pir[8]; /* Posted interrupt requested */
420 u32 control; /* bit 0 of control is outstanding notification bit */
421 u32 rsvd[7];
422} __aligned(64);
423
a20ed54d
YZ		 424static bool pi_test_and_set_on(struct pi_desc *pi_desc)
425{
426 return test_and_set_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
431{
432 return test_and_clear_bit(POSTED_INTR_ON,
433 (unsigned long *)&pi_desc->control);
434}
435
436static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
437{
438 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
439}
440
a2fa3e9f 441struct vcpu_vmx {
fb3f0f51 442 struct kvm_vcpu vcpu;
313dbd49 443 unsigned long host_rsp;
29bd8a78 444 u8 fail;
9d58b931 445 bool nmi_known_unmasked;
51aa01d1 446 u32 exit_intr_info;
1155f76a 447 u32 idt_vectoring_info;
6de12732 448 ulong rflags;
26bb0981 449 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 450 int nmsrs;
451 int save_nmsrs;
a547c6db 452 unsigned long host_idt_base;
a2fa3e9f 453#ifdef CONFIG_X86_64
44ea2b17
AK		 454 u64 msr_host_kernel_gs_base;
455 u64 msr_guest_kernel_gs_base;
a2fa3e9f 456#endif
2961e876
GN		 457 u32 vm_entry_controls_shadow;
458 u32 vm_exit_controls_shadow;
d462b819
NHE		 459 /*
460 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
461 * non-nested (L1) guest, it always points to vmcs01. For a nested
462 * guest (L2), it points to a different VMCS.
463 */
464 struct loaded_vmcs vmcs01;
465 struct loaded_vmcs *loaded_vmcs;
466 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 467 struct msr_autoload {
468 unsigned nr;
469 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
470 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
471 } msr_autoload;
a2fa3e9f
GH		 472 struct {
473 int loaded;
474 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 475#ifdef CONFIG_X86_64
476 u16 ds_sel, es_sel;
477#endif
152d3f2f
LV		 478 int gs_ldt_reload_needed;
479 int fs_reload_needed;
da8999d3 480 u64 msr_host_bndcfgs;
d974baa3 481 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 482 } host_state;
9c8cba37 483 struct {
7ffd92c5 484 int vm86_active;
78ac8b47 485 ulong save_rflags;
f5f7b2fe
AK		 486 struct kvm_segment segs[8];
487 } rmode;
488 struct {
489 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 490 struct kvm_save_segment {
491 u16 selector;
492 unsigned long base;
493 u32 limit;
494 u32 ar;
f5f7b2fe 495 } seg[8];
2fb92db1 496 } segment_cache;
2384d2b3 497 int vpid;
04fa4d32 498 bool emulation_required;
3b86cd99
JK		 499
500 /* Support for vnmi-less CPUs */
501 int soft_vnmi_blocked;
502 ktime_t entry_time;
503 s64 vnmi_blocked_time;
a0861c02 504 u32 exit_reason;
4e47c7a6
SY		 505
506 bool rdtscp_enabled;
ec378aee 507
01e439be
YZ		 508 /* Posted interrupt descriptor */
509 struct pi_desc pi_desc;
510
ec378aee
NHE		 511 /* Support for a guest hypervisor (nested VMX) */
512 struct nested_vmx nested;
a7653ecd
RK		 513
514 /* Dynamic PLE window. */
515 int ple_window;
516 bool ple_window_dirty;
843e4330
KH		 517
518 /* Support for PML */
519#define PML_ENTITY_NUM 512
520 struct page *pml_pg;
a2fa3e9f
GH		 521};
522
2fb92db1
AK		 523enum segment_cache_field {
524 SEG_FIELD_SEL = 0,
525 SEG_FIELD_BASE = 1,
526 SEG_FIELD_LIMIT = 2,
527 SEG_FIELD_AR = 3,
528
529 SEG_FIELD_NR = 4
530};
531
a2fa3e9f
GH		 532static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
533{
fb3f0f51 534 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 535}
536
22bd0358
NHE		 537#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
538#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
539#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
540 [number##_HIGH] = VMCS12_OFFSET(name)+4
541
4607c2d7 542
fe2b201b 543static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 544 /*
545 * We do NOT shadow fields that are modified when L0
546 * traps and emulates any vmx instruction (e.g. VMPTRLD,
547 * VMXON...) executed by L1.
548 * For example, VM_INSTRUCTION_ERROR is read
549 * by L1 if a vmx instruction fails (part of the error path).
550 * Note the code assumes this logic. If for some reason
551 * we start shadowing these fields then we need to
552 * force a shadow sync when L0 emulates vmx instructions
553 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
554 * by nested_vmx_failValid)
555 */
556 VM_EXIT_REASON,
557 VM_EXIT_INTR_INFO,
558 VM_EXIT_INSTRUCTION_LEN,
559 IDT_VECTORING_INFO_FIELD,
560 IDT_VECTORING_ERROR_CODE,
561 VM_EXIT_INTR_ERROR_CODE,
562 EXIT_QUALIFICATION,
563 GUEST_LINEAR_ADDRESS,
564 GUEST_PHYSICAL_ADDRESS
565};
fe2b201b 566static int max_shadow_read_only_fields =
4607c2d7
AG		 567 ARRAY_SIZE(shadow_read_only_fields);
568
fe2b201b 569static unsigned long shadow_read_write_fields[] = {
a7c0b07d 570 TPR_THRESHOLD,
4607c2d7
AG		 571 GUEST_RIP,
572 GUEST_RSP,
573 GUEST_CR0,
574 GUEST_CR3,
575 GUEST_CR4,
576 GUEST_INTERRUPTIBILITY_INFO,
577 GUEST_RFLAGS,
578 GUEST_CS_SELECTOR,
579 GUEST_CS_AR_BYTES,
580 GUEST_CS_LIMIT,
581 GUEST_CS_BASE,
582 GUEST_ES_BASE,
36be0b9d 583 GUEST_BNDCFGS,
4607c2d7
AG		 584 CR0_GUEST_HOST_MASK,
585 CR0_READ_SHADOW,
586 CR4_READ_SHADOW,
587 TSC_OFFSET,
588 EXCEPTION_BITMAP,
589 CPU_BASED_VM_EXEC_CONTROL,
590 VM_ENTRY_EXCEPTION_ERROR_CODE,
591 VM_ENTRY_INTR_INFO_FIELD,
592 VM_ENTRY_INSTRUCTION_LEN,
593 VM_ENTRY_EXCEPTION_ERROR_CODE,
594 HOST_FS_BASE,
595 HOST_GS_BASE,
596 HOST_FS_SELECTOR,
597 HOST_GS_SELECTOR
598};
fe2b201b 599static int max_shadow_read_write_fields =
4607c2d7
AG		 600 ARRAY_SIZE(shadow_read_write_fields);
601
772e0318 602static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 603 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
604 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
605 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
606 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
607 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
608 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
609 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
610 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
611 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
612 FIELD(HOST_ES_SELECTOR, host_es_selector),
613 FIELD(HOST_CS_SELECTOR, host_cs_selector),
614 FIELD(HOST_SS_SELECTOR, host_ss_selector),
615 FIELD(HOST_DS_SELECTOR, host_ds_selector),
616 FIELD(HOST_FS_SELECTOR, host_fs_selector),
617 FIELD(HOST_GS_SELECTOR, host_gs_selector),
618 FIELD(HOST_TR_SELECTOR, host_tr_selector),
619 FIELD64(IO_BITMAP_A, io_bitmap_a),
620 FIELD64(IO_BITMAP_B, io_bitmap_b),
621 FIELD64(MSR_BITMAP, msr_bitmap),
622 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
623 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
624 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
625 FIELD64(TSC_OFFSET, tsc_offset),
626 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
627 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
628 FIELD64(EPT_POINTER, ept_pointer),
81dc01f7 629 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 630 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
631 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
632 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
633 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
634 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
635 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
636 FIELD64(GUEST_PDPTR0, guest_pdptr0),
637 FIELD64(GUEST_PDPTR1, guest_pdptr1),
638 FIELD64(GUEST_PDPTR2, guest_pdptr2),
639 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 640 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 641 FIELD64(HOST_IA32_PAT, host_ia32_pat),
642 FIELD64(HOST_IA32_EFER, host_ia32_efer),
643 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
644 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
645 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
646 FIELD(EXCEPTION_BITMAP, exception_bitmap),
647 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
648 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
649 FIELD(CR3_TARGET_COUNT, cr3_target_count),
650 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
651 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
652 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
653 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
654 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
655 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
656 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
657 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
658 FIELD(TPR_THRESHOLD, tpr_threshold),
659 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
660 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
661 FIELD(VM_EXIT_REASON, vm_exit_reason),
662 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
663 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
664 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
665 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
666 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
667 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
668 FIELD(GUEST_ES_LIMIT, guest_es_limit),
669 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
670 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
671 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
672 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
673 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
674 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
675 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
676 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
677 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
678 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
679 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
680 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
681 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
682 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
683 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
684 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
685 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
686 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
687 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
688 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
689 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 690 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 691 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
692 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
693 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
694 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
695 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
696 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
697 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
698 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
699 FIELD(EXIT_QUALIFICATION, exit_qualification),
700 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
701 FIELD(GUEST_CR0, guest_cr0),
702 FIELD(GUEST_CR3, guest_cr3),
703 FIELD(GUEST_CR4, guest_cr4),
704 FIELD(GUEST_ES_BASE, guest_es_base),
705 FIELD(GUEST_CS_BASE, guest_cs_base),
706 FIELD(GUEST_SS_BASE, guest_ss_base),
707 FIELD(GUEST_DS_BASE, guest_ds_base),
708 FIELD(GUEST_FS_BASE, guest_fs_base),
709 FIELD(GUEST_GS_BASE, guest_gs_base),
710 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
711 FIELD(GUEST_TR_BASE, guest_tr_base),
712 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
713 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
714 FIELD(GUEST_DR7, guest_dr7),
715 FIELD(GUEST_RSP, guest_rsp),
716 FIELD(GUEST_RIP, guest_rip),
717 FIELD(GUEST_RFLAGS, guest_rflags),
718 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
719 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
720 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
721 FIELD(HOST_CR0, host_cr0),
722 FIELD(HOST_CR3, host_cr3),
723 FIELD(HOST_CR4, host_cr4),
724 FIELD(HOST_FS_BASE, host_fs_base),
725 FIELD(HOST_GS_BASE, host_gs_base),
726 FIELD(HOST_TR_BASE, host_tr_base),
727 FIELD(HOST_GDTR_BASE, host_gdtr_base),
728 FIELD(HOST_IDTR_BASE, host_idtr_base),
729 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
730 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
731 FIELD(HOST_RSP, host_rsp),
732 FIELD(HOST_RIP, host_rip),
733};
22bd0358
NHE		 734
735static inline short vmcs_field_to_offset(unsigned long field)
736{
a2ae9df7
PB		 737 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
738
739 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
740 vmcs_field_to_offset_table[field] == 0)
741 return -ENOENT;
742
22bd0358
NHE		 743 return vmcs_field_to_offset_table[field];
744}
745
a9d30f33
NHE		 746static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
747{
748 return to_vmx(vcpu)->nested.current_vmcs12;
749}
750
751static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
752{
753 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 754 if (is_error_page(page))
a9d30f33 755 return NULL;
32cad84f 756
a9d30f33
NHE		 757 return page;
758}
759
760static void nested_release_page(struct page *page)
761{
762 kvm_release_page_dirty(page);
763}
764
765static void nested_release_page_clean(struct page *page)
766{
767 kvm_release_page_clean(page);
768}
769
bfd0a56b 770static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 771static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 772static void kvm_cpu_vmxon(u64 addr);
773static void kvm_cpu_vmxoff(void);
93c4adc7 774static bool vmx_mpx_supported(void);
f53cd63c 775static bool vmx_xsaves_supported(void);
776e58ea 776static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 777static void vmx_set_segment(struct kvm_vcpu *vcpu,
778 struct kvm_segment *var, int seg);
779static void vmx_get_segment(struct kvm_vcpu *vcpu,
780 struct kvm_segment *var, int seg);
d99e4152
GN		 781static bool guest_state_valid(struct kvm_vcpu *vcpu);
782static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 783static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 784static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 785static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 786static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 787
6aa8b732
AK		 788static DEFINE_PER_CPU(struct vmcs *, vmxarea);
789static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 790/*
791 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
792 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
793 */
794static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 795static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 796
3e7c73e9
AK		 797static unsigned long *vmx_io_bitmap_a;
798static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 799static unsigned long *vmx_msr_bitmap_legacy;
800static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 801static unsigned long *vmx_msr_bitmap_legacy_x2apic;
802static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 803static unsigned long *vmx_vmread_bitmap;
804static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 805
110312c8 806static bool cpu_has_load_ia32_efer;
8bf00a52 807static bool cpu_has_load_perf_global_ctrl;
110312c8 808
2384d2b3
SY		 809static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
810static DEFINE_SPINLOCK(vmx_vpid_lock);
811
1c3d14fe 812static struct vmcs_config {
6aa8b732
AK		 813 int size;
814 int order;
815 u32 revision_id;
1c3d14fe
YS		 816 u32 pin_based_exec_ctrl;
817 u32 cpu_based_exec_ctrl;
f78e0e2e 818 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 819 u32 vmexit_ctrl;
820 u32 vmentry_ctrl;
821} vmcs_config;
6aa8b732 822
efff9e53 823static struct vmx_capability {
d56f546d
SY		 824 u32 ept;
825 u32 vpid;
826} vmx_capability;
827
6aa8b732
AK		 828#define VMX_SEGMENT_FIELD(seg) \
829 [VCPU_SREG_##seg] = { \
830 .selector = GUEST_##seg##_SELECTOR, \
831 .base = GUEST_##seg##_BASE, \
832 .limit = GUEST_##seg##_LIMIT, \
833 .ar_bytes = GUEST_##seg##_AR_BYTES, \
834 }
835
772e0318 836static const struct kvm_vmx_segment_field {
6aa8b732
AK		 837 unsigned selector;
838 unsigned base;
839 unsigned limit;
840 unsigned ar_bytes;
841} kvm_vmx_segment_fields[] = {
842 VMX_SEGMENT_FIELD(CS),
843 VMX_SEGMENT_FIELD(DS),
844 VMX_SEGMENT_FIELD(ES),
845 VMX_SEGMENT_FIELD(FS),
846 VMX_SEGMENT_FIELD(GS),
847 VMX_SEGMENT_FIELD(SS),
848 VMX_SEGMENT_FIELD(TR),
849 VMX_SEGMENT_FIELD(LDTR),
850};
851
26bb0981
AK		 852static u64 host_efer;
853
6de4f3ad
AK		 854static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
855
4d56c8a7 856/*
8c06585d 857 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 858 * away by decrementing the array size.
859 */
6aa8b732 860static const u32 vmx_msr_index[] = {
05b3e0c2 861#ifdef CONFIG_X86_64
44ea2b17 862 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 863#endif
8c06585d 864 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 865};
6aa8b732 866
31299944 867static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 868{
869 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
870 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 871 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 872}
873
31299944 874static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 875{
876 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
877 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 878 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 879}
880
31299944 881static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 882{
883 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
884 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 885 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 886}
887
31299944 888static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 889{
890 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
891 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
892}
893
31299944 894static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 895{
896 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
897 INTR_INFO_VALID_MASK)) ==
898 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
899}
900
31299944 901static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 902{
04547156 903 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 904}
905
31299944 906static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 907{
04547156 908 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 909}
910
31299944 911static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 912{
04547156 913 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 914}
915
31299944 916static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 917{
04547156
SY		 918 return vmcs_config.cpu_based_exec_ctrl &
919 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 920}
921
774ead3a 922static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 923{
04547156
SY		 924 return vmcs_config.cpu_based_2nd_exec_ctrl &
925 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
926}
927
8d14695f
YZ		 928static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
929{
930 return vmcs_config.cpu_based_2nd_exec_ctrl &
931 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
932}
933
83d4c286
YZ		 934static inline bool cpu_has_vmx_apic_register_virt(void)
935{
936 return vmcs_config.cpu_based_2nd_exec_ctrl &
937 SECONDARY_EXEC_APIC_REGISTER_VIRT;
938}
939
c7c9c56c
YZ		 940static inline bool cpu_has_vmx_virtual_intr_delivery(void)
941{
942 return vmcs_config.cpu_based_2nd_exec_ctrl &
943 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
944}
945
01e439be
YZ		 946static inline bool cpu_has_vmx_posted_intr(void)
947{
948 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
949}
950
951static inline bool cpu_has_vmx_apicv(void)
952{
953 return cpu_has_vmx_apic_register_virt() &&
954 cpu_has_vmx_virtual_intr_delivery() &&
955 cpu_has_vmx_posted_intr();
956}
957
04547156
SY		 958static inline bool cpu_has_vmx_flexpriority(void)
959{
960 return cpu_has_vmx_tpr_shadow() &&
961 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 962}
963
e799794e
MT		 964static inline bool cpu_has_vmx_ept_execute_only(void)
965{
31299944 966 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 967}
968
e799794e
MT		 969static inline bool cpu_has_vmx_ept_2m_page(void)
970{
31299944 971 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 972}
973
878403b7
SY		 974static inline bool cpu_has_vmx_ept_1g_page(void)
975{
31299944 976 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 977}
978
4bc9b982
SY		 979static inline bool cpu_has_vmx_ept_4levels(void)
980{
981 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
982}
983
83c3a331
XH		 984static inline bool cpu_has_vmx_ept_ad_bits(void)
985{
986 return vmx_capability.ept & VMX_EPT_AD_BIT;
987}
988
31299944 989static inline bool cpu_has_vmx_invept_context(void)
d56f546d 990{
31299944 991 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 992}
993
31299944 994static inline bool cpu_has_vmx_invept_global(void)
d56f546d 995{
31299944 996 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 997}
998
518c8aee
GJ		 999static inline bool cpu_has_vmx_invvpid_single(void)
1000{
1001 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1002}
1003
b9d762fa
GJ		 1004static inline bool cpu_has_vmx_invvpid_global(void)
1005{
1006 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1007}
1008
31299944 1009static inline bool cpu_has_vmx_ept(void)
d56f546d 1010{
04547156
SY		 1011 return vmcs_config.cpu_based_2nd_exec_ctrl &
1012 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1013}
1014
31299944 1015static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1016{
1017 return vmcs_config.cpu_based_2nd_exec_ctrl &
1018 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1019}
1020
31299944 1021static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1022{
1023 return vmcs_config.cpu_based_2nd_exec_ctrl &
1024 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1025}
1026
31299944 1027static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1028{
6d3e435e 1029 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1033{
04547156
SY		 1034 return vmcs_config.cpu_based_2nd_exec_ctrl &
1035 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1036}
1037
31299944 1038static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1039{
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_RDTSCP;
1042}
1043
ad756a16
MJ		 1044static inline bool cpu_has_vmx_invpcid(void)
1045{
1046 return vmcs_config.cpu_based_2nd_exec_ctrl &
1047 SECONDARY_EXEC_ENABLE_INVPCID;
1048}
1049
31299944 1050static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1051{
1052 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1053}
1054
f5f48ee1
SY		 1055static inline bool cpu_has_vmx_wbinvd_exit(void)
1056{
1057 return vmcs_config.cpu_based_2nd_exec_ctrl &
1058 SECONDARY_EXEC_WBINVD_EXITING;
1059}
1060
abc4fc58
AG		 1061static inline bool cpu_has_vmx_shadow_vmcs(void)
1062{
1063 u64 vmx_msr;
1064 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1065 /* check if the cpu supports writing r/o exit information fields */
1066 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1067 return false;
1068
1069 return vmcs_config.cpu_based_2nd_exec_ctrl &
1070 SECONDARY_EXEC_SHADOW_VMCS;
1071}
1072
843e4330
KH		 1073static inline bool cpu_has_vmx_pml(void)
1074{
1075 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1076}
1077
04547156
SY		 1078static inline bool report_flexpriority(void)
1079{
1080 return flexpriority_enabled;
1081}
1082
fe3ef05c
NHE		 1083static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1084{
1085 return vmcs12->cpu_based_vm_exec_control & bit;
1086}
1087
1088static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1089{
1090 return (vmcs12->cpu_based_vm_exec_control &
1091 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1092 (vmcs12->secondary_vm_exec_control & bit);
1093}
1094
f5c4368f 1095static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1096{
1097 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1098}
1099
f4124500
JK		 1100static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1101{
1102 return vmcs12->pin_based_vm_exec_control &
1103 PIN_BASED_VMX_PREEMPTION_TIMER;
1104}
1105
155a97a3
NHE		 1106static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1107{
1108 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1109}
1110
81dc01f7
WL		 1111static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1112{
1113 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1114 vmx_xsaves_supported();
1115}
1116
644d711a
NHE		 1117static inline bool is_exception(u32 intr_info)
1118{
1119 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1120 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1121}
1122
533558bc
JK		 1123static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1124 u32 exit_intr_info,
1125 unsigned long exit_qualification);
7c177938
NHE		 1126static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1127 struct vmcs12 *vmcs12,
1128 u32 reason, unsigned long qualification);
1129
8b9cf98c 1130static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1131{
1132 int i;
1133
a2fa3e9f 1134 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1135 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1136 return i;
1137 return -1;
1138}
1139
2384d2b3
SY		 1140static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1141{
1142 struct {
1143 u64 vpid : 16;
1144 u64 rsvd : 48;
1145 u64 gva;
1146 } operand = { vpid, 0, gva };
1147
4ecac3fd 1148 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1149 /* CF==1 or ZF==1 --> rc = -1 */
1150 "; ja 1f ; ud2 ; 1:"
1151 : : "a"(&operand), "c"(ext) : "cc", "memory");
1152}
1153
1439442c
SY		 1154static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1155{
1156 struct {
1157 u64 eptp, gpa;
1158 } operand = {eptp, gpa};
1159
4ecac3fd 1160 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1161 /* CF==1 or ZF==1 --> rc = -1 */
1162 "; ja 1f ; ud2 ; 1:\n"
1163 : : "a" (&operand), "c" (ext) : "cc", "memory");
1164}
1165
26bb0981 1166static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1167{
1168 int i;
1169
8b9cf98c 1170 i = __find_msr_index(vmx, msr);
a75beee6 1171 if (i >= 0)
a2fa3e9f 1172 return &vmx->guest_msrs[i];
8b6d44c7 1173 return NULL;
7725f0ba
AK		 1174}
1175
6aa8b732
AK		 1176static void vmcs_clear(struct vmcs *vmcs)
1177{
1178 u64 phys_addr = __pa(vmcs);
1179 u8 error;
1180
4ecac3fd 1181 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1182 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1183 : "cc", "memory");
1184 if (error)
1185 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1186 vmcs, phys_addr);
1187}
1188
d462b819
NHE		 1189static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1190{
1191 vmcs_clear(loaded_vmcs->vmcs);
1192 loaded_vmcs->cpu = -1;
1193 loaded_vmcs->launched = 0;
1194}
1195
7725b894
DX		 1196static void vmcs_load(struct vmcs *vmcs)
1197{
1198 u64 phys_addr = __pa(vmcs);
1199 u8 error;
1200
1201 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1202 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1203 : "cc", "memory");
1204 if (error)
2844d849 1205 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1206 vmcs, phys_addr);
1207}
1208
8f536b76
ZY		 1209#ifdef CONFIG_KEXEC
1210/*
1211 * This bitmap is used to indicate whether the vmclear
1212 * operation is enabled on all cpus. All disabled by
1213 * default.
1214 */
1215static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1216
1217static inline void crash_enable_local_vmclear(int cpu)
1218{
1219 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1220}
1221
1222static inline void crash_disable_local_vmclear(int cpu)
1223{
1224 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1225}
1226
1227static inline int crash_local_vmclear_enabled(int cpu)
1228{
1229 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1230}
1231
1232static void crash_vmclear_local_loaded_vmcss(void)
1233{
1234 int cpu = raw_smp_processor_id();
1235 struct loaded_vmcs *v;
1236
1237 if (!crash_local_vmclear_enabled(cpu))
1238 return;
1239
1240 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1241 loaded_vmcss_on_cpu_link)
1242 vmcs_clear(v->vmcs);
1243}
1244#else
1245static inline void crash_enable_local_vmclear(int cpu) { }
1246static inline void crash_disable_local_vmclear(int cpu) { }
1247#endif /* CONFIG_KEXEC */
1248
d462b819 1249static void __loaded_vmcs_clear(void *arg)
6aa8b732 1250{
d462b819 1251 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1252 int cpu = raw_smp_processor_id();
6aa8b732 1253
d462b819
NHE		 1254 if (loaded_vmcs->cpu != cpu)
1255 return; /* vcpu migration can race with cpu offline */
1256 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1257 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1258 crash_disable_local_vmclear(cpu);
d462b819 1259 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1260
1261 /*
1262 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1263 * is before setting loaded_vmcs->vcpu to -1 which is done in
1264 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1265 * then adds the vmcs into percpu list before it is deleted.
1266 */
1267 smp_wmb();
1268
d462b819 1269 loaded_vmcs_init(loaded_vmcs);
8f536b76 1270 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1271}
1272
d462b819 1273static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1274{
e6c7d321
XG		 1275 int cpu = loaded_vmcs->cpu;
1276
1277 if (cpu != -1)
1278 smp_call_function_single(cpu,
1279 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1280}
1281
1760dd49 1282static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1283{
1284 if (vmx->vpid == 0)
1285 return;
1286
518c8aee
GJ		 1287 if (cpu_has_vmx_invvpid_single())
1288 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1289}
1290
b9d762fa
GJ		 1291static inline void vpid_sync_vcpu_global(void)
1292{
1293 if (cpu_has_vmx_invvpid_global())
1294 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1295}
1296
1297static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1298{
1299 if (cpu_has_vmx_invvpid_single())
1760dd49 1300 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1301 else
1302 vpid_sync_vcpu_global();
1303}
1304
1439442c
SY		 1305static inline void ept_sync_global(void)
1306{
1307 if (cpu_has_vmx_invept_global())
1308 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1309}
1310
1311static inline void ept_sync_context(u64 eptp)
1312{
089d034e 1313 if (enable_ept) {
1439442c
SY		 1314 if (cpu_has_vmx_invept_context())
1315 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1316 else
1317 ept_sync_global();
1318 }
1319}
1320
96304217 1321static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1322{
5e520e62 1323 unsigned long value;
6aa8b732 1324
5e520e62
AK		 1325 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1326 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1327 return value;
1328}
1329
96304217 1330static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1331{
1332 return vmcs_readl(field);
1333}
1334
96304217 1335static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1336{
1337 return vmcs_readl(field);
1338}
1339
96304217 1340static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1341{
05b3e0c2 1342#ifdef CONFIG_X86_64
6aa8b732
AK		 1343 return vmcs_readl(field);
1344#else
1345 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1346#endif
1347}
1348
e52de1b8
AK		 1349static noinline void vmwrite_error(unsigned long field, unsigned long value)
1350{
1351 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1352 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1353 dump_stack();
1354}
1355
6aa8b732
AK		 1356static void vmcs_writel(unsigned long field, unsigned long value)
1357{
1358 u8 error;
1359
4ecac3fd 1360 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1361 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1362 if (unlikely(error))
1363 vmwrite_error(field, value);
6aa8b732
AK		 1364}
1365
1366static void vmcs_write16(unsigned long field, u16 value)
1367{
1368 vmcs_writel(field, value);
1369}
1370
1371static void vmcs_write32(unsigned long field, u32 value)
1372{
1373 vmcs_writel(field, value);
1374}
1375
1376static void vmcs_write64(unsigned long field, u64 value)
1377{
6aa8b732 1378 vmcs_writel(field, value);
7682f2d0 1379#ifndef CONFIG_X86_64
6aa8b732
AK		 1380 asm volatile ("");
1381 vmcs_writel(field+1, value >> 32);
1382#endif
1383}
1384
2ab455cc
AL		 1385static void vmcs_clear_bits(unsigned long field, u32 mask)
1386{
1387 vmcs_writel(field, vmcs_readl(field) & ~mask);
1388}
1389
1390static void vmcs_set_bits(unsigned long field, u32 mask)
1391{
1392 vmcs_writel(field, vmcs_readl(field) | mask);
1393}
1394
2961e876
GN		 1395static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1396{
1397 vmcs_write32(VM_ENTRY_CONTROLS, val);
1398 vmx->vm_entry_controls_shadow = val;
1399}
1400
1401static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1402{
1403 if (vmx->vm_entry_controls_shadow != val)
1404 vm_entry_controls_init(vmx, val);
1405}
1406
1407static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1408{
1409 return vmx->vm_entry_controls_shadow;
1410}
1411
1412
1413static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1414{
1415 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1416}
1417
1418static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1419{
1420 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1421}
1422
1423static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1424{
1425 vmcs_write32(VM_EXIT_CONTROLS, val);
1426 vmx->vm_exit_controls_shadow = val;
1427}
1428
1429static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1430{
1431 if (vmx->vm_exit_controls_shadow != val)
1432 vm_exit_controls_init(vmx, val);
1433}
1434
1435static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1436{
1437 return vmx->vm_exit_controls_shadow;
1438}
1439
1440
1441static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1442{
1443 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1444}
1445
1446static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1447{
1448 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1449}
1450
2fb92db1
AK		 1451static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1452{
1453 vmx->segment_cache.bitmask = 0;
1454}
1455
1456static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1457 unsigned field)
1458{
1459 bool ret;
1460 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1461
1462 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1463 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1464 vmx->segment_cache.bitmask = 0;
1465 }
1466 ret = vmx->segment_cache.bitmask & mask;
1467 vmx->segment_cache.bitmask |= mask;
1468 return ret;
1469}
1470
1471static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1472{
1473 u16 *p = &vmx->segment_cache.seg[seg].selector;
1474
1475 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1476 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1477 return *p;
1478}
1479
1480static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1481{
1482 ulong *p = &vmx->segment_cache.seg[seg].base;
1483
1484 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1485 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1486 return *p;
1487}
1488
1489static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1490{
1491 u32 *p = &vmx->segment_cache.seg[seg].limit;
1492
1493 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1494 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1495 return *p;
1496}
1497
1498static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1499{
1500 u32 *p = &vmx->segment_cache.seg[seg].ar;
1501
1502 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1503 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1504 return *p;
1505}
1506
abd3f2d6
AK		 1507static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1508{
1509 u32 eb;
1510
fd7373cc
JK		 1511 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1512 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1513 if ((vcpu->guest_debug &
1514 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1515 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1516 eb |= 1u << BP_VECTOR;
7ffd92c5 1517 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1518 eb = ~0;
089d034e 1519 if (enable_ept)
1439442c 1520 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1521 if (vcpu->fpu_active)
1522 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1523
1524 /* When we are running a nested L2 guest and L1 specified for it a
1525 * certain exception bitmap, we must trap the same exceptions and pass
1526 * them to L1. When running L2, we will only handle the exceptions
1527 * specified above if L1 did not want them.
1528 */
1529 if (is_guest_mode(vcpu))
1530 eb |= get_vmcs12(vcpu)->exception_bitmap;
1531
abd3f2d6
AK		 1532 vmcs_write32(EXCEPTION_BITMAP, eb);
1533}
1534
2961e876
GN		 1535static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1536 unsigned long entry, unsigned long exit)
8bf00a52 1537{
2961e876
GN		 1538 vm_entry_controls_clearbit(vmx, entry);
1539 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1540}
1541
61d2ef2c
AK		 1542static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1543{
1544 unsigned i;
1545 struct msr_autoload *m = &vmx->msr_autoload;
1546
8bf00a52
GN		 1547 switch (msr) {
1548 case MSR_EFER:
1549 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1550 clear_atomic_switch_msr_special(vmx,
1551 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1552 VM_EXIT_LOAD_IA32_EFER);
1553 return;
1554 }
1555 break;
1556 case MSR_CORE_PERF_GLOBAL_CTRL:
1557 if (cpu_has_load_perf_global_ctrl) {
2961e876 1558 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1559 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1560 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1561 return;
1562 }
1563 break;
110312c8
AK		 1564 }
1565
61d2ef2c
AK		 1566 for (i = 0; i < m->nr; ++i)
1567 if (m->guest[i].index == msr)
1568 break;
1569
1570 if (i == m->nr)
1571 return;
1572 --m->nr;
1573 m->guest[i] = m->guest[m->nr];
1574 m->host[i] = m->host[m->nr];
1575 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1576 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1577}
1578
2961e876
GN		 1579static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1580 unsigned long entry, unsigned long exit,
1581 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1582 u64 guest_val, u64 host_val)
8bf00a52
GN		 1583{
1584 vmcs_write64(guest_val_vmcs, guest_val);
1585 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1586 vm_entry_controls_setbit(vmx, entry);
1587 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1588}
1589
61d2ef2c
AK		 1590static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1591 u64 guest_val, u64 host_val)
1592{
1593 unsigned i;
1594 struct msr_autoload *m = &vmx->msr_autoload;
1595
8bf00a52
GN		 1596 switch (msr) {
1597 case MSR_EFER:
1598 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1599 add_atomic_switch_msr_special(vmx,
1600 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1601 VM_EXIT_LOAD_IA32_EFER,
1602 GUEST_IA32_EFER,
1603 HOST_IA32_EFER,
1604 guest_val, host_val);
1605 return;
1606 }
1607 break;
1608 case MSR_CORE_PERF_GLOBAL_CTRL:
1609 if (cpu_has_load_perf_global_ctrl) {
2961e876 1610 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1611 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1612 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1613 GUEST_IA32_PERF_GLOBAL_CTRL,
1614 HOST_IA32_PERF_GLOBAL_CTRL,
1615 guest_val, host_val);
1616 return;
1617 }
1618 break;
110312c8
AK		 1619 }
1620
61d2ef2c
AK		 1621 for (i = 0; i < m->nr; ++i)
1622 if (m->guest[i].index == msr)
1623 break;
1624
e7fc6f93 1625 if (i == NR_AUTOLOAD_MSRS) {
60266204 1626 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1627 "Can't add msr %x\n", msr);
1628 return;
1629 } else if (i == m->nr) {
61d2ef2c
AK		 1630 ++m->nr;
1631 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1632 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1633 }
1634
1635 m->guest[i].index = msr;
1636 m->guest[i].value = guest_val;
1637 m->host[i].index = msr;
1638 m->host[i].value = host_val;
1639}
1640
33ed6329
AK		 1641static void reload_tss(void)
1642{
33ed6329
AK		 1643 /*
1644 * VT restores TR but not its size. Useless.
1645 */
89cbc767 1646 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1647 struct desc_struct *descs;
33ed6329 1648
d359192f 1649 descs = (void *)gdt->address;
33ed6329
AK		 1650 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1651 load_TR_desc();
33ed6329
AK		 1652}
1653
92c0d900 1654static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1655{
3a34a881 1656 u64 guest_efer;
51c6cf66
AK		 1657 u64 ignore_bits;
1658
f6801dff 1659 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1660
51c6cf66 1661 /*
0fa06071 1662 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1663 * outside long mode
1664 */
1665 ignore_bits = EFER_NX | EFER_SCE;
1666#ifdef CONFIG_X86_64
1667 ignore_bits |= EFER_LMA | EFER_LME;
1668 /* SCE is meaningful only in long mode on Intel */
1669 if (guest_efer & EFER_LMA)
1670 ignore_bits &= ~(u64)EFER_SCE;
1671#endif
51c6cf66
AK		 1672 guest_efer &= ~ignore_bits;
1673 guest_efer |= host_efer & ignore_bits;
26bb0981 1674 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1675 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1676
1677 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1678
1679 /*
1680 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1681 * On CPUs that support "load IA32_EFER", always switch EFER
1682 * atomically, since it's faster than switching it manually.
1683 */
1684 if (cpu_has_load_ia32_efer ||
1685 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1686 guest_efer = vmx->vcpu.arch.efer;
1687 if (!(guest_efer & EFER_LMA))
1688 guest_efer &= ~EFER_LME;
54b98bff
AL		 1689 if (guest_efer != host_efer)
1690 add_atomic_switch_msr(vmx, MSR_EFER,
1691 guest_efer, host_efer);
84ad33ef
AK		 1692 return false;
1693 }
1694
26bb0981 1695 return true;
51c6cf66
AK		 1696}
1697
2d49ec72
GN		 1698static unsigned long segment_base(u16 selector)
1699{
89cbc767 1700 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1701 struct desc_struct *d;
1702 unsigned long table_base;
1703 unsigned long v;
1704
1705 if (!(selector & ~3))
1706 return 0;
1707
d359192f 1708 table_base = gdt->address;
2d49ec72
GN		 1709
1710 if (selector & 4) { /* from ldt */
1711 u16 ldt_selector = kvm_read_ldt();
1712
1713 if (!(ldt_selector & ~3))
1714 return 0;
1715
1716 table_base = segment_base(ldt_selector);
1717 }
1718 d = (struct desc_struct *)(table_base + (selector & ~7));
1719 v = get_desc_base(d);
1720#ifdef CONFIG_X86_64
1721 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1722 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1723#endif
1724 return v;
1725}
1726
1727static inline unsigned long kvm_read_tr_base(void)
1728{
1729 u16 tr;
1730 asm("str %0" : "=g"(tr));
1731 return segment_base(tr);
1732}
1733
04d2cc77 1734static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1735{
04d2cc77 1736 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1737 int i;
04d2cc77 1738
a2fa3e9f 1739 if (vmx->host_state.loaded)
33ed6329
AK		 1740 return;
1741
a2fa3e9f 1742 vmx->host_state.loaded = 1;
33ed6329
AK		 1743 /*
1744 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1745 * allow segment selectors with cpl > 0 or ti == 1.
1746 */
d6e88aec 1747 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1748 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1749 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1750 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1751 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1752 vmx->host_state.fs_reload_needed = 0;
1753 } else {
33ed6329 1754 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1755 vmx->host_state.fs_reload_needed = 1;
33ed6329 1756 }
9581d442 1757 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1758 if (!(vmx->host_state.gs_sel & 7))
1759 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1760 else {
1761 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1762 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1763 }
1764
b2da15ac
AK		 1765#ifdef CONFIG_X86_64
1766 savesegment(ds, vmx->host_state.ds_sel);
1767 savesegment(es, vmx->host_state.es_sel);
1768#endif
1769
33ed6329
AK		 1770#ifdef CONFIG_X86_64
1771 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1772 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1773#else
a2fa3e9f
GH		 1774 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1775 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1776#endif
707c0874
AK		 1777
1778#ifdef CONFIG_X86_64
c8770e7b
AK		 1779 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1780 if (is_long_mode(&vmx->vcpu))
44ea2b17 1781 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1782#endif
da8999d3
LJ		 1783 if (boot_cpu_has(X86_FEATURE_MPX))
1784 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1785 for (i = 0; i < vmx->save_nmsrs; ++i)
1786 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1787 vmx->guest_msrs[i].data,
1788 vmx->guest_msrs[i].mask);
33ed6329
AK		 1789}
1790
a9b21b62 1791static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1792{
a2fa3e9f 1793 if (!vmx->host_state.loaded)
33ed6329
AK		 1794 return;
1795
e1beb1d3 1796 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1797 vmx->host_state.loaded = 0;
c8770e7b
AK		 1798#ifdef CONFIG_X86_64
1799 if (is_long_mode(&vmx->vcpu))
1800 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1801#endif
152d3f2f 1802 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1803 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1804#ifdef CONFIG_X86_64
9581d442 1805 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1806#else
1807 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1808#endif
33ed6329 1809 }
0a77fe4c
AK		 1810 if (vmx->host_state.fs_reload_needed)
1811 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1812#ifdef CONFIG_X86_64
1813 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1814 loadsegment(ds, vmx->host_state.ds_sel);
1815 loadsegment(es, vmx->host_state.es_sel);
1816 }
b2da15ac 1817#endif
152d3f2f 1818 reload_tss();
44ea2b17 1819#ifdef CONFIG_X86_64
c8770e7b 1820 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1821#endif
da8999d3
LJ		 1822 if (vmx->host_state.msr_host_bndcfgs)
1823 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1824 /*
1825 * If the FPU is not active (through the host task or
1826 * the guest vcpu), then restore the cr0.TS bit.
1827 */
1828 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1829 stts();
89cbc767 1830 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1831}
1832
a9b21b62
AK		 1833static void vmx_load_host_state(struct vcpu_vmx *vmx)
1834{
1835 preempt_disable();
1836 __vmx_load_host_state(vmx);
1837 preempt_enable();
1838}
1839
6aa8b732
AK		 1840/*
1841 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1842 * vcpu mutex is already taken.
1843 */
15ad7146 1844static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1845{
a2fa3e9f 1846 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1847 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1848
4610c9cc
DX		 1849 if (!vmm_exclusive)
1850 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1851 else if (vmx->loaded_vmcs->cpu != cpu)
1852 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1853
d462b819
NHE		 1854 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1855 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1856 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1857 }
1858
d462b819 1859 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1860 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1861 unsigned long sysenter_esp;
1862
a8eeb04a 1863 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1864 local_irq_disable();
8f536b76 1865 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1866
1867 /*
1868 * Read loaded_vmcs->cpu should be before fetching
1869 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1870 * See the comments in __loaded_vmcs_clear().
1871 */
1872 smp_rmb();
1873
d462b819
NHE		 1874 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1875 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1876 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1877 local_irq_enable();
1878
6aa8b732
AK		 1879 /*
1880 * Linux uses per-cpu TSS and GDT, so set these when switching
1881 * processors.
1882 */
d6e88aec 1883 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1884 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1885
1886 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1887 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1888 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1889 }
6aa8b732
AK		 1890}
1891
1892static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1893{
a9b21b62 1894 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1895 if (!vmm_exclusive) {
d462b819
NHE		 1896 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1897 vcpu->cpu = -1;
4610c9cc
DX		 1898 kvm_cpu_vmxoff();
1899 }
6aa8b732
AK		 1900}
1901
5fd86fcf
AK		 1902static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1903{
81231c69
AK		 1904 ulong cr0;
1905
5fd86fcf
AK		 1906 if (vcpu->fpu_active)
1907 return;
1908 vcpu->fpu_active = 1;
81231c69
AK		 1909 cr0 = vmcs_readl(GUEST_CR0);
1910 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1911 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1912 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1913 update_exception_bitmap(vcpu);
edcafe3c 1914 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1915 if (is_guest_mode(vcpu))
1916 vcpu->arch.cr0_guest_owned_bits &=
1917 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1918 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1919}
1920
edcafe3c
AK		 1921static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1922
fe3ef05c
NHE		 1923/*
1924 * Return the cr0 value that a nested guest would read. This is a combination
1925 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1926 * its hypervisor (cr0_read_shadow).
1927 */
1928static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1929{
1930 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1931 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1932}
1933static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1934{
1935 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1936 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1937}
1938
5fd86fcf
AK		 1939static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1940{
36cf24e0
NHE		 1941 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1942 * set this *before* calling this function.
1943 */
edcafe3c 1944 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1945 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1946 update_exception_bitmap(vcpu);
edcafe3c
AK		 1947 vcpu->arch.cr0_guest_owned_bits = 0;
1948 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1949 if (is_guest_mode(vcpu)) {
1950 /*
1951 * L1's specified read shadow might not contain the TS bit,
1952 * so now that we turned on shadowing of this bit, we need to
1953 * set this bit of the shadow. Like in nested_vmx_run we need
1954 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1955 * up-to-date here because we just decached cr0.TS (and we'll
1956 * only update vmcs12->guest_cr0 on nested exit).
1957 */
1958 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1959 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1960 (vcpu->arch.cr0 & X86_CR0_TS);
1961 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1962 } else
1963 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1964}
1965
6aa8b732
AK		 1966static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1967{
78ac8b47 1968 unsigned long rflags, save_rflags;
345dcaa8 1969
6de12732
AK		 1970 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1971 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1972 rflags = vmcs_readl(GUEST_RFLAGS);
1973 if (to_vmx(vcpu)->rmode.vm86_active) {
1974 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1975 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1976 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1977 }
1978 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1979 }
6de12732 1980 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1981}
1982
1983static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1984{
6de12732
AK		 1985 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1986 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1987 if (to_vmx(vcpu)->rmode.vm86_active) {
1988 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1989 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1990 }
6aa8b732
AK		 1991 vmcs_writel(GUEST_RFLAGS, rflags);
1992}
1993
37ccdcbe 1994static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1995{
1996 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1997 int ret = 0;
1998
1999 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2000 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2001 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2002 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2003
37ccdcbe 2004 return ret;
2809f5d2
GC		 2005}
2006
2007static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2008{
2009 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2010 u32 interruptibility = interruptibility_old;
2011
2012 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2013
48005f64 2014 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2015 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2016 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2017 interruptibility |= GUEST_INTR_STATE_STI;
2018
2019 if ((interruptibility != interruptibility_old))
2020 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2021}
2022
6aa8b732
AK		 2023static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2024{
2025 unsigned long rip;
6aa8b732 2026
5fdbf976 2027 rip = kvm_rip_read(vcpu);
6aa8b732 2028 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2029 kvm_rip_write(vcpu, rip);
6aa8b732 2030
2809f5d2
GC		 2031 /* skipping an emulated instruction also counts */
2032 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2033}
2034
0b6ac343
NHE		 2035/*
2036 * KVM wants to inject page-faults which it got to the guest. This function
2037 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2038 */
e011c663 2039static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2040{
2041 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2042
e011c663 2043 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2044 return 0;
2045
533558bc
JK		 2046 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2047 vmcs_read32(VM_EXIT_INTR_INFO),
2048 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2049 return 1;
2050}
2051
298101da 2052static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2053 bool has_error_code, u32 error_code,
2054 bool reinject)
298101da 2055{
77ab6db0 2056 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2057 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2058
e011c663
GN		 2059 if (!reinject && is_guest_mode(vcpu) &&
2060 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2061 return;
2062
8ab2d2e2 2063 if (has_error_code) {
77ab6db0 2064 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2065 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2066 }
77ab6db0 2067
7ffd92c5 2068 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2069 int inc_eip = 0;
2070 if (kvm_exception_is_soft(nr))
2071 inc_eip = vcpu->arch.event_exit_inst_len;
2072 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2073 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2074 return;
2075 }
2076
66fd3f7f
GN		 2077 if (kvm_exception_is_soft(nr)) {
2078 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2079 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2080 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2081 } else
2082 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2083
2084 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2085}
2086
4e47c7a6
SY		 2087static bool vmx_rdtscp_supported(void)
2088{
2089 return cpu_has_vmx_rdtscp();
2090}
2091
ad756a16
MJ		 2092static bool vmx_invpcid_supported(void)
2093{
2094 return cpu_has_vmx_invpcid() && enable_ept;
2095}
2096
a75beee6
ED		 2097/*
2098 * Swap MSR entry in host/guest MSR entry array.
2099 */
8b9cf98c 2100static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2101{
26bb0981 2102 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2103
2104 tmp = vmx->guest_msrs[to];
2105 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2106 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2107}
2108
8d14695f
YZ		 2109static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2110{
2111 unsigned long *msr_bitmap;
2112
2113 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2114 if (is_long_mode(vcpu))
2115 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2116 else
2117 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2118 } else {
2119 if (is_long_mode(vcpu))
2120 msr_bitmap = vmx_msr_bitmap_longmode;
2121 else
2122 msr_bitmap = vmx_msr_bitmap_legacy;
2123 }
2124
2125 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2126}
2127
e38aea3e
AK		 2128/*
2129 * Set up the vmcs to automatically save and restore system
2130 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2131 * mode, as fiddling with msrs is very expensive.
2132 */
8b9cf98c 2133static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2134{
26bb0981 2135 int save_nmsrs, index;
e38aea3e 2136
a75beee6
ED		 2137 save_nmsrs = 0;
2138#ifdef CONFIG_X86_64
8b9cf98c 2139 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2140 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2141 if (index >= 0)
8b9cf98c
RR		 2142 move_msr_up(vmx, index, save_nmsrs++);
2143 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2144 if (index >= 0)
8b9cf98c
RR		 2145 move_msr_up(vmx, index, save_nmsrs++);
2146 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2147 if (index >= 0)
8b9cf98c 2148 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2149 index = __find_msr_index(vmx, MSR_TSC_AUX);
2150 if (index >= 0 && vmx->rdtscp_enabled)
2151 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2152 /*
8c06585d 2153 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2154 * if efer.sce is enabled.
2155 */
8c06585d 2156 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2157 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2158 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2159 }
2160#endif
92c0d900
AK		 2161 index = __find_msr_index(vmx, MSR_EFER);
2162 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2163 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2164
26bb0981 2165 vmx->save_nmsrs = save_nmsrs;
5897297b 2166
8d14695f
YZ		 2167 if (cpu_has_vmx_msr_bitmap())
2168 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2169}
2170
6aa8b732
AK		 2171/*
2172 * reads and returns guest's timestamp counter "register"
2173 * guest_tsc = host_tsc + tsc_offset -- 21.3
2174 */
2175static u64 guest_read_tsc(void)
2176{
2177 u64 host_tsc, tsc_offset;
2178
2179 rdtscll(host_tsc);
2180 tsc_offset = vmcs_read64(TSC_OFFSET);
2181 return host_tsc + tsc_offset;
2182}
2183
d5c1785d
NHE		 2184/*
2185 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2186 * counter, even if a nested guest (L2) is currently running.
2187 */
48d89b92 2188static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2189{
886b470c 2190 u64 tsc_offset;
d5c1785d 2191
d5c1785d
NHE		 2192 tsc_offset = is_guest_mode(vcpu) ?
2193 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2194 vmcs_read64(TSC_OFFSET);
2195 return host_tsc + tsc_offset;
2196}
2197
4051b188 2198/*
cc578287
ZA		 2199 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2200 * software catchup for faster rates on slower CPUs.
4051b188 2201 */
cc578287 2202static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2203{
cc578287
ZA		 2204 if (!scale)
2205 return;
2206
2207 if (user_tsc_khz > tsc_khz) {
2208 vcpu->arch.tsc_catchup = 1;
2209 vcpu->arch.tsc_always_catchup = 1;
2210 } else
2211 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2212}
2213
ba904635
WA		 2214static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2215{
2216 return vmcs_read64(TSC_OFFSET);
2217}
2218
6aa8b732 2219/*
99e3e30a 2220 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2221 */
99e3e30a 2222static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2223{
27fc51b2 2224 if (is_guest_mode(vcpu)) {
7991825b 2225 /*
27fc51b2
NHE		 2226 * We're here if L1 chose not to trap WRMSR to TSC. According
2227 * to the spec, this should set L1's TSC; The offset that L1
2228 * set for L2 remains unchanged, and still needs to be added
2229 * to the newly set TSC to get L2's TSC.
7991825b 2230 */
27fc51b2
NHE		 2231 struct vmcs12 *vmcs12;
2232 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2233 /* recalculate vmcs02.TSC_OFFSET: */
2234 vmcs12 = get_vmcs12(vcpu);
2235 vmcs_write64(TSC_OFFSET, offset +
2236 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2237 vmcs12->tsc_offset : 0));
2238 } else {
489223ed
YY		 2239 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2240 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2241 vmcs_write64(TSC_OFFSET, offset);
2242 }
6aa8b732
AK		 2243}
2244
f1e2b260 2245static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2246{
2247 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2248
e48672fa 2249 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2250 if (is_guest_mode(vcpu)) {
2251 /* Even when running L2, the adjustment needs to apply to L1 */
2252 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2253 } else
2254 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2255 offset + adjustment);
e48672fa
ZA		 2256}
2257
857e4099
JR		 2258static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2259{
2260 return target_tsc - native_read_tsc();
2261}
2262
801d3424
NHE		 2263static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2264{
2265 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2266 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2267}
2268
2269/*
2270 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2271 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2272 * all guests if the "nested" module option is off, and can also be disabled
2273 * for a single guest by disabling its VMX cpuid bit.
2274 */
2275static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2276{
2277 return nested && guest_cpuid_has_vmx(vcpu);
2278}
2279
b87a51ae
NHE		 2280/*
2281 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2282 * returned for the various VMX controls MSRs when nested VMX is enabled.
2283 * The same values should also be used to verify that vmcs12 control fields are
2284 * valid during nested entry from L1 to L2.
2285 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2286 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2287 * bit in the high half is on if the corresponding bit in the control field
2288 * may be on. See also vmx_control_verify().
2289 * TODO: allow these variables to be modified (downgraded) by module options
2290 * or other means.
2291 */
2292static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2293static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2294static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2295static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2296static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2297static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2298static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2299static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2300static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2301static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2302static __init void nested_vmx_setup_ctls_msrs(void)
2303{
2304 /*
2305 * Note that as a general rule, the high half of the MSRs (bits in
2306 * the control fields which may be 1) should be initialized by the
2307 * intersection of the underlying hardware's MSR (i.e., features which
2308 * can be supported) and the list of features we want to expose -
2309 * because they are known to be properly supported in our code.
2310 * Also, usually, the low half of the MSRs (bits which must be 1) can
2311 * be set to 0, meaning that L1 may turn off any of these bits. The
2312 * reason is that if one of these bits is necessary, it will appear
2313 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2314 * fields of vmcs01 and vmcs02, will turn these bits off - and
2315 * nested_vmx_exit_handled() will not pass related exits to L1.
2316 * These rules have exceptions below.
2317 */
2318
2319 /* pin-based controls */
eabeaacc
JK		 2320 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2321 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2322 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2323 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2324 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2325 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2326 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2327
3dbcd8da 2328 /* exit controls */
c0dfee58
ACL		 2329 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2330 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2331 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2332
c0dfee58 2333 nested_vmx_exit_ctls_high &=
b87a51ae 2334#ifdef CONFIG_X86_64
c0dfee58 2335 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2336#endif
f4124500
JK		 2337 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2338 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2339 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2340 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2341
36be0b9d
PB		 2342 if (vmx_mpx_supported())
2343 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2344
2996fca0
JK		 2345 /* We support free control of debug control saving. */
2346 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2347 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2348
b87a51ae
NHE		 2349 /* entry controls */
2350 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2351 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2352 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2353 nested_vmx_entry_ctls_high &=
57435349
JK		 2354#ifdef CONFIG_X86_64
2355 VM_ENTRY_IA32E_MODE |
2356#endif
2357 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2358 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2359 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2360 if (vmx_mpx_supported())
2361 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2362
2996fca0
JK		 2363 /* We support free control of debug control loading. */
2364 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2365 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2366
b87a51ae
NHE		 2367 /* cpu-based controls */
2368 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2369 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2370 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2371 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2372 CPU_BASED_VIRTUAL_INTR_PENDING |
2373 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2374 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2375 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2376 CPU_BASED_CR3_STORE_EXITING |
2377#ifdef CONFIG_X86_64
2378 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2379#endif
2380 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2381 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2382 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2383 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2384 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2385 /*
2386 * We can allow some features even when not supported by the
2387 * hardware. For example, L1 can specify an MSR bitmap - and we
2388 * can use it to avoid exits to L1 - even when L0 runs L2
2389 * without MSR bitmaps.
2390 */
560b7ee1
JK		 2391 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2392 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2393
3dcdf3ec
JK		 2394 /* We support free control of CR3 access interception. */
2395 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2396 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2397
b87a51ae
NHE		 2398 /* secondary cpu-based controls */
2399 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2400 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2401 nested_vmx_secondary_ctls_low = 0;
2402 nested_vmx_secondary_ctls_high &=
d6851fbe 2403 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
81dc01f7
WL		 2404 SECONDARY_EXEC_WBINVD_EXITING |
2405 SECONDARY_EXEC_XSAVES;
c18911a2 2406
afa61f75
NHE		 2407 if (enable_ept) {
2408 /* nested EPT: emulate EPT also to L1 */
78051e3b
BD		 2409 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT |
2410 SECONDARY_EXEC_UNRESTRICTED_GUEST;
ca72d970 2411 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2412 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2413 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2414 nested_vmx_ept_caps &= vmx_capability.ept;
2415 /*
4b855078
BD		 2416 * For nested guests, we don't do anything specific
2417 * for single context invalidation. Hence, only advertise
2418 * support for global context invalidation.
afa61f75 2419 */
4b855078 2420 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2421 } else
2422 nested_vmx_ept_caps = 0;
2423
c18911a2
JK		 2424 /* miscellaneous data */
2425 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2426 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2427 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2428 VMX_MISC_ACTIVITY_HLT;
c18911a2 2429 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2430}
2431
2432static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2433{
2434 /*
2435 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2436 */
2437 return ((control & high) | low) == control;
2438}
2439
2440static inline u64 vmx_control_msr(u32 low, u32 high)
2441{
2442 return low | ((u64)high << 32);
2443}
2444
cae50139 2445/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2446static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2447{
b87a51ae 2448 switch (msr_index) {
b87a51ae
NHE		 2449 case MSR_IA32_VMX_BASIC:
2450 /*
2451 * This MSR reports some information about VMX support. We
2452 * should return information about the VMX we emulate for the
2453 * guest, and the VMCS structure we give it - not about the
2454 * VMX support of the underlying hardware.
2455 */
3dbcd8da 2456 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2457 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2458 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2459 break;
2460 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2461 case MSR_IA32_VMX_PINBASED_CTLS:
2462 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2463 nested_vmx_pinbased_ctls_high);
2464 break;
2465 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2466 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2467 nested_vmx_procbased_ctls_high);
2468 break;
b87a51ae
NHE		 2469 case MSR_IA32_VMX_PROCBASED_CTLS:
2470 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2471 nested_vmx_procbased_ctls_high);
2472 break;
2473 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2474 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2475 nested_vmx_exit_ctls_high);
2476 break;
b87a51ae
NHE		 2477 case MSR_IA32_VMX_EXIT_CTLS:
2478 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2479 nested_vmx_exit_ctls_high);
2480 break;
2481 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2482 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2483 nested_vmx_entry_ctls_high);
2484 break;
b87a51ae
NHE		 2485 case MSR_IA32_VMX_ENTRY_CTLS:
2486 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2487 nested_vmx_entry_ctls_high);
2488 break;
2489 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2490 *pdata = vmx_control_msr(nested_vmx_misc_low,
2491 nested_vmx_misc_high);
b87a51ae
NHE		 2492 break;
2493 /*
2494 * These MSRs specify bits which the guest must keep fixed (on or off)
2495 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2496 * We picked the standard core2 setting.
2497 */
2498#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2499#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2500 case MSR_IA32_VMX_CR0_FIXED0:
2501 *pdata = VMXON_CR0_ALWAYSON;
2502 break;
2503 case MSR_IA32_VMX_CR0_FIXED1:
2504 *pdata = -1ULL;
2505 break;
2506 case MSR_IA32_VMX_CR4_FIXED0:
2507 *pdata = VMXON_CR4_ALWAYSON;
2508 break;
2509 case MSR_IA32_VMX_CR4_FIXED1:
2510 *pdata = -1ULL;
2511 break;
2512 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2513 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2514 break;
2515 case MSR_IA32_VMX_PROCBASED_CTLS2:
2516 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2517 nested_vmx_secondary_ctls_high);
2518 break;
2519 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2520 /* Currently, no nested vpid support */
2521 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2522 break;
2523 default:
b87a51ae 2524 return 1;
b3897a49
NHE		 2525 }
2526
b87a51ae
NHE		 2527 return 0;
2528}
2529
6aa8b732
AK		 2530/*
2531 * Reads an msr value (of 'msr_index') into 'pdata'.
2532 * Returns 0 on success, non-0 otherwise.
2533 * Assumes vcpu_load() was already called.
2534 */
2535static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2536{
2537 u64 data;
26bb0981 2538 struct shared_msr_entry *msr;
6aa8b732
AK		 2539
2540 if (!pdata) {
2541 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2542 return -EINVAL;
2543 }
2544
2545 switch (msr_index) {
05b3e0c2 2546#ifdef CONFIG_X86_64
6aa8b732
AK		 2547 case MSR_FS_BASE:
2548 data = vmcs_readl(GUEST_FS_BASE);
2549 break;
2550 case MSR_GS_BASE:
2551 data = vmcs_readl(GUEST_GS_BASE);
2552 break;
44ea2b17
AK		 2553 case MSR_KERNEL_GS_BASE:
2554 vmx_load_host_state(to_vmx(vcpu));
2555 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2556 break;
26bb0981 2557#endif
6aa8b732 2558 case MSR_EFER:
3bab1f5d 2559 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2560 case MSR_IA32_TSC:
6aa8b732
AK		 2561 data = guest_read_tsc();
2562 break;
2563 case MSR_IA32_SYSENTER_CS:
2564 data = vmcs_read32(GUEST_SYSENTER_CS);
2565 break;
2566 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2567 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2568 break;
2569 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2570 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2571 break;
0dd376e7 2572 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2573 if (!vmx_mpx_supported())
2574 return 1;
0dd376e7
LJ		 2575 data = vmcs_read64(GUEST_BNDCFGS);
2576 break;
cae50139
JK		 2577 case MSR_IA32_FEATURE_CONTROL:
2578 if (!nested_vmx_allowed(vcpu))
2579 return 1;
2580 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2581 break;
2582 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2583 if (!nested_vmx_allowed(vcpu))
2584 return 1;
2585 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2586 case MSR_IA32_XSS:
2587 if (!vmx_xsaves_supported())
2588 return 1;
2589 data = vcpu->arch.ia32_xss;
2590 break;
4e47c7a6
SY		 2591 case MSR_TSC_AUX:
2592 if (!to_vmx(vcpu)->rdtscp_enabled)
2593 return 1;
2594 /* Otherwise falls through */
6aa8b732 2595 default:
8b9cf98c 2596 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2597 if (msr) {
2598 data = msr->data;
2599 break;
6aa8b732 2600 }
3bab1f5d 2601 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2602 }
2603
2604 *pdata = data;
2605 return 0;
2606}
2607
cae50139
JK		 2608static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2609
6aa8b732
AK		 2610/*
2611 * Writes msr value into into the appropriate "register".
2612 * Returns 0 on success, non-0 otherwise.
2613 * Assumes vcpu_load() was already called.
2614 */
8fe8ab46 2615static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2616{
a2fa3e9f 2617 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2618 struct shared_msr_entry *msr;
2cc51560 2619 int ret = 0;
8fe8ab46
WA		 2620 u32 msr_index = msr_info->index;
2621 u64 data = msr_info->data;
2cc51560 2622
6aa8b732 2623 switch (msr_index) {
3bab1f5d 2624 case MSR_EFER:
8fe8ab46 2625 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2626 break;
16175a79 2627#ifdef CONFIG_X86_64
6aa8b732 2628 case MSR_FS_BASE:
2fb92db1 2629 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2630 vmcs_writel(GUEST_FS_BASE, data);
2631 break;
2632 case MSR_GS_BASE:
2fb92db1 2633 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2634 vmcs_writel(GUEST_GS_BASE, data);
2635 break;
44ea2b17
AK		 2636 case MSR_KERNEL_GS_BASE:
2637 vmx_load_host_state(vmx);
2638 vmx->msr_guest_kernel_gs_base = data;
2639 break;
6aa8b732
AK		 2640#endif
2641 case MSR_IA32_SYSENTER_CS:
2642 vmcs_write32(GUEST_SYSENTER_CS, data);
2643 break;
2644 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2645 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2646 break;
2647 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2648 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2649 break;
0dd376e7 2650 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2651 if (!vmx_mpx_supported())
2652 return 1;
0dd376e7
LJ		 2653 vmcs_write64(GUEST_BNDCFGS, data);
2654 break;
af24a4e4 2655 case MSR_IA32_TSC:
8fe8ab46 2656 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2657 break;
468d472f
SY		 2658 case MSR_IA32_CR_PAT:
2659 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2660 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2661 return 1;
468d472f
SY		 2662 vmcs_write64(GUEST_IA32_PAT, data);
2663 vcpu->arch.pat = data;
2664 break;
2665 }
8fe8ab46 2666 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2667 break;
ba904635
WA		 2668 case MSR_IA32_TSC_ADJUST:
2669 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2670 break;
cae50139
JK		 2671 case MSR_IA32_FEATURE_CONTROL:
2672 if (!nested_vmx_allowed(vcpu) ||
2673 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2674 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2675 return 1;
2676 vmx->nested.msr_ia32_feature_control = data;
2677 if (msr_info->host_initiated && data == 0)
2678 vmx_leave_nested(vcpu);
2679 break;
2680 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2681 return 1; /* they are read-only */
20300099
WL		 2682 case MSR_IA32_XSS:
2683 if (!vmx_xsaves_supported())
2684 return 1;
2685 /*
2686 * The only supported bit as of Skylake is bit 8, but
2687 * it is not supported on KVM.
2688 */
2689 if (data != 0)
2690 return 1;
2691 vcpu->arch.ia32_xss = data;
2692 if (vcpu->arch.ia32_xss != host_xss)
2693 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2694 vcpu->arch.ia32_xss, host_xss);
2695 else
2696 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2697 break;
4e47c7a6
SY		 2698 case MSR_TSC_AUX:
2699 if (!vmx->rdtscp_enabled)
2700 return 1;
2701 /* Check reserved bit, higher 32 bits should be zero */
2702 if ((data >> 32) != 0)
2703 return 1;
2704 /* Otherwise falls through */
6aa8b732 2705 default:
8b9cf98c 2706 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2707 if (msr) {
8b3c3104 2708 u64 old_msr_data = msr->data;
3bab1f5d 2709 msr->data = data;
2225fd56
AK		 2710 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2711 preempt_disable();
8b3c3104
AH		 2712 ret = kvm_set_shared_msr(msr->index, msr->data,
2713 msr->mask);
2225fd56 2714 preempt_enable();
8b3c3104
AH		 2715 if (ret)
2716 msr->data = old_msr_data;
2225fd56 2717 }
3bab1f5d 2718 break;
6aa8b732 2719 }
8fe8ab46 2720 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2721 }
2722
2cc51560 2723 return ret;
6aa8b732
AK		 2724}
2725
5fdbf976 2726static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2727{
5fdbf976
MT		 2728 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2729 switch (reg) {
2730 case VCPU_REGS_RSP:
2731 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2732 break;
2733 case VCPU_REGS_RIP:
2734 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2735 break;
6de4f3ad
AK		 2736 case VCPU_EXREG_PDPTR:
2737 if (enable_ept)
2738 ept_save_pdptrs(vcpu);
2739 break;
5fdbf976
MT		 2740 default:
2741 break;
2742 }
6aa8b732
AK		 2743}
2744
6aa8b732
AK		 2745static __init int cpu_has_kvm_support(void)
2746{
6210e37b 2747 return cpu_has_vmx();
6aa8b732
AK		 2748}
2749
2750static __init int vmx_disabled_by_bios(void)
2751{
2752 u64 msr;
2753
2754 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2755 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2756 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2757 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2758 && tboot_enabled())
2759 return 1;
23f3e991 2760 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2761 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2762 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2763 && !tboot_enabled()) {
2764 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2765 "activate TXT before enabling KVM\n");
cafd6659 2766 return 1;
f9335afe 2767 }
23f3e991
JC		 2768 /* launched w/o TXT and VMX disabled */
2769 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2770 && !tboot_enabled())
2771 return 1;
cafd6659
SW		 2772 }
2773
2774 return 0;
6aa8b732
AK		 2775}
2776
7725b894
DX		 2777static void kvm_cpu_vmxon(u64 addr)
2778{
2779 asm volatile (ASM_VMX_VMXON_RAX
2780 : : "a"(&addr), "m"(addr)
2781 : "memory", "cc");
2782}
2783
13a34e06 2784static int hardware_enable(void)
6aa8b732
AK		 2785{
2786 int cpu = raw_smp_processor_id();
2787 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2788 u64 old, test_bits;
6aa8b732 2789
10474ae8
AG		 2790 if (read_cr4() & X86_CR4_VMXE)
2791 return -EBUSY;
2792
d462b819 2793 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2794
2795 /*
2796 * Now we can enable the vmclear operation in kdump
2797 * since the loaded_vmcss_on_cpu list on this cpu
2798 * has been initialized.
2799 *
2800 * Though the cpu is not in VMX operation now, there
2801 * is no problem to enable the vmclear operation
2802 * for the loaded_vmcss_on_cpu list is empty!
2803 */
2804 crash_enable_local_vmclear(cpu);
2805
6aa8b732 2806 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2807
2808 test_bits = FEATURE_CONTROL_LOCKED;
2809 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2810 if (tboot_enabled())
2811 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2812
2813 if ((old & test_bits) != test_bits) {
6aa8b732 2814 /* enable and lock */
cafd6659
SW		 2815 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2816 }
66aee91a 2817 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2818
4610c9cc
DX		 2819 if (vmm_exclusive) {
2820 kvm_cpu_vmxon(phys_addr);
2821 ept_sync_global();
2822 }
10474ae8 2823
89cbc767 2824 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2825
10474ae8 2826 return 0;
6aa8b732
AK		 2827}
2828
d462b819 2829static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2830{
2831 int cpu = raw_smp_processor_id();
d462b819 2832 struct loaded_vmcs *v, *n;
543e4243 2833
d462b819
NHE		 2834 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2835 loaded_vmcss_on_cpu_link)
2836 __loaded_vmcs_clear(v);
543e4243
AK		 2837}
2838
710ff4a8
EH		 2839
2840/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2841 * tricks.
2842 */
2843static void kvm_cpu_vmxoff(void)
6aa8b732 2844{
4ecac3fd 2845 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2846}
2847
13a34e06 2848static void hardware_disable(void)
710ff4a8 2849{
4610c9cc 2850 if (vmm_exclusive) {
d462b819 2851 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2852 kvm_cpu_vmxoff();
2853 }
7725b894 2854 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2855}
2856
1c3d14fe 2857static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2858 u32 msr, u32 *result)
1c3d14fe
YS		 2859{
2860 u32 vmx_msr_low, vmx_msr_high;
2861 u32 ctl = ctl_min | ctl_opt;
2862
2863 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2864
2865 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2866 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2867
2868 /* Ensure minimum (required) set of control bits are supported. */
2869 if (ctl_min & ~ctl)
002c7f7c 2870 return -EIO;
1c3d14fe
YS		 2871
2872 *result = ctl;
2873 return 0;
2874}
2875
110312c8
AK		 2876static __init bool allow_1_setting(u32 msr, u32 ctl)
2877{
2878 u32 vmx_msr_low, vmx_msr_high;
2879
2880 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2881 return vmx_msr_high & ctl;
2882}
2883
002c7f7c 2884static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2885{
2886 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2887 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2888 u32 _pin_based_exec_control = 0;
2889 u32 _cpu_based_exec_control = 0;
f78e0e2e 2890 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2891 u32 _vmexit_control = 0;
2892 u32 _vmentry_control = 0;
2893
10166744 2894 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2895#ifdef CONFIG_X86_64
2896 CPU_BASED_CR8_LOAD_EXITING |
2897 CPU_BASED_CR8_STORE_EXITING |
2898#endif
d56f546d
SY		 2899 CPU_BASED_CR3_LOAD_EXITING |
2900 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2901 CPU_BASED_USE_IO_BITMAPS |
2902 CPU_BASED_MOV_DR_EXITING |
a7052897 2903 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2904 CPU_BASED_MWAIT_EXITING |
2905 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2906 CPU_BASED_INVLPG_EXITING |
2907 CPU_BASED_RDPMC_EXITING;
443381a8 2908
f78e0e2e 2909 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2910 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2911 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2912 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2913 &_cpu_based_exec_control) < 0)
002c7f7c 2914 return -EIO;
6e5d865c
YS		 2915#ifdef CONFIG_X86_64
2916 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2917 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2918 ~CPU_BASED_CR8_STORE_EXITING;
2919#endif
f78e0e2e 2920 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2921 min2 = 0;
2922 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2923 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2924 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2925 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2926 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2927 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2928 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2929 SECONDARY_EXEC_RDTSCP |
83d4c286 2930 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2931 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2932 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2933 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 2934 SECONDARY_EXEC_XSAVES |
2935 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 2936 if (adjust_vmx_controls(min2, opt2,
2937 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2938 &_cpu_based_2nd_exec_control) < 0)
2939 return -EIO;
2940 }
2941#ifndef CONFIG_X86_64
2942 if (!(_cpu_based_2nd_exec_control &
2943 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2944 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2945#endif
83d4c286
YZ		 2946
2947 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2948 _cpu_based_2nd_exec_control &= ~(
8d14695f 2949 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2950 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2951 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2952
d56f546d 2953 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2954 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2955 enabled */
5fff7d27
GN		 2956 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2957 CPU_BASED_CR3_STORE_EXITING |
2958 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2959 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2960 vmx_capability.ept, vmx_capability.vpid);
2961 }
1c3d14fe 2962
81908bf4 2963 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2964#ifdef CONFIG_X86_64
2965 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2966#endif
a547c6db 2967 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2968 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2969 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2970 &_vmexit_control) < 0)
002c7f7c 2971 return -EIO;
1c3d14fe 2972
01e439be
YZ		 2973 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2974 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2975 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2976 &_pin_based_exec_control) < 0)
2977 return -EIO;
2978
2979 if (!(_cpu_based_2nd_exec_control &
2980 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2981 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2982 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2983
c845f9c6 2984 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2985 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2986 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2987 &_vmentry_control) < 0)
002c7f7c 2988 return -EIO;
6aa8b732 2989
c68876fd 2990 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2991
2992 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2993 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2994 return -EIO;
1c3d14fe
YS		 2995
2996#ifdef CONFIG_X86_64
2997 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2998 if (vmx_msr_high & (1u<<16))
002c7f7c 2999 return -EIO;
1c3d14fe
YS		 3000#endif
3001
3002 /* Require Write-Back (WB) memory type for VMCS accesses. */
3003 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3004 return -EIO;
1c3d14fe 3005
002c7f7c
YS		 3006 vmcs_conf->size = vmx_msr_high & 0x1fff;
3007 vmcs_conf->order = get_order(vmcs_config.size);
3008 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3009
002c7f7c
YS		 3010 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3011 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3012 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3013 vmcs_conf->vmexit_ctrl = _vmexit_control;
3014 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3015
110312c8
AK		 3016 cpu_has_load_ia32_efer =
3017 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3018 VM_ENTRY_LOAD_IA32_EFER)
3019 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3020 VM_EXIT_LOAD_IA32_EFER);
3021
8bf00a52
GN		 3022 cpu_has_load_perf_global_ctrl =
3023 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3024 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3025 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3026 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3027
3028 /*
3029 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3030 * but due to arrata below it can't be used. Workaround is to use
3031 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3032 *
3033 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3034 *
3035 * AAK155 (model 26)
3036 * AAP115 (model 30)
3037 * AAT100 (model 37)
3038 * BC86,AAY89,BD102 (model 44)
3039 * BA97 (model 46)
3040 *
3041 */
3042 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3043 switch (boot_cpu_data.x86_model) {
3044 case 26:
3045 case 30:
3046 case 37:
3047 case 44:
3048 case 46:
3049 cpu_has_load_perf_global_ctrl = false;
3050 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3051 "does not work properly. Using workaround\n");
3052 break;
3053 default:
3054 break;
3055 }
3056 }
3057
20300099
WL		 3058 if (cpu_has_xsaves)
3059 rdmsrl(MSR_IA32_XSS, host_xss);
3060
1c3d14fe 3061 return 0;
c68876fd 3062}
6aa8b732
AK		 3063
3064static struct vmcs *alloc_vmcs_cpu(int cpu)
3065{
3066 int node = cpu_to_node(cpu);
3067 struct page *pages;
3068 struct vmcs *vmcs;
3069
6484eb3e 3070 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3071 if (!pages)
3072 return NULL;
3073 vmcs = page_address(pages);
1c3d14fe
YS		 3074 memset(vmcs, 0, vmcs_config.size);
3075 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3076 return vmcs;
3077}
3078
3079static struct vmcs *alloc_vmcs(void)
3080{
d3b2c338 3081 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3082}
3083
3084static void free_vmcs(struct vmcs *vmcs)
3085{
1c3d14fe 3086 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3087}
3088
d462b819
NHE		 3089/*
3090 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3091 */
3092static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3093{
3094 if (!loaded_vmcs->vmcs)
3095 return;
3096 loaded_vmcs_clear(loaded_vmcs);
3097 free_vmcs(loaded_vmcs->vmcs);
3098 loaded_vmcs->vmcs = NULL;
3099}
3100
39959588 3101static void free_kvm_area(void)
6aa8b732
AK		 3102{
3103 int cpu;
3104
3230bb47 3105 for_each_possible_cpu(cpu) {
6aa8b732 3106 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3107 per_cpu(vmxarea, cpu) = NULL;
3108 }
6aa8b732
AK		 3109}
3110
fe2b201b
BD		 3111static void init_vmcs_shadow_fields(void)
3112{
3113 int i, j;
3114
3115 /* No checks for read only fields yet */
3116
3117 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3118 switch (shadow_read_write_fields[i]) {
3119 case GUEST_BNDCFGS:
3120 if (!vmx_mpx_supported())
3121 continue;
3122 break;
3123 default:
3124 break;
3125 }
3126
3127 if (j < i)
3128 shadow_read_write_fields[j] =
3129 shadow_read_write_fields[i];
3130 j++;
3131 }
3132 max_shadow_read_write_fields = j;
3133
3134 /* shadowed fields guest access without vmexit */
3135 for (i = 0; i < max_shadow_read_write_fields; i++) {
3136 clear_bit(shadow_read_write_fields[i],
3137 vmx_vmwrite_bitmap);
3138 clear_bit(shadow_read_write_fields[i],
3139 vmx_vmread_bitmap);
3140 }
3141 for (i = 0; i < max_shadow_read_only_fields; i++)
3142 clear_bit(shadow_read_only_fields[i],
3143 vmx_vmread_bitmap);
3144}
3145
6aa8b732
AK		 3146static __init int alloc_kvm_area(void)
3147{
3148 int cpu;
3149
3230bb47 3150 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3151 struct vmcs *vmcs;
3152
3153 vmcs = alloc_vmcs_cpu(cpu);
3154 if (!vmcs) {
3155 free_kvm_area();
3156 return -ENOMEM;
3157 }
3158
3159 per_cpu(vmxarea, cpu) = vmcs;
3160 }
3161 return 0;
3162}
3163
14168786
GN		 3164static bool emulation_required(struct kvm_vcpu *vcpu)
3165{
3166 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3167}
3168
91b0aa2c 3169static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3170 struct kvm_segment *save)
6aa8b732 3171{
d99e4152
GN		 3172 if (!emulate_invalid_guest_state) {
3173 /*
3174 * CS and SS RPL should be equal during guest entry according
3175 * to VMX spec, but in reality it is not always so. Since vcpu
3176 * is in the middle of the transition from real mode to
3177 * protected mode it is safe to assume that RPL 0 is a good
3178 * default value.
3179 */
3180 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3181 save->selector &= ~SELECTOR_RPL_MASK;
3182 save->dpl = save->selector & SELECTOR_RPL_MASK;
3183 save->s = 1;
6aa8b732 3184 }
d99e4152 3185 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3186}
3187
3188static void enter_pmode(struct kvm_vcpu *vcpu)
3189{
3190 unsigned long flags;
a89a8fb9 3191 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3192
d99e4152
GN		 3193 /*
3194 * Update real mode segment cache. It may be not up-to-date if sement
3195 * register was written while vcpu was in a guest mode.
3196 */
3197 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3198 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3199 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3200 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3201 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3202 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3203
7ffd92c5 3204 vmx->rmode.vm86_active = 0;
6aa8b732 3205
2fb92db1
AK		 3206 vmx_segment_cache_clear(vmx);
3207
f5f7b2fe 3208 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3209
3210 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3211 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3212 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3213 vmcs_writel(GUEST_RFLAGS, flags);
3214
66aee91a
RR		 3215 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3216 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3217
3218 update_exception_bitmap(vcpu);
3219
91b0aa2c
GN		 3220 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3221 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3222 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3223 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3224 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3225 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3226}
3227
f5f7b2fe 3228static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3229{
772e0318 3230 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3231 struct kvm_segment var = *save;
3232
3233 var.dpl = 0x3;
3234 if (seg == VCPU_SREG_CS)
3235 var.type = 0x3;
3236
3237 if (!emulate_invalid_guest_state) {
3238 var.selector = var.base >> 4;
3239 var.base = var.base & 0xffff0;
3240 var.limit = 0xffff;
3241 var.g = 0;
3242 var.db = 0;
3243 var.present = 1;
3244 var.s = 1;
3245 var.l = 0;
3246 var.unusable = 0;
3247 var.type = 0x3;
3248 var.avl = 0;
3249 if (save->base & 0xf)
3250 printk_once(KERN_WARNING "kvm: segment base is not "
3251 "paragraph aligned when entering "
3252 "protected mode (seg=%d)", seg);
3253 }
6aa8b732 3254
d99e4152
GN		 3255 vmcs_write16(sf->selector, var.selector);
3256 vmcs_write32(sf->base, var.base);
3257 vmcs_write32(sf->limit, var.limit);
3258 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3259}
3260
3261static void enter_rmode(struct kvm_vcpu *vcpu)
3262{
3263 unsigned long flags;
a89a8fb9 3264 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3265
f5f7b2fe
AK		 3266 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3267 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3268 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3269 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3270 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3271 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3272 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3273
7ffd92c5 3274 vmx->rmode.vm86_active = 1;
6aa8b732 3275
776e58ea
GN		 3276 /*
3277 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3278 * vcpu. Warn the user that an update is overdue.
776e58ea 3279 */
4918c6ca 3280 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3281 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3282 "called before entering vcpu\n");
776e58ea 3283
2fb92db1
AK		 3284 vmx_segment_cache_clear(vmx);
3285
4918c6ca 3286 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3287 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3288 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3289
3290 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3291 vmx->rmode.save_rflags = flags;
6aa8b732 3292
053de044 3293 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3294
3295 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3296 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3297 update_exception_bitmap(vcpu);
3298
d99e4152
GN		 3299 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3300 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3301 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3302 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3303 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3304 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3305
8668a3c4 3306 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3307}
3308
401d10de
AS		 3309static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3310{
3311 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3312 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3313
3314 if (!msr)
3315 return;
401d10de 3316
44ea2b17
AK		 3317 /*
3318 * Force kernel_gs_base reloading before EFER changes, as control
3319 * of this msr depends on is_long_mode().
3320 */
3321 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3322 vcpu->arch.efer = efer;
401d10de 3323 if (efer & EFER_LMA) {
2961e876 3324 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3325 msr->data = efer;
3326 } else {
2961e876 3327 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3328
3329 msr->data = efer & ~EFER_LME;
3330 }
3331 setup_msrs(vmx);
3332}
3333
05b3e0c2 3334#ifdef CONFIG_X86_64
6aa8b732
AK		 3335
3336static void enter_lmode(struct kvm_vcpu *vcpu)
3337{
3338 u32 guest_tr_ar;
3339
2fb92db1
AK		 3340 vmx_segment_cache_clear(to_vmx(vcpu));
3341
6aa8b732
AK		 3342 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3343 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3344 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3345 __func__);
6aa8b732
AK		 3346 vmcs_write32(GUEST_TR_AR_BYTES,
3347 (guest_tr_ar & ~AR_TYPE_MASK)
3348 | AR_TYPE_BUSY_64_TSS);
3349 }
da38f438 3350 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3351}
3352
3353static void exit_lmode(struct kvm_vcpu *vcpu)
3354{
2961e876 3355 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3356 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3357}
3358
3359#endif
3360
2384d2b3
SY		 3361static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3362{
b9d762fa 3363 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3364 if (enable_ept) {
3365 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3366 return;
4e1096d2 3367 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3368 }
2384d2b3
SY		 3369}
3370
e8467fda
AK		 3371static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3372{
3373 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3374
3375 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3376 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3377}
3378
aff48baa
AK		 3379static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3380{
3381 if (enable_ept && is_paging(vcpu))
3382 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3383 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3384}
3385
25c4c276 3386static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3387{
fc78f519
AK		 3388 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3389
3390 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3391 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3392}
3393
1439442c
SY		 3394static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3395{
d0d538b9
GN		 3396 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3397
6de4f3ad
AK		 3398 if (!test_bit(VCPU_EXREG_PDPTR,
3399 (unsigned long *)&vcpu->arch.regs_dirty))
3400 return;
3401
1439442c 3402 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3403 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3404 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3405 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3406 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3407 }
3408}
3409
8f5d549f
AK		 3410static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3411{
d0d538b9
GN		 3412 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3413
8f5d549f 3414 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3415 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3416 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3417 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3418 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3419 }
6de4f3ad
AK		 3420
3421 __set_bit(VCPU_EXREG_PDPTR,
3422 (unsigned long *)&vcpu->arch.regs_avail);
3423 __set_bit(VCPU_EXREG_PDPTR,
3424 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3425}
3426
5e1746d6 3427static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3428
3429static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3430 unsigned long cr0,
3431 struct kvm_vcpu *vcpu)
3432{
5233dd51
MT		 3433 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3434 vmx_decache_cr3(vcpu);
1439442c
SY		 3435 if (!(cr0 & X86_CR0_PG)) {
3436 /* From paging/starting to nonpaging */
3437 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3438 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3439 (CPU_BASED_CR3_LOAD_EXITING |
3440 CPU_BASED_CR3_STORE_EXITING));
3441 vcpu->arch.cr0 = cr0;
fc78f519 3442 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3443 } else if (!is_paging(vcpu)) {
3444 /* From nonpaging to paging */
3445 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3446 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3447 ~(CPU_BASED_CR3_LOAD_EXITING |
3448 CPU_BASED_CR3_STORE_EXITING));
3449 vcpu->arch.cr0 = cr0;
fc78f519 3450 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3451 }
95eb84a7
SY		 3452
3453 if (!(cr0 & X86_CR0_WP))
3454 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3455}
3456
6aa8b732
AK		 3457static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3458{
7ffd92c5 3459 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3460 unsigned long hw_cr0;
3461
5037878e 3462 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3463 if (enable_unrestricted_guest)
5037878e 3464 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3465 else {
5037878e 3466 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3467
218e763f
GN		 3468 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3469 enter_pmode(vcpu);
6aa8b732 3470
218e763f
GN		 3471 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3472 enter_rmode(vcpu);
3473 }
6aa8b732 3474
05b3e0c2 3475#ifdef CONFIG_X86_64
f6801dff 3476 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3477 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3478 enter_lmode(vcpu);
707d92fa 3479 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3480 exit_lmode(vcpu);
3481 }
3482#endif
3483
089d034e 3484 if (enable_ept)
1439442c
SY		 3485 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3486
02daab21 3487 if (!vcpu->fpu_active)
81231c69 3488 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3489
6aa8b732 3490 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3491 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3492 vcpu->arch.cr0 = cr0;
14168786
GN		 3493
3494 /* depends on vcpu->arch.cr0 to be set to a new value */
3495 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3496}
3497
1439442c
SY		 3498static u64 construct_eptp(unsigned long root_hpa)
3499{
3500 u64 eptp;
3501
3502 /* TODO write the value reading from MSR */
3503 eptp = VMX_EPT_DEFAULT_MT |
3504 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3505 if (enable_ept_ad_bits)
3506 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3507 eptp |= (root_hpa & PAGE_MASK);
3508
3509 return eptp;
3510}
3511
6aa8b732
AK		 3512static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3513{
1439442c
SY		 3514 unsigned long guest_cr3;
3515 u64 eptp;
3516
3517 guest_cr3 = cr3;
089d034e 3518 if (enable_ept) {
1439442c
SY		 3519 eptp = construct_eptp(cr3);
3520 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3521 if (is_paging(vcpu) || is_guest_mode(vcpu))
3522 guest_cr3 = kvm_read_cr3(vcpu);
3523 else
3524 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3525 ept_load_pdptrs(vcpu);
1439442c
SY		 3526 }
3527
2384d2b3 3528 vmx_flush_tlb(vcpu);
1439442c 3529 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3530}
3531
5e1746d6 3532static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3533{
7ffd92c5 3534 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3535 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3536
5e1746d6
NHE		 3537 if (cr4 & X86_CR4_VMXE) {
3538 /*
3539 * To use VMXON (and later other VMX instructions), a guest
3540 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3541 * So basically the check on whether to allow nested VMX
3542 * is here.
3543 */
3544 if (!nested_vmx_allowed(vcpu))
3545 return 1;
1a0d74e6
JK		 3546 }
3547 if (to_vmx(vcpu)->nested.vmxon &&
3548 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3549 return 1;
3550
ad312c7c 3551 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3552 if (enable_ept) {
3553 if (!is_paging(vcpu)) {
3554 hw_cr4 &= ~X86_CR4_PAE;
3555 hw_cr4 |= X86_CR4_PSE;
c08800a5 3556 /*
e1e746b3
FW		 3557 * SMEP/SMAP is disabled if CPU is in non-paging mode
3558 * in hardware. However KVM always uses paging mode to
c08800a5 3559 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3560 * To emulate this behavior, SMEP/SMAP needs to be
3561 * manually disabled when guest switches to non-paging
3562 * mode.
c08800a5 3563 */
e1e746b3 3564 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3565 } else if (!(cr4 & X86_CR4_PAE)) {
3566 hw_cr4 &= ~X86_CR4_PAE;
3567 }
3568 }
1439442c
SY		 3569
3570 vmcs_writel(CR4_READ_SHADOW, cr4);
3571 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3572 return 0;
6aa8b732
AK		 3573}
3574
6aa8b732
AK		 3575static void vmx_get_segment(struct kvm_vcpu *vcpu,
3576 struct kvm_segment *var, int seg)
3577{
a9179499 3578 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3579 u32 ar;
3580
c6ad1153 3581 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3582 *var = vmx->rmode.segs[seg];
a9179499 3583 if (seg == VCPU_SREG_TR
2fb92db1 3584 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3585 return;
1390a28b
AK		 3586 var->base = vmx_read_guest_seg_base(vmx, seg);
3587 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3588 return;
a9179499 3589 }
2fb92db1
AK		 3590 var->base = vmx_read_guest_seg_base(vmx, seg);
3591 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3592 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3593 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3594 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3595 var->type = ar & 15;
3596 var->s = (ar >> 4) & 1;
3597 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3598 /*
3599 * Some userspaces do not preserve unusable property. Since usable
3600 * segment has to be present according to VMX spec we can use present
3601 * property to amend userspace bug by making unusable segment always
3602 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3603 * segment as unusable.
3604 */
3605 var->present = !var->unusable;
6aa8b732
AK		 3606 var->avl = (ar >> 12) & 1;
3607 var->l = (ar >> 13) & 1;
3608 var->db = (ar >> 14) & 1;
3609 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3610}
3611
a9179499
AK		 3612static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3613{
a9179499
AK		 3614 struct kvm_segment s;
3615
3616 if (to_vmx(vcpu)->rmode.vm86_active) {
3617 vmx_get_segment(vcpu, &s, seg);
3618 return s.base;
3619 }
2fb92db1 3620 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3621}
3622
b09408d0 3623static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3624{
b09408d0
MT		 3625 struct vcpu_vmx *vmx = to_vmx(vcpu);
3626
ae9fedc7 3627 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3628 return 0;
ae9fedc7
PB		 3629 else {
3630 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3631 return AR_DPL(ar);
69c73028 3632 }
69c73028
AK		 3633}
3634
653e3108 3635static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3636{
6aa8b732
AK		 3637 u32 ar;
3638
f0495f9b 3639 if (var->unusable || !var->present)
6aa8b732
AK		 3640 ar = 1 << 16;
3641 else {
3642 ar = var->type & 15;
3643 ar |= (var->s & 1) << 4;
3644 ar |= (var->dpl & 3) << 5;
3645 ar |= (var->present & 1) << 7;
3646 ar |= (var->avl & 1) << 12;
3647 ar |= (var->l & 1) << 13;
3648 ar |= (var->db & 1) << 14;
3649 ar |= (var->g & 1) << 15;
3650 }
653e3108
AK		 3651
3652 return ar;
3653}
3654
3655static void vmx_set_segment(struct kvm_vcpu *vcpu,
3656 struct kvm_segment *var, int seg)
3657{
7ffd92c5 3658 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3659 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3660
2fb92db1
AK		 3661 vmx_segment_cache_clear(vmx);
3662
1ecd50a9
GN		 3663 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3664 vmx->rmode.segs[seg] = *var;
3665 if (seg == VCPU_SREG_TR)
3666 vmcs_write16(sf->selector, var->selector);
3667 else if (var->s)
3668 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3669 goto out;
653e3108 3670 }
1ecd50a9 3671
653e3108
AK		 3672 vmcs_writel(sf->base, var->base);
3673 vmcs_write32(sf->limit, var->limit);
3674 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3675
3676 /*
3677 * Fix the "Accessed" bit in AR field of segment registers for older
3678 * qemu binaries.
3679 * IA32 arch specifies that at the time of processor reset the
3680 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3681 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3682 * state vmexit when "unrestricted guest" mode is turned on.
3683 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3684 * tree. Newer qemu binaries with that qemu fix would not need this
3685 * kvm hack.
3686 */
3687 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3688 var->type |= 0x1; /* Accessed */
3a624e29 3689
f924d66d 3690 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3691
3692out:
98eb2f8b 3693 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3694}
3695
6aa8b732
AK		 3696static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3697{
2fb92db1 3698 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3699
3700 *db = (ar >> 14) & 1;
3701 *l = (ar >> 13) & 1;
3702}
3703
89a27f4d 3704static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3705{
89a27f4d
GN		 3706 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3707 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3708}
3709
89a27f4d 3710static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3711{
89a27f4d
GN		 3712 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3713 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3714}
3715
89a27f4d 3716static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3717{
89a27f4d
GN		 3718 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3719 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3720}
3721
89a27f4d 3722static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3723{
89a27f4d
GN		 3724 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3725 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3726}
3727
648dfaa7
MG		 3728static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3729{
3730 struct kvm_segment var;
3731 u32 ar;
3732
3733 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3734 var.dpl = 0x3;
0647f4aa
GN		 3735 if (seg == VCPU_SREG_CS)
3736 var.type = 0x3;
648dfaa7
MG		 3737 ar = vmx_segment_access_rights(&var);
3738
3739 if (var.base != (var.selector << 4))
3740 return false;
89efbed0 3741 if (var.limit != 0xffff)
648dfaa7 3742 return false;
07f42f5f 3743 if (ar != 0xf3)
648dfaa7
MG		 3744 return false;
3745
3746 return true;
3747}
3748
3749static bool code_segment_valid(struct kvm_vcpu *vcpu)
3750{
3751 struct kvm_segment cs;
3752 unsigned int cs_rpl;
3753
3754 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3755 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3756
1872a3f4
AK		 3757 if (cs.unusable)
3758 return false;
648dfaa7
MG		 3759 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3760 return false;
3761 if (!cs.s)
3762 return false;
1872a3f4 3763 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3764 if (cs.dpl > cs_rpl)
3765 return false;
1872a3f4 3766 } else {
648dfaa7
MG		 3767 if (cs.dpl != cs_rpl)
3768 return false;
3769 }
3770 if (!cs.present)
3771 return false;
3772
3773 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3774 return true;
3775}
3776
3777static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3778{
3779 struct kvm_segment ss;
3780 unsigned int ss_rpl;
3781
3782 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3783 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3784
1872a3f4
AK		 3785 if (ss.unusable)
3786 return true;
3787 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3788 return false;
3789 if (!ss.s)
3790 return false;
3791 if (ss.dpl != ss_rpl) /* DPL != RPL */
3792 return false;
3793 if (!ss.present)
3794 return false;
3795
3796 return true;
3797}
3798
3799static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3800{
3801 struct kvm_segment var;
3802 unsigned int rpl;
3803
3804 vmx_get_segment(vcpu, &var, seg);
3805 rpl = var.selector & SELECTOR_RPL_MASK;
3806
1872a3f4
AK		 3807 if (var.unusable)
3808 return true;
648dfaa7
MG		 3809 if (!var.s)
3810 return false;
3811 if (!var.present)
3812 return false;
3813 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3814 if (var.dpl < rpl) /* DPL < RPL */
3815 return false;
3816 }
3817
3818 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3819 * rights flags
3820 */
3821 return true;
3822}
3823
3824static bool tr_valid(struct kvm_vcpu *vcpu)
3825{
3826 struct kvm_segment tr;
3827
3828 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3829
1872a3f4
AK		 3830 if (tr.unusable)
3831 return false;
648dfaa7
MG		 3832 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3833 return false;
1872a3f4 3834 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3835 return false;
3836 if (!tr.present)
3837 return false;
3838
3839 return true;
3840}
3841
3842static bool ldtr_valid(struct kvm_vcpu *vcpu)
3843{
3844 struct kvm_segment ldtr;
3845
3846 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3847
1872a3f4
AK		 3848 if (ldtr.unusable)
3849 return true;
648dfaa7
MG		 3850 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3851 return false;
3852 if (ldtr.type != 2)
3853 return false;
3854 if (!ldtr.present)
3855 return false;
3856
3857 return true;
3858}
3859
3860static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3861{
3862 struct kvm_segment cs, ss;
3863
3864 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3865 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3866
3867 return ((cs.selector & SELECTOR_RPL_MASK) ==
3868 (ss.selector & SELECTOR_RPL_MASK));
3869}
3870
3871/*
3872 * Check if guest state is valid. Returns true if valid, false if
3873 * not.
3874 * We assume that registers are always usable
3875 */
3876static bool guest_state_valid(struct kvm_vcpu *vcpu)
3877{
c5e97c80
GN		 3878 if (enable_unrestricted_guest)
3879 return true;
3880
648dfaa7 3881 /* real mode guest state checks */
f13882d8 3882 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3883 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3884 return false;
3885 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3886 return false;
3887 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3888 return false;
3889 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3890 return false;
3891 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3892 return false;
3893 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3894 return false;
3895 } else {
3896 /* protected mode guest state checks */
3897 if (!cs_ss_rpl_check(vcpu))
3898 return false;
3899 if (!code_segment_valid(vcpu))
3900 return false;
3901 if (!stack_segment_valid(vcpu))
3902 return false;
3903 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3904 return false;
3905 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3906 return false;
3907 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3908 return false;
3909 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3910 return false;
3911 if (!tr_valid(vcpu))
3912 return false;
3913 if (!ldtr_valid(vcpu))
3914 return false;
3915 }
3916 /* TODO:
3917 * - Add checks on RIP
3918 * - Add checks on RFLAGS
3919 */
3920
3921 return true;
3922}
3923
d77c26fc 3924static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3925{
40dcaa9f 3926 gfn_t fn;
195aefde 3927 u16 data = 0;
1f755a82 3928 int idx, r;
6aa8b732 3929
40dcaa9f 3930 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3931 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3932 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3933 if (r < 0)
10589a46 3934 goto out;
195aefde 3935 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3936 r = kvm_write_guest_page(kvm, fn++, &data,
3937 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3938 if (r < 0)
10589a46 3939 goto out;
195aefde
IE		 3940 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3941 if (r < 0)
10589a46 3942 goto out;
195aefde
IE		 3943 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3944 if (r < 0)
10589a46 3945 goto out;
195aefde 3946 data = ~0;
10589a46
MT		 3947 r = kvm_write_guest_page(kvm, fn, &data,
3948 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3949 sizeof(u8));
10589a46 3950out:
40dcaa9f 3951 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3952 return r;
6aa8b732
AK		 3953}
3954
b7ebfb05
SY		 3955static int init_rmode_identity_map(struct kvm *kvm)
3956{
f51770ed 3957 int i, idx, r = 0;
b7ebfb05
SY		 3958 pfn_t identity_map_pfn;
3959 u32 tmp;
3960
089d034e 3961 if (!enable_ept)
f51770ed 3962 return 0;
a255d479
TC		 3963
3964 /* Protect kvm->arch.ept_identity_pagetable_done. */
3965 mutex_lock(&kvm->slots_lock);
3966
f51770ed 3967 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3968 goto out2;
a255d479 3969
b927a3ce 3970 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3971
3972 r = alloc_identity_pagetable(kvm);
f51770ed 3973 if (r < 0)
a255d479
TC		 3974 goto out2;
3975
40dcaa9f 3976 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3977 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3978 if (r < 0)
3979 goto out;
3980 /* Set up identity-mapping pagetable for EPT in real mode */
3981 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3982 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3983 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3984 r = kvm_write_guest_page(kvm, identity_map_pfn,
3985 &tmp, i * sizeof(tmp), sizeof(tmp));
3986 if (r < 0)
3987 goto out;
3988 }
3989 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3990
b7ebfb05 3991out:
40dcaa9f 3992 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3993
3994out2:
3995 mutex_unlock(&kvm->slots_lock);
f51770ed 3996 return r;
b7ebfb05
SY		 3997}
3998
6aa8b732
AK		 3999static void seg_setup(int seg)
4000{
772e0318 4001 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4002 unsigned int ar;
6aa8b732
AK		 4003
4004 vmcs_write16(sf->selector, 0);
4005 vmcs_writel(sf->base, 0);
4006 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4007 ar = 0x93;
4008 if (seg == VCPU_SREG_CS)
4009 ar |= 0x08; /* code segment */
3a624e29
NK		 4010
4011 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4012}
4013
f78e0e2e
SY		 4014static int alloc_apic_access_page(struct kvm *kvm)
4015{
4484141a 4016 struct page *page;
f78e0e2e
SY		 4017 struct kvm_userspace_memory_region kvm_userspace_mem;
4018 int r = 0;
4019
79fac95e 4020 mutex_lock(&kvm->slots_lock);
c24ae0dc 4021 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4022 goto out;
4023 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4024 kvm_userspace_mem.flags = 0;
73a6d941 4025 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4026 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4027 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4028 if (r)
4029 goto out;
72dc67a6 4030
73a6d941 4031 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4032 if (is_error_page(page)) {
4033 r = -EFAULT;
4034 goto out;
4035 }
4036
c24ae0dc
TC		 4037 /*
4038 * Do not pin the page in memory, so that memory hot-unplug
4039 * is able to migrate it.
4040 */
4041 put_page(page);
4042 kvm->arch.apic_access_page_done = true;
f78e0e2e 4043out:
79fac95e 4044 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4045 return r;
4046}
4047
b7ebfb05
SY		 4048static int alloc_identity_pagetable(struct kvm *kvm)
4049{
a255d479
TC		 4050 /* Called with kvm->slots_lock held. */
4051
b7ebfb05
SY		 4052 struct kvm_userspace_memory_region kvm_userspace_mem;
4053 int r = 0;
4054
a255d479
TC		 4055 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4056
b7ebfb05
SY		 4057 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4058 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4059 kvm_userspace_mem.guest_phys_addr =
4060 kvm->arch.ept_identity_map_addr;
b7ebfb05 4061 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4062 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4063
b7ebfb05
SY		 4064 return r;
4065}
4066
2384d2b3
SY		 4067static void allocate_vpid(struct vcpu_vmx *vmx)
4068{
4069 int vpid;
4070
4071 vmx->vpid = 0;
919818ab 4072 if (!enable_vpid)
2384d2b3
SY		 4073 return;
4074 spin_lock(&vmx_vpid_lock);
4075 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4076 if (vpid < VMX_NR_VPIDS) {
4077 vmx->vpid = vpid;
4078 __set_bit(vpid, vmx_vpid_bitmap);
4079 }
4080 spin_unlock(&vmx_vpid_lock);
4081}
4082
cdbecfc3
LJ		 4083static void free_vpid(struct vcpu_vmx *vmx)
4084{
4085 if (!enable_vpid)
4086 return;
4087 spin_lock(&vmx_vpid_lock);
4088 if (vmx->vpid != 0)
4089 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4090 spin_unlock(&vmx_vpid_lock);
4091}
4092
8d14695f
YZ		 4093#define MSR_TYPE_R 1
4094#define MSR_TYPE_W 2
4095static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4096 u32 msr, int type)
25c5f225 4097{
3e7c73e9 4098 int f = sizeof(unsigned long);
25c5f225
SY		 4099
4100 if (!cpu_has_vmx_msr_bitmap())
4101 return;
4102
4103 /*
4104 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4105 * have the write-low and read-high bitmap offsets the wrong way round.
4106 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4107 */
25c5f225 4108 if (msr <= 0x1fff) {
8d14695f
YZ		 4109 if (type & MSR_TYPE_R)
4110 /* read-low */
4111 __clear_bit(msr, msr_bitmap + 0x000 / f);
4112
4113 if (type & MSR_TYPE_W)
4114 /* write-low */
4115 __clear_bit(msr, msr_bitmap + 0x800 / f);
4116
25c5f225
SY		 4117 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4118 msr &= 0x1fff;
8d14695f
YZ		 4119 if (type & MSR_TYPE_R)
4120 /* read-high */
4121 __clear_bit(msr, msr_bitmap + 0x400 / f);
4122
4123 if (type & MSR_TYPE_W)
4124 /* write-high */
4125 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4126
4127 }
4128}
4129
4130static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4131 u32 msr, int type)
4132{
4133 int f = sizeof(unsigned long);
4134
4135 if (!cpu_has_vmx_msr_bitmap())
4136 return;
4137
4138 /*
4139 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4140 * have the write-low and read-high bitmap offsets the wrong way round.
4141 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4142 */
4143 if (msr <= 0x1fff) {
4144 if (type & MSR_TYPE_R)
4145 /* read-low */
4146 __set_bit(msr, msr_bitmap + 0x000 / f);
4147
4148 if (type & MSR_TYPE_W)
4149 /* write-low */
4150 __set_bit(msr, msr_bitmap + 0x800 / f);
4151
4152 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4153 msr &= 0x1fff;
4154 if (type & MSR_TYPE_R)
4155 /* read-high */
4156 __set_bit(msr, msr_bitmap + 0x400 / f);
4157
4158 if (type & MSR_TYPE_W)
4159 /* write-high */
4160 __set_bit(msr, msr_bitmap + 0xc00 / f);
4161
25c5f225 4162 }
25c5f225
SY		 4163}
4164
5897297b
AK		 4165static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4166{
4167 if (!longmode_only)
8d14695f
YZ		 4168 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4169 msr, MSR_TYPE_R | MSR_TYPE_W);
4170 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4171 msr, MSR_TYPE_R | MSR_TYPE_W);
4172}
4173
4174static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4175{
4176 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4177 msr, MSR_TYPE_R);
4178 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4179 msr, MSR_TYPE_R);
4180}
4181
4182static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4183{
4184 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4185 msr, MSR_TYPE_R);
4186 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4187 msr, MSR_TYPE_R);
4188}
4189
4190static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4191{
4192 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4193 msr, MSR_TYPE_W);
4194 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4195 msr, MSR_TYPE_W);
5897297b
AK		 4196}
4197
01e439be
YZ		 4198static int vmx_vm_has_apicv(struct kvm *kvm)
4199{
4200 return enable_apicv && irqchip_in_kernel(kvm);
4201}
4202
a20ed54d
YZ		 4203/*
4204 * Send interrupt to vcpu via posted interrupt way.
4205 * 1. If target vcpu is running(non-root mode), send posted interrupt
4206 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4207 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4208 * interrupt from PIR in next vmentry.
4209 */
4210static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4211{
4212 struct vcpu_vmx *vmx = to_vmx(vcpu);
4213 int r;
4214
4215 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4216 return;
4217
4218 r = pi_test_and_set_on(&vmx->pi_desc);
4219 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4220#ifdef CONFIG_SMP
a20ed54d
YZ		 4221 if (!r && (vcpu->mode == IN_GUEST_MODE))
4222 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4223 POSTED_INTR_VECTOR);
4224 else
6ffbbbba 4225#endif
a20ed54d
YZ		 4226 kvm_vcpu_kick(vcpu);
4227}
4228
4229static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4230{
4231 struct vcpu_vmx *vmx = to_vmx(vcpu);
4232
4233 if (!pi_test_and_clear_on(&vmx->pi_desc))
4234 return;
4235
4236 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4237}
4238
4239static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4240{
4241 return;
4242}
4243
a3a8ff8e
NHE		 4244/*
4245 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4246 * will not change in the lifetime of the guest.
4247 * Note that host-state that does change is set elsewhere. E.g., host-state
4248 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4249 */
a547c6db 4250static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4251{
4252 u32 low32, high32;
4253 unsigned long tmpl;
4254 struct desc_ptr dt;
d974baa3 4255 unsigned long cr4;
a3a8ff8e 4256
b1a74bf8 4257 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4258 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4259
d974baa3
AL		 4260 /* Save the most likely value for this task's CR4 in the VMCS. */
4261 cr4 = read_cr4();
4262 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4263 vmx->host_state.vmcs_host_cr4 = cr4;
4264
a3a8ff8e 4265 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4266#ifdef CONFIG_X86_64
4267 /*
4268 * Load null selectors, so we can avoid reloading them in
4269 * __vmx_load_host_state(), in case userspace uses the null selectors
4270 * too (the expected case).
4271 */
4272 vmcs_write16(HOST_DS_SELECTOR, 0);
4273 vmcs_write16(HOST_ES_SELECTOR, 0);
4274#else
a3a8ff8e
NHE		 4275 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4276 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4277#endif
a3a8ff8e
NHE		 4278 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4279 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4280
4281 native_store_idt(&dt);
4282 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4283 vmx->host_idt_base = dt.address;
a3a8ff8e 4284
83287ea4 4285 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4286
4287 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4288 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4289 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4290 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4291
4292 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4293 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4294 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4295 }
4296}
4297
bf8179a0
NHE		 4298static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4299{
4300 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4301 if (enable_ept)
4302 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4303 if (is_guest_mode(&vmx->vcpu))
4304 vmx->vcpu.arch.cr4_guest_owned_bits &=
4305 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4306 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4307}
4308
01e439be
YZ		 4309static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4310{
4311 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4312
4313 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4314 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4315 return pin_based_exec_ctrl;
4316}
4317
bf8179a0
NHE		 4318static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4319{
4320 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4321
4322 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4323 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4324
bf8179a0
NHE		 4325 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4326 exec_control &= ~CPU_BASED_TPR_SHADOW;
4327#ifdef CONFIG_X86_64
4328 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4329 CPU_BASED_CR8_LOAD_EXITING;
4330#endif
4331 }
4332 if (!enable_ept)
4333 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4334 CPU_BASED_CR3_LOAD_EXITING |
4335 CPU_BASED_INVLPG_EXITING;
4336 return exec_control;
4337}
4338
4339static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4340{
4341 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4342 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4343 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4344 if (vmx->vpid == 0)
4345 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4346 if (!enable_ept) {
4347 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4348 enable_unrestricted_guest = 0;
ad756a16
MJ		 4349 /* Enable INVPCID for non-ept guests may cause performance regression. */
4350 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4351 }
4352 if (!enable_unrestricted_guest)
4353 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4354 if (!ple_gap)
4355 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4356 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4357 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4358 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4359 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4360 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4361 (handle_vmptrld).
4362 We can NOT enable shadow_vmcs here because we don't have yet
4363 a current VMCS12
4364 */
4365 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4366 /* PML is enabled/disabled in creating/destorying vcpu */
4367 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4368
bf8179a0
NHE		 4369 return exec_control;
4370}
4371
ce88decf
XG		 4372static void ept_set_mmio_spte_mask(void)
4373{
4374 /*
4375 * EPT Misconfigurations can be generated if the value of bits 2:0
4376 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4377 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4378 * spte.
4379 */
885032b9 4380 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4381}
4382
f53cd63c 4383#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4384/*
4385 * Sets up the vmcs for emulated real mode.
4386 */
8b9cf98c 4387static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4388{
2e4ce7f5 4389#ifdef CONFIG_X86_64
6aa8b732 4390 unsigned long a;
2e4ce7f5 4391#endif
6aa8b732 4392 int i;
6aa8b732 4393
6aa8b732 4394 /* I/O */
3e7c73e9
AK		 4395 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4396 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4397
4607c2d7
AG		 4398 if (enable_shadow_vmcs) {
4399 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4400 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4401 }
25c5f225 4402 if (cpu_has_vmx_msr_bitmap())
5897297b 4403 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4404
6aa8b732
AK		 4405 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4406
6aa8b732 4407 /* Control */
01e439be 4408 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4409
bf8179a0 4410 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4411
83ff3b9d 4412 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4413 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4414 vmx_secondary_exec_control(vmx));
83ff3b9d 4415 }
f78e0e2e 4416
01e439be 4417 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4418 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4419 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4420 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4421 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4422
4423 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4424
4425 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4426 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4427 }
4428
4b8d54f9
ZE		 4429 if (ple_gap) {
4430 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4431 vmx->ple_window = ple_window;
4432 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4433 }
4434
c3707958
XG		 4435 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4436 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4437 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4438
9581d442
AK		 4439 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4440 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4441 vmx_set_constant_host_state(vmx);
05b3e0c2 4442#ifdef CONFIG_X86_64
6aa8b732
AK		 4443 rdmsrl(MSR_FS_BASE, a);
4444 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4445 rdmsrl(MSR_GS_BASE, a);
4446 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4447#else
4448 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4449 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4450#endif
4451
2cc51560
ED		 4452 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4454 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4455 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4456 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4457
468d472f 4458 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4459 u32 msr_low, msr_high;
4460 u64 host_pat;
468d472f
SY		 4461 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4462 host_pat = msr_low | ((u64) msr_high << 32);
4463 /* Write the default value follow host pat */
4464 vmcs_write64(GUEST_IA32_PAT, host_pat);
4465 /* Keep arch.pat sync with GUEST_IA32_PAT */
4466 vmx->vcpu.arch.pat = host_pat;
4467 }
4468
03916db9 4469 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4470 u32 index = vmx_msr_index[i];
4471 u32 data_low, data_high;
a2fa3e9f 4472 int j = vmx->nmsrs;
6aa8b732
AK		 4473
4474 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4475 continue;
432bd6cb
AK		 4476 if (wrmsr_safe(index, data_low, data_high) < 0)
4477 continue;
26bb0981
AK		 4478 vmx->guest_msrs[j].index = i;
4479 vmx->guest_msrs[j].data = 0;
d5696725 4480 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4481 ++vmx->nmsrs;
6aa8b732 4482 }
6aa8b732 4483
2961e876
GN		 4484
4485 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4486
4487 /* 22.2.1, 20.8.1 */
2961e876 4488 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4489
e00c8cf2 4490 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4491 set_cr4_guest_host_mask(vmx);
e00c8cf2 4492
f53cd63c
WL		 4493 if (vmx_xsaves_supported())
4494 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4495
e00c8cf2
AK		 4496 return 0;
4497}
4498
57f252f2 4499static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4500{
4501 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4502 struct msr_data apic_base_msr;
e00c8cf2 4503
7ffd92c5 4504 vmx->rmode.vm86_active = 0;
e00c8cf2 4505
3b86cd99
JK		 4506 vmx->soft_vnmi_blocked = 0;
4507
ad312c7c 4508 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4509 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4510 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4511 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4512 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4513 apic_base_msr.host_initiated = true;
4514 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4515
2fb92db1
AK		 4516 vmx_segment_cache_clear(vmx);
4517
5706be0d 4518 seg_setup(VCPU_SREG_CS);
66450a21 4519 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4520 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4521
4522 seg_setup(VCPU_SREG_DS);
4523 seg_setup(VCPU_SREG_ES);
4524 seg_setup(VCPU_SREG_FS);
4525 seg_setup(VCPU_SREG_GS);
4526 seg_setup(VCPU_SREG_SS);
4527
4528 vmcs_write16(GUEST_TR_SELECTOR, 0);
4529 vmcs_writel(GUEST_TR_BASE, 0);
4530 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4531 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4532
4533 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4534 vmcs_writel(GUEST_LDTR_BASE, 0);
4535 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4536 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4537
4538 vmcs_write32(GUEST_SYSENTER_CS, 0);
4539 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4540 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4541
4542 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4543 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4544
e00c8cf2
AK		 4545 vmcs_writel(GUEST_GDTR_BASE, 0);
4546 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4547
4548 vmcs_writel(GUEST_IDTR_BASE, 0);
4549 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4550
443381a8 4551 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4552 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4553 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4554
e00c8cf2
AK		 4555 /* Special registers */
4556 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4557
4558 setup_msrs(vmx);
4559
6aa8b732
AK		 4560 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4561
f78e0e2e
SY		 4562 if (cpu_has_vmx_tpr_shadow()) {
4563 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4564 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4565 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4566 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4567 vmcs_write32(TPR_THRESHOLD, 0);
4568 }
4569
a73896cb 4570 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4571
01e439be
YZ		 4572 if (vmx_vm_has_apicv(vcpu->kvm))
4573 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4574
2384d2b3
SY		 4575 if (vmx->vpid != 0)
4576 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4577
fa40052c 4578 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4579 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4580 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4581 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4582 vmx_fpu_activate(&vmx->vcpu);
4583 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4584
b9d762fa 4585 vpid_sync_context(vmx);
6aa8b732
AK		 4586}
4587
b6f1250e
NHE		 4588/*
4589 * In nested virtualization, check if L1 asked to exit on external interrupts.
4590 * For most existing hypervisors, this will always return true.
4591 */
4592static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4593{
4594 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4595 PIN_BASED_EXT_INTR_MASK;
4596}
4597
77b0f5d6
BD		 4598/*
4599 * In nested virtualization, check if L1 has set
4600 * VM_EXIT_ACK_INTR_ON_EXIT
4601 */
4602static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4603{
4604 return get_vmcs12(vcpu)->vm_exit_controls &
4605 VM_EXIT_ACK_INTR_ON_EXIT;
4606}
4607
ea8ceb83
JK		 4608static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4609{
4610 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4611 PIN_BASED_NMI_EXITING;
4612}
4613
c9a7953f 4614static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4615{
4616 u32 cpu_based_vm_exec_control;
730dca42 4617
3b86cd99
JK		 4618 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4619 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4620 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4621}
4622
c9a7953f 4623static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4624{
4625 u32 cpu_based_vm_exec_control;
4626
c9a7953f
JK		 4627 if (!cpu_has_virtual_nmis() ||
4628 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4629 enable_irq_window(vcpu);
4630 return;
4631 }
3b86cd99
JK		 4632
4633 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4634 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4635 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4636}
4637
66fd3f7f 4638static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4639{
9c8cba37 4640 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4641 uint32_t intr;
4642 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4643
229456fc 4644 trace_kvm_inj_virq(irq);
2714d1d3 4645
fa89a817 4646 ++vcpu->stat.irq_injections;
7ffd92c5 4647 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4648 int inc_eip = 0;
4649 if (vcpu->arch.interrupt.soft)
4650 inc_eip = vcpu->arch.event_exit_inst_len;
4651 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4652 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4653 return;
4654 }
66fd3f7f
GN		 4655 intr = irq | INTR_INFO_VALID_MASK;
4656 if (vcpu->arch.interrupt.soft) {
4657 intr |= INTR_TYPE_SOFT_INTR;
4658 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4659 vmx->vcpu.arch.event_exit_inst_len);
4660 } else
4661 intr |= INTR_TYPE_EXT_INTR;
4662 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4663}
4664
f08864b4
SY		 4665static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4666{
66a5a347
JK		 4667 struct vcpu_vmx *vmx = to_vmx(vcpu);
4668
0b6ac343
NHE		 4669 if (is_guest_mode(vcpu))
4670 return;
4671
3b86cd99
JK		 4672 if (!cpu_has_virtual_nmis()) {
4673 /*
4674 * Tracking the NMI-blocked state in software is built upon
4675 * finding the next open IRQ window. This, in turn, depends on
4676 * well-behaving guests: They have to keep IRQs disabled at
4677 * least as long as the NMI handler runs. Otherwise we may
4678 * cause NMI nesting, maybe breaking the guest. But as this is
4679 * highly unlikely, we can live with the residual risk.
4680 */
4681 vmx->soft_vnmi_blocked = 1;
4682 vmx->vnmi_blocked_time = 0;
4683 }
4684
487b391d 4685 ++vcpu->stat.nmi_injections;
9d58b931 4686 vmx->nmi_known_unmasked = false;
7ffd92c5 4687 if (vmx->rmode.vm86_active) {
71f9833b 4688 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4689 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4690 return;
4691 }
f08864b4
SY		 4692 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4693 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4694}
4695
3cfc3092
JK		 4696static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4697{
4698 if (!cpu_has_virtual_nmis())
4699 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4700 if (to_vmx(vcpu)->nmi_known_unmasked)
4701 return false;
c332c83a 4702 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4703}
4704
4705static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4706{
4707 struct vcpu_vmx *vmx = to_vmx(vcpu);
4708
4709 if (!cpu_has_virtual_nmis()) {
4710 if (vmx->soft_vnmi_blocked != masked) {
4711 vmx->soft_vnmi_blocked = masked;
4712 vmx->vnmi_blocked_time = 0;
4713 }
4714 } else {
9d58b931 4715 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4716 if (masked)
4717 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4718 GUEST_INTR_STATE_NMI);
4719 else
4720 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4721 GUEST_INTR_STATE_NMI);
4722 }
4723}
4724
2505dc9f
JK		 4725static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4726{
b6b8a145
JK		 4727 if (to_vmx(vcpu)->nested.nested_run_pending)
4728 return 0;
ea8ceb83 4729
2505dc9f
JK		 4730 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4731 return 0;
4732
4733 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4734 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4735 | GUEST_INTR_STATE_NMI));
4736}
4737
78646121
GN		 4738static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4739{
b6b8a145
JK		 4740 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4741 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4742 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4743 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4744}
4745
cbc94022
IE		 4746static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4747{
4748 int ret;
4749 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4750 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4751 .guest_phys_addr = addr,
4752 .memory_size = PAGE_SIZE * 3,
4753 .flags = 0,
4754 };
4755
47ae31e2 4756 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4757 if (ret)
4758 return ret;
bfc6d222 4759 kvm->arch.tss_addr = addr;
1f755a82 4760 return init_rmode_tss(kvm);
cbc94022
IE		 4761}
4762
0ca1b4f4 4763static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4764{
77ab6db0 4765 switch (vec) {
77ab6db0 4766 case BP_VECTOR:
c573cd22
JK		 4767 /*
4768 * Update instruction length as we may reinject the exception
4769 * from user space while in guest debugging mode.
4770 */
4771 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4772 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4773 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4774 return false;
4775 /* fall through */
4776 case DB_VECTOR:
4777 if (vcpu->guest_debug &
4778 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4779 return false;
d0bfb940
JK		 4780 /* fall through */
4781 case DE_VECTOR:
77ab6db0
JK		 4782 case OF_VECTOR:
4783 case BR_VECTOR:
4784 case UD_VECTOR:
4785 case DF_VECTOR:
4786 case SS_VECTOR:
4787 case GP_VECTOR:
4788 case MF_VECTOR:
0ca1b4f4
GN		 4789 return true;
4790 break;
77ab6db0 4791 }
0ca1b4f4
GN		 4792 return false;
4793}
4794
4795static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4796 int vec, u32 err_code)
4797{
4798 /*
4799 * Instruction with address size override prefix opcode 0x67
4800 * Cause the #SS fault with 0 error code in VM86 mode.
4801 */
4802 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4803 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4804 if (vcpu->arch.halt_request) {
4805 vcpu->arch.halt_request = 0;
4806 return kvm_emulate_halt(vcpu);
4807 }
4808 return 1;
4809 }
4810 return 0;
4811 }
4812
4813 /*
4814 * Forward all other exceptions that are valid in real mode.
4815 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4816 * the required debugging infrastructure rework.
4817 */
4818 kvm_queue_exception(vcpu, vec);
4819 return 1;
6aa8b732
AK		 4820}
4821
a0861c02
AK		 4822/*
4823 * Trigger machine check on the host. We assume all the MSRs are already set up
4824 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4825 * We pass a fake environment to the machine check handler because we want
4826 * the guest to be always treated like user space, no matter what context
4827 * it used internally.
4828 */
4829static void kvm_machine_check(void)
4830{
4831#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4832 struct pt_regs regs = {
4833 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4834 .flags = X86_EFLAGS_IF,
4835 };
4836
4837 do_machine_check(&regs, 0);
4838#endif
4839}
4840
851ba692 4841static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4842{
4843 /* already handled by vcpu_run */
4844 return 1;
4845}
4846
851ba692 4847static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4848{
1155f76a 4849 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4850 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4851 u32 intr_info, ex_no, error_code;
42dbaa5a 4852 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4853 u32 vect_info;
4854 enum emulation_result er;
4855
1155f76a 4856 vect_info = vmx->idt_vectoring_info;
88786475 4857 intr_info = vmx->exit_intr_info;
6aa8b732 4858
a0861c02 4859 if (is_machine_check(intr_info))
851ba692 4860 return handle_machine_check(vcpu);
a0861c02 4861
e4a41889 4862 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4863 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4864
4865 if (is_no_device(intr_info)) {
5fd86fcf 4866 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4867 return 1;
4868 }
4869
7aa81cc0 4870 if (is_invalid_opcode(intr_info)) {
51d8b661 4871 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4872 if (er != EMULATE_DONE)
7ee5d940 4873 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4874 return 1;
4875 }
4876
6aa8b732 4877 error_code = 0;
2e11384c 4878 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4879 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4880
4881 /*
4882 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4883 * MMIO, it is better to report an internal error.
4884 * See the comments in vmx_handle_exit.
4885 */
4886 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4887 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4888 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4889 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4890 vcpu->run->internal.ndata = 2;
4891 vcpu->run->internal.data[0] = vect_info;
4892 vcpu->run->internal.data[1] = intr_info;
4893 return 0;
4894 }
4895
6aa8b732 4896 if (is_page_fault(intr_info)) {
1439442c 4897 /* EPT won't cause page fault directly */
cf3ace79 4898 BUG_ON(enable_ept);
6aa8b732 4899 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4900 trace_kvm_page_fault(cr2, error_code);
4901
3298b75c 4902 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4903 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4904 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4905 }
4906
d0bfb940 4907 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4908
4909 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4910 return handle_rmode_exception(vcpu, ex_no, error_code);
4911
42dbaa5a
JK		 4912 switch (ex_no) {
4913 case DB_VECTOR:
4914 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4915 if (!(vcpu->guest_debug &
4916 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4917 vcpu->arch.dr6 &= ~15;
6f43ed01 4918 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4919 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4920 skip_emulated_instruction(vcpu);
4921
42dbaa5a
JK		 4922 kvm_queue_exception(vcpu, DB_VECTOR);
4923 return 1;
4924 }
4925 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4926 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4927 /* fall through */
4928 case BP_VECTOR:
c573cd22
JK		 4929 /*
4930 * Update instruction length as we may reinject #BP from
4931 * user space while in guest debugging mode. Reading it for
4932 * #DB as well causes no harm, it is not used in that case.
4933 */
4934 vmx->vcpu.arch.event_exit_inst_len =
4935 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4936 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4937 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4938 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4939 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4940 break;
4941 default:
d0bfb940
JK		 4942 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4943 kvm_run->ex.exception = ex_no;
4944 kvm_run->ex.error_code = error_code;
42dbaa5a 4945 break;
6aa8b732 4946 }
6aa8b732
AK		 4947 return 0;
4948}
4949
851ba692 4950static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4951{
1165f5fe 4952 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4953 return 1;
4954}
4955
851ba692 4956static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4957{
851ba692 4958 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4959 return 0;
4960}
6aa8b732 4961
851ba692 4962static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4963{
bfdaab09 4964 unsigned long exit_qualification;
34c33d16 4965 int size, in, string;
039576c0 4966 unsigned port;
6aa8b732 4967
bfdaab09 4968 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4969 string = (exit_qualification & 16) != 0;
cf8f70bf 4970 in = (exit_qualification & 8) != 0;
e70669ab 4971
cf8f70bf 4972 ++vcpu->stat.io_exits;
e70669ab 4973
cf8f70bf 4974 if (string || in)
51d8b661 4975 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4976
cf8f70bf
GN		 4977 port = exit_qualification >> 16;
4978 size = (exit_qualification & 7) + 1;
e93f36bc 4979 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4980
4981 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4982}
4983
102d8325
IM		 4984static void
4985vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4986{
4987 /*
4988 * Patch in the VMCALL instruction:
4989 */
4990 hypercall[0] = 0x0f;
4991 hypercall[1] = 0x01;
4992 hypercall[2] = 0xc1;
102d8325
IM		 4993}
4994
92fbc7b1
JK		 4995static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4996{
4997 unsigned long always_on = VMXON_CR0_ALWAYSON;
4998
4999 if (nested_vmx_secondary_ctls_high &
5000 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5001 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5002 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5003 return (val & always_on) == always_on;
5004}
5005
0fa06071 5006/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5007static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5008{
eeadf9e7 5009 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5010 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5011 unsigned long orig_val = val;
5012
eeadf9e7
NHE		 5013 /*
5014 * We get here when L2 changed cr0 in a way that did not change
5015 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5016 * but did change L0 shadowed bits. So we first calculate the
5017 * effective cr0 value that L1 would like to write into the
5018 * hardware. It consists of the L2-owned bits from the new
5019 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5020 */
1a0d74e6
JK		 5021 val = (val & ~vmcs12->cr0_guest_host_mask) |
5022 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5023
92fbc7b1 5024 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5025 return 1;
1a0d74e6
JK		 5026
5027 if (kvm_set_cr0(vcpu, val))
5028 return 1;
5029 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5030 return 0;
1a0d74e6
JK		 5031 } else {
5032 if (to_vmx(vcpu)->nested.vmxon &&
5033 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5034 return 1;
eeadf9e7 5035 return kvm_set_cr0(vcpu, val);
1a0d74e6 5036 }
eeadf9e7
NHE		 5037}
5038
5039static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5040{
5041 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5042 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5043 unsigned long orig_val = val;
5044
5045 /* analogously to handle_set_cr0 */
5046 val = (val & ~vmcs12->cr4_guest_host_mask) |
5047 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5048 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5049 return 1;
1a0d74e6 5050 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5051 return 0;
5052 } else
5053 return kvm_set_cr4(vcpu, val);
5054}
5055
5056/* called to set cr0 as approriate for clts instruction exit. */
5057static void handle_clts(struct kvm_vcpu *vcpu)
5058{
5059 if (is_guest_mode(vcpu)) {
5060 /*
5061 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5062 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5063 * just pretend it's off (also in arch.cr0 for fpu_activate).
5064 */
5065 vmcs_writel(CR0_READ_SHADOW,
5066 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5067 vcpu->arch.cr0 &= ~X86_CR0_TS;
5068 } else
5069 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5070}
5071
851ba692 5072static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5073{
229456fc 5074 unsigned long exit_qualification, val;
6aa8b732
AK		 5075 int cr;
5076 int reg;
49a9b07e 5077 int err;
6aa8b732 5078
bfdaab09 5079 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5080 cr = exit_qualification & 15;
5081 reg = (exit_qualification >> 8) & 15;
5082 switch ((exit_qualification >> 4) & 3) {
5083 case 0: /* mov to cr */
1e32c079 5084 val = kvm_register_readl(vcpu, reg);
229456fc 5085 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5086 switch (cr) {
5087 case 0:
eeadf9e7 5088 err = handle_set_cr0(vcpu, val);
db8fcefa 5089 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5090 return 1;
5091 case 3:
2390218b 5092 err = kvm_set_cr3(vcpu, val);
db8fcefa 5093 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5094 return 1;
5095 case 4:
eeadf9e7 5096 err = handle_set_cr4(vcpu, val);
db8fcefa 5097 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5098 return 1;
0a5fff19
GN		 5099 case 8: {
5100 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5101 u8 cr8 = (u8)val;
eea1cff9 5102 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5103 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5104 if (irqchip_in_kernel(vcpu->kvm))
5105 return 1;
5106 if (cr8_prev <= cr8)
5107 return 1;
851ba692 5108 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5109 return 0;
5110 }
4b8073e4 5111 }
6aa8b732 5112 break;
25c4c276 5113 case 2: /* clts */
eeadf9e7 5114 handle_clts(vcpu);
4d4ec087 5115 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5116 skip_emulated_instruction(vcpu);
6b52d186 5117 vmx_fpu_activate(vcpu);
25c4c276 5118 return 1;
6aa8b732
AK		 5119 case 1: /*mov from cr*/
5120 switch (cr) {
5121 case 3:
9f8fe504
AK		 5122 val = kvm_read_cr3(vcpu);
5123 kvm_register_write(vcpu, reg, val);
5124 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5125 skip_emulated_instruction(vcpu);
5126 return 1;
5127 case 8:
229456fc
MT		 5128 val = kvm_get_cr8(vcpu);
5129 kvm_register_write(vcpu, reg, val);
5130 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5131 skip_emulated_instruction(vcpu);
5132 return 1;
5133 }
5134 break;
5135 case 3: /* lmsw */
a1f83a74 5136 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5137 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5138 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5139
5140 skip_emulated_instruction(vcpu);
5141 return 1;
5142 default:
5143 break;
5144 }
851ba692 5145 vcpu->run->exit_reason = 0;
a737f256 5146 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5147 (int)(exit_qualification >> 4) & 3, cr);
5148 return 0;
5149}
5150
851ba692 5151static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5152{
bfdaab09 5153 unsigned long exit_qualification;
16f8a6f9
NA		 5154 int dr, dr7, reg;
5155
5156 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5157 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5158
5159 /* First, if DR does not exist, trigger UD */
5160 if (!kvm_require_dr(vcpu, dr))
5161 return 1;
6aa8b732 5162
f2483415 5163 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5164 if (!kvm_require_cpl(vcpu, 0))
5165 return 1;
16f8a6f9
NA		 5166 dr7 = vmcs_readl(GUEST_DR7);
5167 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5168 /*
5169 * As the vm-exit takes precedence over the debug trap, we
5170 * need to emulate the latter, either for the host or the
5171 * guest debugging itself.
5172 */
5173 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5174 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5175 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5176 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5177 vcpu->run->debug.arch.exception = DB_VECTOR;
5178 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5179 return 0;
5180 } else {
7305eb5d 5181 vcpu->arch.dr6 &= ~15;
6f43ed01 5182 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5183 kvm_queue_exception(vcpu, DB_VECTOR);
5184 return 1;
5185 }
5186 }
5187
81908bf4
PB		 5188 if (vcpu->guest_debug == 0) {
5189 u32 cpu_based_vm_exec_control;
5190
5191 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5192 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5193 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5194
5195 /*
5196 * No more DR vmexits; force a reload of the debug registers
5197 * and reenter on this instruction. The next vmexit will
5198 * retrieve the full state of the debug registers.
5199 */
5200 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5201 return 1;
5202 }
5203
42dbaa5a
JK		 5204 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5205 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5206 unsigned long val;
4c4d563b
JK		 5207
5208 if (kvm_get_dr(vcpu, dr, &val))
5209 return 1;
5210 kvm_register_write(vcpu, reg, val);
020df079 5211 } else
5777392e 5212 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5213 return 1;
5214
6aa8b732
AK		 5215 skip_emulated_instruction(vcpu);
5216 return 1;
5217}
5218
73aaf249
JK		 5219static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5220{
5221 return vcpu->arch.dr6;
5222}
5223
5224static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5225{
5226}
5227
81908bf4
PB		 5228static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5229{
5230 u32 cpu_based_vm_exec_control;
5231
5232 get_debugreg(vcpu->arch.db[0], 0);
5233 get_debugreg(vcpu->arch.db[1], 1);
5234 get_debugreg(vcpu->arch.db[2], 2);
5235 get_debugreg(vcpu->arch.db[3], 3);
5236 get_debugreg(vcpu->arch.dr6, 6);
5237 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5238
5239 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5240
5241 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5242 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5243 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5244}
5245
020df079
GN		 5246static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5247{
5248 vmcs_writel(GUEST_DR7, val);
5249}
5250
851ba692 5251static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5252{
06465c5a
AK		 5253 kvm_emulate_cpuid(vcpu);
5254 return 1;
6aa8b732
AK		 5255}
5256
851ba692 5257static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5258{
ad312c7c 5259 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5260 u64 data;
5261
5262 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5263 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5264 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5265 return 1;
5266 }
5267
229456fc 5268 trace_kvm_msr_read(ecx, data);
2714d1d3 5269
6aa8b732 5270 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5271 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5272 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5273 skip_emulated_instruction(vcpu);
5274 return 1;
5275}
5276
851ba692 5277static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5278{
8fe8ab46 5279 struct msr_data msr;
ad312c7c
ZX		 5280 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5281 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5282 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5283
8fe8ab46
WA		 5284 msr.data = data;
5285 msr.index = ecx;
5286 msr.host_initiated = false;
854e8bb1 5287 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5288 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5289 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5290 return 1;
5291 }
5292
59200273 5293 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5294 skip_emulated_instruction(vcpu);
5295 return 1;
5296}
5297
851ba692 5298static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5299{
3842d135 5300 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5301 return 1;
5302}
5303
851ba692 5304static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5305{
85f455f7
ED		 5306 u32 cpu_based_vm_exec_control;
5307
5308 /* clear pending irq */
5309 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5310 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5311 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5312
3842d135
AK		 5313 kvm_make_request(KVM_REQ_EVENT, vcpu);
5314
a26bf12a 5315 ++vcpu->stat.irq_window_exits;
2714d1d3 5316
c1150d8c
DL		 5317 /*
5318 * If the user space waits to inject interrupts, exit as soon as
5319 * possible
5320 */
8061823a 5321 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5322 vcpu->run->request_interrupt_window &&
8061823a 5323 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5324 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5325 return 0;
5326 }
6aa8b732
AK		 5327 return 1;
5328}
5329
851ba692 5330static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5331{
5332 skip_emulated_instruction(vcpu);
d3bef15f 5333 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5334}
5335
851ba692 5336static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5337{
510043da 5338 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5339 kvm_emulate_hypercall(vcpu);
5340 return 1;
c21415e8
IM		 5341}
5342
ec25d5e6
GN		 5343static int handle_invd(struct kvm_vcpu *vcpu)
5344{
51d8b661 5345 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5346}
5347
851ba692 5348static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5349{
f9c617f6 5350 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5351
5352 kvm_mmu_invlpg(vcpu, exit_qualification);
5353 skip_emulated_instruction(vcpu);
5354 return 1;
5355}
5356
fee84b07
AK		 5357static int handle_rdpmc(struct kvm_vcpu *vcpu)
5358{
5359 int err;
5360
5361 err = kvm_rdpmc(vcpu);
5362 kvm_complete_insn_gp(vcpu, err);
5363
5364 return 1;
5365}
5366
851ba692 5367static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5368{
5369 skip_emulated_instruction(vcpu);
f5f48ee1 5370 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5371 return 1;
5372}
5373
2acf923e
DC		 5374static int handle_xsetbv(struct kvm_vcpu *vcpu)
5375{
5376 u64 new_bv = kvm_read_edx_eax(vcpu);
5377 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5378
5379 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5380 skip_emulated_instruction(vcpu);
5381 return 1;
5382}
5383
f53cd63c
WL		 5384static int handle_xsaves(struct kvm_vcpu *vcpu)
5385{
5386 skip_emulated_instruction(vcpu);
5387 WARN(1, "this should never happen\n");
5388 return 1;
5389}
5390
5391static int handle_xrstors(struct kvm_vcpu *vcpu)
5392{
5393 skip_emulated_instruction(vcpu);
5394 WARN(1, "this should never happen\n");
5395 return 1;
5396}
5397
851ba692 5398static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5399{
58fbbf26
KT		 5400 if (likely(fasteoi)) {
5401 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5402 int access_type, offset;
5403
5404 access_type = exit_qualification & APIC_ACCESS_TYPE;
5405 offset = exit_qualification & APIC_ACCESS_OFFSET;
5406 /*
5407 * Sane guest uses MOV to write EOI, with written value
5408 * not cared. So make a short-circuit here by avoiding
5409 * heavy instruction emulation.
5410 */
5411 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5412 (offset == APIC_EOI)) {
5413 kvm_lapic_set_eoi(vcpu);
5414 skip_emulated_instruction(vcpu);
5415 return 1;
5416 }
5417 }
51d8b661 5418 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5419}
5420
c7c9c56c
YZ		 5421static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5422{
5423 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5424 int vector = exit_qualification & 0xff;
5425
5426 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5427 kvm_apic_set_eoi_accelerated(vcpu, vector);
5428 return 1;
5429}
5430
83d4c286
YZ		 5431static int handle_apic_write(struct kvm_vcpu *vcpu)
5432{
5433 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5434 u32 offset = exit_qualification & 0xfff;
5435
5436 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5437 kvm_apic_write_nodecode(vcpu, offset);
5438 return 1;
5439}
5440
851ba692 5441static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5442{
60637aac 5443 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5444 unsigned long exit_qualification;
e269fb21
JK		 5445 bool has_error_code = false;
5446 u32 error_code = 0;
37817f29 5447 u16 tss_selector;
7f3d35fd 5448 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5449
5450 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5451 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5452 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5453
5454 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5455
5456 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5457 if (reason == TASK_SWITCH_GATE && idt_v) {
5458 switch (type) {
5459 case INTR_TYPE_NMI_INTR:
5460 vcpu->arch.nmi_injected = false;
654f06fc 5461 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5462 break;
5463 case INTR_TYPE_EXT_INTR:
66fd3f7f 5464 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5465 kvm_clear_interrupt_queue(vcpu);
5466 break;
5467 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5468 if (vmx->idt_vectoring_info &
5469 VECTORING_INFO_DELIVER_CODE_MASK) {
5470 has_error_code = true;
5471 error_code =
5472 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5473 }
5474 /* fall through */
64a7ec06
GN		 5475 case INTR_TYPE_SOFT_EXCEPTION:
5476 kvm_clear_exception_queue(vcpu);
5477 break;
5478 default:
5479 break;
5480 }
60637aac 5481 }
37817f29
IE		 5482 tss_selector = exit_qualification;
5483
64a7ec06
GN		 5484 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5485 type != INTR_TYPE_EXT_INTR &&
5486 type != INTR_TYPE_NMI_INTR))
5487 skip_emulated_instruction(vcpu);
5488
7f3d35fd
KW		 5489 if (kvm_task_switch(vcpu, tss_selector,
5490 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5491 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5492 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5493 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5494 vcpu->run->internal.ndata = 0;
42dbaa5a 5495 return 0;
acb54517 5496 }
42dbaa5a
JK		 5497
5498 /* clear all local breakpoint enable flags */
0e8a0996 5499 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5500
5501 /*
5502 * TODO: What about debug traps on tss switch?
5503 * Are we supposed to inject them and update dr6?
5504 */
5505
5506 return 1;
37817f29
IE		 5507}
5508
851ba692 5509static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5510{
f9c617f6 5511 unsigned long exit_qualification;
1439442c 5512 gpa_t gpa;
4f5982a5 5513 u32 error_code;
1439442c 5514 int gla_validity;
1439442c 5515
f9c617f6 5516 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5517
1439442c
SY		 5518 gla_validity = (exit_qualification >> 7) & 0x3;
5519 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5520 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5521 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5522 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5523 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5524 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5525 (long unsigned int)exit_qualification);
851ba692
AK		 5526 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5527 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5528 return 0;
1439442c
SY		 5529 }
5530
0be9c7a8
GN		 5531 /*
5532 * EPT violation happened while executing iret from NMI,
5533 * "blocked by NMI" bit has to be set before next VM entry.
5534 * There are errata that may cause this bit to not be set:
5535 * AAK134, BY25.
5536 */
bcd1c294
GN		 5537 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5538 cpu_has_virtual_nmis() &&
5539 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5540 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5541
1439442c 5542 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5543 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5544
5545 /* It is a write fault? */
81ed33e4 5546 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5547 /* It is a fetch fault? */
81ed33e4 5548 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5549 /* ept page table is present? */
81ed33e4 5550 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5551
25d92081
YZ		 5552 vcpu->arch.exit_qualification = exit_qualification;
5553
4f5982a5 5554 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5555}
5556
68f89400
MT		 5557static u64 ept_rsvd_mask(u64 spte, int level)
5558{
5559 int i;
5560 u64 mask = 0;
5561
5562 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5563 mask |= (1ULL << i);
5564
a32e8459 5565 if (level == 4)
68f89400
MT		 5566 /* bits 7:3 reserved */
5567 mask |= 0xf8;
a32e8459
WL		 5568 else if (spte & (1ULL << 7))
5569 /*
5570 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5571 * level == 1 if the hypervisor is using the ignored bit 7.
5572 */
5573 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5574 else if (level > 1)
5575 /* bits 6:3 reserved */
5576 mask |= 0x78;
68f89400
MT		 5577
5578 return mask;
5579}
5580
5581static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5582 int level)
5583{
5584 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5585
5586 /* 010b (write-only) */
5587 WARN_ON((spte & 0x7) == 0x2);
5588
5589 /* 110b (write/execute) */
5590 WARN_ON((spte & 0x7) == 0x6);
5591
5592 /* 100b (execute-only) and value not supported by logical processor */
5593 if (!cpu_has_vmx_ept_execute_only())
5594 WARN_ON((spte & 0x7) == 0x4);
5595
5596 /* not 000b */
5597 if ((spte & 0x7)) {
5598 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5599
5600 if (rsvd_bits != 0) {
5601 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5602 __func__, rsvd_bits);
5603 WARN_ON(1);
5604 }
5605
a32e8459
WL		 5606 /* bits 5:3 are _not_ reserved for large page or leaf page */
5607 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5608 u64 ept_mem_type = (spte & 0x38) >> 3;
5609
5610 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5611 ept_mem_type == 7) {
5612 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5613 __func__, ept_mem_type);
5614 WARN_ON(1);
5615 }
5616 }
5617 }
5618}
5619
851ba692 5620static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5621{
5622 u64 sptes[4];
ce88decf 5623 int nr_sptes, i, ret;
68f89400
MT		 5624 gpa_t gpa;
5625
5626 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5627 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5628 skip_emulated_instruction(vcpu);
5629 return 1;
5630 }
68f89400 5631
ce88decf 5632 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5633 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5634 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5635 EMULATE_DONE;
f8f55942
XG		 5636
5637 if (unlikely(ret == RET_MMIO_PF_INVALID))
5638 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5639
b37fbea6 5640 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5641 return 1;
5642
5643 /* It is the real ept misconfig */
68f89400
MT		 5644 printk(KERN_ERR "EPT: Misconfiguration.\n");
5645 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5646
5647 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5648
5649 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5650 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5651
851ba692
AK		 5652 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5653 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5654
5655 return 0;
5656}
5657
851ba692 5658static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5659{
5660 u32 cpu_based_vm_exec_control;
5661
5662 /* clear pending NMI */
5663 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5664 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5665 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5666 ++vcpu->stat.nmi_window_exits;
3842d135 5667 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5668
5669 return 1;
5670}
5671
80ced186 5672static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5673{
8b3079a5
AK		 5674 struct vcpu_vmx *vmx = to_vmx(vcpu);
5675 enum emulation_result err = EMULATE_DONE;
80ced186 5676 int ret = 1;
49e9d557
AK		 5677 u32 cpu_exec_ctrl;
5678 bool intr_window_requested;
b8405c18 5679 unsigned count = 130;
49e9d557
AK		 5680
5681 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5682 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5683
98eb2f8b 5684 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5685 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5686 return handle_interrupt_window(&vmx->vcpu);
5687
de87dcdd
AK		 5688 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5689 return 1;
5690
991eebf9 5691 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5692
ac0a48c3 5693 if (err == EMULATE_USER_EXIT) {
94452b9e 5694 ++vcpu->stat.mmio_exits;
80ced186
MG		 5695 ret = 0;
5696 goto out;
5697 }
1d5a4d9b 5698
de5f70e0
AK		 5699 if (err != EMULATE_DONE) {
5700 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5701 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5702 vcpu->run->internal.ndata = 0;
6d77dbfc 5703 return 0;
de5f70e0 5704 }
ea953ef0 5705
8d76c49e
GN		 5706 if (vcpu->arch.halt_request) {
5707 vcpu->arch.halt_request = 0;
5708 ret = kvm_emulate_halt(vcpu);
5709 goto out;
5710 }
5711
ea953ef0 5712 if (signal_pending(current))
80ced186 5713 goto out;
ea953ef0
MG		 5714 if (need_resched())
5715 schedule();
5716 }
5717
80ced186
MG		 5718out:
5719 return ret;
ea953ef0
MG		 5720}
5721
b4a2d31d
RK		 5722static int __grow_ple_window(int val)
5723{
5724 if (ple_window_grow < 1)
5725 return ple_window;
5726
5727 val = min(val, ple_window_actual_max);
5728
5729 if (ple_window_grow < ple_window)
5730 val *= ple_window_grow;
5731 else
5732 val += ple_window_grow;
5733
5734 return val;
5735}
5736
5737static int __shrink_ple_window(int val, int modifier, int minimum)
5738{
5739 if (modifier < 1)
5740 return ple_window;
5741
5742 if (modifier < ple_window)
5743 val /= modifier;
5744 else
5745 val -= modifier;
5746
5747 return max(val, minimum);
5748}
5749
5750static void grow_ple_window(struct kvm_vcpu *vcpu)
5751{
5752 struct vcpu_vmx *vmx = to_vmx(vcpu);
5753 int old = vmx->ple_window;
5754
5755 vmx->ple_window = __grow_ple_window(old);
5756
5757 if (vmx->ple_window != old)
5758 vmx->ple_window_dirty = true;
7b46268d
RK		 5759
5760 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5761}
5762
5763static void shrink_ple_window(struct kvm_vcpu *vcpu)
5764{
5765 struct vcpu_vmx *vmx = to_vmx(vcpu);
5766 int old = vmx->ple_window;
5767
5768 vmx->ple_window = __shrink_ple_window(old,
5769 ple_window_shrink, ple_window);
5770
5771 if (vmx->ple_window != old)
5772 vmx->ple_window_dirty = true;
7b46268d
RK		 5773
5774 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5775}
5776
5777/*
5778 * ple_window_actual_max is computed to be one grow_ple_window() below
5779 * ple_window_max. (See __grow_ple_window for the reason.)
5780 * This prevents overflows, because ple_window_max is int.
5781 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5782 * this process.
5783 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5784 */
5785static void update_ple_window_actual_max(void)
5786{
5787 ple_window_actual_max =
5788 __shrink_ple_window(max(ple_window_max, ple_window),
5789 ple_window_grow, INT_MIN);
5790}
5791
f2c7648d
TC		 5792static __init int hardware_setup(void)
5793{
34a1cd60
TC		 5794 int r = -ENOMEM, i, msr;
5795
5796 rdmsrl_safe(MSR_EFER, &host_efer);
5797
5798 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5799 kvm_define_shared_msr(i, vmx_msr_index[i]);
5800
5801 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5802 if (!vmx_io_bitmap_a)
5803 return r;
5804
5805 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5806 if (!vmx_io_bitmap_b)
5807 goto out;
5808
5809 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5810 if (!vmx_msr_bitmap_legacy)
5811 goto out1;
5812
5813 vmx_msr_bitmap_legacy_x2apic =
5814 (unsigned long *)__get_free_page(GFP_KERNEL);
5815 if (!vmx_msr_bitmap_legacy_x2apic)
5816 goto out2;
5817
5818 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5819 if (!vmx_msr_bitmap_longmode)
5820 goto out3;
5821
5822 vmx_msr_bitmap_longmode_x2apic =
5823 (unsigned long *)__get_free_page(GFP_KERNEL);
5824 if (!vmx_msr_bitmap_longmode_x2apic)
5825 goto out4;
5826 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5827 if (!vmx_vmread_bitmap)
5828 goto out5;
5829
5830 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5831 if (!vmx_vmwrite_bitmap)
5832 goto out6;
5833
5834 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5835 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5836
5837 /*
5838 * Allow direct access to the PC debug port (it is often used for I/O
5839 * delays, but the vmexits simply slow things down).
5840 */
5841 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5842 clear_bit(0x80, vmx_io_bitmap_a);
5843
5844 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5845
5846 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5847 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5848
34a1cd60
TC		 5849 if (setup_vmcs_config(&vmcs_config) < 0) {
5850 r = -EIO;
5851 goto out7;
baa03522 5852 }
f2c7648d
TC		 5853
5854 if (boot_cpu_has(X86_FEATURE_NX))
5855 kvm_enable_efer_bits(EFER_NX);
5856
5857 if (!cpu_has_vmx_vpid())
5858 enable_vpid = 0;
5859 if (!cpu_has_vmx_shadow_vmcs())
5860 enable_shadow_vmcs = 0;
5861 if (enable_shadow_vmcs)
5862 init_vmcs_shadow_fields();
5863
5864 if (!cpu_has_vmx_ept() ||
5865 !cpu_has_vmx_ept_4levels()) {
5866 enable_ept = 0;
5867 enable_unrestricted_guest = 0;
5868 enable_ept_ad_bits = 0;
5869 }
5870
5871 if (!cpu_has_vmx_ept_ad_bits())
5872 enable_ept_ad_bits = 0;
5873
5874 if (!cpu_has_vmx_unrestricted_guest())
5875 enable_unrestricted_guest = 0;
5876
ad15a296 5877 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 5878 flexpriority_enabled = 0;
5879
ad15a296
PB		 5880 /*
5881 * set_apic_access_page_addr() is used to reload apic access
5882 * page upon invalidation. No need to do anything if not
5883 * using the APIC_ACCESS_ADDR VMCS field.
5884 */
5885 if (!flexpriority_enabled)
f2c7648d 5886 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 5887
5888 if (!cpu_has_vmx_tpr_shadow())
5889 kvm_x86_ops->update_cr8_intercept = NULL;
5890
5891 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5892 kvm_disable_largepages();
5893
5894 if (!cpu_has_vmx_ple())
5895 ple_gap = 0;
5896
5897 if (!cpu_has_vmx_apicv())
5898 enable_apicv = 0;
5899
5900 if (enable_apicv)
5901 kvm_x86_ops->update_cr8_intercept = NULL;
5902 else {
5903 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 5904 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 5905 kvm_x86_ops->deliver_posted_interrupt = NULL;
5906 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5907 }
5908
5909 if (nested)
5910 nested_vmx_setup_ctls_msrs();
5911
baa03522
TC		 5912 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5913 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5914 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5915 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5916 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5917 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5918 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5919
5920 memcpy(vmx_msr_bitmap_legacy_x2apic,
5921 vmx_msr_bitmap_legacy, PAGE_SIZE);
5922 memcpy(vmx_msr_bitmap_longmode_x2apic,
5923 vmx_msr_bitmap_longmode, PAGE_SIZE);
5924
5925 if (enable_apicv) {
5926 for (msr = 0x800; msr <= 0x8ff; msr++)
5927 vmx_disable_intercept_msr_read_x2apic(msr);
5928
5929 /* According SDM, in x2apic mode, the whole id reg is used.
5930 * But in KVM, it only use the highest eight bits. Need to
5931 * intercept it */
5932 vmx_enable_intercept_msr_read_x2apic(0x802);
5933 /* TMCCT */
5934 vmx_enable_intercept_msr_read_x2apic(0x839);
5935 /* TPR */
5936 vmx_disable_intercept_msr_write_x2apic(0x808);
5937 /* EOI */
5938 vmx_disable_intercept_msr_write_x2apic(0x80b);
5939 /* SELF-IPI */
5940 vmx_disable_intercept_msr_write_x2apic(0x83f);
5941 }
5942
5943 if (enable_ept) {
5944 kvm_mmu_set_mask_ptes(0ull,
5945 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5946 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5947 0ull, VMX_EPT_EXECUTABLE_MASK);
5948 ept_set_mmio_spte_mask();
5949 kvm_enable_tdp();
5950 } else
5951 kvm_disable_tdp();
5952
5953 update_ple_window_actual_max();
5954
843e4330
KH		 5955 /*
5956 * Only enable PML when hardware supports PML feature, and both EPT
5957 * and EPT A/D bit features are enabled -- PML depends on them to work.
5958 */
5959 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
5960 enable_pml = 0;
5961
5962 if (!enable_pml) {
5963 kvm_x86_ops->slot_enable_log_dirty = NULL;
5964 kvm_x86_ops->slot_disable_log_dirty = NULL;
5965 kvm_x86_ops->flush_log_dirty = NULL;
5966 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
5967 }
5968
f2c7648d 5969 return alloc_kvm_area();
34a1cd60
TC		 5970
5971out7:
5972 free_page((unsigned long)vmx_vmwrite_bitmap);
5973out6:
5974 free_page((unsigned long)vmx_vmread_bitmap);
5975out5:
5976 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5977out4:
5978 free_page((unsigned long)vmx_msr_bitmap_longmode);
5979out3:
5980 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5981out2:
5982 free_page((unsigned long)vmx_msr_bitmap_legacy);
5983out1:
5984 free_page((unsigned long)vmx_io_bitmap_b);
5985out:
5986 free_page((unsigned long)vmx_io_bitmap_a);
5987
5988 return r;
f2c7648d
TC		 5989}
5990
5991static __exit void hardware_unsetup(void)
5992{
34a1cd60
TC		 5993 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5994 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5995 free_page((unsigned long)vmx_msr_bitmap_legacy);
5996 free_page((unsigned long)vmx_msr_bitmap_longmode);
5997 free_page((unsigned long)vmx_io_bitmap_b);
5998 free_page((unsigned long)vmx_io_bitmap_a);
5999 free_page((unsigned long)vmx_vmwrite_bitmap);
6000 free_page((unsigned long)vmx_vmread_bitmap);
6001
f2c7648d
TC		 6002 free_kvm_area();
6003}
6004
4b8d54f9
ZE		 6005/*
6006 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6007 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6008 */
9fb41ba8 6009static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6010{
b4a2d31d
RK		 6011 if (ple_gap)
6012 grow_ple_window(vcpu);
6013
4b8d54f9
ZE		 6014 skip_emulated_instruction(vcpu);
6015 kvm_vcpu_on_spin(vcpu);
6016
6017 return 1;
6018}
6019
87c00572 6020static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6021{
87c00572 6022 skip_emulated_instruction(vcpu);
59708670
SY		 6023 return 1;
6024}
6025
87c00572
GS		 6026static int handle_mwait(struct kvm_vcpu *vcpu)
6027{
6028 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6029 return handle_nop(vcpu);
6030}
6031
6032static int handle_monitor(struct kvm_vcpu *vcpu)
6033{
6034 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6035 return handle_nop(vcpu);
6036}
6037
ff2f6fe9
NHE		 6038/*
6039 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6040 * We could reuse a single VMCS for all the L2 guests, but we also want the
6041 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6042 * allows keeping them loaded on the processor, and in the future will allow
6043 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6044 * every entry if they never change.
6045 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6046 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6047 *
6048 * The following functions allocate and free a vmcs02 in this pool.
6049 */
6050
6051/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6052static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6053{
6054 struct vmcs02_list *item;
6055 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6056 if (item->vmptr == vmx->nested.current_vmptr) {
6057 list_move(&item->list, &vmx->nested.vmcs02_pool);
6058 return &item->vmcs02;
6059 }
6060
6061 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6062 /* Recycle the least recently used VMCS. */
6063 item = list_entry(vmx->nested.vmcs02_pool.prev,
6064 struct vmcs02_list, list);
6065 item->vmptr = vmx->nested.current_vmptr;
6066 list_move(&item->list, &vmx->nested.vmcs02_pool);
6067 return &item->vmcs02;
6068 }
6069
6070 /* Create a new VMCS */
0fa24ce3 6071 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6072 if (!item)
6073 return NULL;
6074 item->vmcs02.vmcs = alloc_vmcs();
6075 if (!item->vmcs02.vmcs) {
6076 kfree(item);
6077 return NULL;
6078 }
6079 loaded_vmcs_init(&item->vmcs02);
6080 item->vmptr = vmx->nested.current_vmptr;
6081 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6082 vmx->nested.vmcs02_num++;
6083 return &item->vmcs02;
6084}
6085
6086/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6087static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6088{
6089 struct vmcs02_list *item;
6090 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6091 if (item->vmptr == vmptr) {
6092 free_loaded_vmcs(&item->vmcs02);
6093 list_del(&item->list);
6094 kfree(item);
6095 vmx->nested.vmcs02_num--;
6096 return;
6097 }
6098}
6099
6100/*
6101 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6102 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6103 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6104 */
6105static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6106{
6107 struct vmcs02_list *item, *n;
4fa7734c
PB		 6108
6109 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6110 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6111 /*
6112 * Something will leak if the above WARN triggers. Better than
6113 * a use-after-free.
6114 */
6115 if (vmx->loaded_vmcs == &item->vmcs02)
6116 continue;
6117
6118 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6119 list_del(&item->list);
6120 kfree(item);
4fa7734c 6121 vmx->nested.vmcs02_num--;
ff2f6fe9 6122 }
ff2f6fe9
NHE		 6123}
6124
0658fbaa
ACL		 6125/*
6126 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6127 * set the success or error code of an emulated VMX instruction, as specified
6128 * by Vol 2B, VMX Instruction Reference, "Conventions".
6129 */
6130static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6131{
6132 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6133 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6134 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6135}
6136
6137static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6138{
6139 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6140 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6141 X86_EFLAGS_SF | X86_EFLAGS_OF))
6142 | X86_EFLAGS_CF);
6143}
6144
145c28dd 6145static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6146 u32 vm_instruction_error)
6147{
6148 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6149 /*
6150 * failValid writes the error number to the current VMCS, which
6151 * can't be done there isn't a current VMCS.
6152 */
6153 nested_vmx_failInvalid(vcpu);
6154 return;
6155 }
6156 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6157 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6158 X86_EFLAGS_SF | X86_EFLAGS_OF))
6159 | X86_EFLAGS_ZF);
6160 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6161 /*
6162 * We don't need to force a shadow sync because
6163 * VM_INSTRUCTION_ERROR is not shadowed
6164 */
6165}
145c28dd 6166
ff651cb6
WV		 6167static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6168{
6169 /* TODO: not to reset guest simply here. */
6170 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6171 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6172}
6173
f4124500
JK		 6174static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6175{
6176 struct vcpu_vmx *vmx =
6177 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6178
6179 vmx->nested.preemption_timer_expired = true;
6180 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6181 kvm_vcpu_kick(&vmx->vcpu);
6182
6183 return HRTIMER_NORESTART;
6184}
6185
19677e32
BD		 6186/*
6187 * Decode the memory-address operand of a vmx instruction, as recorded on an
6188 * exit caused by such an instruction (run by a guest hypervisor).
6189 * On success, returns 0. When the operand is invalid, returns 1 and throws
6190 * #UD or #GP.
6191 */
6192static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6193 unsigned long exit_qualification,
6194 u32 vmx_instruction_info, gva_t *ret)
6195{
6196 /*
6197 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6198 * Execution", on an exit, vmx_instruction_info holds most of the
6199 * addressing components of the operand. Only the displacement part
6200 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6201 * For how an actual address is calculated from all these components,
6202 * refer to Vol. 1, "Operand Addressing".
6203 */
6204 int scaling = vmx_instruction_info & 3;
6205 int addr_size = (vmx_instruction_info >> 7) & 7;
6206 bool is_reg = vmx_instruction_info & (1u << 10);
6207 int seg_reg = (vmx_instruction_info >> 15) & 7;
6208 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6209 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6210 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6211 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6212
6213 if (is_reg) {
6214 kvm_queue_exception(vcpu, UD_VECTOR);
6215 return 1;
6216 }
6217
6218 /* Addr = segment_base + offset */
6219 /* offset = base + [index * scale] + displacement */
6220 *ret = vmx_get_segment_base(vcpu, seg_reg);
6221 if (base_is_valid)
6222 *ret += kvm_register_read(vcpu, base_reg);
6223 if (index_is_valid)
6224 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6225 *ret += exit_qualification; /* holds the displacement */
6226
6227 if (addr_size == 1) /* 32 bit */
6228 *ret &= 0xffffffff;
6229
6230 /*
6231 * TODO: throw #GP (and return 1) in various cases that the VM*
6232 * instructions require it - e.g., offset beyond segment limit,
6233 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6234 * address, and so on. Currently these are not checked.
6235 */
6236 return 0;
6237}
6238
3573e22c
BD		 6239/*
6240 * This function performs the various checks including
6241 * - if it's 4KB aligned
6242 * - No bits beyond the physical address width are set
6243 * - Returns 0 on success or else 1
4291b588 6244 * (Intel SDM Section 30.3)
3573e22c 6245 */
4291b588
BD		 6246static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6247 gpa_t *vmpointer)
3573e22c
BD		 6248{
6249 gva_t gva;
6250 gpa_t vmptr;
6251 struct x86_exception e;
6252 struct page *page;
6253 struct vcpu_vmx *vmx = to_vmx(vcpu);
6254 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6255
6256 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6257 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6258 return 1;
6259
6260 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6261 sizeof(vmptr), &e)) {
6262 kvm_inject_page_fault(vcpu, &e);
6263 return 1;
6264 }
6265
6266 switch (exit_reason) {
6267 case EXIT_REASON_VMON:
6268 /*
6269 * SDM 3: 24.11.5
6270 * The first 4 bytes of VMXON region contain the supported
6271 * VMCS revision identifier
6272 *
6273 * Note - IA32_VMX_BASIC[48] will never be 1
6274 * for the nested case;
6275 * which replaces physical address width with 32
6276 *
6277 */
bc39c4db 6278 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6279 nested_vmx_failInvalid(vcpu);
6280 skip_emulated_instruction(vcpu);
6281 return 1;
6282 }
6283
6284 page = nested_get_page(vcpu, vmptr);
6285 if (page == NULL ||
6286 *(u32 *)kmap(page) != VMCS12_REVISION) {
6287 nested_vmx_failInvalid(vcpu);
6288 kunmap(page);
6289 skip_emulated_instruction(vcpu);
6290 return 1;
6291 }
6292 kunmap(page);
6293 vmx->nested.vmxon_ptr = vmptr;
6294 break;
4291b588 6295 case EXIT_REASON_VMCLEAR:
bc39c4db 6296 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6297 nested_vmx_failValid(vcpu,
6298 VMXERR_VMCLEAR_INVALID_ADDRESS);
6299 skip_emulated_instruction(vcpu);
6300 return 1;
6301 }
6302
6303 if (vmptr == vmx->nested.vmxon_ptr) {
6304 nested_vmx_failValid(vcpu,
6305 VMXERR_VMCLEAR_VMXON_POINTER);
6306 skip_emulated_instruction(vcpu);
6307 return 1;
6308 }
6309 break;
6310 case EXIT_REASON_VMPTRLD:
bc39c4db 6311 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6312 nested_vmx_failValid(vcpu,
6313 VMXERR_VMPTRLD_INVALID_ADDRESS);
6314 skip_emulated_instruction(vcpu);
6315 return 1;
6316 }
3573e22c 6317
4291b588
BD		 6318 if (vmptr == vmx->nested.vmxon_ptr) {
6319 nested_vmx_failValid(vcpu,
6320 VMXERR_VMCLEAR_VMXON_POINTER);
6321 skip_emulated_instruction(vcpu);
6322 return 1;
6323 }
6324 break;
3573e22c
BD		 6325 default:
6326 return 1; /* shouldn't happen */
6327 }
6328
4291b588
BD		 6329 if (vmpointer)
6330 *vmpointer = vmptr;
3573e22c
BD		 6331 return 0;
6332}
6333
ec378aee
NHE		 6334/*
6335 * Emulate the VMXON instruction.
6336 * Currently, we just remember that VMX is active, and do not save or even
6337 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6338 * do not currently need to store anything in that guest-allocated memory
6339 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6340 * argument is different from the VMXON pointer (which the spec says they do).
6341 */
6342static int handle_vmon(struct kvm_vcpu *vcpu)
6343{
6344 struct kvm_segment cs;
6345 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6346 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6347 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6348 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6349
6350 /* The Intel VMX Instruction Reference lists a bunch of bits that
6351 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6352 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6353 * Otherwise, we should fail with #UD. We test these now:
6354 */
6355 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6356 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6357 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6358 kvm_queue_exception(vcpu, UD_VECTOR);
6359 return 1;
6360 }
6361
6362 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6363 if (is_long_mode(vcpu) && !cs.l) {
6364 kvm_queue_exception(vcpu, UD_VECTOR);
6365 return 1;
6366 }
6367
6368 if (vmx_get_cpl(vcpu)) {
6369 kvm_inject_gp(vcpu, 0);
6370 return 1;
6371 }
3573e22c 6372
4291b588 6373 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6374 return 1;
6375
145c28dd
AG		 6376 if (vmx->nested.vmxon) {
6377 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6378 skip_emulated_instruction(vcpu);
6379 return 1;
6380 }
b3897a49
NHE		 6381
6382 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6383 != VMXON_NEEDED_FEATURES) {
6384 kvm_inject_gp(vcpu, 0);
6385 return 1;
6386 }
6387
8de48833
AG		 6388 if (enable_shadow_vmcs) {
6389 shadow_vmcs = alloc_vmcs();
6390 if (!shadow_vmcs)
6391 return -ENOMEM;
6392 /* mark vmcs as shadow */
6393 shadow_vmcs->revision_id |= (1u << 31);
6394 /* init shadow vmcs */
6395 vmcs_clear(shadow_vmcs);
6396 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6397 }
ec378aee 6398
ff2f6fe9
NHE		 6399 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6400 vmx->nested.vmcs02_num = 0;
6401
f4124500
JK		 6402 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6403 HRTIMER_MODE_REL);
6404 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6405
ec378aee
NHE		 6406 vmx->nested.vmxon = true;
6407
6408 skip_emulated_instruction(vcpu);
a25eb114 6409 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6410 return 1;
6411}
6412
6413/*
6414 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6415 * for running VMX instructions (except VMXON, whose prerequisites are
6416 * slightly different). It also specifies what exception to inject otherwise.
6417 */
6418static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6419{
6420 struct kvm_segment cs;
6421 struct vcpu_vmx *vmx = to_vmx(vcpu);
6422
6423 if (!vmx->nested.vmxon) {
6424 kvm_queue_exception(vcpu, UD_VECTOR);
6425 return 0;
6426 }
6427
6428 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6429 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6430 (is_long_mode(vcpu) && !cs.l)) {
6431 kvm_queue_exception(vcpu, UD_VECTOR);
6432 return 0;
6433 }
6434
6435 if (vmx_get_cpl(vcpu)) {
6436 kvm_inject_gp(vcpu, 0);
6437 return 0;
6438 }
6439
6440 return 1;
6441}
6442
e7953d7f
AG		 6443static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6444{
8a1b9dd0 6445 u32 exec_control;
9a2a05b9
PB		 6446 if (vmx->nested.current_vmptr == -1ull)
6447 return;
6448
6449 /* current_vmptr and current_vmcs12 are always set/reset together */
6450 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6451 return;
6452
012f83cb 6453 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6454 /* copy to memory all shadowed fields in case
6455 they were modified */
6456 copy_shadow_to_vmcs12(vmx);
6457 vmx->nested.sync_shadow_vmcs = false;
6458 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6459 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6460 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6461 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6462 }
e7953d7f
AG		 6463 kunmap(vmx->nested.current_vmcs12_page);
6464 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6465 vmx->nested.current_vmptr = -1ull;
6466 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6467}
6468
ec378aee
NHE		 6469/*
6470 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6471 * just stops using VMX.
6472 */
6473static void free_nested(struct vcpu_vmx *vmx)
6474{
6475 if (!vmx->nested.vmxon)
6476 return;
9a2a05b9 6477
ec378aee 6478 vmx->nested.vmxon = false;
9a2a05b9 6479 nested_release_vmcs12(vmx);
e7953d7f
AG		 6480 if (enable_shadow_vmcs)
6481 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6482 /* Unpin physical memory we referred to in current vmcs02 */
6483 if (vmx->nested.apic_access_page) {
6484 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6485 vmx->nested.apic_access_page = NULL;
fe3ef05c 6486 }
a7c0b07d
WL		 6487 if (vmx->nested.virtual_apic_page) {
6488 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6489 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6490 }
ff2f6fe9
NHE		 6491
6492 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6493}
6494
6495/* Emulate the VMXOFF instruction */
6496static int handle_vmoff(struct kvm_vcpu *vcpu)
6497{
6498 if (!nested_vmx_check_permission(vcpu))
6499 return 1;
6500 free_nested(to_vmx(vcpu));
6501 skip_emulated_instruction(vcpu);
a25eb114 6502 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6503 return 1;
6504}
6505
27d6c865
NHE		 6506/* Emulate the VMCLEAR instruction */
6507static int handle_vmclear(struct kvm_vcpu *vcpu)
6508{
6509 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6510 gpa_t vmptr;
6511 struct vmcs12 *vmcs12;
6512 struct page *page;
27d6c865
NHE		 6513
6514 if (!nested_vmx_check_permission(vcpu))
6515 return 1;
6516
4291b588 6517 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6518 return 1;
27d6c865 6519
9a2a05b9 6520 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6521 nested_release_vmcs12(vmx);
27d6c865
NHE		 6522
6523 page = nested_get_page(vcpu, vmptr);
6524 if (page == NULL) {
6525 /*
6526 * For accurate processor emulation, VMCLEAR beyond available
6527 * physical memory should do nothing at all. However, it is
6528 * possible that a nested vmx bug, not a guest hypervisor bug,
6529 * resulted in this case, so let's shut down before doing any
6530 * more damage:
6531 */
6532 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6533 return 1;
6534 }
6535 vmcs12 = kmap(page);
6536 vmcs12->launch_state = 0;
6537 kunmap(page);
6538 nested_release_page(page);
6539
6540 nested_free_vmcs02(vmx, vmptr);
6541
6542 skip_emulated_instruction(vcpu);
6543 nested_vmx_succeed(vcpu);
6544 return 1;
6545}
6546
cd232ad0
NHE		 6547static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6548
6549/* Emulate the VMLAUNCH instruction */
6550static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6551{
6552 return nested_vmx_run(vcpu, true);
6553}
6554
6555/* Emulate the VMRESUME instruction */
6556static int handle_vmresume(struct kvm_vcpu *vcpu)
6557{
6558
6559 return nested_vmx_run(vcpu, false);
6560}
6561
49f705c5
NHE		 6562enum vmcs_field_type {
6563 VMCS_FIELD_TYPE_U16 = 0,
6564 VMCS_FIELD_TYPE_U64 = 1,
6565 VMCS_FIELD_TYPE_U32 = 2,
6566 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6567};
6568
6569static inline int vmcs_field_type(unsigned long field)
6570{
6571 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6572 return VMCS_FIELD_TYPE_U32;
6573 return (field >> 13) & 0x3 ;
6574}
6575
6576static inline int vmcs_field_readonly(unsigned long field)
6577{
6578 return (((field >> 10) & 0x3) == 1);
6579}
6580
6581/*
6582 * Read a vmcs12 field. Since these can have varying lengths and we return
6583 * one type, we chose the biggest type (u64) and zero-extend the return value
6584 * to that size. Note that the caller, handle_vmread, might need to use only
6585 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6586 * 64-bit fields are to be returned).
6587 */
a2ae9df7
PB		 6588static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6589 unsigned long field, u64 *ret)
49f705c5
NHE		 6590{
6591 short offset = vmcs_field_to_offset(field);
6592 char *p;
6593
6594 if (offset < 0)
a2ae9df7 6595 return offset;
49f705c5
NHE		 6596
6597 p = ((char *)(get_vmcs12(vcpu))) + offset;
6598
6599 switch (vmcs_field_type(field)) {
6600 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6601 *ret = *((natural_width *)p);
a2ae9df7 6602 return 0;
49f705c5
NHE		 6603 case VMCS_FIELD_TYPE_U16:
6604 *ret = *((u16 *)p);
a2ae9df7 6605 return 0;
49f705c5
NHE		 6606 case VMCS_FIELD_TYPE_U32:
6607 *ret = *((u32 *)p);
a2ae9df7 6608 return 0;
49f705c5
NHE		 6609 case VMCS_FIELD_TYPE_U64:
6610 *ret = *((u64 *)p);
a2ae9df7 6611 return 0;
49f705c5 6612 default:
a2ae9df7
PB		 6613 WARN_ON(1);
6614 return -ENOENT;
49f705c5
NHE		 6615 }
6616}
6617
20b97fea 6618
a2ae9df7
PB		 6619static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6620 unsigned long field, u64 field_value){
20b97fea
AG		 6621 short offset = vmcs_field_to_offset(field);
6622 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6623 if (offset < 0)
a2ae9df7 6624 return offset;
20b97fea
AG		 6625
6626 switch (vmcs_field_type(field)) {
6627 case VMCS_FIELD_TYPE_U16:
6628 *(u16 *)p = field_value;
a2ae9df7 6629 return 0;
20b97fea
AG		 6630 case VMCS_FIELD_TYPE_U32:
6631 *(u32 *)p = field_value;
a2ae9df7 6632 return 0;
20b97fea
AG		 6633 case VMCS_FIELD_TYPE_U64:
6634 *(u64 *)p = field_value;
a2ae9df7 6635 return 0;
20b97fea
AG		 6636 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6637 *(natural_width *)p = field_value;
a2ae9df7 6638 return 0;
20b97fea 6639 default:
a2ae9df7
PB		 6640 WARN_ON(1);
6641 return -ENOENT;
20b97fea
AG		 6642 }
6643
6644}
6645
16f5b903
AG		 6646static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6647{
6648 int i;
6649 unsigned long field;
6650 u64 field_value;
6651 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6652 const unsigned long *fields = shadow_read_write_fields;
6653 const int num_fields = max_shadow_read_write_fields;
16f5b903 6654
282da870
JK		 6655 preempt_disable();
6656
16f5b903
AG		 6657 vmcs_load(shadow_vmcs);
6658
6659 for (i = 0; i < num_fields; i++) {
6660 field = fields[i];
6661 switch (vmcs_field_type(field)) {
6662 case VMCS_FIELD_TYPE_U16:
6663 field_value = vmcs_read16(field);
6664 break;
6665 case VMCS_FIELD_TYPE_U32:
6666 field_value = vmcs_read32(field);
6667 break;
6668 case VMCS_FIELD_TYPE_U64:
6669 field_value = vmcs_read64(field);
6670 break;
6671 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6672 field_value = vmcs_readl(field);
6673 break;
a2ae9df7
PB		 6674 default:
6675 WARN_ON(1);
6676 continue;
16f5b903
AG		 6677 }
6678 vmcs12_write_any(&vmx->vcpu, field, field_value);
6679 }
6680
6681 vmcs_clear(shadow_vmcs);
6682 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6683
6684 preempt_enable();
16f5b903
AG		 6685}
6686
c3114420
AG		 6687static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6688{
c2bae893
MK		 6689 const unsigned long *fields[] = {
6690 shadow_read_write_fields,
6691 shadow_read_only_fields
c3114420 6692 };
c2bae893 6693 const int max_fields[] = {
c3114420
AG		 6694 max_shadow_read_write_fields,
6695 max_shadow_read_only_fields
6696 };
6697 int i, q;
6698 unsigned long field;
6699 u64 field_value = 0;
6700 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6701
6702 vmcs_load(shadow_vmcs);
6703
c2bae893 6704 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6705 for (i = 0; i < max_fields[q]; i++) {
6706 field = fields[q][i];
6707 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6708
6709 switch (vmcs_field_type(field)) {
6710 case VMCS_FIELD_TYPE_U16:
6711 vmcs_write16(field, (u16)field_value);
6712 break;
6713 case VMCS_FIELD_TYPE_U32:
6714 vmcs_write32(field, (u32)field_value);
6715 break;
6716 case VMCS_FIELD_TYPE_U64:
6717 vmcs_write64(field, (u64)field_value);
6718 break;
6719 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6720 vmcs_writel(field, (long)field_value);
6721 break;
a2ae9df7
PB		 6722 default:
6723 WARN_ON(1);
6724 break;
c3114420
AG		 6725 }
6726 }
6727 }
6728
6729 vmcs_clear(shadow_vmcs);
6730 vmcs_load(vmx->loaded_vmcs->vmcs);
6731}
6732
49f705c5
NHE		 6733/*
6734 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6735 * used before) all generate the same failure when it is missing.
6736 */
6737static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6738{
6739 struct vcpu_vmx *vmx = to_vmx(vcpu);
6740 if (vmx->nested.current_vmptr == -1ull) {
6741 nested_vmx_failInvalid(vcpu);
6742 skip_emulated_instruction(vcpu);
6743 return 0;
6744 }
6745 return 1;
6746}
6747
6748static int handle_vmread(struct kvm_vcpu *vcpu)
6749{
6750 unsigned long field;
6751 u64 field_value;
6752 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6753 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6754 gva_t gva = 0;
6755
6756 if (!nested_vmx_check_permission(vcpu) ||
6757 !nested_vmx_check_vmcs12(vcpu))
6758 return 1;
6759
6760 /* Decode instruction info and find the field to read */
27e6fb5d 6761 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6762 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6763 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6764 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6765 skip_emulated_instruction(vcpu);
6766 return 1;
6767 }
6768 /*
6769 * Now copy part of this value to register or memory, as requested.
6770 * Note that the number of bits actually copied is 32 or 64 depending
6771 * on the guest's mode (32 or 64 bit), not on the given field's length.
6772 */
6773 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6774 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6775 field_value);
6776 } else {
6777 if (get_vmx_mem_address(vcpu, exit_qualification,
6778 vmx_instruction_info, &gva))
6779 return 1;
6780 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6781 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6782 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6783 }
6784
6785 nested_vmx_succeed(vcpu);
6786 skip_emulated_instruction(vcpu);
6787 return 1;
6788}
6789
6790
6791static int handle_vmwrite(struct kvm_vcpu *vcpu)
6792{
6793 unsigned long field;
6794 gva_t gva;
6795 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6796 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6797 /* The value to write might be 32 or 64 bits, depending on L1's long
6798 * mode, and eventually we need to write that into a field of several
6799 * possible lengths. The code below first zero-extends the value to 64
6800 * bit (field_value), and then copies only the approriate number of
6801 * bits into the vmcs12 field.
6802 */
6803 u64 field_value = 0;
6804 struct x86_exception e;
6805
6806 if (!nested_vmx_check_permission(vcpu) ||
6807 !nested_vmx_check_vmcs12(vcpu))
6808 return 1;
6809
6810 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6811 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6812 (((vmx_instruction_info) >> 3) & 0xf));
6813 else {
6814 if (get_vmx_mem_address(vcpu, exit_qualification,
6815 vmx_instruction_info, &gva))
6816 return 1;
6817 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6818 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6819 kvm_inject_page_fault(vcpu, &e);
6820 return 1;
6821 }
6822 }
6823
6824
27e6fb5d 6825 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6826 if (vmcs_field_readonly(field)) {
6827 nested_vmx_failValid(vcpu,
6828 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6829 skip_emulated_instruction(vcpu);
6830 return 1;
6831 }
6832
a2ae9df7 6833 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6834 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6835 skip_emulated_instruction(vcpu);
6836 return 1;
6837 }
6838
6839 nested_vmx_succeed(vcpu);
6840 skip_emulated_instruction(vcpu);
6841 return 1;
6842}
6843
63846663
NHE		 6844/* Emulate the VMPTRLD instruction */
6845static int handle_vmptrld(struct kvm_vcpu *vcpu)
6846{
6847 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6848 gpa_t vmptr;
8a1b9dd0 6849 u32 exec_control;
63846663
NHE		 6850
6851 if (!nested_vmx_check_permission(vcpu))
6852 return 1;
6853
4291b588 6854 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6855 return 1;
63846663
NHE		 6856
6857 if (vmx->nested.current_vmptr != vmptr) {
6858 struct vmcs12 *new_vmcs12;
6859 struct page *page;
6860 page = nested_get_page(vcpu, vmptr);
6861 if (page == NULL) {
6862 nested_vmx_failInvalid(vcpu);
6863 skip_emulated_instruction(vcpu);
6864 return 1;
6865 }
6866 new_vmcs12 = kmap(page);
6867 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6868 kunmap(page);
6869 nested_release_page_clean(page);
6870 nested_vmx_failValid(vcpu,
6871 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6872 skip_emulated_instruction(vcpu);
6873 return 1;
6874 }
63846663 6875
9a2a05b9 6876 nested_release_vmcs12(vmx);
63846663
NHE		 6877 vmx->nested.current_vmptr = vmptr;
6878 vmx->nested.current_vmcs12 = new_vmcs12;
6879 vmx->nested.current_vmcs12_page = page;
012f83cb 6880 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6881 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6882 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6883 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6884 vmcs_write64(VMCS_LINK_POINTER,
6885 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6886 vmx->nested.sync_shadow_vmcs = true;
6887 }
63846663
NHE		 6888 }
6889
6890 nested_vmx_succeed(vcpu);
6891 skip_emulated_instruction(vcpu);
6892 return 1;
6893}
6894
6a4d7550
NHE		 6895/* Emulate the VMPTRST instruction */
6896static int handle_vmptrst(struct kvm_vcpu *vcpu)
6897{
6898 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6899 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6900 gva_t vmcs_gva;
6901 struct x86_exception e;
6902
6903 if (!nested_vmx_check_permission(vcpu))
6904 return 1;
6905
6906 if (get_vmx_mem_address(vcpu, exit_qualification,
6907 vmx_instruction_info, &vmcs_gva))
6908 return 1;
6909 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6910 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6911 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6912 sizeof(u64), &e)) {
6913 kvm_inject_page_fault(vcpu, &e);
6914 return 1;
6915 }
6916 nested_vmx_succeed(vcpu);
6917 skip_emulated_instruction(vcpu);
6918 return 1;
6919}
6920
bfd0a56b
NHE		 6921/* Emulate the INVEPT instruction */
6922static int handle_invept(struct kvm_vcpu *vcpu)
6923{
6924 u32 vmx_instruction_info, types;
6925 unsigned long type;
6926 gva_t gva;
6927 struct x86_exception e;
6928 struct {
6929 u64 eptp, gpa;
6930 } operand;
bfd0a56b
NHE		 6931
6932 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6933 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6934 kvm_queue_exception(vcpu, UD_VECTOR);
6935 return 1;
6936 }
6937
6938 if (!nested_vmx_check_permission(vcpu))
6939 return 1;
6940
6941 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6942 kvm_queue_exception(vcpu, UD_VECTOR);
6943 return 1;
6944 }
6945
6946 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6947 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6948
6949 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6950
6951 if (!(types & (1UL << type))) {
6952 nested_vmx_failValid(vcpu,
6953 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6954 return 1;
6955 }
6956
6957 /* According to the Intel VMX instruction reference, the memory
6958 * operand is read even if it isn't needed (e.g., for type==global)
6959 */
6960 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6961 vmx_instruction_info, &gva))
6962 return 1;
6963 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6964 sizeof(operand), &e)) {
6965 kvm_inject_page_fault(vcpu, &e);
6966 return 1;
6967 }
6968
6969 switch (type) {
bfd0a56b
NHE		 6970 case VMX_EPT_EXTENT_GLOBAL:
6971 kvm_mmu_sync_roots(vcpu);
77c3913b 6972 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6973 nested_vmx_succeed(vcpu);
6974 break;
6975 default:
4b855078 6976 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6977 BUG_ON(1);
6978 break;
6979 }
6980
6981 skip_emulated_instruction(vcpu);
6982 return 1;
6983}
6984
a642fc30
PM		 6985static int handle_invvpid(struct kvm_vcpu *vcpu)
6986{
6987 kvm_queue_exception(vcpu, UD_VECTOR);
6988 return 1;
6989}
6990
843e4330
KH		 6991static int handle_pml_full(struct kvm_vcpu *vcpu)
6992{
6993 unsigned long exit_qualification;
6994
6995 trace_kvm_pml_full(vcpu->vcpu_id);
6996
6997 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6998
6999 /*
7000 * PML buffer FULL happened while executing iret from NMI,
7001 * "blocked by NMI" bit has to be set before next VM entry.
7002 */
7003 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7004 cpu_has_virtual_nmis() &&
7005 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7006 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7007 GUEST_INTR_STATE_NMI);
7008
7009 /*
7010 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7011 * here.., and there's no userspace involvement needed for PML.
7012 */
7013 return 1;
7014}
7015
6aa8b732
AK		 7016/*
7017 * The exit handlers return 1 if the exit was handled fully and guest execution
7018 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7019 * to be done to userspace and return 0.
7020 */
772e0318 7021static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7022 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7023 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7024 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7025 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7026 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7027 [EXIT_REASON_CR_ACCESS] = handle_cr,
7028 [EXIT_REASON_DR_ACCESS] = handle_dr,
7029 [EXIT_REASON_CPUID] = handle_cpuid,
7030 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7031 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7032 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7033 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7034 [EXIT_REASON_INVD] = handle_invd,
a7052897 7035 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7036 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7037 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7038 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7039 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7040 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7041 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7042 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7043 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7044 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7045 [EXIT_REASON_VMOFF] = handle_vmoff,
7046 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7047 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7048 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7049 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7050 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7051 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7052 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7053 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7054 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7055 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7056 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7057 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7058 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7059 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7060 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7061 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7062 [EXIT_REASON_XSAVES] = handle_xsaves,
7063 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7064 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7065};
7066
7067static const int kvm_vmx_max_exit_handlers =
50a3485c 7068 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7069
908a7bdd
JK		 7070static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7071 struct vmcs12 *vmcs12)
7072{
7073 unsigned long exit_qualification;
7074 gpa_t bitmap, last_bitmap;
7075 unsigned int port;
7076 int size;
7077 u8 b;
7078
908a7bdd 7079 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7080 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7081
7082 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7083
7084 port = exit_qualification >> 16;
7085 size = (exit_qualification & 7) + 1;
7086
7087 last_bitmap = (gpa_t)-1;
7088 b = -1;
7089
7090 while (size > 0) {
7091 if (port < 0x8000)
7092 bitmap = vmcs12->io_bitmap_a;
7093 else if (port < 0x10000)
7094 bitmap = vmcs12->io_bitmap_b;
7095 else
7096 return 1;
7097 bitmap += (port & 0x7fff) / 8;
7098
7099 if (last_bitmap != bitmap)
7100 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7101 return 1;
7102 if (b & (1 << (port & 7)))
7103 return 1;
7104
7105 port++;
7106 size--;
7107 last_bitmap = bitmap;
7108 }
7109
7110 return 0;
7111}
7112
644d711a
NHE		 7113/*
7114 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7115 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7116 * disinterest in the current event (read or write a specific MSR) by using an
7117 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7118 */
7119static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7120 struct vmcs12 *vmcs12, u32 exit_reason)
7121{
7122 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7123 gpa_t bitmap;
7124
cbd29cb6 7125 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7126 return 1;
7127
7128 /*
7129 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7130 * for the four combinations of read/write and low/high MSR numbers.
7131 * First we need to figure out which of the four to use:
7132 */
7133 bitmap = vmcs12->msr_bitmap;
7134 if (exit_reason == EXIT_REASON_MSR_WRITE)
7135 bitmap += 2048;
7136 if (msr_index >= 0xc0000000) {
7137 msr_index -= 0xc0000000;
7138 bitmap += 1024;
7139 }
7140
7141 /* Then read the msr_index'th bit from this bitmap: */
7142 if (msr_index < 1024*8) {
7143 unsigned char b;
bd31a7f5
JK		 7144 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7145 return 1;
644d711a
NHE		 7146 return 1 & (b >> (msr_index & 7));
7147 } else
7148 return 1; /* let L1 handle the wrong parameter */
7149}
7150
7151/*
7152 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7153 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7154 * intercept (via guest_host_mask etc.) the current event.
7155 */
7156static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7157 struct vmcs12 *vmcs12)
7158{
7159 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7160 int cr = exit_qualification & 15;
7161 int reg = (exit_qualification >> 8) & 15;
1e32c079 7162 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7163
7164 switch ((exit_qualification >> 4) & 3) {
7165 case 0: /* mov to cr */
7166 switch (cr) {
7167 case 0:
7168 if (vmcs12->cr0_guest_host_mask &
7169 (val ^ vmcs12->cr0_read_shadow))
7170 return 1;
7171 break;
7172 case 3:
7173 if ((vmcs12->cr3_target_count >= 1 &&
7174 vmcs12->cr3_target_value0 == val) ||
7175 (vmcs12->cr3_target_count >= 2 &&
7176 vmcs12->cr3_target_value1 == val) ||
7177 (vmcs12->cr3_target_count >= 3 &&
7178 vmcs12->cr3_target_value2 == val) ||
7179 (vmcs12->cr3_target_count >= 4 &&
7180 vmcs12->cr3_target_value3 == val))
7181 return 0;
7182 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7183 return 1;
7184 break;
7185 case 4:
7186 if (vmcs12->cr4_guest_host_mask &
7187 (vmcs12->cr4_read_shadow ^ val))
7188 return 1;
7189 break;
7190 case 8:
7191 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7192 return 1;
7193 break;
7194 }
7195 break;
7196 case 2: /* clts */
7197 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7198 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7199 return 1;
7200 break;
7201 case 1: /* mov from cr */
7202 switch (cr) {
7203 case 3:
7204 if (vmcs12->cpu_based_vm_exec_control &
7205 CPU_BASED_CR3_STORE_EXITING)
7206 return 1;
7207 break;
7208 case 8:
7209 if (vmcs12->cpu_based_vm_exec_control &
7210 CPU_BASED_CR8_STORE_EXITING)
7211 return 1;
7212 break;
7213 }
7214 break;
7215 case 3: /* lmsw */
7216 /*
7217 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7218 * cr0. Other attempted changes are ignored, with no exit.
7219 */
7220 if (vmcs12->cr0_guest_host_mask & 0xe &
7221 (val ^ vmcs12->cr0_read_shadow))
7222 return 1;
7223 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7224 !(vmcs12->cr0_read_shadow & 0x1) &&
7225 (val & 0x1))
7226 return 1;
7227 break;
7228 }
7229 return 0;
7230}
7231
7232/*
7233 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7234 * should handle it ourselves in L0 (and then continue L2). Only call this
7235 * when in is_guest_mode (L2).
7236 */
7237static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7238{
644d711a
NHE		 7239 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7240 struct vcpu_vmx *vmx = to_vmx(vcpu);
7241 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7242 u32 exit_reason = vmx->exit_reason;
644d711a 7243
542060ea
JK		 7244 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7245 vmcs_readl(EXIT_QUALIFICATION),
7246 vmx->idt_vectoring_info,
7247 intr_info,
7248 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7249 KVM_ISA_VMX);
7250
644d711a
NHE		 7251 if (vmx->nested.nested_run_pending)
7252 return 0;
7253
7254 if (unlikely(vmx->fail)) {
bd80158a
JK		 7255 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7256 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7257 return 1;
7258 }
7259
7260 switch (exit_reason) {
7261 case EXIT_REASON_EXCEPTION_NMI:
7262 if (!is_exception(intr_info))
7263 return 0;
7264 else if (is_page_fault(intr_info))
7265 return enable_ept;
e504c909 7266 else if (is_no_device(intr_info) &&
ccf9844e 7267 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7268 return 0;
644d711a
NHE		 7269 return vmcs12->exception_bitmap &
7270 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7271 case EXIT_REASON_EXTERNAL_INTERRUPT:
7272 return 0;
7273 case EXIT_REASON_TRIPLE_FAULT:
7274 return 1;
7275 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7276 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7277 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7278 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7279 case EXIT_REASON_TASK_SWITCH:
7280 return 1;
7281 case EXIT_REASON_CPUID:
bc613494
MT		 7282 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7283 return 0;
644d711a
NHE		 7284 return 1;
7285 case EXIT_REASON_HLT:
7286 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7287 case EXIT_REASON_INVD:
7288 return 1;
7289 case EXIT_REASON_INVLPG:
7290 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7291 case EXIT_REASON_RDPMC:
7292 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7293 case EXIT_REASON_RDTSC:
7294 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7295 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7296 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7297 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7298 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7299 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7300 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7301 /*
7302 * VMX instructions trap unconditionally. This allows L1 to
7303 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7304 */
7305 return 1;
7306 case EXIT_REASON_CR_ACCESS:
7307 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7308 case EXIT_REASON_DR_ACCESS:
7309 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7310 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7311 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7312 case EXIT_REASON_MSR_READ:
7313 case EXIT_REASON_MSR_WRITE:
7314 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7315 case EXIT_REASON_INVALID_STATE:
7316 return 1;
7317 case EXIT_REASON_MWAIT_INSTRUCTION:
7318 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7319 case EXIT_REASON_MONITOR_INSTRUCTION:
7320 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7321 case EXIT_REASON_PAUSE_INSTRUCTION:
7322 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7323 nested_cpu_has2(vmcs12,
7324 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7325 case EXIT_REASON_MCE_DURING_VMENTRY:
7326 return 0;
7327 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7328 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7329 case EXIT_REASON_APIC_ACCESS:
7330 return nested_cpu_has2(vmcs12,
7331 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7332 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7333 /*
7334 * L0 always deals with the EPT violation. If nested EPT is
7335 * used, and the nested mmu code discovers that the address is
7336 * missing in the guest EPT table (EPT12), the EPT violation
7337 * will be injected with nested_ept_inject_page_fault()
7338 */
7339 return 0;
644d711a 7340 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7341 /*
7342 * L2 never uses directly L1's EPT, but rather L0's own EPT
7343 * table (shadow on EPT) or a merged EPT table that L0 built
7344 * (EPT on EPT). So any problems with the structure of the
7345 * table is L0's fault.
7346 */
644d711a
NHE		 7347 return 0;
7348 case EXIT_REASON_WBINVD:
7349 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7350 case EXIT_REASON_XSETBV:
7351 return 1;
81dc01f7
WL		 7352 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7353 /*
7354 * This should never happen, since it is not possible to
7355 * set XSS to a non-zero value---neither in L1 nor in L2.
7356 * If if it were, XSS would have to be checked against
7357 * the XSS exit bitmap in vmcs12.
7358 */
7359 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a
NHE		 7360 default:
7361 return 1;
7362 }
7363}
7364
586f9607
AK		 7365static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7366{
7367 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7368 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7369}
7370
843e4330
KH		 7371static int vmx_enable_pml(struct vcpu_vmx *vmx)
7372{
7373 struct page *pml_pg;
7374 u32 exec_control;
7375
7376 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7377 if (!pml_pg)
7378 return -ENOMEM;
7379
7380 vmx->pml_pg = pml_pg;
7381
7382 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7383 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7384
7385 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7386 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7387 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7388
7389 return 0;
7390}
7391
7392static void vmx_disable_pml(struct vcpu_vmx *vmx)
7393{
7394 u32 exec_control;
7395
7396 ASSERT(vmx->pml_pg);
7397 __free_page(vmx->pml_pg);
7398 vmx->pml_pg = NULL;
7399
7400 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7401 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7402 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7403}
7404
7405static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7406{
7407 struct kvm *kvm = vmx->vcpu.kvm;
7408 u64 *pml_buf;
7409 u16 pml_idx;
7410
7411 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7412
7413 /* Do nothing if PML buffer is empty */
7414 if (pml_idx == (PML_ENTITY_NUM - 1))
7415 return;
7416
7417 /* PML index always points to next available PML buffer entity */
7418 if (pml_idx >= PML_ENTITY_NUM)
7419 pml_idx = 0;
7420 else
7421 pml_idx++;
7422
7423 pml_buf = page_address(vmx->pml_pg);
7424 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7425 u64 gpa;
7426
7427 gpa = pml_buf[pml_idx];
7428 WARN_ON(gpa & (PAGE_SIZE - 1));
7429 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7430 }
7431
7432 /* reset PML index */
7433 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7434}
7435
7436/*
7437 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7438 * Called before reporting dirty_bitmap to userspace.
7439 */
7440static void kvm_flush_pml_buffers(struct kvm *kvm)
7441{
7442 int i;
7443 struct kvm_vcpu *vcpu;
7444 /*
7445 * We only need to kick vcpu out of guest mode here, as PML buffer
7446 * is flushed at beginning of all VMEXITs, and it's obvious that only
7447 * vcpus running in guest are possible to have unflushed GPAs in PML
7448 * buffer.
7449 */
7450 kvm_for_each_vcpu(i, vcpu, kvm)
7451 kvm_vcpu_kick(vcpu);
7452}
7453
6aa8b732
AK		 7454/*
7455 * The guest has exited. See if we can fix it or if we need userspace
7456 * assistance.
7457 */
851ba692 7458static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7459{
29bd8a78 7460 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7461 u32 exit_reason = vmx->exit_reason;
1155f76a 7462 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7463
843e4330
KH		 7464 /*
7465 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7466 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7467 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7468 * mode as if vcpus is in root mode, the PML buffer must has been
7469 * flushed already.
7470 */
7471 if (enable_pml)
7472 vmx_flush_pml_buffer(vmx);
7473
80ced186 7474 /* If guest state is invalid, start emulating */
14168786 7475 if (vmx->emulation_required)
80ced186 7476 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7477
644d711a 7478 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7479 nested_vmx_vmexit(vcpu, exit_reason,
7480 vmcs_read32(VM_EXIT_INTR_INFO),
7481 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7482 return 1;
7483 }
7484
5120702e
MG		 7485 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7486 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7487 vcpu->run->fail_entry.hardware_entry_failure_reason
7488 = exit_reason;
7489 return 0;
7490 }
7491
29bd8a78 7492 if (unlikely(vmx->fail)) {
851ba692
AK		 7493 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7494 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7495 = vmcs_read32(VM_INSTRUCTION_ERROR);
7496 return 0;
7497 }
6aa8b732 7498
b9bf6882
XG		 7499 /*
7500 * Note:
7501 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7502 * delivery event since it indicates guest is accessing MMIO.
7503 * The vm-exit can be triggered again after return to guest that
7504 * will cause infinite loop.
7505 */
d77c26fc 7506 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7507 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7508 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7509 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7510 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7511 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7512 vcpu->run->internal.ndata = 2;
7513 vcpu->run->internal.data[0] = vectoring_info;
7514 vcpu->run->internal.data[1] = exit_reason;
7515 return 0;
7516 }
3b86cd99 7517
644d711a
NHE		 7518 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7519 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7520 get_vmcs12(vcpu))))) {
c4282df9 7521 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7522 vmx->soft_vnmi_blocked = 0;
3b86cd99 7523 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7524 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7525 /*
7526 * This CPU don't support us in finding the end of an
7527 * NMI-blocked window if the guest runs with IRQs
7528 * disabled. So we pull the trigger after 1 s of
7529 * futile waiting, but inform the user about this.
7530 */
7531 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7532 "state on VCPU %d after 1 s timeout\n",
7533 __func__, vcpu->vcpu_id);
7534 vmx->soft_vnmi_blocked = 0;
3b86cd99 7535 }
3b86cd99
JK		 7536 }
7537
6aa8b732
AK		 7538 if (exit_reason < kvm_vmx_max_exit_handlers
7539 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7540 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7541 else {
2bc19dc3
MT		 7542 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7543 kvm_queue_exception(vcpu, UD_VECTOR);
7544 return 1;
6aa8b732 7545 }
6aa8b732
AK		 7546}
7547
95ba8273 7548static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7549{
a7c0b07d
WL		 7550 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7551
7552 if (is_guest_mode(vcpu) &&
7553 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7554 return;
7555
95ba8273 7556 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7557 vmcs_write32(TPR_THRESHOLD, 0);
7558 return;
7559 }
7560
95ba8273 7561 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7562}
7563
8d14695f
YZ		 7564static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7565{
7566 u32 sec_exec_control;
7567
7568 /*
7569 * There is not point to enable virtualize x2apic without enable
7570 * apicv
7571 */
c7c9c56c
YZ		 7572 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7573 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7574 return;
7575
7576 if (!vm_need_tpr_shadow(vcpu->kvm))
7577 return;
7578
7579 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7580
7581 if (set) {
7582 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7583 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7584 } else {
7585 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7586 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7587 }
7588 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7589
7590 vmx_set_msr_bitmap(vcpu);
7591}
7592
38b99173
TC		 7593static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7594{
7595 struct vcpu_vmx *vmx = to_vmx(vcpu);
7596
7597 /*
7598 * Currently we do not handle the nested case where L2 has an
7599 * APIC access page of its own; that page is still pinned.
7600 * Hence, we skip the case where the VCPU is in guest mode _and_
7601 * L1 prepared an APIC access page for L2.
7602 *
7603 * For the case where L1 and L2 share the same APIC access page
7604 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7605 * in the vmcs12), this function will only update either the vmcs01
7606 * or the vmcs02. If the former, the vmcs02 will be updated by
7607 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7608 * the next L2->L1 exit.
7609 */
7610 if (!is_guest_mode(vcpu) ||
7611 !nested_cpu_has2(vmx->nested.current_vmcs12,
7612 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7613 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7614}
7615
c7c9c56c
YZ		 7616static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7617{
7618 u16 status;
7619 u8 old;
7620
c7c9c56c
YZ		 7621 if (isr == -1)
7622 isr = 0;
7623
7624 status = vmcs_read16(GUEST_INTR_STATUS);
7625 old = status >> 8;
7626 if (isr != old) {
7627 status &= 0xff;
7628 status |= isr << 8;
7629 vmcs_write16(GUEST_INTR_STATUS, status);
7630 }
7631}
7632
7633static void vmx_set_rvi(int vector)
7634{
7635 u16 status;
7636 u8 old;
7637
4114c27d
WW		 7638 if (vector == -1)
7639 vector = 0;
7640
c7c9c56c
YZ		 7641 status = vmcs_read16(GUEST_INTR_STATUS);
7642 old = (u8)status & 0xff;
7643 if ((u8)vector != old) {
7644 status &= ~0xff;
7645 status |= (u8)vector;
7646 vmcs_write16(GUEST_INTR_STATUS, status);
7647 }
7648}
7649
7650static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7651{
4114c27d
WW		 7652 if (!is_guest_mode(vcpu)) {
7653 vmx_set_rvi(max_irr);
7654 return;
7655 }
7656
c7c9c56c
YZ		 7657 if (max_irr == -1)
7658 return;
7659
963fee16 7660 /*
4114c27d
WW		 7661 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7662 * handles it.
963fee16 7663 */
4114c27d 7664 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7665 return;
7666
963fee16 7667 /*
4114c27d 7668 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7669 * is run without virtual interrupt delivery.
7670 */
7671 if (!kvm_event_needs_reinjection(vcpu) &&
7672 vmx_interrupt_allowed(vcpu)) {
7673 kvm_queue_interrupt(vcpu, max_irr, false);
7674 vmx_inject_irq(vcpu);
7675 }
c7c9c56c
YZ		 7676}
7677
7678static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7679{
3d81bc7e
YZ		 7680 if (!vmx_vm_has_apicv(vcpu->kvm))
7681 return;
7682
c7c9c56c
YZ		 7683 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7684 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7685 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7686 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7687}
7688
51aa01d1 7689static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7690{
00eba012
AK		 7691 u32 exit_intr_info;
7692
7693 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7694 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7695 return;
7696
c5ca8e57 7697 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7698 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7699
7700 /* Handle machine checks before interrupts are enabled */
00eba012 7701 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7702 kvm_machine_check();
7703
20f65983 7704 /* We need to handle NMIs before interrupts are enabled */
00eba012 7705 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7706 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7707 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7708 asm("int $2");
ff9d07a0
ZY		 7709 kvm_after_handle_nmi(&vmx->vcpu);
7710 }
51aa01d1 7711}
20f65983 7712
a547c6db
YZ		 7713static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7714{
7715 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7716
7717 /*
7718 * If external interrupt exists, IF bit is set in rflags/eflags on the
7719 * interrupt stack frame, and interrupt will be enabled on a return
7720 * from interrupt handler.
7721 */
7722 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7723 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7724 unsigned int vector;
7725 unsigned long entry;
7726 gate_desc *desc;
7727 struct vcpu_vmx *vmx = to_vmx(vcpu);
7728#ifdef CONFIG_X86_64
7729 unsigned long tmp;
7730#endif
7731
7732 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7733 desc = (gate_desc *)vmx->host_idt_base + vector;
7734 entry = gate_offset(*desc);
7735 asm volatile(
7736#ifdef CONFIG_X86_64
7737 "mov %%" _ASM_SP ", %[sp]\n\t"
7738 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7739 "push $%c[ss]\n\t"
7740 "push %[sp]\n\t"
7741#endif
7742 "pushf\n\t"
7743 "orl $0x200, (%%" _ASM_SP ")\n\t"
7744 __ASM_SIZE(push) " $%c[cs]\n\t"
7745 "call *%[entry]\n\t"
7746 :
7747#ifdef CONFIG_X86_64
7748 [sp]"=&r"(tmp)
7749#endif
7750 :
7751 [entry]"r"(entry),
7752 [ss]"i"(__KERNEL_DS),
7753 [cs]"i"(__KERNEL_CS)
7754 );
7755 } else
7756 local_irq_enable();
7757}
7758
da8999d3
LJ		 7759static bool vmx_mpx_supported(void)
7760{
7761 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7762 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7763}
7764
55412b2e
WL		 7765static bool vmx_xsaves_supported(void)
7766{
7767 return vmcs_config.cpu_based_2nd_exec_ctrl &
7768 SECONDARY_EXEC_XSAVES;
7769}
7770
51aa01d1
AK		 7771static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7772{
c5ca8e57 7773 u32 exit_intr_info;
51aa01d1
AK		 7774 bool unblock_nmi;
7775 u8 vector;
7776 bool idtv_info_valid;
7777
7778 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7779
cf393f75 7780 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7781 if (vmx->nmi_known_unmasked)
7782 return;
c5ca8e57
AK		 7783 /*
7784 * Can't use vmx->exit_intr_info since we're not sure what
7785 * the exit reason is.
7786 */
7787 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7788 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7789 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7790 /*
7b4a25cb 7791 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7792 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7793 * a guest IRET fault.
7b4a25cb
GN		 7794 * SDM 3: 23.2.2 (September 2008)
7795 * Bit 12 is undefined in any of the following cases:
7796 * If the VM exit sets the valid bit in the IDT-vectoring
7797 * information field.
7798 * If the VM exit is due to a double fault.
cf393f75 7799 */
7b4a25cb
GN		 7800 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7801 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7802 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7803 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7804 else
7805 vmx->nmi_known_unmasked =
7806 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7807 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7808 } else if (unlikely(vmx->soft_vnmi_blocked))
7809 vmx->vnmi_blocked_time +=
7810 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7811}
7812
3ab66e8a 7813static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7814 u32 idt_vectoring_info,
7815 int instr_len_field,
7816 int error_code_field)
51aa01d1 7817{
51aa01d1
AK		 7818 u8 vector;
7819 int type;
7820 bool idtv_info_valid;
7821
7822 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7823
3ab66e8a
JK		 7824 vcpu->arch.nmi_injected = false;
7825 kvm_clear_exception_queue(vcpu);
7826 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7827
7828 if (!idtv_info_valid)
7829 return;
7830
3ab66e8a 7831 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7832
668f612f
AK		 7833 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7834 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7835
64a7ec06 7836 switch (type) {
37b96e98 7837 case INTR_TYPE_NMI_INTR:
3ab66e8a 7838 vcpu->arch.nmi_injected = true;
668f612f 7839 /*
7b4a25cb 7840 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7841 * Clear bit "block by NMI" before VM entry if a NMI
7842 * delivery faulted.
668f612f 7843 */
3ab66e8a 7844 vmx_set_nmi_mask(vcpu, false);
37b96e98 7845 break;
37b96e98 7846 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7847 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7848 /* fall through */
7849 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7850 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7851 u32 err = vmcs_read32(error_code_field);
851eb667 7852 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7853 } else
851eb667 7854 kvm_requeue_exception(vcpu, vector);
37b96e98 7855 break;
66fd3f7f 7856 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7857 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7858 /* fall through */
37b96e98 7859 case INTR_TYPE_EXT_INTR:
3ab66e8a 7860 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7861 break;
7862 default:
7863 break;
f7d9238f 7864 }
cf393f75
AK		 7865}
7866
83422e17
AK		 7867static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7868{
3ab66e8a 7869 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7870 VM_EXIT_INSTRUCTION_LEN,
7871 IDT_VECTORING_ERROR_CODE);
7872}
7873
b463a6f7
AK		 7874static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7875{
3ab66e8a 7876 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7877 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7878 VM_ENTRY_INSTRUCTION_LEN,
7879 VM_ENTRY_EXCEPTION_ERROR_CODE);
7880
7881 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7882}
7883
d7cd9796
GN		 7884static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7885{
7886 int i, nr_msrs;
7887 struct perf_guest_switch_msr *msrs;
7888
7889 msrs = perf_guest_get_msrs(&nr_msrs);
7890
7891 if (!msrs)
7892 return;
7893
7894 for (i = 0; i < nr_msrs; i++)
7895 if (msrs[i].host == msrs[i].guest)
7896 clear_atomic_switch_msr(vmx, msrs[i].msr);
7897 else
7898 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7899 msrs[i].host);
7900}
7901
a3b5ba49 7902static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7903{
a2fa3e9f 7904 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7905 unsigned long debugctlmsr, cr4;
104f226b
AK		 7906
7907 /* Record the guest's net vcpu time for enforced NMI injections. */
7908 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7909 vmx->entry_time = ktime_get();
7910
7911 /* Don't enter VMX if guest state is invalid, let the exit handler
7912 start emulation until we arrive back to a valid state */
14168786 7913 if (vmx->emulation_required)
104f226b
AK		 7914 return;
7915
a7653ecd
RK		 7916 if (vmx->ple_window_dirty) {
7917 vmx->ple_window_dirty = false;
7918 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7919 }
7920
012f83cb
AG		 7921 if (vmx->nested.sync_shadow_vmcs) {
7922 copy_vmcs12_to_shadow(vmx);
7923 vmx->nested.sync_shadow_vmcs = false;
7924 }
7925
104f226b
AK		 7926 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7927 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7928 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7929 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7930
d974baa3
AL		 7931 cr4 = read_cr4();
7932 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7933 vmcs_writel(HOST_CR4, cr4);
7934 vmx->host_state.vmcs_host_cr4 = cr4;
7935 }
7936
104f226b
AK		 7937 /* When single-stepping over STI and MOV SS, we must clear the
7938 * corresponding interruptibility bits in the guest state. Otherwise
7939 * vmentry fails as it then expects bit 14 (BS) in pending debug
7940 * exceptions being set, but that's not correct for the guest debugging
7941 * case. */
7942 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7943 vmx_set_interrupt_shadow(vcpu, 0);
7944
d7cd9796 7945 atomic_switch_perf_msrs(vmx);
2a7921b7 7946 debugctlmsr = get_debugctlmsr();
d7cd9796 7947
d462b819 7948 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7949 asm(
6aa8b732 7950 /* Store host registers */
b188c81f
AK		 7951 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7952 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7953 "push %%" _ASM_CX " \n\t"
7954 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7955 "je 1f \n\t"
b188c81f 7956 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7957 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7958 "1: \n\t"
d3edefc0 7959 /* Reload cr2 if changed */
b188c81f
AK		 7960 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7961 "mov %%cr2, %%" _ASM_DX " \n\t"
7962 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7963 "je 2f \n\t"
b188c81f 7964 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7965 "2: \n\t"
6aa8b732 7966 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7967 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7968 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7969 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7970 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7971 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7972 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7973 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7974 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7975#ifdef CONFIG_X86_64
e08aa78a
AK		 7976 "mov %c[r8](%0), %%r8 \n\t"
7977 "mov %c[r9](%0), %%r9 \n\t"
7978 "mov %c[r10](%0), %%r10 \n\t"
7979 "mov %c[r11](%0), %%r11 \n\t"
7980 "mov %c[r12](%0), %%r12 \n\t"
7981 "mov %c[r13](%0), %%r13 \n\t"
7982 "mov %c[r14](%0), %%r14 \n\t"
7983 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7984#endif
b188c81f 7985 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7986
6aa8b732 7987 /* Enter guest mode */
83287ea4 7988 "jne 1f \n\t"
4ecac3fd 7989 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7990 "jmp 2f \n\t"
7991 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7992 "2: "
6aa8b732 7993 /* Save guest registers, load host registers, keep flags */
b188c81f 7994 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7995 "pop %0 \n\t"
b188c81f
AK		 7996 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7997 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7998 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7999 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8000 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8001 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8002 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8003#ifdef CONFIG_X86_64
e08aa78a
AK		 8004 "mov %%r8, %c[r8](%0) \n\t"
8005 "mov %%r9, %c[r9](%0) \n\t"
8006 "mov %%r10, %c[r10](%0) \n\t"
8007 "mov %%r11, %c[r11](%0) \n\t"
8008 "mov %%r12, %c[r12](%0) \n\t"
8009 "mov %%r13, %c[r13](%0) \n\t"
8010 "mov %%r14, %c[r14](%0) \n\t"
8011 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8012#endif
b188c81f
AK		 8013 "mov %%cr2, %%" _ASM_AX " \n\t"
8014 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8015
b188c81f 8016 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8017 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8018 ".pushsection .rodata \n\t"
8019 ".global vmx_return \n\t"
8020 "vmx_return: " _ASM_PTR " 2b \n\t"
8021 ".popsection"
e08aa78a 8022 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8023 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8024 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8025 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8026 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8027 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8028 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8029 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8030 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8031 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8032 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8033#ifdef CONFIG_X86_64
ad312c7c
ZX		 8034 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8035 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8036 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8037 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8038 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8039 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8040 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8041 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8042#endif
40712fae
AK		 8043 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8044 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8045 : "cc", "memory"
8046#ifdef CONFIG_X86_64
b188c81f 8047 , "rax", "rbx", "rdi", "rsi"
c2036300 8048 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8049#else
8050 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8051#endif
8052 );
6aa8b732 8053
2a7921b7
GN		 8054 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8055 if (debugctlmsr)
8056 update_debugctlmsr(debugctlmsr);
8057
aa67f609
AK		 8058#ifndef CONFIG_X86_64
8059 /*
8060 * The sysexit path does not restore ds/es, so we must set them to
8061 * a reasonable value ourselves.
8062 *
8063 * We can't defer this to vmx_load_host_state() since that function
8064 * may be executed in interrupt context, which saves and restore segments
8065 * around it, nullifying its effect.
8066 */
8067 loadsegment(ds, __USER_DS);
8068 loadsegment(es, __USER_DS);
8069#endif
8070
6de4f3ad 8071 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8072 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8073 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8074 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8075 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8076 vcpu->arch.regs_dirty = 0;
8077
1155f76a
AK		 8078 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8079
d462b819 8080 vmx->loaded_vmcs->launched = 1;
1b6269db 8081
51aa01d1 8082 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8083 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8084
e0b890d3
GN		 8085 /*
8086 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8087 * we did not inject a still-pending event to L1 now because of
8088 * nested_run_pending, we need to re-enable this bit.
8089 */
8090 if (vmx->nested.nested_run_pending)
8091 kvm_make_request(KVM_REQ_EVENT, vcpu);
8092
8093 vmx->nested.nested_run_pending = 0;
8094
51aa01d1
AK		 8095 vmx_complete_atomic_exit(vmx);
8096 vmx_recover_nmi_blocking(vmx);
cf393f75 8097 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8098}
8099
4fa7734c
PB		 8100static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8101{
8102 struct vcpu_vmx *vmx = to_vmx(vcpu);
8103 int cpu;
8104
8105 if (vmx->loaded_vmcs == &vmx->vmcs01)
8106 return;
8107
8108 cpu = get_cpu();
8109 vmx->loaded_vmcs = &vmx->vmcs01;
8110 vmx_vcpu_put(vcpu);
8111 vmx_vcpu_load(vcpu, cpu);
8112 vcpu->cpu = cpu;
8113 put_cpu();
8114}
8115
6aa8b732
AK		 8116static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8117{
fb3f0f51
RR		 8118 struct vcpu_vmx *vmx = to_vmx(vcpu);
8119
843e4330
KH		 8120 if (enable_pml)
8121 vmx_disable_pml(vmx);
cdbecfc3 8122 free_vpid(vmx);
4fa7734c
PB		 8123 leave_guest_mode(vcpu);
8124 vmx_load_vmcs01(vcpu);
26a865f4 8125 free_nested(vmx);
4fa7734c 8126 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8127 kfree(vmx->guest_msrs);
8128 kvm_vcpu_uninit(vcpu);
a4770347 8129 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8130}
8131
fb3f0f51 8132static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8133{
fb3f0f51 8134 int err;
c16f862d 8135 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8136 int cpu;
6aa8b732 8137
a2fa3e9f 8138 if (!vmx)
fb3f0f51
RR		 8139 return ERR_PTR(-ENOMEM);
8140
2384d2b3
SY		 8141 allocate_vpid(vmx);
8142
fb3f0f51
RR		 8143 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8144 if (err)
8145 goto free_vcpu;
965b58a5 8146
a2fa3e9f 8147 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8148 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8149 > PAGE_SIZE);
0123be42 8150
be6d05cf 8151 err = -ENOMEM;
fb3f0f51 8152 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8153 goto uninit_vcpu;
8154 }
965b58a5 8155
d462b819
NHE		 8156 vmx->loaded_vmcs = &vmx->vmcs01;
8157 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8158 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8159 goto free_msrs;
d462b819
NHE		 8160 if (!vmm_exclusive)
8161 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8162 loaded_vmcs_init(vmx->loaded_vmcs);
8163 if (!vmm_exclusive)
8164 kvm_cpu_vmxoff();
a2fa3e9f 8165
15ad7146
AK		 8166 cpu = get_cpu();
8167 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8168 vmx->vcpu.cpu = cpu;
8b9cf98c 8169 err = vmx_vcpu_setup(vmx);
fb3f0f51 8170 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8171 put_cpu();
fb3f0f51
RR		 8172 if (err)
8173 goto free_vmcs;
a63cb560 8174 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8175 err = alloc_apic_access_page(kvm);
8176 if (err)
5e4a0b3c 8177 goto free_vmcs;
a63cb560 8178 }
fb3f0f51 8179
b927a3ce
SY		 8180 if (enable_ept) {
8181 if (!kvm->arch.ept_identity_map_addr)
8182 kvm->arch.ept_identity_map_addr =
8183 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8184 err = init_rmode_identity_map(kvm);
8185 if (err)
93ea5388 8186 goto free_vmcs;
b927a3ce 8187 }
b7ebfb05 8188
a9d30f33
NHE		 8189 vmx->nested.current_vmptr = -1ull;
8190 vmx->nested.current_vmcs12 = NULL;
8191
843e4330
KH		 8192 /*
8193 * If PML is turned on, failure on enabling PML just results in failure
8194 * of creating the vcpu, therefore we can simplify PML logic (by
8195 * avoiding dealing with cases, such as enabling PML partially on vcpus
8196 * for the guest, etc.
8197 */
8198 if (enable_pml) {
8199 err = vmx_enable_pml(vmx);
8200 if (err)
8201 goto free_vmcs;
8202 }
8203
fb3f0f51
RR		 8204 return &vmx->vcpu;
8205
8206free_vmcs:
5f3fbc34 8207 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8208free_msrs:
fb3f0f51
RR		 8209 kfree(vmx->guest_msrs);
8210uninit_vcpu:
8211 kvm_vcpu_uninit(&vmx->vcpu);
8212free_vcpu:
cdbecfc3 8213 free_vpid(vmx);
a4770347 8214 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8215 return ERR_PTR(err);
6aa8b732
AK		 8216}
8217
002c7f7c
YS		 8218static void __init vmx_check_processor_compat(void *rtn)
8219{
8220 struct vmcs_config vmcs_conf;
8221
8222 *(int *)rtn = 0;
8223 if (setup_vmcs_config(&vmcs_conf) < 0)
8224 *(int *)rtn = -EIO;
8225 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8226 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8227 smp_processor_id());
8228 *(int *)rtn = -EIO;
8229 }
8230}
8231
67253af5
SY		 8232static int get_ept_level(void)
8233{
8234 return VMX_EPT_DEFAULT_GAW + 1;
8235}
8236
4b12f0de 8237static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8238{
4b12f0de
SY		 8239 u64 ret;
8240
522c68c4
SY		 8241 /* For VT-d and EPT combination
8242 * 1. MMIO: always map as UC
8243 * 2. EPT with VT-d:
8244 * a. VT-d without snooping control feature: can't guarantee the
8245 * result, try to trust guest.
8246 * b. VT-d with snooping control feature: snooping control feature of
8247 * VT-d engine can guarantee the cache correctness. Just set it
8248 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8249 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8250 * consistent with host MTRR
8251 */
4b12f0de
SY		 8252 if (is_mmio)
8253 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8254 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8255 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8256 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8257 else
522c68c4 8258 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8259 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8260
8261 return ret;
64d4d521
SY		 8262}
8263
17cc3935 8264static int vmx_get_lpage_level(void)
344f414f 8265{
878403b7
SY		 8266 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8267 return PT_DIRECTORY_LEVEL;
8268 else
8269 /* For shadow and EPT supported 1GB page */
8270 return PT_PDPE_LEVEL;
344f414f
JR		 8271}
8272
0e851880
SY		 8273static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8274{
4e47c7a6
SY		 8275 struct kvm_cpuid_entry2 *best;
8276 struct vcpu_vmx *vmx = to_vmx(vcpu);
8277 u32 exec_control;
8278
8279 vmx->rdtscp_enabled = false;
8280 if (vmx_rdtscp_supported()) {
8281 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8282 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8283 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8284 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8285 vmx->rdtscp_enabled = true;
8286 else {
8287 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8288 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8289 exec_control);
8290 }
8291 }
8292 }
ad756a16 8293
ad756a16
MJ		 8294 /* Exposing INVPCID only when PCID is exposed */
8295 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8296 if (vmx_invpcid_supported() &&
4f977045 8297 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8298 guest_cpuid_has_pcid(vcpu)) {
29282fde 8299 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8300 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8301 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8302 exec_control);
8303 } else {
29282fde
TI		 8304 if (cpu_has_secondary_exec_ctrls()) {
8305 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8306 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8307 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8308 exec_control);
8309 }
ad756a16 8310 if (best)
4f977045 8311 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8312 }
0e851880
SY		 8313}
8314
d4330ef2
JR		 8315static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8316{
7b8050f5
NHE		 8317 if (func == 1 && nested)
8318 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8319}
8320
25d92081
YZ		 8321static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8322 struct x86_exception *fault)
8323{
533558bc
JK		 8324 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8325 u32 exit_reason;
25d92081
YZ		 8326
8327 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8328 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8329 else
533558bc
JK		 8330 exit_reason = EXIT_REASON_EPT_VIOLATION;
8331 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8332 vmcs12->guest_physical_address = fault->address;
8333}
8334
155a97a3
NHE		 8335/* Callbacks for nested_ept_init_mmu_context: */
8336
8337static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8338{
8339 /* return the page table to be shadowed - in our case, EPT12 */
8340 return get_vmcs12(vcpu)->ept_pointer;
8341}
8342
8a3c1a33 8343static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8344{
ad896af0
PB		 8345 WARN_ON(mmu_is_nested(vcpu));
8346 kvm_init_shadow_ept_mmu(vcpu,
155a97a3 8347 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8348 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8349 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8350 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8351
8352 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8353}
8354
8355static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8356{
8357 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8358}
8359
19d5f10b
EK		 8360static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8361 u16 error_code)
8362{
8363 bool inequality, bit;
8364
8365 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8366 inequality =
8367 (error_code & vmcs12->page_fault_error_code_mask) !=
8368 vmcs12->page_fault_error_code_match;
8369 return inequality ^ bit;
8370}
8371
feaf0c7d
GN		 8372static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8373 struct x86_exception *fault)
8374{
8375 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8376
8377 WARN_ON(!is_guest_mode(vcpu));
8378
19d5f10b 8379 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8380 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8381 vmcs_read32(VM_EXIT_INTR_INFO),
8382 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8383 else
8384 kvm_inject_page_fault(vcpu, fault);
8385}
8386
a2bcba50
WL		 8387static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8388 struct vmcs12 *vmcs12)
8389{
8390 struct vcpu_vmx *vmx = to_vmx(vcpu);
8391
8392 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8393 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8394 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8395 return false;
8396
8397 /*
8398 * Translate L1 physical address to host physical
8399 * address for vmcs02. Keep the page pinned, so this
8400 * physical address remains valid. We keep a reference
8401 * to it so we can release it later.
8402 */
8403 if (vmx->nested.apic_access_page) /* shouldn't happen */
8404 nested_release_page(vmx->nested.apic_access_page);
8405 vmx->nested.apic_access_page =
8406 nested_get_page(vcpu, vmcs12->apic_access_addr);
8407 }
a7c0b07d
WL		 8408
8409 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8410 /* TODO: Also verify bits beyond physical address width are 0 */
8411 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8412 return false;
8413
8414 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8415 nested_release_page(vmx->nested.virtual_apic_page);
8416 vmx->nested.virtual_apic_page =
8417 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8418
8419 /*
8420 * Failing the vm entry is _not_ what the processor does
8421 * but it's basically the only possibility we have.
8422 * We could still enter the guest if CR8 load exits are
8423 * enabled, CR8 store exits are enabled, and virtualize APIC
8424 * access is disabled; in this case the processor would never
8425 * use the TPR shadow and we could simply clear the bit from
8426 * the execution control. But such a configuration is useless,
8427 * so let's keep the code simple.
8428 */
8429 if (!vmx->nested.virtual_apic_page)
8430 return false;
8431 }
8432
a2bcba50
WL		 8433 return true;
8434}
8435
f4124500
JK		 8436static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8437{
8438 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8439 struct vcpu_vmx *vmx = to_vmx(vcpu);
8440
8441 if (vcpu->arch.virtual_tsc_khz == 0)
8442 return;
8443
8444 /* Make sure short timeouts reliably trigger an immediate vmexit.
8445 * hrtimer_start does not guarantee this. */
8446 if (preemption_timeout <= 1) {
8447 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8448 return;
8449 }
8450
8451 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8452 preemption_timeout *= 1000000;
8453 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8454 hrtimer_start(&vmx->nested.preemption_timer,
8455 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8456}
8457
e9ac033e
EK		 8458static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8459 unsigned long count_field,
8460 unsigned long addr_field,
8461 int maxphyaddr)
ff651cb6 8462{
e9ac033e
EK		 8463 u64 count, addr;
8464
8465 if (vmcs12_read_any(vcpu, count_field, &count) ||
8466 vmcs12_read_any(vcpu, addr_field, &addr)) {
8467 WARN_ON(1);
8468 return -EINVAL;
8469 }
8470 if (count == 0)
8471 return 0;
8472 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8473 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8474 pr_warn_ratelimited(
8475 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8476 addr_field, maxphyaddr, count, addr);
8477 return -EINVAL;
8478 }
8479 return 0;
8480}
8481
8482static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8483 struct vmcs12 *vmcs12)
8484{
8485 int maxphyaddr;
8486
8487 if (vmcs12->vm_exit_msr_load_count == 0 &&
8488 vmcs12->vm_exit_msr_store_count == 0 &&
8489 vmcs12->vm_entry_msr_load_count == 0)
8490 return 0; /* Fast path */
8491 maxphyaddr = cpuid_maxphyaddr(vcpu);
8492 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8493 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8494 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8495 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8496 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8497 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8498 return -EINVAL;
8499 return 0;
8500}
8501
8502static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8503 struct vmx_msr_entry *e)
8504{
8505 /* x2APIC MSR accesses are not allowed */
8506 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8507 return -EINVAL;
8508 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8509 e->index == MSR_IA32_UCODE_REV)
8510 return -EINVAL;
8511 if (e->reserved != 0)
ff651cb6
WV		 8512 return -EINVAL;
8513 return 0;
8514}
8515
e9ac033e
EK		 8516static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8517 struct vmx_msr_entry *e)
ff651cb6
WV		 8518{
8519 if (e->index == MSR_FS_BASE ||
8520 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8521 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8522 nested_vmx_msr_check_common(vcpu, e))
8523 return -EINVAL;
8524 return 0;
8525}
8526
8527static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8528 struct vmx_msr_entry *e)
8529{
8530 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8531 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8532 return -EINVAL;
8533 return 0;
8534}
8535
8536/*
8537 * Load guest's/host's msr at nested entry/exit.
8538 * return 0 for success, entry index for failure.
8539 */
8540static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8541{
8542 u32 i;
8543 struct vmx_msr_entry e;
8544 struct msr_data msr;
8545
8546 msr.host_initiated = false;
8547 for (i = 0; i < count; i++) {
e9ac033e
EK		 8548 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8549 &e, sizeof(e))) {
8550 pr_warn_ratelimited(
8551 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8552 __func__, i, gpa + i * sizeof(e));
ff651cb6 8553 goto fail;
e9ac033e
EK		 8554 }
8555 if (nested_vmx_load_msr_check(vcpu, &e)) {
8556 pr_warn_ratelimited(
8557 "%s check failed (%u, 0x%x, 0x%x)\n",
8558 __func__, i, e.index, e.reserved);
8559 goto fail;
8560 }
ff651cb6
WV		 8561 msr.index = e.index;
8562 msr.data = e.value;
e9ac033e
EK		 8563 if (kvm_set_msr(vcpu, &msr)) {
8564 pr_warn_ratelimited(
8565 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8566 __func__, i, e.index, e.value);
ff651cb6 8567 goto fail;
e9ac033e 8568 }
ff651cb6
WV		 8569 }
8570 return 0;
8571fail:
8572 return i + 1;
8573}
8574
8575static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8576{
8577 u32 i;
8578 struct vmx_msr_entry e;
8579
8580 for (i = 0; i < count; i++) {
e9ac033e
EK		 8581 if (kvm_read_guest(vcpu->kvm,
8582 gpa + i * sizeof(e),
8583 &e, 2 * sizeof(u32))) {
8584 pr_warn_ratelimited(
8585 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8586 __func__, i, gpa + i * sizeof(e));
ff651cb6 8587 return -EINVAL;
e9ac033e
EK		 8588 }
8589 if (nested_vmx_store_msr_check(vcpu, &e)) {
8590 pr_warn_ratelimited(
8591 "%s check failed (%u, 0x%x, 0x%x)\n",
8592 __func__, i, e.index, e.reserved);
ff651cb6 8593 return -EINVAL;
e9ac033e
EK		 8594 }
8595 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8596 pr_warn_ratelimited(
8597 "%s cannot read MSR (%u, 0x%x)\n",
8598 __func__, i, e.index);
8599 return -EINVAL;
8600 }
8601 if (kvm_write_guest(vcpu->kvm,
8602 gpa + i * sizeof(e) +
ff651cb6 8603 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 8604 &e.value, sizeof(e.value))) {
8605 pr_warn_ratelimited(
8606 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8607 __func__, i, e.index, e.value);
8608 return -EINVAL;
8609 }
ff651cb6
WV		 8610 }
8611 return 0;
8612}
8613
fe3ef05c
NHE		 8614/*
8615 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8616 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8617 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8618 * guest in a way that will both be appropriate to L1's requests, and our
8619 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8620 * function also has additional necessary side-effects, like setting various
8621 * vcpu->arch fields.
8622 */
8623static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8624{
8625 struct vcpu_vmx *vmx = to_vmx(vcpu);
8626 u32 exec_control;
8627
8628 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8629 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8630 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8631 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8632 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8633 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8634 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8635 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8636 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8637 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8638 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8639 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8640 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8641 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8642 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8643 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8644 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8645 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8646 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8647 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8648 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8649 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8650 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8651 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8652 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8653 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8654 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8655 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8656 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8657 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8658 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8659 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8660 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8661 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8662 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8663 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8664
2996fca0
JK		 8665 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8666 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8667 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8668 } else {
8669 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8670 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8671 }
fe3ef05c
NHE		 8672 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8673 vmcs12->vm_entry_intr_info_field);
8674 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8675 vmcs12->vm_entry_exception_error_code);
8676 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8677 vmcs12->vm_entry_instruction_len);
8678 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8679 vmcs12->guest_interruptibility_info);
fe3ef05c 8680 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8681 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8682 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8683 vmcs12->guest_pending_dbg_exceptions);
8684 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8685 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8686
81dc01f7
WL		 8687 if (nested_cpu_has_xsaves(vmcs12))
8688 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 8689 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8690
f4124500
JK		 8691 exec_control = vmcs12->pin_based_vm_exec_control;
8692 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8693 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8694 PIN_BASED_POSTED_INTR);
f4124500 8695 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8696
f4124500
JK		 8697 vmx->nested.preemption_timer_expired = false;
8698 if (nested_cpu_has_preemption_timer(vmcs12))
8699 vmx_start_preemption_timer(vcpu);
0238ea91 8700
fe3ef05c
NHE		 8701 /*
8702 * Whether page-faults are trapped is determined by a combination of
8703 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8704 * If enable_ept, L0 doesn't care about page faults and we should
8705 * set all of these to L1's desires. However, if !enable_ept, L0 does
8706 * care about (at least some) page faults, and because it is not easy
8707 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8708 * to exit on each and every L2 page fault. This is done by setting
8709 * MASK=MATCH=0 and (see below) EB.PF=1.
8710 * Note that below we don't need special code to set EB.PF beyond the
8711 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8712 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8713 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8714 *
8715 * A problem with this approach (when !enable_ept) is that L1 may be
8716 * injected with more page faults than it asked for. This could have
8717 * caused problems, but in practice existing hypervisors don't care.
8718 * To fix this, we will need to emulate the PFEC checking (on the L1
8719 * page tables), using walk_addr(), when injecting PFs to L1.
8720 */
8721 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8722 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8723 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8724 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8725
8726 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8727 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8728 if (!vmx->rdtscp_enabled)
8729 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8730 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8731 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8732 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8733 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8734 if (nested_cpu_has(vmcs12,
8735 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8736 exec_control |= vmcs12->secondary_vm_exec_control;
8737
8738 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8739 /*
8740 * If translation failed, no matter: This feature asks
8741 * to exit when accessing the given address, and if it
8742 * can never be accessed, this feature won't do
8743 * anything anyway.
8744 */
8745 if (!vmx->nested.apic_access_page)
8746 exec_control &=
8747 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8748 else
8749 vmcs_write64(APIC_ACCESS_ADDR,
8750 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8751 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8752 exec_control |=
8753 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8754 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8755 }
8756
8757 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8758 }
8759
8760
8761 /*
8762 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8763 * Some constant fields are set here by vmx_set_constant_host_state().
8764 * Other fields are different per CPU, and will be set later when
8765 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8766 */
a547c6db 8767 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8768
8769 /*
8770 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8771 * entry, but only if the current (host) sp changed from the value
8772 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8773 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8774 * here we just force the write to happen on entry.
8775 */
8776 vmx->host_rsp = 0;
8777
8778 exec_control = vmx_exec_control(vmx); /* L0's desires */
8779 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8780 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8781 exec_control &= ~CPU_BASED_TPR_SHADOW;
8782 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8783
8784 if (exec_control & CPU_BASED_TPR_SHADOW) {
8785 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8786 page_to_phys(vmx->nested.virtual_apic_page));
8787 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8788 }
8789
fe3ef05c
NHE		 8790 /*
8791 * Merging of IO and MSR bitmaps not currently supported.
8792 * Rather, exit every time.
8793 */
8794 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8795 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8796 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8797
8798 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8799
8800 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8801 * bitwise-or of what L1 wants to trap for L2, and what we want to
8802 * trap. Note that CR0.TS also needs updating - we do this later.
8803 */
8804 update_exception_bitmap(vcpu);
8805 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8806 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8807
8049d651
NHE		 8808 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8809 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8810 * bits are further modified by vmx_set_efer() below.
8811 */
f4124500 8812 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8813
8814 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8815 * emulated by vmx_set_efer(), below.
8816 */
2961e876 8817 vm_entry_controls_init(vmx,
8049d651
NHE		 8818 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8819 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8820 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8821
44811c02 8822 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8823 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8824 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8825 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8826 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8827
8828
8829 set_cr4_guest_host_mask(vmx);
8830
36be0b9d
PB		 8831 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8832 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8833
27fc51b2
NHE		 8834 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8835 vmcs_write64(TSC_OFFSET,
8836 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8837 else
8838 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8839
8840 if (enable_vpid) {
8841 /*
8842 * Trivially support vpid by letting L2s share their parent
8843 * L1's vpid. TODO: move to a more elaborate solution, giving
8844 * each L2 its own vpid and exposing the vpid feature to L1.
8845 */
8846 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8847 vmx_flush_tlb(vcpu);
8848 }
8849
155a97a3
NHE		 8850 if (nested_cpu_has_ept(vmcs12)) {
8851 kvm_mmu_unload(vcpu);
8852 nested_ept_init_mmu_context(vcpu);
8853 }
8854
fe3ef05c
NHE		 8855 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8856 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8857 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8858 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8859 else
8860 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8861 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8862 vmx_set_efer(vcpu, vcpu->arch.efer);
8863
8864 /*
8865 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8866 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8867 * The CR0_READ_SHADOW is what L2 should have expected to read given
8868 * the specifications by L1; It's not enough to take
8869 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8870 * have more bits than L1 expected.
8871 */
8872 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8873 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8874
8875 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8876 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8877
8878 /* shadow page tables on either EPT or shadow page tables */
8879 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8880 kvm_mmu_reset_context(vcpu);
8881
feaf0c7d
GN		 8882 if (!enable_ept)
8883 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8884
3633cfc3
NHE		 8885 /*
8886 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8887 */
8888 if (enable_ept) {
8889 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8890 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8891 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8892 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8893 }
8894
fe3ef05c
NHE		 8895 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8896 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8897}
8898
cd232ad0
NHE		 8899/*
8900 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8901 * for running an L2 nested guest.
8902 */
8903static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8904{
8905 struct vmcs12 *vmcs12;
8906 struct vcpu_vmx *vmx = to_vmx(vcpu);
8907 int cpu;
8908 struct loaded_vmcs *vmcs02;
384bb783 8909 bool ia32e;
ff651cb6 8910 u32 msr_entry_idx;
cd232ad0
NHE		 8911
8912 if (!nested_vmx_check_permission(vcpu) ||
8913 !nested_vmx_check_vmcs12(vcpu))
8914 return 1;
8915
8916 skip_emulated_instruction(vcpu);
8917 vmcs12 = get_vmcs12(vcpu);
8918
012f83cb
AG		 8919 if (enable_shadow_vmcs)
8920 copy_shadow_to_vmcs12(vmx);
8921
7c177938
NHE		 8922 /*
8923 * The nested entry process starts with enforcing various prerequisites
8924 * on vmcs12 as required by the Intel SDM, and act appropriately when
8925 * they fail: As the SDM explains, some conditions should cause the
8926 * instruction to fail, while others will cause the instruction to seem
8927 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8928 * To speed up the normal (success) code path, we should avoid checking
8929 * for misconfigurations which will anyway be caught by the processor
8930 * when using the merged vmcs02.
8931 */
8932 if (vmcs12->launch_state == launch) {
8933 nested_vmx_failValid(vcpu,
8934 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8935 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8936 return 1;
8937 }
8938
6dfacadd
JK		 8939 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8940 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8941 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8942 return 1;
8943 }
8944
7c177938 8945 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8946 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8947 /*TODO: Also verify bits beyond physical address width are 0*/
8948 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8949 return 1;
8950 }
8951
a2bcba50 8952 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8953 /*TODO: Also verify bits beyond physical address width are 0*/
8954 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8955 return 1;
8956 }
8957
e9ac033e
EK		 8958 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
8959 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8960 return 1;
8961 }
8962
7c177938 8963 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8964 nested_vmx_true_procbased_ctls_low,
8965 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8966 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8967 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8968 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8969 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8970 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8971 nested_vmx_true_exit_ctls_low,
8972 nested_vmx_exit_ctls_high) ||
7c177938 8973 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8974 nested_vmx_true_entry_ctls_low,
8975 nested_vmx_entry_ctls_high))
7c177938
NHE		 8976 {
8977 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8978 return 1;
8979 }
8980
8981 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8982 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8983 nested_vmx_failValid(vcpu,
8984 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8985 return 1;
8986 }
8987
92fbc7b1 8988 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8989 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8990 nested_vmx_entry_failure(vcpu, vmcs12,
8991 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8992 return 1;
8993 }
8994 if (vmcs12->vmcs_link_pointer != -1ull) {
8995 nested_vmx_entry_failure(vcpu, vmcs12,
8996 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8997 return 1;
8998 }
8999
384bb783 9000 /*
cb0c8cda 9001 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9002 * are performed on the field for the IA32_EFER MSR:
9003 * - Bits reserved in the IA32_EFER MSR must be 0.
9004 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9005 * the IA-32e mode guest VM-exit control. It must also be identical
9006 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9007 * CR0.PG) is 1.
9008 */
9009 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9010 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9011 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9012 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9013 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9014 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9015 nested_vmx_entry_failure(vcpu, vmcs12,
9016 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9017 return 1;
9018 }
9019 }
9020
9021 /*
9022 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9023 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9024 * the values of the LMA and LME bits in the field must each be that of
9025 * the host address-space size VM-exit control.
9026 */
9027 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9028 ia32e = (vmcs12->vm_exit_controls &
9029 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9030 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9031 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9032 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9033 nested_vmx_entry_failure(vcpu, vmcs12,
9034 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9035 return 1;
9036 }
9037 }
9038
7c177938
NHE		 9039 /*
9040 * We're finally done with prerequisite checking, and can start with
9041 * the nested entry.
9042 */
9043
cd232ad0
NHE		 9044 vmcs02 = nested_get_current_vmcs02(vmx);
9045 if (!vmcs02)
9046 return -ENOMEM;
9047
9048 enter_guest_mode(vcpu);
9049
9050 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9051
2996fca0
JK		 9052 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9053 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9054
cd232ad0
NHE		 9055 cpu = get_cpu();
9056 vmx->loaded_vmcs = vmcs02;
9057 vmx_vcpu_put(vcpu);
9058 vmx_vcpu_load(vcpu, cpu);
9059 vcpu->cpu = cpu;
9060 put_cpu();
9061
36c3cc42
JK		 9062 vmx_segment_cache_clear(vmx);
9063
cd232ad0
NHE		 9064 prepare_vmcs02(vcpu, vmcs12);
9065
ff651cb6
WV		 9066 msr_entry_idx = nested_vmx_load_msr(vcpu,
9067 vmcs12->vm_entry_msr_load_addr,
9068 vmcs12->vm_entry_msr_load_count);
9069 if (msr_entry_idx) {
9070 leave_guest_mode(vcpu);
9071 vmx_load_vmcs01(vcpu);
9072 nested_vmx_entry_failure(vcpu, vmcs12,
9073 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9074 return 1;
9075 }
9076
9077 vmcs12->launch_state = 1;
9078
6dfacadd
JK		 9079 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9080 return kvm_emulate_halt(vcpu);
9081
7af40ad3
JK		 9082 vmx->nested.nested_run_pending = 1;
9083
cd232ad0
NHE		 9084 /*
9085 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9086 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9087 * returned as far as L1 is concerned. It will only return (and set
9088 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9089 */
9090 return 1;
9091}
9092
4704d0be
NHE		 9093/*
9094 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9095 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9096 * This function returns the new value we should put in vmcs12.guest_cr0.
9097 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9098 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9099 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9100 * didn't trap the bit, because if L1 did, so would L0).
9101 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9102 * been modified by L2, and L1 knows it. So just leave the old value of
9103 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9104 * isn't relevant, because if L0 traps this bit it can set it to anything.
9105 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9106 * changed these bits, and therefore they need to be updated, but L0
9107 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9108 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9109 */
9110static inline unsigned long
9111vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9112{
9113 return
9114 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9115 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9116 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9117 vcpu->arch.cr0_guest_owned_bits));
9118}
9119
9120static inline unsigned long
9121vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9122{
9123 return
9124 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9125 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9126 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9127 vcpu->arch.cr4_guest_owned_bits));
9128}
9129
5f3d5799
JK		 9130static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9131 struct vmcs12 *vmcs12)
9132{
9133 u32 idt_vectoring;
9134 unsigned int nr;
9135
851eb667 9136 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9137 nr = vcpu->arch.exception.nr;
9138 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9139
9140 if (kvm_exception_is_soft(nr)) {
9141 vmcs12->vm_exit_instruction_len =
9142 vcpu->arch.event_exit_inst_len;
9143 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9144 } else
9145 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9146
9147 if (vcpu->arch.exception.has_error_code) {
9148 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9149 vmcs12->idt_vectoring_error_code =
9150 vcpu->arch.exception.error_code;
9151 }
9152
9153 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9154 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9155 vmcs12->idt_vectoring_info_field =
9156 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9157 } else if (vcpu->arch.interrupt.pending) {
9158 nr = vcpu->arch.interrupt.nr;
9159 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9160
9161 if (vcpu->arch.interrupt.soft) {
9162 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9163 vmcs12->vm_entry_instruction_len =
9164 vcpu->arch.event_exit_inst_len;
9165 } else
9166 idt_vectoring |= INTR_TYPE_EXT_INTR;
9167
9168 vmcs12->idt_vectoring_info_field = idt_vectoring;
9169 }
9170}
9171
b6b8a145
JK		 9172static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9173{
9174 struct vcpu_vmx *vmx = to_vmx(vcpu);
9175
f4124500
JK		 9176 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9177 vmx->nested.preemption_timer_expired) {
9178 if (vmx->nested.nested_run_pending)
9179 return -EBUSY;
9180 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9181 return 0;
9182 }
9183
b6b8a145 9184 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9185 if (vmx->nested.nested_run_pending ||
9186 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9187 return -EBUSY;
9188 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9189 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9190 INTR_INFO_VALID_MASK, 0);
9191 /*
9192 * The NMI-triggered VM exit counts as injection:
9193 * clear this one and block further NMIs.
9194 */
9195 vcpu->arch.nmi_pending = 0;
9196 vmx_set_nmi_mask(vcpu, true);
9197 return 0;
9198 }
9199
9200 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9201 nested_exit_on_intr(vcpu)) {
9202 if (vmx->nested.nested_run_pending)
9203 return -EBUSY;
9204 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9205 }
9206
9207 return 0;
9208}
9209
f4124500
JK		 9210static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9211{
9212 ktime_t remaining =
9213 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9214 u64 value;
9215
9216 if (ktime_to_ns(remaining) <= 0)
9217 return 0;
9218
9219 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9220 do_div(value, 1000000);
9221 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9222}
9223
4704d0be
NHE		 9224/*
9225 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9226 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9227 * and this function updates it to reflect the changes to the guest state while
9228 * L2 was running (and perhaps made some exits which were handled directly by L0
9229 * without going back to L1), and to reflect the exit reason.
9230 * Note that we do not have to copy here all VMCS fields, just those that
9231 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9232 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9233 * which already writes to vmcs12 directly.
9234 */
533558bc
JK		 9235static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9236 u32 exit_reason, u32 exit_intr_info,
9237 unsigned long exit_qualification)
4704d0be
NHE		 9238{
9239 /* update guest state fields: */
9240 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9241 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9242
4704d0be
NHE		 9243 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9244 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9245 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9246
9247 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9248 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9249 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9250 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9251 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9252 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9253 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9254 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9255 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9256 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9257 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9258 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9259 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9260 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9261 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9262 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9263 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9264 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9265 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9266 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9267 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9268 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9269 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9270 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9271 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9272 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9273 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9274 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9275 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9276 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9277 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9278 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9279 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9280 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9281 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9282 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9283
4704d0be
NHE		 9284 vmcs12->guest_interruptibility_info =
9285 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9286 vmcs12->guest_pending_dbg_exceptions =
9287 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9288 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9289 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9290 else
9291 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9292
f4124500
JK		 9293 if (nested_cpu_has_preemption_timer(vmcs12)) {
9294 if (vmcs12->vm_exit_controls &
9295 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9296 vmcs12->vmx_preemption_timer_value =
9297 vmx_get_preemption_timer_value(vcpu);
9298 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9299 }
7854cbca 9300
3633cfc3
NHE		 9301 /*
9302 * In some cases (usually, nested EPT), L2 is allowed to change its
9303 * own CR3 without exiting. If it has changed it, we must keep it.
9304 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9305 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9306 *
9307 * Additionally, restore L2's PDPTR to vmcs12.
9308 */
9309 if (enable_ept) {
9310 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9311 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9312 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9313 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9314 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9315 }
9316
c18911a2
JK		 9317 vmcs12->vm_entry_controls =
9318 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9319 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9320
2996fca0
JK		 9321 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9322 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9323 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9324 }
9325
4704d0be
NHE		 9326 /* TODO: These cannot have changed unless we have MSR bitmaps and
9327 * the relevant bit asks not to trap the change */
b8c07d55 9328 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9329 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9330 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9331 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9332 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9333 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9334 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9335 if (vmx_mpx_supported())
9336 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9337 if (nested_cpu_has_xsaves(vmcs12))
9338 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9339
9340 /* update exit information fields: */
9341
533558bc
JK		 9342 vmcs12->vm_exit_reason = exit_reason;
9343 vmcs12->exit_qualification = exit_qualification;
4704d0be 9344
533558bc 9345 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9346 if ((vmcs12->vm_exit_intr_info &
9347 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9348 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9349 vmcs12->vm_exit_intr_error_code =
9350 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9351 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9352 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9353 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9354
5f3d5799
JK		 9355 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9356 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9357 * instead of reading the real value. */
4704d0be 9358 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9359
9360 /*
9361 * Transfer the event that L0 or L1 may wanted to inject into
9362 * L2 to IDT_VECTORING_INFO_FIELD.
9363 */
9364 vmcs12_save_pending_event(vcpu, vmcs12);
9365 }
9366
9367 /*
9368 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9369 * preserved above and would only end up incorrectly in L1.
9370 */
9371 vcpu->arch.nmi_injected = false;
9372 kvm_clear_exception_queue(vcpu);
9373 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9374}
9375
9376/*
9377 * A part of what we need to when the nested L2 guest exits and we want to
9378 * run its L1 parent, is to reset L1's guest state to the host state specified
9379 * in vmcs12.
9380 * This function is to be called not only on normal nested exit, but also on
9381 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9382 * Failures During or After Loading Guest State").
9383 * This function should be called when the active VMCS is L1's (vmcs01).
9384 */
733568f9
JK		 9385static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9386 struct vmcs12 *vmcs12)
4704d0be 9387{
21feb4eb
ACL		 9388 struct kvm_segment seg;
9389
4704d0be
NHE		 9390 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9391 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9392 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9393 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9394 else
9395 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9396 vmx_set_efer(vcpu, vcpu->arch.efer);
9397
9398 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9399 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9400 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9401 /*
9402 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9403 * actually changed, because it depends on the current state of
9404 * fpu_active (which may have changed).
9405 * Note that vmx_set_cr0 refers to efer set above.
9406 */
9e3e4dbf 9407 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9408 /*
9409 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9410 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9411 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9412 */
9413 update_exception_bitmap(vcpu);
9414 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9415 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9416
9417 /*
9418 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9419 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9420 */
9421 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9422 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9423
29bf08f1 9424 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9425
4704d0be
NHE		 9426 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9427 kvm_mmu_reset_context(vcpu);
9428
feaf0c7d
GN		 9429 if (!enable_ept)
9430 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9431
4704d0be
NHE		 9432 if (enable_vpid) {
9433 /*
9434 * Trivially support vpid by letting L2s share their parent
9435 * L1's vpid. TODO: move to a more elaborate solution, giving
9436 * each L2 its own vpid and exposing the vpid feature to L1.
9437 */
9438 vmx_flush_tlb(vcpu);
9439 }
9440
9441
9442 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9443 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9444 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9445 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9446 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9447
36be0b9d
PB		 9448 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9449 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9450 vmcs_write64(GUEST_BNDCFGS, 0);
9451
44811c02 9452 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9453 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9454 vcpu->arch.pat = vmcs12->host_ia32_pat;
9455 }
4704d0be
NHE		 9456 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9457 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9458 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9459
21feb4eb
ACL		 9460 /* Set L1 segment info according to Intel SDM
9461 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9462 seg = (struct kvm_segment) {
9463 .base = 0,
9464 .limit = 0xFFFFFFFF,
9465 .selector = vmcs12->host_cs_selector,
9466 .type = 11,
9467 .present = 1,
9468 .s = 1,
9469 .g = 1
9470 };
9471 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9472 seg.l = 1;
9473 else
9474 seg.db = 1;
9475 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9476 seg = (struct kvm_segment) {
9477 .base = 0,
9478 .limit = 0xFFFFFFFF,
9479 .type = 3,
9480 .present = 1,
9481 .s = 1,
9482 .db = 1,
9483 .g = 1
9484 };
9485 seg.selector = vmcs12->host_ds_selector;
9486 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9487 seg.selector = vmcs12->host_es_selector;
9488 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9489 seg.selector = vmcs12->host_ss_selector;
9490 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9491 seg.selector = vmcs12->host_fs_selector;
9492 seg.base = vmcs12->host_fs_base;
9493 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9494 seg.selector = vmcs12->host_gs_selector;
9495 seg.base = vmcs12->host_gs_base;
9496 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9497 seg = (struct kvm_segment) {
205befd9 9498 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9499 .limit = 0x67,
9500 .selector = vmcs12->host_tr_selector,
9501 .type = 11,
9502 .present = 1
9503 };
9504 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9505
503cd0c5
JK		 9506 kvm_set_dr(vcpu, 7, 0x400);
9507 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6
WV		 9508
9509 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9510 vmcs12->vm_exit_msr_load_count))
9511 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9512}
9513
9514/*
9515 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9516 * and modify vmcs12 to make it see what it would expect to see there if
9517 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9518 */
533558bc
JK		 9519static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9520 u32 exit_intr_info,
9521 unsigned long exit_qualification)
4704d0be
NHE		 9522{
9523 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9524 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9525
5f3d5799
JK		 9526 /* trying to cancel vmlaunch/vmresume is a bug */
9527 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9528
4704d0be 9529 leave_guest_mode(vcpu);
533558bc
JK		 9530 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9531 exit_qualification);
4704d0be 9532
ff651cb6
WV		 9533 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9534 vmcs12->vm_exit_msr_store_count))
9535 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9536
f3380ca5
WL		 9537 vmx_load_vmcs01(vcpu);
9538
77b0f5d6
BD		 9539 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9540 && nested_exit_intr_ack_set(vcpu)) {
9541 int irq = kvm_cpu_get_interrupt(vcpu);
9542 WARN_ON(irq < 0);
9543 vmcs12->vm_exit_intr_info = irq |
9544 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9545 }
9546
542060ea
JK		 9547 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9548 vmcs12->exit_qualification,
9549 vmcs12->idt_vectoring_info_field,
9550 vmcs12->vm_exit_intr_info,
9551 vmcs12->vm_exit_intr_error_code,
9552 KVM_ISA_VMX);
4704d0be 9553
2961e876
GN		 9554 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9555 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9556 vmx_segment_cache_clear(vmx);
9557
4704d0be
NHE		 9558 /* if no vmcs02 cache requested, remove the one we used */
9559 if (VMCS02_POOL_SIZE == 0)
9560 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9561
9562 load_vmcs12_host_state(vcpu, vmcs12);
9563
27fc51b2 9564 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9565 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9566
9567 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9568 vmx->host_rsp = 0;
9569
9570 /* Unpin physical memory we referred to in vmcs02 */
9571 if (vmx->nested.apic_access_page) {
9572 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9573 vmx->nested.apic_access_page = NULL;
4704d0be 9574 }
a7c0b07d
WL		 9575 if (vmx->nested.virtual_apic_page) {
9576 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9577 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9578 }
4704d0be 9579
38b99173
TC		 9580 /*
9581 * We are now running in L2, mmu_notifier will force to reload the
9582 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9583 */
9584 kvm_vcpu_reload_apic_access_page(vcpu);
9585
4704d0be
NHE		 9586 /*
9587 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9588 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9589 * success or failure flag accordingly.
9590 */
9591 if (unlikely(vmx->fail)) {
9592 vmx->fail = 0;
9593 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9594 } else
9595 nested_vmx_succeed(vcpu);
012f83cb
AG		 9596 if (enable_shadow_vmcs)
9597 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9598
9599 /* in case we halted in L2 */
9600 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9601}
9602
42124925
JK		 9603/*
9604 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9605 */
9606static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9607{
9608 if (is_guest_mode(vcpu))
533558bc 9609 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9610 free_nested(to_vmx(vcpu));
9611}
9612
7c177938
NHE		 9613/*
9614 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9615 * 23.7 "VM-entry failures during or after loading guest state" (this also
9616 * lists the acceptable exit-reason and exit-qualification parameters).
9617 * It should only be called before L2 actually succeeded to run, and when
9618 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9619 */
9620static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9621 struct vmcs12 *vmcs12,
9622 u32 reason, unsigned long qualification)
9623{
9624 load_vmcs12_host_state(vcpu, vmcs12);
9625 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9626 vmcs12->exit_qualification = qualification;
9627 nested_vmx_succeed(vcpu);
012f83cb
AG		 9628 if (enable_shadow_vmcs)
9629 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9630}
9631
8a76d7f2
JR		 9632static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9633 struct x86_instruction_info *info,
9634 enum x86_intercept_stage stage)
9635{
9636 return X86EMUL_CONTINUE;
9637}
9638
48d89b92 9639static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9640{
b4a2d31d
RK		 9641 if (ple_gap)
9642 shrink_ple_window(vcpu);
ae97a3b8
RK		 9643}
9644
843e4330
KH		 9645static void vmx_slot_enable_log_dirty(struct kvm *kvm,
9646 struct kvm_memory_slot *slot)
9647{
9648 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
9649 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
9650}
9651
9652static void vmx_slot_disable_log_dirty(struct kvm *kvm,
9653 struct kvm_memory_slot *slot)
9654{
9655 kvm_mmu_slot_set_dirty(kvm, slot);
9656}
9657
9658static void vmx_flush_log_dirty(struct kvm *kvm)
9659{
9660 kvm_flush_pml_buffers(kvm);
9661}
9662
9663static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
9664 struct kvm_memory_slot *memslot,
9665 gfn_t offset, unsigned long mask)
9666{
9667 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
9668}
9669
cbdd1bea 9670static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9671 .cpu_has_kvm_support = cpu_has_kvm_support,
9672 .disabled_by_bios = vmx_disabled_by_bios,
9673 .hardware_setup = hardware_setup,
9674 .hardware_unsetup = hardware_unsetup,
002c7f7c 9675 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9676 .hardware_enable = hardware_enable,
9677 .hardware_disable = hardware_disable,
04547156 9678 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9679
9680 .vcpu_create = vmx_create_vcpu,
9681 .vcpu_free = vmx_free_vcpu,
04d2cc77 9682 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9683
04d2cc77 9684 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9685 .vcpu_load = vmx_vcpu_load,
9686 .vcpu_put = vmx_vcpu_put,
9687
c8639010 9688 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9689 .get_msr = vmx_get_msr,
9690 .set_msr = vmx_set_msr,
9691 .get_segment_base = vmx_get_segment_base,
9692 .get_segment = vmx_get_segment,
9693 .set_segment = vmx_set_segment,
2e4d2653 9694 .get_cpl = vmx_get_cpl,
6aa8b732 9695 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9696 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9697 .decache_cr3 = vmx_decache_cr3,
25c4c276 9698 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9699 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9700 .set_cr3 = vmx_set_cr3,
9701 .set_cr4 = vmx_set_cr4,
6aa8b732 9702 .set_efer = vmx_set_efer,
6aa8b732
AK		 9703 .get_idt = vmx_get_idt,
9704 .set_idt = vmx_set_idt,
9705 .get_gdt = vmx_get_gdt,
9706 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9707 .get_dr6 = vmx_get_dr6,
9708 .set_dr6 = vmx_set_dr6,
020df079 9709 .set_dr7 = vmx_set_dr7,
81908bf4 9710 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9711 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9712 .get_rflags = vmx_get_rflags,
9713 .set_rflags = vmx_set_rflags,
02daab21 9714 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9715
9716 .tlb_flush = vmx_flush_tlb,
6aa8b732 9717
6aa8b732 9718 .run = vmx_vcpu_run,
6062d012 9719 .handle_exit = vmx_handle_exit,
6aa8b732 9720 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9721 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9722 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9723 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9724 .set_irq = vmx_inject_irq,
95ba8273 9725 .set_nmi = vmx_inject_nmi,
298101da 9726 .queue_exception = vmx_queue_exception,
b463a6f7 9727 .cancel_injection = vmx_cancel_injection,
78646121 9728 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9729 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9730 .get_nmi_mask = vmx_get_nmi_mask,
9731 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9732 .enable_nmi_window = enable_nmi_window,
9733 .enable_irq_window = enable_irq_window,
9734 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9735 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9736 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9737 .vm_has_apicv = vmx_vm_has_apicv,
9738 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9739 .hwapic_irr_update = vmx_hwapic_irr_update,
9740 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9741 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9742 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9743
cbc94022 9744 .set_tss_addr = vmx_set_tss_addr,
67253af5 9745 .get_tdp_level = get_ept_level,
4b12f0de 9746 .get_mt_mask = vmx_get_mt_mask,
229456fc 9747
586f9607 9748 .get_exit_info = vmx_get_exit_info,
586f9607 9749
17cc3935 9750 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9751
9752 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9753
9754 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9755 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9756
9757 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9758
9759 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9760
4051b188 9761 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9762 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9763 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9764 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9765 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9766 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9767
9768 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9769
9770 .check_intercept = vmx_check_intercept,
a547c6db 9771 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9772 .mpx_supported = vmx_mpx_supported,
55412b2e 9773 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 9774
9775 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9776
9777 .sched_in = vmx_sched_in,
843e4330
KH		 9778
9779 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
9780 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
9781 .flush_log_dirty = vmx_flush_log_dirty,
9782 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 9783};
9784
9785static int __init vmx_init(void)
9786{
34a1cd60
TC		 9787 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9788 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9789 if (r)
34a1cd60 9790 return r;
25c5f225 9791
8f536b76
ZY		 9792#ifdef CONFIG_KEXEC
9793 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9794 crash_vmclear_local_loaded_vmcss);
9795#endif
9796
fdef3ad1 9797 return 0;
6aa8b732
AK		 9798}
9799
9800static void __exit vmx_exit(void)
9801{
8f536b76 9802#ifdef CONFIG_KEXEC
3b63a43f 9803 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9804 synchronize_rcu();
9805#endif
9806
cb498ea2 9807 kvm_exit();
6aa8b732
AK		 9808}
9809
9810module_init(vmx_init)
9811module_exit(vmx_exit)
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