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KVM: nVMX: Enable nested virtual interrupt delivery
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
20300099
WL		 102static u64 __read_mostly host_xss;
103
843e4330
KH		 104static bool __read_mostly enable_pml = 1;
105module_param_named(pml, enable_pml, bool, S_IRUGO);
106
5037878e
GN		 107#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
108#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 109#define KVM_VM_CR0_ALWAYS_ON \
110 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 111#define KVM_CR4_GUEST_OWNED_BITS \
112 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 113 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 114
cdc0e244
AK		 115#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
116#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
117
78ac8b47
AK		 118#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
119
f4124500
JK		 120#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
121
4b8d54f9
ZE		 122/*
123 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
124 * ple_gap: upper bound on the amount of time between two successive
125 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 126 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 127 * ple_window: upper bound on the amount of time a guest is allowed to execute
128 * in a PAUSE loop. Tests indicate that most spinlocks are held for
129 * less than 2^12 cycles
130 * Time is measured based on a counter that runs at the same rate as the TSC,
131 * refer SDM volume 3b section 21.6.13 & 22.1.3.
132 */
b4a2d31d
RK		 133#define KVM_VMX_DEFAULT_PLE_GAP 128
134#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
135#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
136#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
137#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
138 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
139
4b8d54f9
ZE		 140static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
141module_param(ple_gap, int, S_IRUGO);
142
143static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
144module_param(ple_window, int, S_IRUGO);
145
b4a2d31d
RK		 146/* Default doubles per-vcpu window every exit. */
147static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
148module_param(ple_window_grow, int, S_IRUGO);
149
150/* Default resets per-vcpu window every exit to ple_window. */
151static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
152module_param(ple_window_shrink, int, S_IRUGO);
153
154/* Default is to compute the maximum so we can never overflow. */
155static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
156static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157module_param(ple_window_max, int, S_IRUGO);
158
83287ea4
AK		 159extern const ulong vmx_return;
160
8bf00a52 161#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 162#define VMCS02_POOL_SIZE 1
61d2ef2c 163
a2fa3e9f
GH		 164struct vmcs {
165 u32 revision_id;
166 u32 abort;
167 char data[0];
168};
169
d462b819
NHE		 170/*
171 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
172 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
173 * loaded on this CPU (so we can clear them if the CPU goes down).
174 */
175struct loaded_vmcs {
176 struct vmcs *vmcs;
177 int cpu;
178 int launched;
179 struct list_head loaded_vmcss_on_cpu_link;
180};
181
26bb0981
AK		 182struct shared_msr_entry {
183 unsigned index;
184 u64 data;
d5696725 185 u64 mask;
26bb0981
AK		 186};
187
a9d30f33
NHE		 188/*
189 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
190 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
191 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
192 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
193 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
194 * More than one of these structures may exist, if L1 runs multiple L2 guests.
195 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
196 * underlying hardware which will be used to run L2.
197 * This structure is packed to ensure that its layout is identical across
198 * machines (necessary for live migration).
199 * If there are changes in this struct, VMCS12_REVISION must be changed.
200 */
22bd0358 201typedef u64 natural_width;
a9d30f33
NHE		 202struct __packed vmcs12 {
203 /* According to the Intel spec, a VMCS region must start with the
204 * following two fields. Then follow implementation-specific data.
205 */
206 u32 revision_id;
207 u32 abort;
22bd0358 208
27d6c865
NHE		 209 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
210 u32 padding[7]; /* room for future expansion */
211
22bd0358
NHE		 212 u64 io_bitmap_a;
213 u64 io_bitmap_b;
214 u64 msr_bitmap;
215 u64 vm_exit_msr_store_addr;
216 u64 vm_exit_msr_load_addr;
217 u64 vm_entry_msr_load_addr;
218 u64 tsc_offset;
219 u64 virtual_apic_page_addr;
220 u64 apic_access_addr;
221 u64 ept_pointer;
608406e2
WV		 222 u64 eoi_exit_bitmap0;
223 u64 eoi_exit_bitmap1;
224 u64 eoi_exit_bitmap2;
225 u64 eoi_exit_bitmap3;
81dc01f7 226 u64 xss_exit_bitmap;
22bd0358
NHE		 227 u64 guest_physical_address;
228 u64 vmcs_link_pointer;
229 u64 guest_ia32_debugctl;
230 u64 guest_ia32_pat;
231 u64 guest_ia32_efer;
232 u64 guest_ia32_perf_global_ctrl;
233 u64 guest_pdptr0;
234 u64 guest_pdptr1;
235 u64 guest_pdptr2;
236 u64 guest_pdptr3;
36be0b9d 237 u64 guest_bndcfgs;
22bd0358
NHE		 238 u64 host_ia32_pat;
239 u64 host_ia32_efer;
240 u64 host_ia32_perf_global_ctrl;
241 u64 padding64[8]; /* room for future expansion */
242 /*
243 * To allow migration of L1 (complete with its L2 guests) between
244 * machines of different natural widths (32 or 64 bit), we cannot have
245 * unsigned long fields with no explict size. We use u64 (aliased
246 * natural_width) instead. Luckily, x86 is little-endian.
247 */
248 natural_width cr0_guest_host_mask;
249 natural_width cr4_guest_host_mask;
250 natural_width cr0_read_shadow;
251 natural_width cr4_read_shadow;
252 natural_width cr3_target_value0;
253 natural_width cr3_target_value1;
254 natural_width cr3_target_value2;
255 natural_width cr3_target_value3;
256 natural_width exit_qualification;
257 natural_width guest_linear_address;
258 natural_width guest_cr0;
259 natural_width guest_cr3;
260 natural_width guest_cr4;
261 natural_width guest_es_base;
262 natural_width guest_cs_base;
263 natural_width guest_ss_base;
264 natural_width guest_ds_base;
265 natural_width guest_fs_base;
266 natural_width guest_gs_base;
267 natural_width guest_ldtr_base;
268 natural_width guest_tr_base;
269 natural_width guest_gdtr_base;
270 natural_width guest_idtr_base;
271 natural_width guest_dr7;
272 natural_width guest_rsp;
273 natural_width guest_rip;
274 natural_width guest_rflags;
275 natural_width guest_pending_dbg_exceptions;
276 natural_width guest_sysenter_esp;
277 natural_width guest_sysenter_eip;
278 natural_width host_cr0;
279 natural_width host_cr3;
280 natural_width host_cr4;
281 natural_width host_fs_base;
282 natural_width host_gs_base;
283 natural_width host_tr_base;
284 natural_width host_gdtr_base;
285 natural_width host_idtr_base;
286 natural_width host_ia32_sysenter_esp;
287 natural_width host_ia32_sysenter_eip;
288 natural_width host_rsp;
289 natural_width host_rip;
290 natural_width paddingl[8]; /* room for future expansion */
291 u32 pin_based_vm_exec_control;
292 u32 cpu_based_vm_exec_control;
293 u32 exception_bitmap;
294 u32 page_fault_error_code_mask;
295 u32 page_fault_error_code_match;
296 u32 cr3_target_count;
297 u32 vm_exit_controls;
298 u32 vm_exit_msr_store_count;
299 u32 vm_exit_msr_load_count;
300 u32 vm_entry_controls;
301 u32 vm_entry_msr_load_count;
302 u32 vm_entry_intr_info_field;
303 u32 vm_entry_exception_error_code;
304 u32 vm_entry_instruction_len;
305 u32 tpr_threshold;
306 u32 secondary_vm_exec_control;
307 u32 vm_instruction_error;
308 u32 vm_exit_reason;
309 u32 vm_exit_intr_info;
310 u32 vm_exit_intr_error_code;
311 u32 idt_vectoring_info_field;
312 u32 idt_vectoring_error_code;
313 u32 vm_exit_instruction_len;
314 u32 vmx_instruction_info;
315 u32 guest_es_limit;
316 u32 guest_cs_limit;
317 u32 guest_ss_limit;
318 u32 guest_ds_limit;
319 u32 guest_fs_limit;
320 u32 guest_gs_limit;
321 u32 guest_ldtr_limit;
322 u32 guest_tr_limit;
323 u32 guest_gdtr_limit;
324 u32 guest_idtr_limit;
325 u32 guest_es_ar_bytes;
326 u32 guest_cs_ar_bytes;
327 u32 guest_ss_ar_bytes;
328 u32 guest_ds_ar_bytes;
329 u32 guest_fs_ar_bytes;
330 u32 guest_gs_ar_bytes;
331 u32 guest_ldtr_ar_bytes;
332 u32 guest_tr_ar_bytes;
333 u32 guest_interruptibility_info;
334 u32 guest_activity_state;
335 u32 guest_sysenter_cs;
336 u32 host_ia32_sysenter_cs;
0238ea91
JK		 337 u32 vmx_preemption_timer_value;
338 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 339 u16 virtual_processor_id;
340 u16 guest_es_selector;
341 u16 guest_cs_selector;
342 u16 guest_ss_selector;
343 u16 guest_ds_selector;
344 u16 guest_fs_selector;
345 u16 guest_gs_selector;
346 u16 guest_ldtr_selector;
347 u16 guest_tr_selector;
608406e2 348 u16 guest_intr_status;
22bd0358
NHE		 349 u16 host_es_selector;
350 u16 host_cs_selector;
351 u16 host_ss_selector;
352 u16 host_ds_selector;
353 u16 host_fs_selector;
354 u16 host_gs_selector;
355 u16 host_tr_selector;
a9d30f33
NHE		 356};
357
358/*
359 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
360 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
361 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
362 */
363#define VMCS12_REVISION 0x11e57ed0
364
365/*
366 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
367 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
368 * current implementation, 4K are reserved to avoid future complications.
369 */
370#define VMCS12_SIZE 0x1000
371
ff2f6fe9
NHE		 372/* Used to remember the last vmcs02 used for some recently used vmcs12s */
373struct vmcs02_list {
374 struct list_head list;
375 gpa_t vmptr;
376 struct loaded_vmcs vmcs02;
377};
378
ec378aee
NHE		 379/*
380 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
381 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
382 */
383struct nested_vmx {
384 /* Has the level1 guest done vmxon? */
385 bool vmxon;
3573e22c 386 gpa_t vmxon_ptr;
a9d30f33
NHE		 387
388 /* The guest-physical address of the current VMCS L1 keeps for L2 */
389 gpa_t current_vmptr;
390 /* The host-usable pointer to the above */
391 struct page *current_vmcs12_page;
392 struct vmcs12 *current_vmcs12;
8de48833 393 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 394 /*
395 * Indicates if the shadow vmcs must be updated with the
396 * data hold by vmcs12
397 */
398 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 399
400 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
401 struct list_head vmcs02_pool;
402 int vmcs02_num;
fe3ef05c 403 u64 vmcs01_tsc_offset;
644d711a
NHE		 404 /* L2 must run next, and mustn't decide to exit to L1. */
405 bool nested_run_pending;
fe3ef05c
NHE		 406 /*
407 * Guest pages referred to in vmcs02 with host-physical pointers, so
408 * we must keep them pinned while L2 runs.
409 */
410 struct page *apic_access_page;
a7c0b07d 411 struct page *virtual_apic_page;
b3897a49 412 u64 msr_ia32_feature_control;
f4124500
JK		 413
414 struct hrtimer preemption_timer;
415 bool preemption_timer_expired;
2996fca0
JK		 416
417 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
418 u64 vmcs01_debugctl;
b9c237bb
WV		 419
420 u32 nested_vmx_procbased_ctls_low;
421 u32 nested_vmx_procbased_ctls_high;
422 u32 nested_vmx_true_procbased_ctls_low;
423 u32 nested_vmx_secondary_ctls_low;
424 u32 nested_vmx_secondary_ctls_high;
425 u32 nested_vmx_pinbased_ctls_low;
426 u32 nested_vmx_pinbased_ctls_high;
427 u32 nested_vmx_exit_ctls_low;
428 u32 nested_vmx_exit_ctls_high;
429 u32 nested_vmx_true_exit_ctls_low;
430 u32 nested_vmx_entry_ctls_low;
431 u32 nested_vmx_entry_ctls_high;
432 u32 nested_vmx_true_entry_ctls_low;
433 u32 nested_vmx_misc_low;
434 u32 nested_vmx_misc_high;
435 u32 nested_vmx_ept_caps;
ec378aee
NHE		 436};
437
01e439be
YZ		 438#define POSTED_INTR_ON 0
439/* Posted-Interrupt Descriptor */
440struct pi_desc {
441 u32 pir[8]; /* Posted interrupt requested */
442 u32 control; /* bit 0 of control is outstanding notification bit */
443 u32 rsvd[7];
444} __aligned(64);
445
a20ed54d
YZ		 446static bool pi_test_and_set_on(struct pi_desc *pi_desc)
447{
448 return test_and_set_bit(POSTED_INTR_ON,
449 (unsigned long *)&pi_desc->control);
450}
451
452static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
453{
454 return test_and_clear_bit(POSTED_INTR_ON,
455 (unsigned long *)&pi_desc->control);
456}
457
458static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
459{
460 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
461}
462
a2fa3e9f 463struct vcpu_vmx {
fb3f0f51 464 struct kvm_vcpu vcpu;
313dbd49 465 unsigned long host_rsp;
29bd8a78 466 u8 fail;
9d58b931 467 bool nmi_known_unmasked;
51aa01d1 468 u32 exit_intr_info;
1155f76a 469 u32 idt_vectoring_info;
6de12732 470 ulong rflags;
26bb0981 471 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 472 int nmsrs;
473 int save_nmsrs;
a547c6db 474 unsigned long host_idt_base;
a2fa3e9f 475#ifdef CONFIG_X86_64
44ea2b17
AK		 476 u64 msr_host_kernel_gs_base;
477 u64 msr_guest_kernel_gs_base;
a2fa3e9f 478#endif
2961e876
GN		 479 u32 vm_entry_controls_shadow;
480 u32 vm_exit_controls_shadow;
d462b819
NHE		 481 /*
482 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
483 * non-nested (L1) guest, it always points to vmcs01. For a nested
484 * guest (L2), it points to a different VMCS.
485 */
486 struct loaded_vmcs vmcs01;
487 struct loaded_vmcs *loaded_vmcs;
488 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 489 struct msr_autoload {
490 unsigned nr;
491 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
492 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
493 } msr_autoload;
a2fa3e9f
GH		 494 struct {
495 int loaded;
496 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 497#ifdef CONFIG_X86_64
498 u16 ds_sel, es_sel;
499#endif
152d3f2f
LV		 500 int gs_ldt_reload_needed;
501 int fs_reload_needed;
da8999d3 502 u64 msr_host_bndcfgs;
d974baa3 503 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 504 } host_state;
9c8cba37 505 struct {
7ffd92c5 506 int vm86_active;
78ac8b47 507 ulong save_rflags;
f5f7b2fe
AK		 508 struct kvm_segment segs[8];
509 } rmode;
510 struct {
511 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 512 struct kvm_save_segment {
513 u16 selector;
514 unsigned long base;
515 u32 limit;
516 u32 ar;
f5f7b2fe 517 } seg[8];
2fb92db1 518 } segment_cache;
2384d2b3 519 int vpid;
04fa4d32 520 bool emulation_required;
3b86cd99
JK		 521
522 /* Support for vnmi-less CPUs */
523 int soft_vnmi_blocked;
524 ktime_t entry_time;
525 s64 vnmi_blocked_time;
a0861c02 526 u32 exit_reason;
4e47c7a6
SY		 527
528 bool rdtscp_enabled;
ec378aee 529
01e439be
YZ		 530 /* Posted interrupt descriptor */
531 struct pi_desc pi_desc;
532
ec378aee
NHE		 533 /* Support for a guest hypervisor (nested VMX) */
534 struct nested_vmx nested;
a7653ecd
RK		 535
536 /* Dynamic PLE window. */
537 int ple_window;
538 bool ple_window_dirty;
843e4330
KH		 539
540 /* Support for PML */
541#define PML_ENTITY_NUM 512
542 struct page *pml_pg;
a2fa3e9f
GH		 543};
544
2fb92db1
AK		 545enum segment_cache_field {
546 SEG_FIELD_SEL = 0,
547 SEG_FIELD_BASE = 1,
548 SEG_FIELD_LIMIT = 2,
549 SEG_FIELD_AR = 3,
550
551 SEG_FIELD_NR = 4
552};
553
a2fa3e9f
GH		 554static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
555{
fb3f0f51 556 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 557}
558
22bd0358
NHE		 559#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
560#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
561#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
562 [number##_HIGH] = VMCS12_OFFSET(name)+4
563
4607c2d7 564
fe2b201b 565static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 566 /*
567 * We do NOT shadow fields that are modified when L0
568 * traps and emulates any vmx instruction (e.g. VMPTRLD,
569 * VMXON...) executed by L1.
570 * For example, VM_INSTRUCTION_ERROR is read
571 * by L1 if a vmx instruction fails (part of the error path).
572 * Note the code assumes this logic. If for some reason
573 * we start shadowing these fields then we need to
574 * force a shadow sync when L0 emulates vmx instructions
575 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
576 * by nested_vmx_failValid)
577 */
578 VM_EXIT_REASON,
579 VM_EXIT_INTR_INFO,
580 VM_EXIT_INSTRUCTION_LEN,
581 IDT_VECTORING_INFO_FIELD,
582 IDT_VECTORING_ERROR_CODE,
583 VM_EXIT_INTR_ERROR_CODE,
584 EXIT_QUALIFICATION,
585 GUEST_LINEAR_ADDRESS,
586 GUEST_PHYSICAL_ADDRESS
587};
fe2b201b 588static int max_shadow_read_only_fields =
4607c2d7
AG		 589 ARRAY_SIZE(shadow_read_only_fields);
590
fe2b201b 591static unsigned long shadow_read_write_fields[] = {
a7c0b07d 592 TPR_THRESHOLD,
4607c2d7
AG		 593 GUEST_RIP,
594 GUEST_RSP,
595 GUEST_CR0,
596 GUEST_CR3,
597 GUEST_CR4,
598 GUEST_INTERRUPTIBILITY_INFO,
599 GUEST_RFLAGS,
600 GUEST_CS_SELECTOR,
601 GUEST_CS_AR_BYTES,
602 GUEST_CS_LIMIT,
603 GUEST_CS_BASE,
604 GUEST_ES_BASE,
36be0b9d 605 GUEST_BNDCFGS,
4607c2d7
AG		 606 CR0_GUEST_HOST_MASK,
607 CR0_READ_SHADOW,
608 CR4_READ_SHADOW,
609 TSC_OFFSET,
610 EXCEPTION_BITMAP,
611 CPU_BASED_VM_EXEC_CONTROL,
612 VM_ENTRY_EXCEPTION_ERROR_CODE,
613 VM_ENTRY_INTR_INFO_FIELD,
614 VM_ENTRY_INSTRUCTION_LEN,
615 VM_ENTRY_EXCEPTION_ERROR_CODE,
616 HOST_FS_BASE,
617 HOST_GS_BASE,
618 HOST_FS_SELECTOR,
619 HOST_GS_SELECTOR
620};
fe2b201b 621static int max_shadow_read_write_fields =
4607c2d7
AG		 622 ARRAY_SIZE(shadow_read_write_fields);
623
772e0318 624static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 625 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
626 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
627 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
628 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
629 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
630 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
631 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
632 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
633 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 634 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 635 FIELD(HOST_ES_SELECTOR, host_es_selector),
636 FIELD(HOST_CS_SELECTOR, host_cs_selector),
637 FIELD(HOST_SS_SELECTOR, host_ss_selector),
638 FIELD(HOST_DS_SELECTOR, host_ds_selector),
639 FIELD(HOST_FS_SELECTOR, host_fs_selector),
640 FIELD(HOST_GS_SELECTOR, host_gs_selector),
641 FIELD(HOST_TR_SELECTOR, host_tr_selector),
642 FIELD64(IO_BITMAP_A, io_bitmap_a),
643 FIELD64(IO_BITMAP_B, io_bitmap_b),
644 FIELD64(MSR_BITMAP, msr_bitmap),
645 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
646 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
647 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
648 FIELD64(TSC_OFFSET, tsc_offset),
649 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
650 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
651 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 652 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
653 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
654 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
655 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 656 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 657 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
658 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
659 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
660 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
661 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
662 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
663 FIELD64(GUEST_PDPTR0, guest_pdptr0),
664 FIELD64(GUEST_PDPTR1, guest_pdptr1),
665 FIELD64(GUEST_PDPTR2, guest_pdptr2),
666 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 667 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 668 FIELD64(HOST_IA32_PAT, host_ia32_pat),
669 FIELD64(HOST_IA32_EFER, host_ia32_efer),
670 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
671 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
672 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
673 FIELD(EXCEPTION_BITMAP, exception_bitmap),
674 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
675 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
676 FIELD(CR3_TARGET_COUNT, cr3_target_count),
677 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
678 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
679 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
680 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
681 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
682 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
683 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
684 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
685 FIELD(TPR_THRESHOLD, tpr_threshold),
686 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
687 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
688 FIELD(VM_EXIT_REASON, vm_exit_reason),
689 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
690 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
691 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
692 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
693 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
694 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
695 FIELD(GUEST_ES_LIMIT, guest_es_limit),
696 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
697 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
698 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
699 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
700 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
701 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
702 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
703 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
704 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
705 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
706 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
707 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
708 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
709 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
710 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
711 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
712 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
713 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
714 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
715 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
716 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 717 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 718 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
719 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
720 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
721 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
722 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
723 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
724 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
725 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
726 FIELD(EXIT_QUALIFICATION, exit_qualification),
727 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
728 FIELD(GUEST_CR0, guest_cr0),
729 FIELD(GUEST_CR3, guest_cr3),
730 FIELD(GUEST_CR4, guest_cr4),
731 FIELD(GUEST_ES_BASE, guest_es_base),
732 FIELD(GUEST_CS_BASE, guest_cs_base),
733 FIELD(GUEST_SS_BASE, guest_ss_base),
734 FIELD(GUEST_DS_BASE, guest_ds_base),
735 FIELD(GUEST_FS_BASE, guest_fs_base),
736 FIELD(GUEST_GS_BASE, guest_gs_base),
737 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
738 FIELD(GUEST_TR_BASE, guest_tr_base),
739 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
740 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
741 FIELD(GUEST_DR7, guest_dr7),
742 FIELD(GUEST_RSP, guest_rsp),
743 FIELD(GUEST_RIP, guest_rip),
744 FIELD(GUEST_RFLAGS, guest_rflags),
745 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
746 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
747 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
748 FIELD(HOST_CR0, host_cr0),
749 FIELD(HOST_CR3, host_cr3),
750 FIELD(HOST_CR4, host_cr4),
751 FIELD(HOST_FS_BASE, host_fs_base),
752 FIELD(HOST_GS_BASE, host_gs_base),
753 FIELD(HOST_TR_BASE, host_tr_base),
754 FIELD(HOST_GDTR_BASE, host_gdtr_base),
755 FIELD(HOST_IDTR_BASE, host_idtr_base),
756 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
757 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
758 FIELD(HOST_RSP, host_rsp),
759 FIELD(HOST_RIP, host_rip),
760};
22bd0358
NHE		 761
762static inline short vmcs_field_to_offset(unsigned long field)
763{
a2ae9df7
PB		 764 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
765
766 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
767 vmcs_field_to_offset_table[field] == 0)
768 return -ENOENT;
769
22bd0358
NHE		 770 return vmcs_field_to_offset_table[field];
771}
772
a9d30f33
NHE		 773static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
774{
775 return to_vmx(vcpu)->nested.current_vmcs12;
776}
777
778static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
779{
780 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 781 if (is_error_page(page))
a9d30f33 782 return NULL;
32cad84f 783
a9d30f33
NHE		 784 return page;
785}
786
787static void nested_release_page(struct page *page)
788{
789 kvm_release_page_dirty(page);
790}
791
792static void nested_release_page_clean(struct page *page)
793{
794 kvm_release_page_clean(page);
795}
796
bfd0a56b 797static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 798static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 799static void kvm_cpu_vmxon(u64 addr);
800static void kvm_cpu_vmxoff(void);
93c4adc7 801static bool vmx_mpx_supported(void);
f53cd63c 802static bool vmx_xsaves_supported(void);
776e58ea 803static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 804static void vmx_set_segment(struct kvm_vcpu *vcpu,
805 struct kvm_segment *var, int seg);
806static void vmx_get_segment(struct kvm_vcpu *vcpu,
807 struct kvm_segment *var, int seg);
d99e4152
GN		 808static bool guest_state_valid(struct kvm_vcpu *vcpu);
809static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 810static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 811static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 812static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 813static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 814
6aa8b732
AK		 815static DEFINE_PER_CPU(struct vmcs *, vmxarea);
816static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 817/*
818 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
819 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
820 */
821static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 822static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 823
3e7c73e9
AK		 824static unsigned long *vmx_io_bitmap_a;
825static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 826static unsigned long *vmx_msr_bitmap_legacy;
827static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 828static unsigned long *vmx_msr_bitmap_legacy_x2apic;
829static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 830static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 831static unsigned long *vmx_vmread_bitmap;
832static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 833
110312c8 834static bool cpu_has_load_ia32_efer;
8bf00a52 835static bool cpu_has_load_perf_global_ctrl;
110312c8 836
2384d2b3
SY		 837static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
838static DEFINE_SPINLOCK(vmx_vpid_lock);
839
1c3d14fe 840static struct vmcs_config {
6aa8b732
AK		 841 int size;
842 int order;
843 u32 revision_id;
1c3d14fe
YS		 844 u32 pin_based_exec_ctrl;
845 u32 cpu_based_exec_ctrl;
f78e0e2e 846 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 847 u32 vmexit_ctrl;
848 u32 vmentry_ctrl;
849} vmcs_config;
6aa8b732 850
efff9e53 851static struct vmx_capability {
d56f546d
SY		 852 u32 ept;
853 u32 vpid;
854} vmx_capability;
855
6aa8b732
AK		 856#define VMX_SEGMENT_FIELD(seg) \
857 [VCPU_SREG_##seg] = { \
858 .selector = GUEST_##seg##_SELECTOR, \
859 .base = GUEST_##seg##_BASE, \
860 .limit = GUEST_##seg##_LIMIT, \
861 .ar_bytes = GUEST_##seg##_AR_BYTES, \
862 }
863
772e0318 864static const struct kvm_vmx_segment_field {
6aa8b732
AK		 865 unsigned selector;
866 unsigned base;
867 unsigned limit;
868 unsigned ar_bytes;
869} kvm_vmx_segment_fields[] = {
870 VMX_SEGMENT_FIELD(CS),
871 VMX_SEGMENT_FIELD(DS),
872 VMX_SEGMENT_FIELD(ES),
873 VMX_SEGMENT_FIELD(FS),
874 VMX_SEGMENT_FIELD(GS),
875 VMX_SEGMENT_FIELD(SS),
876 VMX_SEGMENT_FIELD(TR),
877 VMX_SEGMENT_FIELD(LDTR),
878};
879
26bb0981
AK		 880static u64 host_efer;
881
6de4f3ad
AK		 882static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
883
4d56c8a7 884/*
8c06585d 885 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 886 * away by decrementing the array size.
887 */
6aa8b732 888static const u32 vmx_msr_index[] = {
05b3e0c2 889#ifdef CONFIG_X86_64
44ea2b17 890 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 891#endif
8c06585d 892 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 893};
6aa8b732 894
31299944 895static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 896{
897 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
898 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 899 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 900}
901
31299944 902static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 903{
904 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
905 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 906 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 907}
908
31299944 909static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 910{
911 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
912 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 913 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 914}
915
31299944 916static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 917{
918 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
919 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
920}
921
31299944 922static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 923{
924 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
925 INTR_INFO_VALID_MASK)) ==
926 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
927}
928
31299944 929static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 930{
04547156 931 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 932}
933
31299944 934static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 935{
04547156 936 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 937}
938
31299944 939static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 940{
04547156 941 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 942}
943
31299944 944static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 945{
04547156
SY		 946 return vmcs_config.cpu_based_exec_ctrl &
947 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 948}
949
774ead3a 950static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 951{
04547156
SY		 952 return vmcs_config.cpu_based_2nd_exec_ctrl &
953 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
954}
955
8d14695f
YZ		 956static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
957{
958 return vmcs_config.cpu_based_2nd_exec_ctrl &
959 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
960}
961
83d4c286
YZ		 962static inline bool cpu_has_vmx_apic_register_virt(void)
963{
964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_APIC_REGISTER_VIRT;
966}
967
c7c9c56c
YZ		 968static inline bool cpu_has_vmx_virtual_intr_delivery(void)
969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
972}
973
01e439be
YZ		 974static inline bool cpu_has_vmx_posted_intr(void)
975{
976 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
977}
978
979static inline bool cpu_has_vmx_apicv(void)
980{
981 return cpu_has_vmx_apic_register_virt() &&
982 cpu_has_vmx_virtual_intr_delivery() &&
983 cpu_has_vmx_posted_intr();
984}
985
04547156
SY		 986static inline bool cpu_has_vmx_flexpriority(void)
987{
988 return cpu_has_vmx_tpr_shadow() &&
989 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 990}
991
e799794e
MT		 992static inline bool cpu_has_vmx_ept_execute_only(void)
993{
31299944 994 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 995}
996
e799794e
MT		 997static inline bool cpu_has_vmx_ept_2m_page(void)
998{
31299944 999 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1000}
1001
878403b7
SY		 1002static inline bool cpu_has_vmx_ept_1g_page(void)
1003{
31299944 1004 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1005}
1006
4bc9b982
SY		 1007static inline bool cpu_has_vmx_ept_4levels(void)
1008{
1009 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1010}
1011
83c3a331
XH		 1012static inline bool cpu_has_vmx_ept_ad_bits(void)
1013{
1014 return vmx_capability.ept & VMX_EPT_AD_BIT;
1015}
1016
31299944 1017static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1018{
31299944 1019 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1020}
1021
31299944 1022static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1023{
31299944 1024 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1025}
1026
518c8aee
GJ		 1027static inline bool cpu_has_vmx_invvpid_single(void)
1028{
1029 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1030}
1031
b9d762fa
GJ		 1032static inline bool cpu_has_vmx_invvpid_global(void)
1033{
1034 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1035}
1036
31299944 1037static inline bool cpu_has_vmx_ept(void)
d56f546d 1038{
04547156
SY		 1039 return vmcs_config.cpu_based_2nd_exec_ctrl &
1040 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1041}
1042
31299944 1043static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1044{
1045 return vmcs_config.cpu_based_2nd_exec_ctrl &
1046 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1047}
1048
31299944 1049static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1050{
1051 return vmcs_config.cpu_based_2nd_exec_ctrl &
1052 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1053}
1054
31299944 1055static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1056{
6d3e435e 1057 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1058}
1059
31299944 1060static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1061{
04547156
SY		 1062 return vmcs_config.cpu_based_2nd_exec_ctrl &
1063 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1064}
1065
31299944 1066static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1067{
1068 return vmcs_config.cpu_based_2nd_exec_ctrl &
1069 SECONDARY_EXEC_RDTSCP;
1070}
1071
ad756a16
MJ		 1072static inline bool cpu_has_vmx_invpcid(void)
1073{
1074 return vmcs_config.cpu_based_2nd_exec_ctrl &
1075 SECONDARY_EXEC_ENABLE_INVPCID;
1076}
1077
31299944 1078static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1079{
1080 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1081}
1082
f5f48ee1
SY		 1083static inline bool cpu_has_vmx_wbinvd_exit(void)
1084{
1085 return vmcs_config.cpu_based_2nd_exec_ctrl &
1086 SECONDARY_EXEC_WBINVD_EXITING;
1087}
1088
abc4fc58
AG		 1089static inline bool cpu_has_vmx_shadow_vmcs(void)
1090{
1091 u64 vmx_msr;
1092 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1093 /* check if the cpu supports writing r/o exit information fields */
1094 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1095 return false;
1096
1097 return vmcs_config.cpu_based_2nd_exec_ctrl &
1098 SECONDARY_EXEC_SHADOW_VMCS;
1099}
1100
843e4330
KH		 1101static inline bool cpu_has_vmx_pml(void)
1102{
1103 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1104}
1105
04547156
SY		 1106static inline bool report_flexpriority(void)
1107{
1108 return flexpriority_enabled;
1109}
1110
fe3ef05c
NHE		 1111static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1112{
1113 return vmcs12->cpu_based_vm_exec_control & bit;
1114}
1115
1116static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1117{
1118 return (vmcs12->cpu_based_vm_exec_control &
1119 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1120 (vmcs12->secondary_vm_exec_control & bit);
1121}
1122
f5c4368f 1123static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1124{
1125 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1126}
1127
f4124500
JK		 1128static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1129{
1130 return vmcs12->pin_based_vm_exec_control &
1131 PIN_BASED_VMX_PREEMPTION_TIMER;
1132}
1133
155a97a3
NHE		 1134static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1135{
1136 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1137}
1138
81dc01f7
WL		 1139static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1140{
1141 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1142 vmx_xsaves_supported();
1143}
1144
f2b93280
WV		 1145static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1146{
1147 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1148}
1149
82f0dd4b
WV		 1150static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1151{
1152 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1153}
1154
608406e2
WV		 1155static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1156{
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1158}
1159
644d711a
NHE		 1160static inline bool is_exception(u32 intr_info)
1161{
1162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1163 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1164}
1165
533558bc
JK		 1166static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1167 u32 exit_intr_info,
1168 unsigned long exit_qualification);
7c177938
NHE		 1169static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1170 struct vmcs12 *vmcs12,
1171 u32 reason, unsigned long qualification);
1172
8b9cf98c 1173static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1174{
1175 int i;
1176
a2fa3e9f 1177 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1178 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1179 return i;
1180 return -1;
1181}
1182
2384d2b3
SY		 1183static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1184{
1185 struct {
1186 u64 vpid : 16;
1187 u64 rsvd : 48;
1188 u64 gva;
1189 } operand = { vpid, 0, gva };
1190
4ecac3fd 1191 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1192 /* CF==1 or ZF==1 --> rc = -1 */
1193 "; ja 1f ; ud2 ; 1:"
1194 : : "a"(&operand), "c"(ext) : "cc", "memory");
1195}
1196
1439442c
SY		 1197static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1198{
1199 struct {
1200 u64 eptp, gpa;
1201 } operand = {eptp, gpa};
1202
4ecac3fd 1203 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1204 /* CF==1 or ZF==1 --> rc = -1 */
1205 "; ja 1f ; ud2 ; 1:\n"
1206 : : "a" (&operand), "c" (ext) : "cc", "memory");
1207}
1208
26bb0981 1209static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1210{
1211 int i;
1212
8b9cf98c 1213 i = __find_msr_index(vmx, msr);
a75beee6 1214 if (i >= 0)
a2fa3e9f 1215 return &vmx->guest_msrs[i];
8b6d44c7 1216 return NULL;
7725f0ba
AK		 1217}
1218
6aa8b732
AK		 1219static void vmcs_clear(struct vmcs *vmcs)
1220{
1221 u64 phys_addr = __pa(vmcs);
1222 u8 error;
1223
4ecac3fd 1224 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1225 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1226 : "cc", "memory");
1227 if (error)
1228 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1229 vmcs, phys_addr);
1230}
1231
d462b819
NHE		 1232static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1233{
1234 vmcs_clear(loaded_vmcs->vmcs);
1235 loaded_vmcs->cpu = -1;
1236 loaded_vmcs->launched = 0;
1237}
1238
7725b894
DX		 1239static void vmcs_load(struct vmcs *vmcs)
1240{
1241 u64 phys_addr = __pa(vmcs);
1242 u8 error;
1243
1244 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1245 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1246 : "cc", "memory");
1247 if (error)
2844d849 1248 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1249 vmcs, phys_addr);
1250}
1251
8f536b76
ZY		 1252#ifdef CONFIG_KEXEC
1253/*
1254 * This bitmap is used to indicate whether the vmclear
1255 * operation is enabled on all cpus. All disabled by
1256 * default.
1257 */
1258static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1259
1260static inline void crash_enable_local_vmclear(int cpu)
1261{
1262 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1263}
1264
1265static inline void crash_disable_local_vmclear(int cpu)
1266{
1267 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1268}
1269
1270static inline int crash_local_vmclear_enabled(int cpu)
1271{
1272 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1273}
1274
1275static void crash_vmclear_local_loaded_vmcss(void)
1276{
1277 int cpu = raw_smp_processor_id();
1278 struct loaded_vmcs *v;
1279
1280 if (!crash_local_vmclear_enabled(cpu))
1281 return;
1282
1283 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1284 loaded_vmcss_on_cpu_link)
1285 vmcs_clear(v->vmcs);
1286}
1287#else
1288static inline void crash_enable_local_vmclear(int cpu) { }
1289static inline void crash_disable_local_vmclear(int cpu) { }
1290#endif /* CONFIG_KEXEC */
1291
d462b819 1292static void __loaded_vmcs_clear(void *arg)
6aa8b732 1293{
d462b819 1294 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1295 int cpu = raw_smp_processor_id();
6aa8b732 1296
d462b819
NHE		 1297 if (loaded_vmcs->cpu != cpu)
1298 return; /* vcpu migration can race with cpu offline */
1299 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1300 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1301 crash_disable_local_vmclear(cpu);
d462b819 1302 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1303
1304 /*
1305 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1306 * is before setting loaded_vmcs->vcpu to -1 which is done in
1307 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1308 * then adds the vmcs into percpu list before it is deleted.
1309 */
1310 smp_wmb();
1311
d462b819 1312 loaded_vmcs_init(loaded_vmcs);
8f536b76 1313 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1314}
1315
d462b819 1316static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1317{
e6c7d321
XG		 1318 int cpu = loaded_vmcs->cpu;
1319
1320 if (cpu != -1)
1321 smp_call_function_single(cpu,
1322 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1323}
1324
1760dd49 1325static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1326{
1327 if (vmx->vpid == 0)
1328 return;
1329
518c8aee
GJ		 1330 if (cpu_has_vmx_invvpid_single())
1331 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1332}
1333
b9d762fa
GJ		 1334static inline void vpid_sync_vcpu_global(void)
1335{
1336 if (cpu_has_vmx_invvpid_global())
1337 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1338}
1339
1340static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1341{
1342 if (cpu_has_vmx_invvpid_single())
1760dd49 1343 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1344 else
1345 vpid_sync_vcpu_global();
1346}
1347
1439442c
SY		 1348static inline void ept_sync_global(void)
1349{
1350 if (cpu_has_vmx_invept_global())
1351 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1352}
1353
1354static inline void ept_sync_context(u64 eptp)
1355{
089d034e 1356 if (enable_ept) {
1439442c
SY		 1357 if (cpu_has_vmx_invept_context())
1358 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1359 else
1360 ept_sync_global();
1361 }
1362}
1363
96304217 1364static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1365{
5e520e62 1366 unsigned long value;
6aa8b732 1367
5e520e62
AK		 1368 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1369 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1370 return value;
1371}
1372
96304217 1373static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1374{
1375 return vmcs_readl(field);
1376}
1377
96304217 1378static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1379{
1380 return vmcs_readl(field);
1381}
1382
96304217 1383static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1384{
05b3e0c2 1385#ifdef CONFIG_X86_64
6aa8b732
AK		 1386 return vmcs_readl(field);
1387#else
1388 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1389#endif
1390}
1391
e52de1b8
AK		 1392static noinline void vmwrite_error(unsigned long field, unsigned long value)
1393{
1394 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1395 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1396 dump_stack();
1397}
1398
6aa8b732
AK		 1399static void vmcs_writel(unsigned long field, unsigned long value)
1400{
1401 u8 error;
1402
4ecac3fd 1403 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1404 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1405 if (unlikely(error))
1406 vmwrite_error(field, value);
6aa8b732
AK		 1407}
1408
1409static void vmcs_write16(unsigned long field, u16 value)
1410{
1411 vmcs_writel(field, value);
1412}
1413
1414static void vmcs_write32(unsigned long field, u32 value)
1415{
1416 vmcs_writel(field, value);
1417}
1418
1419static void vmcs_write64(unsigned long field, u64 value)
1420{
6aa8b732 1421 vmcs_writel(field, value);
7682f2d0 1422#ifndef CONFIG_X86_64
6aa8b732
AK		 1423 asm volatile ("");
1424 vmcs_writel(field+1, value >> 32);
1425#endif
1426}
1427
2ab455cc
AL		 1428static void vmcs_clear_bits(unsigned long field, u32 mask)
1429{
1430 vmcs_writel(field, vmcs_readl(field) & ~mask);
1431}
1432
1433static void vmcs_set_bits(unsigned long field, u32 mask)
1434{
1435 vmcs_writel(field, vmcs_readl(field) | mask);
1436}
1437
2961e876
GN		 1438static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1439{
1440 vmcs_write32(VM_ENTRY_CONTROLS, val);
1441 vmx->vm_entry_controls_shadow = val;
1442}
1443
1444static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1445{
1446 if (vmx->vm_entry_controls_shadow != val)
1447 vm_entry_controls_init(vmx, val);
1448}
1449
1450static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1451{
1452 return vmx->vm_entry_controls_shadow;
1453}
1454
1455
1456static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1457{
1458 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1459}
1460
1461static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1462{
1463 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1464}
1465
1466static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1467{
1468 vmcs_write32(VM_EXIT_CONTROLS, val);
1469 vmx->vm_exit_controls_shadow = val;
1470}
1471
1472static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1473{
1474 if (vmx->vm_exit_controls_shadow != val)
1475 vm_exit_controls_init(vmx, val);
1476}
1477
1478static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1479{
1480 return vmx->vm_exit_controls_shadow;
1481}
1482
1483
1484static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1485{
1486 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1487}
1488
1489static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1490{
1491 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1492}
1493
2fb92db1
AK		 1494static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1495{
1496 vmx->segment_cache.bitmask = 0;
1497}
1498
1499static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1500 unsigned field)
1501{
1502 bool ret;
1503 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1504
1505 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1506 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1507 vmx->segment_cache.bitmask = 0;
1508 }
1509 ret = vmx->segment_cache.bitmask & mask;
1510 vmx->segment_cache.bitmask |= mask;
1511 return ret;
1512}
1513
1514static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1515{
1516 u16 *p = &vmx->segment_cache.seg[seg].selector;
1517
1518 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1519 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1520 return *p;
1521}
1522
1523static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1524{
1525 ulong *p = &vmx->segment_cache.seg[seg].base;
1526
1527 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1528 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1529 return *p;
1530}
1531
1532static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1533{
1534 u32 *p = &vmx->segment_cache.seg[seg].limit;
1535
1536 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1537 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1538 return *p;
1539}
1540
1541static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1542{
1543 u32 *p = &vmx->segment_cache.seg[seg].ar;
1544
1545 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1546 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1547 return *p;
1548}
1549
abd3f2d6
AK		 1550static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1551{
1552 u32 eb;
1553
fd7373cc
JK		 1554 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1555 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1556 if ((vcpu->guest_debug &
1557 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1558 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1559 eb |= 1u << BP_VECTOR;
7ffd92c5 1560 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1561 eb = ~0;
089d034e 1562 if (enable_ept)
1439442c 1563 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1564 if (vcpu->fpu_active)
1565 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1566
1567 /* When we are running a nested L2 guest and L1 specified for it a
1568 * certain exception bitmap, we must trap the same exceptions and pass
1569 * them to L1. When running L2, we will only handle the exceptions
1570 * specified above if L1 did not want them.
1571 */
1572 if (is_guest_mode(vcpu))
1573 eb |= get_vmcs12(vcpu)->exception_bitmap;
1574
abd3f2d6
AK		 1575 vmcs_write32(EXCEPTION_BITMAP, eb);
1576}
1577
2961e876
GN		 1578static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1579 unsigned long entry, unsigned long exit)
8bf00a52 1580{
2961e876
GN		 1581 vm_entry_controls_clearbit(vmx, entry);
1582 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1583}
1584
61d2ef2c
AK		 1585static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1586{
1587 unsigned i;
1588 struct msr_autoload *m = &vmx->msr_autoload;
1589
8bf00a52
GN		 1590 switch (msr) {
1591 case MSR_EFER:
1592 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1593 clear_atomic_switch_msr_special(vmx,
1594 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1595 VM_EXIT_LOAD_IA32_EFER);
1596 return;
1597 }
1598 break;
1599 case MSR_CORE_PERF_GLOBAL_CTRL:
1600 if (cpu_has_load_perf_global_ctrl) {
2961e876 1601 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1602 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1603 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1604 return;
1605 }
1606 break;
110312c8
AK		 1607 }
1608
61d2ef2c
AK		 1609 for (i = 0; i < m->nr; ++i)
1610 if (m->guest[i].index == msr)
1611 break;
1612
1613 if (i == m->nr)
1614 return;
1615 --m->nr;
1616 m->guest[i] = m->guest[m->nr];
1617 m->host[i] = m->host[m->nr];
1618 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1619 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1620}
1621
2961e876
GN		 1622static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1623 unsigned long entry, unsigned long exit,
1624 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1625 u64 guest_val, u64 host_val)
8bf00a52
GN		 1626{
1627 vmcs_write64(guest_val_vmcs, guest_val);
1628 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1629 vm_entry_controls_setbit(vmx, entry);
1630 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1631}
1632
61d2ef2c
AK		 1633static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1634 u64 guest_val, u64 host_val)
1635{
1636 unsigned i;
1637 struct msr_autoload *m = &vmx->msr_autoload;
1638
8bf00a52
GN		 1639 switch (msr) {
1640 case MSR_EFER:
1641 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1642 add_atomic_switch_msr_special(vmx,
1643 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1644 VM_EXIT_LOAD_IA32_EFER,
1645 GUEST_IA32_EFER,
1646 HOST_IA32_EFER,
1647 guest_val, host_val);
1648 return;
1649 }
1650 break;
1651 case MSR_CORE_PERF_GLOBAL_CTRL:
1652 if (cpu_has_load_perf_global_ctrl) {
2961e876 1653 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1654 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1655 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1656 GUEST_IA32_PERF_GLOBAL_CTRL,
1657 HOST_IA32_PERF_GLOBAL_CTRL,
1658 guest_val, host_val);
1659 return;
1660 }
1661 break;
110312c8
AK		 1662 }
1663
61d2ef2c
AK		 1664 for (i = 0; i < m->nr; ++i)
1665 if (m->guest[i].index == msr)
1666 break;
1667
e7fc6f93 1668 if (i == NR_AUTOLOAD_MSRS) {
60266204 1669 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1670 "Can't add msr %x\n", msr);
1671 return;
1672 } else if (i == m->nr) {
61d2ef2c
AK		 1673 ++m->nr;
1674 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1675 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1676 }
1677
1678 m->guest[i].index = msr;
1679 m->guest[i].value = guest_val;
1680 m->host[i].index = msr;
1681 m->host[i].value = host_val;
1682}
1683
33ed6329
AK		 1684static void reload_tss(void)
1685{
33ed6329
AK		 1686 /*
1687 * VT restores TR but not its size. Useless.
1688 */
89cbc767 1689 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1690 struct desc_struct *descs;
33ed6329 1691
d359192f 1692 descs = (void *)gdt->address;
33ed6329
AK		 1693 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1694 load_TR_desc();
33ed6329
AK		 1695}
1696
92c0d900 1697static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1698{
3a34a881 1699 u64 guest_efer;
51c6cf66
AK		 1700 u64 ignore_bits;
1701
f6801dff 1702 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1703
51c6cf66 1704 /*
0fa06071 1705 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1706 * outside long mode
1707 */
1708 ignore_bits = EFER_NX | EFER_SCE;
1709#ifdef CONFIG_X86_64
1710 ignore_bits |= EFER_LMA | EFER_LME;
1711 /* SCE is meaningful only in long mode on Intel */
1712 if (guest_efer & EFER_LMA)
1713 ignore_bits &= ~(u64)EFER_SCE;
1714#endif
51c6cf66
AK		 1715 guest_efer &= ~ignore_bits;
1716 guest_efer |= host_efer & ignore_bits;
26bb0981 1717 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1718 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1719
1720 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1721
1722 /*
1723 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1724 * On CPUs that support "load IA32_EFER", always switch EFER
1725 * atomically, since it's faster than switching it manually.
1726 */
1727 if (cpu_has_load_ia32_efer ||
1728 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1729 guest_efer = vmx->vcpu.arch.efer;
1730 if (!(guest_efer & EFER_LMA))
1731 guest_efer &= ~EFER_LME;
54b98bff
AL		 1732 if (guest_efer != host_efer)
1733 add_atomic_switch_msr(vmx, MSR_EFER,
1734 guest_efer, host_efer);
84ad33ef
AK		 1735 return false;
1736 }
1737
26bb0981 1738 return true;
51c6cf66
AK		 1739}
1740
2d49ec72
GN		 1741static unsigned long segment_base(u16 selector)
1742{
89cbc767 1743 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1744 struct desc_struct *d;
1745 unsigned long table_base;
1746 unsigned long v;
1747
1748 if (!(selector & ~3))
1749 return 0;
1750
d359192f 1751 table_base = gdt->address;
2d49ec72
GN		 1752
1753 if (selector & 4) { /* from ldt */
1754 u16 ldt_selector = kvm_read_ldt();
1755
1756 if (!(ldt_selector & ~3))
1757 return 0;
1758
1759 table_base = segment_base(ldt_selector);
1760 }
1761 d = (struct desc_struct *)(table_base + (selector & ~7));
1762 v = get_desc_base(d);
1763#ifdef CONFIG_X86_64
1764 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1765 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1766#endif
1767 return v;
1768}
1769
1770static inline unsigned long kvm_read_tr_base(void)
1771{
1772 u16 tr;
1773 asm("str %0" : "=g"(tr));
1774 return segment_base(tr);
1775}
1776
04d2cc77 1777static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1778{
04d2cc77 1779 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1780 int i;
04d2cc77 1781
a2fa3e9f 1782 if (vmx->host_state.loaded)
33ed6329
AK		 1783 return;
1784
a2fa3e9f 1785 vmx->host_state.loaded = 1;
33ed6329
AK		 1786 /*
1787 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1788 * allow segment selectors with cpl > 0 or ti == 1.
1789 */
d6e88aec 1790 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1791 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1792 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1793 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1794 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1795 vmx->host_state.fs_reload_needed = 0;
1796 } else {
33ed6329 1797 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1798 vmx->host_state.fs_reload_needed = 1;
33ed6329 1799 }
9581d442 1800 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1801 if (!(vmx->host_state.gs_sel & 7))
1802 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1803 else {
1804 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1805 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1806 }
1807
b2da15ac
AK		 1808#ifdef CONFIG_X86_64
1809 savesegment(ds, vmx->host_state.ds_sel);
1810 savesegment(es, vmx->host_state.es_sel);
1811#endif
1812
33ed6329
AK		 1813#ifdef CONFIG_X86_64
1814 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1815 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1816#else
a2fa3e9f
GH		 1817 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1818 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1819#endif
707c0874
AK		 1820
1821#ifdef CONFIG_X86_64
c8770e7b
AK		 1822 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1823 if (is_long_mode(&vmx->vcpu))
44ea2b17 1824 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1825#endif
da8999d3
LJ		 1826 if (boot_cpu_has(X86_FEATURE_MPX))
1827 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1828 for (i = 0; i < vmx->save_nmsrs; ++i)
1829 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1830 vmx->guest_msrs[i].data,
1831 vmx->guest_msrs[i].mask);
33ed6329
AK		 1832}
1833
a9b21b62 1834static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1835{
a2fa3e9f 1836 if (!vmx->host_state.loaded)
33ed6329
AK		 1837 return;
1838
e1beb1d3 1839 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1840 vmx->host_state.loaded = 0;
c8770e7b
AK		 1841#ifdef CONFIG_X86_64
1842 if (is_long_mode(&vmx->vcpu))
1843 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1844#endif
152d3f2f 1845 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1846 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1847#ifdef CONFIG_X86_64
9581d442 1848 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1849#else
1850 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1851#endif
33ed6329 1852 }
0a77fe4c
AK		 1853 if (vmx->host_state.fs_reload_needed)
1854 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1855#ifdef CONFIG_X86_64
1856 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1857 loadsegment(ds, vmx->host_state.ds_sel);
1858 loadsegment(es, vmx->host_state.es_sel);
1859 }
b2da15ac 1860#endif
152d3f2f 1861 reload_tss();
44ea2b17 1862#ifdef CONFIG_X86_64
c8770e7b 1863 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1864#endif
da8999d3
LJ		 1865 if (vmx->host_state.msr_host_bndcfgs)
1866 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1867 /*
1868 * If the FPU is not active (through the host task or
1869 * the guest vcpu), then restore the cr0.TS bit.
1870 */
1871 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1872 stts();
89cbc767 1873 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1874}
1875
a9b21b62
AK		 1876static void vmx_load_host_state(struct vcpu_vmx *vmx)
1877{
1878 preempt_disable();
1879 __vmx_load_host_state(vmx);
1880 preempt_enable();
1881}
1882
6aa8b732
AK		 1883/*
1884 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1885 * vcpu mutex is already taken.
1886 */
15ad7146 1887static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1888{
a2fa3e9f 1889 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1890 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1891
4610c9cc
DX		 1892 if (!vmm_exclusive)
1893 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1894 else if (vmx->loaded_vmcs->cpu != cpu)
1895 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1896
d462b819
NHE		 1897 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1898 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1899 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1900 }
1901
d462b819 1902 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1903 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1904 unsigned long sysenter_esp;
1905
a8eeb04a 1906 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1907 local_irq_disable();
8f536b76 1908 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1909
1910 /*
1911 * Read loaded_vmcs->cpu should be before fetching
1912 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1913 * See the comments in __loaded_vmcs_clear().
1914 */
1915 smp_rmb();
1916
d462b819
NHE		 1917 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1918 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1919 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1920 local_irq_enable();
1921
6aa8b732
AK		 1922 /*
1923 * Linux uses per-cpu TSS and GDT, so set these when switching
1924 * processors.
1925 */
d6e88aec 1926 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1927 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1928
1929 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1930 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1931 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1932 }
6aa8b732
AK		 1933}
1934
1935static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1936{
a9b21b62 1937 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1938 if (!vmm_exclusive) {
d462b819
NHE		 1939 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1940 vcpu->cpu = -1;
4610c9cc
DX		 1941 kvm_cpu_vmxoff();
1942 }
6aa8b732
AK		 1943}
1944
5fd86fcf
AK		 1945static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1946{
81231c69
AK		 1947 ulong cr0;
1948
5fd86fcf
AK		 1949 if (vcpu->fpu_active)
1950 return;
1951 vcpu->fpu_active = 1;
81231c69
AK		 1952 cr0 = vmcs_readl(GUEST_CR0);
1953 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1954 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1955 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1956 update_exception_bitmap(vcpu);
edcafe3c 1957 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1958 if (is_guest_mode(vcpu))
1959 vcpu->arch.cr0_guest_owned_bits &=
1960 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1961 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1962}
1963
edcafe3c
AK		 1964static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1965
fe3ef05c
NHE		 1966/*
1967 * Return the cr0 value that a nested guest would read. This is a combination
1968 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1969 * its hypervisor (cr0_read_shadow).
1970 */
1971static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1972{
1973 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1974 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1975}
1976static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1977{
1978 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1979 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1980}
1981
5fd86fcf
AK		 1982static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1983{
36cf24e0
NHE		 1984 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1985 * set this *before* calling this function.
1986 */
edcafe3c 1987 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1988 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1989 update_exception_bitmap(vcpu);
edcafe3c
AK		 1990 vcpu->arch.cr0_guest_owned_bits = 0;
1991 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1992 if (is_guest_mode(vcpu)) {
1993 /*
1994 * L1's specified read shadow might not contain the TS bit,
1995 * so now that we turned on shadowing of this bit, we need to
1996 * set this bit of the shadow. Like in nested_vmx_run we need
1997 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1998 * up-to-date here because we just decached cr0.TS (and we'll
1999 * only update vmcs12->guest_cr0 on nested exit).
2000 */
2001 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2002 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2003 (vcpu->arch.cr0 & X86_CR0_TS);
2004 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2005 } else
2006 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2007}
2008
6aa8b732
AK		 2009static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2010{
78ac8b47 2011 unsigned long rflags, save_rflags;
345dcaa8 2012
6de12732
AK		 2013 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2014 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2015 rflags = vmcs_readl(GUEST_RFLAGS);
2016 if (to_vmx(vcpu)->rmode.vm86_active) {
2017 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2018 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2019 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2020 }
2021 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2022 }
6de12732 2023 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2024}
2025
2026static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2027{
6de12732
AK		 2028 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2029 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2030 if (to_vmx(vcpu)->rmode.vm86_active) {
2031 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2032 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2033 }
6aa8b732
AK		 2034 vmcs_writel(GUEST_RFLAGS, rflags);
2035}
2036
37ccdcbe 2037static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2038{
2039 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2040 int ret = 0;
2041
2042 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2043 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2044 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2045 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2046
37ccdcbe 2047 return ret;
2809f5d2
GC		 2048}
2049
2050static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2051{
2052 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2053 u32 interruptibility = interruptibility_old;
2054
2055 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2056
48005f64 2057 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2058 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2059 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2060 interruptibility |= GUEST_INTR_STATE_STI;
2061
2062 if ((interruptibility != interruptibility_old))
2063 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2064}
2065
6aa8b732
AK		 2066static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2067{
2068 unsigned long rip;
6aa8b732 2069
5fdbf976 2070 rip = kvm_rip_read(vcpu);
6aa8b732 2071 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2072 kvm_rip_write(vcpu, rip);
6aa8b732 2073
2809f5d2
GC		 2074 /* skipping an emulated instruction also counts */
2075 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2076}
2077
0b6ac343
NHE		 2078/*
2079 * KVM wants to inject page-faults which it got to the guest. This function
2080 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2081 */
e011c663 2082static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2083{
2084 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2085
e011c663 2086 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2087 return 0;
2088
533558bc
JK		 2089 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2090 vmcs_read32(VM_EXIT_INTR_INFO),
2091 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2092 return 1;
2093}
2094
298101da 2095static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2096 bool has_error_code, u32 error_code,
2097 bool reinject)
298101da 2098{
77ab6db0 2099 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2100 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2101
e011c663
GN		 2102 if (!reinject && is_guest_mode(vcpu) &&
2103 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2104 return;
2105
8ab2d2e2 2106 if (has_error_code) {
77ab6db0 2107 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2108 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2109 }
77ab6db0 2110
7ffd92c5 2111 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2112 int inc_eip = 0;
2113 if (kvm_exception_is_soft(nr))
2114 inc_eip = vcpu->arch.event_exit_inst_len;
2115 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2116 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2117 return;
2118 }
2119
66fd3f7f
GN		 2120 if (kvm_exception_is_soft(nr)) {
2121 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2122 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2123 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2124 } else
2125 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2126
2127 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2128}
2129
4e47c7a6
SY		 2130static bool vmx_rdtscp_supported(void)
2131{
2132 return cpu_has_vmx_rdtscp();
2133}
2134
ad756a16
MJ		 2135static bool vmx_invpcid_supported(void)
2136{
2137 return cpu_has_vmx_invpcid() && enable_ept;
2138}
2139
a75beee6
ED		 2140/*
2141 * Swap MSR entry in host/guest MSR entry array.
2142 */
8b9cf98c 2143static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2144{
26bb0981 2145 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2146
2147 tmp = vmx->guest_msrs[to];
2148 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2149 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2150}
2151
8d14695f
YZ		 2152static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2153{
2154 unsigned long *msr_bitmap;
2155
2156 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2157 if (is_long_mode(vcpu))
2158 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2159 else
2160 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2161 } else {
2162 if (is_long_mode(vcpu))
2163 msr_bitmap = vmx_msr_bitmap_longmode;
2164 else
2165 msr_bitmap = vmx_msr_bitmap_legacy;
2166 }
2167
2168 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2169}
2170
e38aea3e
AK		 2171/*
2172 * Set up the vmcs to automatically save and restore system
2173 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2174 * mode, as fiddling with msrs is very expensive.
2175 */
8b9cf98c 2176static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2177{
26bb0981 2178 int save_nmsrs, index;
e38aea3e 2179
a75beee6
ED		 2180 save_nmsrs = 0;
2181#ifdef CONFIG_X86_64
8b9cf98c 2182 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2183 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2184 if (index >= 0)
8b9cf98c
RR		 2185 move_msr_up(vmx, index, save_nmsrs++);
2186 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2187 if (index >= 0)
8b9cf98c
RR		 2188 move_msr_up(vmx, index, save_nmsrs++);
2189 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2190 if (index >= 0)
8b9cf98c 2191 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2192 index = __find_msr_index(vmx, MSR_TSC_AUX);
2193 if (index >= 0 && vmx->rdtscp_enabled)
2194 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2195 /*
8c06585d 2196 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2197 * if efer.sce is enabled.
2198 */
8c06585d 2199 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2200 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2201 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2202 }
2203#endif
92c0d900
AK		 2204 index = __find_msr_index(vmx, MSR_EFER);
2205 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2206 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2207
26bb0981 2208 vmx->save_nmsrs = save_nmsrs;
5897297b 2209
8d14695f
YZ		 2210 if (cpu_has_vmx_msr_bitmap())
2211 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2212}
2213
6aa8b732
AK		 2214/*
2215 * reads and returns guest's timestamp counter "register"
2216 * guest_tsc = host_tsc + tsc_offset -- 21.3
2217 */
2218static u64 guest_read_tsc(void)
2219{
2220 u64 host_tsc, tsc_offset;
2221
2222 rdtscll(host_tsc);
2223 tsc_offset = vmcs_read64(TSC_OFFSET);
2224 return host_tsc + tsc_offset;
2225}
2226
d5c1785d
NHE		 2227/*
2228 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2229 * counter, even if a nested guest (L2) is currently running.
2230 */
48d89b92 2231static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2232{
886b470c 2233 u64 tsc_offset;
d5c1785d 2234
d5c1785d
NHE		 2235 tsc_offset = is_guest_mode(vcpu) ?
2236 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2237 vmcs_read64(TSC_OFFSET);
2238 return host_tsc + tsc_offset;
2239}
2240
4051b188 2241/*
cc578287
ZA		 2242 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2243 * software catchup for faster rates on slower CPUs.
4051b188 2244 */
cc578287 2245static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2246{
cc578287
ZA		 2247 if (!scale)
2248 return;
2249
2250 if (user_tsc_khz > tsc_khz) {
2251 vcpu->arch.tsc_catchup = 1;
2252 vcpu->arch.tsc_always_catchup = 1;
2253 } else
2254 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2255}
2256
ba904635
WA		 2257static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2258{
2259 return vmcs_read64(TSC_OFFSET);
2260}
2261
6aa8b732 2262/*
99e3e30a 2263 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2264 */
99e3e30a 2265static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2266{
27fc51b2 2267 if (is_guest_mode(vcpu)) {
7991825b 2268 /*
27fc51b2
NHE		 2269 * We're here if L1 chose not to trap WRMSR to TSC. According
2270 * to the spec, this should set L1's TSC; The offset that L1
2271 * set for L2 remains unchanged, and still needs to be added
2272 * to the newly set TSC to get L2's TSC.
7991825b 2273 */
27fc51b2
NHE		 2274 struct vmcs12 *vmcs12;
2275 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2276 /* recalculate vmcs02.TSC_OFFSET: */
2277 vmcs12 = get_vmcs12(vcpu);
2278 vmcs_write64(TSC_OFFSET, offset +
2279 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2280 vmcs12->tsc_offset : 0));
2281 } else {
489223ed
YY		 2282 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2283 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2284 vmcs_write64(TSC_OFFSET, offset);
2285 }
6aa8b732
AK		 2286}
2287
f1e2b260 2288static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2289{
2290 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2291
e48672fa 2292 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2293 if (is_guest_mode(vcpu)) {
2294 /* Even when running L2, the adjustment needs to apply to L1 */
2295 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2296 } else
2297 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2298 offset + adjustment);
e48672fa
ZA		 2299}
2300
857e4099
JR		 2301static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2302{
2303 return target_tsc - native_read_tsc();
2304}
2305
801d3424
NHE		 2306static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2307{
2308 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2309 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2310}
2311
2312/*
2313 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2314 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2315 * all guests if the "nested" module option is off, and can also be disabled
2316 * for a single guest by disabling its VMX cpuid bit.
2317 */
2318static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2319{
2320 return nested && guest_cpuid_has_vmx(vcpu);
2321}
2322
b87a51ae
NHE		 2323/*
2324 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2325 * returned for the various VMX controls MSRs when nested VMX is enabled.
2326 * The same values should also be used to verify that vmcs12 control fields are
2327 * valid during nested entry from L1 to L2.
2328 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2329 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2330 * bit in the high half is on if the corresponding bit in the control field
2331 * may be on. See also vmx_control_verify().
b87a51ae 2332 */
b9c237bb 2333static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2334{
2335 /*
2336 * Note that as a general rule, the high half of the MSRs (bits in
2337 * the control fields which may be 1) should be initialized by the
2338 * intersection of the underlying hardware's MSR (i.e., features which
2339 * can be supported) and the list of features we want to expose -
2340 * because they are known to be properly supported in our code.
2341 * Also, usually, the low half of the MSRs (bits which must be 1) can
2342 * be set to 0, meaning that L1 may turn off any of these bits. The
2343 * reason is that if one of these bits is necessary, it will appear
2344 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2345 * fields of vmcs01 and vmcs02, will turn these bits off - and
2346 * nested_vmx_exit_handled() will not pass related exits to L1.
2347 * These rules have exceptions below.
2348 */
2349
2350 /* pin-based controls */
eabeaacc 2351 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2352 vmx->nested.nested_vmx_pinbased_ctls_low,
2353 vmx->nested.nested_vmx_pinbased_ctls_high);
2354 vmx->nested.nested_vmx_pinbased_ctls_low |=
2355 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2356 vmx->nested.nested_vmx_pinbased_ctls_high &=
2357 PIN_BASED_EXT_INTR_MASK |
2358 PIN_BASED_NMI_EXITING |
2359 PIN_BASED_VIRTUAL_NMIS;
2360 vmx->nested.nested_vmx_pinbased_ctls_high |=
2361 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2362 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2363
3dbcd8da 2364 /* exit controls */
c0dfee58 2365 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2366 vmx->nested.nested_vmx_exit_ctls_low,
2367 vmx->nested.nested_vmx_exit_ctls_high);
2368 vmx->nested.nested_vmx_exit_ctls_low =
2369 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2370
b9c237bb 2371 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2372#ifdef CONFIG_X86_64
c0dfee58 2373 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2374#endif
f4124500 2375 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2376 vmx->nested.nested_vmx_exit_ctls_high |=
2377 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2378 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2379 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2380
36be0b9d 2381 if (vmx_mpx_supported())
b9c237bb 2382 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2383
2996fca0 2384 /* We support free control of debug control saving. */
b9c237bb
WV		 2385 vmx->nested.nested_vmx_true_exit_ctls_low =
2386 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2387 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2388
b87a51ae
NHE		 2389 /* entry controls */
2390 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2391 vmx->nested.nested_vmx_entry_ctls_low,
2392 vmx->nested.nested_vmx_entry_ctls_high);
2393 vmx->nested.nested_vmx_entry_ctls_low =
2394 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2395 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2396#ifdef CONFIG_X86_64
2397 VM_ENTRY_IA32E_MODE |
2398#endif
2399 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2400 vmx->nested.nested_vmx_entry_ctls_high |=
2401 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2402 if (vmx_mpx_supported())
b9c237bb 2403 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2404
2996fca0 2405 /* We support free control of debug control loading. */
b9c237bb
WV		 2406 vmx->nested.nested_vmx_true_entry_ctls_low =
2407 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2408 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2409
b87a51ae
NHE		 2410 /* cpu-based controls */
2411 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2412 vmx->nested.nested_vmx_procbased_ctls_low,
2413 vmx->nested.nested_vmx_procbased_ctls_high);
2414 vmx->nested.nested_vmx_procbased_ctls_low =
2415 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2416 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2417 CPU_BASED_VIRTUAL_INTR_PENDING |
2418 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2419 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2420 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2421 CPU_BASED_CR3_STORE_EXITING |
2422#ifdef CONFIG_X86_64
2423 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2424#endif
2425 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2426 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2427 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2428 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2429 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2430 /*
2431 * We can allow some features even when not supported by the
2432 * hardware. For example, L1 can specify an MSR bitmap - and we
2433 * can use it to avoid exits to L1 - even when L0 runs L2
2434 * without MSR bitmaps.
2435 */
b9c237bb
WV		 2436 vmx->nested.nested_vmx_procbased_ctls_high |=
2437 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2438 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2439
3dcdf3ec 2440 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2441 vmx->nested.nested_vmx_true_procbased_ctls_low =
2442 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2443 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2444
b87a51ae
NHE		 2445 /* secondary cpu-based controls */
2446 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2447 vmx->nested.nested_vmx_secondary_ctls_low,
2448 vmx->nested.nested_vmx_secondary_ctls_high);
2449 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2450 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2451 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
f2b93280 2452 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2453 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2454 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7
WL		 2455 SECONDARY_EXEC_WBINVD_EXITING |
2456 SECONDARY_EXEC_XSAVES;
c18911a2 2457
afa61f75
NHE		 2458 if (enable_ept) {
2459 /* nested EPT: emulate EPT also to L1 */
b9c237bb
WV		 2460 vmx->nested.nested_vmx_secondary_ctls_high |=
2461 SECONDARY_EXEC_ENABLE_EPT |
78051e3b 2462 SECONDARY_EXEC_UNRESTRICTED_GUEST;
b9c237bb 2463 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2464 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2465 VMX_EPT_INVEPT_BIT;
b9c237bb 2466 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2467 /*
4b855078
BD		 2468 * For nested guests, we don't do anything specific
2469 * for single context invalidation. Hence, only advertise
2470 * support for global context invalidation.
afa61f75 2471 */
b9c237bb 2472 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2473 } else
b9c237bb 2474 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2475
c18911a2 2476 /* miscellaneous data */
b9c237bb
WV		 2477 rdmsr(MSR_IA32_VMX_MISC,
2478 vmx->nested.nested_vmx_misc_low,
2479 vmx->nested.nested_vmx_misc_high);
2480 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2481 vmx->nested.nested_vmx_misc_low |=
2482 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2483 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2484 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2485}
2486
2487static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2488{
2489 /*
2490 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2491 */
2492 return ((control & high) | low) == control;
2493}
2494
2495static inline u64 vmx_control_msr(u32 low, u32 high)
2496{
2497 return low | ((u64)high << 32);
2498}
2499
cae50139 2500/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2501static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2502{
b9c237bb
WV		 2503 struct vcpu_vmx *vmx = to_vmx(vcpu);
2504
b87a51ae 2505 switch (msr_index) {
b87a51ae
NHE		 2506 case MSR_IA32_VMX_BASIC:
2507 /*
2508 * This MSR reports some information about VMX support. We
2509 * should return information about the VMX we emulate for the
2510 * guest, and the VMCS structure we give it - not about the
2511 * VMX support of the underlying hardware.
2512 */
3dbcd8da 2513 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2514 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2515 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2516 break;
2517 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2518 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2519 *pdata = vmx_control_msr(
2520 vmx->nested.nested_vmx_pinbased_ctls_low,
2521 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2522 break;
2523 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2524 *pdata = vmx_control_msr(
2525 vmx->nested.nested_vmx_true_procbased_ctls_low,
2526 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2527 break;
b87a51ae 2528 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2529 *pdata = vmx_control_msr(
2530 vmx->nested.nested_vmx_procbased_ctls_low,
2531 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2532 break;
2533 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2534 *pdata = vmx_control_msr(
2535 vmx->nested.nested_vmx_true_exit_ctls_low,
2536 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2537 break;
b87a51ae 2538 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2539 *pdata = vmx_control_msr(
2540 vmx->nested.nested_vmx_exit_ctls_low,
2541 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2542 break;
2543 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2544 *pdata = vmx_control_msr(
2545 vmx->nested.nested_vmx_true_entry_ctls_low,
2546 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2547 break;
b87a51ae 2548 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2549 *pdata = vmx_control_msr(
2550 vmx->nested.nested_vmx_entry_ctls_low,
2551 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2552 break;
2553 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2554 *pdata = vmx_control_msr(
2555 vmx->nested.nested_vmx_misc_low,
2556 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2557 break;
2558 /*
2559 * These MSRs specify bits which the guest must keep fixed (on or off)
2560 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2561 * We picked the standard core2 setting.
2562 */
2563#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2564#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2565 case MSR_IA32_VMX_CR0_FIXED0:
2566 *pdata = VMXON_CR0_ALWAYSON;
2567 break;
2568 case MSR_IA32_VMX_CR0_FIXED1:
2569 *pdata = -1ULL;
2570 break;
2571 case MSR_IA32_VMX_CR4_FIXED0:
2572 *pdata = VMXON_CR4_ALWAYSON;
2573 break;
2574 case MSR_IA32_VMX_CR4_FIXED1:
2575 *pdata = -1ULL;
2576 break;
2577 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2578 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2579 break;
2580 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2581 *pdata = vmx_control_msr(
2582 vmx->nested.nested_vmx_secondary_ctls_low,
2583 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2584 break;
2585 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2586 /* Currently, no nested vpid support */
b9c237bb 2587 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2588 break;
2589 default:
b87a51ae 2590 return 1;
b3897a49
NHE		 2591 }
2592
b87a51ae
NHE		 2593 return 0;
2594}
2595
6aa8b732
AK		 2596/*
2597 * Reads an msr value (of 'msr_index') into 'pdata'.
2598 * Returns 0 on success, non-0 otherwise.
2599 * Assumes vcpu_load() was already called.
2600 */
2601static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2602{
2603 u64 data;
26bb0981 2604 struct shared_msr_entry *msr;
6aa8b732
AK		 2605
2606 if (!pdata) {
2607 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2608 return -EINVAL;
2609 }
2610
2611 switch (msr_index) {
05b3e0c2 2612#ifdef CONFIG_X86_64
6aa8b732
AK		 2613 case MSR_FS_BASE:
2614 data = vmcs_readl(GUEST_FS_BASE);
2615 break;
2616 case MSR_GS_BASE:
2617 data = vmcs_readl(GUEST_GS_BASE);
2618 break;
44ea2b17
AK		 2619 case MSR_KERNEL_GS_BASE:
2620 vmx_load_host_state(to_vmx(vcpu));
2621 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2622 break;
26bb0981 2623#endif
6aa8b732 2624 case MSR_EFER:
3bab1f5d 2625 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2626 case MSR_IA32_TSC:
6aa8b732
AK		 2627 data = guest_read_tsc();
2628 break;
2629 case MSR_IA32_SYSENTER_CS:
2630 data = vmcs_read32(GUEST_SYSENTER_CS);
2631 break;
2632 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2633 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2634 break;
2635 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2636 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2637 break;
0dd376e7 2638 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2639 if (!vmx_mpx_supported())
2640 return 1;
0dd376e7
LJ		 2641 data = vmcs_read64(GUEST_BNDCFGS);
2642 break;
cae50139
JK		 2643 case MSR_IA32_FEATURE_CONTROL:
2644 if (!nested_vmx_allowed(vcpu))
2645 return 1;
2646 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2647 break;
2648 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2649 if (!nested_vmx_allowed(vcpu))
2650 return 1;
2651 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2652 case MSR_IA32_XSS:
2653 if (!vmx_xsaves_supported())
2654 return 1;
2655 data = vcpu->arch.ia32_xss;
2656 break;
4e47c7a6
SY		 2657 case MSR_TSC_AUX:
2658 if (!to_vmx(vcpu)->rdtscp_enabled)
2659 return 1;
2660 /* Otherwise falls through */
6aa8b732 2661 default:
8b9cf98c 2662 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2663 if (msr) {
2664 data = msr->data;
2665 break;
6aa8b732 2666 }
3bab1f5d 2667 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2668 }
2669
2670 *pdata = data;
2671 return 0;
2672}
2673
cae50139
JK		 2674static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2675
6aa8b732
AK		 2676/*
2677 * Writes msr value into into the appropriate "register".
2678 * Returns 0 on success, non-0 otherwise.
2679 * Assumes vcpu_load() was already called.
2680 */
8fe8ab46 2681static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2682{
a2fa3e9f 2683 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2684 struct shared_msr_entry *msr;
2cc51560 2685 int ret = 0;
8fe8ab46
WA		 2686 u32 msr_index = msr_info->index;
2687 u64 data = msr_info->data;
2cc51560 2688
6aa8b732 2689 switch (msr_index) {
3bab1f5d 2690 case MSR_EFER:
8fe8ab46 2691 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2692 break;
16175a79 2693#ifdef CONFIG_X86_64
6aa8b732 2694 case MSR_FS_BASE:
2fb92db1 2695 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2696 vmcs_writel(GUEST_FS_BASE, data);
2697 break;
2698 case MSR_GS_BASE:
2fb92db1 2699 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2700 vmcs_writel(GUEST_GS_BASE, data);
2701 break;
44ea2b17
AK		 2702 case MSR_KERNEL_GS_BASE:
2703 vmx_load_host_state(vmx);
2704 vmx->msr_guest_kernel_gs_base = data;
2705 break;
6aa8b732
AK		 2706#endif
2707 case MSR_IA32_SYSENTER_CS:
2708 vmcs_write32(GUEST_SYSENTER_CS, data);
2709 break;
2710 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2711 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2712 break;
2713 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2714 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2715 break;
0dd376e7 2716 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2717 if (!vmx_mpx_supported())
2718 return 1;
0dd376e7
LJ		 2719 vmcs_write64(GUEST_BNDCFGS, data);
2720 break;
af24a4e4 2721 case MSR_IA32_TSC:
8fe8ab46 2722 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2723 break;
468d472f
SY		 2724 case MSR_IA32_CR_PAT:
2725 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2726 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2727 return 1;
468d472f
SY		 2728 vmcs_write64(GUEST_IA32_PAT, data);
2729 vcpu->arch.pat = data;
2730 break;
2731 }
8fe8ab46 2732 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2733 break;
ba904635
WA		 2734 case MSR_IA32_TSC_ADJUST:
2735 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2736 break;
cae50139
JK		 2737 case MSR_IA32_FEATURE_CONTROL:
2738 if (!nested_vmx_allowed(vcpu) ||
2739 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2740 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2741 return 1;
2742 vmx->nested.msr_ia32_feature_control = data;
2743 if (msr_info->host_initiated && data == 0)
2744 vmx_leave_nested(vcpu);
2745 break;
2746 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2747 return 1; /* they are read-only */
20300099
WL		 2748 case MSR_IA32_XSS:
2749 if (!vmx_xsaves_supported())
2750 return 1;
2751 /*
2752 * The only supported bit as of Skylake is bit 8, but
2753 * it is not supported on KVM.
2754 */
2755 if (data != 0)
2756 return 1;
2757 vcpu->arch.ia32_xss = data;
2758 if (vcpu->arch.ia32_xss != host_xss)
2759 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2760 vcpu->arch.ia32_xss, host_xss);
2761 else
2762 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2763 break;
4e47c7a6
SY		 2764 case MSR_TSC_AUX:
2765 if (!vmx->rdtscp_enabled)
2766 return 1;
2767 /* Check reserved bit, higher 32 bits should be zero */
2768 if ((data >> 32) != 0)
2769 return 1;
2770 /* Otherwise falls through */
6aa8b732 2771 default:
8b9cf98c 2772 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2773 if (msr) {
8b3c3104 2774 u64 old_msr_data = msr->data;
3bab1f5d 2775 msr->data = data;
2225fd56
AK		 2776 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2777 preempt_disable();
8b3c3104
AH		 2778 ret = kvm_set_shared_msr(msr->index, msr->data,
2779 msr->mask);
2225fd56 2780 preempt_enable();
8b3c3104
AH		 2781 if (ret)
2782 msr->data = old_msr_data;
2225fd56 2783 }
3bab1f5d 2784 break;
6aa8b732 2785 }
8fe8ab46 2786 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2787 }
2788
2cc51560 2789 return ret;
6aa8b732
AK		 2790}
2791
5fdbf976 2792static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2793{
5fdbf976
MT		 2794 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2795 switch (reg) {
2796 case VCPU_REGS_RSP:
2797 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2798 break;
2799 case VCPU_REGS_RIP:
2800 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2801 break;
6de4f3ad
AK		 2802 case VCPU_EXREG_PDPTR:
2803 if (enable_ept)
2804 ept_save_pdptrs(vcpu);
2805 break;
5fdbf976
MT		 2806 default:
2807 break;
2808 }
6aa8b732
AK		 2809}
2810
6aa8b732
AK		 2811static __init int cpu_has_kvm_support(void)
2812{
6210e37b 2813 return cpu_has_vmx();
6aa8b732
AK		 2814}
2815
2816static __init int vmx_disabled_by_bios(void)
2817{
2818 u64 msr;
2819
2820 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2821 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2822 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2823 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2824 && tboot_enabled())
2825 return 1;
23f3e991 2826 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2827 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2828 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2829 && !tboot_enabled()) {
2830 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2831 "activate TXT before enabling KVM\n");
cafd6659 2832 return 1;
f9335afe 2833 }
23f3e991
JC		 2834 /* launched w/o TXT and VMX disabled */
2835 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2836 && !tboot_enabled())
2837 return 1;
cafd6659
SW		 2838 }
2839
2840 return 0;
6aa8b732
AK		 2841}
2842
7725b894
DX		 2843static void kvm_cpu_vmxon(u64 addr)
2844{
2845 asm volatile (ASM_VMX_VMXON_RAX
2846 : : "a"(&addr), "m"(addr)
2847 : "memory", "cc");
2848}
2849
13a34e06 2850static int hardware_enable(void)
6aa8b732
AK		 2851{
2852 int cpu = raw_smp_processor_id();
2853 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2854 u64 old, test_bits;
6aa8b732 2855
10474ae8
AG		 2856 if (read_cr4() & X86_CR4_VMXE)
2857 return -EBUSY;
2858
d462b819 2859 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2860
2861 /*
2862 * Now we can enable the vmclear operation in kdump
2863 * since the loaded_vmcss_on_cpu list on this cpu
2864 * has been initialized.
2865 *
2866 * Though the cpu is not in VMX operation now, there
2867 * is no problem to enable the vmclear operation
2868 * for the loaded_vmcss_on_cpu list is empty!
2869 */
2870 crash_enable_local_vmclear(cpu);
2871
6aa8b732 2872 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2873
2874 test_bits = FEATURE_CONTROL_LOCKED;
2875 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2876 if (tboot_enabled())
2877 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2878
2879 if ((old & test_bits) != test_bits) {
6aa8b732 2880 /* enable and lock */
cafd6659
SW		 2881 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2882 }
66aee91a 2883 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2884
4610c9cc
DX		 2885 if (vmm_exclusive) {
2886 kvm_cpu_vmxon(phys_addr);
2887 ept_sync_global();
2888 }
10474ae8 2889
89cbc767 2890 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2891
10474ae8 2892 return 0;
6aa8b732
AK		 2893}
2894
d462b819 2895static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2896{
2897 int cpu = raw_smp_processor_id();
d462b819 2898 struct loaded_vmcs *v, *n;
543e4243 2899
d462b819
NHE		 2900 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2901 loaded_vmcss_on_cpu_link)
2902 __loaded_vmcs_clear(v);
543e4243
AK		 2903}
2904
710ff4a8
EH		 2905
2906/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2907 * tricks.
2908 */
2909static void kvm_cpu_vmxoff(void)
6aa8b732 2910{
4ecac3fd 2911 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2912}
2913
13a34e06 2914static void hardware_disable(void)
710ff4a8 2915{
4610c9cc 2916 if (vmm_exclusive) {
d462b819 2917 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2918 kvm_cpu_vmxoff();
2919 }
7725b894 2920 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2921}
2922
1c3d14fe 2923static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2924 u32 msr, u32 *result)
1c3d14fe
YS		 2925{
2926 u32 vmx_msr_low, vmx_msr_high;
2927 u32 ctl = ctl_min | ctl_opt;
2928
2929 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2930
2931 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2932 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2933
2934 /* Ensure minimum (required) set of control bits are supported. */
2935 if (ctl_min & ~ctl)
002c7f7c 2936 return -EIO;
1c3d14fe
YS		 2937
2938 *result = ctl;
2939 return 0;
2940}
2941
110312c8
AK		 2942static __init bool allow_1_setting(u32 msr, u32 ctl)
2943{
2944 u32 vmx_msr_low, vmx_msr_high;
2945
2946 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2947 return vmx_msr_high & ctl;
2948}
2949
002c7f7c 2950static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2951{
2952 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2953 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2954 u32 _pin_based_exec_control = 0;
2955 u32 _cpu_based_exec_control = 0;
f78e0e2e 2956 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2957 u32 _vmexit_control = 0;
2958 u32 _vmentry_control = 0;
2959
10166744 2960 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2961#ifdef CONFIG_X86_64
2962 CPU_BASED_CR8_LOAD_EXITING |
2963 CPU_BASED_CR8_STORE_EXITING |
2964#endif
d56f546d
SY		 2965 CPU_BASED_CR3_LOAD_EXITING |
2966 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2967 CPU_BASED_USE_IO_BITMAPS |
2968 CPU_BASED_MOV_DR_EXITING |
a7052897 2969 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2970 CPU_BASED_MWAIT_EXITING |
2971 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2972 CPU_BASED_INVLPG_EXITING |
2973 CPU_BASED_RDPMC_EXITING;
443381a8 2974
f78e0e2e 2975 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2976 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2977 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2978 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2979 &_cpu_based_exec_control) < 0)
002c7f7c 2980 return -EIO;
6e5d865c
YS		 2981#ifdef CONFIG_X86_64
2982 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2983 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2984 ~CPU_BASED_CR8_STORE_EXITING;
2985#endif
f78e0e2e 2986 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2987 min2 = 0;
2988 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2989 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2990 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2991 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2992 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2993 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2994 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2995 SECONDARY_EXEC_RDTSCP |
83d4c286 2996 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2997 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2998 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2999 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 3000 SECONDARY_EXEC_XSAVES |
3001 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 3002 if (adjust_vmx_controls(min2, opt2,
3003 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3004 &_cpu_based_2nd_exec_control) < 0)
3005 return -EIO;
3006 }
3007#ifndef CONFIG_X86_64
3008 if (!(_cpu_based_2nd_exec_control &
3009 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3010 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3011#endif
83d4c286
YZ		 3012
3013 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3014 _cpu_based_2nd_exec_control &= ~(
8d14695f 3015 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3016 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3017 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3018
d56f546d 3019 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3020 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3021 enabled */
5fff7d27
GN		 3022 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3023 CPU_BASED_CR3_STORE_EXITING |
3024 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3025 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3026 vmx_capability.ept, vmx_capability.vpid);
3027 }
1c3d14fe 3028
81908bf4 3029 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3030#ifdef CONFIG_X86_64
3031 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3032#endif
a547c6db 3033 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3034 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3035 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3036 &_vmexit_control) < 0)
002c7f7c 3037 return -EIO;
1c3d14fe 3038
01e439be
YZ		 3039 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3040 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3041 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3042 &_pin_based_exec_control) < 0)
3043 return -EIO;
3044
3045 if (!(_cpu_based_2nd_exec_control &
3046 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3047 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3048 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3049
c845f9c6 3050 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3051 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3052 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3053 &_vmentry_control) < 0)
002c7f7c 3054 return -EIO;
6aa8b732 3055
c68876fd 3056 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3057
3058 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3059 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3060 return -EIO;
1c3d14fe
YS		 3061
3062#ifdef CONFIG_X86_64
3063 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3064 if (vmx_msr_high & (1u<<16))
002c7f7c 3065 return -EIO;
1c3d14fe
YS		 3066#endif
3067
3068 /* Require Write-Back (WB) memory type for VMCS accesses. */
3069 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3070 return -EIO;
1c3d14fe 3071
002c7f7c
YS		 3072 vmcs_conf->size = vmx_msr_high & 0x1fff;
3073 vmcs_conf->order = get_order(vmcs_config.size);
3074 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3075
002c7f7c
YS		 3076 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3077 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3078 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3079 vmcs_conf->vmexit_ctrl = _vmexit_control;
3080 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3081
110312c8
AK		 3082 cpu_has_load_ia32_efer =
3083 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3084 VM_ENTRY_LOAD_IA32_EFER)
3085 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3086 VM_EXIT_LOAD_IA32_EFER);
3087
8bf00a52
GN		 3088 cpu_has_load_perf_global_ctrl =
3089 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3090 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3091 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3092 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3093
3094 /*
3095 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3096 * but due to arrata below it can't be used. Workaround is to use
3097 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3098 *
3099 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3100 *
3101 * AAK155 (model 26)
3102 * AAP115 (model 30)
3103 * AAT100 (model 37)
3104 * BC86,AAY89,BD102 (model 44)
3105 * BA97 (model 46)
3106 *
3107 */
3108 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3109 switch (boot_cpu_data.x86_model) {
3110 case 26:
3111 case 30:
3112 case 37:
3113 case 44:
3114 case 46:
3115 cpu_has_load_perf_global_ctrl = false;
3116 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3117 "does not work properly. Using workaround\n");
3118 break;
3119 default:
3120 break;
3121 }
3122 }
3123
20300099
WL		 3124 if (cpu_has_xsaves)
3125 rdmsrl(MSR_IA32_XSS, host_xss);
3126
1c3d14fe 3127 return 0;
c68876fd 3128}
6aa8b732
AK		 3129
3130static struct vmcs *alloc_vmcs_cpu(int cpu)
3131{
3132 int node = cpu_to_node(cpu);
3133 struct page *pages;
3134 struct vmcs *vmcs;
3135
6484eb3e 3136 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3137 if (!pages)
3138 return NULL;
3139 vmcs = page_address(pages);
1c3d14fe
YS		 3140 memset(vmcs, 0, vmcs_config.size);
3141 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3142 return vmcs;
3143}
3144
3145static struct vmcs *alloc_vmcs(void)
3146{
d3b2c338 3147 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3148}
3149
3150static void free_vmcs(struct vmcs *vmcs)
3151{
1c3d14fe 3152 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3153}
3154
d462b819
NHE		 3155/*
3156 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3157 */
3158static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3159{
3160 if (!loaded_vmcs->vmcs)
3161 return;
3162 loaded_vmcs_clear(loaded_vmcs);
3163 free_vmcs(loaded_vmcs->vmcs);
3164 loaded_vmcs->vmcs = NULL;
3165}
3166
39959588 3167static void free_kvm_area(void)
6aa8b732
AK		 3168{
3169 int cpu;
3170
3230bb47 3171 for_each_possible_cpu(cpu) {
6aa8b732 3172 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3173 per_cpu(vmxarea, cpu) = NULL;
3174 }
6aa8b732
AK		 3175}
3176
fe2b201b
BD		 3177static void init_vmcs_shadow_fields(void)
3178{
3179 int i, j;
3180
3181 /* No checks for read only fields yet */
3182
3183 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3184 switch (shadow_read_write_fields[i]) {
3185 case GUEST_BNDCFGS:
3186 if (!vmx_mpx_supported())
3187 continue;
3188 break;
3189 default:
3190 break;
3191 }
3192
3193 if (j < i)
3194 shadow_read_write_fields[j] =
3195 shadow_read_write_fields[i];
3196 j++;
3197 }
3198 max_shadow_read_write_fields = j;
3199
3200 /* shadowed fields guest access without vmexit */
3201 for (i = 0; i < max_shadow_read_write_fields; i++) {
3202 clear_bit(shadow_read_write_fields[i],
3203 vmx_vmwrite_bitmap);
3204 clear_bit(shadow_read_write_fields[i],
3205 vmx_vmread_bitmap);
3206 }
3207 for (i = 0; i < max_shadow_read_only_fields; i++)
3208 clear_bit(shadow_read_only_fields[i],
3209 vmx_vmread_bitmap);
3210}
3211
6aa8b732
AK		 3212static __init int alloc_kvm_area(void)
3213{
3214 int cpu;
3215
3230bb47 3216 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3217 struct vmcs *vmcs;
3218
3219 vmcs = alloc_vmcs_cpu(cpu);
3220 if (!vmcs) {
3221 free_kvm_area();
3222 return -ENOMEM;
3223 }
3224
3225 per_cpu(vmxarea, cpu) = vmcs;
3226 }
3227 return 0;
3228}
3229
14168786
GN		 3230static bool emulation_required(struct kvm_vcpu *vcpu)
3231{
3232 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3233}
3234
91b0aa2c 3235static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3236 struct kvm_segment *save)
6aa8b732 3237{
d99e4152
GN		 3238 if (!emulate_invalid_guest_state) {
3239 /*
3240 * CS and SS RPL should be equal during guest entry according
3241 * to VMX spec, but in reality it is not always so. Since vcpu
3242 * is in the middle of the transition from real mode to
3243 * protected mode it is safe to assume that RPL 0 is a good
3244 * default value.
3245 */
3246 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3247 save->selector &= ~SELECTOR_RPL_MASK;
3248 save->dpl = save->selector & SELECTOR_RPL_MASK;
3249 save->s = 1;
6aa8b732 3250 }
d99e4152 3251 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3252}
3253
3254static void enter_pmode(struct kvm_vcpu *vcpu)
3255{
3256 unsigned long flags;
a89a8fb9 3257 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3258
d99e4152
GN		 3259 /*
3260 * Update real mode segment cache. It may be not up-to-date if sement
3261 * register was written while vcpu was in a guest mode.
3262 */
3263 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3264 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3265 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3266 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3267 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3268 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3269
7ffd92c5 3270 vmx->rmode.vm86_active = 0;
6aa8b732 3271
2fb92db1
AK		 3272 vmx_segment_cache_clear(vmx);
3273
f5f7b2fe 3274 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3275
3276 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3277 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3278 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3279 vmcs_writel(GUEST_RFLAGS, flags);
3280
66aee91a
RR		 3281 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3282 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3283
3284 update_exception_bitmap(vcpu);
3285
91b0aa2c
GN		 3286 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3287 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3288 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3289 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3290 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3291 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3292}
3293
f5f7b2fe 3294static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3295{
772e0318 3296 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3297 struct kvm_segment var = *save;
3298
3299 var.dpl = 0x3;
3300 if (seg == VCPU_SREG_CS)
3301 var.type = 0x3;
3302
3303 if (!emulate_invalid_guest_state) {
3304 var.selector = var.base >> 4;
3305 var.base = var.base & 0xffff0;
3306 var.limit = 0xffff;
3307 var.g = 0;
3308 var.db = 0;
3309 var.present = 1;
3310 var.s = 1;
3311 var.l = 0;
3312 var.unusable = 0;
3313 var.type = 0x3;
3314 var.avl = 0;
3315 if (save->base & 0xf)
3316 printk_once(KERN_WARNING "kvm: segment base is not "
3317 "paragraph aligned when entering "
3318 "protected mode (seg=%d)", seg);
3319 }
6aa8b732 3320
d99e4152
GN		 3321 vmcs_write16(sf->selector, var.selector);
3322 vmcs_write32(sf->base, var.base);
3323 vmcs_write32(sf->limit, var.limit);
3324 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3325}
3326
3327static void enter_rmode(struct kvm_vcpu *vcpu)
3328{
3329 unsigned long flags;
a89a8fb9 3330 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3331
f5f7b2fe
AK		 3332 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3333 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3334 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3335 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3336 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3337 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3338 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3339
7ffd92c5 3340 vmx->rmode.vm86_active = 1;
6aa8b732 3341
776e58ea
GN		 3342 /*
3343 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3344 * vcpu. Warn the user that an update is overdue.
776e58ea 3345 */
4918c6ca 3346 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3347 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3348 "called before entering vcpu\n");
776e58ea 3349
2fb92db1
AK		 3350 vmx_segment_cache_clear(vmx);
3351
4918c6ca 3352 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3353 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3354 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3355
3356 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3357 vmx->rmode.save_rflags = flags;
6aa8b732 3358
053de044 3359 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3360
3361 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3362 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3363 update_exception_bitmap(vcpu);
3364
d99e4152
GN		 3365 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3366 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3367 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3368 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3369 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3370 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3371
8668a3c4 3372 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3373}
3374
401d10de
AS		 3375static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3376{
3377 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3378 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3379
3380 if (!msr)
3381 return;
401d10de 3382
44ea2b17
AK		 3383 /*
3384 * Force kernel_gs_base reloading before EFER changes, as control
3385 * of this msr depends on is_long_mode().
3386 */
3387 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3388 vcpu->arch.efer = efer;
401d10de 3389 if (efer & EFER_LMA) {
2961e876 3390 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3391 msr->data = efer;
3392 } else {
2961e876 3393 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3394
3395 msr->data = efer & ~EFER_LME;
3396 }
3397 setup_msrs(vmx);
3398}
3399
05b3e0c2 3400#ifdef CONFIG_X86_64
6aa8b732
AK		 3401
3402static void enter_lmode(struct kvm_vcpu *vcpu)
3403{
3404 u32 guest_tr_ar;
3405
2fb92db1
AK		 3406 vmx_segment_cache_clear(to_vmx(vcpu));
3407
6aa8b732
AK		 3408 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3409 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3410 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3411 __func__);
6aa8b732
AK		 3412 vmcs_write32(GUEST_TR_AR_BYTES,
3413 (guest_tr_ar & ~AR_TYPE_MASK)
3414 | AR_TYPE_BUSY_64_TSS);
3415 }
da38f438 3416 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3417}
3418
3419static void exit_lmode(struct kvm_vcpu *vcpu)
3420{
2961e876 3421 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3422 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3423}
3424
3425#endif
3426
2384d2b3
SY		 3427static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3428{
b9d762fa 3429 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3430 if (enable_ept) {
3431 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3432 return;
4e1096d2 3433 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3434 }
2384d2b3
SY		 3435}
3436
e8467fda
AK		 3437static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3438{
3439 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3440
3441 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3442 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3443}
3444
aff48baa
AK		 3445static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3446{
3447 if (enable_ept && is_paging(vcpu))
3448 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3449 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3450}
3451
25c4c276 3452static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3453{
fc78f519
AK		 3454 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3455
3456 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3457 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3458}
3459
1439442c
SY		 3460static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3461{
d0d538b9
GN		 3462 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3463
6de4f3ad
AK		 3464 if (!test_bit(VCPU_EXREG_PDPTR,
3465 (unsigned long *)&vcpu->arch.regs_dirty))
3466 return;
3467
1439442c 3468 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3469 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3470 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3471 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3472 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3473 }
3474}
3475
8f5d549f
AK		 3476static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3477{
d0d538b9
GN		 3478 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3479
8f5d549f 3480 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3481 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3482 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3483 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3484 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3485 }
6de4f3ad
AK		 3486
3487 __set_bit(VCPU_EXREG_PDPTR,
3488 (unsigned long *)&vcpu->arch.regs_avail);
3489 __set_bit(VCPU_EXREG_PDPTR,
3490 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3491}
3492
5e1746d6 3493static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3494
3495static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3496 unsigned long cr0,
3497 struct kvm_vcpu *vcpu)
3498{
5233dd51
MT		 3499 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3500 vmx_decache_cr3(vcpu);
1439442c
SY		 3501 if (!(cr0 & X86_CR0_PG)) {
3502 /* From paging/starting to nonpaging */
3503 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3504 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3505 (CPU_BASED_CR3_LOAD_EXITING |
3506 CPU_BASED_CR3_STORE_EXITING));
3507 vcpu->arch.cr0 = cr0;
fc78f519 3508 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3509 } else if (!is_paging(vcpu)) {
3510 /* From nonpaging to paging */
3511 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3512 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3513 ~(CPU_BASED_CR3_LOAD_EXITING |
3514 CPU_BASED_CR3_STORE_EXITING));
3515 vcpu->arch.cr0 = cr0;
fc78f519 3516 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3517 }
95eb84a7
SY		 3518
3519 if (!(cr0 & X86_CR0_WP))
3520 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3521}
3522
6aa8b732
AK		 3523static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3524{
7ffd92c5 3525 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3526 unsigned long hw_cr0;
3527
5037878e 3528 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3529 if (enable_unrestricted_guest)
5037878e 3530 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3531 else {
5037878e 3532 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3533
218e763f
GN		 3534 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3535 enter_pmode(vcpu);
6aa8b732 3536
218e763f
GN		 3537 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3538 enter_rmode(vcpu);
3539 }
6aa8b732 3540
05b3e0c2 3541#ifdef CONFIG_X86_64
f6801dff 3542 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3543 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3544 enter_lmode(vcpu);
707d92fa 3545 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3546 exit_lmode(vcpu);
3547 }
3548#endif
3549
089d034e 3550 if (enable_ept)
1439442c
SY		 3551 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3552
02daab21 3553 if (!vcpu->fpu_active)
81231c69 3554 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3555
6aa8b732 3556 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3557 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3558 vcpu->arch.cr0 = cr0;
14168786
GN		 3559
3560 /* depends on vcpu->arch.cr0 to be set to a new value */
3561 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3562}
3563
1439442c
SY		 3564static u64 construct_eptp(unsigned long root_hpa)
3565{
3566 u64 eptp;
3567
3568 /* TODO write the value reading from MSR */
3569 eptp = VMX_EPT_DEFAULT_MT |
3570 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3571 if (enable_ept_ad_bits)
3572 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3573 eptp |= (root_hpa & PAGE_MASK);
3574
3575 return eptp;
3576}
3577
6aa8b732
AK		 3578static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3579{
1439442c
SY		 3580 unsigned long guest_cr3;
3581 u64 eptp;
3582
3583 guest_cr3 = cr3;
089d034e 3584 if (enable_ept) {
1439442c
SY		 3585 eptp = construct_eptp(cr3);
3586 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3587 if (is_paging(vcpu) || is_guest_mode(vcpu))
3588 guest_cr3 = kvm_read_cr3(vcpu);
3589 else
3590 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3591 ept_load_pdptrs(vcpu);
1439442c
SY		 3592 }
3593
2384d2b3 3594 vmx_flush_tlb(vcpu);
1439442c 3595 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3596}
3597
5e1746d6 3598static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3599{
7ffd92c5 3600 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3601 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3602
5e1746d6
NHE		 3603 if (cr4 & X86_CR4_VMXE) {
3604 /*
3605 * To use VMXON (and later other VMX instructions), a guest
3606 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3607 * So basically the check on whether to allow nested VMX
3608 * is here.
3609 */
3610 if (!nested_vmx_allowed(vcpu))
3611 return 1;
1a0d74e6
JK		 3612 }
3613 if (to_vmx(vcpu)->nested.vmxon &&
3614 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3615 return 1;
3616
ad312c7c 3617 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3618 if (enable_ept) {
3619 if (!is_paging(vcpu)) {
3620 hw_cr4 &= ~X86_CR4_PAE;
3621 hw_cr4 |= X86_CR4_PSE;
c08800a5 3622 /*
e1e746b3
FW		 3623 * SMEP/SMAP is disabled if CPU is in non-paging mode
3624 * in hardware. However KVM always uses paging mode to
c08800a5 3625 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3626 * To emulate this behavior, SMEP/SMAP needs to be
3627 * manually disabled when guest switches to non-paging
3628 * mode.
c08800a5 3629 */
e1e746b3 3630 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3631 } else if (!(cr4 & X86_CR4_PAE)) {
3632 hw_cr4 &= ~X86_CR4_PAE;
3633 }
3634 }
1439442c
SY		 3635
3636 vmcs_writel(CR4_READ_SHADOW, cr4);
3637 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3638 return 0;
6aa8b732
AK		 3639}
3640
6aa8b732
AK		 3641static void vmx_get_segment(struct kvm_vcpu *vcpu,
3642 struct kvm_segment *var, int seg)
3643{
a9179499 3644 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3645 u32 ar;
3646
c6ad1153 3647 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3648 *var = vmx->rmode.segs[seg];
a9179499 3649 if (seg == VCPU_SREG_TR
2fb92db1 3650 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3651 return;
1390a28b
AK		 3652 var->base = vmx_read_guest_seg_base(vmx, seg);
3653 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3654 return;
a9179499 3655 }
2fb92db1
AK		 3656 var->base = vmx_read_guest_seg_base(vmx, seg);
3657 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3658 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3659 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3660 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3661 var->type = ar & 15;
3662 var->s = (ar >> 4) & 1;
3663 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3664 /*
3665 * Some userspaces do not preserve unusable property. Since usable
3666 * segment has to be present according to VMX spec we can use present
3667 * property to amend userspace bug by making unusable segment always
3668 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3669 * segment as unusable.
3670 */
3671 var->present = !var->unusable;
6aa8b732
AK		 3672 var->avl = (ar >> 12) & 1;
3673 var->l = (ar >> 13) & 1;
3674 var->db = (ar >> 14) & 1;
3675 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3676}
3677
a9179499
AK		 3678static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3679{
a9179499
AK		 3680 struct kvm_segment s;
3681
3682 if (to_vmx(vcpu)->rmode.vm86_active) {
3683 vmx_get_segment(vcpu, &s, seg);
3684 return s.base;
3685 }
2fb92db1 3686 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3687}
3688
b09408d0 3689static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3690{
b09408d0
MT		 3691 struct vcpu_vmx *vmx = to_vmx(vcpu);
3692
ae9fedc7 3693 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3694 return 0;
ae9fedc7
PB		 3695 else {
3696 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3697 return AR_DPL(ar);
69c73028 3698 }
69c73028
AK		 3699}
3700
653e3108 3701static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3702{
6aa8b732
AK		 3703 u32 ar;
3704
f0495f9b 3705 if (var->unusable || !var->present)
6aa8b732
AK		 3706 ar = 1 << 16;
3707 else {
3708 ar = var->type & 15;
3709 ar |= (var->s & 1) << 4;
3710 ar |= (var->dpl & 3) << 5;
3711 ar |= (var->present & 1) << 7;
3712 ar |= (var->avl & 1) << 12;
3713 ar |= (var->l & 1) << 13;
3714 ar |= (var->db & 1) << 14;
3715 ar |= (var->g & 1) << 15;
3716 }
653e3108
AK		 3717
3718 return ar;
3719}
3720
3721static void vmx_set_segment(struct kvm_vcpu *vcpu,
3722 struct kvm_segment *var, int seg)
3723{
7ffd92c5 3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3725 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3726
2fb92db1
AK		 3727 vmx_segment_cache_clear(vmx);
3728
1ecd50a9
GN		 3729 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3730 vmx->rmode.segs[seg] = *var;
3731 if (seg == VCPU_SREG_TR)
3732 vmcs_write16(sf->selector, var->selector);
3733 else if (var->s)
3734 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3735 goto out;
653e3108 3736 }
1ecd50a9 3737
653e3108
AK		 3738 vmcs_writel(sf->base, var->base);
3739 vmcs_write32(sf->limit, var->limit);
3740 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3741
3742 /*
3743 * Fix the "Accessed" bit in AR field of segment registers for older
3744 * qemu binaries.
3745 * IA32 arch specifies that at the time of processor reset the
3746 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3747 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3748 * state vmexit when "unrestricted guest" mode is turned on.
3749 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3750 * tree. Newer qemu binaries with that qemu fix would not need this
3751 * kvm hack.
3752 */
3753 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3754 var->type |= 0x1; /* Accessed */
3a624e29 3755
f924d66d 3756 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3757
3758out:
98eb2f8b 3759 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3760}
3761
6aa8b732
AK		 3762static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3763{
2fb92db1 3764 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3765
3766 *db = (ar >> 14) & 1;
3767 *l = (ar >> 13) & 1;
3768}
3769
89a27f4d 3770static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3771{
89a27f4d
GN		 3772 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3773 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3774}
3775
89a27f4d 3776static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3777{
89a27f4d
GN		 3778 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3779 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3780}
3781
89a27f4d 3782static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3783{
89a27f4d
GN		 3784 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3785 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3786}
3787
89a27f4d 3788static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3789{
89a27f4d
GN		 3790 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3791 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3792}
3793
648dfaa7
MG		 3794static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3795{
3796 struct kvm_segment var;
3797 u32 ar;
3798
3799 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3800 var.dpl = 0x3;
0647f4aa
GN		 3801 if (seg == VCPU_SREG_CS)
3802 var.type = 0x3;
648dfaa7
MG		 3803 ar = vmx_segment_access_rights(&var);
3804
3805 if (var.base != (var.selector << 4))
3806 return false;
89efbed0 3807 if (var.limit != 0xffff)
648dfaa7 3808 return false;
07f42f5f 3809 if (ar != 0xf3)
648dfaa7
MG		 3810 return false;
3811
3812 return true;
3813}
3814
3815static bool code_segment_valid(struct kvm_vcpu *vcpu)
3816{
3817 struct kvm_segment cs;
3818 unsigned int cs_rpl;
3819
3820 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3821 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3822
1872a3f4
AK		 3823 if (cs.unusable)
3824 return false;
648dfaa7
MG		 3825 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3826 return false;
3827 if (!cs.s)
3828 return false;
1872a3f4 3829 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3830 if (cs.dpl > cs_rpl)
3831 return false;
1872a3f4 3832 } else {
648dfaa7
MG		 3833 if (cs.dpl != cs_rpl)
3834 return false;
3835 }
3836 if (!cs.present)
3837 return false;
3838
3839 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3840 return true;
3841}
3842
3843static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3844{
3845 struct kvm_segment ss;
3846 unsigned int ss_rpl;
3847
3848 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3849 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3850
1872a3f4
AK		 3851 if (ss.unusable)
3852 return true;
3853 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3854 return false;
3855 if (!ss.s)
3856 return false;
3857 if (ss.dpl != ss_rpl) /* DPL != RPL */
3858 return false;
3859 if (!ss.present)
3860 return false;
3861
3862 return true;
3863}
3864
3865static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3866{
3867 struct kvm_segment var;
3868 unsigned int rpl;
3869
3870 vmx_get_segment(vcpu, &var, seg);
3871 rpl = var.selector & SELECTOR_RPL_MASK;
3872
1872a3f4
AK		 3873 if (var.unusable)
3874 return true;
648dfaa7
MG		 3875 if (!var.s)
3876 return false;
3877 if (!var.present)
3878 return false;
3879 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3880 if (var.dpl < rpl) /* DPL < RPL */
3881 return false;
3882 }
3883
3884 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3885 * rights flags
3886 */
3887 return true;
3888}
3889
3890static bool tr_valid(struct kvm_vcpu *vcpu)
3891{
3892 struct kvm_segment tr;
3893
3894 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3895
1872a3f4
AK		 3896 if (tr.unusable)
3897 return false;
648dfaa7
MG		 3898 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3899 return false;
1872a3f4 3900 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3901 return false;
3902 if (!tr.present)
3903 return false;
3904
3905 return true;
3906}
3907
3908static bool ldtr_valid(struct kvm_vcpu *vcpu)
3909{
3910 struct kvm_segment ldtr;
3911
3912 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3913
1872a3f4
AK		 3914 if (ldtr.unusable)
3915 return true;
648dfaa7
MG		 3916 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3917 return false;
3918 if (ldtr.type != 2)
3919 return false;
3920 if (!ldtr.present)
3921 return false;
3922
3923 return true;
3924}
3925
3926static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3927{
3928 struct kvm_segment cs, ss;
3929
3930 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3931 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3932
3933 return ((cs.selector & SELECTOR_RPL_MASK) ==
3934 (ss.selector & SELECTOR_RPL_MASK));
3935}
3936
3937/*
3938 * Check if guest state is valid. Returns true if valid, false if
3939 * not.
3940 * We assume that registers are always usable
3941 */
3942static bool guest_state_valid(struct kvm_vcpu *vcpu)
3943{
c5e97c80
GN		 3944 if (enable_unrestricted_guest)
3945 return true;
3946
648dfaa7 3947 /* real mode guest state checks */
f13882d8 3948 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3949 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3950 return false;
3951 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3952 return false;
3953 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3954 return false;
3955 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3956 return false;
3957 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3958 return false;
3959 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3960 return false;
3961 } else {
3962 /* protected mode guest state checks */
3963 if (!cs_ss_rpl_check(vcpu))
3964 return false;
3965 if (!code_segment_valid(vcpu))
3966 return false;
3967 if (!stack_segment_valid(vcpu))
3968 return false;
3969 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3970 return false;
3971 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3972 return false;
3973 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3974 return false;
3975 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3976 return false;
3977 if (!tr_valid(vcpu))
3978 return false;
3979 if (!ldtr_valid(vcpu))
3980 return false;
3981 }
3982 /* TODO:
3983 * - Add checks on RIP
3984 * - Add checks on RFLAGS
3985 */
3986
3987 return true;
3988}
3989
d77c26fc 3990static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3991{
40dcaa9f 3992 gfn_t fn;
195aefde 3993 u16 data = 0;
1f755a82 3994 int idx, r;
6aa8b732 3995
40dcaa9f 3996 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3997 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3998 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3999 if (r < 0)
10589a46 4000 goto out;
195aefde 4001 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4002 r = kvm_write_guest_page(kvm, fn++, &data,
4003 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4004 if (r < 0)
10589a46 4005 goto out;
195aefde
IE		 4006 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4007 if (r < 0)
10589a46 4008 goto out;
195aefde
IE		 4009 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4010 if (r < 0)
10589a46 4011 goto out;
195aefde 4012 data = ~0;
10589a46
MT		 4013 r = kvm_write_guest_page(kvm, fn, &data,
4014 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4015 sizeof(u8));
10589a46 4016out:
40dcaa9f 4017 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4018 return r;
6aa8b732
AK		 4019}
4020
b7ebfb05
SY		 4021static int init_rmode_identity_map(struct kvm *kvm)
4022{
f51770ed 4023 int i, idx, r = 0;
b7ebfb05
SY		 4024 pfn_t identity_map_pfn;
4025 u32 tmp;
4026
089d034e 4027 if (!enable_ept)
f51770ed 4028 return 0;
a255d479
TC		 4029
4030 /* Protect kvm->arch.ept_identity_pagetable_done. */
4031 mutex_lock(&kvm->slots_lock);
4032
f51770ed 4033 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4034 goto out2;
a255d479 4035
b927a3ce 4036 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4037
4038 r = alloc_identity_pagetable(kvm);
f51770ed 4039 if (r < 0)
a255d479
TC		 4040 goto out2;
4041
40dcaa9f 4042 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4043 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4044 if (r < 0)
4045 goto out;
4046 /* Set up identity-mapping pagetable for EPT in real mode */
4047 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4048 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4049 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4050 r = kvm_write_guest_page(kvm, identity_map_pfn,
4051 &tmp, i * sizeof(tmp), sizeof(tmp));
4052 if (r < 0)
4053 goto out;
4054 }
4055 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4056
b7ebfb05 4057out:
40dcaa9f 4058 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4059
4060out2:
4061 mutex_unlock(&kvm->slots_lock);
f51770ed 4062 return r;
b7ebfb05
SY		 4063}
4064
6aa8b732
AK		 4065static void seg_setup(int seg)
4066{
772e0318 4067 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4068 unsigned int ar;
6aa8b732
AK		 4069
4070 vmcs_write16(sf->selector, 0);
4071 vmcs_writel(sf->base, 0);
4072 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4073 ar = 0x93;
4074 if (seg == VCPU_SREG_CS)
4075 ar |= 0x08; /* code segment */
3a624e29
NK		 4076
4077 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4078}
4079
f78e0e2e
SY		 4080static int alloc_apic_access_page(struct kvm *kvm)
4081{
4484141a 4082 struct page *page;
f78e0e2e
SY		 4083 struct kvm_userspace_memory_region kvm_userspace_mem;
4084 int r = 0;
4085
79fac95e 4086 mutex_lock(&kvm->slots_lock);
c24ae0dc 4087 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4088 goto out;
4089 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4090 kvm_userspace_mem.flags = 0;
73a6d941 4091 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4092 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4093 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4094 if (r)
4095 goto out;
72dc67a6 4096
73a6d941 4097 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4098 if (is_error_page(page)) {
4099 r = -EFAULT;
4100 goto out;
4101 }
4102
c24ae0dc
TC		 4103 /*
4104 * Do not pin the page in memory, so that memory hot-unplug
4105 * is able to migrate it.
4106 */
4107 put_page(page);
4108 kvm->arch.apic_access_page_done = true;
f78e0e2e 4109out:
79fac95e 4110 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4111 return r;
4112}
4113
b7ebfb05
SY		 4114static int alloc_identity_pagetable(struct kvm *kvm)
4115{
a255d479
TC		 4116 /* Called with kvm->slots_lock held. */
4117
b7ebfb05
SY		 4118 struct kvm_userspace_memory_region kvm_userspace_mem;
4119 int r = 0;
4120
a255d479
TC		 4121 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4122
b7ebfb05
SY		 4123 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4124 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4125 kvm_userspace_mem.guest_phys_addr =
4126 kvm->arch.ept_identity_map_addr;
b7ebfb05 4127 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4128 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4129
b7ebfb05
SY		 4130 return r;
4131}
4132
2384d2b3
SY		 4133static void allocate_vpid(struct vcpu_vmx *vmx)
4134{
4135 int vpid;
4136
4137 vmx->vpid = 0;
919818ab 4138 if (!enable_vpid)
2384d2b3
SY		 4139 return;
4140 spin_lock(&vmx_vpid_lock);
4141 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4142 if (vpid < VMX_NR_VPIDS) {
4143 vmx->vpid = vpid;
4144 __set_bit(vpid, vmx_vpid_bitmap);
4145 }
4146 spin_unlock(&vmx_vpid_lock);
4147}
4148
cdbecfc3
LJ		 4149static void free_vpid(struct vcpu_vmx *vmx)
4150{
4151 if (!enable_vpid)
4152 return;
4153 spin_lock(&vmx_vpid_lock);
4154 if (vmx->vpid != 0)
4155 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4156 spin_unlock(&vmx_vpid_lock);
4157}
4158
8d14695f
YZ		 4159#define MSR_TYPE_R 1
4160#define MSR_TYPE_W 2
4161static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4162 u32 msr, int type)
25c5f225 4163{
3e7c73e9 4164 int f = sizeof(unsigned long);
25c5f225
SY		 4165
4166 if (!cpu_has_vmx_msr_bitmap())
4167 return;
4168
4169 /*
4170 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4171 * have the write-low and read-high bitmap offsets the wrong way round.
4172 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4173 */
25c5f225 4174 if (msr <= 0x1fff) {
8d14695f
YZ		 4175 if (type & MSR_TYPE_R)
4176 /* read-low */
4177 __clear_bit(msr, msr_bitmap + 0x000 / f);
4178
4179 if (type & MSR_TYPE_W)
4180 /* write-low */
4181 __clear_bit(msr, msr_bitmap + 0x800 / f);
4182
25c5f225
SY		 4183 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4184 msr &= 0x1fff;
8d14695f
YZ		 4185 if (type & MSR_TYPE_R)
4186 /* read-high */
4187 __clear_bit(msr, msr_bitmap + 0x400 / f);
4188
4189 if (type & MSR_TYPE_W)
4190 /* write-high */
4191 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4192
4193 }
4194}
4195
4196static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4197 u32 msr, int type)
4198{
4199 int f = sizeof(unsigned long);
4200
4201 if (!cpu_has_vmx_msr_bitmap())
4202 return;
4203
4204 /*
4205 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4206 * have the write-low and read-high bitmap offsets the wrong way round.
4207 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4208 */
4209 if (msr <= 0x1fff) {
4210 if (type & MSR_TYPE_R)
4211 /* read-low */
4212 __set_bit(msr, msr_bitmap + 0x000 / f);
4213
4214 if (type & MSR_TYPE_W)
4215 /* write-low */
4216 __set_bit(msr, msr_bitmap + 0x800 / f);
4217
4218 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4219 msr &= 0x1fff;
4220 if (type & MSR_TYPE_R)
4221 /* read-high */
4222 __set_bit(msr, msr_bitmap + 0x400 / f);
4223
4224 if (type & MSR_TYPE_W)
4225 /* write-high */
4226 __set_bit(msr, msr_bitmap + 0xc00 / f);
4227
25c5f225 4228 }
25c5f225
SY		 4229}
4230
f2b93280
WV		 4231/*
4232 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4233 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4234 */
4235static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4236 unsigned long *msr_bitmap_nested,
4237 u32 msr, int type)
4238{
4239 int f = sizeof(unsigned long);
4240
4241 if (!cpu_has_vmx_msr_bitmap()) {
4242 WARN_ON(1);
4243 return;
4244 }
4245
4246 /*
4247 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4248 * have the write-low and read-high bitmap offsets the wrong way round.
4249 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4250 */
4251 if (msr <= 0x1fff) {
4252 if (type & MSR_TYPE_R &&
4253 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4254 /* read-low */
4255 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4256
4257 if (type & MSR_TYPE_W &&
4258 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4259 /* write-low */
4260 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4261
4262 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4263 msr &= 0x1fff;
4264 if (type & MSR_TYPE_R &&
4265 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4266 /* read-high */
4267 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4268
4269 if (type & MSR_TYPE_W &&
4270 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4271 /* write-high */
4272 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4273
4274 }
4275}
4276
5897297b
AK		 4277static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4278{
4279 if (!longmode_only)
8d14695f
YZ		 4280 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4281 msr, MSR_TYPE_R | MSR_TYPE_W);
4282 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4283 msr, MSR_TYPE_R | MSR_TYPE_W);
4284}
4285
4286static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4287{
4288 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4289 msr, MSR_TYPE_R);
4290 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4291 msr, MSR_TYPE_R);
4292}
4293
4294static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4295{
4296 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4297 msr, MSR_TYPE_R);
4298 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4299 msr, MSR_TYPE_R);
4300}
4301
4302static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4303{
4304 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4305 msr, MSR_TYPE_W);
4306 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4307 msr, MSR_TYPE_W);
5897297b
AK		 4308}
4309
01e439be
YZ		 4310static int vmx_vm_has_apicv(struct kvm *kvm)
4311{
4312 return enable_apicv && irqchip_in_kernel(kvm);
4313}
4314
a20ed54d
YZ		 4315/*
4316 * Send interrupt to vcpu via posted interrupt way.
4317 * 1. If target vcpu is running(non-root mode), send posted interrupt
4318 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4319 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4320 * interrupt from PIR in next vmentry.
4321 */
4322static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4323{
4324 struct vcpu_vmx *vmx = to_vmx(vcpu);
4325 int r;
4326
4327 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4328 return;
4329
4330 r = pi_test_and_set_on(&vmx->pi_desc);
4331 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4332#ifdef CONFIG_SMP
a20ed54d
YZ		 4333 if (!r && (vcpu->mode == IN_GUEST_MODE))
4334 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4335 POSTED_INTR_VECTOR);
4336 else
6ffbbbba 4337#endif
a20ed54d
YZ		 4338 kvm_vcpu_kick(vcpu);
4339}
4340
4341static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4342{
4343 struct vcpu_vmx *vmx = to_vmx(vcpu);
4344
4345 if (!pi_test_and_clear_on(&vmx->pi_desc))
4346 return;
4347
4348 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4349}
4350
4351static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4352{
4353 return;
4354}
4355
a3a8ff8e
NHE		 4356/*
4357 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4358 * will not change in the lifetime of the guest.
4359 * Note that host-state that does change is set elsewhere. E.g., host-state
4360 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4361 */
a547c6db 4362static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4363{
4364 u32 low32, high32;
4365 unsigned long tmpl;
4366 struct desc_ptr dt;
d974baa3 4367 unsigned long cr4;
a3a8ff8e 4368
b1a74bf8 4369 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4370 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4371
d974baa3
AL		 4372 /* Save the most likely value for this task's CR4 in the VMCS. */
4373 cr4 = read_cr4();
4374 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4375 vmx->host_state.vmcs_host_cr4 = cr4;
4376
a3a8ff8e 4377 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4378#ifdef CONFIG_X86_64
4379 /*
4380 * Load null selectors, so we can avoid reloading them in
4381 * __vmx_load_host_state(), in case userspace uses the null selectors
4382 * too (the expected case).
4383 */
4384 vmcs_write16(HOST_DS_SELECTOR, 0);
4385 vmcs_write16(HOST_ES_SELECTOR, 0);
4386#else
a3a8ff8e
NHE		 4387 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4388 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4389#endif
a3a8ff8e
NHE		 4390 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4391 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4392
4393 native_store_idt(&dt);
4394 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4395 vmx->host_idt_base = dt.address;
a3a8ff8e 4396
83287ea4 4397 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4398
4399 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4400 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4401 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4402 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4403
4404 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4405 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4406 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4407 }
4408}
4409
bf8179a0
NHE		 4410static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4411{
4412 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4413 if (enable_ept)
4414 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4415 if (is_guest_mode(&vmx->vcpu))
4416 vmx->vcpu.arch.cr4_guest_owned_bits &=
4417 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4418 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4419}
4420
01e439be
YZ		 4421static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4422{
4423 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4424
4425 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4426 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4427 return pin_based_exec_ctrl;
4428}
4429
bf8179a0
NHE		 4430static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4431{
4432 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4433
4434 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4435 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4436
bf8179a0
NHE		 4437 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4438 exec_control &= ~CPU_BASED_TPR_SHADOW;
4439#ifdef CONFIG_X86_64
4440 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4441 CPU_BASED_CR8_LOAD_EXITING;
4442#endif
4443 }
4444 if (!enable_ept)
4445 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4446 CPU_BASED_CR3_LOAD_EXITING |
4447 CPU_BASED_INVLPG_EXITING;
4448 return exec_control;
4449}
4450
4451static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4452{
4453 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4454 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4455 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4456 if (vmx->vpid == 0)
4457 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4458 if (!enable_ept) {
4459 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4460 enable_unrestricted_guest = 0;
ad756a16
MJ		 4461 /* Enable INVPCID for non-ept guests may cause performance regression. */
4462 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4463 }
4464 if (!enable_unrestricted_guest)
4465 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4466 if (!ple_gap)
4467 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4468 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4469 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4470 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4471 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4472 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4473 (handle_vmptrld).
4474 We can NOT enable shadow_vmcs here because we don't have yet
4475 a current VMCS12
4476 */
4477 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4478 /* PML is enabled/disabled in creating/destorying vcpu */
4479 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4480
bf8179a0
NHE		 4481 return exec_control;
4482}
4483
ce88decf
XG		 4484static void ept_set_mmio_spte_mask(void)
4485{
4486 /*
4487 * EPT Misconfigurations can be generated if the value of bits 2:0
4488 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4489 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4490 * spte.
4491 */
885032b9 4492 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4493}
4494
f53cd63c 4495#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4496/*
4497 * Sets up the vmcs for emulated real mode.
4498 */
8b9cf98c 4499static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4500{
2e4ce7f5 4501#ifdef CONFIG_X86_64
6aa8b732 4502 unsigned long a;
2e4ce7f5 4503#endif
6aa8b732 4504 int i;
6aa8b732 4505
6aa8b732 4506 /* I/O */
3e7c73e9
AK		 4507 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4508 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4509
4607c2d7
AG		 4510 if (enable_shadow_vmcs) {
4511 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4512 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4513 }
25c5f225 4514 if (cpu_has_vmx_msr_bitmap())
5897297b 4515 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4516
6aa8b732
AK		 4517 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4518
6aa8b732 4519 /* Control */
01e439be 4520 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4521
bf8179a0 4522 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4523
83ff3b9d 4524 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4525 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4526 vmx_secondary_exec_control(vmx));
83ff3b9d 4527 }
f78e0e2e 4528
01e439be 4529 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4530 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4531 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4532 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4533 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4534
4535 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4536
4537 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4538 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4539 }
4540
4b8d54f9
ZE		 4541 if (ple_gap) {
4542 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4543 vmx->ple_window = ple_window;
4544 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4545 }
4546
c3707958
XG		 4547 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4548 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4549 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4550
9581d442
AK		 4551 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4552 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4553 vmx_set_constant_host_state(vmx);
05b3e0c2 4554#ifdef CONFIG_X86_64
6aa8b732
AK		 4555 rdmsrl(MSR_FS_BASE, a);
4556 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4557 rdmsrl(MSR_GS_BASE, a);
4558 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4559#else
4560 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4561 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4562#endif
4563
2cc51560
ED		 4564 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4565 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4566 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4567 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4568 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4569
468d472f 4570 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4571 u32 msr_low, msr_high;
4572 u64 host_pat;
468d472f
SY		 4573 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4574 host_pat = msr_low | ((u64) msr_high << 32);
4575 /* Write the default value follow host pat */
4576 vmcs_write64(GUEST_IA32_PAT, host_pat);
4577 /* Keep arch.pat sync with GUEST_IA32_PAT */
4578 vmx->vcpu.arch.pat = host_pat;
4579 }
4580
03916db9 4581 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4582 u32 index = vmx_msr_index[i];
4583 u32 data_low, data_high;
a2fa3e9f 4584 int j = vmx->nmsrs;
6aa8b732
AK		 4585
4586 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4587 continue;
432bd6cb
AK		 4588 if (wrmsr_safe(index, data_low, data_high) < 0)
4589 continue;
26bb0981
AK		 4590 vmx->guest_msrs[j].index = i;
4591 vmx->guest_msrs[j].data = 0;
d5696725 4592 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4593 ++vmx->nmsrs;
6aa8b732 4594 }
6aa8b732 4595
2961e876
GN		 4596
4597 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4598
4599 /* 22.2.1, 20.8.1 */
2961e876 4600 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4601
e00c8cf2 4602 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4603 set_cr4_guest_host_mask(vmx);
e00c8cf2 4604
f53cd63c
WL		 4605 if (vmx_xsaves_supported())
4606 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4607
e00c8cf2
AK		 4608 return 0;
4609}
4610
57f252f2 4611static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4612{
4613 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4614 struct msr_data apic_base_msr;
e00c8cf2 4615
7ffd92c5 4616 vmx->rmode.vm86_active = 0;
e00c8cf2 4617
3b86cd99
JK		 4618 vmx->soft_vnmi_blocked = 0;
4619
ad312c7c 4620 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4621 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4622 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4623 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4624 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4625 apic_base_msr.host_initiated = true;
4626 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4627
2fb92db1
AK		 4628 vmx_segment_cache_clear(vmx);
4629
5706be0d 4630 seg_setup(VCPU_SREG_CS);
66450a21 4631 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4632 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4633
4634 seg_setup(VCPU_SREG_DS);
4635 seg_setup(VCPU_SREG_ES);
4636 seg_setup(VCPU_SREG_FS);
4637 seg_setup(VCPU_SREG_GS);
4638 seg_setup(VCPU_SREG_SS);
4639
4640 vmcs_write16(GUEST_TR_SELECTOR, 0);
4641 vmcs_writel(GUEST_TR_BASE, 0);
4642 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4643 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4644
4645 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4646 vmcs_writel(GUEST_LDTR_BASE, 0);
4647 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4648 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4649
4650 vmcs_write32(GUEST_SYSENTER_CS, 0);
4651 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4652 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4653
4654 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4655 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4656
e00c8cf2
AK		 4657 vmcs_writel(GUEST_GDTR_BASE, 0);
4658 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4659
4660 vmcs_writel(GUEST_IDTR_BASE, 0);
4661 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4662
443381a8 4663 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4664 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4665 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4666
e00c8cf2
AK		 4667 /* Special registers */
4668 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4669
4670 setup_msrs(vmx);
4671
6aa8b732
AK		 4672 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4673
f78e0e2e
SY		 4674 if (cpu_has_vmx_tpr_shadow()) {
4675 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4676 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4677 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4678 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4679 vmcs_write32(TPR_THRESHOLD, 0);
4680 }
4681
a73896cb 4682 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4683
01e439be
YZ		 4684 if (vmx_vm_has_apicv(vcpu->kvm))
4685 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4686
2384d2b3
SY		 4687 if (vmx->vpid != 0)
4688 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4689
fa40052c 4690 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4691 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4692 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4693 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4694 vmx_fpu_activate(&vmx->vcpu);
4695 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4696
b9d762fa 4697 vpid_sync_context(vmx);
6aa8b732
AK		 4698}
4699
b6f1250e
NHE		 4700/*
4701 * In nested virtualization, check if L1 asked to exit on external interrupts.
4702 * For most existing hypervisors, this will always return true.
4703 */
4704static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4705{
4706 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4707 PIN_BASED_EXT_INTR_MASK;
4708}
4709
77b0f5d6
BD		 4710/*
4711 * In nested virtualization, check if L1 has set
4712 * VM_EXIT_ACK_INTR_ON_EXIT
4713 */
4714static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4715{
4716 return get_vmcs12(vcpu)->vm_exit_controls &
4717 VM_EXIT_ACK_INTR_ON_EXIT;
4718}
4719
ea8ceb83
JK		 4720static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4721{
4722 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4723 PIN_BASED_NMI_EXITING;
4724}
4725
c9a7953f 4726static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4727{
4728 u32 cpu_based_vm_exec_control;
730dca42 4729
3b86cd99
JK		 4730 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4731 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4732 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4733}
4734
c9a7953f 4735static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4736{
4737 u32 cpu_based_vm_exec_control;
4738
c9a7953f
JK		 4739 if (!cpu_has_virtual_nmis() ||
4740 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4741 enable_irq_window(vcpu);
4742 return;
4743 }
3b86cd99
JK		 4744
4745 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4746 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4747 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4748}
4749
66fd3f7f 4750static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4751{
9c8cba37 4752 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4753 uint32_t intr;
4754 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4755
229456fc 4756 trace_kvm_inj_virq(irq);
2714d1d3 4757
fa89a817 4758 ++vcpu->stat.irq_injections;
7ffd92c5 4759 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4760 int inc_eip = 0;
4761 if (vcpu->arch.interrupt.soft)
4762 inc_eip = vcpu->arch.event_exit_inst_len;
4763 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4764 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4765 return;
4766 }
66fd3f7f
GN		 4767 intr = irq | INTR_INFO_VALID_MASK;
4768 if (vcpu->arch.interrupt.soft) {
4769 intr |= INTR_TYPE_SOFT_INTR;
4770 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4771 vmx->vcpu.arch.event_exit_inst_len);
4772 } else
4773 intr |= INTR_TYPE_EXT_INTR;
4774 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4775}
4776
f08864b4
SY		 4777static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4778{
66a5a347
JK		 4779 struct vcpu_vmx *vmx = to_vmx(vcpu);
4780
0b6ac343
NHE		 4781 if (is_guest_mode(vcpu))
4782 return;
4783
3b86cd99
JK		 4784 if (!cpu_has_virtual_nmis()) {
4785 /*
4786 * Tracking the NMI-blocked state in software is built upon
4787 * finding the next open IRQ window. This, in turn, depends on
4788 * well-behaving guests: They have to keep IRQs disabled at
4789 * least as long as the NMI handler runs. Otherwise we may
4790 * cause NMI nesting, maybe breaking the guest. But as this is
4791 * highly unlikely, we can live with the residual risk.
4792 */
4793 vmx->soft_vnmi_blocked = 1;
4794 vmx->vnmi_blocked_time = 0;
4795 }
4796
487b391d 4797 ++vcpu->stat.nmi_injections;
9d58b931 4798 vmx->nmi_known_unmasked = false;
7ffd92c5 4799 if (vmx->rmode.vm86_active) {
71f9833b 4800 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4801 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4802 return;
4803 }
f08864b4
SY		 4804 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4805 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4806}
4807
3cfc3092
JK		 4808static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4809{
4810 if (!cpu_has_virtual_nmis())
4811 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4812 if (to_vmx(vcpu)->nmi_known_unmasked)
4813 return false;
c332c83a 4814 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4815}
4816
4817static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4818{
4819 struct vcpu_vmx *vmx = to_vmx(vcpu);
4820
4821 if (!cpu_has_virtual_nmis()) {
4822 if (vmx->soft_vnmi_blocked != masked) {
4823 vmx->soft_vnmi_blocked = masked;
4824 vmx->vnmi_blocked_time = 0;
4825 }
4826 } else {
9d58b931 4827 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4828 if (masked)
4829 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4830 GUEST_INTR_STATE_NMI);
4831 else
4832 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4833 GUEST_INTR_STATE_NMI);
4834 }
4835}
4836
2505dc9f
JK		 4837static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4838{
b6b8a145
JK		 4839 if (to_vmx(vcpu)->nested.nested_run_pending)
4840 return 0;
ea8ceb83 4841
2505dc9f
JK		 4842 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4843 return 0;
4844
4845 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4846 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4847 | GUEST_INTR_STATE_NMI));
4848}
4849
78646121
GN		 4850static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4851{
b6b8a145
JK		 4852 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4853 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4854 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4855 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4856}
4857
cbc94022
IE		 4858static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4859{
4860 int ret;
4861 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4862 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4863 .guest_phys_addr = addr,
4864 .memory_size = PAGE_SIZE * 3,
4865 .flags = 0,
4866 };
4867
47ae31e2 4868 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4869 if (ret)
4870 return ret;
bfc6d222 4871 kvm->arch.tss_addr = addr;
1f755a82 4872 return init_rmode_tss(kvm);
cbc94022
IE		 4873}
4874
0ca1b4f4 4875static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4876{
77ab6db0 4877 switch (vec) {
77ab6db0 4878 case BP_VECTOR:
c573cd22
JK		 4879 /*
4880 * Update instruction length as we may reinject the exception
4881 * from user space while in guest debugging mode.
4882 */
4883 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4884 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4885 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4886 return false;
4887 /* fall through */
4888 case DB_VECTOR:
4889 if (vcpu->guest_debug &
4890 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4891 return false;
d0bfb940
JK		 4892 /* fall through */
4893 case DE_VECTOR:
77ab6db0
JK		 4894 case OF_VECTOR:
4895 case BR_VECTOR:
4896 case UD_VECTOR:
4897 case DF_VECTOR:
4898 case SS_VECTOR:
4899 case GP_VECTOR:
4900 case MF_VECTOR:
0ca1b4f4
GN		 4901 return true;
4902 break;
77ab6db0 4903 }
0ca1b4f4
GN		 4904 return false;
4905}
4906
4907static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4908 int vec, u32 err_code)
4909{
4910 /*
4911 * Instruction with address size override prefix opcode 0x67
4912 * Cause the #SS fault with 0 error code in VM86 mode.
4913 */
4914 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4915 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4916 if (vcpu->arch.halt_request) {
4917 vcpu->arch.halt_request = 0;
4918 return kvm_emulate_halt(vcpu);
4919 }
4920 return 1;
4921 }
4922 return 0;
4923 }
4924
4925 /*
4926 * Forward all other exceptions that are valid in real mode.
4927 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4928 * the required debugging infrastructure rework.
4929 */
4930 kvm_queue_exception(vcpu, vec);
4931 return 1;
6aa8b732
AK		 4932}
4933
a0861c02
AK		 4934/*
4935 * Trigger machine check on the host. We assume all the MSRs are already set up
4936 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4937 * We pass a fake environment to the machine check handler because we want
4938 * the guest to be always treated like user space, no matter what context
4939 * it used internally.
4940 */
4941static void kvm_machine_check(void)
4942{
4943#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4944 struct pt_regs regs = {
4945 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4946 .flags = X86_EFLAGS_IF,
4947 };
4948
4949 do_machine_check(&regs, 0);
4950#endif
4951}
4952
851ba692 4953static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4954{
4955 /* already handled by vcpu_run */
4956 return 1;
4957}
4958
851ba692 4959static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4960{
1155f76a 4961 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4962 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4963 u32 intr_info, ex_no, error_code;
42dbaa5a 4964 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4965 u32 vect_info;
4966 enum emulation_result er;
4967
1155f76a 4968 vect_info = vmx->idt_vectoring_info;
88786475 4969 intr_info = vmx->exit_intr_info;
6aa8b732 4970
a0861c02 4971 if (is_machine_check(intr_info))
851ba692 4972 return handle_machine_check(vcpu);
a0861c02 4973
e4a41889 4974 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4975 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4976
4977 if (is_no_device(intr_info)) {
5fd86fcf 4978 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4979 return 1;
4980 }
4981
7aa81cc0 4982 if (is_invalid_opcode(intr_info)) {
51d8b661 4983 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4984 if (er != EMULATE_DONE)
7ee5d940 4985 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4986 return 1;
4987 }
4988
6aa8b732 4989 error_code = 0;
2e11384c 4990 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4991 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4992
4993 /*
4994 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4995 * MMIO, it is better to report an internal error.
4996 * See the comments in vmx_handle_exit.
4997 */
4998 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4999 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5000 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5001 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5002 vcpu->run->internal.ndata = 2;
5003 vcpu->run->internal.data[0] = vect_info;
5004 vcpu->run->internal.data[1] = intr_info;
5005 return 0;
5006 }
5007
6aa8b732 5008 if (is_page_fault(intr_info)) {
1439442c 5009 /* EPT won't cause page fault directly */
cf3ace79 5010 BUG_ON(enable_ept);
6aa8b732 5011 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5012 trace_kvm_page_fault(cr2, error_code);
5013
3298b75c 5014 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5015 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5016 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5017 }
5018
d0bfb940 5019 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5020
5021 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5022 return handle_rmode_exception(vcpu, ex_no, error_code);
5023
42dbaa5a
JK		 5024 switch (ex_no) {
5025 case DB_VECTOR:
5026 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5027 if (!(vcpu->guest_debug &
5028 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5029 vcpu->arch.dr6 &= ~15;
6f43ed01 5030 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5031 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5032 skip_emulated_instruction(vcpu);
5033
42dbaa5a
JK		 5034 kvm_queue_exception(vcpu, DB_VECTOR);
5035 return 1;
5036 }
5037 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5038 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5039 /* fall through */
5040 case BP_VECTOR:
c573cd22
JK		 5041 /*
5042 * Update instruction length as we may reinject #BP from
5043 * user space while in guest debugging mode. Reading it for
5044 * #DB as well causes no harm, it is not used in that case.
5045 */
5046 vmx->vcpu.arch.event_exit_inst_len =
5047 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5048 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5049 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5050 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5051 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5052 break;
5053 default:
d0bfb940
JK		 5054 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5055 kvm_run->ex.exception = ex_no;
5056 kvm_run->ex.error_code = error_code;
42dbaa5a 5057 break;
6aa8b732 5058 }
6aa8b732
AK		 5059 return 0;
5060}
5061
851ba692 5062static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5063{
1165f5fe 5064 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5065 return 1;
5066}
5067
851ba692 5068static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5069{
851ba692 5070 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5071 return 0;
5072}
6aa8b732 5073
851ba692 5074static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5075{
bfdaab09 5076 unsigned long exit_qualification;
34c33d16 5077 int size, in, string;
039576c0 5078 unsigned port;
6aa8b732 5079
bfdaab09 5080 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5081 string = (exit_qualification & 16) != 0;
cf8f70bf 5082 in = (exit_qualification & 8) != 0;
e70669ab 5083
cf8f70bf 5084 ++vcpu->stat.io_exits;
e70669ab 5085
cf8f70bf 5086 if (string || in)
51d8b661 5087 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5088
cf8f70bf
GN		 5089 port = exit_qualification >> 16;
5090 size = (exit_qualification & 7) + 1;
e93f36bc 5091 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5092
5093 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5094}
5095
102d8325
IM		 5096static void
5097vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5098{
5099 /*
5100 * Patch in the VMCALL instruction:
5101 */
5102 hypercall[0] = 0x0f;
5103 hypercall[1] = 0x01;
5104 hypercall[2] = 0xc1;
102d8325
IM		 5105}
5106
b9c237bb 5107static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5108{
5109 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5110 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5111
b9c237bb 5112 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5113 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5114 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5115 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5116 return (val & always_on) == always_on;
5117}
5118
0fa06071 5119/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5120static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5121{
eeadf9e7 5122 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5123 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5124 unsigned long orig_val = val;
5125
eeadf9e7
NHE		 5126 /*
5127 * We get here when L2 changed cr0 in a way that did not change
5128 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5129 * but did change L0 shadowed bits. So we first calculate the
5130 * effective cr0 value that L1 would like to write into the
5131 * hardware. It consists of the L2-owned bits from the new
5132 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5133 */
1a0d74e6
JK		 5134 val = (val & ~vmcs12->cr0_guest_host_mask) |
5135 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5136
b9c237bb 5137 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5138 return 1;
1a0d74e6
JK		 5139
5140 if (kvm_set_cr0(vcpu, val))
5141 return 1;
5142 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5143 return 0;
1a0d74e6
JK		 5144 } else {
5145 if (to_vmx(vcpu)->nested.vmxon &&
5146 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5147 return 1;
eeadf9e7 5148 return kvm_set_cr0(vcpu, val);
1a0d74e6 5149 }
eeadf9e7
NHE		 5150}
5151
5152static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5153{
5154 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5155 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5156 unsigned long orig_val = val;
5157
5158 /* analogously to handle_set_cr0 */
5159 val = (val & ~vmcs12->cr4_guest_host_mask) |
5160 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5161 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5162 return 1;
1a0d74e6 5163 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5164 return 0;
5165 } else
5166 return kvm_set_cr4(vcpu, val);
5167}
5168
5169/* called to set cr0 as approriate for clts instruction exit. */
5170static void handle_clts(struct kvm_vcpu *vcpu)
5171{
5172 if (is_guest_mode(vcpu)) {
5173 /*
5174 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5175 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5176 * just pretend it's off (also in arch.cr0 for fpu_activate).
5177 */
5178 vmcs_writel(CR0_READ_SHADOW,
5179 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5180 vcpu->arch.cr0 &= ~X86_CR0_TS;
5181 } else
5182 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5183}
5184
851ba692 5185static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5186{
229456fc 5187 unsigned long exit_qualification, val;
6aa8b732
AK		 5188 int cr;
5189 int reg;
49a9b07e 5190 int err;
6aa8b732 5191
bfdaab09 5192 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5193 cr = exit_qualification & 15;
5194 reg = (exit_qualification >> 8) & 15;
5195 switch ((exit_qualification >> 4) & 3) {
5196 case 0: /* mov to cr */
1e32c079 5197 val = kvm_register_readl(vcpu, reg);
229456fc 5198 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5199 switch (cr) {
5200 case 0:
eeadf9e7 5201 err = handle_set_cr0(vcpu, val);
db8fcefa 5202 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5203 return 1;
5204 case 3:
2390218b 5205 err = kvm_set_cr3(vcpu, val);
db8fcefa 5206 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5207 return 1;
5208 case 4:
eeadf9e7 5209 err = handle_set_cr4(vcpu, val);
db8fcefa 5210 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5211 return 1;
0a5fff19
GN		 5212 case 8: {
5213 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5214 u8 cr8 = (u8)val;
eea1cff9 5215 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5216 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5217 if (irqchip_in_kernel(vcpu->kvm))
5218 return 1;
5219 if (cr8_prev <= cr8)
5220 return 1;
851ba692 5221 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5222 return 0;
5223 }
4b8073e4 5224 }
6aa8b732 5225 break;
25c4c276 5226 case 2: /* clts */
eeadf9e7 5227 handle_clts(vcpu);
4d4ec087 5228 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5229 skip_emulated_instruction(vcpu);
6b52d186 5230 vmx_fpu_activate(vcpu);
25c4c276 5231 return 1;
6aa8b732
AK		 5232 case 1: /*mov from cr*/
5233 switch (cr) {
5234 case 3:
9f8fe504
AK		 5235 val = kvm_read_cr3(vcpu);
5236 kvm_register_write(vcpu, reg, val);
5237 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5238 skip_emulated_instruction(vcpu);
5239 return 1;
5240 case 8:
229456fc
MT		 5241 val = kvm_get_cr8(vcpu);
5242 kvm_register_write(vcpu, reg, val);
5243 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5244 skip_emulated_instruction(vcpu);
5245 return 1;
5246 }
5247 break;
5248 case 3: /* lmsw */
a1f83a74 5249 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5250 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5251 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5252
5253 skip_emulated_instruction(vcpu);
5254 return 1;
5255 default:
5256 break;
5257 }
851ba692 5258 vcpu->run->exit_reason = 0;
a737f256 5259 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5260 (int)(exit_qualification >> 4) & 3, cr);
5261 return 0;
5262}
5263
851ba692 5264static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5265{
bfdaab09 5266 unsigned long exit_qualification;
16f8a6f9
NA		 5267 int dr, dr7, reg;
5268
5269 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5270 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5271
5272 /* First, if DR does not exist, trigger UD */
5273 if (!kvm_require_dr(vcpu, dr))
5274 return 1;
6aa8b732 5275
f2483415 5276 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5277 if (!kvm_require_cpl(vcpu, 0))
5278 return 1;
16f8a6f9
NA		 5279 dr7 = vmcs_readl(GUEST_DR7);
5280 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5281 /*
5282 * As the vm-exit takes precedence over the debug trap, we
5283 * need to emulate the latter, either for the host or the
5284 * guest debugging itself.
5285 */
5286 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5287 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5288 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5289 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5290 vcpu->run->debug.arch.exception = DB_VECTOR;
5291 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5292 return 0;
5293 } else {
7305eb5d 5294 vcpu->arch.dr6 &= ~15;
6f43ed01 5295 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5296 kvm_queue_exception(vcpu, DB_VECTOR);
5297 return 1;
5298 }
5299 }
5300
81908bf4
PB		 5301 if (vcpu->guest_debug == 0) {
5302 u32 cpu_based_vm_exec_control;
5303
5304 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5305 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5306 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5307
5308 /*
5309 * No more DR vmexits; force a reload of the debug registers
5310 * and reenter on this instruction. The next vmexit will
5311 * retrieve the full state of the debug registers.
5312 */
5313 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5314 return 1;
5315 }
5316
42dbaa5a
JK		 5317 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5318 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5319 unsigned long val;
4c4d563b
JK		 5320
5321 if (kvm_get_dr(vcpu, dr, &val))
5322 return 1;
5323 kvm_register_write(vcpu, reg, val);
020df079 5324 } else
5777392e 5325 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5326 return 1;
5327
6aa8b732
AK		 5328 skip_emulated_instruction(vcpu);
5329 return 1;
5330}
5331
73aaf249
JK		 5332static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5333{
5334 return vcpu->arch.dr6;
5335}
5336
5337static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5338{
5339}
5340
81908bf4
PB		 5341static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5342{
5343 u32 cpu_based_vm_exec_control;
5344
5345 get_debugreg(vcpu->arch.db[0], 0);
5346 get_debugreg(vcpu->arch.db[1], 1);
5347 get_debugreg(vcpu->arch.db[2], 2);
5348 get_debugreg(vcpu->arch.db[3], 3);
5349 get_debugreg(vcpu->arch.dr6, 6);
5350 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5351
5352 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5353
5354 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5355 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5356 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5357}
5358
020df079
GN		 5359static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5360{
5361 vmcs_writel(GUEST_DR7, val);
5362}
5363
851ba692 5364static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5365{
06465c5a
AK		 5366 kvm_emulate_cpuid(vcpu);
5367 return 1;
6aa8b732
AK		 5368}
5369
851ba692 5370static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5371{
ad312c7c 5372 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5373 u64 data;
5374
5375 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5376 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5377 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5378 return 1;
5379 }
5380
229456fc 5381 trace_kvm_msr_read(ecx, data);
2714d1d3 5382
6aa8b732 5383 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5384 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5385 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5386 skip_emulated_instruction(vcpu);
5387 return 1;
5388}
5389
851ba692 5390static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5391{
8fe8ab46 5392 struct msr_data msr;
ad312c7c
ZX		 5393 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5394 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5395 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5396
8fe8ab46
WA		 5397 msr.data = data;
5398 msr.index = ecx;
5399 msr.host_initiated = false;
854e8bb1 5400 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5401 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5402 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5403 return 1;
5404 }
5405
59200273 5406 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5407 skip_emulated_instruction(vcpu);
5408 return 1;
5409}
5410
851ba692 5411static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5412{
3842d135 5413 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5414 return 1;
5415}
5416
851ba692 5417static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5418{
85f455f7
ED		 5419 u32 cpu_based_vm_exec_control;
5420
5421 /* clear pending irq */
5422 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5423 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5424 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5425
3842d135
AK		 5426 kvm_make_request(KVM_REQ_EVENT, vcpu);
5427
a26bf12a 5428 ++vcpu->stat.irq_window_exits;
2714d1d3 5429
c1150d8c
DL		 5430 /*
5431 * If the user space waits to inject interrupts, exit as soon as
5432 * possible
5433 */
8061823a 5434 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5435 vcpu->run->request_interrupt_window &&
8061823a 5436 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5437 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5438 return 0;
5439 }
6aa8b732
AK		 5440 return 1;
5441}
5442
851ba692 5443static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5444{
5445 skip_emulated_instruction(vcpu);
d3bef15f 5446 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5447}
5448
851ba692 5449static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5450{
510043da 5451 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5452 kvm_emulate_hypercall(vcpu);
5453 return 1;
c21415e8
IM		 5454}
5455
ec25d5e6
GN		 5456static int handle_invd(struct kvm_vcpu *vcpu)
5457{
51d8b661 5458 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5459}
5460
851ba692 5461static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5462{
f9c617f6 5463 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5464
5465 kvm_mmu_invlpg(vcpu, exit_qualification);
5466 skip_emulated_instruction(vcpu);
5467 return 1;
5468}
5469
fee84b07
AK		 5470static int handle_rdpmc(struct kvm_vcpu *vcpu)
5471{
5472 int err;
5473
5474 err = kvm_rdpmc(vcpu);
5475 kvm_complete_insn_gp(vcpu, err);
5476
5477 return 1;
5478}
5479
851ba692 5480static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5481{
5482 skip_emulated_instruction(vcpu);
f5f48ee1 5483 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5484 return 1;
5485}
5486
2acf923e
DC		 5487static int handle_xsetbv(struct kvm_vcpu *vcpu)
5488{
5489 u64 new_bv = kvm_read_edx_eax(vcpu);
5490 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5491
5492 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5493 skip_emulated_instruction(vcpu);
5494 return 1;
5495}
5496
f53cd63c
WL		 5497static int handle_xsaves(struct kvm_vcpu *vcpu)
5498{
5499 skip_emulated_instruction(vcpu);
5500 WARN(1, "this should never happen\n");
5501 return 1;
5502}
5503
5504static int handle_xrstors(struct kvm_vcpu *vcpu)
5505{
5506 skip_emulated_instruction(vcpu);
5507 WARN(1, "this should never happen\n");
5508 return 1;
5509}
5510
851ba692 5511static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5512{
58fbbf26
KT		 5513 if (likely(fasteoi)) {
5514 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5515 int access_type, offset;
5516
5517 access_type = exit_qualification & APIC_ACCESS_TYPE;
5518 offset = exit_qualification & APIC_ACCESS_OFFSET;
5519 /*
5520 * Sane guest uses MOV to write EOI, with written value
5521 * not cared. So make a short-circuit here by avoiding
5522 * heavy instruction emulation.
5523 */
5524 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5525 (offset == APIC_EOI)) {
5526 kvm_lapic_set_eoi(vcpu);
5527 skip_emulated_instruction(vcpu);
5528 return 1;
5529 }
5530 }
51d8b661 5531 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5532}
5533
c7c9c56c
YZ		 5534static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5535{
5536 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5537 int vector = exit_qualification & 0xff;
5538
5539 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5540 kvm_apic_set_eoi_accelerated(vcpu, vector);
5541 return 1;
5542}
5543
83d4c286
YZ		 5544static int handle_apic_write(struct kvm_vcpu *vcpu)
5545{
5546 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5547 u32 offset = exit_qualification & 0xfff;
5548
5549 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5550 kvm_apic_write_nodecode(vcpu, offset);
5551 return 1;
5552}
5553
851ba692 5554static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5555{
60637aac 5556 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5557 unsigned long exit_qualification;
e269fb21
JK		 5558 bool has_error_code = false;
5559 u32 error_code = 0;
37817f29 5560 u16 tss_selector;
7f3d35fd 5561 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5562
5563 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5564 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5565 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5566
5567 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5568
5569 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5570 if (reason == TASK_SWITCH_GATE && idt_v) {
5571 switch (type) {
5572 case INTR_TYPE_NMI_INTR:
5573 vcpu->arch.nmi_injected = false;
654f06fc 5574 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5575 break;
5576 case INTR_TYPE_EXT_INTR:
66fd3f7f 5577 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5578 kvm_clear_interrupt_queue(vcpu);
5579 break;
5580 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5581 if (vmx->idt_vectoring_info &
5582 VECTORING_INFO_DELIVER_CODE_MASK) {
5583 has_error_code = true;
5584 error_code =
5585 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5586 }
5587 /* fall through */
64a7ec06
GN		 5588 case INTR_TYPE_SOFT_EXCEPTION:
5589 kvm_clear_exception_queue(vcpu);
5590 break;
5591 default:
5592 break;
5593 }
60637aac 5594 }
37817f29
IE		 5595 tss_selector = exit_qualification;
5596
64a7ec06
GN		 5597 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5598 type != INTR_TYPE_EXT_INTR &&
5599 type != INTR_TYPE_NMI_INTR))
5600 skip_emulated_instruction(vcpu);
5601
7f3d35fd
KW		 5602 if (kvm_task_switch(vcpu, tss_selector,
5603 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5604 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5605 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5606 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5607 vcpu->run->internal.ndata = 0;
42dbaa5a 5608 return 0;
acb54517 5609 }
42dbaa5a
JK		 5610
5611 /* clear all local breakpoint enable flags */
0e8a0996 5612 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5613
5614 /*
5615 * TODO: What about debug traps on tss switch?
5616 * Are we supposed to inject them and update dr6?
5617 */
5618
5619 return 1;
37817f29
IE		 5620}
5621
851ba692 5622static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5623{
f9c617f6 5624 unsigned long exit_qualification;
1439442c 5625 gpa_t gpa;
4f5982a5 5626 u32 error_code;
1439442c 5627 int gla_validity;
1439442c 5628
f9c617f6 5629 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5630
1439442c
SY		 5631 gla_validity = (exit_qualification >> 7) & 0x3;
5632 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5633 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5634 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5635 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5636 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5637 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5638 (long unsigned int)exit_qualification);
851ba692
AK		 5639 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5640 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5641 return 0;
1439442c
SY		 5642 }
5643
0be9c7a8
GN		 5644 /*
5645 * EPT violation happened while executing iret from NMI,
5646 * "blocked by NMI" bit has to be set before next VM entry.
5647 * There are errata that may cause this bit to not be set:
5648 * AAK134, BY25.
5649 */
bcd1c294
GN		 5650 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5651 cpu_has_virtual_nmis() &&
5652 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5653 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5654
1439442c 5655 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5656 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5657
5658 /* It is a write fault? */
81ed33e4 5659 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5660 /* It is a fetch fault? */
81ed33e4 5661 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5662 /* ept page table is present? */
81ed33e4 5663 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5664
25d92081
YZ		 5665 vcpu->arch.exit_qualification = exit_qualification;
5666
4f5982a5 5667 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5668}
5669
68f89400
MT		 5670static u64 ept_rsvd_mask(u64 spte, int level)
5671{
5672 int i;
5673 u64 mask = 0;
5674
5675 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5676 mask |= (1ULL << i);
5677
a32e8459 5678 if (level == 4)
68f89400
MT		 5679 /* bits 7:3 reserved */
5680 mask |= 0xf8;
a32e8459
WL		 5681 else if (spte & (1ULL << 7))
5682 /*
5683 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5684 * level == 1 if the hypervisor is using the ignored bit 7.
5685 */
5686 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5687 else if (level > 1)
5688 /* bits 6:3 reserved */
5689 mask |= 0x78;
68f89400
MT		 5690
5691 return mask;
5692}
5693
5694static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5695 int level)
5696{
5697 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5698
5699 /* 010b (write-only) */
5700 WARN_ON((spte & 0x7) == 0x2);
5701
5702 /* 110b (write/execute) */
5703 WARN_ON((spte & 0x7) == 0x6);
5704
5705 /* 100b (execute-only) and value not supported by logical processor */
5706 if (!cpu_has_vmx_ept_execute_only())
5707 WARN_ON((spte & 0x7) == 0x4);
5708
5709 /* not 000b */
5710 if ((spte & 0x7)) {
5711 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5712
5713 if (rsvd_bits != 0) {
5714 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5715 __func__, rsvd_bits);
5716 WARN_ON(1);
5717 }
5718
a32e8459
WL		 5719 /* bits 5:3 are _not_ reserved for large page or leaf page */
5720 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5721 u64 ept_mem_type = (spte & 0x38) >> 3;
5722
5723 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5724 ept_mem_type == 7) {
5725 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5726 __func__, ept_mem_type);
5727 WARN_ON(1);
5728 }
5729 }
5730 }
5731}
5732
851ba692 5733static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5734{
5735 u64 sptes[4];
ce88decf 5736 int nr_sptes, i, ret;
68f89400
MT		 5737 gpa_t gpa;
5738
5739 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5740 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5741 skip_emulated_instruction(vcpu);
5742 return 1;
5743 }
68f89400 5744
ce88decf 5745 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5746 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5747 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5748 EMULATE_DONE;
f8f55942
XG		 5749
5750 if (unlikely(ret == RET_MMIO_PF_INVALID))
5751 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5752
b37fbea6 5753 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5754 return 1;
5755
5756 /* It is the real ept misconfig */
68f89400
MT		 5757 printk(KERN_ERR "EPT: Misconfiguration.\n");
5758 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5759
5760 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5761
5762 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5763 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5764
851ba692
AK		 5765 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5766 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5767
5768 return 0;
5769}
5770
851ba692 5771static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5772{
5773 u32 cpu_based_vm_exec_control;
5774
5775 /* clear pending NMI */
5776 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5777 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5778 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5779 ++vcpu->stat.nmi_window_exits;
3842d135 5780 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5781
5782 return 1;
5783}
5784
80ced186 5785static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5786{
8b3079a5
AK		 5787 struct vcpu_vmx *vmx = to_vmx(vcpu);
5788 enum emulation_result err = EMULATE_DONE;
80ced186 5789 int ret = 1;
49e9d557
AK		 5790 u32 cpu_exec_ctrl;
5791 bool intr_window_requested;
b8405c18 5792 unsigned count = 130;
49e9d557
AK		 5793
5794 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5795 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5796
98eb2f8b 5797 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5798 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5799 return handle_interrupt_window(&vmx->vcpu);
5800
de87dcdd
AK		 5801 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5802 return 1;
5803
991eebf9 5804 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5805
ac0a48c3 5806 if (err == EMULATE_USER_EXIT) {
94452b9e 5807 ++vcpu->stat.mmio_exits;
80ced186
MG		 5808 ret = 0;
5809 goto out;
5810 }
1d5a4d9b 5811
de5f70e0
AK		 5812 if (err != EMULATE_DONE) {
5813 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5814 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5815 vcpu->run->internal.ndata = 0;
6d77dbfc 5816 return 0;
de5f70e0 5817 }
ea953ef0 5818
8d76c49e
GN		 5819 if (vcpu->arch.halt_request) {
5820 vcpu->arch.halt_request = 0;
5821 ret = kvm_emulate_halt(vcpu);
5822 goto out;
5823 }
5824
ea953ef0 5825 if (signal_pending(current))
80ced186 5826 goto out;
ea953ef0
MG		 5827 if (need_resched())
5828 schedule();
5829 }
5830
80ced186
MG		 5831out:
5832 return ret;
ea953ef0
MG		 5833}
5834
b4a2d31d
RK		 5835static int __grow_ple_window(int val)
5836{
5837 if (ple_window_grow < 1)
5838 return ple_window;
5839
5840 val = min(val, ple_window_actual_max);
5841
5842 if (ple_window_grow < ple_window)
5843 val *= ple_window_grow;
5844 else
5845 val += ple_window_grow;
5846
5847 return val;
5848}
5849
5850static int __shrink_ple_window(int val, int modifier, int minimum)
5851{
5852 if (modifier < 1)
5853 return ple_window;
5854
5855 if (modifier < ple_window)
5856 val /= modifier;
5857 else
5858 val -= modifier;
5859
5860 return max(val, minimum);
5861}
5862
5863static void grow_ple_window(struct kvm_vcpu *vcpu)
5864{
5865 struct vcpu_vmx *vmx = to_vmx(vcpu);
5866 int old = vmx->ple_window;
5867
5868 vmx->ple_window = __grow_ple_window(old);
5869
5870 if (vmx->ple_window != old)
5871 vmx->ple_window_dirty = true;
7b46268d
RK		 5872
5873 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5874}
5875
5876static void shrink_ple_window(struct kvm_vcpu *vcpu)
5877{
5878 struct vcpu_vmx *vmx = to_vmx(vcpu);
5879 int old = vmx->ple_window;
5880
5881 vmx->ple_window = __shrink_ple_window(old,
5882 ple_window_shrink, ple_window);
5883
5884 if (vmx->ple_window != old)
5885 vmx->ple_window_dirty = true;
7b46268d
RK		 5886
5887 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5888}
5889
5890/*
5891 * ple_window_actual_max is computed to be one grow_ple_window() below
5892 * ple_window_max. (See __grow_ple_window for the reason.)
5893 * This prevents overflows, because ple_window_max is int.
5894 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5895 * this process.
5896 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5897 */
5898static void update_ple_window_actual_max(void)
5899{
5900 ple_window_actual_max =
5901 __shrink_ple_window(max(ple_window_max, ple_window),
5902 ple_window_grow, INT_MIN);
5903}
5904
f2c7648d
TC		 5905static __init int hardware_setup(void)
5906{
34a1cd60
TC		 5907 int r = -ENOMEM, i, msr;
5908
5909 rdmsrl_safe(MSR_EFER, &host_efer);
5910
5911 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5912 kvm_define_shared_msr(i, vmx_msr_index[i]);
5913
5914 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5915 if (!vmx_io_bitmap_a)
5916 return r;
5917
5918 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5919 if (!vmx_io_bitmap_b)
5920 goto out;
5921
5922 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5923 if (!vmx_msr_bitmap_legacy)
5924 goto out1;
5925
5926 vmx_msr_bitmap_legacy_x2apic =
5927 (unsigned long *)__get_free_page(GFP_KERNEL);
5928 if (!vmx_msr_bitmap_legacy_x2apic)
5929 goto out2;
5930
5931 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5932 if (!vmx_msr_bitmap_longmode)
5933 goto out3;
5934
5935 vmx_msr_bitmap_longmode_x2apic =
5936 (unsigned long *)__get_free_page(GFP_KERNEL);
5937 if (!vmx_msr_bitmap_longmode_x2apic)
5938 goto out4;
3af18d9c
WV		 5939
5940 if (nested) {
5941 vmx_msr_bitmap_nested =
5942 (unsigned long *)__get_free_page(GFP_KERNEL);
5943 if (!vmx_msr_bitmap_nested)
5944 goto out5;
5945 }
5946
34a1cd60
TC		 5947 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5948 if (!vmx_vmread_bitmap)
3af18d9c 5949 goto out6;
34a1cd60
TC		 5950
5951 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5952 if (!vmx_vmwrite_bitmap)
3af18d9c 5953 goto out7;
34a1cd60
TC		 5954
5955 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5956 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5957
5958 /*
5959 * Allow direct access to the PC debug port (it is often used for I/O
5960 * delays, but the vmexits simply slow things down).
5961 */
5962 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5963 clear_bit(0x80, vmx_io_bitmap_a);
5964
5965 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5966
5967 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5968 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 5969 if (nested)
5970 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 5971
34a1cd60
TC		 5972 if (setup_vmcs_config(&vmcs_config) < 0) {
5973 r = -EIO;
3af18d9c 5974 goto out8;
baa03522 5975 }
f2c7648d
TC		 5976
5977 if (boot_cpu_has(X86_FEATURE_NX))
5978 kvm_enable_efer_bits(EFER_NX);
5979
5980 if (!cpu_has_vmx_vpid())
5981 enable_vpid = 0;
5982 if (!cpu_has_vmx_shadow_vmcs())
5983 enable_shadow_vmcs = 0;
5984 if (enable_shadow_vmcs)
5985 init_vmcs_shadow_fields();
5986
5987 if (!cpu_has_vmx_ept() ||
5988 !cpu_has_vmx_ept_4levels()) {
5989 enable_ept = 0;
5990 enable_unrestricted_guest = 0;
5991 enable_ept_ad_bits = 0;
5992 }
5993
5994 if (!cpu_has_vmx_ept_ad_bits())
5995 enable_ept_ad_bits = 0;
5996
5997 if (!cpu_has_vmx_unrestricted_guest())
5998 enable_unrestricted_guest = 0;
5999
ad15a296 6000 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6001 flexpriority_enabled = 0;
6002
ad15a296
PB		 6003 /*
6004 * set_apic_access_page_addr() is used to reload apic access
6005 * page upon invalidation. No need to do anything if not
6006 * using the APIC_ACCESS_ADDR VMCS field.
6007 */
6008 if (!flexpriority_enabled)
f2c7648d 6009 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6010
6011 if (!cpu_has_vmx_tpr_shadow())
6012 kvm_x86_ops->update_cr8_intercept = NULL;
6013
6014 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6015 kvm_disable_largepages();
6016
6017 if (!cpu_has_vmx_ple())
6018 ple_gap = 0;
6019
6020 if (!cpu_has_vmx_apicv())
6021 enable_apicv = 0;
6022
6023 if (enable_apicv)
6024 kvm_x86_ops->update_cr8_intercept = NULL;
6025 else {
6026 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6027 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6028 kvm_x86_ops->deliver_posted_interrupt = NULL;
6029 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6030 }
6031
baa03522
TC		 6032 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6033 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6034 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6035 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6036 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6037 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6038 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6039
6040 memcpy(vmx_msr_bitmap_legacy_x2apic,
6041 vmx_msr_bitmap_legacy, PAGE_SIZE);
6042 memcpy(vmx_msr_bitmap_longmode_x2apic,
6043 vmx_msr_bitmap_longmode, PAGE_SIZE);
6044
6045 if (enable_apicv) {
6046 for (msr = 0x800; msr <= 0x8ff; msr++)
6047 vmx_disable_intercept_msr_read_x2apic(msr);
6048
6049 /* According SDM, in x2apic mode, the whole id reg is used.
6050 * But in KVM, it only use the highest eight bits. Need to
6051 * intercept it */
6052 vmx_enable_intercept_msr_read_x2apic(0x802);
6053 /* TMCCT */
6054 vmx_enable_intercept_msr_read_x2apic(0x839);
6055 /* TPR */
6056 vmx_disable_intercept_msr_write_x2apic(0x808);
6057 /* EOI */
6058 vmx_disable_intercept_msr_write_x2apic(0x80b);
6059 /* SELF-IPI */
6060 vmx_disable_intercept_msr_write_x2apic(0x83f);
6061 }
6062
6063 if (enable_ept) {
6064 kvm_mmu_set_mask_ptes(0ull,
6065 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6066 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6067 0ull, VMX_EPT_EXECUTABLE_MASK);
6068 ept_set_mmio_spte_mask();
6069 kvm_enable_tdp();
6070 } else
6071 kvm_disable_tdp();
6072
6073 update_ple_window_actual_max();
6074
843e4330
KH		 6075 /*
6076 * Only enable PML when hardware supports PML feature, and both EPT
6077 * and EPT A/D bit features are enabled -- PML depends on them to work.
6078 */
6079 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6080 enable_pml = 0;
6081
6082 if (!enable_pml) {
6083 kvm_x86_ops->slot_enable_log_dirty = NULL;
6084 kvm_x86_ops->slot_disable_log_dirty = NULL;
6085 kvm_x86_ops->flush_log_dirty = NULL;
6086 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6087 }
6088
f2c7648d 6089 return alloc_kvm_area();
34a1cd60 6090
3af18d9c 6091out8:
34a1cd60 6092 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6093out7:
34a1cd60 6094 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6095out6:
6096 if (nested)
6097 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6098out5:
6099 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6100out4:
6101 free_page((unsigned long)vmx_msr_bitmap_longmode);
6102out3:
6103 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6104out2:
6105 free_page((unsigned long)vmx_msr_bitmap_legacy);
6106out1:
6107 free_page((unsigned long)vmx_io_bitmap_b);
6108out:
6109 free_page((unsigned long)vmx_io_bitmap_a);
6110
6111 return r;
f2c7648d
TC		 6112}
6113
6114static __exit void hardware_unsetup(void)
6115{
34a1cd60
TC		 6116 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6117 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6118 free_page((unsigned long)vmx_msr_bitmap_legacy);
6119 free_page((unsigned long)vmx_msr_bitmap_longmode);
6120 free_page((unsigned long)vmx_io_bitmap_b);
6121 free_page((unsigned long)vmx_io_bitmap_a);
6122 free_page((unsigned long)vmx_vmwrite_bitmap);
6123 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6124 if (nested)
6125 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6126
f2c7648d
TC		 6127 free_kvm_area();
6128}
6129
4b8d54f9
ZE		 6130/*
6131 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6132 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6133 */
9fb41ba8 6134static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6135{
b4a2d31d
RK		 6136 if (ple_gap)
6137 grow_ple_window(vcpu);
6138
4b8d54f9
ZE		 6139 skip_emulated_instruction(vcpu);
6140 kvm_vcpu_on_spin(vcpu);
6141
6142 return 1;
6143}
6144
87c00572 6145static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6146{
87c00572 6147 skip_emulated_instruction(vcpu);
59708670
SY		 6148 return 1;
6149}
6150
87c00572
GS		 6151static int handle_mwait(struct kvm_vcpu *vcpu)
6152{
6153 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6154 return handle_nop(vcpu);
6155}
6156
6157static int handle_monitor(struct kvm_vcpu *vcpu)
6158{
6159 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6160 return handle_nop(vcpu);
6161}
6162
ff2f6fe9
NHE		 6163/*
6164 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6165 * We could reuse a single VMCS for all the L2 guests, but we also want the
6166 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6167 * allows keeping them loaded on the processor, and in the future will allow
6168 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6169 * every entry if they never change.
6170 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6171 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6172 *
6173 * The following functions allocate and free a vmcs02 in this pool.
6174 */
6175
6176/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6177static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6178{
6179 struct vmcs02_list *item;
6180 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6181 if (item->vmptr == vmx->nested.current_vmptr) {
6182 list_move(&item->list, &vmx->nested.vmcs02_pool);
6183 return &item->vmcs02;
6184 }
6185
6186 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6187 /* Recycle the least recently used VMCS. */
6188 item = list_entry(vmx->nested.vmcs02_pool.prev,
6189 struct vmcs02_list, list);
6190 item->vmptr = vmx->nested.current_vmptr;
6191 list_move(&item->list, &vmx->nested.vmcs02_pool);
6192 return &item->vmcs02;
6193 }
6194
6195 /* Create a new VMCS */
0fa24ce3 6196 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6197 if (!item)
6198 return NULL;
6199 item->vmcs02.vmcs = alloc_vmcs();
6200 if (!item->vmcs02.vmcs) {
6201 kfree(item);
6202 return NULL;
6203 }
6204 loaded_vmcs_init(&item->vmcs02);
6205 item->vmptr = vmx->nested.current_vmptr;
6206 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6207 vmx->nested.vmcs02_num++;
6208 return &item->vmcs02;
6209}
6210
6211/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6212static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6213{
6214 struct vmcs02_list *item;
6215 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6216 if (item->vmptr == vmptr) {
6217 free_loaded_vmcs(&item->vmcs02);
6218 list_del(&item->list);
6219 kfree(item);
6220 vmx->nested.vmcs02_num--;
6221 return;
6222 }
6223}
6224
6225/*
6226 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6227 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6228 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6229 */
6230static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6231{
6232 struct vmcs02_list *item, *n;
4fa7734c
PB		 6233
6234 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6235 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6236 /*
6237 * Something will leak if the above WARN triggers. Better than
6238 * a use-after-free.
6239 */
6240 if (vmx->loaded_vmcs == &item->vmcs02)
6241 continue;
6242
6243 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6244 list_del(&item->list);
6245 kfree(item);
4fa7734c 6246 vmx->nested.vmcs02_num--;
ff2f6fe9 6247 }
ff2f6fe9
NHE		 6248}
6249
0658fbaa
ACL		 6250/*
6251 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6252 * set the success or error code of an emulated VMX instruction, as specified
6253 * by Vol 2B, VMX Instruction Reference, "Conventions".
6254 */
6255static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6256{
6257 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6258 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6259 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6260}
6261
6262static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6263{
6264 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6265 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6266 X86_EFLAGS_SF | X86_EFLAGS_OF))
6267 | X86_EFLAGS_CF);
6268}
6269
145c28dd 6270static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6271 u32 vm_instruction_error)
6272{
6273 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6274 /*
6275 * failValid writes the error number to the current VMCS, which
6276 * can't be done there isn't a current VMCS.
6277 */
6278 nested_vmx_failInvalid(vcpu);
6279 return;
6280 }
6281 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6282 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6283 X86_EFLAGS_SF | X86_EFLAGS_OF))
6284 | X86_EFLAGS_ZF);
6285 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6286 /*
6287 * We don't need to force a shadow sync because
6288 * VM_INSTRUCTION_ERROR is not shadowed
6289 */
6290}
145c28dd 6291
ff651cb6
WV		 6292static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6293{
6294 /* TODO: not to reset guest simply here. */
6295 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6296 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6297}
6298
f4124500
JK		 6299static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6300{
6301 struct vcpu_vmx *vmx =
6302 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6303
6304 vmx->nested.preemption_timer_expired = true;
6305 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6306 kvm_vcpu_kick(&vmx->vcpu);
6307
6308 return HRTIMER_NORESTART;
6309}
6310
19677e32
BD		 6311/*
6312 * Decode the memory-address operand of a vmx instruction, as recorded on an
6313 * exit caused by such an instruction (run by a guest hypervisor).
6314 * On success, returns 0. When the operand is invalid, returns 1 and throws
6315 * #UD or #GP.
6316 */
6317static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6318 unsigned long exit_qualification,
6319 u32 vmx_instruction_info, gva_t *ret)
6320{
6321 /*
6322 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6323 * Execution", on an exit, vmx_instruction_info holds most of the
6324 * addressing components of the operand. Only the displacement part
6325 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6326 * For how an actual address is calculated from all these components,
6327 * refer to Vol. 1, "Operand Addressing".
6328 */
6329 int scaling = vmx_instruction_info & 3;
6330 int addr_size = (vmx_instruction_info >> 7) & 7;
6331 bool is_reg = vmx_instruction_info & (1u << 10);
6332 int seg_reg = (vmx_instruction_info >> 15) & 7;
6333 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6334 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6335 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6336 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6337
6338 if (is_reg) {
6339 kvm_queue_exception(vcpu, UD_VECTOR);
6340 return 1;
6341 }
6342
6343 /* Addr = segment_base + offset */
6344 /* offset = base + [index * scale] + displacement */
6345 *ret = vmx_get_segment_base(vcpu, seg_reg);
6346 if (base_is_valid)
6347 *ret += kvm_register_read(vcpu, base_reg);
6348 if (index_is_valid)
6349 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6350 *ret += exit_qualification; /* holds the displacement */
6351
6352 if (addr_size == 1) /* 32 bit */
6353 *ret &= 0xffffffff;
6354
6355 /*
6356 * TODO: throw #GP (and return 1) in various cases that the VM*
6357 * instructions require it - e.g., offset beyond segment limit,
6358 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6359 * address, and so on. Currently these are not checked.
6360 */
6361 return 0;
6362}
6363
3573e22c
BD		 6364/*
6365 * This function performs the various checks including
6366 * - if it's 4KB aligned
6367 * - No bits beyond the physical address width are set
6368 * - Returns 0 on success or else 1
4291b588 6369 * (Intel SDM Section 30.3)
3573e22c 6370 */
4291b588
BD		 6371static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6372 gpa_t *vmpointer)
3573e22c
BD		 6373{
6374 gva_t gva;
6375 gpa_t vmptr;
6376 struct x86_exception e;
6377 struct page *page;
6378 struct vcpu_vmx *vmx = to_vmx(vcpu);
6379 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6380
6381 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6382 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6383 return 1;
6384
6385 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6386 sizeof(vmptr), &e)) {
6387 kvm_inject_page_fault(vcpu, &e);
6388 return 1;
6389 }
6390
6391 switch (exit_reason) {
6392 case EXIT_REASON_VMON:
6393 /*
6394 * SDM 3: 24.11.5
6395 * The first 4 bytes of VMXON region contain the supported
6396 * VMCS revision identifier
6397 *
6398 * Note - IA32_VMX_BASIC[48] will never be 1
6399 * for the nested case;
6400 * which replaces physical address width with 32
6401 *
6402 */
bc39c4db 6403 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6404 nested_vmx_failInvalid(vcpu);
6405 skip_emulated_instruction(vcpu);
6406 return 1;
6407 }
6408
6409 page = nested_get_page(vcpu, vmptr);
6410 if (page == NULL ||
6411 *(u32 *)kmap(page) != VMCS12_REVISION) {
6412 nested_vmx_failInvalid(vcpu);
6413 kunmap(page);
6414 skip_emulated_instruction(vcpu);
6415 return 1;
6416 }
6417 kunmap(page);
6418 vmx->nested.vmxon_ptr = vmptr;
6419 break;
4291b588 6420 case EXIT_REASON_VMCLEAR:
bc39c4db 6421 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6422 nested_vmx_failValid(vcpu,
6423 VMXERR_VMCLEAR_INVALID_ADDRESS);
6424 skip_emulated_instruction(vcpu);
6425 return 1;
6426 }
6427
6428 if (vmptr == vmx->nested.vmxon_ptr) {
6429 nested_vmx_failValid(vcpu,
6430 VMXERR_VMCLEAR_VMXON_POINTER);
6431 skip_emulated_instruction(vcpu);
6432 return 1;
6433 }
6434 break;
6435 case EXIT_REASON_VMPTRLD:
bc39c4db 6436 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6437 nested_vmx_failValid(vcpu,
6438 VMXERR_VMPTRLD_INVALID_ADDRESS);
6439 skip_emulated_instruction(vcpu);
6440 return 1;
6441 }
3573e22c 6442
4291b588
BD		 6443 if (vmptr == vmx->nested.vmxon_ptr) {
6444 nested_vmx_failValid(vcpu,
6445 VMXERR_VMCLEAR_VMXON_POINTER);
6446 skip_emulated_instruction(vcpu);
6447 return 1;
6448 }
6449 break;
3573e22c
BD		 6450 default:
6451 return 1; /* shouldn't happen */
6452 }
6453
4291b588
BD		 6454 if (vmpointer)
6455 *vmpointer = vmptr;
3573e22c
BD		 6456 return 0;
6457}
6458
ec378aee
NHE		 6459/*
6460 * Emulate the VMXON instruction.
6461 * Currently, we just remember that VMX is active, and do not save or even
6462 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6463 * do not currently need to store anything in that guest-allocated memory
6464 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6465 * argument is different from the VMXON pointer (which the spec says they do).
6466 */
6467static int handle_vmon(struct kvm_vcpu *vcpu)
6468{
6469 struct kvm_segment cs;
6470 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6471 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6472 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6473 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6474
6475 /* The Intel VMX Instruction Reference lists a bunch of bits that
6476 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6477 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6478 * Otherwise, we should fail with #UD. We test these now:
6479 */
6480 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6481 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6482 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6483 kvm_queue_exception(vcpu, UD_VECTOR);
6484 return 1;
6485 }
6486
6487 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6488 if (is_long_mode(vcpu) && !cs.l) {
6489 kvm_queue_exception(vcpu, UD_VECTOR);
6490 return 1;
6491 }
6492
6493 if (vmx_get_cpl(vcpu)) {
6494 kvm_inject_gp(vcpu, 0);
6495 return 1;
6496 }
3573e22c 6497
4291b588 6498 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6499 return 1;
6500
145c28dd
AG		 6501 if (vmx->nested.vmxon) {
6502 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6503 skip_emulated_instruction(vcpu);
6504 return 1;
6505 }
b3897a49
NHE		 6506
6507 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6508 != VMXON_NEEDED_FEATURES) {
6509 kvm_inject_gp(vcpu, 0);
6510 return 1;
6511 }
6512
8de48833
AG		 6513 if (enable_shadow_vmcs) {
6514 shadow_vmcs = alloc_vmcs();
6515 if (!shadow_vmcs)
6516 return -ENOMEM;
6517 /* mark vmcs as shadow */
6518 shadow_vmcs->revision_id |= (1u << 31);
6519 /* init shadow vmcs */
6520 vmcs_clear(shadow_vmcs);
6521 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6522 }
ec378aee 6523
ff2f6fe9
NHE		 6524 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6525 vmx->nested.vmcs02_num = 0;
6526
f4124500
JK		 6527 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6528 HRTIMER_MODE_REL);
6529 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6530
ec378aee
NHE		 6531 vmx->nested.vmxon = true;
6532
6533 skip_emulated_instruction(vcpu);
a25eb114 6534 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6535 return 1;
6536}
6537
6538/*
6539 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6540 * for running VMX instructions (except VMXON, whose prerequisites are
6541 * slightly different). It also specifies what exception to inject otherwise.
6542 */
6543static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6544{
6545 struct kvm_segment cs;
6546 struct vcpu_vmx *vmx = to_vmx(vcpu);
6547
6548 if (!vmx->nested.vmxon) {
6549 kvm_queue_exception(vcpu, UD_VECTOR);
6550 return 0;
6551 }
6552
6553 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6554 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6555 (is_long_mode(vcpu) && !cs.l)) {
6556 kvm_queue_exception(vcpu, UD_VECTOR);
6557 return 0;
6558 }
6559
6560 if (vmx_get_cpl(vcpu)) {
6561 kvm_inject_gp(vcpu, 0);
6562 return 0;
6563 }
6564
6565 return 1;
6566}
6567
e7953d7f
AG		 6568static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6569{
8a1b9dd0 6570 u32 exec_control;
9a2a05b9
PB		 6571 if (vmx->nested.current_vmptr == -1ull)
6572 return;
6573
6574 /* current_vmptr and current_vmcs12 are always set/reset together */
6575 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6576 return;
6577
012f83cb 6578 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6579 /* copy to memory all shadowed fields in case
6580 they were modified */
6581 copy_shadow_to_vmcs12(vmx);
6582 vmx->nested.sync_shadow_vmcs = false;
6583 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6584 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6585 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6586 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6587 }
e7953d7f
AG		 6588 kunmap(vmx->nested.current_vmcs12_page);
6589 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6590 vmx->nested.current_vmptr = -1ull;
6591 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6592}
6593
ec378aee
NHE		 6594/*
6595 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6596 * just stops using VMX.
6597 */
6598static void free_nested(struct vcpu_vmx *vmx)
6599{
6600 if (!vmx->nested.vmxon)
6601 return;
9a2a05b9 6602
ec378aee 6603 vmx->nested.vmxon = false;
9a2a05b9 6604 nested_release_vmcs12(vmx);
e7953d7f
AG		 6605 if (enable_shadow_vmcs)
6606 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6607 /* Unpin physical memory we referred to in current vmcs02 */
6608 if (vmx->nested.apic_access_page) {
6609 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6610 vmx->nested.apic_access_page = NULL;
fe3ef05c 6611 }
a7c0b07d
WL		 6612 if (vmx->nested.virtual_apic_page) {
6613 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6614 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6615 }
ff2f6fe9
NHE		 6616
6617 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6618}
6619
6620/* Emulate the VMXOFF instruction */
6621static int handle_vmoff(struct kvm_vcpu *vcpu)
6622{
6623 if (!nested_vmx_check_permission(vcpu))
6624 return 1;
6625 free_nested(to_vmx(vcpu));
6626 skip_emulated_instruction(vcpu);
a25eb114 6627 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6628 return 1;
6629}
6630
27d6c865
NHE		 6631/* Emulate the VMCLEAR instruction */
6632static int handle_vmclear(struct kvm_vcpu *vcpu)
6633{
6634 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6635 gpa_t vmptr;
6636 struct vmcs12 *vmcs12;
6637 struct page *page;
27d6c865
NHE		 6638
6639 if (!nested_vmx_check_permission(vcpu))
6640 return 1;
6641
4291b588 6642 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6643 return 1;
27d6c865 6644
9a2a05b9 6645 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6646 nested_release_vmcs12(vmx);
27d6c865
NHE		 6647
6648 page = nested_get_page(vcpu, vmptr);
6649 if (page == NULL) {
6650 /*
6651 * For accurate processor emulation, VMCLEAR beyond available
6652 * physical memory should do nothing at all. However, it is
6653 * possible that a nested vmx bug, not a guest hypervisor bug,
6654 * resulted in this case, so let's shut down before doing any
6655 * more damage:
6656 */
6657 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6658 return 1;
6659 }
6660 vmcs12 = kmap(page);
6661 vmcs12->launch_state = 0;
6662 kunmap(page);
6663 nested_release_page(page);
6664
6665 nested_free_vmcs02(vmx, vmptr);
6666
6667 skip_emulated_instruction(vcpu);
6668 nested_vmx_succeed(vcpu);
6669 return 1;
6670}
6671
cd232ad0
NHE		 6672static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6673
6674/* Emulate the VMLAUNCH instruction */
6675static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6676{
6677 return nested_vmx_run(vcpu, true);
6678}
6679
6680/* Emulate the VMRESUME instruction */
6681static int handle_vmresume(struct kvm_vcpu *vcpu)
6682{
6683
6684 return nested_vmx_run(vcpu, false);
6685}
6686
49f705c5
NHE		 6687enum vmcs_field_type {
6688 VMCS_FIELD_TYPE_U16 = 0,
6689 VMCS_FIELD_TYPE_U64 = 1,
6690 VMCS_FIELD_TYPE_U32 = 2,
6691 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6692};
6693
6694static inline int vmcs_field_type(unsigned long field)
6695{
6696 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6697 return VMCS_FIELD_TYPE_U32;
6698 return (field >> 13) & 0x3 ;
6699}
6700
6701static inline int vmcs_field_readonly(unsigned long field)
6702{
6703 return (((field >> 10) & 0x3) == 1);
6704}
6705
6706/*
6707 * Read a vmcs12 field. Since these can have varying lengths and we return
6708 * one type, we chose the biggest type (u64) and zero-extend the return value
6709 * to that size. Note that the caller, handle_vmread, might need to use only
6710 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6711 * 64-bit fields are to be returned).
6712 */
a2ae9df7
PB		 6713static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6714 unsigned long field, u64 *ret)
49f705c5
NHE		 6715{
6716 short offset = vmcs_field_to_offset(field);
6717 char *p;
6718
6719 if (offset < 0)
a2ae9df7 6720 return offset;
49f705c5
NHE		 6721
6722 p = ((char *)(get_vmcs12(vcpu))) + offset;
6723
6724 switch (vmcs_field_type(field)) {
6725 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6726 *ret = *((natural_width *)p);
a2ae9df7 6727 return 0;
49f705c5
NHE		 6728 case VMCS_FIELD_TYPE_U16:
6729 *ret = *((u16 *)p);
a2ae9df7 6730 return 0;
49f705c5
NHE		 6731 case VMCS_FIELD_TYPE_U32:
6732 *ret = *((u32 *)p);
a2ae9df7 6733 return 0;
49f705c5
NHE		 6734 case VMCS_FIELD_TYPE_U64:
6735 *ret = *((u64 *)p);
a2ae9df7 6736 return 0;
49f705c5 6737 default:
a2ae9df7
PB		 6738 WARN_ON(1);
6739 return -ENOENT;
49f705c5
NHE		 6740 }
6741}
6742
20b97fea 6743
a2ae9df7
PB		 6744static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6745 unsigned long field, u64 field_value){
20b97fea
AG		 6746 short offset = vmcs_field_to_offset(field);
6747 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6748 if (offset < 0)
a2ae9df7 6749 return offset;
20b97fea
AG		 6750
6751 switch (vmcs_field_type(field)) {
6752 case VMCS_FIELD_TYPE_U16:
6753 *(u16 *)p = field_value;
a2ae9df7 6754 return 0;
20b97fea
AG		 6755 case VMCS_FIELD_TYPE_U32:
6756 *(u32 *)p = field_value;
a2ae9df7 6757 return 0;
20b97fea
AG		 6758 case VMCS_FIELD_TYPE_U64:
6759 *(u64 *)p = field_value;
a2ae9df7 6760 return 0;
20b97fea
AG		 6761 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6762 *(natural_width *)p = field_value;
a2ae9df7 6763 return 0;
20b97fea 6764 default:
a2ae9df7
PB		 6765 WARN_ON(1);
6766 return -ENOENT;
20b97fea
AG		 6767 }
6768
6769}
6770
16f5b903
AG		 6771static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6772{
6773 int i;
6774 unsigned long field;
6775 u64 field_value;
6776 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6777 const unsigned long *fields = shadow_read_write_fields;
6778 const int num_fields = max_shadow_read_write_fields;
16f5b903 6779
282da870
JK		 6780 preempt_disable();
6781
16f5b903
AG		 6782 vmcs_load(shadow_vmcs);
6783
6784 for (i = 0; i < num_fields; i++) {
6785 field = fields[i];
6786 switch (vmcs_field_type(field)) {
6787 case VMCS_FIELD_TYPE_U16:
6788 field_value = vmcs_read16(field);
6789 break;
6790 case VMCS_FIELD_TYPE_U32:
6791 field_value = vmcs_read32(field);
6792 break;
6793 case VMCS_FIELD_TYPE_U64:
6794 field_value = vmcs_read64(field);
6795 break;
6796 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6797 field_value = vmcs_readl(field);
6798 break;
a2ae9df7
PB		 6799 default:
6800 WARN_ON(1);
6801 continue;
16f5b903
AG		 6802 }
6803 vmcs12_write_any(&vmx->vcpu, field, field_value);
6804 }
6805
6806 vmcs_clear(shadow_vmcs);
6807 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6808
6809 preempt_enable();
16f5b903
AG		 6810}
6811
c3114420
AG		 6812static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6813{
c2bae893
MK		 6814 const unsigned long *fields[] = {
6815 shadow_read_write_fields,
6816 shadow_read_only_fields
c3114420 6817 };
c2bae893 6818 const int max_fields[] = {
c3114420
AG		 6819 max_shadow_read_write_fields,
6820 max_shadow_read_only_fields
6821 };
6822 int i, q;
6823 unsigned long field;
6824 u64 field_value = 0;
6825 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6826
6827 vmcs_load(shadow_vmcs);
6828
c2bae893 6829 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6830 for (i = 0; i < max_fields[q]; i++) {
6831 field = fields[q][i];
6832 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6833
6834 switch (vmcs_field_type(field)) {
6835 case VMCS_FIELD_TYPE_U16:
6836 vmcs_write16(field, (u16)field_value);
6837 break;
6838 case VMCS_FIELD_TYPE_U32:
6839 vmcs_write32(field, (u32)field_value);
6840 break;
6841 case VMCS_FIELD_TYPE_U64:
6842 vmcs_write64(field, (u64)field_value);
6843 break;
6844 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6845 vmcs_writel(field, (long)field_value);
6846 break;
a2ae9df7
PB		 6847 default:
6848 WARN_ON(1);
6849 break;
c3114420
AG		 6850 }
6851 }
6852 }
6853
6854 vmcs_clear(shadow_vmcs);
6855 vmcs_load(vmx->loaded_vmcs->vmcs);
6856}
6857
49f705c5
NHE		 6858/*
6859 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6860 * used before) all generate the same failure when it is missing.
6861 */
6862static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6863{
6864 struct vcpu_vmx *vmx = to_vmx(vcpu);
6865 if (vmx->nested.current_vmptr == -1ull) {
6866 nested_vmx_failInvalid(vcpu);
6867 skip_emulated_instruction(vcpu);
6868 return 0;
6869 }
6870 return 1;
6871}
6872
6873static int handle_vmread(struct kvm_vcpu *vcpu)
6874{
6875 unsigned long field;
6876 u64 field_value;
6877 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6878 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6879 gva_t gva = 0;
6880
6881 if (!nested_vmx_check_permission(vcpu) ||
6882 !nested_vmx_check_vmcs12(vcpu))
6883 return 1;
6884
6885 /* Decode instruction info and find the field to read */
27e6fb5d 6886 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6887 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6888 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6889 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6890 skip_emulated_instruction(vcpu);
6891 return 1;
6892 }
6893 /*
6894 * Now copy part of this value to register or memory, as requested.
6895 * Note that the number of bits actually copied is 32 or 64 depending
6896 * on the guest's mode (32 or 64 bit), not on the given field's length.
6897 */
6898 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6899 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6900 field_value);
6901 } else {
6902 if (get_vmx_mem_address(vcpu, exit_qualification,
6903 vmx_instruction_info, &gva))
6904 return 1;
6905 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6906 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6907 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6908 }
6909
6910 nested_vmx_succeed(vcpu);
6911 skip_emulated_instruction(vcpu);
6912 return 1;
6913}
6914
6915
6916static int handle_vmwrite(struct kvm_vcpu *vcpu)
6917{
6918 unsigned long field;
6919 gva_t gva;
6920 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6921 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6922 /* The value to write might be 32 or 64 bits, depending on L1's long
6923 * mode, and eventually we need to write that into a field of several
6924 * possible lengths. The code below first zero-extends the value to 64
6925 * bit (field_value), and then copies only the approriate number of
6926 * bits into the vmcs12 field.
6927 */
6928 u64 field_value = 0;
6929 struct x86_exception e;
6930
6931 if (!nested_vmx_check_permission(vcpu) ||
6932 !nested_vmx_check_vmcs12(vcpu))
6933 return 1;
6934
6935 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6936 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6937 (((vmx_instruction_info) >> 3) & 0xf));
6938 else {
6939 if (get_vmx_mem_address(vcpu, exit_qualification,
6940 vmx_instruction_info, &gva))
6941 return 1;
6942 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6943 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6944 kvm_inject_page_fault(vcpu, &e);
6945 return 1;
6946 }
6947 }
6948
6949
27e6fb5d 6950 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6951 if (vmcs_field_readonly(field)) {
6952 nested_vmx_failValid(vcpu,
6953 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6954 skip_emulated_instruction(vcpu);
6955 return 1;
6956 }
6957
a2ae9df7 6958 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6959 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6960 skip_emulated_instruction(vcpu);
6961 return 1;
6962 }
6963
6964 nested_vmx_succeed(vcpu);
6965 skip_emulated_instruction(vcpu);
6966 return 1;
6967}
6968
63846663
NHE		 6969/* Emulate the VMPTRLD instruction */
6970static int handle_vmptrld(struct kvm_vcpu *vcpu)
6971{
6972 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6973 gpa_t vmptr;
8a1b9dd0 6974 u32 exec_control;
63846663
NHE		 6975
6976 if (!nested_vmx_check_permission(vcpu))
6977 return 1;
6978
4291b588 6979 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6980 return 1;
63846663
NHE		 6981
6982 if (vmx->nested.current_vmptr != vmptr) {
6983 struct vmcs12 *new_vmcs12;
6984 struct page *page;
6985 page = nested_get_page(vcpu, vmptr);
6986 if (page == NULL) {
6987 nested_vmx_failInvalid(vcpu);
6988 skip_emulated_instruction(vcpu);
6989 return 1;
6990 }
6991 new_vmcs12 = kmap(page);
6992 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6993 kunmap(page);
6994 nested_release_page_clean(page);
6995 nested_vmx_failValid(vcpu,
6996 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6997 skip_emulated_instruction(vcpu);
6998 return 1;
6999 }
63846663 7000
9a2a05b9 7001 nested_release_vmcs12(vmx);
63846663
NHE		 7002 vmx->nested.current_vmptr = vmptr;
7003 vmx->nested.current_vmcs12 = new_vmcs12;
7004 vmx->nested.current_vmcs12_page = page;
012f83cb 7005 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7006 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7007 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7008 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7009 vmcs_write64(VMCS_LINK_POINTER,
7010 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7011 vmx->nested.sync_shadow_vmcs = true;
7012 }
63846663
NHE		 7013 }
7014
7015 nested_vmx_succeed(vcpu);
7016 skip_emulated_instruction(vcpu);
7017 return 1;
7018}
7019
6a4d7550
NHE		 7020/* Emulate the VMPTRST instruction */
7021static int handle_vmptrst(struct kvm_vcpu *vcpu)
7022{
7023 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7024 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7025 gva_t vmcs_gva;
7026 struct x86_exception e;
7027
7028 if (!nested_vmx_check_permission(vcpu))
7029 return 1;
7030
7031 if (get_vmx_mem_address(vcpu, exit_qualification,
7032 vmx_instruction_info, &vmcs_gva))
7033 return 1;
7034 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7035 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7036 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7037 sizeof(u64), &e)) {
7038 kvm_inject_page_fault(vcpu, &e);
7039 return 1;
7040 }
7041 nested_vmx_succeed(vcpu);
7042 skip_emulated_instruction(vcpu);
7043 return 1;
7044}
7045
bfd0a56b
NHE		 7046/* Emulate the INVEPT instruction */
7047static int handle_invept(struct kvm_vcpu *vcpu)
7048{
b9c237bb 7049 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7050 u32 vmx_instruction_info, types;
7051 unsigned long type;
7052 gva_t gva;
7053 struct x86_exception e;
7054 struct {
7055 u64 eptp, gpa;
7056 } operand;
bfd0a56b 7057
b9c237bb
WV		 7058 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7059 SECONDARY_EXEC_ENABLE_EPT) ||
7060 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7061 kvm_queue_exception(vcpu, UD_VECTOR);
7062 return 1;
7063 }
7064
7065 if (!nested_vmx_check_permission(vcpu))
7066 return 1;
7067
7068 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7069 kvm_queue_exception(vcpu, UD_VECTOR);
7070 return 1;
7071 }
7072
7073 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7074 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7075
b9c237bb 7076 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7077
7078 if (!(types & (1UL << type))) {
7079 nested_vmx_failValid(vcpu,
7080 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7081 return 1;
7082 }
7083
7084 /* According to the Intel VMX instruction reference, the memory
7085 * operand is read even if it isn't needed (e.g., for type==global)
7086 */
7087 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7088 vmx_instruction_info, &gva))
7089 return 1;
7090 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7091 sizeof(operand), &e)) {
7092 kvm_inject_page_fault(vcpu, &e);
7093 return 1;
7094 }
7095
7096 switch (type) {
bfd0a56b
NHE		 7097 case VMX_EPT_EXTENT_GLOBAL:
7098 kvm_mmu_sync_roots(vcpu);
77c3913b 7099 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7100 nested_vmx_succeed(vcpu);
7101 break;
7102 default:
4b855078 7103 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7104 BUG_ON(1);
7105 break;
7106 }
7107
7108 skip_emulated_instruction(vcpu);
7109 return 1;
7110}
7111
a642fc30
PM		 7112static int handle_invvpid(struct kvm_vcpu *vcpu)
7113{
7114 kvm_queue_exception(vcpu, UD_VECTOR);
7115 return 1;
7116}
7117
843e4330
KH		 7118static int handle_pml_full(struct kvm_vcpu *vcpu)
7119{
7120 unsigned long exit_qualification;
7121
7122 trace_kvm_pml_full(vcpu->vcpu_id);
7123
7124 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7125
7126 /*
7127 * PML buffer FULL happened while executing iret from NMI,
7128 * "blocked by NMI" bit has to be set before next VM entry.
7129 */
7130 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7131 cpu_has_virtual_nmis() &&
7132 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7133 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7134 GUEST_INTR_STATE_NMI);
7135
7136 /*
7137 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7138 * here.., and there's no userspace involvement needed for PML.
7139 */
7140 return 1;
7141}
7142
6aa8b732
AK		 7143/*
7144 * The exit handlers return 1 if the exit was handled fully and guest execution
7145 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7146 * to be done to userspace and return 0.
7147 */
772e0318 7148static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7149 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7150 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7151 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7152 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7153 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7154 [EXIT_REASON_CR_ACCESS] = handle_cr,
7155 [EXIT_REASON_DR_ACCESS] = handle_dr,
7156 [EXIT_REASON_CPUID] = handle_cpuid,
7157 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7158 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7159 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7160 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7161 [EXIT_REASON_INVD] = handle_invd,
a7052897 7162 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7163 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7164 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7165 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7166 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7167 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7168 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7169 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7170 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7171 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7172 [EXIT_REASON_VMOFF] = handle_vmoff,
7173 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7174 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7175 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7176 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7177 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7178 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7179 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7180 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7181 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7182 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7183 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7184 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7185 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7186 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7187 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7188 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7189 [EXIT_REASON_XSAVES] = handle_xsaves,
7190 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7191 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7192};
7193
7194static const int kvm_vmx_max_exit_handlers =
50a3485c 7195 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7196
908a7bdd
JK		 7197static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7198 struct vmcs12 *vmcs12)
7199{
7200 unsigned long exit_qualification;
7201 gpa_t bitmap, last_bitmap;
7202 unsigned int port;
7203 int size;
7204 u8 b;
7205
908a7bdd 7206 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7207 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7208
7209 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7210
7211 port = exit_qualification >> 16;
7212 size = (exit_qualification & 7) + 1;
7213
7214 last_bitmap = (gpa_t)-1;
7215 b = -1;
7216
7217 while (size > 0) {
7218 if (port < 0x8000)
7219 bitmap = vmcs12->io_bitmap_a;
7220 else if (port < 0x10000)
7221 bitmap = vmcs12->io_bitmap_b;
7222 else
7223 return 1;
7224 bitmap += (port & 0x7fff) / 8;
7225
7226 if (last_bitmap != bitmap)
7227 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7228 return 1;
7229 if (b & (1 << (port & 7)))
7230 return 1;
7231
7232 port++;
7233 size--;
7234 last_bitmap = bitmap;
7235 }
7236
7237 return 0;
7238}
7239
644d711a
NHE		 7240/*
7241 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7242 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7243 * disinterest in the current event (read or write a specific MSR) by using an
7244 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7245 */
7246static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7247 struct vmcs12 *vmcs12, u32 exit_reason)
7248{
7249 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7250 gpa_t bitmap;
7251
cbd29cb6 7252 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7253 return 1;
7254
7255 /*
7256 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7257 * for the four combinations of read/write and low/high MSR numbers.
7258 * First we need to figure out which of the four to use:
7259 */
7260 bitmap = vmcs12->msr_bitmap;
7261 if (exit_reason == EXIT_REASON_MSR_WRITE)
7262 bitmap += 2048;
7263 if (msr_index >= 0xc0000000) {
7264 msr_index -= 0xc0000000;
7265 bitmap += 1024;
7266 }
7267
7268 /* Then read the msr_index'th bit from this bitmap: */
7269 if (msr_index < 1024*8) {
7270 unsigned char b;
bd31a7f5
JK		 7271 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7272 return 1;
644d711a
NHE		 7273 return 1 & (b >> (msr_index & 7));
7274 } else
7275 return 1; /* let L1 handle the wrong parameter */
7276}
7277
7278/*
7279 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7280 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7281 * intercept (via guest_host_mask etc.) the current event.
7282 */
7283static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7284 struct vmcs12 *vmcs12)
7285{
7286 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7287 int cr = exit_qualification & 15;
7288 int reg = (exit_qualification >> 8) & 15;
1e32c079 7289 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7290
7291 switch ((exit_qualification >> 4) & 3) {
7292 case 0: /* mov to cr */
7293 switch (cr) {
7294 case 0:
7295 if (vmcs12->cr0_guest_host_mask &
7296 (val ^ vmcs12->cr0_read_shadow))
7297 return 1;
7298 break;
7299 case 3:
7300 if ((vmcs12->cr3_target_count >= 1 &&
7301 vmcs12->cr3_target_value0 == val) ||
7302 (vmcs12->cr3_target_count >= 2 &&
7303 vmcs12->cr3_target_value1 == val) ||
7304 (vmcs12->cr3_target_count >= 3 &&
7305 vmcs12->cr3_target_value2 == val) ||
7306 (vmcs12->cr3_target_count >= 4 &&
7307 vmcs12->cr3_target_value3 == val))
7308 return 0;
7309 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7310 return 1;
7311 break;
7312 case 4:
7313 if (vmcs12->cr4_guest_host_mask &
7314 (vmcs12->cr4_read_shadow ^ val))
7315 return 1;
7316 break;
7317 case 8:
7318 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7319 return 1;
7320 break;
7321 }
7322 break;
7323 case 2: /* clts */
7324 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7325 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7326 return 1;
7327 break;
7328 case 1: /* mov from cr */
7329 switch (cr) {
7330 case 3:
7331 if (vmcs12->cpu_based_vm_exec_control &
7332 CPU_BASED_CR3_STORE_EXITING)
7333 return 1;
7334 break;
7335 case 8:
7336 if (vmcs12->cpu_based_vm_exec_control &
7337 CPU_BASED_CR8_STORE_EXITING)
7338 return 1;
7339 break;
7340 }
7341 break;
7342 case 3: /* lmsw */
7343 /*
7344 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7345 * cr0. Other attempted changes are ignored, with no exit.
7346 */
7347 if (vmcs12->cr0_guest_host_mask & 0xe &
7348 (val ^ vmcs12->cr0_read_shadow))
7349 return 1;
7350 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7351 !(vmcs12->cr0_read_shadow & 0x1) &&
7352 (val & 0x1))
7353 return 1;
7354 break;
7355 }
7356 return 0;
7357}
7358
7359/*
7360 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7361 * should handle it ourselves in L0 (and then continue L2). Only call this
7362 * when in is_guest_mode (L2).
7363 */
7364static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7365{
644d711a
NHE		 7366 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7367 struct vcpu_vmx *vmx = to_vmx(vcpu);
7368 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7369 u32 exit_reason = vmx->exit_reason;
644d711a 7370
542060ea
JK		 7371 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7372 vmcs_readl(EXIT_QUALIFICATION),
7373 vmx->idt_vectoring_info,
7374 intr_info,
7375 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7376 KVM_ISA_VMX);
7377
644d711a
NHE		 7378 if (vmx->nested.nested_run_pending)
7379 return 0;
7380
7381 if (unlikely(vmx->fail)) {
bd80158a
JK		 7382 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7383 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7384 return 1;
7385 }
7386
7387 switch (exit_reason) {
7388 case EXIT_REASON_EXCEPTION_NMI:
7389 if (!is_exception(intr_info))
7390 return 0;
7391 else if (is_page_fault(intr_info))
7392 return enable_ept;
e504c909 7393 else if (is_no_device(intr_info) &&
ccf9844e 7394 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7395 return 0;
644d711a
NHE		 7396 return vmcs12->exception_bitmap &
7397 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7398 case EXIT_REASON_EXTERNAL_INTERRUPT:
7399 return 0;
7400 case EXIT_REASON_TRIPLE_FAULT:
7401 return 1;
7402 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7403 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7404 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7405 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7406 case EXIT_REASON_TASK_SWITCH:
7407 return 1;
7408 case EXIT_REASON_CPUID:
bc613494
MT		 7409 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7410 return 0;
644d711a
NHE		 7411 return 1;
7412 case EXIT_REASON_HLT:
7413 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7414 case EXIT_REASON_INVD:
7415 return 1;
7416 case EXIT_REASON_INVLPG:
7417 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7418 case EXIT_REASON_RDPMC:
7419 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7420 case EXIT_REASON_RDTSC:
7421 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7422 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7423 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7424 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7425 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7426 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7427 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7428 /*
7429 * VMX instructions trap unconditionally. This allows L1 to
7430 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7431 */
7432 return 1;
7433 case EXIT_REASON_CR_ACCESS:
7434 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7435 case EXIT_REASON_DR_ACCESS:
7436 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7437 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7438 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7439 case EXIT_REASON_MSR_READ:
7440 case EXIT_REASON_MSR_WRITE:
7441 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7442 case EXIT_REASON_INVALID_STATE:
7443 return 1;
7444 case EXIT_REASON_MWAIT_INSTRUCTION:
7445 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7446 case EXIT_REASON_MONITOR_INSTRUCTION:
7447 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7448 case EXIT_REASON_PAUSE_INSTRUCTION:
7449 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7450 nested_cpu_has2(vmcs12,
7451 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7452 case EXIT_REASON_MCE_DURING_VMENTRY:
7453 return 0;
7454 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7455 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7456 case EXIT_REASON_APIC_ACCESS:
7457 return nested_cpu_has2(vmcs12,
7458 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7459 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7460 case EXIT_REASON_EOI_INDUCED:
7461 /* apic_write and eoi_induced should exit unconditionally. */
82f0dd4b 7462 return 1;
644d711a 7463 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7464 /*
7465 * L0 always deals with the EPT violation. If nested EPT is
7466 * used, and the nested mmu code discovers that the address is
7467 * missing in the guest EPT table (EPT12), the EPT violation
7468 * will be injected with nested_ept_inject_page_fault()
7469 */
7470 return 0;
644d711a 7471 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7472 /*
7473 * L2 never uses directly L1's EPT, but rather L0's own EPT
7474 * table (shadow on EPT) or a merged EPT table that L0 built
7475 * (EPT on EPT). So any problems with the structure of the
7476 * table is L0's fault.
7477 */
644d711a
NHE		 7478 return 0;
7479 case EXIT_REASON_WBINVD:
7480 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7481 case EXIT_REASON_XSETBV:
7482 return 1;
81dc01f7
WL		 7483 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7484 /*
7485 * This should never happen, since it is not possible to
7486 * set XSS to a non-zero value---neither in L1 nor in L2.
7487 * If if it were, XSS would have to be checked against
7488 * the XSS exit bitmap in vmcs12.
7489 */
7490 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a
NHE		 7491 default:
7492 return 1;
7493 }
7494}
7495
586f9607
AK		 7496static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7497{
7498 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7499 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7500}
7501
843e4330
KH		 7502static int vmx_enable_pml(struct vcpu_vmx *vmx)
7503{
7504 struct page *pml_pg;
7505 u32 exec_control;
7506
7507 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7508 if (!pml_pg)
7509 return -ENOMEM;
7510
7511 vmx->pml_pg = pml_pg;
7512
7513 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7514 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7515
7516 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7517 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7518 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7519
7520 return 0;
7521}
7522
7523static void vmx_disable_pml(struct vcpu_vmx *vmx)
7524{
7525 u32 exec_control;
7526
7527 ASSERT(vmx->pml_pg);
7528 __free_page(vmx->pml_pg);
7529 vmx->pml_pg = NULL;
7530
7531 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7532 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7533 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7534}
7535
7536static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7537{
7538 struct kvm *kvm = vmx->vcpu.kvm;
7539 u64 *pml_buf;
7540 u16 pml_idx;
7541
7542 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7543
7544 /* Do nothing if PML buffer is empty */
7545 if (pml_idx == (PML_ENTITY_NUM - 1))
7546 return;
7547
7548 /* PML index always points to next available PML buffer entity */
7549 if (pml_idx >= PML_ENTITY_NUM)
7550 pml_idx = 0;
7551 else
7552 pml_idx++;
7553
7554 pml_buf = page_address(vmx->pml_pg);
7555 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7556 u64 gpa;
7557
7558 gpa = pml_buf[pml_idx];
7559 WARN_ON(gpa & (PAGE_SIZE - 1));
7560 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7561 }
7562
7563 /* reset PML index */
7564 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7565}
7566
7567/*
7568 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7569 * Called before reporting dirty_bitmap to userspace.
7570 */
7571static void kvm_flush_pml_buffers(struct kvm *kvm)
7572{
7573 int i;
7574 struct kvm_vcpu *vcpu;
7575 /*
7576 * We only need to kick vcpu out of guest mode here, as PML buffer
7577 * is flushed at beginning of all VMEXITs, and it's obvious that only
7578 * vcpus running in guest are possible to have unflushed GPAs in PML
7579 * buffer.
7580 */
7581 kvm_for_each_vcpu(i, vcpu, kvm)
7582 kvm_vcpu_kick(vcpu);
7583}
7584
6aa8b732
AK		 7585/*
7586 * The guest has exited. See if we can fix it or if we need userspace
7587 * assistance.
7588 */
851ba692 7589static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7590{
29bd8a78 7591 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7592 u32 exit_reason = vmx->exit_reason;
1155f76a 7593 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7594
843e4330
KH		 7595 /*
7596 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7597 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7598 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7599 * mode as if vcpus is in root mode, the PML buffer must has been
7600 * flushed already.
7601 */
7602 if (enable_pml)
7603 vmx_flush_pml_buffer(vmx);
7604
80ced186 7605 /* If guest state is invalid, start emulating */
14168786 7606 if (vmx->emulation_required)
80ced186 7607 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7608
644d711a 7609 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7610 nested_vmx_vmexit(vcpu, exit_reason,
7611 vmcs_read32(VM_EXIT_INTR_INFO),
7612 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7613 return 1;
7614 }
7615
5120702e
MG		 7616 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7617 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7618 vcpu->run->fail_entry.hardware_entry_failure_reason
7619 = exit_reason;
7620 return 0;
7621 }
7622
29bd8a78 7623 if (unlikely(vmx->fail)) {
851ba692
AK		 7624 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7625 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7626 = vmcs_read32(VM_INSTRUCTION_ERROR);
7627 return 0;
7628 }
6aa8b732 7629
b9bf6882
XG		 7630 /*
7631 * Note:
7632 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7633 * delivery event since it indicates guest is accessing MMIO.
7634 * The vm-exit can be triggered again after return to guest that
7635 * will cause infinite loop.
7636 */
d77c26fc 7637 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7638 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7639 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7640 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7641 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7642 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7643 vcpu->run->internal.ndata = 2;
7644 vcpu->run->internal.data[0] = vectoring_info;
7645 vcpu->run->internal.data[1] = exit_reason;
7646 return 0;
7647 }
3b86cd99 7648
644d711a
NHE		 7649 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7650 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7651 get_vmcs12(vcpu))))) {
c4282df9 7652 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7653 vmx->soft_vnmi_blocked = 0;
3b86cd99 7654 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7655 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7656 /*
7657 * This CPU don't support us in finding the end of an
7658 * NMI-blocked window if the guest runs with IRQs
7659 * disabled. So we pull the trigger after 1 s of
7660 * futile waiting, but inform the user about this.
7661 */
7662 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7663 "state on VCPU %d after 1 s timeout\n",
7664 __func__, vcpu->vcpu_id);
7665 vmx->soft_vnmi_blocked = 0;
3b86cd99 7666 }
3b86cd99
JK		 7667 }
7668
6aa8b732
AK		 7669 if (exit_reason < kvm_vmx_max_exit_handlers
7670 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7671 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7672 else {
2bc19dc3
MT		 7673 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7674 kvm_queue_exception(vcpu, UD_VECTOR);
7675 return 1;
6aa8b732 7676 }
6aa8b732
AK		 7677}
7678
95ba8273 7679static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7680{
a7c0b07d
WL		 7681 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7682
7683 if (is_guest_mode(vcpu) &&
7684 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7685 return;
7686
95ba8273 7687 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7688 vmcs_write32(TPR_THRESHOLD, 0);
7689 return;
7690 }
7691
95ba8273 7692 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7693}
7694
8d14695f
YZ		 7695static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7696{
7697 u32 sec_exec_control;
7698
7699 /*
7700 * There is not point to enable virtualize x2apic without enable
7701 * apicv
7702 */
c7c9c56c
YZ		 7703 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7704 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7705 return;
7706
7707 if (!vm_need_tpr_shadow(vcpu->kvm))
7708 return;
7709
7710 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7711
7712 if (set) {
7713 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7714 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7715 } else {
7716 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7717 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7718 }
7719 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7720
7721 vmx_set_msr_bitmap(vcpu);
7722}
7723
38b99173
TC		 7724static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7725{
7726 struct vcpu_vmx *vmx = to_vmx(vcpu);
7727
7728 /*
7729 * Currently we do not handle the nested case where L2 has an
7730 * APIC access page of its own; that page is still pinned.
7731 * Hence, we skip the case where the VCPU is in guest mode _and_
7732 * L1 prepared an APIC access page for L2.
7733 *
7734 * For the case where L1 and L2 share the same APIC access page
7735 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7736 * in the vmcs12), this function will only update either the vmcs01
7737 * or the vmcs02. If the former, the vmcs02 will be updated by
7738 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7739 * the next L2->L1 exit.
7740 */
7741 if (!is_guest_mode(vcpu) ||
7742 !nested_cpu_has2(vmx->nested.current_vmcs12,
7743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7744 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7745}
7746
c7c9c56c
YZ		 7747static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7748{
7749 u16 status;
7750 u8 old;
7751
c7c9c56c
YZ		 7752 if (isr == -1)
7753 isr = 0;
7754
7755 status = vmcs_read16(GUEST_INTR_STATUS);
7756 old = status >> 8;
7757 if (isr != old) {
7758 status &= 0xff;
7759 status |= isr << 8;
7760 vmcs_write16(GUEST_INTR_STATUS, status);
7761 }
7762}
7763
7764static void vmx_set_rvi(int vector)
7765{
7766 u16 status;
7767 u8 old;
7768
4114c27d
WW		 7769 if (vector == -1)
7770 vector = 0;
7771
c7c9c56c
YZ		 7772 status = vmcs_read16(GUEST_INTR_STATUS);
7773 old = (u8)status & 0xff;
7774 if ((u8)vector != old) {
7775 status &= ~0xff;
7776 status |= (u8)vector;
7777 vmcs_write16(GUEST_INTR_STATUS, status);
7778 }
7779}
7780
7781static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7782{
4114c27d
WW		 7783 if (!is_guest_mode(vcpu)) {
7784 vmx_set_rvi(max_irr);
7785 return;
7786 }
7787
c7c9c56c
YZ		 7788 if (max_irr == -1)
7789 return;
7790
963fee16 7791 /*
4114c27d
WW		 7792 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7793 * handles it.
963fee16 7794 */
4114c27d 7795 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7796 return;
7797
963fee16 7798 /*
4114c27d 7799 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7800 * is run without virtual interrupt delivery.
7801 */
7802 if (!kvm_event_needs_reinjection(vcpu) &&
7803 vmx_interrupt_allowed(vcpu)) {
7804 kvm_queue_interrupt(vcpu, max_irr, false);
7805 vmx_inject_irq(vcpu);
7806 }
c7c9c56c
YZ		 7807}
7808
7809static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7810{
3d81bc7e
YZ		 7811 if (!vmx_vm_has_apicv(vcpu->kvm))
7812 return;
7813
c7c9c56c
YZ		 7814 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7815 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7816 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7817 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7818}
7819
51aa01d1 7820static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7821{
00eba012
AK		 7822 u32 exit_intr_info;
7823
7824 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7825 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7826 return;
7827
c5ca8e57 7828 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7829 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7830
7831 /* Handle machine checks before interrupts are enabled */
00eba012 7832 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7833 kvm_machine_check();
7834
20f65983 7835 /* We need to handle NMIs before interrupts are enabled */
00eba012 7836 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7837 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7838 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7839 asm("int $2");
ff9d07a0
ZY		 7840 kvm_after_handle_nmi(&vmx->vcpu);
7841 }
51aa01d1 7842}
20f65983 7843
a547c6db
YZ		 7844static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7845{
7846 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7847
7848 /*
7849 * If external interrupt exists, IF bit is set in rflags/eflags on the
7850 * interrupt stack frame, and interrupt will be enabled on a return
7851 * from interrupt handler.
7852 */
7853 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7854 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7855 unsigned int vector;
7856 unsigned long entry;
7857 gate_desc *desc;
7858 struct vcpu_vmx *vmx = to_vmx(vcpu);
7859#ifdef CONFIG_X86_64
7860 unsigned long tmp;
7861#endif
7862
7863 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7864 desc = (gate_desc *)vmx->host_idt_base + vector;
7865 entry = gate_offset(*desc);
7866 asm volatile(
7867#ifdef CONFIG_X86_64
7868 "mov %%" _ASM_SP ", %[sp]\n\t"
7869 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7870 "push $%c[ss]\n\t"
7871 "push %[sp]\n\t"
7872#endif
7873 "pushf\n\t"
7874 "orl $0x200, (%%" _ASM_SP ")\n\t"
7875 __ASM_SIZE(push) " $%c[cs]\n\t"
7876 "call *%[entry]\n\t"
7877 :
7878#ifdef CONFIG_X86_64
7879 [sp]"=&r"(tmp)
7880#endif
7881 :
7882 [entry]"r"(entry),
7883 [ss]"i"(__KERNEL_DS),
7884 [cs]"i"(__KERNEL_CS)
7885 );
7886 } else
7887 local_irq_enable();
7888}
7889
da8999d3
LJ		 7890static bool vmx_mpx_supported(void)
7891{
7892 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7893 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7894}
7895
55412b2e
WL		 7896static bool vmx_xsaves_supported(void)
7897{
7898 return vmcs_config.cpu_based_2nd_exec_ctrl &
7899 SECONDARY_EXEC_XSAVES;
7900}
7901
51aa01d1
AK		 7902static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7903{
c5ca8e57 7904 u32 exit_intr_info;
51aa01d1
AK		 7905 bool unblock_nmi;
7906 u8 vector;
7907 bool idtv_info_valid;
7908
7909 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7910
cf393f75 7911 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7912 if (vmx->nmi_known_unmasked)
7913 return;
c5ca8e57
AK		 7914 /*
7915 * Can't use vmx->exit_intr_info since we're not sure what
7916 * the exit reason is.
7917 */
7918 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7919 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7920 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7921 /*
7b4a25cb 7922 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7923 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7924 * a guest IRET fault.
7b4a25cb
GN		 7925 * SDM 3: 23.2.2 (September 2008)
7926 * Bit 12 is undefined in any of the following cases:
7927 * If the VM exit sets the valid bit in the IDT-vectoring
7928 * information field.
7929 * If the VM exit is due to a double fault.
cf393f75 7930 */
7b4a25cb
GN		 7931 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7932 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7933 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7934 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7935 else
7936 vmx->nmi_known_unmasked =
7937 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7938 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7939 } else if (unlikely(vmx->soft_vnmi_blocked))
7940 vmx->vnmi_blocked_time +=
7941 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7942}
7943
3ab66e8a 7944static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7945 u32 idt_vectoring_info,
7946 int instr_len_field,
7947 int error_code_field)
51aa01d1 7948{
51aa01d1
AK		 7949 u8 vector;
7950 int type;
7951 bool idtv_info_valid;
7952
7953 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7954
3ab66e8a
JK		 7955 vcpu->arch.nmi_injected = false;
7956 kvm_clear_exception_queue(vcpu);
7957 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7958
7959 if (!idtv_info_valid)
7960 return;
7961
3ab66e8a 7962 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7963
668f612f
AK		 7964 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7965 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7966
64a7ec06 7967 switch (type) {
37b96e98 7968 case INTR_TYPE_NMI_INTR:
3ab66e8a 7969 vcpu->arch.nmi_injected = true;
668f612f 7970 /*
7b4a25cb 7971 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7972 * Clear bit "block by NMI" before VM entry if a NMI
7973 * delivery faulted.
668f612f 7974 */
3ab66e8a 7975 vmx_set_nmi_mask(vcpu, false);
37b96e98 7976 break;
37b96e98 7977 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7978 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7979 /* fall through */
7980 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7981 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7982 u32 err = vmcs_read32(error_code_field);
851eb667 7983 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7984 } else
851eb667 7985 kvm_requeue_exception(vcpu, vector);
37b96e98 7986 break;
66fd3f7f 7987 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7988 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7989 /* fall through */
37b96e98 7990 case INTR_TYPE_EXT_INTR:
3ab66e8a 7991 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7992 break;
7993 default:
7994 break;
f7d9238f 7995 }
cf393f75
AK		 7996}
7997
83422e17
AK		 7998static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7999{
3ab66e8a 8000 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8001 VM_EXIT_INSTRUCTION_LEN,
8002 IDT_VECTORING_ERROR_CODE);
8003}
8004
b463a6f7
AK		 8005static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8006{
3ab66e8a 8007 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8008 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8009 VM_ENTRY_INSTRUCTION_LEN,
8010 VM_ENTRY_EXCEPTION_ERROR_CODE);
8011
8012 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8013}
8014
d7cd9796
GN		 8015static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8016{
8017 int i, nr_msrs;
8018 struct perf_guest_switch_msr *msrs;
8019
8020 msrs = perf_guest_get_msrs(&nr_msrs);
8021
8022 if (!msrs)
8023 return;
8024
8025 for (i = 0; i < nr_msrs; i++)
8026 if (msrs[i].host == msrs[i].guest)
8027 clear_atomic_switch_msr(vmx, msrs[i].msr);
8028 else
8029 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8030 msrs[i].host);
8031}
8032
a3b5ba49 8033static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8034{
a2fa3e9f 8035 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8036 unsigned long debugctlmsr, cr4;
104f226b
AK		 8037
8038 /* Record the guest's net vcpu time for enforced NMI injections. */
8039 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8040 vmx->entry_time = ktime_get();
8041
8042 /* Don't enter VMX if guest state is invalid, let the exit handler
8043 start emulation until we arrive back to a valid state */
14168786 8044 if (vmx->emulation_required)
104f226b
AK		 8045 return;
8046
a7653ecd
RK		 8047 if (vmx->ple_window_dirty) {
8048 vmx->ple_window_dirty = false;
8049 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8050 }
8051
012f83cb
AG		 8052 if (vmx->nested.sync_shadow_vmcs) {
8053 copy_vmcs12_to_shadow(vmx);
8054 vmx->nested.sync_shadow_vmcs = false;
8055 }
8056
104f226b
AK		 8057 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8058 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8059 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8060 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8061
d974baa3
AL		 8062 cr4 = read_cr4();
8063 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8064 vmcs_writel(HOST_CR4, cr4);
8065 vmx->host_state.vmcs_host_cr4 = cr4;
8066 }
8067
104f226b
AK		 8068 /* When single-stepping over STI and MOV SS, we must clear the
8069 * corresponding interruptibility bits in the guest state. Otherwise
8070 * vmentry fails as it then expects bit 14 (BS) in pending debug
8071 * exceptions being set, but that's not correct for the guest debugging
8072 * case. */
8073 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8074 vmx_set_interrupt_shadow(vcpu, 0);
8075
d7cd9796 8076 atomic_switch_perf_msrs(vmx);
2a7921b7 8077 debugctlmsr = get_debugctlmsr();
d7cd9796 8078
d462b819 8079 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8080 asm(
6aa8b732 8081 /* Store host registers */
b188c81f
AK		 8082 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8083 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8084 "push %%" _ASM_CX " \n\t"
8085 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8086 "je 1f \n\t"
b188c81f 8087 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8088 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8089 "1: \n\t"
d3edefc0 8090 /* Reload cr2 if changed */
b188c81f
AK		 8091 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8092 "mov %%cr2, %%" _ASM_DX " \n\t"
8093 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8094 "je 2f \n\t"
b188c81f 8095 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8096 "2: \n\t"
6aa8b732 8097 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8098 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8099 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8100 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8101 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8102 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8103 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8104 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8105 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8106#ifdef CONFIG_X86_64
e08aa78a
AK		 8107 "mov %c[r8](%0), %%r8 \n\t"
8108 "mov %c[r9](%0), %%r9 \n\t"
8109 "mov %c[r10](%0), %%r10 \n\t"
8110 "mov %c[r11](%0), %%r11 \n\t"
8111 "mov %c[r12](%0), %%r12 \n\t"
8112 "mov %c[r13](%0), %%r13 \n\t"
8113 "mov %c[r14](%0), %%r14 \n\t"
8114 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8115#endif
b188c81f 8116 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8117
6aa8b732 8118 /* Enter guest mode */
83287ea4 8119 "jne 1f \n\t"
4ecac3fd 8120 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8121 "jmp 2f \n\t"
8122 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8123 "2: "
6aa8b732 8124 /* Save guest registers, load host registers, keep flags */
b188c81f 8125 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8126 "pop %0 \n\t"
b188c81f
AK		 8127 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8128 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8129 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8130 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8131 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8132 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8133 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8134#ifdef CONFIG_X86_64
e08aa78a
AK		 8135 "mov %%r8, %c[r8](%0) \n\t"
8136 "mov %%r9, %c[r9](%0) \n\t"
8137 "mov %%r10, %c[r10](%0) \n\t"
8138 "mov %%r11, %c[r11](%0) \n\t"
8139 "mov %%r12, %c[r12](%0) \n\t"
8140 "mov %%r13, %c[r13](%0) \n\t"
8141 "mov %%r14, %c[r14](%0) \n\t"
8142 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8143#endif
b188c81f
AK		 8144 "mov %%cr2, %%" _ASM_AX " \n\t"
8145 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8146
b188c81f 8147 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8148 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8149 ".pushsection .rodata \n\t"
8150 ".global vmx_return \n\t"
8151 "vmx_return: " _ASM_PTR " 2b \n\t"
8152 ".popsection"
e08aa78a 8153 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8154 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8155 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8156 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8157 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8158 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8159 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8160 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8161 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8162 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8163 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8164#ifdef CONFIG_X86_64
ad312c7c
ZX		 8165 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8166 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8167 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8168 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8169 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8170 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8171 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8172 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8173#endif
40712fae
AK		 8174 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8175 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8176 : "cc", "memory"
8177#ifdef CONFIG_X86_64
b188c81f 8178 , "rax", "rbx", "rdi", "rsi"
c2036300 8179 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8180#else
8181 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8182#endif
8183 );
6aa8b732 8184
2a7921b7
GN		 8185 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8186 if (debugctlmsr)
8187 update_debugctlmsr(debugctlmsr);
8188
aa67f609
AK		 8189#ifndef CONFIG_X86_64
8190 /*
8191 * The sysexit path does not restore ds/es, so we must set them to
8192 * a reasonable value ourselves.
8193 *
8194 * We can't defer this to vmx_load_host_state() since that function
8195 * may be executed in interrupt context, which saves and restore segments
8196 * around it, nullifying its effect.
8197 */
8198 loadsegment(ds, __USER_DS);
8199 loadsegment(es, __USER_DS);
8200#endif
8201
6de4f3ad 8202 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8203 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8204 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8205 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8206 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8207 vcpu->arch.regs_dirty = 0;
8208
1155f76a
AK		 8209 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8210
d462b819 8211 vmx->loaded_vmcs->launched = 1;
1b6269db 8212
51aa01d1 8213 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8214 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8215
e0b890d3
GN		 8216 /*
8217 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8218 * we did not inject a still-pending event to L1 now because of
8219 * nested_run_pending, we need to re-enable this bit.
8220 */
8221 if (vmx->nested.nested_run_pending)
8222 kvm_make_request(KVM_REQ_EVENT, vcpu);
8223
8224 vmx->nested.nested_run_pending = 0;
8225
51aa01d1
AK		 8226 vmx_complete_atomic_exit(vmx);
8227 vmx_recover_nmi_blocking(vmx);
cf393f75 8228 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8229}
8230
4fa7734c
PB		 8231static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8232{
8233 struct vcpu_vmx *vmx = to_vmx(vcpu);
8234 int cpu;
8235
8236 if (vmx->loaded_vmcs == &vmx->vmcs01)
8237 return;
8238
8239 cpu = get_cpu();
8240 vmx->loaded_vmcs = &vmx->vmcs01;
8241 vmx_vcpu_put(vcpu);
8242 vmx_vcpu_load(vcpu, cpu);
8243 vcpu->cpu = cpu;
8244 put_cpu();
8245}
8246
6aa8b732
AK		 8247static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8248{
fb3f0f51
RR		 8249 struct vcpu_vmx *vmx = to_vmx(vcpu);
8250
843e4330
KH		 8251 if (enable_pml)
8252 vmx_disable_pml(vmx);
cdbecfc3 8253 free_vpid(vmx);
4fa7734c
PB		 8254 leave_guest_mode(vcpu);
8255 vmx_load_vmcs01(vcpu);
26a865f4 8256 free_nested(vmx);
4fa7734c 8257 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8258 kfree(vmx->guest_msrs);
8259 kvm_vcpu_uninit(vcpu);
a4770347 8260 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8261}
8262
fb3f0f51 8263static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8264{
fb3f0f51 8265 int err;
c16f862d 8266 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8267 int cpu;
6aa8b732 8268
a2fa3e9f 8269 if (!vmx)
fb3f0f51
RR		 8270 return ERR_PTR(-ENOMEM);
8271
2384d2b3
SY		 8272 allocate_vpid(vmx);
8273
fb3f0f51
RR		 8274 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8275 if (err)
8276 goto free_vcpu;
965b58a5 8277
a2fa3e9f 8278 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8279 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8280 > PAGE_SIZE);
0123be42 8281
be6d05cf 8282 err = -ENOMEM;
fb3f0f51 8283 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8284 goto uninit_vcpu;
8285 }
965b58a5 8286
d462b819
NHE		 8287 vmx->loaded_vmcs = &vmx->vmcs01;
8288 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8289 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8290 goto free_msrs;
d462b819
NHE		 8291 if (!vmm_exclusive)
8292 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8293 loaded_vmcs_init(vmx->loaded_vmcs);
8294 if (!vmm_exclusive)
8295 kvm_cpu_vmxoff();
a2fa3e9f 8296
15ad7146
AK		 8297 cpu = get_cpu();
8298 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8299 vmx->vcpu.cpu = cpu;
8b9cf98c 8300 err = vmx_vcpu_setup(vmx);
fb3f0f51 8301 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8302 put_cpu();
fb3f0f51
RR		 8303 if (err)
8304 goto free_vmcs;
a63cb560 8305 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8306 err = alloc_apic_access_page(kvm);
8307 if (err)
5e4a0b3c 8308 goto free_vmcs;
a63cb560 8309 }
fb3f0f51 8310
b927a3ce
SY		 8311 if (enable_ept) {
8312 if (!kvm->arch.ept_identity_map_addr)
8313 kvm->arch.ept_identity_map_addr =
8314 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8315 err = init_rmode_identity_map(kvm);
8316 if (err)
93ea5388 8317 goto free_vmcs;
b927a3ce 8318 }
b7ebfb05 8319
b9c237bb
WV		 8320 if (nested)
8321 nested_vmx_setup_ctls_msrs(vmx);
8322
a9d30f33
NHE		 8323 vmx->nested.current_vmptr = -1ull;
8324 vmx->nested.current_vmcs12 = NULL;
8325
843e4330
KH		 8326 /*
8327 * If PML is turned on, failure on enabling PML just results in failure
8328 * of creating the vcpu, therefore we can simplify PML logic (by
8329 * avoiding dealing with cases, such as enabling PML partially on vcpus
8330 * for the guest, etc.
8331 */
8332 if (enable_pml) {
8333 err = vmx_enable_pml(vmx);
8334 if (err)
8335 goto free_vmcs;
8336 }
8337
fb3f0f51
RR		 8338 return &vmx->vcpu;
8339
8340free_vmcs:
5f3fbc34 8341 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8342free_msrs:
fb3f0f51
RR		 8343 kfree(vmx->guest_msrs);
8344uninit_vcpu:
8345 kvm_vcpu_uninit(&vmx->vcpu);
8346free_vcpu:
cdbecfc3 8347 free_vpid(vmx);
a4770347 8348 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8349 return ERR_PTR(err);
6aa8b732
AK		 8350}
8351
002c7f7c
YS		 8352static void __init vmx_check_processor_compat(void *rtn)
8353{
8354 struct vmcs_config vmcs_conf;
8355
8356 *(int *)rtn = 0;
8357 if (setup_vmcs_config(&vmcs_conf) < 0)
8358 *(int *)rtn = -EIO;
8359 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8360 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8361 smp_processor_id());
8362 *(int *)rtn = -EIO;
8363 }
8364}
8365
67253af5
SY		 8366static int get_ept_level(void)
8367{
8368 return VMX_EPT_DEFAULT_GAW + 1;
8369}
8370
4b12f0de 8371static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8372{
4b12f0de
SY		 8373 u64 ret;
8374
522c68c4
SY		 8375 /* For VT-d and EPT combination
8376 * 1. MMIO: always map as UC
8377 * 2. EPT with VT-d:
8378 * a. VT-d without snooping control feature: can't guarantee the
8379 * result, try to trust guest.
8380 * b. VT-d with snooping control feature: snooping control feature of
8381 * VT-d engine can guarantee the cache correctness. Just set it
8382 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8383 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8384 * consistent with host MTRR
8385 */
4b12f0de
SY		 8386 if (is_mmio)
8387 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8388 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8389 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8390 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8391 else
522c68c4 8392 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8393 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8394
8395 return ret;
64d4d521
SY		 8396}
8397
17cc3935 8398static int vmx_get_lpage_level(void)
344f414f 8399{
878403b7
SY		 8400 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8401 return PT_DIRECTORY_LEVEL;
8402 else
8403 /* For shadow and EPT supported 1GB page */
8404 return PT_PDPE_LEVEL;
344f414f
JR		 8405}
8406
0e851880
SY		 8407static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8408{
4e47c7a6
SY		 8409 struct kvm_cpuid_entry2 *best;
8410 struct vcpu_vmx *vmx = to_vmx(vcpu);
8411 u32 exec_control;
8412
8413 vmx->rdtscp_enabled = false;
8414 if (vmx_rdtscp_supported()) {
8415 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8416 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8417 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8418 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8419 vmx->rdtscp_enabled = true;
8420 else {
8421 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8422 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8423 exec_control);
8424 }
8425 }
8426 }
ad756a16 8427
ad756a16
MJ		 8428 /* Exposing INVPCID only when PCID is exposed */
8429 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8430 if (vmx_invpcid_supported() &&
4f977045 8431 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8432 guest_cpuid_has_pcid(vcpu)) {
29282fde 8433 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8434 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8435 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8436 exec_control);
8437 } else {
29282fde
TI		 8438 if (cpu_has_secondary_exec_ctrls()) {
8439 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8440 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8441 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8442 exec_control);
8443 }
ad756a16 8444 if (best)
4f977045 8445 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8446 }
0e851880
SY		 8447}
8448
d4330ef2
JR		 8449static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8450{
7b8050f5
NHE		 8451 if (func == 1 && nested)
8452 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8453}
8454
25d92081
YZ		 8455static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8456 struct x86_exception *fault)
8457{
533558bc
JK		 8458 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8459 u32 exit_reason;
25d92081
YZ		 8460
8461 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8462 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8463 else
533558bc
JK		 8464 exit_reason = EXIT_REASON_EPT_VIOLATION;
8465 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8466 vmcs12->guest_physical_address = fault->address;
8467}
8468
155a97a3
NHE		 8469/* Callbacks for nested_ept_init_mmu_context: */
8470
8471static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8472{
8473 /* return the page table to be shadowed - in our case, EPT12 */
8474 return get_vmcs12(vcpu)->ept_pointer;
8475}
8476
8a3c1a33 8477static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8478{
ad896af0
PB		 8479 WARN_ON(mmu_is_nested(vcpu));
8480 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8481 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8482 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8483 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8484 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8485 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8486
8487 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8488}
8489
8490static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8491{
8492 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8493}
8494
19d5f10b
EK		 8495static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8496 u16 error_code)
8497{
8498 bool inequality, bit;
8499
8500 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8501 inequality =
8502 (error_code & vmcs12->page_fault_error_code_mask) !=
8503 vmcs12->page_fault_error_code_match;
8504 return inequality ^ bit;
8505}
8506
feaf0c7d
GN		 8507static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8508 struct x86_exception *fault)
8509{
8510 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8511
8512 WARN_ON(!is_guest_mode(vcpu));
8513
19d5f10b 8514 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8515 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8516 vmcs_read32(VM_EXIT_INTR_INFO),
8517 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8518 else
8519 kvm_inject_page_fault(vcpu, fault);
8520}
8521
a2bcba50
WL		 8522static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8523 struct vmcs12 *vmcs12)
8524{
8525 struct vcpu_vmx *vmx = to_vmx(vcpu);
8526
8527 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8528 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8529 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8530 return false;
8531
8532 /*
8533 * Translate L1 physical address to host physical
8534 * address for vmcs02. Keep the page pinned, so this
8535 * physical address remains valid. We keep a reference
8536 * to it so we can release it later.
8537 */
8538 if (vmx->nested.apic_access_page) /* shouldn't happen */
8539 nested_release_page(vmx->nested.apic_access_page);
8540 vmx->nested.apic_access_page =
8541 nested_get_page(vcpu, vmcs12->apic_access_addr);
8542 }
a7c0b07d
WL		 8543
8544 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8545 /* TODO: Also verify bits beyond physical address width are 0 */
8546 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8547 return false;
8548
8549 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8550 nested_release_page(vmx->nested.virtual_apic_page);
8551 vmx->nested.virtual_apic_page =
8552 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8553
8554 /*
8555 * Failing the vm entry is _not_ what the processor does
8556 * but it's basically the only possibility we have.
8557 * We could still enter the guest if CR8 load exits are
8558 * enabled, CR8 store exits are enabled, and virtualize APIC
8559 * access is disabled; in this case the processor would never
8560 * use the TPR shadow and we could simply clear the bit from
8561 * the execution control. But such a configuration is useless,
8562 * so let's keep the code simple.
8563 */
8564 if (!vmx->nested.virtual_apic_page)
8565 return false;
8566 }
8567
a2bcba50
WL		 8568 return true;
8569}
8570
f4124500
JK		 8571static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8572{
8573 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8574 struct vcpu_vmx *vmx = to_vmx(vcpu);
8575
8576 if (vcpu->arch.virtual_tsc_khz == 0)
8577 return;
8578
8579 /* Make sure short timeouts reliably trigger an immediate vmexit.
8580 * hrtimer_start does not guarantee this. */
8581 if (preemption_timeout <= 1) {
8582 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8583 return;
8584 }
8585
8586 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8587 preemption_timeout *= 1000000;
8588 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8589 hrtimer_start(&vmx->nested.preemption_timer,
8590 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8591}
8592
3af18d9c
WV		 8593static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8594 struct vmcs12 *vmcs12)
8595{
8596 int maxphyaddr;
8597 u64 addr;
8598
8599 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8600 return 0;
8601
8602 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8603 WARN_ON(1);
8604 return -EINVAL;
8605 }
8606 maxphyaddr = cpuid_maxphyaddr(vcpu);
8607
8608 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8609 ((addr + PAGE_SIZE) >> maxphyaddr))
8610 return -EINVAL;
8611
8612 return 0;
8613}
8614
8615/*
8616 * Merge L0's and L1's MSR bitmap, return false to indicate that
8617 * we do not use the hardware.
8618 */
8619static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8620 struct vmcs12 *vmcs12)
8621{
82f0dd4b 8622 int msr;
f2b93280
WV		 8623 struct page *page;
8624 unsigned long *msr_bitmap;
8625
8626 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8627 return false;
8628
8629 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8630 if (!page) {
8631 WARN_ON(1);
8632 return false;
8633 }
8634 msr_bitmap = (unsigned long *)kmap(page);
8635 if (!msr_bitmap) {
8636 nested_release_page_clean(page);
8637 WARN_ON(1);
8638 return false;
8639 }
8640
8641 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8642 if (nested_cpu_has_apic_reg_virt(vmcs12))
8643 for (msr = 0x800; msr <= 0x8ff; msr++)
8644 nested_vmx_disable_intercept_for_msr(
8645 msr_bitmap,
8646 vmx_msr_bitmap_nested,
8647 msr, MSR_TYPE_R);
f2b93280
WV		 8648 /* TPR is allowed */
8649 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8650 vmx_msr_bitmap_nested,
8651 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8652 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8653 if (nested_cpu_has_vid(vmcs12)) {
8654 /* EOI and self-IPI are allowed */
8655 nested_vmx_disable_intercept_for_msr(
8656 msr_bitmap,
8657 vmx_msr_bitmap_nested,
8658 APIC_BASE_MSR + (APIC_EOI >> 4),
8659 MSR_TYPE_W);
8660 nested_vmx_disable_intercept_for_msr(
8661 msr_bitmap,
8662 vmx_msr_bitmap_nested,
8663 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8664 MSR_TYPE_W);
8665 }
82f0dd4b
WV		 8666 } else {
8667 /*
8668 * Enable reading intercept of all the x2apic
8669 * MSRs. We should not rely on vmcs12 to do any
8670 * optimizations here, it may have been modified
8671 * by L1.
8672 */
8673 for (msr = 0x800; msr <= 0x8ff; msr++)
8674 __vmx_enable_intercept_for_msr(
8675 vmx_msr_bitmap_nested,
8676 msr,
8677 MSR_TYPE_R);
8678
f2b93280
WV		 8679 __vmx_enable_intercept_for_msr(
8680 vmx_msr_bitmap_nested,
8681 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8682 MSR_TYPE_W);
608406e2
WV		 8683 __vmx_enable_intercept_for_msr(
8684 vmx_msr_bitmap_nested,
8685 APIC_BASE_MSR + (APIC_EOI >> 4),
8686 MSR_TYPE_W);
8687 __vmx_enable_intercept_for_msr(
8688 vmx_msr_bitmap_nested,
8689 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8690 MSR_TYPE_W);
82f0dd4b 8691 }
f2b93280
WV		 8692 kunmap(page);
8693 nested_release_page_clean(page);
8694
8695 return true;
8696}
8697
8698static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8699 struct vmcs12 *vmcs12)
8700{
82f0dd4b 8701 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2
WV		 8702 !nested_cpu_has_apic_reg_virt(vmcs12) &&
8703 !nested_cpu_has_vid(vmcs12))
f2b93280
WV		 8704 return 0;
8705
8706 /*
8707 * If virtualize x2apic mode is enabled,
8708 * virtualize apic access must be disabled.
8709 */
82f0dd4b
WV		 8710 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8711 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 8712 return -EINVAL;
8713
608406e2
WV		 8714 /*
8715 * If virtual interrupt delivery is enabled,
8716 * we must exit on external interrupts.
8717 */
8718 if (nested_cpu_has_vid(vmcs12) &&
8719 !nested_exit_on_intr(vcpu))
8720 return -EINVAL;
8721
f2b93280
WV		 8722 /* tpr shadow is needed by all apicv features. */
8723 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8724 return -EINVAL;
8725
8726 return 0;
3af18d9c
WV		 8727}
8728
e9ac033e
EK		 8729static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8730 unsigned long count_field,
8731 unsigned long addr_field,
8732 int maxphyaddr)
ff651cb6 8733{
e9ac033e
EK		 8734 u64 count, addr;
8735
8736 if (vmcs12_read_any(vcpu, count_field, &count) ||
8737 vmcs12_read_any(vcpu, addr_field, &addr)) {
8738 WARN_ON(1);
8739 return -EINVAL;
8740 }
8741 if (count == 0)
8742 return 0;
8743 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8744 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8745 pr_warn_ratelimited(
8746 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8747 addr_field, maxphyaddr, count, addr);
8748 return -EINVAL;
8749 }
8750 return 0;
8751}
8752
8753static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8754 struct vmcs12 *vmcs12)
8755{
8756 int maxphyaddr;
8757
8758 if (vmcs12->vm_exit_msr_load_count == 0 &&
8759 vmcs12->vm_exit_msr_store_count == 0 &&
8760 vmcs12->vm_entry_msr_load_count == 0)
8761 return 0; /* Fast path */
8762 maxphyaddr = cpuid_maxphyaddr(vcpu);
8763 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8764 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8765 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8766 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8767 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8768 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8769 return -EINVAL;
8770 return 0;
8771}
8772
8773static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8774 struct vmx_msr_entry *e)
8775{
8776 /* x2APIC MSR accesses are not allowed */
8777 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8778 return -EINVAL;
8779 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8780 e->index == MSR_IA32_UCODE_REV)
8781 return -EINVAL;
8782 if (e->reserved != 0)
ff651cb6
WV		 8783 return -EINVAL;
8784 return 0;
8785}
8786
e9ac033e
EK		 8787static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8788 struct vmx_msr_entry *e)
ff651cb6
WV		 8789{
8790 if (e->index == MSR_FS_BASE ||
8791 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8792 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8793 nested_vmx_msr_check_common(vcpu, e))
8794 return -EINVAL;
8795 return 0;
8796}
8797
8798static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8799 struct vmx_msr_entry *e)
8800{
8801 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8802 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8803 return -EINVAL;
8804 return 0;
8805}
8806
8807/*
8808 * Load guest's/host's msr at nested entry/exit.
8809 * return 0 for success, entry index for failure.
8810 */
8811static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8812{
8813 u32 i;
8814 struct vmx_msr_entry e;
8815 struct msr_data msr;
8816
8817 msr.host_initiated = false;
8818 for (i = 0; i < count; i++) {
e9ac033e
EK		 8819 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8820 &e, sizeof(e))) {
8821 pr_warn_ratelimited(
8822 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8823 __func__, i, gpa + i * sizeof(e));
ff651cb6 8824 goto fail;
e9ac033e
EK		 8825 }
8826 if (nested_vmx_load_msr_check(vcpu, &e)) {
8827 pr_warn_ratelimited(
8828 "%s check failed (%u, 0x%x, 0x%x)\n",
8829 __func__, i, e.index, e.reserved);
8830 goto fail;
8831 }
ff651cb6
WV		 8832 msr.index = e.index;
8833 msr.data = e.value;
e9ac033e
EK		 8834 if (kvm_set_msr(vcpu, &msr)) {
8835 pr_warn_ratelimited(
8836 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8837 __func__, i, e.index, e.value);
ff651cb6 8838 goto fail;
e9ac033e 8839 }
ff651cb6
WV		 8840 }
8841 return 0;
8842fail:
8843 return i + 1;
8844}
8845
8846static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8847{
8848 u32 i;
8849 struct vmx_msr_entry e;
8850
8851 for (i = 0; i < count; i++) {
e9ac033e
EK		 8852 if (kvm_read_guest(vcpu->kvm,
8853 gpa + i * sizeof(e),
8854 &e, 2 * sizeof(u32))) {
8855 pr_warn_ratelimited(
8856 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8857 __func__, i, gpa + i * sizeof(e));
ff651cb6 8858 return -EINVAL;
e9ac033e
EK		 8859 }
8860 if (nested_vmx_store_msr_check(vcpu, &e)) {
8861 pr_warn_ratelimited(
8862 "%s check failed (%u, 0x%x, 0x%x)\n",
8863 __func__, i, e.index, e.reserved);
ff651cb6 8864 return -EINVAL;
e9ac033e
EK		 8865 }
8866 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8867 pr_warn_ratelimited(
8868 "%s cannot read MSR (%u, 0x%x)\n",
8869 __func__, i, e.index);
8870 return -EINVAL;
8871 }
8872 if (kvm_write_guest(vcpu->kvm,
8873 gpa + i * sizeof(e) +
ff651cb6 8874 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 8875 &e.value, sizeof(e.value))) {
8876 pr_warn_ratelimited(
8877 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8878 __func__, i, e.index, e.value);
8879 return -EINVAL;
8880 }
ff651cb6
WV		 8881 }
8882 return 0;
8883}
8884
fe3ef05c
NHE		 8885/*
8886 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8887 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8888 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8889 * guest in a way that will both be appropriate to L1's requests, and our
8890 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8891 * function also has additional necessary side-effects, like setting various
8892 * vcpu->arch fields.
8893 */
8894static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8895{
8896 struct vcpu_vmx *vmx = to_vmx(vcpu);
8897 u32 exec_control;
8898
8899 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8900 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8901 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8902 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8903 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8904 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8905 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8906 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8907 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8908 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8909 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8910 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8911 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8912 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8913 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8914 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8915 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8916 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8917 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8918 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8919 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8920 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8921 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8922 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8923 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8924 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8925 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8926 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8927 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8928 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8929 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8930 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8931 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8932 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8933 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8934 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8935
2996fca0
JK		 8936 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8937 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8938 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8939 } else {
8940 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8941 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8942 }
fe3ef05c
NHE		 8943 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8944 vmcs12->vm_entry_intr_info_field);
8945 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8946 vmcs12->vm_entry_exception_error_code);
8947 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8948 vmcs12->vm_entry_instruction_len);
8949 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8950 vmcs12->guest_interruptibility_info);
fe3ef05c 8951 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8952 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8953 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8954 vmcs12->guest_pending_dbg_exceptions);
8955 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8956 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8957
81dc01f7
WL		 8958 if (nested_cpu_has_xsaves(vmcs12))
8959 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 8960 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8961
f4124500
JK		 8962 exec_control = vmcs12->pin_based_vm_exec_control;
8963 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8964 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8965 PIN_BASED_POSTED_INTR);
f4124500 8966 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8967
f4124500
JK		 8968 vmx->nested.preemption_timer_expired = false;
8969 if (nested_cpu_has_preemption_timer(vmcs12))
8970 vmx_start_preemption_timer(vcpu);
0238ea91 8971
fe3ef05c
NHE		 8972 /*
8973 * Whether page-faults are trapped is determined by a combination of
8974 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8975 * If enable_ept, L0 doesn't care about page faults and we should
8976 * set all of these to L1's desires. However, if !enable_ept, L0 does
8977 * care about (at least some) page faults, and because it is not easy
8978 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8979 * to exit on each and every L2 page fault. This is done by setting
8980 * MASK=MATCH=0 and (see below) EB.PF=1.
8981 * Note that below we don't need special code to set EB.PF beyond the
8982 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8983 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8984 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8985 *
8986 * A problem with this approach (when !enable_ept) is that L1 may be
8987 * injected with more page faults than it asked for. This could have
8988 * caused problems, but in practice existing hypervisors don't care.
8989 * To fix this, we will need to emulate the PFEC checking (on the L1
8990 * page tables), using walk_addr(), when injecting PFs to L1.
8991 */
8992 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8993 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8994 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8995 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8996
8997 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8998 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8999 if (!vmx->rdtscp_enabled)
9000 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9001 /* Take the following fields only from vmcs12 */
696dfd95
PB		 9002 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9003 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9004 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 9005 if (nested_cpu_has(vmcs12,
9006 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9007 exec_control |= vmcs12->secondary_vm_exec_control;
9008
9009 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9010 /*
9011 * If translation failed, no matter: This feature asks
9012 * to exit when accessing the given address, and if it
9013 * can never be accessed, this feature won't do
9014 * anything anyway.
9015 */
9016 if (!vmx->nested.apic_access_page)
9017 exec_control &=
9018 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9019 else
9020 vmcs_write64(APIC_ACCESS_ADDR,
9021 page_to_phys(vmx->nested.apic_access_page));
f2b93280
WV		 9022 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9023 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
ca3f257a
JK		 9024 exec_control |=
9025 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9026 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9027 }
9028
608406e2
WV		 9029 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9030 vmcs_write64(EOI_EXIT_BITMAP0,
9031 vmcs12->eoi_exit_bitmap0);
9032 vmcs_write64(EOI_EXIT_BITMAP1,
9033 vmcs12->eoi_exit_bitmap1);
9034 vmcs_write64(EOI_EXIT_BITMAP2,
9035 vmcs12->eoi_exit_bitmap2);
9036 vmcs_write64(EOI_EXIT_BITMAP3,
9037 vmcs12->eoi_exit_bitmap3);
9038 vmcs_write16(GUEST_INTR_STATUS,
9039 vmcs12->guest_intr_status);
9040 }
9041
fe3ef05c
NHE		 9042 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9043 }
9044
9045
9046 /*
9047 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9048 * Some constant fields are set here by vmx_set_constant_host_state().
9049 * Other fields are different per CPU, and will be set later when
9050 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9051 */
a547c6db 9052 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9053
9054 /*
9055 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9056 * entry, but only if the current (host) sp changed from the value
9057 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9058 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9059 * here we just force the write to happen on entry.
9060 */
9061 vmx->host_rsp = 0;
9062
9063 exec_control = vmx_exec_control(vmx); /* L0's desires */
9064 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9065 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9066 exec_control &= ~CPU_BASED_TPR_SHADOW;
9067 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9068
9069 if (exec_control & CPU_BASED_TPR_SHADOW) {
9070 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9071 page_to_phys(vmx->nested.virtual_apic_page));
9072 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9073 }
9074
3af18d9c
WV		 9075 if (cpu_has_vmx_msr_bitmap() &&
9076 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9077 nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) {
9078 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_nested));
9079 } else
9080 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9081
fe3ef05c 9082 /*
3af18d9c 9083 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9084 * Rather, exit every time.
9085 */
fe3ef05c
NHE		 9086 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9087 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9088
9089 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9090
9091 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9092 * bitwise-or of what L1 wants to trap for L2, and what we want to
9093 * trap. Note that CR0.TS also needs updating - we do this later.
9094 */
9095 update_exception_bitmap(vcpu);
9096 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9097 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9098
8049d651
NHE		 9099 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9100 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9101 * bits are further modified by vmx_set_efer() below.
9102 */
f4124500 9103 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9104
9105 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9106 * emulated by vmx_set_efer(), below.
9107 */
2961e876 9108 vm_entry_controls_init(vmx,
8049d651
NHE		 9109 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9110 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9111 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9112
44811c02 9113 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9114 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9115 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9116 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9117 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9118
9119
9120 set_cr4_guest_host_mask(vmx);
9121
36be0b9d
PB		 9122 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9123 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9124
27fc51b2
NHE		 9125 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9126 vmcs_write64(TSC_OFFSET,
9127 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9128 else
9129 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9130
9131 if (enable_vpid) {
9132 /*
9133 * Trivially support vpid by letting L2s share their parent
9134 * L1's vpid. TODO: move to a more elaborate solution, giving
9135 * each L2 its own vpid and exposing the vpid feature to L1.
9136 */
9137 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9138 vmx_flush_tlb(vcpu);
9139 }
9140
155a97a3
NHE		 9141 if (nested_cpu_has_ept(vmcs12)) {
9142 kvm_mmu_unload(vcpu);
9143 nested_ept_init_mmu_context(vcpu);
9144 }
9145
fe3ef05c
NHE		 9146 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9147 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9148 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9149 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9150 else
9151 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9152 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9153 vmx_set_efer(vcpu, vcpu->arch.efer);
9154
9155 /*
9156 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9157 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9158 * The CR0_READ_SHADOW is what L2 should have expected to read given
9159 * the specifications by L1; It's not enough to take
9160 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9161 * have more bits than L1 expected.
9162 */
9163 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9164 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9165
9166 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9167 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9168
9169 /* shadow page tables on either EPT or shadow page tables */
9170 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9171 kvm_mmu_reset_context(vcpu);
9172
feaf0c7d
GN		 9173 if (!enable_ept)
9174 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9175
3633cfc3
NHE		 9176 /*
9177 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9178 */
9179 if (enable_ept) {
9180 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9181 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9182 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9183 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9184 }
9185
fe3ef05c
NHE		 9186 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9187 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9188}
9189
cd232ad0
NHE		 9190/*
9191 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9192 * for running an L2 nested guest.
9193 */
9194static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9195{
9196 struct vmcs12 *vmcs12;
9197 struct vcpu_vmx *vmx = to_vmx(vcpu);
9198 int cpu;
9199 struct loaded_vmcs *vmcs02;
384bb783 9200 bool ia32e;
ff651cb6 9201 u32 msr_entry_idx;
cd232ad0
NHE		 9202
9203 if (!nested_vmx_check_permission(vcpu) ||
9204 !nested_vmx_check_vmcs12(vcpu))
9205 return 1;
9206
9207 skip_emulated_instruction(vcpu);
9208 vmcs12 = get_vmcs12(vcpu);
9209
012f83cb
AG		 9210 if (enable_shadow_vmcs)
9211 copy_shadow_to_vmcs12(vmx);
9212
7c177938
NHE		 9213 /*
9214 * The nested entry process starts with enforcing various prerequisites
9215 * on vmcs12 as required by the Intel SDM, and act appropriately when
9216 * they fail: As the SDM explains, some conditions should cause the
9217 * instruction to fail, while others will cause the instruction to seem
9218 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9219 * To speed up the normal (success) code path, we should avoid checking
9220 * for misconfigurations which will anyway be caught by the processor
9221 * when using the merged vmcs02.
9222 */
9223 if (vmcs12->launch_state == launch) {
9224 nested_vmx_failValid(vcpu,
9225 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9226 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9227 return 1;
9228 }
9229
6dfacadd
JK		 9230 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9231 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9232 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9233 return 1;
9234 }
9235
3af18d9c 9236 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9237 /*TODO: Also verify bits beyond physical address width are 0*/
9238 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9239 return 1;
9240 }
9241
3af18d9c 9242 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9243 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9244 return 1;
9245 }
9246
f2b93280
WV		 9247 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9248 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9249 return 1;
9250 }
9251
e9ac033e
EK		 9252 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9253 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9254 return 1;
9255 }
9256
7c177938 9257 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9258 vmx->nested.nested_vmx_true_procbased_ctls_low,
9259 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9260 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9261 vmx->nested.nested_vmx_secondary_ctls_low,
9262 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9263 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9264 vmx->nested.nested_vmx_pinbased_ctls_low,
9265 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9266 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9267 vmx->nested.nested_vmx_true_exit_ctls_low,
9268 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9269 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9270 vmx->nested.nested_vmx_true_entry_ctls_low,
9271 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9272 {
9273 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9274 return 1;
9275 }
9276
9277 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9278 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9279 nested_vmx_failValid(vcpu,
9280 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9281 return 1;
9282 }
9283
b9c237bb 9284 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9285 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9286 nested_vmx_entry_failure(vcpu, vmcs12,
9287 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9288 return 1;
9289 }
9290 if (vmcs12->vmcs_link_pointer != -1ull) {
9291 nested_vmx_entry_failure(vcpu, vmcs12,
9292 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9293 return 1;
9294 }
9295
384bb783 9296 /*
cb0c8cda 9297 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9298 * are performed on the field for the IA32_EFER MSR:
9299 * - Bits reserved in the IA32_EFER MSR must be 0.
9300 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9301 * the IA-32e mode guest VM-exit control. It must also be identical
9302 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9303 * CR0.PG) is 1.
9304 */
9305 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9306 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9307 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9308 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9309 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9310 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9311 nested_vmx_entry_failure(vcpu, vmcs12,
9312 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9313 return 1;
9314 }
9315 }
9316
9317 /*
9318 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9319 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9320 * the values of the LMA and LME bits in the field must each be that of
9321 * the host address-space size VM-exit control.
9322 */
9323 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9324 ia32e = (vmcs12->vm_exit_controls &
9325 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9326 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9327 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9328 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9329 nested_vmx_entry_failure(vcpu, vmcs12,
9330 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9331 return 1;
9332 }
9333 }
9334
7c177938
NHE		 9335 /*
9336 * We're finally done with prerequisite checking, and can start with
9337 * the nested entry.
9338 */
9339
cd232ad0
NHE		 9340 vmcs02 = nested_get_current_vmcs02(vmx);
9341 if (!vmcs02)
9342 return -ENOMEM;
9343
9344 enter_guest_mode(vcpu);
9345
9346 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9347
2996fca0
JK		 9348 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9349 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9350
cd232ad0
NHE		 9351 cpu = get_cpu();
9352 vmx->loaded_vmcs = vmcs02;
9353 vmx_vcpu_put(vcpu);
9354 vmx_vcpu_load(vcpu, cpu);
9355 vcpu->cpu = cpu;
9356 put_cpu();
9357
36c3cc42
JK		 9358 vmx_segment_cache_clear(vmx);
9359
cd232ad0
NHE		 9360 prepare_vmcs02(vcpu, vmcs12);
9361
ff651cb6
WV		 9362 msr_entry_idx = nested_vmx_load_msr(vcpu,
9363 vmcs12->vm_entry_msr_load_addr,
9364 vmcs12->vm_entry_msr_load_count);
9365 if (msr_entry_idx) {
9366 leave_guest_mode(vcpu);
9367 vmx_load_vmcs01(vcpu);
9368 nested_vmx_entry_failure(vcpu, vmcs12,
9369 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9370 return 1;
9371 }
9372
9373 vmcs12->launch_state = 1;
9374
6dfacadd
JK		 9375 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9376 return kvm_emulate_halt(vcpu);
9377
7af40ad3
JK		 9378 vmx->nested.nested_run_pending = 1;
9379
cd232ad0
NHE		 9380 /*
9381 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9382 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9383 * returned as far as L1 is concerned. It will only return (and set
9384 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9385 */
9386 return 1;
9387}
9388
4704d0be
NHE		 9389/*
9390 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9391 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9392 * This function returns the new value we should put in vmcs12.guest_cr0.
9393 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9394 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9395 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9396 * didn't trap the bit, because if L1 did, so would L0).
9397 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9398 * been modified by L2, and L1 knows it. So just leave the old value of
9399 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9400 * isn't relevant, because if L0 traps this bit it can set it to anything.
9401 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9402 * changed these bits, and therefore they need to be updated, but L0
9403 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9404 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9405 */
9406static inline unsigned long
9407vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9408{
9409 return
9410 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9411 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9412 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9413 vcpu->arch.cr0_guest_owned_bits));
9414}
9415
9416static inline unsigned long
9417vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9418{
9419 return
9420 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9421 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9422 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9423 vcpu->arch.cr4_guest_owned_bits));
9424}
9425
5f3d5799
JK		 9426static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9427 struct vmcs12 *vmcs12)
9428{
9429 u32 idt_vectoring;
9430 unsigned int nr;
9431
851eb667 9432 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9433 nr = vcpu->arch.exception.nr;
9434 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9435
9436 if (kvm_exception_is_soft(nr)) {
9437 vmcs12->vm_exit_instruction_len =
9438 vcpu->arch.event_exit_inst_len;
9439 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9440 } else
9441 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9442
9443 if (vcpu->arch.exception.has_error_code) {
9444 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9445 vmcs12->idt_vectoring_error_code =
9446 vcpu->arch.exception.error_code;
9447 }
9448
9449 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9450 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9451 vmcs12->idt_vectoring_info_field =
9452 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9453 } else if (vcpu->arch.interrupt.pending) {
9454 nr = vcpu->arch.interrupt.nr;
9455 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9456
9457 if (vcpu->arch.interrupt.soft) {
9458 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9459 vmcs12->vm_entry_instruction_len =
9460 vcpu->arch.event_exit_inst_len;
9461 } else
9462 idt_vectoring |= INTR_TYPE_EXT_INTR;
9463
9464 vmcs12->idt_vectoring_info_field = idt_vectoring;
9465 }
9466}
9467
b6b8a145
JK		 9468static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9469{
9470 struct vcpu_vmx *vmx = to_vmx(vcpu);
9471
f4124500
JK		 9472 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9473 vmx->nested.preemption_timer_expired) {
9474 if (vmx->nested.nested_run_pending)
9475 return -EBUSY;
9476 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9477 return 0;
9478 }
9479
b6b8a145 9480 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9481 if (vmx->nested.nested_run_pending ||
9482 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9483 return -EBUSY;
9484 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9485 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9486 INTR_INFO_VALID_MASK, 0);
9487 /*
9488 * The NMI-triggered VM exit counts as injection:
9489 * clear this one and block further NMIs.
9490 */
9491 vcpu->arch.nmi_pending = 0;
9492 vmx_set_nmi_mask(vcpu, true);
9493 return 0;
9494 }
9495
9496 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9497 nested_exit_on_intr(vcpu)) {
9498 if (vmx->nested.nested_run_pending)
9499 return -EBUSY;
9500 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9501 }
9502
9503 return 0;
9504}
9505
f4124500
JK		 9506static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9507{
9508 ktime_t remaining =
9509 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9510 u64 value;
9511
9512 if (ktime_to_ns(remaining) <= 0)
9513 return 0;
9514
9515 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9516 do_div(value, 1000000);
9517 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9518}
9519
4704d0be
NHE		 9520/*
9521 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9522 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9523 * and this function updates it to reflect the changes to the guest state while
9524 * L2 was running (and perhaps made some exits which were handled directly by L0
9525 * without going back to L1), and to reflect the exit reason.
9526 * Note that we do not have to copy here all VMCS fields, just those that
9527 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9528 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9529 * which already writes to vmcs12 directly.
9530 */
533558bc
JK		 9531static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9532 u32 exit_reason, u32 exit_intr_info,
9533 unsigned long exit_qualification)
4704d0be
NHE		 9534{
9535 /* update guest state fields: */
9536 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9537 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9538
4704d0be
NHE		 9539 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9540 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9541 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9542
9543 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9544 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9545 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9546 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9547 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9548 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9549 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9550 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9551 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9552 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9553 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9554 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9555 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9556 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9557 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9558 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9559 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9560 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9561 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9562 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9563 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9564 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9565 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9566 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9567 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9568 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9569 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9570 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9571 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9572 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9573 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9574 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9575 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9576 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9577 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9578 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9579
4704d0be
NHE		 9580 vmcs12->guest_interruptibility_info =
9581 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9582 vmcs12->guest_pending_dbg_exceptions =
9583 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9584 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9585 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9586 else
9587 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9588
f4124500
JK		 9589 if (nested_cpu_has_preemption_timer(vmcs12)) {
9590 if (vmcs12->vm_exit_controls &
9591 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9592 vmcs12->vmx_preemption_timer_value =
9593 vmx_get_preemption_timer_value(vcpu);
9594 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9595 }
7854cbca 9596
3633cfc3
NHE		 9597 /*
9598 * In some cases (usually, nested EPT), L2 is allowed to change its
9599 * own CR3 without exiting. If it has changed it, we must keep it.
9600 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9601 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9602 *
9603 * Additionally, restore L2's PDPTR to vmcs12.
9604 */
9605 if (enable_ept) {
9606 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9607 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9608 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9609 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9610 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9611 }
9612
608406e2
WV		 9613 if (nested_cpu_has_vid(vmcs12))
9614 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9615
c18911a2
JK		 9616 vmcs12->vm_entry_controls =
9617 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9618 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9619
2996fca0
JK		 9620 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9621 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9622 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9623 }
9624
4704d0be
NHE		 9625 /* TODO: These cannot have changed unless we have MSR bitmaps and
9626 * the relevant bit asks not to trap the change */
b8c07d55 9627 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9628 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9629 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9630 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9631 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9632 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9633 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9634 if (vmx_mpx_supported())
9635 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9636 if (nested_cpu_has_xsaves(vmcs12))
9637 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9638
9639 /* update exit information fields: */
9640
533558bc
JK		 9641 vmcs12->vm_exit_reason = exit_reason;
9642 vmcs12->exit_qualification = exit_qualification;
4704d0be 9643
533558bc 9644 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9645 if ((vmcs12->vm_exit_intr_info &
9646 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9647 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9648 vmcs12->vm_exit_intr_error_code =
9649 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9650 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9651 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9652 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9653
5f3d5799
JK		 9654 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9655 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9656 * instead of reading the real value. */
4704d0be 9657 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9658
9659 /*
9660 * Transfer the event that L0 or L1 may wanted to inject into
9661 * L2 to IDT_VECTORING_INFO_FIELD.
9662 */
9663 vmcs12_save_pending_event(vcpu, vmcs12);
9664 }
9665
9666 /*
9667 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9668 * preserved above and would only end up incorrectly in L1.
9669 */
9670 vcpu->arch.nmi_injected = false;
9671 kvm_clear_exception_queue(vcpu);
9672 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9673}
9674
9675/*
9676 * A part of what we need to when the nested L2 guest exits and we want to
9677 * run its L1 parent, is to reset L1's guest state to the host state specified
9678 * in vmcs12.
9679 * This function is to be called not only on normal nested exit, but also on
9680 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9681 * Failures During or After Loading Guest State").
9682 * This function should be called when the active VMCS is L1's (vmcs01).
9683 */
733568f9
JK		 9684static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9685 struct vmcs12 *vmcs12)
4704d0be 9686{
21feb4eb
ACL		 9687 struct kvm_segment seg;
9688
4704d0be
NHE		 9689 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9690 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9691 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9692 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9693 else
9694 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9695 vmx_set_efer(vcpu, vcpu->arch.efer);
9696
9697 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9698 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9699 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9700 /*
9701 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9702 * actually changed, because it depends on the current state of
9703 * fpu_active (which may have changed).
9704 * Note that vmx_set_cr0 refers to efer set above.
9705 */
9e3e4dbf 9706 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9707 /*
9708 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9709 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9710 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9711 */
9712 update_exception_bitmap(vcpu);
9713 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9714 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9715
9716 /*
9717 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9718 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9719 */
9720 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9721 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9722
29bf08f1 9723 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9724
4704d0be
NHE		 9725 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9726 kvm_mmu_reset_context(vcpu);
9727
feaf0c7d
GN		 9728 if (!enable_ept)
9729 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9730
4704d0be
NHE		 9731 if (enable_vpid) {
9732 /*
9733 * Trivially support vpid by letting L2s share their parent
9734 * L1's vpid. TODO: move to a more elaborate solution, giving
9735 * each L2 its own vpid and exposing the vpid feature to L1.
9736 */
9737 vmx_flush_tlb(vcpu);
9738 }
9739
9740
9741 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9742 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9743 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9744 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9745 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9746
36be0b9d
PB		 9747 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9748 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9749 vmcs_write64(GUEST_BNDCFGS, 0);
9750
44811c02 9751 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9752 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9753 vcpu->arch.pat = vmcs12->host_ia32_pat;
9754 }
4704d0be
NHE		 9755 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9756 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9757 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9758
21feb4eb
ACL		 9759 /* Set L1 segment info according to Intel SDM
9760 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9761 seg = (struct kvm_segment) {
9762 .base = 0,
9763 .limit = 0xFFFFFFFF,
9764 .selector = vmcs12->host_cs_selector,
9765 .type = 11,
9766 .present = 1,
9767 .s = 1,
9768 .g = 1
9769 };
9770 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9771 seg.l = 1;
9772 else
9773 seg.db = 1;
9774 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9775 seg = (struct kvm_segment) {
9776 .base = 0,
9777 .limit = 0xFFFFFFFF,
9778 .type = 3,
9779 .present = 1,
9780 .s = 1,
9781 .db = 1,
9782 .g = 1
9783 };
9784 seg.selector = vmcs12->host_ds_selector;
9785 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9786 seg.selector = vmcs12->host_es_selector;
9787 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9788 seg.selector = vmcs12->host_ss_selector;
9789 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9790 seg.selector = vmcs12->host_fs_selector;
9791 seg.base = vmcs12->host_fs_base;
9792 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9793 seg.selector = vmcs12->host_gs_selector;
9794 seg.base = vmcs12->host_gs_base;
9795 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9796 seg = (struct kvm_segment) {
205befd9 9797 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9798 .limit = 0x67,
9799 .selector = vmcs12->host_tr_selector,
9800 .type = 11,
9801 .present = 1
9802 };
9803 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9804
503cd0c5
JK		 9805 kvm_set_dr(vcpu, 7, 0x400);
9806 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 9807
3af18d9c
WV		 9808 if (cpu_has_vmx_msr_bitmap())
9809 vmx_set_msr_bitmap(vcpu);
9810
ff651cb6
WV		 9811 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9812 vmcs12->vm_exit_msr_load_count))
9813 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9814}
9815
9816/*
9817 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9818 * and modify vmcs12 to make it see what it would expect to see there if
9819 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9820 */
533558bc
JK		 9821static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9822 u32 exit_intr_info,
9823 unsigned long exit_qualification)
4704d0be
NHE		 9824{
9825 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9826 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9827
5f3d5799
JK		 9828 /* trying to cancel vmlaunch/vmresume is a bug */
9829 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9830
4704d0be 9831 leave_guest_mode(vcpu);
533558bc
JK		 9832 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9833 exit_qualification);
4704d0be 9834
ff651cb6
WV		 9835 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9836 vmcs12->vm_exit_msr_store_count))
9837 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9838
f3380ca5
WL		 9839 vmx_load_vmcs01(vcpu);
9840
77b0f5d6
BD		 9841 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9842 && nested_exit_intr_ack_set(vcpu)) {
9843 int irq = kvm_cpu_get_interrupt(vcpu);
9844 WARN_ON(irq < 0);
9845 vmcs12->vm_exit_intr_info = irq |
9846 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9847 }
9848
542060ea
JK		 9849 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9850 vmcs12->exit_qualification,
9851 vmcs12->idt_vectoring_info_field,
9852 vmcs12->vm_exit_intr_info,
9853 vmcs12->vm_exit_intr_error_code,
9854 KVM_ISA_VMX);
4704d0be 9855
2961e876
GN		 9856 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9857 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9858 vmx_segment_cache_clear(vmx);
9859
4704d0be
NHE		 9860 /* if no vmcs02 cache requested, remove the one we used */
9861 if (VMCS02_POOL_SIZE == 0)
9862 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9863
9864 load_vmcs12_host_state(vcpu, vmcs12);
9865
27fc51b2 9866 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9867 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9868
9869 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9870 vmx->host_rsp = 0;
9871
9872 /* Unpin physical memory we referred to in vmcs02 */
9873 if (vmx->nested.apic_access_page) {
9874 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9875 vmx->nested.apic_access_page = NULL;
4704d0be 9876 }
a7c0b07d
WL		 9877 if (vmx->nested.virtual_apic_page) {
9878 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9879 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9880 }
4704d0be 9881
38b99173
TC		 9882 /*
9883 * We are now running in L2, mmu_notifier will force to reload the
9884 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9885 */
9886 kvm_vcpu_reload_apic_access_page(vcpu);
9887
4704d0be
NHE		 9888 /*
9889 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9890 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9891 * success or failure flag accordingly.
9892 */
9893 if (unlikely(vmx->fail)) {
9894 vmx->fail = 0;
9895 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9896 } else
9897 nested_vmx_succeed(vcpu);
012f83cb
AG		 9898 if (enable_shadow_vmcs)
9899 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9900
9901 /* in case we halted in L2 */
9902 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9903}
9904
42124925
JK		 9905/*
9906 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9907 */
9908static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9909{
9910 if (is_guest_mode(vcpu))
533558bc 9911 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9912 free_nested(to_vmx(vcpu));
9913}
9914
7c177938
NHE		 9915/*
9916 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9917 * 23.7 "VM-entry failures during or after loading guest state" (this also
9918 * lists the acceptable exit-reason and exit-qualification parameters).
9919 * It should only be called before L2 actually succeeded to run, and when
9920 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9921 */
9922static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9923 struct vmcs12 *vmcs12,
9924 u32 reason, unsigned long qualification)
9925{
9926 load_vmcs12_host_state(vcpu, vmcs12);
9927 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9928 vmcs12->exit_qualification = qualification;
9929 nested_vmx_succeed(vcpu);
012f83cb
AG		 9930 if (enable_shadow_vmcs)
9931 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9932}
9933
8a76d7f2
JR		 9934static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9935 struct x86_instruction_info *info,
9936 enum x86_intercept_stage stage)
9937{
9938 return X86EMUL_CONTINUE;
9939}
9940
48d89b92 9941static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9942{
b4a2d31d
RK		 9943 if (ple_gap)
9944 shrink_ple_window(vcpu);
ae97a3b8
RK		 9945}
9946
843e4330
KH		 9947static void vmx_slot_enable_log_dirty(struct kvm *kvm,
9948 struct kvm_memory_slot *slot)
9949{
9950 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
9951 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
9952}
9953
9954static void vmx_slot_disable_log_dirty(struct kvm *kvm,
9955 struct kvm_memory_slot *slot)
9956{
9957 kvm_mmu_slot_set_dirty(kvm, slot);
9958}
9959
9960static void vmx_flush_log_dirty(struct kvm *kvm)
9961{
9962 kvm_flush_pml_buffers(kvm);
9963}
9964
9965static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
9966 struct kvm_memory_slot *memslot,
9967 gfn_t offset, unsigned long mask)
9968{
9969 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
9970}
9971
cbdd1bea 9972static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9973 .cpu_has_kvm_support = cpu_has_kvm_support,
9974 .disabled_by_bios = vmx_disabled_by_bios,
9975 .hardware_setup = hardware_setup,
9976 .hardware_unsetup = hardware_unsetup,
002c7f7c 9977 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9978 .hardware_enable = hardware_enable,
9979 .hardware_disable = hardware_disable,
04547156 9980 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9981
9982 .vcpu_create = vmx_create_vcpu,
9983 .vcpu_free = vmx_free_vcpu,
04d2cc77 9984 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9985
04d2cc77 9986 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9987 .vcpu_load = vmx_vcpu_load,
9988 .vcpu_put = vmx_vcpu_put,
9989
c8639010 9990 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9991 .get_msr = vmx_get_msr,
9992 .set_msr = vmx_set_msr,
9993 .get_segment_base = vmx_get_segment_base,
9994 .get_segment = vmx_get_segment,
9995 .set_segment = vmx_set_segment,
2e4d2653 9996 .get_cpl = vmx_get_cpl,
6aa8b732 9997 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9998 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9999 .decache_cr3 = vmx_decache_cr3,
25c4c276 10000 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10001 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10002 .set_cr3 = vmx_set_cr3,
10003 .set_cr4 = vmx_set_cr4,
6aa8b732 10004 .set_efer = vmx_set_efer,
6aa8b732
AK		 10005 .get_idt = vmx_get_idt,
10006 .set_idt = vmx_set_idt,
10007 .get_gdt = vmx_get_gdt,
10008 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10009 .get_dr6 = vmx_get_dr6,
10010 .set_dr6 = vmx_set_dr6,
020df079 10011 .set_dr7 = vmx_set_dr7,
81908bf4 10012 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10013 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10014 .get_rflags = vmx_get_rflags,
10015 .set_rflags = vmx_set_rflags,
02daab21 10016 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10017
10018 .tlb_flush = vmx_flush_tlb,
6aa8b732 10019
6aa8b732 10020 .run = vmx_vcpu_run,
6062d012 10021 .handle_exit = vmx_handle_exit,
6aa8b732 10022 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10023 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10024 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10025 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10026 .set_irq = vmx_inject_irq,
95ba8273 10027 .set_nmi = vmx_inject_nmi,
298101da 10028 .queue_exception = vmx_queue_exception,
b463a6f7 10029 .cancel_injection = vmx_cancel_injection,
78646121 10030 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10031 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10032 .get_nmi_mask = vmx_get_nmi_mask,
10033 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10034 .enable_nmi_window = enable_nmi_window,
10035 .enable_irq_window = enable_irq_window,
10036 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10037 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10038 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 10039 .vm_has_apicv = vmx_vm_has_apicv,
10040 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10041 .hwapic_irr_update = vmx_hwapic_irr_update,
10042 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10043 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10044 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10045
cbc94022 10046 .set_tss_addr = vmx_set_tss_addr,
67253af5 10047 .get_tdp_level = get_ept_level,
4b12f0de 10048 .get_mt_mask = vmx_get_mt_mask,
229456fc 10049
586f9607 10050 .get_exit_info = vmx_get_exit_info,
586f9607 10051
17cc3935 10052 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10053
10054 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10055
10056 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10057 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10058
10059 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10060
10061 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10062
4051b188 10063 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10064 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10065 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10066 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10067 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10068 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10069
10070 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10071
10072 .check_intercept = vmx_check_intercept,
a547c6db 10073 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10074 .mpx_supported = vmx_mpx_supported,
55412b2e 10075 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10076
10077 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10078
10079 .sched_in = vmx_sched_in,
843e4330
KH		 10080
10081 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10082 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10083 .flush_log_dirty = vmx_flush_log_dirty,
10084 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 10085};
10086
10087static int __init vmx_init(void)
10088{
34a1cd60
TC		 10089 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10090 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10091 if (r)
34a1cd60 10092 return r;
25c5f225 10093
8f536b76
ZY		 10094#ifdef CONFIG_KEXEC
10095 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10096 crash_vmclear_local_loaded_vmcss);
10097#endif
10098
fdef3ad1 10099 return 0;
6aa8b732
AK		 10100}
10101
10102static void __exit vmx_exit(void)
10103{
8f536b76 10104#ifdef CONFIG_KEXEC
3b63a43f 10105 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10106 synchronize_rcu();
10107#endif
10108
cb498ea2 10109 kvm_exit();
6aa8b732
AK		 10110}
10111
10112module_init(vmx_init)
10113module_exit(vmx_exit)
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