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KVM: x86: fix warning on 32-bit compilation
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 108 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
b4a2d31d
RK		 128#define KVM_VMX_DEFAULT_PLE_GAP 128
129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
131#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
132#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
133 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
134
4b8d54f9
ZE		 135static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
136module_param(ple_gap, int, S_IRUGO);
137
138static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
139module_param(ple_window, int, S_IRUGO);
140
b4a2d31d
RK		 141/* Default doubles per-vcpu window every exit. */
142static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
143module_param(ple_window_grow, int, S_IRUGO);
144
145/* Default resets per-vcpu window every exit to ple_window. */
146static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
147module_param(ple_window_shrink, int, S_IRUGO);
148
149/* Default is to compute the maximum so we can never overflow. */
150static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
151static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
152module_param(ple_window_max, int, S_IRUGO);
153
83287ea4
AK		 154extern const ulong vmx_return;
155
8bf00a52 156#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 157#define VMCS02_POOL_SIZE 1
61d2ef2c 158
a2fa3e9f
GH		 159struct vmcs {
160 u32 revision_id;
161 u32 abort;
162 char data[0];
163};
164
d462b819
NHE		 165/*
166 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
167 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
168 * loaded on this CPU (so we can clear them if the CPU goes down).
169 */
170struct loaded_vmcs {
171 struct vmcs *vmcs;
172 int cpu;
173 int launched;
174 struct list_head loaded_vmcss_on_cpu_link;
175};
176
26bb0981
AK		 177struct shared_msr_entry {
178 unsigned index;
179 u64 data;
d5696725 180 u64 mask;
26bb0981
AK		 181};
182
a9d30f33
NHE		 183/*
184 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
185 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
186 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
187 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
188 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
189 * More than one of these structures may exist, if L1 runs multiple L2 guests.
190 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
191 * underlying hardware which will be used to run L2.
192 * This structure is packed to ensure that its layout is identical across
193 * machines (necessary for live migration).
194 * If there are changes in this struct, VMCS12_REVISION must be changed.
195 */
22bd0358 196typedef u64 natural_width;
a9d30f33
NHE		 197struct __packed vmcs12 {
198 /* According to the Intel spec, a VMCS region must start with the
199 * following two fields. Then follow implementation-specific data.
200 */
201 u32 revision_id;
202 u32 abort;
22bd0358 203
27d6c865
NHE		 204 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
205 u32 padding[7]; /* room for future expansion */
206
22bd0358
NHE		 207 u64 io_bitmap_a;
208 u64 io_bitmap_b;
209 u64 msr_bitmap;
210 u64 vm_exit_msr_store_addr;
211 u64 vm_exit_msr_load_addr;
212 u64 vm_entry_msr_load_addr;
213 u64 tsc_offset;
214 u64 virtual_apic_page_addr;
215 u64 apic_access_addr;
216 u64 ept_pointer;
217 u64 guest_physical_address;
218 u64 vmcs_link_pointer;
219 u64 guest_ia32_debugctl;
220 u64 guest_ia32_pat;
221 u64 guest_ia32_efer;
222 u64 guest_ia32_perf_global_ctrl;
223 u64 guest_pdptr0;
224 u64 guest_pdptr1;
225 u64 guest_pdptr2;
226 u64 guest_pdptr3;
36be0b9d 227 u64 guest_bndcfgs;
22bd0358
NHE		 228 u64 host_ia32_pat;
229 u64 host_ia32_efer;
230 u64 host_ia32_perf_global_ctrl;
231 u64 padding64[8]; /* room for future expansion */
232 /*
233 * To allow migration of L1 (complete with its L2 guests) between
234 * machines of different natural widths (32 or 64 bit), we cannot have
235 * unsigned long fields with no explict size. We use u64 (aliased
236 * natural_width) instead. Luckily, x86 is little-endian.
237 */
238 natural_width cr0_guest_host_mask;
239 natural_width cr4_guest_host_mask;
240 natural_width cr0_read_shadow;
241 natural_width cr4_read_shadow;
242 natural_width cr3_target_value0;
243 natural_width cr3_target_value1;
244 natural_width cr3_target_value2;
245 natural_width cr3_target_value3;
246 natural_width exit_qualification;
247 natural_width guest_linear_address;
248 natural_width guest_cr0;
249 natural_width guest_cr3;
250 natural_width guest_cr4;
251 natural_width guest_es_base;
252 natural_width guest_cs_base;
253 natural_width guest_ss_base;
254 natural_width guest_ds_base;
255 natural_width guest_fs_base;
256 natural_width guest_gs_base;
257 natural_width guest_ldtr_base;
258 natural_width guest_tr_base;
259 natural_width guest_gdtr_base;
260 natural_width guest_idtr_base;
261 natural_width guest_dr7;
262 natural_width guest_rsp;
263 natural_width guest_rip;
264 natural_width guest_rflags;
265 natural_width guest_pending_dbg_exceptions;
266 natural_width guest_sysenter_esp;
267 natural_width guest_sysenter_eip;
268 natural_width host_cr0;
269 natural_width host_cr3;
270 natural_width host_cr4;
271 natural_width host_fs_base;
272 natural_width host_gs_base;
273 natural_width host_tr_base;
274 natural_width host_gdtr_base;
275 natural_width host_idtr_base;
276 natural_width host_ia32_sysenter_esp;
277 natural_width host_ia32_sysenter_eip;
278 natural_width host_rsp;
279 natural_width host_rip;
280 natural_width paddingl[8]; /* room for future expansion */
281 u32 pin_based_vm_exec_control;
282 u32 cpu_based_vm_exec_control;
283 u32 exception_bitmap;
284 u32 page_fault_error_code_mask;
285 u32 page_fault_error_code_match;
286 u32 cr3_target_count;
287 u32 vm_exit_controls;
288 u32 vm_exit_msr_store_count;
289 u32 vm_exit_msr_load_count;
290 u32 vm_entry_controls;
291 u32 vm_entry_msr_load_count;
292 u32 vm_entry_intr_info_field;
293 u32 vm_entry_exception_error_code;
294 u32 vm_entry_instruction_len;
295 u32 tpr_threshold;
296 u32 secondary_vm_exec_control;
297 u32 vm_instruction_error;
298 u32 vm_exit_reason;
299 u32 vm_exit_intr_info;
300 u32 vm_exit_intr_error_code;
301 u32 idt_vectoring_info_field;
302 u32 idt_vectoring_error_code;
303 u32 vm_exit_instruction_len;
304 u32 vmx_instruction_info;
305 u32 guest_es_limit;
306 u32 guest_cs_limit;
307 u32 guest_ss_limit;
308 u32 guest_ds_limit;
309 u32 guest_fs_limit;
310 u32 guest_gs_limit;
311 u32 guest_ldtr_limit;
312 u32 guest_tr_limit;
313 u32 guest_gdtr_limit;
314 u32 guest_idtr_limit;
315 u32 guest_es_ar_bytes;
316 u32 guest_cs_ar_bytes;
317 u32 guest_ss_ar_bytes;
318 u32 guest_ds_ar_bytes;
319 u32 guest_fs_ar_bytes;
320 u32 guest_gs_ar_bytes;
321 u32 guest_ldtr_ar_bytes;
322 u32 guest_tr_ar_bytes;
323 u32 guest_interruptibility_info;
324 u32 guest_activity_state;
325 u32 guest_sysenter_cs;
326 u32 host_ia32_sysenter_cs;
0238ea91
JK		 327 u32 vmx_preemption_timer_value;
328 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 329 u16 virtual_processor_id;
330 u16 guest_es_selector;
331 u16 guest_cs_selector;
332 u16 guest_ss_selector;
333 u16 guest_ds_selector;
334 u16 guest_fs_selector;
335 u16 guest_gs_selector;
336 u16 guest_ldtr_selector;
337 u16 guest_tr_selector;
338 u16 host_es_selector;
339 u16 host_cs_selector;
340 u16 host_ss_selector;
341 u16 host_ds_selector;
342 u16 host_fs_selector;
343 u16 host_gs_selector;
344 u16 host_tr_selector;
a9d30f33
NHE		 345};
346
347/*
348 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
349 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
350 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
351 */
352#define VMCS12_REVISION 0x11e57ed0
353
354/*
355 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
356 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
357 * current implementation, 4K are reserved to avoid future complications.
358 */
359#define VMCS12_SIZE 0x1000
360
ff2f6fe9
NHE		 361/* Used to remember the last vmcs02 used for some recently used vmcs12s */
362struct vmcs02_list {
363 struct list_head list;
364 gpa_t vmptr;
365 struct loaded_vmcs vmcs02;
366};
367
ec378aee
NHE		 368/*
369 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
370 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
371 */
372struct nested_vmx {
373 /* Has the level1 guest done vmxon? */
374 bool vmxon;
3573e22c 375 gpa_t vmxon_ptr;
a9d30f33
NHE		 376
377 /* The guest-physical address of the current VMCS L1 keeps for L2 */
378 gpa_t current_vmptr;
379 /* The host-usable pointer to the above */
380 struct page *current_vmcs12_page;
381 struct vmcs12 *current_vmcs12;
8de48833 382 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 383 /*
384 * Indicates if the shadow vmcs must be updated with the
385 * data hold by vmcs12
386 */
387 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 388
389 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
390 struct list_head vmcs02_pool;
391 int vmcs02_num;
fe3ef05c 392 u64 vmcs01_tsc_offset;
644d711a
NHE		 393 /* L2 must run next, and mustn't decide to exit to L1. */
394 bool nested_run_pending;
fe3ef05c
NHE		 395 /*
396 * Guest pages referred to in vmcs02 with host-physical pointers, so
397 * we must keep them pinned while L2 runs.
398 */
399 struct page *apic_access_page;
a7c0b07d 400 struct page *virtual_apic_page;
b3897a49 401 u64 msr_ia32_feature_control;
f4124500
JK		 402
403 struct hrtimer preemption_timer;
404 bool preemption_timer_expired;
2996fca0
JK		 405
406 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
407 u64 vmcs01_debugctl;
ec378aee
NHE		 408};
409
01e439be
YZ		 410#define POSTED_INTR_ON 0
411/* Posted-Interrupt Descriptor */
412struct pi_desc {
413 u32 pir[8]; /* Posted interrupt requested */
414 u32 control; /* bit 0 of control is outstanding notification bit */
415 u32 rsvd[7];
416} __aligned(64);
417
a20ed54d
YZ		 418static bool pi_test_and_set_on(struct pi_desc *pi_desc)
419{
420 return test_and_set_bit(POSTED_INTR_ON,
421 (unsigned long *)&pi_desc->control);
422}
423
424static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
425{
426 return test_and_clear_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
431{
432 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
433}
434
a2fa3e9f 435struct vcpu_vmx {
fb3f0f51 436 struct kvm_vcpu vcpu;
313dbd49 437 unsigned long host_rsp;
29bd8a78 438 u8 fail;
9d58b931 439 bool nmi_known_unmasked;
51aa01d1 440 u32 exit_intr_info;
1155f76a 441 u32 idt_vectoring_info;
6de12732 442 ulong rflags;
26bb0981 443 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 444 int nmsrs;
445 int save_nmsrs;
a547c6db 446 unsigned long host_idt_base;
a2fa3e9f 447#ifdef CONFIG_X86_64
44ea2b17
AK		 448 u64 msr_host_kernel_gs_base;
449 u64 msr_guest_kernel_gs_base;
a2fa3e9f 450#endif
2961e876
GN		 451 u32 vm_entry_controls_shadow;
452 u32 vm_exit_controls_shadow;
d462b819
NHE		 453 /*
454 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
455 * non-nested (L1) guest, it always points to vmcs01. For a nested
456 * guest (L2), it points to a different VMCS.
457 */
458 struct loaded_vmcs vmcs01;
459 struct loaded_vmcs *loaded_vmcs;
460 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 461 struct msr_autoload {
462 unsigned nr;
463 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
464 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
465 } msr_autoload;
a2fa3e9f
GH		 466 struct {
467 int loaded;
468 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 469#ifdef CONFIG_X86_64
470 u16 ds_sel, es_sel;
471#endif
152d3f2f
LV		 472 int gs_ldt_reload_needed;
473 int fs_reload_needed;
da8999d3 474 u64 msr_host_bndcfgs;
d974baa3 475 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 476 } host_state;
9c8cba37 477 struct {
7ffd92c5 478 int vm86_active;
78ac8b47 479 ulong save_rflags;
f5f7b2fe
AK		 480 struct kvm_segment segs[8];
481 } rmode;
482 struct {
483 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 484 struct kvm_save_segment {
485 u16 selector;
486 unsigned long base;
487 u32 limit;
488 u32 ar;
f5f7b2fe 489 } seg[8];
2fb92db1 490 } segment_cache;
2384d2b3 491 int vpid;
04fa4d32 492 bool emulation_required;
3b86cd99
JK		 493
494 /* Support for vnmi-less CPUs */
495 int soft_vnmi_blocked;
496 ktime_t entry_time;
497 s64 vnmi_blocked_time;
a0861c02 498 u32 exit_reason;
4e47c7a6
SY		 499
500 bool rdtscp_enabled;
ec378aee 501
01e439be
YZ		 502 /* Posted interrupt descriptor */
503 struct pi_desc pi_desc;
504
ec378aee
NHE		 505 /* Support for a guest hypervisor (nested VMX) */
506 struct nested_vmx nested;
a7653ecd
RK		 507
508 /* Dynamic PLE window. */
509 int ple_window;
510 bool ple_window_dirty;
a2fa3e9f
GH		 511};
512
2fb92db1
AK		 513enum segment_cache_field {
514 SEG_FIELD_SEL = 0,
515 SEG_FIELD_BASE = 1,
516 SEG_FIELD_LIMIT = 2,
517 SEG_FIELD_AR = 3,
518
519 SEG_FIELD_NR = 4
520};
521
a2fa3e9f
GH		 522static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
523{
fb3f0f51 524 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 525}
526
22bd0358
NHE		 527#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
528#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
529#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
530 [number##_HIGH] = VMCS12_OFFSET(name)+4
531
4607c2d7 532
fe2b201b 533static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 534 /*
535 * We do NOT shadow fields that are modified when L0
536 * traps and emulates any vmx instruction (e.g. VMPTRLD,
537 * VMXON...) executed by L1.
538 * For example, VM_INSTRUCTION_ERROR is read
539 * by L1 if a vmx instruction fails (part of the error path).
540 * Note the code assumes this logic. If for some reason
541 * we start shadowing these fields then we need to
542 * force a shadow sync when L0 emulates vmx instructions
543 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
544 * by nested_vmx_failValid)
545 */
546 VM_EXIT_REASON,
547 VM_EXIT_INTR_INFO,
548 VM_EXIT_INSTRUCTION_LEN,
549 IDT_VECTORING_INFO_FIELD,
550 IDT_VECTORING_ERROR_CODE,
551 VM_EXIT_INTR_ERROR_CODE,
552 EXIT_QUALIFICATION,
553 GUEST_LINEAR_ADDRESS,
554 GUEST_PHYSICAL_ADDRESS
555};
fe2b201b 556static int max_shadow_read_only_fields =
4607c2d7
AG		 557 ARRAY_SIZE(shadow_read_only_fields);
558
fe2b201b 559static unsigned long shadow_read_write_fields[] = {
a7c0b07d 560 TPR_THRESHOLD,
4607c2d7
AG		 561 GUEST_RIP,
562 GUEST_RSP,
563 GUEST_CR0,
564 GUEST_CR3,
565 GUEST_CR4,
566 GUEST_INTERRUPTIBILITY_INFO,
567 GUEST_RFLAGS,
568 GUEST_CS_SELECTOR,
569 GUEST_CS_AR_BYTES,
570 GUEST_CS_LIMIT,
571 GUEST_CS_BASE,
572 GUEST_ES_BASE,
36be0b9d 573 GUEST_BNDCFGS,
4607c2d7
AG		 574 CR0_GUEST_HOST_MASK,
575 CR0_READ_SHADOW,
576 CR4_READ_SHADOW,
577 TSC_OFFSET,
578 EXCEPTION_BITMAP,
579 CPU_BASED_VM_EXEC_CONTROL,
580 VM_ENTRY_EXCEPTION_ERROR_CODE,
581 VM_ENTRY_INTR_INFO_FIELD,
582 VM_ENTRY_INSTRUCTION_LEN,
583 VM_ENTRY_EXCEPTION_ERROR_CODE,
584 HOST_FS_BASE,
585 HOST_GS_BASE,
586 HOST_FS_SELECTOR,
587 HOST_GS_SELECTOR
588};
fe2b201b 589static int max_shadow_read_write_fields =
4607c2d7
AG		 590 ARRAY_SIZE(shadow_read_write_fields);
591
772e0318 592static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 593 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
594 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
595 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
596 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
597 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
598 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
599 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
600 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
601 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
602 FIELD(HOST_ES_SELECTOR, host_es_selector),
603 FIELD(HOST_CS_SELECTOR, host_cs_selector),
604 FIELD(HOST_SS_SELECTOR, host_ss_selector),
605 FIELD(HOST_DS_SELECTOR, host_ds_selector),
606 FIELD(HOST_FS_SELECTOR, host_fs_selector),
607 FIELD(HOST_GS_SELECTOR, host_gs_selector),
608 FIELD(HOST_TR_SELECTOR, host_tr_selector),
609 FIELD64(IO_BITMAP_A, io_bitmap_a),
610 FIELD64(IO_BITMAP_B, io_bitmap_b),
611 FIELD64(MSR_BITMAP, msr_bitmap),
612 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
613 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
614 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
615 FIELD64(TSC_OFFSET, tsc_offset),
616 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
617 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
618 FIELD64(EPT_POINTER, ept_pointer),
619 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
620 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
621 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
622 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
623 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
624 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
625 FIELD64(GUEST_PDPTR0, guest_pdptr0),
626 FIELD64(GUEST_PDPTR1, guest_pdptr1),
627 FIELD64(GUEST_PDPTR2, guest_pdptr2),
628 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 629 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 630 FIELD64(HOST_IA32_PAT, host_ia32_pat),
631 FIELD64(HOST_IA32_EFER, host_ia32_efer),
632 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
633 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
634 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
635 FIELD(EXCEPTION_BITMAP, exception_bitmap),
636 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
637 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
638 FIELD(CR3_TARGET_COUNT, cr3_target_count),
639 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
640 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
641 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
642 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
643 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
644 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
645 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
646 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
647 FIELD(TPR_THRESHOLD, tpr_threshold),
648 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
649 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
650 FIELD(VM_EXIT_REASON, vm_exit_reason),
651 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
652 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
653 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
654 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
655 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
656 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
657 FIELD(GUEST_ES_LIMIT, guest_es_limit),
658 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
659 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
660 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
661 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
662 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
663 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
664 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
665 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
666 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
667 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
668 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
669 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
670 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
671 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
672 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
673 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
674 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
675 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
676 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
677 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
678 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 679 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 680 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
681 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
682 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
683 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
684 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
685 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
686 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
687 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
688 FIELD(EXIT_QUALIFICATION, exit_qualification),
689 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
690 FIELD(GUEST_CR0, guest_cr0),
691 FIELD(GUEST_CR3, guest_cr3),
692 FIELD(GUEST_CR4, guest_cr4),
693 FIELD(GUEST_ES_BASE, guest_es_base),
694 FIELD(GUEST_CS_BASE, guest_cs_base),
695 FIELD(GUEST_SS_BASE, guest_ss_base),
696 FIELD(GUEST_DS_BASE, guest_ds_base),
697 FIELD(GUEST_FS_BASE, guest_fs_base),
698 FIELD(GUEST_GS_BASE, guest_gs_base),
699 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
700 FIELD(GUEST_TR_BASE, guest_tr_base),
701 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
702 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
703 FIELD(GUEST_DR7, guest_dr7),
704 FIELD(GUEST_RSP, guest_rsp),
705 FIELD(GUEST_RIP, guest_rip),
706 FIELD(GUEST_RFLAGS, guest_rflags),
707 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
708 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
709 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
710 FIELD(HOST_CR0, host_cr0),
711 FIELD(HOST_CR3, host_cr3),
712 FIELD(HOST_CR4, host_cr4),
713 FIELD(HOST_FS_BASE, host_fs_base),
714 FIELD(HOST_GS_BASE, host_gs_base),
715 FIELD(HOST_TR_BASE, host_tr_base),
716 FIELD(HOST_GDTR_BASE, host_gdtr_base),
717 FIELD(HOST_IDTR_BASE, host_idtr_base),
718 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
719 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
720 FIELD(HOST_RSP, host_rsp),
721 FIELD(HOST_RIP, host_rip),
722};
22bd0358
NHE		 723
724static inline short vmcs_field_to_offset(unsigned long field)
725{
a2ae9df7
PB		 726 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
727
728 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
729 vmcs_field_to_offset_table[field] == 0)
730 return -ENOENT;
731
22bd0358
NHE		 732 return vmcs_field_to_offset_table[field];
733}
734
a9d30f33
NHE		 735static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
736{
737 return to_vmx(vcpu)->nested.current_vmcs12;
738}
739
740static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
741{
742 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 743 if (is_error_page(page))
a9d30f33 744 return NULL;
32cad84f 745
a9d30f33
NHE		 746 return page;
747}
748
749static void nested_release_page(struct page *page)
750{
751 kvm_release_page_dirty(page);
752}
753
754static void nested_release_page_clean(struct page *page)
755{
756 kvm_release_page_clean(page);
757}
758
bfd0a56b 759static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 760static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 761static void kvm_cpu_vmxon(u64 addr);
762static void kvm_cpu_vmxoff(void);
93c4adc7 763static bool vmx_mpx_supported(void);
776e58ea 764static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 765static void vmx_set_segment(struct kvm_vcpu *vcpu,
766 struct kvm_segment *var, int seg);
767static void vmx_get_segment(struct kvm_vcpu *vcpu,
768 struct kvm_segment *var, int seg);
d99e4152
GN		 769static bool guest_state_valid(struct kvm_vcpu *vcpu);
770static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 771static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 772static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 773static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 774static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 775
6aa8b732
AK		 776static DEFINE_PER_CPU(struct vmcs *, vmxarea);
777static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 778/*
779 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
780 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
781 */
782static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 783static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 784
3e7c73e9
AK		 785static unsigned long *vmx_io_bitmap_a;
786static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 787static unsigned long *vmx_msr_bitmap_legacy;
788static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 789static unsigned long *vmx_msr_bitmap_legacy_x2apic;
790static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 791static unsigned long *vmx_vmread_bitmap;
792static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 793
110312c8 794static bool cpu_has_load_ia32_efer;
8bf00a52 795static bool cpu_has_load_perf_global_ctrl;
110312c8 796
2384d2b3
SY		 797static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
798static DEFINE_SPINLOCK(vmx_vpid_lock);
799
1c3d14fe 800static struct vmcs_config {
6aa8b732
AK		 801 int size;
802 int order;
803 u32 revision_id;
1c3d14fe
YS		 804 u32 pin_based_exec_ctrl;
805 u32 cpu_based_exec_ctrl;
f78e0e2e 806 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 807 u32 vmexit_ctrl;
808 u32 vmentry_ctrl;
809} vmcs_config;
6aa8b732 810
efff9e53 811static struct vmx_capability {
d56f546d
SY		 812 u32 ept;
813 u32 vpid;
814} vmx_capability;
815
6aa8b732
AK		 816#define VMX_SEGMENT_FIELD(seg) \
817 [VCPU_SREG_##seg] = { \
818 .selector = GUEST_##seg##_SELECTOR, \
819 .base = GUEST_##seg##_BASE, \
820 .limit = GUEST_##seg##_LIMIT, \
821 .ar_bytes = GUEST_##seg##_AR_BYTES, \
822 }
823
772e0318 824static const struct kvm_vmx_segment_field {
6aa8b732
AK		 825 unsigned selector;
826 unsigned base;
827 unsigned limit;
828 unsigned ar_bytes;
829} kvm_vmx_segment_fields[] = {
830 VMX_SEGMENT_FIELD(CS),
831 VMX_SEGMENT_FIELD(DS),
832 VMX_SEGMENT_FIELD(ES),
833 VMX_SEGMENT_FIELD(FS),
834 VMX_SEGMENT_FIELD(GS),
835 VMX_SEGMENT_FIELD(SS),
836 VMX_SEGMENT_FIELD(TR),
837 VMX_SEGMENT_FIELD(LDTR),
838};
839
26bb0981
AK		 840static u64 host_efer;
841
6de4f3ad
AK		 842static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
843
4d56c8a7 844/*
8c06585d 845 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 846 * away by decrementing the array size.
847 */
6aa8b732 848static const u32 vmx_msr_index[] = {
05b3e0c2 849#ifdef CONFIG_X86_64
44ea2b17 850 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 851#endif
8c06585d 852 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 853};
6aa8b732 854
31299944 855static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 856{
857 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
858 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 859 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 860}
861
31299944 862static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 863{
864 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
865 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 866 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 867}
868
31299944 869static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 870{
871 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
872 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 873 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 874}
875
31299944 876static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 877{
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
880}
881
31299944 882static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 883{
884 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
885 INTR_INFO_VALID_MASK)) ==
886 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
887}
888
31299944 889static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 890{
04547156 891 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 892}
893
31299944 894static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 895{
04547156 896 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 897}
898
31299944 899static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 900{
04547156 901 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 902}
903
31299944 904static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 905{
04547156
SY		 906 return vmcs_config.cpu_based_exec_ctrl &
907 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 908}
909
774ead3a 910static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 911{
04547156
SY		 912 return vmcs_config.cpu_based_2nd_exec_ctrl &
913 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
914}
915
8d14695f
YZ		 916static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
917{
918 return vmcs_config.cpu_based_2nd_exec_ctrl &
919 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
920}
921
83d4c286
YZ		 922static inline bool cpu_has_vmx_apic_register_virt(void)
923{
924 return vmcs_config.cpu_based_2nd_exec_ctrl &
925 SECONDARY_EXEC_APIC_REGISTER_VIRT;
926}
927
c7c9c56c
YZ		 928static inline bool cpu_has_vmx_virtual_intr_delivery(void)
929{
930 return vmcs_config.cpu_based_2nd_exec_ctrl &
931 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
932}
933
01e439be
YZ		 934static inline bool cpu_has_vmx_posted_intr(void)
935{
936 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
937}
938
939static inline bool cpu_has_vmx_apicv(void)
940{
941 return cpu_has_vmx_apic_register_virt() &&
942 cpu_has_vmx_virtual_intr_delivery() &&
943 cpu_has_vmx_posted_intr();
944}
945
04547156
SY		 946static inline bool cpu_has_vmx_flexpriority(void)
947{
948 return cpu_has_vmx_tpr_shadow() &&
949 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 950}
951
e799794e
MT		 952static inline bool cpu_has_vmx_ept_execute_only(void)
953{
31299944 954 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 955}
956
957static inline bool cpu_has_vmx_eptp_uncacheable(void)
958{
31299944 959 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 960}
961
962static inline bool cpu_has_vmx_eptp_writeback(void)
963{
31299944 964 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 965}
966
967static inline bool cpu_has_vmx_ept_2m_page(void)
968{
31299944 969 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 970}
971
878403b7
SY		 972static inline bool cpu_has_vmx_ept_1g_page(void)
973{
31299944 974 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 975}
976
4bc9b982
SY		 977static inline bool cpu_has_vmx_ept_4levels(void)
978{
979 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
980}
981
83c3a331
XH		 982static inline bool cpu_has_vmx_ept_ad_bits(void)
983{
984 return vmx_capability.ept & VMX_EPT_AD_BIT;
985}
986
31299944 987static inline bool cpu_has_vmx_invept_context(void)
d56f546d 988{
31299944 989 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 990}
991
31299944 992static inline bool cpu_has_vmx_invept_global(void)
d56f546d 993{
31299944 994 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 995}
996
518c8aee
GJ		 997static inline bool cpu_has_vmx_invvpid_single(void)
998{
999 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1000}
1001
b9d762fa
GJ		 1002static inline bool cpu_has_vmx_invvpid_global(void)
1003{
1004 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1005}
1006
31299944 1007static inline bool cpu_has_vmx_ept(void)
d56f546d 1008{
04547156
SY		 1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1011}
1012
31299944 1013static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1014{
1015 return vmcs_config.cpu_based_2nd_exec_ctrl &
1016 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1017}
1018
31299944 1019static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1020{
1021 return vmcs_config.cpu_based_2nd_exec_ctrl &
1022 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1023}
1024
31299944 1025static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1026{
6d3e435e 1027 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1028}
1029
31299944 1030static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1031{
04547156
SY		 1032 return vmcs_config.cpu_based_2nd_exec_ctrl &
1033 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1034}
1035
31299944 1036static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1037{
1038 return vmcs_config.cpu_based_2nd_exec_ctrl &
1039 SECONDARY_EXEC_RDTSCP;
1040}
1041
ad756a16
MJ		 1042static inline bool cpu_has_vmx_invpcid(void)
1043{
1044 return vmcs_config.cpu_based_2nd_exec_ctrl &
1045 SECONDARY_EXEC_ENABLE_INVPCID;
1046}
1047
31299944 1048static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1049{
1050 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1051}
1052
f5f48ee1
SY		 1053static inline bool cpu_has_vmx_wbinvd_exit(void)
1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_WBINVD_EXITING;
1057}
1058
abc4fc58
AG		 1059static inline bool cpu_has_vmx_shadow_vmcs(void)
1060{
1061 u64 vmx_msr;
1062 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1063 /* check if the cpu supports writing r/o exit information fields */
1064 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1065 return false;
1066
1067 return vmcs_config.cpu_based_2nd_exec_ctrl &
1068 SECONDARY_EXEC_SHADOW_VMCS;
1069}
1070
04547156
SY		 1071static inline bool report_flexpriority(void)
1072{
1073 return flexpriority_enabled;
1074}
1075
fe3ef05c
NHE		 1076static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1077{
1078 return vmcs12->cpu_based_vm_exec_control & bit;
1079}
1080
1081static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1082{
1083 return (vmcs12->cpu_based_vm_exec_control &
1084 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1085 (vmcs12->secondary_vm_exec_control & bit);
1086}
1087
f5c4368f 1088static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1089{
1090 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f4124500
JK		 1093static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1094{
1095 return vmcs12->pin_based_vm_exec_control &
1096 PIN_BASED_VMX_PREEMPTION_TIMER;
1097}
1098
155a97a3
NHE		 1099static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1100{
1101 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1102}
1103
644d711a
NHE		 1104static inline bool is_exception(u32 intr_info)
1105{
1106 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1107 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1108}
1109
533558bc
JK		 1110static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1111 u32 exit_intr_info,
1112 unsigned long exit_qualification);
7c177938
NHE		 1113static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1114 struct vmcs12 *vmcs12,
1115 u32 reason, unsigned long qualification);
1116
8b9cf98c 1117static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1118{
1119 int i;
1120
a2fa3e9f 1121 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1122 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1123 return i;
1124 return -1;
1125}
1126
2384d2b3
SY		 1127static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1128{
1129 struct {
1130 u64 vpid : 16;
1131 u64 rsvd : 48;
1132 u64 gva;
1133 } operand = { vpid, 0, gva };
1134
4ecac3fd 1135 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1136 /* CF==1 or ZF==1 --> rc = -1 */
1137 "; ja 1f ; ud2 ; 1:"
1138 : : "a"(&operand), "c"(ext) : "cc", "memory");
1139}
1140
1439442c
SY		 1141static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1142{
1143 struct {
1144 u64 eptp, gpa;
1145 } operand = {eptp, gpa};
1146
4ecac3fd 1147 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1148 /* CF==1 or ZF==1 --> rc = -1 */
1149 "; ja 1f ; ud2 ; 1:\n"
1150 : : "a" (&operand), "c" (ext) : "cc", "memory");
1151}
1152
26bb0981 1153static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1154{
1155 int i;
1156
8b9cf98c 1157 i = __find_msr_index(vmx, msr);
a75beee6 1158 if (i >= 0)
a2fa3e9f 1159 return &vmx->guest_msrs[i];
8b6d44c7 1160 return NULL;
7725f0ba
AK		 1161}
1162
6aa8b732
AK		 1163static void vmcs_clear(struct vmcs *vmcs)
1164{
1165 u64 phys_addr = __pa(vmcs);
1166 u8 error;
1167
4ecac3fd 1168 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1169 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1170 : "cc", "memory");
1171 if (error)
1172 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1173 vmcs, phys_addr);
1174}
1175
d462b819
NHE		 1176static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1177{
1178 vmcs_clear(loaded_vmcs->vmcs);
1179 loaded_vmcs->cpu = -1;
1180 loaded_vmcs->launched = 0;
1181}
1182
7725b894
DX		 1183static void vmcs_load(struct vmcs *vmcs)
1184{
1185 u64 phys_addr = __pa(vmcs);
1186 u8 error;
1187
1188 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1189 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1190 : "cc", "memory");
1191 if (error)
2844d849 1192 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1193 vmcs, phys_addr);
1194}
1195
8f536b76
ZY		 1196#ifdef CONFIG_KEXEC
1197/*
1198 * This bitmap is used to indicate whether the vmclear
1199 * operation is enabled on all cpus. All disabled by
1200 * default.
1201 */
1202static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1203
1204static inline void crash_enable_local_vmclear(int cpu)
1205{
1206 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1207}
1208
1209static inline void crash_disable_local_vmclear(int cpu)
1210{
1211 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1212}
1213
1214static inline int crash_local_vmclear_enabled(int cpu)
1215{
1216 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1217}
1218
1219static void crash_vmclear_local_loaded_vmcss(void)
1220{
1221 int cpu = raw_smp_processor_id();
1222 struct loaded_vmcs *v;
1223
1224 if (!crash_local_vmclear_enabled(cpu))
1225 return;
1226
1227 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1228 loaded_vmcss_on_cpu_link)
1229 vmcs_clear(v->vmcs);
1230}
1231#else
1232static inline void crash_enable_local_vmclear(int cpu) { }
1233static inline void crash_disable_local_vmclear(int cpu) { }
1234#endif /* CONFIG_KEXEC */
1235
d462b819 1236static void __loaded_vmcs_clear(void *arg)
6aa8b732 1237{
d462b819 1238 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1239 int cpu = raw_smp_processor_id();
6aa8b732 1240
d462b819
NHE		 1241 if (loaded_vmcs->cpu != cpu)
1242 return; /* vcpu migration can race with cpu offline */
1243 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1244 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1245 crash_disable_local_vmclear(cpu);
d462b819 1246 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1247
1248 /*
1249 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1250 * is before setting loaded_vmcs->vcpu to -1 which is done in
1251 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1252 * then adds the vmcs into percpu list before it is deleted.
1253 */
1254 smp_wmb();
1255
d462b819 1256 loaded_vmcs_init(loaded_vmcs);
8f536b76 1257 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1258}
1259
d462b819 1260static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1261{
e6c7d321
XG		 1262 int cpu = loaded_vmcs->cpu;
1263
1264 if (cpu != -1)
1265 smp_call_function_single(cpu,
1266 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1267}
1268
1760dd49 1269static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1270{
1271 if (vmx->vpid == 0)
1272 return;
1273
518c8aee
GJ		 1274 if (cpu_has_vmx_invvpid_single())
1275 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1276}
1277
b9d762fa
GJ		 1278static inline void vpid_sync_vcpu_global(void)
1279{
1280 if (cpu_has_vmx_invvpid_global())
1281 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1282}
1283
1284static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1285{
1286 if (cpu_has_vmx_invvpid_single())
1760dd49 1287 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1288 else
1289 vpid_sync_vcpu_global();
1290}
1291
1439442c
SY		 1292static inline void ept_sync_global(void)
1293{
1294 if (cpu_has_vmx_invept_global())
1295 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1296}
1297
1298static inline void ept_sync_context(u64 eptp)
1299{
089d034e 1300 if (enable_ept) {
1439442c
SY		 1301 if (cpu_has_vmx_invept_context())
1302 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1303 else
1304 ept_sync_global();
1305 }
1306}
1307
96304217 1308static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1309{
5e520e62 1310 unsigned long value;
6aa8b732 1311
5e520e62
AK		 1312 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1313 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1314 return value;
1315}
1316
96304217 1317static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1318{
1319 return vmcs_readl(field);
1320}
1321
96304217 1322static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1323{
1324 return vmcs_readl(field);
1325}
1326
96304217 1327static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1328{
05b3e0c2 1329#ifdef CONFIG_X86_64
6aa8b732
AK		 1330 return vmcs_readl(field);
1331#else
1332 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1333#endif
1334}
1335
e52de1b8
AK		 1336static noinline void vmwrite_error(unsigned long field, unsigned long value)
1337{
1338 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1339 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1340 dump_stack();
1341}
1342
6aa8b732
AK		 1343static void vmcs_writel(unsigned long field, unsigned long value)
1344{
1345 u8 error;
1346
4ecac3fd 1347 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1348 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1349 if (unlikely(error))
1350 vmwrite_error(field, value);
6aa8b732
AK		 1351}
1352
1353static void vmcs_write16(unsigned long field, u16 value)
1354{
1355 vmcs_writel(field, value);
1356}
1357
1358static void vmcs_write32(unsigned long field, u32 value)
1359{
1360 vmcs_writel(field, value);
1361}
1362
1363static void vmcs_write64(unsigned long field, u64 value)
1364{
6aa8b732 1365 vmcs_writel(field, value);
7682f2d0 1366#ifndef CONFIG_X86_64
6aa8b732
AK		 1367 asm volatile ("");
1368 vmcs_writel(field+1, value >> 32);
1369#endif
1370}
1371
2ab455cc
AL		 1372static void vmcs_clear_bits(unsigned long field, u32 mask)
1373{
1374 vmcs_writel(field, vmcs_readl(field) & ~mask);
1375}
1376
1377static void vmcs_set_bits(unsigned long field, u32 mask)
1378{
1379 vmcs_writel(field, vmcs_readl(field) | mask);
1380}
1381
2961e876
GN		 1382static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1383{
1384 vmcs_write32(VM_ENTRY_CONTROLS, val);
1385 vmx->vm_entry_controls_shadow = val;
1386}
1387
1388static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1389{
1390 if (vmx->vm_entry_controls_shadow != val)
1391 vm_entry_controls_init(vmx, val);
1392}
1393
1394static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1395{
1396 return vmx->vm_entry_controls_shadow;
1397}
1398
1399
1400static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1401{
1402 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1403}
1404
1405static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1406{
1407 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1408}
1409
1410static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1411{
1412 vmcs_write32(VM_EXIT_CONTROLS, val);
1413 vmx->vm_exit_controls_shadow = val;
1414}
1415
1416static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1417{
1418 if (vmx->vm_exit_controls_shadow != val)
1419 vm_exit_controls_init(vmx, val);
1420}
1421
1422static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1423{
1424 return vmx->vm_exit_controls_shadow;
1425}
1426
1427
1428static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1429{
1430 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1431}
1432
1433static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1434{
1435 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1436}
1437
2fb92db1
AK		 1438static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1439{
1440 vmx->segment_cache.bitmask = 0;
1441}
1442
1443static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1444 unsigned field)
1445{
1446 bool ret;
1447 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1448
1449 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1450 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1451 vmx->segment_cache.bitmask = 0;
1452 }
1453 ret = vmx->segment_cache.bitmask & mask;
1454 vmx->segment_cache.bitmask |= mask;
1455 return ret;
1456}
1457
1458static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1459{
1460 u16 *p = &vmx->segment_cache.seg[seg].selector;
1461
1462 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1463 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1464 return *p;
1465}
1466
1467static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1468{
1469 ulong *p = &vmx->segment_cache.seg[seg].base;
1470
1471 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1472 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1473 return *p;
1474}
1475
1476static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1477{
1478 u32 *p = &vmx->segment_cache.seg[seg].limit;
1479
1480 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1481 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1482 return *p;
1483}
1484
1485static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1486{
1487 u32 *p = &vmx->segment_cache.seg[seg].ar;
1488
1489 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1490 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1491 return *p;
1492}
1493
abd3f2d6
AK		 1494static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1495{
1496 u32 eb;
1497
fd7373cc
JK		 1498 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1499 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1500 if ((vcpu->guest_debug &
1501 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1502 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1503 eb |= 1u << BP_VECTOR;
7ffd92c5 1504 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1505 eb = ~0;
089d034e 1506 if (enable_ept)
1439442c 1507 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1508 if (vcpu->fpu_active)
1509 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1510
1511 /* When we are running a nested L2 guest and L1 specified for it a
1512 * certain exception bitmap, we must trap the same exceptions and pass
1513 * them to L1. When running L2, we will only handle the exceptions
1514 * specified above if L1 did not want them.
1515 */
1516 if (is_guest_mode(vcpu))
1517 eb |= get_vmcs12(vcpu)->exception_bitmap;
1518
abd3f2d6
AK		 1519 vmcs_write32(EXCEPTION_BITMAP, eb);
1520}
1521
2961e876
GN		 1522static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1523 unsigned long entry, unsigned long exit)
8bf00a52 1524{
2961e876
GN		 1525 vm_entry_controls_clearbit(vmx, entry);
1526 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1527}
1528
61d2ef2c
AK		 1529static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1530{
1531 unsigned i;
1532 struct msr_autoload *m = &vmx->msr_autoload;
1533
8bf00a52
GN		 1534 switch (msr) {
1535 case MSR_EFER:
1536 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1537 clear_atomic_switch_msr_special(vmx,
1538 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1539 VM_EXIT_LOAD_IA32_EFER);
1540 return;
1541 }
1542 break;
1543 case MSR_CORE_PERF_GLOBAL_CTRL:
1544 if (cpu_has_load_perf_global_ctrl) {
2961e876 1545 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1546 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1547 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1548 return;
1549 }
1550 break;
110312c8
AK		 1551 }
1552
61d2ef2c
AK		 1553 for (i = 0; i < m->nr; ++i)
1554 if (m->guest[i].index == msr)
1555 break;
1556
1557 if (i == m->nr)
1558 return;
1559 --m->nr;
1560 m->guest[i] = m->guest[m->nr];
1561 m->host[i] = m->host[m->nr];
1562 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1563 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1564}
1565
2961e876
GN		 1566static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1567 unsigned long entry, unsigned long exit,
1568 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1569 u64 guest_val, u64 host_val)
8bf00a52
GN		 1570{
1571 vmcs_write64(guest_val_vmcs, guest_val);
1572 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1573 vm_entry_controls_setbit(vmx, entry);
1574 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1575}
1576
61d2ef2c
AK		 1577static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1578 u64 guest_val, u64 host_val)
1579{
1580 unsigned i;
1581 struct msr_autoload *m = &vmx->msr_autoload;
1582
8bf00a52
GN		 1583 switch (msr) {
1584 case MSR_EFER:
1585 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1586 add_atomic_switch_msr_special(vmx,
1587 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1588 VM_EXIT_LOAD_IA32_EFER,
1589 GUEST_IA32_EFER,
1590 HOST_IA32_EFER,
1591 guest_val, host_val);
1592 return;
1593 }
1594 break;
1595 case MSR_CORE_PERF_GLOBAL_CTRL:
1596 if (cpu_has_load_perf_global_ctrl) {
2961e876 1597 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1598 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1599 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1600 GUEST_IA32_PERF_GLOBAL_CTRL,
1601 HOST_IA32_PERF_GLOBAL_CTRL,
1602 guest_val, host_val);
1603 return;
1604 }
1605 break;
110312c8
AK		 1606 }
1607
61d2ef2c
AK		 1608 for (i = 0; i < m->nr; ++i)
1609 if (m->guest[i].index == msr)
1610 break;
1611
e7fc6f93 1612 if (i == NR_AUTOLOAD_MSRS) {
60266204 1613 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1614 "Can't add msr %x\n", msr);
1615 return;
1616 } else if (i == m->nr) {
61d2ef2c
AK		 1617 ++m->nr;
1618 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1619 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1620 }
1621
1622 m->guest[i].index = msr;
1623 m->guest[i].value = guest_val;
1624 m->host[i].index = msr;
1625 m->host[i].value = host_val;
1626}
1627
33ed6329
AK		 1628static void reload_tss(void)
1629{
33ed6329
AK		 1630 /*
1631 * VT restores TR but not its size. Useless.
1632 */
89cbc767 1633 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1634 struct desc_struct *descs;
33ed6329 1635
d359192f 1636 descs = (void *)gdt->address;
33ed6329
AK		 1637 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1638 load_TR_desc();
33ed6329
AK		 1639}
1640
92c0d900 1641static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1642{
3a34a881 1643 u64 guest_efer;
51c6cf66
AK		 1644 u64 ignore_bits;
1645
f6801dff 1646 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1647
51c6cf66 1648 /*
0fa06071 1649 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1650 * outside long mode
1651 */
1652 ignore_bits = EFER_NX | EFER_SCE;
1653#ifdef CONFIG_X86_64
1654 ignore_bits |= EFER_LMA | EFER_LME;
1655 /* SCE is meaningful only in long mode on Intel */
1656 if (guest_efer & EFER_LMA)
1657 ignore_bits &= ~(u64)EFER_SCE;
1658#endif
51c6cf66
AK		 1659 guest_efer &= ~ignore_bits;
1660 guest_efer |= host_efer & ignore_bits;
26bb0981 1661 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1662 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1663
1664 clear_atomic_switch_msr(vmx, MSR_EFER);
1665 /* On ept, can't emulate nx, and must switch nx atomically */
1666 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1667 guest_efer = vmx->vcpu.arch.efer;
1668 if (!(guest_efer & EFER_LMA))
1669 guest_efer &= ~EFER_LME;
1670 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1671 return false;
1672 }
1673
26bb0981 1674 return true;
51c6cf66
AK		 1675}
1676
2d49ec72
GN		 1677static unsigned long segment_base(u16 selector)
1678{
89cbc767 1679 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1680 struct desc_struct *d;
1681 unsigned long table_base;
1682 unsigned long v;
1683
1684 if (!(selector & ~3))
1685 return 0;
1686
d359192f 1687 table_base = gdt->address;
2d49ec72
GN		 1688
1689 if (selector & 4) { /* from ldt */
1690 u16 ldt_selector = kvm_read_ldt();
1691
1692 if (!(ldt_selector & ~3))
1693 return 0;
1694
1695 table_base = segment_base(ldt_selector);
1696 }
1697 d = (struct desc_struct *)(table_base + (selector & ~7));
1698 v = get_desc_base(d);
1699#ifdef CONFIG_X86_64
1700 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1701 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1702#endif
1703 return v;
1704}
1705
1706static inline unsigned long kvm_read_tr_base(void)
1707{
1708 u16 tr;
1709 asm("str %0" : "=g"(tr));
1710 return segment_base(tr);
1711}
1712
04d2cc77 1713static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1714{
04d2cc77 1715 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1716 int i;
04d2cc77 1717
a2fa3e9f 1718 if (vmx->host_state.loaded)
33ed6329
AK		 1719 return;
1720
a2fa3e9f 1721 vmx->host_state.loaded = 1;
33ed6329
AK		 1722 /*
1723 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1724 * allow segment selectors with cpl > 0 or ti == 1.
1725 */
d6e88aec 1726 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1727 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1728 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1729 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1730 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1731 vmx->host_state.fs_reload_needed = 0;
1732 } else {
33ed6329 1733 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1734 vmx->host_state.fs_reload_needed = 1;
33ed6329 1735 }
9581d442 1736 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1737 if (!(vmx->host_state.gs_sel & 7))
1738 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1739 else {
1740 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1741 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1742 }
1743
b2da15ac
AK		 1744#ifdef CONFIG_X86_64
1745 savesegment(ds, vmx->host_state.ds_sel);
1746 savesegment(es, vmx->host_state.es_sel);
1747#endif
1748
33ed6329
AK		 1749#ifdef CONFIG_X86_64
1750 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1751 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1752#else
a2fa3e9f
GH		 1753 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1754 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1755#endif
707c0874
AK		 1756
1757#ifdef CONFIG_X86_64
c8770e7b
AK		 1758 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1759 if (is_long_mode(&vmx->vcpu))
44ea2b17 1760 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1761#endif
da8999d3
LJ		 1762 if (boot_cpu_has(X86_FEATURE_MPX))
1763 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1764 for (i = 0; i < vmx->save_nmsrs; ++i)
1765 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1766 vmx->guest_msrs[i].data,
1767 vmx->guest_msrs[i].mask);
33ed6329
AK		 1768}
1769
a9b21b62 1770static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1771{
a2fa3e9f 1772 if (!vmx->host_state.loaded)
33ed6329
AK		 1773 return;
1774
e1beb1d3 1775 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1776 vmx->host_state.loaded = 0;
c8770e7b
AK		 1777#ifdef CONFIG_X86_64
1778 if (is_long_mode(&vmx->vcpu))
1779 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1780#endif
152d3f2f 1781 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1782 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1783#ifdef CONFIG_X86_64
9581d442 1784 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1785#else
1786 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1787#endif
33ed6329 1788 }
0a77fe4c
AK		 1789 if (vmx->host_state.fs_reload_needed)
1790 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1791#ifdef CONFIG_X86_64
1792 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1793 loadsegment(ds, vmx->host_state.ds_sel);
1794 loadsegment(es, vmx->host_state.es_sel);
1795 }
b2da15ac 1796#endif
152d3f2f 1797 reload_tss();
44ea2b17 1798#ifdef CONFIG_X86_64
c8770e7b 1799 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1800#endif
da8999d3
LJ		 1801 if (vmx->host_state.msr_host_bndcfgs)
1802 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1803 /*
1804 * If the FPU is not active (through the host task or
1805 * the guest vcpu), then restore the cr0.TS bit.
1806 */
1807 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1808 stts();
89cbc767 1809 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1810}
1811
a9b21b62
AK		 1812static void vmx_load_host_state(struct vcpu_vmx *vmx)
1813{
1814 preempt_disable();
1815 __vmx_load_host_state(vmx);
1816 preempt_enable();
1817}
1818
6aa8b732
AK		 1819/*
1820 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1821 * vcpu mutex is already taken.
1822 */
15ad7146 1823static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1824{
a2fa3e9f 1825 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1826 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1827
4610c9cc
DX		 1828 if (!vmm_exclusive)
1829 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1830 else if (vmx->loaded_vmcs->cpu != cpu)
1831 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1832
d462b819
NHE		 1833 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1834 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1835 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1836 }
1837
d462b819 1838 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1839 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1840 unsigned long sysenter_esp;
1841
a8eeb04a 1842 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1843 local_irq_disable();
8f536b76 1844 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1845
1846 /*
1847 * Read loaded_vmcs->cpu should be before fetching
1848 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1849 * See the comments in __loaded_vmcs_clear().
1850 */
1851 smp_rmb();
1852
d462b819
NHE		 1853 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1854 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1855 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1856 local_irq_enable();
1857
6aa8b732
AK		 1858 /*
1859 * Linux uses per-cpu TSS and GDT, so set these when switching
1860 * processors.
1861 */
d6e88aec 1862 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1863 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1864
1865 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1866 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1867 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1868 }
6aa8b732
AK		 1869}
1870
1871static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1872{
a9b21b62 1873 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1874 if (!vmm_exclusive) {
d462b819
NHE		 1875 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1876 vcpu->cpu = -1;
4610c9cc
DX		 1877 kvm_cpu_vmxoff();
1878 }
6aa8b732
AK		 1879}
1880
5fd86fcf
AK		 1881static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1882{
81231c69
AK		 1883 ulong cr0;
1884
5fd86fcf
AK		 1885 if (vcpu->fpu_active)
1886 return;
1887 vcpu->fpu_active = 1;
81231c69
AK		 1888 cr0 = vmcs_readl(GUEST_CR0);
1889 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1890 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1891 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1892 update_exception_bitmap(vcpu);
edcafe3c 1893 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1894 if (is_guest_mode(vcpu))
1895 vcpu->arch.cr0_guest_owned_bits &=
1896 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1897 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1898}
1899
edcafe3c
AK		 1900static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1901
fe3ef05c
NHE		 1902/*
1903 * Return the cr0 value that a nested guest would read. This is a combination
1904 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1905 * its hypervisor (cr0_read_shadow).
1906 */
1907static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1908{
1909 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1910 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1911}
1912static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1913{
1914 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1915 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1916}
1917
5fd86fcf
AK		 1918static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1919{
36cf24e0
NHE		 1920 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1921 * set this *before* calling this function.
1922 */
edcafe3c 1923 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1924 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1925 update_exception_bitmap(vcpu);
edcafe3c
AK		 1926 vcpu->arch.cr0_guest_owned_bits = 0;
1927 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1928 if (is_guest_mode(vcpu)) {
1929 /*
1930 * L1's specified read shadow might not contain the TS bit,
1931 * so now that we turned on shadowing of this bit, we need to
1932 * set this bit of the shadow. Like in nested_vmx_run we need
1933 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1934 * up-to-date here because we just decached cr0.TS (and we'll
1935 * only update vmcs12->guest_cr0 on nested exit).
1936 */
1937 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1938 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1939 (vcpu->arch.cr0 & X86_CR0_TS);
1940 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1941 } else
1942 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1943}
1944
6aa8b732
AK		 1945static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1946{
78ac8b47 1947 unsigned long rflags, save_rflags;
345dcaa8 1948
6de12732
AK		 1949 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1950 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1951 rflags = vmcs_readl(GUEST_RFLAGS);
1952 if (to_vmx(vcpu)->rmode.vm86_active) {
1953 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1954 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1955 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1956 }
1957 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1958 }
6de12732 1959 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1960}
1961
1962static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1963{
6de12732
AK		 1964 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1965 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1966 if (to_vmx(vcpu)->rmode.vm86_active) {
1967 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1968 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1969 }
6aa8b732
AK		 1970 vmcs_writel(GUEST_RFLAGS, rflags);
1971}
1972
37ccdcbe 1973static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1974{
1975 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1976 int ret = 0;
1977
1978 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1979 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1980 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1981 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1982
37ccdcbe 1983 return ret;
2809f5d2
GC		 1984}
1985
1986static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1987{
1988 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1989 u32 interruptibility = interruptibility_old;
1990
1991 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1992
48005f64 1993 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1994 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1995 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1996 interruptibility |= GUEST_INTR_STATE_STI;
1997
1998 if ((interruptibility != interruptibility_old))
1999 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2000}
2001
6aa8b732
AK		 2002static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2003{
2004 unsigned long rip;
6aa8b732 2005
5fdbf976 2006 rip = kvm_rip_read(vcpu);
6aa8b732 2007 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2008 kvm_rip_write(vcpu, rip);
6aa8b732 2009
2809f5d2
GC		 2010 /* skipping an emulated instruction also counts */
2011 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2012}
2013
0b6ac343
NHE		 2014/*
2015 * KVM wants to inject page-faults which it got to the guest. This function
2016 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2017 */
e011c663 2018static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2019{
2020 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2021
e011c663 2022 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2023 return 0;
2024
533558bc
JK		 2025 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2026 vmcs_read32(VM_EXIT_INTR_INFO),
2027 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2028 return 1;
2029}
2030
298101da 2031static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2032 bool has_error_code, u32 error_code,
2033 bool reinject)
298101da 2034{
77ab6db0 2035 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2036 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2037
e011c663
GN		 2038 if (!reinject && is_guest_mode(vcpu) &&
2039 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2040 return;
2041
8ab2d2e2 2042 if (has_error_code) {
77ab6db0 2043 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2044 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2045 }
77ab6db0 2046
7ffd92c5 2047 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2048 int inc_eip = 0;
2049 if (kvm_exception_is_soft(nr))
2050 inc_eip = vcpu->arch.event_exit_inst_len;
2051 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2052 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2053 return;
2054 }
2055
66fd3f7f
GN		 2056 if (kvm_exception_is_soft(nr)) {
2057 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2058 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2059 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2060 } else
2061 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2062
2063 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2064}
2065
4e47c7a6
SY		 2066static bool vmx_rdtscp_supported(void)
2067{
2068 return cpu_has_vmx_rdtscp();
2069}
2070
ad756a16
MJ		 2071static bool vmx_invpcid_supported(void)
2072{
2073 return cpu_has_vmx_invpcid() && enable_ept;
2074}
2075
a75beee6
ED		 2076/*
2077 * Swap MSR entry in host/guest MSR entry array.
2078 */
8b9cf98c 2079static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2080{
26bb0981 2081 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2082
2083 tmp = vmx->guest_msrs[to];
2084 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2085 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2086}
2087
8d14695f
YZ		 2088static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2089{
2090 unsigned long *msr_bitmap;
2091
2092 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2093 if (is_long_mode(vcpu))
2094 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2095 else
2096 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2097 } else {
2098 if (is_long_mode(vcpu))
2099 msr_bitmap = vmx_msr_bitmap_longmode;
2100 else
2101 msr_bitmap = vmx_msr_bitmap_legacy;
2102 }
2103
2104 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2105}
2106
e38aea3e
AK		 2107/*
2108 * Set up the vmcs to automatically save and restore system
2109 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2110 * mode, as fiddling with msrs is very expensive.
2111 */
8b9cf98c 2112static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2113{
26bb0981 2114 int save_nmsrs, index;
e38aea3e 2115
a75beee6
ED		 2116 save_nmsrs = 0;
2117#ifdef CONFIG_X86_64
8b9cf98c 2118 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2119 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2120 if (index >= 0)
8b9cf98c
RR		 2121 move_msr_up(vmx, index, save_nmsrs++);
2122 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2123 if (index >= 0)
8b9cf98c
RR		 2124 move_msr_up(vmx, index, save_nmsrs++);
2125 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2126 if (index >= 0)
8b9cf98c 2127 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2128 index = __find_msr_index(vmx, MSR_TSC_AUX);
2129 if (index >= 0 && vmx->rdtscp_enabled)
2130 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2131 /*
8c06585d 2132 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2133 * if efer.sce is enabled.
2134 */
8c06585d 2135 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2136 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2137 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2138 }
2139#endif
92c0d900
AK		 2140 index = __find_msr_index(vmx, MSR_EFER);
2141 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2142 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2143
26bb0981 2144 vmx->save_nmsrs = save_nmsrs;
5897297b 2145
8d14695f
YZ		 2146 if (cpu_has_vmx_msr_bitmap())
2147 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2148}
2149
6aa8b732
AK		 2150/*
2151 * reads and returns guest's timestamp counter "register"
2152 * guest_tsc = host_tsc + tsc_offset -- 21.3
2153 */
2154static u64 guest_read_tsc(void)
2155{
2156 u64 host_tsc, tsc_offset;
2157
2158 rdtscll(host_tsc);
2159 tsc_offset = vmcs_read64(TSC_OFFSET);
2160 return host_tsc + tsc_offset;
2161}
2162
d5c1785d
NHE		 2163/*
2164 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2165 * counter, even if a nested guest (L2) is currently running.
2166 */
48d89b92 2167static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2168{
886b470c 2169 u64 tsc_offset;
d5c1785d 2170
d5c1785d
NHE		 2171 tsc_offset = is_guest_mode(vcpu) ?
2172 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2173 vmcs_read64(TSC_OFFSET);
2174 return host_tsc + tsc_offset;
2175}
2176
4051b188 2177/*
cc578287
ZA		 2178 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2179 * software catchup for faster rates on slower CPUs.
4051b188 2180 */
cc578287 2181static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2182{
cc578287
ZA		 2183 if (!scale)
2184 return;
2185
2186 if (user_tsc_khz > tsc_khz) {
2187 vcpu->arch.tsc_catchup = 1;
2188 vcpu->arch.tsc_always_catchup = 1;
2189 } else
2190 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2191}
2192
ba904635
WA		 2193static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2194{
2195 return vmcs_read64(TSC_OFFSET);
2196}
2197
6aa8b732 2198/*
99e3e30a 2199 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2200 */
99e3e30a 2201static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2202{
27fc51b2 2203 if (is_guest_mode(vcpu)) {
7991825b 2204 /*
27fc51b2
NHE		 2205 * We're here if L1 chose not to trap WRMSR to TSC. According
2206 * to the spec, this should set L1's TSC; The offset that L1
2207 * set for L2 remains unchanged, and still needs to be added
2208 * to the newly set TSC to get L2's TSC.
7991825b 2209 */
27fc51b2
NHE		 2210 struct vmcs12 *vmcs12;
2211 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2212 /* recalculate vmcs02.TSC_OFFSET: */
2213 vmcs12 = get_vmcs12(vcpu);
2214 vmcs_write64(TSC_OFFSET, offset +
2215 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2216 vmcs12->tsc_offset : 0));
2217 } else {
489223ed
YY		 2218 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2219 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2220 vmcs_write64(TSC_OFFSET, offset);
2221 }
6aa8b732
AK		 2222}
2223
f1e2b260 2224static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2225{
2226 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2227
e48672fa 2228 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2229 if (is_guest_mode(vcpu)) {
2230 /* Even when running L2, the adjustment needs to apply to L1 */
2231 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2232 } else
2233 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2234 offset + adjustment);
e48672fa
ZA		 2235}
2236
857e4099
JR		 2237static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2238{
2239 return target_tsc - native_read_tsc();
2240}
2241
801d3424
NHE		 2242static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2243{
2244 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2245 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2246}
2247
2248/*
2249 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2250 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2251 * all guests if the "nested" module option is off, and can also be disabled
2252 * for a single guest by disabling its VMX cpuid bit.
2253 */
2254static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2255{
2256 return nested && guest_cpuid_has_vmx(vcpu);
2257}
2258
b87a51ae
NHE		 2259/*
2260 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2261 * returned for the various VMX controls MSRs when nested VMX is enabled.
2262 * The same values should also be used to verify that vmcs12 control fields are
2263 * valid during nested entry from L1 to L2.
2264 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2265 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2266 * bit in the high half is on if the corresponding bit in the control field
2267 * may be on. See also vmx_control_verify().
2268 * TODO: allow these variables to be modified (downgraded) by module options
2269 * or other means.
2270 */
2271static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2272static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2273static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2274static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2275static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2276static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2277static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2278static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2279static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2280static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2281static __init void nested_vmx_setup_ctls_msrs(void)
2282{
2283 /*
2284 * Note that as a general rule, the high half of the MSRs (bits in
2285 * the control fields which may be 1) should be initialized by the
2286 * intersection of the underlying hardware's MSR (i.e., features which
2287 * can be supported) and the list of features we want to expose -
2288 * because they are known to be properly supported in our code.
2289 * Also, usually, the low half of the MSRs (bits which must be 1) can
2290 * be set to 0, meaning that L1 may turn off any of these bits. The
2291 * reason is that if one of these bits is necessary, it will appear
2292 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2293 * fields of vmcs01 and vmcs02, will turn these bits off - and
2294 * nested_vmx_exit_handled() will not pass related exits to L1.
2295 * These rules have exceptions below.
2296 */
2297
2298 /* pin-based controls */
eabeaacc
JK		 2299 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2300 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2301 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2302 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2303 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2304 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2305 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2306
3dbcd8da 2307 /* exit controls */
c0dfee58
ACL		 2308 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2309 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2310 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2311
c0dfee58 2312 nested_vmx_exit_ctls_high &=
b87a51ae 2313#ifdef CONFIG_X86_64
c0dfee58 2314 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2315#endif
f4124500
JK		 2316 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2317 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2318 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2319 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2320
36be0b9d
PB		 2321 if (vmx_mpx_supported())
2322 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2323
2996fca0
JK		 2324 /* We support free control of debug control saving. */
2325 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2326 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2327
b87a51ae
NHE		 2328 /* entry controls */
2329 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2330 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2331 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2332 nested_vmx_entry_ctls_high &=
57435349
JK		 2333#ifdef CONFIG_X86_64
2334 VM_ENTRY_IA32E_MODE |
2335#endif
2336 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2337 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2338 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2339 if (vmx_mpx_supported())
2340 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2341
2996fca0
JK		 2342 /* We support free control of debug control loading. */
2343 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2344 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2345
b87a51ae
NHE		 2346 /* cpu-based controls */
2347 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2348 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2349 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2350 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2351 CPU_BASED_VIRTUAL_INTR_PENDING |
2352 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2353 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2354 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2355 CPU_BASED_CR3_STORE_EXITING |
2356#ifdef CONFIG_X86_64
2357 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2358#endif
2359 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2360 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2361 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2362 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2363 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2364 /*
2365 * We can allow some features even when not supported by the
2366 * hardware. For example, L1 can specify an MSR bitmap - and we
2367 * can use it to avoid exits to L1 - even when L0 runs L2
2368 * without MSR bitmaps.
2369 */
560b7ee1
JK		 2370 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2371 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2372
3dcdf3ec
JK		 2373 /* We support free control of CR3 access interception. */
2374 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2375 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2376
b87a51ae
NHE		 2377 /* secondary cpu-based controls */
2378 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2379 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2380 nested_vmx_secondary_ctls_low = 0;
2381 nested_vmx_secondary_ctls_high &=
d6851fbe 2382 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2383 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2384 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2385
afa61f75
NHE		 2386 if (enable_ept) {
2387 /* nested EPT: emulate EPT also to L1 */
2388 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2389 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2390 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2391 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2392 nested_vmx_ept_caps &= vmx_capability.ept;
2393 /*
4b855078
BD		 2394 * For nested guests, we don't do anything specific
2395 * for single context invalidation. Hence, only advertise
2396 * support for global context invalidation.
afa61f75 2397 */
4b855078 2398 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2399 } else
2400 nested_vmx_ept_caps = 0;
2401
c18911a2
JK		 2402 /* miscellaneous data */
2403 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2404 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2405 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2406 VMX_MISC_ACTIVITY_HLT;
c18911a2 2407 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2408}
2409
2410static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2411{
2412 /*
2413 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2414 */
2415 return ((control & high) | low) == control;
2416}
2417
2418static inline u64 vmx_control_msr(u32 low, u32 high)
2419{
2420 return low | ((u64)high << 32);
2421}
2422
cae50139 2423/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2424static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2425{
b87a51ae 2426 switch (msr_index) {
b87a51ae
NHE		 2427 case MSR_IA32_VMX_BASIC:
2428 /*
2429 * This MSR reports some information about VMX support. We
2430 * should return information about the VMX we emulate for the
2431 * guest, and the VMCS structure we give it - not about the
2432 * VMX support of the underlying hardware.
2433 */
3dbcd8da 2434 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2435 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2436 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2437 break;
2438 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2439 case MSR_IA32_VMX_PINBASED_CTLS:
2440 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2441 nested_vmx_pinbased_ctls_high);
2442 break;
2443 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2444 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2445 nested_vmx_procbased_ctls_high);
2446 break;
b87a51ae
NHE		 2447 case MSR_IA32_VMX_PROCBASED_CTLS:
2448 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2449 nested_vmx_procbased_ctls_high);
2450 break;
2451 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2452 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2453 nested_vmx_exit_ctls_high);
2454 break;
b87a51ae
NHE		 2455 case MSR_IA32_VMX_EXIT_CTLS:
2456 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2457 nested_vmx_exit_ctls_high);
2458 break;
2459 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2460 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2461 nested_vmx_entry_ctls_high);
2462 break;
b87a51ae
NHE		 2463 case MSR_IA32_VMX_ENTRY_CTLS:
2464 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2465 nested_vmx_entry_ctls_high);
2466 break;
2467 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2468 *pdata = vmx_control_msr(nested_vmx_misc_low,
2469 nested_vmx_misc_high);
b87a51ae
NHE		 2470 break;
2471 /*
2472 * These MSRs specify bits which the guest must keep fixed (on or off)
2473 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2474 * We picked the standard core2 setting.
2475 */
2476#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2477#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2478 case MSR_IA32_VMX_CR0_FIXED0:
2479 *pdata = VMXON_CR0_ALWAYSON;
2480 break;
2481 case MSR_IA32_VMX_CR0_FIXED1:
2482 *pdata = -1ULL;
2483 break;
2484 case MSR_IA32_VMX_CR4_FIXED0:
2485 *pdata = VMXON_CR4_ALWAYSON;
2486 break;
2487 case MSR_IA32_VMX_CR4_FIXED1:
2488 *pdata = -1ULL;
2489 break;
2490 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2491 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2492 break;
2493 case MSR_IA32_VMX_PROCBASED_CTLS2:
2494 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2495 nested_vmx_secondary_ctls_high);
2496 break;
2497 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2498 /* Currently, no nested vpid support */
2499 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2500 break;
2501 default:
b87a51ae 2502 return 1;
b3897a49
NHE		 2503 }
2504
b87a51ae
NHE		 2505 return 0;
2506}
2507
6aa8b732
AK		 2508/*
2509 * Reads an msr value (of 'msr_index') into 'pdata'.
2510 * Returns 0 on success, non-0 otherwise.
2511 * Assumes vcpu_load() was already called.
2512 */
2513static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2514{
2515 u64 data;
26bb0981 2516 struct shared_msr_entry *msr;
6aa8b732
AK		 2517
2518 if (!pdata) {
2519 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2520 return -EINVAL;
2521 }
2522
2523 switch (msr_index) {
05b3e0c2 2524#ifdef CONFIG_X86_64
6aa8b732
AK		 2525 case MSR_FS_BASE:
2526 data = vmcs_readl(GUEST_FS_BASE);
2527 break;
2528 case MSR_GS_BASE:
2529 data = vmcs_readl(GUEST_GS_BASE);
2530 break;
44ea2b17
AK		 2531 case MSR_KERNEL_GS_BASE:
2532 vmx_load_host_state(to_vmx(vcpu));
2533 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2534 break;
26bb0981 2535#endif
6aa8b732 2536 case MSR_EFER:
3bab1f5d 2537 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2538 case MSR_IA32_TSC:
6aa8b732
AK		 2539 data = guest_read_tsc();
2540 break;
2541 case MSR_IA32_SYSENTER_CS:
2542 data = vmcs_read32(GUEST_SYSENTER_CS);
2543 break;
2544 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2545 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2546 break;
2547 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2548 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2549 break;
0dd376e7 2550 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2551 if (!vmx_mpx_supported())
2552 return 1;
0dd376e7
LJ		 2553 data = vmcs_read64(GUEST_BNDCFGS);
2554 break;
cae50139
JK		 2555 case MSR_IA32_FEATURE_CONTROL:
2556 if (!nested_vmx_allowed(vcpu))
2557 return 1;
2558 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2559 break;
2560 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2561 if (!nested_vmx_allowed(vcpu))
2562 return 1;
2563 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2564 case MSR_TSC_AUX:
2565 if (!to_vmx(vcpu)->rdtscp_enabled)
2566 return 1;
2567 /* Otherwise falls through */
6aa8b732 2568 default:
8b9cf98c 2569 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2570 if (msr) {
2571 data = msr->data;
2572 break;
6aa8b732 2573 }
3bab1f5d 2574 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2575 }
2576
2577 *pdata = data;
2578 return 0;
2579}
2580
cae50139
JK		 2581static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2582
6aa8b732
AK		 2583/*
2584 * Writes msr value into into the appropriate "register".
2585 * Returns 0 on success, non-0 otherwise.
2586 * Assumes vcpu_load() was already called.
2587 */
8fe8ab46 2588static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2589{
a2fa3e9f 2590 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2591 struct shared_msr_entry *msr;
2cc51560 2592 int ret = 0;
8fe8ab46
WA		 2593 u32 msr_index = msr_info->index;
2594 u64 data = msr_info->data;
2cc51560 2595
6aa8b732 2596 switch (msr_index) {
3bab1f5d 2597 case MSR_EFER:
8fe8ab46 2598 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2599 break;
16175a79 2600#ifdef CONFIG_X86_64
6aa8b732 2601 case MSR_FS_BASE:
2fb92db1 2602 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2603 vmcs_writel(GUEST_FS_BASE, data);
2604 break;
2605 case MSR_GS_BASE:
2fb92db1 2606 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2607 vmcs_writel(GUEST_GS_BASE, data);
2608 break;
44ea2b17
AK		 2609 case MSR_KERNEL_GS_BASE:
2610 vmx_load_host_state(vmx);
2611 vmx->msr_guest_kernel_gs_base = data;
2612 break;
6aa8b732
AK		 2613#endif
2614 case MSR_IA32_SYSENTER_CS:
2615 vmcs_write32(GUEST_SYSENTER_CS, data);
2616 break;
2617 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2618 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2619 break;
2620 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2621 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2622 break;
0dd376e7 2623 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2624 if (!vmx_mpx_supported())
2625 return 1;
0dd376e7
LJ		 2626 vmcs_write64(GUEST_BNDCFGS, data);
2627 break;
af24a4e4 2628 case MSR_IA32_TSC:
8fe8ab46 2629 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2630 break;
468d472f
SY		 2631 case MSR_IA32_CR_PAT:
2632 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2633 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2634 return 1;
468d472f
SY		 2635 vmcs_write64(GUEST_IA32_PAT, data);
2636 vcpu->arch.pat = data;
2637 break;
2638 }
8fe8ab46 2639 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2640 break;
ba904635
WA		 2641 case MSR_IA32_TSC_ADJUST:
2642 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2643 break;
cae50139
JK		 2644 case MSR_IA32_FEATURE_CONTROL:
2645 if (!nested_vmx_allowed(vcpu) ||
2646 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2647 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2648 return 1;
2649 vmx->nested.msr_ia32_feature_control = data;
2650 if (msr_info->host_initiated && data == 0)
2651 vmx_leave_nested(vcpu);
2652 break;
2653 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2654 return 1; /* they are read-only */
4e47c7a6
SY		 2655 case MSR_TSC_AUX:
2656 if (!vmx->rdtscp_enabled)
2657 return 1;
2658 /* Check reserved bit, higher 32 bits should be zero */
2659 if ((data >> 32) != 0)
2660 return 1;
2661 /* Otherwise falls through */
6aa8b732 2662 default:
8b9cf98c 2663 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2664 if (msr) {
8b3c3104 2665 u64 old_msr_data = msr->data;
3bab1f5d 2666 msr->data = data;
2225fd56
AK		 2667 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2668 preempt_disable();
8b3c3104
AH		 2669 ret = kvm_set_shared_msr(msr->index, msr->data,
2670 msr->mask);
2225fd56 2671 preempt_enable();
8b3c3104
AH		 2672 if (ret)
2673 msr->data = old_msr_data;
2225fd56 2674 }
3bab1f5d 2675 break;
6aa8b732 2676 }
8fe8ab46 2677 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2678 }
2679
2cc51560 2680 return ret;
6aa8b732
AK		 2681}
2682
5fdbf976 2683static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2684{
5fdbf976
MT		 2685 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2686 switch (reg) {
2687 case VCPU_REGS_RSP:
2688 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2689 break;
2690 case VCPU_REGS_RIP:
2691 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2692 break;
6de4f3ad
AK		 2693 case VCPU_EXREG_PDPTR:
2694 if (enable_ept)
2695 ept_save_pdptrs(vcpu);
2696 break;
5fdbf976
MT		 2697 default:
2698 break;
2699 }
6aa8b732
AK		 2700}
2701
6aa8b732
AK		 2702static __init int cpu_has_kvm_support(void)
2703{
6210e37b 2704 return cpu_has_vmx();
6aa8b732
AK		 2705}
2706
2707static __init int vmx_disabled_by_bios(void)
2708{
2709 u64 msr;
2710
2711 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2712 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2713 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2714 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2715 && tboot_enabled())
2716 return 1;
23f3e991 2717 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2718 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2719 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2720 && !tboot_enabled()) {
2721 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2722 "activate TXT before enabling KVM\n");
cafd6659 2723 return 1;
f9335afe 2724 }
23f3e991
JC		 2725 /* launched w/o TXT and VMX disabled */
2726 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2727 && !tboot_enabled())
2728 return 1;
cafd6659
SW		 2729 }
2730
2731 return 0;
6aa8b732
AK		 2732}
2733
7725b894
DX		 2734static void kvm_cpu_vmxon(u64 addr)
2735{
2736 asm volatile (ASM_VMX_VMXON_RAX
2737 : : "a"(&addr), "m"(addr)
2738 : "memory", "cc");
2739}
2740
13a34e06 2741static int hardware_enable(void)
6aa8b732
AK		 2742{
2743 int cpu = raw_smp_processor_id();
2744 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2745 u64 old, test_bits;
6aa8b732 2746
10474ae8
AG		 2747 if (read_cr4() & X86_CR4_VMXE)
2748 return -EBUSY;
2749
d462b819 2750 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2751
2752 /*
2753 * Now we can enable the vmclear operation in kdump
2754 * since the loaded_vmcss_on_cpu list on this cpu
2755 * has been initialized.
2756 *
2757 * Though the cpu is not in VMX operation now, there
2758 * is no problem to enable the vmclear operation
2759 * for the loaded_vmcss_on_cpu list is empty!
2760 */
2761 crash_enable_local_vmclear(cpu);
2762
6aa8b732 2763 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2764
2765 test_bits = FEATURE_CONTROL_LOCKED;
2766 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2767 if (tboot_enabled())
2768 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2769
2770 if ((old & test_bits) != test_bits) {
6aa8b732 2771 /* enable and lock */
cafd6659
SW		 2772 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2773 }
66aee91a 2774 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2775
4610c9cc
DX		 2776 if (vmm_exclusive) {
2777 kvm_cpu_vmxon(phys_addr);
2778 ept_sync_global();
2779 }
10474ae8 2780
89cbc767 2781 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2782
10474ae8 2783 return 0;
6aa8b732
AK		 2784}
2785
d462b819 2786static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2787{
2788 int cpu = raw_smp_processor_id();
d462b819 2789 struct loaded_vmcs *v, *n;
543e4243 2790
d462b819
NHE		 2791 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2792 loaded_vmcss_on_cpu_link)
2793 __loaded_vmcs_clear(v);
543e4243
AK		 2794}
2795
710ff4a8
EH		 2796
2797/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2798 * tricks.
2799 */
2800static void kvm_cpu_vmxoff(void)
6aa8b732 2801{
4ecac3fd 2802 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2803}
2804
13a34e06 2805static void hardware_disable(void)
710ff4a8 2806{
4610c9cc 2807 if (vmm_exclusive) {
d462b819 2808 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2809 kvm_cpu_vmxoff();
2810 }
7725b894 2811 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2812}
2813
1c3d14fe 2814static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2815 u32 msr, u32 *result)
1c3d14fe
YS		 2816{
2817 u32 vmx_msr_low, vmx_msr_high;
2818 u32 ctl = ctl_min | ctl_opt;
2819
2820 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2821
2822 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2823 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2824
2825 /* Ensure minimum (required) set of control bits are supported. */
2826 if (ctl_min & ~ctl)
002c7f7c 2827 return -EIO;
1c3d14fe
YS		 2828
2829 *result = ctl;
2830 return 0;
2831}
2832
110312c8
AK		 2833static __init bool allow_1_setting(u32 msr, u32 ctl)
2834{
2835 u32 vmx_msr_low, vmx_msr_high;
2836
2837 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2838 return vmx_msr_high & ctl;
2839}
2840
002c7f7c 2841static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2842{
2843 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2844 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2845 u32 _pin_based_exec_control = 0;
2846 u32 _cpu_based_exec_control = 0;
f78e0e2e 2847 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2848 u32 _vmexit_control = 0;
2849 u32 _vmentry_control = 0;
2850
10166744 2851 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2852#ifdef CONFIG_X86_64
2853 CPU_BASED_CR8_LOAD_EXITING |
2854 CPU_BASED_CR8_STORE_EXITING |
2855#endif
d56f546d
SY		 2856 CPU_BASED_CR3_LOAD_EXITING |
2857 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2858 CPU_BASED_USE_IO_BITMAPS |
2859 CPU_BASED_MOV_DR_EXITING |
a7052897 2860 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2861 CPU_BASED_MWAIT_EXITING |
2862 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2863 CPU_BASED_INVLPG_EXITING |
2864 CPU_BASED_RDPMC_EXITING;
443381a8 2865
f78e0e2e 2866 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2867 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2868 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2869 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2870 &_cpu_based_exec_control) < 0)
002c7f7c 2871 return -EIO;
6e5d865c
YS		 2872#ifdef CONFIG_X86_64
2873 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2874 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2875 ~CPU_BASED_CR8_STORE_EXITING;
2876#endif
f78e0e2e 2877 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2878 min2 = 0;
2879 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2880 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2881 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2882 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2883 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2884 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2885 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2886 SECONDARY_EXEC_RDTSCP |
83d4c286 2887 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2888 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2889 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2890 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2891 if (adjust_vmx_controls(min2, opt2,
2892 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2893 &_cpu_based_2nd_exec_control) < 0)
2894 return -EIO;
2895 }
2896#ifndef CONFIG_X86_64
2897 if (!(_cpu_based_2nd_exec_control &
2898 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2899 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2900#endif
83d4c286
YZ		 2901
2902 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2903 _cpu_based_2nd_exec_control &= ~(
8d14695f 2904 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2905 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2906 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2907
d56f546d 2908 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2909 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2910 enabled */
5fff7d27
GN		 2911 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2912 CPU_BASED_CR3_STORE_EXITING |
2913 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2914 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2915 vmx_capability.ept, vmx_capability.vpid);
2916 }
1c3d14fe 2917
81908bf4 2918 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2919#ifdef CONFIG_X86_64
2920 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2921#endif
a547c6db 2922 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2923 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2924 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2925 &_vmexit_control) < 0)
002c7f7c 2926 return -EIO;
1c3d14fe 2927
01e439be
YZ		 2928 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2929 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2930 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2931 &_pin_based_exec_control) < 0)
2932 return -EIO;
2933
2934 if (!(_cpu_based_2nd_exec_control &
2935 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2936 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2937 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2938
c845f9c6 2939 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2940 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2941 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2942 &_vmentry_control) < 0)
002c7f7c 2943 return -EIO;
6aa8b732 2944
c68876fd 2945 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2946
2947 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2948 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2949 return -EIO;
1c3d14fe
YS		 2950
2951#ifdef CONFIG_X86_64
2952 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2953 if (vmx_msr_high & (1u<<16))
002c7f7c 2954 return -EIO;
1c3d14fe
YS		 2955#endif
2956
2957 /* Require Write-Back (WB) memory type for VMCS accesses. */
2958 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2959 return -EIO;
1c3d14fe 2960
002c7f7c
YS		 2961 vmcs_conf->size = vmx_msr_high & 0x1fff;
2962 vmcs_conf->order = get_order(vmcs_config.size);
2963 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2964
002c7f7c
YS		 2965 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2966 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2967 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2968 vmcs_conf->vmexit_ctrl = _vmexit_control;
2969 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2970
110312c8
AK		 2971 cpu_has_load_ia32_efer =
2972 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2973 VM_ENTRY_LOAD_IA32_EFER)
2974 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2975 VM_EXIT_LOAD_IA32_EFER);
2976
8bf00a52
GN		 2977 cpu_has_load_perf_global_ctrl =
2978 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2979 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2980 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2981 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2982
2983 /*
2984 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2985 * but due to arrata below it can't be used. Workaround is to use
2986 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2987 *
2988 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2989 *
2990 * AAK155 (model 26)
2991 * AAP115 (model 30)
2992 * AAT100 (model 37)
2993 * BC86,AAY89,BD102 (model 44)
2994 * BA97 (model 46)
2995 *
2996 */
2997 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2998 switch (boot_cpu_data.x86_model) {
2999 case 26:
3000 case 30:
3001 case 37:
3002 case 44:
3003 case 46:
3004 cpu_has_load_perf_global_ctrl = false;
3005 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3006 "does not work properly. Using workaround\n");
3007 break;
3008 default:
3009 break;
3010 }
3011 }
3012
1c3d14fe 3013 return 0;
c68876fd 3014}
6aa8b732
AK		 3015
3016static struct vmcs *alloc_vmcs_cpu(int cpu)
3017{
3018 int node = cpu_to_node(cpu);
3019 struct page *pages;
3020 struct vmcs *vmcs;
3021
6484eb3e 3022 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3023 if (!pages)
3024 return NULL;
3025 vmcs = page_address(pages);
1c3d14fe
YS		 3026 memset(vmcs, 0, vmcs_config.size);
3027 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3028 return vmcs;
3029}
3030
3031static struct vmcs *alloc_vmcs(void)
3032{
d3b2c338 3033 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3034}
3035
3036static void free_vmcs(struct vmcs *vmcs)
3037{
1c3d14fe 3038 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3039}
3040
d462b819
NHE		 3041/*
3042 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3043 */
3044static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3045{
3046 if (!loaded_vmcs->vmcs)
3047 return;
3048 loaded_vmcs_clear(loaded_vmcs);
3049 free_vmcs(loaded_vmcs->vmcs);
3050 loaded_vmcs->vmcs = NULL;
3051}
3052
39959588 3053static void free_kvm_area(void)
6aa8b732
AK		 3054{
3055 int cpu;
3056
3230bb47 3057 for_each_possible_cpu(cpu) {
6aa8b732 3058 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3059 per_cpu(vmxarea, cpu) = NULL;
3060 }
6aa8b732
AK		 3061}
3062
fe2b201b
BD		 3063static void init_vmcs_shadow_fields(void)
3064{
3065 int i, j;
3066
3067 /* No checks for read only fields yet */
3068
3069 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3070 switch (shadow_read_write_fields[i]) {
3071 case GUEST_BNDCFGS:
3072 if (!vmx_mpx_supported())
3073 continue;
3074 break;
3075 default:
3076 break;
3077 }
3078
3079 if (j < i)
3080 shadow_read_write_fields[j] =
3081 shadow_read_write_fields[i];
3082 j++;
3083 }
3084 max_shadow_read_write_fields = j;
3085
3086 /* shadowed fields guest access without vmexit */
3087 for (i = 0; i < max_shadow_read_write_fields; i++) {
3088 clear_bit(shadow_read_write_fields[i],
3089 vmx_vmwrite_bitmap);
3090 clear_bit(shadow_read_write_fields[i],
3091 vmx_vmread_bitmap);
3092 }
3093 for (i = 0; i < max_shadow_read_only_fields; i++)
3094 clear_bit(shadow_read_only_fields[i],
3095 vmx_vmread_bitmap);
3096}
3097
6aa8b732
AK		 3098static __init int alloc_kvm_area(void)
3099{
3100 int cpu;
3101
3230bb47 3102 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3103 struct vmcs *vmcs;
3104
3105 vmcs = alloc_vmcs_cpu(cpu);
3106 if (!vmcs) {
3107 free_kvm_area();
3108 return -ENOMEM;
3109 }
3110
3111 per_cpu(vmxarea, cpu) = vmcs;
3112 }
3113 return 0;
3114}
3115
14168786
GN		 3116static bool emulation_required(struct kvm_vcpu *vcpu)
3117{
3118 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3119}
3120
91b0aa2c 3121static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3122 struct kvm_segment *save)
6aa8b732 3123{
d99e4152
GN		 3124 if (!emulate_invalid_guest_state) {
3125 /*
3126 * CS and SS RPL should be equal during guest entry according
3127 * to VMX spec, but in reality it is not always so. Since vcpu
3128 * is in the middle of the transition from real mode to
3129 * protected mode it is safe to assume that RPL 0 is a good
3130 * default value.
3131 */
3132 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3133 save->selector &= ~SELECTOR_RPL_MASK;
3134 save->dpl = save->selector & SELECTOR_RPL_MASK;
3135 save->s = 1;
6aa8b732 3136 }
d99e4152 3137 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3138}
3139
3140static void enter_pmode(struct kvm_vcpu *vcpu)
3141{
3142 unsigned long flags;
a89a8fb9 3143 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3144
d99e4152
GN		 3145 /*
3146 * Update real mode segment cache. It may be not up-to-date if sement
3147 * register was written while vcpu was in a guest mode.
3148 */
3149 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3150 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3151 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3152 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3153 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3154 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3155
7ffd92c5 3156 vmx->rmode.vm86_active = 0;
6aa8b732 3157
2fb92db1
AK		 3158 vmx_segment_cache_clear(vmx);
3159
f5f7b2fe 3160 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3161
3162 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3163 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3164 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3165 vmcs_writel(GUEST_RFLAGS, flags);
3166
66aee91a
RR		 3167 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3168 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3169
3170 update_exception_bitmap(vcpu);
3171
91b0aa2c
GN		 3172 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3173 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3174 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3175 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3176 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3177 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3178}
3179
f5f7b2fe 3180static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3181{
772e0318 3182 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3183 struct kvm_segment var = *save;
3184
3185 var.dpl = 0x3;
3186 if (seg == VCPU_SREG_CS)
3187 var.type = 0x3;
3188
3189 if (!emulate_invalid_guest_state) {
3190 var.selector = var.base >> 4;
3191 var.base = var.base & 0xffff0;
3192 var.limit = 0xffff;
3193 var.g = 0;
3194 var.db = 0;
3195 var.present = 1;
3196 var.s = 1;
3197 var.l = 0;
3198 var.unusable = 0;
3199 var.type = 0x3;
3200 var.avl = 0;
3201 if (save->base & 0xf)
3202 printk_once(KERN_WARNING "kvm: segment base is not "
3203 "paragraph aligned when entering "
3204 "protected mode (seg=%d)", seg);
3205 }
6aa8b732 3206
d99e4152
GN		 3207 vmcs_write16(sf->selector, var.selector);
3208 vmcs_write32(sf->base, var.base);
3209 vmcs_write32(sf->limit, var.limit);
3210 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3211}
3212
3213static void enter_rmode(struct kvm_vcpu *vcpu)
3214{
3215 unsigned long flags;
a89a8fb9 3216 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3217
f5f7b2fe
AK		 3218 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3219 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3220 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3221 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3222 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3223 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3224 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3225
7ffd92c5 3226 vmx->rmode.vm86_active = 1;
6aa8b732 3227
776e58ea
GN		 3228 /*
3229 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3230 * vcpu. Warn the user that an update is overdue.
776e58ea 3231 */
4918c6ca 3232 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3233 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3234 "called before entering vcpu\n");
776e58ea 3235
2fb92db1
AK		 3236 vmx_segment_cache_clear(vmx);
3237
4918c6ca 3238 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3239 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3240 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3241
3242 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3243 vmx->rmode.save_rflags = flags;
6aa8b732 3244
053de044 3245 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3246
3247 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3248 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3249 update_exception_bitmap(vcpu);
3250
d99e4152
GN		 3251 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3252 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3253 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3254 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3255 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3256 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3257
8668a3c4 3258 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3259}
3260
401d10de
AS		 3261static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3262{
3263 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3264 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3265
3266 if (!msr)
3267 return;
401d10de 3268
44ea2b17
AK		 3269 /*
3270 * Force kernel_gs_base reloading before EFER changes, as control
3271 * of this msr depends on is_long_mode().
3272 */
3273 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3274 vcpu->arch.efer = efer;
401d10de 3275 if (efer & EFER_LMA) {
2961e876 3276 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3277 msr->data = efer;
3278 } else {
2961e876 3279 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3280
3281 msr->data = efer & ~EFER_LME;
3282 }
3283 setup_msrs(vmx);
3284}
3285
05b3e0c2 3286#ifdef CONFIG_X86_64
6aa8b732
AK		 3287
3288static void enter_lmode(struct kvm_vcpu *vcpu)
3289{
3290 u32 guest_tr_ar;
3291
2fb92db1
AK		 3292 vmx_segment_cache_clear(to_vmx(vcpu));
3293
6aa8b732
AK		 3294 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3295 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3296 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3297 __func__);
6aa8b732
AK		 3298 vmcs_write32(GUEST_TR_AR_BYTES,
3299 (guest_tr_ar & ~AR_TYPE_MASK)
3300 | AR_TYPE_BUSY_64_TSS);
3301 }
da38f438 3302 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3303}
3304
3305static void exit_lmode(struct kvm_vcpu *vcpu)
3306{
2961e876 3307 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3308 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3309}
3310
3311#endif
3312
2384d2b3
SY		 3313static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3314{
b9d762fa 3315 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3316 if (enable_ept) {
3317 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3318 return;
4e1096d2 3319 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3320 }
2384d2b3
SY		 3321}
3322
e8467fda
AK		 3323static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3324{
3325 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3326
3327 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3328 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3329}
3330
aff48baa
AK		 3331static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3332{
3333 if (enable_ept && is_paging(vcpu))
3334 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3335 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3336}
3337
25c4c276 3338static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3339{
fc78f519
AK		 3340 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3341
3342 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3343 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3344}
3345
1439442c
SY		 3346static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3347{
d0d538b9
GN		 3348 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3349
6de4f3ad
AK		 3350 if (!test_bit(VCPU_EXREG_PDPTR,
3351 (unsigned long *)&vcpu->arch.regs_dirty))
3352 return;
3353
1439442c 3354 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3355 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3356 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3357 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3358 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3359 }
3360}
3361
8f5d549f
AK		 3362static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3363{
d0d538b9
GN		 3364 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3365
8f5d549f 3366 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3367 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3368 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3369 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3370 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3371 }
6de4f3ad
AK		 3372
3373 __set_bit(VCPU_EXREG_PDPTR,
3374 (unsigned long *)&vcpu->arch.regs_avail);
3375 __set_bit(VCPU_EXREG_PDPTR,
3376 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3377}
3378
5e1746d6 3379static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3380
3381static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3382 unsigned long cr0,
3383 struct kvm_vcpu *vcpu)
3384{
5233dd51
MT		 3385 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3386 vmx_decache_cr3(vcpu);
1439442c
SY		 3387 if (!(cr0 & X86_CR0_PG)) {
3388 /* From paging/starting to nonpaging */
3389 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3390 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3391 (CPU_BASED_CR3_LOAD_EXITING |
3392 CPU_BASED_CR3_STORE_EXITING));
3393 vcpu->arch.cr0 = cr0;
fc78f519 3394 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3395 } else if (!is_paging(vcpu)) {
3396 /* From nonpaging to paging */
3397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3398 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3399 ~(CPU_BASED_CR3_LOAD_EXITING |
3400 CPU_BASED_CR3_STORE_EXITING));
3401 vcpu->arch.cr0 = cr0;
fc78f519 3402 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3403 }
95eb84a7
SY		 3404
3405 if (!(cr0 & X86_CR0_WP))
3406 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3407}
3408
6aa8b732
AK		 3409static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3410{
7ffd92c5 3411 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3412 unsigned long hw_cr0;
3413
5037878e 3414 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3415 if (enable_unrestricted_guest)
5037878e 3416 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3417 else {
5037878e 3418 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3419
218e763f
GN		 3420 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3421 enter_pmode(vcpu);
6aa8b732 3422
218e763f
GN		 3423 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3424 enter_rmode(vcpu);
3425 }
6aa8b732 3426
05b3e0c2 3427#ifdef CONFIG_X86_64
f6801dff 3428 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3429 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3430 enter_lmode(vcpu);
707d92fa 3431 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3432 exit_lmode(vcpu);
3433 }
3434#endif
3435
089d034e 3436 if (enable_ept)
1439442c
SY		 3437 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3438
02daab21 3439 if (!vcpu->fpu_active)
81231c69 3440 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3441
6aa8b732 3442 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3443 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3444 vcpu->arch.cr0 = cr0;
14168786
GN		 3445
3446 /* depends on vcpu->arch.cr0 to be set to a new value */
3447 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3448}
3449
1439442c
SY		 3450static u64 construct_eptp(unsigned long root_hpa)
3451{
3452 u64 eptp;
3453
3454 /* TODO write the value reading from MSR */
3455 eptp = VMX_EPT_DEFAULT_MT |
3456 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3457 if (enable_ept_ad_bits)
3458 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3459 eptp |= (root_hpa & PAGE_MASK);
3460
3461 return eptp;
3462}
3463
6aa8b732
AK		 3464static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3465{
1439442c
SY		 3466 unsigned long guest_cr3;
3467 u64 eptp;
3468
3469 guest_cr3 = cr3;
089d034e 3470 if (enable_ept) {
1439442c
SY		 3471 eptp = construct_eptp(cr3);
3472 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3473 if (is_paging(vcpu) || is_guest_mode(vcpu))
3474 guest_cr3 = kvm_read_cr3(vcpu);
3475 else
3476 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3477 ept_load_pdptrs(vcpu);
1439442c
SY		 3478 }
3479
2384d2b3 3480 vmx_flush_tlb(vcpu);
1439442c 3481 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3482}
3483
5e1746d6 3484static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3485{
7ffd92c5 3486 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3487 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3488
5e1746d6
NHE		 3489 if (cr4 & X86_CR4_VMXE) {
3490 /*
3491 * To use VMXON (and later other VMX instructions), a guest
3492 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3493 * So basically the check on whether to allow nested VMX
3494 * is here.
3495 */
3496 if (!nested_vmx_allowed(vcpu))
3497 return 1;
1a0d74e6
JK		 3498 }
3499 if (to_vmx(vcpu)->nested.vmxon &&
3500 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3501 return 1;
3502
ad312c7c 3503 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3504 if (enable_ept) {
3505 if (!is_paging(vcpu)) {
3506 hw_cr4 &= ~X86_CR4_PAE;
3507 hw_cr4 |= X86_CR4_PSE;
c08800a5 3508 /*
e1e746b3
FW		 3509 * SMEP/SMAP is disabled if CPU is in non-paging mode
3510 * in hardware. However KVM always uses paging mode to
c08800a5 3511 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3512 * To emulate this behavior, SMEP/SMAP needs to be
3513 * manually disabled when guest switches to non-paging
3514 * mode.
c08800a5 3515 */
e1e746b3 3516 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3517 } else if (!(cr4 & X86_CR4_PAE)) {
3518 hw_cr4 &= ~X86_CR4_PAE;
3519 }
3520 }
1439442c
SY		 3521
3522 vmcs_writel(CR4_READ_SHADOW, cr4);
3523 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3524 return 0;
6aa8b732
AK		 3525}
3526
6aa8b732
AK		 3527static void vmx_get_segment(struct kvm_vcpu *vcpu,
3528 struct kvm_segment *var, int seg)
3529{
a9179499 3530 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3531 u32 ar;
3532
c6ad1153 3533 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3534 *var = vmx->rmode.segs[seg];
a9179499 3535 if (seg == VCPU_SREG_TR
2fb92db1 3536 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3537 return;
1390a28b
AK		 3538 var->base = vmx_read_guest_seg_base(vmx, seg);
3539 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3540 return;
a9179499 3541 }
2fb92db1
AK		 3542 var->base = vmx_read_guest_seg_base(vmx, seg);
3543 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3544 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3545 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3546 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3547 var->type = ar & 15;
3548 var->s = (ar >> 4) & 1;
3549 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3550 /*
3551 * Some userspaces do not preserve unusable property. Since usable
3552 * segment has to be present according to VMX spec we can use present
3553 * property to amend userspace bug by making unusable segment always
3554 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3555 * segment as unusable.
3556 */
3557 var->present = !var->unusable;
6aa8b732
AK		 3558 var->avl = (ar >> 12) & 1;
3559 var->l = (ar >> 13) & 1;
3560 var->db = (ar >> 14) & 1;
3561 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3562}
3563
a9179499
AK		 3564static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3565{
a9179499
AK		 3566 struct kvm_segment s;
3567
3568 if (to_vmx(vcpu)->rmode.vm86_active) {
3569 vmx_get_segment(vcpu, &s, seg);
3570 return s.base;
3571 }
2fb92db1 3572 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3573}
3574
b09408d0 3575static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3576{
b09408d0
MT		 3577 struct vcpu_vmx *vmx = to_vmx(vcpu);
3578
ae9fedc7 3579 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3580 return 0;
ae9fedc7
PB		 3581 else {
3582 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3583 return AR_DPL(ar);
69c73028 3584 }
69c73028
AK		 3585}
3586
653e3108 3587static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3588{
6aa8b732
AK		 3589 u32 ar;
3590
f0495f9b 3591 if (var->unusable || !var->present)
6aa8b732
AK		 3592 ar = 1 << 16;
3593 else {
3594 ar = var->type & 15;
3595 ar |= (var->s & 1) << 4;
3596 ar |= (var->dpl & 3) << 5;
3597 ar |= (var->present & 1) << 7;
3598 ar |= (var->avl & 1) << 12;
3599 ar |= (var->l & 1) << 13;
3600 ar |= (var->db & 1) << 14;
3601 ar |= (var->g & 1) << 15;
3602 }
653e3108
AK		 3603
3604 return ar;
3605}
3606
3607static void vmx_set_segment(struct kvm_vcpu *vcpu,
3608 struct kvm_segment *var, int seg)
3609{
7ffd92c5 3610 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3611 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3612
2fb92db1
AK		 3613 vmx_segment_cache_clear(vmx);
3614
1ecd50a9
GN		 3615 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3616 vmx->rmode.segs[seg] = *var;
3617 if (seg == VCPU_SREG_TR)
3618 vmcs_write16(sf->selector, var->selector);
3619 else if (var->s)
3620 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3621 goto out;
653e3108 3622 }
1ecd50a9 3623
653e3108
AK		 3624 vmcs_writel(sf->base, var->base);
3625 vmcs_write32(sf->limit, var->limit);
3626 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3627
3628 /*
3629 * Fix the "Accessed" bit in AR field of segment registers for older
3630 * qemu binaries.
3631 * IA32 arch specifies that at the time of processor reset the
3632 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3633 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3634 * state vmexit when "unrestricted guest" mode is turned on.
3635 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3636 * tree. Newer qemu binaries with that qemu fix would not need this
3637 * kvm hack.
3638 */
3639 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3640 var->type |= 0x1; /* Accessed */
3a624e29 3641
f924d66d 3642 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3643
3644out:
98eb2f8b 3645 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3646}
3647
6aa8b732
AK		 3648static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3649{
2fb92db1 3650 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3651
3652 *db = (ar >> 14) & 1;
3653 *l = (ar >> 13) & 1;
3654}
3655
89a27f4d 3656static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3657{
89a27f4d
GN		 3658 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3659 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3660}
3661
89a27f4d 3662static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3663{
89a27f4d
GN		 3664 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3665 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3666}
3667
89a27f4d 3668static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3669{
89a27f4d
GN		 3670 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3671 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3672}
3673
89a27f4d 3674static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3675{
89a27f4d
GN		 3676 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3677 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3678}
3679
648dfaa7
MG		 3680static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3681{
3682 struct kvm_segment var;
3683 u32 ar;
3684
3685 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3686 var.dpl = 0x3;
0647f4aa
GN		 3687 if (seg == VCPU_SREG_CS)
3688 var.type = 0x3;
648dfaa7
MG		 3689 ar = vmx_segment_access_rights(&var);
3690
3691 if (var.base != (var.selector << 4))
3692 return false;
89efbed0 3693 if (var.limit != 0xffff)
648dfaa7 3694 return false;
07f42f5f 3695 if (ar != 0xf3)
648dfaa7
MG		 3696 return false;
3697
3698 return true;
3699}
3700
3701static bool code_segment_valid(struct kvm_vcpu *vcpu)
3702{
3703 struct kvm_segment cs;
3704 unsigned int cs_rpl;
3705
3706 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3707 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3708
1872a3f4
AK		 3709 if (cs.unusable)
3710 return false;
648dfaa7
MG		 3711 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3712 return false;
3713 if (!cs.s)
3714 return false;
1872a3f4 3715 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3716 if (cs.dpl > cs_rpl)
3717 return false;
1872a3f4 3718 } else {
648dfaa7
MG		 3719 if (cs.dpl != cs_rpl)
3720 return false;
3721 }
3722 if (!cs.present)
3723 return false;
3724
3725 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3726 return true;
3727}
3728
3729static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3730{
3731 struct kvm_segment ss;
3732 unsigned int ss_rpl;
3733
3734 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3735 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3736
1872a3f4
AK		 3737 if (ss.unusable)
3738 return true;
3739 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3740 return false;
3741 if (!ss.s)
3742 return false;
3743 if (ss.dpl != ss_rpl) /* DPL != RPL */
3744 return false;
3745 if (!ss.present)
3746 return false;
3747
3748 return true;
3749}
3750
3751static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3752{
3753 struct kvm_segment var;
3754 unsigned int rpl;
3755
3756 vmx_get_segment(vcpu, &var, seg);
3757 rpl = var.selector & SELECTOR_RPL_MASK;
3758
1872a3f4
AK		 3759 if (var.unusable)
3760 return true;
648dfaa7
MG		 3761 if (!var.s)
3762 return false;
3763 if (!var.present)
3764 return false;
3765 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3766 if (var.dpl < rpl) /* DPL < RPL */
3767 return false;
3768 }
3769
3770 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3771 * rights flags
3772 */
3773 return true;
3774}
3775
3776static bool tr_valid(struct kvm_vcpu *vcpu)
3777{
3778 struct kvm_segment tr;
3779
3780 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3781
1872a3f4
AK		 3782 if (tr.unusable)
3783 return false;
648dfaa7
MG		 3784 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3785 return false;
1872a3f4 3786 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3787 return false;
3788 if (!tr.present)
3789 return false;
3790
3791 return true;
3792}
3793
3794static bool ldtr_valid(struct kvm_vcpu *vcpu)
3795{
3796 struct kvm_segment ldtr;
3797
3798 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3799
1872a3f4
AK		 3800 if (ldtr.unusable)
3801 return true;
648dfaa7
MG		 3802 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3803 return false;
3804 if (ldtr.type != 2)
3805 return false;
3806 if (!ldtr.present)
3807 return false;
3808
3809 return true;
3810}
3811
3812static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3813{
3814 struct kvm_segment cs, ss;
3815
3816 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3817 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3818
3819 return ((cs.selector & SELECTOR_RPL_MASK) ==
3820 (ss.selector & SELECTOR_RPL_MASK));
3821}
3822
3823/*
3824 * Check if guest state is valid. Returns true if valid, false if
3825 * not.
3826 * We assume that registers are always usable
3827 */
3828static bool guest_state_valid(struct kvm_vcpu *vcpu)
3829{
c5e97c80
GN		 3830 if (enable_unrestricted_guest)
3831 return true;
3832
648dfaa7 3833 /* real mode guest state checks */
f13882d8 3834 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3835 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3836 return false;
3837 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3838 return false;
3839 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3840 return false;
3841 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3842 return false;
3843 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3844 return false;
3845 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3846 return false;
3847 } else {
3848 /* protected mode guest state checks */
3849 if (!cs_ss_rpl_check(vcpu))
3850 return false;
3851 if (!code_segment_valid(vcpu))
3852 return false;
3853 if (!stack_segment_valid(vcpu))
3854 return false;
3855 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3856 return false;
3857 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3858 return false;
3859 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3860 return false;
3861 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3862 return false;
3863 if (!tr_valid(vcpu))
3864 return false;
3865 if (!ldtr_valid(vcpu))
3866 return false;
3867 }
3868 /* TODO:
3869 * - Add checks on RIP
3870 * - Add checks on RFLAGS
3871 */
3872
3873 return true;
3874}
3875
d77c26fc 3876static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3877{
40dcaa9f 3878 gfn_t fn;
195aefde 3879 u16 data = 0;
1f755a82 3880 int idx, r;
6aa8b732 3881
40dcaa9f 3882 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3883 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3884 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3885 if (r < 0)
10589a46 3886 goto out;
195aefde 3887 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3888 r = kvm_write_guest_page(kvm, fn++, &data,
3889 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3890 if (r < 0)
10589a46 3891 goto out;
195aefde
IE		 3892 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3893 if (r < 0)
10589a46 3894 goto out;
195aefde
IE		 3895 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3896 if (r < 0)
10589a46 3897 goto out;
195aefde 3898 data = ~0;
10589a46
MT		 3899 r = kvm_write_guest_page(kvm, fn, &data,
3900 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3901 sizeof(u8));
10589a46 3902out:
40dcaa9f 3903 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3904 return r;
6aa8b732
AK		 3905}
3906
b7ebfb05
SY		 3907static int init_rmode_identity_map(struct kvm *kvm)
3908{
f51770ed 3909 int i, idx, r = 0;
b7ebfb05
SY		 3910 pfn_t identity_map_pfn;
3911 u32 tmp;
3912
089d034e 3913 if (!enable_ept)
f51770ed 3914 return 0;
a255d479
TC		 3915
3916 /* Protect kvm->arch.ept_identity_pagetable_done. */
3917 mutex_lock(&kvm->slots_lock);
3918
f51770ed 3919 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3920 goto out2;
a255d479 3921
b927a3ce 3922 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3923
3924 r = alloc_identity_pagetable(kvm);
f51770ed 3925 if (r < 0)
a255d479
TC		 3926 goto out2;
3927
40dcaa9f 3928 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3929 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3930 if (r < 0)
3931 goto out;
3932 /* Set up identity-mapping pagetable for EPT in real mode */
3933 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3934 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3935 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3936 r = kvm_write_guest_page(kvm, identity_map_pfn,
3937 &tmp, i * sizeof(tmp), sizeof(tmp));
3938 if (r < 0)
3939 goto out;
3940 }
3941 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3942
b7ebfb05 3943out:
40dcaa9f 3944 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3945
3946out2:
3947 mutex_unlock(&kvm->slots_lock);
f51770ed 3948 return r;
b7ebfb05
SY		 3949}
3950
6aa8b732
AK		 3951static void seg_setup(int seg)
3952{
772e0318 3953 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3954 unsigned int ar;
6aa8b732
AK		 3955
3956 vmcs_write16(sf->selector, 0);
3957 vmcs_writel(sf->base, 0);
3958 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3959 ar = 0x93;
3960 if (seg == VCPU_SREG_CS)
3961 ar |= 0x08; /* code segment */
3a624e29
NK		 3962
3963 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3964}
3965
f78e0e2e
SY		 3966static int alloc_apic_access_page(struct kvm *kvm)
3967{
4484141a 3968 struct page *page;
f78e0e2e
SY		 3969 struct kvm_userspace_memory_region kvm_userspace_mem;
3970 int r = 0;
3971
79fac95e 3972 mutex_lock(&kvm->slots_lock);
c24ae0dc 3973 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 3974 goto out;
3975 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3976 kvm_userspace_mem.flags = 0;
73a6d941 3977 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 3978 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3979 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3980 if (r)
3981 goto out;
72dc67a6 3982
73a6d941 3983 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3984 if (is_error_page(page)) {
3985 r = -EFAULT;
3986 goto out;
3987 }
3988
c24ae0dc
TC		 3989 /*
3990 * Do not pin the page in memory, so that memory hot-unplug
3991 * is able to migrate it.
3992 */
3993 put_page(page);
3994 kvm->arch.apic_access_page_done = true;
f78e0e2e 3995out:
79fac95e 3996 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3997 return r;
3998}
3999
b7ebfb05
SY		 4000static int alloc_identity_pagetable(struct kvm *kvm)
4001{
a255d479
TC		 4002 /* Called with kvm->slots_lock held. */
4003
b7ebfb05
SY		 4004 struct kvm_userspace_memory_region kvm_userspace_mem;
4005 int r = 0;
4006
a255d479
TC		 4007 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4008
b7ebfb05
SY		 4009 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4010 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4011 kvm_userspace_mem.guest_phys_addr =
4012 kvm->arch.ept_identity_map_addr;
b7ebfb05 4013 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4014 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4015
b7ebfb05
SY		 4016 return r;
4017}
4018
2384d2b3
SY		 4019static void allocate_vpid(struct vcpu_vmx *vmx)
4020{
4021 int vpid;
4022
4023 vmx->vpid = 0;
919818ab 4024 if (!enable_vpid)
2384d2b3
SY		 4025 return;
4026 spin_lock(&vmx_vpid_lock);
4027 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4028 if (vpid < VMX_NR_VPIDS) {
4029 vmx->vpid = vpid;
4030 __set_bit(vpid, vmx_vpid_bitmap);
4031 }
4032 spin_unlock(&vmx_vpid_lock);
4033}
4034
cdbecfc3
LJ		 4035static void free_vpid(struct vcpu_vmx *vmx)
4036{
4037 if (!enable_vpid)
4038 return;
4039 spin_lock(&vmx_vpid_lock);
4040 if (vmx->vpid != 0)
4041 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4042 spin_unlock(&vmx_vpid_lock);
4043}
4044
8d14695f
YZ		 4045#define MSR_TYPE_R 1
4046#define MSR_TYPE_W 2
4047static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4048 u32 msr, int type)
25c5f225 4049{
3e7c73e9 4050 int f = sizeof(unsigned long);
25c5f225
SY		 4051
4052 if (!cpu_has_vmx_msr_bitmap())
4053 return;
4054
4055 /*
4056 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4057 * have the write-low and read-high bitmap offsets the wrong way round.
4058 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4059 */
25c5f225 4060 if (msr <= 0x1fff) {
8d14695f
YZ		 4061 if (type & MSR_TYPE_R)
4062 /* read-low */
4063 __clear_bit(msr, msr_bitmap + 0x000 / f);
4064
4065 if (type & MSR_TYPE_W)
4066 /* write-low */
4067 __clear_bit(msr, msr_bitmap + 0x800 / f);
4068
25c5f225
SY		 4069 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4070 msr &= 0x1fff;
8d14695f
YZ		 4071 if (type & MSR_TYPE_R)
4072 /* read-high */
4073 __clear_bit(msr, msr_bitmap + 0x400 / f);
4074
4075 if (type & MSR_TYPE_W)
4076 /* write-high */
4077 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4078
4079 }
4080}
4081
4082static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4083 u32 msr, int type)
4084{
4085 int f = sizeof(unsigned long);
4086
4087 if (!cpu_has_vmx_msr_bitmap())
4088 return;
4089
4090 /*
4091 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4092 * have the write-low and read-high bitmap offsets the wrong way round.
4093 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4094 */
4095 if (msr <= 0x1fff) {
4096 if (type & MSR_TYPE_R)
4097 /* read-low */
4098 __set_bit(msr, msr_bitmap + 0x000 / f);
4099
4100 if (type & MSR_TYPE_W)
4101 /* write-low */
4102 __set_bit(msr, msr_bitmap + 0x800 / f);
4103
4104 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4105 msr &= 0x1fff;
4106 if (type & MSR_TYPE_R)
4107 /* read-high */
4108 __set_bit(msr, msr_bitmap + 0x400 / f);
4109
4110 if (type & MSR_TYPE_W)
4111 /* write-high */
4112 __set_bit(msr, msr_bitmap + 0xc00 / f);
4113
25c5f225 4114 }
25c5f225
SY		 4115}
4116
5897297b
AK		 4117static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4118{
4119 if (!longmode_only)
8d14695f
YZ		 4120 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4121 msr, MSR_TYPE_R | MSR_TYPE_W);
4122 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4123 msr, MSR_TYPE_R | MSR_TYPE_W);
4124}
4125
4126static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4127{
4128 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4129 msr, MSR_TYPE_R);
4130 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4131 msr, MSR_TYPE_R);
4132}
4133
4134static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4135{
4136 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4137 msr, MSR_TYPE_R);
4138 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4139 msr, MSR_TYPE_R);
4140}
4141
4142static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4143{
4144 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4145 msr, MSR_TYPE_W);
4146 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4147 msr, MSR_TYPE_W);
5897297b
AK		 4148}
4149
01e439be
YZ		 4150static int vmx_vm_has_apicv(struct kvm *kvm)
4151{
4152 return enable_apicv && irqchip_in_kernel(kvm);
4153}
4154
a20ed54d
YZ		 4155/*
4156 * Send interrupt to vcpu via posted interrupt way.
4157 * 1. If target vcpu is running(non-root mode), send posted interrupt
4158 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4159 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4160 * interrupt from PIR in next vmentry.
4161 */
4162static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4163{
4164 struct vcpu_vmx *vmx = to_vmx(vcpu);
4165 int r;
4166
4167 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4168 return;
4169
4170 r = pi_test_and_set_on(&vmx->pi_desc);
4171 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4172#ifdef CONFIG_SMP
a20ed54d
YZ		 4173 if (!r && (vcpu->mode == IN_GUEST_MODE))
4174 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4175 POSTED_INTR_VECTOR);
4176 else
6ffbbbba 4177#endif
a20ed54d
YZ		 4178 kvm_vcpu_kick(vcpu);
4179}
4180
4181static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4182{
4183 struct vcpu_vmx *vmx = to_vmx(vcpu);
4184
4185 if (!pi_test_and_clear_on(&vmx->pi_desc))
4186 return;
4187
4188 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4189}
4190
4191static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4192{
4193 return;
4194}
4195
a3a8ff8e
NHE		 4196/*
4197 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4198 * will not change in the lifetime of the guest.
4199 * Note that host-state that does change is set elsewhere. E.g., host-state
4200 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4201 */
a547c6db 4202static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4203{
4204 u32 low32, high32;
4205 unsigned long tmpl;
4206 struct desc_ptr dt;
d974baa3 4207 unsigned long cr4;
a3a8ff8e 4208
b1a74bf8 4209 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4210 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4211
d974baa3
AL		 4212 /* Save the most likely value for this task's CR4 in the VMCS. */
4213 cr4 = read_cr4();
4214 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4215 vmx->host_state.vmcs_host_cr4 = cr4;
4216
a3a8ff8e 4217 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4218#ifdef CONFIG_X86_64
4219 /*
4220 * Load null selectors, so we can avoid reloading them in
4221 * __vmx_load_host_state(), in case userspace uses the null selectors
4222 * too (the expected case).
4223 */
4224 vmcs_write16(HOST_DS_SELECTOR, 0);
4225 vmcs_write16(HOST_ES_SELECTOR, 0);
4226#else
a3a8ff8e
NHE		 4227 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4228 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4229#endif
a3a8ff8e
NHE		 4230 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4231 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4232
4233 native_store_idt(&dt);
4234 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4235 vmx->host_idt_base = dt.address;
a3a8ff8e 4236
83287ea4 4237 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4238
4239 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4240 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4241 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4242 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4243
4244 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4245 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4246 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4247 }
4248}
4249
bf8179a0
NHE		 4250static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4251{
4252 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4253 if (enable_ept)
4254 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4255 if (is_guest_mode(&vmx->vcpu))
4256 vmx->vcpu.arch.cr4_guest_owned_bits &=
4257 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4258 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4259}
4260
01e439be
YZ		 4261static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4262{
4263 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4264
4265 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4266 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4267 return pin_based_exec_ctrl;
4268}
4269
bf8179a0
NHE		 4270static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4271{
4272 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4273
4274 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4275 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4276
bf8179a0
NHE		 4277 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4278 exec_control &= ~CPU_BASED_TPR_SHADOW;
4279#ifdef CONFIG_X86_64
4280 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4281 CPU_BASED_CR8_LOAD_EXITING;
4282#endif
4283 }
4284 if (!enable_ept)
4285 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4286 CPU_BASED_CR3_LOAD_EXITING |
4287 CPU_BASED_INVLPG_EXITING;
4288 return exec_control;
4289}
4290
4291static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4292{
4293 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4294 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4295 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4296 if (vmx->vpid == 0)
4297 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4298 if (!enable_ept) {
4299 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4300 enable_unrestricted_guest = 0;
ad756a16
MJ		 4301 /* Enable INVPCID for non-ept guests may cause performance regression. */
4302 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4303 }
4304 if (!enable_unrestricted_guest)
4305 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4306 if (!ple_gap)
4307 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4308 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4309 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4310 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4311 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4312 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4313 (handle_vmptrld).
4314 We can NOT enable shadow_vmcs here because we don't have yet
4315 a current VMCS12
4316 */
4317 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4318 return exec_control;
4319}
4320
ce88decf
XG		 4321static void ept_set_mmio_spte_mask(void)
4322{
4323 /*
4324 * EPT Misconfigurations can be generated if the value of bits 2:0
4325 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4326 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4327 * spte.
4328 */
885032b9 4329 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4330}
4331
6aa8b732
AK		 4332/*
4333 * Sets up the vmcs for emulated real mode.
4334 */
8b9cf98c 4335static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4336{
2e4ce7f5 4337#ifdef CONFIG_X86_64
6aa8b732 4338 unsigned long a;
2e4ce7f5 4339#endif
6aa8b732 4340 int i;
6aa8b732 4341
6aa8b732 4342 /* I/O */
3e7c73e9
AK		 4343 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4344 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4345
4607c2d7
AG		 4346 if (enable_shadow_vmcs) {
4347 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4348 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4349 }
25c5f225 4350 if (cpu_has_vmx_msr_bitmap())
5897297b 4351 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4352
6aa8b732
AK		 4353 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4354
6aa8b732 4355 /* Control */
01e439be 4356 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4357
bf8179a0 4358 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4359
83ff3b9d 4360 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4361 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4362 vmx_secondary_exec_control(vmx));
83ff3b9d 4363 }
f78e0e2e 4364
01e439be 4365 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4366 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4367 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4368 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4369 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4370
4371 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4372
4373 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4374 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4375 }
4376
4b8d54f9
ZE		 4377 if (ple_gap) {
4378 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4379 vmx->ple_window = ple_window;
4380 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4381 }
4382
c3707958
XG		 4383 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4384 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4385 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4386
9581d442
AK		 4387 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4388 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4389 vmx_set_constant_host_state(vmx);
05b3e0c2 4390#ifdef CONFIG_X86_64
6aa8b732
AK		 4391 rdmsrl(MSR_FS_BASE, a);
4392 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4393 rdmsrl(MSR_GS_BASE, a);
4394 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4395#else
4396 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4397 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4398#endif
4399
2cc51560
ED		 4400 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4401 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4402 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4403 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4404 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4405
468d472f 4406 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4407 u32 msr_low, msr_high;
4408 u64 host_pat;
468d472f
SY		 4409 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4410 host_pat = msr_low | ((u64) msr_high << 32);
4411 /* Write the default value follow host pat */
4412 vmcs_write64(GUEST_IA32_PAT, host_pat);
4413 /* Keep arch.pat sync with GUEST_IA32_PAT */
4414 vmx->vcpu.arch.pat = host_pat;
4415 }
4416
03916db9 4417 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4418 u32 index = vmx_msr_index[i];
4419 u32 data_low, data_high;
a2fa3e9f 4420 int j = vmx->nmsrs;
6aa8b732
AK		 4421
4422 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4423 continue;
432bd6cb
AK		 4424 if (wrmsr_safe(index, data_low, data_high) < 0)
4425 continue;
26bb0981
AK		 4426 vmx->guest_msrs[j].index = i;
4427 vmx->guest_msrs[j].data = 0;
d5696725 4428 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4429 ++vmx->nmsrs;
6aa8b732 4430 }
6aa8b732 4431
2961e876
GN		 4432
4433 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4434
4435 /* 22.2.1, 20.8.1 */
2961e876 4436 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4437
e00c8cf2 4438 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4439 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4440
4441 return 0;
4442}
4443
57f252f2 4444static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4445{
4446 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4447 struct msr_data apic_base_msr;
e00c8cf2 4448
7ffd92c5 4449 vmx->rmode.vm86_active = 0;
e00c8cf2 4450
3b86cd99
JK		 4451 vmx->soft_vnmi_blocked = 0;
4452
ad312c7c 4453 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4454 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4455 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4456 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4457 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4458 apic_base_msr.host_initiated = true;
4459 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4460
2fb92db1
AK		 4461 vmx_segment_cache_clear(vmx);
4462
5706be0d 4463 seg_setup(VCPU_SREG_CS);
66450a21 4464 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4465 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4466
4467 seg_setup(VCPU_SREG_DS);
4468 seg_setup(VCPU_SREG_ES);
4469 seg_setup(VCPU_SREG_FS);
4470 seg_setup(VCPU_SREG_GS);
4471 seg_setup(VCPU_SREG_SS);
4472
4473 vmcs_write16(GUEST_TR_SELECTOR, 0);
4474 vmcs_writel(GUEST_TR_BASE, 0);
4475 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4476 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4477
4478 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4479 vmcs_writel(GUEST_LDTR_BASE, 0);
4480 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4481 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4482
4483 vmcs_write32(GUEST_SYSENTER_CS, 0);
4484 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4485 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4486
4487 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4488 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4489
e00c8cf2
AK		 4490 vmcs_writel(GUEST_GDTR_BASE, 0);
4491 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4492
4493 vmcs_writel(GUEST_IDTR_BASE, 0);
4494 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4495
443381a8 4496 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4497 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4498 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4499
e00c8cf2
AK		 4500 /* Special registers */
4501 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4502
4503 setup_msrs(vmx);
4504
6aa8b732
AK		 4505 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4506
f78e0e2e
SY		 4507 if (cpu_has_vmx_tpr_shadow()) {
4508 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4509 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4510 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4511 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4512 vmcs_write32(TPR_THRESHOLD, 0);
4513 }
4514
a73896cb 4515 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4516
01e439be
YZ		 4517 if (vmx_vm_has_apicv(vcpu->kvm))
4518 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4519
2384d2b3
SY		 4520 if (vmx->vpid != 0)
4521 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4522
fa40052c 4523 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4524 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4525 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4526 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4527 vmx_fpu_activate(&vmx->vcpu);
4528 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4529
b9d762fa 4530 vpid_sync_context(vmx);
6aa8b732
AK		 4531}
4532
b6f1250e
NHE		 4533/*
4534 * In nested virtualization, check if L1 asked to exit on external interrupts.
4535 * For most existing hypervisors, this will always return true.
4536 */
4537static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4538{
4539 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4540 PIN_BASED_EXT_INTR_MASK;
4541}
4542
77b0f5d6
BD		 4543/*
4544 * In nested virtualization, check if L1 has set
4545 * VM_EXIT_ACK_INTR_ON_EXIT
4546 */
4547static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4548{
4549 return get_vmcs12(vcpu)->vm_exit_controls &
4550 VM_EXIT_ACK_INTR_ON_EXIT;
4551}
4552
ea8ceb83
JK		 4553static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4554{
4555 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4556 PIN_BASED_NMI_EXITING;
4557}
4558
c9a7953f 4559static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4560{
4561 u32 cpu_based_vm_exec_control;
730dca42 4562
3b86cd99
JK		 4563 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4564 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4565 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4566}
4567
c9a7953f 4568static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4569{
4570 u32 cpu_based_vm_exec_control;
4571
c9a7953f
JK		 4572 if (!cpu_has_virtual_nmis() ||
4573 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4574 enable_irq_window(vcpu);
4575 return;
4576 }
3b86cd99
JK		 4577
4578 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4579 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4580 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4581}
4582
66fd3f7f 4583static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4584{
9c8cba37 4585 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4586 uint32_t intr;
4587 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4588
229456fc 4589 trace_kvm_inj_virq(irq);
2714d1d3 4590
fa89a817 4591 ++vcpu->stat.irq_injections;
7ffd92c5 4592 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4593 int inc_eip = 0;
4594 if (vcpu->arch.interrupt.soft)
4595 inc_eip = vcpu->arch.event_exit_inst_len;
4596 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4597 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4598 return;
4599 }
66fd3f7f
GN		 4600 intr = irq | INTR_INFO_VALID_MASK;
4601 if (vcpu->arch.interrupt.soft) {
4602 intr |= INTR_TYPE_SOFT_INTR;
4603 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4604 vmx->vcpu.arch.event_exit_inst_len);
4605 } else
4606 intr |= INTR_TYPE_EXT_INTR;
4607 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4608}
4609
f08864b4
SY		 4610static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4611{
66a5a347
JK		 4612 struct vcpu_vmx *vmx = to_vmx(vcpu);
4613
0b6ac343
NHE		 4614 if (is_guest_mode(vcpu))
4615 return;
4616
3b86cd99
JK		 4617 if (!cpu_has_virtual_nmis()) {
4618 /*
4619 * Tracking the NMI-blocked state in software is built upon
4620 * finding the next open IRQ window. This, in turn, depends on
4621 * well-behaving guests: They have to keep IRQs disabled at
4622 * least as long as the NMI handler runs. Otherwise we may
4623 * cause NMI nesting, maybe breaking the guest. But as this is
4624 * highly unlikely, we can live with the residual risk.
4625 */
4626 vmx->soft_vnmi_blocked = 1;
4627 vmx->vnmi_blocked_time = 0;
4628 }
4629
487b391d 4630 ++vcpu->stat.nmi_injections;
9d58b931 4631 vmx->nmi_known_unmasked = false;
7ffd92c5 4632 if (vmx->rmode.vm86_active) {
71f9833b 4633 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4634 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4635 return;
4636 }
f08864b4
SY		 4637 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4638 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4639}
4640
3cfc3092
JK		 4641static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4642{
4643 if (!cpu_has_virtual_nmis())
4644 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4645 if (to_vmx(vcpu)->nmi_known_unmasked)
4646 return false;
c332c83a 4647 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4648}
4649
4650static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4651{
4652 struct vcpu_vmx *vmx = to_vmx(vcpu);
4653
4654 if (!cpu_has_virtual_nmis()) {
4655 if (vmx->soft_vnmi_blocked != masked) {
4656 vmx->soft_vnmi_blocked = masked;
4657 vmx->vnmi_blocked_time = 0;
4658 }
4659 } else {
9d58b931 4660 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4661 if (masked)
4662 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4663 GUEST_INTR_STATE_NMI);
4664 else
4665 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4666 GUEST_INTR_STATE_NMI);
4667 }
4668}
4669
2505dc9f
JK		 4670static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4671{
b6b8a145
JK		 4672 if (to_vmx(vcpu)->nested.nested_run_pending)
4673 return 0;
ea8ceb83 4674
2505dc9f
JK		 4675 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4676 return 0;
4677
4678 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4679 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4680 | GUEST_INTR_STATE_NMI));
4681}
4682
78646121
GN		 4683static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4684{
b6b8a145
JK		 4685 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4686 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4687 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4688 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4689}
4690
cbc94022
IE		 4691static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4692{
4693 int ret;
4694 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4695 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4696 .guest_phys_addr = addr,
4697 .memory_size = PAGE_SIZE * 3,
4698 .flags = 0,
4699 };
4700
47ae31e2 4701 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4702 if (ret)
4703 return ret;
bfc6d222 4704 kvm->arch.tss_addr = addr;
1f755a82 4705 return init_rmode_tss(kvm);
cbc94022
IE		 4706}
4707
0ca1b4f4 4708static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4709{
77ab6db0 4710 switch (vec) {
77ab6db0 4711 case BP_VECTOR:
c573cd22
JK		 4712 /*
4713 * Update instruction length as we may reinject the exception
4714 * from user space while in guest debugging mode.
4715 */
4716 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4717 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4718 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4719 return false;
4720 /* fall through */
4721 case DB_VECTOR:
4722 if (vcpu->guest_debug &
4723 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4724 return false;
d0bfb940
JK		 4725 /* fall through */
4726 case DE_VECTOR:
77ab6db0
JK		 4727 case OF_VECTOR:
4728 case BR_VECTOR:
4729 case UD_VECTOR:
4730 case DF_VECTOR:
4731 case SS_VECTOR:
4732 case GP_VECTOR:
4733 case MF_VECTOR:
0ca1b4f4
GN		 4734 return true;
4735 break;
77ab6db0 4736 }
0ca1b4f4
GN		 4737 return false;
4738}
4739
4740static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4741 int vec, u32 err_code)
4742{
4743 /*
4744 * Instruction with address size override prefix opcode 0x67
4745 * Cause the #SS fault with 0 error code in VM86 mode.
4746 */
4747 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4748 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4749 if (vcpu->arch.halt_request) {
4750 vcpu->arch.halt_request = 0;
4751 return kvm_emulate_halt(vcpu);
4752 }
4753 return 1;
4754 }
4755 return 0;
4756 }
4757
4758 /*
4759 * Forward all other exceptions that are valid in real mode.
4760 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4761 * the required debugging infrastructure rework.
4762 */
4763 kvm_queue_exception(vcpu, vec);
4764 return 1;
6aa8b732
AK		 4765}
4766
a0861c02
AK		 4767/*
4768 * Trigger machine check on the host. We assume all the MSRs are already set up
4769 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4770 * We pass a fake environment to the machine check handler because we want
4771 * the guest to be always treated like user space, no matter what context
4772 * it used internally.
4773 */
4774static void kvm_machine_check(void)
4775{
4776#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4777 struct pt_regs regs = {
4778 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4779 .flags = X86_EFLAGS_IF,
4780 };
4781
4782 do_machine_check(&regs, 0);
4783#endif
4784}
4785
851ba692 4786static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4787{
4788 /* already handled by vcpu_run */
4789 return 1;
4790}
4791
851ba692 4792static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4793{
1155f76a 4794 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4795 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4796 u32 intr_info, ex_no, error_code;
42dbaa5a 4797 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4798 u32 vect_info;
4799 enum emulation_result er;
4800
1155f76a 4801 vect_info = vmx->idt_vectoring_info;
88786475 4802 intr_info = vmx->exit_intr_info;
6aa8b732 4803
a0861c02 4804 if (is_machine_check(intr_info))
851ba692 4805 return handle_machine_check(vcpu);
a0861c02 4806
e4a41889 4807 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4808 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4809
4810 if (is_no_device(intr_info)) {
5fd86fcf 4811 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4812 return 1;
4813 }
4814
7aa81cc0 4815 if (is_invalid_opcode(intr_info)) {
51d8b661 4816 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4817 if (er != EMULATE_DONE)
7ee5d940 4818 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4819 return 1;
4820 }
4821
6aa8b732 4822 error_code = 0;
2e11384c 4823 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4824 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4825
4826 /*
4827 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4828 * MMIO, it is better to report an internal error.
4829 * See the comments in vmx_handle_exit.
4830 */
4831 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4832 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4833 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4834 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4835 vcpu->run->internal.ndata = 2;
4836 vcpu->run->internal.data[0] = vect_info;
4837 vcpu->run->internal.data[1] = intr_info;
4838 return 0;
4839 }
4840
6aa8b732 4841 if (is_page_fault(intr_info)) {
1439442c 4842 /* EPT won't cause page fault directly */
cf3ace79 4843 BUG_ON(enable_ept);
6aa8b732 4844 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4845 trace_kvm_page_fault(cr2, error_code);
4846
3298b75c 4847 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4848 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4849 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4850 }
4851
d0bfb940 4852 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4853
4854 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4855 return handle_rmode_exception(vcpu, ex_no, error_code);
4856
42dbaa5a
JK		 4857 switch (ex_no) {
4858 case DB_VECTOR:
4859 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4860 if (!(vcpu->guest_debug &
4861 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4862 vcpu->arch.dr6 &= ~15;
6f43ed01 4863 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4864 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4865 skip_emulated_instruction(vcpu);
4866
42dbaa5a
JK		 4867 kvm_queue_exception(vcpu, DB_VECTOR);
4868 return 1;
4869 }
4870 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4871 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4872 /* fall through */
4873 case BP_VECTOR:
c573cd22
JK		 4874 /*
4875 * Update instruction length as we may reinject #BP from
4876 * user space while in guest debugging mode. Reading it for
4877 * #DB as well causes no harm, it is not used in that case.
4878 */
4879 vmx->vcpu.arch.event_exit_inst_len =
4880 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4881 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4882 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4883 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4884 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4885 break;
4886 default:
d0bfb940
JK		 4887 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4888 kvm_run->ex.exception = ex_no;
4889 kvm_run->ex.error_code = error_code;
42dbaa5a 4890 break;
6aa8b732 4891 }
6aa8b732
AK		 4892 return 0;
4893}
4894
851ba692 4895static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4896{
1165f5fe 4897 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4898 return 1;
4899}
4900
851ba692 4901static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4902{
851ba692 4903 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4904 return 0;
4905}
6aa8b732 4906
851ba692 4907static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4908{
bfdaab09 4909 unsigned long exit_qualification;
34c33d16 4910 int size, in, string;
039576c0 4911 unsigned port;
6aa8b732 4912
bfdaab09 4913 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4914 string = (exit_qualification & 16) != 0;
cf8f70bf 4915 in = (exit_qualification & 8) != 0;
e70669ab 4916
cf8f70bf 4917 ++vcpu->stat.io_exits;
e70669ab 4918
cf8f70bf 4919 if (string || in)
51d8b661 4920 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4921
cf8f70bf
GN		 4922 port = exit_qualification >> 16;
4923 size = (exit_qualification & 7) + 1;
e93f36bc 4924 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4925
4926 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4927}
4928
102d8325
IM		 4929static void
4930vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4931{
4932 /*
4933 * Patch in the VMCALL instruction:
4934 */
4935 hypercall[0] = 0x0f;
4936 hypercall[1] = 0x01;
4937 hypercall[2] = 0xc1;
102d8325
IM		 4938}
4939
92fbc7b1
JK		 4940static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4941{
4942 unsigned long always_on = VMXON_CR0_ALWAYSON;
4943
4944 if (nested_vmx_secondary_ctls_high &
4945 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4946 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4947 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4948 return (val & always_on) == always_on;
4949}
4950
0fa06071 4951/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4952static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4953{
eeadf9e7 4954 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4955 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4956 unsigned long orig_val = val;
4957
eeadf9e7
NHE		 4958 /*
4959 * We get here when L2 changed cr0 in a way that did not change
4960 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4961 * but did change L0 shadowed bits. So we first calculate the
4962 * effective cr0 value that L1 would like to write into the
4963 * hardware. It consists of the L2-owned bits from the new
4964 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4965 */
1a0d74e6
JK		 4966 val = (val & ~vmcs12->cr0_guest_host_mask) |
4967 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4968
92fbc7b1 4969 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4970 return 1;
1a0d74e6
JK		 4971
4972 if (kvm_set_cr0(vcpu, val))
4973 return 1;
4974 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4975 return 0;
1a0d74e6
JK		 4976 } else {
4977 if (to_vmx(vcpu)->nested.vmxon &&
4978 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4979 return 1;
eeadf9e7 4980 return kvm_set_cr0(vcpu, val);
1a0d74e6 4981 }
eeadf9e7
NHE		 4982}
4983
4984static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4985{
4986 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4987 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4988 unsigned long orig_val = val;
4989
4990 /* analogously to handle_set_cr0 */
4991 val = (val & ~vmcs12->cr4_guest_host_mask) |
4992 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4993 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4994 return 1;
1a0d74e6 4995 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4996 return 0;
4997 } else
4998 return kvm_set_cr4(vcpu, val);
4999}
5000
5001/* called to set cr0 as approriate for clts instruction exit. */
5002static void handle_clts(struct kvm_vcpu *vcpu)
5003{
5004 if (is_guest_mode(vcpu)) {
5005 /*
5006 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5007 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5008 * just pretend it's off (also in arch.cr0 for fpu_activate).
5009 */
5010 vmcs_writel(CR0_READ_SHADOW,
5011 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5012 vcpu->arch.cr0 &= ~X86_CR0_TS;
5013 } else
5014 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5015}
5016
851ba692 5017static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5018{
229456fc 5019 unsigned long exit_qualification, val;
6aa8b732
AK		 5020 int cr;
5021 int reg;
49a9b07e 5022 int err;
6aa8b732 5023
bfdaab09 5024 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5025 cr = exit_qualification & 15;
5026 reg = (exit_qualification >> 8) & 15;
5027 switch ((exit_qualification >> 4) & 3) {
5028 case 0: /* mov to cr */
1e32c079 5029 val = kvm_register_readl(vcpu, reg);
229456fc 5030 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5031 switch (cr) {
5032 case 0:
eeadf9e7 5033 err = handle_set_cr0(vcpu, val);
db8fcefa 5034 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5035 return 1;
5036 case 3:
2390218b 5037 err = kvm_set_cr3(vcpu, val);
db8fcefa 5038 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5039 return 1;
5040 case 4:
eeadf9e7 5041 err = handle_set_cr4(vcpu, val);
db8fcefa 5042 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5043 return 1;
0a5fff19
GN		 5044 case 8: {
5045 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5046 u8 cr8 = (u8)val;
eea1cff9 5047 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5048 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5049 if (irqchip_in_kernel(vcpu->kvm))
5050 return 1;
5051 if (cr8_prev <= cr8)
5052 return 1;
851ba692 5053 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5054 return 0;
5055 }
4b8073e4 5056 }
6aa8b732 5057 break;
25c4c276 5058 case 2: /* clts */
eeadf9e7 5059 handle_clts(vcpu);
4d4ec087 5060 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5061 skip_emulated_instruction(vcpu);
6b52d186 5062 vmx_fpu_activate(vcpu);
25c4c276 5063 return 1;
6aa8b732
AK		 5064 case 1: /*mov from cr*/
5065 switch (cr) {
5066 case 3:
9f8fe504
AK		 5067 val = kvm_read_cr3(vcpu);
5068 kvm_register_write(vcpu, reg, val);
5069 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5070 skip_emulated_instruction(vcpu);
5071 return 1;
5072 case 8:
229456fc
MT		 5073 val = kvm_get_cr8(vcpu);
5074 kvm_register_write(vcpu, reg, val);
5075 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5076 skip_emulated_instruction(vcpu);
5077 return 1;
5078 }
5079 break;
5080 case 3: /* lmsw */
a1f83a74 5081 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5082 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5083 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5084
5085 skip_emulated_instruction(vcpu);
5086 return 1;
5087 default:
5088 break;
5089 }
851ba692 5090 vcpu->run->exit_reason = 0;
a737f256 5091 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5092 (int)(exit_qualification >> 4) & 3, cr);
5093 return 0;
5094}
5095
851ba692 5096static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5097{
bfdaab09 5098 unsigned long exit_qualification;
16f8a6f9
NA		 5099 int dr, dr7, reg;
5100
5101 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5102 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5103
5104 /* First, if DR does not exist, trigger UD */
5105 if (!kvm_require_dr(vcpu, dr))
5106 return 1;
6aa8b732 5107
f2483415 5108 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5109 if (!kvm_require_cpl(vcpu, 0))
5110 return 1;
16f8a6f9
NA		 5111 dr7 = vmcs_readl(GUEST_DR7);
5112 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5113 /*
5114 * As the vm-exit takes precedence over the debug trap, we
5115 * need to emulate the latter, either for the host or the
5116 * guest debugging itself.
5117 */
5118 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5119 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5120 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5121 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5122 vcpu->run->debug.arch.exception = DB_VECTOR;
5123 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5124 return 0;
5125 } else {
7305eb5d 5126 vcpu->arch.dr6 &= ~15;
6f43ed01 5127 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5128 kvm_queue_exception(vcpu, DB_VECTOR);
5129 return 1;
5130 }
5131 }
5132
81908bf4
PB		 5133 if (vcpu->guest_debug == 0) {
5134 u32 cpu_based_vm_exec_control;
5135
5136 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5137 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5138 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5139
5140 /*
5141 * No more DR vmexits; force a reload of the debug registers
5142 * and reenter on this instruction. The next vmexit will
5143 * retrieve the full state of the debug registers.
5144 */
5145 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5146 return 1;
5147 }
5148
42dbaa5a
JK		 5149 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5150 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5151 unsigned long val;
4c4d563b
JK		 5152
5153 if (kvm_get_dr(vcpu, dr, &val))
5154 return 1;
5155 kvm_register_write(vcpu, reg, val);
020df079 5156 } else
5777392e 5157 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5158 return 1;
5159
6aa8b732
AK		 5160 skip_emulated_instruction(vcpu);
5161 return 1;
5162}
5163
73aaf249
JK		 5164static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5165{
5166 return vcpu->arch.dr6;
5167}
5168
5169static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5170{
5171}
5172
81908bf4
PB		 5173static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5174{
5175 u32 cpu_based_vm_exec_control;
5176
5177 get_debugreg(vcpu->arch.db[0], 0);
5178 get_debugreg(vcpu->arch.db[1], 1);
5179 get_debugreg(vcpu->arch.db[2], 2);
5180 get_debugreg(vcpu->arch.db[3], 3);
5181 get_debugreg(vcpu->arch.dr6, 6);
5182 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5183
5184 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5185
5186 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5187 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5188 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5189}
5190
020df079
GN		 5191static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5192{
5193 vmcs_writel(GUEST_DR7, val);
5194}
5195
851ba692 5196static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5197{
06465c5a
AK		 5198 kvm_emulate_cpuid(vcpu);
5199 return 1;
6aa8b732
AK		 5200}
5201
851ba692 5202static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5203{
ad312c7c 5204 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5205 u64 data;
5206
5207 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5208 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5209 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5210 return 1;
5211 }
5212
229456fc 5213 trace_kvm_msr_read(ecx, data);
2714d1d3 5214
6aa8b732 5215 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5216 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5217 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5218 skip_emulated_instruction(vcpu);
5219 return 1;
5220}
5221
851ba692 5222static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5223{
8fe8ab46 5224 struct msr_data msr;
ad312c7c
ZX		 5225 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5226 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5227 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5228
8fe8ab46
WA		 5229 msr.data = data;
5230 msr.index = ecx;
5231 msr.host_initiated = false;
854e8bb1 5232 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5233 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5234 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5235 return 1;
5236 }
5237
59200273 5238 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5239 skip_emulated_instruction(vcpu);
5240 return 1;
5241}
5242
851ba692 5243static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5244{
3842d135 5245 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5246 return 1;
5247}
5248
851ba692 5249static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5250{
85f455f7
ED		 5251 u32 cpu_based_vm_exec_control;
5252
5253 /* clear pending irq */
5254 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5255 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5256 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5257
3842d135
AK		 5258 kvm_make_request(KVM_REQ_EVENT, vcpu);
5259
a26bf12a 5260 ++vcpu->stat.irq_window_exits;
2714d1d3 5261
c1150d8c
DL		 5262 /*
5263 * If the user space waits to inject interrupts, exit as soon as
5264 * possible
5265 */
8061823a 5266 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5267 vcpu->run->request_interrupt_window &&
8061823a 5268 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5269 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5270 return 0;
5271 }
6aa8b732
AK		 5272 return 1;
5273}
5274
851ba692 5275static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5276{
5277 skip_emulated_instruction(vcpu);
d3bef15f 5278 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5279}
5280
851ba692 5281static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5282{
510043da 5283 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5284 kvm_emulate_hypercall(vcpu);
5285 return 1;
c21415e8
IM		 5286}
5287
ec25d5e6
GN		 5288static int handle_invd(struct kvm_vcpu *vcpu)
5289{
51d8b661 5290 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5291}
5292
851ba692 5293static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5294{
f9c617f6 5295 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5296
5297 kvm_mmu_invlpg(vcpu, exit_qualification);
5298 skip_emulated_instruction(vcpu);
5299 return 1;
5300}
5301
fee84b07
AK		 5302static int handle_rdpmc(struct kvm_vcpu *vcpu)
5303{
5304 int err;
5305
5306 err = kvm_rdpmc(vcpu);
5307 kvm_complete_insn_gp(vcpu, err);
5308
5309 return 1;
5310}
5311
851ba692 5312static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5313{
5314 skip_emulated_instruction(vcpu);
f5f48ee1 5315 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5316 return 1;
5317}
5318
2acf923e
DC		 5319static int handle_xsetbv(struct kvm_vcpu *vcpu)
5320{
5321 u64 new_bv = kvm_read_edx_eax(vcpu);
5322 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5323
5324 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5325 skip_emulated_instruction(vcpu);
5326 return 1;
5327}
5328
851ba692 5329static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5330{
58fbbf26
KT		 5331 if (likely(fasteoi)) {
5332 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5333 int access_type, offset;
5334
5335 access_type = exit_qualification & APIC_ACCESS_TYPE;
5336 offset = exit_qualification & APIC_ACCESS_OFFSET;
5337 /*
5338 * Sane guest uses MOV to write EOI, with written value
5339 * not cared. So make a short-circuit here by avoiding
5340 * heavy instruction emulation.
5341 */
5342 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5343 (offset == APIC_EOI)) {
5344 kvm_lapic_set_eoi(vcpu);
5345 skip_emulated_instruction(vcpu);
5346 return 1;
5347 }
5348 }
51d8b661 5349 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5350}
5351
c7c9c56c
YZ		 5352static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5353{
5354 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5355 int vector = exit_qualification & 0xff;
5356
5357 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5358 kvm_apic_set_eoi_accelerated(vcpu, vector);
5359 return 1;
5360}
5361
83d4c286
YZ		 5362static int handle_apic_write(struct kvm_vcpu *vcpu)
5363{
5364 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5365 u32 offset = exit_qualification & 0xfff;
5366
5367 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5368 kvm_apic_write_nodecode(vcpu, offset);
5369 return 1;
5370}
5371
851ba692 5372static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5373{
60637aac 5374 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5375 unsigned long exit_qualification;
e269fb21
JK		 5376 bool has_error_code = false;
5377 u32 error_code = 0;
37817f29 5378 u16 tss_selector;
7f3d35fd 5379 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5380
5381 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5382 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5383 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5384
5385 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5386
5387 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5388 if (reason == TASK_SWITCH_GATE && idt_v) {
5389 switch (type) {
5390 case INTR_TYPE_NMI_INTR:
5391 vcpu->arch.nmi_injected = false;
654f06fc 5392 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5393 break;
5394 case INTR_TYPE_EXT_INTR:
66fd3f7f 5395 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5396 kvm_clear_interrupt_queue(vcpu);
5397 break;
5398 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5399 if (vmx->idt_vectoring_info &
5400 VECTORING_INFO_DELIVER_CODE_MASK) {
5401 has_error_code = true;
5402 error_code =
5403 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5404 }
5405 /* fall through */
64a7ec06
GN		 5406 case INTR_TYPE_SOFT_EXCEPTION:
5407 kvm_clear_exception_queue(vcpu);
5408 break;
5409 default:
5410 break;
5411 }
60637aac 5412 }
37817f29
IE		 5413 tss_selector = exit_qualification;
5414
64a7ec06
GN		 5415 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5416 type != INTR_TYPE_EXT_INTR &&
5417 type != INTR_TYPE_NMI_INTR))
5418 skip_emulated_instruction(vcpu);
5419
7f3d35fd
KW		 5420 if (kvm_task_switch(vcpu, tss_selector,
5421 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5422 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5423 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5424 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5425 vcpu->run->internal.ndata = 0;
42dbaa5a 5426 return 0;
acb54517 5427 }
42dbaa5a
JK		 5428
5429 /* clear all local breakpoint enable flags */
0e8a0996 5430 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5431
5432 /*
5433 * TODO: What about debug traps on tss switch?
5434 * Are we supposed to inject them and update dr6?
5435 */
5436
5437 return 1;
37817f29
IE		 5438}
5439
851ba692 5440static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5441{
f9c617f6 5442 unsigned long exit_qualification;
1439442c 5443 gpa_t gpa;
4f5982a5 5444 u32 error_code;
1439442c 5445 int gla_validity;
1439442c 5446
f9c617f6 5447 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5448
1439442c
SY		 5449 gla_validity = (exit_qualification >> 7) & 0x3;
5450 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5451 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5452 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5453 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5454 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5455 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5456 (long unsigned int)exit_qualification);
851ba692
AK		 5457 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5458 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5459 return 0;
1439442c
SY		 5460 }
5461
0be9c7a8
GN		 5462 /*
5463 * EPT violation happened while executing iret from NMI,
5464 * "blocked by NMI" bit has to be set before next VM entry.
5465 * There are errata that may cause this bit to not be set:
5466 * AAK134, BY25.
5467 */
bcd1c294
GN		 5468 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5469 cpu_has_virtual_nmis() &&
5470 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5471 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5472
1439442c 5473 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5474 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5475
5476 /* It is a write fault? */
5477 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5478 /* It is a fetch fault? */
5479 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5480 /* ept page table is present? */
5481 error_code |= (exit_qualification >> 3) & 0x1;
5482
25d92081
YZ		 5483 vcpu->arch.exit_qualification = exit_qualification;
5484
4f5982a5 5485 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5486}
5487
68f89400
MT		 5488static u64 ept_rsvd_mask(u64 spte, int level)
5489{
5490 int i;
5491 u64 mask = 0;
5492
5493 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5494 mask |= (1ULL << i);
5495
a32e8459 5496 if (level == 4)
68f89400
MT		 5497 /* bits 7:3 reserved */
5498 mask |= 0xf8;
a32e8459
WL		 5499 else if (spte & (1ULL << 7))
5500 /*
5501 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5502 * level == 1 if the hypervisor is using the ignored bit 7.
5503 */
5504 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5505 else if (level > 1)
5506 /* bits 6:3 reserved */
5507 mask |= 0x78;
68f89400
MT		 5508
5509 return mask;
5510}
5511
5512static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5513 int level)
5514{
5515 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5516
5517 /* 010b (write-only) */
5518 WARN_ON((spte & 0x7) == 0x2);
5519
5520 /* 110b (write/execute) */
5521 WARN_ON((spte & 0x7) == 0x6);
5522
5523 /* 100b (execute-only) and value not supported by logical processor */
5524 if (!cpu_has_vmx_ept_execute_only())
5525 WARN_ON((spte & 0x7) == 0x4);
5526
5527 /* not 000b */
5528 if ((spte & 0x7)) {
5529 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5530
5531 if (rsvd_bits != 0) {
5532 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5533 __func__, rsvd_bits);
5534 WARN_ON(1);
5535 }
5536
a32e8459
WL		 5537 /* bits 5:3 are _not_ reserved for large page or leaf page */
5538 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5539 u64 ept_mem_type = (spte & 0x38) >> 3;
5540
5541 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5542 ept_mem_type == 7) {
5543 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5544 __func__, ept_mem_type);
5545 WARN_ON(1);
5546 }
5547 }
5548 }
5549}
5550
851ba692 5551static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5552{
5553 u64 sptes[4];
ce88decf 5554 int nr_sptes, i, ret;
68f89400
MT		 5555 gpa_t gpa;
5556
5557 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5558 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5559 skip_emulated_instruction(vcpu);
5560 return 1;
5561 }
68f89400 5562
ce88decf 5563 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5564 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5565 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5566 EMULATE_DONE;
f8f55942
XG		 5567
5568 if (unlikely(ret == RET_MMIO_PF_INVALID))
5569 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5570
b37fbea6 5571 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5572 return 1;
5573
5574 /* It is the real ept misconfig */
68f89400
MT		 5575 printk(KERN_ERR "EPT: Misconfiguration.\n");
5576 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5577
5578 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5579
5580 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5581 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5582
851ba692
AK		 5583 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5584 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5585
5586 return 0;
5587}
5588
851ba692 5589static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5590{
5591 u32 cpu_based_vm_exec_control;
5592
5593 /* clear pending NMI */
5594 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5595 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5596 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5597 ++vcpu->stat.nmi_window_exits;
3842d135 5598 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5599
5600 return 1;
5601}
5602
80ced186 5603static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5604{
8b3079a5
AK		 5605 struct vcpu_vmx *vmx = to_vmx(vcpu);
5606 enum emulation_result err = EMULATE_DONE;
80ced186 5607 int ret = 1;
49e9d557
AK		 5608 u32 cpu_exec_ctrl;
5609 bool intr_window_requested;
b8405c18 5610 unsigned count = 130;
49e9d557
AK		 5611
5612 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5613 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5614
98eb2f8b 5615 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5616 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5617 return handle_interrupt_window(&vmx->vcpu);
5618
de87dcdd
AK		 5619 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5620 return 1;
5621
991eebf9 5622 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5623
ac0a48c3 5624 if (err == EMULATE_USER_EXIT) {
94452b9e 5625 ++vcpu->stat.mmio_exits;
80ced186
MG		 5626 ret = 0;
5627 goto out;
5628 }
1d5a4d9b 5629
de5f70e0
AK		 5630 if (err != EMULATE_DONE) {
5631 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5632 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5633 vcpu->run->internal.ndata = 0;
6d77dbfc 5634 return 0;
de5f70e0 5635 }
ea953ef0 5636
8d76c49e
GN		 5637 if (vcpu->arch.halt_request) {
5638 vcpu->arch.halt_request = 0;
5639 ret = kvm_emulate_halt(vcpu);
5640 goto out;
5641 }
5642
ea953ef0 5643 if (signal_pending(current))
80ced186 5644 goto out;
ea953ef0
MG		 5645 if (need_resched())
5646 schedule();
5647 }
5648
80ced186
MG		 5649out:
5650 return ret;
ea953ef0
MG		 5651}
5652
b4a2d31d
RK		 5653static int __grow_ple_window(int val)
5654{
5655 if (ple_window_grow < 1)
5656 return ple_window;
5657
5658 val = min(val, ple_window_actual_max);
5659
5660 if (ple_window_grow < ple_window)
5661 val *= ple_window_grow;
5662 else
5663 val += ple_window_grow;
5664
5665 return val;
5666}
5667
5668static int __shrink_ple_window(int val, int modifier, int minimum)
5669{
5670 if (modifier < 1)
5671 return ple_window;
5672
5673 if (modifier < ple_window)
5674 val /= modifier;
5675 else
5676 val -= modifier;
5677
5678 return max(val, minimum);
5679}
5680
5681static void grow_ple_window(struct kvm_vcpu *vcpu)
5682{
5683 struct vcpu_vmx *vmx = to_vmx(vcpu);
5684 int old = vmx->ple_window;
5685
5686 vmx->ple_window = __grow_ple_window(old);
5687
5688 if (vmx->ple_window != old)
5689 vmx->ple_window_dirty = true;
7b46268d
RK		 5690
5691 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5692}
5693
5694static void shrink_ple_window(struct kvm_vcpu *vcpu)
5695{
5696 struct vcpu_vmx *vmx = to_vmx(vcpu);
5697 int old = vmx->ple_window;
5698
5699 vmx->ple_window = __shrink_ple_window(old,
5700 ple_window_shrink, ple_window);
5701
5702 if (vmx->ple_window != old)
5703 vmx->ple_window_dirty = true;
7b46268d
RK		 5704
5705 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5706}
5707
5708/*
5709 * ple_window_actual_max is computed to be one grow_ple_window() below
5710 * ple_window_max. (See __grow_ple_window for the reason.)
5711 * This prevents overflows, because ple_window_max is int.
5712 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5713 * this process.
5714 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5715 */
5716static void update_ple_window_actual_max(void)
5717{
5718 ple_window_actual_max =
5719 __shrink_ple_window(max(ple_window_max, ple_window),
5720 ple_window_grow, INT_MIN);
5721}
5722
f2c7648d
TC		 5723static __init int hardware_setup(void)
5724{
34a1cd60
TC		 5725 int r = -ENOMEM, i, msr;
5726
5727 rdmsrl_safe(MSR_EFER, &host_efer);
5728
5729 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5730 kvm_define_shared_msr(i, vmx_msr_index[i]);
5731
5732 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5733 if (!vmx_io_bitmap_a)
5734 return r;
5735
5736 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5737 if (!vmx_io_bitmap_b)
5738 goto out;
5739
5740 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5741 if (!vmx_msr_bitmap_legacy)
5742 goto out1;
5743
5744 vmx_msr_bitmap_legacy_x2apic =
5745 (unsigned long *)__get_free_page(GFP_KERNEL);
5746 if (!vmx_msr_bitmap_legacy_x2apic)
5747 goto out2;
5748
5749 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5750 if (!vmx_msr_bitmap_longmode)
5751 goto out3;
5752
5753 vmx_msr_bitmap_longmode_x2apic =
5754 (unsigned long *)__get_free_page(GFP_KERNEL);
5755 if (!vmx_msr_bitmap_longmode_x2apic)
5756 goto out4;
5757 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5758 if (!vmx_vmread_bitmap)
5759 goto out5;
5760
5761 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5762 if (!vmx_vmwrite_bitmap)
5763 goto out6;
5764
5765 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5766 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5767
5768 /*
5769 * Allow direct access to the PC debug port (it is often used for I/O
5770 * delays, but the vmexits simply slow things down).
5771 */
5772 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5773 clear_bit(0x80, vmx_io_bitmap_a);
5774
5775 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5776
5777 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5778 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
5779
5780 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5781 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5782 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5783 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5784 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5785 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5786 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5787
5788 memcpy(vmx_msr_bitmap_legacy_x2apic,
5789 vmx_msr_bitmap_legacy, PAGE_SIZE);
5790 memcpy(vmx_msr_bitmap_longmode_x2apic,
5791 vmx_msr_bitmap_longmode, PAGE_SIZE);
5792
5793 if (enable_apicv) {
5794 for (msr = 0x800; msr <= 0x8ff; msr++)
5795 vmx_disable_intercept_msr_read_x2apic(msr);
5796
5797 /* According SDM, in x2apic mode, the whole id reg is used.
5798 * But in KVM, it only use the highest eight bits. Need to
5799 * intercept it */
5800 vmx_enable_intercept_msr_read_x2apic(0x802);
5801 /* TMCCT */
5802 vmx_enable_intercept_msr_read_x2apic(0x839);
5803 /* TPR */
5804 vmx_disable_intercept_msr_write_x2apic(0x808);
5805 /* EOI */
5806 vmx_disable_intercept_msr_write_x2apic(0x80b);
5807 /* SELF-IPI */
5808 vmx_disable_intercept_msr_write_x2apic(0x83f);
5809 }
5810
5811 if (enable_ept) {
5812 kvm_mmu_set_mask_ptes(0ull,
5813 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
5814 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
5815 0ull, VMX_EPT_EXECUTABLE_MASK);
5816 ept_set_mmio_spte_mask();
5817 kvm_enable_tdp();
5818 } else
5819 kvm_disable_tdp();
5820
5821 update_ple_window_actual_max();
5822
5823 if (setup_vmcs_config(&vmcs_config) < 0) {
5824 r = -EIO;
5825 goto out7;
5826 }
f2c7648d
TC		 5827
5828 if (boot_cpu_has(X86_FEATURE_NX))
5829 kvm_enable_efer_bits(EFER_NX);
5830
5831 if (!cpu_has_vmx_vpid())
5832 enable_vpid = 0;
5833 if (!cpu_has_vmx_shadow_vmcs())
5834 enable_shadow_vmcs = 0;
5835 if (enable_shadow_vmcs)
5836 init_vmcs_shadow_fields();
5837
5838 if (!cpu_has_vmx_ept() ||
5839 !cpu_has_vmx_ept_4levels()) {
5840 enable_ept = 0;
5841 enable_unrestricted_guest = 0;
5842 enable_ept_ad_bits = 0;
5843 }
5844
5845 if (!cpu_has_vmx_ept_ad_bits())
5846 enable_ept_ad_bits = 0;
5847
5848 if (!cpu_has_vmx_unrestricted_guest())
5849 enable_unrestricted_guest = 0;
5850
5851 if (!cpu_has_vmx_flexpriority()) {
5852 flexpriority_enabled = 0;
5853
5854 /*
5855 * set_apic_access_page_addr() is used to reload apic access
5856 * page upon invalidation. No need to do anything if the
5857 * processor does not have the APIC_ACCESS_ADDR VMCS field.
5858 */
5859 kvm_x86_ops->set_apic_access_page_addr = NULL;
5860 }
5861
5862 if (!cpu_has_vmx_tpr_shadow())
5863 kvm_x86_ops->update_cr8_intercept = NULL;
5864
5865 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5866 kvm_disable_largepages();
5867
5868 if (!cpu_has_vmx_ple())
5869 ple_gap = 0;
5870
5871 if (!cpu_has_vmx_apicv())
5872 enable_apicv = 0;
5873
5874 if (enable_apicv)
5875 kvm_x86_ops->update_cr8_intercept = NULL;
5876 else {
5877 kvm_x86_ops->hwapic_irr_update = NULL;
5878 kvm_x86_ops->deliver_posted_interrupt = NULL;
5879 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5880 }
5881
5882 if (nested)
5883 nested_vmx_setup_ctls_msrs();
5884
5885 return alloc_kvm_area();
34a1cd60
TC		 5886
5887out7:
5888 free_page((unsigned long)vmx_vmwrite_bitmap);
5889out6:
5890 free_page((unsigned long)vmx_vmread_bitmap);
5891out5:
5892 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5893out4:
5894 free_page((unsigned long)vmx_msr_bitmap_longmode);
5895out3:
5896 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5897out2:
5898 free_page((unsigned long)vmx_msr_bitmap_legacy);
5899out1:
5900 free_page((unsigned long)vmx_io_bitmap_b);
5901out:
5902 free_page((unsigned long)vmx_io_bitmap_a);
5903
5904 return r;
f2c7648d
TC		 5905}
5906
5907static __exit void hardware_unsetup(void)
5908{
34a1cd60
TC		 5909 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
5910 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5911 free_page((unsigned long)vmx_msr_bitmap_legacy);
5912 free_page((unsigned long)vmx_msr_bitmap_longmode);
5913 free_page((unsigned long)vmx_io_bitmap_b);
5914 free_page((unsigned long)vmx_io_bitmap_a);
5915 free_page((unsigned long)vmx_vmwrite_bitmap);
5916 free_page((unsigned long)vmx_vmread_bitmap);
5917
f2c7648d
TC		 5918 free_kvm_area();
5919}
5920
4b8d54f9
ZE		 5921/*
5922 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5923 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5924 */
9fb41ba8 5925static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 5926{
b4a2d31d
RK		 5927 if (ple_gap)
5928 grow_ple_window(vcpu);
5929
4b8d54f9
ZE		 5930 skip_emulated_instruction(vcpu);
5931 kvm_vcpu_on_spin(vcpu);
5932
5933 return 1;
5934}
5935
87c00572 5936static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5937{
87c00572 5938 skip_emulated_instruction(vcpu);
59708670
SY		 5939 return 1;
5940}
5941
87c00572
GS		 5942static int handle_mwait(struct kvm_vcpu *vcpu)
5943{
5944 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5945 return handle_nop(vcpu);
5946}
5947
5948static int handle_monitor(struct kvm_vcpu *vcpu)
5949{
5950 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5951 return handle_nop(vcpu);
5952}
5953
ff2f6fe9
NHE		 5954/*
5955 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5956 * We could reuse a single VMCS for all the L2 guests, but we also want the
5957 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5958 * allows keeping them loaded on the processor, and in the future will allow
5959 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5960 * every entry if they never change.
5961 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5962 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5963 *
5964 * The following functions allocate and free a vmcs02 in this pool.
5965 */
5966
5967/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5968static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5969{
5970 struct vmcs02_list *item;
5971 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5972 if (item->vmptr == vmx->nested.current_vmptr) {
5973 list_move(&item->list, &vmx->nested.vmcs02_pool);
5974 return &item->vmcs02;
5975 }
5976
5977 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5978 /* Recycle the least recently used VMCS. */
5979 item = list_entry(vmx->nested.vmcs02_pool.prev,
5980 struct vmcs02_list, list);
5981 item->vmptr = vmx->nested.current_vmptr;
5982 list_move(&item->list, &vmx->nested.vmcs02_pool);
5983 return &item->vmcs02;
5984 }
5985
5986 /* Create a new VMCS */
0fa24ce3 5987 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5988 if (!item)
5989 return NULL;
5990 item->vmcs02.vmcs = alloc_vmcs();
5991 if (!item->vmcs02.vmcs) {
5992 kfree(item);
5993 return NULL;
5994 }
5995 loaded_vmcs_init(&item->vmcs02);
5996 item->vmptr = vmx->nested.current_vmptr;
5997 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5998 vmx->nested.vmcs02_num++;
5999 return &item->vmcs02;
6000}
6001
6002/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6003static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6004{
6005 struct vmcs02_list *item;
6006 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6007 if (item->vmptr == vmptr) {
6008 free_loaded_vmcs(&item->vmcs02);
6009 list_del(&item->list);
6010 kfree(item);
6011 vmx->nested.vmcs02_num--;
6012 return;
6013 }
6014}
6015
6016/*
6017 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6018 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6019 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6020 */
6021static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6022{
6023 struct vmcs02_list *item, *n;
4fa7734c
PB		 6024
6025 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6026 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6027 /*
6028 * Something will leak if the above WARN triggers. Better than
6029 * a use-after-free.
6030 */
6031 if (vmx->loaded_vmcs == &item->vmcs02)
6032 continue;
6033
6034 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6035 list_del(&item->list);
6036 kfree(item);
4fa7734c 6037 vmx->nested.vmcs02_num--;
ff2f6fe9 6038 }
ff2f6fe9
NHE		 6039}
6040
0658fbaa
ACL		 6041/*
6042 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6043 * set the success or error code of an emulated VMX instruction, as specified
6044 * by Vol 2B, VMX Instruction Reference, "Conventions".
6045 */
6046static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6047{
6048 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6049 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6050 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6051}
6052
6053static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6054{
6055 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6056 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6057 X86_EFLAGS_SF | X86_EFLAGS_OF))
6058 | X86_EFLAGS_CF);
6059}
6060
145c28dd 6061static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6062 u32 vm_instruction_error)
6063{
6064 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6065 /*
6066 * failValid writes the error number to the current VMCS, which
6067 * can't be done there isn't a current VMCS.
6068 */
6069 nested_vmx_failInvalid(vcpu);
6070 return;
6071 }
6072 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6073 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6074 X86_EFLAGS_SF | X86_EFLAGS_OF))
6075 | X86_EFLAGS_ZF);
6076 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6077 /*
6078 * We don't need to force a shadow sync because
6079 * VM_INSTRUCTION_ERROR is not shadowed
6080 */
6081}
145c28dd 6082
f4124500
JK		 6083static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6084{
6085 struct vcpu_vmx *vmx =
6086 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6087
6088 vmx->nested.preemption_timer_expired = true;
6089 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6090 kvm_vcpu_kick(&vmx->vcpu);
6091
6092 return HRTIMER_NORESTART;
6093}
6094
19677e32
BD		 6095/*
6096 * Decode the memory-address operand of a vmx instruction, as recorded on an
6097 * exit caused by such an instruction (run by a guest hypervisor).
6098 * On success, returns 0. When the operand is invalid, returns 1 and throws
6099 * #UD or #GP.
6100 */
6101static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6102 unsigned long exit_qualification,
6103 u32 vmx_instruction_info, gva_t *ret)
6104{
6105 /*
6106 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6107 * Execution", on an exit, vmx_instruction_info holds most of the
6108 * addressing components of the operand. Only the displacement part
6109 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6110 * For how an actual address is calculated from all these components,
6111 * refer to Vol. 1, "Operand Addressing".
6112 */
6113 int scaling = vmx_instruction_info & 3;
6114 int addr_size = (vmx_instruction_info >> 7) & 7;
6115 bool is_reg = vmx_instruction_info & (1u << 10);
6116 int seg_reg = (vmx_instruction_info >> 15) & 7;
6117 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6118 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6119 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6120 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6121
6122 if (is_reg) {
6123 kvm_queue_exception(vcpu, UD_VECTOR);
6124 return 1;
6125 }
6126
6127 /* Addr = segment_base + offset */
6128 /* offset = base + [index * scale] + displacement */
6129 *ret = vmx_get_segment_base(vcpu, seg_reg);
6130 if (base_is_valid)
6131 *ret += kvm_register_read(vcpu, base_reg);
6132 if (index_is_valid)
6133 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6134 *ret += exit_qualification; /* holds the displacement */
6135
6136 if (addr_size == 1) /* 32 bit */
6137 *ret &= 0xffffffff;
6138
6139 /*
6140 * TODO: throw #GP (and return 1) in various cases that the VM*
6141 * instructions require it - e.g., offset beyond segment limit,
6142 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6143 * address, and so on. Currently these are not checked.
6144 */
6145 return 0;
6146}
6147
3573e22c
BD		 6148/*
6149 * This function performs the various checks including
6150 * - if it's 4KB aligned
6151 * - No bits beyond the physical address width are set
6152 * - Returns 0 on success or else 1
4291b588 6153 * (Intel SDM Section 30.3)
3573e22c 6154 */
4291b588
BD		 6155static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6156 gpa_t *vmpointer)
3573e22c
BD		 6157{
6158 gva_t gva;
6159 gpa_t vmptr;
6160 struct x86_exception e;
6161 struct page *page;
6162 struct vcpu_vmx *vmx = to_vmx(vcpu);
6163 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6164
6165 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6166 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6167 return 1;
6168
6169 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6170 sizeof(vmptr), &e)) {
6171 kvm_inject_page_fault(vcpu, &e);
6172 return 1;
6173 }
6174
6175 switch (exit_reason) {
6176 case EXIT_REASON_VMON:
6177 /*
6178 * SDM 3: 24.11.5
6179 * The first 4 bytes of VMXON region contain the supported
6180 * VMCS revision identifier
6181 *
6182 * Note - IA32_VMX_BASIC[48] will never be 1
6183 * for the nested case;
6184 * which replaces physical address width with 32
6185 *
6186 */
bc39c4db 6187 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6188 nested_vmx_failInvalid(vcpu);
6189 skip_emulated_instruction(vcpu);
6190 return 1;
6191 }
6192
6193 page = nested_get_page(vcpu, vmptr);
6194 if (page == NULL ||
6195 *(u32 *)kmap(page) != VMCS12_REVISION) {
6196 nested_vmx_failInvalid(vcpu);
6197 kunmap(page);
6198 skip_emulated_instruction(vcpu);
6199 return 1;
6200 }
6201 kunmap(page);
6202 vmx->nested.vmxon_ptr = vmptr;
6203 break;
4291b588 6204 case EXIT_REASON_VMCLEAR:
bc39c4db 6205 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6206 nested_vmx_failValid(vcpu,
6207 VMXERR_VMCLEAR_INVALID_ADDRESS);
6208 skip_emulated_instruction(vcpu);
6209 return 1;
6210 }
6211
6212 if (vmptr == vmx->nested.vmxon_ptr) {
6213 nested_vmx_failValid(vcpu,
6214 VMXERR_VMCLEAR_VMXON_POINTER);
6215 skip_emulated_instruction(vcpu);
6216 return 1;
6217 }
6218 break;
6219 case EXIT_REASON_VMPTRLD:
bc39c4db 6220 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6221 nested_vmx_failValid(vcpu,
6222 VMXERR_VMPTRLD_INVALID_ADDRESS);
6223 skip_emulated_instruction(vcpu);
6224 return 1;
6225 }
3573e22c 6226
4291b588
BD		 6227 if (vmptr == vmx->nested.vmxon_ptr) {
6228 nested_vmx_failValid(vcpu,
6229 VMXERR_VMCLEAR_VMXON_POINTER);
6230 skip_emulated_instruction(vcpu);
6231 return 1;
6232 }
6233 break;
3573e22c
BD		 6234 default:
6235 return 1; /* shouldn't happen */
6236 }
6237
4291b588
BD		 6238 if (vmpointer)
6239 *vmpointer = vmptr;
3573e22c
BD		 6240 return 0;
6241}
6242
ec378aee
NHE		 6243/*
6244 * Emulate the VMXON instruction.
6245 * Currently, we just remember that VMX is active, and do not save or even
6246 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6247 * do not currently need to store anything in that guest-allocated memory
6248 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6249 * argument is different from the VMXON pointer (which the spec says they do).
6250 */
6251static int handle_vmon(struct kvm_vcpu *vcpu)
6252{
6253 struct kvm_segment cs;
6254 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6255 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6256 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6257 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6258
6259 /* The Intel VMX Instruction Reference lists a bunch of bits that
6260 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6261 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6262 * Otherwise, we should fail with #UD. We test these now:
6263 */
6264 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6265 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6266 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6267 kvm_queue_exception(vcpu, UD_VECTOR);
6268 return 1;
6269 }
6270
6271 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6272 if (is_long_mode(vcpu) && !cs.l) {
6273 kvm_queue_exception(vcpu, UD_VECTOR);
6274 return 1;
6275 }
6276
6277 if (vmx_get_cpl(vcpu)) {
6278 kvm_inject_gp(vcpu, 0);
6279 return 1;
6280 }
3573e22c 6281
4291b588 6282 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6283 return 1;
6284
145c28dd
AG		 6285 if (vmx->nested.vmxon) {
6286 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6287 skip_emulated_instruction(vcpu);
6288 return 1;
6289 }
b3897a49
NHE		 6290
6291 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6292 != VMXON_NEEDED_FEATURES) {
6293 kvm_inject_gp(vcpu, 0);
6294 return 1;
6295 }
6296
8de48833
AG		 6297 if (enable_shadow_vmcs) {
6298 shadow_vmcs = alloc_vmcs();
6299 if (!shadow_vmcs)
6300 return -ENOMEM;
6301 /* mark vmcs as shadow */
6302 shadow_vmcs->revision_id |= (1u << 31);
6303 /* init shadow vmcs */
6304 vmcs_clear(shadow_vmcs);
6305 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6306 }
ec378aee 6307
ff2f6fe9
NHE		 6308 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6309 vmx->nested.vmcs02_num = 0;
6310
f4124500
JK		 6311 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6312 HRTIMER_MODE_REL);
6313 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6314
ec378aee
NHE		 6315 vmx->nested.vmxon = true;
6316
6317 skip_emulated_instruction(vcpu);
a25eb114 6318 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6319 return 1;
6320}
6321
6322/*
6323 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6324 * for running VMX instructions (except VMXON, whose prerequisites are
6325 * slightly different). It also specifies what exception to inject otherwise.
6326 */
6327static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6328{
6329 struct kvm_segment cs;
6330 struct vcpu_vmx *vmx = to_vmx(vcpu);
6331
6332 if (!vmx->nested.vmxon) {
6333 kvm_queue_exception(vcpu, UD_VECTOR);
6334 return 0;
6335 }
6336
6337 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6338 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6339 (is_long_mode(vcpu) && !cs.l)) {
6340 kvm_queue_exception(vcpu, UD_VECTOR);
6341 return 0;
6342 }
6343
6344 if (vmx_get_cpl(vcpu)) {
6345 kvm_inject_gp(vcpu, 0);
6346 return 0;
6347 }
6348
6349 return 1;
6350}
6351
e7953d7f
AG		 6352static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6353{
8a1b9dd0 6354 u32 exec_control;
9a2a05b9
PB		 6355 if (vmx->nested.current_vmptr == -1ull)
6356 return;
6357
6358 /* current_vmptr and current_vmcs12 are always set/reset together */
6359 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6360 return;
6361
012f83cb 6362 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6363 /* copy to memory all shadowed fields in case
6364 they were modified */
6365 copy_shadow_to_vmcs12(vmx);
6366 vmx->nested.sync_shadow_vmcs = false;
6367 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6368 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6369 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6370 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6371 }
e7953d7f
AG		 6372 kunmap(vmx->nested.current_vmcs12_page);
6373 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6374 vmx->nested.current_vmptr = -1ull;
6375 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6376}
6377
ec378aee
NHE		 6378/*
6379 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6380 * just stops using VMX.
6381 */
6382static void free_nested(struct vcpu_vmx *vmx)
6383{
6384 if (!vmx->nested.vmxon)
6385 return;
9a2a05b9 6386
ec378aee 6387 vmx->nested.vmxon = false;
9a2a05b9 6388 nested_release_vmcs12(vmx);
e7953d7f
AG		 6389 if (enable_shadow_vmcs)
6390 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6391 /* Unpin physical memory we referred to in current vmcs02 */
6392 if (vmx->nested.apic_access_page) {
6393 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6394 vmx->nested.apic_access_page = NULL;
fe3ef05c 6395 }
a7c0b07d
WL		 6396 if (vmx->nested.virtual_apic_page) {
6397 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6398 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6399 }
ff2f6fe9
NHE		 6400
6401 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6402}
6403
6404/* Emulate the VMXOFF instruction */
6405static int handle_vmoff(struct kvm_vcpu *vcpu)
6406{
6407 if (!nested_vmx_check_permission(vcpu))
6408 return 1;
6409 free_nested(to_vmx(vcpu));
6410 skip_emulated_instruction(vcpu);
a25eb114 6411 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6412 return 1;
6413}
6414
27d6c865
NHE		 6415/* Emulate the VMCLEAR instruction */
6416static int handle_vmclear(struct kvm_vcpu *vcpu)
6417{
6418 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6419 gpa_t vmptr;
6420 struct vmcs12 *vmcs12;
6421 struct page *page;
27d6c865
NHE		 6422
6423 if (!nested_vmx_check_permission(vcpu))
6424 return 1;
6425
4291b588 6426 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6427 return 1;
27d6c865 6428
9a2a05b9 6429 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6430 nested_release_vmcs12(vmx);
27d6c865
NHE		 6431
6432 page = nested_get_page(vcpu, vmptr);
6433 if (page == NULL) {
6434 /*
6435 * For accurate processor emulation, VMCLEAR beyond available
6436 * physical memory should do nothing at all. However, it is
6437 * possible that a nested vmx bug, not a guest hypervisor bug,
6438 * resulted in this case, so let's shut down before doing any
6439 * more damage:
6440 */
6441 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6442 return 1;
6443 }
6444 vmcs12 = kmap(page);
6445 vmcs12->launch_state = 0;
6446 kunmap(page);
6447 nested_release_page(page);
6448
6449 nested_free_vmcs02(vmx, vmptr);
6450
6451 skip_emulated_instruction(vcpu);
6452 nested_vmx_succeed(vcpu);
6453 return 1;
6454}
6455
cd232ad0
NHE		 6456static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6457
6458/* Emulate the VMLAUNCH instruction */
6459static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6460{
6461 return nested_vmx_run(vcpu, true);
6462}
6463
6464/* Emulate the VMRESUME instruction */
6465static int handle_vmresume(struct kvm_vcpu *vcpu)
6466{
6467
6468 return nested_vmx_run(vcpu, false);
6469}
6470
49f705c5
NHE		 6471enum vmcs_field_type {
6472 VMCS_FIELD_TYPE_U16 = 0,
6473 VMCS_FIELD_TYPE_U64 = 1,
6474 VMCS_FIELD_TYPE_U32 = 2,
6475 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6476};
6477
6478static inline int vmcs_field_type(unsigned long field)
6479{
6480 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6481 return VMCS_FIELD_TYPE_U32;
6482 return (field >> 13) & 0x3 ;
6483}
6484
6485static inline int vmcs_field_readonly(unsigned long field)
6486{
6487 return (((field >> 10) & 0x3) == 1);
6488}
6489
6490/*
6491 * Read a vmcs12 field. Since these can have varying lengths and we return
6492 * one type, we chose the biggest type (u64) and zero-extend the return value
6493 * to that size. Note that the caller, handle_vmread, might need to use only
6494 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6495 * 64-bit fields are to be returned).
6496 */
a2ae9df7
PB		 6497static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6498 unsigned long field, u64 *ret)
49f705c5
NHE		 6499{
6500 short offset = vmcs_field_to_offset(field);
6501 char *p;
6502
6503 if (offset < 0)
a2ae9df7 6504 return offset;
49f705c5
NHE		 6505
6506 p = ((char *)(get_vmcs12(vcpu))) + offset;
6507
6508 switch (vmcs_field_type(field)) {
6509 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6510 *ret = *((natural_width *)p);
a2ae9df7 6511 return 0;
49f705c5
NHE		 6512 case VMCS_FIELD_TYPE_U16:
6513 *ret = *((u16 *)p);
a2ae9df7 6514 return 0;
49f705c5
NHE		 6515 case VMCS_FIELD_TYPE_U32:
6516 *ret = *((u32 *)p);
a2ae9df7 6517 return 0;
49f705c5
NHE		 6518 case VMCS_FIELD_TYPE_U64:
6519 *ret = *((u64 *)p);
a2ae9df7 6520 return 0;
49f705c5 6521 default:
a2ae9df7
PB		 6522 WARN_ON(1);
6523 return -ENOENT;
49f705c5
NHE		 6524 }
6525}
6526
20b97fea 6527
a2ae9df7
PB		 6528static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6529 unsigned long field, u64 field_value){
20b97fea
AG		 6530 short offset = vmcs_field_to_offset(field);
6531 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6532 if (offset < 0)
a2ae9df7 6533 return offset;
20b97fea
AG		 6534
6535 switch (vmcs_field_type(field)) {
6536 case VMCS_FIELD_TYPE_U16:
6537 *(u16 *)p = field_value;
a2ae9df7 6538 return 0;
20b97fea
AG		 6539 case VMCS_FIELD_TYPE_U32:
6540 *(u32 *)p = field_value;
a2ae9df7 6541 return 0;
20b97fea
AG		 6542 case VMCS_FIELD_TYPE_U64:
6543 *(u64 *)p = field_value;
a2ae9df7 6544 return 0;
20b97fea
AG		 6545 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6546 *(natural_width *)p = field_value;
a2ae9df7 6547 return 0;
20b97fea 6548 default:
a2ae9df7
PB		 6549 WARN_ON(1);
6550 return -ENOENT;
20b97fea
AG		 6551 }
6552
6553}
6554
16f5b903
AG		 6555static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6556{
6557 int i;
6558 unsigned long field;
6559 u64 field_value;
6560 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6561 const unsigned long *fields = shadow_read_write_fields;
6562 const int num_fields = max_shadow_read_write_fields;
16f5b903 6563
282da870
JK		 6564 preempt_disable();
6565
16f5b903
AG		 6566 vmcs_load(shadow_vmcs);
6567
6568 for (i = 0; i < num_fields; i++) {
6569 field = fields[i];
6570 switch (vmcs_field_type(field)) {
6571 case VMCS_FIELD_TYPE_U16:
6572 field_value = vmcs_read16(field);
6573 break;
6574 case VMCS_FIELD_TYPE_U32:
6575 field_value = vmcs_read32(field);
6576 break;
6577 case VMCS_FIELD_TYPE_U64:
6578 field_value = vmcs_read64(field);
6579 break;
6580 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6581 field_value = vmcs_readl(field);
6582 break;
a2ae9df7
PB		 6583 default:
6584 WARN_ON(1);
6585 continue;
16f5b903
AG		 6586 }
6587 vmcs12_write_any(&vmx->vcpu, field, field_value);
6588 }
6589
6590 vmcs_clear(shadow_vmcs);
6591 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6592
6593 preempt_enable();
16f5b903
AG		 6594}
6595
c3114420
AG		 6596static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6597{
c2bae893
MK		 6598 const unsigned long *fields[] = {
6599 shadow_read_write_fields,
6600 shadow_read_only_fields
c3114420 6601 };
c2bae893 6602 const int max_fields[] = {
c3114420
AG		 6603 max_shadow_read_write_fields,
6604 max_shadow_read_only_fields
6605 };
6606 int i, q;
6607 unsigned long field;
6608 u64 field_value = 0;
6609 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6610
6611 vmcs_load(shadow_vmcs);
6612
c2bae893 6613 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6614 for (i = 0; i < max_fields[q]; i++) {
6615 field = fields[q][i];
6616 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6617
6618 switch (vmcs_field_type(field)) {
6619 case VMCS_FIELD_TYPE_U16:
6620 vmcs_write16(field, (u16)field_value);
6621 break;
6622 case VMCS_FIELD_TYPE_U32:
6623 vmcs_write32(field, (u32)field_value);
6624 break;
6625 case VMCS_FIELD_TYPE_U64:
6626 vmcs_write64(field, (u64)field_value);
6627 break;
6628 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6629 vmcs_writel(field, (long)field_value);
6630 break;
a2ae9df7
PB		 6631 default:
6632 WARN_ON(1);
6633 break;
c3114420
AG		 6634 }
6635 }
6636 }
6637
6638 vmcs_clear(shadow_vmcs);
6639 vmcs_load(vmx->loaded_vmcs->vmcs);
6640}
6641
49f705c5
NHE		 6642/*
6643 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6644 * used before) all generate the same failure when it is missing.
6645 */
6646static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6647{
6648 struct vcpu_vmx *vmx = to_vmx(vcpu);
6649 if (vmx->nested.current_vmptr == -1ull) {
6650 nested_vmx_failInvalid(vcpu);
6651 skip_emulated_instruction(vcpu);
6652 return 0;
6653 }
6654 return 1;
6655}
6656
6657static int handle_vmread(struct kvm_vcpu *vcpu)
6658{
6659 unsigned long field;
6660 u64 field_value;
6661 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6662 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6663 gva_t gva = 0;
6664
6665 if (!nested_vmx_check_permission(vcpu) ||
6666 !nested_vmx_check_vmcs12(vcpu))
6667 return 1;
6668
6669 /* Decode instruction info and find the field to read */
27e6fb5d 6670 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6671 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6672 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6673 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6674 skip_emulated_instruction(vcpu);
6675 return 1;
6676 }
6677 /*
6678 * Now copy part of this value to register or memory, as requested.
6679 * Note that the number of bits actually copied is 32 or 64 depending
6680 * on the guest's mode (32 or 64 bit), not on the given field's length.
6681 */
6682 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6683 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6684 field_value);
6685 } else {
6686 if (get_vmx_mem_address(vcpu, exit_qualification,
6687 vmx_instruction_info, &gva))
6688 return 1;
6689 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6690 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6691 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6692 }
6693
6694 nested_vmx_succeed(vcpu);
6695 skip_emulated_instruction(vcpu);
6696 return 1;
6697}
6698
6699
6700static int handle_vmwrite(struct kvm_vcpu *vcpu)
6701{
6702 unsigned long field;
6703 gva_t gva;
6704 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6705 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6706 /* The value to write might be 32 or 64 bits, depending on L1's long
6707 * mode, and eventually we need to write that into a field of several
6708 * possible lengths. The code below first zero-extends the value to 64
6709 * bit (field_value), and then copies only the approriate number of
6710 * bits into the vmcs12 field.
6711 */
6712 u64 field_value = 0;
6713 struct x86_exception e;
6714
6715 if (!nested_vmx_check_permission(vcpu) ||
6716 !nested_vmx_check_vmcs12(vcpu))
6717 return 1;
6718
6719 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6720 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6721 (((vmx_instruction_info) >> 3) & 0xf));
6722 else {
6723 if (get_vmx_mem_address(vcpu, exit_qualification,
6724 vmx_instruction_info, &gva))
6725 return 1;
6726 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6727 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6728 kvm_inject_page_fault(vcpu, &e);
6729 return 1;
6730 }
6731 }
6732
6733
27e6fb5d 6734 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6735 if (vmcs_field_readonly(field)) {
6736 nested_vmx_failValid(vcpu,
6737 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6738 skip_emulated_instruction(vcpu);
6739 return 1;
6740 }
6741
a2ae9df7 6742 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6743 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6744 skip_emulated_instruction(vcpu);
6745 return 1;
6746 }
6747
6748 nested_vmx_succeed(vcpu);
6749 skip_emulated_instruction(vcpu);
6750 return 1;
6751}
6752
63846663
NHE		 6753/* Emulate the VMPTRLD instruction */
6754static int handle_vmptrld(struct kvm_vcpu *vcpu)
6755{
6756 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6757 gpa_t vmptr;
8a1b9dd0 6758 u32 exec_control;
63846663
NHE		 6759
6760 if (!nested_vmx_check_permission(vcpu))
6761 return 1;
6762
4291b588 6763 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6764 return 1;
63846663
NHE		 6765
6766 if (vmx->nested.current_vmptr != vmptr) {
6767 struct vmcs12 *new_vmcs12;
6768 struct page *page;
6769 page = nested_get_page(vcpu, vmptr);
6770 if (page == NULL) {
6771 nested_vmx_failInvalid(vcpu);
6772 skip_emulated_instruction(vcpu);
6773 return 1;
6774 }
6775 new_vmcs12 = kmap(page);
6776 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6777 kunmap(page);
6778 nested_release_page_clean(page);
6779 nested_vmx_failValid(vcpu,
6780 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6781 skip_emulated_instruction(vcpu);
6782 return 1;
6783 }
63846663 6784
9a2a05b9 6785 nested_release_vmcs12(vmx);
63846663
NHE		 6786 vmx->nested.current_vmptr = vmptr;
6787 vmx->nested.current_vmcs12 = new_vmcs12;
6788 vmx->nested.current_vmcs12_page = page;
012f83cb 6789 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6790 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6791 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6792 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6793 vmcs_write64(VMCS_LINK_POINTER,
6794 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6795 vmx->nested.sync_shadow_vmcs = true;
6796 }
63846663
NHE		 6797 }
6798
6799 nested_vmx_succeed(vcpu);
6800 skip_emulated_instruction(vcpu);
6801 return 1;
6802}
6803
6a4d7550
NHE		 6804/* Emulate the VMPTRST instruction */
6805static int handle_vmptrst(struct kvm_vcpu *vcpu)
6806{
6807 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6808 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6809 gva_t vmcs_gva;
6810 struct x86_exception e;
6811
6812 if (!nested_vmx_check_permission(vcpu))
6813 return 1;
6814
6815 if (get_vmx_mem_address(vcpu, exit_qualification,
6816 vmx_instruction_info, &vmcs_gva))
6817 return 1;
6818 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6819 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6820 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6821 sizeof(u64), &e)) {
6822 kvm_inject_page_fault(vcpu, &e);
6823 return 1;
6824 }
6825 nested_vmx_succeed(vcpu);
6826 skip_emulated_instruction(vcpu);
6827 return 1;
6828}
6829
bfd0a56b
NHE		 6830/* Emulate the INVEPT instruction */
6831static int handle_invept(struct kvm_vcpu *vcpu)
6832{
6833 u32 vmx_instruction_info, types;
6834 unsigned long type;
6835 gva_t gva;
6836 struct x86_exception e;
6837 struct {
6838 u64 eptp, gpa;
6839 } operand;
bfd0a56b
NHE		 6840
6841 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6842 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6843 kvm_queue_exception(vcpu, UD_VECTOR);
6844 return 1;
6845 }
6846
6847 if (!nested_vmx_check_permission(vcpu))
6848 return 1;
6849
6850 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6851 kvm_queue_exception(vcpu, UD_VECTOR);
6852 return 1;
6853 }
6854
6855 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6856 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6857
6858 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6859
6860 if (!(types & (1UL << type))) {
6861 nested_vmx_failValid(vcpu,
6862 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6863 return 1;
6864 }
6865
6866 /* According to the Intel VMX instruction reference, the memory
6867 * operand is read even if it isn't needed (e.g., for type==global)
6868 */
6869 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6870 vmx_instruction_info, &gva))
6871 return 1;
6872 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6873 sizeof(operand), &e)) {
6874 kvm_inject_page_fault(vcpu, &e);
6875 return 1;
6876 }
6877
6878 switch (type) {
bfd0a56b
NHE		 6879 case VMX_EPT_EXTENT_GLOBAL:
6880 kvm_mmu_sync_roots(vcpu);
77c3913b 6881 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 6882 nested_vmx_succeed(vcpu);
6883 break;
6884 default:
4b855078 6885 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6886 BUG_ON(1);
6887 break;
6888 }
6889
6890 skip_emulated_instruction(vcpu);
6891 return 1;
6892}
6893
a642fc30
PM		 6894static int handle_invvpid(struct kvm_vcpu *vcpu)
6895{
6896 kvm_queue_exception(vcpu, UD_VECTOR);
6897 return 1;
6898}
6899
6aa8b732
AK		 6900/*
6901 * The exit handlers return 1 if the exit was handled fully and guest execution
6902 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6903 * to be done to userspace and return 0.
6904 */
772e0318 6905static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6906 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6907 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6908 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6909 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6910 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6911 [EXIT_REASON_CR_ACCESS] = handle_cr,
6912 [EXIT_REASON_DR_ACCESS] = handle_dr,
6913 [EXIT_REASON_CPUID] = handle_cpuid,
6914 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6915 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6916 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6917 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6918 [EXIT_REASON_INVD] = handle_invd,
a7052897 6919 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6920 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6921 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6922 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6923 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6924 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6925 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6926 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6927 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6928 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6929 [EXIT_REASON_VMOFF] = handle_vmoff,
6930 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6931 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6932 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6933 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6934 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6935 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6936 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6937 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6938 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6939 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6940 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6941 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6942 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6943 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6944 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 6945 [EXIT_REASON_INVVPID] = handle_invvpid,
6aa8b732
AK		 6946};
6947
6948static const int kvm_vmx_max_exit_handlers =
50a3485c 6949 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6950
908a7bdd
JK		 6951static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6952 struct vmcs12 *vmcs12)
6953{
6954 unsigned long exit_qualification;
6955 gpa_t bitmap, last_bitmap;
6956 unsigned int port;
6957 int size;
6958 u8 b;
6959
908a7bdd 6960 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6961 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6962
6963 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6964
6965 port = exit_qualification >> 16;
6966 size = (exit_qualification & 7) + 1;
6967
6968 last_bitmap = (gpa_t)-1;
6969 b = -1;
6970
6971 while (size > 0) {
6972 if (port < 0x8000)
6973 bitmap = vmcs12->io_bitmap_a;
6974 else if (port < 0x10000)
6975 bitmap = vmcs12->io_bitmap_b;
6976 else
6977 return 1;
6978 bitmap += (port & 0x7fff) / 8;
6979
6980 if (last_bitmap != bitmap)
6981 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6982 return 1;
6983 if (b & (1 << (port & 7)))
6984 return 1;
6985
6986 port++;
6987 size--;
6988 last_bitmap = bitmap;
6989 }
6990
6991 return 0;
6992}
6993
644d711a
NHE		 6994/*
6995 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6996 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6997 * disinterest in the current event (read or write a specific MSR) by using an
6998 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6999 */
7000static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7001 struct vmcs12 *vmcs12, u32 exit_reason)
7002{
7003 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7004 gpa_t bitmap;
7005
cbd29cb6 7006 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7007 return 1;
7008
7009 /*
7010 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7011 * for the four combinations of read/write and low/high MSR numbers.
7012 * First we need to figure out which of the four to use:
7013 */
7014 bitmap = vmcs12->msr_bitmap;
7015 if (exit_reason == EXIT_REASON_MSR_WRITE)
7016 bitmap += 2048;
7017 if (msr_index >= 0xc0000000) {
7018 msr_index -= 0xc0000000;
7019 bitmap += 1024;
7020 }
7021
7022 /* Then read the msr_index'th bit from this bitmap: */
7023 if (msr_index < 1024*8) {
7024 unsigned char b;
bd31a7f5
JK		 7025 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7026 return 1;
644d711a
NHE		 7027 return 1 & (b >> (msr_index & 7));
7028 } else
7029 return 1; /* let L1 handle the wrong parameter */
7030}
7031
7032/*
7033 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7034 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7035 * intercept (via guest_host_mask etc.) the current event.
7036 */
7037static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7038 struct vmcs12 *vmcs12)
7039{
7040 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7041 int cr = exit_qualification & 15;
7042 int reg = (exit_qualification >> 8) & 15;
1e32c079 7043 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7044
7045 switch ((exit_qualification >> 4) & 3) {
7046 case 0: /* mov to cr */
7047 switch (cr) {
7048 case 0:
7049 if (vmcs12->cr0_guest_host_mask &
7050 (val ^ vmcs12->cr0_read_shadow))
7051 return 1;
7052 break;
7053 case 3:
7054 if ((vmcs12->cr3_target_count >= 1 &&
7055 vmcs12->cr3_target_value0 == val) ||
7056 (vmcs12->cr3_target_count >= 2 &&
7057 vmcs12->cr3_target_value1 == val) ||
7058 (vmcs12->cr3_target_count >= 3 &&
7059 vmcs12->cr3_target_value2 == val) ||
7060 (vmcs12->cr3_target_count >= 4 &&
7061 vmcs12->cr3_target_value3 == val))
7062 return 0;
7063 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7064 return 1;
7065 break;
7066 case 4:
7067 if (vmcs12->cr4_guest_host_mask &
7068 (vmcs12->cr4_read_shadow ^ val))
7069 return 1;
7070 break;
7071 case 8:
7072 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7073 return 1;
7074 break;
7075 }
7076 break;
7077 case 2: /* clts */
7078 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7079 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7080 return 1;
7081 break;
7082 case 1: /* mov from cr */
7083 switch (cr) {
7084 case 3:
7085 if (vmcs12->cpu_based_vm_exec_control &
7086 CPU_BASED_CR3_STORE_EXITING)
7087 return 1;
7088 break;
7089 case 8:
7090 if (vmcs12->cpu_based_vm_exec_control &
7091 CPU_BASED_CR8_STORE_EXITING)
7092 return 1;
7093 break;
7094 }
7095 break;
7096 case 3: /* lmsw */
7097 /*
7098 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7099 * cr0. Other attempted changes are ignored, with no exit.
7100 */
7101 if (vmcs12->cr0_guest_host_mask & 0xe &
7102 (val ^ vmcs12->cr0_read_shadow))
7103 return 1;
7104 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7105 !(vmcs12->cr0_read_shadow & 0x1) &&
7106 (val & 0x1))
7107 return 1;
7108 break;
7109 }
7110 return 0;
7111}
7112
7113/*
7114 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7115 * should handle it ourselves in L0 (and then continue L2). Only call this
7116 * when in is_guest_mode (L2).
7117 */
7118static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7119{
644d711a
NHE		 7120 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7121 struct vcpu_vmx *vmx = to_vmx(vcpu);
7122 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7123 u32 exit_reason = vmx->exit_reason;
644d711a 7124
542060ea
JK		 7125 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7126 vmcs_readl(EXIT_QUALIFICATION),
7127 vmx->idt_vectoring_info,
7128 intr_info,
7129 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7130 KVM_ISA_VMX);
7131
644d711a
NHE		 7132 if (vmx->nested.nested_run_pending)
7133 return 0;
7134
7135 if (unlikely(vmx->fail)) {
bd80158a
JK		 7136 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7137 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7138 return 1;
7139 }
7140
7141 switch (exit_reason) {
7142 case EXIT_REASON_EXCEPTION_NMI:
7143 if (!is_exception(intr_info))
7144 return 0;
7145 else if (is_page_fault(intr_info))
7146 return enable_ept;
e504c909 7147 else if (is_no_device(intr_info) &&
ccf9844e 7148 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7149 return 0;
644d711a
NHE		 7150 return vmcs12->exception_bitmap &
7151 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7152 case EXIT_REASON_EXTERNAL_INTERRUPT:
7153 return 0;
7154 case EXIT_REASON_TRIPLE_FAULT:
7155 return 1;
7156 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7157 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7158 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7159 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7160 case EXIT_REASON_TASK_SWITCH:
7161 return 1;
7162 case EXIT_REASON_CPUID:
bc613494
MT		 7163 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7164 return 0;
644d711a
NHE		 7165 return 1;
7166 case EXIT_REASON_HLT:
7167 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7168 case EXIT_REASON_INVD:
7169 return 1;
7170 case EXIT_REASON_INVLPG:
7171 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7172 case EXIT_REASON_RDPMC:
7173 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7174 case EXIT_REASON_RDTSC:
7175 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7176 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7177 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7178 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7179 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7180 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7181 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7182 /*
7183 * VMX instructions trap unconditionally. This allows L1 to
7184 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7185 */
7186 return 1;
7187 case EXIT_REASON_CR_ACCESS:
7188 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7189 case EXIT_REASON_DR_ACCESS:
7190 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7191 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7192 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7193 case EXIT_REASON_MSR_READ:
7194 case EXIT_REASON_MSR_WRITE:
7195 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7196 case EXIT_REASON_INVALID_STATE:
7197 return 1;
7198 case EXIT_REASON_MWAIT_INSTRUCTION:
7199 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7200 case EXIT_REASON_MONITOR_INSTRUCTION:
7201 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7202 case EXIT_REASON_PAUSE_INSTRUCTION:
7203 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7204 nested_cpu_has2(vmcs12,
7205 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7206 case EXIT_REASON_MCE_DURING_VMENTRY:
7207 return 0;
7208 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7209 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7210 case EXIT_REASON_APIC_ACCESS:
7211 return nested_cpu_has2(vmcs12,
7212 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7213 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7214 /*
7215 * L0 always deals with the EPT violation. If nested EPT is
7216 * used, and the nested mmu code discovers that the address is
7217 * missing in the guest EPT table (EPT12), the EPT violation
7218 * will be injected with nested_ept_inject_page_fault()
7219 */
7220 return 0;
644d711a 7221 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7222 /*
7223 * L2 never uses directly L1's EPT, but rather L0's own EPT
7224 * table (shadow on EPT) or a merged EPT table that L0 built
7225 * (EPT on EPT). So any problems with the structure of the
7226 * table is L0's fault.
7227 */
644d711a
NHE		 7228 return 0;
7229 case EXIT_REASON_WBINVD:
7230 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7231 case EXIT_REASON_XSETBV:
7232 return 1;
7233 default:
7234 return 1;
7235 }
7236}
7237
586f9607
AK		 7238static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7239{
7240 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7241 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7242}
7243
6aa8b732
AK		 7244/*
7245 * The guest has exited. See if we can fix it or if we need userspace
7246 * assistance.
7247 */
851ba692 7248static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7249{
29bd8a78 7250 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7251 u32 exit_reason = vmx->exit_reason;
1155f76a 7252 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7253
80ced186 7254 /* If guest state is invalid, start emulating */
14168786 7255 if (vmx->emulation_required)
80ced186 7256 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7257
644d711a 7258 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7259 nested_vmx_vmexit(vcpu, exit_reason,
7260 vmcs_read32(VM_EXIT_INTR_INFO),
7261 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7262 return 1;
7263 }
7264
5120702e
MG		 7265 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7266 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7267 vcpu->run->fail_entry.hardware_entry_failure_reason
7268 = exit_reason;
7269 return 0;
7270 }
7271
29bd8a78 7272 if (unlikely(vmx->fail)) {
851ba692
AK		 7273 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7274 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7275 = vmcs_read32(VM_INSTRUCTION_ERROR);
7276 return 0;
7277 }
6aa8b732 7278
b9bf6882
XG		 7279 /*
7280 * Note:
7281 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7282 * delivery event since it indicates guest is accessing MMIO.
7283 * The vm-exit can be triggered again after return to guest that
7284 * will cause infinite loop.
7285 */
d77c26fc 7286 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7287 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7288 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7289 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7290 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7291 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7292 vcpu->run->internal.ndata = 2;
7293 vcpu->run->internal.data[0] = vectoring_info;
7294 vcpu->run->internal.data[1] = exit_reason;
7295 return 0;
7296 }
3b86cd99 7297
644d711a
NHE		 7298 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7299 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7300 get_vmcs12(vcpu))))) {
c4282df9 7301 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7302 vmx->soft_vnmi_blocked = 0;
3b86cd99 7303 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7304 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7305 /*
7306 * This CPU don't support us in finding the end of an
7307 * NMI-blocked window if the guest runs with IRQs
7308 * disabled. So we pull the trigger after 1 s of
7309 * futile waiting, but inform the user about this.
7310 */
7311 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7312 "state on VCPU %d after 1 s timeout\n",
7313 __func__, vcpu->vcpu_id);
7314 vmx->soft_vnmi_blocked = 0;
3b86cd99 7315 }
3b86cd99
JK		 7316 }
7317
6aa8b732
AK		 7318 if (exit_reason < kvm_vmx_max_exit_handlers
7319 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7320 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7321 else {
2bc19dc3
MT		 7322 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7323 kvm_queue_exception(vcpu, UD_VECTOR);
7324 return 1;
6aa8b732 7325 }
6aa8b732
AK		 7326}
7327
95ba8273 7328static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7329{
a7c0b07d
WL		 7330 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7331
7332 if (is_guest_mode(vcpu) &&
7333 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7334 return;
7335
95ba8273 7336 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7337 vmcs_write32(TPR_THRESHOLD, 0);
7338 return;
7339 }
7340
95ba8273 7341 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7342}
7343
8d14695f
YZ		 7344static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7345{
7346 u32 sec_exec_control;
7347
7348 /*
7349 * There is not point to enable virtualize x2apic without enable
7350 * apicv
7351 */
c7c9c56c
YZ		 7352 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7353 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7354 return;
7355
7356 if (!vm_need_tpr_shadow(vcpu->kvm))
7357 return;
7358
7359 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7360
7361 if (set) {
7362 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7363 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7364 } else {
7365 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7366 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7367 }
7368 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7369
7370 vmx_set_msr_bitmap(vcpu);
7371}
7372
38b99173
TC		 7373static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7374{
7375 struct vcpu_vmx *vmx = to_vmx(vcpu);
7376
7377 /*
7378 * Currently we do not handle the nested case where L2 has an
7379 * APIC access page of its own; that page is still pinned.
7380 * Hence, we skip the case where the VCPU is in guest mode _and_
7381 * L1 prepared an APIC access page for L2.
7382 *
7383 * For the case where L1 and L2 share the same APIC access page
7384 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7385 * in the vmcs12), this function will only update either the vmcs01
7386 * or the vmcs02. If the former, the vmcs02 will be updated by
7387 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7388 * the next L2->L1 exit.
7389 */
7390 if (!is_guest_mode(vcpu) ||
7391 !nested_cpu_has2(vmx->nested.current_vmcs12,
7392 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7393 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7394}
7395
c7c9c56c
YZ		 7396static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7397{
7398 u16 status;
7399 u8 old;
7400
7401 if (!vmx_vm_has_apicv(kvm))
7402 return;
7403
7404 if (isr == -1)
7405 isr = 0;
7406
7407 status = vmcs_read16(GUEST_INTR_STATUS);
7408 old = status >> 8;
7409 if (isr != old) {
7410 status &= 0xff;
7411 status |= isr << 8;
7412 vmcs_write16(GUEST_INTR_STATUS, status);
7413 }
7414}
7415
7416static void vmx_set_rvi(int vector)
7417{
7418 u16 status;
7419 u8 old;
7420
4114c27d
WW		 7421 if (vector == -1)
7422 vector = 0;
7423
c7c9c56c
YZ		 7424 status = vmcs_read16(GUEST_INTR_STATUS);
7425 old = (u8)status & 0xff;
7426 if ((u8)vector != old) {
7427 status &= ~0xff;
7428 status |= (u8)vector;
7429 vmcs_write16(GUEST_INTR_STATUS, status);
7430 }
7431}
7432
7433static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7434{
4114c27d
WW		 7435 if (!is_guest_mode(vcpu)) {
7436 vmx_set_rvi(max_irr);
7437 return;
7438 }
7439
c7c9c56c
YZ		 7440 if (max_irr == -1)
7441 return;
7442
963fee16 7443 /*
4114c27d
WW		 7444 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7445 * handles it.
963fee16 7446 */
4114c27d 7447 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7448 return;
7449
963fee16 7450 /*
4114c27d 7451 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7452 * is run without virtual interrupt delivery.
7453 */
7454 if (!kvm_event_needs_reinjection(vcpu) &&
7455 vmx_interrupt_allowed(vcpu)) {
7456 kvm_queue_interrupt(vcpu, max_irr, false);
7457 vmx_inject_irq(vcpu);
7458 }
c7c9c56c
YZ		 7459}
7460
7461static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7462{
3d81bc7e
YZ		 7463 if (!vmx_vm_has_apicv(vcpu->kvm))
7464 return;
7465
c7c9c56c
YZ		 7466 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7467 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7468 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7469 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7470}
7471
51aa01d1 7472static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7473{
00eba012
AK		 7474 u32 exit_intr_info;
7475
7476 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7477 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7478 return;
7479
c5ca8e57 7480 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7481 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7482
7483 /* Handle machine checks before interrupts are enabled */
00eba012 7484 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7485 kvm_machine_check();
7486
20f65983 7487 /* We need to handle NMIs before interrupts are enabled */
00eba012 7488 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7489 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7490 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7491 asm("int $2");
ff9d07a0
ZY		 7492 kvm_after_handle_nmi(&vmx->vcpu);
7493 }
51aa01d1 7494}
20f65983 7495
a547c6db
YZ		 7496static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7497{
7498 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7499
7500 /*
7501 * If external interrupt exists, IF bit is set in rflags/eflags on the
7502 * interrupt stack frame, and interrupt will be enabled on a return
7503 * from interrupt handler.
7504 */
7505 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7506 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7507 unsigned int vector;
7508 unsigned long entry;
7509 gate_desc *desc;
7510 struct vcpu_vmx *vmx = to_vmx(vcpu);
7511#ifdef CONFIG_X86_64
7512 unsigned long tmp;
7513#endif
7514
7515 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7516 desc = (gate_desc *)vmx->host_idt_base + vector;
7517 entry = gate_offset(*desc);
7518 asm volatile(
7519#ifdef CONFIG_X86_64
7520 "mov %%" _ASM_SP ", %[sp]\n\t"
7521 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7522 "push $%c[ss]\n\t"
7523 "push %[sp]\n\t"
7524#endif
7525 "pushf\n\t"
7526 "orl $0x200, (%%" _ASM_SP ")\n\t"
7527 __ASM_SIZE(push) " $%c[cs]\n\t"
7528 "call *%[entry]\n\t"
7529 :
7530#ifdef CONFIG_X86_64
7531 [sp]"=&r"(tmp)
7532#endif
7533 :
7534 [entry]"r"(entry),
7535 [ss]"i"(__KERNEL_DS),
7536 [cs]"i"(__KERNEL_CS)
7537 );
7538 } else
7539 local_irq_enable();
7540}
7541
da8999d3
LJ		 7542static bool vmx_mpx_supported(void)
7543{
7544 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7545 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7546}
7547
51aa01d1
AK		 7548static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7549{
c5ca8e57 7550 u32 exit_intr_info;
51aa01d1
AK		 7551 bool unblock_nmi;
7552 u8 vector;
7553 bool idtv_info_valid;
7554
7555 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7556
cf393f75 7557 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7558 if (vmx->nmi_known_unmasked)
7559 return;
c5ca8e57
AK		 7560 /*
7561 * Can't use vmx->exit_intr_info since we're not sure what
7562 * the exit reason is.
7563 */
7564 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7565 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7566 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7567 /*
7b4a25cb 7568 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7569 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7570 * a guest IRET fault.
7b4a25cb
GN		 7571 * SDM 3: 23.2.2 (September 2008)
7572 * Bit 12 is undefined in any of the following cases:
7573 * If the VM exit sets the valid bit in the IDT-vectoring
7574 * information field.
7575 * If the VM exit is due to a double fault.
cf393f75 7576 */
7b4a25cb
GN		 7577 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7578 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7579 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7580 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7581 else
7582 vmx->nmi_known_unmasked =
7583 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7584 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7585 } else if (unlikely(vmx->soft_vnmi_blocked))
7586 vmx->vnmi_blocked_time +=
7587 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7588}
7589
3ab66e8a 7590static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7591 u32 idt_vectoring_info,
7592 int instr_len_field,
7593 int error_code_field)
51aa01d1 7594{
51aa01d1
AK		 7595 u8 vector;
7596 int type;
7597 bool idtv_info_valid;
7598
7599 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7600
3ab66e8a
JK		 7601 vcpu->arch.nmi_injected = false;
7602 kvm_clear_exception_queue(vcpu);
7603 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7604
7605 if (!idtv_info_valid)
7606 return;
7607
3ab66e8a 7608 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7609
668f612f
AK		 7610 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7611 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7612
64a7ec06 7613 switch (type) {
37b96e98 7614 case INTR_TYPE_NMI_INTR:
3ab66e8a 7615 vcpu->arch.nmi_injected = true;
668f612f 7616 /*
7b4a25cb 7617 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7618 * Clear bit "block by NMI" before VM entry if a NMI
7619 * delivery faulted.
668f612f 7620 */
3ab66e8a 7621 vmx_set_nmi_mask(vcpu, false);
37b96e98 7622 break;
37b96e98 7623 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7624 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7625 /* fall through */
7626 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7627 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7628 u32 err = vmcs_read32(error_code_field);
851eb667 7629 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7630 } else
851eb667 7631 kvm_requeue_exception(vcpu, vector);
37b96e98 7632 break;
66fd3f7f 7633 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7634 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7635 /* fall through */
37b96e98 7636 case INTR_TYPE_EXT_INTR:
3ab66e8a 7637 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7638 break;
7639 default:
7640 break;
f7d9238f 7641 }
cf393f75
AK		 7642}
7643
83422e17
AK		 7644static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7645{
3ab66e8a 7646 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7647 VM_EXIT_INSTRUCTION_LEN,
7648 IDT_VECTORING_ERROR_CODE);
7649}
7650
b463a6f7
AK		 7651static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7652{
3ab66e8a 7653 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7654 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7655 VM_ENTRY_INSTRUCTION_LEN,
7656 VM_ENTRY_EXCEPTION_ERROR_CODE);
7657
7658 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7659}
7660
d7cd9796
GN		 7661static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7662{
7663 int i, nr_msrs;
7664 struct perf_guest_switch_msr *msrs;
7665
7666 msrs = perf_guest_get_msrs(&nr_msrs);
7667
7668 if (!msrs)
7669 return;
7670
7671 for (i = 0; i < nr_msrs; i++)
7672 if (msrs[i].host == msrs[i].guest)
7673 clear_atomic_switch_msr(vmx, msrs[i].msr);
7674 else
7675 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7676 msrs[i].host);
7677}
7678
a3b5ba49 7679static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7680{
a2fa3e9f 7681 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7682 unsigned long debugctlmsr, cr4;
104f226b
AK		 7683
7684 /* Record the guest's net vcpu time for enforced NMI injections. */
7685 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7686 vmx->entry_time = ktime_get();
7687
7688 /* Don't enter VMX if guest state is invalid, let the exit handler
7689 start emulation until we arrive back to a valid state */
14168786 7690 if (vmx->emulation_required)
104f226b
AK		 7691 return;
7692
a7653ecd
RK		 7693 if (vmx->ple_window_dirty) {
7694 vmx->ple_window_dirty = false;
7695 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7696 }
7697
012f83cb
AG		 7698 if (vmx->nested.sync_shadow_vmcs) {
7699 copy_vmcs12_to_shadow(vmx);
7700 vmx->nested.sync_shadow_vmcs = false;
7701 }
7702
104f226b
AK		 7703 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7704 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7705 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7706 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7707
d974baa3
AL		 7708 cr4 = read_cr4();
7709 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
7710 vmcs_writel(HOST_CR4, cr4);
7711 vmx->host_state.vmcs_host_cr4 = cr4;
7712 }
7713
104f226b
AK		 7714 /* When single-stepping over STI and MOV SS, we must clear the
7715 * corresponding interruptibility bits in the guest state. Otherwise
7716 * vmentry fails as it then expects bit 14 (BS) in pending debug
7717 * exceptions being set, but that's not correct for the guest debugging
7718 * case. */
7719 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7720 vmx_set_interrupt_shadow(vcpu, 0);
7721
d7cd9796 7722 atomic_switch_perf_msrs(vmx);
2a7921b7 7723 debugctlmsr = get_debugctlmsr();
d7cd9796 7724
d462b819 7725 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7726 asm(
6aa8b732 7727 /* Store host registers */
b188c81f
AK		 7728 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7729 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7730 "push %%" _ASM_CX " \n\t"
7731 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7732 "je 1f \n\t"
b188c81f 7733 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7734 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7735 "1: \n\t"
d3edefc0 7736 /* Reload cr2 if changed */
b188c81f
AK		 7737 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7738 "mov %%cr2, %%" _ASM_DX " \n\t"
7739 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7740 "je 2f \n\t"
b188c81f 7741 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7742 "2: \n\t"
6aa8b732 7743 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7744 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7745 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7746 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7747 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7748 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7749 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7750 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7751 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7752#ifdef CONFIG_X86_64
e08aa78a
AK		 7753 "mov %c[r8](%0), %%r8 \n\t"
7754 "mov %c[r9](%0), %%r9 \n\t"
7755 "mov %c[r10](%0), %%r10 \n\t"
7756 "mov %c[r11](%0), %%r11 \n\t"
7757 "mov %c[r12](%0), %%r12 \n\t"
7758 "mov %c[r13](%0), %%r13 \n\t"
7759 "mov %c[r14](%0), %%r14 \n\t"
7760 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7761#endif
b188c81f 7762 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7763
6aa8b732 7764 /* Enter guest mode */
83287ea4 7765 "jne 1f \n\t"
4ecac3fd 7766 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7767 "jmp 2f \n\t"
7768 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7769 "2: "
6aa8b732 7770 /* Save guest registers, load host registers, keep flags */
b188c81f 7771 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7772 "pop %0 \n\t"
b188c81f
AK		 7773 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7774 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7775 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7776 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7777 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7778 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7779 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7780#ifdef CONFIG_X86_64
e08aa78a
AK		 7781 "mov %%r8, %c[r8](%0) \n\t"
7782 "mov %%r9, %c[r9](%0) \n\t"
7783 "mov %%r10, %c[r10](%0) \n\t"
7784 "mov %%r11, %c[r11](%0) \n\t"
7785 "mov %%r12, %c[r12](%0) \n\t"
7786 "mov %%r13, %c[r13](%0) \n\t"
7787 "mov %%r14, %c[r14](%0) \n\t"
7788 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7789#endif
b188c81f
AK		 7790 "mov %%cr2, %%" _ASM_AX " \n\t"
7791 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7792
b188c81f 7793 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7794 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7795 ".pushsection .rodata \n\t"
7796 ".global vmx_return \n\t"
7797 "vmx_return: " _ASM_PTR " 2b \n\t"
7798 ".popsection"
e08aa78a 7799 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7800 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7801 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7802 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7803 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7804 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7805 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7806 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7807 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7808 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7809 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7810#ifdef CONFIG_X86_64
ad312c7c
ZX		 7811 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7812 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7813 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7814 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7815 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7816 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7817 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7818 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7819#endif
40712fae
AK		 7820 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7821 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7822 : "cc", "memory"
7823#ifdef CONFIG_X86_64
b188c81f 7824 , "rax", "rbx", "rdi", "rsi"
c2036300 7825 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7826#else
7827 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7828#endif
7829 );
6aa8b732 7830
2a7921b7
GN		 7831 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7832 if (debugctlmsr)
7833 update_debugctlmsr(debugctlmsr);
7834
aa67f609
AK		 7835#ifndef CONFIG_X86_64
7836 /*
7837 * The sysexit path does not restore ds/es, so we must set them to
7838 * a reasonable value ourselves.
7839 *
7840 * We can't defer this to vmx_load_host_state() since that function
7841 * may be executed in interrupt context, which saves and restore segments
7842 * around it, nullifying its effect.
7843 */
7844 loadsegment(ds, __USER_DS);
7845 loadsegment(es, __USER_DS);
7846#endif
7847
6de4f3ad 7848 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7849 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7850 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7851 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7852 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7853 vcpu->arch.regs_dirty = 0;
7854
1155f76a
AK		 7855 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7856
d462b819 7857 vmx->loaded_vmcs->launched = 1;
1b6269db 7858
51aa01d1 7859 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7860 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7861
e0b890d3
GN		 7862 /*
7863 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7864 * we did not inject a still-pending event to L1 now because of
7865 * nested_run_pending, we need to re-enable this bit.
7866 */
7867 if (vmx->nested.nested_run_pending)
7868 kvm_make_request(KVM_REQ_EVENT, vcpu);
7869
7870 vmx->nested.nested_run_pending = 0;
7871
51aa01d1
AK		 7872 vmx_complete_atomic_exit(vmx);
7873 vmx_recover_nmi_blocking(vmx);
cf393f75 7874 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7875}
7876
4fa7734c
PB		 7877static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7878{
7879 struct vcpu_vmx *vmx = to_vmx(vcpu);
7880 int cpu;
7881
7882 if (vmx->loaded_vmcs == &vmx->vmcs01)
7883 return;
7884
7885 cpu = get_cpu();
7886 vmx->loaded_vmcs = &vmx->vmcs01;
7887 vmx_vcpu_put(vcpu);
7888 vmx_vcpu_load(vcpu, cpu);
7889 vcpu->cpu = cpu;
7890 put_cpu();
7891}
7892
6aa8b732
AK		 7893static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7894{
fb3f0f51
RR		 7895 struct vcpu_vmx *vmx = to_vmx(vcpu);
7896
cdbecfc3 7897 free_vpid(vmx);
4fa7734c
PB		 7898 leave_guest_mode(vcpu);
7899 vmx_load_vmcs01(vcpu);
26a865f4 7900 free_nested(vmx);
4fa7734c 7901 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7902 kfree(vmx->guest_msrs);
7903 kvm_vcpu_uninit(vcpu);
a4770347 7904 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7905}
7906
fb3f0f51 7907static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7908{
fb3f0f51 7909 int err;
c16f862d 7910 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7911 int cpu;
6aa8b732 7912
a2fa3e9f 7913 if (!vmx)
fb3f0f51
RR		 7914 return ERR_PTR(-ENOMEM);
7915
2384d2b3
SY		 7916 allocate_vpid(vmx);
7917
fb3f0f51
RR		 7918 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7919 if (err)
7920 goto free_vcpu;
965b58a5 7921
a2fa3e9f 7922 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7923 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7924 > PAGE_SIZE);
0123be42 7925
be6d05cf 7926 err = -ENOMEM;
fb3f0f51 7927 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7928 goto uninit_vcpu;
7929 }
965b58a5 7930
d462b819
NHE		 7931 vmx->loaded_vmcs = &vmx->vmcs01;
7932 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7933 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7934 goto free_msrs;
d462b819
NHE		 7935 if (!vmm_exclusive)
7936 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7937 loaded_vmcs_init(vmx->loaded_vmcs);
7938 if (!vmm_exclusive)
7939 kvm_cpu_vmxoff();
a2fa3e9f 7940
15ad7146
AK		 7941 cpu = get_cpu();
7942 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7943 vmx->vcpu.cpu = cpu;
8b9cf98c 7944 err = vmx_vcpu_setup(vmx);
fb3f0f51 7945 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7946 put_cpu();
fb3f0f51
RR		 7947 if (err)
7948 goto free_vmcs;
a63cb560 7949 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7950 err = alloc_apic_access_page(kvm);
7951 if (err)
5e4a0b3c 7952 goto free_vmcs;
a63cb560 7953 }
fb3f0f51 7954
b927a3ce
SY		 7955 if (enable_ept) {
7956 if (!kvm->arch.ept_identity_map_addr)
7957 kvm->arch.ept_identity_map_addr =
7958 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 7959 err = init_rmode_identity_map(kvm);
7960 if (err)
93ea5388 7961 goto free_vmcs;
b927a3ce 7962 }
b7ebfb05 7963
a9d30f33
NHE		 7964 vmx->nested.current_vmptr = -1ull;
7965 vmx->nested.current_vmcs12 = NULL;
7966
fb3f0f51
RR		 7967 return &vmx->vcpu;
7968
7969free_vmcs:
5f3fbc34 7970 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7971free_msrs:
fb3f0f51
RR		 7972 kfree(vmx->guest_msrs);
7973uninit_vcpu:
7974 kvm_vcpu_uninit(&vmx->vcpu);
7975free_vcpu:
cdbecfc3 7976 free_vpid(vmx);
a4770347 7977 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7978 return ERR_PTR(err);
6aa8b732
AK		 7979}
7980
002c7f7c
YS		 7981static void __init vmx_check_processor_compat(void *rtn)
7982{
7983 struct vmcs_config vmcs_conf;
7984
7985 *(int *)rtn = 0;
7986 if (setup_vmcs_config(&vmcs_conf) < 0)
7987 *(int *)rtn = -EIO;
7988 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7989 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7990 smp_processor_id());
7991 *(int *)rtn = -EIO;
7992 }
7993}
7994
67253af5
SY		 7995static int get_ept_level(void)
7996{
7997 return VMX_EPT_DEFAULT_GAW + 1;
7998}
7999
4b12f0de 8000static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8001{
4b12f0de
SY		 8002 u64 ret;
8003
522c68c4
SY		 8004 /* For VT-d and EPT combination
8005 * 1. MMIO: always map as UC
8006 * 2. EPT with VT-d:
8007 * a. VT-d without snooping control feature: can't guarantee the
8008 * result, try to trust guest.
8009 * b. VT-d with snooping control feature: snooping control feature of
8010 * VT-d engine can guarantee the cache correctness. Just set it
8011 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8012 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8013 * consistent with host MTRR
8014 */
4b12f0de
SY		 8015 if (is_mmio)
8016 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8017 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8018 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8019 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8020 else
522c68c4 8021 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8022 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8023
8024 return ret;
64d4d521
SY		 8025}
8026
17cc3935 8027static int vmx_get_lpage_level(void)
344f414f 8028{
878403b7
SY		 8029 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8030 return PT_DIRECTORY_LEVEL;
8031 else
8032 /* For shadow and EPT supported 1GB page */
8033 return PT_PDPE_LEVEL;
344f414f
JR		 8034}
8035
0e851880
SY		 8036static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8037{
4e47c7a6
SY		 8038 struct kvm_cpuid_entry2 *best;
8039 struct vcpu_vmx *vmx = to_vmx(vcpu);
8040 u32 exec_control;
8041
8042 vmx->rdtscp_enabled = false;
8043 if (vmx_rdtscp_supported()) {
8044 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8045 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8046 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8047 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8048 vmx->rdtscp_enabled = true;
8049 else {
8050 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8051 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8052 exec_control);
8053 }
8054 }
8055 }
ad756a16 8056
ad756a16
MJ		 8057 /* Exposing INVPCID only when PCID is exposed */
8058 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8059 if (vmx_invpcid_supported() &&
4f977045 8060 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8061 guest_cpuid_has_pcid(vcpu)) {
29282fde 8062 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8063 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8064 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8065 exec_control);
8066 } else {
29282fde
TI		 8067 if (cpu_has_secondary_exec_ctrls()) {
8068 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8069 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8070 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8071 exec_control);
8072 }
ad756a16 8073 if (best)
4f977045 8074 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8075 }
0e851880
SY		 8076}
8077
d4330ef2
JR		 8078static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8079{
7b8050f5
NHE		 8080 if (func == 1 && nested)
8081 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8082}
8083
25d92081
YZ		 8084static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8085 struct x86_exception *fault)
8086{
533558bc
JK		 8087 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8088 u32 exit_reason;
25d92081
YZ		 8089
8090 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8091 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8092 else
533558bc
JK		 8093 exit_reason = EXIT_REASON_EPT_VIOLATION;
8094 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8095 vmcs12->guest_physical_address = fault->address;
8096}
8097
155a97a3
NHE		 8098/* Callbacks for nested_ept_init_mmu_context: */
8099
8100static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8101{
8102 /* return the page table to be shadowed - in our case, EPT12 */
8103 return get_vmcs12(vcpu)->ept_pointer;
8104}
8105
8a3c1a33 8106static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8107{
8a3c1a33 8108 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 8109 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
8110
8111 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8112 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8113 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8114
8115 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8116}
8117
8118static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8119{
8120 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8121}
8122
feaf0c7d
GN		 8123static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8124 struct x86_exception *fault)
8125{
8126 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8127
8128 WARN_ON(!is_guest_mode(vcpu));
8129
8130 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
8131 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 8132 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8133 vmcs_read32(VM_EXIT_INTR_INFO),
8134 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8135 else
8136 kvm_inject_page_fault(vcpu, fault);
8137}
8138
a2bcba50
WL		 8139static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8140 struct vmcs12 *vmcs12)
8141{
8142 struct vcpu_vmx *vmx = to_vmx(vcpu);
8143
8144 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8145 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8146 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8147 return false;
8148
8149 /*
8150 * Translate L1 physical address to host physical
8151 * address for vmcs02. Keep the page pinned, so this
8152 * physical address remains valid. We keep a reference
8153 * to it so we can release it later.
8154 */
8155 if (vmx->nested.apic_access_page) /* shouldn't happen */
8156 nested_release_page(vmx->nested.apic_access_page);
8157 vmx->nested.apic_access_page =
8158 nested_get_page(vcpu, vmcs12->apic_access_addr);
8159 }
a7c0b07d
WL		 8160
8161 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8162 /* TODO: Also verify bits beyond physical address width are 0 */
8163 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8164 return false;
8165
8166 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8167 nested_release_page(vmx->nested.virtual_apic_page);
8168 vmx->nested.virtual_apic_page =
8169 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8170
8171 /*
8172 * Failing the vm entry is _not_ what the processor does
8173 * but it's basically the only possibility we have.
8174 * We could still enter the guest if CR8 load exits are
8175 * enabled, CR8 store exits are enabled, and virtualize APIC
8176 * access is disabled; in this case the processor would never
8177 * use the TPR shadow and we could simply clear the bit from
8178 * the execution control. But such a configuration is useless,
8179 * so let's keep the code simple.
8180 */
8181 if (!vmx->nested.virtual_apic_page)
8182 return false;
8183 }
8184
a2bcba50
WL		 8185 return true;
8186}
8187
f4124500
JK		 8188static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8189{
8190 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8191 struct vcpu_vmx *vmx = to_vmx(vcpu);
8192
8193 if (vcpu->arch.virtual_tsc_khz == 0)
8194 return;
8195
8196 /* Make sure short timeouts reliably trigger an immediate vmexit.
8197 * hrtimer_start does not guarantee this. */
8198 if (preemption_timeout <= 1) {
8199 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8200 return;
8201 }
8202
8203 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8204 preemption_timeout *= 1000000;
8205 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8206 hrtimer_start(&vmx->nested.preemption_timer,
8207 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8208}
8209
fe3ef05c
NHE		 8210/*
8211 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8212 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8213 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8214 * guest in a way that will both be appropriate to L1's requests, and our
8215 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8216 * function also has additional necessary side-effects, like setting various
8217 * vcpu->arch fields.
8218 */
8219static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8220{
8221 struct vcpu_vmx *vmx = to_vmx(vcpu);
8222 u32 exec_control;
8223
8224 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8225 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8226 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8227 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8228 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8229 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8230 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8231 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8232 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8233 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8234 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8235 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8236 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8237 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8238 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8239 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8240 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8241 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8242 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8243 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8244 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8245 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8246 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8247 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8248 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8249 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8250 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8251 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8252 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8253 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8254 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8255 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8256 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8257 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8258 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8259 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8260
2996fca0
JK		 8261 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8262 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8263 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8264 } else {
8265 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8266 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8267 }
fe3ef05c
NHE		 8268 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8269 vmcs12->vm_entry_intr_info_field);
8270 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8271 vmcs12->vm_entry_exception_error_code);
8272 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8273 vmcs12->vm_entry_instruction_len);
8274 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8275 vmcs12->guest_interruptibility_info);
fe3ef05c 8276 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8277 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8278 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8279 vmcs12->guest_pending_dbg_exceptions);
8280 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8281 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8282
8283 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8284
f4124500
JK		 8285 exec_control = vmcs12->pin_based_vm_exec_control;
8286 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8287 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8288 PIN_BASED_POSTED_INTR);
f4124500 8289 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8290
f4124500
JK		 8291 vmx->nested.preemption_timer_expired = false;
8292 if (nested_cpu_has_preemption_timer(vmcs12))
8293 vmx_start_preemption_timer(vcpu);
0238ea91 8294
fe3ef05c
NHE		 8295 /*
8296 * Whether page-faults are trapped is determined by a combination of
8297 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8298 * If enable_ept, L0 doesn't care about page faults and we should
8299 * set all of these to L1's desires. However, if !enable_ept, L0 does
8300 * care about (at least some) page faults, and because it is not easy
8301 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8302 * to exit on each and every L2 page fault. This is done by setting
8303 * MASK=MATCH=0 and (see below) EB.PF=1.
8304 * Note that below we don't need special code to set EB.PF beyond the
8305 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8306 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8307 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8308 *
8309 * A problem with this approach (when !enable_ept) is that L1 may be
8310 * injected with more page faults than it asked for. This could have
8311 * caused problems, but in practice existing hypervisors don't care.
8312 * To fix this, we will need to emulate the PFEC checking (on the L1
8313 * page tables), using walk_addr(), when injecting PFs to L1.
8314 */
8315 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8316 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8317 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8318 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8319
8320 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8321 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8322 if (!vmx->rdtscp_enabled)
8323 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8324 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8325 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8326 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8327 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8328 if (nested_cpu_has(vmcs12,
8329 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8330 exec_control |= vmcs12->secondary_vm_exec_control;
8331
8332 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8333 /*
8334 * If translation failed, no matter: This feature asks
8335 * to exit when accessing the given address, and if it
8336 * can never be accessed, this feature won't do
8337 * anything anyway.
8338 */
8339 if (!vmx->nested.apic_access_page)
8340 exec_control &=
8341 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8342 else
8343 vmcs_write64(APIC_ACCESS_ADDR,
8344 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8345 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8346 exec_control |=
8347 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8348 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8349 }
8350
8351 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8352 }
8353
8354
8355 /*
8356 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8357 * Some constant fields are set here by vmx_set_constant_host_state().
8358 * Other fields are different per CPU, and will be set later when
8359 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8360 */
a547c6db 8361 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8362
8363 /*
8364 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8365 * entry, but only if the current (host) sp changed from the value
8366 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8367 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8368 * here we just force the write to happen on entry.
8369 */
8370 vmx->host_rsp = 0;
8371
8372 exec_control = vmx_exec_control(vmx); /* L0's desires */
8373 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8374 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8375 exec_control &= ~CPU_BASED_TPR_SHADOW;
8376 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8377
8378 if (exec_control & CPU_BASED_TPR_SHADOW) {
8379 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8380 page_to_phys(vmx->nested.virtual_apic_page));
8381 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8382 }
8383
fe3ef05c
NHE		 8384 /*
8385 * Merging of IO and MSR bitmaps not currently supported.
8386 * Rather, exit every time.
8387 */
8388 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8389 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8390 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8391
8392 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8393
8394 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8395 * bitwise-or of what L1 wants to trap for L2, and what we want to
8396 * trap. Note that CR0.TS also needs updating - we do this later.
8397 */
8398 update_exception_bitmap(vcpu);
8399 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8400 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8401
8049d651
NHE		 8402 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8403 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8404 * bits are further modified by vmx_set_efer() below.
8405 */
f4124500 8406 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8407
8408 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8409 * emulated by vmx_set_efer(), below.
8410 */
2961e876 8411 vm_entry_controls_init(vmx,
8049d651
NHE		 8412 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8413 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8414 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8415
44811c02 8416 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8417 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8418 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8419 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8420 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8421
8422
8423 set_cr4_guest_host_mask(vmx);
8424
36be0b9d
PB		 8425 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8426 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8427
27fc51b2
NHE		 8428 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8429 vmcs_write64(TSC_OFFSET,
8430 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8431 else
8432 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8433
8434 if (enable_vpid) {
8435 /*
8436 * Trivially support vpid by letting L2s share their parent
8437 * L1's vpid. TODO: move to a more elaborate solution, giving
8438 * each L2 its own vpid and exposing the vpid feature to L1.
8439 */
8440 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8441 vmx_flush_tlb(vcpu);
8442 }
8443
155a97a3
NHE		 8444 if (nested_cpu_has_ept(vmcs12)) {
8445 kvm_mmu_unload(vcpu);
8446 nested_ept_init_mmu_context(vcpu);
8447 }
8448
fe3ef05c
NHE		 8449 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8450 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8451 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8452 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8453 else
8454 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8455 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8456 vmx_set_efer(vcpu, vcpu->arch.efer);
8457
8458 /*
8459 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8460 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8461 * The CR0_READ_SHADOW is what L2 should have expected to read given
8462 * the specifications by L1; It's not enough to take
8463 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8464 * have more bits than L1 expected.
8465 */
8466 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8467 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8468
8469 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8470 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8471
8472 /* shadow page tables on either EPT or shadow page tables */
8473 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8474 kvm_mmu_reset_context(vcpu);
8475
feaf0c7d
GN		 8476 if (!enable_ept)
8477 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8478
3633cfc3
NHE		 8479 /*
8480 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8481 */
8482 if (enable_ept) {
8483 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8484 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8485 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8486 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8487 }
8488
fe3ef05c
NHE		 8489 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8490 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8491}
8492
cd232ad0
NHE		 8493/*
8494 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8495 * for running an L2 nested guest.
8496 */
8497static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8498{
8499 struct vmcs12 *vmcs12;
8500 struct vcpu_vmx *vmx = to_vmx(vcpu);
8501 int cpu;
8502 struct loaded_vmcs *vmcs02;
384bb783 8503 bool ia32e;
cd232ad0
NHE		 8504
8505 if (!nested_vmx_check_permission(vcpu) ||
8506 !nested_vmx_check_vmcs12(vcpu))
8507 return 1;
8508
8509 skip_emulated_instruction(vcpu);
8510 vmcs12 = get_vmcs12(vcpu);
8511
012f83cb
AG		 8512 if (enable_shadow_vmcs)
8513 copy_shadow_to_vmcs12(vmx);
8514
7c177938
NHE		 8515 /*
8516 * The nested entry process starts with enforcing various prerequisites
8517 * on vmcs12 as required by the Intel SDM, and act appropriately when
8518 * they fail: As the SDM explains, some conditions should cause the
8519 * instruction to fail, while others will cause the instruction to seem
8520 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8521 * To speed up the normal (success) code path, we should avoid checking
8522 * for misconfigurations which will anyway be caught by the processor
8523 * when using the merged vmcs02.
8524 */
8525 if (vmcs12->launch_state == launch) {
8526 nested_vmx_failValid(vcpu,
8527 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8528 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8529 return 1;
8530 }
8531
6dfacadd
JK		 8532 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8533 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8534 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8535 return 1;
8536 }
8537
7c177938 8538 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8539 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8540 /*TODO: Also verify bits beyond physical address width are 0*/
8541 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8542 return 1;
8543 }
8544
a2bcba50 8545 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 8546 /*TODO: Also verify bits beyond physical address width are 0*/
8547 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8548 return 1;
8549 }
8550
8551 if (vmcs12->vm_entry_msr_load_count > 0 ||
8552 vmcs12->vm_exit_msr_load_count > 0 ||
8553 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8554 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8555 __func__);
7c177938
NHE		 8556 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8557 return 1;
8558 }
8559
8560 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8561 nested_vmx_true_procbased_ctls_low,
8562 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8563 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8564 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8565 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8566 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8567 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8568 nested_vmx_true_exit_ctls_low,
8569 nested_vmx_exit_ctls_high) ||
7c177938 8570 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8571 nested_vmx_true_entry_ctls_low,
8572 nested_vmx_entry_ctls_high))
7c177938
NHE		 8573 {
8574 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8575 return 1;
8576 }
8577
8578 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8579 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8580 nested_vmx_failValid(vcpu,
8581 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8582 return 1;
8583 }
8584
92fbc7b1 8585 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8586 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8587 nested_vmx_entry_failure(vcpu, vmcs12,
8588 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8589 return 1;
8590 }
8591 if (vmcs12->vmcs_link_pointer != -1ull) {
8592 nested_vmx_entry_failure(vcpu, vmcs12,
8593 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8594 return 1;
8595 }
8596
384bb783 8597 /*
cb0c8cda 8598 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8599 * are performed on the field for the IA32_EFER MSR:
8600 * - Bits reserved in the IA32_EFER MSR must be 0.
8601 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8602 * the IA-32e mode guest VM-exit control. It must also be identical
8603 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8604 * CR0.PG) is 1.
8605 */
8606 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8607 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8608 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8609 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8610 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8611 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8612 nested_vmx_entry_failure(vcpu, vmcs12,
8613 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8614 return 1;
8615 }
8616 }
8617
8618 /*
8619 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8620 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8621 * the values of the LMA and LME bits in the field must each be that of
8622 * the host address-space size VM-exit control.
8623 */
8624 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8625 ia32e = (vmcs12->vm_exit_controls &
8626 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8627 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8628 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8629 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8630 nested_vmx_entry_failure(vcpu, vmcs12,
8631 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8632 return 1;
8633 }
8634 }
8635
7c177938
NHE		 8636 /*
8637 * We're finally done with prerequisite checking, and can start with
8638 * the nested entry.
8639 */
8640
cd232ad0
NHE		 8641 vmcs02 = nested_get_current_vmcs02(vmx);
8642 if (!vmcs02)
8643 return -ENOMEM;
8644
8645 enter_guest_mode(vcpu);
8646
8647 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8648
2996fca0
JK		 8649 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8650 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8651
cd232ad0
NHE		 8652 cpu = get_cpu();
8653 vmx->loaded_vmcs = vmcs02;
8654 vmx_vcpu_put(vcpu);
8655 vmx_vcpu_load(vcpu, cpu);
8656 vcpu->cpu = cpu;
8657 put_cpu();
8658
36c3cc42
JK		 8659 vmx_segment_cache_clear(vmx);
8660
cd232ad0
NHE		 8661 vmcs12->launch_state = 1;
8662
8663 prepare_vmcs02(vcpu, vmcs12);
8664
6dfacadd
JK		 8665 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8666 return kvm_emulate_halt(vcpu);
8667
7af40ad3
JK		 8668 vmx->nested.nested_run_pending = 1;
8669
cd232ad0
NHE		 8670 /*
8671 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8672 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8673 * returned as far as L1 is concerned. It will only return (and set
8674 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8675 */
8676 return 1;
8677}
8678
4704d0be
NHE		 8679/*
8680 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8681 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8682 * This function returns the new value we should put in vmcs12.guest_cr0.
8683 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8684 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8685 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8686 * didn't trap the bit, because if L1 did, so would L0).
8687 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8688 * been modified by L2, and L1 knows it. So just leave the old value of
8689 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8690 * isn't relevant, because if L0 traps this bit it can set it to anything.
8691 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8692 * changed these bits, and therefore they need to be updated, but L0
8693 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8694 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8695 */
8696static inline unsigned long
8697vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8698{
8699 return
8700 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8701 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8702 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8703 vcpu->arch.cr0_guest_owned_bits));
8704}
8705
8706static inline unsigned long
8707vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8708{
8709 return
8710 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8711 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8712 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8713 vcpu->arch.cr4_guest_owned_bits));
8714}
8715
5f3d5799
JK		 8716static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8717 struct vmcs12 *vmcs12)
8718{
8719 u32 idt_vectoring;
8720 unsigned int nr;
8721
851eb667 8722 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8723 nr = vcpu->arch.exception.nr;
8724 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8725
8726 if (kvm_exception_is_soft(nr)) {
8727 vmcs12->vm_exit_instruction_len =
8728 vcpu->arch.event_exit_inst_len;
8729 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8730 } else
8731 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8732
8733 if (vcpu->arch.exception.has_error_code) {
8734 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8735 vmcs12->idt_vectoring_error_code =
8736 vcpu->arch.exception.error_code;
8737 }
8738
8739 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8740 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8741 vmcs12->idt_vectoring_info_field =
8742 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8743 } else if (vcpu->arch.interrupt.pending) {
8744 nr = vcpu->arch.interrupt.nr;
8745 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8746
8747 if (vcpu->arch.interrupt.soft) {
8748 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8749 vmcs12->vm_entry_instruction_len =
8750 vcpu->arch.event_exit_inst_len;
8751 } else
8752 idt_vectoring |= INTR_TYPE_EXT_INTR;
8753
8754 vmcs12->idt_vectoring_info_field = idt_vectoring;
8755 }
8756}
8757
b6b8a145
JK		 8758static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8759{
8760 struct vcpu_vmx *vmx = to_vmx(vcpu);
8761
f4124500
JK		 8762 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8763 vmx->nested.preemption_timer_expired) {
8764 if (vmx->nested.nested_run_pending)
8765 return -EBUSY;
8766 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8767 return 0;
8768 }
8769
b6b8a145 8770 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8771 if (vmx->nested.nested_run_pending ||
8772 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8773 return -EBUSY;
8774 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8775 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8776 INTR_INFO_VALID_MASK, 0);
8777 /*
8778 * The NMI-triggered VM exit counts as injection:
8779 * clear this one and block further NMIs.
8780 */
8781 vcpu->arch.nmi_pending = 0;
8782 vmx_set_nmi_mask(vcpu, true);
8783 return 0;
8784 }
8785
8786 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8787 nested_exit_on_intr(vcpu)) {
8788 if (vmx->nested.nested_run_pending)
8789 return -EBUSY;
8790 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8791 }
8792
8793 return 0;
8794}
8795
f4124500
JK		 8796static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8797{
8798 ktime_t remaining =
8799 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8800 u64 value;
8801
8802 if (ktime_to_ns(remaining) <= 0)
8803 return 0;
8804
8805 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8806 do_div(value, 1000000);
8807 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8808}
8809
4704d0be
NHE		 8810/*
8811 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8812 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8813 * and this function updates it to reflect the changes to the guest state while
8814 * L2 was running (and perhaps made some exits which were handled directly by L0
8815 * without going back to L1), and to reflect the exit reason.
8816 * Note that we do not have to copy here all VMCS fields, just those that
8817 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8818 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8819 * which already writes to vmcs12 directly.
8820 */
533558bc
JK		 8821static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8822 u32 exit_reason, u32 exit_intr_info,
8823 unsigned long exit_qualification)
4704d0be
NHE		 8824{
8825 /* update guest state fields: */
8826 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8827 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8828
4704d0be
NHE		 8829 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8830 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8831 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8832
8833 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8834 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8835 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8836 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8837 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8838 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8839 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8840 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8841 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8842 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8843 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8844 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8845 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8846 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8847 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8848 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8849 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8850 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8851 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8852 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8853 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8854 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8855 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8856 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8857 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8858 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8859 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8860 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8861 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8862 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8863 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8864 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8865 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8866 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8867 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8868 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8869
4704d0be
NHE		 8870 vmcs12->guest_interruptibility_info =
8871 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8872 vmcs12->guest_pending_dbg_exceptions =
8873 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8874 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8875 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8876 else
8877 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8878
f4124500
JK		 8879 if (nested_cpu_has_preemption_timer(vmcs12)) {
8880 if (vmcs12->vm_exit_controls &
8881 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8882 vmcs12->vmx_preemption_timer_value =
8883 vmx_get_preemption_timer_value(vcpu);
8884 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8885 }
7854cbca 8886
3633cfc3
NHE		 8887 /*
8888 * In some cases (usually, nested EPT), L2 is allowed to change its
8889 * own CR3 without exiting. If it has changed it, we must keep it.
8890 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8891 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8892 *
8893 * Additionally, restore L2's PDPTR to vmcs12.
8894 */
8895 if (enable_ept) {
8896 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8897 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8898 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8899 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8900 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8901 }
8902
c18911a2
JK		 8903 vmcs12->vm_entry_controls =
8904 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8905 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8906
2996fca0
JK		 8907 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8908 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8909 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8910 }
8911
4704d0be
NHE		 8912 /* TODO: These cannot have changed unless we have MSR bitmaps and
8913 * the relevant bit asks not to trap the change */
b8c07d55 8914 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8915 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8916 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8917 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8918 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8919 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8920 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8921 if (vmx_mpx_supported())
8922 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8923
8924 /* update exit information fields: */
8925
533558bc
JK		 8926 vmcs12->vm_exit_reason = exit_reason;
8927 vmcs12->exit_qualification = exit_qualification;
4704d0be 8928
533558bc 8929 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8930 if ((vmcs12->vm_exit_intr_info &
8931 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8932 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8933 vmcs12->vm_exit_intr_error_code =
8934 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8935 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8936 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8937 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8938
5f3d5799
JK		 8939 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8940 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8941 * instead of reading the real value. */
4704d0be 8942 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8943
8944 /*
8945 * Transfer the event that L0 or L1 may wanted to inject into
8946 * L2 to IDT_VECTORING_INFO_FIELD.
8947 */
8948 vmcs12_save_pending_event(vcpu, vmcs12);
8949 }
8950
8951 /*
8952 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8953 * preserved above and would only end up incorrectly in L1.
8954 */
8955 vcpu->arch.nmi_injected = false;
8956 kvm_clear_exception_queue(vcpu);
8957 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8958}
8959
8960/*
8961 * A part of what we need to when the nested L2 guest exits and we want to
8962 * run its L1 parent, is to reset L1's guest state to the host state specified
8963 * in vmcs12.
8964 * This function is to be called not only on normal nested exit, but also on
8965 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8966 * Failures During or After Loading Guest State").
8967 * This function should be called when the active VMCS is L1's (vmcs01).
8968 */
733568f9
JK		 8969static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8970 struct vmcs12 *vmcs12)
4704d0be 8971{
21feb4eb
ACL		 8972 struct kvm_segment seg;
8973
4704d0be
NHE		 8974 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8975 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8976 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8977 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8978 else
8979 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8980 vmx_set_efer(vcpu, vcpu->arch.efer);
8981
8982 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8983 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8984 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8985 /*
8986 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8987 * actually changed, because it depends on the current state of
8988 * fpu_active (which may have changed).
8989 * Note that vmx_set_cr0 refers to efer set above.
8990 */
9e3e4dbf 8991 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8992 /*
8993 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8994 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8995 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8996 */
8997 update_exception_bitmap(vcpu);
8998 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8999 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9000
9001 /*
9002 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9003 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9004 */
9005 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9006 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9007
29bf08f1 9008 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9009
4704d0be
NHE		 9010 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9011 kvm_mmu_reset_context(vcpu);
9012
feaf0c7d
GN		 9013 if (!enable_ept)
9014 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9015
4704d0be
NHE		 9016 if (enable_vpid) {
9017 /*
9018 * Trivially support vpid by letting L2s share their parent
9019 * L1's vpid. TODO: move to a more elaborate solution, giving
9020 * each L2 its own vpid and exposing the vpid feature to L1.
9021 */
9022 vmx_flush_tlb(vcpu);
9023 }
9024
9025
9026 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9027 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9028 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9029 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9030 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9031
36be0b9d
PB		 9032 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9033 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9034 vmcs_write64(GUEST_BNDCFGS, 0);
9035
44811c02 9036 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9037 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9038 vcpu->arch.pat = vmcs12->host_ia32_pat;
9039 }
4704d0be
NHE		 9040 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9041 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9042 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9043
21feb4eb
ACL		 9044 /* Set L1 segment info according to Intel SDM
9045 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9046 seg = (struct kvm_segment) {
9047 .base = 0,
9048 .limit = 0xFFFFFFFF,
9049 .selector = vmcs12->host_cs_selector,
9050 .type = 11,
9051 .present = 1,
9052 .s = 1,
9053 .g = 1
9054 };
9055 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9056 seg.l = 1;
9057 else
9058 seg.db = 1;
9059 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9060 seg = (struct kvm_segment) {
9061 .base = 0,
9062 .limit = 0xFFFFFFFF,
9063 .type = 3,
9064 .present = 1,
9065 .s = 1,
9066 .db = 1,
9067 .g = 1
9068 };
9069 seg.selector = vmcs12->host_ds_selector;
9070 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9071 seg.selector = vmcs12->host_es_selector;
9072 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9073 seg.selector = vmcs12->host_ss_selector;
9074 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9075 seg.selector = vmcs12->host_fs_selector;
9076 seg.base = vmcs12->host_fs_base;
9077 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9078 seg.selector = vmcs12->host_gs_selector;
9079 seg.base = vmcs12->host_gs_base;
9080 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9081 seg = (struct kvm_segment) {
205befd9 9082 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9083 .limit = 0x67,
9084 .selector = vmcs12->host_tr_selector,
9085 .type = 11,
9086 .present = 1
9087 };
9088 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9089
503cd0c5
JK		 9090 kvm_set_dr(vcpu, 7, 0x400);
9091 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 9092}
9093
9094/*
9095 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9096 * and modify vmcs12 to make it see what it would expect to see there if
9097 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9098 */
533558bc
JK		 9099static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9100 u32 exit_intr_info,
9101 unsigned long exit_qualification)
4704d0be
NHE		 9102{
9103 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9104 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9105
5f3d5799
JK		 9106 /* trying to cancel vmlaunch/vmresume is a bug */
9107 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9108
4704d0be 9109 leave_guest_mode(vcpu);
533558bc
JK		 9110 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9111 exit_qualification);
4704d0be 9112
f3380ca5
WL		 9113 vmx_load_vmcs01(vcpu);
9114
77b0f5d6
BD		 9115 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9116 && nested_exit_intr_ack_set(vcpu)) {
9117 int irq = kvm_cpu_get_interrupt(vcpu);
9118 WARN_ON(irq < 0);
9119 vmcs12->vm_exit_intr_info = irq |
9120 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9121 }
9122
542060ea
JK		 9123 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9124 vmcs12->exit_qualification,
9125 vmcs12->idt_vectoring_info_field,
9126 vmcs12->vm_exit_intr_info,
9127 vmcs12->vm_exit_intr_error_code,
9128 KVM_ISA_VMX);
4704d0be 9129
2961e876
GN		 9130 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9131 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9132 vmx_segment_cache_clear(vmx);
9133
4704d0be
NHE		 9134 /* if no vmcs02 cache requested, remove the one we used */
9135 if (VMCS02_POOL_SIZE == 0)
9136 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9137
9138 load_vmcs12_host_state(vcpu, vmcs12);
9139
27fc51b2 9140 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9141 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9142
9143 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9144 vmx->host_rsp = 0;
9145
9146 /* Unpin physical memory we referred to in vmcs02 */
9147 if (vmx->nested.apic_access_page) {
9148 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9149 vmx->nested.apic_access_page = NULL;
4704d0be 9150 }
a7c0b07d
WL		 9151 if (vmx->nested.virtual_apic_page) {
9152 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9153 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9154 }
4704d0be 9155
38b99173
TC		 9156 /*
9157 * We are now running in L2, mmu_notifier will force to reload the
9158 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9159 */
9160 kvm_vcpu_reload_apic_access_page(vcpu);
9161
4704d0be
NHE		 9162 /*
9163 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9164 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9165 * success or failure flag accordingly.
9166 */
9167 if (unlikely(vmx->fail)) {
9168 vmx->fail = 0;
9169 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9170 } else
9171 nested_vmx_succeed(vcpu);
012f83cb
AG		 9172 if (enable_shadow_vmcs)
9173 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9174
9175 /* in case we halted in L2 */
9176 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9177}
9178
42124925
JK		 9179/*
9180 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9181 */
9182static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9183{
9184 if (is_guest_mode(vcpu))
533558bc 9185 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9186 free_nested(to_vmx(vcpu));
9187}
9188
7c177938
NHE		 9189/*
9190 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9191 * 23.7 "VM-entry failures during or after loading guest state" (this also
9192 * lists the acceptable exit-reason and exit-qualification parameters).
9193 * It should only be called before L2 actually succeeded to run, and when
9194 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9195 */
9196static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9197 struct vmcs12 *vmcs12,
9198 u32 reason, unsigned long qualification)
9199{
9200 load_vmcs12_host_state(vcpu, vmcs12);
9201 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9202 vmcs12->exit_qualification = qualification;
9203 nested_vmx_succeed(vcpu);
012f83cb
AG		 9204 if (enable_shadow_vmcs)
9205 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9206}
9207
8a76d7f2
JR		 9208static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9209 struct x86_instruction_info *info,
9210 enum x86_intercept_stage stage)
9211{
9212 return X86EMUL_CONTINUE;
9213}
9214
48d89b92 9215static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9216{
b4a2d31d
RK		 9217 if (ple_gap)
9218 shrink_ple_window(vcpu);
ae97a3b8
RK		 9219}
9220
cbdd1bea 9221static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9222 .cpu_has_kvm_support = cpu_has_kvm_support,
9223 .disabled_by_bios = vmx_disabled_by_bios,
9224 .hardware_setup = hardware_setup,
9225 .hardware_unsetup = hardware_unsetup,
002c7f7c 9226 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9227 .hardware_enable = hardware_enable,
9228 .hardware_disable = hardware_disable,
04547156 9229 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9230
9231 .vcpu_create = vmx_create_vcpu,
9232 .vcpu_free = vmx_free_vcpu,
04d2cc77 9233 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9234
04d2cc77 9235 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9236 .vcpu_load = vmx_vcpu_load,
9237 .vcpu_put = vmx_vcpu_put,
9238
c8639010 9239 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9240 .get_msr = vmx_get_msr,
9241 .set_msr = vmx_set_msr,
9242 .get_segment_base = vmx_get_segment_base,
9243 .get_segment = vmx_get_segment,
9244 .set_segment = vmx_set_segment,
2e4d2653 9245 .get_cpl = vmx_get_cpl,
6aa8b732 9246 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9247 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9248 .decache_cr3 = vmx_decache_cr3,
25c4c276 9249 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9250 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9251 .set_cr3 = vmx_set_cr3,
9252 .set_cr4 = vmx_set_cr4,
6aa8b732 9253 .set_efer = vmx_set_efer,
6aa8b732
AK		 9254 .get_idt = vmx_get_idt,
9255 .set_idt = vmx_set_idt,
9256 .get_gdt = vmx_get_gdt,
9257 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9258 .get_dr6 = vmx_get_dr6,
9259 .set_dr6 = vmx_set_dr6,
020df079 9260 .set_dr7 = vmx_set_dr7,
81908bf4 9261 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9262 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9263 .get_rflags = vmx_get_rflags,
9264 .set_rflags = vmx_set_rflags,
02daab21 9265 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9266
9267 .tlb_flush = vmx_flush_tlb,
6aa8b732 9268
6aa8b732 9269 .run = vmx_vcpu_run,
6062d012 9270 .handle_exit = vmx_handle_exit,
6aa8b732 9271 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9272 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9273 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9274 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9275 .set_irq = vmx_inject_irq,
95ba8273 9276 .set_nmi = vmx_inject_nmi,
298101da 9277 .queue_exception = vmx_queue_exception,
b463a6f7 9278 .cancel_injection = vmx_cancel_injection,
78646121 9279 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9280 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9281 .get_nmi_mask = vmx_get_nmi_mask,
9282 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9283 .enable_nmi_window = enable_nmi_window,
9284 .enable_irq_window = enable_irq_window,
9285 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9286 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9287 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9288 .vm_has_apicv = vmx_vm_has_apicv,
9289 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9290 .hwapic_irr_update = vmx_hwapic_irr_update,
9291 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9292 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9293 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9294
cbc94022 9295 .set_tss_addr = vmx_set_tss_addr,
67253af5 9296 .get_tdp_level = get_ept_level,
4b12f0de 9297 .get_mt_mask = vmx_get_mt_mask,
229456fc 9298
586f9607 9299 .get_exit_info = vmx_get_exit_info,
586f9607 9300
17cc3935 9301 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9302
9303 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9304
9305 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9306 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9307
9308 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9309
9310 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9311
4051b188 9312 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9313 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9314 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9315 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9316 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9317 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9318
9319 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9320
9321 .check_intercept = vmx_check_intercept,
a547c6db 9322 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9323 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 9324
9325 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9326
9327 .sched_in = vmx_sched_in,
6aa8b732
AK		 9328};
9329
9330static int __init vmx_init(void)
9331{
34a1cd60
TC		 9332 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9333 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9334 if (r)
34a1cd60 9335 return r;
25c5f225 9336
8f536b76
ZY		 9337#ifdef CONFIG_KEXEC
9338 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9339 crash_vmclear_local_loaded_vmcss);
9340#endif
9341
fdef3ad1 9342 return 0;
6aa8b732
AK		 9343}
9344
9345static void __exit vmx_exit(void)
9346{
8f536b76 9347#ifdef CONFIG_KEXEC
3b63a43f 9348 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9349 synchronize_rcu();
9350#endif
9351
cb498ea2 9352 kvm_exit();
6aa8b732
AK		 9353}
9354
9355module_init(vmx_init)
9356module_exit(vmx_exit)
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