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KVM: nVMX: Make nested control MSRs per-cpu
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
20300099
WL		 102static u64 __read_mostly host_xss;
103
843e4330
KH		 104static bool __read_mostly enable_pml = 1;
105module_param_named(pml, enable_pml, bool, S_IRUGO);
106
5037878e
GN		 107#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
108#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 109#define KVM_VM_CR0_ALWAYS_ON \
110 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 111#define KVM_CR4_GUEST_OWNED_BITS \
112 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 113 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 114
cdc0e244
AK		 115#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
116#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
117
78ac8b47
AK		 118#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
119
f4124500
JK		 120#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
121
4b8d54f9
ZE		 122/*
123 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
124 * ple_gap: upper bound on the amount of time between two successive
125 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 126 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 127 * ple_window: upper bound on the amount of time a guest is allowed to execute
128 * in a PAUSE loop. Tests indicate that most spinlocks are held for
129 * less than 2^12 cycles
130 * Time is measured based on a counter that runs at the same rate as the TSC,
131 * refer SDM volume 3b section 21.6.13 & 22.1.3.
132 */
b4a2d31d
RK		 133#define KVM_VMX_DEFAULT_PLE_GAP 128
134#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
135#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
136#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
137#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
138 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
139
4b8d54f9
ZE		 140static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
141module_param(ple_gap, int, S_IRUGO);
142
143static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
144module_param(ple_window, int, S_IRUGO);
145
b4a2d31d
RK		 146/* Default doubles per-vcpu window every exit. */
147static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
148module_param(ple_window_grow, int, S_IRUGO);
149
150/* Default resets per-vcpu window every exit to ple_window. */
151static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
152module_param(ple_window_shrink, int, S_IRUGO);
153
154/* Default is to compute the maximum so we can never overflow. */
155static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
156static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157module_param(ple_window_max, int, S_IRUGO);
158
83287ea4
AK		 159extern const ulong vmx_return;
160
8bf00a52 161#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 162#define VMCS02_POOL_SIZE 1
61d2ef2c 163
a2fa3e9f
GH		 164struct vmcs {
165 u32 revision_id;
166 u32 abort;
167 char data[0];
168};
169
d462b819
NHE		 170/*
171 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
172 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
173 * loaded on this CPU (so we can clear them if the CPU goes down).
174 */
175struct loaded_vmcs {
176 struct vmcs *vmcs;
177 int cpu;
178 int launched;
179 struct list_head loaded_vmcss_on_cpu_link;
180};
181
26bb0981
AK		 182struct shared_msr_entry {
183 unsigned index;
184 u64 data;
d5696725 185 u64 mask;
26bb0981
AK		 186};
187
a9d30f33
NHE		 188/*
189 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
190 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
191 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
192 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
193 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
194 * More than one of these structures may exist, if L1 runs multiple L2 guests.
195 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
196 * underlying hardware which will be used to run L2.
197 * This structure is packed to ensure that its layout is identical across
198 * machines (necessary for live migration).
199 * If there are changes in this struct, VMCS12_REVISION must be changed.
200 */
22bd0358 201typedef u64 natural_width;
a9d30f33
NHE		 202struct __packed vmcs12 {
203 /* According to the Intel spec, a VMCS region must start with the
204 * following two fields. Then follow implementation-specific data.
205 */
206 u32 revision_id;
207 u32 abort;
22bd0358 208
27d6c865
NHE		 209 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
210 u32 padding[7]; /* room for future expansion */
211
22bd0358
NHE		 212 u64 io_bitmap_a;
213 u64 io_bitmap_b;
214 u64 msr_bitmap;
215 u64 vm_exit_msr_store_addr;
216 u64 vm_exit_msr_load_addr;
217 u64 vm_entry_msr_load_addr;
218 u64 tsc_offset;
219 u64 virtual_apic_page_addr;
220 u64 apic_access_addr;
221 u64 ept_pointer;
81dc01f7 222 u64 xss_exit_bitmap;
22bd0358
NHE		 223 u64 guest_physical_address;
224 u64 vmcs_link_pointer;
225 u64 guest_ia32_debugctl;
226 u64 guest_ia32_pat;
227 u64 guest_ia32_efer;
228 u64 guest_ia32_perf_global_ctrl;
229 u64 guest_pdptr0;
230 u64 guest_pdptr1;
231 u64 guest_pdptr2;
232 u64 guest_pdptr3;
36be0b9d 233 u64 guest_bndcfgs;
22bd0358
NHE		 234 u64 host_ia32_pat;
235 u64 host_ia32_efer;
236 u64 host_ia32_perf_global_ctrl;
237 u64 padding64[8]; /* room for future expansion */
238 /*
239 * To allow migration of L1 (complete with its L2 guests) between
240 * machines of different natural widths (32 or 64 bit), we cannot have
241 * unsigned long fields with no explict size. We use u64 (aliased
242 * natural_width) instead. Luckily, x86 is little-endian.
243 */
244 natural_width cr0_guest_host_mask;
245 natural_width cr4_guest_host_mask;
246 natural_width cr0_read_shadow;
247 natural_width cr4_read_shadow;
248 natural_width cr3_target_value0;
249 natural_width cr3_target_value1;
250 natural_width cr3_target_value2;
251 natural_width cr3_target_value3;
252 natural_width exit_qualification;
253 natural_width guest_linear_address;
254 natural_width guest_cr0;
255 natural_width guest_cr3;
256 natural_width guest_cr4;
257 natural_width guest_es_base;
258 natural_width guest_cs_base;
259 natural_width guest_ss_base;
260 natural_width guest_ds_base;
261 natural_width guest_fs_base;
262 natural_width guest_gs_base;
263 natural_width guest_ldtr_base;
264 natural_width guest_tr_base;
265 natural_width guest_gdtr_base;
266 natural_width guest_idtr_base;
267 natural_width guest_dr7;
268 natural_width guest_rsp;
269 natural_width guest_rip;
270 natural_width guest_rflags;
271 natural_width guest_pending_dbg_exceptions;
272 natural_width guest_sysenter_esp;
273 natural_width guest_sysenter_eip;
274 natural_width host_cr0;
275 natural_width host_cr3;
276 natural_width host_cr4;
277 natural_width host_fs_base;
278 natural_width host_gs_base;
279 natural_width host_tr_base;
280 natural_width host_gdtr_base;
281 natural_width host_idtr_base;
282 natural_width host_ia32_sysenter_esp;
283 natural_width host_ia32_sysenter_eip;
284 natural_width host_rsp;
285 natural_width host_rip;
286 natural_width paddingl[8]; /* room for future expansion */
287 u32 pin_based_vm_exec_control;
288 u32 cpu_based_vm_exec_control;
289 u32 exception_bitmap;
290 u32 page_fault_error_code_mask;
291 u32 page_fault_error_code_match;
292 u32 cr3_target_count;
293 u32 vm_exit_controls;
294 u32 vm_exit_msr_store_count;
295 u32 vm_exit_msr_load_count;
296 u32 vm_entry_controls;
297 u32 vm_entry_msr_load_count;
298 u32 vm_entry_intr_info_field;
299 u32 vm_entry_exception_error_code;
300 u32 vm_entry_instruction_len;
301 u32 tpr_threshold;
302 u32 secondary_vm_exec_control;
303 u32 vm_instruction_error;
304 u32 vm_exit_reason;
305 u32 vm_exit_intr_info;
306 u32 vm_exit_intr_error_code;
307 u32 idt_vectoring_info_field;
308 u32 idt_vectoring_error_code;
309 u32 vm_exit_instruction_len;
310 u32 vmx_instruction_info;
311 u32 guest_es_limit;
312 u32 guest_cs_limit;
313 u32 guest_ss_limit;
314 u32 guest_ds_limit;
315 u32 guest_fs_limit;
316 u32 guest_gs_limit;
317 u32 guest_ldtr_limit;
318 u32 guest_tr_limit;
319 u32 guest_gdtr_limit;
320 u32 guest_idtr_limit;
321 u32 guest_es_ar_bytes;
322 u32 guest_cs_ar_bytes;
323 u32 guest_ss_ar_bytes;
324 u32 guest_ds_ar_bytes;
325 u32 guest_fs_ar_bytes;
326 u32 guest_gs_ar_bytes;
327 u32 guest_ldtr_ar_bytes;
328 u32 guest_tr_ar_bytes;
329 u32 guest_interruptibility_info;
330 u32 guest_activity_state;
331 u32 guest_sysenter_cs;
332 u32 host_ia32_sysenter_cs;
0238ea91
JK		 333 u32 vmx_preemption_timer_value;
334 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 335 u16 virtual_processor_id;
336 u16 guest_es_selector;
337 u16 guest_cs_selector;
338 u16 guest_ss_selector;
339 u16 guest_ds_selector;
340 u16 guest_fs_selector;
341 u16 guest_gs_selector;
342 u16 guest_ldtr_selector;
343 u16 guest_tr_selector;
344 u16 host_es_selector;
345 u16 host_cs_selector;
346 u16 host_ss_selector;
347 u16 host_ds_selector;
348 u16 host_fs_selector;
349 u16 host_gs_selector;
350 u16 host_tr_selector;
a9d30f33
NHE		 351};
352
353/*
354 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
355 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
356 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
357 */
358#define VMCS12_REVISION 0x11e57ed0
359
360/*
361 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
362 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
363 * current implementation, 4K are reserved to avoid future complications.
364 */
365#define VMCS12_SIZE 0x1000
366
ff2f6fe9
NHE		 367/* Used to remember the last vmcs02 used for some recently used vmcs12s */
368struct vmcs02_list {
369 struct list_head list;
370 gpa_t vmptr;
371 struct loaded_vmcs vmcs02;
372};
373
ec378aee
NHE		 374/*
375 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
376 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
377 */
378struct nested_vmx {
379 /* Has the level1 guest done vmxon? */
380 bool vmxon;
3573e22c 381 gpa_t vmxon_ptr;
a9d30f33
NHE		 382
383 /* The guest-physical address of the current VMCS L1 keeps for L2 */
384 gpa_t current_vmptr;
385 /* The host-usable pointer to the above */
386 struct page *current_vmcs12_page;
387 struct vmcs12 *current_vmcs12;
8de48833 388 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 389 /*
390 * Indicates if the shadow vmcs must be updated with the
391 * data hold by vmcs12
392 */
393 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 394
395 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
396 struct list_head vmcs02_pool;
397 int vmcs02_num;
fe3ef05c 398 u64 vmcs01_tsc_offset;
644d711a
NHE		 399 /* L2 must run next, and mustn't decide to exit to L1. */
400 bool nested_run_pending;
fe3ef05c
NHE		 401 /*
402 * Guest pages referred to in vmcs02 with host-physical pointers, so
403 * we must keep them pinned while L2 runs.
404 */
405 struct page *apic_access_page;
a7c0b07d 406 struct page *virtual_apic_page;
b3897a49 407 u64 msr_ia32_feature_control;
f4124500
JK		 408
409 struct hrtimer preemption_timer;
410 bool preemption_timer_expired;
2996fca0
JK		 411
412 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
413 u64 vmcs01_debugctl;
b9c237bb
WV		 414
415 u32 nested_vmx_procbased_ctls_low;
416 u32 nested_vmx_procbased_ctls_high;
417 u32 nested_vmx_true_procbased_ctls_low;
418 u32 nested_vmx_secondary_ctls_low;
419 u32 nested_vmx_secondary_ctls_high;
420 u32 nested_vmx_pinbased_ctls_low;
421 u32 nested_vmx_pinbased_ctls_high;
422 u32 nested_vmx_exit_ctls_low;
423 u32 nested_vmx_exit_ctls_high;
424 u32 nested_vmx_true_exit_ctls_low;
425 u32 nested_vmx_entry_ctls_low;
426 u32 nested_vmx_entry_ctls_high;
427 u32 nested_vmx_true_entry_ctls_low;
428 u32 nested_vmx_misc_low;
429 u32 nested_vmx_misc_high;
430 u32 nested_vmx_ept_caps;
ec378aee
NHE		 431};
432
01e439be
YZ		 433#define POSTED_INTR_ON 0
434/* Posted-Interrupt Descriptor */
435struct pi_desc {
436 u32 pir[8]; /* Posted interrupt requested */
437 u32 control; /* bit 0 of control is outstanding notification bit */
438 u32 rsvd[7];
439} __aligned(64);
440
a20ed54d
YZ		 441static bool pi_test_and_set_on(struct pi_desc *pi_desc)
442{
443 return test_and_set_bit(POSTED_INTR_ON,
444 (unsigned long *)&pi_desc->control);
445}
446
447static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
448{
449 return test_and_clear_bit(POSTED_INTR_ON,
450 (unsigned long *)&pi_desc->control);
451}
452
453static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
456}
457
a2fa3e9f 458struct vcpu_vmx {
fb3f0f51 459 struct kvm_vcpu vcpu;
313dbd49 460 unsigned long host_rsp;
29bd8a78 461 u8 fail;
9d58b931 462 bool nmi_known_unmasked;
51aa01d1 463 u32 exit_intr_info;
1155f76a 464 u32 idt_vectoring_info;
6de12732 465 ulong rflags;
26bb0981 466 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 467 int nmsrs;
468 int save_nmsrs;
a547c6db 469 unsigned long host_idt_base;
a2fa3e9f 470#ifdef CONFIG_X86_64
44ea2b17
AK		 471 u64 msr_host_kernel_gs_base;
472 u64 msr_guest_kernel_gs_base;
a2fa3e9f 473#endif
2961e876
GN		 474 u32 vm_entry_controls_shadow;
475 u32 vm_exit_controls_shadow;
d462b819
NHE		 476 /*
477 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
478 * non-nested (L1) guest, it always points to vmcs01. For a nested
479 * guest (L2), it points to a different VMCS.
480 */
481 struct loaded_vmcs vmcs01;
482 struct loaded_vmcs *loaded_vmcs;
483 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 484 struct msr_autoload {
485 unsigned nr;
486 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
487 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
488 } msr_autoload;
a2fa3e9f
GH		 489 struct {
490 int loaded;
491 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 492#ifdef CONFIG_X86_64
493 u16 ds_sel, es_sel;
494#endif
152d3f2f
LV		 495 int gs_ldt_reload_needed;
496 int fs_reload_needed;
da8999d3 497 u64 msr_host_bndcfgs;
d974baa3 498 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 499 } host_state;
9c8cba37 500 struct {
7ffd92c5 501 int vm86_active;
78ac8b47 502 ulong save_rflags;
f5f7b2fe
AK		 503 struct kvm_segment segs[8];
504 } rmode;
505 struct {
506 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 507 struct kvm_save_segment {
508 u16 selector;
509 unsigned long base;
510 u32 limit;
511 u32 ar;
f5f7b2fe 512 } seg[8];
2fb92db1 513 } segment_cache;
2384d2b3 514 int vpid;
04fa4d32 515 bool emulation_required;
3b86cd99
JK		 516
517 /* Support for vnmi-less CPUs */
518 int soft_vnmi_blocked;
519 ktime_t entry_time;
520 s64 vnmi_blocked_time;
a0861c02 521 u32 exit_reason;
4e47c7a6
SY		 522
523 bool rdtscp_enabled;
ec378aee 524
01e439be
YZ		 525 /* Posted interrupt descriptor */
526 struct pi_desc pi_desc;
527
ec378aee
NHE		 528 /* Support for a guest hypervisor (nested VMX) */
529 struct nested_vmx nested;
a7653ecd
RK		 530
531 /* Dynamic PLE window. */
532 int ple_window;
533 bool ple_window_dirty;
843e4330
KH		 534
535 /* Support for PML */
536#define PML_ENTITY_NUM 512
537 struct page *pml_pg;
a2fa3e9f
GH		 538};
539
2fb92db1
AK		 540enum segment_cache_field {
541 SEG_FIELD_SEL = 0,
542 SEG_FIELD_BASE = 1,
543 SEG_FIELD_LIMIT = 2,
544 SEG_FIELD_AR = 3,
545
546 SEG_FIELD_NR = 4
547};
548
a2fa3e9f
GH		 549static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
550{
fb3f0f51 551 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 552}
553
22bd0358
NHE		 554#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
555#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
556#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
557 [number##_HIGH] = VMCS12_OFFSET(name)+4
558
4607c2d7 559
fe2b201b 560static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 561 /*
562 * We do NOT shadow fields that are modified when L0
563 * traps and emulates any vmx instruction (e.g. VMPTRLD,
564 * VMXON...) executed by L1.
565 * For example, VM_INSTRUCTION_ERROR is read
566 * by L1 if a vmx instruction fails (part of the error path).
567 * Note the code assumes this logic. If for some reason
568 * we start shadowing these fields then we need to
569 * force a shadow sync when L0 emulates vmx instructions
570 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
571 * by nested_vmx_failValid)
572 */
573 VM_EXIT_REASON,
574 VM_EXIT_INTR_INFO,
575 VM_EXIT_INSTRUCTION_LEN,
576 IDT_VECTORING_INFO_FIELD,
577 IDT_VECTORING_ERROR_CODE,
578 VM_EXIT_INTR_ERROR_CODE,
579 EXIT_QUALIFICATION,
580 GUEST_LINEAR_ADDRESS,
581 GUEST_PHYSICAL_ADDRESS
582};
fe2b201b 583static int max_shadow_read_only_fields =
4607c2d7
AG		 584 ARRAY_SIZE(shadow_read_only_fields);
585
fe2b201b 586static unsigned long shadow_read_write_fields[] = {
a7c0b07d 587 TPR_THRESHOLD,
4607c2d7
AG		 588 GUEST_RIP,
589 GUEST_RSP,
590 GUEST_CR0,
591 GUEST_CR3,
592 GUEST_CR4,
593 GUEST_INTERRUPTIBILITY_INFO,
594 GUEST_RFLAGS,
595 GUEST_CS_SELECTOR,
596 GUEST_CS_AR_BYTES,
597 GUEST_CS_LIMIT,
598 GUEST_CS_BASE,
599 GUEST_ES_BASE,
36be0b9d 600 GUEST_BNDCFGS,
4607c2d7
AG		 601 CR0_GUEST_HOST_MASK,
602 CR0_READ_SHADOW,
603 CR4_READ_SHADOW,
604 TSC_OFFSET,
605 EXCEPTION_BITMAP,
606 CPU_BASED_VM_EXEC_CONTROL,
607 VM_ENTRY_EXCEPTION_ERROR_CODE,
608 VM_ENTRY_INTR_INFO_FIELD,
609 VM_ENTRY_INSTRUCTION_LEN,
610 VM_ENTRY_EXCEPTION_ERROR_CODE,
611 HOST_FS_BASE,
612 HOST_GS_BASE,
613 HOST_FS_SELECTOR,
614 HOST_GS_SELECTOR
615};
fe2b201b 616static int max_shadow_read_write_fields =
4607c2d7
AG		 617 ARRAY_SIZE(shadow_read_write_fields);
618
772e0318 619static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 620 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
621 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
622 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
623 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
624 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
625 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
626 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
627 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
628 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
629 FIELD(HOST_ES_SELECTOR, host_es_selector),
630 FIELD(HOST_CS_SELECTOR, host_cs_selector),
631 FIELD(HOST_SS_SELECTOR, host_ss_selector),
632 FIELD(HOST_DS_SELECTOR, host_ds_selector),
633 FIELD(HOST_FS_SELECTOR, host_fs_selector),
634 FIELD(HOST_GS_SELECTOR, host_gs_selector),
635 FIELD(HOST_TR_SELECTOR, host_tr_selector),
636 FIELD64(IO_BITMAP_A, io_bitmap_a),
637 FIELD64(IO_BITMAP_B, io_bitmap_b),
638 FIELD64(MSR_BITMAP, msr_bitmap),
639 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
640 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
641 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
642 FIELD64(TSC_OFFSET, tsc_offset),
643 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
644 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
645 FIELD64(EPT_POINTER, ept_pointer),
81dc01f7 646 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 647 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
648 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
649 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
650 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
651 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
652 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
653 FIELD64(GUEST_PDPTR0, guest_pdptr0),
654 FIELD64(GUEST_PDPTR1, guest_pdptr1),
655 FIELD64(GUEST_PDPTR2, guest_pdptr2),
656 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 657 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 658 FIELD64(HOST_IA32_PAT, host_ia32_pat),
659 FIELD64(HOST_IA32_EFER, host_ia32_efer),
660 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
661 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
662 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
663 FIELD(EXCEPTION_BITMAP, exception_bitmap),
664 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
665 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
666 FIELD(CR3_TARGET_COUNT, cr3_target_count),
667 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
668 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
669 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
670 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
671 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
672 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
673 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
674 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
675 FIELD(TPR_THRESHOLD, tpr_threshold),
676 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
677 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
678 FIELD(VM_EXIT_REASON, vm_exit_reason),
679 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
680 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
681 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
682 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
683 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
684 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
685 FIELD(GUEST_ES_LIMIT, guest_es_limit),
686 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
687 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
688 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
689 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
690 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
691 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
692 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
693 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
694 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
695 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
696 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
697 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
698 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
699 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
700 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
701 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
702 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
703 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
704 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
705 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
706 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 707 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 708 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
709 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
710 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
711 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
712 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
713 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
714 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
715 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
716 FIELD(EXIT_QUALIFICATION, exit_qualification),
717 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
718 FIELD(GUEST_CR0, guest_cr0),
719 FIELD(GUEST_CR3, guest_cr3),
720 FIELD(GUEST_CR4, guest_cr4),
721 FIELD(GUEST_ES_BASE, guest_es_base),
722 FIELD(GUEST_CS_BASE, guest_cs_base),
723 FIELD(GUEST_SS_BASE, guest_ss_base),
724 FIELD(GUEST_DS_BASE, guest_ds_base),
725 FIELD(GUEST_FS_BASE, guest_fs_base),
726 FIELD(GUEST_GS_BASE, guest_gs_base),
727 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
728 FIELD(GUEST_TR_BASE, guest_tr_base),
729 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
730 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
731 FIELD(GUEST_DR7, guest_dr7),
732 FIELD(GUEST_RSP, guest_rsp),
733 FIELD(GUEST_RIP, guest_rip),
734 FIELD(GUEST_RFLAGS, guest_rflags),
735 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
736 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
737 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
738 FIELD(HOST_CR0, host_cr0),
739 FIELD(HOST_CR3, host_cr3),
740 FIELD(HOST_CR4, host_cr4),
741 FIELD(HOST_FS_BASE, host_fs_base),
742 FIELD(HOST_GS_BASE, host_gs_base),
743 FIELD(HOST_TR_BASE, host_tr_base),
744 FIELD(HOST_GDTR_BASE, host_gdtr_base),
745 FIELD(HOST_IDTR_BASE, host_idtr_base),
746 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
747 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
748 FIELD(HOST_RSP, host_rsp),
749 FIELD(HOST_RIP, host_rip),
750};
22bd0358
NHE		 751
752static inline short vmcs_field_to_offset(unsigned long field)
753{
a2ae9df7
PB		 754 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
755
756 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
757 vmcs_field_to_offset_table[field] == 0)
758 return -ENOENT;
759
22bd0358
NHE		 760 return vmcs_field_to_offset_table[field];
761}
762
a9d30f33
NHE		 763static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
764{
765 return to_vmx(vcpu)->nested.current_vmcs12;
766}
767
768static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
769{
770 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 771 if (is_error_page(page))
a9d30f33 772 return NULL;
32cad84f 773
a9d30f33
NHE		 774 return page;
775}
776
777static void nested_release_page(struct page *page)
778{
779 kvm_release_page_dirty(page);
780}
781
782static void nested_release_page_clean(struct page *page)
783{
784 kvm_release_page_clean(page);
785}
786
bfd0a56b 787static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 788static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 789static void kvm_cpu_vmxon(u64 addr);
790static void kvm_cpu_vmxoff(void);
93c4adc7 791static bool vmx_mpx_supported(void);
f53cd63c 792static bool vmx_xsaves_supported(void);
776e58ea 793static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 794static void vmx_set_segment(struct kvm_vcpu *vcpu,
795 struct kvm_segment *var, int seg);
796static void vmx_get_segment(struct kvm_vcpu *vcpu,
797 struct kvm_segment *var, int seg);
d99e4152
GN		 798static bool guest_state_valid(struct kvm_vcpu *vcpu);
799static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 800static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 801static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 802static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 803static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 804
6aa8b732
AK		 805static DEFINE_PER_CPU(struct vmcs *, vmxarea);
806static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 807/*
808 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
809 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
810 */
811static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 812static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 813
3e7c73e9
AK		 814static unsigned long *vmx_io_bitmap_a;
815static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 816static unsigned long *vmx_msr_bitmap_legacy;
817static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 818static unsigned long *vmx_msr_bitmap_legacy_x2apic;
819static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 820static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 821static unsigned long *vmx_vmread_bitmap;
822static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 823
110312c8 824static bool cpu_has_load_ia32_efer;
8bf00a52 825static bool cpu_has_load_perf_global_ctrl;
110312c8 826
2384d2b3
SY		 827static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
828static DEFINE_SPINLOCK(vmx_vpid_lock);
829
1c3d14fe 830static struct vmcs_config {
6aa8b732
AK		 831 int size;
832 int order;
833 u32 revision_id;
1c3d14fe
YS		 834 u32 pin_based_exec_ctrl;
835 u32 cpu_based_exec_ctrl;
f78e0e2e 836 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 837 u32 vmexit_ctrl;
838 u32 vmentry_ctrl;
839} vmcs_config;
6aa8b732 840
efff9e53 841static struct vmx_capability {
d56f546d
SY		 842 u32 ept;
843 u32 vpid;
844} vmx_capability;
845
6aa8b732
AK		 846#define VMX_SEGMENT_FIELD(seg) \
847 [VCPU_SREG_##seg] = { \
848 .selector = GUEST_##seg##_SELECTOR, \
849 .base = GUEST_##seg##_BASE, \
850 .limit = GUEST_##seg##_LIMIT, \
851 .ar_bytes = GUEST_##seg##_AR_BYTES, \
852 }
853
772e0318 854static const struct kvm_vmx_segment_field {
6aa8b732
AK		 855 unsigned selector;
856 unsigned base;
857 unsigned limit;
858 unsigned ar_bytes;
859} kvm_vmx_segment_fields[] = {
860 VMX_SEGMENT_FIELD(CS),
861 VMX_SEGMENT_FIELD(DS),
862 VMX_SEGMENT_FIELD(ES),
863 VMX_SEGMENT_FIELD(FS),
864 VMX_SEGMENT_FIELD(GS),
865 VMX_SEGMENT_FIELD(SS),
866 VMX_SEGMENT_FIELD(TR),
867 VMX_SEGMENT_FIELD(LDTR),
868};
869
26bb0981
AK		 870static u64 host_efer;
871
6de4f3ad
AK		 872static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
873
4d56c8a7 874/*
8c06585d 875 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 876 * away by decrementing the array size.
877 */
6aa8b732 878static const u32 vmx_msr_index[] = {
05b3e0c2 879#ifdef CONFIG_X86_64
44ea2b17 880 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 881#endif
8c06585d 882 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 883};
6aa8b732 884
31299944 885static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 886{
887 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
888 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 889 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 890}
891
31299944 892static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 893{
894 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
895 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 896 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 897}
898
31299944 899static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 900{
901 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
902 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 903 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 904}
905
31299944 906static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 907{
908 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
909 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
910}
911
31299944 912static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
916 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
917}
918
31299944 919static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 920{
04547156 921 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 922}
923
31299944 924static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 925{
04547156 926 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 927}
928
31299944 929static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 930{
04547156 931 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 932}
933
31299944 934static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 935{
04547156
SY		 936 return vmcs_config.cpu_based_exec_ctrl &
937 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 938}
939
774ead3a 940static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 941{
04547156
SY		 942 return vmcs_config.cpu_based_2nd_exec_ctrl &
943 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
944}
945
8d14695f
YZ		 946static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
947{
948 return vmcs_config.cpu_based_2nd_exec_ctrl &
949 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
950}
951
83d4c286
YZ		 952static inline bool cpu_has_vmx_apic_register_virt(void)
953{
954 return vmcs_config.cpu_based_2nd_exec_ctrl &
955 SECONDARY_EXEC_APIC_REGISTER_VIRT;
956}
957
c7c9c56c
YZ		 958static inline bool cpu_has_vmx_virtual_intr_delivery(void)
959{
960 return vmcs_config.cpu_based_2nd_exec_ctrl &
961 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
962}
963
01e439be
YZ		 964static inline bool cpu_has_vmx_posted_intr(void)
965{
966 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
967}
968
969static inline bool cpu_has_vmx_apicv(void)
970{
971 return cpu_has_vmx_apic_register_virt() &&
972 cpu_has_vmx_virtual_intr_delivery() &&
973 cpu_has_vmx_posted_intr();
974}
975
04547156
SY		 976static inline bool cpu_has_vmx_flexpriority(void)
977{
978 return cpu_has_vmx_tpr_shadow() &&
979 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 980}
981
e799794e
MT		 982static inline bool cpu_has_vmx_ept_execute_only(void)
983{
31299944 984 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 985}
986
e799794e
MT		 987static inline bool cpu_has_vmx_ept_2m_page(void)
988{
31299944 989 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 990}
991
878403b7
SY		 992static inline bool cpu_has_vmx_ept_1g_page(void)
993{
31299944 994 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 995}
996
4bc9b982
SY		 997static inline bool cpu_has_vmx_ept_4levels(void)
998{
999 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1000}
1001
83c3a331
XH		 1002static inline bool cpu_has_vmx_ept_ad_bits(void)
1003{
1004 return vmx_capability.ept & VMX_EPT_AD_BIT;
1005}
1006
31299944 1007static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1008{
31299944 1009 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1010}
1011
31299944 1012static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1013{
31299944 1014 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1015}
1016
518c8aee
GJ		 1017static inline bool cpu_has_vmx_invvpid_single(void)
1018{
1019 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1020}
1021
b9d762fa
GJ		 1022static inline bool cpu_has_vmx_invvpid_global(void)
1023{
1024 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1025}
1026
31299944 1027static inline bool cpu_has_vmx_ept(void)
d56f546d 1028{
04547156
SY		 1029 return vmcs_config.cpu_based_2nd_exec_ctrl &
1030 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1031}
1032
31299944 1033static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1034{
1035 return vmcs_config.cpu_based_2nd_exec_ctrl &
1036 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1037}
1038
31299944 1039static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1040{
1041 return vmcs_config.cpu_based_2nd_exec_ctrl &
1042 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1043}
1044
31299944 1045static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1046{
6d3e435e 1047 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1048}
1049
31299944 1050static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1051{
04547156
SY		 1052 return vmcs_config.cpu_based_2nd_exec_ctrl &
1053 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1054}
1055
31299944 1056static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1057{
1058 return vmcs_config.cpu_based_2nd_exec_ctrl &
1059 SECONDARY_EXEC_RDTSCP;
1060}
1061
ad756a16
MJ		 1062static inline bool cpu_has_vmx_invpcid(void)
1063{
1064 return vmcs_config.cpu_based_2nd_exec_ctrl &
1065 SECONDARY_EXEC_ENABLE_INVPCID;
1066}
1067
31299944 1068static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1069{
1070 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1071}
1072
f5f48ee1
SY		 1073static inline bool cpu_has_vmx_wbinvd_exit(void)
1074{
1075 return vmcs_config.cpu_based_2nd_exec_ctrl &
1076 SECONDARY_EXEC_WBINVD_EXITING;
1077}
1078
abc4fc58
AG		 1079static inline bool cpu_has_vmx_shadow_vmcs(void)
1080{
1081 u64 vmx_msr;
1082 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1083 /* check if the cpu supports writing r/o exit information fields */
1084 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1085 return false;
1086
1087 return vmcs_config.cpu_based_2nd_exec_ctrl &
1088 SECONDARY_EXEC_SHADOW_VMCS;
1089}
1090
843e4330
KH		 1091static inline bool cpu_has_vmx_pml(void)
1092{
1093 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1094}
1095
04547156
SY		 1096static inline bool report_flexpriority(void)
1097{
1098 return flexpriority_enabled;
1099}
1100
fe3ef05c
NHE		 1101static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1102{
1103 return vmcs12->cpu_based_vm_exec_control & bit;
1104}
1105
1106static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1107{
1108 return (vmcs12->cpu_based_vm_exec_control &
1109 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1110 (vmcs12->secondary_vm_exec_control & bit);
1111}
1112
f5c4368f 1113static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1114{
1115 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1116}
1117
f4124500
JK		 1118static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1119{
1120 return vmcs12->pin_based_vm_exec_control &
1121 PIN_BASED_VMX_PREEMPTION_TIMER;
1122}
1123
155a97a3
NHE		 1124static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1125{
1126 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1127}
1128
81dc01f7
WL		 1129static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1130{
1131 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1132 vmx_xsaves_supported();
1133}
1134
f2b93280
WV		 1135static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1136{
1137 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1138}
1139
644d711a
NHE		 1140static inline bool is_exception(u32 intr_info)
1141{
1142 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1143 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1144}
1145
533558bc
JK		 1146static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1147 u32 exit_intr_info,
1148 unsigned long exit_qualification);
7c177938
NHE		 1149static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1150 struct vmcs12 *vmcs12,
1151 u32 reason, unsigned long qualification);
1152
8b9cf98c 1153static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1154{
1155 int i;
1156
a2fa3e9f 1157 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1158 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1159 return i;
1160 return -1;
1161}
1162
2384d2b3
SY		 1163static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1164{
1165 struct {
1166 u64 vpid : 16;
1167 u64 rsvd : 48;
1168 u64 gva;
1169 } operand = { vpid, 0, gva };
1170
4ecac3fd 1171 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1172 /* CF==1 or ZF==1 --> rc = -1 */
1173 "; ja 1f ; ud2 ; 1:"
1174 : : "a"(&operand), "c"(ext) : "cc", "memory");
1175}
1176
1439442c
SY		 1177static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1178{
1179 struct {
1180 u64 eptp, gpa;
1181 } operand = {eptp, gpa};
1182
4ecac3fd 1183 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1184 /* CF==1 or ZF==1 --> rc = -1 */
1185 "; ja 1f ; ud2 ; 1:\n"
1186 : : "a" (&operand), "c" (ext) : "cc", "memory");
1187}
1188
26bb0981 1189static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1190{
1191 int i;
1192
8b9cf98c 1193 i = __find_msr_index(vmx, msr);
a75beee6 1194 if (i >= 0)
a2fa3e9f 1195 return &vmx->guest_msrs[i];
8b6d44c7 1196 return NULL;
7725f0ba
AK		 1197}
1198
6aa8b732
AK		 1199static void vmcs_clear(struct vmcs *vmcs)
1200{
1201 u64 phys_addr = __pa(vmcs);
1202 u8 error;
1203
4ecac3fd 1204 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1205 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1206 : "cc", "memory");
1207 if (error)
1208 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1209 vmcs, phys_addr);
1210}
1211
d462b819
NHE		 1212static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1213{
1214 vmcs_clear(loaded_vmcs->vmcs);
1215 loaded_vmcs->cpu = -1;
1216 loaded_vmcs->launched = 0;
1217}
1218
7725b894
DX		 1219static void vmcs_load(struct vmcs *vmcs)
1220{
1221 u64 phys_addr = __pa(vmcs);
1222 u8 error;
1223
1224 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1225 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1226 : "cc", "memory");
1227 if (error)
2844d849 1228 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1229 vmcs, phys_addr);
1230}
1231
8f536b76
ZY		 1232#ifdef CONFIG_KEXEC
1233/*
1234 * This bitmap is used to indicate whether the vmclear
1235 * operation is enabled on all cpus. All disabled by
1236 * default.
1237 */
1238static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1239
1240static inline void crash_enable_local_vmclear(int cpu)
1241{
1242 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1243}
1244
1245static inline void crash_disable_local_vmclear(int cpu)
1246{
1247 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1248}
1249
1250static inline int crash_local_vmclear_enabled(int cpu)
1251{
1252 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1253}
1254
1255static void crash_vmclear_local_loaded_vmcss(void)
1256{
1257 int cpu = raw_smp_processor_id();
1258 struct loaded_vmcs *v;
1259
1260 if (!crash_local_vmclear_enabled(cpu))
1261 return;
1262
1263 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1264 loaded_vmcss_on_cpu_link)
1265 vmcs_clear(v->vmcs);
1266}
1267#else
1268static inline void crash_enable_local_vmclear(int cpu) { }
1269static inline void crash_disable_local_vmclear(int cpu) { }
1270#endif /* CONFIG_KEXEC */
1271
d462b819 1272static void __loaded_vmcs_clear(void *arg)
6aa8b732 1273{
d462b819 1274 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1275 int cpu = raw_smp_processor_id();
6aa8b732 1276
d462b819
NHE		 1277 if (loaded_vmcs->cpu != cpu)
1278 return; /* vcpu migration can race with cpu offline */
1279 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1280 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1281 crash_disable_local_vmclear(cpu);
d462b819 1282 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1283
1284 /*
1285 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1286 * is before setting loaded_vmcs->vcpu to -1 which is done in
1287 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1288 * then adds the vmcs into percpu list before it is deleted.
1289 */
1290 smp_wmb();
1291
d462b819 1292 loaded_vmcs_init(loaded_vmcs);
8f536b76 1293 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1294}
1295
d462b819 1296static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1297{
e6c7d321
XG		 1298 int cpu = loaded_vmcs->cpu;
1299
1300 if (cpu != -1)
1301 smp_call_function_single(cpu,
1302 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1303}
1304
1760dd49 1305static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1306{
1307 if (vmx->vpid == 0)
1308 return;
1309
518c8aee
GJ		 1310 if (cpu_has_vmx_invvpid_single())
1311 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1312}
1313
b9d762fa
GJ		 1314static inline void vpid_sync_vcpu_global(void)
1315{
1316 if (cpu_has_vmx_invvpid_global())
1317 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1318}
1319
1320static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1321{
1322 if (cpu_has_vmx_invvpid_single())
1760dd49 1323 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1324 else
1325 vpid_sync_vcpu_global();
1326}
1327
1439442c
SY		 1328static inline void ept_sync_global(void)
1329{
1330 if (cpu_has_vmx_invept_global())
1331 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1332}
1333
1334static inline void ept_sync_context(u64 eptp)
1335{
089d034e 1336 if (enable_ept) {
1439442c
SY		 1337 if (cpu_has_vmx_invept_context())
1338 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1339 else
1340 ept_sync_global();
1341 }
1342}
1343
96304217 1344static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1345{
5e520e62 1346 unsigned long value;
6aa8b732 1347
5e520e62
AK		 1348 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1349 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1350 return value;
1351}
1352
96304217 1353static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1354{
1355 return vmcs_readl(field);
1356}
1357
96304217 1358static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1359{
1360 return vmcs_readl(field);
1361}
1362
96304217 1363static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1364{
05b3e0c2 1365#ifdef CONFIG_X86_64
6aa8b732
AK		 1366 return vmcs_readl(field);
1367#else
1368 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1369#endif
1370}
1371
e52de1b8
AK		 1372static noinline void vmwrite_error(unsigned long field, unsigned long value)
1373{
1374 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1375 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1376 dump_stack();
1377}
1378
6aa8b732
AK		 1379static void vmcs_writel(unsigned long field, unsigned long value)
1380{
1381 u8 error;
1382
4ecac3fd 1383 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1384 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1385 if (unlikely(error))
1386 vmwrite_error(field, value);
6aa8b732
AK		 1387}
1388
1389static void vmcs_write16(unsigned long field, u16 value)
1390{
1391 vmcs_writel(field, value);
1392}
1393
1394static void vmcs_write32(unsigned long field, u32 value)
1395{
1396 vmcs_writel(field, value);
1397}
1398
1399static void vmcs_write64(unsigned long field, u64 value)
1400{
6aa8b732 1401 vmcs_writel(field, value);
7682f2d0 1402#ifndef CONFIG_X86_64
6aa8b732
AK		 1403 asm volatile ("");
1404 vmcs_writel(field+1, value >> 32);
1405#endif
1406}
1407
2ab455cc
AL		 1408static void vmcs_clear_bits(unsigned long field, u32 mask)
1409{
1410 vmcs_writel(field, vmcs_readl(field) & ~mask);
1411}
1412
1413static void vmcs_set_bits(unsigned long field, u32 mask)
1414{
1415 vmcs_writel(field, vmcs_readl(field) | mask);
1416}
1417
2961e876
GN		 1418static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1419{
1420 vmcs_write32(VM_ENTRY_CONTROLS, val);
1421 vmx->vm_entry_controls_shadow = val;
1422}
1423
1424static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1425{
1426 if (vmx->vm_entry_controls_shadow != val)
1427 vm_entry_controls_init(vmx, val);
1428}
1429
1430static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1431{
1432 return vmx->vm_entry_controls_shadow;
1433}
1434
1435
1436static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1437{
1438 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1439}
1440
1441static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1442{
1443 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1444}
1445
1446static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1447{
1448 vmcs_write32(VM_EXIT_CONTROLS, val);
1449 vmx->vm_exit_controls_shadow = val;
1450}
1451
1452static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1453{
1454 if (vmx->vm_exit_controls_shadow != val)
1455 vm_exit_controls_init(vmx, val);
1456}
1457
1458static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1459{
1460 return vmx->vm_exit_controls_shadow;
1461}
1462
1463
1464static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1465{
1466 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1467}
1468
1469static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1470{
1471 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1472}
1473
2fb92db1
AK		 1474static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1475{
1476 vmx->segment_cache.bitmask = 0;
1477}
1478
1479static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1480 unsigned field)
1481{
1482 bool ret;
1483 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1484
1485 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1486 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1487 vmx->segment_cache.bitmask = 0;
1488 }
1489 ret = vmx->segment_cache.bitmask & mask;
1490 vmx->segment_cache.bitmask |= mask;
1491 return ret;
1492}
1493
1494static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1495{
1496 u16 *p = &vmx->segment_cache.seg[seg].selector;
1497
1498 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1499 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1500 return *p;
1501}
1502
1503static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1504{
1505 ulong *p = &vmx->segment_cache.seg[seg].base;
1506
1507 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1508 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1509 return *p;
1510}
1511
1512static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1513{
1514 u32 *p = &vmx->segment_cache.seg[seg].limit;
1515
1516 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1517 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1518 return *p;
1519}
1520
1521static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1522{
1523 u32 *p = &vmx->segment_cache.seg[seg].ar;
1524
1525 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1526 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1527 return *p;
1528}
1529
abd3f2d6
AK		 1530static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1531{
1532 u32 eb;
1533
fd7373cc
JK		 1534 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1535 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1536 if ((vcpu->guest_debug &
1537 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1538 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1539 eb |= 1u << BP_VECTOR;
7ffd92c5 1540 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1541 eb = ~0;
089d034e 1542 if (enable_ept)
1439442c 1543 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1544 if (vcpu->fpu_active)
1545 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1546
1547 /* When we are running a nested L2 guest and L1 specified for it a
1548 * certain exception bitmap, we must trap the same exceptions and pass
1549 * them to L1. When running L2, we will only handle the exceptions
1550 * specified above if L1 did not want them.
1551 */
1552 if (is_guest_mode(vcpu))
1553 eb |= get_vmcs12(vcpu)->exception_bitmap;
1554
abd3f2d6
AK		 1555 vmcs_write32(EXCEPTION_BITMAP, eb);
1556}
1557
2961e876
GN		 1558static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1559 unsigned long entry, unsigned long exit)
8bf00a52 1560{
2961e876
GN		 1561 vm_entry_controls_clearbit(vmx, entry);
1562 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1563}
1564
61d2ef2c
AK		 1565static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1566{
1567 unsigned i;
1568 struct msr_autoload *m = &vmx->msr_autoload;
1569
8bf00a52
GN		 1570 switch (msr) {
1571 case MSR_EFER:
1572 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1573 clear_atomic_switch_msr_special(vmx,
1574 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1575 VM_EXIT_LOAD_IA32_EFER);
1576 return;
1577 }
1578 break;
1579 case MSR_CORE_PERF_GLOBAL_CTRL:
1580 if (cpu_has_load_perf_global_ctrl) {
2961e876 1581 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1582 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1583 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1584 return;
1585 }
1586 break;
110312c8
AK		 1587 }
1588
61d2ef2c
AK		 1589 for (i = 0; i < m->nr; ++i)
1590 if (m->guest[i].index == msr)
1591 break;
1592
1593 if (i == m->nr)
1594 return;
1595 --m->nr;
1596 m->guest[i] = m->guest[m->nr];
1597 m->host[i] = m->host[m->nr];
1598 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1599 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1600}
1601
2961e876
GN		 1602static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1603 unsigned long entry, unsigned long exit,
1604 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1605 u64 guest_val, u64 host_val)
8bf00a52
GN		 1606{
1607 vmcs_write64(guest_val_vmcs, guest_val);
1608 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1609 vm_entry_controls_setbit(vmx, entry);
1610 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1611}
1612
61d2ef2c
AK		 1613static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1614 u64 guest_val, u64 host_val)
1615{
1616 unsigned i;
1617 struct msr_autoload *m = &vmx->msr_autoload;
1618
8bf00a52
GN		 1619 switch (msr) {
1620 case MSR_EFER:
1621 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1622 add_atomic_switch_msr_special(vmx,
1623 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1624 VM_EXIT_LOAD_IA32_EFER,
1625 GUEST_IA32_EFER,
1626 HOST_IA32_EFER,
1627 guest_val, host_val);
1628 return;
1629 }
1630 break;
1631 case MSR_CORE_PERF_GLOBAL_CTRL:
1632 if (cpu_has_load_perf_global_ctrl) {
2961e876 1633 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1634 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1635 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1636 GUEST_IA32_PERF_GLOBAL_CTRL,
1637 HOST_IA32_PERF_GLOBAL_CTRL,
1638 guest_val, host_val);
1639 return;
1640 }
1641 break;
110312c8
AK		 1642 }
1643
61d2ef2c
AK		 1644 for (i = 0; i < m->nr; ++i)
1645 if (m->guest[i].index == msr)
1646 break;
1647
e7fc6f93 1648 if (i == NR_AUTOLOAD_MSRS) {
60266204 1649 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1650 "Can't add msr %x\n", msr);
1651 return;
1652 } else if (i == m->nr) {
61d2ef2c
AK		 1653 ++m->nr;
1654 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1655 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1656 }
1657
1658 m->guest[i].index = msr;
1659 m->guest[i].value = guest_val;
1660 m->host[i].index = msr;
1661 m->host[i].value = host_val;
1662}
1663
33ed6329
AK		 1664static void reload_tss(void)
1665{
33ed6329
AK		 1666 /*
1667 * VT restores TR but not its size. Useless.
1668 */
89cbc767 1669 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1670 struct desc_struct *descs;
33ed6329 1671
d359192f 1672 descs = (void *)gdt->address;
33ed6329
AK		 1673 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1674 load_TR_desc();
33ed6329
AK		 1675}
1676
92c0d900 1677static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1678{
3a34a881 1679 u64 guest_efer;
51c6cf66
AK		 1680 u64 ignore_bits;
1681
f6801dff 1682 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1683
51c6cf66 1684 /*
0fa06071 1685 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1686 * outside long mode
1687 */
1688 ignore_bits = EFER_NX | EFER_SCE;
1689#ifdef CONFIG_X86_64
1690 ignore_bits |= EFER_LMA | EFER_LME;
1691 /* SCE is meaningful only in long mode on Intel */
1692 if (guest_efer & EFER_LMA)
1693 ignore_bits &= ~(u64)EFER_SCE;
1694#endif
51c6cf66
AK		 1695 guest_efer &= ~ignore_bits;
1696 guest_efer |= host_efer & ignore_bits;
26bb0981 1697 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1698 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1699
1700 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1701
1702 /*
1703 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1704 * On CPUs that support "load IA32_EFER", always switch EFER
1705 * atomically, since it's faster than switching it manually.
1706 */
1707 if (cpu_has_load_ia32_efer ||
1708 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1709 guest_efer = vmx->vcpu.arch.efer;
1710 if (!(guest_efer & EFER_LMA))
1711 guest_efer &= ~EFER_LME;
54b98bff
AL		 1712 if (guest_efer != host_efer)
1713 add_atomic_switch_msr(vmx, MSR_EFER,
1714 guest_efer, host_efer);
84ad33ef
AK		 1715 return false;
1716 }
1717
26bb0981 1718 return true;
51c6cf66
AK		 1719}
1720
2d49ec72
GN		 1721static unsigned long segment_base(u16 selector)
1722{
89cbc767 1723 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1724 struct desc_struct *d;
1725 unsigned long table_base;
1726 unsigned long v;
1727
1728 if (!(selector & ~3))
1729 return 0;
1730
d359192f 1731 table_base = gdt->address;
2d49ec72
GN		 1732
1733 if (selector & 4) { /* from ldt */
1734 u16 ldt_selector = kvm_read_ldt();
1735
1736 if (!(ldt_selector & ~3))
1737 return 0;
1738
1739 table_base = segment_base(ldt_selector);
1740 }
1741 d = (struct desc_struct *)(table_base + (selector & ~7));
1742 v = get_desc_base(d);
1743#ifdef CONFIG_X86_64
1744 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1745 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1746#endif
1747 return v;
1748}
1749
1750static inline unsigned long kvm_read_tr_base(void)
1751{
1752 u16 tr;
1753 asm("str %0" : "=g"(tr));
1754 return segment_base(tr);
1755}
1756
04d2cc77 1757static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1758{
04d2cc77 1759 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1760 int i;
04d2cc77 1761
a2fa3e9f 1762 if (vmx->host_state.loaded)
33ed6329
AK		 1763 return;
1764
a2fa3e9f 1765 vmx->host_state.loaded = 1;
33ed6329
AK		 1766 /*
1767 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1768 * allow segment selectors with cpl > 0 or ti == 1.
1769 */
d6e88aec 1770 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1771 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1772 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1773 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1774 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1775 vmx->host_state.fs_reload_needed = 0;
1776 } else {
33ed6329 1777 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1778 vmx->host_state.fs_reload_needed = 1;
33ed6329 1779 }
9581d442 1780 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1781 if (!(vmx->host_state.gs_sel & 7))
1782 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1783 else {
1784 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1785 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1786 }
1787
b2da15ac
AK		 1788#ifdef CONFIG_X86_64
1789 savesegment(ds, vmx->host_state.ds_sel);
1790 savesegment(es, vmx->host_state.es_sel);
1791#endif
1792
33ed6329
AK		 1793#ifdef CONFIG_X86_64
1794 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1795 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1796#else
a2fa3e9f
GH		 1797 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1798 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1799#endif
707c0874
AK		 1800
1801#ifdef CONFIG_X86_64
c8770e7b
AK		 1802 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1803 if (is_long_mode(&vmx->vcpu))
44ea2b17 1804 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1805#endif
da8999d3
LJ		 1806 if (boot_cpu_has(X86_FEATURE_MPX))
1807 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1808 for (i = 0; i < vmx->save_nmsrs; ++i)
1809 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1810 vmx->guest_msrs[i].data,
1811 vmx->guest_msrs[i].mask);
33ed6329
AK		 1812}
1813
a9b21b62 1814static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1815{
a2fa3e9f 1816 if (!vmx->host_state.loaded)
33ed6329
AK		 1817 return;
1818
e1beb1d3 1819 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1820 vmx->host_state.loaded = 0;
c8770e7b
AK		 1821#ifdef CONFIG_X86_64
1822 if (is_long_mode(&vmx->vcpu))
1823 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1824#endif
152d3f2f 1825 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1826 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1827#ifdef CONFIG_X86_64
9581d442 1828 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1829#else
1830 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1831#endif
33ed6329 1832 }
0a77fe4c
AK		 1833 if (vmx->host_state.fs_reload_needed)
1834 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1835#ifdef CONFIG_X86_64
1836 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1837 loadsegment(ds, vmx->host_state.ds_sel);
1838 loadsegment(es, vmx->host_state.es_sel);
1839 }
b2da15ac 1840#endif
152d3f2f 1841 reload_tss();
44ea2b17 1842#ifdef CONFIG_X86_64
c8770e7b 1843 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1844#endif
da8999d3
LJ		 1845 if (vmx->host_state.msr_host_bndcfgs)
1846 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1847 /*
1848 * If the FPU is not active (through the host task or
1849 * the guest vcpu), then restore the cr0.TS bit.
1850 */
1851 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1852 stts();
89cbc767 1853 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1854}
1855
a9b21b62
AK		 1856static void vmx_load_host_state(struct vcpu_vmx *vmx)
1857{
1858 preempt_disable();
1859 __vmx_load_host_state(vmx);
1860 preempt_enable();
1861}
1862
6aa8b732
AK		 1863/*
1864 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1865 * vcpu mutex is already taken.
1866 */
15ad7146 1867static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1868{
a2fa3e9f 1869 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1870 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1871
4610c9cc
DX		 1872 if (!vmm_exclusive)
1873 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1874 else if (vmx->loaded_vmcs->cpu != cpu)
1875 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1876
d462b819
NHE		 1877 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1878 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1879 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1880 }
1881
d462b819 1882 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1883 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1884 unsigned long sysenter_esp;
1885
a8eeb04a 1886 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1887 local_irq_disable();
8f536b76 1888 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1889
1890 /*
1891 * Read loaded_vmcs->cpu should be before fetching
1892 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1893 * See the comments in __loaded_vmcs_clear().
1894 */
1895 smp_rmb();
1896
d462b819
NHE		 1897 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1898 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1899 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1900 local_irq_enable();
1901
6aa8b732
AK		 1902 /*
1903 * Linux uses per-cpu TSS and GDT, so set these when switching
1904 * processors.
1905 */
d6e88aec 1906 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1907 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1908
1909 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1910 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1911 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1912 }
6aa8b732
AK		 1913}
1914
1915static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1916{
a9b21b62 1917 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1918 if (!vmm_exclusive) {
d462b819
NHE		 1919 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1920 vcpu->cpu = -1;
4610c9cc
DX		 1921 kvm_cpu_vmxoff();
1922 }
6aa8b732
AK		 1923}
1924
5fd86fcf
AK		 1925static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1926{
81231c69
AK		 1927 ulong cr0;
1928
5fd86fcf
AK		 1929 if (vcpu->fpu_active)
1930 return;
1931 vcpu->fpu_active = 1;
81231c69
AK		 1932 cr0 = vmcs_readl(GUEST_CR0);
1933 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1934 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1935 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1936 update_exception_bitmap(vcpu);
edcafe3c 1937 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1938 if (is_guest_mode(vcpu))
1939 vcpu->arch.cr0_guest_owned_bits &=
1940 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1941 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1942}
1943
edcafe3c
AK		 1944static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1945
fe3ef05c
NHE		 1946/*
1947 * Return the cr0 value that a nested guest would read. This is a combination
1948 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1949 * its hypervisor (cr0_read_shadow).
1950 */
1951static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1952{
1953 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1954 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1955}
1956static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1957{
1958 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1959 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1960}
1961
5fd86fcf
AK		 1962static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1963{
36cf24e0
NHE		 1964 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1965 * set this *before* calling this function.
1966 */
edcafe3c 1967 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1968 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1969 update_exception_bitmap(vcpu);
edcafe3c
AK		 1970 vcpu->arch.cr0_guest_owned_bits = 0;
1971 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1972 if (is_guest_mode(vcpu)) {
1973 /*
1974 * L1's specified read shadow might not contain the TS bit,
1975 * so now that we turned on shadowing of this bit, we need to
1976 * set this bit of the shadow. Like in nested_vmx_run we need
1977 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1978 * up-to-date here because we just decached cr0.TS (and we'll
1979 * only update vmcs12->guest_cr0 on nested exit).
1980 */
1981 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1982 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1983 (vcpu->arch.cr0 & X86_CR0_TS);
1984 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1985 } else
1986 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1987}
1988
6aa8b732
AK		 1989static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1990{
78ac8b47 1991 unsigned long rflags, save_rflags;
345dcaa8 1992
6de12732
AK		 1993 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1994 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1995 rflags = vmcs_readl(GUEST_RFLAGS);
1996 if (to_vmx(vcpu)->rmode.vm86_active) {
1997 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1998 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1999 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2000 }
2001 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2002 }
6de12732 2003 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2004}
2005
2006static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2007{
6de12732
AK		 2008 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2009 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2010 if (to_vmx(vcpu)->rmode.vm86_active) {
2011 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2012 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2013 }
6aa8b732
AK		 2014 vmcs_writel(GUEST_RFLAGS, rflags);
2015}
2016
37ccdcbe 2017static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2018{
2019 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2020 int ret = 0;
2021
2022 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2023 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2024 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2025 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2026
37ccdcbe 2027 return ret;
2809f5d2
GC		 2028}
2029
2030static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2031{
2032 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2033 u32 interruptibility = interruptibility_old;
2034
2035 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2036
48005f64 2037 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2038 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2039 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2040 interruptibility |= GUEST_INTR_STATE_STI;
2041
2042 if ((interruptibility != interruptibility_old))
2043 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2044}
2045
6aa8b732
AK		 2046static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2047{
2048 unsigned long rip;
6aa8b732 2049
5fdbf976 2050 rip = kvm_rip_read(vcpu);
6aa8b732 2051 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2052 kvm_rip_write(vcpu, rip);
6aa8b732 2053
2809f5d2
GC		 2054 /* skipping an emulated instruction also counts */
2055 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2056}
2057
0b6ac343
NHE		 2058/*
2059 * KVM wants to inject page-faults which it got to the guest. This function
2060 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2061 */
e011c663 2062static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2063{
2064 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2065
e011c663 2066 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2067 return 0;
2068
533558bc
JK		 2069 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2070 vmcs_read32(VM_EXIT_INTR_INFO),
2071 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2072 return 1;
2073}
2074
298101da 2075static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2076 bool has_error_code, u32 error_code,
2077 bool reinject)
298101da 2078{
77ab6db0 2079 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2080 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2081
e011c663
GN		 2082 if (!reinject && is_guest_mode(vcpu) &&
2083 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2084 return;
2085
8ab2d2e2 2086 if (has_error_code) {
77ab6db0 2087 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2088 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2089 }
77ab6db0 2090
7ffd92c5 2091 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2092 int inc_eip = 0;
2093 if (kvm_exception_is_soft(nr))
2094 inc_eip = vcpu->arch.event_exit_inst_len;
2095 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2096 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2097 return;
2098 }
2099
66fd3f7f
GN		 2100 if (kvm_exception_is_soft(nr)) {
2101 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2102 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2103 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2104 } else
2105 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2106
2107 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2108}
2109
4e47c7a6
SY		 2110static bool vmx_rdtscp_supported(void)
2111{
2112 return cpu_has_vmx_rdtscp();
2113}
2114
ad756a16
MJ		 2115static bool vmx_invpcid_supported(void)
2116{
2117 return cpu_has_vmx_invpcid() && enable_ept;
2118}
2119
a75beee6
ED		 2120/*
2121 * Swap MSR entry in host/guest MSR entry array.
2122 */
8b9cf98c 2123static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2124{
26bb0981 2125 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2126
2127 tmp = vmx->guest_msrs[to];
2128 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2129 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2130}
2131
8d14695f
YZ		 2132static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2133{
2134 unsigned long *msr_bitmap;
2135
2136 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2137 if (is_long_mode(vcpu))
2138 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2139 else
2140 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2141 } else {
2142 if (is_long_mode(vcpu))
2143 msr_bitmap = vmx_msr_bitmap_longmode;
2144 else
2145 msr_bitmap = vmx_msr_bitmap_legacy;
2146 }
2147
2148 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2149}
2150
e38aea3e
AK		 2151/*
2152 * Set up the vmcs to automatically save and restore system
2153 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2154 * mode, as fiddling with msrs is very expensive.
2155 */
8b9cf98c 2156static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2157{
26bb0981 2158 int save_nmsrs, index;
e38aea3e 2159
a75beee6
ED		 2160 save_nmsrs = 0;
2161#ifdef CONFIG_X86_64
8b9cf98c 2162 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2163 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2164 if (index >= 0)
8b9cf98c
RR		 2165 move_msr_up(vmx, index, save_nmsrs++);
2166 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2167 if (index >= 0)
8b9cf98c
RR		 2168 move_msr_up(vmx, index, save_nmsrs++);
2169 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2170 if (index >= 0)
8b9cf98c 2171 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2172 index = __find_msr_index(vmx, MSR_TSC_AUX);
2173 if (index >= 0 && vmx->rdtscp_enabled)
2174 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2175 /*
8c06585d 2176 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2177 * if efer.sce is enabled.
2178 */
8c06585d 2179 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2180 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2181 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2182 }
2183#endif
92c0d900
AK		 2184 index = __find_msr_index(vmx, MSR_EFER);
2185 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2186 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2187
26bb0981 2188 vmx->save_nmsrs = save_nmsrs;
5897297b 2189
8d14695f
YZ		 2190 if (cpu_has_vmx_msr_bitmap())
2191 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2192}
2193
6aa8b732
AK		 2194/*
2195 * reads and returns guest's timestamp counter "register"
2196 * guest_tsc = host_tsc + tsc_offset -- 21.3
2197 */
2198static u64 guest_read_tsc(void)
2199{
2200 u64 host_tsc, tsc_offset;
2201
2202 rdtscll(host_tsc);
2203 tsc_offset = vmcs_read64(TSC_OFFSET);
2204 return host_tsc + tsc_offset;
2205}
2206
d5c1785d
NHE		 2207/*
2208 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2209 * counter, even if a nested guest (L2) is currently running.
2210 */
48d89b92 2211static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2212{
886b470c 2213 u64 tsc_offset;
d5c1785d 2214
d5c1785d
NHE		 2215 tsc_offset = is_guest_mode(vcpu) ?
2216 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2217 vmcs_read64(TSC_OFFSET);
2218 return host_tsc + tsc_offset;
2219}
2220
4051b188 2221/*
cc578287
ZA		 2222 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2223 * software catchup for faster rates on slower CPUs.
4051b188 2224 */
cc578287 2225static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2226{
cc578287
ZA		 2227 if (!scale)
2228 return;
2229
2230 if (user_tsc_khz > tsc_khz) {
2231 vcpu->arch.tsc_catchup = 1;
2232 vcpu->arch.tsc_always_catchup = 1;
2233 } else
2234 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2235}
2236
ba904635
WA		 2237static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2238{
2239 return vmcs_read64(TSC_OFFSET);
2240}
2241
6aa8b732 2242/*
99e3e30a 2243 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2244 */
99e3e30a 2245static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2246{
27fc51b2 2247 if (is_guest_mode(vcpu)) {
7991825b 2248 /*
27fc51b2
NHE		 2249 * We're here if L1 chose not to trap WRMSR to TSC. According
2250 * to the spec, this should set L1's TSC; The offset that L1
2251 * set for L2 remains unchanged, and still needs to be added
2252 * to the newly set TSC to get L2's TSC.
7991825b 2253 */
27fc51b2
NHE		 2254 struct vmcs12 *vmcs12;
2255 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2256 /* recalculate vmcs02.TSC_OFFSET: */
2257 vmcs12 = get_vmcs12(vcpu);
2258 vmcs_write64(TSC_OFFSET, offset +
2259 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2260 vmcs12->tsc_offset : 0));
2261 } else {
489223ed
YY		 2262 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2263 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2264 vmcs_write64(TSC_OFFSET, offset);
2265 }
6aa8b732
AK		 2266}
2267
f1e2b260 2268static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2269{
2270 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2271
e48672fa 2272 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2273 if (is_guest_mode(vcpu)) {
2274 /* Even when running L2, the adjustment needs to apply to L1 */
2275 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2276 } else
2277 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2278 offset + adjustment);
e48672fa
ZA		 2279}
2280
857e4099
JR		 2281static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2282{
2283 return target_tsc - native_read_tsc();
2284}
2285
801d3424
NHE		 2286static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2287{
2288 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2289 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2290}
2291
2292/*
2293 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2294 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2295 * all guests if the "nested" module option is off, and can also be disabled
2296 * for a single guest by disabling its VMX cpuid bit.
2297 */
2298static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2299{
2300 return nested && guest_cpuid_has_vmx(vcpu);
2301}
2302
b87a51ae
NHE		 2303/*
2304 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2305 * returned for the various VMX controls MSRs when nested VMX is enabled.
2306 * The same values should also be used to verify that vmcs12 control fields are
2307 * valid during nested entry from L1 to L2.
2308 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2309 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2310 * bit in the high half is on if the corresponding bit in the control field
2311 * may be on. See also vmx_control_verify().
b87a51ae 2312 */
b9c237bb 2313static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2314{
2315 /*
2316 * Note that as a general rule, the high half of the MSRs (bits in
2317 * the control fields which may be 1) should be initialized by the
2318 * intersection of the underlying hardware's MSR (i.e., features which
2319 * can be supported) and the list of features we want to expose -
2320 * because they are known to be properly supported in our code.
2321 * Also, usually, the low half of the MSRs (bits which must be 1) can
2322 * be set to 0, meaning that L1 may turn off any of these bits. The
2323 * reason is that if one of these bits is necessary, it will appear
2324 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2325 * fields of vmcs01 and vmcs02, will turn these bits off - and
2326 * nested_vmx_exit_handled() will not pass related exits to L1.
2327 * These rules have exceptions below.
2328 */
2329
2330 /* pin-based controls */
eabeaacc 2331 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2332 vmx->nested.nested_vmx_pinbased_ctls_low,
2333 vmx->nested.nested_vmx_pinbased_ctls_high);
2334 vmx->nested.nested_vmx_pinbased_ctls_low |=
2335 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2336 vmx->nested.nested_vmx_pinbased_ctls_high &=
2337 PIN_BASED_EXT_INTR_MASK |
2338 PIN_BASED_NMI_EXITING |
2339 PIN_BASED_VIRTUAL_NMIS;
2340 vmx->nested.nested_vmx_pinbased_ctls_high |=
2341 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2342 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2343
3dbcd8da 2344 /* exit controls */
c0dfee58 2345 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2346 vmx->nested.nested_vmx_exit_ctls_low,
2347 vmx->nested.nested_vmx_exit_ctls_high);
2348 vmx->nested.nested_vmx_exit_ctls_low =
2349 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2350
b9c237bb 2351 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2352#ifdef CONFIG_X86_64
c0dfee58 2353 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2354#endif
f4124500 2355 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2356 vmx->nested.nested_vmx_exit_ctls_high |=
2357 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2358 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2359 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2360
36be0b9d 2361 if (vmx_mpx_supported())
b9c237bb 2362 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2363
2996fca0 2364 /* We support free control of debug control saving. */
b9c237bb
WV		 2365 vmx->nested.nested_vmx_true_exit_ctls_low =
2366 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2367 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2368
b87a51ae
NHE		 2369 /* entry controls */
2370 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2371 vmx->nested.nested_vmx_entry_ctls_low,
2372 vmx->nested.nested_vmx_entry_ctls_high);
2373 vmx->nested.nested_vmx_entry_ctls_low =
2374 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2375 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2376#ifdef CONFIG_X86_64
2377 VM_ENTRY_IA32E_MODE |
2378#endif
2379 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2380 vmx->nested.nested_vmx_entry_ctls_high |=
2381 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2382 if (vmx_mpx_supported())
b9c237bb 2383 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2384
2996fca0 2385 /* We support free control of debug control loading. */
b9c237bb
WV		 2386 vmx->nested.nested_vmx_true_entry_ctls_low =
2387 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2388 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2389
b87a51ae
NHE		 2390 /* cpu-based controls */
2391 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2392 vmx->nested.nested_vmx_procbased_ctls_low,
2393 vmx->nested.nested_vmx_procbased_ctls_high);
2394 vmx->nested.nested_vmx_procbased_ctls_low =
2395 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2396 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2397 CPU_BASED_VIRTUAL_INTR_PENDING |
2398 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2399 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2400 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2401 CPU_BASED_CR3_STORE_EXITING |
2402#ifdef CONFIG_X86_64
2403 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2404#endif
2405 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2406 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2407 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2408 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2409 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2410 /*
2411 * We can allow some features even when not supported by the
2412 * hardware. For example, L1 can specify an MSR bitmap - and we
2413 * can use it to avoid exits to L1 - even when L0 runs L2
2414 * without MSR bitmaps.
2415 */
b9c237bb
WV		 2416 vmx->nested.nested_vmx_procbased_ctls_high |=
2417 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2418 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2419
3dcdf3ec 2420 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2421 vmx->nested.nested_vmx_true_procbased_ctls_low =
2422 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2423 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2424
b87a51ae
NHE		 2425 /* secondary cpu-based controls */
2426 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2427 vmx->nested.nested_vmx_secondary_ctls_low,
2428 vmx->nested.nested_vmx_secondary_ctls_high);
2429 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2430 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2431 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
f2b93280 2432 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
81dc01f7
WL		 2433 SECONDARY_EXEC_WBINVD_EXITING |
2434 SECONDARY_EXEC_XSAVES;
c18911a2 2435
afa61f75
NHE		 2436 if (enable_ept) {
2437 /* nested EPT: emulate EPT also to L1 */
b9c237bb
WV		 2438 vmx->nested.nested_vmx_secondary_ctls_high |=
2439 SECONDARY_EXEC_ENABLE_EPT |
78051e3b 2440 SECONDARY_EXEC_UNRESTRICTED_GUEST;
b9c237bb 2441 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2442 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2443 VMX_EPT_INVEPT_BIT;
b9c237bb 2444 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2445 /*
4b855078
BD		 2446 * For nested guests, we don't do anything specific
2447 * for single context invalidation. Hence, only advertise
2448 * support for global context invalidation.
afa61f75 2449 */
b9c237bb 2450 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2451 } else
b9c237bb 2452 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2453
c18911a2 2454 /* miscellaneous data */
b9c237bb
WV		 2455 rdmsr(MSR_IA32_VMX_MISC,
2456 vmx->nested.nested_vmx_misc_low,
2457 vmx->nested.nested_vmx_misc_high);
2458 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2459 vmx->nested.nested_vmx_misc_low |=
2460 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2461 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2462 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2463}
2464
2465static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2466{
2467 /*
2468 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2469 */
2470 return ((control & high) | low) == control;
2471}
2472
2473static inline u64 vmx_control_msr(u32 low, u32 high)
2474{
2475 return low | ((u64)high << 32);
2476}
2477
cae50139 2478/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2479static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2480{
b9c237bb
WV		 2481 struct vcpu_vmx *vmx = to_vmx(vcpu);
2482
b87a51ae 2483 switch (msr_index) {
b87a51ae
NHE		 2484 case MSR_IA32_VMX_BASIC:
2485 /*
2486 * This MSR reports some information about VMX support. We
2487 * should return information about the VMX we emulate for the
2488 * guest, and the VMCS structure we give it - not about the
2489 * VMX support of the underlying hardware.
2490 */
3dbcd8da 2491 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2492 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2493 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2494 break;
2495 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2496 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2497 *pdata = vmx_control_msr(
2498 vmx->nested.nested_vmx_pinbased_ctls_low,
2499 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2500 break;
2501 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2502 *pdata = vmx_control_msr(
2503 vmx->nested.nested_vmx_true_procbased_ctls_low,
2504 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2505 break;
b87a51ae 2506 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2507 *pdata = vmx_control_msr(
2508 vmx->nested.nested_vmx_procbased_ctls_low,
2509 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2510 break;
2511 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2512 *pdata = vmx_control_msr(
2513 vmx->nested.nested_vmx_true_exit_ctls_low,
2514 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2515 break;
b87a51ae 2516 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2517 *pdata = vmx_control_msr(
2518 vmx->nested.nested_vmx_exit_ctls_low,
2519 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2520 break;
2521 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2522 *pdata = vmx_control_msr(
2523 vmx->nested.nested_vmx_true_entry_ctls_low,
2524 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2525 break;
b87a51ae 2526 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2527 *pdata = vmx_control_msr(
2528 vmx->nested.nested_vmx_entry_ctls_low,
2529 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2530 break;
2531 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2532 *pdata = vmx_control_msr(
2533 vmx->nested.nested_vmx_misc_low,
2534 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2535 break;
2536 /*
2537 * These MSRs specify bits which the guest must keep fixed (on or off)
2538 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2539 * We picked the standard core2 setting.
2540 */
2541#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2542#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2543 case MSR_IA32_VMX_CR0_FIXED0:
2544 *pdata = VMXON_CR0_ALWAYSON;
2545 break;
2546 case MSR_IA32_VMX_CR0_FIXED1:
2547 *pdata = -1ULL;
2548 break;
2549 case MSR_IA32_VMX_CR4_FIXED0:
2550 *pdata = VMXON_CR4_ALWAYSON;
2551 break;
2552 case MSR_IA32_VMX_CR4_FIXED1:
2553 *pdata = -1ULL;
2554 break;
2555 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2556 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2557 break;
2558 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2559 *pdata = vmx_control_msr(
2560 vmx->nested.nested_vmx_secondary_ctls_low,
2561 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2562 break;
2563 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2564 /* Currently, no nested vpid support */
b9c237bb 2565 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2566 break;
2567 default:
b87a51ae 2568 return 1;
b3897a49
NHE		 2569 }
2570
b87a51ae
NHE		 2571 return 0;
2572}
2573
6aa8b732
AK		 2574/*
2575 * Reads an msr value (of 'msr_index') into 'pdata'.
2576 * Returns 0 on success, non-0 otherwise.
2577 * Assumes vcpu_load() was already called.
2578 */
2579static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2580{
2581 u64 data;
26bb0981 2582 struct shared_msr_entry *msr;
6aa8b732
AK		 2583
2584 if (!pdata) {
2585 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2586 return -EINVAL;
2587 }
2588
2589 switch (msr_index) {
05b3e0c2 2590#ifdef CONFIG_X86_64
6aa8b732
AK		 2591 case MSR_FS_BASE:
2592 data = vmcs_readl(GUEST_FS_BASE);
2593 break;
2594 case MSR_GS_BASE:
2595 data = vmcs_readl(GUEST_GS_BASE);
2596 break;
44ea2b17
AK		 2597 case MSR_KERNEL_GS_BASE:
2598 vmx_load_host_state(to_vmx(vcpu));
2599 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2600 break;
26bb0981 2601#endif
6aa8b732 2602 case MSR_EFER:
3bab1f5d 2603 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2604 case MSR_IA32_TSC:
6aa8b732
AK		 2605 data = guest_read_tsc();
2606 break;
2607 case MSR_IA32_SYSENTER_CS:
2608 data = vmcs_read32(GUEST_SYSENTER_CS);
2609 break;
2610 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2611 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2612 break;
2613 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2614 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2615 break;
0dd376e7 2616 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2617 if (!vmx_mpx_supported())
2618 return 1;
0dd376e7
LJ		 2619 data = vmcs_read64(GUEST_BNDCFGS);
2620 break;
cae50139
JK		 2621 case MSR_IA32_FEATURE_CONTROL:
2622 if (!nested_vmx_allowed(vcpu))
2623 return 1;
2624 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2625 break;
2626 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2627 if (!nested_vmx_allowed(vcpu))
2628 return 1;
2629 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2630 case MSR_IA32_XSS:
2631 if (!vmx_xsaves_supported())
2632 return 1;
2633 data = vcpu->arch.ia32_xss;
2634 break;
4e47c7a6
SY		 2635 case MSR_TSC_AUX:
2636 if (!to_vmx(vcpu)->rdtscp_enabled)
2637 return 1;
2638 /* Otherwise falls through */
6aa8b732 2639 default:
8b9cf98c 2640 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2641 if (msr) {
2642 data = msr->data;
2643 break;
6aa8b732 2644 }
3bab1f5d 2645 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2646 }
2647
2648 *pdata = data;
2649 return 0;
2650}
2651
cae50139
JK		 2652static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2653
6aa8b732
AK		 2654/*
2655 * Writes msr value into into the appropriate "register".
2656 * Returns 0 on success, non-0 otherwise.
2657 * Assumes vcpu_load() was already called.
2658 */
8fe8ab46 2659static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2660{
a2fa3e9f 2661 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2662 struct shared_msr_entry *msr;
2cc51560 2663 int ret = 0;
8fe8ab46
WA		 2664 u32 msr_index = msr_info->index;
2665 u64 data = msr_info->data;
2cc51560 2666
6aa8b732 2667 switch (msr_index) {
3bab1f5d 2668 case MSR_EFER:
8fe8ab46 2669 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2670 break;
16175a79 2671#ifdef CONFIG_X86_64
6aa8b732 2672 case MSR_FS_BASE:
2fb92db1 2673 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2674 vmcs_writel(GUEST_FS_BASE, data);
2675 break;
2676 case MSR_GS_BASE:
2fb92db1 2677 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2678 vmcs_writel(GUEST_GS_BASE, data);
2679 break;
44ea2b17
AK		 2680 case MSR_KERNEL_GS_BASE:
2681 vmx_load_host_state(vmx);
2682 vmx->msr_guest_kernel_gs_base = data;
2683 break;
6aa8b732
AK		 2684#endif
2685 case MSR_IA32_SYSENTER_CS:
2686 vmcs_write32(GUEST_SYSENTER_CS, data);
2687 break;
2688 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2689 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2690 break;
2691 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2692 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2693 break;
0dd376e7 2694 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2695 if (!vmx_mpx_supported())
2696 return 1;
0dd376e7
LJ		 2697 vmcs_write64(GUEST_BNDCFGS, data);
2698 break;
af24a4e4 2699 case MSR_IA32_TSC:
8fe8ab46 2700 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2701 break;
468d472f
SY		 2702 case MSR_IA32_CR_PAT:
2703 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2704 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2705 return 1;
468d472f
SY		 2706 vmcs_write64(GUEST_IA32_PAT, data);
2707 vcpu->arch.pat = data;
2708 break;
2709 }
8fe8ab46 2710 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2711 break;
ba904635
WA		 2712 case MSR_IA32_TSC_ADJUST:
2713 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2714 break;
cae50139
JK		 2715 case MSR_IA32_FEATURE_CONTROL:
2716 if (!nested_vmx_allowed(vcpu) ||
2717 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2718 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2719 return 1;
2720 vmx->nested.msr_ia32_feature_control = data;
2721 if (msr_info->host_initiated && data == 0)
2722 vmx_leave_nested(vcpu);
2723 break;
2724 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2725 return 1; /* they are read-only */
20300099
WL		 2726 case MSR_IA32_XSS:
2727 if (!vmx_xsaves_supported())
2728 return 1;
2729 /*
2730 * The only supported bit as of Skylake is bit 8, but
2731 * it is not supported on KVM.
2732 */
2733 if (data != 0)
2734 return 1;
2735 vcpu->arch.ia32_xss = data;
2736 if (vcpu->arch.ia32_xss != host_xss)
2737 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2738 vcpu->arch.ia32_xss, host_xss);
2739 else
2740 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2741 break;
4e47c7a6
SY		 2742 case MSR_TSC_AUX:
2743 if (!vmx->rdtscp_enabled)
2744 return 1;
2745 /* Check reserved bit, higher 32 bits should be zero */
2746 if ((data >> 32) != 0)
2747 return 1;
2748 /* Otherwise falls through */
6aa8b732 2749 default:
8b9cf98c 2750 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2751 if (msr) {
8b3c3104 2752 u64 old_msr_data = msr->data;
3bab1f5d 2753 msr->data = data;
2225fd56
AK		 2754 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2755 preempt_disable();
8b3c3104
AH		 2756 ret = kvm_set_shared_msr(msr->index, msr->data,
2757 msr->mask);
2225fd56 2758 preempt_enable();
8b3c3104
AH		 2759 if (ret)
2760 msr->data = old_msr_data;
2225fd56 2761 }
3bab1f5d 2762 break;
6aa8b732 2763 }
8fe8ab46 2764 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2765 }
2766
2cc51560 2767 return ret;
6aa8b732
AK		 2768}
2769
5fdbf976 2770static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2771{
5fdbf976
MT		 2772 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2773 switch (reg) {
2774 case VCPU_REGS_RSP:
2775 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2776 break;
2777 case VCPU_REGS_RIP:
2778 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2779 break;
6de4f3ad
AK		 2780 case VCPU_EXREG_PDPTR:
2781 if (enable_ept)
2782 ept_save_pdptrs(vcpu);
2783 break;
5fdbf976
MT		 2784 default:
2785 break;
2786 }
6aa8b732
AK		 2787}
2788
6aa8b732
AK		 2789static __init int cpu_has_kvm_support(void)
2790{
6210e37b 2791 return cpu_has_vmx();
6aa8b732
AK		 2792}
2793
2794static __init int vmx_disabled_by_bios(void)
2795{
2796 u64 msr;
2797
2798 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2799 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2800 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2801 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2802 && tboot_enabled())
2803 return 1;
23f3e991 2804 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2805 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2806 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2807 && !tboot_enabled()) {
2808 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2809 "activate TXT before enabling KVM\n");
cafd6659 2810 return 1;
f9335afe 2811 }
23f3e991
JC		 2812 /* launched w/o TXT and VMX disabled */
2813 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2814 && !tboot_enabled())
2815 return 1;
cafd6659
SW		 2816 }
2817
2818 return 0;
6aa8b732
AK		 2819}
2820
7725b894
DX		 2821static void kvm_cpu_vmxon(u64 addr)
2822{
2823 asm volatile (ASM_VMX_VMXON_RAX
2824 : : "a"(&addr), "m"(addr)
2825 : "memory", "cc");
2826}
2827
13a34e06 2828static int hardware_enable(void)
6aa8b732
AK		 2829{
2830 int cpu = raw_smp_processor_id();
2831 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2832 u64 old, test_bits;
6aa8b732 2833
10474ae8
AG		 2834 if (read_cr4() & X86_CR4_VMXE)
2835 return -EBUSY;
2836
d462b819 2837 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2838
2839 /*
2840 * Now we can enable the vmclear operation in kdump
2841 * since the loaded_vmcss_on_cpu list on this cpu
2842 * has been initialized.
2843 *
2844 * Though the cpu is not in VMX operation now, there
2845 * is no problem to enable the vmclear operation
2846 * for the loaded_vmcss_on_cpu list is empty!
2847 */
2848 crash_enable_local_vmclear(cpu);
2849
6aa8b732 2850 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2851
2852 test_bits = FEATURE_CONTROL_LOCKED;
2853 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2854 if (tboot_enabled())
2855 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2856
2857 if ((old & test_bits) != test_bits) {
6aa8b732 2858 /* enable and lock */
cafd6659
SW		 2859 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2860 }
66aee91a 2861 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2862
4610c9cc
DX		 2863 if (vmm_exclusive) {
2864 kvm_cpu_vmxon(phys_addr);
2865 ept_sync_global();
2866 }
10474ae8 2867
89cbc767 2868 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2869
10474ae8 2870 return 0;
6aa8b732
AK		 2871}
2872
d462b819 2873static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2874{
2875 int cpu = raw_smp_processor_id();
d462b819 2876 struct loaded_vmcs *v, *n;
543e4243 2877
d462b819
NHE		 2878 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2879 loaded_vmcss_on_cpu_link)
2880 __loaded_vmcs_clear(v);
543e4243
AK		 2881}
2882
710ff4a8
EH		 2883
2884/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2885 * tricks.
2886 */
2887static void kvm_cpu_vmxoff(void)
6aa8b732 2888{
4ecac3fd 2889 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2890}
2891
13a34e06 2892static void hardware_disable(void)
710ff4a8 2893{
4610c9cc 2894 if (vmm_exclusive) {
d462b819 2895 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2896 kvm_cpu_vmxoff();
2897 }
7725b894 2898 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2899}
2900
1c3d14fe 2901static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2902 u32 msr, u32 *result)
1c3d14fe
YS		 2903{
2904 u32 vmx_msr_low, vmx_msr_high;
2905 u32 ctl = ctl_min | ctl_opt;
2906
2907 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2908
2909 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2910 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2911
2912 /* Ensure minimum (required) set of control bits are supported. */
2913 if (ctl_min & ~ctl)
002c7f7c 2914 return -EIO;
1c3d14fe
YS		 2915
2916 *result = ctl;
2917 return 0;
2918}
2919
110312c8
AK		 2920static __init bool allow_1_setting(u32 msr, u32 ctl)
2921{
2922 u32 vmx_msr_low, vmx_msr_high;
2923
2924 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2925 return vmx_msr_high & ctl;
2926}
2927
002c7f7c 2928static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2929{
2930 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2931 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2932 u32 _pin_based_exec_control = 0;
2933 u32 _cpu_based_exec_control = 0;
f78e0e2e 2934 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2935 u32 _vmexit_control = 0;
2936 u32 _vmentry_control = 0;
2937
10166744 2938 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2939#ifdef CONFIG_X86_64
2940 CPU_BASED_CR8_LOAD_EXITING |
2941 CPU_BASED_CR8_STORE_EXITING |
2942#endif
d56f546d
SY		 2943 CPU_BASED_CR3_LOAD_EXITING |
2944 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2945 CPU_BASED_USE_IO_BITMAPS |
2946 CPU_BASED_MOV_DR_EXITING |
a7052897 2947 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2948 CPU_BASED_MWAIT_EXITING |
2949 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2950 CPU_BASED_INVLPG_EXITING |
2951 CPU_BASED_RDPMC_EXITING;
443381a8 2952
f78e0e2e 2953 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2954 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2955 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2956 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2957 &_cpu_based_exec_control) < 0)
002c7f7c 2958 return -EIO;
6e5d865c
YS		 2959#ifdef CONFIG_X86_64
2960 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2961 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2962 ~CPU_BASED_CR8_STORE_EXITING;
2963#endif
f78e0e2e 2964 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2965 min2 = 0;
2966 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2967 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2968 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2969 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2970 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2971 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2972 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2973 SECONDARY_EXEC_RDTSCP |
83d4c286 2974 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2975 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2976 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2977 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 2978 SECONDARY_EXEC_XSAVES |
2979 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 2980 if (adjust_vmx_controls(min2, opt2,
2981 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2982 &_cpu_based_2nd_exec_control) < 0)
2983 return -EIO;
2984 }
2985#ifndef CONFIG_X86_64
2986 if (!(_cpu_based_2nd_exec_control &
2987 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2988 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2989#endif
83d4c286
YZ		 2990
2991 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2992 _cpu_based_2nd_exec_control &= ~(
8d14695f 2993 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2994 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2995 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2996
d56f546d 2997 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2998 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2999 enabled */
5fff7d27
GN		 3000 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3001 CPU_BASED_CR3_STORE_EXITING |
3002 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3003 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3004 vmx_capability.ept, vmx_capability.vpid);
3005 }
1c3d14fe 3006
81908bf4 3007 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3008#ifdef CONFIG_X86_64
3009 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3010#endif
a547c6db 3011 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3012 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3013 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3014 &_vmexit_control) < 0)
002c7f7c 3015 return -EIO;
1c3d14fe 3016
01e439be
YZ		 3017 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3018 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3019 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3020 &_pin_based_exec_control) < 0)
3021 return -EIO;
3022
3023 if (!(_cpu_based_2nd_exec_control &
3024 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3025 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3026 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3027
c845f9c6 3028 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3029 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3030 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3031 &_vmentry_control) < 0)
002c7f7c 3032 return -EIO;
6aa8b732 3033
c68876fd 3034 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3035
3036 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3037 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3038 return -EIO;
1c3d14fe
YS		 3039
3040#ifdef CONFIG_X86_64
3041 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3042 if (vmx_msr_high & (1u<<16))
002c7f7c 3043 return -EIO;
1c3d14fe
YS		 3044#endif
3045
3046 /* Require Write-Back (WB) memory type for VMCS accesses. */
3047 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3048 return -EIO;
1c3d14fe 3049
002c7f7c
YS		 3050 vmcs_conf->size = vmx_msr_high & 0x1fff;
3051 vmcs_conf->order = get_order(vmcs_config.size);
3052 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3053
002c7f7c
YS		 3054 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3055 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3056 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3057 vmcs_conf->vmexit_ctrl = _vmexit_control;
3058 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3059
110312c8
AK		 3060 cpu_has_load_ia32_efer =
3061 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3062 VM_ENTRY_LOAD_IA32_EFER)
3063 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3064 VM_EXIT_LOAD_IA32_EFER);
3065
8bf00a52
GN		 3066 cpu_has_load_perf_global_ctrl =
3067 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3068 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3069 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3070 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3071
3072 /*
3073 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3074 * but due to arrata below it can't be used. Workaround is to use
3075 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3076 *
3077 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3078 *
3079 * AAK155 (model 26)
3080 * AAP115 (model 30)
3081 * AAT100 (model 37)
3082 * BC86,AAY89,BD102 (model 44)
3083 * BA97 (model 46)
3084 *
3085 */
3086 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3087 switch (boot_cpu_data.x86_model) {
3088 case 26:
3089 case 30:
3090 case 37:
3091 case 44:
3092 case 46:
3093 cpu_has_load_perf_global_ctrl = false;
3094 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3095 "does not work properly. Using workaround\n");
3096 break;
3097 default:
3098 break;
3099 }
3100 }
3101
20300099
WL		 3102 if (cpu_has_xsaves)
3103 rdmsrl(MSR_IA32_XSS, host_xss);
3104
1c3d14fe 3105 return 0;
c68876fd 3106}
6aa8b732
AK		 3107
3108static struct vmcs *alloc_vmcs_cpu(int cpu)
3109{
3110 int node = cpu_to_node(cpu);
3111 struct page *pages;
3112 struct vmcs *vmcs;
3113
6484eb3e 3114 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3115 if (!pages)
3116 return NULL;
3117 vmcs = page_address(pages);
1c3d14fe
YS		 3118 memset(vmcs, 0, vmcs_config.size);
3119 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3120 return vmcs;
3121}
3122
3123static struct vmcs *alloc_vmcs(void)
3124{
d3b2c338 3125 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3126}
3127
3128static void free_vmcs(struct vmcs *vmcs)
3129{
1c3d14fe 3130 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3131}
3132
d462b819
NHE		 3133/*
3134 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3135 */
3136static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3137{
3138 if (!loaded_vmcs->vmcs)
3139 return;
3140 loaded_vmcs_clear(loaded_vmcs);
3141 free_vmcs(loaded_vmcs->vmcs);
3142 loaded_vmcs->vmcs = NULL;
3143}
3144
39959588 3145static void free_kvm_area(void)
6aa8b732
AK		 3146{
3147 int cpu;
3148
3230bb47 3149 for_each_possible_cpu(cpu) {
6aa8b732 3150 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3151 per_cpu(vmxarea, cpu) = NULL;
3152 }
6aa8b732
AK		 3153}
3154
fe2b201b
BD		 3155static void init_vmcs_shadow_fields(void)
3156{
3157 int i, j;
3158
3159 /* No checks for read only fields yet */
3160
3161 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3162 switch (shadow_read_write_fields[i]) {
3163 case GUEST_BNDCFGS:
3164 if (!vmx_mpx_supported())
3165 continue;
3166 break;
3167 default:
3168 break;
3169 }
3170
3171 if (j < i)
3172 shadow_read_write_fields[j] =
3173 shadow_read_write_fields[i];
3174 j++;
3175 }
3176 max_shadow_read_write_fields = j;
3177
3178 /* shadowed fields guest access without vmexit */
3179 for (i = 0; i < max_shadow_read_write_fields; i++) {
3180 clear_bit(shadow_read_write_fields[i],
3181 vmx_vmwrite_bitmap);
3182 clear_bit(shadow_read_write_fields[i],
3183 vmx_vmread_bitmap);
3184 }
3185 for (i = 0; i < max_shadow_read_only_fields; i++)
3186 clear_bit(shadow_read_only_fields[i],
3187 vmx_vmread_bitmap);
3188}
3189
6aa8b732
AK		 3190static __init int alloc_kvm_area(void)
3191{
3192 int cpu;
3193
3230bb47 3194 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3195 struct vmcs *vmcs;
3196
3197 vmcs = alloc_vmcs_cpu(cpu);
3198 if (!vmcs) {
3199 free_kvm_area();
3200 return -ENOMEM;
3201 }
3202
3203 per_cpu(vmxarea, cpu) = vmcs;
3204 }
3205 return 0;
3206}
3207
14168786
GN		 3208static bool emulation_required(struct kvm_vcpu *vcpu)
3209{
3210 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3211}
3212
91b0aa2c 3213static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3214 struct kvm_segment *save)
6aa8b732 3215{
d99e4152
GN		 3216 if (!emulate_invalid_guest_state) {
3217 /*
3218 * CS and SS RPL should be equal during guest entry according
3219 * to VMX spec, but in reality it is not always so. Since vcpu
3220 * is in the middle of the transition from real mode to
3221 * protected mode it is safe to assume that RPL 0 is a good
3222 * default value.
3223 */
3224 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3225 save->selector &= ~SELECTOR_RPL_MASK;
3226 save->dpl = save->selector & SELECTOR_RPL_MASK;
3227 save->s = 1;
6aa8b732 3228 }
d99e4152 3229 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3230}
3231
3232static void enter_pmode(struct kvm_vcpu *vcpu)
3233{
3234 unsigned long flags;
a89a8fb9 3235 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3236
d99e4152
GN		 3237 /*
3238 * Update real mode segment cache. It may be not up-to-date if sement
3239 * register was written while vcpu was in a guest mode.
3240 */
3241 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3242 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3243 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3244 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3245 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3246 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3247
7ffd92c5 3248 vmx->rmode.vm86_active = 0;
6aa8b732 3249
2fb92db1
AK		 3250 vmx_segment_cache_clear(vmx);
3251
f5f7b2fe 3252 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3253
3254 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3255 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3256 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3257 vmcs_writel(GUEST_RFLAGS, flags);
3258
66aee91a
RR		 3259 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3260 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3261
3262 update_exception_bitmap(vcpu);
3263
91b0aa2c
GN		 3264 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3265 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3266 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3267 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3268 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3269 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3270}
3271
f5f7b2fe 3272static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3273{
772e0318 3274 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3275 struct kvm_segment var = *save;
3276
3277 var.dpl = 0x3;
3278 if (seg == VCPU_SREG_CS)
3279 var.type = 0x3;
3280
3281 if (!emulate_invalid_guest_state) {
3282 var.selector = var.base >> 4;
3283 var.base = var.base & 0xffff0;
3284 var.limit = 0xffff;
3285 var.g = 0;
3286 var.db = 0;
3287 var.present = 1;
3288 var.s = 1;
3289 var.l = 0;
3290 var.unusable = 0;
3291 var.type = 0x3;
3292 var.avl = 0;
3293 if (save->base & 0xf)
3294 printk_once(KERN_WARNING "kvm: segment base is not "
3295 "paragraph aligned when entering "
3296 "protected mode (seg=%d)", seg);
3297 }
6aa8b732 3298
d99e4152
GN		 3299 vmcs_write16(sf->selector, var.selector);
3300 vmcs_write32(sf->base, var.base);
3301 vmcs_write32(sf->limit, var.limit);
3302 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3303}
3304
3305static void enter_rmode(struct kvm_vcpu *vcpu)
3306{
3307 unsigned long flags;
a89a8fb9 3308 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3309
f5f7b2fe
AK		 3310 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3311 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3312 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3313 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3314 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3315 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3316 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3317
7ffd92c5 3318 vmx->rmode.vm86_active = 1;
6aa8b732 3319
776e58ea
GN		 3320 /*
3321 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3322 * vcpu. Warn the user that an update is overdue.
776e58ea 3323 */
4918c6ca 3324 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3325 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3326 "called before entering vcpu\n");
776e58ea 3327
2fb92db1
AK		 3328 vmx_segment_cache_clear(vmx);
3329
4918c6ca 3330 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3331 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3332 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3333
3334 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3335 vmx->rmode.save_rflags = flags;
6aa8b732 3336
053de044 3337 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3338
3339 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3340 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3341 update_exception_bitmap(vcpu);
3342
d99e4152
GN		 3343 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3344 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3345 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3346 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3347 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3348 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3349
8668a3c4 3350 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3351}
3352
401d10de
AS		 3353static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3354{
3355 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3356 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3357
3358 if (!msr)
3359 return;
401d10de 3360
44ea2b17
AK		 3361 /*
3362 * Force kernel_gs_base reloading before EFER changes, as control
3363 * of this msr depends on is_long_mode().
3364 */
3365 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3366 vcpu->arch.efer = efer;
401d10de 3367 if (efer & EFER_LMA) {
2961e876 3368 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3369 msr->data = efer;
3370 } else {
2961e876 3371 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3372
3373 msr->data = efer & ~EFER_LME;
3374 }
3375 setup_msrs(vmx);
3376}
3377
05b3e0c2 3378#ifdef CONFIG_X86_64
6aa8b732
AK		 3379
3380static void enter_lmode(struct kvm_vcpu *vcpu)
3381{
3382 u32 guest_tr_ar;
3383
2fb92db1
AK		 3384 vmx_segment_cache_clear(to_vmx(vcpu));
3385
6aa8b732
AK		 3386 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3387 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3388 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3389 __func__);
6aa8b732
AK		 3390 vmcs_write32(GUEST_TR_AR_BYTES,
3391 (guest_tr_ar & ~AR_TYPE_MASK)
3392 | AR_TYPE_BUSY_64_TSS);
3393 }
da38f438 3394 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3395}
3396
3397static void exit_lmode(struct kvm_vcpu *vcpu)
3398{
2961e876 3399 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3400 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3401}
3402
3403#endif
3404
2384d2b3
SY		 3405static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3406{
b9d762fa 3407 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3408 if (enable_ept) {
3409 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3410 return;
4e1096d2 3411 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3412 }
2384d2b3
SY		 3413}
3414
e8467fda
AK		 3415static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3416{
3417 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3418
3419 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3420 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3421}
3422
aff48baa
AK		 3423static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3424{
3425 if (enable_ept && is_paging(vcpu))
3426 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3427 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3428}
3429
25c4c276 3430static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3431{
fc78f519
AK		 3432 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3433
3434 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3435 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3436}
3437
1439442c
SY		 3438static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3439{
d0d538b9
GN		 3440 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3441
6de4f3ad
AK		 3442 if (!test_bit(VCPU_EXREG_PDPTR,
3443 (unsigned long *)&vcpu->arch.regs_dirty))
3444 return;
3445
1439442c 3446 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3447 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3448 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3449 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3450 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3451 }
3452}
3453
8f5d549f
AK		 3454static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3455{
d0d538b9
GN		 3456 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3457
8f5d549f 3458 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3459 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3460 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3461 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3462 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3463 }
6de4f3ad
AK		 3464
3465 __set_bit(VCPU_EXREG_PDPTR,
3466 (unsigned long *)&vcpu->arch.regs_avail);
3467 __set_bit(VCPU_EXREG_PDPTR,
3468 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3469}
3470
5e1746d6 3471static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3472
3473static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3474 unsigned long cr0,
3475 struct kvm_vcpu *vcpu)
3476{
5233dd51
MT		 3477 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3478 vmx_decache_cr3(vcpu);
1439442c
SY		 3479 if (!(cr0 & X86_CR0_PG)) {
3480 /* From paging/starting to nonpaging */
3481 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3482 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3483 (CPU_BASED_CR3_LOAD_EXITING |
3484 CPU_BASED_CR3_STORE_EXITING));
3485 vcpu->arch.cr0 = cr0;
fc78f519 3486 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3487 } else if (!is_paging(vcpu)) {
3488 /* From nonpaging to paging */
3489 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3490 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3491 ~(CPU_BASED_CR3_LOAD_EXITING |
3492 CPU_BASED_CR3_STORE_EXITING));
3493 vcpu->arch.cr0 = cr0;
fc78f519 3494 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3495 }
95eb84a7
SY		 3496
3497 if (!(cr0 & X86_CR0_WP))
3498 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3499}
3500
6aa8b732
AK		 3501static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3502{
7ffd92c5 3503 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3504 unsigned long hw_cr0;
3505
5037878e 3506 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3507 if (enable_unrestricted_guest)
5037878e 3508 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3509 else {
5037878e 3510 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3511
218e763f
GN		 3512 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3513 enter_pmode(vcpu);
6aa8b732 3514
218e763f
GN		 3515 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3516 enter_rmode(vcpu);
3517 }
6aa8b732 3518
05b3e0c2 3519#ifdef CONFIG_X86_64
f6801dff 3520 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3521 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3522 enter_lmode(vcpu);
707d92fa 3523 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3524 exit_lmode(vcpu);
3525 }
3526#endif
3527
089d034e 3528 if (enable_ept)
1439442c
SY		 3529 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3530
02daab21 3531 if (!vcpu->fpu_active)
81231c69 3532 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3533
6aa8b732 3534 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3535 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3536 vcpu->arch.cr0 = cr0;
14168786
GN		 3537
3538 /* depends on vcpu->arch.cr0 to be set to a new value */
3539 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3540}
3541
1439442c
SY		 3542static u64 construct_eptp(unsigned long root_hpa)
3543{
3544 u64 eptp;
3545
3546 /* TODO write the value reading from MSR */
3547 eptp = VMX_EPT_DEFAULT_MT |
3548 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3549 if (enable_ept_ad_bits)
3550 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3551 eptp |= (root_hpa & PAGE_MASK);
3552
3553 return eptp;
3554}
3555
6aa8b732
AK		 3556static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3557{
1439442c
SY		 3558 unsigned long guest_cr3;
3559 u64 eptp;
3560
3561 guest_cr3 = cr3;
089d034e 3562 if (enable_ept) {
1439442c
SY		 3563 eptp = construct_eptp(cr3);
3564 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3565 if (is_paging(vcpu) || is_guest_mode(vcpu))
3566 guest_cr3 = kvm_read_cr3(vcpu);
3567 else
3568 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3569 ept_load_pdptrs(vcpu);
1439442c
SY		 3570 }
3571
2384d2b3 3572 vmx_flush_tlb(vcpu);
1439442c 3573 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3574}
3575
5e1746d6 3576static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3577{
7ffd92c5 3578 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3579 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3580
5e1746d6
NHE		 3581 if (cr4 & X86_CR4_VMXE) {
3582 /*
3583 * To use VMXON (and later other VMX instructions), a guest
3584 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3585 * So basically the check on whether to allow nested VMX
3586 * is here.
3587 */
3588 if (!nested_vmx_allowed(vcpu))
3589 return 1;
1a0d74e6
JK		 3590 }
3591 if (to_vmx(vcpu)->nested.vmxon &&
3592 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3593 return 1;
3594
ad312c7c 3595 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3596 if (enable_ept) {
3597 if (!is_paging(vcpu)) {
3598 hw_cr4 &= ~X86_CR4_PAE;
3599 hw_cr4 |= X86_CR4_PSE;
c08800a5 3600 /*
e1e746b3
FW		 3601 * SMEP/SMAP is disabled if CPU is in non-paging mode
3602 * in hardware. However KVM always uses paging mode to
c08800a5 3603 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3604 * To emulate this behavior, SMEP/SMAP needs to be
3605 * manually disabled when guest switches to non-paging
3606 * mode.
c08800a5 3607 */
e1e746b3 3608 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3609 } else if (!(cr4 & X86_CR4_PAE)) {
3610 hw_cr4 &= ~X86_CR4_PAE;
3611 }
3612 }
1439442c
SY		 3613
3614 vmcs_writel(CR4_READ_SHADOW, cr4);
3615 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3616 return 0;
6aa8b732
AK		 3617}
3618
6aa8b732
AK		 3619static void vmx_get_segment(struct kvm_vcpu *vcpu,
3620 struct kvm_segment *var, int seg)
3621{
a9179499 3622 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3623 u32 ar;
3624
c6ad1153 3625 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3626 *var = vmx->rmode.segs[seg];
a9179499 3627 if (seg == VCPU_SREG_TR
2fb92db1 3628 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3629 return;
1390a28b
AK		 3630 var->base = vmx_read_guest_seg_base(vmx, seg);
3631 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3632 return;
a9179499 3633 }
2fb92db1
AK		 3634 var->base = vmx_read_guest_seg_base(vmx, seg);
3635 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3636 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3637 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3638 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3639 var->type = ar & 15;
3640 var->s = (ar >> 4) & 1;
3641 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3642 /*
3643 * Some userspaces do not preserve unusable property. Since usable
3644 * segment has to be present according to VMX spec we can use present
3645 * property to amend userspace bug by making unusable segment always
3646 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3647 * segment as unusable.
3648 */
3649 var->present = !var->unusable;
6aa8b732
AK		 3650 var->avl = (ar >> 12) & 1;
3651 var->l = (ar >> 13) & 1;
3652 var->db = (ar >> 14) & 1;
3653 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3654}
3655
a9179499
AK		 3656static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3657{
a9179499
AK		 3658 struct kvm_segment s;
3659
3660 if (to_vmx(vcpu)->rmode.vm86_active) {
3661 vmx_get_segment(vcpu, &s, seg);
3662 return s.base;
3663 }
2fb92db1 3664 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3665}
3666
b09408d0 3667static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3668{
b09408d0
MT		 3669 struct vcpu_vmx *vmx = to_vmx(vcpu);
3670
ae9fedc7 3671 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3672 return 0;
ae9fedc7
PB		 3673 else {
3674 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3675 return AR_DPL(ar);
69c73028 3676 }
69c73028
AK		 3677}
3678
653e3108 3679static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3680{
6aa8b732
AK		 3681 u32 ar;
3682
f0495f9b 3683 if (var->unusable || !var->present)
6aa8b732
AK		 3684 ar = 1 << 16;
3685 else {
3686 ar = var->type & 15;
3687 ar |= (var->s & 1) << 4;
3688 ar |= (var->dpl & 3) << 5;
3689 ar |= (var->present & 1) << 7;
3690 ar |= (var->avl & 1) << 12;
3691 ar |= (var->l & 1) << 13;
3692 ar |= (var->db & 1) << 14;
3693 ar |= (var->g & 1) << 15;
3694 }
653e3108
AK		 3695
3696 return ar;
3697}
3698
3699static void vmx_set_segment(struct kvm_vcpu *vcpu,
3700 struct kvm_segment *var, int seg)
3701{
7ffd92c5 3702 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3703 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3704
2fb92db1
AK		 3705 vmx_segment_cache_clear(vmx);
3706
1ecd50a9
GN		 3707 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3708 vmx->rmode.segs[seg] = *var;
3709 if (seg == VCPU_SREG_TR)
3710 vmcs_write16(sf->selector, var->selector);
3711 else if (var->s)
3712 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3713 goto out;
653e3108 3714 }
1ecd50a9 3715
653e3108
AK		 3716 vmcs_writel(sf->base, var->base);
3717 vmcs_write32(sf->limit, var->limit);
3718 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3719
3720 /*
3721 * Fix the "Accessed" bit in AR field of segment registers for older
3722 * qemu binaries.
3723 * IA32 arch specifies that at the time of processor reset the
3724 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3725 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3726 * state vmexit when "unrestricted guest" mode is turned on.
3727 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3728 * tree. Newer qemu binaries with that qemu fix would not need this
3729 * kvm hack.
3730 */
3731 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3732 var->type |= 0x1; /* Accessed */
3a624e29 3733
f924d66d 3734 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3735
3736out:
98eb2f8b 3737 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3738}
3739
6aa8b732
AK		 3740static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3741{
2fb92db1 3742 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3743
3744 *db = (ar >> 14) & 1;
3745 *l = (ar >> 13) & 1;
3746}
3747
89a27f4d 3748static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3749{
89a27f4d
GN		 3750 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3751 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3752}
3753
89a27f4d 3754static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3755{
89a27f4d
GN		 3756 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3757 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3758}
3759
89a27f4d 3760static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3761{
89a27f4d
GN		 3762 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3763 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3764}
3765
89a27f4d 3766static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3767{
89a27f4d
GN		 3768 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3769 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3770}
3771
648dfaa7
MG		 3772static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3773{
3774 struct kvm_segment var;
3775 u32 ar;
3776
3777 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3778 var.dpl = 0x3;
0647f4aa
GN		 3779 if (seg == VCPU_SREG_CS)
3780 var.type = 0x3;
648dfaa7
MG		 3781 ar = vmx_segment_access_rights(&var);
3782
3783 if (var.base != (var.selector << 4))
3784 return false;
89efbed0 3785 if (var.limit != 0xffff)
648dfaa7 3786 return false;
07f42f5f 3787 if (ar != 0xf3)
648dfaa7
MG		 3788 return false;
3789
3790 return true;
3791}
3792
3793static bool code_segment_valid(struct kvm_vcpu *vcpu)
3794{
3795 struct kvm_segment cs;
3796 unsigned int cs_rpl;
3797
3798 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3799 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3800
1872a3f4
AK		 3801 if (cs.unusable)
3802 return false;
648dfaa7
MG		 3803 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3804 return false;
3805 if (!cs.s)
3806 return false;
1872a3f4 3807 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3808 if (cs.dpl > cs_rpl)
3809 return false;
1872a3f4 3810 } else {
648dfaa7
MG		 3811 if (cs.dpl != cs_rpl)
3812 return false;
3813 }
3814 if (!cs.present)
3815 return false;
3816
3817 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3818 return true;
3819}
3820
3821static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3822{
3823 struct kvm_segment ss;
3824 unsigned int ss_rpl;
3825
3826 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3827 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3828
1872a3f4
AK		 3829 if (ss.unusable)
3830 return true;
3831 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3832 return false;
3833 if (!ss.s)
3834 return false;
3835 if (ss.dpl != ss_rpl) /* DPL != RPL */
3836 return false;
3837 if (!ss.present)
3838 return false;
3839
3840 return true;
3841}
3842
3843static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3844{
3845 struct kvm_segment var;
3846 unsigned int rpl;
3847
3848 vmx_get_segment(vcpu, &var, seg);
3849 rpl = var.selector & SELECTOR_RPL_MASK;
3850
1872a3f4
AK		 3851 if (var.unusable)
3852 return true;
648dfaa7
MG		 3853 if (!var.s)
3854 return false;
3855 if (!var.present)
3856 return false;
3857 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3858 if (var.dpl < rpl) /* DPL < RPL */
3859 return false;
3860 }
3861
3862 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3863 * rights flags
3864 */
3865 return true;
3866}
3867
3868static bool tr_valid(struct kvm_vcpu *vcpu)
3869{
3870 struct kvm_segment tr;
3871
3872 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3873
1872a3f4
AK		 3874 if (tr.unusable)
3875 return false;
648dfaa7
MG		 3876 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3877 return false;
1872a3f4 3878 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3879 return false;
3880 if (!tr.present)
3881 return false;
3882
3883 return true;
3884}
3885
3886static bool ldtr_valid(struct kvm_vcpu *vcpu)
3887{
3888 struct kvm_segment ldtr;
3889
3890 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3891
1872a3f4
AK		 3892 if (ldtr.unusable)
3893 return true;
648dfaa7
MG		 3894 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3895 return false;
3896 if (ldtr.type != 2)
3897 return false;
3898 if (!ldtr.present)
3899 return false;
3900
3901 return true;
3902}
3903
3904static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3905{
3906 struct kvm_segment cs, ss;
3907
3908 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3909 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3910
3911 return ((cs.selector & SELECTOR_RPL_MASK) ==
3912 (ss.selector & SELECTOR_RPL_MASK));
3913}
3914
3915/*
3916 * Check if guest state is valid. Returns true if valid, false if
3917 * not.
3918 * We assume that registers are always usable
3919 */
3920static bool guest_state_valid(struct kvm_vcpu *vcpu)
3921{
c5e97c80
GN		 3922 if (enable_unrestricted_guest)
3923 return true;
3924
648dfaa7 3925 /* real mode guest state checks */
f13882d8 3926 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3927 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3928 return false;
3929 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3930 return false;
3931 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3932 return false;
3933 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3934 return false;
3935 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3936 return false;
3937 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3938 return false;
3939 } else {
3940 /* protected mode guest state checks */
3941 if (!cs_ss_rpl_check(vcpu))
3942 return false;
3943 if (!code_segment_valid(vcpu))
3944 return false;
3945 if (!stack_segment_valid(vcpu))
3946 return false;
3947 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3948 return false;
3949 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3950 return false;
3951 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3952 return false;
3953 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3954 return false;
3955 if (!tr_valid(vcpu))
3956 return false;
3957 if (!ldtr_valid(vcpu))
3958 return false;
3959 }
3960 /* TODO:
3961 * - Add checks on RIP
3962 * - Add checks on RFLAGS
3963 */
3964
3965 return true;
3966}
3967
d77c26fc 3968static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3969{
40dcaa9f 3970 gfn_t fn;
195aefde 3971 u16 data = 0;
1f755a82 3972 int idx, r;
6aa8b732 3973
40dcaa9f 3974 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3975 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3976 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3977 if (r < 0)
10589a46 3978 goto out;
195aefde 3979 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3980 r = kvm_write_guest_page(kvm, fn++, &data,
3981 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3982 if (r < 0)
10589a46 3983 goto out;
195aefde
IE		 3984 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3985 if (r < 0)
10589a46 3986 goto out;
195aefde
IE		 3987 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3988 if (r < 0)
10589a46 3989 goto out;
195aefde 3990 data = ~0;
10589a46
MT		 3991 r = kvm_write_guest_page(kvm, fn, &data,
3992 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3993 sizeof(u8));
10589a46 3994out:
40dcaa9f 3995 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3996 return r;
6aa8b732
AK		 3997}
3998
b7ebfb05
SY		 3999static int init_rmode_identity_map(struct kvm *kvm)
4000{
f51770ed 4001 int i, idx, r = 0;
b7ebfb05
SY		 4002 pfn_t identity_map_pfn;
4003 u32 tmp;
4004
089d034e 4005 if (!enable_ept)
f51770ed 4006 return 0;
a255d479
TC		 4007
4008 /* Protect kvm->arch.ept_identity_pagetable_done. */
4009 mutex_lock(&kvm->slots_lock);
4010
f51770ed 4011 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4012 goto out2;
a255d479 4013
b927a3ce 4014 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4015
4016 r = alloc_identity_pagetable(kvm);
f51770ed 4017 if (r < 0)
a255d479
TC		 4018 goto out2;
4019
40dcaa9f 4020 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4021 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4022 if (r < 0)
4023 goto out;
4024 /* Set up identity-mapping pagetable for EPT in real mode */
4025 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4026 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4027 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4028 r = kvm_write_guest_page(kvm, identity_map_pfn,
4029 &tmp, i * sizeof(tmp), sizeof(tmp));
4030 if (r < 0)
4031 goto out;
4032 }
4033 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4034
b7ebfb05 4035out:
40dcaa9f 4036 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4037
4038out2:
4039 mutex_unlock(&kvm->slots_lock);
f51770ed 4040 return r;
b7ebfb05
SY		 4041}
4042
6aa8b732
AK		 4043static void seg_setup(int seg)
4044{
772e0318 4045 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4046 unsigned int ar;
6aa8b732
AK		 4047
4048 vmcs_write16(sf->selector, 0);
4049 vmcs_writel(sf->base, 0);
4050 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4051 ar = 0x93;
4052 if (seg == VCPU_SREG_CS)
4053 ar |= 0x08; /* code segment */
3a624e29
NK		 4054
4055 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4056}
4057
f78e0e2e
SY		 4058static int alloc_apic_access_page(struct kvm *kvm)
4059{
4484141a 4060 struct page *page;
f78e0e2e
SY		 4061 struct kvm_userspace_memory_region kvm_userspace_mem;
4062 int r = 0;
4063
79fac95e 4064 mutex_lock(&kvm->slots_lock);
c24ae0dc 4065 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4066 goto out;
4067 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4068 kvm_userspace_mem.flags = 0;
73a6d941 4069 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4070 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4071 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4072 if (r)
4073 goto out;
72dc67a6 4074
73a6d941 4075 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4076 if (is_error_page(page)) {
4077 r = -EFAULT;
4078 goto out;
4079 }
4080
c24ae0dc
TC		 4081 /*
4082 * Do not pin the page in memory, so that memory hot-unplug
4083 * is able to migrate it.
4084 */
4085 put_page(page);
4086 kvm->arch.apic_access_page_done = true;
f78e0e2e 4087out:
79fac95e 4088 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4089 return r;
4090}
4091
b7ebfb05
SY		 4092static int alloc_identity_pagetable(struct kvm *kvm)
4093{
a255d479
TC		 4094 /* Called with kvm->slots_lock held. */
4095
b7ebfb05
SY		 4096 struct kvm_userspace_memory_region kvm_userspace_mem;
4097 int r = 0;
4098
a255d479
TC		 4099 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4100
b7ebfb05
SY		 4101 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4102 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4103 kvm_userspace_mem.guest_phys_addr =
4104 kvm->arch.ept_identity_map_addr;
b7ebfb05 4105 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4106 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4107
b7ebfb05
SY		 4108 return r;
4109}
4110
2384d2b3
SY		 4111static void allocate_vpid(struct vcpu_vmx *vmx)
4112{
4113 int vpid;
4114
4115 vmx->vpid = 0;
919818ab 4116 if (!enable_vpid)
2384d2b3
SY		 4117 return;
4118 spin_lock(&vmx_vpid_lock);
4119 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4120 if (vpid < VMX_NR_VPIDS) {
4121 vmx->vpid = vpid;
4122 __set_bit(vpid, vmx_vpid_bitmap);
4123 }
4124 spin_unlock(&vmx_vpid_lock);
4125}
4126
cdbecfc3
LJ		 4127static void free_vpid(struct vcpu_vmx *vmx)
4128{
4129 if (!enable_vpid)
4130 return;
4131 spin_lock(&vmx_vpid_lock);
4132 if (vmx->vpid != 0)
4133 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4134 spin_unlock(&vmx_vpid_lock);
4135}
4136
8d14695f
YZ		 4137#define MSR_TYPE_R 1
4138#define MSR_TYPE_W 2
4139static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4140 u32 msr, int type)
25c5f225 4141{
3e7c73e9 4142 int f = sizeof(unsigned long);
25c5f225
SY		 4143
4144 if (!cpu_has_vmx_msr_bitmap())
4145 return;
4146
4147 /*
4148 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4149 * have the write-low and read-high bitmap offsets the wrong way round.
4150 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4151 */
25c5f225 4152 if (msr <= 0x1fff) {
8d14695f
YZ		 4153 if (type & MSR_TYPE_R)
4154 /* read-low */
4155 __clear_bit(msr, msr_bitmap + 0x000 / f);
4156
4157 if (type & MSR_TYPE_W)
4158 /* write-low */
4159 __clear_bit(msr, msr_bitmap + 0x800 / f);
4160
25c5f225
SY		 4161 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4162 msr &= 0x1fff;
8d14695f
YZ		 4163 if (type & MSR_TYPE_R)
4164 /* read-high */
4165 __clear_bit(msr, msr_bitmap + 0x400 / f);
4166
4167 if (type & MSR_TYPE_W)
4168 /* write-high */
4169 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4170
4171 }
4172}
4173
4174static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4175 u32 msr, int type)
4176{
4177 int f = sizeof(unsigned long);
4178
4179 if (!cpu_has_vmx_msr_bitmap())
4180 return;
4181
4182 /*
4183 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4184 * have the write-low and read-high bitmap offsets the wrong way round.
4185 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4186 */
4187 if (msr <= 0x1fff) {
4188 if (type & MSR_TYPE_R)
4189 /* read-low */
4190 __set_bit(msr, msr_bitmap + 0x000 / f);
4191
4192 if (type & MSR_TYPE_W)
4193 /* write-low */
4194 __set_bit(msr, msr_bitmap + 0x800 / f);
4195
4196 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4197 msr &= 0x1fff;
4198 if (type & MSR_TYPE_R)
4199 /* read-high */
4200 __set_bit(msr, msr_bitmap + 0x400 / f);
4201
4202 if (type & MSR_TYPE_W)
4203 /* write-high */
4204 __set_bit(msr, msr_bitmap + 0xc00 / f);
4205
25c5f225 4206 }
25c5f225
SY		 4207}
4208
f2b93280
WV		 4209/*
4210 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4211 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4212 */
4213static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4214 unsigned long *msr_bitmap_nested,
4215 u32 msr, int type)
4216{
4217 int f = sizeof(unsigned long);
4218
4219 if (!cpu_has_vmx_msr_bitmap()) {
4220 WARN_ON(1);
4221 return;
4222 }
4223
4224 /*
4225 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4226 * have the write-low and read-high bitmap offsets the wrong way round.
4227 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4228 */
4229 if (msr <= 0x1fff) {
4230 if (type & MSR_TYPE_R &&
4231 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4232 /* read-low */
4233 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4234
4235 if (type & MSR_TYPE_W &&
4236 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4237 /* write-low */
4238 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4239
4240 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4241 msr &= 0x1fff;
4242 if (type & MSR_TYPE_R &&
4243 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4244 /* read-high */
4245 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4246
4247 if (type & MSR_TYPE_W &&
4248 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4249 /* write-high */
4250 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4251
4252 }
4253}
4254
5897297b
AK		 4255static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4256{
4257 if (!longmode_only)
8d14695f
YZ		 4258 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4259 msr, MSR_TYPE_R | MSR_TYPE_W);
4260 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4261 msr, MSR_TYPE_R | MSR_TYPE_W);
4262}
4263
4264static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4265{
4266 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4267 msr, MSR_TYPE_R);
4268 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4269 msr, MSR_TYPE_R);
4270}
4271
4272static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4273{
4274 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4275 msr, MSR_TYPE_R);
4276 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4277 msr, MSR_TYPE_R);
4278}
4279
4280static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4281{
4282 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4283 msr, MSR_TYPE_W);
4284 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4285 msr, MSR_TYPE_W);
5897297b
AK		 4286}
4287
01e439be
YZ		 4288static int vmx_vm_has_apicv(struct kvm *kvm)
4289{
4290 return enable_apicv && irqchip_in_kernel(kvm);
4291}
4292
a20ed54d
YZ		 4293/*
4294 * Send interrupt to vcpu via posted interrupt way.
4295 * 1. If target vcpu is running(non-root mode), send posted interrupt
4296 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4297 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4298 * interrupt from PIR in next vmentry.
4299 */
4300static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4301{
4302 struct vcpu_vmx *vmx = to_vmx(vcpu);
4303 int r;
4304
4305 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4306 return;
4307
4308 r = pi_test_and_set_on(&vmx->pi_desc);
4309 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4310#ifdef CONFIG_SMP
a20ed54d
YZ		 4311 if (!r && (vcpu->mode == IN_GUEST_MODE))
4312 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4313 POSTED_INTR_VECTOR);
4314 else
6ffbbbba 4315#endif
a20ed54d
YZ		 4316 kvm_vcpu_kick(vcpu);
4317}
4318
4319static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4320{
4321 struct vcpu_vmx *vmx = to_vmx(vcpu);
4322
4323 if (!pi_test_and_clear_on(&vmx->pi_desc))
4324 return;
4325
4326 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4327}
4328
4329static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4330{
4331 return;
4332}
4333
a3a8ff8e
NHE		 4334/*
4335 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4336 * will not change in the lifetime of the guest.
4337 * Note that host-state that does change is set elsewhere. E.g., host-state
4338 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4339 */
a547c6db 4340static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4341{
4342 u32 low32, high32;
4343 unsigned long tmpl;
4344 struct desc_ptr dt;
d974baa3 4345 unsigned long cr4;
a3a8ff8e 4346
b1a74bf8 4347 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4348 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4349
d974baa3
AL		 4350 /* Save the most likely value for this task's CR4 in the VMCS. */
4351 cr4 = read_cr4();
4352 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4353 vmx->host_state.vmcs_host_cr4 = cr4;
4354
a3a8ff8e 4355 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4356#ifdef CONFIG_X86_64
4357 /*
4358 * Load null selectors, so we can avoid reloading them in
4359 * __vmx_load_host_state(), in case userspace uses the null selectors
4360 * too (the expected case).
4361 */
4362 vmcs_write16(HOST_DS_SELECTOR, 0);
4363 vmcs_write16(HOST_ES_SELECTOR, 0);
4364#else
a3a8ff8e
NHE		 4365 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4366 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4367#endif
a3a8ff8e
NHE		 4368 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4369 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4370
4371 native_store_idt(&dt);
4372 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4373 vmx->host_idt_base = dt.address;
a3a8ff8e 4374
83287ea4 4375 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4376
4377 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4378 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4379 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4380 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4381
4382 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4383 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4384 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4385 }
4386}
4387
bf8179a0
NHE		 4388static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4389{
4390 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4391 if (enable_ept)
4392 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4393 if (is_guest_mode(&vmx->vcpu))
4394 vmx->vcpu.arch.cr4_guest_owned_bits &=
4395 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4396 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4397}
4398
01e439be
YZ		 4399static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4400{
4401 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4402
4403 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4404 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4405 return pin_based_exec_ctrl;
4406}
4407
bf8179a0
NHE		 4408static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4409{
4410 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4411
4412 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4413 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4414
bf8179a0
NHE		 4415 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4416 exec_control &= ~CPU_BASED_TPR_SHADOW;
4417#ifdef CONFIG_X86_64
4418 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4419 CPU_BASED_CR8_LOAD_EXITING;
4420#endif
4421 }
4422 if (!enable_ept)
4423 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4424 CPU_BASED_CR3_LOAD_EXITING |
4425 CPU_BASED_INVLPG_EXITING;
4426 return exec_control;
4427}
4428
4429static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4430{
4431 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4432 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4433 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4434 if (vmx->vpid == 0)
4435 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4436 if (!enable_ept) {
4437 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4438 enable_unrestricted_guest = 0;
ad756a16
MJ		 4439 /* Enable INVPCID for non-ept guests may cause performance regression. */
4440 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4441 }
4442 if (!enable_unrestricted_guest)
4443 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4444 if (!ple_gap)
4445 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4446 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4447 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4448 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4449 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4450 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4451 (handle_vmptrld).
4452 We can NOT enable shadow_vmcs here because we don't have yet
4453 a current VMCS12
4454 */
4455 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4456 /* PML is enabled/disabled in creating/destorying vcpu */
4457 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4458
bf8179a0
NHE		 4459 return exec_control;
4460}
4461
ce88decf
XG		 4462static void ept_set_mmio_spte_mask(void)
4463{
4464 /*
4465 * EPT Misconfigurations can be generated if the value of bits 2:0
4466 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4467 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4468 * spte.
4469 */
885032b9 4470 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4471}
4472
f53cd63c 4473#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4474/*
4475 * Sets up the vmcs for emulated real mode.
4476 */
8b9cf98c 4477static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4478{
2e4ce7f5 4479#ifdef CONFIG_X86_64
6aa8b732 4480 unsigned long a;
2e4ce7f5 4481#endif
6aa8b732 4482 int i;
6aa8b732 4483
6aa8b732 4484 /* I/O */
3e7c73e9
AK		 4485 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4486 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4487
4607c2d7
AG		 4488 if (enable_shadow_vmcs) {
4489 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4490 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4491 }
25c5f225 4492 if (cpu_has_vmx_msr_bitmap())
5897297b 4493 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4494
6aa8b732
AK		 4495 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4496
6aa8b732 4497 /* Control */
01e439be 4498 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4499
bf8179a0 4500 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4501
83ff3b9d 4502 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4503 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4504 vmx_secondary_exec_control(vmx));
83ff3b9d 4505 }
f78e0e2e 4506
01e439be 4507 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4508 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4509 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4510 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4511 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4512
4513 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4514
4515 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4516 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4517 }
4518
4b8d54f9
ZE		 4519 if (ple_gap) {
4520 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4521 vmx->ple_window = ple_window;
4522 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4523 }
4524
c3707958
XG		 4525 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4526 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4527 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4528
9581d442
AK		 4529 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4530 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4531 vmx_set_constant_host_state(vmx);
05b3e0c2 4532#ifdef CONFIG_X86_64
6aa8b732
AK		 4533 rdmsrl(MSR_FS_BASE, a);
4534 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4535 rdmsrl(MSR_GS_BASE, a);
4536 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4537#else
4538 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4539 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4540#endif
4541
2cc51560
ED		 4542 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4543 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4544 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4545 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4546 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4547
468d472f 4548 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4549 u32 msr_low, msr_high;
4550 u64 host_pat;
468d472f
SY		 4551 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4552 host_pat = msr_low | ((u64) msr_high << 32);
4553 /* Write the default value follow host pat */
4554 vmcs_write64(GUEST_IA32_PAT, host_pat);
4555 /* Keep arch.pat sync with GUEST_IA32_PAT */
4556 vmx->vcpu.arch.pat = host_pat;
4557 }
4558
03916db9 4559 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4560 u32 index = vmx_msr_index[i];
4561 u32 data_low, data_high;
a2fa3e9f 4562 int j = vmx->nmsrs;
6aa8b732
AK		 4563
4564 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4565 continue;
432bd6cb
AK		 4566 if (wrmsr_safe(index, data_low, data_high) < 0)
4567 continue;
26bb0981
AK		 4568 vmx->guest_msrs[j].index = i;
4569 vmx->guest_msrs[j].data = 0;
d5696725 4570 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4571 ++vmx->nmsrs;
6aa8b732 4572 }
6aa8b732 4573
2961e876
GN		 4574
4575 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4576
4577 /* 22.2.1, 20.8.1 */
2961e876 4578 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4579
e00c8cf2 4580 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4581 set_cr4_guest_host_mask(vmx);
e00c8cf2 4582
f53cd63c
WL		 4583 if (vmx_xsaves_supported())
4584 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4585
e00c8cf2
AK		 4586 return 0;
4587}
4588
57f252f2 4589static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4590{
4591 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4592 struct msr_data apic_base_msr;
e00c8cf2 4593
7ffd92c5 4594 vmx->rmode.vm86_active = 0;
e00c8cf2 4595
3b86cd99
JK		 4596 vmx->soft_vnmi_blocked = 0;
4597
ad312c7c 4598 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4599 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4600 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4601 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4602 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4603 apic_base_msr.host_initiated = true;
4604 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4605
2fb92db1
AK		 4606 vmx_segment_cache_clear(vmx);
4607
5706be0d 4608 seg_setup(VCPU_SREG_CS);
66450a21 4609 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4610 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4611
4612 seg_setup(VCPU_SREG_DS);
4613 seg_setup(VCPU_SREG_ES);
4614 seg_setup(VCPU_SREG_FS);
4615 seg_setup(VCPU_SREG_GS);
4616 seg_setup(VCPU_SREG_SS);
4617
4618 vmcs_write16(GUEST_TR_SELECTOR, 0);
4619 vmcs_writel(GUEST_TR_BASE, 0);
4620 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4621 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4622
4623 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4624 vmcs_writel(GUEST_LDTR_BASE, 0);
4625 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4626 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4627
4628 vmcs_write32(GUEST_SYSENTER_CS, 0);
4629 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4630 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4631
4632 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4633 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4634
e00c8cf2
AK		 4635 vmcs_writel(GUEST_GDTR_BASE, 0);
4636 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4637
4638 vmcs_writel(GUEST_IDTR_BASE, 0);
4639 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4640
443381a8 4641 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4642 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4643 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4644
e00c8cf2
AK		 4645 /* Special registers */
4646 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4647
4648 setup_msrs(vmx);
4649
6aa8b732
AK		 4650 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4651
f78e0e2e
SY		 4652 if (cpu_has_vmx_tpr_shadow()) {
4653 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4654 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4655 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4656 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4657 vmcs_write32(TPR_THRESHOLD, 0);
4658 }
4659
a73896cb 4660 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4661
01e439be
YZ		 4662 if (vmx_vm_has_apicv(vcpu->kvm))
4663 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4664
2384d2b3
SY		 4665 if (vmx->vpid != 0)
4666 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4667
fa40052c 4668 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4669 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4670 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4671 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4672 vmx_fpu_activate(&vmx->vcpu);
4673 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4674
b9d762fa 4675 vpid_sync_context(vmx);
6aa8b732
AK		 4676}
4677
b6f1250e
NHE		 4678/*
4679 * In nested virtualization, check if L1 asked to exit on external interrupts.
4680 * For most existing hypervisors, this will always return true.
4681 */
4682static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4683{
4684 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4685 PIN_BASED_EXT_INTR_MASK;
4686}
4687
77b0f5d6
BD		 4688/*
4689 * In nested virtualization, check if L1 has set
4690 * VM_EXIT_ACK_INTR_ON_EXIT
4691 */
4692static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4693{
4694 return get_vmcs12(vcpu)->vm_exit_controls &
4695 VM_EXIT_ACK_INTR_ON_EXIT;
4696}
4697
ea8ceb83
JK		 4698static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4699{
4700 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4701 PIN_BASED_NMI_EXITING;
4702}
4703
c9a7953f 4704static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4705{
4706 u32 cpu_based_vm_exec_control;
730dca42 4707
3b86cd99
JK		 4708 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4709 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4710 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4711}
4712
c9a7953f 4713static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4714{
4715 u32 cpu_based_vm_exec_control;
4716
c9a7953f
JK		 4717 if (!cpu_has_virtual_nmis() ||
4718 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4719 enable_irq_window(vcpu);
4720 return;
4721 }
3b86cd99
JK		 4722
4723 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4724 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4725 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4726}
4727
66fd3f7f 4728static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4729{
9c8cba37 4730 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4731 uint32_t intr;
4732 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4733
229456fc 4734 trace_kvm_inj_virq(irq);
2714d1d3 4735
fa89a817 4736 ++vcpu->stat.irq_injections;
7ffd92c5 4737 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4738 int inc_eip = 0;
4739 if (vcpu->arch.interrupt.soft)
4740 inc_eip = vcpu->arch.event_exit_inst_len;
4741 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4742 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4743 return;
4744 }
66fd3f7f
GN		 4745 intr = irq | INTR_INFO_VALID_MASK;
4746 if (vcpu->arch.interrupt.soft) {
4747 intr |= INTR_TYPE_SOFT_INTR;
4748 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4749 vmx->vcpu.arch.event_exit_inst_len);
4750 } else
4751 intr |= INTR_TYPE_EXT_INTR;
4752 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4753}
4754
f08864b4
SY		 4755static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4756{
66a5a347
JK		 4757 struct vcpu_vmx *vmx = to_vmx(vcpu);
4758
0b6ac343
NHE		 4759 if (is_guest_mode(vcpu))
4760 return;
4761
3b86cd99
JK		 4762 if (!cpu_has_virtual_nmis()) {
4763 /*
4764 * Tracking the NMI-blocked state in software is built upon
4765 * finding the next open IRQ window. This, in turn, depends on
4766 * well-behaving guests: They have to keep IRQs disabled at
4767 * least as long as the NMI handler runs. Otherwise we may
4768 * cause NMI nesting, maybe breaking the guest. But as this is
4769 * highly unlikely, we can live with the residual risk.
4770 */
4771 vmx->soft_vnmi_blocked = 1;
4772 vmx->vnmi_blocked_time = 0;
4773 }
4774
487b391d 4775 ++vcpu->stat.nmi_injections;
9d58b931 4776 vmx->nmi_known_unmasked = false;
7ffd92c5 4777 if (vmx->rmode.vm86_active) {
71f9833b 4778 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4779 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4780 return;
4781 }
f08864b4
SY		 4782 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4783 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4784}
4785
3cfc3092
JK		 4786static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4787{
4788 if (!cpu_has_virtual_nmis())
4789 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4790 if (to_vmx(vcpu)->nmi_known_unmasked)
4791 return false;
c332c83a 4792 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4793}
4794
4795static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4796{
4797 struct vcpu_vmx *vmx = to_vmx(vcpu);
4798
4799 if (!cpu_has_virtual_nmis()) {
4800 if (vmx->soft_vnmi_blocked != masked) {
4801 vmx->soft_vnmi_blocked = masked;
4802 vmx->vnmi_blocked_time = 0;
4803 }
4804 } else {
9d58b931 4805 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4806 if (masked)
4807 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4808 GUEST_INTR_STATE_NMI);
4809 else
4810 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4811 GUEST_INTR_STATE_NMI);
4812 }
4813}
4814
2505dc9f
JK		 4815static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4816{
b6b8a145
JK		 4817 if (to_vmx(vcpu)->nested.nested_run_pending)
4818 return 0;
ea8ceb83 4819
2505dc9f
JK		 4820 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4821 return 0;
4822
4823 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4824 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4825 | GUEST_INTR_STATE_NMI));
4826}
4827
78646121
GN		 4828static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4829{
b6b8a145
JK		 4830 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4831 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4832 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4833 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4834}
4835
cbc94022
IE		 4836static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4837{
4838 int ret;
4839 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4840 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4841 .guest_phys_addr = addr,
4842 .memory_size = PAGE_SIZE * 3,
4843 .flags = 0,
4844 };
4845
47ae31e2 4846 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4847 if (ret)
4848 return ret;
bfc6d222 4849 kvm->arch.tss_addr = addr;
1f755a82 4850 return init_rmode_tss(kvm);
cbc94022
IE		 4851}
4852
0ca1b4f4 4853static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4854{
77ab6db0 4855 switch (vec) {
77ab6db0 4856 case BP_VECTOR:
c573cd22
JK		 4857 /*
4858 * Update instruction length as we may reinject the exception
4859 * from user space while in guest debugging mode.
4860 */
4861 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4862 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4863 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4864 return false;
4865 /* fall through */
4866 case DB_VECTOR:
4867 if (vcpu->guest_debug &
4868 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4869 return false;
d0bfb940
JK		 4870 /* fall through */
4871 case DE_VECTOR:
77ab6db0
JK		 4872 case OF_VECTOR:
4873 case BR_VECTOR:
4874 case UD_VECTOR:
4875 case DF_VECTOR:
4876 case SS_VECTOR:
4877 case GP_VECTOR:
4878 case MF_VECTOR:
0ca1b4f4
GN		 4879 return true;
4880 break;
77ab6db0 4881 }
0ca1b4f4
GN		 4882 return false;
4883}
4884
4885static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4886 int vec, u32 err_code)
4887{
4888 /*
4889 * Instruction with address size override prefix opcode 0x67
4890 * Cause the #SS fault with 0 error code in VM86 mode.
4891 */
4892 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4893 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4894 if (vcpu->arch.halt_request) {
4895 vcpu->arch.halt_request = 0;
4896 return kvm_emulate_halt(vcpu);
4897 }
4898 return 1;
4899 }
4900 return 0;
4901 }
4902
4903 /*
4904 * Forward all other exceptions that are valid in real mode.
4905 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4906 * the required debugging infrastructure rework.
4907 */
4908 kvm_queue_exception(vcpu, vec);
4909 return 1;
6aa8b732
AK		 4910}
4911
a0861c02
AK		 4912/*
4913 * Trigger machine check on the host. We assume all the MSRs are already set up
4914 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4915 * We pass a fake environment to the machine check handler because we want
4916 * the guest to be always treated like user space, no matter what context
4917 * it used internally.
4918 */
4919static void kvm_machine_check(void)
4920{
4921#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4922 struct pt_regs regs = {
4923 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4924 .flags = X86_EFLAGS_IF,
4925 };
4926
4927 do_machine_check(&regs, 0);
4928#endif
4929}
4930
851ba692 4931static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4932{
4933 /* already handled by vcpu_run */
4934 return 1;
4935}
4936
851ba692 4937static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4938{
1155f76a 4939 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4940 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4941 u32 intr_info, ex_no, error_code;
42dbaa5a 4942 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4943 u32 vect_info;
4944 enum emulation_result er;
4945
1155f76a 4946 vect_info = vmx->idt_vectoring_info;
88786475 4947 intr_info = vmx->exit_intr_info;
6aa8b732 4948
a0861c02 4949 if (is_machine_check(intr_info))
851ba692 4950 return handle_machine_check(vcpu);
a0861c02 4951
e4a41889 4952 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4953 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4954
4955 if (is_no_device(intr_info)) {
5fd86fcf 4956 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4957 return 1;
4958 }
4959
7aa81cc0 4960 if (is_invalid_opcode(intr_info)) {
51d8b661 4961 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4962 if (er != EMULATE_DONE)
7ee5d940 4963 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4964 return 1;
4965 }
4966
6aa8b732 4967 error_code = 0;
2e11384c 4968 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4969 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4970
4971 /*
4972 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4973 * MMIO, it is better to report an internal error.
4974 * See the comments in vmx_handle_exit.
4975 */
4976 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4977 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4978 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4979 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4980 vcpu->run->internal.ndata = 2;
4981 vcpu->run->internal.data[0] = vect_info;
4982 vcpu->run->internal.data[1] = intr_info;
4983 return 0;
4984 }
4985
6aa8b732 4986 if (is_page_fault(intr_info)) {
1439442c 4987 /* EPT won't cause page fault directly */
cf3ace79 4988 BUG_ON(enable_ept);
6aa8b732 4989 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4990 trace_kvm_page_fault(cr2, error_code);
4991
3298b75c 4992 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4993 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4994 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4995 }
4996
d0bfb940 4997 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4998
4999 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5000 return handle_rmode_exception(vcpu, ex_no, error_code);
5001
42dbaa5a
JK		 5002 switch (ex_no) {
5003 case DB_VECTOR:
5004 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5005 if (!(vcpu->guest_debug &
5006 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5007 vcpu->arch.dr6 &= ~15;
6f43ed01 5008 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5009 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5010 skip_emulated_instruction(vcpu);
5011
42dbaa5a
JK		 5012 kvm_queue_exception(vcpu, DB_VECTOR);
5013 return 1;
5014 }
5015 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5016 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5017 /* fall through */
5018 case BP_VECTOR:
c573cd22
JK		 5019 /*
5020 * Update instruction length as we may reinject #BP from
5021 * user space while in guest debugging mode. Reading it for
5022 * #DB as well causes no harm, it is not used in that case.
5023 */
5024 vmx->vcpu.arch.event_exit_inst_len =
5025 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5026 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5027 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5028 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5029 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5030 break;
5031 default:
d0bfb940
JK		 5032 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5033 kvm_run->ex.exception = ex_no;
5034 kvm_run->ex.error_code = error_code;
42dbaa5a 5035 break;
6aa8b732 5036 }
6aa8b732
AK		 5037 return 0;
5038}
5039
851ba692 5040static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5041{
1165f5fe 5042 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5043 return 1;
5044}
5045
851ba692 5046static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5047{
851ba692 5048 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5049 return 0;
5050}
6aa8b732 5051
851ba692 5052static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5053{
bfdaab09 5054 unsigned long exit_qualification;
34c33d16 5055 int size, in, string;
039576c0 5056 unsigned port;
6aa8b732 5057
bfdaab09 5058 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5059 string = (exit_qualification & 16) != 0;
cf8f70bf 5060 in = (exit_qualification & 8) != 0;
e70669ab 5061
cf8f70bf 5062 ++vcpu->stat.io_exits;
e70669ab 5063
cf8f70bf 5064 if (string || in)
51d8b661 5065 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5066
cf8f70bf
GN		 5067 port = exit_qualification >> 16;
5068 size = (exit_qualification & 7) + 1;
e93f36bc 5069 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5070
5071 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5072}
5073
102d8325
IM		 5074static void
5075vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5076{
5077 /*
5078 * Patch in the VMCALL instruction:
5079 */
5080 hypercall[0] = 0x0f;
5081 hypercall[1] = 0x01;
5082 hypercall[2] = 0xc1;
102d8325
IM		 5083}
5084
b9c237bb 5085static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5086{
5087 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5088 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5089
b9c237bb 5090 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5091 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5092 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5093 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5094 return (val & always_on) == always_on;
5095}
5096
0fa06071 5097/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5098static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5099{
eeadf9e7 5100 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5101 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5102 unsigned long orig_val = val;
5103
eeadf9e7
NHE		 5104 /*
5105 * We get here when L2 changed cr0 in a way that did not change
5106 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5107 * but did change L0 shadowed bits. So we first calculate the
5108 * effective cr0 value that L1 would like to write into the
5109 * hardware. It consists of the L2-owned bits from the new
5110 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5111 */
1a0d74e6
JK		 5112 val = (val & ~vmcs12->cr0_guest_host_mask) |
5113 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5114
b9c237bb 5115 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5116 return 1;
1a0d74e6
JK		 5117
5118 if (kvm_set_cr0(vcpu, val))
5119 return 1;
5120 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5121 return 0;
1a0d74e6
JK		 5122 } else {
5123 if (to_vmx(vcpu)->nested.vmxon &&
5124 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5125 return 1;
eeadf9e7 5126 return kvm_set_cr0(vcpu, val);
1a0d74e6 5127 }
eeadf9e7
NHE		 5128}
5129
5130static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5131{
5132 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5133 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5134 unsigned long orig_val = val;
5135
5136 /* analogously to handle_set_cr0 */
5137 val = (val & ~vmcs12->cr4_guest_host_mask) |
5138 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5139 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5140 return 1;
1a0d74e6 5141 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5142 return 0;
5143 } else
5144 return kvm_set_cr4(vcpu, val);
5145}
5146
5147/* called to set cr0 as approriate for clts instruction exit. */
5148static void handle_clts(struct kvm_vcpu *vcpu)
5149{
5150 if (is_guest_mode(vcpu)) {
5151 /*
5152 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5153 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5154 * just pretend it's off (also in arch.cr0 for fpu_activate).
5155 */
5156 vmcs_writel(CR0_READ_SHADOW,
5157 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5158 vcpu->arch.cr0 &= ~X86_CR0_TS;
5159 } else
5160 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5161}
5162
851ba692 5163static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5164{
229456fc 5165 unsigned long exit_qualification, val;
6aa8b732
AK		 5166 int cr;
5167 int reg;
49a9b07e 5168 int err;
6aa8b732 5169
bfdaab09 5170 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5171 cr = exit_qualification & 15;
5172 reg = (exit_qualification >> 8) & 15;
5173 switch ((exit_qualification >> 4) & 3) {
5174 case 0: /* mov to cr */
1e32c079 5175 val = kvm_register_readl(vcpu, reg);
229456fc 5176 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5177 switch (cr) {
5178 case 0:
eeadf9e7 5179 err = handle_set_cr0(vcpu, val);
db8fcefa 5180 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5181 return 1;
5182 case 3:
2390218b 5183 err = kvm_set_cr3(vcpu, val);
db8fcefa 5184 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5185 return 1;
5186 case 4:
eeadf9e7 5187 err = handle_set_cr4(vcpu, val);
db8fcefa 5188 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5189 return 1;
0a5fff19
GN		 5190 case 8: {
5191 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5192 u8 cr8 = (u8)val;
eea1cff9 5193 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5194 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5195 if (irqchip_in_kernel(vcpu->kvm))
5196 return 1;
5197 if (cr8_prev <= cr8)
5198 return 1;
851ba692 5199 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5200 return 0;
5201 }
4b8073e4 5202 }
6aa8b732 5203 break;
25c4c276 5204 case 2: /* clts */
eeadf9e7 5205 handle_clts(vcpu);
4d4ec087 5206 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5207 skip_emulated_instruction(vcpu);
6b52d186 5208 vmx_fpu_activate(vcpu);
25c4c276 5209 return 1;
6aa8b732
AK		 5210 case 1: /*mov from cr*/
5211 switch (cr) {
5212 case 3:
9f8fe504
AK		 5213 val = kvm_read_cr3(vcpu);
5214 kvm_register_write(vcpu, reg, val);
5215 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5216 skip_emulated_instruction(vcpu);
5217 return 1;
5218 case 8:
229456fc
MT		 5219 val = kvm_get_cr8(vcpu);
5220 kvm_register_write(vcpu, reg, val);
5221 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5222 skip_emulated_instruction(vcpu);
5223 return 1;
5224 }
5225 break;
5226 case 3: /* lmsw */
a1f83a74 5227 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5228 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5229 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5230
5231 skip_emulated_instruction(vcpu);
5232 return 1;
5233 default:
5234 break;
5235 }
851ba692 5236 vcpu->run->exit_reason = 0;
a737f256 5237 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5238 (int)(exit_qualification >> 4) & 3, cr);
5239 return 0;
5240}
5241
851ba692 5242static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5243{
bfdaab09 5244 unsigned long exit_qualification;
16f8a6f9
NA		 5245 int dr, dr7, reg;
5246
5247 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5248 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5249
5250 /* First, if DR does not exist, trigger UD */
5251 if (!kvm_require_dr(vcpu, dr))
5252 return 1;
6aa8b732 5253
f2483415 5254 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5255 if (!kvm_require_cpl(vcpu, 0))
5256 return 1;
16f8a6f9
NA		 5257 dr7 = vmcs_readl(GUEST_DR7);
5258 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5259 /*
5260 * As the vm-exit takes precedence over the debug trap, we
5261 * need to emulate the latter, either for the host or the
5262 * guest debugging itself.
5263 */
5264 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5265 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5266 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5267 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5268 vcpu->run->debug.arch.exception = DB_VECTOR;
5269 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5270 return 0;
5271 } else {
7305eb5d 5272 vcpu->arch.dr6 &= ~15;
6f43ed01 5273 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5274 kvm_queue_exception(vcpu, DB_VECTOR);
5275 return 1;
5276 }
5277 }
5278
81908bf4
PB		 5279 if (vcpu->guest_debug == 0) {
5280 u32 cpu_based_vm_exec_control;
5281
5282 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5283 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5284 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5285
5286 /*
5287 * No more DR vmexits; force a reload of the debug registers
5288 * and reenter on this instruction. The next vmexit will
5289 * retrieve the full state of the debug registers.
5290 */
5291 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5292 return 1;
5293 }
5294
42dbaa5a
JK		 5295 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5296 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5297 unsigned long val;
4c4d563b
JK		 5298
5299 if (kvm_get_dr(vcpu, dr, &val))
5300 return 1;
5301 kvm_register_write(vcpu, reg, val);
020df079 5302 } else
5777392e 5303 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5304 return 1;
5305
6aa8b732
AK		 5306 skip_emulated_instruction(vcpu);
5307 return 1;
5308}
5309
73aaf249
JK		 5310static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5311{
5312 return vcpu->arch.dr6;
5313}
5314
5315static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5316{
5317}
5318
81908bf4
PB		 5319static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5320{
5321 u32 cpu_based_vm_exec_control;
5322
5323 get_debugreg(vcpu->arch.db[0], 0);
5324 get_debugreg(vcpu->arch.db[1], 1);
5325 get_debugreg(vcpu->arch.db[2], 2);
5326 get_debugreg(vcpu->arch.db[3], 3);
5327 get_debugreg(vcpu->arch.dr6, 6);
5328 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5329
5330 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5331
5332 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5333 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5334 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5335}
5336
020df079
GN		 5337static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5338{
5339 vmcs_writel(GUEST_DR7, val);
5340}
5341
851ba692 5342static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5343{
06465c5a
AK		 5344 kvm_emulate_cpuid(vcpu);
5345 return 1;
6aa8b732
AK		 5346}
5347
851ba692 5348static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5349{
ad312c7c 5350 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5351 u64 data;
5352
5353 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5354 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5355 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5356 return 1;
5357 }
5358
229456fc 5359 trace_kvm_msr_read(ecx, data);
2714d1d3 5360
6aa8b732 5361 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5362 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5363 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5364 skip_emulated_instruction(vcpu);
5365 return 1;
5366}
5367
851ba692 5368static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5369{
8fe8ab46 5370 struct msr_data msr;
ad312c7c
ZX		 5371 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5372 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5373 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5374
8fe8ab46
WA		 5375 msr.data = data;
5376 msr.index = ecx;
5377 msr.host_initiated = false;
854e8bb1 5378 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5379 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5380 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5381 return 1;
5382 }
5383
59200273 5384 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5385 skip_emulated_instruction(vcpu);
5386 return 1;
5387}
5388
851ba692 5389static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5390{
3842d135 5391 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5392 return 1;
5393}
5394
851ba692 5395static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5396{
85f455f7
ED		 5397 u32 cpu_based_vm_exec_control;
5398
5399 /* clear pending irq */
5400 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5401 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5402 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5403
3842d135
AK		 5404 kvm_make_request(KVM_REQ_EVENT, vcpu);
5405
a26bf12a 5406 ++vcpu->stat.irq_window_exits;
2714d1d3 5407
c1150d8c
DL		 5408 /*
5409 * If the user space waits to inject interrupts, exit as soon as
5410 * possible
5411 */
8061823a 5412 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5413 vcpu->run->request_interrupt_window &&
8061823a 5414 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5415 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5416 return 0;
5417 }
6aa8b732
AK		 5418 return 1;
5419}
5420
851ba692 5421static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5422{
5423 skip_emulated_instruction(vcpu);
d3bef15f 5424 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5425}
5426
851ba692 5427static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5428{
510043da 5429 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5430 kvm_emulate_hypercall(vcpu);
5431 return 1;
c21415e8
IM		 5432}
5433
ec25d5e6
GN		 5434static int handle_invd(struct kvm_vcpu *vcpu)
5435{
51d8b661 5436 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5437}
5438
851ba692 5439static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5440{
f9c617f6 5441 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5442
5443 kvm_mmu_invlpg(vcpu, exit_qualification);
5444 skip_emulated_instruction(vcpu);
5445 return 1;
5446}
5447
fee84b07
AK		 5448static int handle_rdpmc(struct kvm_vcpu *vcpu)
5449{
5450 int err;
5451
5452 err = kvm_rdpmc(vcpu);
5453 kvm_complete_insn_gp(vcpu, err);
5454
5455 return 1;
5456}
5457
851ba692 5458static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5459{
5460 skip_emulated_instruction(vcpu);
f5f48ee1 5461 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5462 return 1;
5463}
5464
2acf923e
DC		 5465static int handle_xsetbv(struct kvm_vcpu *vcpu)
5466{
5467 u64 new_bv = kvm_read_edx_eax(vcpu);
5468 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5469
5470 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5471 skip_emulated_instruction(vcpu);
5472 return 1;
5473}
5474
f53cd63c
WL		 5475static int handle_xsaves(struct kvm_vcpu *vcpu)
5476{
5477 skip_emulated_instruction(vcpu);
5478 WARN(1, "this should never happen\n");
5479 return 1;
5480}
5481
5482static int handle_xrstors(struct kvm_vcpu *vcpu)
5483{
5484 skip_emulated_instruction(vcpu);
5485 WARN(1, "this should never happen\n");
5486 return 1;
5487}
5488
851ba692 5489static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5490{
58fbbf26
KT		 5491 if (likely(fasteoi)) {
5492 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5493 int access_type, offset;
5494
5495 access_type = exit_qualification & APIC_ACCESS_TYPE;
5496 offset = exit_qualification & APIC_ACCESS_OFFSET;
5497 /*
5498 * Sane guest uses MOV to write EOI, with written value
5499 * not cared. So make a short-circuit here by avoiding
5500 * heavy instruction emulation.
5501 */
5502 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5503 (offset == APIC_EOI)) {
5504 kvm_lapic_set_eoi(vcpu);
5505 skip_emulated_instruction(vcpu);
5506 return 1;
5507 }
5508 }
51d8b661 5509 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5510}
5511
c7c9c56c
YZ		 5512static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5513{
5514 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5515 int vector = exit_qualification & 0xff;
5516
5517 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5518 kvm_apic_set_eoi_accelerated(vcpu, vector);
5519 return 1;
5520}
5521
83d4c286
YZ		 5522static int handle_apic_write(struct kvm_vcpu *vcpu)
5523{
5524 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5525 u32 offset = exit_qualification & 0xfff;
5526
5527 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5528 kvm_apic_write_nodecode(vcpu, offset);
5529 return 1;
5530}
5531
851ba692 5532static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5533{
60637aac 5534 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5535 unsigned long exit_qualification;
e269fb21
JK		 5536 bool has_error_code = false;
5537 u32 error_code = 0;
37817f29 5538 u16 tss_selector;
7f3d35fd 5539 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5540
5541 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5542 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5543 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5544
5545 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5546
5547 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5548 if (reason == TASK_SWITCH_GATE && idt_v) {
5549 switch (type) {
5550 case INTR_TYPE_NMI_INTR:
5551 vcpu->arch.nmi_injected = false;
654f06fc 5552 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5553 break;
5554 case INTR_TYPE_EXT_INTR:
66fd3f7f 5555 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5556 kvm_clear_interrupt_queue(vcpu);
5557 break;
5558 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5559 if (vmx->idt_vectoring_info &
5560 VECTORING_INFO_DELIVER_CODE_MASK) {
5561 has_error_code = true;
5562 error_code =
5563 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5564 }
5565 /* fall through */
64a7ec06
GN		 5566 case INTR_TYPE_SOFT_EXCEPTION:
5567 kvm_clear_exception_queue(vcpu);
5568 break;
5569 default:
5570 break;
5571 }
60637aac 5572 }
37817f29
IE		 5573 tss_selector = exit_qualification;
5574
64a7ec06
GN		 5575 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5576 type != INTR_TYPE_EXT_INTR &&
5577 type != INTR_TYPE_NMI_INTR))
5578 skip_emulated_instruction(vcpu);
5579
7f3d35fd
KW		 5580 if (kvm_task_switch(vcpu, tss_selector,
5581 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5582 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5583 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5584 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5585 vcpu->run->internal.ndata = 0;
42dbaa5a 5586 return 0;
acb54517 5587 }
42dbaa5a
JK		 5588
5589 /* clear all local breakpoint enable flags */
0e8a0996 5590 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5591
5592 /*
5593 * TODO: What about debug traps on tss switch?
5594 * Are we supposed to inject them and update dr6?
5595 */
5596
5597 return 1;
37817f29
IE		 5598}
5599
851ba692 5600static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5601{
f9c617f6 5602 unsigned long exit_qualification;
1439442c 5603 gpa_t gpa;
4f5982a5 5604 u32 error_code;
1439442c 5605 int gla_validity;
1439442c 5606
f9c617f6 5607 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5608
1439442c
SY		 5609 gla_validity = (exit_qualification >> 7) & 0x3;
5610 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5611 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5612 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5613 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5614 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5615 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5616 (long unsigned int)exit_qualification);
851ba692
AK		 5617 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5618 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5619 return 0;
1439442c
SY		 5620 }
5621
0be9c7a8
GN		 5622 /*
5623 * EPT violation happened while executing iret from NMI,
5624 * "blocked by NMI" bit has to be set before next VM entry.
5625 * There are errata that may cause this bit to not be set:
5626 * AAK134, BY25.
5627 */
bcd1c294
GN		 5628 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5629 cpu_has_virtual_nmis() &&
5630 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5631 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5632
1439442c 5633 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5634 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5635
5636 /* It is a write fault? */
81ed33e4 5637 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5638 /* It is a fetch fault? */
81ed33e4 5639 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5640 /* ept page table is present? */
81ed33e4 5641 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5642
25d92081
YZ		 5643 vcpu->arch.exit_qualification = exit_qualification;
5644
4f5982a5 5645 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5646}
5647
68f89400
MT		 5648static u64 ept_rsvd_mask(u64 spte, int level)
5649{
5650 int i;
5651 u64 mask = 0;
5652
5653 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5654 mask |= (1ULL << i);
5655
a32e8459 5656 if (level == 4)
68f89400
MT		 5657 /* bits 7:3 reserved */
5658 mask |= 0xf8;
a32e8459
WL		 5659 else if (spte & (1ULL << 7))
5660 /*
5661 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5662 * level == 1 if the hypervisor is using the ignored bit 7.
5663 */
5664 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5665 else if (level > 1)
5666 /* bits 6:3 reserved */
5667 mask |= 0x78;
68f89400
MT		 5668
5669 return mask;
5670}
5671
5672static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5673 int level)
5674{
5675 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5676
5677 /* 010b (write-only) */
5678 WARN_ON((spte & 0x7) == 0x2);
5679
5680 /* 110b (write/execute) */
5681 WARN_ON((spte & 0x7) == 0x6);
5682
5683 /* 100b (execute-only) and value not supported by logical processor */
5684 if (!cpu_has_vmx_ept_execute_only())
5685 WARN_ON((spte & 0x7) == 0x4);
5686
5687 /* not 000b */
5688 if ((spte & 0x7)) {
5689 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5690
5691 if (rsvd_bits != 0) {
5692 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5693 __func__, rsvd_bits);
5694 WARN_ON(1);
5695 }
5696
a32e8459
WL		 5697 /* bits 5:3 are _not_ reserved for large page or leaf page */
5698 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5699 u64 ept_mem_type = (spte & 0x38) >> 3;
5700
5701 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5702 ept_mem_type == 7) {
5703 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5704 __func__, ept_mem_type);
5705 WARN_ON(1);
5706 }
5707 }
5708 }
5709}
5710
851ba692 5711static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5712{
5713 u64 sptes[4];
ce88decf 5714 int nr_sptes, i, ret;
68f89400
MT		 5715 gpa_t gpa;
5716
5717 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5718 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5719 skip_emulated_instruction(vcpu);
5720 return 1;
5721 }
68f89400 5722
ce88decf 5723 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5724 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5725 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5726 EMULATE_DONE;
f8f55942
XG		 5727
5728 if (unlikely(ret == RET_MMIO_PF_INVALID))
5729 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5730
b37fbea6 5731 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5732 return 1;
5733
5734 /* It is the real ept misconfig */
68f89400
MT		 5735 printk(KERN_ERR "EPT: Misconfiguration.\n");
5736 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5737
5738 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5739
5740 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5741 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5742
851ba692
AK		 5743 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5744 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5745
5746 return 0;
5747}
5748
851ba692 5749static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5750{
5751 u32 cpu_based_vm_exec_control;
5752
5753 /* clear pending NMI */
5754 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5755 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5756 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5757 ++vcpu->stat.nmi_window_exits;
3842d135 5758 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5759
5760 return 1;
5761}
5762
80ced186 5763static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5764{
8b3079a5
AK		 5765 struct vcpu_vmx *vmx = to_vmx(vcpu);
5766 enum emulation_result err = EMULATE_DONE;
80ced186 5767 int ret = 1;
49e9d557
AK		 5768 u32 cpu_exec_ctrl;
5769 bool intr_window_requested;
b8405c18 5770 unsigned count = 130;
49e9d557
AK		 5771
5772 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5773 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5774
98eb2f8b 5775 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5776 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5777 return handle_interrupt_window(&vmx->vcpu);
5778
de87dcdd
AK		 5779 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5780 return 1;
5781
991eebf9 5782 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5783
ac0a48c3 5784 if (err == EMULATE_USER_EXIT) {
94452b9e 5785 ++vcpu->stat.mmio_exits;
80ced186
MG		 5786 ret = 0;
5787 goto out;
5788 }
1d5a4d9b 5789
de5f70e0
AK		 5790 if (err != EMULATE_DONE) {
5791 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5792 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5793 vcpu->run->internal.ndata = 0;
6d77dbfc 5794 return 0;
de5f70e0 5795 }
ea953ef0 5796
8d76c49e
GN		 5797 if (vcpu->arch.halt_request) {
5798 vcpu->arch.halt_request = 0;
5799 ret = kvm_emulate_halt(vcpu);
5800 goto out;
5801 }
5802
ea953ef0 5803 if (signal_pending(current))
80ced186 5804 goto out;
ea953ef0
MG		 5805 if (need_resched())
5806 schedule();
5807 }
5808
80ced186
MG		 5809out:
5810 return ret;
ea953ef0
MG		 5811}
5812
b4a2d31d
RK		 5813static int __grow_ple_window(int val)
5814{
5815 if (ple_window_grow < 1)
5816 return ple_window;
5817
5818 val = min(val, ple_window_actual_max);
5819
5820 if (ple_window_grow < ple_window)
5821 val *= ple_window_grow;
5822 else
5823 val += ple_window_grow;
5824
5825 return val;
5826}
5827
5828static int __shrink_ple_window(int val, int modifier, int minimum)
5829{
5830 if (modifier < 1)
5831 return ple_window;
5832
5833 if (modifier < ple_window)
5834 val /= modifier;
5835 else
5836 val -= modifier;
5837
5838 return max(val, minimum);
5839}
5840
5841static void grow_ple_window(struct kvm_vcpu *vcpu)
5842{
5843 struct vcpu_vmx *vmx = to_vmx(vcpu);
5844 int old = vmx->ple_window;
5845
5846 vmx->ple_window = __grow_ple_window(old);
5847
5848 if (vmx->ple_window != old)
5849 vmx->ple_window_dirty = true;
7b46268d
RK		 5850
5851 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5852}
5853
5854static void shrink_ple_window(struct kvm_vcpu *vcpu)
5855{
5856 struct vcpu_vmx *vmx = to_vmx(vcpu);
5857 int old = vmx->ple_window;
5858
5859 vmx->ple_window = __shrink_ple_window(old,
5860 ple_window_shrink, ple_window);
5861
5862 if (vmx->ple_window != old)
5863 vmx->ple_window_dirty = true;
7b46268d
RK		 5864
5865 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5866}
5867
5868/*
5869 * ple_window_actual_max is computed to be one grow_ple_window() below
5870 * ple_window_max. (See __grow_ple_window for the reason.)
5871 * This prevents overflows, because ple_window_max is int.
5872 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5873 * this process.
5874 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5875 */
5876static void update_ple_window_actual_max(void)
5877{
5878 ple_window_actual_max =
5879 __shrink_ple_window(max(ple_window_max, ple_window),
5880 ple_window_grow, INT_MIN);
5881}
5882
f2c7648d
TC		 5883static __init int hardware_setup(void)
5884{
34a1cd60
TC		 5885 int r = -ENOMEM, i, msr;
5886
5887 rdmsrl_safe(MSR_EFER, &host_efer);
5888
5889 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5890 kvm_define_shared_msr(i, vmx_msr_index[i]);
5891
5892 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5893 if (!vmx_io_bitmap_a)
5894 return r;
5895
5896 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5897 if (!vmx_io_bitmap_b)
5898 goto out;
5899
5900 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5901 if (!vmx_msr_bitmap_legacy)
5902 goto out1;
5903
5904 vmx_msr_bitmap_legacy_x2apic =
5905 (unsigned long *)__get_free_page(GFP_KERNEL);
5906 if (!vmx_msr_bitmap_legacy_x2apic)
5907 goto out2;
5908
5909 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5910 if (!vmx_msr_bitmap_longmode)
5911 goto out3;
5912
5913 vmx_msr_bitmap_longmode_x2apic =
5914 (unsigned long *)__get_free_page(GFP_KERNEL);
5915 if (!vmx_msr_bitmap_longmode_x2apic)
5916 goto out4;
3af18d9c
WV		 5917
5918 if (nested) {
5919 vmx_msr_bitmap_nested =
5920 (unsigned long *)__get_free_page(GFP_KERNEL);
5921 if (!vmx_msr_bitmap_nested)
5922 goto out5;
5923 }
5924
34a1cd60
TC		 5925 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5926 if (!vmx_vmread_bitmap)
3af18d9c 5927 goto out6;
34a1cd60
TC		 5928
5929 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5930 if (!vmx_vmwrite_bitmap)
3af18d9c 5931 goto out7;
34a1cd60
TC		 5932
5933 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5934 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5935
5936 /*
5937 * Allow direct access to the PC debug port (it is often used for I/O
5938 * delays, but the vmexits simply slow things down).
5939 */
5940 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5941 clear_bit(0x80, vmx_io_bitmap_a);
5942
5943 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5944
5945 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5946 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 5947 if (nested)
5948 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 5949
34a1cd60
TC		 5950 if (setup_vmcs_config(&vmcs_config) < 0) {
5951 r = -EIO;
3af18d9c 5952 goto out8;
baa03522 5953 }
f2c7648d
TC		 5954
5955 if (boot_cpu_has(X86_FEATURE_NX))
5956 kvm_enable_efer_bits(EFER_NX);
5957
5958 if (!cpu_has_vmx_vpid())
5959 enable_vpid = 0;
5960 if (!cpu_has_vmx_shadow_vmcs())
5961 enable_shadow_vmcs = 0;
5962 if (enable_shadow_vmcs)
5963 init_vmcs_shadow_fields();
5964
5965 if (!cpu_has_vmx_ept() ||
5966 !cpu_has_vmx_ept_4levels()) {
5967 enable_ept = 0;
5968 enable_unrestricted_guest = 0;
5969 enable_ept_ad_bits = 0;
5970 }
5971
5972 if (!cpu_has_vmx_ept_ad_bits())
5973 enable_ept_ad_bits = 0;
5974
5975 if (!cpu_has_vmx_unrestricted_guest())
5976 enable_unrestricted_guest = 0;
5977
ad15a296 5978 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 5979 flexpriority_enabled = 0;
5980
ad15a296
PB		 5981 /*
5982 * set_apic_access_page_addr() is used to reload apic access
5983 * page upon invalidation. No need to do anything if not
5984 * using the APIC_ACCESS_ADDR VMCS field.
5985 */
5986 if (!flexpriority_enabled)
f2c7648d 5987 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 5988
5989 if (!cpu_has_vmx_tpr_shadow())
5990 kvm_x86_ops->update_cr8_intercept = NULL;
5991
5992 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5993 kvm_disable_largepages();
5994
5995 if (!cpu_has_vmx_ple())
5996 ple_gap = 0;
5997
5998 if (!cpu_has_vmx_apicv())
5999 enable_apicv = 0;
6000
6001 if (enable_apicv)
6002 kvm_x86_ops->update_cr8_intercept = NULL;
6003 else {
6004 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6005 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6006 kvm_x86_ops->deliver_posted_interrupt = NULL;
6007 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6008 }
6009
baa03522
TC		 6010 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6011 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6012 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6013 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6014 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6015 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6016 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6017
6018 memcpy(vmx_msr_bitmap_legacy_x2apic,
6019 vmx_msr_bitmap_legacy, PAGE_SIZE);
6020 memcpy(vmx_msr_bitmap_longmode_x2apic,
6021 vmx_msr_bitmap_longmode, PAGE_SIZE);
6022
6023 if (enable_apicv) {
6024 for (msr = 0x800; msr <= 0x8ff; msr++)
6025 vmx_disable_intercept_msr_read_x2apic(msr);
6026
6027 /* According SDM, in x2apic mode, the whole id reg is used.
6028 * But in KVM, it only use the highest eight bits. Need to
6029 * intercept it */
6030 vmx_enable_intercept_msr_read_x2apic(0x802);
6031 /* TMCCT */
6032 vmx_enable_intercept_msr_read_x2apic(0x839);
6033 /* TPR */
6034 vmx_disable_intercept_msr_write_x2apic(0x808);
6035 /* EOI */
6036 vmx_disable_intercept_msr_write_x2apic(0x80b);
6037 /* SELF-IPI */
6038 vmx_disable_intercept_msr_write_x2apic(0x83f);
6039 }
6040
6041 if (enable_ept) {
6042 kvm_mmu_set_mask_ptes(0ull,
6043 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6044 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6045 0ull, VMX_EPT_EXECUTABLE_MASK);
6046 ept_set_mmio_spte_mask();
6047 kvm_enable_tdp();
6048 } else
6049 kvm_disable_tdp();
6050
6051 update_ple_window_actual_max();
6052
843e4330
KH		 6053 /*
6054 * Only enable PML when hardware supports PML feature, and both EPT
6055 * and EPT A/D bit features are enabled -- PML depends on them to work.
6056 */
6057 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6058 enable_pml = 0;
6059
6060 if (!enable_pml) {
6061 kvm_x86_ops->slot_enable_log_dirty = NULL;
6062 kvm_x86_ops->slot_disable_log_dirty = NULL;
6063 kvm_x86_ops->flush_log_dirty = NULL;
6064 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6065 }
6066
f2c7648d 6067 return alloc_kvm_area();
34a1cd60 6068
3af18d9c 6069out8:
34a1cd60 6070 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6071out7:
34a1cd60 6072 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6073out6:
6074 if (nested)
6075 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6076out5:
6077 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6078out4:
6079 free_page((unsigned long)vmx_msr_bitmap_longmode);
6080out3:
6081 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6082out2:
6083 free_page((unsigned long)vmx_msr_bitmap_legacy);
6084out1:
6085 free_page((unsigned long)vmx_io_bitmap_b);
6086out:
6087 free_page((unsigned long)vmx_io_bitmap_a);
6088
6089 return r;
f2c7648d
TC		 6090}
6091
6092static __exit void hardware_unsetup(void)
6093{
34a1cd60
TC		 6094 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6095 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6096 free_page((unsigned long)vmx_msr_bitmap_legacy);
6097 free_page((unsigned long)vmx_msr_bitmap_longmode);
6098 free_page((unsigned long)vmx_io_bitmap_b);
6099 free_page((unsigned long)vmx_io_bitmap_a);
6100 free_page((unsigned long)vmx_vmwrite_bitmap);
6101 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6102 if (nested)
6103 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6104
f2c7648d
TC		 6105 free_kvm_area();
6106}
6107
4b8d54f9
ZE		 6108/*
6109 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6110 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6111 */
9fb41ba8 6112static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6113{
b4a2d31d
RK		 6114 if (ple_gap)
6115 grow_ple_window(vcpu);
6116
4b8d54f9
ZE		 6117 skip_emulated_instruction(vcpu);
6118 kvm_vcpu_on_spin(vcpu);
6119
6120 return 1;
6121}
6122
87c00572 6123static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6124{
87c00572 6125 skip_emulated_instruction(vcpu);
59708670
SY		 6126 return 1;
6127}
6128
87c00572
GS		 6129static int handle_mwait(struct kvm_vcpu *vcpu)
6130{
6131 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6132 return handle_nop(vcpu);
6133}
6134
6135static int handle_monitor(struct kvm_vcpu *vcpu)
6136{
6137 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6138 return handle_nop(vcpu);
6139}
6140
ff2f6fe9
NHE		 6141/*
6142 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6143 * We could reuse a single VMCS for all the L2 guests, but we also want the
6144 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6145 * allows keeping them loaded on the processor, and in the future will allow
6146 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6147 * every entry if they never change.
6148 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6149 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6150 *
6151 * The following functions allocate and free a vmcs02 in this pool.
6152 */
6153
6154/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6155static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6156{
6157 struct vmcs02_list *item;
6158 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6159 if (item->vmptr == vmx->nested.current_vmptr) {
6160 list_move(&item->list, &vmx->nested.vmcs02_pool);
6161 return &item->vmcs02;
6162 }
6163
6164 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6165 /* Recycle the least recently used VMCS. */
6166 item = list_entry(vmx->nested.vmcs02_pool.prev,
6167 struct vmcs02_list, list);
6168 item->vmptr = vmx->nested.current_vmptr;
6169 list_move(&item->list, &vmx->nested.vmcs02_pool);
6170 return &item->vmcs02;
6171 }
6172
6173 /* Create a new VMCS */
0fa24ce3 6174 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6175 if (!item)
6176 return NULL;
6177 item->vmcs02.vmcs = alloc_vmcs();
6178 if (!item->vmcs02.vmcs) {
6179 kfree(item);
6180 return NULL;
6181 }
6182 loaded_vmcs_init(&item->vmcs02);
6183 item->vmptr = vmx->nested.current_vmptr;
6184 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6185 vmx->nested.vmcs02_num++;
6186 return &item->vmcs02;
6187}
6188
6189/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6190static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6191{
6192 struct vmcs02_list *item;
6193 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6194 if (item->vmptr == vmptr) {
6195 free_loaded_vmcs(&item->vmcs02);
6196 list_del(&item->list);
6197 kfree(item);
6198 vmx->nested.vmcs02_num--;
6199 return;
6200 }
6201}
6202
6203/*
6204 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6205 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6206 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6207 */
6208static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6209{
6210 struct vmcs02_list *item, *n;
4fa7734c
PB		 6211
6212 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6213 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6214 /*
6215 * Something will leak if the above WARN triggers. Better than
6216 * a use-after-free.
6217 */
6218 if (vmx->loaded_vmcs == &item->vmcs02)
6219 continue;
6220
6221 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6222 list_del(&item->list);
6223 kfree(item);
4fa7734c 6224 vmx->nested.vmcs02_num--;
ff2f6fe9 6225 }
ff2f6fe9
NHE		 6226}
6227
0658fbaa
ACL		 6228/*
6229 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6230 * set the success or error code of an emulated VMX instruction, as specified
6231 * by Vol 2B, VMX Instruction Reference, "Conventions".
6232 */
6233static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6234{
6235 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6236 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6237 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6238}
6239
6240static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6241{
6242 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6243 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6244 X86_EFLAGS_SF | X86_EFLAGS_OF))
6245 | X86_EFLAGS_CF);
6246}
6247
145c28dd 6248static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6249 u32 vm_instruction_error)
6250{
6251 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6252 /*
6253 * failValid writes the error number to the current VMCS, which
6254 * can't be done there isn't a current VMCS.
6255 */
6256 nested_vmx_failInvalid(vcpu);
6257 return;
6258 }
6259 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6260 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6261 X86_EFLAGS_SF | X86_EFLAGS_OF))
6262 | X86_EFLAGS_ZF);
6263 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6264 /*
6265 * We don't need to force a shadow sync because
6266 * VM_INSTRUCTION_ERROR is not shadowed
6267 */
6268}
145c28dd 6269
ff651cb6
WV		 6270static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6271{
6272 /* TODO: not to reset guest simply here. */
6273 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6274 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6275}
6276
f4124500
JK		 6277static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6278{
6279 struct vcpu_vmx *vmx =
6280 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6281
6282 vmx->nested.preemption_timer_expired = true;
6283 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6284 kvm_vcpu_kick(&vmx->vcpu);
6285
6286 return HRTIMER_NORESTART;
6287}
6288
19677e32
BD		 6289/*
6290 * Decode the memory-address operand of a vmx instruction, as recorded on an
6291 * exit caused by such an instruction (run by a guest hypervisor).
6292 * On success, returns 0. When the operand is invalid, returns 1 and throws
6293 * #UD or #GP.
6294 */
6295static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6296 unsigned long exit_qualification,
6297 u32 vmx_instruction_info, gva_t *ret)
6298{
6299 /*
6300 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6301 * Execution", on an exit, vmx_instruction_info holds most of the
6302 * addressing components of the operand. Only the displacement part
6303 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6304 * For how an actual address is calculated from all these components,
6305 * refer to Vol. 1, "Operand Addressing".
6306 */
6307 int scaling = vmx_instruction_info & 3;
6308 int addr_size = (vmx_instruction_info >> 7) & 7;
6309 bool is_reg = vmx_instruction_info & (1u << 10);
6310 int seg_reg = (vmx_instruction_info >> 15) & 7;
6311 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6312 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6313 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6314 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6315
6316 if (is_reg) {
6317 kvm_queue_exception(vcpu, UD_VECTOR);
6318 return 1;
6319 }
6320
6321 /* Addr = segment_base + offset */
6322 /* offset = base + [index * scale] + displacement */
6323 *ret = vmx_get_segment_base(vcpu, seg_reg);
6324 if (base_is_valid)
6325 *ret += kvm_register_read(vcpu, base_reg);
6326 if (index_is_valid)
6327 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6328 *ret += exit_qualification; /* holds the displacement */
6329
6330 if (addr_size == 1) /* 32 bit */
6331 *ret &= 0xffffffff;
6332
6333 /*
6334 * TODO: throw #GP (and return 1) in various cases that the VM*
6335 * instructions require it - e.g., offset beyond segment limit,
6336 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6337 * address, and so on. Currently these are not checked.
6338 */
6339 return 0;
6340}
6341
3573e22c
BD		 6342/*
6343 * This function performs the various checks including
6344 * - if it's 4KB aligned
6345 * - No bits beyond the physical address width are set
6346 * - Returns 0 on success or else 1
4291b588 6347 * (Intel SDM Section 30.3)
3573e22c 6348 */
4291b588
BD		 6349static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6350 gpa_t *vmpointer)
3573e22c
BD		 6351{
6352 gva_t gva;
6353 gpa_t vmptr;
6354 struct x86_exception e;
6355 struct page *page;
6356 struct vcpu_vmx *vmx = to_vmx(vcpu);
6357 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6358
6359 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6360 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6361 return 1;
6362
6363 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6364 sizeof(vmptr), &e)) {
6365 kvm_inject_page_fault(vcpu, &e);
6366 return 1;
6367 }
6368
6369 switch (exit_reason) {
6370 case EXIT_REASON_VMON:
6371 /*
6372 * SDM 3: 24.11.5
6373 * The first 4 bytes of VMXON region contain the supported
6374 * VMCS revision identifier
6375 *
6376 * Note - IA32_VMX_BASIC[48] will never be 1
6377 * for the nested case;
6378 * which replaces physical address width with 32
6379 *
6380 */
bc39c4db 6381 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6382 nested_vmx_failInvalid(vcpu);
6383 skip_emulated_instruction(vcpu);
6384 return 1;
6385 }
6386
6387 page = nested_get_page(vcpu, vmptr);
6388 if (page == NULL ||
6389 *(u32 *)kmap(page) != VMCS12_REVISION) {
6390 nested_vmx_failInvalid(vcpu);
6391 kunmap(page);
6392 skip_emulated_instruction(vcpu);
6393 return 1;
6394 }
6395 kunmap(page);
6396 vmx->nested.vmxon_ptr = vmptr;
6397 break;
4291b588 6398 case EXIT_REASON_VMCLEAR:
bc39c4db 6399 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6400 nested_vmx_failValid(vcpu,
6401 VMXERR_VMCLEAR_INVALID_ADDRESS);
6402 skip_emulated_instruction(vcpu);
6403 return 1;
6404 }
6405
6406 if (vmptr == vmx->nested.vmxon_ptr) {
6407 nested_vmx_failValid(vcpu,
6408 VMXERR_VMCLEAR_VMXON_POINTER);
6409 skip_emulated_instruction(vcpu);
6410 return 1;
6411 }
6412 break;
6413 case EXIT_REASON_VMPTRLD:
bc39c4db 6414 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6415 nested_vmx_failValid(vcpu,
6416 VMXERR_VMPTRLD_INVALID_ADDRESS);
6417 skip_emulated_instruction(vcpu);
6418 return 1;
6419 }
3573e22c 6420
4291b588
BD		 6421 if (vmptr == vmx->nested.vmxon_ptr) {
6422 nested_vmx_failValid(vcpu,
6423 VMXERR_VMCLEAR_VMXON_POINTER);
6424 skip_emulated_instruction(vcpu);
6425 return 1;
6426 }
6427 break;
3573e22c
BD		 6428 default:
6429 return 1; /* shouldn't happen */
6430 }
6431
4291b588
BD		 6432 if (vmpointer)
6433 *vmpointer = vmptr;
3573e22c
BD		 6434 return 0;
6435}
6436
ec378aee
NHE		 6437/*
6438 * Emulate the VMXON instruction.
6439 * Currently, we just remember that VMX is active, and do not save or even
6440 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6441 * do not currently need to store anything in that guest-allocated memory
6442 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6443 * argument is different from the VMXON pointer (which the spec says they do).
6444 */
6445static int handle_vmon(struct kvm_vcpu *vcpu)
6446{
6447 struct kvm_segment cs;
6448 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6449 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6450 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6451 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6452
6453 /* The Intel VMX Instruction Reference lists a bunch of bits that
6454 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6455 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6456 * Otherwise, we should fail with #UD. We test these now:
6457 */
6458 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6459 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6460 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6461 kvm_queue_exception(vcpu, UD_VECTOR);
6462 return 1;
6463 }
6464
6465 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6466 if (is_long_mode(vcpu) && !cs.l) {
6467 kvm_queue_exception(vcpu, UD_VECTOR);
6468 return 1;
6469 }
6470
6471 if (vmx_get_cpl(vcpu)) {
6472 kvm_inject_gp(vcpu, 0);
6473 return 1;
6474 }
3573e22c 6475
4291b588 6476 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6477 return 1;
6478
145c28dd
AG		 6479 if (vmx->nested.vmxon) {
6480 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6481 skip_emulated_instruction(vcpu);
6482 return 1;
6483 }
b3897a49
NHE		 6484
6485 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6486 != VMXON_NEEDED_FEATURES) {
6487 kvm_inject_gp(vcpu, 0);
6488 return 1;
6489 }
6490
8de48833
AG		 6491 if (enable_shadow_vmcs) {
6492 shadow_vmcs = alloc_vmcs();
6493 if (!shadow_vmcs)
6494 return -ENOMEM;
6495 /* mark vmcs as shadow */
6496 shadow_vmcs->revision_id |= (1u << 31);
6497 /* init shadow vmcs */
6498 vmcs_clear(shadow_vmcs);
6499 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6500 }
ec378aee 6501
ff2f6fe9
NHE		 6502 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6503 vmx->nested.vmcs02_num = 0;
6504
f4124500
JK		 6505 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6506 HRTIMER_MODE_REL);
6507 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6508
ec378aee
NHE		 6509 vmx->nested.vmxon = true;
6510
6511 skip_emulated_instruction(vcpu);
a25eb114 6512 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6513 return 1;
6514}
6515
6516/*
6517 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6518 * for running VMX instructions (except VMXON, whose prerequisites are
6519 * slightly different). It also specifies what exception to inject otherwise.
6520 */
6521static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6522{
6523 struct kvm_segment cs;
6524 struct vcpu_vmx *vmx = to_vmx(vcpu);
6525
6526 if (!vmx->nested.vmxon) {
6527 kvm_queue_exception(vcpu, UD_VECTOR);
6528 return 0;
6529 }
6530
6531 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6532 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6533 (is_long_mode(vcpu) && !cs.l)) {
6534 kvm_queue_exception(vcpu, UD_VECTOR);
6535 return 0;
6536 }
6537
6538 if (vmx_get_cpl(vcpu)) {
6539 kvm_inject_gp(vcpu, 0);
6540 return 0;
6541 }
6542
6543 return 1;
6544}
6545
e7953d7f
AG		 6546static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6547{
8a1b9dd0 6548 u32 exec_control;
9a2a05b9
PB		 6549 if (vmx->nested.current_vmptr == -1ull)
6550 return;
6551
6552 /* current_vmptr and current_vmcs12 are always set/reset together */
6553 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6554 return;
6555
012f83cb 6556 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6557 /* copy to memory all shadowed fields in case
6558 they were modified */
6559 copy_shadow_to_vmcs12(vmx);
6560 vmx->nested.sync_shadow_vmcs = false;
6561 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6562 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6563 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6564 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6565 }
e7953d7f
AG		 6566 kunmap(vmx->nested.current_vmcs12_page);
6567 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6568 vmx->nested.current_vmptr = -1ull;
6569 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6570}
6571
ec378aee
NHE		 6572/*
6573 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6574 * just stops using VMX.
6575 */
6576static void free_nested(struct vcpu_vmx *vmx)
6577{
6578 if (!vmx->nested.vmxon)
6579 return;
9a2a05b9 6580
ec378aee 6581 vmx->nested.vmxon = false;
9a2a05b9 6582 nested_release_vmcs12(vmx);
e7953d7f
AG		 6583 if (enable_shadow_vmcs)
6584 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6585 /* Unpin physical memory we referred to in current vmcs02 */
6586 if (vmx->nested.apic_access_page) {
6587 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6588 vmx->nested.apic_access_page = NULL;
fe3ef05c 6589 }
a7c0b07d
WL		 6590 if (vmx->nested.virtual_apic_page) {
6591 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6592 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6593 }
ff2f6fe9
NHE		 6594
6595 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6596}
6597
6598/* Emulate the VMXOFF instruction */
6599static int handle_vmoff(struct kvm_vcpu *vcpu)
6600{
6601 if (!nested_vmx_check_permission(vcpu))
6602 return 1;
6603 free_nested(to_vmx(vcpu));
6604 skip_emulated_instruction(vcpu);
a25eb114 6605 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6606 return 1;
6607}
6608
27d6c865
NHE		 6609/* Emulate the VMCLEAR instruction */
6610static int handle_vmclear(struct kvm_vcpu *vcpu)
6611{
6612 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6613 gpa_t vmptr;
6614 struct vmcs12 *vmcs12;
6615 struct page *page;
27d6c865
NHE		 6616
6617 if (!nested_vmx_check_permission(vcpu))
6618 return 1;
6619
4291b588 6620 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6621 return 1;
27d6c865 6622
9a2a05b9 6623 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6624 nested_release_vmcs12(vmx);
27d6c865
NHE		 6625
6626 page = nested_get_page(vcpu, vmptr);
6627 if (page == NULL) {
6628 /*
6629 * For accurate processor emulation, VMCLEAR beyond available
6630 * physical memory should do nothing at all. However, it is
6631 * possible that a nested vmx bug, not a guest hypervisor bug,
6632 * resulted in this case, so let's shut down before doing any
6633 * more damage:
6634 */
6635 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6636 return 1;
6637 }
6638 vmcs12 = kmap(page);
6639 vmcs12->launch_state = 0;
6640 kunmap(page);
6641 nested_release_page(page);
6642
6643 nested_free_vmcs02(vmx, vmptr);
6644
6645 skip_emulated_instruction(vcpu);
6646 nested_vmx_succeed(vcpu);
6647 return 1;
6648}
6649
cd232ad0
NHE		 6650static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6651
6652/* Emulate the VMLAUNCH instruction */
6653static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6654{
6655 return nested_vmx_run(vcpu, true);
6656}
6657
6658/* Emulate the VMRESUME instruction */
6659static int handle_vmresume(struct kvm_vcpu *vcpu)
6660{
6661
6662 return nested_vmx_run(vcpu, false);
6663}
6664
49f705c5
NHE		 6665enum vmcs_field_type {
6666 VMCS_FIELD_TYPE_U16 = 0,
6667 VMCS_FIELD_TYPE_U64 = 1,
6668 VMCS_FIELD_TYPE_U32 = 2,
6669 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6670};
6671
6672static inline int vmcs_field_type(unsigned long field)
6673{
6674 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6675 return VMCS_FIELD_TYPE_U32;
6676 return (field >> 13) & 0x3 ;
6677}
6678
6679static inline int vmcs_field_readonly(unsigned long field)
6680{
6681 return (((field >> 10) & 0x3) == 1);
6682}
6683
6684/*
6685 * Read a vmcs12 field. Since these can have varying lengths and we return
6686 * one type, we chose the biggest type (u64) and zero-extend the return value
6687 * to that size. Note that the caller, handle_vmread, might need to use only
6688 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6689 * 64-bit fields are to be returned).
6690 */
a2ae9df7
PB		 6691static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6692 unsigned long field, u64 *ret)
49f705c5
NHE		 6693{
6694 short offset = vmcs_field_to_offset(field);
6695 char *p;
6696
6697 if (offset < 0)
a2ae9df7 6698 return offset;
49f705c5
NHE		 6699
6700 p = ((char *)(get_vmcs12(vcpu))) + offset;
6701
6702 switch (vmcs_field_type(field)) {
6703 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6704 *ret = *((natural_width *)p);
a2ae9df7 6705 return 0;
49f705c5
NHE		 6706 case VMCS_FIELD_TYPE_U16:
6707 *ret = *((u16 *)p);
a2ae9df7 6708 return 0;
49f705c5
NHE		 6709 case VMCS_FIELD_TYPE_U32:
6710 *ret = *((u32 *)p);
a2ae9df7 6711 return 0;
49f705c5
NHE		 6712 case VMCS_FIELD_TYPE_U64:
6713 *ret = *((u64 *)p);
a2ae9df7 6714 return 0;
49f705c5 6715 default:
a2ae9df7
PB		 6716 WARN_ON(1);
6717 return -ENOENT;
49f705c5
NHE		 6718 }
6719}
6720
20b97fea 6721
a2ae9df7
PB		 6722static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6723 unsigned long field, u64 field_value){
20b97fea
AG		 6724 short offset = vmcs_field_to_offset(field);
6725 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6726 if (offset < 0)
a2ae9df7 6727 return offset;
20b97fea
AG		 6728
6729 switch (vmcs_field_type(field)) {
6730 case VMCS_FIELD_TYPE_U16:
6731 *(u16 *)p = field_value;
a2ae9df7 6732 return 0;
20b97fea
AG		 6733 case VMCS_FIELD_TYPE_U32:
6734 *(u32 *)p = field_value;
a2ae9df7 6735 return 0;
20b97fea
AG		 6736 case VMCS_FIELD_TYPE_U64:
6737 *(u64 *)p = field_value;
a2ae9df7 6738 return 0;
20b97fea
AG		 6739 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6740 *(natural_width *)p = field_value;
a2ae9df7 6741 return 0;
20b97fea 6742 default:
a2ae9df7
PB		 6743 WARN_ON(1);
6744 return -ENOENT;
20b97fea
AG		 6745 }
6746
6747}
6748
16f5b903
AG		 6749static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6750{
6751 int i;
6752 unsigned long field;
6753 u64 field_value;
6754 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6755 const unsigned long *fields = shadow_read_write_fields;
6756 const int num_fields = max_shadow_read_write_fields;
16f5b903 6757
282da870
JK		 6758 preempt_disable();
6759
16f5b903
AG		 6760 vmcs_load(shadow_vmcs);
6761
6762 for (i = 0; i < num_fields; i++) {
6763 field = fields[i];
6764 switch (vmcs_field_type(field)) {
6765 case VMCS_FIELD_TYPE_U16:
6766 field_value = vmcs_read16(field);
6767 break;
6768 case VMCS_FIELD_TYPE_U32:
6769 field_value = vmcs_read32(field);
6770 break;
6771 case VMCS_FIELD_TYPE_U64:
6772 field_value = vmcs_read64(field);
6773 break;
6774 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6775 field_value = vmcs_readl(field);
6776 break;
a2ae9df7
PB		 6777 default:
6778 WARN_ON(1);
6779 continue;
16f5b903
AG		 6780 }
6781 vmcs12_write_any(&vmx->vcpu, field, field_value);
6782 }
6783
6784 vmcs_clear(shadow_vmcs);
6785 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6786
6787 preempt_enable();
16f5b903
AG		 6788}
6789
c3114420
AG		 6790static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6791{
c2bae893
MK		 6792 const unsigned long *fields[] = {
6793 shadow_read_write_fields,
6794 shadow_read_only_fields
c3114420 6795 };
c2bae893 6796 const int max_fields[] = {
c3114420
AG		 6797 max_shadow_read_write_fields,
6798 max_shadow_read_only_fields
6799 };
6800 int i, q;
6801 unsigned long field;
6802 u64 field_value = 0;
6803 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6804
6805 vmcs_load(shadow_vmcs);
6806
c2bae893 6807 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6808 for (i = 0; i < max_fields[q]; i++) {
6809 field = fields[q][i];
6810 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6811
6812 switch (vmcs_field_type(field)) {
6813 case VMCS_FIELD_TYPE_U16:
6814 vmcs_write16(field, (u16)field_value);
6815 break;
6816 case VMCS_FIELD_TYPE_U32:
6817 vmcs_write32(field, (u32)field_value);
6818 break;
6819 case VMCS_FIELD_TYPE_U64:
6820 vmcs_write64(field, (u64)field_value);
6821 break;
6822 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6823 vmcs_writel(field, (long)field_value);
6824 break;
a2ae9df7
PB		 6825 default:
6826 WARN_ON(1);
6827 break;
c3114420
AG		 6828 }
6829 }
6830 }
6831
6832 vmcs_clear(shadow_vmcs);
6833 vmcs_load(vmx->loaded_vmcs->vmcs);
6834}
6835
49f705c5
NHE		 6836/*
6837 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6838 * used before) all generate the same failure when it is missing.
6839 */
6840static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6841{
6842 struct vcpu_vmx *vmx = to_vmx(vcpu);
6843 if (vmx->nested.current_vmptr == -1ull) {
6844 nested_vmx_failInvalid(vcpu);
6845 skip_emulated_instruction(vcpu);
6846 return 0;
6847 }
6848 return 1;
6849}
6850
6851static int handle_vmread(struct kvm_vcpu *vcpu)
6852{
6853 unsigned long field;
6854 u64 field_value;
6855 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6856 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6857 gva_t gva = 0;
6858
6859 if (!nested_vmx_check_permission(vcpu) ||
6860 !nested_vmx_check_vmcs12(vcpu))
6861 return 1;
6862
6863 /* Decode instruction info and find the field to read */
27e6fb5d 6864 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6865 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6866 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6867 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6868 skip_emulated_instruction(vcpu);
6869 return 1;
6870 }
6871 /*
6872 * Now copy part of this value to register or memory, as requested.
6873 * Note that the number of bits actually copied is 32 or 64 depending
6874 * on the guest's mode (32 or 64 bit), not on the given field's length.
6875 */
6876 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6877 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6878 field_value);
6879 } else {
6880 if (get_vmx_mem_address(vcpu, exit_qualification,
6881 vmx_instruction_info, &gva))
6882 return 1;
6883 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6884 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6885 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6886 }
6887
6888 nested_vmx_succeed(vcpu);
6889 skip_emulated_instruction(vcpu);
6890 return 1;
6891}
6892
6893
6894static int handle_vmwrite(struct kvm_vcpu *vcpu)
6895{
6896 unsigned long field;
6897 gva_t gva;
6898 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6899 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6900 /* The value to write might be 32 or 64 bits, depending on L1's long
6901 * mode, and eventually we need to write that into a field of several
6902 * possible lengths. The code below first zero-extends the value to 64
6903 * bit (field_value), and then copies only the approriate number of
6904 * bits into the vmcs12 field.
6905 */
6906 u64 field_value = 0;
6907 struct x86_exception e;
6908
6909 if (!nested_vmx_check_permission(vcpu) ||
6910 !nested_vmx_check_vmcs12(vcpu))
6911 return 1;
6912
6913 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6914 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6915 (((vmx_instruction_info) >> 3) & 0xf));
6916 else {
6917 if (get_vmx_mem_address(vcpu, exit_qualification,
6918 vmx_instruction_info, &gva))
6919 return 1;
6920 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6921 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6922 kvm_inject_page_fault(vcpu, &e);
6923 return 1;
6924 }
6925 }
6926
6927
27e6fb5d 6928 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6929 if (vmcs_field_readonly(field)) {
6930 nested_vmx_failValid(vcpu,
6931 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6932 skip_emulated_instruction(vcpu);
6933 return 1;
6934 }
6935
a2ae9df7 6936 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6937 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6938 skip_emulated_instruction(vcpu);
6939 return 1;
6940 }
6941
6942 nested_vmx_succeed(vcpu);
6943 skip_emulated_instruction(vcpu);
6944 return 1;
6945}
6946
63846663
NHE		 6947/* Emulate the VMPTRLD instruction */
6948static int handle_vmptrld(struct kvm_vcpu *vcpu)
6949{
6950 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6951 gpa_t vmptr;
8a1b9dd0 6952 u32 exec_control;
63846663
NHE		 6953
6954 if (!nested_vmx_check_permission(vcpu))
6955 return 1;
6956
4291b588 6957 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6958 return 1;
63846663
NHE		 6959
6960 if (vmx->nested.current_vmptr != vmptr) {
6961 struct vmcs12 *new_vmcs12;
6962 struct page *page;
6963 page = nested_get_page(vcpu, vmptr);
6964 if (page == NULL) {
6965 nested_vmx_failInvalid(vcpu);
6966 skip_emulated_instruction(vcpu);
6967 return 1;
6968 }
6969 new_vmcs12 = kmap(page);
6970 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6971 kunmap(page);
6972 nested_release_page_clean(page);
6973 nested_vmx_failValid(vcpu,
6974 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6975 skip_emulated_instruction(vcpu);
6976 return 1;
6977 }
63846663 6978
9a2a05b9 6979 nested_release_vmcs12(vmx);
63846663
NHE		 6980 vmx->nested.current_vmptr = vmptr;
6981 vmx->nested.current_vmcs12 = new_vmcs12;
6982 vmx->nested.current_vmcs12_page = page;
012f83cb 6983 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6984 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6985 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6986 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6987 vmcs_write64(VMCS_LINK_POINTER,
6988 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6989 vmx->nested.sync_shadow_vmcs = true;
6990 }
63846663
NHE		 6991 }
6992
6993 nested_vmx_succeed(vcpu);
6994 skip_emulated_instruction(vcpu);
6995 return 1;
6996}
6997
6a4d7550
NHE		 6998/* Emulate the VMPTRST instruction */
6999static int handle_vmptrst(struct kvm_vcpu *vcpu)
7000{
7001 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7002 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7003 gva_t vmcs_gva;
7004 struct x86_exception e;
7005
7006 if (!nested_vmx_check_permission(vcpu))
7007 return 1;
7008
7009 if (get_vmx_mem_address(vcpu, exit_qualification,
7010 vmx_instruction_info, &vmcs_gva))
7011 return 1;
7012 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7013 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7014 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7015 sizeof(u64), &e)) {
7016 kvm_inject_page_fault(vcpu, &e);
7017 return 1;
7018 }
7019 nested_vmx_succeed(vcpu);
7020 skip_emulated_instruction(vcpu);
7021 return 1;
7022}
7023
bfd0a56b
NHE		 7024/* Emulate the INVEPT instruction */
7025static int handle_invept(struct kvm_vcpu *vcpu)
7026{
b9c237bb 7027 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7028 u32 vmx_instruction_info, types;
7029 unsigned long type;
7030 gva_t gva;
7031 struct x86_exception e;
7032 struct {
7033 u64 eptp, gpa;
7034 } operand;
bfd0a56b 7035
b9c237bb
WV		 7036 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7037 SECONDARY_EXEC_ENABLE_EPT) ||
7038 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7039 kvm_queue_exception(vcpu, UD_VECTOR);
7040 return 1;
7041 }
7042
7043 if (!nested_vmx_check_permission(vcpu))
7044 return 1;
7045
7046 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7047 kvm_queue_exception(vcpu, UD_VECTOR);
7048 return 1;
7049 }
7050
7051 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7052 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7053
b9c237bb 7054 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7055
7056 if (!(types & (1UL << type))) {
7057 nested_vmx_failValid(vcpu,
7058 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7059 return 1;
7060 }
7061
7062 /* According to the Intel VMX instruction reference, the memory
7063 * operand is read even if it isn't needed (e.g., for type==global)
7064 */
7065 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7066 vmx_instruction_info, &gva))
7067 return 1;
7068 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7069 sizeof(operand), &e)) {
7070 kvm_inject_page_fault(vcpu, &e);
7071 return 1;
7072 }
7073
7074 switch (type) {
bfd0a56b
NHE		 7075 case VMX_EPT_EXTENT_GLOBAL:
7076 kvm_mmu_sync_roots(vcpu);
77c3913b 7077 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7078 nested_vmx_succeed(vcpu);
7079 break;
7080 default:
4b855078 7081 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7082 BUG_ON(1);
7083 break;
7084 }
7085
7086 skip_emulated_instruction(vcpu);
7087 return 1;
7088}
7089
a642fc30
PM		 7090static int handle_invvpid(struct kvm_vcpu *vcpu)
7091{
7092 kvm_queue_exception(vcpu, UD_VECTOR);
7093 return 1;
7094}
7095
843e4330
KH		 7096static int handle_pml_full(struct kvm_vcpu *vcpu)
7097{
7098 unsigned long exit_qualification;
7099
7100 trace_kvm_pml_full(vcpu->vcpu_id);
7101
7102 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7103
7104 /*
7105 * PML buffer FULL happened while executing iret from NMI,
7106 * "blocked by NMI" bit has to be set before next VM entry.
7107 */
7108 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7109 cpu_has_virtual_nmis() &&
7110 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7111 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7112 GUEST_INTR_STATE_NMI);
7113
7114 /*
7115 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7116 * here.., and there's no userspace involvement needed for PML.
7117 */
7118 return 1;
7119}
7120
6aa8b732
AK		 7121/*
7122 * The exit handlers return 1 if the exit was handled fully and guest execution
7123 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7124 * to be done to userspace and return 0.
7125 */
772e0318 7126static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7127 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7128 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7129 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7130 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7131 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7132 [EXIT_REASON_CR_ACCESS] = handle_cr,
7133 [EXIT_REASON_DR_ACCESS] = handle_dr,
7134 [EXIT_REASON_CPUID] = handle_cpuid,
7135 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7136 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7137 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7138 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7139 [EXIT_REASON_INVD] = handle_invd,
a7052897 7140 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7141 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7142 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7143 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7144 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7145 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7146 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7147 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7148 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7149 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7150 [EXIT_REASON_VMOFF] = handle_vmoff,
7151 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7152 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7153 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7154 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7155 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7156 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7157 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7158 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7159 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7160 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7161 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7162 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7163 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7164 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7165 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7166 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7167 [EXIT_REASON_XSAVES] = handle_xsaves,
7168 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7169 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7170};
7171
7172static const int kvm_vmx_max_exit_handlers =
50a3485c 7173 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7174
908a7bdd
JK		 7175static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7176 struct vmcs12 *vmcs12)
7177{
7178 unsigned long exit_qualification;
7179 gpa_t bitmap, last_bitmap;
7180 unsigned int port;
7181 int size;
7182 u8 b;
7183
908a7bdd 7184 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7185 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7186
7187 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7188
7189 port = exit_qualification >> 16;
7190 size = (exit_qualification & 7) + 1;
7191
7192 last_bitmap = (gpa_t)-1;
7193 b = -1;
7194
7195 while (size > 0) {
7196 if (port < 0x8000)
7197 bitmap = vmcs12->io_bitmap_a;
7198 else if (port < 0x10000)
7199 bitmap = vmcs12->io_bitmap_b;
7200 else
7201 return 1;
7202 bitmap += (port & 0x7fff) / 8;
7203
7204 if (last_bitmap != bitmap)
7205 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7206 return 1;
7207 if (b & (1 << (port & 7)))
7208 return 1;
7209
7210 port++;
7211 size--;
7212 last_bitmap = bitmap;
7213 }
7214
7215 return 0;
7216}
7217
644d711a
NHE		 7218/*
7219 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7220 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7221 * disinterest in the current event (read or write a specific MSR) by using an
7222 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7223 */
7224static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7225 struct vmcs12 *vmcs12, u32 exit_reason)
7226{
7227 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7228 gpa_t bitmap;
7229
cbd29cb6 7230 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7231 return 1;
7232
7233 /*
7234 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7235 * for the four combinations of read/write and low/high MSR numbers.
7236 * First we need to figure out which of the four to use:
7237 */
7238 bitmap = vmcs12->msr_bitmap;
7239 if (exit_reason == EXIT_REASON_MSR_WRITE)
7240 bitmap += 2048;
7241 if (msr_index >= 0xc0000000) {
7242 msr_index -= 0xc0000000;
7243 bitmap += 1024;
7244 }
7245
7246 /* Then read the msr_index'th bit from this bitmap: */
7247 if (msr_index < 1024*8) {
7248 unsigned char b;
bd31a7f5
JK		 7249 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7250 return 1;
644d711a
NHE		 7251 return 1 & (b >> (msr_index & 7));
7252 } else
7253 return 1; /* let L1 handle the wrong parameter */
7254}
7255
7256/*
7257 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7258 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7259 * intercept (via guest_host_mask etc.) the current event.
7260 */
7261static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7262 struct vmcs12 *vmcs12)
7263{
7264 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7265 int cr = exit_qualification & 15;
7266 int reg = (exit_qualification >> 8) & 15;
1e32c079 7267 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7268
7269 switch ((exit_qualification >> 4) & 3) {
7270 case 0: /* mov to cr */
7271 switch (cr) {
7272 case 0:
7273 if (vmcs12->cr0_guest_host_mask &
7274 (val ^ vmcs12->cr0_read_shadow))
7275 return 1;
7276 break;
7277 case 3:
7278 if ((vmcs12->cr3_target_count >= 1 &&
7279 vmcs12->cr3_target_value0 == val) ||
7280 (vmcs12->cr3_target_count >= 2 &&
7281 vmcs12->cr3_target_value1 == val) ||
7282 (vmcs12->cr3_target_count >= 3 &&
7283 vmcs12->cr3_target_value2 == val) ||
7284 (vmcs12->cr3_target_count >= 4 &&
7285 vmcs12->cr3_target_value3 == val))
7286 return 0;
7287 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7288 return 1;
7289 break;
7290 case 4:
7291 if (vmcs12->cr4_guest_host_mask &
7292 (vmcs12->cr4_read_shadow ^ val))
7293 return 1;
7294 break;
7295 case 8:
7296 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7297 return 1;
7298 break;
7299 }
7300 break;
7301 case 2: /* clts */
7302 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7303 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7304 return 1;
7305 break;
7306 case 1: /* mov from cr */
7307 switch (cr) {
7308 case 3:
7309 if (vmcs12->cpu_based_vm_exec_control &
7310 CPU_BASED_CR3_STORE_EXITING)
7311 return 1;
7312 break;
7313 case 8:
7314 if (vmcs12->cpu_based_vm_exec_control &
7315 CPU_BASED_CR8_STORE_EXITING)
7316 return 1;
7317 break;
7318 }
7319 break;
7320 case 3: /* lmsw */
7321 /*
7322 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7323 * cr0. Other attempted changes are ignored, with no exit.
7324 */
7325 if (vmcs12->cr0_guest_host_mask & 0xe &
7326 (val ^ vmcs12->cr0_read_shadow))
7327 return 1;
7328 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7329 !(vmcs12->cr0_read_shadow & 0x1) &&
7330 (val & 0x1))
7331 return 1;
7332 break;
7333 }
7334 return 0;
7335}
7336
7337/*
7338 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7339 * should handle it ourselves in L0 (and then continue L2). Only call this
7340 * when in is_guest_mode (L2).
7341 */
7342static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7343{
644d711a
NHE		 7344 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7345 struct vcpu_vmx *vmx = to_vmx(vcpu);
7346 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7347 u32 exit_reason = vmx->exit_reason;
644d711a 7348
542060ea
JK		 7349 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7350 vmcs_readl(EXIT_QUALIFICATION),
7351 vmx->idt_vectoring_info,
7352 intr_info,
7353 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7354 KVM_ISA_VMX);
7355
644d711a
NHE		 7356 if (vmx->nested.nested_run_pending)
7357 return 0;
7358
7359 if (unlikely(vmx->fail)) {
bd80158a
JK		 7360 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7361 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7362 return 1;
7363 }
7364
7365 switch (exit_reason) {
7366 case EXIT_REASON_EXCEPTION_NMI:
7367 if (!is_exception(intr_info))
7368 return 0;
7369 else if (is_page_fault(intr_info))
7370 return enable_ept;
e504c909 7371 else if (is_no_device(intr_info) &&
ccf9844e 7372 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7373 return 0;
644d711a
NHE		 7374 return vmcs12->exception_bitmap &
7375 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7376 case EXIT_REASON_EXTERNAL_INTERRUPT:
7377 return 0;
7378 case EXIT_REASON_TRIPLE_FAULT:
7379 return 1;
7380 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7381 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7382 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7383 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7384 case EXIT_REASON_TASK_SWITCH:
7385 return 1;
7386 case EXIT_REASON_CPUID:
bc613494
MT		 7387 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7388 return 0;
644d711a
NHE		 7389 return 1;
7390 case EXIT_REASON_HLT:
7391 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7392 case EXIT_REASON_INVD:
7393 return 1;
7394 case EXIT_REASON_INVLPG:
7395 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7396 case EXIT_REASON_RDPMC:
7397 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7398 case EXIT_REASON_RDTSC:
7399 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7400 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7401 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7402 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7403 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7404 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7405 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7406 /*
7407 * VMX instructions trap unconditionally. This allows L1 to
7408 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7409 */
7410 return 1;
7411 case EXIT_REASON_CR_ACCESS:
7412 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7413 case EXIT_REASON_DR_ACCESS:
7414 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7415 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7416 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7417 case EXIT_REASON_MSR_READ:
7418 case EXIT_REASON_MSR_WRITE:
7419 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7420 case EXIT_REASON_INVALID_STATE:
7421 return 1;
7422 case EXIT_REASON_MWAIT_INSTRUCTION:
7423 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7424 case EXIT_REASON_MONITOR_INSTRUCTION:
7425 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7426 case EXIT_REASON_PAUSE_INSTRUCTION:
7427 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7428 nested_cpu_has2(vmcs12,
7429 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7430 case EXIT_REASON_MCE_DURING_VMENTRY:
7431 return 0;
7432 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7433 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7434 case EXIT_REASON_APIC_ACCESS:
7435 return nested_cpu_has2(vmcs12,
7436 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7437 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7438 /*
7439 * L0 always deals with the EPT violation. If nested EPT is
7440 * used, and the nested mmu code discovers that the address is
7441 * missing in the guest EPT table (EPT12), the EPT violation
7442 * will be injected with nested_ept_inject_page_fault()
7443 */
7444 return 0;
644d711a 7445 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7446 /*
7447 * L2 never uses directly L1's EPT, but rather L0's own EPT
7448 * table (shadow on EPT) or a merged EPT table that L0 built
7449 * (EPT on EPT). So any problems with the structure of the
7450 * table is L0's fault.
7451 */
644d711a
NHE		 7452 return 0;
7453 case EXIT_REASON_WBINVD:
7454 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7455 case EXIT_REASON_XSETBV:
7456 return 1;
81dc01f7
WL		 7457 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7458 /*
7459 * This should never happen, since it is not possible to
7460 * set XSS to a non-zero value---neither in L1 nor in L2.
7461 * If if it were, XSS would have to be checked against
7462 * the XSS exit bitmap in vmcs12.
7463 */
7464 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a
NHE		 7465 default:
7466 return 1;
7467 }
7468}
7469
586f9607
AK		 7470static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7471{
7472 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7473 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7474}
7475
843e4330
KH		 7476static int vmx_enable_pml(struct vcpu_vmx *vmx)
7477{
7478 struct page *pml_pg;
7479 u32 exec_control;
7480
7481 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7482 if (!pml_pg)
7483 return -ENOMEM;
7484
7485 vmx->pml_pg = pml_pg;
7486
7487 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7488 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7489
7490 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7491 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7492 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7493
7494 return 0;
7495}
7496
7497static void vmx_disable_pml(struct vcpu_vmx *vmx)
7498{
7499 u32 exec_control;
7500
7501 ASSERT(vmx->pml_pg);
7502 __free_page(vmx->pml_pg);
7503 vmx->pml_pg = NULL;
7504
7505 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7506 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7507 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7508}
7509
7510static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7511{
7512 struct kvm *kvm = vmx->vcpu.kvm;
7513 u64 *pml_buf;
7514 u16 pml_idx;
7515
7516 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7517
7518 /* Do nothing if PML buffer is empty */
7519 if (pml_idx == (PML_ENTITY_NUM - 1))
7520 return;
7521
7522 /* PML index always points to next available PML buffer entity */
7523 if (pml_idx >= PML_ENTITY_NUM)
7524 pml_idx = 0;
7525 else
7526 pml_idx++;
7527
7528 pml_buf = page_address(vmx->pml_pg);
7529 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7530 u64 gpa;
7531
7532 gpa = pml_buf[pml_idx];
7533 WARN_ON(gpa & (PAGE_SIZE - 1));
7534 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7535 }
7536
7537 /* reset PML index */
7538 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7539}
7540
7541/*
7542 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7543 * Called before reporting dirty_bitmap to userspace.
7544 */
7545static void kvm_flush_pml_buffers(struct kvm *kvm)
7546{
7547 int i;
7548 struct kvm_vcpu *vcpu;
7549 /*
7550 * We only need to kick vcpu out of guest mode here, as PML buffer
7551 * is flushed at beginning of all VMEXITs, and it's obvious that only
7552 * vcpus running in guest are possible to have unflushed GPAs in PML
7553 * buffer.
7554 */
7555 kvm_for_each_vcpu(i, vcpu, kvm)
7556 kvm_vcpu_kick(vcpu);
7557}
7558
6aa8b732
AK		 7559/*
7560 * The guest has exited. See if we can fix it or if we need userspace
7561 * assistance.
7562 */
851ba692 7563static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7564{
29bd8a78 7565 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7566 u32 exit_reason = vmx->exit_reason;
1155f76a 7567 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7568
843e4330
KH		 7569 /*
7570 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7571 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7572 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7573 * mode as if vcpus is in root mode, the PML buffer must has been
7574 * flushed already.
7575 */
7576 if (enable_pml)
7577 vmx_flush_pml_buffer(vmx);
7578
80ced186 7579 /* If guest state is invalid, start emulating */
14168786 7580 if (vmx->emulation_required)
80ced186 7581 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7582
644d711a 7583 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7584 nested_vmx_vmexit(vcpu, exit_reason,
7585 vmcs_read32(VM_EXIT_INTR_INFO),
7586 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7587 return 1;
7588 }
7589
5120702e
MG		 7590 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7591 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7592 vcpu->run->fail_entry.hardware_entry_failure_reason
7593 = exit_reason;
7594 return 0;
7595 }
7596
29bd8a78 7597 if (unlikely(vmx->fail)) {
851ba692
AK		 7598 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7599 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7600 = vmcs_read32(VM_INSTRUCTION_ERROR);
7601 return 0;
7602 }
6aa8b732 7603
b9bf6882
XG		 7604 /*
7605 * Note:
7606 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7607 * delivery event since it indicates guest is accessing MMIO.
7608 * The vm-exit can be triggered again after return to guest that
7609 * will cause infinite loop.
7610 */
d77c26fc 7611 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7612 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7613 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7614 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7615 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7616 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7617 vcpu->run->internal.ndata = 2;
7618 vcpu->run->internal.data[0] = vectoring_info;
7619 vcpu->run->internal.data[1] = exit_reason;
7620 return 0;
7621 }
3b86cd99 7622
644d711a
NHE		 7623 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7624 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7625 get_vmcs12(vcpu))))) {
c4282df9 7626 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7627 vmx->soft_vnmi_blocked = 0;
3b86cd99 7628 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7629 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7630 /*
7631 * This CPU don't support us in finding the end of an
7632 * NMI-blocked window if the guest runs with IRQs
7633 * disabled. So we pull the trigger after 1 s of
7634 * futile waiting, but inform the user about this.
7635 */
7636 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7637 "state on VCPU %d after 1 s timeout\n",
7638 __func__, vcpu->vcpu_id);
7639 vmx->soft_vnmi_blocked = 0;
3b86cd99 7640 }
3b86cd99
JK		 7641 }
7642
6aa8b732
AK		 7643 if (exit_reason < kvm_vmx_max_exit_handlers
7644 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7645 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7646 else {
2bc19dc3
MT		 7647 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7648 kvm_queue_exception(vcpu, UD_VECTOR);
7649 return 1;
6aa8b732 7650 }
6aa8b732
AK		 7651}
7652
95ba8273 7653static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7654{
a7c0b07d
WL		 7655 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7656
7657 if (is_guest_mode(vcpu) &&
7658 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7659 return;
7660
95ba8273 7661 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7662 vmcs_write32(TPR_THRESHOLD, 0);
7663 return;
7664 }
7665
95ba8273 7666 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7667}
7668
8d14695f
YZ		 7669static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7670{
7671 u32 sec_exec_control;
7672
7673 /*
7674 * There is not point to enable virtualize x2apic without enable
7675 * apicv
7676 */
c7c9c56c
YZ		 7677 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7678 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7679 return;
7680
7681 if (!vm_need_tpr_shadow(vcpu->kvm))
7682 return;
7683
7684 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7685
7686 if (set) {
7687 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7688 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7689 } else {
7690 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7691 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7692 }
7693 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7694
7695 vmx_set_msr_bitmap(vcpu);
7696}
7697
38b99173
TC		 7698static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7699{
7700 struct vcpu_vmx *vmx = to_vmx(vcpu);
7701
7702 /*
7703 * Currently we do not handle the nested case where L2 has an
7704 * APIC access page of its own; that page is still pinned.
7705 * Hence, we skip the case where the VCPU is in guest mode _and_
7706 * L1 prepared an APIC access page for L2.
7707 *
7708 * For the case where L1 and L2 share the same APIC access page
7709 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7710 * in the vmcs12), this function will only update either the vmcs01
7711 * or the vmcs02. If the former, the vmcs02 will be updated by
7712 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7713 * the next L2->L1 exit.
7714 */
7715 if (!is_guest_mode(vcpu) ||
7716 !nested_cpu_has2(vmx->nested.current_vmcs12,
7717 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7718 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7719}
7720
c7c9c56c
YZ		 7721static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7722{
7723 u16 status;
7724 u8 old;
7725
c7c9c56c
YZ		 7726 if (isr == -1)
7727 isr = 0;
7728
7729 status = vmcs_read16(GUEST_INTR_STATUS);
7730 old = status >> 8;
7731 if (isr != old) {
7732 status &= 0xff;
7733 status |= isr << 8;
7734 vmcs_write16(GUEST_INTR_STATUS, status);
7735 }
7736}
7737
7738static void vmx_set_rvi(int vector)
7739{
7740 u16 status;
7741 u8 old;
7742
4114c27d
WW		 7743 if (vector == -1)
7744 vector = 0;
7745
c7c9c56c
YZ		 7746 status = vmcs_read16(GUEST_INTR_STATUS);
7747 old = (u8)status & 0xff;
7748 if ((u8)vector != old) {
7749 status &= ~0xff;
7750 status |= (u8)vector;
7751 vmcs_write16(GUEST_INTR_STATUS, status);
7752 }
7753}
7754
7755static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7756{
4114c27d
WW		 7757 if (!is_guest_mode(vcpu)) {
7758 vmx_set_rvi(max_irr);
7759 return;
7760 }
7761
c7c9c56c
YZ		 7762 if (max_irr == -1)
7763 return;
7764
963fee16 7765 /*
4114c27d
WW		 7766 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7767 * handles it.
963fee16 7768 */
4114c27d 7769 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7770 return;
7771
963fee16 7772 /*
4114c27d 7773 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7774 * is run without virtual interrupt delivery.
7775 */
7776 if (!kvm_event_needs_reinjection(vcpu) &&
7777 vmx_interrupt_allowed(vcpu)) {
7778 kvm_queue_interrupt(vcpu, max_irr, false);
7779 vmx_inject_irq(vcpu);
7780 }
c7c9c56c
YZ		 7781}
7782
7783static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7784{
3d81bc7e
YZ		 7785 if (!vmx_vm_has_apicv(vcpu->kvm))
7786 return;
7787
c7c9c56c
YZ		 7788 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7789 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7790 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7791 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7792}
7793
51aa01d1 7794static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7795{
00eba012
AK		 7796 u32 exit_intr_info;
7797
7798 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7799 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7800 return;
7801
c5ca8e57 7802 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7803 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7804
7805 /* Handle machine checks before interrupts are enabled */
00eba012 7806 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7807 kvm_machine_check();
7808
20f65983 7809 /* We need to handle NMIs before interrupts are enabled */
00eba012 7810 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7811 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7812 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7813 asm("int $2");
ff9d07a0
ZY		 7814 kvm_after_handle_nmi(&vmx->vcpu);
7815 }
51aa01d1 7816}
20f65983 7817
a547c6db
YZ		 7818static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7819{
7820 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7821
7822 /*
7823 * If external interrupt exists, IF bit is set in rflags/eflags on the
7824 * interrupt stack frame, and interrupt will be enabled on a return
7825 * from interrupt handler.
7826 */
7827 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7828 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7829 unsigned int vector;
7830 unsigned long entry;
7831 gate_desc *desc;
7832 struct vcpu_vmx *vmx = to_vmx(vcpu);
7833#ifdef CONFIG_X86_64
7834 unsigned long tmp;
7835#endif
7836
7837 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7838 desc = (gate_desc *)vmx->host_idt_base + vector;
7839 entry = gate_offset(*desc);
7840 asm volatile(
7841#ifdef CONFIG_X86_64
7842 "mov %%" _ASM_SP ", %[sp]\n\t"
7843 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7844 "push $%c[ss]\n\t"
7845 "push %[sp]\n\t"
7846#endif
7847 "pushf\n\t"
7848 "orl $0x200, (%%" _ASM_SP ")\n\t"
7849 __ASM_SIZE(push) " $%c[cs]\n\t"
7850 "call *%[entry]\n\t"
7851 :
7852#ifdef CONFIG_X86_64
7853 [sp]"=&r"(tmp)
7854#endif
7855 :
7856 [entry]"r"(entry),
7857 [ss]"i"(__KERNEL_DS),
7858 [cs]"i"(__KERNEL_CS)
7859 );
7860 } else
7861 local_irq_enable();
7862}
7863
da8999d3
LJ		 7864static bool vmx_mpx_supported(void)
7865{
7866 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7867 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7868}
7869
55412b2e
WL		 7870static bool vmx_xsaves_supported(void)
7871{
7872 return vmcs_config.cpu_based_2nd_exec_ctrl &
7873 SECONDARY_EXEC_XSAVES;
7874}
7875
51aa01d1
AK		 7876static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7877{
c5ca8e57 7878 u32 exit_intr_info;
51aa01d1
AK		 7879 bool unblock_nmi;
7880 u8 vector;
7881 bool idtv_info_valid;
7882
7883 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7884
cf393f75 7885 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7886 if (vmx->nmi_known_unmasked)
7887 return;
c5ca8e57
AK		 7888 /*
7889 * Can't use vmx->exit_intr_info since we're not sure what
7890 * the exit reason is.
7891 */
7892 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7893 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7894 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7895 /*
7b4a25cb 7896 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7897 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7898 * a guest IRET fault.
7b4a25cb
GN		 7899 * SDM 3: 23.2.2 (September 2008)
7900 * Bit 12 is undefined in any of the following cases:
7901 * If the VM exit sets the valid bit in the IDT-vectoring
7902 * information field.
7903 * If the VM exit is due to a double fault.
cf393f75 7904 */
7b4a25cb
GN		 7905 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7906 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7907 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7908 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7909 else
7910 vmx->nmi_known_unmasked =
7911 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7912 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7913 } else if (unlikely(vmx->soft_vnmi_blocked))
7914 vmx->vnmi_blocked_time +=
7915 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7916}
7917
3ab66e8a 7918static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7919 u32 idt_vectoring_info,
7920 int instr_len_field,
7921 int error_code_field)
51aa01d1 7922{
51aa01d1
AK		 7923 u8 vector;
7924 int type;
7925 bool idtv_info_valid;
7926
7927 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7928
3ab66e8a
JK		 7929 vcpu->arch.nmi_injected = false;
7930 kvm_clear_exception_queue(vcpu);
7931 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7932
7933 if (!idtv_info_valid)
7934 return;
7935
3ab66e8a 7936 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7937
668f612f
AK		 7938 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7939 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7940
64a7ec06 7941 switch (type) {
37b96e98 7942 case INTR_TYPE_NMI_INTR:
3ab66e8a 7943 vcpu->arch.nmi_injected = true;
668f612f 7944 /*
7b4a25cb 7945 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7946 * Clear bit "block by NMI" before VM entry if a NMI
7947 * delivery faulted.
668f612f 7948 */
3ab66e8a 7949 vmx_set_nmi_mask(vcpu, false);
37b96e98 7950 break;
37b96e98 7951 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7952 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7953 /* fall through */
7954 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7955 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7956 u32 err = vmcs_read32(error_code_field);
851eb667 7957 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7958 } else
851eb667 7959 kvm_requeue_exception(vcpu, vector);
37b96e98 7960 break;
66fd3f7f 7961 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7962 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7963 /* fall through */
37b96e98 7964 case INTR_TYPE_EXT_INTR:
3ab66e8a 7965 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7966 break;
7967 default:
7968 break;
f7d9238f 7969 }
cf393f75
AK		 7970}
7971
83422e17
AK		 7972static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7973{
3ab66e8a 7974 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7975 VM_EXIT_INSTRUCTION_LEN,
7976 IDT_VECTORING_ERROR_CODE);
7977}
7978
b463a6f7
AK		 7979static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7980{
3ab66e8a 7981 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7982 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7983 VM_ENTRY_INSTRUCTION_LEN,
7984 VM_ENTRY_EXCEPTION_ERROR_CODE);
7985
7986 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7987}
7988
d7cd9796
GN		 7989static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7990{
7991 int i, nr_msrs;
7992 struct perf_guest_switch_msr *msrs;
7993
7994 msrs = perf_guest_get_msrs(&nr_msrs);
7995
7996 if (!msrs)
7997 return;
7998
7999 for (i = 0; i < nr_msrs; i++)
8000 if (msrs[i].host == msrs[i].guest)
8001 clear_atomic_switch_msr(vmx, msrs[i].msr);
8002 else
8003 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8004 msrs[i].host);
8005}
8006
a3b5ba49 8007static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8008{
a2fa3e9f 8009 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8010 unsigned long debugctlmsr, cr4;
104f226b
AK		 8011
8012 /* Record the guest's net vcpu time for enforced NMI injections. */
8013 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8014 vmx->entry_time = ktime_get();
8015
8016 /* Don't enter VMX if guest state is invalid, let the exit handler
8017 start emulation until we arrive back to a valid state */
14168786 8018 if (vmx->emulation_required)
104f226b
AK		 8019 return;
8020
a7653ecd
RK		 8021 if (vmx->ple_window_dirty) {
8022 vmx->ple_window_dirty = false;
8023 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8024 }
8025
012f83cb
AG		 8026 if (vmx->nested.sync_shadow_vmcs) {
8027 copy_vmcs12_to_shadow(vmx);
8028 vmx->nested.sync_shadow_vmcs = false;
8029 }
8030
104f226b
AK		 8031 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8032 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8033 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8034 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8035
d974baa3
AL		 8036 cr4 = read_cr4();
8037 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8038 vmcs_writel(HOST_CR4, cr4);
8039 vmx->host_state.vmcs_host_cr4 = cr4;
8040 }
8041
104f226b
AK		 8042 /* When single-stepping over STI and MOV SS, we must clear the
8043 * corresponding interruptibility bits in the guest state. Otherwise
8044 * vmentry fails as it then expects bit 14 (BS) in pending debug
8045 * exceptions being set, but that's not correct for the guest debugging
8046 * case. */
8047 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8048 vmx_set_interrupt_shadow(vcpu, 0);
8049
d7cd9796 8050 atomic_switch_perf_msrs(vmx);
2a7921b7 8051 debugctlmsr = get_debugctlmsr();
d7cd9796 8052
d462b819 8053 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8054 asm(
6aa8b732 8055 /* Store host registers */
b188c81f
AK		 8056 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8057 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8058 "push %%" _ASM_CX " \n\t"
8059 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8060 "je 1f \n\t"
b188c81f 8061 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8062 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8063 "1: \n\t"
d3edefc0 8064 /* Reload cr2 if changed */
b188c81f
AK		 8065 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8066 "mov %%cr2, %%" _ASM_DX " \n\t"
8067 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8068 "je 2f \n\t"
b188c81f 8069 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8070 "2: \n\t"
6aa8b732 8071 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8072 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8073 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8074 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8075 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8076 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8077 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8078 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8079 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8080#ifdef CONFIG_X86_64
e08aa78a
AK		 8081 "mov %c[r8](%0), %%r8 \n\t"
8082 "mov %c[r9](%0), %%r9 \n\t"
8083 "mov %c[r10](%0), %%r10 \n\t"
8084 "mov %c[r11](%0), %%r11 \n\t"
8085 "mov %c[r12](%0), %%r12 \n\t"
8086 "mov %c[r13](%0), %%r13 \n\t"
8087 "mov %c[r14](%0), %%r14 \n\t"
8088 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8089#endif
b188c81f 8090 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8091
6aa8b732 8092 /* Enter guest mode */
83287ea4 8093 "jne 1f \n\t"
4ecac3fd 8094 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8095 "jmp 2f \n\t"
8096 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8097 "2: "
6aa8b732 8098 /* Save guest registers, load host registers, keep flags */
b188c81f 8099 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8100 "pop %0 \n\t"
b188c81f
AK		 8101 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8102 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8103 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8104 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8105 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8106 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8107 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8108#ifdef CONFIG_X86_64
e08aa78a
AK		 8109 "mov %%r8, %c[r8](%0) \n\t"
8110 "mov %%r9, %c[r9](%0) \n\t"
8111 "mov %%r10, %c[r10](%0) \n\t"
8112 "mov %%r11, %c[r11](%0) \n\t"
8113 "mov %%r12, %c[r12](%0) \n\t"
8114 "mov %%r13, %c[r13](%0) \n\t"
8115 "mov %%r14, %c[r14](%0) \n\t"
8116 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8117#endif
b188c81f
AK		 8118 "mov %%cr2, %%" _ASM_AX " \n\t"
8119 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8120
b188c81f 8121 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8122 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8123 ".pushsection .rodata \n\t"
8124 ".global vmx_return \n\t"
8125 "vmx_return: " _ASM_PTR " 2b \n\t"
8126 ".popsection"
e08aa78a 8127 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8128 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8129 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8130 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8131 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8132 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8133 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8134 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8135 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8136 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8137 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8138#ifdef CONFIG_X86_64
ad312c7c
ZX		 8139 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8140 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8141 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8142 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8143 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8144 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8145 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8146 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8147#endif
40712fae
AK		 8148 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8149 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8150 : "cc", "memory"
8151#ifdef CONFIG_X86_64
b188c81f 8152 , "rax", "rbx", "rdi", "rsi"
c2036300 8153 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8154#else
8155 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8156#endif
8157 );
6aa8b732 8158
2a7921b7
GN		 8159 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8160 if (debugctlmsr)
8161 update_debugctlmsr(debugctlmsr);
8162
aa67f609
AK		 8163#ifndef CONFIG_X86_64
8164 /*
8165 * The sysexit path does not restore ds/es, so we must set them to
8166 * a reasonable value ourselves.
8167 *
8168 * We can't defer this to vmx_load_host_state() since that function
8169 * may be executed in interrupt context, which saves and restore segments
8170 * around it, nullifying its effect.
8171 */
8172 loadsegment(ds, __USER_DS);
8173 loadsegment(es, __USER_DS);
8174#endif
8175
6de4f3ad 8176 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8177 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8178 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8179 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8180 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8181 vcpu->arch.regs_dirty = 0;
8182
1155f76a
AK		 8183 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8184
d462b819 8185 vmx->loaded_vmcs->launched = 1;
1b6269db 8186
51aa01d1 8187 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8188 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8189
e0b890d3
GN		 8190 /*
8191 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8192 * we did not inject a still-pending event to L1 now because of
8193 * nested_run_pending, we need to re-enable this bit.
8194 */
8195 if (vmx->nested.nested_run_pending)
8196 kvm_make_request(KVM_REQ_EVENT, vcpu);
8197
8198 vmx->nested.nested_run_pending = 0;
8199
51aa01d1
AK		 8200 vmx_complete_atomic_exit(vmx);
8201 vmx_recover_nmi_blocking(vmx);
cf393f75 8202 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8203}
8204
4fa7734c
PB		 8205static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8206{
8207 struct vcpu_vmx *vmx = to_vmx(vcpu);
8208 int cpu;
8209
8210 if (vmx->loaded_vmcs == &vmx->vmcs01)
8211 return;
8212
8213 cpu = get_cpu();
8214 vmx->loaded_vmcs = &vmx->vmcs01;
8215 vmx_vcpu_put(vcpu);
8216 vmx_vcpu_load(vcpu, cpu);
8217 vcpu->cpu = cpu;
8218 put_cpu();
8219}
8220
6aa8b732
AK		 8221static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8222{
fb3f0f51
RR		 8223 struct vcpu_vmx *vmx = to_vmx(vcpu);
8224
843e4330
KH		 8225 if (enable_pml)
8226 vmx_disable_pml(vmx);
cdbecfc3 8227 free_vpid(vmx);
4fa7734c
PB		 8228 leave_guest_mode(vcpu);
8229 vmx_load_vmcs01(vcpu);
26a865f4 8230 free_nested(vmx);
4fa7734c 8231 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8232 kfree(vmx->guest_msrs);
8233 kvm_vcpu_uninit(vcpu);
a4770347 8234 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8235}
8236
fb3f0f51 8237static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8238{
fb3f0f51 8239 int err;
c16f862d 8240 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8241 int cpu;
6aa8b732 8242
a2fa3e9f 8243 if (!vmx)
fb3f0f51
RR		 8244 return ERR_PTR(-ENOMEM);
8245
2384d2b3
SY		 8246 allocate_vpid(vmx);
8247
fb3f0f51
RR		 8248 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8249 if (err)
8250 goto free_vcpu;
965b58a5 8251
a2fa3e9f 8252 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8253 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8254 > PAGE_SIZE);
0123be42 8255
be6d05cf 8256 err = -ENOMEM;
fb3f0f51 8257 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8258 goto uninit_vcpu;
8259 }
965b58a5 8260
d462b819
NHE		 8261 vmx->loaded_vmcs = &vmx->vmcs01;
8262 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8263 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8264 goto free_msrs;
d462b819
NHE		 8265 if (!vmm_exclusive)
8266 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8267 loaded_vmcs_init(vmx->loaded_vmcs);
8268 if (!vmm_exclusive)
8269 kvm_cpu_vmxoff();
a2fa3e9f 8270
15ad7146
AK		 8271 cpu = get_cpu();
8272 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8273 vmx->vcpu.cpu = cpu;
8b9cf98c 8274 err = vmx_vcpu_setup(vmx);
fb3f0f51 8275 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8276 put_cpu();
fb3f0f51
RR		 8277 if (err)
8278 goto free_vmcs;
a63cb560 8279 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8280 err = alloc_apic_access_page(kvm);
8281 if (err)
5e4a0b3c 8282 goto free_vmcs;
a63cb560 8283 }
fb3f0f51 8284
b927a3ce
SY		 8285 if (enable_ept) {
8286 if (!kvm->arch.ept_identity_map_addr)
8287 kvm->arch.ept_identity_map_addr =
8288 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8289 err = init_rmode_identity_map(kvm);
8290 if (err)
93ea5388 8291 goto free_vmcs;
b927a3ce 8292 }
b7ebfb05 8293
b9c237bb
WV		 8294 if (nested)
8295 nested_vmx_setup_ctls_msrs(vmx);
8296
a9d30f33
NHE		 8297 vmx->nested.current_vmptr = -1ull;
8298 vmx->nested.current_vmcs12 = NULL;
8299
843e4330
KH		 8300 /*
8301 * If PML is turned on, failure on enabling PML just results in failure
8302 * of creating the vcpu, therefore we can simplify PML logic (by
8303 * avoiding dealing with cases, such as enabling PML partially on vcpus
8304 * for the guest, etc.
8305 */
8306 if (enable_pml) {
8307 err = vmx_enable_pml(vmx);
8308 if (err)
8309 goto free_vmcs;
8310 }
8311
fb3f0f51
RR		 8312 return &vmx->vcpu;
8313
8314free_vmcs:
5f3fbc34 8315 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8316free_msrs:
fb3f0f51
RR		 8317 kfree(vmx->guest_msrs);
8318uninit_vcpu:
8319 kvm_vcpu_uninit(&vmx->vcpu);
8320free_vcpu:
cdbecfc3 8321 free_vpid(vmx);
a4770347 8322 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8323 return ERR_PTR(err);
6aa8b732
AK		 8324}
8325
002c7f7c
YS		 8326static void __init vmx_check_processor_compat(void *rtn)
8327{
8328 struct vmcs_config vmcs_conf;
8329
8330 *(int *)rtn = 0;
8331 if (setup_vmcs_config(&vmcs_conf) < 0)
8332 *(int *)rtn = -EIO;
8333 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8334 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8335 smp_processor_id());
8336 *(int *)rtn = -EIO;
8337 }
8338}
8339
67253af5
SY		 8340static int get_ept_level(void)
8341{
8342 return VMX_EPT_DEFAULT_GAW + 1;
8343}
8344
4b12f0de 8345static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8346{
4b12f0de
SY		 8347 u64 ret;
8348
522c68c4
SY		 8349 /* For VT-d and EPT combination
8350 * 1. MMIO: always map as UC
8351 * 2. EPT with VT-d:
8352 * a. VT-d without snooping control feature: can't guarantee the
8353 * result, try to trust guest.
8354 * b. VT-d with snooping control feature: snooping control feature of
8355 * VT-d engine can guarantee the cache correctness. Just set it
8356 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8357 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8358 * consistent with host MTRR
8359 */
4b12f0de
SY		 8360 if (is_mmio)
8361 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8362 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8363 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8364 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8365 else
522c68c4 8366 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8367 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8368
8369 return ret;
64d4d521
SY		 8370}
8371
17cc3935 8372static int vmx_get_lpage_level(void)
344f414f 8373{
878403b7
SY		 8374 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8375 return PT_DIRECTORY_LEVEL;
8376 else
8377 /* For shadow and EPT supported 1GB page */
8378 return PT_PDPE_LEVEL;
344f414f
JR		 8379}
8380
0e851880
SY		 8381static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8382{
4e47c7a6
SY		 8383 struct kvm_cpuid_entry2 *best;
8384 struct vcpu_vmx *vmx = to_vmx(vcpu);
8385 u32 exec_control;
8386
8387 vmx->rdtscp_enabled = false;
8388 if (vmx_rdtscp_supported()) {
8389 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8390 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8391 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8392 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8393 vmx->rdtscp_enabled = true;
8394 else {
8395 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8396 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8397 exec_control);
8398 }
8399 }
8400 }
ad756a16 8401
ad756a16
MJ		 8402 /* Exposing INVPCID only when PCID is exposed */
8403 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8404 if (vmx_invpcid_supported() &&
4f977045 8405 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8406 guest_cpuid_has_pcid(vcpu)) {
29282fde 8407 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8408 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8409 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8410 exec_control);
8411 } else {
29282fde
TI		 8412 if (cpu_has_secondary_exec_ctrls()) {
8413 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8414 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8415 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8416 exec_control);
8417 }
ad756a16 8418 if (best)
4f977045 8419 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8420 }
0e851880
SY		 8421}
8422
d4330ef2
JR		 8423static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8424{
7b8050f5
NHE		 8425 if (func == 1 && nested)
8426 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8427}
8428
25d92081
YZ		 8429static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8430 struct x86_exception *fault)
8431{
533558bc
JK		 8432 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8433 u32 exit_reason;
25d92081
YZ		 8434
8435 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8436 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8437 else
533558bc
JK		 8438 exit_reason = EXIT_REASON_EPT_VIOLATION;
8439 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8440 vmcs12->guest_physical_address = fault->address;
8441}
8442
155a97a3
NHE		 8443/* Callbacks for nested_ept_init_mmu_context: */
8444
8445static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8446{
8447 /* return the page table to be shadowed - in our case, EPT12 */
8448 return get_vmcs12(vcpu)->ept_pointer;
8449}
8450
8a3c1a33 8451static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8452{
ad896af0
PB		 8453 WARN_ON(mmu_is_nested(vcpu));
8454 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8455 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8456 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8457 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8458 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8459 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8460
8461 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8462}
8463
8464static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8465{
8466 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8467}
8468
19d5f10b
EK		 8469static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8470 u16 error_code)
8471{
8472 bool inequality, bit;
8473
8474 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8475 inequality =
8476 (error_code & vmcs12->page_fault_error_code_mask) !=
8477 vmcs12->page_fault_error_code_match;
8478 return inequality ^ bit;
8479}
8480
feaf0c7d
GN		 8481static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8482 struct x86_exception *fault)
8483{
8484 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8485
8486 WARN_ON(!is_guest_mode(vcpu));
8487
19d5f10b 8488 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8489 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8490 vmcs_read32(VM_EXIT_INTR_INFO),
8491 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8492 else
8493 kvm_inject_page_fault(vcpu, fault);
8494}
8495
a2bcba50
WL		 8496static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8497 struct vmcs12 *vmcs12)
8498{
8499 struct vcpu_vmx *vmx = to_vmx(vcpu);
8500
8501 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8502 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8503 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8504 return false;
8505
8506 /*
8507 * Translate L1 physical address to host physical
8508 * address for vmcs02. Keep the page pinned, so this
8509 * physical address remains valid. We keep a reference
8510 * to it so we can release it later.
8511 */
8512 if (vmx->nested.apic_access_page) /* shouldn't happen */
8513 nested_release_page(vmx->nested.apic_access_page);
8514 vmx->nested.apic_access_page =
8515 nested_get_page(vcpu, vmcs12->apic_access_addr);
8516 }
a7c0b07d
WL		 8517
8518 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8519 /* TODO: Also verify bits beyond physical address width are 0 */
8520 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8521 return false;
8522
8523 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8524 nested_release_page(vmx->nested.virtual_apic_page);
8525 vmx->nested.virtual_apic_page =
8526 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8527
8528 /*
8529 * Failing the vm entry is _not_ what the processor does
8530 * but it's basically the only possibility we have.
8531 * We could still enter the guest if CR8 load exits are
8532 * enabled, CR8 store exits are enabled, and virtualize APIC
8533 * access is disabled; in this case the processor would never
8534 * use the TPR shadow and we could simply clear the bit from
8535 * the execution control. But such a configuration is useless,
8536 * so let's keep the code simple.
8537 */
8538 if (!vmx->nested.virtual_apic_page)
8539 return false;
8540 }
8541
a2bcba50
WL		 8542 return true;
8543}
8544
f4124500
JK		 8545static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8546{
8547 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8548 struct vcpu_vmx *vmx = to_vmx(vcpu);
8549
8550 if (vcpu->arch.virtual_tsc_khz == 0)
8551 return;
8552
8553 /* Make sure short timeouts reliably trigger an immediate vmexit.
8554 * hrtimer_start does not guarantee this. */
8555 if (preemption_timeout <= 1) {
8556 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8557 return;
8558 }
8559
8560 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8561 preemption_timeout *= 1000000;
8562 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8563 hrtimer_start(&vmx->nested.preemption_timer,
8564 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8565}
8566
3af18d9c
WV		 8567static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8568 struct vmcs12 *vmcs12)
8569{
8570 int maxphyaddr;
8571 u64 addr;
8572
8573 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8574 return 0;
8575
8576 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8577 WARN_ON(1);
8578 return -EINVAL;
8579 }
8580 maxphyaddr = cpuid_maxphyaddr(vcpu);
8581
8582 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8583 ((addr + PAGE_SIZE) >> maxphyaddr))
8584 return -EINVAL;
8585
8586 return 0;
8587}
8588
8589/*
8590 * Merge L0's and L1's MSR bitmap, return false to indicate that
8591 * we do not use the hardware.
8592 */
8593static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8594 struct vmcs12 *vmcs12)
8595{
f2b93280
WV		 8596 struct page *page;
8597 unsigned long *msr_bitmap;
8598
8599 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8600 return false;
8601
8602 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8603 if (!page) {
8604 WARN_ON(1);
8605 return false;
8606 }
8607 msr_bitmap = (unsigned long *)kmap(page);
8608 if (!msr_bitmap) {
8609 nested_release_page_clean(page);
8610 WARN_ON(1);
8611 return false;
8612 }
8613
8614 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8615 /* TPR is allowed */
8616 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8617 vmx_msr_bitmap_nested,
8618 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8619 MSR_TYPE_R | MSR_TYPE_W);
8620 } else
8621 __vmx_enable_intercept_for_msr(
8622 vmx_msr_bitmap_nested,
8623 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8624 MSR_TYPE_R | MSR_TYPE_W);
8625 kunmap(page);
8626 nested_release_page_clean(page);
8627
8628 return true;
8629}
8630
8631static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8632 struct vmcs12 *vmcs12)
8633{
8634 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8635 return 0;
8636
8637 /*
8638 * If virtualize x2apic mode is enabled,
8639 * virtualize apic access must be disabled.
8640 */
8641 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8642 return -EINVAL;
8643
8644 /* tpr shadow is needed by all apicv features. */
8645 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8646 return -EINVAL;
8647
8648 return 0;
3af18d9c
WV		 8649}
8650
e9ac033e
EK		 8651static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8652 unsigned long count_field,
8653 unsigned long addr_field,
8654 int maxphyaddr)
ff651cb6 8655{
e9ac033e
EK		 8656 u64 count, addr;
8657
8658 if (vmcs12_read_any(vcpu, count_field, &count) ||
8659 vmcs12_read_any(vcpu, addr_field, &addr)) {
8660 WARN_ON(1);
8661 return -EINVAL;
8662 }
8663 if (count == 0)
8664 return 0;
8665 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8666 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8667 pr_warn_ratelimited(
8668 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8669 addr_field, maxphyaddr, count, addr);
8670 return -EINVAL;
8671 }
8672 return 0;
8673}
8674
8675static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8676 struct vmcs12 *vmcs12)
8677{
8678 int maxphyaddr;
8679
8680 if (vmcs12->vm_exit_msr_load_count == 0 &&
8681 vmcs12->vm_exit_msr_store_count == 0 &&
8682 vmcs12->vm_entry_msr_load_count == 0)
8683 return 0; /* Fast path */
8684 maxphyaddr = cpuid_maxphyaddr(vcpu);
8685 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8686 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8687 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8688 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8689 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8690 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8691 return -EINVAL;
8692 return 0;
8693}
8694
8695static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8696 struct vmx_msr_entry *e)
8697{
8698 /* x2APIC MSR accesses are not allowed */
8699 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8700 return -EINVAL;
8701 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8702 e->index == MSR_IA32_UCODE_REV)
8703 return -EINVAL;
8704 if (e->reserved != 0)
ff651cb6
WV		 8705 return -EINVAL;
8706 return 0;
8707}
8708
e9ac033e
EK		 8709static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8710 struct vmx_msr_entry *e)
ff651cb6
WV		 8711{
8712 if (e->index == MSR_FS_BASE ||
8713 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8714 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8715 nested_vmx_msr_check_common(vcpu, e))
8716 return -EINVAL;
8717 return 0;
8718}
8719
8720static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8721 struct vmx_msr_entry *e)
8722{
8723 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8724 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8725 return -EINVAL;
8726 return 0;
8727}
8728
8729/*
8730 * Load guest's/host's msr at nested entry/exit.
8731 * return 0 for success, entry index for failure.
8732 */
8733static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8734{
8735 u32 i;
8736 struct vmx_msr_entry e;
8737 struct msr_data msr;
8738
8739 msr.host_initiated = false;
8740 for (i = 0; i < count; i++) {
e9ac033e
EK		 8741 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8742 &e, sizeof(e))) {
8743 pr_warn_ratelimited(
8744 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8745 __func__, i, gpa + i * sizeof(e));
ff651cb6 8746 goto fail;
e9ac033e
EK		 8747 }
8748 if (nested_vmx_load_msr_check(vcpu, &e)) {
8749 pr_warn_ratelimited(
8750 "%s check failed (%u, 0x%x, 0x%x)\n",
8751 __func__, i, e.index, e.reserved);
8752 goto fail;
8753 }
ff651cb6
WV		 8754 msr.index = e.index;
8755 msr.data = e.value;
e9ac033e
EK		 8756 if (kvm_set_msr(vcpu, &msr)) {
8757 pr_warn_ratelimited(
8758 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8759 __func__, i, e.index, e.value);
ff651cb6 8760 goto fail;
e9ac033e 8761 }
ff651cb6
WV		 8762 }
8763 return 0;
8764fail:
8765 return i + 1;
8766}
8767
8768static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8769{
8770 u32 i;
8771 struct vmx_msr_entry e;
8772
8773 for (i = 0; i < count; i++) {
e9ac033e
EK		 8774 if (kvm_read_guest(vcpu->kvm,
8775 gpa + i * sizeof(e),
8776 &e, 2 * sizeof(u32))) {
8777 pr_warn_ratelimited(
8778 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8779 __func__, i, gpa + i * sizeof(e));
ff651cb6 8780 return -EINVAL;
e9ac033e
EK		 8781 }
8782 if (nested_vmx_store_msr_check(vcpu, &e)) {
8783 pr_warn_ratelimited(
8784 "%s check failed (%u, 0x%x, 0x%x)\n",
8785 __func__, i, e.index, e.reserved);
ff651cb6 8786 return -EINVAL;
e9ac033e
EK		 8787 }
8788 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8789 pr_warn_ratelimited(
8790 "%s cannot read MSR (%u, 0x%x)\n",
8791 __func__, i, e.index);
8792 return -EINVAL;
8793 }
8794 if (kvm_write_guest(vcpu->kvm,
8795 gpa + i * sizeof(e) +
ff651cb6 8796 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 8797 &e.value, sizeof(e.value))) {
8798 pr_warn_ratelimited(
8799 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8800 __func__, i, e.index, e.value);
8801 return -EINVAL;
8802 }
ff651cb6
WV		 8803 }
8804 return 0;
8805}
8806
fe3ef05c
NHE		 8807/*
8808 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8809 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8810 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8811 * guest in a way that will both be appropriate to L1's requests, and our
8812 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8813 * function also has additional necessary side-effects, like setting various
8814 * vcpu->arch fields.
8815 */
8816static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8817{
8818 struct vcpu_vmx *vmx = to_vmx(vcpu);
8819 u32 exec_control;
8820
8821 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8822 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8823 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8824 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8825 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8826 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8827 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8828 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8829 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8830 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8831 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8832 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8833 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8834 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8835 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8836 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8837 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8838 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8839 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8840 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8841 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8842 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8843 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8844 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8845 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8846 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8847 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8848 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8849 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8850 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8851 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8852 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8853 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8854 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8855 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8856 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8857
2996fca0
JK		 8858 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8859 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8860 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8861 } else {
8862 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8863 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8864 }
fe3ef05c
NHE		 8865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8866 vmcs12->vm_entry_intr_info_field);
8867 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8868 vmcs12->vm_entry_exception_error_code);
8869 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8870 vmcs12->vm_entry_instruction_len);
8871 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8872 vmcs12->guest_interruptibility_info);
fe3ef05c 8873 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8874 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8875 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8876 vmcs12->guest_pending_dbg_exceptions);
8877 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8878 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8879
81dc01f7
WL		 8880 if (nested_cpu_has_xsaves(vmcs12))
8881 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 8882 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8883
f4124500
JK		 8884 exec_control = vmcs12->pin_based_vm_exec_control;
8885 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8886 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8887 PIN_BASED_POSTED_INTR);
f4124500 8888 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8889
f4124500
JK		 8890 vmx->nested.preemption_timer_expired = false;
8891 if (nested_cpu_has_preemption_timer(vmcs12))
8892 vmx_start_preemption_timer(vcpu);
0238ea91 8893
fe3ef05c
NHE		 8894 /*
8895 * Whether page-faults are trapped is determined by a combination of
8896 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8897 * If enable_ept, L0 doesn't care about page faults and we should
8898 * set all of these to L1's desires. However, if !enable_ept, L0 does
8899 * care about (at least some) page faults, and because it is not easy
8900 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8901 * to exit on each and every L2 page fault. This is done by setting
8902 * MASK=MATCH=0 and (see below) EB.PF=1.
8903 * Note that below we don't need special code to set EB.PF beyond the
8904 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8905 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8906 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8907 *
8908 * A problem with this approach (when !enable_ept) is that L1 may be
8909 * injected with more page faults than it asked for. This could have
8910 * caused problems, but in practice existing hypervisors don't care.
8911 * To fix this, we will need to emulate the PFEC checking (on the L1
8912 * page tables), using walk_addr(), when injecting PFs to L1.
8913 */
8914 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8915 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8916 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8917 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8918
8919 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8920 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8921 if (!vmx->rdtscp_enabled)
8922 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8923 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8924 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8925 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8926 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8927 if (nested_cpu_has(vmcs12,
8928 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8929 exec_control |= vmcs12->secondary_vm_exec_control;
8930
8931 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8932 /*
8933 * If translation failed, no matter: This feature asks
8934 * to exit when accessing the given address, and if it
8935 * can never be accessed, this feature won't do
8936 * anything anyway.
8937 */
8938 if (!vmx->nested.apic_access_page)
8939 exec_control &=
8940 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8941 else
8942 vmcs_write64(APIC_ACCESS_ADDR,
8943 page_to_phys(vmx->nested.apic_access_page));
f2b93280
WV		 8944 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
8945 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
ca3f257a
JK		 8946 exec_control |=
8947 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8948 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8949 }
8950
8951 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8952 }
8953
8954
8955 /*
8956 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8957 * Some constant fields are set here by vmx_set_constant_host_state().
8958 * Other fields are different per CPU, and will be set later when
8959 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8960 */
a547c6db 8961 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8962
8963 /*
8964 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8965 * entry, but only if the current (host) sp changed from the value
8966 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8967 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8968 * here we just force the write to happen on entry.
8969 */
8970 vmx->host_rsp = 0;
8971
8972 exec_control = vmx_exec_control(vmx); /* L0's desires */
8973 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8974 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8975 exec_control &= ~CPU_BASED_TPR_SHADOW;
8976 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8977
8978 if (exec_control & CPU_BASED_TPR_SHADOW) {
8979 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8980 page_to_phys(vmx->nested.virtual_apic_page));
8981 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8982 }
8983
3af18d9c
WV		 8984 if (cpu_has_vmx_msr_bitmap() &&
8985 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
8986 nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) {
8987 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_nested));
8988 } else
8989 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8990
fe3ef05c 8991 /*
3af18d9c 8992 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 8993 * Rather, exit every time.
8994 */
fe3ef05c
NHE		 8995 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8996 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8997
8998 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8999
9000 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9001 * bitwise-or of what L1 wants to trap for L2, and what we want to
9002 * trap. Note that CR0.TS also needs updating - we do this later.
9003 */
9004 update_exception_bitmap(vcpu);
9005 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9007
8049d651
NHE		 9008 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9009 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9010 * bits are further modified by vmx_set_efer() below.
9011 */
f4124500 9012 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9013
9014 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9015 * emulated by vmx_set_efer(), below.
9016 */
2961e876 9017 vm_entry_controls_init(vmx,
8049d651
NHE		 9018 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9019 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9020 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9021
44811c02 9022 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9023 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9024 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9025 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9026 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9027
9028
9029 set_cr4_guest_host_mask(vmx);
9030
36be0b9d
PB		 9031 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9032 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9033
27fc51b2
NHE		 9034 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9035 vmcs_write64(TSC_OFFSET,
9036 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9037 else
9038 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9039
9040 if (enable_vpid) {
9041 /*
9042 * Trivially support vpid by letting L2s share their parent
9043 * L1's vpid. TODO: move to a more elaborate solution, giving
9044 * each L2 its own vpid and exposing the vpid feature to L1.
9045 */
9046 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9047 vmx_flush_tlb(vcpu);
9048 }
9049
155a97a3
NHE		 9050 if (nested_cpu_has_ept(vmcs12)) {
9051 kvm_mmu_unload(vcpu);
9052 nested_ept_init_mmu_context(vcpu);
9053 }
9054
fe3ef05c
NHE		 9055 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9056 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9057 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9058 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9059 else
9060 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9061 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9062 vmx_set_efer(vcpu, vcpu->arch.efer);
9063
9064 /*
9065 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9066 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9067 * The CR0_READ_SHADOW is what L2 should have expected to read given
9068 * the specifications by L1; It's not enough to take
9069 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9070 * have more bits than L1 expected.
9071 */
9072 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9073 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9074
9075 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9076 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9077
9078 /* shadow page tables on either EPT or shadow page tables */
9079 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9080 kvm_mmu_reset_context(vcpu);
9081
feaf0c7d
GN		 9082 if (!enable_ept)
9083 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9084
3633cfc3
NHE		 9085 /*
9086 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9087 */
9088 if (enable_ept) {
9089 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9090 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9091 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9092 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9093 }
9094
fe3ef05c
NHE		 9095 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9096 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9097}
9098
cd232ad0
NHE		 9099/*
9100 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9101 * for running an L2 nested guest.
9102 */
9103static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9104{
9105 struct vmcs12 *vmcs12;
9106 struct vcpu_vmx *vmx = to_vmx(vcpu);
9107 int cpu;
9108 struct loaded_vmcs *vmcs02;
384bb783 9109 bool ia32e;
ff651cb6 9110 u32 msr_entry_idx;
cd232ad0
NHE		 9111
9112 if (!nested_vmx_check_permission(vcpu) ||
9113 !nested_vmx_check_vmcs12(vcpu))
9114 return 1;
9115
9116 skip_emulated_instruction(vcpu);
9117 vmcs12 = get_vmcs12(vcpu);
9118
012f83cb
AG		 9119 if (enable_shadow_vmcs)
9120 copy_shadow_to_vmcs12(vmx);
9121
7c177938
NHE		 9122 /*
9123 * The nested entry process starts with enforcing various prerequisites
9124 * on vmcs12 as required by the Intel SDM, and act appropriately when
9125 * they fail: As the SDM explains, some conditions should cause the
9126 * instruction to fail, while others will cause the instruction to seem
9127 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9128 * To speed up the normal (success) code path, we should avoid checking
9129 * for misconfigurations which will anyway be caught by the processor
9130 * when using the merged vmcs02.
9131 */
9132 if (vmcs12->launch_state == launch) {
9133 nested_vmx_failValid(vcpu,
9134 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9135 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9136 return 1;
9137 }
9138
6dfacadd
JK		 9139 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9140 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9141 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9142 return 1;
9143 }
9144
3af18d9c 9145 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9146 /*TODO: Also verify bits beyond physical address width are 0*/
9147 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9148 return 1;
9149 }
9150
3af18d9c 9151 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9152 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9153 return 1;
9154 }
9155
f2b93280
WV		 9156 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9157 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9158 return 1;
9159 }
9160
e9ac033e
EK		 9161 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9162 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9163 return 1;
9164 }
9165
7c177938 9166 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9167 vmx->nested.nested_vmx_true_procbased_ctls_low,
9168 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9169 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9170 vmx->nested.nested_vmx_secondary_ctls_low,
9171 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9172 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9173 vmx->nested.nested_vmx_pinbased_ctls_low,
9174 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9175 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9176 vmx->nested.nested_vmx_true_exit_ctls_low,
9177 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9178 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9179 vmx->nested.nested_vmx_true_entry_ctls_low,
9180 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9181 {
9182 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9183 return 1;
9184 }
9185
9186 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9187 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9188 nested_vmx_failValid(vcpu,
9189 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9190 return 1;
9191 }
9192
b9c237bb 9193 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9194 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9195 nested_vmx_entry_failure(vcpu, vmcs12,
9196 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9197 return 1;
9198 }
9199 if (vmcs12->vmcs_link_pointer != -1ull) {
9200 nested_vmx_entry_failure(vcpu, vmcs12,
9201 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9202 return 1;
9203 }
9204
384bb783 9205 /*
cb0c8cda 9206 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9207 * are performed on the field for the IA32_EFER MSR:
9208 * - Bits reserved in the IA32_EFER MSR must be 0.
9209 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9210 * the IA-32e mode guest VM-exit control. It must also be identical
9211 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9212 * CR0.PG) is 1.
9213 */
9214 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9215 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9216 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9217 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9218 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9219 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9220 nested_vmx_entry_failure(vcpu, vmcs12,
9221 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9222 return 1;
9223 }
9224 }
9225
9226 /*
9227 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9228 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9229 * the values of the LMA and LME bits in the field must each be that of
9230 * the host address-space size VM-exit control.
9231 */
9232 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9233 ia32e = (vmcs12->vm_exit_controls &
9234 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9235 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9236 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9237 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9238 nested_vmx_entry_failure(vcpu, vmcs12,
9239 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9240 return 1;
9241 }
9242 }
9243
7c177938
NHE		 9244 /*
9245 * We're finally done with prerequisite checking, and can start with
9246 * the nested entry.
9247 */
9248
cd232ad0
NHE		 9249 vmcs02 = nested_get_current_vmcs02(vmx);
9250 if (!vmcs02)
9251 return -ENOMEM;
9252
9253 enter_guest_mode(vcpu);
9254
9255 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9256
2996fca0
JK		 9257 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9258 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9259
cd232ad0
NHE		 9260 cpu = get_cpu();
9261 vmx->loaded_vmcs = vmcs02;
9262 vmx_vcpu_put(vcpu);
9263 vmx_vcpu_load(vcpu, cpu);
9264 vcpu->cpu = cpu;
9265 put_cpu();
9266
36c3cc42
JK		 9267 vmx_segment_cache_clear(vmx);
9268
cd232ad0
NHE		 9269 prepare_vmcs02(vcpu, vmcs12);
9270
ff651cb6
WV		 9271 msr_entry_idx = nested_vmx_load_msr(vcpu,
9272 vmcs12->vm_entry_msr_load_addr,
9273 vmcs12->vm_entry_msr_load_count);
9274 if (msr_entry_idx) {
9275 leave_guest_mode(vcpu);
9276 vmx_load_vmcs01(vcpu);
9277 nested_vmx_entry_failure(vcpu, vmcs12,
9278 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9279 return 1;
9280 }
9281
9282 vmcs12->launch_state = 1;
9283
6dfacadd
JK		 9284 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9285 return kvm_emulate_halt(vcpu);
9286
7af40ad3
JK		 9287 vmx->nested.nested_run_pending = 1;
9288
cd232ad0
NHE		 9289 /*
9290 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9291 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9292 * returned as far as L1 is concerned. It will only return (and set
9293 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9294 */
9295 return 1;
9296}
9297
4704d0be
NHE		 9298/*
9299 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9300 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9301 * This function returns the new value we should put in vmcs12.guest_cr0.
9302 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9303 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9304 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9305 * didn't trap the bit, because if L1 did, so would L0).
9306 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9307 * been modified by L2, and L1 knows it. So just leave the old value of
9308 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9309 * isn't relevant, because if L0 traps this bit it can set it to anything.
9310 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9311 * changed these bits, and therefore they need to be updated, but L0
9312 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9313 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9314 */
9315static inline unsigned long
9316vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9317{
9318 return
9319 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9320 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9321 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9322 vcpu->arch.cr0_guest_owned_bits));
9323}
9324
9325static inline unsigned long
9326vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9327{
9328 return
9329 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9330 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9331 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9332 vcpu->arch.cr4_guest_owned_bits));
9333}
9334
5f3d5799
JK		 9335static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9336 struct vmcs12 *vmcs12)
9337{
9338 u32 idt_vectoring;
9339 unsigned int nr;
9340
851eb667 9341 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9342 nr = vcpu->arch.exception.nr;
9343 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9344
9345 if (kvm_exception_is_soft(nr)) {
9346 vmcs12->vm_exit_instruction_len =
9347 vcpu->arch.event_exit_inst_len;
9348 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9349 } else
9350 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9351
9352 if (vcpu->arch.exception.has_error_code) {
9353 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9354 vmcs12->idt_vectoring_error_code =
9355 vcpu->arch.exception.error_code;
9356 }
9357
9358 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9359 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9360 vmcs12->idt_vectoring_info_field =
9361 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9362 } else if (vcpu->arch.interrupt.pending) {
9363 nr = vcpu->arch.interrupt.nr;
9364 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9365
9366 if (vcpu->arch.interrupt.soft) {
9367 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9368 vmcs12->vm_entry_instruction_len =
9369 vcpu->arch.event_exit_inst_len;
9370 } else
9371 idt_vectoring |= INTR_TYPE_EXT_INTR;
9372
9373 vmcs12->idt_vectoring_info_field = idt_vectoring;
9374 }
9375}
9376
b6b8a145
JK		 9377static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9378{
9379 struct vcpu_vmx *vmx = to_vmx(vcpu);
9380
f4124500
JK		 9381 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9382 vmx->nested.preemption_timer_expired) {
9383 if (vmx->nested.nested_run_pending)
9384 return -EBUSY;
9385 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9386 return 0;
9387 }
9388
b6b8a145 9389 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9390 if (vmx->nested.nested_run_pending ||
9391 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9392 return -EBUSY;
9393 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9394 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9395 INTR_INFO_VALID_MASK, 0);
9396 /*
9397 * The NMI-triggered VM exit counts as injection:
9398 * clear this one and block further NMIs.
9399 */
9400 vcpu->arch.nmi_pending = 0;
9401 vmx_set_nmi_mask(vcpu, true);
9402 return 0;
9403 }
9404
9405 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9406 nested_exit_on_intr(vcpu)) {
9407 if (vmx->nested.nested_run_pending)
9408 return -EBUSY;
9409 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9410 }
9411
9412 return 0;
9413}
9414
f4124500
JK		 9415static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9416{
9417 ktime_t remaining =
9418 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9419 u64 value;
9420
9421 if (ktime_to_ns(remaining) <= 0)
9422 return 0;
9423
9424 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9425 do_div(value, 1000000);
9426 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9427}
9428
4704d0be
NHE		 9429/*
9430 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9431 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9432 * and this function updates it to reflect the changes to the guest state while
9433 * L2 was running (and perhaps made some exits which were handled directly by L0
9434 * without going back to L1), and to reflect the exit reason.
9435 * Note that we do not have to copy here all VMCS fields, just those that
9436 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9437 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9438 * which already writes to vmcs12 directly.
9439 */
533558bc
JK		 9440static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9441 u32 exit_reason, u32 exit_intr_info,
9442 unsigned long exit_qualification)
4704d0be
NHE		 9443{
9444 /* update guest state fields: */
9445 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9446 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9447
4704d0be
NHE		 9448 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9449 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9450 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9451
9452 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9453 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9454 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9455 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9456 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9457 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9458 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9459 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9460 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9461 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9462 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9463 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9464 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9465 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9466 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9467 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9468 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9469 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9470 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9471 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9472 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9473 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9474 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9475 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9476 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9477 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9478 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9479 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9480 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9481 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9482 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9483 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9484 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9485 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9486 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9487 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9488
4704d0be
NHE		 9489 vmcs12->guest_interruptibility_info =
9490 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9491 vmcs12->guest_pending_dbg_exceptions =
9492 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9493 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9494 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9495 else
9496 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9497
f4124500
JK		 9498 if (nested_cpu_has_preemption_timer(vmcs12)) {
9499 if (vmcs12->vm_exit_controls &
9500 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9501 vmcs12->vmx_preemption_timer_value =
9502 vmx_get_preemption_timer_value(vcpu);
9503 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9504 }
7854cbca 9505
3633cfc3
NHE		 9506 /*
9507 * In some cases (usually, nested EPT), L2 is allowed to change its
9508 * own CR3 without exiting. If it has changed it, we must keep it.
9509 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9510 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9511 *
9512 * Additionally, restore L2's PDPTR to vmcs12.
9513 */
9514 if (enable_ept) {
9515 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9516 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9517 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9518 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9519 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9520 }
9521
c18911a2
JK		 9522 vmcs12->vm_entry_controls =
9523 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9524 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9525
2996fca0
JK		 9526 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9527 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9528 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9529 }
9530
4704d0be
NHE		 9531 /* TODO: These cannot have changed unless we have MSR bitmaps and
9532 * the relevant bit asks not to trap the change */
b8c07d55 9533 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9534 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9535 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9536 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9537 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9538 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9539 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9540 if (vmx_mpx_supported())
9541 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9542 if (nested_cpu_has_xsaves(vmcs12))
9543 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9544
9545 /* update exit information fields: */
9546
533558bc
JK		 9547 vmcs12->vm_exit_reason = exit_reason;
9548 vmcs12->exit_qualification = exit_qualification;
4704d0be 9549
533558bc 9550 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9551 if ((vmcs12->vm_exit_intr_info &
9552 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9553 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9554 vmcs12->vm_exit_intr_error_code =
9555 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9556 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9557 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9558 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9559
5f3d5799
JK		 9560 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9561 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9562 * instead of reading the real value. */
4704d0be 9563 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9564
9565 /*
9566 * Transfer the event that L0 or L1 may wanted to inject into
9567 * L2 to IDT_VECTORING_INFO_FIELD.
9568 */
9569 vmcs12_save_pending_event(vcpu, vmcs12);
9570 }
9571
9572 /*
9573 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9574 * preserved above and would only end up incorrectly in L1.
9575 */
9576 vcpu->arch.nmi_injected = false;
9577 kvm_clear_exception_queue(vcpu);
9578 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9579}
9580
9581/*
9582 * A part of what we need to when the nested L2 guest exits and we want to
9583 * run its L1 parent, is to reset L1's guest state to the host state specified
9584 * in vmcs12.
9585 * This function is to be called not only on normal nested exit, but also on
9586 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9587 * Failures During or After Loading Guest State").
9588 * This function should be called when the active VMCS is L1's (vmcs01).
9589 */
733568f9
JK		 9590static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9591 struct vmcs12 *vmcs12)
4704d0be 9592{
21feb4eb
ACL		 9593 struct kvm_segment seg;
9594
4704d0be
NHE		 9595 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9596 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9597 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9598 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9599 else
9600 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9601 vmx_set_efer(vcpu, vcpu->arch.efer);
9602
9603 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9604 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9605 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9606 /*
9607 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9608 * actually changed, because it depends on the current state of
9609 * fpu_active (which may have changed).
9610 * Note that vmx_set_cr0 refers to efer set above.
9611 */
9e3e4dbf 9612 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9613 /*
9614 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9615 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9616 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9617 */
9618 update_exception_bitmap(vcpu);
9619 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9620 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9621
9622 /*
9623 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9624 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9625 */
9626 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9627 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9628
29bf08f1 9629 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9630
4704d0be
NHE		 9631 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9632 kvm_mmu_reset_context(vcpu);
9633
feaf0c7d
GN		 9634 if (!enable_ept)
9635 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9636
4704d0be
NHE		 9637 if (enable_vpid) {
9638 /*
9639 * Trivially support vpid by letting L2s share their parent
9640 * L1's vpid. TODO: move to a more elaborate solution, giving
9641 * each L2 its own vpid and exposing the vpid feature to L1.
9642 */
9643 vmx_flush_tlb(vcpu);
9644 }
9645
9646
9647 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9648 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9649 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9650 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9651 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9652
36be0b9d
PB		 9653 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9654 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9655 vmcs_write64(GUEST_BNDCFGS, 0);
9656
44811c02 9657 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9658 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9659 vcpu->arch.pat = vmcs12->host_ia32_pat;
9660 }
4704d0be
NHE		 9661 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9662 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9663 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9664
21feb4eb
ACL		 9665 /* Set L1 segment info according to Intel SDM
9666 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9667 seg = (struct kvm_segment) {
9668 .base = 0,
9669 .limit = 0xFFFFFFFF,
9670 .selector = vmcs12->host_cs_selector,
9671 .type = 11,
9672 .present = 1,
9673 .s = 1,
9674 .g = 1
9675 };
9676 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9677 seg.l = 1;
9678 else
9679 seg.db = 1;
9680 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9681 seg = (struct kvm_segment) {
9682 .base = 0,
9683 .limit = 0xFFFFFFFF,
9684 .type = 3,
9685 .present = 1,
9686 .s = 1,
9687 .db = 1,
9688 .g = 1
9689 };
9690 seg.selector = vmcs12->host_ds_selector;
9691 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9692 seg.selector = vmcs12->host_es_selector;
9693 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9694 seg.selector = vmcs12->host_ss_selector;
9695 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9696 seg.selector = vmcs12->host_fs_selector;
9697 seg.base = vmcs12->host_fs_base;
9698 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9699 seg.selector = vmcs12->host_gs_selector;
9700 seg.base = vmcs12->host_gs_base;
9701 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9702 seg = (struct kvm_segment) {
205befd9 9703 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9704 .limit = 0x67,
9705 .selector = vmcs12->host_tr_selector,
9706 .type = 11,
9707 .present = 1
9708 };
9709 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9710
503cd0c5
JK		 9711 kvm_set_dr(vcpu, 7, 0x400);
9712 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 9713
3af18d9c
WV		 9714 if (cpu_has_vmx_msr_bitmap())
9715 vmx_set_msr_bitmap(vcpu);
9716
ff651cb6
WV		 9717 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9718 vmcs12->vm_exit_msr_load_count))
9719 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9720}
9721
9722/*
9723 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9724 * and modify vmcs12 to make it see what it would expect to see there if
9725 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9726 */
533558bc
JK		 9727static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9728 u32 exit_intr_info,
9729 unsigned long exit_qualification)
4704d0be
NHE		 9730{
9731 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9732 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9733
5f3d5799
JK		 9734 /* trying to cancel vmlaunch/vmresume is a bug */
9735 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9736
4704d0be 9737 leave_guest_mode(vcpu);
533558bc
JK		 9738 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9739 exit_qualification);
4704d0be 9740
ff651cb6
WV		 9741 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9742 vmcs12->vm_exit_msr_store_count))
9743 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9744
f3380ca5
WL		 9745 vmx_load_vmcs01(vcpu);
9746
77b0f5d6
BD		 9747 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9748 && nested_exit_intr_ack_set(vcpu)) {
9749 int irq = kvm_cpu_get_interrupt(vcpu);
9750 WARN_ON(irq < 0);
9751 vmcs12->vm_exit_intr_info = irq |
9752 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9753 }
9754
542060ea
JK		 9755 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9756 vmcs12->exit_qualification,
9757 vmcs12->idt_vectoring_info_field,
9758 vmcs12->vm_exit_intr_info,
9759 vmcs12->vm_exit_intr_error_code,
9760 KVM_ISA_VMX);
4704d0be 9761
2961e876
GN		 9762 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9763 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9764 vmx_segment_cache_clear(vmx);
9765
4704d0be
NHE		 9766 /* if no vmcs02 cache requested, remove the one we used */
9767 if (VMCS02_POOL_SIZE == 0)
9768 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9769
9770 load_vmcs12_host_state(vcpu, vmcs12);
9771
27fc51b2 9772 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9773 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9774
9775 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9776 vmx->host_rsp = 0;
9777
9778 /* Unpin physical memory we referred to in vmcs02 */
9779 if (vmx->nested.apic_access_page) {
9780 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9781 vmx->nested.apic_access_page = NULL;
4704d0be 9782 }
a7c0b07d
WL		 9783 if (vmx->nested.virtual_apic_page) {
9784 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9785 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9786 }
4704d0be 9787
38b99173
TC		 9788 /*
9789 * We are now running in L2, mmu_notifier will force to reload the
9790 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9791 */
9792 kvm_vcpu_reload_apic_access_page(vcpu);
9793
4704d0be
NHE		 9794 /*
9795 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9796 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9797 * success or failure flag accordingly.
9798 */
9799 if (unlikely(vmx->fail)) {
9800 vmx->fail = 0;
9801 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9802 } else
9803 nested_vmx_succeed(vcpu);
012f83cb
AG		 9804 if (enable_shadow_vmcs)
9805 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9806
9807 /* in case we halted in L2 */
9808 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9809}
9810
42124925
JK		 9811/*
9812 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9813 */
9814static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9815{
9816 if (is_guest_mode(vcpu))
533558bc 9817 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9818 free_nested(to_vmx(vcpu));
9819}
9820
7c177938
NHE		 9821/*
9822 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9823 * 23.7 "VM-entry failures during or after loading guest state" (this also
9824 * lists the acceptable exit-reason and exit-qualification parameters).
9825 * It should only be called before L2 actually succeeded to run, and when
9826 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9827 */
9828static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9829 struct vmcs12 *vmcs12,
9830 u32 reason, unsigned long qualification)
9831{
9832 load_vmcs12_host_state(vcpu, vmcs12);
9833 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9834 vmcs12->exit_qualification = qualification;
9835 nested_vmx_succeed(vcpu);
012f83cb
AG		 9836 if (enable_shadow_vmcs)
9837 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9838}
9839
8a76d7f2
JR		 9840static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9841 struct x86_instruction_info *info,
9842 enum x86_intercept_stage stage)
9843{
9844 return X86EMUL_CONTINUE;
9845}
9846
48d89b92 9847static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9848{
b4a2d31d
RK		 9849 if (ple_gap)
9850 shrink_ple_window(vcpu);
ae97a3b8
RK		 9851}
9852
843e4330
KH		 9853static void vmx_slot_enable_log_dirty(struct kvm *kvm,
9854 struct kvm_memory_slot *slot)
9855{
9856 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
9857 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
9858}
9859
9860static void vmx_slot_disable_log_dirty(struct kvm *kvm,
9861 struct kvm_memory_slot *slot)
9862{
9863 kvm_mmu_slot_set_dirty(kvm, slot);
9864}
9865
9866static void vmx_flush_log_dirty(struct kvm *kvm)
9867{
9868 kvm_flush_pml_buffers(kvm);
9869}
9870
9871static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
9872 struct kvm_memory_slot *memslot,
9873 gfn_t offset, unsigned long mask)
9874{
9875 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
9876}
9877
cbdd1bea 9878static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9879 .cpu_has_kvm_support = cpu_has_kvm_support,
9880 .disabled_by_bios = vmx_disabled_by_bios,
9881 .hardware_setup = hardware_setup,
9882 .hardware_unsetup = hardware_unsetup,
002c7f7c 9883 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9884 .hardware_enable = hardware_enable,
9885 .hardware_disable = hardware_disable,
04547156 9886 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9887
9888 .vcpu_create = vmx_create_vcpu,
9889 .vcpu_free = vmx_free_vcpu,
04d2cc77 9890 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9891
04d2cc77 9892 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9893 .vcpu_load = vmx_vcpu_load,
9894 .vcpu_put = vmx_vcpu_put,
9895
c8639010 9896 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9897 .get_msr = vmx_get_msr,
9898 .set_msr = vmx_set_msr,
9899 .get_segment_base = vmx_get_segment_base,
9900 .get_segment = vmx_get_segment,
9901 .set_segment = vmx_set_segment,
2e4d2653 9902 .get_cpl = vmx_get_cpl,
6aa8b732 9903 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9904 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9905 .decache_cr3 = vmx_decache_cr3,
25c4c276 9906 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9907 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9908 .set_cr3 = vmx_set_cr3,
9909 .set_cr4 = vmx_set_cr4,
6aa8b732 9910 .set_efer = vmx_set_efer,
6aa8b732
AK		 9911 .get_idt = vmx_get_idt,
9912 .set_idt = vmx_set_idt,
9913 .get_gdt = vmx_get_gdt,
9914 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9915 .get_dr6 = vmx_get_dr6,
9916 .set_dr6 = vmx_set_dr6,
020df079 9917 .set_dr7 = vmx_set_dr7,
81908bf4 9918 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9919 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9920 .get_rflags = vmx_get_rflags,
9921 .set_rflags = vmx_set_rflags,
02daab21 9922 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9923
9924 .tlb_flush = vmx_flush_tlb,
6aa8b732 9925
6aa8b732 9926 .run = vmx_vcpu_run,
6062d012 9927 .handle_exit = vmx_handle_exit,
6aa8b732 9928 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9929 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9930 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9931 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9932 .set_irq = vmx_inject_irq,
95ba8273 9933 .set_nmi = vmx_inject_nmi,
298101da 9934 .queue_exception = vmx_queue_exception,
b463a6f7 9935 .cancel_injection = vmx_cancel_injection,
78646121 9936 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9937 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9938 .get_nmi_mask = vmx_get_nmi_mask,
9939 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9940 .enable_nmi_window = enable_nmi_window,
9941 .enable_irq_window = enable_irq_window,
9942 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9943 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9944 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9945 .vm_has_apicv = vmx_vm_has_apicv,
9946 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9947 .hwapic_irr_update = vmx_hwapic_irr_update,
9948 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9949 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9950 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9951
cbc94022 9952 .set_tss_addr = vmx_set_tss_addr,
67253af5 9953 .get_tdp_level = get_ept_level,
4b12f0de 9954 .get_mt_mask = vmx_get_mt_mask,
229456fc 9955
586f9607 9956 .get_exit_info = vmx_get_exit_info,
586f9607 9957
17cc3935 9958 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9959
9960 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9961
9962 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9963 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9964
9965 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9966
9967 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9968
4051b188 9969 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9970 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9971 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9972 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9973 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9974 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9975
9976 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9977
9978 .check_intercept = vmx_check_intercept,
a547c6db 9979 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9980 .mpx_supported = vmx_mpx_supported,
55412b2e 9981 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 9982
9983 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9984
9985 .sched_in = vmx_sched_in,
843e4330
KH		 9986
9987 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
9988 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
9989 .flush_log_dirty = vmx_flush_log_dirty,
9990 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 9991};
9992
9993static int __init vmx_init(void)
9994{
34a1cd60
TC		 9995 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9996 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9997 if (r)
34a1cd60 9998 return r;
25c5f225 9999
8f536b76
ZY		 10000#ifdef CONFIG_KEXEC
10001 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10002 crash_vmclear_local_loaded_vmcss);
10003#endif
10004
fdef3ad1 10005 return 0;
6aa8b732
AK		 10006}
10007
10008static void __exit vmx_exit(void)
10009{
8f536b76 10010#ifdef CONFIG_KEXEC
3b63a43f 10011 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10012 synchronize_rcu();
10013#endif
10014
cb498ea2 10015 kvm_exit();
6aa8b732
AK		 10016}
10017
10018module_init(vmx_init)
10019module_exit(vmx_exit)
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