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kvm: x86: i8259: return initialized data on invalid-size read
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
dab2087d 48#include <asm/apic.h>
6aa8b732 49
229456fc
MT		 50#include "trace.h"
51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6
SY		 534
535 bool rdtscp_enabled;
ec378aee 536
01e439be
YZ		 537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
539
ec378aee
NHE		 540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
a7653ecd
RK		 542
543 /* Dynamic PLE window. */
544 int ple_window;
545 bool ple_window_dirty;
843e4330
KH		 546
547 /* Support for PML */
548#define PML_ENTITY_NUM 512
549 struct page *pml_pg;
a2fa3e9f
GH		 550};
551
2fb92db1
AK		 552enum segment_cache_field {
553 SEG_FIELD_SEL = 0,
554 SEG_FIELD_BASE = 1,
555 SEG_FIELD_LIMIT = 2,
556 SEG_FIELD_AR = 3,
557
558 SEG_FIELD_NR = 4
559};
560
a2fa3e9f
GH		 561static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562{
fb3f0f51 563 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 564}
565
22bd0358
NHE		 566#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
4607c2d7 571
fe2b201b 572static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 573 /*
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
584 */
585 VM_EXIT_REASON,
586 VM_EXIT_INTR_INFO,
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
591 EXIT_QUALIFICATION,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
594};
fe2b201b 595static int max_shadow_read_only_fields =
4607c2d7
AG		 596 ARRAY_SIZE(shadow_read_only_fields);
597
fe2b201b 598static unsigned long shadow_read_write_fields[] = {
a7c0b07d 599 TPR_THRESHOLD,
4607c2d7
AG		 600 GUEST_RIP,
601 GUEST_RSP,
602 GUEST_CR0,
603 GUEST_CR3,
604 GUEST_CR4,
605 GUEST_INTERRUPTIBILITY_INFO,
606 GUEST_RFLAGS,
607 GUEST_CS_SELECTOR,
608 GUEST_CS_AR_BYTES,
609 GUEST_CS_LIMIT,
610 GUEST_CS_BASE,
611 GUEST_ES_BASE,
36be0b9d 612 GUEST_BNDCFGS,
4607c2d7
AG		 613 CR0_GUEST_HOST_MASK,
614 CR0_READ_SHADOW,
615 CR4_READ_SHADOW,
616 TSC_OFFSET,
617 EXCEPTION_BITMAP,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
623 HOST_FS_BASE,
624 HOST_GS_BASE,
625 HOST_FS_SELECTOR,
626 HOST_GS_SELECTOR
627};
fe2b201b 628static int max_shadow_read_write_fields =
4607c2d7
AG		 629 ARRAY_SIZE(shadow_read_write_fields);
630
772e0318 631static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 633 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 660 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
769};
22bd0358
NHE		 770
771static inline short vmcs_field_to_offset(unsigned long field)
772{
a2ae9df7
PB		 773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
777 return -ENOENT;
778
22bd0358
NHE		 779 return vmcs_field_to_offset_table[field];
780}
781
a9d30f33
NHE		 782static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783{
784 return to_vmx(vcpu)->nested.current_vmcs12;
785}
786
787static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788{
789 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 790 if (is_error_page(page))
a9d30f33 791 return NULL;
32cad84f 792
a9d30f33
NHE		 793 return page;
794}
795
796static void nested_release_page(struct page *page)
797{
798 kvm_release_page_dirty(page);
799}
800
801static void nested_release_page_clean(struct page *page)
802{
803 kvm_release_page_clean(page);
804}
805
bfd0a56b 806static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 807static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 808static void kvm_cpu_vmxon(u64 addr);
809static void kvm_cpu_vmxoff(void);
93c4adc7 810static bool vmx_mpx_supported(void);
f53cd63c 811static bool vmx_xsaves_supported(void);
705699a1 812static int vmx_vm_has_apicv(struct kvm *kvm);
776e58ea 813static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 814static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
d99e4152
GN		 818static bool guest_state_valid(struct kvm_vcpu *vcpu);
819static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 820static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 821static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 822static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 823static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 824
6aa8b732
AK		 825static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 827/*
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 */
831static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 832static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 833
3e7c73e9
AK		 834static unsigned long *vmx_io_bitmap_a;
835static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 836static unsigned long *vmx_msr_bitmap_legacy;
837static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 838static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 840static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 841static unsigned long *vmx_vmread_bitmap;
842static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 843
110312c8 844static bool cpu_has_load_ia32_efer;
8bf00a52 845static bool cpu_has_load_perf_global_ctrl;
110312c8 846
2384d2b3
SY		 847static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848static DEFINE_SPINLOCK(vmx_vpid_lock);
849
1c3d14fe 850static struct vmcs_config {
6aa8b732
AK		 851 int size;
852 int order;
853 u32 revision_id;
1c3d14fe
YS		 854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
f78e0e2e 856 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 857 u32 vmexit_ctrl;
858 u32 vmentry_ctrl;
859} vmcs_config;
6aa8b732 860
efff9e53 861static struct vmx_capability {
d56f546d
SY		 862 u32 ept;
863 u32 vpid;
864} vmx_capability;
865
6aa8b732
AK		 866#define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
872 }
873
772e0318 874static const struct kvm_vmx_segment_field {
6aa8b732
AK		 875 unsigned selector;
876 unsigned base;
877 unsigned limit;
878 unsigned ar_bytes;
879} kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
888};
889
26bb0981
AK		 890static u64 host_efer;
891
6de4f3ad
AK		 892static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
4d56c8a7 894/*
8c06585d 895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 896 * away by decrementing the array size.
897 */
6aa8b732 898static const u32 vmx_msr_index[] = {
05b3e0c2 899#ifdef CONFIG_X86_64
44ea2b17 900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 901#endif
8c06585d 902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 903};
6aa8b732 904
31299944 905static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 910}
911
31299944 912static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 917}
918
31299944 919static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 924}
925
31299944 926static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930}
931
31299944 932static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 933{
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937}
938
31299944 939static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 940{
04547156 941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 942}
943
31299944 944static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 945{
04547156 946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 947}
948
31299944 949static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 950{
04547156 951 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 952}
953
31299944 954static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 955{
04547156
SY		 956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 958}
959
774ead3a 960static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 961{
04547156
SY		 962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964}
965
8d14695f
YZ		 966static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967{
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970}
971
83d4c286
YZ		 972static inline bool cpu_has_vmx_apic_register_virt(void)
973{
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976}
977
c7c9c56c
YZ		 978static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982}
983
01e439be
YZ		 984static inline bool cpu_has_vmx_posted_intr(void)
985{
986 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
987}
988
989static inline bool cpu_has_vmx_apicv(void)
990{
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
994}
995
04547156
SY		 996static inline bool cpu_has_vmx_flexpriority(void)
997{
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1000}
1001
e799794e
MT		 1002static inline bool cpu_has_vmx_ept_execute_only(void)
1003{
31299944 1004 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1005}
1006
e799794e
MT		 1007static inline bool cpu_has_vmx_ept_2m_page(void)
1008{
31299944 1009 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1010}
1011
878403b7
SY		 1012static inline bool cpu_has_vmx_ept_1g_page(void)
1013{
31299944 1014 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1015}
1016
4bc9b982
SY		 1017static inline bool cpu_has_vmx_ept_4levels(void)
1018{
1019 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020}
1021
83c3a331
XH		 1022static inline bool cpu_has_vmx_ept_ad_bits(void)
1023{
1024 return vmx_capability.ept & VMX_EPT_AD_BIT;
1025}
1026
31299944 1027static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1028{
31299944 1029 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1033{
31299944 1034 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1035}
1036
518c8aee
GJ		 1037static inline bool cpu_has_vmx_invvpid_single(void)
1038{
1039 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040}
1041
b9d762fa
GJ		 1042static inline bool cpu_has_vmx_invvpid_global(void)
1043{
1044 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045}
1046
31299944 1047static inline bool cpu_has_vmx_ept(void)
d56f546d 1048{
04547156
SY		 1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1051}
1052
31299944 1053static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057}
1058
31299944 1059static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1060{
1061 return vmcs_config.cpu_based_2nd_exec_ctrl &
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063}
1064
31299944 1065static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1066{
6d3e435e 1067 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1068}
1069
31299944 1070static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1071{
04547156
SY		 1072 return vmcs_config.cpu_based_2nd_exec_ctrl &
1073 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1074}
1075
31299944 1076static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1077{
1078 return vmcs_config.cpu_based_2nd_exec_ctrl &
1079 SECONDARY_EXEC_RDTSCP;
1080}
1081
ad756a16
MJ		 1082static inline bool cpu_has_vmx_invpcid(void)
1083{
1084 return vmcs_config.cpu_based_2nd_exec_ctrl &
1085 SECONDARY_EXEC_ENABLE_INVPCID;
1086}
1087
31299944 1088static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1089{
1090 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f5f48ee1
SY		 1093static inline bool cpu_has_vmx_wbinvd_exit(void)
1094{
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_WBINVD_EXITING;
1097}
1098
abc4fc58
AG		 1099static inline bool cpu_has_vmx_shadow_vmcs(void)
1100{
1101 u64 vmx_msr;
1102 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105 return false;
1106
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_SHADOW_VMCS;
1109}
1110
843e4330
KH		 1111static inline bool cpu_has_vmx_pml(void)
1112{
1113 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114}
1115
04547156
SY		 1116static inline bool report_flexpriority(void)
1117{
1118 return flexpriority_enabled;
1119}
1120
fe3ef05c
NHE		 1121static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122{
1123 return vmcs12->cpu_based_vm_exec_control & bit;
1124}
1125
1126static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127{
1128 return (vmcs12->cpu_based_vm_exec_control &
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130 (vmcs12->secondary_vm_exec_control & bit);
1131}
1132
f5c4368f 1133static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1134{
1135 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136}
1137
f4124500
JK		 1138static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139{
1140 return vmcs12->pin_based_vm_exec_control &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1142}
1143
155a97a3
NHE		 1144static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145{
1146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147}
1148
81dc01f7
WL		 1149static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150{
1151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152 vmx_xsaves_supported();
1153}
1154
f2b93280
WV		 1155static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156{
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158}
1159
82f0dd4b
WV		 1160static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161{
1162 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163}
1164
608406e2
WV		 1165static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166{
1167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168}
1169
705699a1
WV		 1170static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171{
1172 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173}
1174
644d711a
NHE		 1175static inline bool is_exception(u32 intr_info)
1176{
1177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179}
1180
533558bc
JK		 1181static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182 u32 exit_intr_info,
1183 unsigned long exit_qualification);
7c177938
NHE		 1184static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185 struct vmcs12 *vmcs12,
1186 u32 reason, unsigned long qualification);
1187
8b9cf98c 1188static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1189{
1190 int i;
1191
a2fa3e9f 1192 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1194 return i;
1195 return -1;
1196}
1197
2384d2b3
SY		 1198static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199{
1200 struct {
1201 u64 vpid : 16;
1202 u64 rsvd : 48;
1203 u64 gva;
1204 } operand = { vpid, 0, gva };
1205
4ecac3fd 1206 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand), "c"(ext) : "cc", "memory");
1210}
1211
1439442c
SY		 1212static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213{
1214 struct {
1215 u64 eptp, gpa;
1216 } operand = {eptp, gpa};
1217
4ecac3fd 1218 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand), "c" (ext) : "cc", "memory");
1222}
1223
26bb0981 1224static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1225{
1226 int i;
1227
8b9cf98c 1228 i = __find_msr_index(vmx, msr);
a75beee6 1229 if (i >= 0)
a2fa3e9f 1230 return &vmx->guest_msrs[i];
8b6d44c7 1231 return NULL;
7725f0ba
AK		 1232}
1233
6aa8b732
AK		 1234static void vmcs_clear(struct vmcs *vmcs)
1235{
1236 u64 phys_addr = __pa(vmcs);
1237 u8 error;
1238
4ecac3fd 1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1240 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1241 : "cc", "memory");
1242 if (error)
1243 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244 vmcs, phys_addr);
1245}
1246
d462b819
NHE		 1247static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248{
1249 vmcs_clear(loaded_vmcs->vmcs);
1250 loaded_vmcs->cpu = -1;
1251 loaded_vmcs->launched = 0;
1252}
1253
7725b894
DX		 1254static void vmcs_load(struct vmcs *vmcs)
1255{
1256 u64 phys_addr = __pa(vmcs);
1257 u8 error;
1258
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1260 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1261 : "cc", "memory");
1262 if (error)
2844d849 1263 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1264 vmcs, phys_addr);
1265}
1266
8f536b76
ZY		 1267#ifdef CONFIG_KEXEC
1268/*
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1271 * default.
1272 */
1273static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275static inline void crash_enable_local_vmclear(int cpu)
1276{
1277 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278}
1279
1280static inline void crash_disable_local_vmclear(int cpu)
1281{
1282 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283}
1284
1285static inline int crash_local_vmclear_enabled(int cpu)
1286{
1287 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288}
1289
1290static void crash_vmclear_local_loaded_vmcss(void)
1291{
1292 int cpu = raw_smp_processor_id();
1293 struct loaded_vmcs *v;
1294
1295 if (!crash_local_vmclear_enabled(cpu))
1296 return;
1297
1298 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299 loaded_vmcss_on_cpu_link)
1300 vmcs_clear(v->vmcs);
1301}
1302#else
1303static inline void crash_enable_local_vmclear(int cpu) { }
1304static inline void crash_disable_local_vmclear(int cpu) { }
1305#endif /* CONFIG_KEXEC */
1306
d462b819 1307static void __loaded_vmcs_clear(void *arg)
6aa8b732 1308{
d462b819 1309 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1310 int cpu = raw_smp_processor_id();
6aa8b732 1311
d462b819
NHE		 1312 if (loaded_vmcs->cpu != cpu)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1315 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1316 crash_disable_local_vmclear(cpu);
d462b819 1317 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1318
1319 /*
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1324 */
1325 smp_wmb();
1326
d462b819 1327 loaded_vmcs_init(loaded_vmcs);
8f536b76 1328 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1329}
1330
d462b819 1331static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1332{
e6c7d321
XG		 1333 int cpu = loaded_vmcs->cpu;
1334
1335 if (cpu != -1)
1336 smp_call_function_single(cpu,
1337 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1338}
1339
1760dd49 1340static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1341{
1342 if (vmx->vpid == 0)
1343 return;
1344
518c8aee
GJ		 1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1347}
1348
b9d762fa
GJ		 1349static inline void vpid_sync_vcpu_global(void)
1350{
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353}
1354
1355static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356{
1357 if (cpu_has_vmx_invvpid_single())
1760dd49 1358 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1359 else
1360 vpid_sync_vcpu_global();
1361}
1362
1439442c
SY		 1363static inline void ept_sync_global(void)
1364{
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367}
1368
1369static inline void ept_sync_context(u64 eptp)
1370{
089d034e 1371 if (enable_ept) {
1439442c
SY		 1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374 else
1375 ept_sync_global();
1376 }
1377}
1378
96304217 1379static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1380{
5e520e62 1381 unsigned long value;
6aa8b732 1382
5e520e62
AK		 1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1385 return value;
1386}
1387
96304217 1388static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1389{
1390 return vmcs_readl(field);
1391}
1392
96304217 1393static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1394{
1395 return vmcs_readl(field);
1396}
1397
96304217 1398static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1399{
05b3e0c2 1400#ifdef CONFIG_X86_64
6aa8b732
AK		 1401 return vmcs_readl(field);
1402#else
1403 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404#endif
1405}
1406
e52de1b8
AK		 1407static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408{
1409 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411 dump_stack();
1412}
1413
6aa8b732
AK		 1414static void vmcs_writel(unsigned long field, unsigned long value)
1415{
1416 u8 error;
1417
4ecac3fd 1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1419 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1420 if (unlikely(error))
1421 vmwrite_error(field, value);
6aa8b732
AK		 1422}
1423
1424static void vmcs_write16(unsigned long field, u16 value)
1425{
1426 vmcs_writel(field, value);
1427}
1428
1429static void vmcs_write32(unsigned long field, u32 value)
1430{
1431 vmcs_writel(field, value);
1432}
1433
1434static void vmcs_write64(unsigned long field, u64 value)
1435{
6aa8b732 1436 vmcs_writel(field, value);
7682f2d0 1437#ifndef CONFIG_X86_64
6aa8b732
AK		 1438 asm volatile ("");
1439 vmcs_writel(field+1, value >> 32);
1440#endif
1441}
1442
2ab455cc
AL		 1443static void vmcs_clear_bits(unsigned long field, u32 mask)
1444{
1445 vmcs_writel(field, vmcs_readl(field) & ~mask);
1446}
1447
1448static void vmcs_set_bits(unsigned long field, u32 mask)
1449{
1450 vmcs_writel(field, vmcs_readl(field) | mask);
1451}
1452
2961e876
GN		 1453static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454{
1455 vmcs_write32(VM_ENTRY_CONTROLS, val);
1456 vmx->vm_entry_controls_shadow = val;
1457}
1458
1459static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460{
1461 if (vmx->vm_entry_controls_shadow != val)
1462 vm_entry_controls_init(vmx, val);
1463}
1464
1465static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466{
1467 return vmx->vm_entry_controls_shadow;
1468}
1469
1470
1471static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472{
1473 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474}
1475
1476static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477{
1478 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479}
1480
1481static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482{
1483 vmcs_write32(VM_EXIT_CONTROLS, val);
1484 vmx->vm_exit_controls_shadow = val;
1485}
1486
1487static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488{
1489 if (vmx->vm_exit_controls_shadow != val)
1490 vm_exit_controls_init(vmx, val);
1491}
1492
1493static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494{
1495 return vmx->vm_exit_controls_shadow;
1496}
1497
1498
1499static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500{
1501 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502}
1503
1504static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505{
1506 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507}
1508
2fb92db1
AK		 1509static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510{
1511 vmx->segment_cache.bitmask = 0;
1512}
1513
1514static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515 unsigned field)
1516{
1517 bool ret;
1518 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522 vmx->segment_cache.bitmask = 0;
1523 }
1524 ret = vmx->segment_cache.bitmask & mask;
1525 vmx->segment_cache.bitmask |= mask;
1526 return ret;
1527}
1528
1529static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530{
1531 u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535 return *p;
1536}
1537
1538static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539{
1540 ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544 return *p;
1545}
1546
1547static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548{
1549 u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553 return *p;
1554}
1555
1556static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557{
1558 u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562 return *p;
1563}
1564
abd3f2d6
AK		 1565static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566{
1567 u32 eb;
1568
fd7373cc
JK		 1569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571 if ((vcpu->guest_debug &
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574 eb |= 1u << BP_VECTOR;
7ffd92c5 1575 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1576 eb = ~0;
089d034e 1577 if (enable_ept)
1439442c 1578 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1579 if (vcpu->fpu_active)
1580 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1581
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1586 */
1587 if (is_guest_mode(vcpu))
1588 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
abd3f2d6
AK		 1590 vmcs_write32(EXCEPTION_BITMAP, eb);
1591}
1592
2961e876
GN		 1593static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594 unsigned long entry, unsigned long exit)
8bf00a52 1595{
2961e876
GN		 1596 vm_entry_controls_clearbit(vmx, entry);
1597 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1598}
1599
61d2ef2c
AK		 1600static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601{
1602 unsigned i;
1603 struct msr_autoload *m = &vmx->msr_autoload;
1604
8bf00a52
GN		 1605 switch (msr) {
1606 case MSR_EFER:
1607 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1608 clear_atomic_switch_msr_special(vmx,
1609 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1610 VM_EXIT_LOAD_IA32_EFER);
1611 return;
1612 }
1613 break;
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
2961e876 1616 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619 return;
1620 }
1621 break;
110312c8
AK		 1622 }
1623
61d2ef2c
AK		 1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1626 break;
1627
1628 if (i == m->nr)
1629 return;
1630 --m->nr;
1631 m->guest[i] = m->guest[m->nr];
1632 m->host[i] = m->host[m->nr];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635}
1636
2961e876
GN		 1637static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638 unsigned long entry, unsigned long exit,
1639 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640 u64 guest_val, u64 host_val)
8bf00a52
GN		 1641{
1642 vmcs_write64(guest_val_vmcs, guest_val);
1643 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1644 vm_entry_controls_setbit(vmx, entry);
1645 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1646}
1647
61d2ef2c
AK		 1648static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649 u64 guest_val, u64 host_val)
1650{
1651 unsigned i;
1652 struct msr_autoload *m = &vmx->msr_autoload;
1653
8bf00a52
GN		 1654 switch (msr) {
1655 case MSR_EFER:
1656 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1657 add_atomic_switch_msr_special(vmx,
1658 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1659 VM_EXIT_LOAD_IA32_EFER,
1660 GUEST_IA32_EFER,
1661 HOST_IA32_EFER,
1662 guest_val, host_val);
1663 return;
1664 }
1665 break;
1666 case MSR_CORE_PERF_GLOBAL_CTRL:
1667 if (cpu_has_load_perf_global_ctrl) {
2961e876 1668 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 GUEST_IA32_PERF_GLOBAL_CTRL,
1672 HOST_IA32_PERF_GLOBAL_CTRL,
1673 guest_val, host_val);
1674 return;
1675 }
1676 break;
110312c8
AK		 1677 }
1678
61d2ef2c
AK		 1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1681 break;
1682
e7fc6f93 1683 if (i == NR_AUTOLOAD_MSRS) {
60266204 1684 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1685 "Can't add msr %x\n", msr);
1686 return;
1687 } else if (i == m->nr) {
61d2ef2c
AK		 1688 ++m->nr;
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691 }
1692
1693 m->guest[i].index = msr;
1694 m->guest[i].value = guest_val;
1695 m->host[i].index = msr;
1696 m->host[i].value = host_val;
1697}
1698
33ed6329
AK		 1699static void reload_tss(void)
1700{
33ed6329
AK		 1701 /*
1702 * VT restores TR but not its size. Useless.
1703 */
89cbc767 1704 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1705 struct desc_struct *descs;
33ed6329 1706
d359192f 1707 descs = (void *)gdt->address;
33ed6329
AK		 1708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709 load_TR_desc();
33ed6329
AK		 1710}
1711
92c0d900 1712static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1713{
3a34a881 1714 u64 guest_efer;
51c6cf66
AK		 1715 u64 ignore_bits;
1716
f6801dff 1717 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1718
51c6cf66 1719 /*
0fa06071 1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1721 * outside long mode
1722 */
1723 ignore_bits = EFER_NX | EFER_SCE;
1724#ifdef CONFIG_X86_64
1725 ignore_bits |= EFER_LMA | EFER_LME;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer & EFER_LMA)
1728 ignore_bits &= ~(u64)EFER_SCE;
1729#endif
51c6cf66
AK		 1730 guest_efer &= ~ignore_bits;
1731 guest_efer |= host_efer & ignore_bits;
26bb0981 1732 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1734
1735 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1736
1737 /*
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1741 */
1742 if (cpu_has_load_ia32_efer ||
1743 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1744 guest_efer = vmx->vcpu.arch.efer;
1745 if (!(guest_efer & EFER_LMA))
1746 guest_efer &= ~EFER_LME;
54b98bff
AL		 1747 if (guest_efer != host_efer)
1748 add_atomic_switch_msr(vmx, MSR_EFER,
1749 guest_efer, host_efer);
84ad33ef
AK		 1750 return false;
1751 }
1752
26bb0981 1753 return true;
51c6cf66
AK		 1754}
1755
2d49ec72
GN		 1756static unsigned long segment_base(u16 selector)
1757{
89cbc767 1758 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1759 struct desc_struct *d;
1760 unsigned long table_base;
1761 unsigned long v;
1762
1763 if (!(selector & ~3))
1764 return 0;
1765
d359192f 1766 table_base = gdt->address;
2d49ec72
GN		 1767
1768 if (selector & 4) { /* from ldt */
1769 u16 ldt_selector = kvm_read_ldt();
1770
1771 if (!(ldt_selector & ~3))
1772 return 0;
1773
1774 table_base = segment_base(ldt_selector);
1775 }
1776 d = (struct desc_struct *)(table_base + (selector & ~7));
1777 v = get_desc_base(d);
1778#ifdef CONFIG_X86_64
1779 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781#endif
1782 return v;
1783}
1784
1785static inline unsigned long kvm_read_tr_base(void)
1786{
1787 u16 tr;
1788 asm("str %0" : "=g"(tr));
1789 return segment_base(tr);
1790}
1791
04d2cc77 1792static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1793{
04d2cc77 1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1795 int i;
04d2cc77 1796
a2fa3e9f 1797 if (vmx->host_state.loaded)
33ed6329
AK		 1798 return;
1799
a2fa3e9f 1800 vmx->host_state.loaded = 1;
33ed6329
AK		 1801 /*
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1804 */
d6e88aec 1805 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1806 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1807 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1808 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1809 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1810 vmx->host_state.fs_reload_needed = 0;
1811 } else {
33ed6329 1812 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1813 vmx->host_state.fs_reload_needed = 1;
33ed6329 1814 }
9581d442 1815 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1816 if (!(vmx->host_state.gs_sel & 7))
1817 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1818 else {
1819 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1820 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1821 }
1822
b2da15ac
AK		 1823#ifdef CONFIG_X86_64
1824 savesegment(ds, vmx->host_state.ds_sel);
1825 savesegment(es, vmx->host_state.es_sel);
1826#endif
1827
33ed6329
AK		 1828#ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831#else
a2fa3e9f
GH		 1832 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1834#endif
707c0874
AK		 1835
1836#ifdef CONFIG_X86_64
c8770e7b
AK		 1837 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838 if (is_long_mode(&vmx->vcpu))
44ea2b17 1839 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1840#endif
da8999d3
LJ		 1841 if (boot_cpu_has(X86_FEATURE_MPX))
1842 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1843 for (i = 0; i < vmx->save_nmsrs; ++i)
1844 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1845 vmx->guest_msrs[i].data,
1846 vmx->guest_msrs[i].mask);
33ed6329
AK		 1847}
1848
a9b21b62 1849static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1850{
a2fa3e9f 1851 if (!vmx->host_state.loaded)
33ed6329
AK		 1852 return;
1853
e1beb1d3 1854 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1855 vmx->host_state.loaded = 0;
c8770e7b
AK		 1856#ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx->vcpu))
1858 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859#endif
152d3f2f 1860 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1861 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1862#ifdef CONFIG_X86_64
9581d442 1863 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1864#else
1865 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1866#endif
33ed6329 1867 }
0a77fe4c
AK		 1868 if (vmx->host_state.fs_reload_needed)
1869 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1870#ifdef CONFIG_X86_64
1871 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872 loadsegment(ds, vmx->host_state.ds_sel);
1873 loadsegment(es, vmx->host_state.es_sel);
1874 }
b2da15ac 1875#endif
152d3f2f 1876 reload_tss();
44ea2b17 1877#ifdef CONFIG_X86_64
c8770e7b 1878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1879#endif
da8999d3
LJ		 1880 if (vmx->host_state.msr_host_bndcfgs)
1881 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1882 /*
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1885 */
1886 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887 stts();
89cbc767 1888 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1889}
1890
a9b21b62
AK		 1891static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892{
1893 preempt_disable();
1894 __vmx_load_host_state(vmx);
1895 preempt_enable();
1896}
1897
6aa8b732
AK		 1898/*
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1901 */
15ad7146 1902static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1903{
a2fa3e9f 1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1905 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1906
4610c9cc
DX		 1907 if (!vmm_exclusive)
1908 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1909 else if (vmx->loaded_vmcs->cpu != cpu)
1910 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1911
d462b819
NHE		 1912 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1915 }
1916
d462b819 1917 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1918 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1919 unsigned long sysenter_esp;
1920
a8eeb04a 1921 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1922 local_irq_disable();
8f536b76 1923 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1924
1925 /*
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1929 */
1930 smp_rmb();
1931
d462b819
NHE		 1932 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1934 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1935 local_irq_enable();
1936
6aa8b732
AK		 1937 /*
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1939 * processors.
1940 */
d6e88aec 1941 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1942 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1943
1944 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1946 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1947 }
6aa8b732
AK		 1948}
1949
1950static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951{
a9b21b62 1952 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1953 if (!vmm_exclusive) {
d462b819
NHE		 1954 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955 vcpu->cpu = -1;
4610c9cc
DX		 1956 kvm_cpu_vmxoff();
1957 }
6aa8b732
AK		 1958}
1959
5fd86fcf
AK		 1960static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961{
81231c69
AK		 1962 ulong cr0;
1963
5fd86fcf
AK		 1964 if (vcpu->fpu_active)
1965 return;
1966 vcpu->fpu_active = 1;
81231c69
AK		 1967 cr0 = vmcs_readl(GUEST_CR0);
1968 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1971 update_exception_bitmap(vcpu);
edcafe3c 1972 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1973 if (is_guest_mode(vcpu))
1974 vcpu->arch.cr0_guest_owned_bits &=
1975 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1977}
1978
edcafe3c
AK		 1979static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
fe3ef05c
NHE		 1981/*
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1985 */
1986static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987{
1988 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990}
1991static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992{
1993 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995}
1996
5fd86fcf
AK		 1997static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998{
36cf24e0
NHE		 1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2001 */
edcafe3c 2002 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2003 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2004 update_exception_bitmap(vcpu);
edcafe3c
AK		 2005 vcpu->arch.cr0_guest_owned_bits = 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2007 if (is_guest_mode(vcpu)) {
2008 /*
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2015 */
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018 (vcpu->arch.cr0 & X86_CR0_TS);
2019 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020 } else
2021 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2022}
2023
6aa8b732
AK		 2024static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025{
78ac8b47 2026 unsigned long rflags, save_rflags;
345dcaa8 2027
6de12732
AK		 2028 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030 rflags = vmcs_readl(GUEST_RFLAGS);
2031 if (to_vmx(vcpu)->rmode.vm86_active) {
2032 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035 }
2036 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2037 }
6de12732 2038 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2039}
2040
2041static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042{
6de12732
AK		 2043 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2045 if (to_vmx(vcpu)->rmode.vm86_active) {
2046 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2047 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2048 }
6aa8b732
AK		 2049 vmcs_writel(GUEST_RFLAGS, rflags);
2050}
2051
37ccdcbe 2052static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2053{
2054 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055 int ret = 0;
2056
2057 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2058 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2059 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2060 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2061
37ccdcbe 2062 return ret;
2809f5d2
GC		 2063}
2064
2065static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066{
2067 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068 u32 interruptibility = interruptibility_old;
2069
2070 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
48005f64 2072 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2073 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2074 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2075 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077 if ((interruptibility != interruptibility_old))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079}
2080
6aa8b732
AK		 2081static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082{
2083 unsigned long rip;
6aa8b732 2084
5fdbf976 2085 rip = kvm_rip_read(vcpu);
6aa8b732 2086 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2087 kvm_rip_write(vcpu, rip);
6aa8b732 2088
2809f5d2
GC		 2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2091}
2092
0b6ac343
NHE		 2093/*
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2096 */
e011c663 2097static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2098{
2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
e011c663 2101 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2102 return 0;
2103
533558bc
JK		 2104 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105 vmcs_read32(VM_EXIT_INTR_INFO),
2106 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2107 return 1;
2108}
2109
298101da 2110static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2111 bool has_error_code, u32 error_code,
2112 bool reinject)
298101da 2113{
77ab6db0 2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2115 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2116
e011c663
GN		 2117 if (!reinject && is_guest_mode(vcpu) &&
2118 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2119 return;
2120
8ab2d2e2 2121 if (has_error_code) {
77ab6db0 2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2123 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124 }
77ab6db0 2125
7ffd92c5 2126 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2127 int inc_eip = 0;
2128 if (kvm_exception_is_soft(nr))
2129 inc_eip = vcpu->arch.event_exit_inst_len;
2130 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2132 return;
2133 }
2134
66fd3f7f
GN		 2135 if (kvm_exception_is_soft(nr)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2138 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139 } else
2140 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2143}
2144
4e47c7a6
SY		 2145static bool vmx_rdtscp_supported(void)
2146{
2147 return cpu_has_vmx_rdtscp();
2148}
2149
ad756a16
MJ		 2150static bool vmx_invpcid_supported(void)
2151{
2152 return cpu_has_vmx_invpcid() && enable_ept;
2153}
2154
a75beee6
ED		 2155/*
2156 * Swap MSR entry in host/guest MSR entry array.
2157 */
8b9cf98c 2158static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2159{
26bb0981 2160 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2161
2162 tmp = vmx->guest_msrs[to];
2163 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2165}
2166
8d14695f
YZ		 2167static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168{
2169 unsigned long *msr_bitmap;
2170
2171 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2172 if (is_long_mode(vcpu))
2173 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2174 else
2175 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2176 } else {
2177 if (is_long_mode(vcpu))
2178 msr_bitmap = vmx_msr_bitmap_longmode;
2179 else
2180 msr_bitmap = vmx_msr_bitmap_legacy;
2181 }
2182
2183 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2184}
2185
e38aea3e
AK		 2186/*
2187 * Set up the vmcs to automatically save and restore system
2188 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2189 * mode, as fiddling with msrs is very expensive.
2190 */
8b9cf98c 2191static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2192{
26bb0981 2193 int save_nmsrs, index;
e38aea3e 2194
a75beee6
ED		 2195 save_nmsrs = 0;
2196#ifdef CONFIG_X86_64
8b9cf98c 2197 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2198 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2199 if (index >= 0)
8b9cf98c
RR		 2200 move_msr_up(vmx, index, save_nmsrs++);
2201 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2202 if (index >= 0)
8b9cf98c
RR		 2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2205 if (index >= 0)
8b9cf98c 2206 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2207 index = __find_msr_index(vmx, MSR_TSC_AUX);
2208 if (index >= 0 && vmx->rdtscp_enabled)
2209 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2210 /*
8c06585d 2211 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2212 * if efer.sce is enabled.
2213 */
8c06585d 2214 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2215 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2216 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2217 }
2218#endif
92c0d900
AK		 2219 index = __find_msr_index(vmx, MSR_EFER);
2220 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2221 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2222
26bb0981 2223 vmx->save_nmsrs = save_nmsrs;
5897297b 2224
8d14695f
YZ		 2225 if (cpu_has_vmx_msr_bitmap())
2226 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2227}
2228
6aa8b732
AK		 2229/*
2230 * reads and returns guest's timestamp counter "register"
2231 * guest_tsc = host_tsc + tsc_offset -- 21.3
2232 */
2233static u64 guest_read_tsc(void)
2234{
2235 u64 host_tsc, tsc_offset;
2236
2237 rdtscll(host_tsc);
2238 tsc_offset = vmcs_read64(TSC_OFFSET);
2239 return host_tsc + tsc_offset;
2240}
2241
d5c1785d
NHE		 2242/*
2243 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2244 * counter, even if a nested guest (L2) is currently running.
2245 */
48d89b92 2246static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2247{
886b470c 2248 u64 tsc_offset;
d5c1785d 2249
d5c1785d
NHE		 2250 tsc_offset = is_guest_mode(vcpu) ?
2251 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2252 vmcs_read64(TSC_OFFSET);
2253 return host_tsc + tsc_offset;
2254}
2255
4051b188 2256/*
cc578287
ZA		 2257 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2258 * software catchup for faster rates on slower CPUs.
4051b188 2259 */
cc578287 2260static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2261{
cc578287
ZA		 2262 if (!scale)
2263 return;
2264
2265 if (user_tsc_khz > tsc_khz) {
2266 vcpu->arch.tsc_catchup = 1;
2267 vcpu->arch.tsc_always_catchup = 1;
2268 } else
2269 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2270}
2271
ba904635
WA		 2272static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2273{
2274 return vmcs_read64(TSC_OFFSET);
2275}
2276
6aa8b732 2277/*
99e3e30a 2278 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2279 */
99e3e30a 2280static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2281{
27fc51b2 2282 if (is_guest_mode(vcpu)) {
7991825b 2283 /*
27fc51b2
NHE		 2284 * We're here if L1 chose not to trap WRMSR to TSC. According
2285 * to the spec, this should set L1's TSC; The offset that L1
2286 * set for L2 remains unchanged, and still needs to be added
2287 * to the newly set TSC to get L2's TSC.
7991825b 2288 */
27fc51b2
NHE		 2289 struct vmcs12 *vmcs12;
2290 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2291 /* recalculate vmcs02.TSC_OFFSET: */
2292 vmcs12 = get_vmcs12(vcpu);
2293 vmcs_write64(TSC_OFFSET, offset +
2294 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2295 vmcs12->tsc_offset : 0));
2296 } else {
489223ed
YY		 2297 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2298 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2299 vmcs_write64(TSC_OFFSET, offset);
2300 }
6aa8b732
AK		 2301}
2302
f1e2b260 2303static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2304{
2305 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2306
e48672fa 2307 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2308 if (is_guest_mode(vcpu)) {
2309 /* Even when running L2, the adjustment needs to apply to L1 */
2310 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2311 } else
2312 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2313 offset + adjustment);
e48672fa
ZA		 2314}
2315
857e4099
JR		 2316static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2317{
2318 return target_tsc - native_read_tsc();
2319}
2320
801d3424
NHE		 2321static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2322{
2323 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2324 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2325}
2326
2327/*
2328 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2329 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2330 * all guests if the "nested" module option is off, and can also be disabled
2331 * for a single guest by disabling its VMX cpuid bit.
2332 */
2333static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2334{
2335 return nested && guest_cpuid_has_vmx(vcpu);
2336}
2337
b87a51ae
NHE		 2338/*
2339 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2340 * returned for the various VMX controls MSRs when nested VMX is enabled.
2341 * The same values should also be used to verify that vmcs12 control fields are
2342 * valid during nested entry from L1 to L2.
2343 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2344 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2345 * bit in the high half is on if the corresponding bit in the control field
2346 * may be on. See also vmx_control_verify().
b87a51ae 2347 */
b9c237bb 2348static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2349{
2350 /*
2351 * Note that as a general rule, the high half of the MSRs (bits in
2352 * the control fields which may be 1) should be initialized by the
2353 * intersection of the underlying hardware's MSR (i.e., features which
2354 * can be supported) and the list of features we want to expose -
2355 * because they are known to be properly supported in our code.
2356 * Also, usually, the low half of the MSRs (bits which must be 1) can
2357 * be set to 0, meaning that L1 may turn off any of these bits. The
2358 * reason is that if one of these bits is necessary, it will appear
2359 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2360 * fields of vmcs01 and vmcs02, will turn these bits off - and
2361 * nested_vmx_exit_handled() will not pass related exits to L1.
2362 * These rules have exceptions below.
2363 */
2364
2365 /* pin-based controls */
eabeaacc 2366 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2367 vmx->nested.nested_vmx_pinbased_ctls_low,
2368 vmx->nested.nested_vmx_pinbased_ctls_high);
2369 vmx->nested.nested_vmx_pinbased_ctls_low |=
2370 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2371 vmx->nested.nested_vmx_pinbased_ctls_high &=
2372 PIN_BASED_EXT_INTR_MASK |
2373 PIN_BASED_NMI_EXITING |
2374 PIN_BASED_VIRTUAL_NMIS;
2375 vmx->nested.nested_vmx_pinbased_ctls_high |=
2376 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2377 PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1
WV		 2378 if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2379 vmx->nested.nested_vmx_pinbased_ctls_high |=
2380 PIN_BASED_POSTED_INTR;
b87a51ae 2381
3dbcd8da 2382 /* exit controls */
c0dfee58 2383 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2384 vmx->nested.nested_vmx_exit_ctls_low,
2385 vmx->nested.nested_vmx_exit_ctls_high);
2386 vmx->nested.nested_vmx_exit_ctls_low =
2387 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2388
b9c237bb 2389 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2390#ifdef CONFIG_X86_64
c0dfee58 2391 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2392#endif
f4124500 2393 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2394 vmx->nested.nested_vmx_exit_ctls_high |=
2395 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2396 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2397 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2398
36be0b9d 2399 if (vmx_mpx_supported())
b9c237bb 2400 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2401
2996fca0 2402 /* We support free control of debug control saving. */
b9c237bb
WV		 2403 vmx->nested.nested_vmx_true_exit_ctls_low =
2404 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2405 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2406
b87a51ae
NHE		 2407 /* entry controls */
2408 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2409 vmx->nested.nested_vmx_entry_ctls_low,
2410 vmx->nested.nested_vmx_entry_ctls_high);
2411 vmx->nested.nested_vmx_entry_ctls_low =
2412 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2413 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2414#ifdef CONFIG_X86_64
2415 VM_ENTRY_IA32E_MODE |
2416#endif
2417 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2418 vmx->nested.nested_vmx_entry_ctls_high |=
2419 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2420 if (vmx_mpx_supported())
b9c237bb 2421 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2422
2996fca0 2423 /* We support free control of debug control loading. */
b9c237bb
WV		 2424 vmx->nested.nested_vmx_true_entry_ctls_low =
2425 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2426 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2427
b87a51ae
NHE		 2428 /* cpu-based controls */
2429 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2430 vmx->nested.nested_vmx_procbased_ctls_low,
2431 vmx->nested.nested_vmx_procbased_ctls_high);
2432 vmx->nested.nested_vmx_procbased_ctls_low =
2433 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2434 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2435 CPU_BASED_VIRTUAL_INTR_PENDING |
2436 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2437 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2438 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2439 CPU_BASED_CR3_STORE_EXITING |
2440#ifdef CONFIG_X86_64
2441 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2442#endif
2443 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2444 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2445 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2446 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2447 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2448 /*
2449 * We can allow some features even when not supported by the
2450 * hardware. For example, L1 can specify an MSR bitmap - and we
2451 * can use it to avoid exits to L1 - even when L0 runs L2
2452 * without MSR bitmaps.
2453 */
b9c237bb
WV		 2454 vmx->nested.nested_vmx_procbased_ctls_high |=
2455 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2456 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2457
3dcdf3ec 2458 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2459 vmx->nested.nested_vmx_true_procbased_ctls_low =
2460 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2461 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2462
b87a51ae
NHE		 2463 /* secondary cpu-based controls */
2464 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2465 vmx->nested.nested_vmx_secondary_ctls_low,
2466 vmx->nested.nested_vmx_secondary_ctls_high);
2467 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2468 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2469 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
f2b93280 2470 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2471 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2472 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7
WL		 2473 SECONDARY_EXEC_WBINVD_EXITING |
2474 SECONDARY_EXEC_XSAVES;
c18911a2 2475
afa61f75
NHE		 2476 if (enable_ept) {
2477 /* nested EPT: emulate EPT also to L1 */
b9c237bb
WV		 2478 vmx->nested.nested_vmx_secondary_ctls_high |=
2479 SECONDARY_EXEC_ENABLE_EPT |
78051e3b 2480 SECONDARY_EXEC_UNRESTRICTED_GUEST;
b9c237bb 2481 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2482 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2483 VMX_EPT_INVEPT_BIT;
b9c237bb 2484 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2485 /*
4b855078
BD		 2486 * For nested guests, we don't do anything specific
2487 * for single context invalidation. Hence, only advertise
2488 * support for global context invalidation.
afa61f75 2489 */
b9c237bb 2490 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2491 } else
b9c237bb 2492 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2493
c18911a2 2494 /* miscellaneous data */
b9c237bb
WV		 2495 rdmsr(MSR_IA32_VMX_MISC,
2496 vmx->nested.nested_vmx_misc_low,
2497 vmx->nested.nested_vmx_misc_high);
2498 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2499 vmx->nested.nested_vmx_misc_low |=
2500 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2501 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2502 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2503}
2504
2505static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2506{
2507 /*
2508 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2509 */
2510 return ((control & high) | low) == control;
2511}
2512
2513static inline u64 vmx_control_msr(u32 low, u32 high)
2514{
2515 return low | ((u64)high << 32);
2516}
2517
cae50139 2518/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2519static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2520{
b9c237bb
WV		 2521 struct vcpu_vmx *vmx = to_vmx(vcpu);
2522
b87a51ae 2523 switch (msr_index) {
b87a51ae
NHE		 2524 case MSR_IA32_VMX_BASIC:
2525 /*
2526 * This MSR reports some information about VMX support. We
2527 * should return information about the VMX we emulate for the
2528 * guest, and the VMCS structure we give it - not about the
2529 * VMX support of the underlying hardware.
2530 */
3dbcd8da 2531 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2532 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2533 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2534 break;
2535 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2536 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2537 *pdata = vmx_control_msr(
2538 vmx->nested.nested_vmx_pinbased_ctls_low,
2539 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2540 break;
2541 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2542 *pdata = vmx_control_msr(
2543 vmx->nested.nested_vmx_true_procbased_ctls_low,
2544 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2545 break;
b87a51ae 2546 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2547 *pdata = vmx_control_msr(
2548 vmx->nested.nested_vmx_procbased_ctls_low,
2549 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2550 break;
2551 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2552 *pdata = vmx_control_msr(
2553 vmx->nested.nested_vmx_true_exit_ctls_low,
2554 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2555 break;
b87a51ae 2556 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2557 *pdata = vmx_control_msr(
2558 vmx->nested.nested_vmx_exit_ctls_low,
2559 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2560 break;
2561 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2562 *pdata = vmx_control_msr(
2563 vmx->nested.nested_vmx_true_entry_ctls_low,
2564 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2565 break;
b87a51ae 2566 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2567 *pdata = vmx_control_msr(
2568 vmx->nested.nested_vmx_entry_ctls_low,
2569 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2570 break;
2571 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2572 *pdata = vmx_control_msr(
2573 vmx->nested.nested_vmx_misc_low,
2574 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2575 break;
2576 /*
2577 * These MSRs specify bits which the guest must keep fixed (on or off)
2578 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2579 * We picked the standard core2 setting.
2580 */
2581#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2582#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2583 case MSR_IA32_VMX_CR0_FIXED0:
2584 *pdata = VMXON_CR0_ALWAYSON;
2585 break;
2586 case MSR_IA32_VMX_CR0_FIXED1:
2587 *pdata = -1ULL;
2588 break;
2589 case MSR_IA32_VMX_CR4_FIXED0:
2590 *pdata = VMXON_CR4_ALWAYSON;
2591 break;
2592 case MSR_IA32_VMX_CR4_FIXED1:
2593 *pdata = -1ULL;
2594 break;
2595 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2596 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2597 break;
2598 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2599 *pdata = vmx_control_msr(
2600 vmx->nested.nested_vmx_secondary_ctls_low,
2601 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2602 break;
2603 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2604 /* Currently, no nested vpid support */
b9c237bb 2605 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2606 break;
2607 default:
b87a51ae 2608 return 1;
b3897a49
NHE		 2609 }
2610
b87a51ae
NHE		 2611 return 0;
2612}
2613
6aa8b732
AK		 2614/*
2615 * Reads an msr value (of 'msr_index') into 'pdata'.
2616 * Returns 0 on success, non-0 otherwise.
2617 * Assumes vcpu_load() was already called.
2618 */
2619static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2620{
2621 u64 data;
26bb0981 2622 struct shared_msr_entry *msr;
6aa8b732
AK		 2623
2624 if (!pdata) {
2625 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2626 return -EINVAL;
2627 }
2628
2629 switch (msr_index) {
05b3e0c2 2630#ifdef CONFIG_X86_64
6aa8b732
AK		 2631 case MSR_FS_BASE:
2632 data = vmcs_readl(GUEST_FS_BASE);
2633 break;
2634 case MSR_GS_BASE:
2635 data = vmcs_readl(GUEST_GS_BASE);
2636 break;
44ea2b17
AK		 2637 case MSR_KERNEL_GS_BASE:
2638 vmx_load_host_state(to_vmx(vcpu));
2639 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2640 break;
26bb0981 2641#endif
6aa8b732 2642 case MSR_EFER:
3bab1f5d 2643 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2644 case MSR_IA32_TSC:
6aa8b732
AK		 2645 data = guest_read_tsc();
2646 break;
2647 case MSR_IA32_SYSENTER_CS:
2648 data = vmcs_read32(GUEST_SYSENTER_CS);
2649 break;
2650 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2651 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2652 break;
2653 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2654 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2655 break;
0dd376e7 2656 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2657 if (!vmx_mpx_supported())
2658 return 1;
0dd376e7
LJ		 2659 data = vmcs_read64(GUEST_BNDCFGS);
2660 break;
cae50139
JK		 2661 case MSR_IA32_FEATURE_CONTROL:
2662 if (!nested_vmx_allowed(vcpu))
2663 return 1;
2664 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2665 break;
2666 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2667 if (!nested_vmx_allowed(vcpu))
2668 return 1;
2669 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2670 case MSR_IA32_XSS:
2671 if (!vmx_xsaves_supported())
2672 return 1;
2673 data = vcpu->arch.ia32_xss;
2674 break;
4e47c7a6
SY		 2675 case MSR_TSC_AUX:
2676 if (!to_vmx(vcpu)->rdtscp_enabled)
2677 return 1;
2678 /* Otherwise falls through */
6aa8b732 2679 default:
8b9cf98c 2680 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2681 if (msr) {
2682 data = msr->data;
2683 break;
6aa8b732 2684 }
3bab1f5d 2685 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2686 }
2687
2688 *pdata = data;
2689 return 0;
2690}
2691
cae50139
JK		 2692static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2693
6aa8b732
AK		 2694/*
2695 * Writes msr value into into the appropriate "register".
2696 * Returns 0 on success, non-0 otherwise.
2697 * Assumes vcpu_load() was already called.
2698 */
8fe8ab46 2699static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2700{
a2fa3e9f 2701 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2702 struct shared_msr_entry *msr;
2cc51560 2703 int ret = 0;
8fe8ab46
WA		 2704 u32 msr_index = msr_info->index;
2705 u64 data = msr_info->data;
2cc51560 2706
6aa8b732 2707 switch (msr_index) {
3bab1f5d 2708 case MSR_EFER:
8fe8ab46 2709 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2710 break;
16175a79 2711#ifdef CONFIG_X86_64
6aa8b732 2712 case MSR_FS_BASE:
2fb92db1 2713 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2714 vmcs_writel(GUEST_FS_BASE, data);
2715 break;
2716 case MSR_GS_BASE:
2fb92db1 2717 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2718 vmcs_writel(GUEST_GS_BASE, data);
2719 break;
44ea2b17
AK		 2720 case MSR_KERNEL_GS_BASE:
2721 vmx_load_host_state(vmx);
2722 vmx->msr_guest_kernel_gs_base = data;
2723 break;
6aa8b732
AK		 2724#endif
2725 case MSR_IA32_SYSENTER_CS:
2726 vmcs_write32(GUEST_SYSENTER_CS, data);
2727 break;
2728 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2729 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2730 break;
2731 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2732 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2733 break;
0dd376e7 2734 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2735 if (!vmx_mpx_supported())
2736 return 1;
0dd376e7
LJ		 2737 vmcs_write64(GUEST_BNDCFGS, data);
2738 break;
af24a4e4 2739 case MSR_IA32_TSC:
8fe8ab46 2740 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2741 break;
468d472f
SY		 2742 case MSR_IA32_CR_PAT:
2743 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2744 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2745 return 1;
468d472f
SY		 2746 vmcs_write64(GUEST_IA32_PAT, data);
2747 vcpu->arch.pat = data;
2748 break;
2749 }
8fe8ab46 2750 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2751 break;
ba904635
WA		 2752 case MSR_IA32_TSC_ADJUST:
2753 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2754 break;
cae50139
JK		 2755 case MSR_IA32_FEATURE_CONTROL:
2756 if (!nested_vmx_allowed(vcpu) ||
2757 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2758 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2759 return 1;
2760 vmx->nested.msr_ia32_feature_control = data;
2761 if (msr_info->host_initiated && data == 0)
2762 vmx_leave_nested(vcpu);
2763 break;
2764 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2765 return 1; /* they are read-only */
20300099
WL		 2766 case MSR_IA32_XSS:
2767 if (!vmx_xsaves_supported())
2768 return 1;
2769 /*
2770 * The only supported bit as of Skylake is bit 8, but
2771 * it is not supported on KVM.
2772 */
2773 if (data != 0)
2774 return 1;
2775 vcpu->arch.ia32_xss = data;
2776 if (vcpu->arch.ia32_xss != host_xss)
2777 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2778 vcpu->arch.ia32_xss, host_xss);
2779 else
2780 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2781 break;
4e47c7a6
SY		 2782 case MSR_TSC_AUX:
2783 if (!vmx->rdtscp_enabled)
2784 return 1;
2785 /* Check reserved bit, higher 32 bits should be zero */
2786 if ((data >> 32) != 0)
2787 return 1;
2788 /* Otherwise falls through */
6aa8b732 2789 default:
8b9cf98c 2790 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2791 if (msr) {
8b3c3104 2792 u64 old_msr_data = msr->data;
3bab1f5d 2793 msr->data = data;
2225fd56
AK		 2794 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2795 preempt_disable();
8b3c3104
AH		 2796 ret = kvm_set_shared_msr(msr->index, msr->data,
2797 msr->mask);
2225fd56 2798 preempt_enable();
8b3c3104
AH		 2799 if (ret)
2800 msr->data = old_msr_data;
2225fd56 2801 }
3bab1f5d 2802 break;
6aa8b732 2803 }
8fe8ab46 2804 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2805 }
2806
2cc51560 2807 return ret;
6aa8b732
AK		 2808}
2809
5fdbf976 2810static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2811{
5fdbf976
MT		 2812 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2813 switch (reg) {
2814 case VCPU_REGS_RSP:
2815 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2816 break;
2817 case VCPU_REGS_RIP:
2818 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2819 break;
6de4f3ad
AK		 2820 case VCPU_EXREG_PDPTR:
2821 if (enable_ept)
2822 ept_save_pdptrs(vcpu);
2823 break;
5fdbf976
MT		 2824 default:
2825 break;
2826 }
6aa8b732
AK		 2827}
2828
6aa8b732
AK		 2829static __init int cpu_has_kvm_support(void)
2830{
6210e37b 2831 return cpu_has_vmx();
6aa8b732
AK		 2832}
2833
2834static __init int vmx_disabled_by_bios(void)
2835{
2836 u64 msr;
2837
2838 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2839 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2840 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2841 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2842 && tboot_enabled())
2843 return 1;
23f3e991 2844 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2845 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2846 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2847 && !tboot_enabled()) {
2848 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2849 "activate TXT before enabling KVM\n");
cafd6659 2850 return 1;
f9335afe 2851 }
23f3e991
JC		 2852 /* launched w/o TXT and VMX disabled */
2853 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2854 && !tboot_enabled())
2855 return 1;
cafd6659
SW		 2856 }
2857
2858 return 0;
6aa8b732
AK		 2859}
2860
7725b894
DX		 2861static void kvm_cpu_vmxon(u64 addr)
2862{
2863 asm volatile (ASM_VMX_VMXON_RAX
2864 : : "a"(&addr), "m"(addr)
2865 : "memory", "cc");
2866}
2867
13a34e06 2868static int hardware_enable(void)
6aa8b732
AK		 2869{
2870 int cpu = raw_smp_processor_id();
2871 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2872 u64 old, test_bits;
6aa8b732 2873
1e02ce4c 2874 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2875 return -EBUSY;
2876
d462b819 2877 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2878
2879 /*
2880 * Now we can enable the vmclear operation in kdump
2881 * since the loaded_vmcss_on_cpu list on this cpu
2882 * has been initialized.
2883 *
2884 * Though the cpu is not in VMX operation now, there
2885 * is no problem to enable the vmclear operation
2886 * for the loaded_vmcss_on_cpu list is empty!
2887 */
2888 crash_enable_local_vmclear(cpu);
2889
6aa8b732 2890 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2891
2892 test_bits = FEATURE_CONTROL_LOCKED;
2893 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2894 if (tboot_enabled())
2895 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2896
2897 if ((old & test_bits) != test_bits) {
6aa8b732 2898 /* enable and lock */
cafd6659
SW		 2899 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2900 }
375074cc 2901 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2902
4610c9cc
DX		 2903 if (vmm_exclusive) {
2904 kvm_cpu_vmxon(phys_addr);
2905 ept_sync_global();
2906 }
10474ae8 2907
89cbc767 2908 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2909
10474ae8 2910 return 0;
6aa8b732
AK		 2911}
2912
d462b819 2913static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2914{
2915 int cpu = raw_smp_processor_id();
d462b819 2916 struct loaded_vmcs *v, *n;
543e4243 2917
d462b819
NHE		 2918 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2919 loaded_vmcss_on_cpu_link)
2920 __loaded_vmcs_clear(v);
543e4243
AK		 2921}
2922
710ff4a8
EH		 2923
2924/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2925 * tricks.
2926 */
2927static void kvm_cpu_vmxoff(void)
6aa8b732 2928{
4ecac3fd 2929 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2930}
2931
13a34e06 2932static void hardware_disable(void)
710ff4a8 2933{
4610c9cc 2934 if (vmm_exclusive) {
d462b819 2935 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2936 kvm_cpu_vmxoff();
2937 }
375074cc 2938 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2939}
2940
1c3d14fe 2941static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2942 u32 msr, u32 *result)
1c3d14fe
YS		 2943{
2944 u32 vmx_msr_low, vmx_msr_high;
2945 u32 ctl = ctl_min | ctl_opt;
2946
2947 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2948
2949 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2950 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2951
2952 /* Ensure minimum (required) set of control bits are supported. */
2953 if (ctl_min & ~ctl)
002c7f7c 2954 return -EIO;
1c3d14fe
YS		 2955
2956 *result = ctl;
2957 return 0;
2958}
2959
110312c8
AK		 2960static __init bool allow_1_setting(u32 msr, u32 ctl)
2961{
2962 u32 vmx_msr_low, vmx_msr_high;
2963
2964 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2965 return vmx_msr_high & ctl;
2966}
2967
002c7f7c 2968static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2969{
2970 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2971 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2972 u32 _pin_based_exec_control = 0;
2973 u32 _cpu_based_exec_control = 0;
f78e0e2e 2974 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2975 u32 _vmexit_control = 0;
2976 u32 _vmentry_control = 0;
2977
10166744 2978 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2979#ifdef CONFIG_X86_64
2980 CPU_BASED_CR8_LOAD_EXITING |
2981 CPU_BASED_CR8_STORE_EXITING |
2982#endif
d56f546d
SY		 2983 CPU_BASED_CR3_LOAD_EXITING |
2984 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2985 CPU_BASED_USE_IO_BITMAPS |
2986 CPU_BASED_MOV_DR_EXITING |
a7052897 2987 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2988 CPU_BASED_MWAIT_EXITING |
2989 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2990 CPU_BASED_INVLPG_EXITING |
2991 CPU_BASED_RDPMC_EXITING;
443381a8 2992
f78e0e2e 2993 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2994 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2995 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2996 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2997 &_cpu_based_exec_control) < 0)
002c7f7c 2998 return -EIO;
6e5d865c
YS		 2999#ifdef CONFIG_X86_64
3000 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3001 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3002 ~CPU_BASED_CR8_STORE_EXITING;
3003#endif
f78e0e2e 3004 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3005 min2 = 0;
3006 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3007 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3008 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3009 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3010 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3011 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3012 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3013 SECONDARY_EXEC_RDTSCP |
83d4c286 3014 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3015 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3016 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3017 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 3018 SECONDARY_EXEC_XSAVES |
3019 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 3020 if (adjust_vmx_controls(min2, opt2,
3021 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3022 &_cpu_based_2nd_exec_control) < 0)
3023 return -EIO;
3024 }
3025#ifndef CONFIG_X86_64
3026 if (!(_cpu_based_2nd_exec_control &
3027 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3028 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3029#endif
83d4c286
YZ		 3030
3031 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3032 _cpu_based_2nd_exec_control &= ~(
8d14695f 3033 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3034 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3036
d56f546d 3037 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3038 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3039 enabled */
5fff7d27
GN		 3040 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3041 CPU_BASED_CR3_STORE_EXITING |
3042 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3043 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3044 vmx_capability.ept, vmx_capability.vpid);
3045 }
1c3d14fe 3046
81908bf4 3047 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3048#ifdef CONFIG_X86_64
3049 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3050#endif
a547c6db 3051 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3052 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3053 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3054 &_vmexit_control) < 0)
002c7f7c 3055 return -EIO;
1c3d14fe 3056
01e439be
YZ		 3057 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3058 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3059 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3060 &_pin_based_exec_control) < 0)
3061 return -EIO;
3062
3063 if (!(_cpu_based_2nd_exec_control &
3064 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3065 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3066 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3067
c845f9c6 3068 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3069 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3070 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3071 &_vmentry_control) < 0)
002c7f7c 3072 return -EIO;
6aa8b732 3073
c68876fd 3074 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3075
3076 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3077 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3078 return -EIO;
1c3d14fe
YS		 3079
3080#ifdef CONFIG_X86_64
3081 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3082 if (vmx_msr_high & (1u<<16))
002c7f7c 3083 return -EIO;
1c3d14fe
YS		 3084#endif
3085
3086 /* Require Write-Back (WB) memory type for VMCS accesses. */
3087 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3088 return -EIO;
1c3d14fe 3089
002c7f7c
YS		 3090 vmcs_conf->size = vmx_msr_high & 0x1fff;
3091 vmcs_conf->order = get_order(vmcs_config.size);
3092 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3093
002c7f7c
YS		 3094 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3095 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3096 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3097 vmcs_conf->vmexit_ctrl = _vmexit_control;
3098 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3099
110312c8
AK		 3100 cpu_has_load_ia32_efer =
3101 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3102 VM_ENTRY_LOAD_IA32_EFER)
3103 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3104 VM_EXIT_LOAD_IA32_EFER);
3105
8bf00a52
GN		 3106 cpu_has_load_perf_global_ctrl =
3107 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3108 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3109 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3110 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3111
3112 /*
3113 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3114 * but due to arrata below it can't be used. Workaround is to use
3115 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3116 *
3117 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3118 *
3119 * AAK155 (model 26)
3120 * AAP115 (model 30)
3121 * AAT100 (model 37)
3122 * BC86,AAY89,BD102 (model 44)
3123 * BA97 (model 46)
3124 *
3125 */
3126 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3127 switch (boot_cpu_data.x86_model) {
3128 case 26:
3129 case 30:
3130 case 37:
3131 case 44:
3132 case 46:
3133 cpu_has_load_perf_global_ctrl = false;
3134 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3135 "does not work properly. Using workaround\n");
3136 break;
3137 default:
3138 break;
3139 }
3140 }
3141
20300099
WL		 3142 if (cpu_has_xsaves)
3143 rdmsrl(MSR_IA32_XSS, host_xss);
3144
1c3d14fe 3145 return 0;
c68876fd 3146}
6aa8b732
AK		 3147
3148static struct vmcs *alloc_vmcs_cpu(int cpu)
3149{
3150 int node = cpu_to_node(cpu);
3151 struct page *pages;
3152 struct vmcs *vmcs;
3153
6484eb3e 3154 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3155 if (!pages)
3156 return NULL;
3157 vmcs = page_address(pages);
1c3d14fe
YS		 3158 memset(vmcs, 0, vmcs_config.size);
3159 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3160 return vmcs;
3161}
3162
3163static struct vmcs *alloc_vmcs(void)
3164{
d3b2c338 3165 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3166}
3167
3168static void free_vmcs(struct vmcs *vmcs)
3169{
1c3d14fe 3170 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3171}
3172
d462b819
NHE		 3173/*
3174 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3175 */
3176static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3177{
3178 if (!loaded_vmcs->vmcs)
3179 return;
3180 loaded_vmcs_clear(loaded_vmcs);
3181 free_vmcs(loaded_vmcs->vmcs);
3182 loaded_vmcs->vmcs = NULL;
3183}
3184
39959588 3185static void free_kvm_area(void)
6aa8b732
AK		 3186{
3187 int cpu;
3188
3230bb47 3189 for_each_possible_cpu(cpu) {
6aa8b732 3190 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3191 per_cpu(vmxarea, cpu) = NULL;
3192 }
6aa8b732
AK		 3193}
3194
fe2b201b
BD		 3195static void init_vmcs_shadow_fields(void)
3196{
3197 int i, j;
3198
3199 /* No checks for read only fields yet */
3200
3201 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3202 switch (shadow_read_write_fields[i]) {
3203 case GUEST_BNDCFGS:
3204 if (!vmx_mpx_supported())
3205 continue;
3206 break;
3207 default:
3208 break;
3209 }
3210
3211 if (j < i)
3212 shadow_read_write_fields[j] =
3213 shadow_read_write_fields[i];
3214 j++;
3215 }
3216 max_shadow_read_write_fields = j;
3217
3218 /* shadowed fields guest access without vmexit */
3219 for (i = 0; i < max_shadow_read_write_fields; i++) {
3220 clear_bit(shadow_read_write_fields[i],
3221 vmx_vmwrite_bitmap);
3222 clear_bit(shadow_read_write_fields[i],
3223 vmx_vmread_bitmap);
3224 }
3225 for (i = 0; i < max_shadow_read_only_fields; i++)
3226 clear_bit(shadow_read_only_fields[i],
3227 vmx_vmread_bitmap);
3228}
3229
6aa8b732
AK		 3230static __init int alloc_kvm_area(void)
3231{
3232 int cpu;
3233
3230bb47 3234 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3235 struct vmcs *vmcs;
3236
3237 vmcs = alloc_vmcs_cpu(cpu);
3238 if (!vmcs) {
3239 free_kvm_area();
3240 return -ENOMEM;
3241 }
3242
3243 per_cpu(vmxarea, cpu) = vmcs;
3244 }
3245 return 0;
3246}
3247
14168786
GN		 3248static bool emulation_required(struct kvm_vcpu *vcpu)
3249{
3250 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3251}
3252
91b0aa2c 3253static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3254 struct kvm_segment *save)
6aa8b732 3255{
d99e4152
GN		 3256 if (!emulate_invalid_guest_state) {
3257 /*
3258 * CS and SS RPL should be equal during guest entry according
3259 * to VMX spec, but in reality it is not always so. Since vcpu
3260 * is in the middle of the transition from real mode to
3261 * protected mode it is safe to assume that RPL 0 is a good
3262 * default value.
3263 */
3264 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3265 save->selector &= ~SELECTOR_RPL_MASK;
3266 save->dpl = save->selector & SELECTOR_RPL_MASK;
3267 save->s = 1;
6aa8b732 3268 }
d99e4152 3269 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3270}
3271
3272static void enter_pmode(struct kvm_vcpu *vcpu)
3273{
3274 unsigned long flags;
a89a8fb9 3275 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3276
d99e4152
GN		 3277 /*
3278 * Update real mode segment cache. It may be not up-to-date if sement
3279 * register was written while vcpu was in a guest mode.
3280 */
3281 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3282 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3287
7ffd92c5 3288 vmx->rmode.vm86_active = 0;
6aa8b732 3289
2fb92db1
AK		 3290 vmx_segment_cache_clear(vmx);
3291
f5f7b2fe 3292 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3293
3294 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3295 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3296 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3297 vmcs_writel(GUEST_RFLAGS, flags);
3298
66aee91a
RR		 3299 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3300 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3301
3302 update_exception_bitmap(vcpu);
3303
91b0aa2c
GN		 3304 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3305 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3306 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3307 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3308 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3309 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3310}
3311
f5f7b2fe 3312static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3313{
772e0318 3314 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3315 struct kvm_segment var = *save;
3316
3317 var.dpl = 0x3;
3318 if (seg == VCPU_SREG_CS)
3319 var.type = 0x3;
3320
3321 if (!emulate_invalid_guest_state) {
3322 var.selector = var.base >> 4;
3323 var.base = var.base & 0xffff0;
3324 var.limit = 0xffff;
3325 var.g = 0;
3326 var.db = 0;
3327 var.present = 1;
3328 var.s = 1;
3329 var.l = 0;
3330 var.unusable = 0;
3331 var.type = 0x3;
3332 var.avl = 0;
3333 if (save->base & 0xf)
3334 printk_once(KERN_WARNING "kvm: segment base is not "
3335 "paragraph aligned when entering "
3336 "protected mode (seg=%d)", seg);
3337 }
6aa8b732 3338
d99e4152
GN		 3339 vmcs_write16(sf->selector, var.selector);
3340 vmcs_write32(sf->base, var.base);
3341 vmcs_write32(sf->limit, var.limit);
3342 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3343}
3344
3345static void enter_rmode(struct kvm_vcpu *vcpu)
3346{
3347 unsigned long flags;
a89a8fb9 3348 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3349
f5f7b2fe
AK		 3350 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3351 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3352 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3357
7ffd92c5 3358 vmx->rmode.vm86_active = 1;
6aa8b732 3359
776e58ea
GN		 3360 /*
3361 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3362 * vcpu. Warn the user that an update is overdue.
776e58ea 3363 */
4918c6ca 3364 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3365 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3366 "called before entering vcpu\n");
776e58ea 3367
2fb92db1
AK		 3368 vmx_segment_cache_clear(vmx);
3369
4918c6ca 3370 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3371 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3372 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3373
3374 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3375 vmx->rmode.save_rflags = flags;
6aa8b732 3376
053de044 3377 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3378
3379 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3380 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3381 update_exception_bitmap(vcpu);
3382
d99e4152
GN		 3383 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3384 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3385 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3386 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3387 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3388 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3389
8668a3c4 3390 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3391}
3392
401d10de
AS		 3393static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3394{
3395 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3396 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3397
3398 if (!msr)
3399 return;
401d10de 3400
44ea2b17
AK		 3401 /*
3402 * Force kernel_gs_base reloading before EFER changes, as control
3403 * of this msr depends on is_long_mode().
3404 */
3405 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3406 vcpu->arch.efer = efer;
401d10de 3407 if (efer & EFER_LMA) {
2961e876 3408 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3409 msr->data = efer;
3410 } else {
2961e876 3411 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3412
3413 msr->data = efer & ~EFER_LME;
3414 }
3415 setup_msrs(vmx);
3416}
3417
05b3e0c2 3418#ifdef CONFIG_X86_64
6aa8b732
AK		 3419
3420static void enter_lmode(struct kvm_vcpu *vcpu)
3421{
3422 u32 guest_tr_ar;
3423
2fb92db1
AK		 3424 vmx_segment_cache_clear(to_vmx(vcpu));
3425
6aa8b732
AK		 3426 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3427 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3428 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3429 __func__);
6aa8b732
AK		 3430 vmcs_write32(GUEST_TR_AR_BYTES,
3431 (guest_tr_ar & ~AR_TYPE_MASK)
3432 | AR_TYPE_BUSY_64_TSS);
3433 }
da38f438 3434 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3435}
3436
3437static void exit_lmode(struct kvm_vcpu *vcpu)
3438{
2961e876 3439 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3440 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3441}
3442
3443#endif
3444
2384d2b3
SY		 3445static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3446{
b9d762fa 3447 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3448 if (enable_ept) {
3449 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3450 return;
4e1096d2 3451 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3452 }
2384d2b3
SY		 3453}
3454
e8467fda
AK		 3455static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3456{
3457 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3458
3459 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3460 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3461}
3462
aff48baa
AK		 3463static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3464{
3465 if (enable_ept && is_paging(vcpu))
3466 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3467 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3468}
3469
25c4c276 3470static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3471{
fc78f519
AK		 3472 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3473
3474 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3475 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3476}
3477
1439442c
SY		 3478static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3479{
d0d538b9
GN		 3480 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3481
6de4f3ad
AK		 3482 if (!test_bit(VCPU_EXREG_PDPTR,
3483 (unsigned long *)&vcpu->arch.regs_dirty))
3484 return;
3485
1439442c 3486 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3487 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3488 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3489 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3490 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3491 }
3492}
3493
8f5d549f
AK		 3494static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3495{
d0d538b9
GN		 3496 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3497
8f5d549f 3498 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3499 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3500 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3501 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3502 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3503 }
6de4f3ad
AK		 3504
3505 __set_bit(VCPU_EXREG_PDPTR,
3506 (unsigned long *)&vcpu->arch.regs_avail);
3507 __set_bit(VCPU_EXREG_PDPTR,
3508 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3509}
3510
5e1746d6 3511static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3512
3513static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3514 unsigned long cr0,
3515 struct kvm_vcpu *vcpu)
3516{
5233dd51
MT		 3517 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3518 vmx_decache_cr3(vcpu);
1439442c
SY		 3519 if (!(cr0 & X86_CR0_PG)) {
3520 /* From paging/starting to nonpaging */
3521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3522 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3523 (CPU_BASED_CR3_LOAD_EXITING |
3524 CPU_BASED_CR3_STORE_EXITING));
3525 vcpu->arch.cr0 = cr0;
fc78f519 3526 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3527 } else if (!is_paging(vcpu)) {
3528 /* From nonpaging to paging */
3529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3530 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3531 ~(CPU_BASED_CR3_LOAD_EXITING |
3532 CPU_BASED_CR3_STORE_EXITING));
3533 vcpu->arch.cr0 = cr0;
fc78f519 3534 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3535 }
95eb84a7
SY		 3536
3537 if (!(cr0 & X86_CR0_WP))
3538 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3539}
3540
6aa8b732
AK		 3541static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3542{
7ffd92c5 3543 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3544 unsigned long hw_cr0;
3545
5037878e 3546 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3547 if (enable_unrestricted_guest)
5037878e 3548 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3549 else {
5037878e 3550 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3551
218e763f
GN		 3552 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3553 enter_pmode(vcpu);
6aa8b732 3554
218e763f
GN		 3555 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3556 enter_rmode(vcpu);
3557 }
6aa8b732 3558
05b3e0c2 3559#ifdef CONFIG_X86_64
f6801dff 3560 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3561 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3562 enter_lmode(vcpu);
707d92fa 3563 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3564 exit_lmode(vcpu);
3565 }
3566#endif
3567
089d034e 3568 if (enable_ept)
1439442c
SY		 3569 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3570
02daab21 3571 if (!vcpu->fpu_active)
81231c69 3572 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3573
6aa8b732 3574 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3575 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3576 vcpu->arch.cr0 = cr0;
14168786
GN		 3577
3578 /* depends on vcpu->arch.cr0 to be set to a new value */
3579 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3580}
3581
1439442c
SY		 3582static u64 construct_eptp(unsigned long root_hpa)
3583{
3584 u64 eptp;
3585
3586 /* TODO write the value reading from MSR */
3587 eptp = VMX_EPT_DEFAULT_MT |
3588 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3589 if (enable_ept_ad_bits)
3590 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3591 eptp |= (root_hpa & PAGE_MASK);
3592
3593 return eptp;
3594}
3595
6aa8b732
AK		 3596static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3597{
1439442c
SY		 3598 unsigned long guest_cr3;
3599 u64 eptp;
3600
3601 guest_cr3 = cr3;
089d034e 3602 if (enable_ept) {
1439442c
SY		 3603 eptp = construct_eptp(cr3);
3604 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3605 if (is_paging(vcpu) || is_guest_mode(vcpu))
3606 guest_cr3 = kvm_read_cr3(vcpu);
3607 else
3608 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3609 ept_load_pdptrs(vcpu);
1439442c
SY		 3610 }
3611
2384d2b3 3612 vmx_flush_tlb(vcpu);
1439442c 3613 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3614}
3615
5e1746d6 3616static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3617{
7ffd92c5 3618 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3619 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3620
5e1746d6
NHE		 3621 if (cr4 & X86_CR4_VMXE) {
3622 /*
3623 * To use VMXON (and later other VMX instructions), a guest
3624 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3625 * So basically the check on whether to allow nested VMX
3626 * is here.
3627 */
3628 if (!nested_vmx_allowed(vcpu))
3629 return 1;
1a0d74e6
JK		 3630 }
3631 if (to_vmx(vcpu)->nested.vmxon &&
3632 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3633 return 1;
3634
ad312c7c 3635 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3636 if (enable_ept) {
3637 if (!is_paging(vcpu)) {
3638 hw_cr4 &= ~X86_CR4_PAE;
3639 hw_cr4 |= X86_CR4_PSE;
c08800a5 3640 /*
e1e746b3
FW		 3641 * SMEP/SMAP is disabled if CPU is in non-paging mode
3642 * in hardware. However KVM always uses paging mode to
c08800a5 3643 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3644 * To emulate this behavior, SMEP/SMAP needs to be
3645 * manually disabled when guest switches to non-paging
3646 * mode.
c08800a5 3647 */
e1e746b3 3648 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3649 } else if (!(cr4 & X86_CR4_PAE)) {
3650 hw_cr4 &= ~X86_CR4_PAE;
3651 }
3652 }
1439442c
SY		 3653
3654 vmcs_writel(CR4_READ_SHADOW, cr4);
3655 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3656 return 0;
6aa8b732
AK		 3657}
3658
6aa8b732
AK		 3659static void vmx_get_segment(struct kvm_vcpu *vcpu,
3660 struct kvm_segment *var, int seg)
3661{
a9179499 3662 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3663 u32 ar;
3664
c6ad1153 3665 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3666 *var = vmx->rmode.segs[seg];
a9179499 3667 if (seg == VCPU_SREG_TR
2fb92db1 3668 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3669 return;
1390a28b
AK		 3670 var->base = vmx_read_guest_seg_base(vmx, seg);
3671 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3672 return;
a9179499 3673 }
2fb92db1
AK		 3674 var->base = vmx_read_guest_seg_base(vmx, seg);
3675 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3676 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3677 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3678 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3679 var->type = ar & 15;
3680 var->s = (ar >> 4) & 1;
3681 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3682 /*
3683 * Some userspaces do not preserve unusable property. Since usable
3684 * segment has to be present according to VMX spec we can use present
3685 * property to amend userspace bug by making unusable segment always
3686 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3687 * segment as unusable.
3688 */
3689 var->present = !var->unusable;
6aa8b732
AK		 3690 var->avl = (ar >> 12) & 1;
3691 var->l = (ar >> 13) & 1;
3692 var->db = (ar >> 14) & 1;
3693 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3694}
3695
a9179499
AK		 3696static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3697{
a9179499
AK		 3698 struct kvm_segment s;
3699
3700 if (to_vmx(vcpu)->rmode.vm86_active) {
3701 vmx_get_segment(vcpu, &s, seg);
3702 return s.base;
3703 }
2fb92db1 3704 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3705}
3706
b09408d0 3707static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3708{
b09408d0
MT		 3709 struct vcpu_vmx *vmx = to_vmx(vcpu);
3710
ae9fedc7 3711 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3712 return 0;
ae9fedc7
PB		 3713 else {
3714 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3715 return AR_DPL(ar);
69c73028 3716 }
69c73028
AK		 3717}
3718
653e3108 3719static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3720{
6aa8b732
AK		 3721 u32 ar;
3722
f0495f9b 3723 if (var->unusable || !var->present)
6aa8b732
AK		 3724 ar = 1 << 16;
3725 else {
3726 ar = var->type & 15;
3727 ar |= (var->s & 1) << 4;
3728 ar |= (var->dpl & 3) << 5;
3729 ar |= (var->present & 1) << 7;
3730 ar |= (var->avl & 1) << 12;
3731 ar |= (var->l & 1) << 13;
3732 ar |= (var->db & 1) << 14;
3733 ar |= (var->g & 1) << 15;
3734 }
653e3108
AK		 3735
3736 return ar;
3737}
3738
3739static void vmx_set_segment(struct kvm_vcpu *vcpu,
3740 struct kvm_segment *var, int seg)
3741{
7ffd92c5 3742 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3743 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3744
2fb92db1
AK		 3745 vmx_segment_cache_clear(vmx);
3746
1ecd50a9
GN		 3747 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3748 vmx->rmode.segs[seg] = *var;
3749 if (seg == VCPU_SREG_TR)
3750 vmcs_write16(sf->selector, var->selector);
3751 else if (var->s)
3752 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3753 goto out;
653e3108 3754 }
1ecd50a9 3755
653e3108
AK		 3756 vmcs_writel(sf->base, var->base);
3757 vmcs_write32(sf->limit, var->limit);
3758 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3759
3760 /*
3761 * Fix the "Accessed" bit in AR field of segment registers for older
3762 * qemu binaries.
3763 * IA32 arch specifies that at the time of processor reset the
3764 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3765 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3766 * state vmexit when "unrestricted guest" mode is turned on.
3767 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3768 * tree. Newer qemu binaries with that qemu fix would not need this
3769 * kvm hack.
3770 */
3771 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3772 var->type |= 0x1; /* Accessed */
3a624e29 3773
f924d66d 3774 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3775
3776out:
98eb2f8b 3777 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3778}
3779
6aa8b732
AK		 3780static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3781{
2fb92db1 3782 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3783
3784 *db = (ar >> 14) & 1;
3785 *l = (ar >> 13) & 1;
3786}
3787
89a27f4d 3788static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3789{
89a27f4d
GN		 3790 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3791 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3792}
3793
89a27f4d 3794static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3795{
89a27f4d
GN		 3796 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3797 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3798}
3799
89a27f4d 3800static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3801{
89a27f4d
GN		 3802 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3803 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3804}
3805
89a27f4d 3806static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3807{
89a27f4d
GN		 3808 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3809 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3810}
3811
648dfaa7
MG		 3812static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3813{
3814 struct kvm_segment var;
3815 u32 ar;
3816
3817 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3818 var.dpl = 0x3;
0647f4aa
GN		 3819 if (seg == VCPU_SREG_CS)
3820 var.type = 0x3;
648dfaa7
MG		 3821 ar = vmx_segment_access_rights(&var);
3822
3823 if (var.base != (var.selector << 4))
3824 return false;
89efbed0 3825 if (var.limit != 0xffff)
648dfaa7 3826 return false;
07f42f5f 3827 if (ar != 0xf3)
648dfaa7
MG		 3828 return false;
3829
3830 return true;
3831}
3832
3833static bool code_segment_valid(struct kvm_vcpu *vcpu)
3834{
3835 struct kvm_segment cs;
3836 unsigned int cs_rpl;
3837
3838 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3839 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3840
1872a3f4
AK		 3841 if (cs.unusable)
3842 return false;
648dfaa7
MG		 3843 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3844 return false;
3845 if (!cs.s)
3846 return false;
1872a3f4 3847 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3848 if (cs.dpl > cs_rpl)
3849 return false;
1872a3f4 3850 } else {
648dfaa7
MG		 3851 if (cs.dpl != cs_rpl)
3852 return false;
3853 }
3854 if (!cs.present)
3855 return false;
3856
3857 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3858 return true;
3859}
3860
3861static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3862{
3863 struct kvm_segment ss;
3864 unsigned int ss_rpl;
3865
3866 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3867 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3868
1872a3f4
AK		 3869 if (ss.unusable)
3870 return true;
3871 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3872 return false;
3873 if (!ss.s)
3874 return false;
3875 if (ss.dpl != ss_rpl) /* DPL != RPL */
3876 return false;
3877 if (!ss.present)
3878 return false;
3879
3880 return true;
3881}
3882
3883static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3884{
3885 struct kvm_segment var;
3886 unsigned int rpl;
3887
3888 vmx_get_segment(vcpu, &var, seg);
3889 rpl = var.selector & SELECTOR_RPL_MASK;
3890
1872a3f4
AK		 3891 if (var.unusable)
3892 return true;
648dfaa7
MG		 3893 if (!var.s)
3894 return false;
3895 if (!var.present)
3896 return false;
3897 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3898 if (var.dpl < rpl) /* DPL < RPL */
3899 return false;
3900 }
3901
3902 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3903 * rights flags
3904 */
3905 return true;
3906}
3907
3908static bool tr_valid(struct kvm_vcpu *vcpu)
3909{
3910 struct kvm_segment tr;
3911
3912 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3913
1872a3f4
AK		 3914 if (tr.unusable)
3915 return false;
648dfaa7
MG		 3916 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3917 return false;
1872a3f4 3918 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3919 return false;
3920 if (!tr.present)
3921 return false;
3922
3923 return true;
3924}
3925
3926static bool ldtr_valid(struct kvm_vcpu *vcpu)
3927{
3928 struct kvm_segment ldtr;
3929
3930 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3931
1872a3f4
AK		 3932 if (ldtr.unusable)
3933 return true;
648dfaa7
MG		 3934 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3935 return false;
3936 if (ldtr.type != 2)
3937 return false;
3938 if (!ldtr.present)
3939 return false;
3940
3941 return true;
3942}
3943
3944static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3945{
3946 struct kvm_segment cs, ss;
3947
3948 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3949 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3950
3951 return ((cs.selector & SELECTOR_RPL_MASK) ==
3952 (ss.selector & SELECTOR_RPL_MASK));
3953}
3954
3955/*
3956 * Check if guest state is valid. Returns true if valid, false if
3957 * not.
3958 * We assume that registers are always usable
3959 */
3960static bool guest_state_valid(struct kvm_vcpu *vcpu)
3961{
c5e97c80
GN		 3962 if (enable_unrestricted_guest)
3963 return true;
3964
648dfaa7 3965 /* real mode guest state checks */
f13882d8 3966 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3967 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3968 return false;
3969 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3970 return false;
3971 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3972 return false;
3973 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3974 return false;
3975 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3976 return false;
3977 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3978 return false;
3979 } else {
3980 /* protected mode guest state checks */
3981 if (!cs_ss_rpl_check(vcpu))
3982 return false;
3983 if (!code_segment_valid(vcpu))
3984 return false;
3985 if (!stack_segment_valid(vcpu))
3986 return false;
3987 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3988 return false;
3989 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3990 return false;
3991 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3992 return false;
3993 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3994 return false;
3995 if (!tr_valid(vcpu))
3996 return false;
3997 if (!ldtr_valid(vcpu))
3998 return false;
3999 }
4000 /* TODO:
4001 * - Add checks on RIP
4002 * - Add checks on RFLAGS
4003 */
4004
4005 return true;
4006}
4007
d77c26fc 4008static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4009{
40dcaa9f 4010 gfn_t fn;
195aefde 4011 u16 data = 0;
1f755a82 4012 int idx, r;
6aa8b732 4013
40dcaa9f 4014 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4015 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4016 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4017 if (r < 0)
10589a46 4018 goto out;
195aefde 4019 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4020 r = kvm_write_guest_page(kvm, fn++, &data,
4021 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4022 if (r < 0)
10589a46 4023 goto out;
195aefde
IE		 4024 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4025 if (r < 0)
10589a46 4026 goto out;
195aefde
IE		 4027 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4028 if (r < 0)
10589a46 4029 goto out;
195aefde 4030 data = ~0;
10589a46
MT		 4031 r = kvm_write_guest_page(kvm, fn, &data,
4032 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4033 sizeof(u8));
10589a46 4034out:
40dcaa9f 4035 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4036 return r;
6aa8b732
AK		 4037}
4038
b7ebfb05
SY		 4039static int init_rmode_identity_map(struct kvm *kvm)
4040{
f51770ed 4041 int i, idx, r = 0;
b7ebfb05
SY		 4042 pfn_t identity_map_pfn;
4043 u32 tmp;
4044
089d034e 4045 if (!enable_ept)
f51770ed 4046 return 0;
a255d479
TC		 4047
4048 /* Protect kvm->arch.ept_identity_pagetable_done. */
4049 mutex_lock(&kvm->slots_lock);
4050
f51770ed 4051 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4052 goto out2;
a255d479 4053
b927a3ce 4054 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4055
4056 r = alloc_identity_pagetable(kvm);
f51770ed 4057 if (r < 0)
a255d479
TC		 4058 goto out2;
4059
40dcaa9f 4060 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4061 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4062 if (r < 0)
4063 goto out;
4064 /* Set up identity-mapping pagetable for EPT in real mode */
4065 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4066 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4067 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4068 r = kvm_write_guest_page(kvm, identity_map_pfn,
4069 &tmp, i * sizeof(tmp), sizeof(tmp));
4070 if (r < 0)
4071 goto out;
4072 }
4073 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4074
b7ebfb05 4075out:
40dcaa9f 4076 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4077
4078out2:
4079 mutex_unlock(&kvm->slots_lock);
f51770ed 4080 return r;
b7ebfb05
SY		 4081}
4082
6aa8b732
AK		 4083static void seg_setup(int seg)
4084{
772e0318 4085 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4086 unsigned int ar;
6aa8b732
AK		 4087
4088 vmcs_write16(sf->selector, 0);
4089 vmcs_writel(sf->base, 0);
4090 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4091 ar = 0x93;
4092 if (seg == VCPU_SREG_CS)
4093 ar |= 0x08; /* code segment */
3a624e29
NK		 4094
4095 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4096}
4097
f78e0e2e
SY		 4098static int alloc_apic_access_page(struct kvm *kvm)
4099{
4484141a 4100 struct page *page;
f78e0e2e
SY		 4101 struct kvm_userspace_memory_region kvm_userspace_mem;
4102 int r = 0;
4103
79fac95e 4104 mutex_lock(&kvm->slots_lock);
c24ae0dc 4105 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4106 goto out;
4107 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4108 kvm_userspace_mem.flags = 0;
73a6d941 4109 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4110 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4111 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4112 if (r)
4113 goto out;
72dc67a6 4114
73a6d941 4115 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4116 if (is_error_page(page)) {
4117 r = -EFAULT;
4118 goto out;
4119 }
4120
c24ae0dc
TC		 4121 /*
4122 * Do not pin the page in memory, so that memory hot-unplug
4123 * is able to migrate it.
4124 */
4125 put_page(page);
4126 kvm->arch.apic_access_page_done = true;
f78e0e2e 4127out:
79fac95e 4128 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4129 return r;
4130}
4131
b7ebfb05
SY		 4132static int alloc_identity_pagetable(struct kvm *kvm)
4133{
a255d479
TC		 4134 /* Called with kvm->slots_lock held. */
4135
b7ebfb05
SY		 4136 struct kvm_userspace_memory_region kvm_userspace_mem;
4137 int r = 0;
4138
a255d479
TC		 4139 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4140
b7ebfb05
SY		 4141 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4142 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4143 kvm_userspace_mem.guest_phys_addr =
4144 kvm->arch.ept_identity_map_addr;
b7ebfb05 4145 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4146 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4147
b7ebfb05
SY		 4148 return r;
4149}
4150
2384d2b3
SY		 4151static void allocate_vpid(struct vcpu_vmx *vmx)
4152{
4153 int vpid;
4154
4155 vmx->vpid = 0;
919818ab 4156 if (!enable_vpid)
2384d2b3
SY		 4157 return;
4158 spin_lock(&vmx_vpid_lock);
4159 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4160 if (vpid < VMX_NR_VPIDS) {
4161 vmx->vpid = vpid;
4162 __set_bit(vpid, vmx_vpid_bitmap);
4163 }
4164 spin_unlock(&vmx_vpid_lock);
4165}
4166
cdbecfc3
LJ		 4167static void free_vpid(struct vcpu_vmx *vmx)
4168{
4169 if (!enable_vpid)
4170 return;
4171 spin_lock(&vmx_vpid_lock);
4172 if (vmx->vpid != 0)
4173 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4174 spin_unlock(&vmx_vpid_lock);
4175}
4176
8d14695f
YZ		 4177#define MSR_TYPE_R 1
4178#define MSR_TYPE_W 2
4179static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4180 u32 msr, int type)
25c5f225 4181{
3e7c73e9 4182 int f = sizeof(unsigned long);
25c5f225
SY		 4183
4184 if (!cpu_has_vmx_msr_bitmap())
4185 return;
4186
4187 /*
4188 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4189 * have the write-low and read-high bitmap offsets the wrong way round.
4190 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4191 */
25c5f225 4192 if (msr <= 0x1fff) {
8d14695f
YZ		 4193 if (type & MSR_TYPE_R)
4194 /* read-low */
4195 __clear_bit(msr, msr_bitmap + 0x000 / f);
4196
4197 if (type & MSR_TYPE_W)
4198 /* write-low */
4199 __clear_bit(msr, msr_bitmap + 0x800 / f);
4200
25c5f225
SY		 4201 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4202 msr &= 0x1fff;
8d14695f
YZ		 4203 if (type & MSR_TYPE_R)
4204 /* read-high */
4205 __clear_bit(msr, msr_bitmap + 0x400 / f);
4206
4207 if (type & MSR_TYPE_W)
4208 /* write-high */
4209 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4210
4211 }
4212}
4213
4214static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4215 u32 msr, int type)
4216{
4217 int f = sizeof(unsigned long);
4218
4219 if (!cpu_has_vmx_msr_bitmap())
4220 return;
4221
4222 /*
4223 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4224 * have the write-low and read-high bitmap offsets the wrong way round.
4225 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4226 */
4227 if (msr <= 0x1fff) {
4228 if (type & MSR_TYPE_R)
4229 /* read-low */
4230 __set_bit(msr, msr_bitmap + 0x000 / f);
4231
4232 if (type & MSR_TYPE_W)
4233 /* write-low */
4234 __set_bit(msr, msr_bitmap + 0x800 / f);
4235
4236 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4237 msr &= 0x1fff;
4238 if (type & MSR_TYPE_R)
4239 /* read-high */
4240 __set_bit(msr, msr_bitmap + 0x400 / f);
4241
4242 if (type & MSR_TYPE_W)
4243 /* write-high */
4244 __set_bit(msr, msr_bitmap + 0xc00 / f);
4245
25c5f225 4246 }
25c5f225
SY		 4247}
4248
f2b93280
WV		 4249/*
4250 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4251 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4252 */
4253static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4254 unsigned long *msr_bitmap_nested,
4255 u32 msr, int type)
4256{
4257 int f = sizeof(unsigned long);
4258
4259 if (!cpu_has_vmx_msr_bitmap()) {
4260 WARN_ON(1);
4261 return;
4262 }
4263
4264 /*
4265 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4266 * have the write-low and read-high bitmap offsets the wrong way round.
4267 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4268 */
4269 if (msr <= 0x1fff) {
4270 if (type & MSR_TYPE_R &&
4271 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4272 /* read-low */
4273 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4274
4275 if (type & MSR_TYPE_W &&
4276 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4277 /* write-low */
4278 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4279
4280 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4281 msr &= 0x1fff;
4282 if (type & MSR_TYPE_R &&
4283 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4284 /* read-high */
4285 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4286
4287 if (type & MSR_TYPE_W &&
4288 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4289 /* write-high */
4290 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4291
4292 }
4293}
4294
5897297b
AK		 4295static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4296{
4297 if (!longmode_only)
8d14695f
YZ		 4298 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4299 msr, MSR_TYPE_R | MSR_TYPE_W);
4300 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4301 msr, MSR_TYPE_R | MSR_TYPE_W);
4302}
4303
4304static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4305{
4306 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4307 msr, MSR_TYPE_R);
4308 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4309 msr, MSR_TYPE_R);
4310}
4311
4312static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4313{
4314 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4315 msr, MSR_TYPE_R);
4316 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4317 msr, MSR_TYPE_R);
4318}
4319
4320static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4321{
4322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4323 msr, MSR_TYPE_W);
4324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4325 msr, MSR_TYPE_W);
5897297b
AK		 4326}
4327
01e439be
YZ		 4328static int vmx_vm_has_apicv(struct kvm *kvm)
4329{
4330 return enable_apicv && irqchip_in_kernel(kvm);
4331}
4332
705699a1
WV		 4333static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4334{
4335 struct vcpu_vmx *vmx = to_vmx(vcpu);
4336 int max_irr;
4337 void *vapic_page;
4338 u16 status;
4339
4340 if (vmx->nested.pi_desc &&
4341 vmx->nested.pi_pending) {
4342 vmx->nested.pi_pending = false;
4343 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4344 return 0;
4345
4346 max_irr = find_last_bit(
4347 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4348
4349 if (max_irr == 256)
4350 return 0;
4351
4352 vapic_page = kmap(vmx->nested.virtual_apic_page);
4353 if (!vapic_page) {
4354 WARN_ON(1);
4355 return -ENOMEM;
4356 }
4357 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4358 kunmap(vmx->nested.virtual_apic_page);
4359
4360 status = vmcs_read16(GUEST_INTR_STATUS);
4361 if ((u8)max_irr > ((u8)status & 0xff)) {
4362 status &= ~0xff;
4363 status |= (u8)max_irr;
4364 vmcs_write16(GUEST_INTR_STATUS, status);
4365 }
4366 }
4367 return 0;
4368}
4369
21bc8dc5
RK		 4370static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4371{
4372#ifdef CONFIG_SMP
4373 if (vcpu->mode == IN_GUEST_MODE) {
4374 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4375 POSTED_INTR_VECTOR);
4376 return true;
4377 }
4378#endif
4379 return false;
4380}
4381
705699a1
WV		 4382static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4383 int vector)
4384{
4385 struct vcpu_vmx *vmx = to_vmx(vcpu);
4386
4387 if (is_guest_mode(vcpu) &&
4388 vector == vmx->nested.posted_intr_nv) {
4389 /* the PIR and ON have been set by L1. */
21bc8dc5 4390 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4391 /*
4392 * If a posted intr is not recognized by hardware,
4393 * we will accomplish it in the next vmentry.
4394 */
4395 vmx->nested.pi_pending = true;
4396 kvm_make_request(KVM_REQ_EVENT, vcpu);
4397 return 0;
4398 }
4399 return -1;
4400}
a20ed54d
YZ		 4401/*
4402 * Send interrupt to vcpu via posted interrupt way.
4403 * 1. If target vcpu is running(non-root mode), send posted interrupt
4404 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4405 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4406 * interrupt from PIR in next vmentry.
4407 */
4408static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4409{
4410 struct vcpu_vmx *vmx = to_vmx(vcpu);
4411 int r;
4412
705699a1
WV		 4413 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4414 if (!r)
4415 return;
4416
a20ed54d
YZ		 4417 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4418 return;
4419
4420 r = pi_test_and_set_on(&vmx->pi_desc);
4421 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4422 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4423 kvm_vcpu_kick(vcpu);
4424}
4425
4426static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4427{
4428 struct vcpu_vmx *vmx = to_vmx(vcpu);
4429
4430 if (!pi_test_and_clear_on(&vmx->pi_desc))
4431 return;
4432
4433 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4434}
4435
4436static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4437{
4438 return;
4439}
4440
a3a8ff8e
NHE		 4441/*
4442 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4443 * will not change in the lifetime of the guest.
4444 * Note that host-state that does change is set elsewhere. E.g., host-state
4445 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4446 */
a547c6db 4447static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4448{
4449 u32 low32, high32;
4450 unsigned long tmpl;
4451 struct desc_ptr dt;
d974baa3 4452 unsigned long cr4;
a3a8ff8e 4453
b1a74bf8 4454 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4455 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4456
d974baa3 4457 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4458 cr4 = cr4_read_shadow();
d974baa3
AL		 4459 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4460 vmx->host_state.vmcs_host_cr4 = cr4;
4461
a3a8ff8e 4462 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4463#ifdef CONFIG_X86_64
4464 /*
4465 * Load null selectors, so we can avoid reloading them in
4466 * __vmx_load_host_state(), in case userspace uses the null selectors
4467 * too (the expected case).
4468 */
4469 vmcs_write16(HOST_DS_SELECTOR, 0);
4470 vmcs_write16(HOST_ES_SELECTOR, 0);
4471#else
a3a8ff8e
NHE		 4472 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4473 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4474#endif
a3a8ff8e
NHE		 4475 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4476 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4477
4478 native_store_idt(&dt);
4479 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4480 vmx->host_idt_base = dt.address;
a3a8ff8e 4481
83287ea4 4482 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4483
4484 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4485 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4486 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4487 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4488
4489 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4490 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4491 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4492 }
4493}
4494
bf8179a0
NHE		 4495static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4496{
4497 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4498 if (enable_ept)
4499 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4500 if (is_guest_mode(&vmx->vcpu))
4501 vmx->vcpu.arch.cr4_guest_owned_bits &=
4502 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4503 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4504}
4505
01e439be
YZ		 4506static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4507{
4508 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4509
4510 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4511 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4512 return pin_based_exec_ctrl;
4513}
4514
bf8179a0
NHE		 4515static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4516{
4517 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4518
4519 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4520 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4521
bf8179a0
NHE		 4522 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4523 exec_control &= ~CPU_BASED_TPR_SHADOW;
4524#ifdef CONFIG_X86_64
4525 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4526 CPU_BASED_CR8_LOAD_EXITING;
4527#endif
4528 }
4529 if (!enable_ept)
4530 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4531 CPU_BASED_CR3_LOAD_EXITING |
4532 CPU_BASED_INVLPG_EXITING;
4533 return exec_control;
4534}
4535
4536static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4537{
4538 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4539 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4540 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4541 if (vmx->vpid == 0)
4542 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4543 if (!enable_ept) {
4544 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4545 enable_unrestricted_guest = 0;
ad756a16
MJ		 4546 /* Enable INVPCID for non-ept guests may cause performance regression. */
4547 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4548 }
4549 if (!enable_unrestricted_guest)
4550 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4551 if (!ple_gap)
4552 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4553 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4554 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4555 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4556 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4557 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4558 (handle_vmptrld).
4559 We can NOT enable shadow_vmcs here because we don't have yet
4560 a current VMCS12
4561 */
4562 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4563 /* PML is enabled/disabled in creating/destorying vcpu */
4564 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4565
bf8179a0
NHE		 4566 return exec_control;
4567}
4568
ce88decf
XG		 4569static void ept_set_mmio_spte_mask(void)
4570{
4571 /*
4572 * EPT Misconfigurations can be generated if the value of bits 2:0
4573 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4574 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4575 * spte.
4576 */
885032b9 4577 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4578}
4579
f53cd63c 4580#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4581/*
4582 * Sets up the vmcs for emulated real mode.
4583 */
8b9cf98c 4584static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4585{
2e4ce7f5 4586#ifdef CONFIG_X86_64
6aa8b732 4587 unsigned long a;
2e4ce7f5 4588#endif
6aa8b732 4589 int i;
6aa8b732 4590
6aa8b732 4591 /* I/O */
3e7c73e9
AK		 4592 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4593 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4594
4607c2d7
AG		 4595 if (enable_shadow_vmcs) {
4596 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4597 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4598 }
25c5f225 4599 if (cpu_has_vmx_msr_bitmap())
5897297b 4600 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4601
6aa8b732
AK		 4602 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4603
6aa8b732 4604 /* Control */
01e439be 4605 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4606
bf8179a0 4607 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4608
83ff3b9d 4609 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4610 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4611 vmx_secondary_exec_control(vmx));
83ff3b9d 4612 }
f78e0e2e 4613
01e439be 4614 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4615 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4616 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4617 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4618 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4619
4620 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4621
4622 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4623 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4624 }
4625
4b8d54f9
ZE		 4626 if (ple_gap) {
4627 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4628 vmx->ple_window = ple_window;
4629 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4630 }
4631
c3707958
XG		 4632 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4633 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4634 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4635
9581d442
AK		 4636 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4637 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4638 vmx_set_constant_host_state(vmx);
05b3e0c2 4639#ifdef CONFIG_X86_64
6aa8b732
AK		 4640 rdmsrl(MSR_FS_BASE, a);
4641 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4642 rdmsrl(MSR_GS_BASE, a);
4643 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4644#else
4645 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4646 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4647#endif
4648
2cc51560
ED		 4649 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4650 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4651 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4652 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4653 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4654
468d472f 4655 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4656 u32 msr_low, msr_high;
4657 u64 host_pat;
468d472f
SY		 4658 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4659 host_pat = msr_low | ((u64) msr_high << 32);
4660 /* Write the default value follow host pat */
4661 vmcs_write64(GUEST_IA32_PAT, host_pat);
4662 /* Keep arch.pat sync with GUEST_IA32_PAT */
4663 vmx->vcpu.arch.pat = host_pat;
4664 }
4665
03916db9 4666 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4667 u32 index = vmx_msr_index[i];
4668 u32 data_low, data_high;
a2fa3e9f 4669 int j = vmx->nmsrs;
6aa8b732
AK		 4670
4671 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4672 continue;
432bd6cb
AK		 4673 if (wrmsr_safe(index, data_low, data_high) < 0)
4674 continue;
26bb0981
AK		 4675 vmx->guest_msrs[j].index = i;
4676 vmx->guest_msrs[j].data = 0;
d5696725 4677 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4678 ++vmx->nmsrs;
6aa8b732 4679 }
6aa8b732 4680
2961e876
GN		 4681
4682 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4683
4684 /* 22.2.1, 20.8.1 */
2961e876 4685 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4686
e00c8cf2 4687 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4688 set_cr4_guest_host_mask(vmx);
e00c8cf2 4689
f53cd63c
WL		 4690 if (vmx_xsaves_supported())
4691 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4692
e00c8cf2
AK		 4693 return 0;
4694}
4695
57f252f2 4696static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4697{
4698 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4699 struct msr_data apic_base_msr;
e00c8cf2 4700
7ffd92c5 4701 vmx->rmode.vm86_active = 0;
e00c8cf2 4702
3b86cd99
JK		 4703 vmx->soft_vnmi_blocked = 0;
4704
ad312c7c 4705 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4706 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4707 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4708 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4709 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4710 apic_base_msr.host_initiated = true;
4711 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4712
2fb92db1
AK		 4713 vmx_segment_cache_clear(vmx);
4714
5706be0d 4715 seg_setup(VCPU_SREG_CS);
66450a21 4716 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4717 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4718
4719 seg_setup(VCPU_SREG_DS);
4720 seg_setup(VCPU_SREG_ES);
4721 seg_setup(VCPU_SREG_FS);
4722 seg_setup(VCPU_SREG_GS);
4723 seg_setup(VCPU_SREG_SS);
4724
4725 vmcs_write16(GUEST_TR_SELECTOR, 0);
4726 vmcs_writel(GUEST_TR_BASE, 0);
4727 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4728 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4729
4730 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4731 vmcs_writel(GUEST_LDTR_BASE, 0);
4732 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4733 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4734
4735 vmcs_write32(GUEST_SYSENTER_CS, 0);
4736 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4737 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4738
4739 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4740 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4741
e00c8cf2
AK		 4742 vmcs_writel(GUEST_GDTR_BASE, 0);
4743 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4744
4745 vmcs_writel(GUEST_IDTR_BASE, 0);
4746 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4747
443381a8 4748 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4749 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4750 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4751
e00c8cf2
AK		 4752 /* Special registers */
4753 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4754
4755 setup_msrs(vmx);
4756
6aa8b732
AK		 4757 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4758
f78e0e2e
SY		 4759 if (cpu_has_vmx_tpr_shadow()) {
4760 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4761 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4762 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4763 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4764 vmcs_write32(TPR_THRESHOLD, 0);
4765 }
4766
a73896cb 4767 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4768
01e439be
YZ		 4769 if (vmx_vm_has_apicv(vcpu->kvm))
4770 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4771
2384d2b3
SY		 4772 if (vmx->vpid != 0)
4773 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4774
fa40052c 4775 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4776 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4777 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4778 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4779 vmx_fpu_activate(&vmx->vcpu);
4780 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4781
b9d762fa 4782 vpid_sync_context(vmx);
6aa8b732
AK		 4783}
4784
b6f1250e
NHE		 4785/*
4786 * In nested virtualization, check if L1 asked to exit on external interrupts.
4787 * For most existing hypervisors, this will always return true.
4788 */
4789static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4790{
4791 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4792 PIN_BASED_EXT_INTR_MASK;
4793}
4794
77b0f5d6
BD		 4795/*
4796 * In nested virtualization, check if L1 has set
4797 * VM_EXIT_ACK_INTR_ON_EXIT
4798 */
4799static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4800{
4801 return get_vmcs12(vcpu)->vm_exit_controls &
4802 VM_EXIT_ACK_INTR_ON_EXIT;
4803}
4804
ea8ceb83
JK		 4805static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4806{
4807 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4808 PIN_BASED_NMI_EXITING;
4809}
4810
c9a7953f 4811static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4812{
4813 u32 cpu_based_vm_exec_control;
730dca42 4814
3b86cd99
JK		 4815 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4816 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4817 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4818}
4819
c9a7953f 4820static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4821{
4822 u32 cpu_based_vm_exec_control;
4823
c9a7953f
JK		 4824 if (!cpu_has_virtual_nmis() ||
4825 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4826 enable_irq_window(vcpu);
4827 return;
4828 }
3b86cd99
JK		 4829
4830 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4831 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4832 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4833}
4834
66fd3f7f 4835static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4836{
9c8cba37 4837 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4838 uint32_t intr;
4839 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4840
229456fc 4841 trace_kvm_inj_virq(irq);
2714d1d3 4842
fa89a817 4843 ++vcpu->stat.irq_injections;
7ffd92c5 4844 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4845 int inc_eip = 0;
4846 if (vcpu->arch.interrupt.soft)
4847 inc_eip = vcpu->arch.event_exit_inst_len;
4848 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4849 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4850 return;
4851 }
66fd3f7f
GN		 4852 intr = irq | INTR_INFO_VALID_MASK;
4853 if (vcpu->arch.interrupt.soft) {
4854 intr |= INTR_TYPE_SOFT_INTR;
4855 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4856 vmx->vcpu.arch.event_exit_inst_len);
4857 } else
4858 intr |= INTR_TYPE_EXT_INTR;
4859 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4860}
4861
f08864b4
SY		 4862static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4863{
66a5a347
JK		 4864 struct vcpu_vmx *vmx = to_vmx(vcpu);
4865
0b6ac343
NHE		 4866 if (is_guest_mode(vcpu))
4867 return;
4868
3b86cd99
JK		 4869 if (!cpu_has_virtual_nmis()) {
4870 /*
4871 * Tracking the NMI-blocked state in software is built upon
4872 * finding the next open IRQ window. This, in turn, depends on
4873 * well-behaving guests: They have to keep IRQs disabled at
4874 * least as long as the NMI handler runs. Otherwise we may
4875 * cause NMI nesting, maybe breaking the guest. But as this is
4876 * highly unlikely, we can live with the residual risk.
4877 */
4878 vmx->soft_vnmi_blocked = 1;
4879 vmx->vnmi_blocked_time = 0;
4880 }
4881
487b391d 4882 ++vcpu->stat.nmi_injections;
9d58b931 4883 vmx->nmi_known_unmasked = false;
7ffd92c5 4884 if (vmx->rmode.vm86_active) {
71f9833b 4885 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4886 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4887 return;
4888 }
f08864b4
SY		 4889 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4890 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4891}
4892
3cfc3092
JK		 4893static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4894{
4895 if (!cpu_has_virtual_nmis())
4896 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4897 if (to_vmx(vcpu)->nmi_known_unmasked)
4898 return false;
c332c83a 4899 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4900}
4901
4902static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4903{
4904 struct vcpu_vmx *vmx = to_vmx(vcpu);
4905
4906 if (!cpu_has_virtual_nmis()) {
4907 if (vmx->soft_vnmi_blocked != masked) {
4908 vmx->soft_vnmi_blocked = masked;
4909 vmx->vnmi_blocked_time = 0;
4910 }
4911 } else {
9d58b931 4912 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4913 if (masked)
4914 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4915 GUEST_INTR_STATE_NMI);
4916 else
4917 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4918 GUEST_INTR_STATE_NMI);
4919 }
4920}
4921
2505dc9f
JK		 4922static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4923{
b6b8a145
JK		 4924 if (to_vmx(vcpu)->nested.nested_run_pending)
4925 return 0;
ea8ceb83 4926
2505dc9f
JK		 4927 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4928 return 0;
4929
4930 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4931 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4932 | GUEST_INTR_STATE_NMI));
4933}
4934
78646121
GN		 4935static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4936{
b6b8a145
JK		 4937 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4938 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4939 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4940 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4941}
4942
cbc94022
IE		 4943static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4944{
4945 int ret;
4946 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4947 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4948 .guest_phys_addr = addr,
4949 .memory_size = PAGE_SIZE * 3,
4950 .flags = 0,
4951 };
4952
47ae31e2 4953 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4954 if (ret)
4955 return ret;
bfc6d222 4956 kvm->arch.tss_addr = addr;
1f755a82 4957 return init_rmode_tss(kvm);
cbc94022
IE		 4958}
4959
0ca1b4f4 4960static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4961{
77ab6db0 4962 switch (vec) {
77ab6db0 4963 case BP_VECTOR:
c573cd22
JK		 4964 /*
4965 * Update instruction length as we may reinject the exception
4966 * from user space while in guest debugging mode.
4967 */
4968 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4969 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4970 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4971 return false;
4972 /* fall through */
4973 case DB_VECTOR:
4974 if (vcpu->guest_debug &
4975 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4976 return false;
d0bfb940
JK		 4977 /* fall through */
4978 case DE_VECTOR:
77ab6db0
JK		 4979 case OF_VECTOR:
4980 case BR_VECTOR:
4981 case UD_VECTOR:
4982 case DF_VECTOR:
4983 case SS_VECTOR:
4984 case GP_VECTOR:
4985 case MF_VECTOR:
0ca1b4f4
GN		 4986 return true;
4987 break;
77ab6db0 4988 }
0ca1b4f4
GN		 4989 return false;
4990}
4991
4992static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4993 int vec, u32 err_code)
4994{
4995 /*
4996 * Instruction with address size override prefix opcode 0x67
4997 * Cause the #SS fault with 0 error code in VM86 mode.
4998 */
4999 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5000 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5001 if (vcpu->arch.halt_request) {
5002 vcpu->arch.halt_request = 0;
5003 return kvm_emulate_halt(vcpu);
5004 }
5005 return 1;
5006 }
5007 return 0;
5008 }
5009
5010 /*
5011 * Forward all other exceptions that are valid in real mode.
5012 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5013 * the required debugging infrastructure rework.
5014 */
5015 kvm_queue_exception(vcpu, vec);
5016 return 1;
6aa8b732
AK		 5017}
5018
a0861c02
AK		 5019/*
5020 * Trigger machine check on the host. We assume all the MSRs are already set up
5021 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5022 * We pass a fake environment to the machine check handler because we want
5023 * the guest to be always treated like user space, no matter what context
5024 * it used internally.
5025 */
5026static void kvm_machine_check(void)
5027{
5028#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5029 struct pt_regs regs = {
5030 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5031 .flags = X86_EFLAGS_IF,
5032 };
5033
5034 do_machine_check(&regs, 0);
5035#endif
5036}
5037
851ba692 5038static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5039{
5040 /* already handled by vcpu_run */
5041 return 1;
5042}
5043
851ba692 5044static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5045{
1155f76a 5046 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5047 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5048 u32 intr_info, ex_no, error_code;
42dbaa5a 5049 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5050 u32 vect_info;
5051 enum emulation_result er;
5052
1155f76a 5053 vect_info = vmx->idt_vectoring_info;
88786475 5054 intr_info = vmx->exit_intr_info;
6aa8b732 5055
a0861c02 5056 if (is_machine_check(intr_info))
851ba692 5057 return handle_machine_check(vcpu);
a0861c02 5058
e4a41889 5059 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5060 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5061
5062 if (is_no_device(intr_info)) {
5fd86fcf 5063 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5064 return 1;
5065 }
5066
7aa81cc0 5067 if (is_invalid_opcode(intr_info)) {
51d8b661 5068 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5069 if (er != EMULATE_DONE)
7ee5d940 5070 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5071 return 1;
5072 }
5073
6aa8b732 5074 error_code = 0;
2e11384c 5075 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5076 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5077
5078 /*
5079 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5080 * MMIO, it is better to report an internal error.
5081 * See the comments in vmx_handle_exit.
5082 */
5083 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5084 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5085 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5086 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5087 vcpu->run->internal.ndata = 2;
5088 vcpu->run->internal.data[0] = vect_info;
5089 vcpu->run->internal.data[1] = intr_info;
5090 return 0;
5091 }
5092
6aa8b732 5093 if (is_page_fault(intr_info)) {
1439442c 5094 /* EPT won't cause page fault directly */
cf3ace79 5095 BUG_ON(enable_ept);
6aa8b732 5096 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5097 trace_kvm_page_fault(cr2, error_code);
5098
3298b75c 5099 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5100 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5101 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5102 }
5103
d0bfb940 5104 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5105
5106 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5107 return handle_rmode_exception(vcpu, ex_no, error_code);
5108
42dbaa5a
JK		 5109 switch (ex_no) {
5110 case DB_VECTOR:
5111 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5112 if (!(vcpu->guest_debug &
5113 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5114 vcpu->arch.dr6 &= ~15;
6f43ed01 5115 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5116 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5117 skip_emulated_instruction(vcpu);
5118
42dbaa5a
JK		 5119 kvm_queue_exception(vcpu, DB_VECTOR);
5120 return 1;
5121 }
5122 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5123 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5124 /* fall through */
5125 case BP_VECTOR:
c573cd22
JK		 5126 /*
5127 * Update instruction length as we may reinject #BP from
5128 * user space while in guest debugging mode. Reading it for
5129 * #DB as well causes no harm, it is not used in that case.
5130 */
5131 vmx->vcpu.arch.event_exit_inst_len =
5132 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5133 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5134 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5135 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5136 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5137 break;
5138 default:
d0bfb940
JK		 5139 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5140 kvm_run->ex.exception = ex_no;
5141 kvm_run->ex.error_code = error_code;
42dbaa5a 5142 break;
6aa8b732 5143 }
6aa8b732
AK		 5144 return 0;
5145}
5146
851ba692 5147static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5148{
1165f5fe 5149 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5150 return 1;
5151}
5152
851ba692 5153static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5154{
851ba692 5155 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5156 return 0;
5157}
6aa8b732 5158
851ba692 5159static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5160{
bfdaab09 5161 unsigned long exit_qualification;
34c33d16 5162 int size, in, string;
039576c0 5163 unsigned port;
6aa8b732 5164
bfdaab09 5165 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5166 string = (exit_qualification & 16) != 0;
cf8f70bf 5167 in = (exit_qualification & 8) != 0;
e70669ab 5168
cf8f70bf 5169 ++vcpu->stat.io_exits;
e70669ab 5170
cf8f70bf 5171 if (string || in)
51d8b661 5172 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5173
cf8f70bf
GN		 5174 port = exit_qualification >> 16;
5175 size = (exit_qualification & 7) + 1;
e93f36bc 5176 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5177
5178 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5179}
5180
102d8325
IM		 5181static void
5182vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5183{
5184 /*
5185 * Patch in the VMCALL instruction:
5186 */
5187 hypercall[0] = 0x0f;
5188 hypercall[1] = 0x01;
5189 hypercall[2] = 0xc1;
102d8325
IM		 5190}
5191
b9c237bb 5192static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5193{
5194 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5195 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5196
b9c237bb 5197 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5198 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5199 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5200 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5201 return (val & always_on) == always_on;
5202}
5203
0fa06071 5204/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5205static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5206{
eeadf9e7 5207 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5208 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5209 unsigned long orig_val = val;
5210
eeadf9e7
NHE		 5211 /*
5212 * We get here when L2 changed cr0 in a way that did not change
5213 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5214 * but did change L0 shadowed bits. So we first calculate the
5215 * effective cr0 value that L1 would like to write into the
5216 * hardware. It consists of the L2-owned bits from the new
5217 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5218 */
1a0d74e6
JK		 5219 val = (val & ~vmcs12->cr0_guest_host_mask) |
5220 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5221
b9c237bb 5222 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5223 return 1;
1a0d74e6
JK		 5224
5225 if (kvm_set_cr0(vcpu, val))
5226 return 1;
5227 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5228 return 0;
1a0d74e6
JK		 5229 } else {
5230 if (to_vmx(vcpu)->nested.vmxon &&
5231 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5232 return 1;
eeadf9e7 5233 return kvm_set_cr0(vcpu, val);
1a0d74e6 5234 }
eeadf9e7
NHE		 5235}
5236
5237static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5238{
5239 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5241 unsigned long orig_val = val;
5242
5243 /* analogously to handle_set_cr0 */
5244 val = (val & ~vmcs12->cr4_guest_host_mask) |
5245 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5246 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5247 return 1;
1a0d74e6 5248 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5249 return 0;
5250 } else
5251 return kvm_set_cr4(vcpu, val);
5252}
5253
5254/* called to set cr0 as approriate for clts instruction exit. */
5255static void handle_clts(struct kvm_vcpu *vcpu)
5256{
5257 if (is_guest_mode(vcpu)) {
5258 /*
5259 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5260 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5261 * just pretend it's off (also in arch.cr0 for fpu_activate).
5262 */
5263 vmcs_writel(CR0_READ_SHADOW,
5264 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5265 vcpu->arch.cr0 &= ~X86_CR0_TS;
5266 } else
5267 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5268}
5269
851ba692 5270static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5271{
229456fc 5272 unsigned long exit_qualification, val;
6aa8b732
AK		 5273 int cr;
5274 int reg;
49a9b07e 5275 int err;
6aa8b732 5276
bfdaab09 5277 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5278 cr = exit_qualification & 15;
5279 reg = (exit_qualification >> 8) & 15;
5280 switch ((exit_qualification >> 4) & 3) {
5281 case 0: /* mov to cr */
1e32c079 5282 val = kvm_register_readl(vcpu, reg);
229456fc 5283 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5284 switch (cr) {
5285 case 0:
eeadf9e7 5286 err = handle_set_cr0(vcpu, val);
db8fcefa 5287 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5288 return 1;
5289 case 3:
2390218b 5290 err = kvm_set_cr3(vcpu, val);
db8fcefa 5291 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5292 return 1;
5293 case 4:
eeadf9e7 5294 err = handle_set_cr4(vcpu, val);
db8fcefa 5295 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5296 return 1;
0a5fff19
GN		 5297 case 8: {
5298 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5299 u8 cr8 = (u8)val;
eea1cff9 5300 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5301 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5302 if (irqchip_in_kernel(vcpu->kvm))
5303 return 1;
5304 if (cr8_prev <= cr8)
5305 return 1;
851ba692 5306 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5307 return 0;
5308 }
4b8073e4 5309 }
6aa8b732 5310 break;
25c4c276 5311 case 2: /* clts */
eeadf9e7 5312 handle_clts(vcpu);
4d4ec087 5313 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5314 skip_emulated_instruction(vcpu);
6b52d186 5315 vmx_fpu_activate(vcpu);
25c4c276 5316 return 1;
6aa8b732
AK		 5317 case 1: /*mov from cr*/
5318 switch (cr) {
5319 case 3:
9f8fe504
AK		 5320 val = kvm_read_cr3(vcpu);
5321 kvm_register_write(vcpu, reg, val);
5322 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5323 skip_emulated_instruction(vcpu);
5324 return 1;
5325 case 8:
229456fc
MT		 5326 val = kvm_get_cr8(vcpu);
5327 kvm_register_write(vcpu, reg, val);
5328 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5329 skip_emulated_instruction(vcpu);
5330 return 1;
5331 }
5332 break;
5333 case 3: /* lmsw */
a1f83a74 5334 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5335 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5336 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5337
5338 skip_emulated_instruction(vcpu);
5339 return 1;
5340 default:
5341 break;
5342 }
851ba692 5343 vcpu->run->exit_reason = 0;
a737f256 5344 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5345 (int)(exit_qualification >> 4) & 3, cr);
5346 return 0;
5347}
5348
851ba692 5349static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5350{
bfdaab09 5351 unsigned long exit_qualification;
16f8a6f9
NA		 5352 int dr, dr7, reg;
5353
5354 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5355 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5356
5357 /* First, if DR does not exist, trigger UD */
5358 if (!kvm_require_dr(vcpu, dr))
5359 return 1;
6aa8b732 5360
f2483415 5361 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5362 if (!kvm_require_cpl(vcpu, 0))
5363 return 1;
16f8a6f9
NA		 5364 dr7 = vmcs_readl(GUEST_DR7);
5365 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5366 /*
5367 * As the vm-exit takes precedence over the debug trap, we
5368 * need to emulate the latter, either for the host or the
5369 * guest debugging itself.
5370 */
5371 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5372 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5373 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5374 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5375 vcpu->run->debug.arch.exception = DB_VECTOR;
5376 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5377 return 0;
5378 } else {
7305eb5d 5379 vcpu->arch.dr6 &= ~15;
6f43ed01 5380 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5381 kvm_queue_exception(vcpu, DB_VECTOR);
5382 return 1;
5383 }
5384 }
5385
81908bf4
PB		 5386 if (vcpu->guest_debug == 0) {
5387 u32 cpu_based_vm_exec_control;
5388
5389 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5390 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5391 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5392
5393 /*
5394 * No more DR vmexits; force a reload of the debug registers
5395 * and reenter on this instruction. The next vmexit will
5396 * retrieve the full state of the debug registers.
5397 */
5398 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5399 return 1;
5400 }
5401
42dbaa5a
JK		 5402 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5403 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5404 unsigned long val;
4c4d563b
JK		 5405
5406 if (kvm_get_dr(vcpu, dr, &val))
5407 return 1;
5408 kvm_register_write(vcpu, reg, val);
020df079 5409 } else
5777392e 5410 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5411 return 1;
5412
6aa8b732
AK		 5413 skip_emulated_instruction(vcpu);
5414 return 1;
5415}
5416
73aaf249
JK		 5417static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5418{
5419 return vcpu->arch.dr6;
5420}
5421
5422static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5423{
5424}
5425
81908bf4
PB		 5426static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5427{
5428 u32 cpu_based_vm_exec_control;
5429
5430 get_debugreg(vcpu->arch.db[0], 0);
5431 get_debugreg(vcpu->arch.db[1], 1);
5432 get_debugreg(vcpu->arch.db[2], 2);
5433 get_debugreg(vcpu->arch.db[3], 3);
5434 get_debugreg(vcpu->arch.dr6, 6);
5435 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5436
5437 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5438
5439 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5440 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5441 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5442}
5443
020df079
GN		 5444static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5445{
5446 vmcs_writel(GUEST_DR7, val);
5447}
5448
851ba692 5449static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5450{
06465c5a
AK		 5451 kvm_emulate_cpuid(vcpu);
5452 return 1;
6aa8b732
AK		 5453}
5454
851ba692 5455static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5456{
ad312c7c 5457 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5458 u64 data;
5459
5460 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5461 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5462 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5463 return 1;
5464 }
5465
229456fc 5466 trace_kvm_msr_read(ecx, data);
2714d1d3 5467
6aa8b732 5468 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5469 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5470 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5471 skip_emulated_instruction(vcpu);
5472 return 1;
5473}
5474
851ba692 5475static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5476{
8fe8ab46 5477 struct msr_data msr;
ad312c7c
ZX		 5478 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5479 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5480 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5481
8fe8ab46
WA		 5482 msr.data = data;
5483 msr.index = ecx;
5484 msr.host_initiated = false;
854e8bb1 5485 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5486 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5487 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5488 return 1;
5489 }
5490
59200273 5491 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5492 skip_emulated_instruction(vcpu);
5493 return 1;
5494}
5495
851ba692 5496static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5497{
3842d135 5498 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5499 return 1;
5500}
5501
851ba692 5502static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5503{
85f455f7
ED		 5504 u32 cpu_based_vm_exec_control;
5505
5506 /* clear pending irq */
5507 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5508 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5509 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5510
3842d135
AK		 5511 kvm_make_request(KVM_REQ_EVENT, vcpu);
5512
a26bf12a 5513 ++vcpu->stat.irq_window_exits;
2714d1d3 5514
c1150d8c
DL		 5515 /*
5516 * If the user space waits to inject interrupts, exit as soon as
5517 * possible
5518 */
8061823a 5519 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5520 vcpu->run->request_interrupt_window &&
8061823a 5521 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5522 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5523 return 0;
5524 }
6aa8b732
AK		 5525 return 1;
5526}
5527
851ba692 5528static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5529{
5530 skip_emulated_instruction(vcpu);
d3bef15f 5531 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5532}
5533
851ba692 5534static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5535{
510043da 5536 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5537 kvm_emulate_hypercall(vcpu);
5538 return 1;
c21415e8
IM		 5539}
5540
ec25d5e6
GN		 5541static int handle_invd(struct kvm_vcpu *vcpu)
5542{
51d8b661 5543 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5544}
5545
851ba692 5546static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5547{
f9c617f6 5548 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5549
5550 kvm_mmu_invlpg(vcpu, exit_qualification);
5551 skip_emulated_instruction(vcpu);
5552 return 1;
5553}
5554
fee84b07
AK		 5555static int handle_rdpmc(struct kvm_vcpu *vcpu)
5556{
5557 int err;
5558
5559 err = kvm_rdpmc(vcpu);
5560 kvm_complete_insn_gp(vcpu, err);
5561
5562 return 1;
5563}
5564
851ba692 5565static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5566{
5567 skip_emulated_instruction(vcpu);
f5f48ee1 5568 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5569 return 1;
5570}
5571
2acf923e
DC		 5572static int handle_xsetbv(struct kvm_vcpu *vcpu)
5573{
5574 u64 new_bv = kvm_read_edx_eax(vcpu);
5575 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5576
5577 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5578 skip_emulated_instruction(vcpu);
5579 return 1;
5580}
5581
f53cd63c
WL		 5582static int handle_xsaves(struct kvm_vcpu *vcpu)
5583{
5584 skip_emulated_instruction(vcpu);
5585 WARN(1, "this should never happen\n");
5586 return 1;
5587}
5588
5589static int handle_xrstors(struct kvm_vcpu *vcpu)
5590{
5591 skip_emulated_instruction(vcpu);
5592 WARN(1, "this should never happen\n");
5593 return 1;
5594}
5595
851ba692 5596static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5597{
58fbbf26
KT		 5598 if (likely(fasteoi)) {
5599 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5600 int access_type, offset;
5601
5602 access_type = exit_qualification & APIC_ACCESS_TYPE;
5603 offset = exit_qualification & APIC_ACCESS_OFFSET;
5604 /*
5605 * Sane guest uses MOV to write EOI, with written value
5606 * not cared. So make a short-circuit here by avoiding
5607 * heavy instruction emulation.
5608 */
5609 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5610 (offset == APIC_EOI)) {
5611 kvm_lapic_set_eoi(vcpu);
5612 skip_emulated_instruction(vcpu);
5613 return 1;
5614 }
5615 }
51d8b661 5616 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5617}
5618
c7c9c56c
YZ		 5619static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5620{
5621 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5622 int vector = exit_qualification & 0xff;
5623
5624 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5625 kvm_apic_set_eoi_accelerated(vcpu, vector);
5626 return 1;
5627}
5628
83d4c286
YZ		 5629static int handle_apic_write(struct kvm_vcpu *vcpu)
5630{
5631 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5632 u32 offset = exit_qualification & 0xfff;
5633
5634 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5635 kvm_apic_write_nodecode(vcpu, offset);
5636 return 1;
5637}
5638
851ba692 5639static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5640{
60637aac 5641 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5642 unsigned long exit_qualification;
e269fb21
JK		 5643 bool has_error_code = false;
5644 u32 error_code = 0;
37817f29 5645 u16 tss_selector;
7f3d35fd 5646 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5647
5648 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5649 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5650 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5651
5652 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5653
5654 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5655 if (reason == TASK_SWITCH_GATE && idt_v) {
5656 switch (type) {
5657 case INTR_TYPE_NMI_INTR:
5658 vcpu->arch.nmi_injected = false;
654f06fc 5659 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5660 break;
5661 case INTR_TYPE_EXT_INTR:
66fd3f7f 5662 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5663 kvm_clear_interrupt_queue(vcpu);
5664 break;
5665 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5666 if (vmx->idt_vectoring_info &
5667 VECTORING_INFO_DELIVER_CODE_MASK) {
5668 has_error_code = true;
5669 error_code =
5670 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5671 }
5672 /* fall through */
64a7ec06
GN		 5673 case INTR_TYPE_SOFT_EXCEPTION:
5674 kvm_clear_exception_queue(vcpu);
5675 break;
5676 default:
5677 break;
5678 }
60637aac 5679 }
37817f29
IE		 5680 tss_selector = exit_qualification;
5681
64a7ec06
GN		 5682 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5683 type != INTR_TYPE_EXT_INTR &&
5684 type != INTR_TYPE_NMI_INTR))
5685 skip_emulated_instruction(vcpu);
5686
7f3d35fd
KW		 5687 if (kvm_task_switch(vcpu, tss_selector,
5688 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5689 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5690 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5691 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5692 vcpu->run->internal.ndata = 0;
42dbaa5a 5693 return 0;
acb54517 5694 }
42dbaa5a
JK		 5695
5696 /* clear all local breakpoint enable flags */
0e8a0996 5697 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5698
5699 /*
5700 * TODO: What about debug traps on tss switch?
5701 * Are we supposed to inject them and update dr6?
5702 */
5703
5704 return 1;
37817f29
IE		 5705}
5706
851ba692 5707static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5708{
f9c617f6 5709 unsigned long exit_qualification;
1439442c 5710 gpa_t gpa;
4f5982a5 5711 u32 error_code;
1439442c 5712 int gla_validity;
1439442c 5713
f9c617f6 5714 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5715
1439442c
SY		 5716 gla_validity = (exit_qualification >> 7) & 0x3;
5717 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5718 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5719 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5720 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5721 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5722 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5723 (long unsigned int)exit_qualification);
851ba692
AK		 5724 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5725 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5726 return 0;
1439442c
SY		 5727 }
5728
0be9c7a8
GN		 5729 /*
5730 * EPT violation happened while executing iret from NMI,
5731 * "blocked by NMI" bit has to be set before next VM entry.
5732 * There are errata that may cause this bit to not be set:
5733 * AAK134, BY25.
5734 */
bcd1c294
GN		 5735 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5736 cpu_has_virtual_nmis() &&
5737 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5738 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5739
1439442c 5740 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5741 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5742
5743 /* It is a write fault? */
81ed33e4 5744 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5745 /* It is a fetch fault? */
81ed33e4 5746 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5747 /* ept page table is present? */
81ed33e4 5748 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5749
25d92081
YZ		 5750 vcpu->arch.exit_qualification = exit_qualification;
5751
4f5982a5 5752 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5753}
5754
68f89400
MT		 5755static u64 ept_rsvd_mask(u64 spte, int level)
5756{
5757 int i;
5758 u64 mask = 0;
5759
5760 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5761 mask |= (1ULL << i);
5762
a32e8459 5763 if (level == 4)
68f89400
MT		 5764 /* bits 7:3 reserved */
5765 mask |= 0xf8;
a32e8459
WL		 5766 else if (spte & (1ULL << 7))
5767 /*
5768 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5769 * level == 1 if the hypervisor is using the ignored bit 7.
5770 */
5771 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5772 else if (level > 1)
5773 /* bits 6:3 reserved */
5774 mask |= 0x78;
68f89400
MT		 5775
5776 return mask;
5777}
5778
5779static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5780 int level)
5781{
5782 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5783
5784 /* 010b (write-only) */
5785 WARN_ON((spte & 0x7) == 0x2);
5786
5787 /* 110b (write/execute) */
5788 WARN_ON((spte & 0x7) == 0x6);
5789
5790 /* 100b (execute-only) and value not supported by logical processor */
5791 if (!cpu_has_vmx_ept_execute_only())
5792 WARN_ON((spte & 0x7) == 0x4);
5793
5794 /* not 000b */
5795 if ((spte & 0x7)) {
5796 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5797
5798 if (rsvd_bits != 0) {
5799 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5800 __func__, rsvd_bits);
5801 WARN_ON(1);
5802 }
5803
a32e8459
WL		 5804 /* bits 5:3 are _not_ reserved for large page or leaf page */
5805 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5806 u64 ept_mem_type = (spte & 0x38) >> 3;
5807
5808 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5809 ept_mem_type == 7) {
5810 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5811 __func__, ept_mem_type);
5812 WARN_ON(1);
5813 }
5814 }
5815 }
5816}
5817
851ba692 5818static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5819{
5820 u64 sptes[4];
ce88decf 5821 int nr_sptes, i, ret;
68f89400
MT		 5822 gpa_t gpa;
5823
5824 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5825 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5826 skip_emulated_instruction(vcpu);
5827 return 1;
5828 }
68f89400 5829
ce88decf 5830 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5831 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5832 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5833 EMULATE_DONE;
f8f55942
XG		 5834
5835 if (unlikely(ret == RET_MMIO_PF_INVALID))
5836 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5837
b37fbea6 5838 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5839 return 1;
5840
5841 /* It is the real ept misconfig */
68f89400
MT		 5842 printk(KERN_ERR "EPT: Misconfiguration.\n");
5843 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5844
5845 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5846
5847 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5848 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5849
851ba692
AK		 5850 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5851 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5852
5853 return 0;
5854}
5855
851ba692 5856static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5857{
5858 u32 cpu_based_vm_exec_control;
5859
5860 /* clear pending NMI */
5861 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5862 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5864 ++vcpu->stat.nmi_window_exits;
3842d135 5865 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5866
5867 return 1;
5868}
5869
80ced186 5870static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5871{
8b3079a5
AK		 5872 struct vcpu_vmx *vmx = to_vmx(vcpu);
5873 enum emulation_result err = EMULATE_DONE;
80ced186 5874 int ret = 1;
49e9d557
AK		 5875 u32 cpu_exec_ctrl;
5876 bool intr_window_requested;
b8405c18 5877 unsigned count = 130;
49e9d557
AK		 5878
5879 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5880 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5881
98eb2f8b 5882 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5883 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5884 return handle_interrupt_window(&vmx->vcpu);
5885
de87dcdd
AK		 5886 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5887 return 1;
5888
991eebf9 5889 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5890
ac0a48c3 5891 if (err == EMULATE_USER_EXIT) {
94452b9e 5892 ++vcpu->stat.mmio_exits;
80ced186
MG		 5893 ret = 0;
5894 goto out;
5895 }
1d5a4d9b 5896
de5f70e0
AK		 5897 if (err != EMULATE_DONE) {
5898 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5899 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5900 vcpu->run->internal.ndata = 0;
6d77dbfc 5901 return 0;
de5f70e0 5902 }
ea953ef0 5903
8d76c49e
GN		 5904 if (vcpu->arch.halt_request) {
5905 vcpu->arch.halt_request = 0;
5906 ret = kvm_emulate_halt(vcpu);
5907 goto out;
5908 }
5909
ea953ef0 5910 if (signal_pending(current))
80ced186 5911 goto out;
ea953ef0
MG		 5912 if (need_resched())
5913 schedule();
5914 }
5915
80ced186
MG		 5916out:
5917 return ret;
ea953ef0
MG		 5918}
5919
b4a2d31d
RK		 5920static int __grow_ple_window(int val)
5921{
5922 if (ple_window_grow < 1)
5923 return ple_window;
5924
5925 val = min(val, ple_window_actual_max);
5926
5927 if (ple_window_grow < ple_window)
5928 val *= ple_window_grow;
5929 else
5930 val += ple_window_grow;
5931
5932 return val;
5933}
5934
5935static int __shrink_ple_window(int val, int modifier, int minimum)
5936{
5937 if (modifier < 1)
5938 return ple_window;
5939
5940 if (modifier < ple_window)
5941 val /= modifier;
5942 else
5943 val -= modifier;
5944
5945 return max(val, minimum);
5946}
5947
5948static void grow_ple_window(struct kvm_vcpu *vcpu)
5949{
5950 struct vcpu_vmx *vmx = to_vmx(vcpu);
5951 int old = vmx->ple_window;
5952
5953 vmx->ple_window = __grow_ple_window(old);
5954
5955 if (vmx->ple_window != old)
5956 vmx->ple_window_dirty = true;
7b46268d
RK		 5957
5958 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5959}
5960
5961static void shrink_ple_window(struct kvm_vcpu *vcpu)
5962{
5963 struct vcpu_vmx *vmx = to_vmx(vcpu);
5964 int old = vmx->ple_window;
5965
5966 vmx->ple_window = __shrink_ple_window(old,
5967 ple_window_shrink, ple_window);
5968
5969 if (vmx->ple_window != old)
5970 vmx->ple_window_dirty = true;
7b46268d
RK		 5971
5972 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5973}
5974
5975/*
5976 * ple_window_actual_max is computed to be one grow_ple_window() below
5977 * ple_window_max. (See __grow_ple_window for the reason.)
5978 * This prevents overflows, because ple_window_max is int.
5979 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5980 * this process.
5981 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5982 */
5983static void update_ple_window_actual_max(void)
5984{
5985 ple_window_actual_max =
5986 __shrink_ple_window(max(ple_window_max, ple_window),
5987 ple_window_grow, INT_MIN);
5988}
5989
f2c7648d
TC		 5990static __init int hardware_setup(void)
5991{
34a1cd60
TC		 5992 int r = -ENOMEM, i, msr;
5993
5994 rdmsrl_safe(MSR_EFER, &host_efer);
5995
5996 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5997 kvm_define_shared_msr(i, vmx_msr_index[i]);
5998
5999 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6000 if (!vmx_io_bitmap_a)
6001 return r;
6002
6003 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6004 if (!vmx_io_bitmap_b)
6005 goto out;
6006
6007 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6008 if (!vmx_msr_bitmap_legacy)
6009 goto out1;
6010
6011 vmx_msr_bitmap_legacy_x2apic =
6012 (unsigned long *)__get_free_page(GFP_KERNEL);
6013 if (!vmx_msr_bitmap_legacy_x2apic)
6014 goto out2;
6015
6016 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6017 if (!vmx_msr_bitmap_longmode)
6018 goto out3;
6019
6020 vmx_msr_bitmap_longmode_x2apic =
6021 (unsigned long *)__get_free_page(GFP_KERNEL);
6022 if (!vmx_msr_bitmap_longmode_x2apic)
6023 goto out4;
3af18d9c
WV		 6024
6025 if (nested) {
6026 vmx_msr_bitmap_nested =
6027 (unsigned long *)__get_free_page(GFP_KERNEL);
6028 if (!vmx_msr_bitmap_nested)
6029 goto out5;
6030 }
6031
34a1cd60
TC		 6032 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6033 if (!vmx_vmread_bitmap)
3af18d9c 6034 goto out6;
34a1cd60
TC		 6035
6036 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6037 if (!vmx_vmwrite_bitmap)
3af18d9c 6038 goto out7;
34a1cd60
TC		 6039
6040 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6041 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6042
6043 /*
6044 * Allow direct access to the PC debug port (it is often used for I/O
6045 * delays, but the vmexits simply slow things down).
6046 */
6047 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6048 clear_bit(0x80, vmx_io_bitmap_a);
6049
6050 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6051
6052 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6053 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6054 if (nested)
6055 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6056
34a1cd60
TC		 6057 if (setup_vmcs_config(&vmcs_config) < 0) {
6058 r = -EIO;
3af18d9c 6059 goto out8;
baa03522 6060 }
f2c7648d
TC		 6061
6062 if (boot_cpu_has(X86_FEATURE_NX))
6063 kvm_enable_efer_bits(EFER_NX);
6064
6065 if (!cpu_has_vmx_vpid())
6066 enable_vpid = 0;
6067 if (!cpu_has_vmx_shadow_vmcs())
6068 enable_shadow_vmcs = 0;
6069 if (enable_shadow_vmcs)
6070 init_vmcs_shadow_fields();
6071
6072 if (!cpu_has_vmx_ept() ||
6073 !cpu_has_vmx_ept_4levels()) {
6074 enable_ept = 0;
6075 enable_unrestricted_guest = 0;
6076 enable_ept_ad_bits = 0;
6077 }
6078
6079 if (!cpu_has_vmx_ept_ad_bits())
6080 enable_ept_ad_bits = 0;
6081
6082 if (!cpu_has_vmx_unrestricted_guest())
6083 enable_unrestricted_guest = 0;
6084
ad15a296 6085 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6086 flexpriority_enabled = 0;
6087
ad15a296
PB		 6088 /*
6089 * set_apic_access_page_addr() is used to reload apic access
6090 * page upon invalidation. No need to do anything if not
6091 * using the APIC_ACCESS_ADDR VMCS field.
6092 */
6093 if (!flexpriority_enabled)
f2c7648d 6094 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6095
6096 if (!cpu_has_vmx_tpr_shadow())
6097 kvm_x86_ops->update_cr8_intercept = NULL;
6098
6099 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6100 kvm_disable_largepages();
6101
6102 if (!cpu_has_vmx_ple())
6103 ple_gap = 0;
6104
6105 if (!cpu_has_vmx_apicv())
6106 enable_apicv = 0;
6107
6108 if (enable_apicv)
6109 kvm_x86_ops->update_cr8_intercept = NULL;
6110 else {
6111 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6112 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6113 kvm_x86_ops->deliver_posted_interrupt = NULL;
6114 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6115 }
6116
baa03522
TC		 6117 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6118 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6119 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6120 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6121 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6122 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6123 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6124
6125 memcpy(vmx_msr_bitmap_legacy_x2apic,
6126 vmx_msr_bitmap_legacy, PAGE_SIZE);
6127 memcpy(vmx_msr_bitmap_longmode_x2apic,
6128 vmx_msr_bitmap_longmode, PAGE_SIZE);
6129
6130 if (enable_apicv) {
6131 for (msr = 0x800; msr <= 0x8ff; msr++)
6132 vmx_disable_intercept_msr_read_x2apic(msr);
6133
6134 /* According SDM, in x2apic mode, the whole id reg is used.
6135 * But in KVM, it only use the highest eight bits. Need to
6136 * intercept it */
6137 vmx_enable_intercept_msr_read_x2apic(0x802);
6138 /* TMCCT */
6139 vmx_enable_intercept_msr_read_x2apic(0x839);
6140 /* TPR */
6141 vmx_disable_intercept_msr_write_x2apic(0x808);
6142 /* EOI */
6143 vmx_disable_intercept_msr_write_x2apic(0x80b);
6144 /* SELF-IPI */
6145 vmx_disable_intercept_msr_write_x2apic(0x83f);
6146 }
6147
6148 if (enable_ept) {
6149 kvm_mmu_set_mask_ptes(0ull,
6150 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6151 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6152 0ull, VMX_EPT_EXECUTABLE_MASK);
6153 ept_set_mmio_spte_mask();
6154 kvm_enable_tdp();
6155 } else
6156 kvm_disable_tdp();
6157
6158 update_ple_window_actual_max();
6159
843e4330
KH		 6160 /*
6161 * Only enable PML when hardware supports PML feature, and both EPT
6162 * and EPT A/D bit features are enabled -- PML depends on them to work.
6163 */
6164 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6165 enable_pml = 0;
6166
6167 if (!enable_pml) {
6168 kvm_x86_ops->slot_enable_log_dirty = NULL;
6169 kvm_x86_ops->slot_disable_log_dirty = NULL;
6170 kvm_x86_ops->flush_log_dirty = NULL;
6171 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6172 }
6173
f2c7648d 6174 return alloc_kvm_area();
34a1cd60 6175
3af18d9c 6176out8:
34a1cd60 6177 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6178out7:
34a1cd60 6179 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6180out6:
6181 if (nested)
6182 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6183out5:
6184 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6185out4:
6186 free_page((unsigned long)vmx_msr_bitmap_longmode);
6187out3:
6188 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6189out2:
6190 free_page((unsigned long)vmx_msr_bitmap_legacy);
6191out1:
6192 free_page((unsigned long)vmx_io_bitmap_b);
6193out:
6194 free_page((unsigned long)vmx_io_bitmap_a);
6195
6196 return r;
f2c7648d
TC		 6197}
6198
6199static __exit void hardware_unsetup(void)
6200{
34a1cd60
TC		 6201 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6202 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6203 free_page((unsigned long)vmx_msr_bitmap_legacy);
6204 free_page((unsigned long)vmx_msr_bitmap_longmode);
6205 free_page((unsigned long)vmx_io_bitmap_b);
6206 free_page((unsigned long)vmx_io_bitmap_a);
6207 free_page((unsigned long)vmx_vmwrite_bitmap);
6208 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6209 if (nested)
6210 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6211
f2c7648d
TC		 6212 free_kvm_area();
6213}
6214
4b8d54f9
ZE		 6215/*
6216 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6217 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6218 */
9fb41ba8 6219static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6220{
b4a2d31d
RK		 6221 if (ple_gap)
6222 grow_ple_window(vcpu);
6223
4b8d54f9
ZE		 6224 skip_emulated_instruction(vcpu);
6225 kvm_vcpu_on_spin(vcpu);
6226
6227 return 1;
6228}
6229
87c00572 6230static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6231{
87c00572 6232 skip_emulated_instruction(vcpu);
59708670
SY		 6233 return 1;
6234}
6235
87c00572
GS		 6236static int handle_mwait(struct kvm_vcpu *vcpu)
6237{
6238 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6239 return handle_nop(vcpu);
6240}
6241
6242static int handle_monitor(struct kvm_vcpu *vcpu)
6243{
6244 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6245 return handle_nop(vcpu);
6246}
6247
ff2f6fe9
NHE		 6248/*
6249 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6250 * We could reuse a single VMCS for all the L2 guests, but we also want the
6251 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6252 * allows keeping them loaded on the processor, and in the future will allow
6253 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6254 * every entry if they never change.
6255 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6256 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6257 *
6258 * The following functions allocate and free a vmcs02 in this pool.
6259 */
6260
6261/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6262static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6263{
6264 struct vmcs02_list *item;
6265 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6266 if (item->vmptr == vmx->nested.current_vmptr) {
6267 list_move(&item->list, &vmx->nested.vmcs02_pool);
6268 return &item->vmcs02;
6269 }
6270
6271 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6272 /* Recycle the least recently used VMCS. */
6273 item = list_entry(vmx->nested.vmcs02_pool.prev,
6274 struct vmcs02_list, list);
6275 item->vmptr = vmx->nested.current_vmptr;
6276 list_move(&item->list, &vmx->nested.vmcs02_pool);
6277 return &item->vmcs02;
6278 }
6279
6280 /* Create a new VMCS */
0fa24ce3 6281 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6282 if (!item)
6283 return NULL;
6284 item->vmcs02.vmcs = alloc_vmcs();
6285 if (!item->vmcs02.vmcs) {
6286 kfree(item);
6287 return NULL;
6288 }
6289 loaded_vmcs_init(&item->vmcs02);
6290 item->vmptr = vmx->nested.current_vmptr;
6291 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6292 vmx->nested.vmcs02_num++;
6293 return &item->vmcs02;
6294}
6295
6296/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6297static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6298{
6299 struct vmcs02_list *item;
6300 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6301 if (item->vmptr == vmptr) {
6302 free_loaded_vmcs(&item->vmcs02);
6303 list_del(&item->list);
6304 kfree(item);
6305 vmx->nested.vmcs02_num--;
6306 return;
6307 }
6308}
6309
6310/*
6311 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6312 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6313 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6314 */
6315static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6316{
6317 struct vmcs02_list *item, *n;
4fa7734c
PB		 6318
6319 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6320 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6321 /*
6322 * Something will leak if the above WARN triggers. Better than
6323 * a use-after-free.
6324 */
6325 if (vmx->loaded_vmcs == &item->vmcs02)
6326 continue;
6327
6328 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6329 list_del(&item->list);
6330 kfree(item);
4fa7734c 6331 vmx->nested.vmcs02_num--;
ff2f6fe9 6332 }
ff2f6fe9
NHE		 6333}
6334
0658fbaa
ACL		 6335/*
6336 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6337 * set the success or error code of an emulated VMX instruction, as specified
6338 * by Vol 2B, VMX Instruction Reference, "Conventions".
6339 */
6340static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6341{
6342 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6343 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6344 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6345}
6346
6347static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6348{
6349 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6350 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6351 X86_EFLAGS_SF | X86_EFLAGS_OF))
6352 | X86_EFLAGS_CF);
6353}
6354
145c28dd 6355static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6356 u32 vm_instruction_error)
6357{
6358 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6359 /*
6360 * failValid writes the error number to the current VMCS, which
6361 * can't be done there isn't a current VMCS.
6362 */
6363 nested_vmx_failInvalid(vcpu);
6364 return;
6365 }
6366 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6367 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6368 X86_EFLAGS_SF | X86_EFLAGS_OF))
6369 | X86_EFLAGS_ZF);
6370 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6371 /*
6372 * We don't need to force a shadow sync because
6373 * VM_INSTRUCTION_ERROR is not shadowed
6374 */
6375}
145c28dd 6376
ff651cb6
WV		 6377static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6378{
6379 /* TODO: not to reset guest simply here. */
6380 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6381 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6382}
6383
f4124500
JK		 6384static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6385{
6386 struct vcpu_vmx *vmx =
6387 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6388
6389 vmx->nested.preemption_timer_expired = true;
6390 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6391 kvm_vcpu_kick(&vmx->vcpu);
6392
6393 return HRTIMER_NORESTART;
6394}
6395
19677e32
BD		 6396/*
6397 * Decode the memory-address operand of a vmx instruction, as recorded on an
6398 * exit caused by such an instruction (run by a guest hypervisor).
6399 * On success, returns 0. When the operand is invalid, returns 1 and throws
6400 * #UD or #GP.
6401 */
6402static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6403 unsigned long exit_qualification,
6404 u32 vmx_instruction_info, gva_t *ret)
6405{
6406 /*
6407 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6408 * Execution", on an exit, vmx_instruction_info holds most of the
6409 * addressing components of the operand. Only the displacement part
6410 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6411 * For how an actual address is calculated from all these components,
6412 * refer to Vol. 1, "Operand Addressing".
6413 */
6414 int scaling = vmx_instruction_info & 3;
6415 int addr_size = (vmx_instruction_info >> 7) & 7;
6416 bool is_reg = vmx_instruction_info & (1u << 10);
6417 int seg_reg = (vmx_instruction_info >> 15) & 7;
6418 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6419 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6420 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6421 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6422
6423 if (is_reg) {
6424 kvm_queue_exception(vcpu, UD_VECTOR);
6425 return 1;
6426 }
6427
6428 /* Addr = segment_base + offset */
6429 /* offset = base + [index * scale] + displacement */
6430 *ret = vmx_get_segment_base(vcpu, seg_reg);
6431 if (base_is_valid)
6432 *ret += kvm_register_read(vcpu, base_reg);
6433 if (index_is_valid)
6434 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6435 *ret += exit_qualification; /* holds the displacement */
6436
6437 if (addr_size == 1) /* 32 bit */
6438 *ret &= 0xffffffff;
6439
6440 /*
6441 * TODO: throw #GP (and return 1) in various cases that the VM*
6442 * instructions require it - e.g., offset beyond segment limit,
6443 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6444 * address, and so on. Currently these are not checked.
6445 */
6446 return 0;
6447}
6448
3573e22c
BD		 6449/*
6450 * This function performs the various checks including
6451 * - if it's 4KB aligned
6452 * - No bits beyond the physical address width are set
6453 * - Returns 0 on success or else 1
4291b588 6454 * (Intel SDM Section 30.3)
3573e22c 6455 */
4291b588
BD		 6456static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6457 gpa_t *vmpointer)
3573e22c
BD		 6458{
6459 gva_t gva;
6460 gpa_t vmptr;
6461 struct x86_exception e;
6462 struct page *page;
6463 struct vcpu_vmx *vmx = to_vmx(vcpu);
6464 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6465
6466 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6467 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6468 return 1;
6469
6470 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6471 sizeof(vmptr), &e)) {
6472 kvm_inject_page_fault(vcpu, &e);
6473 return 1;
6474 }
6475
6476 switch (exit_reason) {
6477 case EXIT_REASON_VMON:
6478 /*
6479 * SDM 3: 24.11.5
6480 * The first 4 bytes of VMXON region contain the supported
6481 * VMCS revision identifier
6482 *
6483 * Note - IA32_VMX_BASIC[48] will never be 1
6484 * for the nested case;
6485 * which replaces physical address width with 32
6486 *
6487 */
bc39c4db 6488 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6489 nested_vmx_failInvalid(vcpu);
6490 skip_emulated_instruction(vcpu);
6491 return 1;
6492 }
6493
6494 page = nested_get_page(vcpu, vmptr);
6495 if (page == NULL ||
6496 *(u32 *)kmap(page) != VMCS12_REVISION) {
6497 nested_vmx_failInvalid(vcpu);
6498 kunmap(page);
6499 skip_emulated_instruction(vcpu);
6500 return 1;
6501 }
6502 kunmap(page);
6503 vmx->nested.vmxon_ptr = vmptr;
6504 break;
4291b588 6505 case EXIT_REASON_VMCLEAR:
bc39c4db 6506 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6507 nested_vmx_failValid(vcpu,
6508 VMXERR_VMCLEAR_INVALID_ADDRESS);
6509 skip_emulated_instruction(vcpu);
6510 return 1;
6511 }
6512
6513 if (vmptr == vmx->nested.vmxon_ptr) {
6514 nested_vmx_failValid(vcpu,
6515 VMXERR_VMCLEAR_VMXON_POINTER);
6516 skip_emulated_instruction(vcpu);
6517 return 1;
6518 }
6519 break;
6520 case EXIT_REASON_VMPTRLD:
bc39c4db 6521 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6522 nested_vmx_failValid(vcpu,
6523 VMXERR_VMPTRLD_INVALID_ADDRESS);
6524 skip_emulated_instruction(vcpu);
6525 return 1;
6526 }
3573e22c 6527
4291b588
BD		 6528 if (vmptr == vmx->nested.vmxon_ptr) {
6529 nested_vmx_failValid(vcpu,
6530 VMXERR_VMCLEAR_VMXON_POINTER);
6531 skip_emulated_instruction(vcpu);
6532 return 1;
6533 }
6534 break;
3573e22c
BD		 6535 default:
6536 return 1; /* shouldn't happen */
6537 }
6538
4291b588
BD		 6539 if (vmpointer)
6540 *vmpointer = vmptr;
3573e22c
BD		 6541 return 0;
6542}
6543
ec378aee
NHE		 6544/*
6545 * Emulate the VMXON instruction.
6546 * Currently, we just remember that VMX is active, and do not save or even
6547 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6548 * do not currently need to store anything in that guest-allocated memory
6549 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6550 * argument is different from the VMXON pointer (which the spec says they do).
6551 */
6552static int handle_vmon(struct kvm_vcpu *vcpu)
6553{
6554 struct kvm_segment cs;
6555 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6556 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6557 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6558 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6559
6560 /* The Intel VMX Instruction Reference lists a bunch of bits that
6561 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6562 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6563 * Otherwise, we should fail with #UD. We test these now:
6564 */
6565 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6566 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6567 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6568 kvm_queue_exception(vcpu, UD_VECTOR);
6569 return 1;
6570 }
6571
6572 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6573 if (is_long_mode(vcpu) && !cs.l) {
6574 kvm_queue_exception(vcpu, UD_VECTOR);
6575 return 1;
6576 }
6577
6578 if (vmx_get_cpl(vcpu)) {
6579 kvm_inject_gp(vcpu, 0);
6580 return 1;
6581 }
3573e22c 6582
4291b588 6583 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6584 return 1;
6585
145c28dd
AG		 6586 if (vmx->nested.vmxon) {
6587 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6588 skip_emulated_instruction(vcpu);
6589 return 1;
6590 }
b3897a49
NHE		 6591
6592 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6593 != VMXON_NEEDED_FEATURES) {
6594 kvm_inject_gp(vcpu, 0);
6595 return 1;
6596 }
6597
8de48833
AG		 6598 if (enable_shadow_vmcs) {
6599 shadow_vmcs = alloc_vmcs();
6600 if (!shadow_vmcs)
6601 return -ENOMEM;
6602 /* mark vmcs as shadow */
6603 shadow_vmcs->revision_id |= (1u << 31);
6604 /* init shadow vmcs */
6605 vmcs_clear(shadow_vmcs);
6606 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6607 }
ec378aee 6608
ff2f6fe9
NHE		 6609 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6610 vmx->nested.vmcs02_num = 0;
6611
f4124500
JK		 6612 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6613 HRTIMER_MODE_REL);
6614 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6615
ec378aee
NHE		 6616 vmx->nested.vmxon = true;
6617
6618 skip_emulated_instruction(vcpu);
a25eb114 6619 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6620 return 1;
6621}
6622
6623/*
6624 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6625 * for running VMX instructions (except VMXON, whose prerequisites are
6626 * slightly different). It also specifies what exception to inject otherwise.
6627 */
6628static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6629{
6630 struct kvm_segment cs;
6631 struct vcpu_vmx *vmx = to_vmx(vcpu);
6632
6633 if (!vmx->nested.vmxon) {
6634 kvm_queue_exception(vcpu, UD_VECTOR);
6635 return 0;
6636 }
6637
6638 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6639 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6640 (is_long_mode(vcpu) && !cs.l)) {
6641 kvm_queue_exception(vcpu, UD_VECTOR);
6642 return 0;
6643 }
6644
6645 if (vmx_get_cpl(vcpu)) {
6646 kvm_inject_gp(vcpu, 0);
6647 return 0;
6648 }
6649
6650 return 1;
6651}
6652
e7953d7f
AG		 6653static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6654{
8a1b9dd0 6655 u32 exec_control;
9a2a05b9
PB		 6656 if (vmx->nested.current_vmptr == -1ull)
6657 return;
6658
6659 /* current_vmptr and current_vmcs12 are always set/reset together */
6660 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6661 return;
6662
012f83cb 6663 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6664 /* copy to memory all shadowed fields in case
6665 they were modified */
6666 copy_shadow_to_vmcs12(vmx);
6667 vmx->nested.sync_shadow_vmcs = false;
6668 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6669 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6670 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6671 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6672 }
705699a1 6673 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6674 kunmap(vmx->nested.current_vmcs12_page);
6675 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6676 vmx->nested.current_vmptr = -1ull;
6677 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6678}
6679
ec378aee
NHE		 6680/*
6681 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6682 * just stops using VMX.
6683 */
6684static void free_nested(struct vcpu_vmx *vmx)
6685{
6686 if (!vmx->nested.vmxon)
6687 return;
9a2a05b9 6688
ec378aee 6689 vmx->nested.vmxon = false;
9a2a05b9 6690 nested_release_vmcs12(vmx);
e7953d7f
AG		 6691 if (enable_shadow_vmcs)
6692 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6693 /* Unpin physical memory we referred to in current vmcs02 */
6694 if (vmx->nested.apic_access_page) {
6695 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6696 vmx->nested.apic_access_page = NULL;
fe3ef05c 6697 }
a7c0b07d
WL		 6698 if (vmx->nested.virtual_apic_page) {
6699 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6700 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6701 }
705699a1
WV		 6702 if (vmx->nested.pi_desc_page) {
6703 kunmap(vmx->nested.pi_desc_page);
6704 nested_release_page(vmx->nested.pi_desc_page);
6705 vmx->nested.pi_desc_page = NULL;
6706 vmx->nested.pi_desc = NULL;
6707 }
ff2f6fe9
NHE		 6708
6709 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6710}
6711
6712/* Emulate the VMXOFF instruction */
6713static int handle_vmoff(struct kvm_vcpu *vcpu)
6714{
6715 if (!nested_vmx_check_permission(vcpu))
6716 return 1;
6717 free_nested(to_vmx(vcpu));
6718 skip_emulated_instruction(vcpu);
a25eb114 6719 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6720 return 1;
6721}
6722
27d6c865
NHE		 6723/* Emulate the VMCLEAR instruction */
6724static int handle_vmclear(struct kvm_vcpu *vcpu)
6725{
6726 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6727 gpa_t vmptr;
6728 struct vmcs12 *vmcs12;
6729 struct page *page;
27d6c865
NHE		 6730
6731 if (!nested_vmx_check_permission(vcpu))
6732 return 1;
6733
4291b588 6734 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6735 return 1;
27d6c865 6736
9a2a05b9 6737 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6738 nested_release_vmcs12(vmx);
27d6c865
NHE		 6739
6740 page = nested_get_page(vcpu, vmptr);
6741 if (page == NULL) {
6742 /*
6743 * For accurate processor emulation, VMCLEAR beyond available
6744 * physical memory should do nothing at all. However, it is
6745 * possible that a nested vmx bug, not a guest hypervisor bug,
6746 * resulted in this case, so let's shut down before doing any
6747 * more damage:
6748 */
6749 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6750 return 1;
6751 }
6752 vmcs12 = kmap(page);
6753 vmcs12->launch_state = 0;
6754 kunmap(page);
6755 nested_release_page(page);
6756
6757 nested_free_vmcs02(vmx, vmptr);
6758
6759 skip_emulated_instruction(vcpu);
6760 nested_vmx_succeed(vcpu);
6761 return 1;
6762}
6763
cd232ad0
NHE		 6764static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6765
6766/* Emulate the VMLAUNCH instruction */
6767static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6768{
6769 return nested_vmx_run(vcpu, true);
6770}
6771
6772/* Emulate the VMRESUME instruction */
6773static int handle_vmresume(struct kvm_vcpu *vcpu)
6774{
6775
6776 return nested_vmx_run(vcpu, false);
6777}
6778
49f705c5
NHE		 6779enum vmcs_field_type {
6780 VMCS_FIELD_TYPE_U16 = 0,
6781 VMCS_FIELD_TYPE_U64 = 1,
6782 VMCS_FIELD_TYPE_U32 = 2,
6783 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6784};
6785
6786static inline int vmcs_field_type(unsigned long field)
6787{
6788 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6789 return VMCS_FIELD_TYPE_U32;
6790 return (field >> 13) & 0x3 ;
6791}
6792
6793static inline int vmcs_field_readonly(unsigned long field)
6794{
6795 return (((field >> 10) & 0x3) == 1);
6796}
6797
6798/*
6799 * Read a vmcs12 field. Since these can have varying lengths and we return
6800 * one type, we chose the biggest type (u64) and zero-extend the return value
6801 * to that size. Note that the caller, handle_vmread, might need to use only
6802 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6803 * 64-bit fields are to be returned).
6804 */
a2ae9df7
PB		 6805static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6806 unsigned long field, u64 *ret)
49f705c5
NHE		 6807{
6808 short offset = vmcs_field_to_offset(field);
6809 char *p;
6810
6811 if (offset < 0)
a2ae9df7 6812 return offset;
49f705c5
NHE		 6813
6814 p = ((char *)(get_vmcs12(vcpu))) + offset;
6815
6816 switch (vmcs_field_type(field)) {
6817 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6818 *ret = *((natural_width *)p);
a2ae9df7 6819 return 0;
49f705c5
NHE		 6820 case VMCS_FIELD_TYPE_U16:
6821 *ret = *((u16 *)p);
a2ae9df7 6822 return 0;
49f705c5
NHE		 6823 case VMCS_FIELD_TYPE_U32:
6824 *ret = *((u32 *)p);
a2ae9df7 6825 return 0;
49f705c5
NHE		 6826 case VMCS_FIELD_TYPE_U64:
6827 *ret = *((u64 *)p);
a2ae9df7 6828 return 0;
49f705c5 6829 default:
a2ae9df7
PB		 6830 WARN_ON(1);
6831 return -ENOENT;
49f705c5
NHE		 6832 }
6833}
6834
20b97fea 6835
a2ae9df7
PB		 6836static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6837 unsigned long field, u64 field_value){
20b97fea
AG		 6838 short offset = vmcs_field_to_offset(field);
6839 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6840 if (offset < 0)
a2ae9df7 6841 return offset;
20b97fea
AG		 6842
6843 switch (vmcs_field_type(field)) {
6844 case VMCS_FIELD_TYPE_U16:
6845 *(u16 *)p = field_value;
a2ae9df7 6846 return 0;
20b97fea
AG		 6847 case VMCS_FIELD_TYPE_U32:
6848 *(u32 *)p = field_value;
a2ae9df7 6849 return 0;
20b97fea
AG		 6850 case VMCS_FIELD_TYPE_U64:
6851 *(u64 *)p = field_value;
a2ae9df7 6852 return 0;
20b97fea
AG		 6853 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6854 *(natural_width *)p = field_value;
a2ae9df7 6855 return 0;
20b97fea 6856 default:
a2ae9df7
PB		 6857 WARN_ON(1);
6858 return -ENOENT;
20b97fea
AG		 6859 }
6860
6861}
6862
16f5b903
AG		 6863static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6864{
6865 int i;
6866 unsigned long field;
6867 u64 field_value;
6868 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6869 const unsigned long *fields = shadow_read_write_fields;
6870 const int num_fields = max_shadow_read_write_fields;
16f5b903 6871
282da870
JK		 6872 preempt_disable();
6873
16f5b903
AG		 6874 vmcs_load(shadow_vmcs);
6875
6876 for (i = 0; i < num_fields; i++) {
6877 field = fields[i];
6878 switch (vmcs_field_type(field)) {
6879 case VMCS_FIELD_TYPE_U16:
6880 field_value = vmcs_read16(field);
6881 break;
6882 case VMCS_FIELD_TYPE_U32:
6883 field_value = vmcs_read32(field);
6884 break;
6885 case VMCS_FIELD_TYPE_U64:
6886 field_value = vmcs_read64(field);
6887 break;
6888 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6889 field_value = vmcs_readl(field);
6890 break;
a2ae9df7
PB		 6891 default:
6892 WARN_ON(1);
6893 continue;
16f5b903
AG		 6894 }
6895 vmcs12_write_any(&vmx->vcpu, field, field_value);
6896 }
6897
6898 vmcs_clear(shadow_vmcs);
6899 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6900
6901 preempt_enable();
16f5b903
AG		 6902}
6903
c3114420
AG		 6904static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6905{
c2bae893
MK		 6906 const unsigned long *fields[] = {
6907 shadow_read_write_fields,
6908 shadow_read_only_fields
c3114420 6909 };
c2bae893 6910 const int max_fields[] = {
c3114420
AG		 6911 max_shadow_read_write_fields,
6912 max_shadow_read_only_fields
6913 };
6914 int i, q;
6915 unsigned long field;
6916 u64 field_value = 0;
6917 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6918
6919 vmcs_load(shadow_vmcs);
6920
c2bae893 6921 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6922 for (i = 0; i < max_fields[q]; i++) {
6923 field = fields[q][i];
6924 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6925
6926 switch (vmcs_field_type(field)) {
6927 case VMCS_FIELD_TYPE_U16:
6928 vmcs_write16(field, (u16)field_value);
6929 break;
6930 case VMCS_FIELD_TYPE_U32:
6931 vmcs_write32(field, (u32)field_value);
6932 break;
6933 case VMCS_FIELD_TYPE_U64:
6934 vmcs_write64(field, (u64)field_value);
6935 break;
6936 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6937 vmcs_writel(field, (long)field_value);
6938 break;
a2ae9df7
PB		 6939 default:
6940 WARN_ON(1);
6941 break;
c3114420
AG		 6942 }
6943 }
6944 }
6945
6946 vmcs_clear(shadow_vmcs);
6947 vmcs_load(vmx->loaded_vmcs->vmcs);
6948}
6949
49f705c5
NHE		 6950/*
6951 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6952 * used before) all generate the same failure when it is missing.
6953 */
6954static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6955{
6956 struct vcpu_vmx *vmx = to_vmx(vcpu);
6957 if (vmx->nested.current_vmptr == -1ull) {
6958 nested_vmx_failInvalid(vcpu);
6959 skip_emulated_instruction(vcpu);
6960 return 0;
6961 }
6962 return 1;
6963}
6964
6965static int handle_vmread(struct kvm_vcpu *vcpu)
6966{
6967 unsigned long field;
6968 u64 field_value;
6969 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6970 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6971 gva_t gva = 0;
6972
6973 if (!nested_vmx_check_permission(vcpu) ||
6974 !nested_vmx_check_vmcs12(vcpu))
6975 return 1;
6976
6977 /* Decode instruction info and find the field to read */
27e6fb5d 6978 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6979 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6980 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6981 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6982 skip_emulated_instruction(vcpu);
6983 return 1;
6984 }
6985 /*
6986 * Now copy part of this value to register or memory, as requested.
6987 * Note that the number of bits actually copied is 32 or 64 depending
6988 * on the guest's mode (32 or 64 bit), not on the given field's length.
6989 */
6990 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6991 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6992 field_value);
6993 } else {
6994 if (get_vmx_mem_address(vcpu, exit_qualification,
6995 vmx_instruction_info, &gva))
6996 return 1;
6997 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6998 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6999 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7000 }
7001
7002 nested_vmx_succeed(vcpu);
7003 skip_emulated_instruction(vcpu);
7004 return 1;
7005}
7006
7007
7008static int handle_vmwrite(struct kvm_vcpu *vcpu)
7009{
7010 unsigned long field;
7011 gva_t gva;
7012 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7013 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7014 /* The value to write might be 32 or 64 bits, depending on L1's long
7015 * mode, and eventually we need to write that into a field of several
7016 * possible lengths. The code below first zero-extends the value to 64
7017 * bit (field_value), and then copies only the approriate number of
7018 * bits into the vmcs12 field.
7019 */
7020 u64 field_value = 0;
7021 struct x86_exception e;
7022
7023 if (!nested_vmx_check_permission(vcpu) ||
7024 !nested_vmx_check_vmcs12(vcpu))
7025 return 1;
7026
7027 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7028 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7029 (((vmx_instruction_info) >> 3) & 0xf));
7030 else {
7031 if (get_vmx_mem_address(vcpu, exit_qualification,
7032 vmx_instruction_info, &gva))
7033 return 1;
7034 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7035 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7036 kvm_inject_page_fault(vcpu, &e);
7037 return 1;
7038 }
7039 }
7040
7041
27e6fb5d 7042 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7043 if (vmcs_field_readonly(field)) {
7044 nested_vmx_failValid(vcpu,
7045 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7046 skip_emulated_instruction(vcpu);
7047 return 1;
7048 }
7049
a2ae9df7 7050 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7051 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7052 skip_emulated_instruction(vcpu);
7053 return 1;
7054 }
7055
7056 nested_vmx_succeed(vcpu);
7057 skip_emulated_instruction(vcpu);
7058 return 1;
7059}
7060
63846663
NHE		 7061/* Emulate the VMPTRLD instruction */
7062static int handle_vmptrld(struct kvm_vcpu *vcpu)
7063{
7064 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7065 gpa_t vmptr;
8a1b9dd0 7066 u32 exec_control;
63846663
NHE		 7067
7068 if (!nested_vmx_check_permission(vcpu))
7069 return 1;
7070
4291b588 7071 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7072 return 1;
63846663
NHE		 7073
7074 if (vmx->nested.current_vmptr != vmptr) {
7075 struct vmcs12 *new_vmcs12;
7076 struct page *page;
7077 page = nested_get_page(vcpu, vmptr);
7078 if (page == NULL) {
7079 nested_vmx_failInvalid(vcpu);
7080 skip_emulated_instruction(vcpu);
7081 return 1;
7082 }
7083 new_vmcs12 = kmap(page);
7084 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7085 kunmap(page);
7086 nested_release_page_clean(page);
7087 nested_vmx_failValid(vcpu,
7088 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7089 skip_emulated_instruction(vcpu);
7090 return 1;
7091 }
63846663 7092
9a2a05b9 7093 nested_release_vmcs12(vmx);
63846663
NHE		 7094 vmx->nested.current_vmptr = vmptr;
7095 vmx->nested.current_vmcs12 = new_vmcs12;
7096 vmx->nested.current_vmcs12_page = page;
012f83cb 7097 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7098 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7099 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7100 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7101 vmcs_write64(VMCS_LINK_POINTER,
7102 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7103 vmx->nested.sync_shadow_vmcs = true;
7104 }
63846663
NHE		 7105 }
7106
7107 nested_vmx_succeed(vcpu);
7108 skip_emulated_instruction(vcpu);
7109 return 1;
7110}
7111
6a4d7550
NHE		 7112/* Emulate the VMPTRST instruction */
7113static int handle_vmptrst(struct kvm_vcpu *vcpu)
7114{
7115 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7116 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7117 gva_t vmcs_gva;
7118 struct x86_exception e;
7119
7120 if (!nested_vmx_check_permission(vcpu))
7121 return 1;
7122
7123 if (get_vmx_mem_address(vcpu, exit_qualification,
7124 vmx_instruction_info, &vmcs_gva))
7125 return 1;
7126 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7127 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7128 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7129 sizeof(u64), &e)) {
7130 kvm_inject_page_fault(vcpu, &e);
7131 return 1;
7132 }
7133 nested_vmx_succeed(vcpu);
7134 skip_emulated_instruction(vcpu);
7135 return 1;
7136}
7137
bfd0a56b
NHE		 7138/* Emulate the INVEPT instruction */
7139static int handle_invept(struct kvm_vcpu *vcpu)
7140{
b9c237bb 7141 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7142 u32 vmx_instruction_info, types;
7143 unsigned long type;
7144 gva_t gva;
7145 struct x86_exception e;
7146 struct {
7147 u64 eptp, gpa;
7148 } operand;
bfd0a56b 7149
b9c237bb
WV		 7150 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7151 SECONDARY_EXEC_ENABLE_EPT) ||
7152 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7153 kvm_queue_exception(vcpu, UD_VECTOR);
7154 return 1;
7155 }
7156
7157 if (!nested_vmx_check_permission(vcpu))
7158 return 1;
7159
7160 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7161 kvm_queue_exception(vcpu, UD_VECTOR);
7162 return 1;
7163 }
7164
7165 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7166 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7167
b9c237bb 7168 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7169
7170 if (!(types & (1UL << type))) {
7171 nested_vmx_failValid(vcpu,
7172 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7173 return 1;
7174 }
7175
7176 /* According to the Intel VMX instruction reference, the memory
7177 * operand is read even if it isn't needed (e.g., for type==global)
7178 */
7179 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7180 vmx_instruction_info, &gva))
7181 return 1;
7182 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7183 sizeof(operand), &e)) {
7184 kvm_inject_page_fault(vcpu, &e);
7185 return 1;
7186 }
7187
7188 switch (type) {
bfd0a56b
NHE		 7189 case VMX_EPT_EXTENT_GLOBAL:
7190 kvm_mmu_sync_roots(vcpu);
77c3913b 7191 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7192 nested_vmx_succeed(vcpu);
7193 break;
7194 default:
4b855078 7195 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7196 BUG_ON(1);
7197 break;
7198 }
7199
7200 skip_emulated_instruction(vcpu);
7201 return 1;
7202}
7203
a642fc30
PM		 7204static int handle_invvpid(struct kvm_vcpu *vcpu)
7205{
7206 kvm_queue_exception(vcpu, UD_VECTOR);
7207 return 1;
7208}
7209
843e4330
KH		 7210static int handle_pml_full(struct kvm_vcpu *vcpu)
7211{
7212 unsigned long exit_qualification;
7213
7214 trace_kvm_pml_full(vcpu->vcpu_id);
7215
7216 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7217
7218 /*
7219 * PML buffer FULL happened while executing iret from NMI,
7220 * "blocked by NMI" bit has to be set before next VM entry.
7221 */
7222 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7223 cpu_has_virtual_nmis() &&
7224 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7225 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7226 GUEST_INTR_STATE_NMI);
7227
7228 /*
7229 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7230 * here.., and there's no userspace involvement needed for PML.
7231 */
7232 return 1;
7233}
7234
6aa8b732
AK		 7235/*
7236 * The exit handlers return 1 if the exit was handled fully and guest execution
7237 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7238 * to be done to userspace and return 0.
7239 */
772e0318 7240static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7241 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7242 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7243 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7244 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7245 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7246 [EXIT_REASON_CR_ACCESS] = handle_cr,
7247 [EXIT_REASON_DR_ACCESS] = handle_dr,
7248 [EXIT_REASON_CPUID] = handle_cpuid,
7249 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7250 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7251 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7252 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7253 [EXIT_REASON_INVD] = handle_invd,
a7052897 7254 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7255 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7256 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7257 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7258 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7259 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7260 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7261 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7262 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7263 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7264 [EXIT_REASON_VMOFF] = handle_vmoff,
7265 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7266 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7267 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7268 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7269 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7270 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7271 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7272 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7273 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7274 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7275 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7276 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7277 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7278 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7279 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7280 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7281 [EXIT_REASON_XSAVES] = handle_xsaves,
7282 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7283 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7284};
7285
7286static const int kvm_vmx_max_exit_handlers =
50a3485c 7287 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7288
908a7bdd
JK		 7289static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7290 struct vmcs12 *vmcs12)
7291{
7292 unsigned long exit_qualification;
7293 gpa_t bitmap, last_bitmap;
7294 unsigned int port;
7295 int size;
7296 u8 b;
7297
908a7bdd 7298 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7299 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7300
7301 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7302
7303 port = exit_qualification >> 16;
7304 size = (exit_qualification & 7) + 1;
7305
7306 last_bitmap = (gpa_t)-1;
7307 b = -1;
7308
7309 while (size > 0) {
7310 if (port < 0x8000)
7311 bitmap = vmcs12->io_bitmap_a;
7312 else if (port < 0x10000)
7313 bitmap = vmcs12->io_bitmap_b;
7314 else
7315 return 1;
7316 bitmap += (port & 0x7fff) / 8;
7317
7318 if (last_bitmap != bitmap)
7319 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7320 return 1;
7321 if (b & (1 << (port & 7)))
7322 return 1;
7323
7324 port++;
7325 size--;
7326 last_bitmap = bitmap;
7327 }
7328
7329 return 0;
7330}
7331
644d711a
NHE		 7332/*
7333 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7334 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7335 * disinterest in the current event (read or write a specific MSR) by using an
7336 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7337 */
7338static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7339 struct vmcs12 *vmcs12, u32 exit_reason)
7340{
7341 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7342 gpa_t bitmap;
7343
cbd29cb6 7344 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7345 return 1;
7346
7347 /*
7348 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7349 * for the four combinations of read/write and low/high MSR numbers.
7350 * First we need to figure out which of the four to use:
7351 */
7352 bitmap = vmcs12->msr_bitmap;
7353 if (exit_reason == EXIT_REASON_MSR_WRITE)
7354 bitmap += 2048;
7355 if (msr_index >= 0xc0000000) {
7356 msr_index -= 0xc0000000;
7357 bitmap += 1024;
7358 }
7359
7360 /* Then read the msr_index'th bit from this bitmap: */
7361 if (msr_index < 1024*8) {
7362 unsigned char b;
bd31a7f5
JK		 7363 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7364 return 1;
644d711a
NHE		 7365 return 1 & (b >> (msr_index & 7));
7366 } else
7367 return 1; /* let L1 handle the wrong parameter */
7368}
7369
7370/*
7371 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7372 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7373 * intercept (via guest_host_mask etc.) the current event.
7374 */
7375static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7376 struct vmcs12 *vmcs12)
7377{
7378 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7379 int cr = exit_qualification & 15;
7380 int reg = (exit_qualification >> 8) & 15;
1e32c079 7381 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7382
7383 switch ((exit_qualification >> 4) & 3) {
7384 case 0: /* mov to cr */
7385 switch (cr) {
7386 case 0:
7387 if (vmcs12->cr0_guest_host_mask &
7388 (val ^ vmcs12->cr0_read_shadow))
7389 return 1;
7390 break;
7391 case 3:
7392 if ((vmcs12->cr3_target_count >= 1 &&
7393 vmcs12->cr3_target_value0 == val) ||
7394 (vmcs12->cr3_target_count >= 2 &&
7395 vmcs12->cr3_target_value1 == val) ||
7396 (vmcs12->cr3_target_count >= 3 &&
7397 vmcs12->cr3_target_value2 == val) ||
7398 (vmcs12->cr3_target_count >= 4 &&
7399 vmcs12->cr3_target_value3 == val))
7400 return 0;
7401 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7402 return 1;
7403 break;
7404 case 4:
7405 if (vmcs12->cr4_guest_host_mask &
7406 (vmcs12->cr4_read_shadow ^ val))
7407 return 1;
7408 break;
7409 case 8:
7410 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7411 return 1;
7412 break;
7413 }
7414 break;
7415 case 2: /* clts */
7416 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7417 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7418 return 1;
7419 break;
7420 case 1: /* mov from cr */
7421 switch (cr) {
7422 case 3:
7423 if (vmcs12->cpu_based_vm_exec_control &
7424 CPU_BASED_CR3_STORE_EXITING)
7425 return 1;
7426 break;
7427 case 8:
7428 if (vmcs12->cpu_based_vm_exec_control &
7429 CPU_BASED_CR8_STORE_EXITING)
7430 return 1;
7431 break;
7432 }
7433 break;
7434 case 3: /* lmsw */
7435 /*
7436 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7437 * cr0. Other attempted changes are ignored, with no exit.
7438 */
7439 if (vmcs12->cr0_guest_host_mask & 0xe &
7440 (val ^ vmcs12->cr0_read_shadow))
7441 return 1;
7442 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7443 !(vmcs12->cr0_read_shadow & 0x1) &&
7444 (val & 0x1))
7445 return 1;
7446 break;
7447 }
7448 return 0;
7449}
7450
7451/*
7452 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7453 * should handle it ourselves in L0 (and then continue L2). Only call this
7454 * when in is_guest_mode (L2).
7455 */
7456static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7457{
644d711a
NHE		 7458 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7459 struct vcpu_vmx *vmx = to_vmx(vcpu);
7460 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7461 u32 exit_reason = vmx->exit_reason;
644d711a 7462
542060ea
JK		 7463 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7464 vmcs_readl(EXIT_QUALIFICATION),
7465 vmx->idt_vectoring_info,
7466 intr_info,
7467 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7468 KVM_ISA_VMX);
7469
644d711a
NHE		 7470 if (vmx->nested.nested_run_pending)
7471 return 0;
7472
7473 if (unlikely(vmx->fail)) {
bd80158a
JK		 7474 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7475 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7476 return 1;
7477 }
7478
7479 switch (exit_reason) {
7480 case EXIT_REASON_EXCEPTION_NMI:
7481 if (!is_exception(intr_info))
7482 return 0;
7483 else if (is_page_fault(intr_info))
7484 return enable_ept;
e504c909 7485 else if (is_no_device(intr_info) &&
ccf9844e 7486 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7487 return 0;
644d711a
NHE		 7488 return vmcs12->exception_bitmap &
7489 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7490 case EXIT_REASON_EXTERNAL_INTERRUPT:
7491 return 0;
7492 case EXIT_REASON_TRIPLE_FAULT:
7493 return 1;
7494 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7495 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7496 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7497 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7498 case EXIT_REASON_TASK_SWITCH:
7499 return 1;
7500 case EXIT_REASON_CPUID:
bc613494
MT		 7501 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7502 return 0;
644d711a
NHE		 7503 return 1;
7504 case EXIT_REASON_HLT:
7505 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7506 case EXIT_REASON_INVD:
7507 return 1;
7508 case EXIT_REASON_INVLPG:
7509 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7510 case EXIT_REASON_RDPMC:
7511 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7512 case EXIT_REASON_RDTSC:
7513 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7514 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7515 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7516 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7517 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7518 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7519 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7520 /*
7521 * VMX instructions trap unconditionally. This allows L1 to
7522 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7523 */
7524 return 1;
7525 case EXIT_REASON_CR_ACCESS:
7526 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7527 case EXIT_REASON_DR_ACCESS:
7528 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7529 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7530 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7531 case EXIT_REASON_MSR_READ:
7532 case EXIT_REASON_MSR_WRITE:
7533 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7534 case EXIT_REASON_INVALID_STATE:
7535 return 1;
7536 case EXIT_REASON_MWAIT_INSTRUCTION:
7537 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7538 case EXIT_REASON_MONITOR_INSTRUCTION:
7539 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7540 case EXIT_REASON_PAUSE_INSTRUCTION:
7541 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7542 nested_cpu_has2(vmcs12,
7543 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7544 case EXIT_REASON_MCE_DURING_VMENTRY:
7545 return 0;
7546 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7547 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7548 case EXIT_REASON_APIC_ACCESS:
7549 return nested_cpu_has2(vmcs12,
7550 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7551 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7552 case EXIT_REASON_EOI_INDUCED:
7553 /* apic_write and eoi_induced should exit unconditionally. */
82f0dd4b 7554 return 1;
644d711a 7555 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7556 /*
7557 * L0 always deals with the EPT violation. If nested EPT is
7558 * used, and the nested mmu code discovers that the address is
7559 * missing in the guest EPT table (EPT12), the EPT violation
7560 * will be injected with nested_ept_inject_page_fault()
7561 */
7562 return 0;
644d711a 7563 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7564 /*
7565 * L2 never uses directly L1's EPT, but rather L0's own EPT
7566 * table (shadow on EPT) or a merged EPT table that L0 built
7567 * (EPT on EPT). So any problems with the structure of the
7568 * table is L0's fault.
7569 */
644d711a
NHE		 7570 return 0;
7571 case EXIT_REASON_WBINVD:
7572 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7573 case EXIT_REASON_XSETBV:
7574 return 1;
81dc01f7
WL		 7575 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7576 /*
7577 * This should never happen, since it is not possible to
7578 * set XSS to a non-zero value---neither in L1 nor in L2.
7579 * If if it were, XSS would have to be checked against
7580 * the XSS exit bitmap in vmcs12.
7581 */
7582 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a
NHE		 7583 default:
7584 return 1;
7585 }
7586}
7587
586f9607
AK		 7588static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7589{
7590 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7591 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7592}
7593
843e4330
KH		 7594static int vmx_enable_pml(struct vcpu_vmx *vmx)
7595{
7596 struct page *pml_pg;
7597 u32 exec_control;
7598
7599 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7600 if (!pml_pg)
7601 return -ENOMEM;
7602
7603 vmx->pml_pg = pml_pg;
7604
7605 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7606 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7607
7608 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7609 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7610 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7611
7612 return 0;
7613}
7614
7615static void vmx_disable_pml(struct vcpu_vmx *vmx)
7616{
7617 u32 exec_control;
7618
7619 ASSERT(vmx->pml_pg);
7620 __free_page(vmx->pml_pg);
7621 vmx->pml_pg = NULL;
7622
7623 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7624 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7625 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7626}
7627
7628static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7629{
7630 struct kvm *kvm = vmx->vcpu.kvm;
7631 u64 *pml_buf;
7632 u16 pml_idx;
7633
7634 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7635
7636 /* Do nothing if PML buffer is empty */
7637 if (pml_idx == (PML_ENTITY_NUM - 1))
7638 return;
7639
7640 /* PML index always points to next available PML buffer entity */
7641 if (pml_idx >= PML_ENTITY_NUM)
7642 pml_idx = 0;
7643 else
7644 pml_idx++;
7645
7646 pml_buf = page_address(vmx->pml_pg);
7647 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7648 u64 gpa;
7649
7650 gpa = pml_buf[pml_idx];
7651 WARN_ON(gpa & (PAGE_SIZE - 1));
7652 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7653 }
7654
7655 /* reset PML index */
7656 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7657}
7658
7659/*
7660 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7661 * Called before reporting dirty_bitmap to userspace.
7662 */
7663static void kvm_flush_pml_buffers(struct kvm *kvm)
7664{
7665 int i;
7666 struct kvm_vcpu *vcpu;
7667 /*
7668 * We only need to kick vcpu out of guest mode here, as PML buffer
7669 * is flushed at beginning of all VMEXITs, and it's obvious that only
7670 * vcpus running in guest are possible to have unflushed GPAs in PML
7671 * buffer.
7672 */
7673 kvm_for_each_vcpu(i, vcpu, kvm)
7674 kvm_vcpu_kick(vcpu);
7675}
7676
6aa8b732
AK		 7677/*
7678 * The guest has exited. See if we can fix it or if we need userspace
7679 * assistance.
7680 */
851ba692 7681static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7682{
29bd8a78 7683 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7684 u32 exit_reason = vmx->exit_reason;
1155f76a 7685 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7686
843e4330
KH		 7687 /*
7688 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7689 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7690 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7691 * mode as if vcpus is in root mode, the PML buffer must has been
7692 * flushed already.
7693 */
7694 if (enable_pml)
7695 vmx_flush_pml_buffer(vmx);
7696
80ced186 7697 /* If guest state is invalid, start emulating */
14168786 7698 if (vmx->emulation_required)
80ced186 7699 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7700
644d711a 7701 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7702 nested_vmx_vmexit(vcpu, exit_reason,
7703 vmcs_read32(VM_EXIT_INTR_INFO),
7704 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7705 return 1;
7706 }
7707
5120702e
MG		 7708 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7709 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7710 vcpu->run->fail_entry.hardware_entry_failure_reason
7711 = exit_reason;
7712 return 0;
7713 }
7714
29bd8a78 7715 if (unlikely(vmx->fail)) {
851ba692
AK		 7716 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7717 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7718 = vmcs_read32(VM_INSTRUCTION_ERROR);
7719 return 0;
7720 }
6aa8b732 7721
b9bf6882
XG		 7722 /*
7723 * Note:
7724 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7725 * delivery event since it indicates guest is accessing MMIO.
7726 * The vm-exit can be triggered again after return to guest that
7727 * will cause infinite loop.
7728 */
d77c26fc 7729 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7730 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7731 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7732 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7733 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7734 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7735 vcpu->run->internal.ndata = 2;
7736 vcpu->run->internal.data[0] = vectoring_info;
7737 vcpu->run->internal.data[1] = exit_reason;
7738 return 0;
7739 }
3b86cd99 7740
644d711a
NHE		 7741 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7742 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7743 get_vmcs12(vcpu))))) {
c4282df9 7744 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7745 vmx->soft_vnmi_blocked = 0;
3b86cd99 7746 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7747 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7748 /*
7749 * This CPU don't support us in finding the end of an
7750 * NMI-blocked window if the guest runs with IRQs
7751 * disabled. So we pull the trigger after 1 s of
7752 * futile waiting, but inform the user about this.
7753 */
7754 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7755 "state on VCPU %d after 1 s timeout\n",
7756 __func__, vcpu->vcpu_id);
7757 vmx->soft_vnmi_blocked = 0;
3b86cd99 7758 }
3b86cd99
JK		 7759 }
7760
6aa8b732
AK		 7761 if (exit_reason < kvm_vmx_max_exit_handlers
7762 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7763 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7764 else {
2bc19dc3
MT		 7765 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7766 kvm_queue_exception(vcpu, UD_VECTOR);
7767 return 1;
6aa8b732 7768 }
6aa8b732
AK		 7769}
7770
95ba8273 7771static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7772{
a7c0b07d
WL		 7773 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7774
7775 if (is_guest_mode(vcpu) &&
7776 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7777 return;
7778
95ba8273 7779 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7780 vmcs_write32(TPR_THRESHOLD, 0);
7781 return;
7782 }
7783
95ba8273 7784 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7785}
7786
8d14695f
YZ		 7787static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7788{
7789 u32 sec_exec_control;
7790
7791 /*
7792 * There is not point to enable virtualize x2apic without enable
7793 * apicv
7794 */
c7c9c56c
YZ		 7795 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7796 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7797 return;
7798
7799 if (!vm_need_tpr_shadow(vcpu->kvm))
7800 return;
7801
7802 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7803
7804 if (set) {
7805 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7806 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7807 } else {
7808 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7809 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7810 }
7811 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7812
7813 vmx_set_msr_bitmap(vcpu);
7814}
7815
38b99173
TC		 7816static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7817{
7818 struct vcpu_vmx *vmx = to_vmx(vcpu);
7819
7820 /*
7821 * Currently we do not handle the nested case where L2 has an
7822 * APIC access page of its own; that page is still pinned.
7823 * Hence, we skip the case where the VCPU is in guest mode _and_
7824 * L1 prepared an APIC access page for L2.
7825 *
7826 * For the case where L1 and L2 share the same APIC access page
7827 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7828 * in the vmcs12), this function will only update either the vmcs01
7829 * or the vmcs02. If the former, the vmcs02 will be updated by
7830 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7831 * the next L2->L1 exit.
7832 */
7833 if (!is_guest_mode(vcpu) ||
7834 !nested_cpu_has2(vmx->nested.current_vmcs12,
7835 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7836 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7837}
7838
c7c9c56c
YZ		 7839static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7840{
7841 u16 status;
7842 u8 old;
7843
c7c9c56c
YZ		 7844 if (isr == -1)
7845 isr = 0;
7846
7847 status = vmcs_read16(GUEST_INTR_STATUS);
7848 old = status >> 8;
7849 if (isr != old) {
7850 status &= 0xff;
7851 status |= isr << 8;
7852 vmcs_write16(GUEST_INTR_STATUS, status);
7853 }
7854}
7855
7856static void vmx_set_rvi(int vector)
7857{
7858 u16 status;
7859 u8 old;
7860
4114c27d
WW		 7861 if (vector == -1)
7862 vector = 0;
7863
c7c9c56c
YZ		 7864 status = vmcs_read16(GUEST_INTR_STATUS);
7865 old = (u8)status & 0xff;
7866 if ((u8)vector != old) {
7867 status &= ~0xff;
7868 status |= (u8)vector;
7869 vmcs_write16(GUEST_INTR_STATUS, status);
7870 }
7871}
7872
7873static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7874{
4114c27d
WW		 7875 if (!is_guest_mode(vcpu)) {
7876 vmx_set_rvi(max_irr);
7877 return;
7878 }
7879
c7c9c56c
YZ		 7880 if (max_irr == -1)
7881 return;
7882
963fee16 7883 /*
4114c27d
WW		 7884 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7885 * handles it.
963fee16 7886 */
4114c27d 7887 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7888 return;
7889
963fee16 7890 /*
4114c27d 7891 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7892 * is run without virtual interrupt delivery.
7893 */
7894 if (!kvm_event_needs_reinjection(vcpu) &&
7895 vmx_interrupt_allowed(vcpu)) {
7896 kvm_queue_interrupt(vcpu, max_irr, false);
7897 vmx_inject_irq(vcpu);
7898 }
c7c9c56c
YZ		 7899}
7900
7901static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7902{
3d81bc7e
YZ		 7903 if (!vmx_vm_has_apicv(vcpu->kvm))
7904 return;
7905
c7c9c56c
YZ		 7906 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7907 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7908 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7909 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7910}
7911
51aa01d1 7912static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7913{
00eba012
AK		 7914 u32 exit_intr_info;
7915
7916 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7917 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7918 return;
7919
c5ca8e57 7920 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7921 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7922
7923 /* Handle machine checks before interrupts are enabled */
00eba012 7924 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7925 kvm_machine_check();
7926
20f65983 7927 /* We need to handle NMIs before interrupts are enabled */
00eba012 7928 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7929 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7930 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7931 asm("int $2");
ff9d07a0
ZY		 7932 kvm_after_handle_nmi(&vmx->vcpu);
7933 }
51aa01d1 7934}
20f65983 7935
a547c6db
YZ		 7936static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7937{
7938 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7939
7940 /*
7941 * If external interrupt exists, IF bit is set in rflags/eflags on the
7942 * interrupt stack frame, and interrupt will be enabled on a return
7943 * from interrupt handler.
7944 */
7945 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7946 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7947 unsigned int vector;
7948 unsigned long entry;
7949 gate_desc *desc;
7950 struct vcpu_vmx *vmx = to_vmx(vcpu);
7951#ifdef CONFIG_X86_64
7952 unsigned long tmp;
7953#endif
7954
7955 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7956 desc = (gate_desc *)vmx->host_idt_base + vector;
7957 entry = gate_offset(*desc);
7958 asm volatile(
7959#ifdef CONFIG_X86_64
7960 "mov %%" _ASM_SP ", %[sp]\n\t"
7961 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7962 "push $%c[ss]\n\t"
7963 "push %[sp]\n\t"
7964#endif
7965 "pushf\n\t"
7966 "orl $0x200, (%%" _ASM_SP ")\n\t"
7967 __ASM_SIZE(push) " $%c[cs]\n\t"
7968 "call *%[entry]\n\t"
7969 :
7970#ifdef CONFIG_X86_64
7971 [sp]"=&r"(tmp)
7972#endif
7973 :
7974 [entry]"r"(entry),
7975 [ss]"i"(__KERNEL_DS),
7976 [cs]"i"(__KERNEL_CS)
7977 );
7978 } else
7979 local_irq_enable();
7980}
7981
da8999d3
LJ		 7982static bool vmx_mpx_supported(void)
7983{
7984 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7985 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7986}
7987
55412b2e
WL		 7988static bool vmx_xsaves_supported(void)
7989{
7990 return vmcs_config.cpu_based_2nd_exec_ctrl &
7991 SECONDARY_EXEC_XSAVES;
7992}
7993
51aa01d1
AK		 7994static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7995{
c5ca8e57 7996 u32 exit_intr_info;
51aa01d1
AK		 7997 bool unblock_nmi;
7998 u8 vector;
7999 bool idtv_info_valid;
8000
8001 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8002
cf393f75 8003 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8004 if (vmx->nmi_known_unmasked)
8005 return;
c5ca8e57
AK		 8006 /*
8007 * Can't use vmx->exit_intr_info since we're not sure what
8008 * the exit reason is.
8009 */
8010 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8011 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8012 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8013 /*
7b4a25cb 8014 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8015 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8016 * a guest IRET fault.
7b4a25cb
GN		 8017 * SDM 3: 23.2.2 (September 2008)
8018 * Bit 12 is undefined in any of the following cases:
8019 * If the VM exit sets the valid bit in the IDT-vectoring
8020 * information field.
8021 * If the VM exit is due to a double fault.
cf393f75 8022 */
7b4a25cb
GN		 8023 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8024 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8025 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8026 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8027 else
8028 vmx->nmi_known_unmasked =
8029 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8030 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8031 } else if (unlikely(vmx->soft_vnmi_blocked))
8032 vmx->vnmi_blocked_time +=
8033 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8034}
8035
3ab66e8a 8036static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8037 u32 idt_vectoring_info,
8038 int instr_len_field,
8039 int error_code_field)
51aa01d1 8040{
51aa01d1
AK		 8041 u8 vector;
8042 int type;
8043 bool idtv_info_valid;
8044
8045 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8046
3ab66e8a
JK		 8047 vcpu->arch.nmi_injected = false;
8048 kvm_clear_exception_queue(vcpu);
8049 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8050
8051 if (!idtv_info_valid)
8052 return;
8053
3ab66e8a 8054 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8055
668f612f
AK		 8056 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8057 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8058
64a7ec06 8059 switch (type) {
37b96e98 8060 case INTR_TYPE_NMI_INTR:
3ab66e8a 8061 vcpu->arch.nmi_injected = true;
668f612f 8062 /*
7b4a25cb 8063 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8064 * Clear bit "block by NMI" before VM entry if a NMI
8065 * delivery faulted.
668f612f 8066 */
3ab66e8a 8067 vmx_set_nmi_mask(vcpu, false);
37b96e98 8068 break;
37b96e98 8069 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8070 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8071 /* fall through */
8072 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8073 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8074 u32 err = vmcs_read32(error_code_field);
851eb667 8075 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8076 } else
851eb667 8077 kvm_requeue_exception(vcpu, vector);
37b96e98 8078 break;
66fd3f7f 8079 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8080 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8081 /* fall through */
37b96e98 8082 case INTR_TYPE_EXT_INTR:
3ab66e8a 8083 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8084 break;
8085 default:
8086 break;
f7d9238f 8087 }
cf393f75
AK		 8088}
8089
83422e17
AK		 8090static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8091{
3ab66e8a 8092 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8093 VM_EXIT_INSTRUCTION_LEN,
8094 IDT_VECTORING_ERROR_CODE);
8095}
8096
b463a6f7
AK		 8097static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8098{
3ab66e8a 8099 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8100 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8101 VM_ENTRY_INSTRUCTION_LEN,
8102 VM_ENTRY_EXCEPTION_ERROR_CODE);
8103
8104 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8105}
8106
d7cd9796
GN		 8107static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8108{
8109 int i, nr_msrs;
8110 struct perf_guest_switch_msr *msrs;
8111
8112 msrs = perf_guest_get_msrs(&nr_msrs);
8113
8114 if (!msrs)
8115 return;
8116
8117 for (i = 0; i < nr_msrs; i++)
8118 if (msrs[i].host == msrs[i].guest)
8119 clear_atomic_switch_msr(vmx, msrs[i].msr);
8120 else
8121 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8122 msrs[i].host);
8123}
8124
a3b5ba49 8125static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8126{
a2fa3e9f 8127 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8128 unsigned long debugctlmsr, cr4;
104f226b
AK		 8129
8130 /* Record the guest's net vcpu time for enforced NMI injections. */
8131 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8132 vmx->entry_time = ktime_get();
8133
8134 /* Don't enter VMX if guest state is invalid, let the exit handler
8135 start emulation until we arrive back to a valid state */
14168786 8136 if (vmx->emulation_required)
104f226b
AK		 8137 return;
8138
a7653ecd
RK		 8139 if (vmx->ple_window_dirty) {
8140 vmx->ple_window_dirty = false;
8141 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8142 }
8143
012f83cb
AG		 8144 if (vmx->nested.sync_shadow_vmcs) {
8145 copy_vmcs12_to_shadow(vmx);
8146 vmx->nested.sync_shadow_vmcs = false;
8147 }
8148
104f226b
AK		 8149 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8150 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8151 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8152 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8153
1e02ce4c 8154 cr4 = cr4_read_shadow();
d974baa3
AL		 8155 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8156 vmcs_writel(HOST_CR4, cr4);
8157 vmx->host_state.vmcs_host_cr4 = cr4;
8158 }
8159
104f226b
AK		 8160 /* When single-stepping over STI and MOV SS, we must clear the
8161 * corresponding interruptibility bits in the guest state. Otherwise
8162 * vmentry fails as it then expects bit 14 (BS) in pending debug
8163 * exceptions being set, but that's not correct for the guest debugging
8164 * case. */
8165 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8166 vmx_set_interrupt_shadow(vcpu, 0);
8167
d7cd9796 8168 atomic_switch_perf_msrs(vmx);
2a7921b7 8169 debugctlmsr = get_debugctlmsr();
d7cd9796 8170
d462b819 8171 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8172 asm(
6aa8b732 8173 /* Store host registers */
b188c81f
AK		 8174 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8175 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8176 "push %%" _ASM_CX " \n\t"
8177 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8178 "je 1f \n\t"
b188c81f 8179 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8180 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8181 "1: \n\t"
d3edefc0 8182 /* Reload cr2 if changed */
b188c81f
AK		 8183 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8184 "mov %%cr2, %%" _ASM_DX " \n\t"
8185 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8186 "je 2f \n\t"
b188c81f 8187 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8188 "2: \n\t"
6aa8b732 8189 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8190 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8191 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8192 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8193 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8194 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8195 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8196 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8197 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8198#ifdef CONFIG_X86_64
e08aa78a
AK		 8199 "mov %c[r8](%0), %%r8 \n\t"
8200 "mov %c[r9](%0), %%r9 \n\t"
8201 "mov %c[r10](%0), %%r10 \n\t"
8202 "mov %c[r11](%0), %%r11 \n\t"
8203 "mov %c[r12](%0), %%r12 \n\t"
8204 "mov %c[r13](%0), %%r13 \n\t"
8205 "mov %c[r14](%0), %%r14 \n\t"
8206 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8207#endif
b188c81f 8208 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8209
6aa8b732 8210 /* Enter guest mode */
83287ea4 8211 "jne 1f \n\t"
4ecac3fd 8212 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8213 "jmp 2f \n\t"
8214 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8215 "2: "
6aa8b732 8216 /* Save guest registers, load host registers, keep flags */
b188c81f 8217 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8218 "pop %0 \n\t"
b188c81f
AK		 8219 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8220 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8221 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8222 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8223 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8224 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8225 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8226#ifdef CONFIG_X86_64
e08aa78a
AK		 8227 "mov %%r8, %c[r8](%0) \n\t"
8228 "mov %%r9, %c[r9](%0) \n\t"
8229 "mov %%r10, %c[r10](%0) \n\t"
8230 "mov %%r11, %c[r11](%0) \n\t"
8231 "mov %%r12, %c[r12](%0) \n\t"
8232 "mov %%r13, %c[r13](%0) \n\t"
8233 "mov %%r14, %c[r14](%0) \n\t"
8234 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8235#endif
b188c81f
AK		 8236 "mov %%cr2, %%" _ASM_AX " \n\t"
8237 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8238
b188c81f 8239 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8240 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8241 ".pushsection .rodata \n\t"
8242 ".global vmx_return \n\t"
8243 "vmx_return: " _ASM_PTR " 2b \n\t"
8244 ".popsection"
e08aa78a 8245 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8246 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8247 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8248 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8249 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8250 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8251 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8252 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8253 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8254 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8255 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8256#ifdef CONFIG_X86_64
ad312c7c
ZX		 8257 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8258 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8259 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8260 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8261 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8262 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8263 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8264 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8265#endif
40712fae
AK		 8266 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8267 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8268 : "cc", "memory"
8269#ifdef CONFIG_X86_64
b188c81f 8270 , "rax", "rbx", "rdi", "rsi"
c2036300 8271 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8272#else
8273 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8274#endif
8275 );
6aa8b732 8276
2a7921b7
GN		 8277 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8278 if (debugctlmsr)
8279 update_debugctlmsr(debugctlmsr);
8280
aa67f609
AK		 8281#ifndef CONFIG_X86_64
8282 /*
8283 * The sysexit path does not restore ds/es, so we must set them to
8284 * a reasonable value ourselves.
8285 *
8286 * We can't defer this to vmx_load_host_state() since that function
8287 * may be executed in interrupt context, which saves and restore segments
8288 * around it, nullifying its effect.
8289 */
8290 loadsegment(ds, __USER_DS);
8291 loadsegment(es, __USER_DS);
8292#endif
8293
6de4f3ad 8294 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8295 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8296 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8297 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8298 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8299 vcpu->arch.regs_dirty = 0;
8300
1155f76a
AK		 8301 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8302
d462b819 8303 vmx->loaded_vmcs->launched = 1;
1b6269db 8304
51aa01d1 8305 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8306 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8307
e0b890d3
GN		 8308 /*
8309 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8310 * we did not inject a still-pending event to L1 now because of
8311 * nested_run_pending, we need to re-enable this bit.
8312 */
8313 if (vmx->nested.nested_run_pending)
8314 kvm_make_request(KVM_REQ_EVENT, vcpu);
8315
8316 vmx->nested.nested_run_pending = 0;
8317
51aa01d1
AK		 8318 vmx_complete_atomic_exit(vmx);
8319 vmx_recover_nmi_blocking(vmx);
cf393f75 8320 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8321}
8322
4fa7734c
PB		 8323static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8324{
8325 struct vcpu_vmx *vmx = to_vmx(vcpu);
8326 int cpu;
8327
8328 if (vmx->loaded_vmcs == &vmx->vmcs01)
8329 return;
8330
8331 cpu = get_cpu();
8332 vmx->loaded_vmcs = &vmx->vmcs01;
8333 vmx_vcpu_put(vcpu);
8334 vmx_vcpu_load(vcpu, cpu);
8335 vcpu->cpu = cpu;
8336 put_cpu();
8337}
8338
6aa8b732
AK		 8339static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8340{
fb3f0f51
RR		 8341 struct vcpu_vmx *vmx = to_vmx(vcpu);
8342
843e4330
KH		 8343 if (enable_pml)
8344 vmx_disable_pml(vmx);
cdbecfc3 8345 free_vpid(vmx);
4fa7734c
PB		 8346 leave_guest_mode(vcpu);
8347 vmx_load_vmcs01(vcpu);
26a865f4 8348 free_nested(vmx);
4fa7734c 8349 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8350 kfree(vmx->guest_msrs);
8351 kvm_vcpu_uninit(vcpu);
a4770347 8352 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8353}
8354
fb3f0f51 8355static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8356{
fb3f0f51 8357 int err;
c16f862d 8358 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8359 int cpu;
6aa8b732 8360
a2fa3e9f 8361 if (!vmx)
fb3f0f51
RR		 8362 return ERR_PTR(-ENOMEM);
8363
2384d2b3
SY		 8364 allocate_vpid(vmx);
8365
fb3f0f51
RR		 8366 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8367 if (err)
8368 goto free_vcpu;
965b58a5 8369
a2fa3e9f 8370 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8371 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8372 > PAGE_SIZE);
0123be42 8373
be6d05cf 8374 err = -ENOMEM;
fb3f0f51 8375 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8376 goto uninit_vcpu;
8377 }
965b58a5 8378
d462b819
NHE		 8379 vmx->loaded_vmcs = &vmx->vmcs01;
8380 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8381 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8382 goto free_msrs;
d462b819
NHE		 8383 if (!vmm_exclusive)
8384 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8385 loaded_vmcs_init(vmx->loaded_vmcs);
8386 if (!vmm_exclusive)
8387 kvm_cpu_vmxoff();
a2fa3e9f 8388
15ad7146
AK		 8389 cpu = get_cpu();
8390 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8391 vmx->vcpu.cpu = cpu;
8b9cf98c 8392 err = vmx_vcpu_setup(vmx);
fb3f0f51 8393 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8394 put_cpu();
fb3f0f51
RR		 8395 if (err)
8396 goto free_vmcs;
a63cb560 8397 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8398 err = alloc_apic_access_page(kvm);
8399 if (err)
5e4a0b3c 8400 goto free_vmcs;
a63cb560 8401 }
fb3f0f51 8402
b927a3ce
SY		 8403 if (enable_ept) {
8404 if (!kvm->arch.ept_identity_map_addr)
8405 kvm->arch.ept_identity_map_addr =
8406 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8407 err = init_rmode_identity_map(kvm);
8408 if (err)
93ea5388 8409 goto free_vmcs;
b927a3ce 8410 }
b7ebfb05 8411
b9c237bb
WV		 8412 if (nested)
8413 nested_vmx_setup_ctls_msrs(vmx);
8414
705699a1 8415 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8416 vmx->nested.current_vmptr = -1ull;
8417 vmx->nested.current_vmcs12 = NULL;
8418
843e4330
KH		 8419 /*
8420 * If PML is turned on, failure on enabling PML just results in failure
8421 * of creating the vcpu, therefore we can simplify PML logic (by
8422 * avoiding dealing with cases, such as enabling PML partially on vcpus
8423 * for the guest, etc.
8424 */
8425 if (enable_pml) {
8426 err = vmx_enable_pml(vmx);
8427 if (err)
8428 goto free_vmcs;
8429 }
8430
fb3f0f51
RR		 8431 return &vmx->vcpu;
8432
8433free_vmcs:
5f3fbc34 8434 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8435free_msrs:
fb3f0f51
RR		 8436 kfree(vmx->guest_msrs);
8437uninit_vcpu:
8438 kvm_vcpu_uninit(&vmx->vcpu);
8439free_vcpu:
cdbecfc3 8440 free_vpid(vmx);
a4770347 8441 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8442 return ERR_PTR(err);
6aa8b732
AK		 8443}
8444
002c7f7c
YS		 8445static void __init vmx_check_processor_compat(void *rtn)
8446{
8447 struct vmcs_config vmcs_conf;
8448
8449 *(int *)rtn = 0;
8450 if (setup_vmcs_config(&vmcs_conf) < 0)
8451 *(int *)rtn = -EIO;
8452 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8453 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8454 smp_processor_id());
8455 *(int *)rtn = -EIO;
8456 }
8457}
8458
67253af5
SY		 8459static int get_ept_level(void)
8460{
8461 return VMX_EPT_DEFAULT_GAW + 1;
8462}
8463
4b12f0de 8464static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8465{
4b12f0de
SY		 8466 u64 ret;
8467
522c68c4
SY		 8468 /* For VT-d and EPT combination
8469 * 1. MMIO: always map as UC
8470 * 2. EPT with VT-d:
8471 * a. VT-d without snooping control feature: can't guarantee the
8472 * result, try to trust guest.
8473 * b. VT-d with snooping control feature: snooping control feature of
8474 * VT-d engine can guarantee the cache correctness. Just set it
8475 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8476 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8477 * consistent with host MTRR
8478 */
4b12f0de
SY		 8479 if (is_mmio)
8480 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8481 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8482 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8483 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8484 else
522c68c4 8485 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8486 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8487
8488 return ret;
64d4d521
SY		 8489}
8490
17cc3935 8491static int vmx_get_lpage_level(void)
344f414f 8492{
878403b7
SY		 8493 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8494 return PT_DIRECTORY_LEVEL;
8495 else
8496 /* For shadow and EPT supported 1GB page */
8497 return PT_PDPE_LEVEL;
344f414f
JR		 8498}
8499
0e851880
SY		 8500static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8501{
4e47c7a6
SY		 8502 struct kvm_cpuid_entry2 *best;
8503 struct vcpu_vmx *vmx = to_vmx(vcpu);
8504 u32 exec_control;
8505
8506 vmx->rdtscp_enabled = false;
8507 if (vmx_rdtscp_supported()) {
8508 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8509 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8510 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8511 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8512 vmx->rdtscp_enabled = true;
8513 else {
8514 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8515 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8516 exec_control);
8517 }
8518 }
8519 }
ad756a16 8520
ad756a16
MJ		 8521 /* Exposing INVPCID only when PCID is exposed */
8522 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8523 if (vmx_invpcid_supported() &&
4f977045 8524 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8525 guest_cpuid_has_pcid(vcpu)) {
29282fde 8526 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8527 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8528 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8529 exec_control);
8530 } else {
29282fde
TI		 8531 if (cpu_has_secondary_exec_ctrls()) {
8532 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8533 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8534 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8535 exec_control);
8536 }
ad756a16 8537 if (best)
4f977045 8538 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8539 }
0e851880
SY		 8540}
8541
d4330ef2
JR		 8542static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8543{
7b8050f5
NHE		 8544 if (func == 1 && nested)
8545 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8546}
8547
25d92081
YZ		 8548static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8549 struct x86_exception *fault)
8550{
533558bc
JK		 8551 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8552 u32 exit_reason;
25d92081
YZ		 8553
8554 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8555 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8556 else
533558bc
JK		 8557 exit_reason = EXIT_REASON_EPT_VIOLATION;
8558 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8559 vmcs12->guest_physical_address = fault->address;
8560}
8561
155a97a3
NHE		 8562/* Callbacks for nested_ept_init_mmu_context: */
8563
8564static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8565{
8566 /* return the page table to be shadowed - in our case, EPT12 */
8567 return get_vmcs12(vcpu)->ept_pointer;
8568}
8569
8a3c1a33 8570static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8571{
ad896af0
PB		 8572 WARN_ON(mmu_is_nested(vcpu));
8573 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8574 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8575 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8576 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8577 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8578 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8579
8580 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8581}
8582
8583static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8584{
8585 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8586}
8587
19d5f10b
EK		 8588static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8589 u16 error_code)
8590{
8591 bool inequality, bit;
8592
8593 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8594 inequality =
8595 (error_code & vmcs12->page_fault_error_code_mask) !=
8596 vmcs12->page_fault_error_code_match;
8597 return inequality ^ bit;
8598}
8599
feaf0c7d
GN		 8600static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8601 struct x86_exception *fault)
8602{
8603 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8604
8605 WARN_ON(!is_guest_mode(vcpu));
8606
19d5f10b 8607 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8608 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8609 vmcs_read32(VM_EXIT_INTR_INFO),
8610 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8611 else
8612 kvm_inject_page_fault(vcpu, fault);
8613}
8614
a2bcba50
WL		 8615static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8616 struct vmcs12 *vmcs12)
8617{
8618 struct vcpu_vmx *vmx = to_vmx(vcpu);
8619
8620 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8621 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8622 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8623 return false;
8624
8625 /*
8626 * Translate L1 physical address to host physical
8627 * address for vmcs02. Keep the page pinned, so this
8628 * physical address remains valid. We keep a reference
8629 * to it so we can release it later.
8630 */
8631 if (vmx->nested.apic_access_page) /* shouldn't happen */
8632 nested_release_page(vmx->nested.apic_access_page);
8633 vmx->nested.apic_access_page =
8634 nested_get_page(vcpu, vmcs12->apic_access_addr);
8635 }
a7c0b07d
WL		 8636
8637 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8638 /* TODO: Also verify bits beyond physical address width are 0 */
8639 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8640 return false;
8641
8642 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8643 nested_release_page(vmx->nested.virtual_apic_page);
8644 vmx->nested.virtual_apic_page =
8645 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8646
8647 /*
8648 * Failing the vm entry is _not_ what the processor does
8649 * but it's basically the only possibility we have.
8650 * We could still enter the guest if CR8 load exits are
8651 * enabled, CR8 store exits are enabled, and virtualize APIC
8652 * access is disabled; in this case the processor would never
8653 * use the TPR shadow and we could simply clear the bit from
8654 * the execution control. But such a configuration is useless,
8655 * so let's keep the code simple.
8656 */
8657 if (!vmx->nested.virtual_apic_page)
8658 return false;
8659 }
8660
705699a1
WV		 8661 if (nested_cpu_has_posted_intr(vmcs12)) {
8662 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64))
8663 return false;
8664
8665 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8666 kunmap(vmx->nested.pi_desc_page);
8667 nested_release_page(vmx->nested.pi_desc_page);
8668 }
8669 vmx->nested.pi_desc_page =
8670 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8671 if (!vmx->nested.pi_desc_page)
8672 return false;
8673
8674 vmx->nested.pi_desc =
8675 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8676 if (!vmx->nested.pi_desc) {
8677 nested_release_page_clean(vmx->nested.pi_desc_page);
8678 return false;
8679 }
8680 vmx->nested.pi_desc =
8681 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8682 (unsigned long)(vmcs12->posted_intr_desc_addr &
8683 (PAGE_SIZE - 1)));
8684 }
8685
a2bcba50
WL		 8686 return true;
8687}
8688
f4124500
JK		 8689static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8690{
8691 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8692 struct vcpu_vmx *vmx = to_vmx(vcpu);
8693
8694 if (vcpu->arch.virtual_tsc_khz == 0)
8695 return;
8696
8697 /* Make sure short timeouts reliably trigger an immediate vmexit.
8698 * hrtimer_start does not guarantee this. */
8699 if (preemption_timeout <= 1) {
8700 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8701 return;
8702 }
8703
8704 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8705 preemption_timeout *= 1000000;
8706 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8707 hrtimer_start(&vmx->nested.preemption_timer,
8708 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8709}
8710
3af18d9c
WV		 8711static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8712 struct vmcs12 *vmcs12)
8713{
8714 int maxphyaddr;
8715 u64 addr;
8716
8717 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8718 return 0;
8719
8720 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8721 WARN_ON(1);
8722 return -EINVAL;
8723 }
8724 maxphyaddr = cpuid_maxphyaddr(vcpu);
8725
8726 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8727 ((addr + PAGE_SIZE) >> maxphyaddr))
8728 return -EINVAL;
8729
8730 return 0;
8731}
8732
8733/*
8734 * Merge L0's and L1's MSR bitmap, return false to indicate that
8735 * we do not use the hardware.
8736 */
8737static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8738 struct vmcs12 *vmcs12)
8739{
82f0dd4b 8740 int msr;
f2b93280
WV		 8741 struct page *page;
8742 unsigned long *msr_bitmap;
8743
8744 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8745 return false;
8746
8747 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8748 if (!page) {
8749 WARN_ON(1);
8750 return false;
8751 }
8752 msr_bitmap = (unsigned long *)kmap(page);
8753 if (!msr_bitmap) {
8754 nested_release_page_clean(page);
8755 WARN_ON(1);
8756 return false;
8757 }
8758
8759 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8760 if (nested_cpu_has_apic_reg_virt(vmcs12))
8761 for (msr = 0x800; msr <= 0x8ff; msr++)
8762 nested_vmx_disable_intercept_for_msr(
8763 msr_bitmap,
8764 vmx_msr_bitmap_nested,
8765 msr, MSR_TYPE_R);
f2b93280
WV		 8766 /* TPR is allowed */
8767 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8768 vmx_msr_bitmap_nested,
8769 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8770 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8771 if (nested_cpu_has_vid(vmcs12)) {
8772 /* EOI and self-IPI are allowed */
8773 nested_vmx_disable_intercept_for_msr(
8774 msr_bitmap,
8775 vmx_msr_bitmap_nested,
8776 APIC_BASE_MSR + (APIC_EOI >> 4),
8777 MSR_TYPE_W);
8778 nested_vmx_disable_intercept_for_msr(
8779 msr_bitmap,
8780 vmx_msr_bitmap_nested,
8781 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8782 MSR_TYPE_W);
8783 }
82f0dd4b
WV		 8784 } else {
8785 /*
8786 * Enable reading intercept of all the x2apic
8787 * MSRs. We should not rely on vmcs12 to do any
8788 * optimizations here, it may have been modified
8789 * by L1.
8790 */
8791 for (msr = 0x800; msr <= 0x8ff; msr++)
8792 __vmx_enable_intercept_for_msr(
8793 vmx_msr_bitmap_nested,
8794 msr,
8795 MSR_TYPE_R);
8796
f2b93280
WV		 8797 __vmx_enable_intercept_for_msr(
8798 vmx_msr_bitmap_nested,
8799 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8800 MSR_TYPE_W);
608406e2
WV		 8801 __vmx_enable_intercept_for_msr(
8802 vmx_msr_bitmap_nested,
8803 APIC_BASE_MSR + (APIC_EOI >> 4),
8804 MSR_TYPE_W);
8805 __vmx_enable_intercept_for_msr(
8806 vmx_msr_bitmap_nested,
8807 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8808 MSR_TYPE_W);
82f0dd4b 8809 }
f2b93280
WV		 8810 kunmap(page);
8811 nested_release_page_clean(page);
8812
8813 return true;
8814}
8815
8816static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8817 struct vmcs12 *vmcs12)
8818{
82f0dd4b 8819 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 8820 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 8821 !nested_cpu_has_vid(vmcs12) &&
8822 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 8823 return 0;
8824
8825 /*
8826 * If virtualize x2apic mode is enabled,
8827 * virtualize apic access must be disabled.
8828 */
82f0dd4b
WV		 8829 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8830 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 8831 return -EINVAL;
8832
608406e2
WV		 8833 /*
8834 * If virtual interrupt delivery is enabled,
8835 * we must exit on external interrupts.
8836 */
8837 if (nested_cpu_has_vid(vmcs12) &&
8838 !nested_exit_on_intr(vcpu))
8839 return -EINVAL;
8840
705699a1
WV		 8841 /*
8842 * bits 15:8 should be zero in posted_intr_nv,
8843 * the descriptor address has been already checked
8844 * in nested_get_vmcs12_pages.
8845 */
8846 if (nested_cpu_has_posted_intr(vmcs12) &&
8847 (!nested_cpu_has_vid(vmcs12) ||
8848 !nested_exit_intr_ack_set(vcpu) ||
8849 vmcs12->posted_intr_nv & 0xff00))
8850 return -EINVAL;
8851
f2b93280
WV		 8852 /* tpr shadow is needed by all apicv features. */
8853 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8854 return -EINVAL;
8855
8856 return 0;
3af18d9c
WV		 8857}
8858
e9ac033e
EK		 8859static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8860 unsigned long count_field,
8861 unsigned long addr_field,
8862 int maxphyaddr)
ff651cb6 8863{
e9ac033e
EK		 8864 u64 count, addr;
8865
8866 if (vmcs12_read_any(vcpu, count_field, &count) ||
8867 vmcs12_read_any(vcpu, addr_field, &addr)) {
8868 WARN_ON(1);
8869 return -EINVAL;
8870 }
8871 if (count == 0)
8872 return 0;
8873 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8874 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8875 pr_warn_ratelimited(
8876 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8877 addr_field, maxphyaddr, count, addr);
8878 return -EINVAL;
8879 }
8880 return 0;
8881}
8882
8883static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8884 struct vmcs12 *vmcs12)
8885{
8886 int maxphyaddr;
8887
8888 if (vmcs12->vm_exit_msr_load_count == 0 &&
8889 vmcs12->vm_exit_msr_store_count == 0 &&
8890 vmcs12->vm_entry_msr_load_count == 0)
8891 return 0; /* Fast path */
8892 maxphyaddr = cpuid_maxphyaddr(vcpu);
8893 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8894 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8895 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8896 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8897 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8898 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8899 return -EINVAL;
8900 return 0;
8901}
8902
8903static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8904 struct vmx_msr_entry *e)
8905{
8906 /* x2APIC MSR accesses are not allowed */
8907 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8908 return -EINVAL;
8909 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8910 e->index == MSR_IA32_UCODE_REV)
8911 return -EINVAL;
8912 if (e->reserved != 0)
ff651cb6
WV		 8913 return -EINVAL;
8914 return 0;
8915}
8916
e9ac033e
EK		 8917static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8918 struct vmx_msr_entry *e)
ff651cb6
WV		 8919{
8920 if (e->index == MSR_FS_BASE ||
8921 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8922 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8923 nested_vmx_msr_check_common(vcpu, e))
8924 return -EINVAL;
8925 return 0;
8926}
8927
8928static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8929 struct vmx_msr_entry *e)
8930{
8931 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8932 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8933 return -EINVAL;
8934 return 0;
8935}
8936
8937/*
8938 * Load guest's/host's msr at nested entry/exit.
8939 * return 0 for success, entry index for failure.
8940 */
8941static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8942{
8943 u32 i;
8944 struct vmx_msr_entry e;
8945 struct msr_data msr;
8946
8947 msr.host_initiated = false;
8948 for (i = 0; i < count; i++) {
e9ac033e
EK		 8949 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8950 &e, sizeof(e))) {
8951 pr_warn_ratelimited(
8952 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8953 __func__, i, gpa + i * sizeof(e));
ff651cb6 8954 goto fail;
e9ac033e
EK		 8955 }
8956 if (nested_vmx_load_msr_check(vcpu, &e)) {
8957 pr_warn_ratelimited(
8958 "%s check failed (%u, 0x%x, 0x%x)\n",
8959 __func__, i, e.index, e.reserved);
8960 goto fail;
8961 }
ff651cb6
WV		 8962 msr.index = e.index;
8963 msr.data = e.value;
e9ac033e
EK		 8964 if (kvm_set_msr(vcpu, &msr)) {
8965 pr_warn_ratelimited(
8966 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8967 __func__, i, e.index, e.value);
ff651cb6 8968 goto fail;
e9ac033e 8969 }
ff651cb6
WV		 8970 }
8971 return 0;
8972fail:
8973 return i + 1;
8974}
8975
8976static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8977{
8978 u32 i;
8979 struct vmx_msr_entry e;
8980
8981 for (i = 0; i < count; i++) {
e9ac033e
EK		 8982 if (kvm_read_guest(vcpu->kvm,
8983 gpa + i * sizeof(e),
8984 &e, 2 * sizeof(u32))) {
8985 pr_warn_ratelimited(
8986 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8987 __func__, i, gpa + i * sizeof(e));
ff651cb6 8988 return -EINVAL;
e9ac033e
EK		 8989 }
8990 if (nested_vmx_store_msr_check(vcpu, &e)) {
8991 pr_warn_ratelimited(
8992 "%s check failed (%u, 0x%x, 0x%x)\n",
8993 __func__, i, e.index, e.reserved);
ff651cb6 8994 return -EINVAL;
e9ac033e
EK		 8995 }
8996 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8997 pr_warn_ratelimited(
8998 "%s cannot read MSR (%u, 0x%x)\n",
8999 __func__, i, e.index);
9000 return -EINVAL;
9001 }
9002 if (kvm_write_guest(vcpu->kvm,
9003 gpa + i * sizeof(e) +
ff651cb6 9004 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 9005 &e.value, sizeof(e.value))) {
9006 pr_warn_ratelimited(
9007 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9008 __func__, i, e.index, e.value);
9009 return -EINVAL;
9010 }
ff651cb6
WV		 9011 }
9012 return 0;
9013}
9014
fe3ef05c
NHE		 9015/*
9016 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9017 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9018 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9019 * guest in a way that will both be appropriate to L1's requests, and our
9020 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9021 * function also has additional necessary side-effects, like setting various
9022 * vcpu->arch fields.
9023 */
9024static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9025{
9026 struct vcpu_vmx *vmx = to_vmx(vcpu);
9027 u32 exec_control;
9028
9029 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9030 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9031 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9032 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9033 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9034 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9035 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9036 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9037 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9038 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9039 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9040 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9041 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9042 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9043 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9044 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9045 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9046 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9047 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9048 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9049 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9050 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9051 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9052 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9053 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9054 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9055 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9056 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9057 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9058 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9059 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9060 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9061 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9062 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9063 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9064 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9065
2996fca0
JK		 9066 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9067 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9068 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9069 } else {
9070 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9071 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9072 }
fe3ef05c
NHE		 9073 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9074 vmcs12->vm_entry_intr_info_field);
9075 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9076 vmcs12->vm_entry_exception_error_code);
9077 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9078 vmcs12->vm_entry_instruction_len);
9079 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9080 vmcs12->guest_interruptibility_info);
fe3ef05c 9081 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9082 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9083 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9084 vmcs12->guest_pending_dbg_exceptions);
9085 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9086 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9087
81dc01f7
WL		 9088 if (nested_cpu_has_xsaves(vmcs12))
9089 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9090 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9091
f4124500
JK		 9092 exec_control = vmcs12->pin_based_vm_exec_control;
9093 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9094 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9095
9096 if (nested_cpu_has_posted_intr(vmcs12)) {
9097 /*
9098 * Note that we use L0's vector here and in
9099 * vmx_deliver_nested_posted_interrupt.
9100 */
9101 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9102 vmx->nested.pi_pending = false;
9103 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9104 vmcs_write64(POSTED_INTR_DESC_ADDR,
9105 page_to_phys(vmx->nested.pi_desc_page) +
9106 (unsigned long)(vmcs12->posted_intr_desc_addr &
9107 (PAGE_SIZE - 1)));
9108 } else
9109 exec_control &= ~PIN_BASED_POSTED_INTR;
9110
f4124500 9111 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9112
f4124500
JK		 9113 vmx->nested.preemption_timer_expired = false;
9114 if (nested_cpu_has_preemption_timer(vmcs12))
9115 vmx_start_preemption_timer(vcpu);
0238ea91 9116
fe3ef05c
NHE		 9117 /*
9118 * Whether page-faults are trapped is determined by a combination of
9119 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9120 * If enable_ept, L0 doesn't care about page faults and we should
9121 * set all of these to L1's desires. However, if !enable_ept, L0 does
9122 * care about (at least some) page faults, and because it is not easy
9123 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9124 * to exit on each and every L2 page fault. This is done by setting
9125 * MASK=MATCH=0 and (see below) EB.PF=1.
9126 * Note that below we don't need special code to set EB.PF beyond the
9127 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9128 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9129 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9130 *
9131 * A problem with this approach (when !enable_ept) is that L1 may be
9132 * injected with more page faults than it asked for. This could have
9133 * caused problems, but in practice existing hypervisors don't care.
9134 * To fix this, we will need to emulate the PFEC checking (on the L1
9135 * page tables), using walk_addr(), when injecting PFs to L1.
9136 */
9137 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9138 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9139 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9140 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9141
9142 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9143 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 9144 if (!vmx->rdtscp_enabled)
9145 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9146 /* Take the following fields only from vmcs12 */
696dfd95
PB		 9147 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9148 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9149 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 9150 if (nested_cpu_has(vmcs12,
9151 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9152 exec_control |= vmcs12->secondary_vm_exec_control;
9153
9154 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9155 /*
9156 * If translation failed, no matter: This feature asks
9157 * to exit when accessing the given address, and if it
9158 * can never be accessed, this feature won't do
9159 * anything anyway.
9160 */
9161 if (!vmx->nested.apic_access_page)
9162 exec_control &=
9163 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9164 else
9165 vmcs_write64(APIC_ACCESS_ADDR,
9166 page_to_phys(vmx->nested.apic_access_page));
f2b93280
WV		 9167 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9168 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
ca3f257a
JK		 9169 exec_control |=
9170 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9171 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9172 }
9173
608406e2
WV		 9174 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9175 vmcs_write64(EOI_EXIT_BITMAP0,
9176 vmcs12->eoi_exit_bitmap0);
9177 vmcs_write64(EOI_EXIT_BITMAP1,
9178 vmcs12->eoi_exit_bitmap1);
9179 vmcs_write64(EOI_EXIT_BITMAP2,
9180 vmcs12->eoi_exit_bitmap2);
9181 vmcs_write64(EOI_EXIT_BITMAP3,
9182 vmcs12->eoi_exit_bitmap3);
9183 vmcs_write16(GUEST_INTR_STATUS,
9184 vmcs12->guest_intr_status);
9185 }
9186
fe3ef05c
NHE		 9187 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9188 }
9189
9190
9191 /*
9192 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9193 * Some constant fields are set here by vmx_set_constant_host_state().
9194 * Other fields are different per CPU, and will be set later when
9195 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9196 */
a547c6db 9197 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9198
9199 /*
9200 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9201 * entry, but only if the current (host) sp changed from the value
9202 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9203 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9204 * here we just force the write to happen on entry.
9205 */
9206 vmx->host_rsp = 0;
9207
9208 exec_control = vmx_exec_control(vmx); /* L0's desires */
9209 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9210 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9211 exec_control &= ~CPU_BASED_TPR_SHADOW;
9212 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9213
9214 if (exec_control & CPU_BASED_TPR_SHADOW) {
9215 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9216 page_to_phys(vmx->nested.virtual_apic_page));
9217 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9218 }
9219
3af18d9c
WV		 9220 if (cpu_has_vmx_msr_bitmap() &&
9221 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9222 nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) {
9223 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_nested));
9224 } else
9225 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9226
fe3ef05c 9227 /*
3af18d9c 9228 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9229 * Rather, exit every time.
9230 */
fe3ef05c
NHE		 9231 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9232 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9233
9234 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9235
9236 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9237 * bitwise-or of what L1 wants to trap for L2, and what we want to
9238 * trap. Note that CR0.TS also needs updating - we do this later.
9239 */
9240 update_exception_bitmap(vcpu);
9241 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9242 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9243
8049d651
NHE		 9244 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9245 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9246 * bits are further modified by vmx_set_efer() below.
9247 */
f4124500 9248 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9249
9250 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9251 * emulated by vmx_set_efer(), below.
9252 */
2961e876 9253 vm_entry_controls_init(vmx,
8049d651
NHE		 9254 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9255 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9256 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9257
44811c02 9258 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9259 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9260 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9261 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9262 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9263
9264
9265 set_cr4_guest_host_mask(vmx);
9266
36be0b9d
PB		 9267 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9268 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9269
27fc51b2
NHE		 9270 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9271 vmcs_write64(TSC_OFFSET,
9272 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9273 else
9274 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9275
9276 if (enable_vpid) {
9277 /*
9278 * Trivially support vpid by letting L2s share their parent
9279 * L1's vpid. TODO: move to a more elaborate solution, giving
9280 * each L2 its own vpid and exposing the vpid feature to L1.
9281 */
9282 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9283 vmx_flush_tlb(vcpu);
9284 }
9285
155a97a3
NHE		 9286 if (nested_cpu_has_ept(vmcs12)) {
9287 kvm_mmu_unload(vcpu);
9288 nested_ept_init_mmu_context(vcpu);
9289 }
9290
fe3ef05c
NHE		 9291 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9292 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9293 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9294 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9295 else
9296 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9297 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9298 vmx_set_efer(vcpu, vcpu->arch.efer);
9299
9300 /*
9301 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9302 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9303 * The CR0_READ_SHADOW is what L2 should have expected to read given
9304 * the specifications by L1; It's not enough to take
9305 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9306 * have more bits than L1 expected.
9307 */
9308 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9309 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9310
9311 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9312 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9313
9314 /* shadow page tables on either EPT or shadow page tables */
9315 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9316 kvm_mmu_reset_context(vcpu);
9317
feaf0c7d
GN		 9318 if (!enable_ept)
9319 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9320
3633cfc3
NHE		 9321 /*
9322 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9323 */
9324 if (enable_ept) {
9325 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9326 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9327 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9328 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9329 }
9330
fe3ef05c
NHE		 9331 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9332 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9333}
9334
cd232ad0
NHE		 9335/*
9336 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9337 * for running an L2 nested guest.
9338 */
9339static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9340{
9341 struct vmcs12 *vmcs12;
9342 struct vcpu_vmx *vmx = to_vmx(vcpu);
9343 int cpu;
9344 struct loaded_vmcs *vmcs02;
384bb783 9345 bool ia32e;
ff651cb6 9346 u32 msr_entry_idx;
cd232ad0
NHE		 9347
9348 if (!nested_vmx_check_permission(vcpu) ||
9349 !nested_vmx_check_vmcs12(vcpu))
9350 return 1;
9351
9352 skip_emulated_instruction(vcpu);
9353 vmcs12 = get_vmcs12(vcpu);
9354
012f83cb
AG		 9355 if (enable_shadow_vmcs)
9356 copy_shadow_to_vmcs12(vmx);
9357
7c177938
NHE		 9358 /*
9359 * The nested entry process starts with enforcing various prerequisites
9360 * on vmcs12 as required by the Intel SDM, and act appropriately when
9361 * they fail: As the SDM explains, some conditions should cause the
9362 * instruction to fail, while others will cause the instruction to seem
9363 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9364 * To speed up the normal (success) code path, we should avoid checking
9365 * for misconfigurations which will anyway be caught by the processor
9366 * when using the merged vmcs02.
9367 */
9368 if (vmcs12->launch_state == launch) {
9369 nested_vmx_failValid(vcpu,
9370 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9371 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9372 return 1;
9373 }
9374
6dfacadd
JK		 9375 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9376 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9377 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9378 return 1;
9379 }
9380
3af18d9c 9381 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9382 /*TODO: Also verify bits beyond physical address width are 0*/
9383 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9384 return 1;
9385 }
9386
3af18d9c 9387 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9388 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9389 return 1;
9390 }
9391
f2b93280
WV		 9392 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9393 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9394 return 1;
9395 }
9396
e9ac033e
EK		 9397 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9398 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9399 return 1;
9400 }
9401
7c177938 9402 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9403 vmx->nested.nested_vmx_true_procbased_ctls_low,
9404 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9405 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9406 vmx->nested.nested_vmx_secondary_ctls_low,
9407 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9408 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9409 vmx->nested.nested_vmx_pinbased_ctls_low,
9410 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9411 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9412 vmx->nested.nested_vmx_true_exit_ctls_low,
9413 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9414 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9415 vmx->nested.nested_vmx_true_entry_ctls_low,
9416 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9417 {
9418 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9419 return 1;
9420 }
9421
9422 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9423 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9424 nested_vmx_failValid(vcpu,
9425 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9426 return 1;
9427 }
9428
b9c237bb 9429 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9430 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9431 nested_vmx_entry_failure(vcpu, vmcs12,
9432 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9433 return 1;
9434 }
9435 if (vmcs12->vmcs_link_pointer != -1ull) {
9436 nested_vmx_entry_failure(vcpu, vmcs12,
9437 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9438 return 1;
9439 }
9440
384bb783 9441 /*
cb0c8cda 9442 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9443 * are performed on the field for the IA32_EFER MSR:
9444 * - Bits reserved in the IA32_EFER MSR must be 0.
9445 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9446 * the IA-32e mode guest VM-exit control. It must also be identical
9447 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9448 * CR0.PG) is 1.
9449 */
9450 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9451 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9452 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9453 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9454 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9455 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9456 nested_vmx_entry_failure(vcpu, vmcs12,
9457 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9458 return 1;
9459 }
9460 }
9461
9462 /*
9463 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9464 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9465 * the values of the LMA and LME bits in the field must each be that of
9466 * the host address-space size VM-exit control.
9467 */
9468 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9469 ia32e = (vmcs12->vm_exit_controls &
9470 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9471 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9472 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9473 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9474 nested_vmx_entry_failure(vcpu, vmcs12,
9475 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9476 return 1;
9477 }
9478 }
9479
7c177938
NHE		 9480 /*
9481 * We're finally done with prerequisite checking, and can start with
9482 * the nested entry.
9483 */
9484
cd232ad0
NHE		 9485 vmcs02 = nested_get_current_vmcs02(vmx);
9486 if (!vmcs02)
9487 return -ENOMEM;
9488
9489 enter_guest_mode(vcpu);
9490
9491 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9492
2996fca0
JK		 9493 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9494 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9495
cd232ad0
NHE		 9496 cpu = get_cpu();
9497 vmx->loaded_vmcs = vmcs02;
9498 vmx_vcpu_put(vcpu);
9499 vmx_vcpu_load(vcpu, cpu);
9500 vcpu->cpu = cpu;
9501 put_cpu();
9502
36c3cc42
JK		 9503 vmx_segment_cache_clear(vmx);
9504
cd232ad0
NHE		 9505 prepare_vmcs02(vcpu, vmcs12);
9506
ff651cb6
WV		 9507 msr_entry_idx = nested_vmx_load_msr(vcpu,
9508 vmcs12->vm_entry_msr_load_addr,
9509 vmcs12->vm_entry_msr_load_count);
9510 if (msr_entry_idx) {
9511 leave_guest_mode(vcpu);
9512 vmx_load_vmcs01(vcpu);
9513 nested_vmx_entry_failure(vcpu, vmcs12,
9514 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9515 return 1;
9516 }
9517
9518 vmcs12->launch_state = 1;
9519
6dfacadd
JK		 9520 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9521 return kvm_emulate_halt(vcpu);
9522
7af40ad3
JK		 9523 vmx->nested.nested_run_pending = 1;
9524
cd232ad0
NHE		 9525 /*
9526 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9527 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9528 * returned as far as L1 is concerned. It will only return (and set
9529 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9530 */
9531 return 1;
9532}
9533
4704d0be
NHE		 9534/*
9535 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9536 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9537 * This function returns the new value we should put in vmcs12.guest_cr0.
9538 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9539 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9540 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9541 * didn't trap the bit, because if L1 did, so would L0).
9542 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9543 * been modified by L2, and L1 knows it. So just leave the old value of
9544 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9545 * isn't relevant, because if L0 traps this bit it can set it to anything.
9546 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9547 * changed these bits, and therefore they need to be updated, but L0
9548 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9549 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9550 */
9551static inline unsigned long
9552vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9553{
9554 return
9555 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9556 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9557 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9558 vcpu->arch.cr0_guest_owned_bits));
9559}
9560
9561static inline unsigned long
9562vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9563{
9564 return
9565 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9566 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9567 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9568 vcpu->arch.cr4_guest_owned_bits));
9569}
9570
5f3d5799
JK		 9571static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9572 struct vmcs12 *vmcs12)
9573{
9574 u32 idt_vectoring;
9575 unsigned int nr;
9576
851eb667 9577 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9578 nr = vcpu->arch.exception.nr;
9579 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9580
9581 if (kvm_exception_is_soft(nr)) {
9582 vmcs12->vm_exit_instruction_len =
9583 vcpu->arch.event_exit_inst_len;
9584 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9585 } else
9586 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9587
9588 if (vcpu->arch.exception.has_error_code) {
9589 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9590 vmcs12->idt_vectoring_error_code =
9591 vcpu->arch.exception.error_code;
9592 }
9593
9594 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9595 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9596 vmcs12->idt_vectoring_info_field =
9597 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9598 } else if (vcpu->arch.interrupt.pending) {
9599 nr = vcpu->arch.interrupt.nr;
9600 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9601
9602 if (vcpu->arch.interrupt.soft) {
9603 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9604 vmcs12->vm_entry_instruction_len =
9605 vcpu->arch.event_exit_inst_len;
9606 } else
9607 idt_vectoring |= INTR_TYPE_EXT_INTR;
9608
9609 vmcs12->idt_vectoring_info_field = idt_vectoring;
9610 }
9611}
9612
b6b8a145
JK		 9613static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9614{
9615 struct vcpu_vmx *vmx = to_vmx(vcpu);
9616
f4124500
JK		 9617 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9618 vmx->nested.preemption_timer_expired) {
9619 if (vmx->nested.nested_run_pending)
9620 return -EBUSY;
9621 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9622 return 0;
9623 }
9624
b6b8a145 9625 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9626 if (vmx->nested.nested_run_pending ||
9627 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9628 return -EBUSY;
9629 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9630 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9631 INTR_INFO_VALID_MASK, 0);
9632 /*
9633 * The NMI-triggered VM exit counts as injection:
9634 * clear this one and block further NMIs.
9635 */
9636 vcpu->arch.nmi_pending = 0;
9637 vmx_set_nmi_mask(vcpu, true);
9638 return 0;
9639 }
9640
9641 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9642 nested_exit_on_intr(vcpu)) {
9643 if (vmx->nested.nested_run_pending)
9644 return -EBUSY;
9645 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9646 return 0;
b6b8a145
JK		 9647 }
9648
705699a1 9649 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9650}
9651
f4124500
JK		 9652static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9653{
9654 ktime_t remaining =
9655 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9656 u64 value;
9657
9658 if (ktime_to_ns(remaining) <= 0)
9659 return 0;
9660
9661 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9662 do_div(value, 1000000);
9663 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9664}
9665
4704d0be
NHE		 9666/*
9667 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9668 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9669 * and this function updates it to reflect the changes to the guest state while
9670 * L2 was running (and perhaps made some exits which were handled directly by L0
9671 * without going back to L1), and to reflect the exit reason.
9672 * Note that we do not have to copy here all VMCS fields, just those that
9673 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9674 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9675 * which already writes to vmcs12 directly.
9676 */
533558bc
JK		 9677static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9678 u32 exit_reason, u32 exit_intr_info,
9679 unsigned long exit_qualification)
4704d0be
NHE		 9680{
9681 /* update guest state fields: */
9682 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9683 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9684
4704d0be
NHE		 9685 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9686 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9687 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9688
9689 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9690 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9691 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9692 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9693 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9694 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9695 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9696 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9697 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9698 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9699 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9700 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9701 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9702 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9703 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9704 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9705 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9706 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9707 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9708 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9709 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9710 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9711 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9712 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9713 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9714 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9715 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9716 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9717 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9718 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9719 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9720 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9721 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9722 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9723 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9724 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9725
4704d0be
NHE		 9726 vmcs12->guest_interruptibility_info =
9727 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9728 vmcs12->guest_pending_dbg_exceptions =
9729 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9730 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9731 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9732 else
9733 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9734
f4124500
JK		 9735 if (nested_cpu_has_preemption_timer(vmcs12)) {
9736 if (vmcs12->vm_exit_controls &
9737 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9738 vmcs12->vmx_preemption_timer_value =
9739 vmx_get_preemption_timer_value(vcpu);
9740 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9741 }
7854cbca 9742
3633cfc3
NHE		 9743 /*
9744 * In some cases (usually, nested EPT), L2 is allowed to change its
9745 * own CR3 without exiting. If it has changed it, we must keep it.
9746 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9747 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9748 *
9749 * Additionally, restore L2's PDPTR to vmcs12.
9750 */
9751 if (enable_ept) {
9752 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9753 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9754 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9755 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9756 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9757 }
9758
608406e2
WV		 9759 if (nested_cpu_has_vid(vmcs12))
9760 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9761
c18911a2
JK		 9762 vmcs12->vm_entry_controls =
9763 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9764 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9765
2996fca0
JK		 9766 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9767 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9768 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9769 }
9770
4704d0be
NHE		 9771 /* TODO: These cannot have changed unless we have MSR bitmaps and
9772 * the relevant bit asks not to trap the change */
b8c07d55 9773 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9774 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9775 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9776 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9777 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9778 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9779 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9780 if (vmx_mpx_supported())
9781 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9782 if (nested_cpu_has_xsaves(vmcs12))
9783 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9784
9785 /* update exit information fields: */
9786
533558bc
JK		 9787 vmcs12->vm_exit_reason = exit_reason;
9788 vmcs12->exit_qualification = exit_qualification;
4704d0be 9789
533558bc 9790 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9791 if ((vmcs12->vm_exit_intr_info &
9792 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9793 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9794 vmcs12->vm_exit_intr_error_code =
9795 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9796 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9797 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9798 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9799
5f3d5799
JK		 9800 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9801 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9802 * instead of reading the real value. */
4704d0be 9803 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9804
9805 /*
9806 * Transfer the event that L0 or L1 may wanted to inject into
9807 * L2 to IDT_VECTORING_INFO_FIELD.
9808 */
9809 vmcs12_save_pending_event(vcpu, vmcs12);
9810 }
9811
9812 /*
9813 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9814 * preserved above and would only end up incorrectly in L1.
9815 */
9816 vcpu->arch.nmi_injected = false;
9817 kvm_clear_exception_queue(vcpu);
9818 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9819}
9820
9821/*
9822 * A part of what we need to when the nested L2 guest exits and we want to
9823 * run its L1 parent, is to reset L1's guest state to the host state specified
9824 * in vmcs12.
9825 * This function is to be called not only on normal nested exit, but also on
9826 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9827 * Failures During or After Loading Guest State").
9828 * This function should be called when the active VMCS is L1's (vmcs01).
9829 */
733568f9
JK		 9830static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9831 struct vmcs12 *vmcs12)
4704d0be 9832{
21feb4eb
ACL		 9833 struct kvm_segment seg;
9834
4704d0be
NHE		 9835 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9836 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9837 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9838 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9839 else
9840 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9841 vmx_set_efer(vcpu, vcpu->arch.efer);
9842
9843 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9844 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9845 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9846 /*
9847 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9848 * actually changed, because it depends on the current state of
9849 * fpu_active (which may have changed).
9850 * Note that vmx_set_cr0 refers to efer set above.
9851 */
9e3e4dbf 9852 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9853 /*
9854 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9855 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9856 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9857 */
9858 update_exception_bitmap(vcpu);
9859 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9860 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9861
9862 /*
9863 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9864 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9865 */
9866 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9867 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9868
29bf08f1 9869 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9870
4704d0be
NHE		 9871 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9872 kvm_mmu_reset_context(vcpu);
9873
feaf0c7d
GN		 9874 if (!enable_ept)
9875 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9876
4704d0be
NHE		 9877 if (enable_vpid) {
9878 /*
9879 * Trivially support vpid by letting L2s share their parent
9880 * L1's vpid. TODO: move to a more elaborate solution, giving
9881 * each L2 its own vpid and exposing the vpid feature to L1.
9882 */
9883 vmx_flush_tlb(vcpu);
9884 }
9885
9886
9887 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9888 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9889 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9890 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9891 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9892
36be0b9d
PB		 9893 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9894 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9895 vmcs_write64(GUEST_BNDCFGS, 0);
9896
44811c02 9897 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9898 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9899 vcpu->arch.pat = vmcs12->host_ia32_pat;
9900 }
4704d0be
NHE		 9901 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9902 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9903 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9904
21feb4eb
ACL		 9905 /* Set L1 segment info according to Intel SDM
9906 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9907 seg = (struct kvm_segment) {
9908 .base = 0,
9909 .limit = 0xFFFFFFFF,
9910 .selector = vmcs12->host_cs_selector,
9911 .type = 11,
9912 .present = 1,
9913 .s = 1,
9914 .g = 1
9915 };
9916 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9917 seg.l = 1;
9918 else
9919 seg.db = 1;
9920 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9921 seg = (struct kvm_segment) {
9922 .base = 0,
9923 .limit = 0xFFFFFFFF,
9924 .type = 3,
9925 .present = 1,
9926 .s = 1,
9927 .db = 1,
9928 .g = 1
9929 };
9930 seg.selector = vmcs12->host_ds_selector;
9931 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9932 seg.selector = vmcs12->host_es_selector;
9933 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9934 seg.selector = vmcs12->host_ss_selector;
9935 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9936 seg.selector = vmcs12->host_fs_selector;
9937 seg.base = vmcs12->host_fs_base;
9938 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9939 seg.selector = vmcs12->host_gs_selector;
9940 seg.base = vmcs12->host_gs_base;
9941 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9942 seg = (struct kvm_segment) {
205befd9 9943 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9944 .limit = 0x67,
9945 .selector = vmcs12->host_tr_selector,
9946 .type = 11,
9947 .present = 1
9948 };
9949 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9950
503cd0c5
JK		 9951 kvm_set_dr(vcpu, 7, 0x400);
9952 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 9953
3af18d9c
WV		 9954 if (cpu_has_vmx_msr_bitmap())
9955 vmx_set_msr_bitmap(vcpu);
9956
ff651cb6
WV		 9957 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9958 vmcs12->vm_exit_msr_load_count))
9959 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9960}
9961
9962/*
9963 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9964 * and modify vmcs12 to make it see what it would expect to see there if
9965 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9966 */
533558bc
JK		 9967static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9968 u32 exit_intr_info,
9969 unsigned long exit_qualification)
4704d0be
NHE		 9970{
9971 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9972 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9973
5f3d5799
JK		 9974 /* trying to cancel vmlaunch/vmresume is a bug */
9975 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9976
4704d0be 9977 leave_guest_mode(vcpu);
533558bc
JK		 9978 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9979 exit_qualification);
4704d0be 9980
ff651cb6
WV		 9981 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9982 vmcs12->vm_exit_msr_store_count))
9983 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9984
f3380ca5
WL		 9985 vmx_load_vmcs01(vcpu);
9986
77b0f5d6
BD		 9987 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9988 && nested_exit_intr_ack_set(vcpu)) {
9989 int irq = kvm_cpu_get_interrupt(vcpu);
9990 WARN_ON(irq < 0);
9991 vmcs12->vm_exit_intr_info = irq |
9992 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9993 }
9994
542060ea
JK		 9995 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9996 vmcs12->exit_qualification,
9997 vmcs12->idt_vectoring_info_field,
9998 vmcs12->vm_exit_intr_info,
9999 vmcs12->vm_exit_intr_error_code,
10000 KVM_ISA_VMX);
4704d0be 10001
2961e876
GN		 10002 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10003 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10004 vmx_segment_cache_clear(vmx);
10005
4704d0be
NHE		 10006 /* if no vmcs02 cache requested, remove the one we used */
10007 if (VMCS02_POOL_SIZE == 0)
10008 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10009
10010 load_vmcs12_host_state(vcpu, vmcs12);
10011
27fc51b2 10012 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10013 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10014
10015 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10016 vmx->host_rsp = 0;
10017
10018 /* Unpin physical memory we referred to in vmcs02 */
10019 if (vmx->nested.apic_access_page) {
10020 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10021 vmx->nested.apic_access_page = NULL;
4704d0be 10022 }
a7c0b07d
WL		 10023 if (vmx->nested.virtual_apic_page) {
10024 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10025 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10026 }
705699a1
WV		 10027 if (vmx->nested.pi_desc_page) {
10028 kunmap(vmx->nested.pi_desc_page);
10029 nested_release_page(vmx->nested.pi_desc_page);
10030 vmx->nested.pi_desc_page = NULL;
10031 vmx->nested.pi_desc = NULL;
10032 }
4704d0be 10033
38b99173
TC		 10034 /*
10035 * We are now running in L2, mmu_notifier will force to reload the
10036 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10037 */
10038 kvm_vcpu_reload_apic_access_page(vcpu);
10039
4704d0be
NHE		 10040 /*
10041 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10042 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10043 * success or failure flag accordingly.
10044 */
10045 if (unlikely(vmx->fail)) {
10046 vmx->fail = 0;
10047 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10048 } else
10049 nested_vmx_succeed(vcpu);
012f83cb
AG		 10050 if (enable_shadow_vmcs)
10051 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10052
10053 /* in case we halted in L2 */
10054 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10055}
10056
42124925
JK		 10057/*
10058 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10059 */
10060static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10061{
10062 if (is_guest_mode(vcpu))
533558bc 10063 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10064 free_nested(to_vmx(vcpu));
10065}
10066
7c177938
NHE		 10067/*
10068 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10069 * 23.7 "VM-entry failures during or after loading guest state" (this also
10070 * lists the acceptable exit-reason and exit-qualification parameters).
10071 * It should only be called before L2 actually succeeded to run, and when
10072 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10073 */
10074static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10075 struct vmcs12 *vmcs12,
10076 u32 reason, unsigned long qualification)
10077{
10078 load_vmcs12_host_state(vcpu, vmcs12);
10079 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10080 vmcs12->exit_qualification = qualification;
10081 nested_vmx_succeed(vcpu);
012f83cb
AG		 10082 if (enable_shadow_vmcs)
10083 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10084}
10085
8a76d7f2
JR		 10086static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10087 struct x86_instruction_info *info,
10088 enum x86_intercept_stage stage)
10089{
10090 return X86EMUL_CONTINUE;
10091}
10092
48d89b92 10093static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10094{
b4a2d31d
RK		 10095 if (ple_gap)
10096 shrink_ple_window(vcpu);
ae97a3b8
RK		 10097}
10098
843e4330
KH		 10099static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10100 struct kvm_memory_slot *slot)
10101{
10102 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10103 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10104}
10105
10106static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10107 struct kvm_memory_slot *slot)
10108{
10109 kvm_mmu_slot_set_dirty(kvm, slot);
10110}
10111
10112static void vmx_flush_log_dirty(struct kvm *kvm)
10113{
10114 kvm_flush_pml_buffers(kvm);
10115}
10116
10117static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10118 struct kvm_memory_slot *memslot,
10119 gfn_t offset, unsigned long mask)
10120{
10121 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10122}
10123
cbdd1bea 10124static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10125 .cpu_has_kvm_support = cpu_has_kvm_support,
10126 .disabled_by_bios = vmx_disabled_by_bios,
10127 .hardware_setup = hardware_setup,
10128 .hardware_unsetup = hardware_unsetup,
002c7f7c 10129 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10130 .hardware_enable = hardware_enable,
10131 .hardware_disable = hardware_disable,
04547156 10132 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 10133
10134 .vcpu_create = vmx_create_vcpu,
10135 .vcpu_free = vmx_free_vcpu,
04d2cc77 10136 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10137
04d2cc77 10138 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10139 .vcpu_load = vmx_vcpu_load,
10140 .vcpu_put = vmx_vcpu_put,
10141
c8639010 10142 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10143 .get_msr = vmx_get_msr,
10144 .set_msr = vmx_set_msr,
10145 .get_segment_base = vmx_get_segment_base,
10146 .get_segment = vmx_get_segment,
10147 .set_segment = vmx_set_segment,
2e4d2653 10148 .get_cpl = vmx_get_cpl,
6aa8b732 10149 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10150 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10151 .decache_cr3 = vmx_decache_cr3,
25c4c276 10152 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10153 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10154 .set_cr3 = vmx_set_cr3,
10155 .set_cr4 = vmx_set_cr4,
6aa8b732 10156 .set_efer = vmx_set_efer,
6aa8b732
AK		 10157 .get_idt = vmx_get_idt,
10158 .set_idt = vmx_set_idt,
10159 .get_gdt = vmx_get_gdt,
10160 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10161 .get_dr6 = vmx_get_dr6,
10162 .set_dr6 = vmx_set_dr6,
020df079 10163 .set_dr7 = vmx_set_dr7,
81908bf4 10164 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10165 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10166 .get_rflags = vmx_get_rflags,
10167 .set_rflags = vmx_set_rflags,
02daab21 10168 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10169
10170 .tlb_flush = vmx_flush_tlb,
6aa8b732 10171
6aa8b732 10172 .run = vmx_vcpu_run,
6062d012 10173 .handle_exit = vmx_handle_exit,
6aa8b732 10174 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10175 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10176 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10177 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10178 .set_irq = vmx_inject_irq,
95ba8273 10179 .set_nmi = vmx_inject_nmi,
298101da 10180 .queue_exception = vmx_queue_exception,
b463a6f7 10181 .cancel_injection = vmx_cancel_injection,
78646121 10182 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10183 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10184 .get_nmi_mask = vmx_get_nmi_mask,
10185 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10186 .enable_nmi_window = enable_nmi_window,
10187 .enable_irq_window = enable_irq_window,
10188 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10189 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10190 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 10191 .vm_has_apicv = vmx_vm_has_apicv,
10192 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10193 .hwapic_irr_update = vmx_hwapic_irr_update,
10194 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10195 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10196 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10197
cbc94022 10198 .set_tss_addr = vmx_set_tss_addr,
67253af5 10199 .get_tdp_level = get_ept_level,
4b12f0de 10200 .get_mt_mask = vmx_get_mt_mask,
229456fc 10201
586f9607 10202 .get_exit_info = vmx_get_exit_info,
586f9607 10203
17cc3935 10204 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10205
10206 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10207
10208 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10209 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10210
10211 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10212
10213 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10214
4051b188 10215 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10216 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10217 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10218 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10219 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10220 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10221
10222 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10223
10224 .check_intercept = vmx_check_intercept,
a547c6db 10225 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10226 .mpx_supported = vmx_mpx_supported,
55412b2e 10227 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10228
10229 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10230
10231 .sched_in = vmx_sched_in,
843e4330
KH		 10232
10233 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10234 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10235 .flush_log_dirty = vmx_flush_log_dirty,
10236 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 10237};
10238
10239static int __init vmx_init(void)
10240{
34a1cd60
TC		 10241 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10242 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10243 if (r)
34a1cd60 10244 return r;
25c5f225 10245
8f536b76
ZY		 10246#ifdef CONFIG_KEXEC
10247 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10248 crash_vmclear_local_loaded_vmcss);
10249#endif
10250
fdef3ad1 10251 return 0;
6aa8b732
AK		 10252}
10253
10254static void __exit vmx_exit(void)
10255{
8f536b76 10256#ifdef CONFIG_KEXEC
3b63a43f 10257 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10258 synchronize_rcu();
10259#endif
10260
cb498ea2 10261 kvm_exit();
6aa8b732
AK		 10262}
10263
10264module_init(vmx_init)
10265module_exit(vmx_exit)
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