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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
dab2087d 48#include <asm/apic.h>
6aa8b732 49
229456fc
MT		 50#include "trace.h"
51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6
SY		 534
535 bool rdtscp_enabled;
ec378aee 536
01e439be
YZ		 537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
539
ec378aee
NHE		 540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
a7653ecd
RK		 542
543 /* Dynamic PLE window. */
544 int ple_window;
545 bool ple_window_dirty;
843e4330
KH		 546
547 /* Support for PML */
548#define PML_ENTITY_NUM 512
549 struct page *pml_pg;
a2fa3e9f
GH		 550};
551
2fb92db1
AK		 552enum segment_cache_field {
553 SEG_FIELD_SEL = 0,
554 SEG_FIELD_BASE = 1,
555 SEG_FIELD_LIMIT = 2,
556 SEG_FIELD_AR = 3,
557
558 SEG_FIELD_NR = 4
559};
560
a2fa3e9f
GH		 561static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562{
fb3f0f51 563 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 564}
565
22bd0358
NHE		 566#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
4607c2d7 571
fe2b201b 572static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 573 /*
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
584 */
585 VM_EXIT_REASON,
586 VM_EXIT_INTR_INFO,
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
591 EXIT_QUALIFICATION,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
594};
fe2b201b 595static int max_shadow_read_only_fields =
4607c2d7
AG		 596 ARRAY_SIZE(shadow_read_only_fields);
597
fe2b201b 598static unsigned long shadow_read_write_fields[] = {
a7c0b07d 599 TPR_THRESHOLD,
4607c2d7
AG		 600 GUEST_RIP,
601 GUEST_RSP,
602 GUEST_CR0,
603 GUEST_CR3,
604 GUEST_CR4,
605 GUEST_INTERRUPTIBILITY_INFO,
606 GUEST_RFLAGS,
607 GUEST_CS_SELECTOR,
608 GUEST_CS_AR_BYTES,
609 GUEST_CS_LIMIT,
610 GUEST_CS_BASE,
611 GUEST_ES_BASE,
36be0b9d 612 GUEST_BNDCFGS,
4607c2d7
AG		 613 CR0_GUEST_HOST_MASK,
614 CR0_READ_SHADOW,
615 CR4_READ_SHADOW,
616 TSC_OFFSET,
617 EXCEPTION_BITMAP,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
623 HOST_FS_BASE,
624 HOST_GS_BASE,
625 HOST_FS_SELECTOR,
626 HOST_GS_SELECTOR
627};
fe2b201b 628static int max_shadow_read_write_fields =
4607c2d7
AG		 629 ARRAY_SIZE(shadow_read_write_fields);
630
772e0318 631static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 633 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 660 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
769};
22bd0358
NHE		 770
771static inline short vmcs_field_to_offset(unsigned long field)
772{
a2ae9df7
PB		 773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
777 return -ENOENT;
778
22bd0358
NHE		 779 return vmcs_field_to_offset_table[field];
780}
781
a9d30f33
NHE		 782static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783{
784 return to_vmx(vcpu)->nested.current_vmcs12;
785}
786
787static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788{
789 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 790 if (is_error_page(page))
a9d30f33 791 return NULL;
32cad84f 792
a9d30f33
NHE		 793 return page;
794}
795
796static void nested_release_page(struct page *page)
797{
798 kvm_release_page_dirty(page);
799}
800
801static void nested_release_page_clean(struct page *page)
802{
803 kvm_release_page_clean(page);
804}
805
bfd0a56b 806static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 807static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 808static void kvm_cpu_vmxon(u64 addr);
809static void kvm_cpu_vmxoff(void);
93c4adc7 810static bool vmx_mpx_supported(void);
f53cd63c 811static bool vmx_xsaves_supported(void);
705699a1 812static int vmx_vm_has_apicv(struct kvm *kvm);
776e58ea 813static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 814static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
d99e4152
GN		 818static bool guest_state_valid(struct kvm_vcpu *vcpu);
819static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 820static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 821static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 822static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 823static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 824
6aa8b732
AK		 825static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 827/*
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 */
831static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 832static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 833
3e7c73e9
AK		 834static unsigned long *vmx_io_bitmap_a;
835static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 836static unsigned long *vmx_msr_bitmap_legacy;
837static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 838static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 840static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 841static unsigned long *vmx_vmread_bitmap;
842static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 843
110312c8 844static bool cpu_has_load_ia32_efer;
8bf00a52 845static bool cpu_has_load_perf_global_ctrl;
110312c8 846
2384d2b3
SY		 847static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848static DEFINE_SPINLOCK(vmx_vpid_lock);
849
1c3d14fe 850static struct vmcs_config {
6aa8b732
AK		 851 int size;
852 int order;
853 u32 revision_id;
1c3d14fe
YS		 854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
f78e0e2e 856 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 857 u32 vmexit_ctrl;
858 u32 vmentry_ctrl;
859} vmcs_config;
6aa8b732 860
efff9e53 861static struct vmx_capability {
d56f546d
SY		 862 u32 ept;
863 u32 vpid;
864} vmx_capability;
865
6aa8b732
AK		 866#define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
872 }
873
772e0318 874static const struct kvm_vmx_segment_field {
6aa8b732
AK		 875 unsigned selector;
876 unsigned base;
877 unsigned limit;
878 unsigned ar_bytes;
879} kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
888};
889
26bb0981
AK		 890static u64 host_efer;
891
6de4f3ad
AK		 892static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
4d56c8a7 894/*
8c06585d 895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 896 * away by decrementing the array size.
897 */
6aa8b732 898static const u32 vmx_msr_index[] = {
05b3e0c2 899#ifdef CONFIG_X86_64
44ea2b17 900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 901#endif
8c06585d 902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 903};
6aa8b732 904
31299944 905static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 910}
911
31299944 912static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 917}
918
31299944 919static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 924}
925
31299944 926static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930}
931
31299944 932static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 933{
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937}
938
31299944 939static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 940{
04547156 941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 942}
943
31299944 944static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 945{
04547156 946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 947}
948
31299944 949static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 950{
04547156 951 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 952}
953
31299944 954static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 955{
04547156
SY		 956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 958}
959
774ead3a 960static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 961{
04547156
SY		 962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964}
965
8d14695f
YZ		 966static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967{
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970}
971
83d4c286
YZ		 972static inline bool cpu_has_vmx_apic_register_virt(void)
973{
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976}
977
c7c9c56c
YZ		 978static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982}
983
01e439be
YZ		 984static inline bool cpu_has_vmx_posted_intr(void)
985{
986 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
987}
988
989static inline bool cpu_has_vmx_apicv(void)
990{
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
994}
995
04547156
SY		 996static inline bool cpu_has_vmx_flexpriority(void)
997{
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1000}
1001
e799794e
MT		 1002static inline bool cpu_has_vmx_ept_execute_only(void)
1003{
31299944 1004 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1005}
1006
e799794e
MT		 1007static inline bool cpu_has_vmx_ept_2m_page(void)
1008{
31299944 1009 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1010}
1011
878403b7
SY		 1012static inline bool cpu_has_vmx_ept_1g_page(void)
1013{
31299944 1014 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1015}
1016
4bc9b982
SY		 1017static inline bool cpu_has_vmx_ept_4levels(void)
1018{
1019 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020}
1021
83c3a331
XH		 1022static inline bool cpu_has_vmx_ept_ad_bits(void)
1023{
1024 return vmx_capability.ept & VMX_EPT_AD_BIT;
1025}
1026
31299944 1027static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1028{
31299944 1029 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1033{
31299944 1034 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1035}
1036
518c8aee
GJ		 1037static inline bool cpu_has_vmx_invvpid_single(void)
1038{
1039 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040}
1041
b9d762fa
GJ		 1042static inline bool cpu_has_vmx_invvpid_global(void)
1043{
1044 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045}
1046
31299944 1047static inline bool cpu_has_vmx_ept(void)
d56f546d 1048{
04547156
SY		 1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1051}
1052
31299944 1053static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057}
1058
31299944 1059static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1060{
1061 return vmcs_config.cpu_based_2nd_exec_ctrl &
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063}
1064
31299944 1065static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1066{
6d3e435e 1067 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1068}
1069
31299944 1070static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1071{
04547156
SY		 1072 return vmcs_config.cpu_based_2nd_exec_ctrl &
1073 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1074}
1075
31299944 1076static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1077{
1078 return vmcs_config.cpu_based_2nd_exec_ctrl &
1079 SECONDARY_EXEC_RDTSCP;
1080}
1081
ad756a16
MJ		 1082static inline bool cpu_has_vmx_invpcid(void)
1083{
1084 return vmcs_config.cpu_based_2nd_exec_ctrl &
1085 SECONDARY_EXEC_ENABLE_INVPCID;
1086}
1087
31299944 1088static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1089{
1090 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f5f48ee1
SY		 1093static inline bool cpu_has_vmx_wbinvd_exit(void)
1094{
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_WBINVD_EXITING;
1097}
1098
abc4fc58
AG		 1099static inline bool cpu_has_vmx_shadow_vmcs(void)
1100{
1101 u64 vmx_msr;
1102 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105 return false;
1106
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_SHADOW_VMCS;
1109}
1110
843e4330
KH		 1111static inline bool cpu_has_vmx_pml(void)
1112{
1113 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114}
1115
04547156
SY		 1116static inline bool report_flexpriority(void)
1117{
1118 return flexpriority_enabled;
1119}
1120
fe3ef05c
NHE		 1121static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122{
1123 return vmcs12->cpu_based_vm_exec_control & bit;
1124}
1125
1126static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127{
1128 return (vmcs12->cpu_based_vm_exec_control &
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130 (vmcs12->secondary_vm_exec_control & bit);
1131}
1132
f5c4368f 1133static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1134{
1135 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136}
1137
f4124500
JK		 1138static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139{
1140 return vmcs12->pin_based_vm_exec_control &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1142}
1143
155a97a3
NHE		 1144static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145{
1146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147}
1148
81dc01f7
WL		 1149static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150{
1151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152 vmx_xsaves_supported();
1153}
1154
f2b93280
WV		 1155static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156{
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158}
1159
82f0dd4b
WV		 1160static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161{
1162 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163}
1164
608406e2
WV		 1165static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166{
1167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168}
1169
705699a1
WV		 1170static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171{
1172 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173}
1174
644d711a
NHE		 1175static inline bool is_exception(u32 intr_info)
1176{
1177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179}
1180
533558bc
JK		 1181static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182 u32 exit_intr_info,
1183 unsigned long exit_qualification);
7c177938
NHE		 1184static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185 struct vmcs12 *vmcs12,
1186 u32 reason, unsigned long qualification);
1187
8b9cf98c 1188static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1189{
1190 int i;
1191
a2fa3e9f 1192 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1194 return i;
1195 return -1;
1196}
1197
2384d2b3
SY		 1198static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199{
1200 struct {
1201 u64 vpid : 16;
1202 u64 rsvd : 48;
1203 u64 gva;
1204 } operand = { vpid, 0, gva };
1205
4ecac3fd 1206 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand), "c"(ext) : "cc", "memory");
1210}
1211
1439442c
SY		 1212static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213{
1214 struct {
1215 u64 eptp, gpa;
1216 } operand = {eptp, gpa};
1217
4ecac3fd 1218 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand), "c" (ext) : "cc", "memory");
1222}
1223
26bb0981 1224static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1225{
1226 int i;
1227
8b9cf98c 1228 i = __find_msr_index(vmx, msr);
a75beee6 1229 if (i >= 0)
a2fa3e9f 1230 return &vmx->guest_msrs[i];
8b6d44c7 1231 return NULL;
7725f0ba
AK		 1232}
1233
6aa8b732
AK		 1234static void vmcs_clear(struct vmcs *vmcs)
1235{
1236 u64 phys_addr = __pa(vmcs);
1237 u8 error;
1238
4ecac3fd 1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1240 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1241 : "cc", "memory");
1242 if (error)
1243 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244 vmcs, phys_addr);
1245}
1246
d462b819
NHE		 1247static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248{
1249 vmcs_clear(loaded_vmcs->vmcs);
1250 loaded_vmcs->cpu = -1;
1251 loaded_vmcs->launched = 0;
1252}
1253
7725b894
DX		 1254static void vmcs_load(struct vmcs *vmcs)
1255{
1256 u64 phys_addr = __pa(vmcs);
1257 u8 error;
1258
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1260 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1261 : "cc", "memory");
1262 if (error)
2844d849 1263 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1264 vmcs, phys_addr);
1265}
1266
8f536b76
ZY		 1267#ifdef CONFIG_KEXEC
1268/*
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1271 * default.
1272 */
1273static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275static inline void crash_enable_local_vmclear(int cpu)
1276{
1277 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278}
1279
1280static inline void crash_disable_local_vmclear(int cpu)
1281{
1282 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283}
1284
1285static inline int crash_local_vmclear_enabled(int cpu)
1286{
1287 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288}
1289
1290static void crash_vmclear_local_loaded_vmcss(void)
1291{
1292 int cpu = raw_smp_processor_id();
1293 struct loaded_vmcs *v;
1294
1295 if (!crash_local_vmclear_enabled(cpu))
1296 return;
1297
1298 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299 loaded_vmcss_on_cpu_link)
1300 vmcs_clear(v->vmcs);
1301}
1302#else
1303static inline void crash_enable_local_vmclear(int cpu) { }
1304static inline void crash_disable_local_vmclear(int cpu) { }
1305#endif /* CONFIG_KEXEC */
1306
d462b819 1307static void __loaded_vmcs_clear(void *arg)
6aa8b732 1308{
d462b819 1309 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1310 int cpu = raw_smp_processor_id();
6aa8b732 1311
d462b819
NHE		 1312 if (loaded_vmcs->cpu != cpu)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1315 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1316 crash_disable_local_vmclear(cpu);
d462b819 1317 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1318
1319 /*
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1324 */
1325 smp_wmb();
1326
d462b819 1327 loaded_vmcs_init(loaded_vmcs);
8f536b76 1328 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1329}
1330
d462b819 1331static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1332{
e6c7d321
XG		 1333 int cpu = loaded_vmcs->cpu;
1334
1335 if (cpu != -1)
1336 smp_call_function_single(cpu,
1337 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1338}
1339
1760dd49 1340static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1341{
1342 if (vmx->vpid == 0)
1343 return;
1344
518c8aee
GJ		 1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1347}
1348
b9d762fa
GJ		 1349static inline void vpid_sync_vcpu_global(void)
1350{
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353}
1354
1355static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356{
1357 if (cpu_has_vmx_invvpid_single())
1760dd49 1358 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1359 else
1360 vpid_sync_vcpu_global();
1361}
1362
1439442c
SY		 1363static inline void ept_sync_global(void)
1364{
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367}
1368
1369static inline void ept_sync_context(u64 eptp)
1370{
089d034e 1371 if (enable_ept) {
1439442c
SY		 1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374 else
1375 ept_sync_global();
1376 }
1377}
1378
96304217 1379static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1380{
5e520e62 1381 unsigned long value;
6aa8b732 1382
5e520e62
AK		 1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1385 return value;
1386}
1387
96304217 1388static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1389{
1390 return vmcs_readl(field);
1391}
1392
96304217 1393static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1394{
1395 return vmcs_readl(field);
1396}
1397
96304217 1398static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1399{
05b3e0c2 1400#ifdef CONFIG_X86_64
6aa8b732
AK		 1401 return vmcs_readl(field);
1402#else
1403 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404#endif
1405}
1406
e52de1b8
AK		 1407static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408{
1409 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411 dump_stack();
1412}
1413
6aa8b732
AK		 1414static void vmcs_writel(unsigned long field, unsigned long value)
1415{
1416 u8 error;
1417
4ecac3fd 1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1419 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1420 if (unlikely(error))
1421 vmwrite_error(field, value);
6aa8b732
AK		 1422}
1423
1424static void vmcs_write16(unsigned long field, u16 value)
1425{
1426 vmcs_writel(field, value);
1427}
1428
1429static void vmcs_write32(unsigned long field, u32 value)
1430{
1431 vmcs_writel(field, value);
1432}
1433
1434static void vmcs_write64(unsigned long field, u64 value)
1435{
6aa8b732 1436 vmcs_writel(field, value);
7682f2d0 1437#ifndef CONFIG_X86_64
6aa8b732
AK		 1438 asm volatile ("");
1439 vmcs_writel(field+1, value >> 32);
1440#endif
1441}
1442
2ab455cc
AL		 1443static void vmcs_clear_bits(unsigned long field, u32 mask)
1444{
1445 vmcs_writel(field, vmcs_readl(field) & ~mask);
1446}
1447
1448static void vmcs_set_bits(unsigned long field, u32 mask)
1449{
1450 vmcs_writel(field, vmcs_readl(field) | mask);
1451}
1452
2961e876
GN		 1453static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454{
1455 vmcs_write32(VM_ENTRY_CONTROLS, val);
1456 vmx->vm_entry_controls_shadow = val;
1457}
1458
1459static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460{
1461 if (vmx->vm_entry_controls_shadow != val)
1462 vm_entry_controls_init(vmx, val);
1463}
1464
1465static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466{
1467 return vmx->vm_entry_controls_shadow;
1468}
1469
1470
1471static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472{
1473 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474}
1475
1476static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477{
1478 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479}
1480
1481static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482{
1483 vmcs_write32(VM_EXIT_CONTROLS, val);
1484 vmx->vm_exit_controls_shadow = val;
1485}
1486
1487static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488{
1489 if (vmx->vm_exit_controls_shadow != val)
1490 vm_exit_controls_init(vmx, val);
1491}
1492
1493static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494{
1495 return vmx->vm_exit_controls_shadow;
1496}
1497
1498
1499static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500{
1501 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502}
1503
1504static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505{
1506 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507}
1508
2fb92db1
AK		 1509static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510{
1511 vmx->segment_cache.bitmask = 0;
1512}
1513
1514static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515 unsigned field)
1516{
1517 bool ret;
1518 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522 vmx->segment_cache.bitmask = 0;
1523 }
1524 ret = vmx->segment_cache.bitmask & mask;
1525 vmx->segment_cache.bitmask |= mask;
1526 return ret;
1527}
1528
1529static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530{
1531 u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535 return *p;
1536}
1537
1538static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539{
1540 ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544 return *p;
1545}
1546
1547static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548{
1549 u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553 return *p;
1554}
1555
1556static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557{
1558 u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562 return *p;
1563}
1564
abd3f2d6
AK		 1565static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566{
1567 u32 eb;
1568
fd7373cc
JK		 1569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571 if ((vcpu->guest_debug &
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574 eb |= 1u << BP_VECTOR;
7ffd92c5 1575 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1576 eb = ~0;
089d034e 1577 if (enable_ept)
1439442c 1578 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1579 if (vcpu->fpu_active)
1580 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1581
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1586 */
1587 if (is_guest_mode(vcpu))
1588 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
abd3f2d6
AK		 1590 vmcs_write32(EXCEPTION_BITMAP, eb);
1591}
1592
2961e876
GN		 1593static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594 unsigned long entry, unsigned long exit)
8bf00a52 1595{
2961e876
GN		 1596 vm_entry_controls_clearbit(vmx, entry);
1597 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1598}
1599
61d2ef2c
AK		 1600static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601{
1602 unsigned i;
1603 struct msr_autoload *m = &vmx->msr_autoload;
1604
8bf00a52
GN		 1605 switch (msr) {
1606 case MSR_EFER:
1607 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1608 clear_atomic_switch_msr_special(vmx,
1609 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1610 VM_EXIT_LOAD_IA32_EFER);
1611 return;
1612 }
1613 break;
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
2961e876 1616 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619 return;
1620 }
1621 break;
110312c8
AK		 1622 }
1623
61d2ef2c
AK		 1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1626 break;
1627
1628 if (i == m->nr)
1629 return;
1630 --m->nr;
1631 m->guest[i] = m->guest[m->nr];
1632 m->host[i] = m->host[m->nr];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635}
1636
2961e876
GN		 1637static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638 unsigned long entry, unsigned long exit,
1639 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640 u64 guest_val, u64 host_val)
8bf00a52
GN		 1641{
1642 vmcs_write64(guest_val_vmcs, guest_val);
1643 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1644 vm_entry_controls_setbit(vmx, entry);
1645 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1646}
1647
61d2ef2c
AK		 1648static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649 u64 guest_val, u64 host_val)
1650{
1651 unsigned i;
1652 struct msr_autoload *m = &vmx->msr_autoload;
1653
8bf00a52
GN		 1654 switch (msr) {
1655 case MSR_EFER:
1656 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1657 add_atomic_switch_msr_special(vmx,
1658 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1659 VM_EXIT_LOAD_IA32_EFER,
1660 GUEST_IA32_EFER,
1661 HOST_IA32_EFER,
1662 guest_val, host_val);
1663 return;
1664 }
1665 break;
1666 case MSR_CORE_PERF_GLOBAL_CTRL:
1667 if (cpu_has_load_perf_global_ctrl) {
2961e876 1668 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 GUEST_IA32_PERF_GLOBAL_CTRL,
1672 HOST_IA32_PERF_GLOBAL_CTRL,
1673 guest_val, host_val);
1674 return;
1675 }
1676 break;
110312c8
AK		 1677 }
1678
61d2ef2c
AK		 1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1681 break;
1682
e7fc6f93 1683 if (i == NR_AUTOLOAD_MSRS) {
60266204 1684 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1685 "Can't add msr %x\n", msr);
1686 return;
1687 } else if (i == m->nr) {
61d2ef2c
AK		 1688 ++m->nr;
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691 }
1692
1693 m->guest[i].index = msr;
1694 m->guest[i].value = guest_val;
1695 m->host[i].index = msr;
1696 m->host[i].value = host_val;
1697}
1698
33ed6329
AK		 1699static void reload_tss(void)
1700{
33ed6329
AK		 1701 /*
1702 * VT restores TR but not its size. Useless.
1703 */
89cbc767 1704 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1705 struct desc_struct *descs;
33ed6329 1706
d359192f 1707 descs = (void *)gdt->address;
33ed6329
AK		 1708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709 load_TR_desc();
33ed6329
AK		 1710}
1711
92c0d900 1712static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1713{
3a34a881 1714 u64 guest_efer;
51c6cf66
AK		 1715 u64 ignore_bits;
1716
f6801dff 1717 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1718
51c6cf66 1719 /*
0fa06071 1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1721 * outside long mode
1722 */
1723 ignore_bits = EFER_NX | EFER_SCE;
1724#ifdef CONFIG_X86_64
1725 ignore_bits |= EFER_LMA | EFER_LME;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer & EFER_LMA)
1728 ignore_bits &= ~(u64)EFER_SCE;
1729#endif
51c6cf66
AK		 1730 guest_efer &= ~ignore_bits;
1731 guest_efer |= host_efer & ignore_bits;
26bb0981 1732 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1734
1735 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1736
1737 /*
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1741 */
1742 if (cpu_has_load_ia32_efer ||
1743 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1744 guest_efer = vmx->vcpu.arch.efer;
1745 if (!(guest_efer & EFER_LMA))
1746 guest_efer &= ~EFER_LME;
54b98bff
AL		 1747 if (guest_efer != host_efer)
1748 add_atomic_switch_msr(vmx, MSR_EFER,
1749 guest_efer, host_efer);
84ad33ef
AK		 1750 return false;
1751 }
1752
26bb0981 1753 return true;
51c6cf66
AK		 1754}
1755
2d49ec72
GN		 1756static unsigned long segment_base(u16 selector)
1757{
89cbc767 1758 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1759 struct desc_struct *d;
1760 unsigned long table_base;
1761 unsigned long v;
1762
1763 if (!(selector & ~3))
1764 return 0;
1765
d359192f 1766 table_base = gdt->address;
2d49ec72
GN		 1767
1768 if (selector & 4) { /* from ldt */
1769 u16 ldt_selector = kvm_read_ldt();
1770
1771 if (!(ldt_selector & ~3))
1772 return 0;
1773
1774 table_base = segment_base(ldt_selector);
1775 }
1776 d = (struct desc_struct *)(table_base + (selector & ~7));
1777 v = get_desc_base(d);
1778#ifdef CONFIG_X86_64
1779 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781#endif
1782 return v;
1783}
1784
1785static inline unsigned long kvm_read_tr_base(void)
1786{
1787 u16 tr;
1788 asm("str %0" : "=g"(tr));
1789 return segment_base(tr);
1790}
1791
04d2cc77 1792static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1793{
04d2cc77 1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1795 int i;
04d2cc77 1796
a2fa3e9f 1797 if (vmx->host_state.loaded)
33ed6329
AK		 1798 return;
1799
a2fa3e9f 1800 vmx->host_state.loaded = 1;
33ed6329
AK		 1801 /*
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1804 */
d6e88aec 1805 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1806 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1807 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1808 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1809 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1810 vmx->host_state.fs_reload_needed = 0;
1811 } else {
33ed6329 1812 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1813 vmx->host_state.fs_reload_needed = 1;
33ed6329 1814 }
9581d442 1815 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1816 if (!(vmx->host_state.gs_sel & 7))
1817 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1818 else {
1819 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1820 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1821 }
1822
b2da15ac
AK		 1823#ifdef CONFIG_X86_64
1824 savesegment(ds, vmx->host_state.ds_sel);
1825 savesegment(es, vmx->host_state.es_sel);
1826#endif
1827
33ed6329
AK		 1828#ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831#else
a2fa3e9f
GH		 1832 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1834#endif
707c0874
AK		 1835
1836#ifdef CONFIG_X86_64
c8770e7b
AK		 1837 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838 if (is_long_mode(&vmx->vcpu))
44ea2b17 1839 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1840#endif
da8999d3
LJ		 1841 if (boot_cpu_has(X86_FEATURE_MPX))
1842 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1843 for (i = 0; i < vmx->save_nmsrs; ++i)
1844 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1845 vmx->guest_msrs[i].data,
1846 vmx->guest_msrs[i].mask);
33ed6329
AK		 1847}
1848
a9b21b62 1849static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1850{
a2fa3e9f 1851 if (!vmx->host_state.loaded)
33ed6329
AK		 1852 return;
1853
e1beb1d3 1854 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1855 vmx->host_state.loaded = 0;
c8770e7b
AK		 1856#ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx->vcpu))
1858 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859#endif
152d3f2f 1860 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1861 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1862#ifdef CONFIG_X86_64
9581d442 1863 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1864#else
1865 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1866#endif
33ed6329 1867 }
0a77fe4c
AK		 1868 if (vmx->host_state.fs_reload_needed)
1869 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1870#ifdef CONFIG_X86_64
1871 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872 loadsegment(ds, vmx->host_state.ds_sel);
1873 loadsegment(es, vmx->host_state.es_sel);
1874 }
b2da15ac 1875#endif
152d3f2f 1876 reload_tss();
44ea2b17 1877#ifdef CONFIG_X86_64
c8770e7b 1878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1879#endif
da8999d3
LJ		 1880 if (vmx->host_state.msr_host_bndcfgs)
1881 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1882 /*
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1885 */
1886 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887 stts();
89cbc767 1888 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1889}
1890
a9b21b62
AK		 1891static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892{
1893 preempt_disable();
1894 __vmx_load_host_state(vmx);
1895 preempt_enable();
1896}
1897
6aa8b732
AK		 1898/*
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1901 */
15ad7146 1902static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1903{
a2fa3e9f 1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1905 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1906
4610c9cc
DX		 1907 if (!vmm_exclusive)
1908 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1909 else if (vmx->loaded_vmcs->cpu != cpu)
1910 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1911
d462b819
NHE		 1912 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1915 }
1916
d462b819 1917 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1918 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1919 unsigned long sysenter_esp;
1920
a8eeb04a 1921 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1922 local_irq_disable();
8f536b76 1923 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1924
1925 /*
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1929 */
1930 smp_rmb();
1931
d462b819
NHE		 1932 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1934 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1935 local_irq_enable();
1936
6aa8b732
AK		 1937 /*
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1939 * processors.
1940 */
d6e88aec 1941 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1942 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1943
1944 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1946 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1947 }
6aa8b732
AK		 1948}
1949
1950static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951{
a9b21b62 1952 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1953 if (!vmm_exclusive) {
d462b819
NHE		 1954 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955 vcpu->cpu = -1;
4610c9cc
DX		 1956 kvm_cpu_vmxoff();
1957 }
6aa8b732
AK		 1958}
1959
5fd86fcf
AK		 1960static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961{
81231c69
AK		 1962 ulong cr0;
1963
5fd86fcf
AK		 1964 if (vcpu->fpu_active)
1965 return;
1966 vcpu->fpu_active = 1;
81231c69
AK		 1967 cr0 = vmcs_readl(GUEST_CR0);
1968 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1971 update_exception_bitmap(vcpu);
edcafe3c 1972 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1973 if (is_guest_mode(vcpu))
1974 vcpu->arch.cr0_guest_owned_bits &=
1975 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1977}
1978
edcafe3c
AK		 1979static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
fe3ef05c
NHE		 1981/*
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1985 */
1986static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987{
1988 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990}
1991static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992{
1993 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995}
1996
5fd86fcf
AK		 1997static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998{
36cf24e0
NHE		 1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2001 */
edcafe3c 2002 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2003 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2004 update_exception_bitmap(vcpu);
edcafe3c
AK		 2005 vcpu->arch.cr0_guest_owned_bits = 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2007 if (is_guest_mode(vcpu)) {
2008 /*
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2015 */
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018 (vcpu->arch.cr0 & X86_CR0_TS);
2019 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020 } else
2021 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2022}
2023
6aa8b732
AK		 2024static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025{
78ac8b47 2026 unsigned long rflags, save_rflags;
345dcaa8 2027
6de12732
AK		 2028 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030 rflags = vmcs_readl(GUEST_RFLAGS);
2031 if (to_vmx(vcpu)->rmode.vm86_active) {
2032 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035 }
2036 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2037 }
6de12732 2038 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2039}
2040
2041static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042{
6de12732
AK		 2043 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2045 if (to_vmx(vcpu)->rmode.vm86_active) {
2046 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2047 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2048 }
6aa8b732
AK		 2049 vmcs_writel(GUEST_RFLAGS, rflags);
2050}
2051
37ccdcbe 2052static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2053{
2054 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055 int ret = 0;
2056
2057 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2058 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2059 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2060 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2061
37ccdcbe 2062 return ret;
2809f5d2
GC		 2063}
2064
2065static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066{
2067 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068 u32 interruptibility = interruptibility_old;
2069
2070 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
48005f64 2072 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2073 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2074 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2075 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077 if ((interruptibility != interruptibility_old))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079}
2080
6aa8b732
AK		 2081static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082{
2083 unsigned long rip;
6aa8b732 2084
5fdbf976 2085 rip = kvm_rip_read(vcpu);
6aa8b732 2086 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2087 kvm_rip_write(vcpu, rip);
6aa8b732 2088
2809f5d2
GC		 2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2091}
2092
0b6ac343
NHE		 2093/*
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2096 */
e011c663 2097static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2098{
2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
e011c663 2101 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2102 return 0;
2103
533558bc
JK		 2104 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105 vmcs_read32(VM_EXIT_INTR_INFO),
2106 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2107 return 1;
2108}
2109
298101da 2110static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2111 bool has_error_code, u32 error_code,
2112 bool reinject)
298101da 2113{
77ab6db0 2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2115 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2116
e011c663
GN		 2117 if (!reinject && is_guest_mode(vcpu) &&
2118 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2119 return;
2120
8ab2d2e2 2121 if (has_error_code) {
77ab6db0 2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2123 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124 }
77ab6db0 2125
7ffd92c5 2126 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2127 int inc_eip = 0;
2128 if (kvm_exception_is_soft(nr))
2129 inc_eip = vcpu->arch.event_exit_inst_len;
2130 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2132 return;
2133 }
2134
66fd3f7f
GN		 2135 if (kvm_exception_is_soft(nr)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2138 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139 } else
2140 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2143}
2144
4e47c7a6
SY		 2145static bool vmx_rdtscp_supported(void)
2146{
2147 return cpu_has_vmx_rdtscp();
2148}
2149
ad756a16
MJ		 2150static bool vmx_invpcid_supported(void)
2151{
2152 return cpu_has_vmx_invpcid() && enable_ept;
2153}
2154
a75beee6
ED		 2155/*
2156 * Swap MSR entry in host/guest MSR entry array.
2157 */
8b9cf98c 2158static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2159{
26bb0981 2160 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2161
2162 tmp = vmx->guest_msrs[to];
2163 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2165}
2166
8d14695f
YZ		 2167static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168{
2169 unsigned long *msr_bitmap;
2170
670125bd
WV		 2171 if (is_guest_mode(vcpu))
2172 msr_bitmap = vmx_msr_bitmap_nested;
2173 else if (irqchip_in_kernel(vcpu->kvm) &&
2174 apic_x2apic_mode(vcpu->arch.apic)) {
8d14695f
YZ		 2175 if (is_long_mode(vcpu))
2176 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177 else
2178 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179 } else {
2180 if (is_long_mode(vcpu))
2181 msr_bitmap = vmx_msr_bitmap_longmode;
2182 else
2183 msr_bitmap = vmx_msr_bitmap_legacy;
2184 }
2185
2186 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187}
2188
e38aea3e
AK		 2189/*
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2193 */
8b9cf98c 2194static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2195{
26bb0981 2196 int save_nmsrs, index;
e38aea3e 2197
a75beee6
ED		 2198 save_nmsrs = 0;
2199#ifdef CONFIG_X86_64
8b9cf98c 2200 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2201 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2202 if (index >= 0)
8b9cf98c
RR		 2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2205 if (index >= 0)
8b9cf98c
RR		 2206 move_msr_up(vmx, index, save_nmsrs++);
2207 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2208 if (index >= 0)
8b9cf98c 2209 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2210 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211 if (index >= 0 && vmx->rdtscp_enabled)
2212 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2213 /*
8c06585d 2214 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2215 * if efer.sce is enabled.
2216 */
8c06585d 2217 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2218 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2219 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2220 }
2221#endif
92c0d900
AK		 2222 index = __find_msr_index(vmx, MSR_EFER);
2223 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2224 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2225
26bb0981 2226 vmx->save_nmsrs = save_nmsrs;
5897297b 2227
8d14695f
YZ		 2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2230}
2231
6aa8b732
AK		 2232/*
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2235 */
2236static u64 guest_read_tsc(void)
2237{
2238 u64 host_tsc, tsc_offset;
2239
2240 rdtscll(host_tsc);
2241 tsc_offset = vmcs_read64(TSC_OFFSET);
2242 return host_tsc + tsc_offset;
2243}
2244
d5c1785d
NHE		 2245/*
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2248 */
48d89b92 2249static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2250{
886b470c 2251 u64 tsc_offset;
d5c1785d 2252
d5c1785d
NHE		 2253 tsc_offset = is_guest_mode(vcpu) ?
2254 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255 vmcs_read64(TSC_OFFSET);
2256 return host_tsc + tsc_offset;
2257}
2258
4051b188 2259/*
cc578287
ZA		 2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
4051b188 2262 */
cc578287 2263static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2264{
cc578287
ZA		 2265 if (!scale)
2266 return;
2267
2268 if (user_tsc_khz > tsc_khz) {
2269 vcpu->arch.tsc_catchup = 1;
2270 vcpu->arch.tsc_always_catchup = 1;
2271 } else
2272 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2273}
2274
ba904635
WA		 2275static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276{
2277 return vmcs_read64(TSC_OFFSET);
2278}
2279
6aa8b732 2280/*
99e3e30a 2281 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2282 */
99e3e30a 2283static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2284{
27fc51b2 2285 if (is_guest_mode(vcpu)) {
7991825b 2286 /*
27fc51b2
NHE		 2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
7991825b 2291 */
27fc51b2
NHE		 2292 struct vmcs12 *vmcs12;
2293 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12 = get_vmcs12(vcpu);
2296 vmcs_write64(TSC_OFFSET, offset +
2297 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298 vmcs12->tsc_offset : 0));
2299 } else {
489223ed
YY		 2300 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2302 vmcs_write64(TSC_OFFSET, offset);
2303 }
6aa8b732
AK		 2304}
2305
f1e2b260 2306static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2307{
2308 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2309
e48672fa 2310 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2311 if (is_guest_mode(vcpu)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2314 } else
2315 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316 offset + adjustment);
e48672fa
ZA		 2317}
2318
857e4099
JR		 2319static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320{
2321 return target_tsc - native_read_tsc();
2322}
2323
801d3424
NHE		 2324static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325{
2326 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328}
2329
2330/*
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2335 */
2336static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337{
2338 return nested && guest_cpuid_has_vmx(vcpu);
2339}
2340
b87a51ae
NHE		 2341/*
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
b87a51ae 2350 */
b9c237bb 2351static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2352{
2353 /*
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2366 */
2367
2368 /* pin-based controls */
eabeaacc 2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2370 vmx->nested.nested_vmx_pinbased_ctls_low,
2371 vmx->nested.nested_vmx_pinbased_ctls_high);
2372 vmx->nested.nested_vmx_pinbased_ctls_low |=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374 vmx->nested.nested_vmx_pinbased_ctls_high &=
2375 PIN_BASED_EXT_INTR_MASK |
2376 PIN_BASED_NMI_EXITING |
2377 PIN_BASED_VIRTUAL_NMIS;
2378 vmx->nested.nested_vmx_pinbased_ctls_high |=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2380 PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1
WV		 2381 if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383 PIN_BASED_POSTED_INTR;
b87a51ae 2384
3dbcd8da 2385 /* exit controls */
c0dfee58 2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2387 vmx->nested.nested_vmx_exit_ctls_low,
2388 vmx->nested.nested_vmx_exit_ctls_high);
2389 vmx->nested.nested_vmx_exit_ctls_low =
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2391
b9c237bb 2392 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2393#ifdef CONFIG_X86_64
c0dfee58 2394 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2395#endif
f4124500 2396 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2397 vmx->nested.nested_vmx_exit_ctls_high |=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2399 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
36be0b9d 2402 if (vmx_mpx_supported())
b9c237bb 2403 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2404
2996fca0 2405 /* We support free control of debug control saving. */
b9c237bb
WV		 2406 vmx->nested.nested_vmx_true_exit_ctls_low =
2407 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
b87a51ae
NHE		 2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2412 vmx->nested.nested_vmx_entry_ctls_low,
2413 vmx->nested.nested_vmx_entry_ctls_high);
2414 vmx->nested.nested_vmx_entry_ctls_low =
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2417#ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE |
2419#endif
2420 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2421 vmx->nested.nested_vmx_entry_ctls_high |=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2423 if (vmx_mpx_supported())
b9c237bb 2424 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2425
2996fca0 2426 /* We support free control of debug control loading. */
b9c237bb
WV		 2427 vmx->nested.nested_vmx_true_entry_ctls_low =
2428 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
b87a51ae
NHE		 2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2433 vmx->nested.nested_vmx_procbased_ctls_low,
2434 vmx->nested.nested_vmx_procbased_ctls_high);
2435 vmx->nested.nested_vmx_procbased_ctls_low =
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2438 CPU_BASED_VIRTUAL_INTR_PENDING |
2439 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2440 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442 CPU_BASED_CR3_STORE_EXITING |
2443#ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445#endif
2446 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2448 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2449 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2450 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451 /*
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2456 */
b9c237bb
WV		 2457 vmx->nested.nested_vmx_procbased_ctls_high |=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2459 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2460
3dcdf3ec 2461 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2462 vmx->nested.nested_vmx_true_procbased_ctls_low =
2463 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2464 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
b87a51ae
NHE		 2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2468 vmx->nested.nested_vmx_secondary_ctls_low,
2469 vmx->nested.nested_vmx_secondary_ctls_high);
2470 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
f2b93280 2473 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2474 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2475 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7
WL		 2476 SECONDARY_EXEC_WBINVD_EXITING |
2477 SECONDARY_EXEC_XSAVES;
c18911a2 2478
afa61f75
NHE		 2479 if (enable_ept) {
2480 /* nested EPT: emulate EPT also to L1 */
b9c237bb
WV		 2481 vmx->nested.nested_vmx_secondary_ctls_high |=
2482 SECONDARY_EXEC_ENABLE_EPT |
78051e3b 2483 SECONDARY_EXEC_UNRESTRICTED_GUEST;
b9c237bb 2484 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2485 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486 VMX_EPT_INVEPT_BIT;
b9c237bb 2487 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2488 /*
4b855078
BD		 2489 * For nested guests, we don't do anything specific
2490 * for single context invalidation. Hence, only advertise
2491 * support for global context invalidation.
afa61f75 2492 */
b9c237bb 2493 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2494 } else
b9c237bb 2495 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2496
c18911a2 2497 /* miscellaneous data */
b9c237bb
WV		 2498 rdmsr(MSR_IA32_VMX_MISC,
2499 vmx->nested.nested_vmx_misc_low,
2500 vmx->nested.nested_vmx_misc_high);
2501 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2502 vmx->nested.nested_vmx_misc_low |=
2503 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2504 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2505 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2506}
2507
2508static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2509{
2510 /*
2511 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2512 */
2513 return ((control & high) | low) == control;
2514}
2515
2516static inline u64 vmx_control_msr(u32 low, u32 high)
2517{
2518 return low | ((u64)high << 32);
2519}
2520
cae50139 2521/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2522static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2523{
b9c237bb
WV		 2524 struct vcpu_vmx *vmx = to_vmx(vcpu);
2525
b87a51ae 2526 switch (msr_index) {
b87a51ae
NHE		 2527 case MSR_IA32_VMX_BASIC:
2528 /*
2529 * This MSR reports some information about VMX support. We
2530 * should return information about the VMX we emulate for the
2531 * guest, and the VMCS structure we give it - not about the
2532 * VMX support of the underlying hardware.
2533 */
3dbcd8da 2534 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2535 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2536 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2537 break;
2538 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2539 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2540 *pdata = vmx_control_msr(
2541 vmx->nested.nested_vmx_pinbased_ctls_low,
2542 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2543 break;
2544 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2545 *pdata = vmx_control_msr(
2546 vmx->nested.nested_vmx_true_procbased_ctls_low,
2547 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2548 break;
b87a51ae 2549 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2550 *pdata = vmx_control_msr(
2551 vmx->nested.nested_vmx_procbased_ctls_low,
2552 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2553 break;
2554 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2555 *pdata = vmx_control_msr(
2556 vmx->nested.nested_vmx_true_exit_ctls_low,
2557 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2558 break;
b87a51ae 2559 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2560 *pdata = vmx_control_msr(
2561 vmx->nested.nested_vmx_exit_ctls_low,
2562 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2563 break;
2564 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2565 *pdata = vmx_control_msr(
2566 vmx->nested.nested_vmx_true_entry_ctls_low,
2567 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2568 break;
b87a51ae 2569 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2570 *pdata = vmx_control_msr(
2571 vmx->nested.nested_vmx_entry_ctls_low,
2572 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2573 break;
2574 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2575 *pdata = vmx_control_msr(
2576 vmx->nested.nested_vmx_misc_low,
2577 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2578 break;
2579 /*
2580 * These MSRs specify bits which the guest must keep fixed (on or off)
2581 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2582 * We picked the standard core2 setting.
2583 */
2584#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2585#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2586 case MSR_IA32_VMX_CR0_FIXED0:
2587 *pdata = VMXON_CR0_ALWAYSON;
2588 break;
2589 case MSR_IA32_VMX_CR0_FIXED1:
2590 *pdata = -1ULL;
2591 break;
2592 case MSR_IA32_VMX_CR4_FIXED0:
2593 *pdata = VMXON_CR4_ALWAYSON;
2594 break;
2595 case MSR_IA32_VMX_CR4_FIXED1:
2596 *pdata = -1ULL;
2597 break;
2598 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2599 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2600 break;
2601 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2602 *pdata = vmx_control_msr(
2603 vmx->nested.nested_vmx_secondary_ctls_low,
2604 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2605 break;
2606 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2607 /* Currently, no nested vpid support */
b9c237bb 2608 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2609 break;
2610 default:
b87a51ae 2611 return 1;
b3897a49
NHE		 2612 }
2613
b87a51ae
NHE		 2614 return 0;
2615}
2616
6aa8b732
AK		 2617/*
2618 * Reads an msr value (of 'msr_index') into 'pdata'.
2619 * Returns 0 on success, non-0 otherwise.
2620 * Assumes vcpu_load() was already called.
2621 */
2622static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2623{
2624 u64 data;
26bb0981 2625 struct shared_msr_entry *msr;
6aa8b732
AK		 2626
2627 if (!pdata) {
2628 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2629 return -EINVAL;
2630 }
2631
2632 switch (msr_index) {
05b3e0c2 2633#ifdef CONFIG_X86_64
6aa8b732
AK		 2634 case MSR_FS_BASE:
2635 data = vmcs_readl(GUEST_FS_BASE);
2636 break;
2637 case MSR_GS_BASE:
2638 data = vmcs_readl(GUEST_GS_BASE);
2639 break;
44ea2b17
AK		 2640 case MSR_KERNEL_GS_BASE:
2641 vmx_load_host_state(to_vmx(vcpu));
2642 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2643 break;
26bb0981 2644#endif
6aa8b732 2645 case MSR_EFER:
3bab1f5d 2646 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2647 case MSR_IA32_TSC:
6aa8b732
AK		 2648 data = guest_read_tsc();
2649 break;
2650 case MSR_IA32_SYSENTER_CS:
2651 data = vmcs_read32(GUEST_SYSENTER_CS);
2652 break;
2653 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2654 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2655 break;
2656 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2657 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2658 break;
0dd376e7 2659 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2660 if (!vmx_mpx_supported())
2661 return 1;
0dd376e7
LJ		 2662 data = vmcs_read64(GUEST_BNDCFGS);
2663 break;
cae50139
JK		 2664 case MSR_IA32_FEATURE_CONTROL:
2665 if (!nested_vmx_allowed(vcpu))
2666 return 1;
2667 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2668 break;
2669 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2670 if (!nested_vmx_allowed(vcpu))
2671 return 1;
2672 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2673 case MSR_IA32_XSS:
2674 if (!vmx_xsaves_supported())
2675 return 1;
2676 data = vcpu->arch.ia32_xss;
2677 break;
4e47c7a6
SY		 2678 case MSR_TSC_AUX:
2679 if (!to_vmx(vcpu)->rdtscp_enabled)
2680 return 1;
2681 /* Otherwise falls through */
6aa8b732 2682 default:
8b9cf98c 2683 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2684 if (msr) {
2685 data = msr->data;
2686 break;
6aa8b732 2687 }
3bab1f5d 2688 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2689 }
2690
2691 *pdata = data;
2692 return 0;
2693}
2694
cae50139
JK		 2695static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2696
6aa8b732
AK		 2697/*
2698 * Writes msr value into into the appropriate "register".
2699 * Returns 0 on success, non-0 otherwise.
2700 * Assumes vcpu_load() was already called.
2701 */
8fe8ab46 2702static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2703{
a2fa3e9f 2704 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2705 struct shared_msr_entry *msr;
2cc51560 2706 int ret = 0;
8fe8ab46
WA		 2707 u32 msr_index = msr_info->index;
2708 u64 data = msr_info->data;
2cc51560 2709
6aa8b732 2710 switch (msr_index) {
3bab1f5d 2711 case MSR_EFER:
8fe8ab46 2712 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2713 break;
16175a79 2714#ifdef CONFIG_X86_64
6aa8b732 2715 case MSR_FS_BASE:
2fb92db1 2716 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2717 vmcs_writel(GUEST_FS_BASE, data);
2718 break;
2719 case MSR_GS_BASE:
2fb92db1 2720 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2721 vmcs_writel(GUEST_GS_BASE, data);
2722 break;
44ea2b17
AK		 2723 case MSR_KERNEL_GS_BASE:
2724 vmx_load_host_state(vmx);
2725 vmx->msr_guest_kernel_gs_base = data;
2726 break;
6aa8b732
AK		 2727#endif
2728 case MSR_IA32_SYSENTER_CS:
2729 vmcs_write32(GUEST_SYSENTER_CS, data);
2730 break;
2731 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2732 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2733 break;
2734 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2735 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2736 break;
0dd376e7 2737 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2738 if (!vmx_mpx_supported())
2739 return 1;
0dd376e7
LJ		 2740 vmcs_write64(GUEST_BNDCFGS, data);
2741 break;
af24a4e4 2742 case MSR_IA32_TSC:
8fe8ab46 2743 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2744 break;
468d472f
SY		 2745 case MSR_IA32_CR_PAT:
2746 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2747 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2748 return 1;
468d472f
SY		 2749 vmcs_write64(GUEST_IA32_PAT, data);
2750 vcpu->arch.pat = data;
2751 break;
2752 }
8fe8ab46 2753 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2754 break;
ba904635
WA		 2755 case MSR_IA32_TSC_ADJUST:
2756 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2757 break;
cae50139
JK		 2758 case MSR_IA32_FEATURE_CONTROL:
2759 if (!nested_vmx_allowed(vcpu) ||
2760 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2761 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2762 return 1;
2763 vmx->nested.msr_ia32_feature_control = data;
2764 if (msr_info->host_initiated && data == 0)
2765 vmx_leave_nested(vcpu);
2766 break;
2767 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2768 return 1; /* they are read-only */
20300099
WL		 2769 case MSR_IA32_XSS:
2770 if (!vmx_xsaves_supported())
2771 return 1;
2772 /*
2773 * The only supported bit as of Skylake is bit 8, but
2774 * it is not supported on KVM.
2775 */
2776 if (data != 0)
2777 return 1;
2778 vcpu->arch.ia32_xss = data;
2779 if (vcpu->arch.ia32_xss != host_xss)
2780 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2781 vcpu->arch.ia32_xss, host_xss);
2782 else
2783 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2784 break;
4e47c7a6
SY		 2785 case MSR_TSC_AUX:
2786 if (!vmx->rdtscp_enabled)
2787 return 1;
2788 /* Check reserved bit, higher 32 bits should be zero */
2789 if ((data >> 32) != 0)
2790 return 1;
2791 /* Otherwise falls through */
6aa8b732 2792 default:
8b9cf98c 2793 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2794 if (msr) {
8b3c3104 2795 u64 old_msr_data = msr->data;
3bab1f5d 2796 msr->data = data;
2225fd56
AK		 2797 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2798 preempt_disable();
8b3c3104
AH		 2799 ret = kvm_set_shared_msr(msr->index, msr->data,
2800 msr->mask);
2225fd56 2801 preempt_enable();
8b3c3104
AH		 2802 if (ret)
2803 msr->data = old_msr_data;
2225fd56 2804 }
3bab1f5d 2805 break;
6aa8b732 2806 }
8fe8ab46 2807 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2808 }
2809
2cc51560 2810 return ret;
6aa8b732
AK		 2811}
2812
5fdbf976 2813static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2814{
5fdbf976
MT		 2815 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2816 switch (reg) {
2817 case VCPU_REGS_RSP:
2818 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2819 break;
2820 case VCPU_REGS_RIP:
2821 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2822 break;
6de4f3ad
AK		 2823 case VCPU_EXREG_PDPTR:
2824 if (enable_ept)
2825 ept_save_pdptrs(vcpu);
2826 break;
5fdbf976
MT		 2827 default:
2828 break;
2829 }
6aa8b732
AK		 2830}
2831
6aa8b732
AK		 2832static __init int cpu_has_kvm_support(void)
2833{
6210e37b 2834 return cpu_has_vmx();
6aa8b732
AK		 2835}
2836
2837static __init int vmx_disabled_by_bios(void)
2838{
2839 u64 msr;
2840
2841 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2842 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2843 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2844 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2845 && tboot_enabled())
2846 return 1;
23f3e991 2847 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2848 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2849 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2850 && !tboot_enabled()) {
2851 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2852 "activate TXT before enabling KVM\n");
cafd6659 2853 return 1;
f9335afe 2854 }
23f3e991
JC		 2855 /* launched w/o TXT and VMX disabled */
2856 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2857 && !tboot_enabled())
2858 return 1;
cafd6659
SW		 2859 }
2860
2861 return 0;
6aa8b732
AK		 2862}
2863
7725b894
DX		 2864static void kvm_cpu_vmxon(u64 addr)
2865{
2866 asm volatile (ASM_VMX_VMXON_RAX
2867 : : "a"(&addr), "m"(addr)
2868 : "memory", "cc");
2869}
2870
13a34e06 2871static int hardware_enable(void)
6aa8b732
AK		 2872{
2873 int cpu = raw_smp_processor_id();
2874 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2875 u64 old, test_bits;
6aa8b732 2876
1e02ce4c 2877 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2878 return -EBUSY;
2879
d462b819 2880 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2881
2882 /*
2883 * Now we can enable the vmclear operation in kdump
2884 * since the loaded_vmcss_on_cpu list on this cpu
2885 * has been initialized.
2886 *
2887 * Though the cpu is not in VMX operation now, there
2888 * is no problem to enable the vmclear operation
2889 * for the loaded_vmcss_on_cpu list is empty!
2890 */
2891 crash_enable_local_vmclear(cpu);
2892
6aa8b732 2893 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2894
2895 test_bits = FEATURE_CONTROL_LOCKED;
2896 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2897 if (tboot_enabled())
2898 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2899
2900 if ((old & test_bits) != test_bits) {
6aa8b732 2901 /* enable and lock */
cafd6659
SW		 2902 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2903 }
375074cc 2904 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2905
4610c9cc
DX		 2906 if (vmm_exclusive) {
2907 kvm_cpu_vmxon(phys_addr);
2908 ept_sync_global();
2909 }
10474ae8 2910
89cbc767 2911 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2912
10474ae8 2913 return 0;
6aa8b732
AK		 2914}
2915
d462b819 2916static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2917{
2918 int cpu = raw_smp_processor_id();
d462b819 2919 struct loaded_vmcs *v, *n;
543e4243 2920
d462b819
NHE		 2921 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2922 loaded_vmcss_on_cpu_link)
2923 __loaded_vmcs_clear(v);
543e4243
AK		 2924}
2925
710ff4a8
EH		 2926
2927/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2928 * tricks.
2929 */
2930static void kvm_cpu_vmxoff(void)
6aa8b732 2931{
4ecac3fd 2932 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2933}
2934
13a34e06 2935static void hardware_disable(void)
710ff4a8 2936{
4610c9cc 2937 if (vmm_exclusive) {
d462b819 2938 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2939 kvm_cpu_vmxoff();
2940 }
375074cc 2941 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2942}
2943
1c3d14fe 2944static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2945 u32 msr, u32 *result)
1c3d14fe
YS		 2946{
2947 u32 vmx_msr_low, vmx_msr_high;
2948 u32 ctl = ctl_min | ctl_opt;
2949
2950 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2951
2952 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2953 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2954
2955 /* Ensure minimum (required) set of control bits are supported. */
2956 if (ctl_min & ~ctl)
002c7f7c 2957 return -EIO;
1c3d14fe
YS		 2958
2959 *result = ctl;
2960 return 0;
2961}
2962
110312c8
AK		 2963static __init bool allow_1_setting(u32 msr, u32 ctl)
2964{
2965 u32 vmx_msr_low, vmx_msr_high;
2966
2967 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2968 return vmx_msr_high & ctl;
2969}
2970
002c7f7c 2971static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2972{
2973 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2974 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2975 u32 _pin_based_exec_control = 0;
2976 u32 _cpu_based_exec_control = 0;
f78e0e2e 2977 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2978 u32 _vmexit_control = 0;
2979 u32 _vmentry_control = 0;
2980
10166744 2981 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2982#ifdef CONFIG_X86_64
2983 CPU_BASED_CR8_LOAD_EXITING |
2984 CPU_BASED_CR8_STORE_EXITING |
2985#endif
d56f546d
SY		 2986 CPU_BASED_CR3_LOAD_EXITING |
2987 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2988 CPU_BASED_USE_IO_BITMAPS |
2989 CPU_BASED_MOV_DR_EXITING |
a7052897 2990 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2991 CPU_BASED_MWAIT_EXITING |
2992 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2993 CPU_BASED_INVLPG_EXITING |
2994 CPU_BASED_RDPMC_EXITING;
443381a8 2995
f78e0e2e 2996 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2997 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2998 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2999 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3000 &_cpu_based_exec_control) < 0)
002c7f7c 3001 return -EIO;
6e5d865c
YS		 3002#ifdef CONFIG_X86_64
3003 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3004 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3005 ~CPU_BASED_CR8_STORE_EXITING;
3006#endif
f78e0e2e 3007 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3008 min2 = 0;
3009 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3010 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3011 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3012 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3013 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3014 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3015 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3016 SECONDARY_EXEC_RDTSCP |
83d4c286 3017 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3018 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3019 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3020 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 3021 SECONDARY_EXEC_XSAVES |
3022 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 3023 if (adjust_vmx_controls(min2, opt2,
3024 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3025 &_cpu_based_2nd_exec_control) < 0)
3026 return -EIO;
3027 }
3028#ifndef CONFIG_X86_64
3029 if (!(_cpu_based_2nd_exec_control &
3030 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3031 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3032#endif
83d4c286
YZ		 3033
3034 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3035 _cpu_based_2nd_exec_control &= ~(
8d14695f 3036 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3037 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3038 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3039
d56f546d 3040 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3041 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3042 enabled */
5fff7d27
GN		 3043 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3044 CPU_BASED_CR3_STORE_EXITING |
3045 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3046 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3047 vmx_capability.ept, vmx_capability.vpid);
3048 }
1c3d14fe 3049
81908bf4 3050 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3051#ifdef CONFIG_X86_64
3052 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3053#endif
a547c6db 3054 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3055 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3056 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3057 &_vmexit_control) < 0)
002c7f7c 3058 return -EIO;
1c3d14fe 3059
01e439be
YZ		 3060 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3061 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3062 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3063 &_pin_based_exec_control) < 0)
3064 return -EIO;
3065
3066 if (!(_cpu_based_2nd_exec_control &
3067 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3068 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3069 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3070
c845f9c6 3071 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3072 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3073 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3074 &_vmentry_control) < 0)
002c7f7c 3075 return -EIO;
6aa8b732 3076
c68876fd 3077 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3078
3079 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3080 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3081 return -EIO;
1c3d14fe
YS		 3082
3083#ifdef CONFIG_X86_64
3084 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3085 if (vmx_msr_high & (1u<<16))
002c7f7c 3086 return -EIO;
1c3d14fe
YS		 3087#endif
3088
3089 /* Require Write-Back (WB) memory type for VMCS accesses. */
3090 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3091 return -EIO;
1c3d14fe 3092
002c7f7c
YS		 3093 vmcs_conf->size = vmx_msr_high & 0x1fff;
3094 vmcs_conf->order = get_order(vmcs_config.size);
3095 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3096
002c7f7c
YS		 3097 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3098 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3099 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3100 vmcs_conf->vmexit_ctrl = _vmexit_control;
3101 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3102
110312c8
AK		 3103 cpu_has_load_ia32_efer =
3104 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3105 VM_ENTRY_LOAD_IA32_EFER)
3106 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3107 VM_EXIT_LOAD_IA32_EFER);
3108
8bf00a52
GN		 3109 cpu_has_load_perf_global_ctrl =
3110 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3111 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3112 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3113 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3114
3115 /*
3116 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3117 * but due to arrata below it can't be used. Workaround is to use
3118 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3119 *
3120 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3121 *
3122 * AAK155 (model 26)
3123 * AAP115 (model 30)
3124 * AAT100 (model 37)
3125 * BC86,AAY89,BD102 (model 44)
3126 * BA97 (model 46)
3127 *
3128 */
3129 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3130 switch (boot_cpu_data.x86_model) {
3131 case 26:
3132 case 30:
3133 case 37:
3134 case 44:
3135 case 46:
3136 cpu_has_load_perf_global_ctrl = false;
3137 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3138 "does not work properly. Using workaround\n");
3139 break;
3140 default:
3141 break;
3142 }
3143 }
3144
20300099
WL		 3145 if (cpu_has_xsaves)
3146 rdmsrl(MSR_IA32_XSS, host_xss);
3147
1c3d14fe 3148 return 0;
c68876fd 3149}
6aa8b732
AK		 3150
3151static struct vmcs *alloc_vmcs_cpu(int cpu)
3152{
3153 int node = cpu_to_node(cpu);
3154 struct page *pages;
3155 struct vmcs *vmcs;
3156
6484eb3e 3157 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3158 if (!pages)
3159 return NULL;
3160 vmcs = page_address(pages);
1c3d14fe
YS		 3161 memset(vmcs, 0, vmcs_config.size);
3162 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3163 return vmcs;
3164}
3165
3166static struct vmcs *alloc_vmcs(void)
3167{
d3b2c338 3168 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3169}
3170
3171static void free_vmcs(struct vmcs *vmcs)
3172{
1c3d14fe 3173 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3174}
3175
d462b819
NHE		 3176/*
3177 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3178 */
3179static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3180{
3181 if (!loaded_vmcs->vmcs)
3182 return;
3183 loaded_vmcs_clear(loaded_vmcs);
3184 free_vmcs(loaded_vmcs->vmcs);
3185 loaded_vmcs->vmcs = NULL;
3186}
3187
39959588 3188static void free_kvm_area(void)
6aa8b732
AK		 3189{
3190 int cpu;
3191
3230bb47 3192 for_each_possible_cpu(cpu) {
6aa8b732 3193 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3194 per_cpu(vmxarea, cpu) = NULL;
3195 }
6aa8b732
AK		 3196}
3197
fe2b201b
BD		 3198static void init_vmcs_shadow_fields(void)
3199{
3200 int i, j;
3201
3202 /* No checks for read only fields yet */
3203
3204 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3205 switch (shadow_read_write_fields[i]) {
3206 case GUEST_BNDCFGS:
3207 if (!vmx_mpx_supported())
3208 continue;
3209 break;
3210 default:
3211 break;
3212 }
3213
3214 if (j < i)
3215 shadow_read_write_fields[j] =
3216 shadow_read_write_fields[i];
3217 j++;
3218 }
3219 max_shadow_read_write_fields = j;
3220
3221 /* shadowed fields guest access without vmexit */
3222 for (i = 0; i < max_shadow_read_write_fields; i++) {
3223 clear_bit(shadow_read_write_fields[i],
3224 vmx_vmwrite_bitmap);
3225 clear_bit(shadow_read_write_fields[i],
3226 vmx_vmread_bitmap);
3227 }
3228 for (i = 0; i < max_shadow_read_only_fields; i++)
3229 clear_bit(shadow_read_only_fields[i],
3230 vmx_vmread_bitmap);
3231}
3232
6aa8b732
AK		 3233static __init int alloc_kvm_area(void)
3234{
3235 int cpu;
3236
3230bb47 3237 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3238 struct vmcs *vmcs;
3239
3240 vmcs = alloc_vmcs_cpu(cpu);
3241 if (!vmcs) {
3242 free_kvm_area();
3243 return -ENOMEM;
3244 }
3245
3246 per_cpu(vmxarea, cpu) = vmcs;
3247 }
3248 return 0;
3249}
3250
14168786
GN		 3251static bool emulation_required(struct kvm_vcpu *vcpu)
3252{
3253 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3254}
3255
91b0aa2c 3256static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3257 struct kvm_segment *save)
6aa8b732 3258{
d99e4152
GN		 3259 if (!emulate_invalid_guest_state) {
3260 /*
3261 * CS and SS RPL should be equal during guest entry according
3262 * to VMX spec, but in reality it is not always so. Since vcpu
3263 * is in the middle of the transition from real mode to
3264 * protected mode it is safe to assume that RPL 0 is a good
3265 * default value.
3266 */
3267 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3268 save->selector &= ~SELECTOR_RPL_MASK;
3269 save->dpl = save->selector & SELECTOR_RPL_MASK;
3270 save->s = 1;
6aa8b732 3271 }
d99e4152 3272 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3273}
3274
3275static void enter_pmode(struct kvm_vcpu *vcpu)
3276{
3277 unsigned long flags;
a89a8fb9 3278 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3279
d99e4152
GN		 3280 /*
3281 * Update real mode segment cache. It may be not up-to-date if sement
3282 * register was written while vcpu was in a guest mode.
3283 */
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3286 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3287 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3289 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3290
7ffd92c5 3291 vmx->rmode.vm86_active = 0;
6aa8b732 3292
2fb92db1
AK		 3293 vmx_segment_cache_clear(vmx);
3294
f5f7b2fe 3295 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3296
3297 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3298 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3299 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3300 vmcs_writel(GUEST_RFLAGS, flags);
3301
66aee91a
RR		 3302 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3303 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3304
3305 update_exception_bitmap(vcpu);
3306
91b0aa2c
GN		 3307 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3308 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3309 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3310 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3311 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3312 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3313}
3314
f5f7b2fe 3315static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3316{
772e0318 3317 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3318 struct kvm_segment var = *save;
3319
3320 var.dpl = 0x3;
3321 if (seg == VCPU_SREG_CS)
3322 var.type = 0x3;
3323
3324 if (!emulate_invalid_guest_state) {
3325 var.selector = var.base >> 4;
3326 var.base = var.base & 0xffff0;
3327 var.limit = 0xffff;
3328 var.g = 0;
3329 var.db = 0;
3330 var.present = 1;
3331 var.s = 1;
3332 var.l = 0;
3333 var.unusable = 0;
3334 var.type = 0x3;
3335 var.avl = 0;
3336 if (save->base & 0xf)
3337 printk_once(KERN_WARNING "kvm: segment base is not "
3338 "paragraph aligned when entering "
3339 "protected mode (seg=%d)", seg);
3340 }
6aa8b732 3341
d99e4152
GN		 3342 vmcs_write16(sf->selector, var.selector);
3343 vmcs_write32(sf->base, var.base);
3344 vmcs_write32(sf->limit, var.limit);
3345 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3346}
3347
3348static void enter_rmode(struct kvm_vcpu *vcpu)
3349{
3350 unsigned long flags;
a89a8fb9 3351 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3352
f5f7b2fe
AK		 3353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3356 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3357 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3358 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3359 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3360
7ffd92c5 3361 vmx->rmode.vm86_active = 1;
6aa8b732 3362
776e58ea
GN		 3363 /*
3364 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3365 * vcpu. Warn the user that an update is overdue.
776e58ea 3366 */
4918c6ca 3367 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3368 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3369 "called before entering vcpu\n");
776e58ea 3370
2fb92db1
AK		 3371 vmx_segment_cache_clear(vmx);
3372
4918c6ca 3373 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3374 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3375 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3376
3377 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3378 vmx->rmode.save_rflags = flags;
6aa8b732 3379
053de044 3380 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3381
3382 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3383 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3384 update_exception_bitmap(vcpu);
3385
d99e4152
GN		 3386 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3387 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3388 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3389 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3390 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3391 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3392
8668a3c4 3393 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3394}
3395
401d10de
AS		 3396static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3397{
3398 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3399 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3400
3401 if (!msr)
3402 return;
401d10de 3403
44ea2b17
AK		 3404 /*
3405 * Force kernel_gs_base reloading before EFER changes, as control
3406 * of this msr depends on is_long_mode().
3407 */
3408 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3409 vcpu->arch.efer = efer;
401d10de 3410 if (efer & EFER_LMA) {
2961e876 3411 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3412 msr->data = efer;
3413 } else {
2961e876 3414 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3415
3416 msr->data = efer & ~EFER_LME;
3417 }
3418 setup_msrs(vmx);
3419}
3420
05b3e0c2 3421#ifdef CONFIG_X86_64
6aa8b732
AK		 3422
3423static void enter_lmode(struct kvm_vcpu *vcpu)
3424{
3425 u32 guest_tr_ar;
3426
2fb92db1
AK		 3427 vmx_segment_cache_clear(to_vmx(vcpu));
3428
6aa8b732
AK		 3429 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3430 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3431 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3432 __func__);
6aa8b732
AK		 3433 vmcs_write32(GUEST_TR_AR_BYTES,
3434 (guest_tr_ar & ~AR_TYPE_MASK)
3435 | AR_TYPE_BUSY_64_TSS);
3436 }
da38f438 3437 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3438}
3439
3440static void exit_lmode(struct kvm_vcpu *vcpu)
3441{
2961e876 3442 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3443 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3444}
3445
3446#endif
3447
2384d2b3
SY		 3448static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3449{
b9d762fa 3450 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3451 if (enable_ept) {
3452 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3453 return;
4e1096d2 3454 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3455 }
2384d2b3
SY		 3456}
3457
e8467fda
AK		 3458static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3459{
3460 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3461
3462 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3463 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3464}
3465
aff48baa
AK		 3466static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3467{
3468 if (enable_ept && is_paging(vcpu))
3469 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3470 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3471}
3472
25c4c276 3473static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3474{
fc78f519
AK		 3475 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3476
3477 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3478 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3479}
3480
1439442c
SY		 3481static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3482{
d0d538b9
GN		 3483 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3484
6de4f3ad
AK		 3485 if (!test_bit(VCPU_EXREG_PDPTR,
3486 (unsigned long *)&vcpu->arch.regs_dirty))
3487 return;
3488
1439442c 3489 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3490 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3491 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3492 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3493 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3494 }
3495}
3496
8f5d549f
AK		 3497static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3498{
d0d538b9
GN		 3499 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3500
8f5d549f 3501 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3502 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3503 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3504 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3505 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3506 }
6de4f3ad
AK		 3507
3508 __set_bit(VCPU_EXREG_PDPTR,
3509 (unsigned long *)&vcpu->arch.regs_avail);
3510 __set_bit(VCPU_EXREG_PDPTR,
3511 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3512}
3513
5e1746d6 3514static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3515
3516static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3517 unsigned long cr0,
3518 struct kvm_vcpu *vcpu)
3519{
5233dd51
MT		 3520 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3521 vmx_decache_cr3(vcpu);
1439442c
SY		 3522 if (!(cr0 & X86_CR0_PG)) {
3523 /* From paging/starting to nonpaging */
3524 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3525 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3526 (CPU_BASED_CR3_LOAD_EXITING |
3527 CPU_BASED_CR3_STORE_EXITING));
3528 vcpu->arch.cr0 = cr0;
fc78f519 3529 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3530 } else if (!is_paging(vcpu)) {
3531 /* From nonpaging to paging */
3532 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3533 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3534 ~(CPU_BASED_CR3_LOAD_EXITING |
3535 CPU_BASED_CR3_STORE_EXITING));
3536 vcpu->arch.cr0 = cr0;
fc78f519 3537 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3538 }
95eb84a7
SY		 3539
3540 if (!(cr0 & X86_CR0_WP))
3541 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3542}
3543
6aa8b732
AK		 3544static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3545{
7ffd92c5 3546 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3547 unsigned long hw_cr0;
3548
5037878e 3549 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3550 if (enable_unrestricted_guest)
5037878e 3551 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3552 else {
5037878e 3553 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3554
218e763f
GN		 3555 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3556 enter_pmode(vcpu);
6aa8b732 3557
218e763f
GN		 3558 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3559 enter_rmode(vcpu);
3560 }
6aa8b732 3561
05b3e0c2 3562#ifdef CONFIG_X86_64
f6801dff 3563 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3564 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3565 enter_lmode(vcpu);
707d92fa 3566 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3567 exit_lmode(vcpu);
3568 }
3569#endif
3570
089d034e 3571 if (enable_ept)
1439442c
SY		 3572 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3573
02daab21 3574 if (!vcpu->fpu_active)
81231c69 3575 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3576
6aa8b732 3577 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3578 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3579 vcpu->arch.cr0 = cr0;
14168786
GN		 3580
3581 /* depends on vcpu->arch.cr0 to be set to a new value */
3582 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3583}
3584
1439442c
SY		 3585static u64 construct_eptp(unsigned long root_hpa)
3586{
3587 u64 eptp;
3588
3589 /* TODO write the value reading from MSR */
3590 eptp = VMX_EPT_DEFAULT_MT |
3591 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3592 if (enable_ept_ad_bits)
3593 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3594 eptp |= (root_hpa & PAGE_MASK);
3595
3596 return eptp;
3597}
3598
6aa8b732
AK		 3599static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3600{
1439442c
SY		 3601 unsigned long guest_cr3;
3602 u64 eptp;
3603
3604 guest_cr3 = cr3;
089d034e 3605 if (enable_ept) {
1439442c
SY		 3606 eptp = construct_eptp(cr3);
3607 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3608 if (is_paging(vcpu) || is_guest_mode(vcpu))
3609 guest_cr3 = kvm_read_cr3(vcpu);
3610 else
3611 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3612 ept_load_pdptrs(vcpu);
1439442c
SY		 3613 }
3614
2384d2b3 3615 vmx_flush_tlb(vcpu);
1439442c 3616 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3617}
3618
5e1746d6 3619static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3620{
7ffd92c5 3621 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3622 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3623
5e1746d6
NHE		 3624 if (cr4 & X86_CR4_VMXE) {
3625 /*
3626 * To use VMXON (and later other VMX instructions), a guest
3627 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3628 * So basically the check on whether to allow nested VMX
3629 * is here.
3630 */
3631 if (!nested_vmx_allowed(vcpu))
3632 return 1;
1a0d74e6
JK		 3633 }
3634 if (to_vmx(vcpu)->nested.vmxon &&
3635 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3636 return 1;
3637
ad312c7c 3638 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3639 if (enable_ept) {
3640 if (!is_paging(vcpu)) {
3641 hw_cr4 &= ~X86_CR4_PAE;
3642 hw_cr4 |= X86_CR4_PSE;
c08800a5 3643 /*
e1e746b3
FW		 3644 * SMEP/SMAP is disabled if CPU is in non-paging mode
3645 * in hardware. However KVM always uses paging mode to
c08800a5 3646 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3647 * To emulate this behavior, SMEP/SMAP needs to be
3648 * manually disabled when guest switches to non-paging
3649 * mode.
c08800a5 3650 */
e1e746b3 3651 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3652 } else if (!(cr4 & X86_CR4_PAE)) {
3653 hw_cr4 &= ~X86_CR4_PAE;
3654 }
3655 }
1439442c
SY		 3656
3657 vmcs_writel(CR4_READ_SHADOW, cr4);
3658 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3659 return 0;
6aa8b732
AK		 3660}
3661
6aa8b732
AK		 3662static void vmx_get_segment(struct kvm_vcpu *vcpu,
3663 struct kvm_segment *var, int seg)
3664{
a9179499 3665 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3666 u32 ar;
3667
c6ad1153 3668 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3669 *var = vmx->rmode.segs[seg];
a9179499 3670 if (seg == VCPU_SREG_TR
2fb92db1 3671 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3672 return;
1390a28b
AK		 3673 var->base = vmx_read_guest_seg_base(vmx, seg);
3674 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3675 return;
a9179499 3676 }
2fb92db1
AK		 3677 var->base = vmx_read_guest_seg_base(vmx, seg);
3678 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3679 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3680 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3681 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3682 var->type = ar & 15;
3683 var->s = (ar >> 4) & 1;
3684 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3685 /*
3686 * Some userspaces do not preserve unusable property. Since usable
3687 * segment has to be present according to VMX spec we can use present
3688 * property to amend userspace bug by making unusable segment always
3689 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3690 * segment as unusable.
3691 */
3692 var->present = !var->unusable;
6aa8b732
AK		 3693 var->avl = (ar >> 12) & 1;
3694 var->l = (ar >> 13) & 1;
3695 var->db = (ar >> 14) & 1;
3696 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3697}
3698
a9179499
AK		 3699static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3700{
a9179499
AK		 3701 struct kvm_segment s;
3702
3703 if (to_vmx(vcpu)->rmode.vm86_active) {
3704 vmx_get_segment(vcpu, &s, seg);
3705 return s.base;
3706 }
2fb92db1 3707 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3708}
3709
b09408d0 3710static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3711{
b09408d0
MT		 3712 struct vcpu_vmx *vmx = to_vmx(vcpu);
3713
ae9fedc7 3714 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3715 return 0;
ae9fedc7
PB		 3716 else {
3717 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3718 return AR_DPL(ar);
69c73028 3719 }
69c73028
AK		 3720}
3721
653e3108 3722static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3723{
6aa8b732
AK		 3724 u32 ar;
3725
f0495f9b 3726 if (var->unusable || !var->present)
6aa8b732
AK		 3727 ar = 1 << 16;
3728 else {
3729 ar = var->type & 15;
3730 ar |= (var->s & 1) << 4;
3731 ar |= (var->dpl & 3) << 5;
3732 ar |= (var->present & 1) << 7;
3733 ar |= (var->avl & 1) << 12;
3734 ar |= (var->l & 1) << 13;
3735 ar |= (var->db & 1) << 14;
3736 ar |= (var->g & 1) << 15;
3737 }
653e3108
AK		 3738
3739 return ar;
3740}
3741
3742static void vmx_set_segment(struct kvm_vcpu *vcpu,
3743 struct kvm_segment *var, int seg)
3744{
7ffd92c5 3745 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3746 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3747
2fb92db1
AK		 3748 vmx_segment_cache_clear(vmx);
3749
1ecd50a9
GN		 3750 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3751 vmx->rmode.segs[seg] = *var;
3752 if (seg == VCPU_SREG_TR)
3753 vmcs_write16(sf->selector, var->selector);
3754 else if (var->s)
3755 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3756 goto out;
653e3108 3757 }
1ecd50a9 3758
653e3108
AK		 3759 vmcs_writel(sf->base, var->base);
3760 vmcs_write32(sf->limit, var->limit);
3761 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3762
3763 /*
3764 * Fix the "Accessed" bit in AR field of segment registers for older
3765 * qemu binaries.
3766 * IA32 arch specifies that at the time of processor reset the
3767 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3768 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3769 * state vmexit when "unrestricted guest" mode is turned on.
3770 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3771 * tree. Newer qemu binaries with that qemu fix would not need this
3772 * kvm hack.
3773 */
3774 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3775 var->type |= 0x1; /* Accessed */
3a624e29 3776
f924d66d 3777 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3778
3779out:
98eb2f8b 3780 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3781}
3782
6aa8b732
AK		 3783static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3784{
2fb92db1 3785 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3786
3787 *db = (ar >> 14) & 1;
3788 *l = (ar >> 13) & 1;
3789}
3790
89a27f4d 3791static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3792{
89a27f4d
GN		 3793 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3794 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3795}
3796
89a27f4d 3797static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3798{
89a27f4d
GN		 3799 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3800 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3801}
3802
89a27f4d 3803static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3804{
89a27f4d
GN		 3805 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3806 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3807}
3808
89a27f4d 3809static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3810{
89a27f4d
GN		 3811 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3812 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3813}
3814
648dfaa7
MG		 3815static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3816{
3817 struct kvm_segment var;
3818 u32 ar;
3819
3820 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3821 var.dpl = 0x3;
0647f4aa
GN		 3822 if (seg == VCPU_SREG_CS)
3823 var.type = 0x3;
648dfaa7
MG		 3824 ar = vmx_segment_access_rights(&var);
3825
3826 if (var.base != (var.selector << 4))
3827 return false;
89efbed0 3828 if (var.limit != 0xffff)
648dfaa7 3829 return false;
07f42f5f 3830 if (ar != 0xf3)
648dfaa7
MG		 3831 return false;
3832
3833 return true;
3834}
3835
3836static bool code_segment_valid(struct kvm_vcpu *vcpu)
3837{
3838 struct kvm_segment cs;
3839 unsigned int cs_rpl;
3840
3841 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3842 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3843
1872a3f4
AK		 3844 if (cs.unusable)
3845 return false;
648dfaa7
MG		 3846 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3847 return false;
3848 if (!cs.s)
3849 return false;
1872a3f4 3850 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3851 if (cs.dpl > cs_rpl)
3852 return false;
1872a3f4 3853 } else {
648dfaa7
MG		 3854 if (cs.dpl != cs_rpl)
3855 return false;
3856 }
3857 if (!cs.present)
3858 return false;
3859
3860 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3861 return true;
3862}
3863
3864static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3865{
3866 struct kvm_segment ss;
3867 unsigned int ss_rpl;
3868
3869 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3870 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3871
1872a3f4
AK		 3872 if (ss.unusable)
3873 return true;
3874 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3875 return false;
3876 if (!ss.s)
3877 return false;
3878 if (ss.dpl != ss_rpl) /* DPL != RPL */
3879 return false;
3880 if (!ss.present)
3881 return false;
3882
3883 return true;
3884}
3885
3886static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3887{
3888 struct kvm_segment var;
3889 unsigned int rpl;
3890
3891 vmx_get_segment(vcpu, &var, seg);
3892 rpl = var.selector & SELECTOR_RPL_MASK;
3893
1872a3f4
AK		 3894 if (var.unusable)
3895 return true;
648dfaa7
MG		 3896 if (!var.s)
3897 return false;
3898 if (!var.present)
3899 return false;
3900 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3901 if (var.dpl < rpl) /* DPL < RPL */
3902 return false;
3903 }
3904
3905 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3906 * rights flags
3907 */
3908 return true;
3909}
3910
3911static bool tr_valid(struct kvm_vcpu *vcpu)
3912{
3913 struct kvm_segment tr;
3914
3915 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3916
1872a3f4
AK		 3917 if (tr.unusable)
3918 return false;
648dfaa7
MG		 3919 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3920 return false;
1872a3f4 3921 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3922 return false;
3923 if (!tr.present)
3924 return false;
3925
3926 return true;
3927}
3928
3929static bool ldtr_valid(struct kvm_vcpu *vcpu)
3930{
3931 struct kvm_segment ldtr;
3932
3933 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3934
1872a3f4
AK		 3935 if (ldtr.unusable)
3936 return true;
648dfaa7
MG		 3937 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3938 return false;
3939 if (ldtr.type != 2)
3940 return false;
3941 if (!ldtr.present)
3942 return false;
3943
3944 return true;
3945}
3946
3947static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3948{
3949 struct kvm_segment cs, ss;
3950
3951 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3952 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3953
3954 return ((cs.selector & SELECTOR_RPL_MASK) ==
3955 (ss.selector & SELECTOR_RPL_MASK));
3956}
3957
3958/*
3959 * Check if guest state is valid. Returns true if valid, false if
3960 * not.
3961 * We assume that registers are always usable
3962 */
3963static bool guest_state_valid(struct kvm_vcpu *vcpu)
3964{
c5e97c80
GN		 3965 if (enable_unrestricted_guest)
3966 return true;
3967
648dfaa7 3968 /* real mode guest state checks */
f13882d8 3969 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3970 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3971 return false;
3972 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3973 return false;
3974 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3975 return false;
3976 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3977 return false;
3978 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3979 return false;
3980 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3981 return false;
3982 } else {
3983 /* protected mode guest state checks */
3984 if (!cs_ss_rpl_check(vcpu))
3985 return false;
3986 if (!code_segment_valid(vcpu))
3987 return false;
3988 if (!stack_segment_valid(vcpu))
3989 return false;
3990 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3991 return false;
3992 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3993 return false;
3994 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3995 return false;
3996 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3997 return false;
3998 if (!tr_valid(vcpu))
3999 return false;
4000 if (!ldtr_valid(vcpu))
4001 return false;
4002 }
4003 /* TODO:
4004 * - Add checks on RIP
4005 * - Add checks on RFLAGS
4006 */
4007
4008 return true;
4009}
4010
d77c26fc 4011static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4012{
40dcaa9f 4013 gfn_t fn;
195aefde 4014 u16 data = 0;
1f755a82 4015 int idx, r;
6aa8b732 4016
40dcaa9f 4017 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4018 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4019 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4020 if (r < 0)
10589a46 4021 goto out;
195aefde 4022 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4023 r = kvm_write_guest_page(kvm, fn++, &data,
4024 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4025 if (r < 0)
10589a46 4026 goto out;
195aefde
IE		 4027 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4028 if (r < 0)
10589a46 4029 goto out;
195aefde
IE		 4030 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4031 if (r < 0)
10589a46 4032 goto out;
195aefde 4033 data = ~0;
10589a46
MT		 4034 r = kvm_write_guest_page(kvm, fn, &data,
4035 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4036 sizeof(u8));
10589a46 4037out:
40dcaa9f 4038 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4039 return r;
6aa8b732
AK		 4040}
4041
b7ebfb05
SY		 4042static int init_rmode_identity_map(struct kvm *kvm)
4043{
f51770ed 4044 int i, idx, r = 0;
b7ebfb05
SY		 4045 pfn_t identity_map_pfn;
4046 u32 tmp;
4047
089d034e 4048 if (!enable_ept)
f51770ed 4049 return 0;
a255d479
TC		 4050
4051 /* Protect kvm->arch.ept_identity_pagetable_done. */
4052 mutex_lock(&kvm->slots_lock);
4053
f51770ed 4054 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4055 goto out2;
a255d479 4056
b927a3ce 4057 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4058
4059 r = alloc_identity_pagetable(kvm);
f51770ed 4060 if (r < 0)
a255d479
TC		 4061 goto out2;
4062
40dcaa9f 4063 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4064 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4065 if (r < 0)
4066 goto out;
4067 /* Set up identity-mapping pagetable for EPT in real mode */
4068 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4069 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4070 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4071 r = kvm_write_guest_page(kvm, identity_map_pfn,
4072 &tmp, i * sizeof(tmp), sizeof(tmp));
4073 if (r < 0)
4074 goto out;
4075 }
4076 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4077
b7ebfb05 4078out:
40dcaa9f 4079 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4080
4081out2:
4082 mutex_unlock(&kvm->slots_lock);
f51770ed 4083 return r;
b7ebfb05
SY		 4084}
4085
6aa8b732
AK		 4086static void seg_setup(int seg)
4087{
772e0318 4088 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4089 unsigned int ar;
6aa8b732
AK		 4090
4091 vmcs_write16(sf->selector, 0);
4092 vmcs_writel(sf->base, 0);
4093 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4094 ar = 0x93;
4095 if (seg == VCPU_SREG_CS)
4096 ar |= 0x08; /* code segment */
3a624e29
NK		 4097
4098 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4099}
4100
f78e0e2e
SY		 4101static int alloc_apic_access_page(struct kvm *kvm)
4102{
4484141a 4103 struct page *page;
f78e0e2e
SY		 4104 struct kvm_userspace_memory_region kvm_userspace_mem;
4105 int r = 0;
4106
79fac95e 4107 mutex_lock(&kvm->slots_lock);
c24ae0dc 4108 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4109 goto out;
4110 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4111 kvm_userspace_mem.flags = 0;
73a6d941 4112 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4113 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4114 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4115 if (r)
4116 goto out;
72dc67a6 4117
73a6d941 4118 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4119 if (is_error_page(page)) {
4120 r = -EFAULT;
4121 goto out;
4122 }
4123
c24ae0dc
TC		 4124 /*
4125 * Do not pin the page in memory, so that memory hot-unplug
4126 * is able to migrate it.
4127 */
4128 put_page(page);
4129 kvm->arch.apic_access_page_done = true;
f78e0e2e 4130out:
79fac95e 4131 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4132 return r;
4133}
4134
b7ebfb05
SY		 4135static int alloc_identity_pagetable(struct kvm *kvm)
4136{
a255d479
TC		 4137 /* Called with kvm->slots_lock held. */
4138
b7ebfb05
SY		 4139 struct kvm_userspace_memory_region kvm_userspace_mem;
4140 int r = 0;
4141
a255d479
TC		 4142 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4143
b7ebfb05
SY		 4144 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4145 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4146 kvm_userspace_mem.guest_phys_addr =
4147 kvm->arch.ept_identity_map_addr;
b7ebfb05 4148 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4149 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4150
b7ebfb05
SY		 4151 return r;
4152}
4153
2384d2b3
SY		 4154static void allocate_vpid(struct vcpu_vmx *vmx)
4155{
4156 int vpid;
4157
4158 vmx->vpid = 0;
919818ab 4159 if (!enable_vpid)
2384d2b3
SY		 4160 return;
4161 spin_lock(&vmx_vpid_lock);
4162 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4163 if (vpid < VMX_NR_VPIDS) {
4164 vmx->vpid = vpid;
4165 __set_bit(vpid, vmx_vpid_bitmap);
4166 }
4167 spin_unlock(&vmx_vpid_lock);
4168}
4169
cdbecfc3
LJ		 4170static void free_vpid(struct vcpu_vmx *vmx)
4171{
4172 if (!enable_vpid)
4173 return;
4174 spin_lock(&vmx_vpid_lock);
4175 if (vmx->vpid != 0)
4176 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4177 spin_unlock(&vmx_vpid_lock);
4178}
4179
8d14695f
YZ		 4180#define MSR_TYPE_R 1
4181#define MSR_TYPE_W 2
4182static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4183 u32 msr, int type)
25c5f225 4184{
3e7c73e9 4185 int f = sizeof(unsigned long);
25c5f225
SY		 4186
4187 if (!cpu_has_vmx_msr_bitmap())
4188 return;
4189
4190 /*
4191 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4192 * have the write-low and read-high bitmap offsets the wrong way round.
4193 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4194 */
25c5f225 4195 if (msr <= 0x1fff) {
8d14695f
YZ		 4196 if (type & MSR_TYPE_R)
4197 /* read-low */
4198 __clear_bit(msr, msr_bitmap + 0x000 / f);
4199
4200 if (type & MSR_TYPE_W)
4201 /* write-low */
4202 __clear_bit(msr, msr_bitmap + 0x800 / f);
4203
25c5f225
SY		 4204 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4205 msr &= 0x1fff;
8d14695f
YZ		 4206 if (type & MSR_TYPE_R)
4207 /* read-high */
4208 __clear_bit(msr, msr_bitmap + 0x400 / f);
4209
4210 if (type & MSR_TYPE_W)
4211 /* write-high */
4212 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4213
4214 }
4215}
4216
4217static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4218 u32 msr, int type)
4219{
4220 int f = sizeof(unsigned long);
4221
4222 if (!cpu_has_vmx_msr_bitmap())
4223 return;
4224
4225 /*
4226 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4227 * have the write-low and read-high bitmap offsets the wrong way round.
4228 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4229 */
4230 if (msr <= 0x1fff) {
4231 if (type & MSR_TYPE_R)
4232 /* read-low */
4233 __set_bit(msr, msr_bitmap + 0x000 / f);
4234
4235 if (type & MSR_TYPE_W)
4236 /* write-low */
4237 __set_bit(msr, msr_bitmap + 0x800 / f);
4238
4239 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4240 msr &= 0x1fff;
4241 if (type & MSR_TYPE_R)
4242 /* read-high */
4243 __set_bit(msr, msr_bitmap + 0x400 / f);
4244
4245 if (type & MSR_TYPE_W)
4246 /* write-high */
4247 __set_bit(msr, msr_bitmap + 0xc00 / f);
4248
25c5f225 4249 }
25c5f225
SY		 4250}
4251
f2b93280
WV		 4252/*
4253 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4254 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4255 */
4256static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4257 unsigned long *msr_bitmap_nested,
4258 u32 msr, int type)
4259{
4260 int f = sizeof(unsigned long);
4261
4262 if (!cpu_has_vmx_msr_bitmap()) {
4263 WARN_ON(1);
4264 return;
4265 }
4266
4267 /*
4268 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4269 * have the write-low and read-high bitmap offsets the wrong way round.
4270 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4271 */
4272 if (msr <= 0x1fff) {
4273 if (type & MSR_TYPE_R &&
4274 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4275 /* read-low */
4276 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4277
4278 if (type & MSR_TYPE_W &&
4279 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4280 /* write-low */
4281 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4282
4283 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4284 msr &= 0x1fff;
4285 if (type & MSR_TYPE_R &&
4286 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4287 /* read-high */
4288 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4289
4290 if (type & MSR_TYPE_W &&
4291 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4292 /* write-high */
4293 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4294
4295 }
4296}
4297
5897297b
AK		 4298static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4299{
4300 if (!longmode_only)
8d14695f
YZ		 4301 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4302 msr, MSR_TYPE_R | MSR_TYPE_W);
4303 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4304 msr, MSR_TYPE_R | MSR_TYPE_W);
4305}
4306
4307static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4308{
4309 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4310 msr, MSR_TYPE_R);
4311 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4312 msr, MSR_TYPE_R);
4313}
4314
4315static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4316{
4317 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4318 msr, MSR_TYPE_R);
4319 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4320 msr, MSR_TYPE_R);
4321}
4322
4323static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4324{
4325 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4326 msr, MSR_TYPE_W);
4327 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4328 msr, MSR_TYPE_W);
5897297b
AK		 4329}
4330
01e439be
YZ		 4331static int vmx_vm_has_apicv(struct kvm *kvm)
4332{
4333 return enable_apicv && irqchip_in_kernel(kvm);
4334}
4335
705699a1
WV		 4336static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4337{
4338 struct vcpu_vmx *vmx = to_vmx(vcpu);
4339 int max_irr;
4340 void *vapic_page;
4341 u16 status;
4342
4343 if (vmx->nested.pi_desc &&
4344 vmx->nested.pi_pending) {
4345 vmx->nested.pi_pending = false;
4346 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4347 return 0;
4348
4349 max_irr = find_last_bit(
4350 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4351
4352 if (max_irr == 256)
4353 return 0;
4354
4355 vapic_page = kmap(vmx->nested.virtual_apic_page);
4356 if (!vapic_page) {
4357 WARN_ON(1);
4358 return -ENOMEM;
4359 }
4360 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4361 kunmap(vmx->nested.virtual_apic_page);
4362
4363 status = vmcs_read16(GUEST_INTR_STATUS);
4364 if ((u8)max_irr > ((u8)status & 0xff)) {
4365 status &= ~0xff;
4366 status |= (u8)max_irr;
4367 vmcs_write16(GUEST_INTR_STATUS, status);
4368 }
4369 }
4370 return 0;
4371}
4372
21bc8dc5
RK		 4373static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4374{
4375#ifdef CONFIG_SMP
4376 if (vcpu->mode == IN_GUEST_MODE) {
4377 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4378 POSTED_INTR_VECTOR);
4379 return true;
4380 }
4381#endif
4382 return false;
4383}
4384
705699a1
WV		 4385static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4386 int vector)
4387{
4388 struct vcpu_vmx *vmx = to_vmx(vcpu);
4389
4390 if (is_guest_mode(vcpu) &&
4391 vector == vmx->nested.posted_intr_nv) {
4392 /* the PIR and ON have been set by L1. */
21bc8dc5 4393 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4394 /*
4395 * If a posted intr is not recognized by hardware,
4396 * we will accomplish it in the next vmentry.
4397 */
4398 vmx->nested.pi_pending = true;
4399 kvm_make_request(KVM_REQ_EVENT, vcpu);
4400 return 0;
4401 }
4402 return -1;
4403}
a20ed54d
YZ		 4404/*
4405 * Send interrupt to vcpu via posted interrupt way.
4406 * 1. If target vcpu is running(non-root mode), send posted interrupt
4407 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4408 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4409 * interrupt from PIR in next vmentry.
4410 */
4411static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4412{
4413 struct vcpu_vmx *vmx = to_vmx(vcpu);
4414 int r;
4415
705699a1
WV		 4416 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4417 if (!r)
4418 return;
4419
a20ed54d
YZ		 4420 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4421 return;
4422
4423 r = pi_test_and_set_on(&vmx->pi_desc);
4424 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4425 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4426 kvm_vcpu_kick(vcpu);
4427}
4428
4429static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4430{
4431 struct vcpu_vmx *vmx = to_vmx(vcpu);
4432
4433 if (!pi_test_and_clear_on(&vmx->pi_desc))
4434 return;
4435
4436 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4437}
4438
4439static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4440{
4441 return;
4442}
4443
a3a8ff8e
NHE		 4444/*
4445 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4446 * will not change in the lifetime of the guest.
4447 * Note that host-state that does change is set elsewhere. E.g., host-state
4448 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4449 */
a547c6db 4450static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4451{
4452 u32 low32, high32;
4453 unsigned long tmpl;
4454 struct desc_ptr dt;
d974baa3 4455 unsigned long cr4;
a3a8ff8e 4456
b1a74bf8 4457 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4458 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4459
d974baa3 4460 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4461 cr4 = cr4_read_shadow();
d974baa3
AL		 4462 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4463 vmx->host_state.vmcs_host_cr4 = cr4;
4464
a3a8ff8e 4465 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4466#ifdef CONFIG_X86_64
4467 /*
4468 * Load null selectors, so we can avoid reloading them in
4469 * __vmx_load_host_state(), in case userspace uses the null selectors
4470 * too (the expected case).
4471 */
4472 vmcs_write16(HOST_DS_SELECTOR, 0);
4473 vmcs_write16(HOST_ES_SELECTOR, 0);
4474#else
a3a8ff8e
NHE		 4475 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4476 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4477#endif
a3a8ff8e
NHE		 4478 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4479 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4480
4481 native_store_idt(&dt);
4482 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4483 vmx->host_idt_base = dt.address;
a3a8ff8e 4484
83287ea4 4485 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4486
4487 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4488 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4489 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4490 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4491
4492 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4493 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4494 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4495 }
4496}
4497
bf8179a0
NHE		 4498static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4499{
4500 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4501 if (enable_ept)
4502 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4503 if (is_guest_mode(&vmx->vcpu))
4504 vmx->vcpu.arch.cr4_guest_owned_bits &=
4505 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4506 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4507}
4508
01e439be
YZ		 4509static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4510{
4511 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4512
4513 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4514 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4515 return pin_based_exec_ctrl;
4516}
4517
bf8179a0
NHE		 4518static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4519{
4520 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4521
4522 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4523 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4524
bf8179a0
NHE		 4525 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4526 exec_control &= ~CPU_BASED_TPR_SHADOW;
4527#ifdef CONFIG_X86_64
4528 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4529 CPU_BASED_CR8_LOAD_EXITING;
4530#endif
4531 }
4532 if (!enable_ept)
4533 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4534 CPU_BASED_CR3_LOAD_EXITING |
4535 CPU_BASED_INVLPG_EXITING;
4536 return exec_control;
4537}
4538
4539static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4540{
4541 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4542 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4543 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4544 if (vmx->vpid == 0)
4545 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4546 if (!enable_ept) {
4547 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4548 enable_unrestricted_guest = 0;
ad756a16
MJ		 4549 /* Enable INVPCID for non-ept guests may cause performance regression. */
4550 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4551 }
4552 if (!enable_unrestricted_guest)
4553 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4554 if (!ple_gap)
4555 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4556 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4557 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4558 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4559 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4560 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4561 (handle_vmptrld).
4562 We can NOT enable shadow_vmcs here because we don't have yet
4563 a current VMCS12
4564 */
4565 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4566 /* PML is enabled/disabled in creating/destorying vcpu */
4567 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4568
bf8179a0
NHE		 4569 return exec_control;
4570}
4571
ce88decf
XG		 4572static void ept_set_mmio_spte_mask(void)
4573{
4574 /*
4575 * EPT Misconfigurations can be generated if the value of bits 2:0
4576 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4577 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4578 * spte.
4579 */
885032b9 4580 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4581}
4582
f53cd63c 4583#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4584/*
4585 * Sets up the vmcs for emulated real mode.
4586 */
8b9cf98c 4587static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4588{
2e4ce7f5 4589#ifdef CONFIG_X86_64
6aa8b732 4590 unsigned long a;
2e4ce7f5 4591#endif
6aa8b732 4592 int i;
6aa8b732 4593
6aa8b732 4594 /* I/O */
3e7c73e9
AK		 4595 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4596 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4597
4607c2d7
AG		 4598 if (enable_shadow_vmcs) {
4599 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4600 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4601 }
25c5f225 4602 if (cpu_has_vmx_msr_bitmap())
5897297b 4603 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4604
6aa8b732
AK		 4605 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4606
6aa8b732 4607 /* Control */
01e439be 4608 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4609
bf8179a0 4610 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4611
83ff3b9d 4612 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4613 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4614 vmx_secondary_exec_control(vmx));
83ff3b9d 4615 }
f78e0e2e 4616
01e439be 4617 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4618 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4619 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4620 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4621 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4622
4623 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4624
4625 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4626 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4627 }
4628
4b8d54f9
ZE		 4629 if (ple_gap) {
4630 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4631 vmx->ple_window = ple_window;
4632 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4633 }
4634
c3707958
XG		 4635 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4636 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4637 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4638
9581d442
AK		 4639 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4640 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4641 vmx_set_constant_host_state(vmx);
05b3e0c2 4642#ifdef CONFIG_X86_64
6aa8b732
AK		 4643 rdmsrl(MSR_FS_BASE, a);
4644 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4645 rdmsrl(MSR_GS_BASE, a);
4646 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4647#else
4648 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4649 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4650#endif
4651
2cc51560
ED		 4652 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4653 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4654 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4655 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4656 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4657
468d472f 4658 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4659 u32 msr_low, msr_high;
4660 u64 host_pat;
468d472f
SY		 4661 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4662 host_pat = msr_low | ((u64) msr_high << 32);
4663 /* Write the default value follow host pat */
4664 vmcs_write64(GUEST_IA32_PAT, host_pat);
4665 /* Keep arch.pat sync with GUEST_IA32_PAT */
4666 vmx->vcpu.arch.pat = host_pat;
4667 }
4668
03916db9 4669 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4670 u32 index = vmx_msr_index[i];
4671 u32 data_low, data_high;
a2fa3e9f 4672 int j = vmx->nmsrs;
6aa8b732
AK		 4673
4674 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4675 continue;
432bd6cb
AK		 4676 if (wrmsr_safe(index, data_low, data_high) < 0)
4677 continue;
26bb0981
AK		 4678 vmx->guest_msrs[j].index = i;
4679 vmx->guest_msrs[j].data = 0;
d5696725 4680 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4681 ++vmx->nmsrs;
6aa8b732 4682 }
6aa8b732 4683
2961e876
GN		 4684
4685 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4686
4687 /* 22.2.1, 20.8.1 */
2961e876 4688 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4689
e00c8cf2 4690 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4691 set_cr4_guest_host_mask(vmx);
e00c8cf2 4692
f53cd63c
WL		 4693 if (vmx_xsaves_supported())
4694 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4695
e00c8cf2
AK		 4696 return 0;
4697}
4698
57f252f2 4699static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4700{
4701 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4702 struct msr_data apic_base_msr;
e00c8cf2 4703
7ffd92c5 4704 vmx->rmode.vm86_active = 0;
e00c8cf2 4705
3b86cd99
JK		 4706 vmx->soft_vnmi_blocked = 0;
4707
ad312c7c 4708 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4709 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4710 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4711 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4712 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4713 apic_base_msr.host_initiated = true;
4714 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4715
2fb92db1
AK		 4716 vmx_segment_cache_clear(vmx);
4717
5706be0d 4718 seg_setup(VCPU_SREG_CS);
66450a21 4719 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4720 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4721
4722 seg_setup(VCPU_SREG_DS);
4723 seg_setup(VCPU_SREG_ES);
4724 seg_setup(VCPU_SREG_FS);
4725 seg_setup(VCPU_SREG_GS);
4726 seg_setup(VCPU_SREG_SS);
4727
4728 vmcs_write16(GUEST_TR_SELECTOR, 0);
4729 vmcs_writel(GUEST_TR_BASE, 0);
4730 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4731 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4732
4733 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4734 vmcs_writel(GUEST_LDTR_BASE, 0);
4735 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4736 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4737
4738 vmcs_write32(GUEST_SYSENTER_CS, 0);
4739 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4740 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4741
4742 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4743 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4744
e00c8cf2
AK		 4745 vmcs_writel(GUEST_GDTR_BASE, 0);
4746 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4747
4748 vmcs_writel(GUEST_IDTR_BASE, 0);
4749 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4750
443381a8 4751 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4752 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4753 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4754
e00c8cf2
AK		 4755 /* Special registers */
4756 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4757
4758 setup_msrs(vmx);
4759
6aa8b732
AK		 4760 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4761
f78e0e2e
SY		 4762 if (cpu_has_vmx_tpr_shadow()) {
4763 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4764 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4765 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4766 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4767 vmcs_write32(TPR_THRESHOLD, 0);
4768 }
4769
a73896cb 4770 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4771
01e439be
YZ		 4772 if (vmx_vm_has_apicv(vcpu->kvm))
4773 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4774
2384d2b3
SY		 4775 if (vmx->vpid != 0)
4776 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4777
fa40052c 4778 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4779 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4780 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4781 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4782 vmx_fpu_activate(&vmx->vcpu);
4783 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4784
b9d762fa 4785 vpid_sync_context(vmx);
6aa8b732
AK		 4786}
4787
b6f1250e
NHE		 4788/*
4789 * In nested virtualization, check if L1 asked to exit on external interrupts.
4790 * For most existing hypervisors, this will always return true.
4791 */
4792static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4793{
4794 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4795 PIN_BASED_EXT_INTR_MASK;
4796}
4797
77b0f5d6
BD		 4798/*
4799 * In nested virtualization, check if L1 has set
4800 * VM_EXIT_ACK_INTR_ON_EXIT
4801 */
4802static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4803{
4804 return get_vmcs12(vcpu)->vm_exit_controls &
4805 VM_EXIT_ACK_INTR_ON_EXIT;
4806}
4807
ea8ceb83
JK		 4808static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4809{
4810 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4811 PIN_BASED_NMI_EXITING;
4812}
4813
c9a7953f 4814static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4815{
4816 u32 cpu_based_vm_exec_control;
730dca42 4817
3b86cd99
JK		 4818 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4819 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4820 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4821}
4822
c9a7953f 4823static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4824{
4825 u32 cpu_based_vm_exec_control;
4826
c9a7953f
JK		 4827 if (!cpu_has_virtual_nmis() ||
4828 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4829 enable_irq_window(vcpu);
4830 return;
4831 }
3b86cd99
JK		 4832
4833 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4834 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4835 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4836}
4837
66fd3f7f 4838static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4839{
9c8cba37 4840 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4841 uint32_t intr;
4842 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4843
229456fc 4844 trace_kvm_inj_virq(irq);
2714d1d3 4845
fa89a817 4846 ++vcpu->stat.irq_injections;
7ffd92c5 4847 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4848 int inc_eip = 0;
4849 if (vcpu->arch.interrupt.soft)
4850 inc_eip = vcpu->arch.event_exit_inst_len;
4851 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4852 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4853 return;
4854 }
66fd3f7f
GN		 4855 intr = irq | INTR_INFO_VALID_MASK;
4856 if (vcpu->arch.interrupt.soft) {
4857 intr |= INTR_TYPE_SOFT_INTR;
4858 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4859 vmx->vcpu.arch.event_exit_inst_len);
4860 } else
4861 intr |= INTR_TYPE_EXT_INTR;
4862 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4863}
4864
f08864b4
SY		 4865static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4866{
66a5a347
JK		 4867 struct vcpu_vmx *vmx = to_vmx(vcpu);
4868
0b6ac343
NHE		 4869 if (is_guest_mode(vcpu))
4870 return;
4871
3b86cd99
JK		 4872 if (!cpu_has_virtual_nmis()) {
4873 /*
4874 * Tracking the NMI-blocked state in software is built upon
4875 * finding the next open IRQ window. This, in turn, depends on
4876 * well-behaving guests: They have to keep IRQs disabled at
4877 * least as long as the NMI handler runs. Otherwise we may
4878 * cause NMI nesting, maybe breaking the guest. But as this is
4879 * highly unlikely, we can live with the residual risk.
4880 */
4881 vmx->soft_vnmi_blocked = 1;
4882 vmx->vnmi_blocked_time = 0;
4883 }
4884
487b391d 4885 ++vcpu->stat.nmi_injections;
9d58b931 4886 vmx->nmi_known_unmasked = false;
7ffd92c5 4887 if (vmx->rmode.vm86_active) {
71f9833b 4888 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4889 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4890 return;
4891 }
f08864b4
SY		 4892 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4893 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4894}
4895
3cfc3092
JK		 4896static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4897{
4898 if (!cpu_has_virtual_nmis())
4899 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4900 if (to_vmx(vcpu)->nmi_known_unmasked)
4901 return false;
c332c83a 4902 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4903}
4904
4905static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4906{
4907 struct vcpu_vmx *vmx = to_vmx(vcpu);
4908
4909 if (!cpu_has_virtual_nmis()) {
4910 if (vmx->soft_vnmi_blocked != masked) {
4911 vmx->soft_vnmi_blocked = masked;
4912 vmx->vnmi_blocked_time = 0;
4913 }
4914 } else {
9d58b931 4915 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4916 if (masked)
4917 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4918 GUEST_INTR_STATE_NMI);
4919 else
4920 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4921 GUEST_INTR_STATE_NMI);
4922 }
4923}
4924
2505dc9f
JK		 4925static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4926{
b6b8a145
JK		 4927 if (to_vmx(vcpu)->nested.nested_run_pending)
4928 return 0;
ea8ceb83 4929
2505dc9f
JK		 4930 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4931 return 0;
4932
4933 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4934 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4935 | GUEST_INTR_STATE_NMI));
4936}
4937
78646121
GN		 4938static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4939{
b6b8a145
JK		 4940 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4941 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4942 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4943 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4944}
4945
cbc94022
IE		 4946static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4947{
4948 int ret;
4949 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4950 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4951 .guest_phys_addr = addr,
4952 .memory_size = PAGE_SIZE * 3,
4953 .flags = 0,
4954 };
4955
47ae31e2 4956 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4957 if (ret)
4958 return ret;
bfc6d222 4959 kvm->arch.tss_addr = addr;
1f755a82 4960 return init_rmode_tss(kvm);
cbc94022
IE		 4961}
4962
0ca1b4f4 4963static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4964{
77ab6db0 4965 switch (vec) {
77ab6db0 4966 case BP_VECTOR:
c573cd22
JK		 4967 /*
4968 * Update instruction length as we may reinject the exception
4969 * from user space while in guest debugging mode.
4970 */
4971 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4972 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4973 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4974 return false;
4975 /* fall through */
4976 case DB_VECTOR:
4977 if (vcpu->guest_debug &
4978 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4979 return false;
d0bfb940
JK		 4980 /* fall through */
4981 case DE_VECTOR:
77ab6db0
JK		 4982 case OF_VECTOR:
4983 case BR_VECTOR:
4984 case UD_VECTOR:
4985 case DF_VECTOR:
4986 case SS_VECTOR:
4987 case GP_VECTOR:
4988 case MF_VECTOR:
0ca1b4f4
GN		 4989 return true;
4990 break;
77ab6db0 4991 }
0ca1b4f4
GN		 4992 return false;
4993}
4994
4995static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4996 int vec, u32 err_code)
4997{
4998 /*
4999 * Instruction with address size override prefix opcode 0x67
5000 * Cause the #SS fault with 0 error code in VM86 mode.
5001 */
5002 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5003 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5004 if (vcpu->arch.halt_request) {
5005 vcpu->arch.halt_request = 0;
5006 return kvm_emulate_halt(vcpu);
5007 }
5008 return 1;
5009 }
5010 return 0;
5011 }
5012
5013 /*
5014 * Forward all other exceptions that are valid in real mode.
5015 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5016 * the required debugging infrastructure rework.
5017 */
5018 kvm_queue_exception(vcpu, vec);
5019 return 1;
6aa8b732
AK		 5020}
5021
a0861c02
AK		 5022/*
5023 * Trigger machine check on the host. We assume all the MSRs are already set up
5024 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5025 * We pass a fake environment to the machine check handler because we want
5026 * the guest to be always treated like user space, no matter what context
5027 * it used internally.
5028 */
5029static void kvm_machine_check(void)
5030{
5031#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5032 struct pt_regs regs = {
5033 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5034 .flags = X86_EFLAGS_IF,
5035 };
5036
5037 do_machine_check(&regs, 0);
5038#endif
5039}
5040
851ba692 5041static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5042{
5043 /* already handled by vcpu_run */
5044 return 1;
5045}
5046
851ba692 5047static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5048{
1155f76a 5049 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5050 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5051 u32 intr_info, ex_no, error_code;
42dbaa5a 5052 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5053 u32 vect_info;
5054 enum emulation_result er;
5055
1155f76a 5056 vect_info = vmx->idt_vectoring_info;
88786475 5057 intr_info = vmx->exit_intr_info;
6aa8b732 5058
a0861c02 5059 if (is_machine_check(intr_info))
851ba692 5060 return handle_machine_check(vcpu);
a0861c02 5061
e4a41889 5062 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5063 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5064
5065 if (is_no_device(intr_info)) {
5fd86fcf 5066 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5067 return 1;
5068 }
5069
7aa81cc0 5070 if (is_invalid_opcode(intr_info)) {
51d8b661 5071 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5072 if (er != EMULATE_DONE)
7ee5d940 5073 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5074 return 1;
5075 }
5076
6aa8b732 5077 error_code = 0;
2e11384c 5078 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5079 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5080
5081 /*
5082 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5083 * MMIO, it is better to report an internal error.
5084 * See the comments in vmx_handle_exit.
5085 */
5086 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5087 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5088 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5089 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5090 vcpu->run->internal.ndata = 2;
5091 vcpu->run->internal.data[0] = vect_info;
5092 vcpu->run->internal.data[1] = intr_info;
5093 return 0;
5094 }
5095
6aa8b732 5096 if (is_page_fault(intr_info)) {
1439442c 5097 /* EPT won't cause page fault directly */
cf3ace79 5098 BUG_ON(enable_ept);
6aa8b732 5099 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5100 trace_kvm_page_fault(cr2, error_code);
5101
3298b75c 5102 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5103 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5104 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5105 }
5106
d0bfb940 5107 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5108
5109 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5110 return handle_rmode_exception(vcpu, ex_no, error_code);
5111
42dbaa5a
JK		 5112 switch (ex_no) {
5113 case DB_VECTOR:
5114 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5115 if (!(vcpu->guest_debug &
5116 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5117 vcpu->arch.dr6 &= ~15;
6f43ed01 5118 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5119 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5120 skip_emulated_instruction(vcpu);
5121
42dbaa5a
JK		 5122 kvm_queue_exception(vcpu, DB_VECTOR);
5123 return 1;
5124 }
5125 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5126 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5127 /* fall through */
5128 case BP_VECTOR:
c573cd22
JK		 5129 /*
5130 * Update instruction length as we may reinject #BP from
5131 * user space while in guest debugging mode. Reading it for
5132 * #DB as well causes no harm, it is not used in that case.
5133 */
5134 vmx->vcpu.arch.event_exit_inst_len =
5135 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5136 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5137 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5138 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5139 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5140 break;
5141 default:
d0bfb940
JK		 5142 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5143 kvm_run->ex.exception = ex_no;
5144 kvm_run->ex.error_code = error_code;
42dbaa5a 5145 break;
6aa8b732 5146 }
6aa8b732
AK		 5147 return 0;
5148}
5149
851ba692 5150static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5151{
1165f5fe 5152 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5153 return 1;
5154}
5155
851ba692 5156static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5157{
851ba692 5158 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5159 return 0;
5160}
6aa8b732 5161
851ba692 5162static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5163{
bfdaab09 5164 unsigned long exit_qualification;
34c33d16 5165 int size, in, string;
039576c0 5166 unsigned port;
6aa8b732 5167
bfdaab09 5168 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5169 string = (exit_qualification & 16) != 0;
cf8f70bf 5170 in = (exit_qualification & 8) != 0;
e70669ab 5171
cf8f70bf 5172 ++vcpu->stat.io_exits;
e70669ab 5173
cf8f70bf 5174 if (string || in)
51d8b661 5175 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5176
cf8f70bf
GN		 5177 port = exit_qualification >> 16;
5178 size = (exit_qualification & 7) + 1;
e93f36bc 5179 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5180
5181 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5182}
5183
102d8325
IM		 5184static void
5185vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5186{
5187 /*
5188 * Patch in the VMCALL instruction:
5189 */
5190 hypercall[0] = 0x0f;
5191 hypercall[1] = 0x01;
5192 hypercall[2] = 0xc1;
102d8325
IM		 5193}
5194
b9c237bb 5195static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5196{
5197 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5198 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5199
b9c237bb 5200 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5201 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5202 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5203 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5204 return (val & always_on) == always_on;
5205}
5206
0fa06071 5207/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5208static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5209{
eeadf9e7 5210 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5211 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5212 unsigned long orig_val = val;
5213
eeadf9e7
NHE		 5214 /*
5215 * We get here when L2 changed cr0 in a way that did not change
5216 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5217 * but did change L0 shadowed bits. So we first calculate the
5218 * effective cr0 value that L1 would like to write into the
5219 * hardware. It consists of the L2-owned bits from the new
5220 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5221 */
1a0d74e6
JK		 5222 val = (val & ~vmcs12->cr0_guest_host_mask) |
5223 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5224
b9c237bb 5225 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5226 return 1;
1a0d74e6
JK		 5227
5228 if (kvm_set_cr0(vcpu, val))
5229 return 1;
5230 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5231 return 0;
1a0d74e6
JK		 5232 } else {
5233 if (to_vmx(vcpu)->nested.vmxon &&
5234 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5235 return 1;
eeadf9e7 5236 return kvm_set_cr0(vcpu, val);
1a0d74e6 5237 }
eeadf9e7
NHE		 5238}
5239
5240static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5241{
5242 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5243 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5244 unsigned long orig_val = val;
5245
5246 /* analogously to handle_set_cr0 */
5247 val = (val & ~vmcs12->cr4_guest_host_mask) |
5248 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5249 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5250 return 1;
1a0d74e6 5251 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5252 return 0;
5253 } else
5254 return kvm_set_cr4(vcpu, val);
5255}
5256
5257/* called to set cr0 as approriate for clts instruction exit. */
5258static void handle_clts(struct kvm_vcpu *vcpu)
5259{
5260 if (is_guest_mode(vcpu)) {
5261 /*
5262 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5263 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5264 * just pretend it's off (also in arch.cr0 for fpu_activate).
5265 */
5266 vmcs_writel(CR0_READ_SHADOW,
5267 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5268 vcpu->arch.cr0 &= ~X86_CR0_TS;
5269 } else
5270 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5271}
5272
851ba692 5273static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5274{
229456fc 5275 unsigned long exit_qualification, val;
6aa8b732
AK		 5276 int cr;
5277 int reg;
49a9b07e 5278 int err;
6aa8b732 5279
bfdaab09 5280 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5281 cr = exit_qualification & 15;
5282 reg = (exit_qualification >> 8) & 15;
5283 switch ((exit_qualification >> 4) & 3) {
5284 case 0: /* mov to cr */
1e32c079 5285 val = kvm_register_readl(vcpu, reg);
229456fc 5286 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5287 switch (cr) {
5288 case 0:
eeadf9e7 5289 err = handle_set_cr0(vcpu, val);
db8fcefa 5290 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5291 return 1;
5292 case 3:
2390218b 5293 err = kvm_set_cr3(vcpu, val);
db8fcefa 5294 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5295 return 1;
5296 case 4:
eeadf9e7 5297 err = handle_set_cr4(vcpu, val);
db8fcefa 5298 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5299 return 1;
0a5fff19
GN		 5300 case 8: {
5301 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5302 u8 cr8 = (u8)val;
eea1cff9 5303 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5304 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5305 if (irqchip_in_kernel(vcpu->kvm))
5306 return 1;
5307 if (cr8_prev <= cr8)
5308 return 1;
851ba692 5309 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5310 return 0;
5311 }
4b8073e4 5312 }
6aa8b732 5313 break;
25c4c276 5314 case 2: /* clts */
eeadf9e7 5315 handle_clts(vcpu);
4d4ec087 5316 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5317 skip_emulated_instruction(vcpu);
6b52d186 5318 vmx_fpu_activate(vcpu);
25c4c276 5319 return 1;
6aa8b732
AK		 5320 case 1: /*mov from cr*/
5321 switch (cr) {
5322 case 3:
9f8fe504
AK		 5323 val = kvm_read_cr3(vcpu);
5324 kvm_register_write(vcpu, reg, val);
5325 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5326 skip_emulated_instruction(vcpu);
5327 return 1;
5328 case 8:
229456fc
MT		 5329 val = kvm_get_cr8(vcpu);
5330 kvm_register_write(vcpu, reg, val);
5331 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5332 skip_emulated_instruction(vcpu);
5333 return 1;
5334 }
5335 break;
5336 case 3: /* lmsw */
a1f83a74 5337 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5338 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5339 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5340
5341 skip_emulated_instruction(vcpu);
5342 return 1;
5343 default:
5344 break;
5345 }
851ba692 5346 vcpu->run->exit_reason = 0;
a737f256 5347 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5348 (int)(exit_qualification >> 4) & 3, cr);
5349 return 0;
5350}
5351
851ba692 5352static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5353{
bfdaab09 5354 unsigned long exit_qualification;
16f8a6f9
NA		 5355 int dr, dr7, reg;
5356
5357 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5358 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5359
5360 /* First, if DR does not exist, trigger UD */
5361 if (!kvm_require_dr(vcpu, dr))
5362 return 1;
6aa8b732 5363
f2483415 5364 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5365 if (!kvm_require_cpl(vcpu, 0))
5366 return 1;
16f8a6f9
NA		 5367 dr7 = vmcs_readl(GUEST_DR7);
5368 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5369 /*
5370 * As the vm-exit takes precedence over the debug trap, we
5371 * need to emulate the latter, either for the host or the
5372 * guest debugging itself.
5373 */
5374 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5375 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5376 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5377 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5378 vcpu->run->debug.arch.exception = DB_VECTOR;
5379 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5380 return 0;
5381 } else {
7305eb5d 5382 vcpu->arch.dr6 &= ~15;
6f43ed01 5383 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5384 kvm_queue_exception(vcpu, DB_VECTOR);
5385 return 1;
5386 }
5387 }
5388
81908bf4
PB		 5389 if (vcpu->guest_debug == 0) {
5390 u32 cpu_based_vm_exec_control;
5391
5392 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5393 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5394 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5395
5396 /*
5397 * No more DR vmexits; force a reload of the debug registers
5398 * and reenter on this instruction. The next vmexit will
5399 * retrieve the full state of the debug registers.
5400 */
5401 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5402 return 1;
5403 }
5404
42dbaa5a
JK		 5405 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5406 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5407 unsigned long val;
4c4d563b
JK		 5408
5409 if (kvm_get_dr(vcpu, dr, &val))
5410 return 1;
5411 kvm_register_write(vcpu, reg, val);
020df079 5412 } else
5777392e 5413 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5414 return 1;
5415
6aa8b732
AK		 5416 skip_emulated_instruction(vcpu);
5417 return 1;
5418}
5419
73aaf249
JK		 5420static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5421{
5422 return vcpu->arch.dr6;
5423}
5424
5425static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5426{
5427}
5428
81908bf4
PB		 5429static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5430{
5431 u32 cpu_based_vm_exec_control;
5432
5433 get_debugreg(vcpu->arch.db[0], 0);
5434 get_debugreg(vcpu->arch.db[1], 1);
5435 get_debugreg(vcpu->arch.db[2], 2);
5436 get_debugreg(vcpu->arch.db[3], 3);
5437 get_debugreg(vcpu->arch.dr6, 6);
5438 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5439
5440 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5441
5442 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5443 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5444 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5445}
5446
020df079
GN		 5447static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5448{
5449 vmcs_writel(GUEST_DR7, val);
5450}
5451
851ba692 5452static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5453{
06465c5a
AK		 5454 kvm_emulate_cpuid(vcpu);
5455 return 1;
6aa8b732
AK		 5456}
5457
851ba692 5458static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5459{
ad312c7c 5460 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5461 u64 data;
5462
5463 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5464 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5465 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5466 return 1;
5467 }
5468
229456fc 5469 trace_kvm_msr_read(ecx, data);
2714d1d3 5470
6aa8b732 5471 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5472 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5473 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5474 skip_emulated_instruction(vcpu);
5475 return 1;
5476}
5477
851ba692 5478static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5479{
8fe8ab46 5480 struct msr_data msr;
ad312c7c
ZX		 5481 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5482 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5483 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5484
8fe8ab46
WA		 5485 msr.data = data;
5486 msr.index = ecx;
5487 msr.host_initiated = false;
854e8bb1 5488 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5489 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5490 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5491 return 1;
5492 }
5493
59200273 5494 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5495 skip_emulated_instruction(vcpu);
5496 return 1;
5497}
5498
851ba692 5499static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5500{
3842d135 5501 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5502 return 1;
5503}
5504
851ba692 5505static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5506{
85f455f7
ED		 5507 u32 cpu_based_vm_exec_control;
5508
5509 /* clear pending irq */
5510 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5511 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5512 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5513
3842d135
AK		 5514 kvm_make_request(KVM_REQ_EVENT, vcpu);
5515
a26bf12a 5516 ++vcpu->stat.irq_window_exits;
2714d1d3 5517
c1150d8c
DL		 5518 /*
5519 * If the user space waits to inject interrupts, exit as soon as
5520 * possible
5521 */
8061823a 5522 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5523 vcpu->run->request_interrupt_window &&
8061823a 5524 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5525 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5526 return 0;
5527 }
6aa8b732
AK		 5528 return 1;
5529}
5530
851ba692 5531static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5532{
5533 skip_emulated_instruction(vcpu);
d3bef15f 5534 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5535}
5536
851ba692 5537static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5538{
510043da 5539 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5540 kvm_emulate_hypercall(vcpu);
5541 return 1;
c21415e8
IM		 5542}
5543
ec25d5e6
GN		 5544static int handle_invd(struct kvm_vcpu *vcpu)
5545{
51d8b661 5546 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5547}
5548
851ba692 5549static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5550{
f9c617f6 5551 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5552
5553 kvm_mmu_invlpg(vcpu, exit_qualification);
5554 skip_emulated_instruction(vcpu);
5555 return 1;
5556}
5557
fee84b07
AK		 5558static int handle_rdpmc(struct kvm_vcpu *vcpu)
5559{
5560 int err;
5561
5562 err = kvm_rdpmc(vcpu);
5563 kvm_complete_insn_gp(vcpu, err);
5564
5565 return 1;
5566}
5567
851ba692 5568static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5569{
5570 skip_emulated_instruction(vcpu);
f5f48ee1 5571 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5572 return 1;
5573}
5574
2acf923e
DC		 5575static int handle_xsetbv(struct kvm_vcpu *vcpu)
5576{
5577 u64 new_bv = kvm_read_edx_eax(vcpu);
5578 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5579
5580 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5581 skip_emulated_instruction(vcpu);
5582 return 1;
5583}
5584
f53cd63c
WL		 5585static int handle_xsaves(struct kvm_vcpu *vcpu)
5586{
5587 skip_emulated_instruction(vcpu);
5588 WARN(1, "this should never happen\n");
5589 return 1;
5590}
5591
5592static int handle_xrstors(struct kvm_vcpu *vcpu)
5593{
5594 skip_emulated_instruction(vcpu);
5595 WARN(1, "this should never happen\n");
5596 return 1;
5597}
5598
851ba692 5599static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5600{
58fbbf26
KT		 5601 if (likely(fasteoi)) {
5602 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5603 int access_type, offset;
5604
5605 access_type = exit_qualification & APIC_ACCESS_TYPE;
5606 offset = exit_qualification & APIC_ACCESS_OFFSET;
5607 /*
5608 * Sane guest uses MOV to write EOI, with written value
5609 * not cared. So make a short-circuit here by avoiding
5610 * heavy instruction emulation.
5611 */
5612 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5613 (offset == APIC_EOI)) {
5614 kvm_lapic_set_eoi(vcpu);
5615 skip_emulated_instruction(vcpu);
5616 return 1;
5617 }
5618 }
51d8b661 5619 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5620}
5621
c7c9c56c
YZ		 5622static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5623{
5624 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5625 int vector = exit_qualification & 0xff;
5626
5627 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5628 kvm_apic_set_eoi_accelerated(vcpu, vector);
5629 return 1;
5630}
5631
83d4c286
YZ		 5632static int handle_apic_write(struct kvm_vcpu *vcpu)
5633{
5634 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5635 u32 offset = exit_qualification & 0xfff;
5636
5637 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5638 kvm_apic_write_nodecode(vcpu, offset);
5639 return 1;
5640}
5641
851ba692 5642static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5643{
60637aac 5644 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5645 unsigned long exit_qualification;
e269fb21
JK		 5646 bool has_error_code = false;
5647 u32 error_code = 0;
37817f29 5648 u16 tss_selector;
7f3d35fd 5649 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5650
5651 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5652 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5653 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5654
5655 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5656
5657 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5658 if (reason == TASK_SWITCH_GATE && idt_v) {
5659 switch (type) {
5660 case INTR_TYPE_NMI_INTR:
5661 vcpu->arch.nmi_injected = false;
654f06fc 5662 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5663 break;
5664 case INTR_TYPE_EXT_INTR:
66fd3f7f 5665 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5666 kvm_clear_interrupt_queue(vcpu);
5667 break;
5668 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5669 if (vmx->idt_vectoring_info &
5670 VECTORING_INFO_DELIVER_CODE_MASK) {
5671 has_error_code = true;
5672 error_code =
5673 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5674 }
5675 /* fall through */
64a7ec06
GN		 5676 case INTR_TYPE_SOFT_EXCEPTION:
5677 kvm_clear_exception_queue(vcpu);
5678 break;
5679 default:
5680 break;
5681 }
60637aac 5682 }
37817f29
IE		 5683 tss_selector = exit_qualification;
5684
64a7ec06
GN		 5685 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5686 type != INTR_TYPE_EXT_INTR &&
5687 type != INTR_TYPE_NMI_INTR))
5688 skip_emulated_instruction(vcpu);
5689
7f3d35fd
KW		 5690 if (kvm_task_switch(vcpu, tss_selector,
5691 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5692 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5693 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5694 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5695 vcpu->run->internal.ndata = 0;
42dbaa5a 5696 return 0;
acb54517 5697 }
42dbaa5a
JK		 5698
5699 /* clear all local breakpoint enable flags */
0e8a0996 5700 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5701
5702 /*
5703 * TODO: What about debug traps on tss switch?
5704 * Are we supposed to inject them and update dr6?
5705 */
5706
5707 return 1;
37817f29
IE		 5708}
5709
851ba692 5710static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5711{
f9c617f6 5712 unsigned long exit_qualification;
1439442c 5713 gpa_t gpa;
4f5982a5 5714 u32 error_code;
1439442c 5715 int gla_validity;
1439442c 5716
f9c617f6 5717 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5718
1439442c
SY		 5719 gla_validity = (exit_qualification >> 7) & 0x3;
5720 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5721 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5722 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5723 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5724 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5725 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5726 (long unsigned int)exit_qualification);
851ba692
AK		 5727 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5728 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5729 return 0;
1439442c
SY		 5730 }
5731
0be9c7a8
GN		 5732 /*
5733 * EPT violation happened while executing iret from NMI,
5734 * "blocked by NMI" bit has to be set before next VM entry.
5735 * There are errata that may cause this bit to not be set:
5736 * AAK134, BY25.
5737 */
bcd1c294
GN		 5738 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5739 cpu_has_virtual_nmis() &&
5740 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5741 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5742
1439442c 5743 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5744 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5745
5746 /* It is a write fault? */
81ed33e4 5747 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5748 /* It is a fetch fault? */
81ed33e4 5749 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5750 /* ept page table is present? */
81ed33e4 5751 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5752
25d92081
YZ		 5753 vcpu->arch.exit_qualification = exit_qualification;
5754
4f5982a5 5755 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5756}
5757
68f89400
MT		 5758static u64 ept_rsvd_mask(u64 spte, int level)
5759{
5760 int i;
5761 u64 mask = 0;
5762
5763 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5764 mask |= (1ULL << i);
5765
a32e8459 5766 if (level == 4)
68f89400
MT		 5767 /* bits 7:3 reserved */
5768 mask |= 0xf8;
a32e8459
WL		 5769 else if (spte & (1ULL << 7))
5770 /*
5771 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5772 * level == 1 if the hypervisor is using the ignored bit 7.
5773 */
5774 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5775 else if (level > 1)
5776 /* bits 6:3 reserved */
5777 mask |= 0x78;
68f89400
MT		 5778
5779 return mask;
5780}
5781
5782static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5783 int level)
5784{
5785 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5786
5787 /* 010b (write-only) */
5788 WARN_ON((spte & 0x7) == 0x2);
5789
5790 /* 110b (write/execute) */
5791 WARN_ON((spte & 0x7) == 0x6);
5792
5793 /* 100b (execute-only) and value not supported by logical processor */
5794 if (!cpu_has_vmx_ept_execute_only())
5795 WARN_ON((spte & 0x7) == 0x4);
5796
5797 /* not 000b */
5798 if ((spte & 0x7)) {
5799 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5800
5801 if (rsvd_bits != 0) {
5802 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5803 __func__, rsvd_bits);
5804 WARN_ON(1);
5805 }
5806
a32e8459
WL		 5807 /* bits 5:3 are _not_ reserved for large page or leaf page */
5808 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5809 u64 ept_mem_type = (spte & 0x38) >> 3;
5810
5811 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5812 ept_mem_type == 7) {
5813 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5814 __func__, ept_mem_type);
5815 WARN_ON(1);
5816 }
5817 }
5818 }
5819}
5820
851ba692 5821static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5822{
5823 u64 sptes[4];
ce88decf 5824 int nr_sptes, i, ret;
68f89400
MT		 5825 gpa_t gpa;
5826
5827 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5828 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5829 skip_emulated_instruction(vcpu);
5830 return 1;
5831 }
68f89400 5832
ce88decf 5833 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5834 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5835 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5836 EMULATE_DONE;
f8f55942
XG		 5837
5838 if (unlikely(ret == RET_MMIO_PF_INVALID))
5839 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5840
b37fbea6 5841 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5842 return 1;
5843
5844 /* It is the real ept misconfig */
68f89400
MT		 5845 printk(KERN_ERR "EPT: Misconfiguration.\n");
5846 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5847
5848 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5849
5850 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5851 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5852
851ba692
AK		 5853 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5854 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5855
5856 return 0;
5857}
5858
851ba692 5859static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5860{
5861 u32 cpu_based_vm_exec_control;
5862
5863 /* clear pending NMI */
5864 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5865 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5866 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5867 ++vcpu->stat.nmi_window_exits;
3842d135 5868 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5869
5870 return 1;
5871}
5872
80ced186 5873static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5874{
8b3079a5
AK		 5875 struct vcpu_vmx *vmx = to_vmx(vcpu);
5876 enum emulation_result err = EMULATE_DONE;
80ced186 5877 int ret = 1;
49e9d557
AK		 5878 u32 cpu_exec_ctrl;
5879 bool intr_window_requested;
b8405c18 5880 unsigned count = 130;
49e9d557
AK		 5881
5882 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5883 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5884
98eb2f8b 5885 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5886 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5887 return handle_interrupt_window(&vmx->vcpu);
5888
de87dcdd
AK		 5889 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5890 return 1;
5891
991eebf9 5892 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5893
ac0a48c3 5894 if (err == EMULATE_USER_EXIT) {
94452b9e 5895 ++vcpu->stat.mmio_exits;
80ced186
MG		 5896 ret = 0;
5897 goto out;
5898 }
1d5a4d9b 5899
de5f70e0
AK		 5900 if (err != EMULATE_DONE) {
5901 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5902 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5903 vcpu->run->internal.ndata = 0;
6d77dbfc 5904 return 0;
de5f70e0 5905 }
ea953ef0 5906
8d76c49e
GN		 5907 if (vcpu->arch.halt_request) {
5908 vcpu->arch.halt_request = 0;
5909 ret = kvm_emulate_halt(vcpu);
5910 goto out;
5911 }
5912
ea953ef0 5913 if (signal_pending(current))
80ced186 5914 goto out;
ea953ef0
MG		 5915 if (need_resched())
5916 schedule();
5917 }
5918
80ced186
MG		 5919out:
5920 return ret;
ea953ef0
MG		 5921}
5922
b4a2d31d
RK		 5923static int __grow_ple_window(int val)
5924{
5925 if (ple_window_grow < 1)
5926 return ple_window;
5927
5928 val = min(val, ple_window_actual_max);
5929
5930 if (ple_window_grow < ple_window)
5931 val *= ple_window_grow;
5932 else
5933 val += ple_window_grow;
5934
5935 return val;
5936}
5937
5938static int __shrink_ple_window(int val, int modifier, int minimum)
5939{
5940 if (modifier < 1)
5941 return ple_window;
5942
5943 if (modifier < ple_window)
5944 val /= modifier;
5945 else
5946 val -= modifier;
5947
5948 return max(val, minimum);
5949}
5950
5951static void grow_ple_window(struct kvm_vcpu *vcpu)
5952{
5953 struct vcpu_vmx *vmx = to_vmx(vcpu);
5954 int old = vmx->ple_window;
5955
5956 vmx->ple_window = __grow_ple_window(old);
5957
5958 if (vmx->ple_window != old)
5959 vmx->ple_window_dirty = true;
7b46268d
RK		 5960
5961 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5962}
5963
5964static void shrink_ple_window(struct kvm_vcpu *vcpu)
5965{
5966 struct vcpu_vmx *vmx = to_vmx(vcpu);
5967 int old = vmx->ple_window;
5968
5969 vmx->ple_window = __shrink_ple_window(old,
5970 ple_window_shrink, ple_window);
5971
5972 if (vmx->ple_window != old)
5973 vmx->ple_window_dirty = true;
7b46268d
RK		 5974
5975 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5976}
5977
5978/*
5979 * ple_window_actual_max is computed to be one grow_ple_window() below
5980 * ple_window_max. (See __grow_ple_window for the reason.)
5981 * This prevents overflows, because ple_window_max is int.
5982 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5983 * this process.
5984 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5985 */
5986static void update_ple_window_actual_max(void)
5987{
5988 ple_window_actual_max =
5989 __shrink_ple_window(max(ple_window_max, ple_window),
5990 ple_window_grow, INT_MIN);
5991}
5992
f2c7648d
TC		 5993static __init int hardware_setup(void)
5994{
34a1cd60
TC		 5995 int r = -ENOMEM, i, msr;
5996
5997 rdmsrl_safe(MSR_EFER, &host_efer);
5998
5999 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6000 kvm_define_shared_msr(i, vmx_msr_index[i]);
6001
6002 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6003 if (!vmx_io_bitmap_a)
6004 return r;
6005
6006 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6007 if (!vmx_io_bitmap_b)
6008 goto out;
6009
6010 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6011 if (!vmx_msr_bitmap_legacy)
6012 goto out1;
6013
6014 vmx_msr_bitmap_legacy_x2apic =
6015 (unsigned long *)__get_free_page(GFP_KERNEL);
6016 if (!vmx_msr_bitmap_legacy_x2apic)
6017 goto out2;
6018
6019 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6020 if (!vmx_msr_bitmap_longmode)
6021 goto out3;
6022
6023 vmx_msr_bitmap_longmode_x2apic =
6024 (unsigned long *)__get_free_page(GFP_KERNEL);
6025 if (!vmx_msr_bitmap_longmode_x2apic)
6026 goto out4;
3af18d9c
WV		 6027
6028 if (nested) {
6029 vmx_msr_bitmap_nested =
6030 (unsigned long *)__get_free_page(GFP_KERNEL);
6031 if (!vmx_msr_bitmap_nested)
6032 goto out5;
6033 }
6034
34a1cd60
TC		 6035 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6036 if (!vmx_vmread_bitmap)
3af18d9c 6037 goto out6;
34a1cd60
TC		 6038
6039 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6040 if (!vmx_vmwrite_bitmap)
3af18d9c 6041 goto out7;
34a1cd60
TC		 6042
6043 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6044 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6045
6046 /*
6047 * Allow direct access to the PC debug port (it is often used for I/O
6048 * delays, but the vmexits simply slow things down).
6049 */
6050 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6051 clear_bit(0x80, vmx_io_bitmap_a);
6052
6053 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6054
6055 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6056 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6057 if (nested)
6058 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6059
34a1cd60
TC		 6060 if (setup_vmcs_config(&vmcs_config) < 0) {
6061 r = -EIO;
3af18d9c 6062 goto out8;
baa03522 6063 }
f2c7648d
TC		 6064
6065 if (boot_cpu_has(X86_FEATURE_NX))
6066 kvm_enable_efer_bits(EFER_NX);
6067
6068 if (!cpu_has_vmx_vpid())
6069 enable_vpid = 0;
6070 if (!cpu_has_vmx_shadow_vmcs())
6071 enable_shadow_vmcs = 0;
6072 if (enable_shadow_vmcs)
6073 init_vmcs_shadow_fields();
6074
6075 if (!cpu_has_vmx_ept() ||
6076 !cpu_has_vmx_ept_4levels()) {
6077 enable_ept = 0;
6078 enable_unrestricted_guest = 0;
6079 enable_ept_ad_bits = 0;
6080 }
6081
6082 if (!cpu_has_vmx_ept_ad_bits())
6083 enable_ept_ad_bits = 0;
6084
6085 if (!cpu_has_vmx_unrestricted_guest())
6086 enable_unrestricted_guest = 0;
6087
ad15a296 6088 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6089 flexpriority_enabled = 0;
6090
ad15a296
PB		 6091 /*
6092 * set_apic_access_page_addr() is used to reload apic access
6093 * page upon invalidation. No need to do anything if not
6094 * using the APIC_ACCESS_ADDR VMCS field.
6095 */
6096 if (!flexpriority_enabled)
f2c7648d 6097 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6098
6099 if (!cpu_has_vmx_tpr_shadow())
6100 kvm_x86_ops->update_cr8_intercept = NULL;
6101
6102 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6103 kvm_disable_largepages();
6104
6105 if (!cpu_has_vmx_ple())
6106 ple_gap = 0;
6107
6108 if (!cpu_has_vmx_apicv())
6109 enable_apicv = 0;
6110
6111 if (enable_apicv)
6112 kvm_x86_ops->update_cr8_intercept = NULL;
6113 else {
6114 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6115 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6116 kvm_x86_ops->deliver_posted_interrupt = NULL;
6117 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6118 }
6119
baa03522
TC		 6120 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6121 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6122 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6123 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6124 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6125 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6126 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6127
6128 memcpy(vmx_msr_bitmap_legacy_x2apic,
6129 vmx_msr_bitmap_legacy, PAGE_SIZE);
6130 memcpy(vmx_msr_bitmap_longmode_x2apic,
6131 vmx_msr_bitmap_longmode, PAGE_SIZE);
6132
6133 if (enable_apicv) {
6134 for (msr = 0x800; msr <= 0x8ff; msr++)
6135 vmx_disable_intercept_msr_read_x2apic(msr);
6136
6137 /* According SDM, in x2apic mode, the whole id reg is used.
6138 * But in KVM, it only use the highest eight bits. Need to
6139 * intercept it */
6140 vmx_enable_intercept_msr_read_x2apic(0x802);
6141 /* TMCCT */
6142 vmx_enable_intercept_msr_read_x2apic(0x839);
6143 /* TPR */
6144 vmx_disable_intercept_msr_write_x2apic(0x808);
6145 /* EOI */
6146 vmx_disable_intercept_msr_write_x2apic(0x80b);
6147 /* SELF-IPI */
6148 vmx_disable_intercept_msr_write_x2apic(0x83f);
6149 }
6150
6151 if (enable_ept) {
6152 kvm_mmu_set_mask_ptes(0ull,
6153 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6154 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6155 0ull, VMX_EPT_EXECUTABLE_MASK);
6156 ept_set_mmio_spte_mask();
6157 kvm_enable_tdp();
6158 } else
6159 kvm_disable_tdp();
6160
6161 update_ple_window_actual_max();
6162
843e4330
KH		 6163 /*
6164 * Only enable PML when hardware supports PML feature, and both EPT
6165 * and EPT A/D bit features are enabled -- PML depends on them to work.
6166 */
6167 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6168 enable_pml = 0;
6169
6170 if (!enable_pml) {
6171 kvm_x86_ops->slot_enable_log_dirty = NULL;
6172 kvm_x86_ops->slot_disable_log_dirty = NULL;
6173 kvm_x86_ops->flush_log_dirty = NULL;
6174 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6175 }
6176
f2c7648d 6177 return alloc_kvm_area();
34a1cd60 6178
3af18d9c 6179out8:
34a1cd60 6180 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6181out7:
34a1cd60 6182 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6183out6:
6184 if (nested)
6185 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6186out5:
6187 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6188out4:
6189 free_page((unsigned long)vmx_msr_bitmap_longmode);
6190out3:
6191 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6192out2:
6193 free_page((unsigned long)vmx_msr_bitmap_legacy);
6194out1:
6195 free_page((unsigned long)vmx_io_bitmap_b);
6196out:
6197 free_page((unsigned long)vmx_io_bitmap_a);
6198
6199 return r;
f2c7648d
TC		 6200}
6201
6202static __exit void hardware_unsetup(void)
6203{
34a1cd60
TC		 6204 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6205 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6206 free_page((unsigned long)vmx_msr_bitmap_legacy);
6207 free_page((unsigned long)vmx_msr_bitmap_longmode);
6208 free_page((unsigned long)vmx_io_bitmap_b);
6209 free_page((unsigned long)vmx_io_bitmap_a);
6210 free_page((unsigned long)vmx_vmwrite_bitmap);
6211 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6212 if (nested)
6213 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6214
f2c7648d
TC		 6215 free_kvm_area();
6216}
6217
4b8d54f9
ZE		 6218/*
6219 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6220 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6221 */
9fb41ba8 6222static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6223{
b4a2d31d
RK		 6224 if (ple_gap)
6225 grow_ple_window(vcpu);
6226
4b8d54f9
ZE		 6227 skip_emulated_instruction(vcpu);
6228 kvm_vcpu_on_spin(vcpu);
6229
6230 return 1;
6231}
6232
87c00572 6233static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6234{
87c00572 6235 skip_emulated_instruction(vcpu);
59708670
SY		 6236 return 1;
6237}
6238
87c00572
GS		 6239static int handle_mwait(struct kvm_vcpu *vcpu)
6240{
6241 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6242 return handle_nop(vcpu);
6243}
6244
6245static int handle_monitor(struct kvm_vcpu *vcpu)
6246{
6247 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6248 return handle_nop(vcpu);
6249}
6250
ff2f6fe9
NHE		 6251/*
6252 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6253 * We could reuse a single VMCS for all the L2 guests, but we also want the
6254 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6255 * allows keeping them loaded on the processor, and in the future will allow
6256 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6257 * every entry if they never change.
6258 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6259 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6260 *
6261 * The following functions allocate and free a vmcs02 in this pool.
6262 */
6263
6264/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6265static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6266{
6267 struct vmcs02_list *item;
6268 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6269 if (item->vmptr == vmx->nested.current_vmptr) {
6270 list_move(&item->list, &vmx->nested.vmcs02_pool);
6271 return &item->vmcs02;
6272 }
6273
6274 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6275 /* Recycle the least recently used VMCS. */
6276 item = list_entry(vmx->nested.vmcs02_pool.prev,
6277 struct vmcs02_list, list);
6278 item->vmptr = vmx->nested.current_vmptr;
6279 list_move(&item->list, &vmx->nested.vmcs02_pool);
6280 return &item->vmcs02;
6281 }
6282
6283 /* Create a new VMCS */
0fa24ce3 6284 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6285 if (!item)
6286 return NULL;
6287 item->vmcs02.vmcs = alloc_vmcs();
6288 if (!item->vmcs02.vmcs) {
6289 kfree(item);
6290 return NULL;
6291 }
6292 loaded_vmcs_init(&item->vmcs02);
6293 item->vmptr = vmx->nested.current_vmptr;
6294 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6295 vmx->nested.vmcs02_num++;
6296 return &item->vmcs02;
6297}
6298
6299/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6300static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6301{
6302 struct vmcs02_list *item;
6303 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6304 if (item->vmptr == vmptr) {
6305 free_loaded_vmcs(&item->vmcs02);
6306 list_del(&item->list);
6307 kfree(item);
6308 vmx->nested.vmcs02_num--;
6309 return;
6310 }
6311}
6312
6313/*
6314 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6315 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6316 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6317 */
6318static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6319{
6320 struct vmcs02_list *item, *n;
4fa7734c
PB		 6321
6322 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6323 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6324 /*
6325 * Something will leak if the above WARN triggers. Better than
6326 * a use-after-free.
6327 */
6328 if (vmx->loaded_vmcs == &item->vmcs02)
6329 continue;
6330
6331 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6332 list_del(&item->list);
6333 kfree(item);
4fa7734c 6334 vmx->nested.vmcs02_num--;
ff2f6fe9 6335 }
ff2f6fe9
NHE		 6336}
6337
0658fbaa
ACL		 6338/*
6339 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6340 * set the success or error code of an emulated VMX instruction, as specified
6341 * by Vol 2B, VMX Instruction Reference, "Conventions".
6342 */
6343static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6344{
6345 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6346 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6347 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6348}
6349
6350static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6351{
6352 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6353 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6354 X86_EFLAGS_SF | X86_EFLAGS_OF))
6355 | X86_EFLAGS_CF);
6356}
6357
145c28dd 6358static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6359 u32 vm_instruction_error)
6360{
6361 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6362 /*
6363 * failValid writes the error number to the current VMCS, which
6364 * can't be done there isn't a current VMCS.
6365 */
6366 nested_vmx_failInvalid(vcpu);
6367 return;
6368 }
6369 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6370 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6371 X86_EFLAGS_SF | X86_EFLAGS_OF))
6372 | X86_EFLAGS_ZF);
6373 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6374 /*
6375 * We don't need to force a shadow sync because
6376 * VM_INSTRUCTION_ERROR is not shadowed
6377 */
6378}
145c28dd 6379
ff651cb6
WV		 6380static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6381{
6382 /* TODO: not to reset guest simply here. */
6383 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6384 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6385}
6386
f4124500
JK		 6387static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6388{
6389 struct vcpu_vmx *vmx =
6390 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6391
6392 vmx->nested.preemption_timer_expired = true;
6393 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6394 kvm_vcpu_kick(&vmx->vcpu);
6395
6396 return HRTIMER_NORESTART;
6397}
6398
19677e32
BD		 6399/*
6400 * Decode the memory-address operand of a vmx instruction, as recorded on an
6401 * exit caused by such an instruction (run by a guest hypervisor).
6402 * On success, returns 0. When the operand is invalid, returns 1 and throws
6403 * #UD or #GP.
6404 */
6405static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6406 unsigned long exit_qualification,
6407 u32 vmx_instruction_info, gva_t *ret)
6408{
6409 /*
6410 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6411 * Execution", on an exit, vmx_instruction_info holds most of the
6412 * addressing components of the operand. Only the displacement part
6413 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6414 * For how an actual address is calculated from all these components,
6415 * refer to Vol. 1, "Operand Addressing".
6416 */
6417 int scaling = vmx_instruction_info & 3;
6418 int addr_size = (vmx_instruction_info >> 7) & 7;
6419 bool is_reg = vmx_instruction_info & (1u << 10);
6420 int seg_reg = (vmx_instruction_info >> 15) & 7;
6421 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6422 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6423 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6424 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6425
6426 if (is_reg) {
6427 kvm_queue_exception(vcpu, UD_VECTOR);
6428 return 1;
6429 }
6430
6431 /* Addr = segment_base + offset */
6432 /* offset = base + [index * scale] + displacement */
6433 *ret = vmx_get_segment_base(vcpu, seg_reg);
6434 if (base_is_valid)
6435 *ret += kvm_register_read(vcpu, base_reg);
6436 if (index_is_valid)
6437 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6438 *ret += exit_qualification; /* holds the displacement */
6439
6440 if (addr_size == 1) /* 32 bit */
6441 *ret &= 0xffffffff;
6442
6443 /*
6444 * TODO: throw #GP (and return 1) in various cases that the VM*
6445 * instructions require it - e.g., offset beyond segment limit,
6446 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6447 * address, and so on. Currently these are not checked.
6448 */
6449 return 0;
6450}
6451
3573e22c
BD		 6452/*
6453 * This function performs the various checks including
6454 * - if it's 4KB aligned
6455 * - No bits beyond the physical address width are set
6456 * - Returns 0 on success or else 1
4291b588 6457 * (Intel SDM Section 30.3)
3573e22c 6458 */
4291b588
BD		 6459static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6460 gpa_t *vmpointer)
3573e22c
BD		 6461{
6462 gva_t gva;
6463 gpa_t vmptr;
6464 struct x86_exception e;
6465 struct page *page;
6466 struct vcpu_vmx *vmx = to_vmx(vcpu);
6467 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6468
6469 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6470 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6471 return 1;
6472
6473 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6474 sizeof(vmptr), &e)) {
6475 kvm_inject_page_fault(vcpu, &e);
6476 return 1;
6477 }
6478
6479 switch (exit_reason) {
6480 case EXIT_REASON_VMON:
6481 /*
6482 * SDM 3: 24.11.5
6483 * The first 4 bytes of VMXON region contain the supported
6484 * VMCS revision identifier
6485 *
6486 * Note - IA32_VMX_BASIC[48] will never be 1
6487 * for the nested case;
6488 * which replaces physical address width with 32
6489 *
6490 */
bc39c4db 6491 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6492 nested_vmx_failInvalid(vcpu);
6493 skip_emulated_instruction(vcpu);
6494 return 1;
6495 }
6496
6497 page = nested_get_page(vcpu, vmptr);
6498 if (page == NULL ||
6499 *(u32 *)kmap(page) != VMCS12_REVISION) {
6500 nested_vmx_failInvalid(vcpu);
6501 kunmap(page);
6502 skip_emulated_instruction(vcpu);
6503 return 1;
6504 }
6505 kunmap(page);
6506 vmx->nested.vmxon_ptr = vmptr;
6507 break;
4291b588 6508 case EXIT_REASON_VMCLEAR:
bc39c4db 6509 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6510 nested_vmx_failValid(vcpu,
6511 VMXERR_VMCLEAR_INVALID_ADDRESS);
6512 skip_emulated_instruction(vcpu);
6513 return 1;
6514 }
6515
6516 if (vmptr == vmx->nested.vmxon_ptr) {
6517 nested_vmx_failValid(vcpu,
6518 VMXERR_VMCLEAR_VMXON_POINTER);
6519 skip_emulated_instruction(vcpu);
6520 return 1;
6521 }
6522 break;
6523 case EXIT_REASON_VMPTRLD:
bc39c4db 6524 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6525 nested_vmx_failValid(vcpu,
6526 VMXERR_VMPTRLD_INVALID_ADDRESS);
6527 skip_emulated_instruction(vcpu);
6528 return 1;
6529 }
3573e22c 6530
4291b588
BD		 6531 if (vmptr == vmx->nested.vmxon_ptr) {
6532 nested_vmx_failValid(vcpu,
6533 VMXERR_VMCLEAR_VMXON_POINTER);
6534 skip_emulated_instruction(vcpu);
6535 return 1;
6536 }
6537 break;
3573e22c
BD		 6538 default:
6539 return 1; /* shouldn't happen */
6540 }
6541
4291b588
BD		 6542 if (vmpointer)
6543 *vmpointer = vmptr;
3573e22c
BD		 6544 return 0;
6545}
6546
ec378aee
NHE		 6547/*
6548 * Emulate the VMXON instruction.
6549 * Currently, we just remember that VMX is active, and do not save or even
6550 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6551 * do not currently need to store anything in that guest-allocated memory
6552 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6553 * argument is different from the VMXON pointer (which the spec says they do).
6554 */
6555static int handle_vmon(struct kvm_vcpu *vcpu)
6556{
6557 struct kvm_segment cs;
6558 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6559 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6560 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6561 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6562
6563 /* The Intel VMX Instruction Reference lists a bunch of bits that
6564 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6565 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6566 * Otherwise, we should fail with #UD. We test these now:
6567 */
6568 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6569 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6570 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6571 kvm_queue_exception(vcpu, UD_VECTOR);
6572 return 1;
6573 }
6574
6575 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6576 if (is_long_mode(vcpu) && !cs.l) {
6577 kvm_queue_exception(vcpu, UD_VECTOR);
6578 return 1;
6579 }
6580
6581 if (vmx_get_cpl(vcpu)) {
6582 kvm_inject_gp(vcpu, 0);
6583 return 1;
6584 }
3573e22c 6585
4291b588 6586 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6587 return 1;
6588
145c28dd
AG		 6589 if (vmx->nested.vmxon) {
6590 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6591 skip_emulated_instruction(vcpu);
6592 return 1;
6593 }
b3897a49
NHE		 6594
6595 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6596 != VMXON_NEEDED_FEATURES) {
6597 kvm_inject_gp(vcpu, 0);
6598 return 1;
6599 }
6600
8de48833
AG		 6601 if (enable_shadow_vmcs) {
6602 shadow_vmcs = alloc_vmcs();
6603 if (!shadow_vmcs)
6604 return -ENOMEM;
6605 /* mark vmcs as shadow */
6606 shadow_vmcs->revision_id |= (1u << 31);
6607 /* init shadow vmcs */
6608 vmcs_clear(shadow_vmcs);
6609 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6610 }
ec378aee 6611
ff2f6fe9
NHE		 6612 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6613 vmx->nested.vmcs02_num = 0;
6614
f4124500
JK		 6615 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6616 HRTIMER_MODE_REL);
6617 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6618
ec378aee
NHE		 6619 vmx->nested.vmxon = true;
6620
6621 skip_emulated_instruction(vcpu);
a25eb114 6622 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6623 return 1;
6624}
6625
6626/*
6627 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6628 * for running VMX instructions (except VMXON, whose prerequisites are
6629 * slightly different). It also specifies what exception to inject otherwise.
6630 */
6631static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6632{
6633 struct kvm_segment cs;
6634 struct vcpu_vmx *vmx = to_vmx(vcpu);
6635
6636 if (!vmx->nested.vmxon) {
6637 kvm_queue_exception(vcpu, UD_VECTOR);
6638 return 0;
6639 }
6640
6641 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6642 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6643 (is_long_mode(vcpu) && !cs.l)) {
6644 kvm_queue_exception(vcpu, UD_VECTOR);
6645 return 0;
6646 }
6647
6648 if (vmx_get_cpl(vcpu)) {
6649 kvm_inject_gp(vcpu, 0);
6650 return 0;
6651 }
6652
6653 return 1;
6654}
6655
e7953d7f
AG		 6656static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6657{
8a1b9dd0 6658 u32 exec_control;
9a2a05b9
PB		 6659 if (vmx->nested.current_vmptr == -1ull)
6660 return;
6661
6662 /* current_vmptr and current_vmcs12 are always set/reset together */
6663 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6664 return;
6665
012f83cb 6666 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6667 /* copy to memory all shadowed fields in case
6668 they were modified */
6669 copy_shadow_to_vmcs12(vmx);
6670 vmx->nested.sync_shadow_vmcs = false;
6671 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6672 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6673 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6674 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6675 }
705699a1 6676 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6677 kunmap(vmx->nested.current_vmcs12_page);
6678 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6679 vmx->nested.current_vmptr = -1ull;
6680 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6681}
6682
ec378aee
NHE		 6683/*
6684 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6685 * just stops using VMX.
6686 */
6687static void free_nested(struct vcpu_vmx *vmx)
6688{
6689 if (!vmx->nested.vmxon)
6690 return;
9a2a05b9 6691
ec378aee 6692 vmx->nested.vmxon = false;
9a2a05b9 6693 nested_release_vmcs12(vmx);
e7953d7f
AG		 6694 if (enable_shadow_vmcs)
6695 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6696 /* Unpin physical memory we referred to in current vmcs02 */
6697 if (vmx->nested.apic_access_page) {
6698 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6699 vmx->nested.apic_access_page = NULL;
fe3ef05c 6700 }
a7c0b07d
WL		 6701 if (vmx->nested.virtual_apic_page) {
6702 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6703 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6704 }
705699a1
WV		 6705 if (vmx->nested.pi_desc_page) {
6706 kunmap(vmx->nested.pi_desc_page);
6707 nested_release_page(vmx->nested.pi_desc_page);
6708 vmx->nested.pi_desc_page = NULL;
6709 vmx->nested.pi_desc = NULL;
6710 }
ff2f6fe9
NHE		 6711
6712 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6713}
6714
6715/* Emulate the VMXOFF instruction */
6716static int handle_vmoff(struct kvm_vcpu *vcpu)
6717{
6718 if (!nested_vmx_check_permission(vcpu))
6719 return 1;
6720 free_nested(to_vmx(vcpu));
6721 skip_emulated_instruction(vcpu);
a25eb114 6722 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6723 return 1;
6724}
6725
27d6c865
NHE		 6726/* Emulate the VMCLEAR instruction */
6727static int handle_vmclear(struct kvm_vcpu *vcpu)
6728{
6729 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6730 gpa_t vmptr;
6731 struct vmcs12 *vmcs12;
6732 struct page *page;
27d6c865
NHE		 6733
6734 if (!nested_vmx_check_permission(vcpu))
6735 return 1;
6736
4291b588 6737 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6738 return 1;
27d6c865 6739
9a2a05b9 6740 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6741 nested_release_vmcs12(vmx);
27d6c865
NHE		 6742
6743 page = nested_get_page(vcpu, vmptr);
6744 if (page == NULL) {
6745 /*
6746 * For accurate processor emulation, VMCLEAR beyond available
6747 * physical memory should do nothing at all. However, it is
6748 * possible that a nested vmx bug, not a guest hypervisor bug,
6749 * resulted in this case, so let's shut down before doing any
6750 * more damage:
6751 */
6752 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6753 return 1;
6754 }
6755 vmcs12 = kmap(page);
6756 vmcs12->launch_state = 0;
6757 kunmap(page);
6758 nested_release_page(page);
6759
6760 nested_free_vmcs02(vmx, vmptr);
6761
6762 skip_emulated_instruction(vcpu);
6763 nested_vmx_succeed(vcpu);
6764 return 1;
6765}
6766
cd232ad0
NHE		 6767static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6768
6769/* Emulate the VMLAUNCH instruction */
6770static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6771{
6772 return nested_vmx_run(vcpu, true);
6773}
6774
6775/* Emulate the VMRESUME instruction */
6776static int handle_vmresume(struct kvm_vcpu *vcpu)
6777{
6778
6779 return nested_vmx_run(vcpu, false);
6780}
6781
49f705c5
NHE		 6782enum vmcs_field_type {
6783 VMCS_FIELD_TYPE_U16 = 0,
6784 VMCS_FIELD_TYPE_U64 = 1,
6785 VMCS_FIELD_TYPE_U32 = 2,
6786 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6787};
6788
6789static inline int vmcs_field_type(unsigned long field)
6790{
6791 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6792 return VMCS_FIELD_TYPE_U32;
6793 return (field >> 13) & 0x3 ;
6794}
6795
6796static inline int vmcs_field_readonly(unsigned long field)
6797{
6798 return (((field >> 10) & 0x3) == 1);
6799}
6800
6801/*
6802 * Read a vmcs12 field. Since these can have varying lengths and we return
6803 * one type, we chose the biggest type (u64) and zero-extend the return value
6804 * to that size. Note that the caller, handle_vmread, might need to use only
6805 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6806 * 64-bit fields are to be returned).
6807 */
a2ae9df7
PB		 6808static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6809 unsigned long field, u64 *ret)
49f705c5
NHE		 6810{
6811 short offset = vmcs_field_to_offset(field);
6812 char *p;
6813
6814 if (offset < 0)
a2ae9df7 6815 return offset;
49f705c5
NHE		 6816
6817 p = ((char *)(get_vmcs12(vcpu))) + offset;
6818
6819 switch (vmcs_field_type(field)) {
6820 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6821 *ret = *((natural_width *)p);
a2ae9df7 6822 return 0;
49f705c5
NHE		 6823 case VMCS_FIELD_TYPE_U16:
6824 *ret = *((u16 *)p);
a2ae9df7 6825 return 0;
49f705c5
NHE		 6826 case VMCS_FIELD_TYPE_U32:
6827 *ret = *((u32 *)p);
a2ae9df7 6828 return 0;
49f705c5
NHE		 6829 case VMCS_FIELD_TYPE_U64:
6830 *ret = *((u64 *)p);
a2ae9df7 6831 return 0;
49f705c5 6832 default:
a2ae9df7
PB		 6833 WARN_ON(1);
6834 return -ENOENT;
49f705c5
NHE		 6835 }
6836}
6837
20b97fea 6838
a2ae9df7
PB		 6839static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6840 unsigned long field, u64 field_value){
20b97fea
AG		 6841 short offset = vmcs_field_to_offset(field);
6842 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6843 if (offset < 0)
a2ae9df7 6844 return offset;
20b97fea
AG		 6845
6846 switch (vmcs_field_type(field)) {
6847 case VMCS_FIELD_TYPE_U16:
6848 *(u16 *)p = field_value;
a2ae9df7 6849 return 0;
20b97fea
AG		 6850 case VMCS_FIELD_TYPE_U32:
6851 *(u32 *)p = field_value;
a2ae9df7 6852 return 0;
20b97fea
AG		 6853 case VMCS_FIELD_TYPE_U64:
6854 *(u64 *)p = field_value;
a2ae9df7 6855 return 0;
20b97fea
AG		 6856 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6857 *(natural_width *)p = field_value;
a2ae9df7 6858 return 0;
20b97fea 6859 default:
a2ae9df7
PB		 6860 WARN_ON(1);
6861 return -ENOENT;
20b97fea
AG		 6862 }
6863
6864}
6865
16f5b903
AG		 6866static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6867{
6868 int i;
6869 unsigned long field;
6870 u64 field_value;
6871 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6872 const unsigned long *fields = shadow_read_write_fields;
6873 const int num_fields = max_shadow_read_write_fields;
16f5b903 6874
282da870
JK		 6875 preempt_disable();
6876
16f5b903
AG		 6877 vmcs_load(shadow_vmcs);
6878
6879 for (i = 0; i < num_fields; i++) {
6880 field = fields[i];
6881 switch (vmcs_field_type(field)) {
6882 case VMCS_FIELD_TYPE_U16:
6883 field_value = vmcs_read16(field);
6884 break;
6885 case VMCS_FIELD_TYPE_U32:
6886 field_value = vmcs_read32(field);
6887 break;
6888 case VMCS_FIELD_TYPE_U64:
6889 field_value = vmcs_read64(field);
6890 break;
6891 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6892 field_value = vmcs_readl(field);
6893 break;
a2ae9df7
PB		 6894 default:
6895 WARN_ON(1);
6896 continue;
16f5b903
AG		 6897 }
6898 vmcs12_write_any(&vmx->vcpu, field, field_value);
6899 }
6900
6901 vmcs_clear(shadow_vmcs);
6902 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6903
6904 preempt_enable();
16f5b903
AG		 6905}
6906
c3114420
AG		 6907static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6908{
c2bae893
MK		 6909 const unsigned long *fields[] = {
6910 shadow_read_write_fields,
6911 shadow_read_only_fields
c3114420 6912 };
c2bae893 6913 const int max_fields[] = {
c3114420
AG		 6914 max_shadow_read_write_fields,
6915 max_shadow_read_only_fields
6916 };
6917 int i, q;
6918 unsigned long field;
6919 u64 field_value = 0;
6920 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6921
6922 vmcs_load(shadow_vmcs);
6923
c2bae893 6924 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6925 for (i = 0; i < max_fields[q]; i++) {
6926 field = fields[q][i];
6927 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6928
6929 switch (vmcs_field_type(field)) {
6930 case VMCS_FIELD_TYPE_U16:
6931 vmcs_write16(field, (u16)field_value);
6932 break;
6933 case VMCS_FIELD_TYPE_U32:
6934 vmcs_write32(field, (u32)field_value);
6935 break;
6936 case VMCS_FIELD_TYPE_U64:
6937 vmcs_write64(field, (u64)field_value);
6938 break;
6939 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6940 vmcs_writel(field, (long)field_value);
6941 break;
a2ae9df7
PB		 6942 default:
6943 WARN_ON(1);
6944 break;
c3114420
AG		 6945 }
6946 }
6947 }
6948
6949 vmcs_clear(shadow_vmcs);
6950 vmcs_load(vmx->loaded_vmcs->vmcs);
6951}
6952
49f705c5
NHE		 6953/*
6954 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6955 * used before) all generate the same failure when it is missing.
6956 */
6957static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6958{
6959 struct vcpu_vmx *vmx = to_vmx(vcpu);
6960 if (vmx->nested.current_vmptr == -1ull) {
6961 nested_vmx_failInvalid(vcpu);
6962 skip_emulated_instruction(vcpu);
6963 return 0;
6964 }
6965 return 1;
6966}
6967
6968static int handle_vmread(struct kvm_vcpu *vcpu)
6969{
6970 unsigned long field;
6971 u64 field_value;
6972 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6973 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6974 gva_t gva = 0;
6975
6976 if (!nested_vmx_check_permission(vcpu) ||
6977 !nested_vmx_check_vmcs12(vcpu))
6978 return 1;
6979
6980 /* Decode instruction info and find the field to read */
27e6fb5d 6981 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6982 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6983 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6984 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6985 skip_emulated_instruction(vcpu);
6986 return 1;
6987 }
6988 /*
6989 * Now copy part of this value to register or memory, as requested.
6990 * Note that the number of bits actually copied is 32 or 64 depending
6991 * on the guest's mode (32 or 64 bit), not on the given field's length.
6992 */
6993 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6994 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6995 field_value);
6996 } else {
6997 if (get_vmx_mem_address(vcpu, exit_qualification,
6998 vmx_instruction_info, &gva))
6999 return 1;
7000 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7001 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7002 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7003 }
7004
7005 nested_vmx_succeed(vcpu);
7006 skip_emulated_instruction(vcpu);
7007 return 1;
7008}
7009
7010
7011static int handle_vmwrite(struct kvm_vcpu *vcpu)
7012{
7013 unsigned long field;
7014 gva_t gva;
7015 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7016 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7017 /* The value to write might be 32 or 64 bits, depending on L1's long
7018 * mode, and eventually we need to write that into a field of several
7019 * possible lengths. The code below first zero-extends the value to 64
7020 * bit (field_value), and then copies only the approriate number of
7021 * bits into the vmcs12 field.
7022 */
7023 u64 field_value = 0;
7024 struct x86_exception e;
7025
7026 if (!nested_vmx_check_permission(vcpu) ||
7027 !nested_vmx_check_vmcs12(vcpu))
7028 return 1;
7029
7030 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7031 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7032 (((vmx_instruction_info) >> 3) & 0xf));
7033 else {
7034 if (get_vmx_mem_address(vcpu, exit_qualification,
7035 vmx_instruction_info, &gva))
7036 return 1;
7037 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7038 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7039 kvm_inject_page_fault(vcpu, &e);
7040 return 1;
7041 }
7042 }
7043
7044
27e6fb5d 7045 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7046 if (vmcs_field_readonly(field)) {
7047 nested_vmx_failValid(vcpu,
7048 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7049 skip_emulated_instruction(vcpu);
7050 return 1;
7051 }
7052
a2ae9df7 7053 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7054 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7055 skip_emulated_instruction(vcpu);
7056 return 1;
7057 }
7058
7059 nested_vmx_succeed(vcpu);
7060 skip_emulated_instruction(vcpu);
7061 return 1;
7062}
7063
63846663
NHE		 7064/* Emulate the VMPTRLD instruction */
7065static int handle_vmptrld(struct kvm_vcpu *vcpu)
7066{
7067 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7068 gpa_t vmptr;
8a1b9dd0 7069 u32 exec_control;
63846663
NHE		 7070
7071 if (!nested_vmx_check_permission(vcpu))
7072 return 1;
7073
4291b588 7074 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7075 return 1;
63846663
NHE		 7076
7077 if (vmx->nested.current_vmptr != vmptr) {
7078 struct vmcs12 *new_vmcs12;
7079 struct page *page;
7080 page = nested_get_page(vcpu, vmptr);
7081 if (page == NULL) {
7082 nested_vmx_failInvalid(vcpu);
7083 skip_emulated_instruction(vcpu);
7084 return 1;
7085 }
7086 new_vmcs12 = kmap(page);
7087 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7088 kunmap(page);
7089 nested_release_page_clean(page);
7090 nested_vmx_failValid(vcpu,
7091 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7092 skip_emulated_instruction(vcpu);
7093 return 1;
7094 }
63846663 7095
9a2a05b9 7096 nested_release_vmcs12(vmx);
63846663
NHE		 7097 vmx->nested.current_vmptr = vmptr;
7098 vmx->nested.current_vmcs12 = new_vmcs12;
7099 vmx->nested.current_vmcs12_page = page;
012f83cb 7100 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7101 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7102 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7103 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7104 vmcs_write64(VMCS_LINK_POINTER,
7105 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7106 vmx->nested.sync_shadow_vmcs = true;
7107 }
63846663
NHE		 7108 }
7109
7110 nested_vmx_succeed(vcpu);
7111 skip_emulated_instruction(vcpu);
7112 return 1;
7113}
7114
6a4d7550
NHE		 7115/* Emulate the VMPTRST instruction */
7116static int handle_vmptrst(struct kvm_vcpu *vcpu)
7117{
7118 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7119 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7120 gva_t vmcs_gva;
7121 struct x86_exception e;
7122
7123 if (!nested_vmx_check_permission(vcpu))
7124 return 1;
7125
7126 if (get_vmx_mem_address(vcpu, exit_qualification,
7127 vmx_instruction_info, &vmcs_gva))
7128 return 1;
7129 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7130 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7131 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7132 sizeof(u64), &e)) {
7133 kvm_inject_page_fault(vcpu, &e);
7134 return 1;
7135 }
7136 nested_vmx_succeed(vcpu);
7137 skip_emulated_instruction(vcpu);
7138 return 1;
7139}
7140
bfd0a56b
NHE		 7141/* Emulate the INVEPT instruction */
7142static int handle_invept(struct kvm_vcpu *vcpu)
7143{
b9c237bb 7144 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7145 u32 vmx_instruction_info, types;
7146 unsigned long type;
7147 gva_t gva;
7148 struct x86_exception e;
7149 struct {
7150 u64 eptp, gpa;
7151 } operand;
bfd0a56b 7152
b9c237bb
WV		 7153 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7154 SECONDARY_EXEC_ENABLE_EPT) ||
7155 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7156 kvm_queue_exception(vcpu, UD_VECTOR);
7157 return 1;
7158 }
7159
7160 if (!nested_vmx_check_permission(vcpu))
7161 return 1;
7162
7163 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7164 kvm_queue_exception(vcpu, UD_VECTOR);
7165 return 1;
7166 }
7167
7168 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7169 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7170
b9c237bb 7171 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7172
7173 if (!(types & (1UL << type))) {
7174 nested_vmx_failValid(vcpu,
7175 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7176 return 1;
7177 }
7178
7179 /* According to the Intel VMX instruction reference, the memory
7180 * operand is read even if it isn't needed (e.g., for type==global)
7181 */
7182 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7183 vmx_instruction_info, &gva))
7184 return 1;
7185 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7186 sizeof(operand), &e)) {
7187 kvm_inject_page_fault(vcpu, &e);
7188 return 1;
7189 }
7190
7191 switch (type) {
bfd0a56b
NHE		 7192 case VMX_EPT_EXTENT_GLOBAL:
7193 kvm_mmu_sync_roots(vcpu);
77c3913b 7194 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7195 nested_vmx_succeed(vcpu);
7196 break;
7197 default:
4b855078 7198 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7199 BUG_ON(1);
7200 break;
7201 }
7202
7203 skip_emulated_instruction(vcpu);
7204 return 1;
7205}
7206
a642fc30
PM		 7207static int handle_invvpid(struct kvm_vcpu *vcpu)
7208{
7209 kvm_queue_exception(vcpu, UD_VECTOR);
7210 return 1;
7211}
7212
843e4330
KH		 7213static int handle_pml_full(struct kvm_vcpu *vcpu)
7214{
7215 unsigned long exit_qualification;
7216
7217 trace_kvm_pml_full(vcpu->vcpu_id);
7218
7219 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7220
7221 /*
7222 * PML buffer FULL happened while executing iret from NMI,
7223 * "blocked by NMI" bit has to be set before next VM entry.
7224 */
7225 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7226 cpu_has_virtual_nmis() &&
7227 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7228 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7229 GUEST_INTR_STATE_NMI);
7230
7231 /*
7232 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7233 * here.., and there's no userspace involvement needed for PML.
7234 */
7235 return 1;
7236}
7237
6aa8b732
AK		 7238/*
7239 * The exit handlers return 1 if the exit was handled fully and guest execution
7240 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7241 * to be done to userspace and return 0.
7242 */
772e0318 7243static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7244 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7245 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7246 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7247 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7248 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7249 [EXIT_REASON_CR_ACCESS] = handle_cr,
7250 [EXIT_REASON_DR_ACCESS] = handle_dr,
7251 [EXIT_REASON_CPUID] = handle_cpuid,
7252 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7253 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7254 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7255 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7256 [EXIT_REASON_INVD] = handle_invd,
a7052897 7257 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7258 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7259 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7260 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7261 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7262 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7263 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7264 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7265 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7266 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7267 [EXIT_REASON_VMOFF] = handle_vmoff,
7268 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7269 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7270 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7271 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7272 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7273 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7274 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7275 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7276 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7277 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7278 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7279 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7280 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7281 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7282 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7283 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7284 [EXIT_REASON_XSAVES] = handle_xsaves,
7285 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7286 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7287};
7288
7289static const int kvm_vmx_max_exit_handlers =
50a3485c 7290 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7291
908a7bdd
JK		 7292static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7293 struct vmcs12 *vmcs12)
7294{
7295 unsigned long exit_qualification;
7296 gpa_t bitmap, last_bitmap;
7297 unsigned int port;
7298 int size;
7299 u8 b;
7300
908a7bdd 7301 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7302 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7303
7304 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7305
7306 port = exit_qualification >> 16;
7307 size = (exit_qualification & 7) + 1;
7308
7309 last_bitmap = (gpa_t)-1;
7310 b = -1;
7311
7312 while (size > 0) {
7313 if (port < 0x8000)
7314 bitmap = vmcs12->io_bitmap_a;
7315 else if (port < 0x10000)
7316 bitmap = vmcs12->io_bitmap_b;
7317 else
7318 return 1;
7319 bitmap += (port & 0x7fff) / 8;
7320
7321 if (last_bitmap != bitmap)
7322 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7323 return 1;
7324 if (b & (1 << (port & 7)))
7325 return 1;
7326
7327 port++;
7328 size--;
7329 last_bitmap = bitmap;
7330 }
7331
7332 return 0;
7333}
7334
644d711a
NHE		 7335/*
7336 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7337 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7338 * disinterest in the current event (read or write a specific MSR) by using an
7339 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7340 */
7341static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7342 struct vmcs12 *vmcs12, u32 exit_reason)
7343{
7344 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7345 gpa_t bitmap;
7346
cbd29cb6 7347 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7348 return 1;
7349
7350 /*
7351 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7352 * for the four combinations of read/write and low/high MSR numbers.
7353 * First we need to figure out which of the four to use:
7354 */
7355 bitmap = vmcs12->msr_bitmap;
7356 if (exit_reason == EXIT_REASON_MSR_WRITE)
7357 bitmap += 2048;
7358 if (msr_index >= 0xc0000000) {
7359 msr_index -= 0xc0000000;
7360 bitmap += 1024;
7361 }
7362
7363 /* Then read the msr_index'th bit from this bitmap: */
7364 if (msr_index < 1024*8) {
7365 unsigned char b;
bd31a7f5
JK		 7366 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7367 return 1;
644d711a
NHE		 7368 return 1 & (b >> (msr_index & 7));
7369 } else
7370 return 1; /* let L1 handle the wrong parameter */
7371}
7372
7373/*
7374 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7375 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7376 * intercept (via guest_host_mask etc.) the current event.
7377 */
7378static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7379 struct vmcs12 *vmcs12)
7380{
7381 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7382 int cr = exit_qualification & 15;
7383 int reg = (exit_qualification >> 8) & 15;
1e32c079 7384 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7385
7386 switch ((exit_qualification >> 4) & 3) {
7387 case 0: /* mov to cr */
7388 switch (cr) {
7389 case 0:
7390 if (vmcs12->cr0_guest_host_mask &
7391 (val ^ vmcs12->cr0_read_shadow))
7392 return 1;
7393 break;
7394 case 3:
7395 if ((vmcs12->cr3_target_count >= 1 &&
7396 vmcs12->cr3_target_value0 == val) ||
7397 (vmcs12->cr3_target_count >= 2 &&
7398 vmcs12->cr3_target_value1 == val) ||
7399 (vmcs12->cr3_target_count >= 3 &&
7400 vmcs12->cr3_target_value2 == val) ||
7401 (vmcs12->cr3_target_count >= 4 &&
7402 vmcs12->cr3_target_value3 == val))
7403 return 0;
7404 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7405 return 1;
7406 break;
7407 case 4:
7408 if (vmcs12->cr4_guest_host_mask &
7409 (vmcs12->cr4_read_shadow ^ val))
7410 return 1;
7411 break;
7412 case 8:
7413 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7414 return 1;
7415 break;
7416 }
7417 break;
7418 case 2: /* clts */
7419 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7420 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7421 return 1;
7422 break;
7423 case 1: /* mov from cr */
7424 switch (cr) {
7425 case 3:
7426 if (vmcs12->cpu_based_vm_exec_control &
7427 CPU_BASED_CR3_STORE_EXITING)
7428 return 1;
7429 break;
7430 case 8:
7431 if (vmcs12->cpu_based_vm_exec_control &
7432 CPU_BASED_CR8_STORE_EXITING)
7433 return 1;
7434 break;
7435 }
7436 break;
7437 case 3: /* lmsw */
7438 /*
7439 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7440 * cr0. Other attempted changes are ignored, with no exit.
7441 */
7442 if (vmcs12->cr0_guest_host_mask & 0xe &
7443 (val ^ vmcs12->cr0_read_shadow))
7444 return 1;
7445 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7446 !(vmcs12->cr0_read_shadow & 0x1) &&
7447 (val & 0x1))
7448 return 1;
7449 break;
7450 }
7451 return 0;
7452}
7453
7454/*
7455 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7456 * should handle it ourselves in L0 (and then continue L2). Only call this
7457 * when in is_guest_mode (L2).
7458 */
7459static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7460{
644d711a
NHE		 7461 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7462 struct vcpu_vmx *vmx = to_vmx(vcpu);
7463 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7464 u32 exit_reason = vmx->exit_reason;
644d711a 7465
542060ea
JK		 7466 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7467 vmcs_readl(EXIT_QUALIFICATION),
7468 vmx->idt_vectoring_info,
7469 intr_info,
7470 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7471 KVM_ISA_VMX);
7472
644d711a
NHE		 7473 if (vmx->nested.nested_run_pending)
7474 return 0;
7475
7476 if (unlikely(vmx->fail)) {
bd80158a
JK		 7477 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7478 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7479 return 1;
7480 }
7481
7482 switch (exit_reason) {
7483 case EXIT_REASON_EXCEPTION_NMI:
7484 if (!is_exception(intr_info))
7485 return 0;
7486 else if (is_page_fault(intr_info))
7487 return enable_ept;
e504c909 7488 else if (is_no_device(intr_info) &&
ccf9844e 7489 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7490 return 0;
644d711a
NHE		 7491 return vmcs12->exception_bitmap &
7492 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7493 case EXIT_REASON_EXTERNAL_INTERRUPT:
7494 return 0;
7495 case EXIT_REASON_TRIPLE_FAULT:
7496 return 1;
7497 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7498 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7499 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7500 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7501 case EXIT_REASON_TASK_SWITCH:
7502 return 1;
7503 case EXIT_REASON_CPUID:
bc613494
MT		 7504 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7505 return 0;
644d711a
NHE		 7506 return 1;
7507 case EXIT_REASON_HLT:
7508 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7509 case EXIT_REASON_INVD:
7510 return 1;
7511 case EXIT_REASON_INVLPG:
7512 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7513 case EXIT_REASON_RDPMC:
7514 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7515 case EXIT_REASON_RDTSC:
7516 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7517 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7518 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7519 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7520 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7521 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7522 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7523 /*
7524 * VMX instructions trap unconditionally. This allows L1 to
7525 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7526 */
7527 return 1;
7528 case EXIT_REASON_CR_ACCESS:
7529 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7530 case EXIT_REASON_DR_ACCESS:
7531 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7532 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7533 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7534 case EXIT_REASON_MSR_READ:
7535 case EXIT_REASON_MSR_WRITE:
7536 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7537 case EXIT_REASON_INVALID_STATE:
7538 return 1;
7539 case EXIT_REASON_MWAIT_INSTRUCTION:
7540 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7541 case EXIT_REASON_MONITOR_INSTRUCTION:
7542 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7543 case EXIT_REASON_PAUSE_INSTRUCTION:
7544 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7545 nested_cpu_has2(vmcs12,
7546 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7547 case EXIT_REASON_MCE_DURING_VMENTRY:
7548 return 0;
7549 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7550 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7551 case EXIT_REASON_APIC_ACCESS:
7552 return nested_cpu_has2(vmcs12,
7553 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7554 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7555 case EXIT_REASON_EOI_INDUCED:
7556 /* apic_write and eoi_induced should exit unconditionally. */
82f0dd4b 7557 return 1;
644d711a 7558 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7559 /*
7560 * L0 always deals with the EPT violation. If nested EPT is
7561 * used, and the nested mmu code discovers that the address is
7562 * missing in the guest EPT table (EPT12), the EPT violation
7563 * will be injected with nested_ept_inject_page_fault()
7564 */
7565 return 0;
644d711a 7566 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7567 /*
7568 * L2 never uses directly L1's EPT, but rather L0's own EPT
7569 * table (shadow on EPT) or a merged EPT table that L0 built
7570 * (EPT on EPT). So any problems with the structure of the
7571 * table is L0's fault.
7572 */
644d711a
NHE		 7573 return 0;
7574 case EXIT_REASON_WBINVD:
7575 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7576 case EXIT_REASON_XSETBV:
7577 return 1;
81dc01f7
WL		 7578 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7579 /*
7580 * This should never happen, since it is not possible to
7581 * set XSS to a non-zero value---neither in L1 nor in L2.
7582 * If if it were, XSS would have to be checked against
7583 * the XSS exit bitmap in vmcs12.
7584 */
7585 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a
NHE		 7586 default:
7587 return 1;
7588 }
7589}
7590
586f9607
AK		 7591static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7592{
7593 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7594 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7595}
7596
843e4330
KH		 7597static int vmx_enable_pml(struct vcpu_vmx *vmx)
7598{
7599 struct page *pml_pg;
7600 u32 exec_control;
7601
7602 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7603 if (!pml_pg)
7604 return -ENOMEM;
7605
7606 vmx->pml_pg = pml_pg;
7607
7608 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7609 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7610
7611 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7612 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7613 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7614
7615 return 0;
7616}
7617
7618static void vmx_disable_pml(struct vcpu_vmx *vmx)
7619{
7620 u32 exec_control;
7621
7622 ASSERT(vmx->pml_pg);
7623 __free_page(vmx->pml_pg);
7624 vmx->pml_pg = NULL;
7625
7626 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7627 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7628 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7629}
7630
7631static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7632{
7633 struct kvm *kvm = vmx->vcpu.kvm;
7634 u64 *pml_buf;
7635 u16 pml_idx;
7636
7637 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7638
7639 /* Do nothing if PML buffer is empty */
7640 if (pml_idx == (PML_ENTITY_NUM - 1))
7641 return;
7642
7643 /* PML index always points to next available PML buffer entity */
7644 if (pml_idx >= PML_ENTITY_NUM)
7645 pml_idx = 0;
7646 else
7647 pml_idx++;
7648
7649 pml_buf = page_address(vmx->pml_pg);
7650 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7651 u64 gpa;
7652
7653 gpa = pml_buf[pml_idx];
7654 WARN_ON(gpa & (PAGE_SIZE - 1));
7655 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7656 }
7657
7658 /* reset PML index */
7659 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7660}
7661
7662/*
7663 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7664 * Called before reporting dirty_bitmap to userspace.
7665 */
7666static void kvm_flush_pml_buffers(struct kvm *kvm)
7667{
7668 int i;
7669 struct kvm_vcpu *vcpu;
7670 /*
7671 * We only need to kick vcpu out of guest mode here, as PML buffer
7672 * is flushed at beginning of all VMEXITs, and it's obvious that only
7673 * vcpus running in guest are possible to have unflushed GPAs in PML
7674 * buffer.
7675 */
7676 kvm_for_each_vcpu(i, vcpu, kvm)
7677 kvm_vcpu_kick(vcpu);
7678}
7679
6aa8b732
AK		 7680/*
7681 * The guest has exited. See if we can fix it or if we need userspace
7682 * assistance.
7683 */
851ba692 7684static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7685{
29bd8a78 7686 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7687 u32 exit_reason = vmx->exit_reason;
1155f76a 7688 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7689
843e4330
KH		 7690 /*
7691 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7692 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7693 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7694 * mode as if vcpus is in root mode, the PML buffer must has been
7695 * flushed already.
7696 */
7697 if (enable_pml)
7698 vmx_flush_pml_buffer(vmx);
7699
80ced186 7700 /* If guest state is invalid, start emulating */
14168786 7701 if (vmx->emulation_required)
80ced186 7702 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7703
644d711a 7704 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7705 nested_vmx_vmexit(vcpu, exit_reason,
7706 vmcs_read32(VM_EXIT_INTR_INFO),
7707 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7708 return 1;
7709 }
7710
5120702e
MG		 7711 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7712 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7713 vcpu->run->fail_entry.hardware_entry_failure_reason
7714 = exit_reason;
7715 return 0;
7716 }
7717
29bd8a78 7718 if (unlikely(vmx->fail)) {
851ba692
AK		 7719 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7720 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7721 = vmcs_read32(VM_INSTRUCTION_ERROR);
7722 return 0;
7723 }
6aa8b732 7724
b9bf6882
XG		 7725 /*
7726 * Note:
7727 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7728 * delivery event since it indicates guest is accessing MMIO.
7729 * The vm-exit can be triggered again after return to guest that
7730 * will cause infinite loop.
7731 */
d77c26fc 7732 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7733 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7734 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7735 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7736 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7737 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7738 vcpu->run->internal.ndata = 2;
7739 vcpu->run->internal.data[0] = vectoring_info;
7740 vcpu->run->internal.data[1] = exit_reason;
7741 return 0;
7742 }
3b86cd99 7743
644d711a
NHE		 7744 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7745 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7746 get_vmcs12(vcpu))))) {
c4282df9 7747 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7748 vmx->soft_vnmi_blocked = 0;
3b86cd99 7749 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7750 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7751 /*
7752 * This CPU don't support us in finding the end of an
7753 * NMI-blocked window if the guest runs with IRQs
7754 * disabled. So we pull the trigger after 1 s of
7755 * futile waiting, but inform the user about this.
7756 */
7757 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7758 "state on VCPU %d after 1 s timeout\n",
7759 __func__, vcpu->vcpu_id);
7760 vmx->soft_vnmi_blocked = 0;
3b86cd99 7761 }
3b86cd99
JK		 7762 }
7763
6aa8b732
AK		 7764 if (exit_reason < kvm_vmx_max_exit_handlers
7765 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7766 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7767 else {
2bc19dc3
MT		 7768 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7769 kvm_queue_exception(vcpu, UD_VECTOR);
7770 return 1;
6aa8b732 7771 }
6aa8b732
AK		 7772}
7773
95ba8273 7774static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7775{
a7c0b07d
WL		 7776 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7777
7778 if (is_guest_mode(vcpu) &&
7779 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7780 return;
7781
95ba8273 7782 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7783 vmcs_write32(TPR_THRESHOLD, 0);
7784 return;
7785 }
7786
95ba8273 7787 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7788}
7789
8d14695f
YZ		 7790static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7791{
7792 u32 sec_exec_control;
7793
7794 /*
7795 * There is not point to enable virtualize x2apic without enable
7796 * apicv
7797 */
c7c9c56c
YZ		 7798 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7799 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7800 return;
7801
7802 if (!vm_need_tpr_shadow(vcpu->kvm))
7803 return;
7804
7805 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7806
7807 if (set) {
7808 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7809 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7810 } else {
7811 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7812 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7813 }
7814 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7815
7816 vmx_set_msr_bitmap(vcpu);
7817}
7818
38b99173
TC		 7819static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7820{
7821 struct vcpu_vmx *vmx = to_vmx(vcpu);
7822
7823 /*
7824 * Currently we do not handle the nested case where L2 has an
7825 * APIC access page of its own; that page is still pinned.
7826 * Hence, we skip the case where the VCPU is in guest mode _and_
7827 * L1 prepared an APIC access page for L2.
7828 *
7829 * For the case where L1 and L2 share the same APIC access page
7830 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7831 * in the vmcs12), this function will only update either the vmcs01
7832 * or the vmcs02. If the former, the vmcs02 will be updated by
7833 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7834 * the next L2->L1 exit.
7835 */
7836 if (!is_guest_mode(vcpu) ||
7837 !nested_cpu_has2(vmx->nested.current_vmcs12,
7838 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7839 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7840}
7841
c7c9c56c
YZ		 7842static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7843{
7844 u16 status;
7845 u8 old;
7846
c7c9c56c
YZ		 7847 if (isr == -1)
7848 isr = 0;
7849
7850 status = vmcs_read16(GUEST_INTR_STATUS);
7851 old = status >> 8;
7852 if (isr != old) {
7853 status &= 0xff;
7854 status |= isr << 8;
7855 vmcs_write16(GUEST_INTR_STATUS, status);
7856 }
7857}
7858
7859static void vmx_set_rvi(int vector)
7860{
7861 u16 status;
7862 u8 old;
7863
4114c27d
WW		 7864 if (vector == -1)
7865 vector = 0;
7866
c7c9c56c
YZ		 7867 status = vmcs_read16(GUEST_INTR_STATUS);
7868 old = (u8)status & 0xff;
7869 if ((u8)vector != old) {
7870 status &= ~0xff;
7871 status |= (u8)vector;
7872 vmcs_write16(GUEST_INTR_STATUS, status);
7873 }
7874}
7875
7876static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7877{
4114c27d
WW		 7878 if (!is_guest_mode(vcpu)) {
7879 vmx_set_rvi(max_irr);
7880 return;
7881 }
7882
c7c9c56c
YZ		 7883 if (max_irr == -1)
7884 return;
7885
963fee16 7886 /*
4114c27d
WW		 7887 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7888 * handles it.
963fee16 7889 */
4114c27d 7890 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7891 return;
7892
963fee16 7893 /*
4114c27d 7894 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7895 * is run without virtual interrupt delivery.
7896 */
7897 if (!kvm_event_needs_reinjection(vcpu) &&
7898 vmx_interrupt_allowed(vcpu)) {
7899 kvm_queue_interrupt(vcpu, max_irr, false);
7900 vmx_inject_irq(vcpu);
7901 }
c7c9c56c
YZ		 7902}
7903
7904static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7905{
3d81bc7e
YZ		 7906 if (!vmx_vm_has_apicv(vcpu->kvm))
7907 return;
7908
c7c9c56c
YZ		 7909 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7910 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7911 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7912 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7913}
7914
51aa01d1 7915static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7916{
00eba012
AK		 7917 u32 exit_intr_info;
7918
7919 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7920 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7921 return;
7922
c5ca8e57 7923 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7924 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7925
7926 /* Handle machine checks before interrupts are enabled */
00eba012 7927 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7928 kvm_machine_check();
7929
20f65983 7930 /* We need to handle NMIs before interrupts are enabled */
00eba012 7931 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7932 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7933 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7934 asm("int $2");
ff9d07a0
ZY		 7935 kvm_after_handle_nmi(&vmx->vcpu);
7936 }
51aa01d1 7937}
20f65983 7938
a547c6db
YZ		 7939static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7940{
7941 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7942
7943 /*
7944 * If external interrupt exists, IF bit is set in rflags/eflags on the
7945 * interrupt stack frame, and interrupt will be enabled on a return
7946 * from interrupt handler.
7947 */
7948 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7949 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7950 unsigned int vector;
7951 unsigned long entry;
7952 gate_desc *desc;
7953 struct vcpu_vmx *vmx = to_vmx(vcpu);
7954#ifdef CONFIG_X86_64
7955 unsigned long tmp;
7956#endif
7957
7958 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7959 desc = (gate_desc *)vmx->host_idt_base + vector;
7960 entry = gate_offset(*desc);
7961 asm volatile(
7962#ifdef CONFIG_X86_64
7963 "mov %%" _ASM_SP ", %[sp]\n\t"
7964 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7965 "push $%c[ss]\n\t"
7966 "push %[sp]\n\t"
7967#endif
7968 "pushf\n\t"
7969 "orl $0x200, (%%" _ASM_SP ")\n\t"
7970 __ASM_SIZE(push) " $%c[cs]\n\t"
7971 "call *%[entry]\n\t"
7972 :
7973#ifdef CONFIG_X86_64
7974 [sp]"=&r"(tmp)
7975#endif
7976 :
7977 [entry]"r"(entry),
7978 [ss]"i"(__KERNEL_DS),
7979 [cs]"i"(__KERNEL_CS)
7980 );
7981 } else
7982 local_irq_enable();
7983}
7984
da8999d3
LJ		 7985static bool vmx_mpx_supported(void)
7986{
7987 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7988 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7989}
7990
55412b2e
WL		 7991static bool vmx_xsaves_supported(void)
7992{
7993 return vmcs_config.cpu_based_2nd_exec_ctrl &
7994 SECONDARY_EXEC_XSAVES;
7995}
7996
51aa01d1
AK		 7997static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7998{
c5ca8e57 7999 u32 exit_intr_info;
51aa01d1
AK		 8000 bool unblock_nmi;
8001 u8 vector;
8002 bool idtv_info_valid;
8003
8004 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8005
cf393f75 8006 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8007 if (vmx->nmi_known_unmasked)
8008 return;
c5ca8e57
AK		 8009 /*
8010 * Can't use vmx->exit_intr_info since we're not sure what
8011 * the exit reason is.
8012 */
8013 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8014 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8015 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8016 /*
7b4a25cb 8017 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8018 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8019 * a guest IRET fault.
7b4a25cb
GN		 8020 * SDM 3: 23.2.2 (September 2008)
8021 * Bit 12 is undefined in any of the following cases:
8022 * If the VM exit sets the valid bit in the IDT-vectoring
8023 * information field.
8024 * If the VM exit is due to a double fault.
cf393f75 8025 */
7b4a25cb
GN		 8026 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8027 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8028 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8029 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8030 else
8031 vmx->nmi_known_unmasked =
8032 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8033 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8034 } else if (unlikely(vmx->soft_vnmi_blocked))
8035 vmx->vnmi_blocked_time +=
8036 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8037}
8038
3ab66e8a 8039static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8040 u32 idt_vectoring_info,
8041 int instr_len_field,
8042 int error_code_field)
51aa01d1 8043{
51aa01d1
AK		 8044 u8 vector;
8045 int type;
8046 bool idtv_info_valid;
8047
8048 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8049
3ab66e8a
JK		 8050 vcpu->arch.nmi_injected = false;
8051 kvm_clear_exception_queue(vcpu);
8052 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8053
8054 if (!idtv_info_valid)
8055 return;
8056
3ab66e8a 8057 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8058
668f612f
AK		 8059 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8060 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8061
64a7ec06 8062 switch (type) {
37b96e98 8063 case INTR_TYPE_NMI_INTR:
3ab66e8a 8064 vcpu->arch.nmi_injected = true;
668f612f 8065 /*
7b4a25cb 8066 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8067 * Clear bit "block by NMI" before VM entry if a NMI
8068 * delivery faulted.
668f612f 8069 */
3ab66e8a 8070 vmx_set_nmi_mask(vcpu, false);
37b96e98 8071 break;
37b96e98 8072 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8073 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8074 /* fall through */
8075 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8076 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8077 u32 err = vmcs_read32(error_code_field);
851eb667 8078 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8079 } else
851eb667 8080 kvm_requeue_exception(vcpu, vector);
37b96e98 8081 break;
66fd3f7f 8082 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8083 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8084 /* fall through */
37b96e98 8085 case INTR_TYPE_EXT_INTR:
3ab66e8a 8086 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8087 break;
8088 default:
8089 break;
f7d9238f 8090 }
cf393f75
AK		 8091}
8092
83422e17
AK		 8093static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8094{
3ab66e8a 8095 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8096 VM_EXIT_INSTRUCTION_LEN,
8097 IDT_VECTORING_ERROR_CODE);
8098}
8099
b463a6f7
AK		 8100static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8101{
3ab66e8a 8102 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8103 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8104 VM_ENTRY_INSTRUCTION_LEN,
8105 VM_ENTRY_EXCEPTION_ERROR_CODE);
8106
8107 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8108}
8109
d7cd9796
GN		 8110static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8111{
8112 int i, nr_msrs;
8113 struct perf_guest_switch_msr *msrs;
8114
8115 msrs = perf_guest_get_msrs(&nr_msrs);
8116
8117 if (!msrs)
8118 return;
8119
8120 for (i = 0; i < nr_msrs; i++)
8121 if (msrs[i].host == msrs[i].guest)
8122 clear_atomic_switch_msr(vmx, msrs[i].msr);
8123 else
8124 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8125 msrs[i].host);
8126}
8127
a3b5ba49 8128static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8129{
a2fa3e9f 8130 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8131 unsigned long debugctlmsr, cr4;
104f226b
AK		 8132
8133 /* Record the guest's net vcpu time for enforced NMI injections. */
8134 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8135 vmx->entry_time = ktime_get();
8136
8137 /* Don't enter VMX if guest state is invalid, let the exit handler
8138 start emulation until we arrive back to a valid state */
14168786 8139 if (vmx->emulation_required)
104f226b
AK		 8140 return;
8141
a7653ecd
RK		 8142 if (vmx->ple_window_dirty) {
8143 vmx->ple_window_dirty = false;
8144 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8145 }
8146
012f83cb
AG		 8147 if (vmx->nested.sync_shadow_vmcs) {
8148 copy_vmcs12_to_shadow(vmx);
8149 vmx->nested.sync_shadow_vmcs = false;
8150 }
8151
104f226b
AK		 8152 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8153 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8154 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8155 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8156
1e02ce4c 8157 cr4 = cr4_read_shadow();
d974baa3
AL		 8158 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8159 vmcs_writel(HOST_CR4, cr4);
8160 vmx->host_state.vmcs_host_cr4 = cr4;
8161 }
8162
104f226b
AK		 8163 /* When single-stepping over STI and MOV SS, we must clear the
8164 * corresponding interruptibility bits in the guest state. Otherwise
8165 * vmentry fails as it then expects bit 14 (BS) in pending debug
8166 * exceptions being set, but that's not correct for the guest debugging
8167 * case. */
8168 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8169 vmx_set_interrupt_shadow(vcpu, 0);
8170
d7cd9796 8171 atomic_switch_perf_msrs(vmx);
2a7921b7 8172 debugctlmsr = get_debugctlmsr();
d7cd9796 8173
d462b819 8174 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8175 asm(
6aa8b732 8176 /* Store host registers */
b188c81f
AK		 8177 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8178 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8179 "push %%" _ASM_CX " \n\t"
8180 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8181 "je 1f \n\t"
b188c81f 8182 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8183 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8184 "1: \n\t"
d3edefc0 8185 /* Reload cr2 if changed */
b188c81f
AK		 8186 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8187 "mov %%cr2, %%" _ASM_DX " \n\t"
8188 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8189 "je 2f \n\t"
b188c81f 8190 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8191 "2: \n\t"
6aa8b732 8192 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8193 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8194 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8195 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8196 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8197 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8198 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8199 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8200 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8201#ifdef CONFIG_X86_64
e08aa78a
AK		 8202 "mov %c[r8](%0), %%r8 \n\t"
8203 "mov %c[r9](%0), %%r9 \n\t"
8204 "mov %c[r10](%0), %%r10 \n\t"
8205 "mov %c[r11](%0), %%r11 \n\t"
8206 "mov %c[r12](%0), %%r12 \n\t"
8207 "mov %c[r13](%0), %%r13 \n\t"
8208 "mov %c[r14](%0), %%r14 \n\t"
8209 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8210#endif
b188c81f 8211 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8212
6aa8b732 8213 /* Enter guest mode */
83287ea4 8214 "jne 1f \n\t"
4ecac3fd 8215 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8216 "jmp 2f \n\t"
8217 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8218 "2: "
6aa8b732 8219 /* Save guest registers, load host registers, keep flags */
b188c81f 8220 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8221 "pop %0 \n\t"
b188c81f
AK		 8222 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8223 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8224 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8225 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8226 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8227 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8228 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8229#ifdef CONFIG_X86_64
e08aa78a
AK		 8230 "mov %%r8, %c[r8](%0) \n\t"
8231 "mov %%r9, %c[r9](%0) \n\t"
8232 "mov %%r10, %c[r10](%0) \n\t"
8233 "mov %%r11, %c[r11](%0) \n\t"
8234 "mov %%r12, %c[r12](%0) \n\t"
8235 "mov %%r13, %c[r13](%0) \n\t"
8236 "mov %%r14, %c[r14](%0) \n\t"
8237 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8238#endif
b188c81f
AK		 8239 "mov %%cr2, %%" _ASM_AX " \n\t"
8240 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8241
b188c81f 8242 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8243 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8244 ".pushsection .rodata \n\t"
8245 ".global vmx_return \n\t"
8246 "vmx_return: " _ASM_PTR " 2b \n\t"
8247 ".popsection"
e08aa78a 8248 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8249 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8250 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8251 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8252 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8253 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8254 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8255 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8256 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8257 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8258 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8259#ifdef CONFIG_X86_64
ad312c7c
ZX		 8260 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8261 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8262 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8263 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8264 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8265 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8266 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8267 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8268#endif
40712fae
AK		 8269 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8270 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8271 : "cc", "memory"
8272#ifdef CONFIG_X86_64
b188c81f 8273 , "rax", "rbx", "rdi", "rsi"
c2036300 8274 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8275#else
8276 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8277#endif
8278 );
6aa8b732 8279
2a7921b7
GN		 8280 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8281 if (debugctlmsr)
8282 update_debugctlmsr(debugctlmsr);
8283
aa67f609
AK		 8284#ifndef CONFIG_X86_64
8285 /*
8286 * The sysexit path does not restore ds/es, so we must set them to
8287 * a reasonable value ourselves.
8288 *
8289 * We can't defer this to vmx_load_host_state() since that function
8290 * may be executed in interrupt context, which saves and restore segments
8291 * around it, nullifying its effect.
8292 */
8293 loadsegment(ds, __USER_DS);
8294 loadsegment(es, __USER_DS);
8295#endif
8296
6de4f3ad 8297 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8298 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8299 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8300 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8301 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8302 vcpu->arch.regs_dirty = 0;
8303
1155f76a
AK		 8304 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8305
d462b819 8306 vmx->loaded_vmcs->launched = 1;
1b6269db 8307
51aa01d1 8308 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8309 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8310
e0b890d3
GN		 8311 /*
8312 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8313 * we did not inject a still-pending event to L1 now because of
8314 * nested_run_pending, we need to re-enable this bit.
8315 */
8316 if (vmx->nested.nested_run_pending)
8317 kvm_make_request(KVM_REQ_EVENT, vcpu);
8318
8319 vmx->nested.nested_run_pending = 0;
8320
51aa01d1
AK		 8321 vmx_complete_atomic_exit(vmx);
8322 vmx_recover_nmi_blocking(vmx);
cf393f75 8323 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8324}
8325
4fa7734c
PB		 8326static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8327{
8328 struct vcpu_vmx *vmx = to_vmx(vcpu);
8329 int cpu;
8330
8331 if (vmx->loaded_vmcs == &vmx->vmcs01)
8332 return;
8333
8334 cpu = get_cpu();
8335 vmx->loaded_vmcs = &vmx->vmcs01;
8336 vmx_vcpu_put(vcpu);
8337 vmx_vcpu_load(vcpu, cpu);
8338 vcpu->cpu = cpu;
8339 put_cpu();
8340}
8341
6aa8b732
AK		 8342static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8343{
fb3f0f51
RR		 8344 struct vcpu_vmx *vmx = to_vmx(vcpu);
8345
843e4330
KH		 8346 if (enable_pml)
8347 vmx_disable_pml(vmx);
cdbecfc3 8348 free_vpid(vmx);
4fa7734c
PB		 8349 leave_guest_mode(vcpu);
8350 vmx_load_vmcs01(vcpu);
26a865f4 8351 free_nested(vmx);
4fa7734c 8352 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8353 kfree(vmx->guest_msrs);
8354 kvm_vcpu_uninit(vcpu);
a4770347 8355 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8356}
8357
fb3f0f51 8358static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8359{
fb3f0f51 8360 int err;
c16f862d 8361 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8362 int cpu;
6aa8b732 8363
a2fa3e9f 8364 if (!vmx)
fb3f0f51
RR		 8365 return ERR_PTR(-ENOMEM);
8366
2384d2b3
SY		 8367 allocate_vpid(vmx);
8368
fb3f0f51
RR		 8369 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8370 if (err)
8371 goto free_vcpu;
965b58a5 8372
a2fa3e9f 8373 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8374 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8375 > PAGE_SIZE);
0123be42 8376
be6d05cf 8377 err = -ENOMEM;
fb3f0f51 8378 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8379 goto uninit_vcpu;
8380 }
965b58a5 8381
d462b819
NHE		 8382 vmx->loaded_vmcs = &vmx->vmcs01;
8383 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8384 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8385 goto free_msrs;
d462b819
NHE		 8386 if (!vmm_exclusive)
8387 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8388 loaded_vmcs_init(vmx->loaded_vmcs);
8389 if (!vmm_exclusive)
8390 kvm_cpu_vmxoff();
a2fa3e9f 8391
15ad7146
AK		 8392 cpu = get_cpu();
8393 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8394 vmx->vcpu.cpu = cpu;
8b9cf98c 8395 err = vmx_vcpu_setup(vmx);
fb3f0f51 8396 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8397 put_cpu();
fb3f0f51
RR		 8398 if (err)
8399 goto free_vmcs;
a63cb560 8400 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8401 err = alloc_apic_access_page(kvm);
8402 if (err)
5e4a0b3c 8403 goto free_vmcs;
a63cb560 8404 }
fb3f0f51 8405
b927a3ce
SY		 8406 if (enable_ept) {
8407 if (!kvm->arch.ept_identity_map_addr)
8408 kvm->arch.ept_identity_map_addr =
8409 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8410 err = init_rmode_identity_map(kvm);
8411 if (err)
93ea5388 8412 goto free_vmcs;
b927a3ce 8413 }
b7ebfb05 8414
b9c237bb
WV		 8415 if (nested)
8416 nested_vmx_setup_ctls_msrs(vmx);
8417
705699a1 8418 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8419 vmx->nested.current_vmptr = -1ull;
8420 vmx->nested.current_vmcs12 = NULL;
8421
843e4330
KH		 8422 /*
8423 * If PML is turned on, failure on enabling PML just results in failure
8424 * of creating the vcpu, therefore we can simplify PML logic (by
8425 * avoiding dealing with cases, such as enabling PML partially on vcpus
8426 * for the guest, etc.
8427 */
8428 if (enable_pml) {
8429 err = vmx_enable_pml(vmx);
8430 if (err)
8431 goto free_vmcs;
8432 }
8433
fb3f0f51
RR		 8434 return &vmx->vcpu;
8435
8436free_vmcs:
5f3fbc34 8437 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8438free_msrs:
fb3f0f51
RR		 8439 kfree(vmx->guest_msrs);
8440uninit_vcpu:
8441 kvm_vcpu_uninit(&vmx->vcpu);
8442free_vcpu:
cdbecfc3 8443 free_vpid(vmx);
a4770347 8444 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8445 return ERR_PTR(err);
6aa8b732
AK		 8446}
8447
002c7f7c
YS		 8448static void __init vmx_check_processor_compat(void *rtn)
8449{
8450 struct vmcs_config vmcs_conf;
8451
8452 *(int *)rtn = 0;
8453 if (setup_vmcs_config(&vmcs_conf) < 0)
8454 *(int *)rtn = -EIO;
8455 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8456 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8457 smp_processor_id());
8458 *(int *)rtn = -EIO;
8459 }
8460}
8461
67253af5
SY		 8462static int get_ept_level(void)
8463{
8464 return VMX_EPT_DEFAULT_GAW + 1;
8465}
8466
4b12f0de 8467static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8468{
4b12f0de
SY		 8469 u64 ret;
8470
522c68c4
SY		 8471 /* For VT-d and EPT combination
8472 * 1. MMIO: always map as UC
8473 * 2. EPT with VT-d:
8474 * a. VT-d without snooping control feature: can't guarantee the
8475 * result, try to trust guest.
8476 * b. VT-d with snooping control feature: snooping control feature of
8477 * VT-d engine can guarantee the cache correctness. Just set it
8478 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8479 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8480 * consistent with host MTRR
8481 */
4b12f0de
SY		 8482 if (is_mmio)
8483 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8484 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8485 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8486 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8487 else
522c68c4 8488 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8489 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8490
8491 return ret;
64d4d521
SY		 8492}
8493
17cc3935 8494static int vmx_get_lpage_level(void)
344f414f 8495{
878403b7
SY		 8496 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8497 return PT_DIRECTORY_LEVEL;
8498 else
8499 /* For shadow and EPT supported 1GB page */
8500 return PT_PDPE_LEVEL;
344f414f
JR		 8501}
8502
0e851880
SY		 8503static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8504{
4e47c7a6
SY		 8505 struct kvm_cpuid_entry2 *best;
8506 struct vcpu_vmx *vmx = to_vmx(vcpu);
8507 u32 exec_control;
8508
8509 vmx->rdtscp_enabled = false;
8510 if (vmx_rdtscp_supported()) {
8511 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8512 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8513 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8514 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8515 vmx->rdtscp_enabled = true;
8516 else {
8517 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8518 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8519 exec_control);
8520 }
8521 }
8522 }
ad756a16 8523
ad756a16
MJ		 8524 /* Exposing INVPCID only when PCID is exposed */
8525 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8526 if (vmx_invpcid_supported() &&
4f977045 8527 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8528 guest_cpuid_has_pcid(vcpu)) {
29282fde 8529 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8530 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8531 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8532 exec_control);
8533 } else {
29282fde
TI		 8534 if (cpu_has_secondary_exec_ctrls()) {
8535 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8536 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8537 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8538 exec_control);
8539 }
ad756a16 8540 if (best)
4f977045 8541 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8542 }
0e851880
SY		 8543}
8544
d4330ef2
JR		 8545static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8546{
7b8050f5
NHE		 8547 if (func == 1 && nested)
8548 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8549}
8550
25d92081
YZ		 8551static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8552 struct x86_exception *fault)
8553{
533558bc
JK		 8554 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8555 u32 exit_reason;
25d92081
YZ		 8556
8557 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8558 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8559 else
533558bc
JK		 8560 exit_reason = EXIT_REASON_EPT_VIOLATION;
8561 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8562 vmcs12->guest_physical_address = fault->address;
8563}
8564
155a97a3
NHE		 8565/* Callbacks for nested_ept_init_mmu_context: */
8566
8567static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8568{
8569 /* return the page table to be shadowed - in our case, EPT12 */
8570 return get_vmcs12(vcpu)->ept_pointer;
8571}
8572
8a3c1a33 8573static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8574{
ad896af0
PB		 8575 WARN_ON(mmu_is_nested(vcpu));
8576 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8577 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8578 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8579 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8580 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8581 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8582
8583 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8584}
8585
8586static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8587{
8588 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8589}
8590
19d5f10b
EK		 8591static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8592 u16 error_code)
8593{
8594 bool inequality, bit;
8595
8596 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8597 inequality =
8598 (error_code & vmcs12->page_fault_error_code_mask) !=
8599 vmcs12->page_fault_error_code_match;
8600 return inequality ^ bit;
8601}
8602
feaf0c7d
GN		 8603static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8604 struct x86_exception *fault)
8605{
8606 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8607
8608 WARN_ON(!is_guest_mode(vcpu));
8609
19d5f10b 8610 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8611 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8612 vmcs_read32(VM_EXIT_INTR_INFO),
8613 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8614 else
8615 kvm_inject_page_fault(vcpu, fault);
8616}
8617
a2bcba50
WL		 8618static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8619 struct vmcs12 *vmcs12)
8620{
8621 struct vcpu_vmx *vmx = to_vmx(vcpu);
8622
8623 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8624 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8625 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8626 return false;
8627
8628 /*
8629 * Translate L1 physical address to host physical
8630 * address for vmcs02. Keep the page pinned, so this
8631 * physical address remains valid. We keep a reference
8632 * to it so we can release it later.
8633 */
8634 if (vmx->nested.apic_access_page) /* shouldn't happen */
8635 nested_release_page(vmx->nested.apic_access_page);
8636 vmx->nested.apic_access_page =
8637 nested_get_page(vcpu, vmcs12->apic_access_addr);
8638 }
a7c0b07d
WL		 8639
8640 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8641 /* TODO: Also verify bits beyond physical address width are 0 */
8642 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8643 return false;
8644
8645 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8646 nested_release_page(vmx->nested.virtual_apic_page);
8647 vmx->nested.virtual_apic_page =
8648 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8649
8650 /*
8651 * Failing the vm entry is _not_ what the processor does
8652 * but it's basically the only possibility we have.
8653 * We could still enter the guest if CR8 load exits are
8654 * enabled, CR8 store exits are enabled, and virtualize APIC
8655 * access is disabled; in this case the processor would never
8656 * use the TPR shadow and we could simply clear the bit from
8657 * the execution control. But such a configuration is useless,
8658 * so let's keep the code simple.
8659 */
8660 if (!vmx->nested.virtual_apic_page)
8661 return false;
8662 }
8663
705699a1
WV		 8664 if (nested_cpu_has_posted_intr(vmcs12)) {
8665 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64))
8666 return false;
8667
8668 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8669 kunmap(vmx->nested.pi_desc_page);
8670 nested_release_page(vmx->nested.pi_desc_page);
8671 }
8672 vmx->nested.pi_desc_page =
8673 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8674 if (!vmx->nested.pi_desc_page)
8675 return false;
8676
8677 vmx->nested.pi_desc =
8678 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8679 if (!vmx->nested.pi_desc) {
8680 nested_release_page_clean(vmx->nested.pi_desc_page);
8681 return false;
8682 }
8683 vmx->nested.pi_desc =
8684 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8685 (unsigned long)(vmcs12->posted_intr_desc_addr &
8686 (PAGE_SIZE - 1)));
8687 }
8688
a2bcba50
WL		 8689 return true;
8690}
8691
f4124500
JK		 8692static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8693{
8694 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8695 struct vcpu_vmx *vmx = to_vmx(vcpu);
8696
8697 if (vcpu->arch.virtual_tsc_khz == 0)
8698 return;
8699
8700 /* Make sure short timeouts reliably trigger an immediate vmexit.
8701 * hrtimer_start does not guarantee this. */
8702 if (preemption_timeout <= 1) {
8703 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8704 return;
8705 }
8706
8707 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8708 preemption_timeout *= 1000000;
8709 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8710 hrtimer_start(&vmx->nested.preemption_timer,
8711 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8712}
8713
3af18d9c
WV		 8714static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8715 struct vmcs12 *vmcs12)
8716{
8717 int maxphyaddr;
8718 u64 addr;
8719
8720 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8721 return 0;
8722
8723 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8724 WARN_ON(1);
8725 return -EINVAL;
8726 }
8727 maxphyaddr = cpuid_maxphyaddr(vcpu);
8728
8729 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8730 ((addr + PAGE_SIZE) >> maxphyaddr))
8731 return -EINVAL;
8732
8733 return 0;
8734}
8735
8736/*
8737 * Merge L0's and L1's MSR bitmap, return false to indicate that
8738 * we do not use the hardware.
8739 */
8740static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8741 struct vmcs12 *vmcs12)
8742{
82f0dd4b 8743 int msr;
f2b93280
WV		 8744 struct page *page;
8745 unsigned long *msr_bitmap;
8746
8747 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8748 return false;
8749
8750 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8751 if (!page) {
8752 WARN_ON(1);
8753 return false;
8754 }
8755 msr_bitmap = (unsigned long *)kmap(page);
8756 if (!msr_bitmap) {
8757 nested_release_page_clean(page);
8758 WARN_ON(1);
8759 return false;
8760 }
8761
8762 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8763 if (nested_cpu_has_apic_reg_virt(vmcs12))
8764 for (msr = 0x800; msr <= 0x8ff; msr++)
8765 nested_vmx_disable_intercept_for_msr(
8766 msr_bitmap,
8767 vmx_msr_bitmap_nested,
8768 msr, MSR_TYPE_R);
f2b93280
WV		 8769 /* TPR is allowed */
8770 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8771 vmx_msr_bitmap_nested,
8772 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8773 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8774 if (nested_cpu_has_vid(vmcs12)) {
8775 /* EOI and self-IPI are allowed */
8776 nested_vmx_disable_intercept_for_msr(
8777 msr_bitmap,
8778 vmx_msr_bitmap_nested,
8779 APIC_BASE_MSR + (APIC_EOI >> 4),
8780 MSR_TYPE_W);
8781 nested_vmx_disable_intercept_for_msr(
8782 msr_bitmap,
8783 vmx_msr_bitmap_nested,
8784 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8785 MSR_TYPE_W);
8786 }
82f0dd4b
WV		 8787 } else {
8788 /*
8789 * Enable reading intercept of all the x2apic
8790 * MSRs. We should not rely on vmcs12 to do any
8791 * optimizations here, it may have been modified
8792 * by L1.
8793 */
8794 for (msr = 0x800; msr <= 0x8ff; msr++)
8795 __vmx_enable_intercept_for_msr(
8796 vmx_msr_bitmap_nested,
8797 msr,
8798 MSR_TYPE_R);
8799
f2b93280
WV		 8800 __vmx_enable_intercept_for_msr(
8801 vmx_msr_bitmap_nested,
8802 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8803 MSR_TYPE_W);
608406e2
WV		 8804 __vmx_enable_intercept_for_msr(
8805 vmx_msr_bitmap_nested,
8806 APIC_BASE_MSR + (APIC_EOI >> 4),
8807 MSR_TYPE_W);
8808 __vmx_enable_intercept_for_msr(
8809 vmx_msr_bitmap_nested,
8810 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8811 MSR_TYPE_W);
82f0dd4b 8812 }
f2b93280
WV		 8813 kunmap(page);
8814 nested_release_page_clean(page);
8815
8816 return true;
8817}
8818
8819static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8820 struct vmcs12 *vmcs12)
8821{
82f0dd4b 8822 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 8823 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 8824 !nested_cpu_has_vid(vmcs12) &&
8825 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 8826 return 0;
8827
8828 /*
8829 * If virtualize x2apic mode is enabled,
8830 * virtualize apic access must be disabled.
8831 */
82f0dd4b
WV		 8832 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8833 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 8834 return -EINVAL;
8835
608406e2
WV		 8836 /*
8837 * If virtual interrupt delivery is enabled,
8838 * we must exit on external interrupts.
8839 */
8840 if (nested_cpu_has_vid(vmcs12) &&
8841 !nested_exit_on_intr(vcpu))
8842 return -EINVAL;
8843
705699a1
WV		 8844 /*
8845 * bits 15:8 should be zero in posted_intr_nv,
8846 * the descriptor address has been already checked
8847 * in nested_get_vmcs12_pages.
8848 */
8849 if (nested_cpu_has_posted_intr(vmcs12) &&
8850 (!nested_cpu_has_vid(vmcs12) ||
8851 !nested_exit_intr_ack_set(vcpu) ||
8852 vmcs12->posted_intr_nv & 0xff00))
8853 return -EINVAL;
8854
f2b93280
WV		 8855 /* tpr shadow is needed by all apicv features. */
8856 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8857 return -EINVAL;
8858
8859 return 0;
3af18d9c
WV		 8860}
8861
e9ac033e
EK		 8862static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8863 unsigned long count_field,
8864 unsigned long addr_field,
8865 int maxphyaddr)
ff651cb6 8866{
e9ac033e
EK		 8867 u64 count, addr;
8868
8869 if (vmcs12_read_any(vcpu, count_field, &count) ||
8870 vmcs12_read_any(vcpu, addr_field, &addr)) {
8871 WARN_ON(1);
8872 return -EINVAL;
8873 }
8874 if (count == 0)
8875 return 0;
8876 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8877 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8878 pr_warn_ratelimited(
8879 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8880 addr_field, maxphyaddr, count, addr);
8881 return -EINVAL;
8882 }
8883 return 0;
8884}
8885
8886static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8887 struct vmcs12 *vmcs12)
8888{
8889 int maxphyaddr;
8890
8891 if (vmcs12->vm_exit_msr_load_count == 0 &&
8892 vmcs12->vm_exit_msr_store_count == 0 &&
8893 vmcs12->vm_entry_msr_load_count == 0)
8894 return 0; /* Fast path */
8895 maxphyaddr = cpuid_maxphyaddr(vcpu);
8896 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8897 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8898 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8899 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8900 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8901 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8902 return -EINVAL;
8903 return 0;
8904}
8905
8906static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8907 struct vmx_msr_entry *e)
8908{
8909 /* x2APIC MSR accesses are not allowed */
8910 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8911 return -EINVAL;
8912 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8913 e->index == MSR_IA32_UCODE_REV)
8914 return -EINVAL;
8915 if (e->reserved != 0)
ff651cb6
WV		 8916 return -EINVAL;
8917 return 0;
8918}
8919
e9ac033e
EK		 8920static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8921 struct vmx_msr_entry *e)
ff651cb6
WV		 8922{
8923 if (e->index == MSR_FS_BASE ||
8924 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8925 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8926 nested_vmx_msr_check_common(vcpu, e))
8927 return -EINVAL;
8928 return 0;
8929}
8930
8931static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8932 struct vmx_msr_entry *e)
8933{
8934 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8935 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8936 return -EINVAL;
8937 return 0;
8938}
8939
8940/*
8941 * Load guest's/host's msr at nested entry/exit.
8942 * return 0 for success, entry index for failure.
8943 */
8944static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8945{
8946 u32 i;
8947 struct vmx_msr_entry e;
8948 struct msr_data msr;
8949
8950 msr.host_initiated = false;
8951 for (i = 0; i < count; i++) {
e9ac033e
EK		 8952 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8953 &e, sizeof(e))) {
8954 pr_warn_ratelimited(
8955 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8956 __func__, i, gpa + i * sizeof(e));
ff651cb6 8957 goto fail;
e9ac033e
EK		 8958 }
8959 if (nested_vmx_load_msr_check(vcpu, &e)) {
8960 pr_warn_ratelimited(
8961 "%s check failed (%u, 0x%x, 0x%x)\n",
8962 __func__, i, e.index, e.reserved);
8963 goto fail;
8964 }
ff651cb6
WV		 8965 msr.index = e.index;
8966 msr.data = e.value;
e9ac033e
EK		 8967 if (kvm_set_msr(vcpu, &msr)) {
8968 pr_warn_ratelimited(
8969 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8970 __func__, i, e.index, e.value);
ff651cb6 8971 goto fail;
e9ac033e 8972 }
ff651cb6
WV		 8973 }
8974 return 0;
8975fail:
8976 return i + 1;
8977}
8978
8979static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8980{
8981 u32 i;
8982 struct vmx_msr_entry e;
8983
8984 for (i = 0; i < count; i++) {
e9ac033e
EK		 8985 if (kvm_read_guest(vcpu->kvm,
8986 gpa + i * sizeof(e),
8987 &e, 2 * sizeof(u32))) {
8988 pr_warn_ratelimited(
8989 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8990 __func__, i, gpa + i * sizeof(e));
ff651cb6 8991 return -EINVAL;
e9ac033e
EK		 8992 }
8993 if (nested_vmx_store_msr_check(vcpu, &e)) {
8994 pr_warn_ratelimited(
8995 "%s check failed (%u, 0x%x, 0x%x)\n",
8996 __func__, i, e.index, e.reserved);
ff651cb6 8997 return -EINVAL;
e9ac033e
EK		 8998 }
8999 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9000 pr_warn_ratelimited(
9001 "%s cannot read MSR (%u, 0x%x)\n",
9002 __func__, i, e.index);
9003 return -EINVAL;
9004 }
9005 if (kvm_write_guest(vcpu->kvm,
9006 gpa + i * sizeof(e) +
ff651cb6 9007 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 9008 &e.value, sizeof(e.value))) {
9009 pr_warn_ratelimited(
9010 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9011 __func__, i, e.index, e.value);
9012 return -EINVAL;
9013 }
ff651cb6
WV		 9014 }
9015 return 0;
9016}
9017
fe3ef05c
NHE		 9018/*
9019 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9020 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9021 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9022 * guest in a way that will both be appropriate to L1's requests, and our
9023 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9024 * function also has additional necessary side-effects, like setting various
9025 * vcpu->arch fields.
9026 */
9027static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9028{
9029 struct vcpu_vmx *vmx = to_vmx(vcpu);
9030 u32 exec_control;
9031
9032 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9033 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9034 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9035 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9036 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9037 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9038 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9039 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9040 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9041 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9042 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9043 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9044 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9045 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9046 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9047 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9048 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9049 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9050 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9051 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9052 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9053 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9054 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9055 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9056 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9057 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9058 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9059 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9060 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9061 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9062 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9063 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9064 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9065 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9066 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9067 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9068
2996fca0
JK		 9069 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9070 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9071 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9072 } else {
9073 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9074 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9075 }
fe3ef05c
NHE		 9076 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9077 vmcs12->vm_entry_intr_info_field);
9078 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9079 vmcs12->vm_entry_exception_error_code);
9080 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9081 vmcs12->vm_entry_instruction_len);
9082 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9083 vmcs12->guest_interruptibility_info);
fe3ef05c 9084 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9085 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9086 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9087 vmcs12->guest_pending_dbg_exceptions);
9088 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9089 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9090
81dc01f7
WL		 9091 if (nested_cpu_has_xsaves(vmcs12))
9092 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9093 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9094
f4124500
JK		 9095 exec_control = vmcs12->pin_based_vm_exec_control;
9096 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9097 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9098
9099 if (nested_cpu_has_posted_intr(vmcs12)) {
9100 /*
9101 * Note that we use L0's vector here and in
9102 * vmx_deliver_nested_posted_interrupt.
9103 */
9104 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9105 vmx->nested.pi_pending = false;
9106 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9107 vmcs_write64(POSTED_INTR_DESC_ADDR,
9108 page_to_phys(vmx->nested.pi_desc_page) +
9109 (unsigned long)(vmcs12->posted_intr_desc_addr &
9110 (PAGE_SIZE - 1)));
9111 } else
9112 exec_control &= ~PIN_BASED_POSTED_INTR;
9113
f4124500 9114 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9115
f4124500
JK		 9116 vmx->nested.preemption_timer_expired = false;
9117 if (nested_cpu_has_preemption_timer(vmcs12))
9118 vmx_start_preemption_timer(vcpu);
0238ea91 9119
fe3ef05c
NHE		 9120 /*
9121 * Whether page-faults are trapped is determined by a combination of
9122 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9123 * If enable_ept, L0 doesn't care about page faults and we should
9124 * set all of these to L1's desires. However, if !enable_ept, L0 does
9125 * care about (at least some) page faults, and because it is not easy
9126 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9127 * to exit on each and every L2 page fault. This is done by setting
9128 * MASK=MATCH=0 and (see below) EB.PF=1.
9129 * Note that below we don't need special code to set EB.PF beyond the
9130 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9131 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9132 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9133 *
9134 * A problem with this approach (when !enable_ept) is that L1 may be
9135 * injected with more page faults than it asked for. This could have
9136 * caused problems, but in practice existing hypervisors don't care.
9137 * To fix this, we will need to emulate the PFEC checking (on the L1
9138 * page tables), using walk_addr(), when injecting PFs to L1.
9139 */
9140 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9141 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9142 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9143 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9144
9145 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9146 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 9147 if (!vmx->rdtscp_enabled)
9148 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9149 /* Take the following fields only from vmcs12 */
696dfd95
PB		 9150 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9151 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9152 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 9153 if (nested_cpu_has(vmcs12,
9154 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9155 exec_control |= vmcs12->secondary_vm_exec_control;
9156
9157 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9158 /*
9159 * If translation failed, no matter: This feature asks
9160 * to exit when accessing the given address, and if it
9161 * can never be accessed, this feature won't do
9162 * anything anyway.
9163 */
9164 if (!vmx->nested.apic_access_page)
9165 exec_control &=
9166 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9167 else
9168 vmcs_write64(APIC_ACCESS_ADDR,
9169 page_to_phys(vmx->nested.apic_access_page));
f2b93280
WV		 9170 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9171 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
ca3f257a
JK		 9172 exec_control |=
9173 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9174 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9175 }
9176
608406e2
WV		 9177 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9178 vmcs_write64(EOI_EXIT_BITMAP0,
9179 vmcs12->eoi_exit_bitmap0);
9180 vmcs_write64(EOI_EXIT_BITMAP1,
9181 vmcs12->eoi_exit_bitmap1);
9182 vmcs_write64(EOI_EXIT_BITMAP2,
9183 vmcs12->eoi_exit_bitmap2);
9184 vmcs_write64(EOI_EXIT_BITMAP3,
9185 vmcs12->eoi_exit_bitmap3);
9186 vmcs_write16(GUEST_INTR_STATUS,
9187 vmcs12->guest_intr_status);
9188 }
9189
fe3ef05c
NHE		 9190 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9191 }
9192
9193
9194 /*
9195 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9196 * Some constant fields are set here by vmx_set_constant_host_state().
9197 * Other fields are different per CPU, and will be set later when
9198 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9199 */
a547c6db 9200 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9201
9202 /*
9203 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9204 * entry, but only if the current (host) sp changed from the value
9205 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9206 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9207 * here we just force the write to happen on entry.
9208 */
9209 vmx->host_rsp = 0;
9210
9211 exec_control = vmx_exec_control(vmx); /* L0's desires */
9212 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9213 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9214 exec_control &= ~CPU_BASED_TPR_SHADOW;
9215 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9216
9217 if (exec_control & CPU_BASED_TPR_SHADOW) {
9218 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9219 page_to_phys(vmx->nested.virtual_apic_page));
9220 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9221 }
9222
3af18d9c 9223 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9224 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9225 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9226 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9227 } else
9228 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9229
fe3ef05c 9230 /*
3af18d9c 9231 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9232 * Rather, exit every time.
9233 */
fe3ef05c
NHE		 9234 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9235 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9236
9237 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9238
9239 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9240 * bitwise-or of what L1 wants to trap for L2, and what we want to
9241 * trap. Note that CR0.TS also needs updating - we do this later.
9242 */
9243 update_exception_bitmap(vcpu);
9244 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9245 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9246
8049d651
NHE		 9247 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9248 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9249 * bits are further modified by vmx_set_efer() below.
9250 */
f4124500 9251 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9252
9253 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9254 * emulated by vmx_set_efer(), below.
9255 */
2961e876 9256 vm_entry_controls_init(vmx,
8049d651
NHE		 9257 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9258 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9259 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9260
44811c02 9261 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9262 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9263 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9264 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9265 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9266
9267
9268 set_cr4_guest_host_mask(vmx);
9269
36be0b9d
PB		 9270 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9271 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9272
27fc51b2
NHE		 9273 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9274 vmcs_write64(TSC_OFFSET,
9275 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9276 else
9277 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9278
9279 if (enable_vpid) {
9280 /*
9281 * Trivially support vpid by letting L2s share their parent
9282 * L1's vpid. TODO: move to a more elaborate solution, giving
9283 * each L2 its own vpid and exposing the vpid feature to L1.
9284 */
9285 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9286 vmx_flush_tlb(vcpu);
9287 }
9288
155a97a3
NHE		 9289 if (nested_cpu_has_ept(vmcs12)) {
9290 kvm_mmu_unload(vcpu);
9291 nested_ept_init_mmu_context(vcpu);
9292 }
9293
fe3ef05c
NHE		 9294 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9295 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9296 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9297 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9298 else
9299 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9300 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9301 vmx_set_efer(vcpu, vcpu->arch.efer);
9302
9303 /*
9304 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9305 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9306 * The CR0_READ_SHADOW is what L2 should have expected to read given
9307 * the specifications by L1; It's not enough to take
9308 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9309 * have more bits than L1 expected.
9310 */
9311 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9312 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9313
9314 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9315 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9316
9317 /* shadow page tables on either EPT or shadow page tables */
9318 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9319 kvm_mmu_reset_context(vcpu);
9320
feaf0c7d
GN		 9321 if (!enable_ept)
9322 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9323
3633cfc3
NHE		 9324 /*
9325 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9326 */
9327 if (enable_ept) {
9328 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9329 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9330 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9331 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9332 }
9333
fe3ef05c
NHE		 9334 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9335 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9336}
9337
cd232ad0
NHE		 9338/*
9339 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9340 * for running an L2 nested guest.
9341 */
9342static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9343{
9344 struct vmcs12 *vmcs12;
9345 struct vcpu_vmx *vmx = to_vmx(vcpu);
9346 int cpu;
9347 struct loaded_vmcs *vmcs02;
384bb783 9348 bool ia32e;
ff651cb6 9349 u32 msr_entry_idx;
cd232ad0
NHE		 9350
9351 if (!nested_vmx_check_permission(vcpu) ||
9352 !nested_vmx_check_vmcs12(vcpu))
9353 return 1;
9354
9355 skip_emulated_instruction(vcpu);
9356 vmcs12 = get_vmcs12(vcpu);
9357
012f83cb
AG		 9358 if (enable_shadow_vmcs)
9359 copy_shadow_to_vmcs12(vmx);
9360
7c177938
NHE		 9361 /*
9362 * The nested entry process starts with enforcing various prerequisites
9363 * on vmcs12 as required by the Intel SDM, and act appropriately when
9364 * they fail: As the SDM explains, some conditions should cause the
9365 * instruction to fail, while others will cause the instruction to seem
9366 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9367 * To speed up the normal (success) code path, we should avoid checking
9368 * for misconfigurations which will anyway be caught by the processor
9369 * when using the merged vmcs02.
9370 */
9371 if (vmcs12->launch_state == launch) {
9372 nested_vmx_failValid(vcpu,
9373 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9374 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9375 return 1;
9376 }
9377
6dfacadd
JK		 9378 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9379 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9380 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9381 return 1;
9382 }
9383
3af18d9c 9384 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9385 /*TODO: Also verify bits beyond physical address width are 0*/
9386 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9387 return 1;
9388 }
9389
3af18d9c 9390 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9391 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9392 return 1;
9393 }
9394
f2b93280
WV		 9395 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9396 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9397 return 1;
9398 }
9399
e9ac033e
EK		 9400 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9401 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9402 return 1;
9403 }
9404
7c177938 9405 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9406 vmx->nested.nested_vmx_true_procbased_ctls_low,
9407 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9408 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9409 vmx->nested.nested_vmx_secondary_ctls_low,
9410 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9411 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9412 vmx->nested.nested_vmx_pinbased_ctls_low,
9413 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9414 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9415 vmx->nested.nested_vmx_true_exit_ctls_low,
9416 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9417 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9418 vmx->nested.nested_vmx_true_entry_ctls_low,
9419 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9420 {
9421 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9422 return 1;
9423 }
9424
9425 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9426 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9427 nested_vmx_failValid(vcpu,
9428 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9429 return 1;
9430 }
9431
b9c237bb 9432 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9433 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9434 nested_vmx_entry_failure(vcpu, vmcs12,
9435 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9436 return 1;
9437 }
9438 if (vmcs12->vmcs_link_pointer != -1ull) {
9439 nested_vmx_entry_failure(vcpu, vmcs12,
9440 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9441 return 1;
9442 }
9443
384bb783 9444 /*
cb0c8cda 9445 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9446 * are performed on the field for the IA32_EFER MSR:
9447 * - Bits reserved in the IA32_EFER MSR must be 0.
9448 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9449 * the IA-32e mode guest VM-exit control. It must also be identical
9450 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9451 * CR0.PG) is 1.
9452 */
9453 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9454 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9455 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9456 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9457 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9458 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9459 nested_vmx_entry_failure(vcpu, vmcs12,
9460 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9461 return 1;
9462 }
9463 }
9464
9465 /*
9466 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9467 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9468 * the values of the LMA and LME bits in the field must each be that of
9469 * the host address-space size VM-exit control.
9470 */
9471 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9472 ia32e = (vmcs12->vm_exit_controls &
9473 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9474 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9475 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9476 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9477 nested_vmx_entry_failure(vcpu, vmcs12,
9478 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9479 return 1;
9480 }
9481 }
9482
7c177938
NHE		 9483 /*
9484 * We're finally done with prerequisite checking, and can start with
9485 * the nested entry.
9486 */
9487
cd232ad0
NHE		 9488 vmcs02 = nested_get_current_vmcs02(vmx);
9489 if (!vmcs02)
9490 return -ENOMEM;
9491
9492 enter_guest_mode(vcpu);
9493
9494 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9495
2996fca0
JK		 9496 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9497 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9498
cd232ad0
NHE		 9499 cpu = get_cpu();
9500 vmx->loaded_vmcs = vmcs02;
9501 vmx_vcpu_put(vcpu);
9502 vmx_vcpu_load(vcpu, cpu);
9503 vcpu->cpu = cpu;
9504 put_cpu();
9505
36c3cc42
JK		 9506 vmx_segment_cache_clear(vmx);
9507
cd232ad0
NHE		 9508 prepare_vmcs02(vcpu, vmcs12);
9509
ff651cb6
WV		 9510 msr_entry_idx = nested_vmx_load_msr(vcpu,
9511 vmcs12->vm_entry_msr_load_addr,
9512 vmcs12->vm_entry_msr_load_count);
9513 if (msr_entry_idx) {
9514 leave_guest_mode(vcpu);
9515 vmx_load_vmcs01(vcpu);
9516 nested_vmx_entry_failure(vcpu, vmcs12,
9517 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9518 return 1;
9519 }
9520
9521 vmcs12->launch_state = 1;
9522
6dfacadd
JK		 9523 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9524 return kvm_emulate_halt(vcpu);
9525
7af40ad3
JK		 9526 vmx->nested.nested_run_pending = 1;
9527
cd232ad0
NHE		 9528 /*
9529 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9530 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9531 * returned as far as L1 is concerned. It will only return (and set
9532 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9533 */
9534 return 1;
9535}
9536
4704d0be
NHE		 9537/*
9538 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9539 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9540 * This function returns the new value we should put in vmcs12.guest_cr0.
9541 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9542 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9543 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9544 * didn't trap the bit, because if L1 did, so would L0).
9545 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9546 * been modified by L2, and L1 knows it. So just leave the old value of
9547 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9548 * isn't relevant, because if L0 traps this bit it can set it to anything.
9549 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9550 * changed these bits, and therefore they need to be updated, but L0
9551 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9552 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9553 */
9554static inline unsigned long
9555vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9556{
9557 return
9558 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9559 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9560 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9561 vcpu->arch.cr0_guest_owned_bits));
9562}
9563
9564static inline unsigned long
9565vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9566{
9567 return
9568 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9569 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9570 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9571 vcpu->arch.cr4_guest_owned_bits));
9572}
9573
5f3d5799
JK		 9574static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9575 struct vmcs12 *vmcs12)
9576{
9577 u32 idt_vectoring;
9578 unsigned int nr;
9579
851eb667 9580 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9581 nr = vcpu->arch.exception.nr;
9582 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9583
9584 if (kvm_exception_is_soft(nr)) {
9585 vmcs12->vm_exit_instruction_len =
9586 vcpu->arch.event_exit_inst_len;
9587 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9588 } else
9589 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9590
9591 if (vcpu->arch.exception.has_error_code) {
9592 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9593 vmcs12->idt_vectoring_error_code =
9594 vcpu->arch.exception.error_code;
9595 }
9596
9597 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9598 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9599 vmcs12->idt_vectoring_info_field =
9600 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9601 } else if (vcpu->arch.interrupt.pending) {
9602 nr = vcpu->arch.interrupt.nr;
9603 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9604
9605 if (vcpu->arch.interrupt.soft) {
9606 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9607 vmcs12->vm_entry_instruction_len =
9608 vcpu->arch.event_exit_inst_len;
9609 } else
9610 idt_vectoring |= INTR_TYPE_EXT_INTR;
9611
9612 vmcs12->idt_vectoring_info_field = idt_vectoring;
9613 }
9614}
9615
b6b8a145
JK		 9616static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9617{
9618 struct vcpu_vmx *vmx = to_vmx(vcpu);
9619
f4124500
JK		 9620 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9621 vmx->nested.preemption_timer_expired) {
9622 if (vmx->nested.nested_run_pending)
9623 return -EBUSY;
9624 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9625 return 0;
9626 }
9627
b6b8a145 9628 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9629 if (vmx->nested.nested_run_pending ||
9630 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9631 return -EBUSY;
9632 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9633 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9634 INTR_INFO_VALID_MASK, 0);
9635 /*
9636 * The NMI-triggered VM exit counts as injection:
9637 * clear this one and block further NMIs.
9638 */
9639 vcpu->arch.nmi_pending = 0;
9640 vmx_set_nmi_mask(vcpu, true);
9641 return 0;
9642 }
9643
9644 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9645 nested_exit_on_intr(vcpu)) {
9646 if (vmx->nested.nested_run_pending)
9647 return -EBUSY;
9648 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9649 return 0;
b6b8a145
JK		 9650 }
9651
705699a1 9652 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9653}
9654
f4124500
JK		 9655static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9656{
9657 ktime_t remaining =
9658 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9659 u64 value;
9660
9661 if (ktime_to_ns(remaining) <= 0)
9662 return 0;
9663
9664 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9665 do_div(value, 1000000);
9666 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9667}
9668
4704d0be
NHE		 9669/*
9670 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9671 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9672 * and this function updates it to reflect the changes to the guest state while
9673 * L2 was running (and perhaps made some exits which were handled directly by L0
9674 * without going back to L1), and to reflect the exit reason.
9675 * Note that we do not have to copy here all VMCS fields, just those that
9676 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9677 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9678 * which already writes to vmcs12 directly.
9679 */
533558bc
JK		 9680static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9681 u32 exit_reason, u32 exit_intr_info,
9682 unsigned long exit_qualification)
4704d0be
NHE		 9683{
9684 /* update guest state fields: */
9685 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9686 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9687
4704d0be
NHE		 9688 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9689 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9690 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9691
9692 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9693 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9694 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9695 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9696 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9697 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9698 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9699 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9700 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9701 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9702 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9703 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9704 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9705 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9706 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9707 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9708 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9709 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9710 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9711 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9712 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9713 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9714 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9715 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9716 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9717 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9718 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9719 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9720 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9721 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9722 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9723 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9724 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9725 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9726 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9727 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9728
4704d0be
NHE		 9729 vmcs12->guest_interruptibility_info =
9730 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9731 vmcs12->guest_pending_dbg_exceptions =
9732 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9733 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9734 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9735 else
9736 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9737
f4124500
JK		 9738 if (nested_cpu_has_preemption_timer(vmcs12)) {
9739 if (vmcs12->vm_exit_controls &
9740 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9741 vmcs12->vmx_preemption_timer_value =
9742 vmx_get_preemption_timer_value(vcpu);
9743 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9744 }
7854cbca 9745
3633cfc3
NHE		 9746 /*
9747 * In some cases (usually, nested EPT), L2 is allowed to change its
9748 * own CR3 without exiting. If it has changed it, we must keep it.
9749 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9750 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9751 *
9752 * Additionally, restore L2's PDPTR to vmcs12.
9753 */
9754 if (enable_ept) {
9755 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9756 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9757 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9758 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9759 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9760 }
9761
608406e2
WV		 9762 if (nested_cpu_has_vid(vmcs12))
9763 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9764
c18911a2
JK		 9765 vmcs12->vm_entry_controls =
9766 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9767 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9768
2996fca0
JK		 9769 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9770 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9771 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9772 }
9773
4704d0be
NHE		 9774 /* TODO: These cannot have changed unless we have MSR bitmaps and
9775 * the relevant bit asks not to trap the change */
b8c07d55 9776 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9777 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9778 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9779 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9780 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9781 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9782 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9783 if (vmx_mpx_supported())
9784 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9785 if (nested_cpu_has_xsaves(vmcs12))
9786 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9787
9788 /* update exit information fields: */
9789
533558bc
JK		 9790 vmcs12->vm_exit_reason = exit_reason;
9791 vmcs12->exit_qualification = exit_qualification;
4704d0be 9792
533558bc 9793 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9794 if ((vmcs12->vm_exit_intr_info &
9795 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9796 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9797 vmcs12->vm_exit_intr_error_code =
9798 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9799 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9800 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9801 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9802
5f3d5799
JK		 9803 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9804 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9805 * instead of reading the real value. */
4704d0be 9806 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9807
9808 /*
9809 * Transfer the event that L0 or L1 may wanted to inject into
9810 * L2 to IDT_VECTORING_INFO_FIELD.
9811 */
9812 vmcs12_save_pending_event(vcpu, vmcs12);
9813 }
9814
9815 /*
9816 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9817 * preserved above and would only end up incorrectly in L1.
9818 */
9819 vcpu->arch.nmi_injected = false;
9820 kvm_clear_exception_queue(vcpu);
9821 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9822}
9823
9824/*
9825 * A part of what we need to when the nested L2 guest exits and we want to
9826 * run its L1 parent, is to reset L1's guest state to the host state specified
9827 * in vmcs12.
9828 * This function is to be called not only on normal nested exit, but also on
9829 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9830 * Failures During or After Loading Guest State").
9831 * This function should be called when the active VMCS is L1's (vmcs01).
9832 */
733568f9
JK		 9833static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9834 struct vmcs12 *vmcs12)
4704d0be 9835{
21feb4eb
ACL		 9836 struct kvm_segment seg;
9837
4704d0be
NHE		 9838 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9839 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9840 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9841 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9842 else
9843 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9844 vmx_set_efer(vcpu, vcpu->arch.efer);
9845
9846 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9847 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9848 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9849 /*
9850 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9851 * actually changed, because it depends on the current state of
9852 * fpu_active (which may have changed).
9853 * Note that vmx_set_cr0 refers to efer set above.
9854 */
9e3e4dbf 9855 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9856 /*
9857 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9858 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9859 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9860 */
9861 update_exception_bitmap(vcpu);
9862 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9863 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9864
9865 /*
9866 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9867 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9868 */
9869 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9870 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9871
29bf08f1 9872 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9873
4704d0be
NHE		 9874 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9875 kvm_mmu_reset_context(vcpu);
9876
feaf0c7d
GN		 9877 if (!enable_ept)
9878 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9879
4704d0be
NHE		 9880 if (enable_vpid) {
9881 /*
9882 * Trivially support vpid by letting L2s share their parent
9883 * L1's vpid. TODO: move to a more elaborate solution, giving
9884 * each L2 its own vpid and exposing the vpid feature to L1.
9885 */
9886 vmx_flush_tlb(vcpu);
9887 }
9888
9889
9890 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9891 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9892 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9893 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9894 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9895
36be0b9d
PB		 9896 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9897 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9898 vmcs_write64(GUEST_BNDCFGS, 0);
9899
44811c02 9900 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9901 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9902 vcpu->arch.pat = vmcs12->host_ia32_pat;
9903 }
4704d0be
NHE		 9904 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9905 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9906 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9907
21feb4eb
ACL		 9908 /* Set L1 segment info according to Intel SDM
9909 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9910 seg = (struct kvm_segment) {
9911 .base = 0,
9912 .limit = 0xFFFFFFFF,
9913 .selector = vmcs12->host_cs_selector,
9914 .type = 11,
9915 .present = 1,
9916 .s = 1,
9917 .g = 1
9918 };
9919 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9920 seg.l = 1;
9921 else
9922 seg.db = 1;
9923 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9924 seg = (struct kvm_segment) {
9925 .base = 0,
9926 .limit = 0xFFFFFFFF,
9927 .type = 3,
9928 .present = 1,
9929 .s = 1,
9930 .db = 1,
9931 .g = 1
9932 };
9933 seg.selector = vmcs12->host_ds_selector;
9934 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9935 seg.selector = vmcs12->host_es_selector;
9936 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9937 seg.selector = vmcs12->host_ss_selector;
9938 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9939 seg.selector = vmcs12->host_fs_selector;
9940 seg.base = vmcs12->host_fs_base;
9941 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9942 seg.selector = vmcs12->host_gs_selector;
9943 seg.base = vmcs12->host_gs_base;
9944 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9945 seg = (struct kvm_segment) {
205befd9 9946 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9947 .limit = 0x67,
9948 .selector = vmcs12->host_tr_selector,
9949 .type = 11,
9950 .present = 1
9951 };
9952 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9953
503cd0c5
JK		 9954 kvm_set_dr(vcpu, 7, 0x400);
9955 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 9956
3af18d9c
WV		 9957 if (cpu_has_vmx_msr_bitmap())
9958 vmx_set_msr_bitmap(vcpu);
9959
ff651cb6
WV		 9960 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9961 vmcs12->vm_exit_msr_load_count))
9962 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9963}
9964
9965/*
9966 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9967 * and modify vmcs12 to make it see what it would expect to see there if
9968 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9969 */
533558bc
JK		 9970static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9971 u32 exit_intr_info,
9972 unsigned long exit_qualification)
4704d0be
NHE		 9973{
9974 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9975 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9976
5f3d5799
JK		 9977 /* trying to cancel vmlaunch/vmresume is a bug */
9978 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9979
4704d0be 9980 leave_guest_mode(vcpu);
533558bc
JK		 9981 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9982 exit_qualification);
4704d0be 9983
ff651cb6
WV		 9984 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9985 vmcs12->vm_exit_msr_store_count))
9986 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9987
f3380ca5
WL		 9988 vmx_load_vmcs01(vcpu);
9989
77b0f5d6
BD		 9990 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9991 && nested_exit_intr_ack_set(vcpu)) {
9992 int irq = kvm_cpu_get_interrupt(vcpu);
9993 WARN_ON(irq < 0);
9994 vmcs12->vm_exit_intr_info = irq |
9995 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9996 }
9997
542060ea
JK		 9998 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9999 vmcs12->exit_qualification,
10000 vmcs12->idt_vectoring_info_field,
10001 vmcs12->vm_exit_intr_info,
10002 vmcs12->vm_exit_intr_error_code,
10003 KVM_ISA_VMX);
4704d0be 10004
2961e876
GN		 10005 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10006 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10007 vmx_segment_cache_clear(vmx);
10008
4704d0be
NHE		 10009 /* if no vmcs02 cache requested, remove the one we used */
10010 if (VMCS02_POOL_SIZE == 0)
10011 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10012
10013 load_vmcs12_host_state(vcpu, vmcs12);
10014
27fc51b2 10015 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10016 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10017
10018 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10019 vmx->host_rsp = 0;
10020
10021 /* Unpin physical memory we referred to in vmcs02 */
10022 if (vmx->nested.apic_access_page) {
10023 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10024 vmx->nested.apic_access_page = NULL;
4704d0be 10025 }
a7c0b07d
WL		 10026 if (vmx->nested.virtual_apic_page) {
10027 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10028 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10029 }
705699a1
WV		 10030 if (vmx->nested.pi_desc_page) {
10031 kunmap(vmx->nested.pi_desc_page);
10032 nested_release_page(vmx->nested.pi_desc_page);
10033 vmx->nested.pi_desc_page = NULL;
10034 vmx->nested.pi_desc = NULL;
10035 }
4704d0be 10036
38b99173
TC		 10037 /*
10038 * We are now running in L2, mmu_notifier will force to reload the
10039 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10040 */
10041 kvm_vcpu_reload_apic_access_page(vcpu);
10042
4704d0be
NHE		 10043 /*
10044 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10045 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10046 * success or failure flag accordingly.
10047 */
10048 if (unlikely(vmx->fail)) {
10049 vmx->fail = 0;
10050 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10051 } else
10052 nested_vmx_succeed(vcpu);
012f83cb
AG		 10053 if (enable_shadow_vmcs)
10054 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10055
10056 /* in case we halted in L2 */
10057 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10058}
10059
42124925
JK		 10060/*
10061 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10062 */
10063static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10064{
10065 if (is_guest_mode(vcpu))
533558bc 10066 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10067 free_nested(to_vmx(vcpu));
10068}
10069
7c177938
NHE		 10070/*
10071 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10072 * 23.7 "VM-entry failures during or after loading guest state" (this also
10073 * lists the acceptable exit-reason and exit-qualification parameters).
10074 * It should only be called before L2 actually succeeded to run, and when
10075 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10076 */
10077static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10078 struct vmcs12 *vmcs12,
10079 u32 reason, unsigned long qualification)
10080{
10081 load_vmcs12_host_state(vcpu, vmcs12);
10082 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10083 vmcs12->exit_qualification = qualification;
10084 nested_vmx_succeed(vcpu);
012f83cb
AG		 10085 if (enable_shadow_vmcs)
10086 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10087}
10088
8a76d7f2
JR		 10089static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10090 struct x86_instruction_info *info,
10091 enum x86_intercept_stage stage)
10092{
10093 return X86EMUL_CONTINUE;
10094}
10095
48d89b92 10096static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10097{
b4a2d31d
RK		 10098 if (ple_gap)
10099 shrink_ple_window(vcpu);
ae97a3b8
RK		 10100}
10101
843e4330
KH		 10102static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10103 struct kvm_memory_slot *slot)
10104{
10105 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10106 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10107}
10108
10109static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10110 struct kvm_memory_slot *slot)
10111{
10112 kvm_mmu_slot_set_dirty(kvm, slot);
10113}
10114
10115static void vmx_flush_log_dirty(struct kvm *kvm)
10116{
10117 kvm_flush_pml_buffers(kvm);
10118}
10119
10120static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10121 struct kvm_memory_slot *memslot,
10122 gfn_t offset, unsigned long mask)
10123{
10124 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10125}
10126
cbdd1bea 10127static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10128 .cpu_has_kvm_support = cpu_has_kvm_support,
10129 .disabled_by_bios = vmx_disabled_by_bios,
10130 .hardware_setup = hardware_setup,
10131 .hardware_unsetup = hardware_unsetup,
002c7f7c 10132 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10133 .hardware_enable = hardware_enable,
10134 .hardware_disable = hardware_disable,
04547156 10135 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 10136
10137 .vcpu_create = vmx_create_vcpu,
10138 .vcpu_free = vmx_free_vcpu,
04d2cc77 10139 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10140
04d2cc77 10141 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10142 .vcpu_load = vmx_vcpu_load,
10143 .vcpu_put = vmx_vcpu_put,
10144
c8639010 10145 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10146 .get_msr = vmx_get_msr,
10147 .set_msr = vmx_set_msr,
10148 .get_segment_base = vmx_get_segment_base,
10149 .get_segment = vmx_get_segment,
10150 .set_segment = vmx_set_segment,
2e4d2653 10151 .get_cpl = vmx_get_cpl,
6aa8b732 10152 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10153 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10154 .decache_cr3 = vmx_decache_cr3,
25c4c276 10155 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10156 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10157 .set_cr3 = vmx_set_cr3,
10158 .set_cr4 = vmx_set_cr4,
6aa8b732 10159 .set_efer = vmx_set_efer,
6aa8b732
AK		 10160 .get_idt = vmx_get_idt,
10161 .set_idt = vmx_set_idt,
10162 .get_gdt = vmx_get_gdt,
10163 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10164 .get_dr6 = vmx_get_dr6,
10165 .set_dr6 = vmx_set_dr6,
020df079 10166 .set_dr7 = vmx_set_dr7,
81908bf4 10167 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10168 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10169 .get_rflags = vmx_get_rflags,
10170 .set_rflags = vmx_set_rflags,
02daab21 10171 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10172
10173 .tlb_flush = vmx_flush_tlb,
6aa8b732 10174
6aa8b732 10175 .run = vmx_vcpu_run,
6062d012 10176 .handle_exit = vmx_handle_exit,
6aa8b732 10177 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10178 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10179 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10180 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10181 .set_irq = vmx_inject_irq,
95ba8273 10182 .set_nmi = vmx_inject_nmi,
298101da 10183 .queue_exception = vmx_queue_exception,
b463a6f7 10184 .cancel_injection = vmx_cancel_injection,
78646121 10185 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10186 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10187 .get_nmi_mask = vmx_get_nmi_mask,
10188 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10189 .enable_nmi_window = enable_nmi_window,
10190 .enable_irq_window = enable_irq_window,
10191 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10192 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10193 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 10194 .vm_has_apicv = vmx_vm_has_apicv,
10195 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10196 .hwapic_irr_update = vmx_hwapic_irr_update,
10197 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10198 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10199 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10200
cbc94022 10201 .set_tss_addr = vmx_set_tss_addr,
67253af5 10202 .get_tdp_level = get_ept_level,
4b12f0de 10203 .get_mt_mask = vmx_get_mt_mask,
229456fc 10204
586f9607 10205 .get_exit_info = vmx_get_exit_info,
586f9607 10206
17cc3935 10207 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10208
10209 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10210
10211 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10212 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10213
10214 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10215
10216 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10217
4051b188 10218 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10219 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10220 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10221 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10222 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10223 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10224
10225 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10226
10227 .check_intercept = vmx_check_intercept,
a547c6db 10228 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10229 .mpx_supported = vmx_mpx_supported,
55412b2e 10230 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10231
10232 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10233
10234 .sched_in = vmx_sched_in,
843e4330
KH		 10235
10236 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10237 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10238 .flush_log_dirty = vmx_flush_log_dirty,
10239 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 10240};
10241
10242static int __init vmx_init(void)
10243{
34a1cd60
TC		 10244 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10245 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10246 if (r)
34a1cd60 10247 return r;
25c5f225 10248
8f536b76
ZY		 10249#ifdef CONFIG_KEXEC
10250 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10251 crash_vmclear_local_loaded_vmcss);
10252#endif
10253
fdef3ad1 10254 return 0;
6aa8b732
AK		 10255}
10256
10257static void __exit vmx_exit(void)
10258{
8f536b76 10259#ifdef CONFIG_KEXEC
3b63a43f 10260 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10261 synchronize_rcu();
10262#endif
10263
cb498ea2 10264 kvm_exit();
6aa8b732
AK		 10265}
10266
10267module_init(vmx_init)
10268module_exit(vmx_exit)
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