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target-i386: Use cpu_generic_init() in cpu_x86_init()
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
296acb64
JR		 248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
a9321a4d 259static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 260 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
f7fda280
XG		 262 "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
263 "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 264};
265
f74eefe0
HH		 266static const char *cpuid_7_0_ecx_feature_name[] = {
267 NULL, NULL, NULL, "pku",
268 "ospke", NULL, NULL, NULL,
269 NULL, NULL, NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274 NULL, NULL, NULL, NULL,
275};
276
303752a9
MT		 277static const char *cpuid_apm_edx_feature_name[] = {
278 NULL, NULL, NULL, NULL,
279 NULL, NULL, NULL, NULL,
280 "invtsc", NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286};
287
0bb0b2d2
PB		 288static const char *cpuid_xsave_feature_name[] = {
289 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
290 NULL, NULL, NULL, NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296 NULL, NULL, NULL, NULL,
297};
298
28b8e4d0
JK		 299static const char *cpuid_6_feature_name[] = {
300 NULL, NULL, "arat", NULL,
301 NULL, NULL, NULL, NULL,
302 NULL, NULL, NULL, NULL,
303 NULL, NULL, NULL, NULL,
304 NULL, NULL, NULL, NULL,
305 NULL, NULL, NULL, NULL,
306 NULL, NULL, NULL, NULL,
307 NULL, NULL, NULL, NULL,
308};
309
621626ce
EH		 310#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
311#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
312 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
313#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
314 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
315 CPUID_PSE36 | CPUID_FXSR)
316#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
317#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
318 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
319 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
320 CPUID_PAE | CPUID_SEP | CPUID_APIC)
321
322#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
323 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
324 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
325 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 326 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 327 /* partly implemented:
328 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
329 /* missing:
330 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
331#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
332 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
333 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 334 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 335 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
336 /* missing:
337 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
338 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
339 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 340 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
341 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 342
343#ifdef TARGET_X86_64
344#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
345#else
346#define TCG_EXT2_X86_64_FEATURES 0
347#endif
348
349#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
350 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
351 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
352 TCG_EXT2_X86_64_FEATURES)
353#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
354 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
355#define TCG_EXT4_FEATURES 0
356#define TCG_SVM_FEATURES 0
357#define TCG_KVM_FEATURES 0
358#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 359 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
360 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
07929f2a 361 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE)
621626ce 362 /* missing:
07929f2a 363 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
621626ce
EH		 364 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
365 CPUID_7_0_EBX_RDSEED */
0f70ed47 366#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 367#define TCG_APM_FEATURES 0
28b8e4d0 368#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 369#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
370 /* missing:
371 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 372
5ef57876
EH		 373typedef struct FeatureWordInfo {
374 const char **feat_names;
04d104b6
EH		 375 uint32_t cpuid_eax; /* Input EAX for CPUID */
376 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
377 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
378 int cpuid_reg; /* output register (R_* constant) */
37ce3522 379 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 380 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 381} FeatureWordInfo;
382
383static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 384 [FEAT_1_EDX] = {
385 .feat_names = feature_name,
386 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 387 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 388 },
389 [FEAT_1_ECX] = {
390 .feat_names = ext_feature_name,
391 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 392 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 393 },
394 [FEAT_8000_0001_EDX] = {
395 .feat_names = ext2_feature_name,
396 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 397 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 398 },
399 [FEAT_8000_0001_ECX] = {
400 .feat_names = ext3_feature_name,
401 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 402 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 403 },
89e49c8b
EH		 404 [FEAT_C000_0001_EDX] = {
405 .feat_names = ext4_feature_name,
406 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 407 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 408 },
bffd67b0
EH		 409 [FEAT_KVM] = {
410 .feat_names = kvm_feature_name,
411 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 412 .tcg_features = TCG_KVM_FEATURES,
bffd67b0
EH		 413 },
414 [FEAT_SVM] = {
415 .feat_names = svm_feature_name,
416 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 417 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 418 },
419 [FEAT_7_0_EBX] = {
420 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 421 .cpuid_eax = 7,
422 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
423 .cpuid_reg = R_EBX,
37ce3522 424 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 425 },
f74eefe0
HH		 426 [FEAT_7_0_ECX] = {
427 .feat_names = cpuid_7_0_ecx_feature_name,
428 .cpuid_eax = 7,
429 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
430 .cpuid_reg = R_ECX,
431 .tcg_features = TCG_7_0_ECX_FEATURES,
432 },
303752a9
MT		 433 [FEAT_8000_0007_EDX] = {
434 .feat_names = cpuid_apm_edx_feature_name,
435 .cpuid_eax = 0x80000007,
436 .cpuid_reg = R_EDX,
437 .tcg_features = TCG_APM_FEATURES,
438 .unmigratable_flags = CPUID_APM_INVTSC,
439 },
0bb0b2d2
PB		 440 [FEAT_XSAVE] = {
441 .feat_names = cpuid_xsave_feature_name,
442 .cpuid_eax = 0xd,
443 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
444 .cpuid_reg = R_EAX,
c9cfe8f9 445 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 446 },
28b8e4d0
JK		 447 [FEAT_6_EAX] = {
448 .feat_names = cpuid_6_feature_name,
449 .cpuid_eax = 6, .cpuid_reg = R_EAX,
450 .tcg_features = TCG_6_EAX_FEATURES,
451 },
5ef57876
EH		 452};
453
8e8aba50
EH		 454typedef struct X86RegisterInfo32 {
455 /* Name of register */
456 const char *name;
457 /* QAPI enum value register */
458 X86CPURegister32 qapi_enum;
459} X86RegisterInfo32;
460
461#define REGISTER(reg) \
5d371f41 462 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 463static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 464 REGISTER(EAX),
465 REGISTER(ECX),
466 REGISTER(EDX),
467 REGISTER(EBX),
468 REGISTER(ESP),
469 REGISTER(EBP),
470 REGISTER(ESI),
471 REGISTER(EDI),
472};
473#undef REGISTER
474
f4f1110e 475const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB		 476 [XSTATE_YMM_BIT] =
477 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 478 .offset = offsetof(X86XSaveArea, avx_state),
479 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 480 [XSTATE_BNDREGS_BIT] =
481 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 482 .offset = offsetof(X86XSaveArea, bndreg_state),
483 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 484 [XSTATE_BNDCSR_BIT] =
485 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 486 .offset = offsetof(X86XSaveArea, bndcsr_state),
487 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 488 [XSTATE_OPMASK_BIT] =
489 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 490 .offset = offsetof(X86XSaveArea, opmask_state),
491 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 492 [XSTATE_ZMM_Hi256_BIT] =
493 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 494 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
495 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 496 [XSTATE_Hi16_ZMM_BIT] =
497 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 498 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
499 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 500 [XSTATE_PKRU_BIT] =
501 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 502 .offset = offsetof(X86XSaveArea, pkru_state),
503 .size = sizeof(XSavePKRU) },
2560f19f 504};
8e8aba50 505
8b4beddc
EH		 506const char *get_register_name_32(unsigned int reg)
507{
31ccdde2 508 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 509 return NULL;
510 }
8e8aba50 511 return x86_reg_info_32[reg].name;
8b4beddc
EH		 512}
513
84f1b92f
EH		 514/*
515 * Returns the set of feature flags that are supported and migratable by
516 * QEMU, for a given FeatureWord.
517 */
518static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
519{
520 FeatureWordInfo *wi = &feature_word_info[w];
521 uint32_t r = 0;
522 int i;
523
524 for (i = 0; i < 32; i++) {
525 uint32_t f = 1U << i;
526 /* If the feature name is unknown, it is not supported by QEMU yet */
527 if (!wi->feat_names[i]) {
528 continue;
529 }
530 /* Skip features known to QEMU, but explicitly marked as unmigratable */
531 if (wi->unmigratable_flags & f) {
532 continue;
533 }
534 r |= f;
535 }
536 return r;
537}
538
bb44e0d1
JK		 539void host_cpuid(uint32_t function, uint32_t count,
540 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 541{
a1fd24af
AL		 542 uint32_t vec[4];
543
544#ifdef __x86_64__
545 asm volatile("cpuid"
546 : "=a"(vec[0]), "=b"(vec[1]),
547 "=c"(vec[2]), "=d"(vec[3])
548 : "0"(function), "c"(count) : "cc");
c1f41226 549#elif defined(__i386__)
a1fd24af
AL		 550 asm volatile("pusha \n\t"
551 "cpuid \n\t"
552 "mov %%eax, 0(%2) \n\t"
553 "mov %%ebx, 4(%2) \n\t"
554 "mov %%ecx, 8(%2) \n\t"
555 "mov %%edx, 12(%2) \n\t"
556 "popa"
557 : : "a"(function), "c"(count), "S"(vec)
558 : "memory", "cc");
c1f41226
EH		 559#else
560 abort();
a1fd24af
AL		 561#endif
562
bdde476a 563 if (eax)
a1fd24af 564 *eax = vec[0];
bdde476a 565 if (ebx)
a1fd24af 566 *ebx = vec[1];
bdde476a 567 if (ecx)
a1fd24af 568 *ecx = vec[2];
bdde476a 569 if (edx)
a1fd24af 570 *edx = vec[3];
bdde476a 571}
c6dc6f63
AP		 572
573#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
574
575/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
576 * a substring. ex if !NULL points to the first char after a substring,
577 * otherwise the string is assumed to sized by a terminating nul.
578 * Return lexical ordering of *s1:*s2.
579 */
8f9d989c
CF		 580static int sstrcmp(const char *s1, const char *e1,
581 const char *s2, const char *e2)
c6dc6f63
AP		 582{
583 for (;;) {
584 if (!*s1 || !*s2 || *s1 != *s2)
585 return (*s1 - *s2);
586 ++s1, ++s2;
587 if (s1 == e1 && s2 == e2)
588 return (0);
589 else if (s1 == e1)
590 return (*s2);
591 else if (s2 == e2)
592 return (*s1);
593 }
594}
595
596/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
597 * '|' delimited (possibly empty) strings in which case search for a match
598 * within the alternatives proceeds left to right. Return 0 for success,
599 * non-zero otherwise.
600 */
601static int altcmp(const char *s, const char *e, const char *altstr)
602{
603 const char *p, *q;
604
605 for (q = p = altstr; ; ) {
606 while (*p && *p != '|')
607 ++p;
608 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
609 return (0);
610 if (!*p)
611 return (1);
612 else
613 q = ++p;
614 }
615}
616
617/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 618 * *pval and return true, otherwise return false
c6dc6f63 619 */
e41e0fc6
JK		 620static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
621 const char **featureset)
c6dc6f63
AP		 622{
623 uint32_t mask;
624 const char **ppc;
e41e0fc6 625 bool found = false;
c6dc6f63 626
e41e0fc6 627 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 628 if (*ppc && !altcmp(s, e, *ppc)) {
629 *pval |= mask;
e41e0fc6 630 found = true;
c6dc6f63 631 }
e41e0fc6
JK		 632 }
633 return found;
c6dc6f63
AP		 634}
635
5ef57876 636static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 637 FeatureWordArray words,
638 Error **errp)
c6dc6f63 639{
5ef57876
EH		 640 FeatureWord w;
641 for (w = 0; w < FEATURE_WORDS; w++) {
642 FeatureWordInfo *wi = &feature_word_info[w];
643 if (wi->feat_names &&
644 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
645 break;
646 }
647 }
648 if (w == FEATURE_WORDS) {
c00c94ab 649 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 650 }
c6dc6f63
AP		 651}
652
d940ee9b
EH		 653/* CPU class name definitions: */
654
655#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
656#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
657
658/* Return type name for a given CPU model name
659 * Caller is responsible for freeing the returned string.
660 */
661static char *x86_cpu_type_name(const char *model_name)
662{
663 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
664}
665
500050d1
AF		 666static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
667{
d940ee9b
EH		 668 ObjectClass *oc;
669 char *typename;
670
500050d1
AF		 671 if (cpu_model == NULL) {
672 return NULL;
673 }
674
d940ee9b
EH		 675 typename = x86_cpu_type_name(cpu_model);
676 oc = object_class_by_name(typename);
677 g_free(typename);
678 return oc;
500050d1
AF		 679}
680
104494ea
IM		 681static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
682{
683 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
684 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
685 return g_strndup(class_name,
686 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
687}
688
d940ee9b 689struct X86CPUDefinition {
c6dc6f63
AP		 690 const char *name;
691 uint32_t level;
90e4b0c3
EH		 692 uint32_t xlevel;
693 uint32_t xlevel2;
99b88a17
IM		 694 /* vendor is zero-terminated, 12 character ASCII string */
695 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 696 int family;
697 int model;
698 int stepping;
0514ef2f 699 FeatureWordArray features;
c6dc6f63 700 char model_id[48];
d940ee9b 701};
c6dc6f63 702
9576de75 703static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 704 {
705 .name = "qemu64",
3046bb5d 706 .level = 0xd,
99b88a17 707 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 708 .family = 6,
f8e6a11a 709 .model = 6,
c6dc6f63 710 .stepping = 3,
0514ef2f 711 .features[FEAT_1_EDX] =
27861ecc 712 PPRO_FEATURES |
c6dc6f63 713 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 714 CPUID_PSE36,
0514ef2f 715 .features[FEAT_1_ECX] =
6aa91e4a 716 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 717 .features[FEAT_8000_0001_EDX] =
c6dc6f63 718 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 719 .features[FEAT_8000_0001_ECX] =
71195672 720 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 721 .xlevel = 0x8000000A,
9cf2cc3d 722 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 723 },
724 {
725 .name = "phenom",
726 .level = 5,
99b88a17 727 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 728 .family = 16,
729 .model = 2,
730 .stepping = 3,
b9fc20bc 731 /* Missing: CPUID_HT */
0514ef2f 732 .features[FEAT_1_EDX] =
27861ecc 733 PPRO_FEATURES |
c6dc6f63 734 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 735 CPUID_PSE36 | CPUID_VME,
0514ef2f 736 .features[FEAT_1_ECX] =
27861ecc 737 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 738 CPUID_EXT_POPCNT,
0514ef2f 739 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 740 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
741 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 742 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 743 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
744 CPUID_EXT3_CR8LEG,
745 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
746 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 747 .features[FEAT_8000_0001_ECX] =
27861ecc 748 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 749 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 750 /* Missing: CPUID_SVM_LBRV */
0514ef2f 751 .features[FEAT_SVM] =
b9fc20bc 752 CPUID_SVM_NPT,
c6dc6f63
AP		 753 .xlevel = 0x8000001A,
754 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
755 },
756 {
757 .name = "core2duo",
758 .level = 10,
99b88a17 759 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 760 .family = 6,
761 .model = 15,
762 .stepping = 11,
b9fc20bc 763 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 764 .features[FEAT_1_EDX] =
27861ecc 765 PPRO_FEATURES |
c6dc6f63 766 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 767 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
768 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 769 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 770 .features[FEAT_1_ECX] =
27861ecc 771 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 772 CPUID_EXT_CX16,
0514ef2f 773 .features[FEAT_8000_0001_EDX] =
27861ecc 774 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 775 .features[FEAT_8000_0001_ECX] =
27861ecc 776 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 777 .xlevel = 0x80000008,
778 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
779 },
780 {
781 .name = "kvm64",
3046bb5d 782 .level = 0xd,
99b88a17 783 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 784 .family = 15,
785 .model = 6,
786 .stepping = 1,
b3a4f0b1 787 /* Missing: CPUID_HT */
0514ef2f 788 .features[FEAT_1_EDX] =
b3a4f0b1 789 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 790 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
791 CPUID_PSE36,
792 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 793 .features[FEAT_1_ECX] =
27861ecc 794 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 795 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 796 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 797 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
798 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
799 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
800 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
801 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 802 .features[FEAT_8000_0001_ECX] =
27861ecc 803 0,
c6dc6f63
AP		 804 .xlevel = 0x80000008,
805 .model_id = "Common KVM processor"
806 },
c6dc6f63
AP		 807 {
808 .name = "qemu32",
809 .level = 4,
99b88a17 810 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 811 .family = 6,
f8e6a11a 812 .model = 6,
c6dc6f63 813 .stepping = 3,
0514ef2f 814 .features[FEAT_1_EDX] =
27861ecc 815 PPRO_FEATURES,
0514ef2f 816 .features[FEAT_1_ECX] =
6aa91e4a 817 CPUID_EXT_SSE3,
58012d66 818 .xlevel = 0x80000004,
9cf2cc3d 819 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 820 },
eafaf1e5
AP		 821 {
822 .name = "kvm32",
823 .level = 5,
99b88a17 824 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 825 .family = 15,
826 .model = 6,
827 .stepping = 1,
0514ef2f 828 .features[FEAT_1_EDX] =
b3a4f0b1 829 PPRO_FEATURES | CPUID_VME |
eafaf1e5 830 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 831 .features[FEAT_1_ECX] =
27861ecc 832 CPUID_EXT_SSE3,
0514ef2f 833 .features[FEAT_8000_0001_ECX] =
27861ecc 834 0,
eafaf1e5
AP		 835 .xlevel = 0x80000008,
836 .model_id = "Common 32-bit KVM processor"
837 },
c6dc6f63
AP		 838 {
839 .name = "coreduo",
840 .level = 10,
99b88a17 841 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 842 .family = 6,
843 .model = 14,
844 .stepping = 8,
b9fc20bc 845 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 846 .features[FEAT_1_EDX] =
27861ecc 847 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 848 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
849 CPUID_SS,
850 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 851 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 852 .features[FEAT_1_ECX] =
e93abc14 853 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 854 .features[FEAT_8000_0001_EDX] =
27861ecc 855 CPUID_EXT2_NX,
c6dc6f63
AP		 856 .xlevel = 0x80000008,
857 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
858 },
859 {
860 .name = "486",
58012d66 861 .level = 1,
99b88a17 862 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 863 .family = 4,
b2a856d9 864 .model = 8,
c6dc6f63 865 .stepping = 0,
0514ef2f 866 .features[FEAT_1_EDX] =
27861ecc 867 I486_FEATURES,
c6dc6f63
AP		 868 .xlevel = 0,
869 },
870 {
871 .name = "pentium",
872 .level = 1,
99b88a17 873 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 874 .family = 5,
875 .model = 4,
876 .stepping = 3,
0514ef2f 877 .features[FEAT_1_EDX] =
27861ecc 878 PENTIUM_FEATURES,
c6dc6f63
AP		 879 .xlevel = 0,
880 },
881 {
882 .name = "pentium2",
883 .level = 2,
99b88a17 884 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 885 .family = 6,
886 .model = 5,
887 .stepping = 2,
0514ef2f 888 .features[FEAT_1_EDX] =
27861ecc 889 PENTIUM2_FEATURES,
c6dc6f63
AP		 890 .xlevel = 0,
891 },
892 {
893 .name = "pentium3",
3046bb5d 894 .level = 3,
99b88a17 895 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 896 .family = 6,
897 .model = 7,
898 .stepping = 3,
0514ef2f 899 .features[FEAT_1_EDX] =
27861ecc 900 PENTIUM3_FEATURES,
c6dc6f63
AP		 901 .xlevel = 0,
902 },
903 {
904 .name = "athlon",
905 .level = 2,
99b88a17 906 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 907 .family = 6,
908 .model = 2,
909 .stepping = 3,
0514ef2f 910 .features[FEAT_1_EDX] =
27861ecc 911 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 912 CPUID_MCA,
0514ef2f 913 .features[FEAT_8000_0001_EDX] =
60032ac0 914 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 915 .xlevel = 0x80000008,
9cf2cc3d 916 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 917 },
918 {
919 .name = "n270",
3046bb5d 920 .level = 10,
99b88a17 921 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 922 .family = 6,
923 .model = 28,
924 .stepping = 2,
b9fc20bc 925 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 926 .features[FEAT_1_EDX] =
27861ecc 927 PPRO_FEATURES |
b9fc20bc
EH		 928 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
929 CPUID_ACPI | CPUID_SS,
c6dc6f63 930 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 931 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
932 * CPUID_EXT_XTPR */
0514ef2f 933 .features[FEAT_1_ECX] =
27861ecc 934 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 935 CPUID_EXT_MOVBE,
0514ef2f 936 .features[FEAT_8000_0001_EDX] =
60032ac0 937 CPUID_EXT2_NX,
0514ef2f 938 .features[FEAT_8000_0001_ECX] =
27861ecc 939 CPUID_EXT3_LAHF_LM,
3046bb5d 940 .xlevel = 0x80000008,
c6dc6f63
AP		 941 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
942 },
3eca4642
EH		 943 {
944 .name = "Conroe",
3046bb5d 945 .level = 10,
99b88a17 946 .vendor = CPUID_VENDOR_INTEL,
3eca4642 947 .family = 6,
ffce9ebb 948 .model = 15,
3eca4642 949 .stepping = 3,
0514ef2f 950 .features[FEAT_1_EDX] =
b3a4f0b1 951 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
955 CPUID_DE | CPUID_FP87,
0514ef2f 956 .features[FEAT_1_ECX] =
27861ecc 957 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 958 .features[FEAT_8000_0001_EDX] =
27861ecc 959 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 960 .features[FEAT_8000_0001_ECX] =
27861ecc 961 CPUID_EXT3_LAHF_LM,
3046bb5d 962 .xlevel = 0x80000008,
3eca4642
EH		 963 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
964 },
965 {
966 .name = "Penryn",
3046bb5d 967 .level = 10,
99b88a17 968 .vendor = CPUID_VENDOR_INTEL,
3eca4642 969 .family = 6,
ffce9ebb 970 .model = 23,
3eca4642 971 .stepping = 3,
0514ef2f 972 .features[FEAT_1_EDX] =
b3a4f0b1 973 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 974 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
975 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
976 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
977 CPUID_DE | CPUID_FP87,
0514ef2f 978 .features[FEAT_1_ECX] =
27861ecc 979 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 980 CPUID_EXT_SSE3,
0514ef2f 981 .features[FEAT_8000_0001_EDX] =
27861ecc 982 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 983 .features[FEAT_8000_0001_ECX] =
27861ecc 984 CPUID_EXT3_LAHF_LM,
3046bb5d 985 .xlevel = 0x80000008,
3eca4642
EH		 986 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
987 },
988 {
989 .name = "Nehalem",
3046bb5d 990 .level = 11,
99b88a17 991 .vendor = CPUID_VENDOR_INTEL,
3eca4642 992 .family = 6,
ffce9ebb 993 .model = 26,
3eca4642 994 .stepping = 3,
0514ef2f 995 .features[FEAT_1_EDX] =
b3a4f0b1 996 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 997 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
998 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
999 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1000 CPUID_DE | CPUID_FP87,
0514ef2f 1001 .features[FEAT_1_ECX] =
27861ecc 1002 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1003 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1004 .features[FEAT_8000_0001_EDX] =
27861ecc 1005 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1006 .features[FEAT_8000_0001_ECX] =
27861ecc 1007 CPUID_EXT3_LAHF_LM,
3046bb5d 1008 .xlevel = 0x80000008,
3eca4642
EH		 1009 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1010 },
1011 {
1012 .name = "Westmere",
1013 .level = 11,
99b88a17 1014 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1015 .family = 6,
1016 .model = 44,
1017 .stepping = 1,
0514ef2f 1018 .features[FEAT_1_EDX] =
b3a4f0b1 1019 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1020 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1021 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1022 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1023 CPUID_DE | CPUID_FP87,
0514ef2f 1024 .features[FEAT_1_ECX] =
27861ecc 1025 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1026 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1027 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1028 .features[FEAT_8000_0001_EDX] =
27861ecc 1029 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1030 .features[FEAT_8000_0001_ECX] =
27861ecc 1031 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1032 .features[FEAT_6_EAX] =
1033 CPUID_6_EAX_ARAT,
3046bb5d 1034 .xlevel = 0x80000008,
3eca4642
EH		 1035 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1036 },
1037 {
1038 .name = "SandyBridge",
1039 .level = 0xd,
99b88a17 1040 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1041 .family = 6,
1042 .model = 42,
1043 .stepping = 1,
0514ef2f 1044 .features[FEAT_1_EDX] =
b3a4f0b1 1045 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1046 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1047 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1048 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1049 CPUID_DE | CPUID_FP87,
0514ef2f 1050 .features[FEAT_1_ECX] =
27861ecc 1051 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1052 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1053 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1054 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1055 CPUID_EXT_SSE3,
0514ef2f 1056 .features[FEAT_8000_0001_EDX] =
27861ecc 1057 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1058 CPUID_EXT2_SYSCALL,
0514ef2f 1059 .features[FEAT_8000_0001_ECX] =
27861ecc 1060 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1061 .features[FEAT_XSAVE] =
1062 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1063 .features[FEAT_6_EAX] =
1064 CPUID_6_EAX_ARAT,
3046bb5d 1065 .xlevel = 0x80000008,
3eca4642
EH		 1066 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1067 },
2f9ac42a
PB		 1068 {
1069 .name = "IvyBridge",
1070 .level = 0xd,
1071 .vendor = CPUID_VENDOR_INTEL,
1072 .family = 6,
1073 .model = 58,
1074 .stepping = 9,
1075 .features[FEAT_1_EDX] =
1076 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1077 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1078 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1079 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1080 CPUID_DE | CPUID_FP87,
1081 .features[FEAT_1_ECX] =
1082 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1083 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1084 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1085 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1086 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1087 .features[FEAT_7_0_EBX] =
1088 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1089 CPUID_7_0_EBX_ERMS,
1090 .features[FEAT_8000_0001_EDX] =
1091 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1092 CPUID_EXT2_SYSCALL,
1093 .features[FEAT_8000_0001_ECX] =
1094 CPUID_EXT3_LAHF_LM,
1095 .features[FEAT_XSAVE] =
1096 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1097 .features[FEAT_6_EAX] =
1098 CPUID_6_EAX_ARAT,
3046bb5d 1099 .xlevel = 0x80000008,
2f9ac42a
PB		 1100 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1101 },
37507094 1102 {
a356850b
EH		 1103 .name = "Haswell-noTSX",
1104 .level = 0xd,
1105 .vendor = CPUID_VENDOR_INTEL,
1106 .family = 6,
1107 .model = 60,
1108 .stepping = 1,
1109 .features[FEAT_1_EDX] =
1110 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1111 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1112 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1113 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1114 CPUID_DE | CPUID_FP87,
1115 .features[FEAT_1_ECX] =
1116 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1117 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1118 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1119 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1120 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1121 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1122 .features[FEAT_8000_0001_EDX] =
1123 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1124 CPUID_EXT2_SYSCALL,
1125 .features[FEAT_8000_0001_ECX] =
becb6667 1126 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1127 .features[FEAT_7_0_EBX] =
1128 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1129 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1130 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1131 .features[FEAT_XSAVE] =
1132 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1133 .features[FEAT_6_EAX] =
1134 CPUID_6_EAX_ARAT,
3046bb5d 1135 .xlevel = 0x80000008,
a356850b
EH		 1136 .model_id = "Intel Core Processor (Haswell, no TSX)",
1137 }, {
37507094
EH		 1138 .name = "Haswell",
1139 .level = 0xd,
99b88a17 1140 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1141 .family = 6,
1142 .model = 60,
1143 .stepping = 1,
0514ef2f 1144 .features[FEAT_1_EDX] =
b3a4f0b1 1145 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1146 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1147 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1148 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1149 CPUID_DE | CPUID_FP87,
0514ef2f 1150 .features[FEAT_1_ECX] =
27861ecc 1151 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1152 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1153 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1154 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1155 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1156 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1157 .features[FEAT_8000_0001_EDX] =
27861ecc 1158 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1159 CPUID_EXT2_SYSCALL,
0514ef2f 1160 .features[FEAT_8000_0001_ECX] =
becb6667 1161 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1162 .features[FEAT_7_0_EBX] =
27861ecc 1163 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1164 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1165 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1166 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1167 .features[FEAT_XSAVE] =
1168 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1169 .features[FEAT_6_EAX] =
1170 CPUID_6_EAX_ARAT,
3046bb5d 1171 .xlevel = 0x80000008,
37507094
EH		 1172 .model_id = "Intel Core Processor (Haswell)",
1173 },
a356850b
EH		 1174 {
1175 .name = "Broadwell-noTSX",
1176 .level = 0xd,
1177 .vendor = CPUID_VENDOR_INTEL,
1178 .family = 6,
1179 .model = 61,
1180 .stepping = 2,
1181 .features[FEAT_1_EDX] =
1182 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1183 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1184 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1185 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1186 CPUID_DE | CPUID_FP87,
1187 .features[FEAT_1_ECX] =
1188 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1189 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1190 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1191 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1192 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1193 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1194 .features[FEAT_8000_0001_EDX] =
1195 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1196 CPUID_EXT2_SYSCALL,
1197 .features[FEAT_8000_0001_ECX] =
becb6667 1198 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1199 .features[FEAT_7_0_EBX] =
1200 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1201 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1202 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1203 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1204 CPUID_7_0_EBX_SMAP,
1205 .features[FEAT_XSAVE] =
1206 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1207 .features[FEAT_6_EAX] =
1208 CPUID_6_EAX_ARAT,
3046bb5d 1209 .xlevel = 0x80000008,
a356850b
EH		 1210 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1211 },
ece01354
EH		 1212 {
1213 .name = "Broadwell",
1214 .level = 0xd,
1215 .vendor = CPUID_VENDOR_INTEL,
1216 .family = 6,
1217 .model = 61,
1218 .stepping = 2,
1219 .features[FEAT_1_EDX] =
b3a4f0b1 1220 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1221 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1222 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1223 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1224 CPUID_DE | CPUID_FP87,
1225 .features[FEAT_1_ECX] =
1226 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1227 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1228 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1229 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1230 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1231 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1232 .features[FEAT_8000_0001_EDX] =
1233 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1234 CPUID_EXT2_SYSCALL,
1235 .features[FEAT_8000_0001_ECX] =
becb6667 1236 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1237 .features[FEAT_7_0_EBX] =
1238 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1239 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1240 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1241 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1242 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1243 .features[FEAT_XSAVE] =
1244 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1245 .features[FEAT_6_EAX] =
1246 CPUID_6_EAX_ARAT,
3046bb5d 1247 .xlevel = 0x80000008,
ece01354
EH		 1248 .model_id = "Intel Core Processor (Broadwell)",
1249 },
f6f949e9
EH		 1250 {
1251 .name = "Skylake-Client",
1252 .level = 0xd,
1253 .vendor = CPUID_VENDOR_INTEL,
1254 .family = 6,
1255 .model = 94,
1256 .stepping = 3,
1257 .features[FEAT_1_EDX] =
1258 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1259 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1260 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1261 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1262 CPUID_DE | CPUID_FP87,
1263 .features[FEAT_1_ECX] =
1264 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1265 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1266 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1267 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1268 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1269 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1270 .features[FEAT_8000_0001_EDX] =
1271 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1272 CPUID_EXT2_SYSCALL,
1273 .features[FEAT_8000_0001_ECX] =
1274 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1275 .features[FEAT_7_0_EBX] =
1276 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1277 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1278 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1279 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1280 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1281 /* Missing: XSAVES (not supported by some Linux versions,
1282 * including v4.1 to v4.6).
1283 * KVM doesn't yet expose any XSAVES state save component,
1284 * and the only one defined in Skylake (processor tracing)
1285 * probably will block migration anyway.
1286 */
1287 .features[FEAT_XSAVE] =
1288 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1289 CPUID_XSAVE_XGETBV1,
1290 .features[FEAT_6_EAX] =
1291 CPUID_6_EAX_ARAT,
1292 .xlevel = 0x80000008,
1293 .model_id = "Intel Core Processor (Skylake)",
1294 },
3eca4642
EH		 1295 {
1296 .name = "Opteron_G1",
1297 .level = 5,
99b88a17 1298 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1299 .family = 15,
1300 .model = 6,
1301 .stepping = 1,
0514ef2f 1302 .features[FEAT_1_EDX] =
b3a4f0b1 1303 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1304 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1305 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1306 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1307 CPUID_DE | CPUID_FP87,
0514ef2f 1308 .features[FEAT_1_ECX] =
27861ecc 1309 CPUID_EXT_SSE3,
0514ef2f 1310 .features[FEAT_8000_0001_EDX] =
27861ecc 1311 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1312 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1313 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1314 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1315 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1316 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1317 .xlevel = 0x80000008,
1318 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1319 },
1320 {
1321 .name = "Opteron_G2",
1322 .level = 5,
99b88a17 1323 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1324 .family = 15,
1325 .model = 6,
1326 .stepping = 1,
0514ef2f 1327 .features[FEAT_1_EDX] =
b3a4f0b1 1328 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1329 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1330 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1331 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1332 CPUID_DE | CPUID_FP87,
0514ef2f 1333 .features[FEAT_1_ECX] =
27861ecc 1334 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1335 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1336 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1337 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1338 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1339 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1340 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1341 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1342 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1343 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1344 .features[FEAT_8000_0001_ECX] =
27861ecc 1345 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1346 .xlevel = 0x80000008,
1347 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1348 },
1349 {
1350 .name = "Opteron_G3",
1351 .level = 5,
99b88a17 1352 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1353 .family = 15,
1354 .model = 6,
1355 .stepping = 1,
0514ef2f 1356 .features[FEAT_1_EDX] =
b3a4f0b1 1357 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1358 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1359 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1360 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1361 CPUID_DE | CPUID_FP87,
0514ef2f 1362 .features[FEAT_1_ECX] =
27861ecc 1363 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1364 CPUID_EXT_SSE3,
33b5e8c0 1365 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1366 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1367 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1368 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1369 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1370 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1371 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1372 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1373 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1374 .features[FEAT_8000_0001_ECX] =
27861ecc 1375 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1376 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1377 .xlevel = 0x80000008,
1378 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1379 },
1380 {
1381 .name = "Opteron_G4",
1382 .level = 0xd,
99b88a17 1383 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1384 .family = 21,
1385 .model = 1,
1386 .stepping = 2,
0514ef2f 1387 .features[FEAT_1_EDX] =
b3a4f0b1 1388 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1389 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1390 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1391 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1392 CPUID_DE | CPUID_FP87,
0514ef2f 1393 .features[FEAT_1_ECX] =
27861ecc 1394 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1395 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1396 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1397 CPUID_EXT_SSE3,
33b5e8c0 1398 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1399 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1400 CPUID_EXT2_LM |
b3fb3a20
EH		 1401 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1402 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1403 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1404 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1405 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1406 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1407 .features[FEAT_8000_0001_ECX] =
27861ecc 1408 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1409 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1410 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1411 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1412 /* no xsaveopt! */
3eca4642
EH		 1413 .xlevel = 0x8000001A,
1414 .model_id = "AMD Opteron 62xx class CPU",
1415 },
021941b9
AP		 1416 {
1417 .name = "Opteron_G5",
1418 .level = 0xd,
99b88a17 1419 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1420 .family = 21,
1421 .model = 2,
1422 .stepping = 0,
0514ef2f 1423 .features[FEAT_1_EDX] =
b3a4f0b1 1424 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1425 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1426 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1427 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1428 CPUID_DE | CPUID_FP87,
0514ef2f 1429 .features[FEAT_1_ECX] =
27861ecc 1430 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1431 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1432 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1433 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1434 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1435 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1436 CPUID_EXT2_LM |
b3fb3a20
EH		 1437 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1438 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1439 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1440 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1441 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1442 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1443 .features[FEAT_8000_0001_ECX] =
27861ecc 1444 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1445 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1446 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1447 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1448 /* no xsaveopt! */
021941b9
AP		 1449 .xlevel = 0x8000001A,
1450 .model_id = "AMD Opteron 63xx class CPU",
1451 },
c6dc6f63
AP		 1452};
1453
5114e842
EH		 1454typedef struct PropValue {
1455 const char *prop, *value;
1456} PropValue;
1457
1458/* KVM-specific features that are automatically added/removed
1459 * from all CPU models when KVM is enabled.
1460 */
1461static PropValue kvm_default_props[] = {
1462 { "kvmclock", "on" },
1463 { "kvm-nopiodelay", "on" },
1464 { "kvm-asyncpf", "on" },
1465 { "kvm-steal-time", "on" },
1466 { "kvm-pv-eoi", "on" },
1467 { "kvmclock-stable-bit", "on" },
1468 { "x2apic", "on" },
1469 { "acpi", "off" },
1470 { "monitor", "off" },
1471 { "svm", "off" },
1472 { NULL, NULL },
1473};
1474
1475void x86_cpu_change_kvm_default(const char *prop, const char *value)
1476{
1477 PropValue *pv;
1478 for (pv = kvm_default_props; pv->prop; pv++) {
1479 if (!strcmp(pv->prop, prop)) {
1480 pv->value = value;
1481 break;
1482 }
1483 }
1484
1485 /* It is valid to call this function only for properties that
1486 * are already present in the kvm_default_props table.
1487 */
1488 assert(pv->prop);
1489}
1490
4d1b279b
EH		 1491static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1492 bool migratable_only);
1493
d940ee9b
EH		 1494#ifdef CONFIG_KVM
1495
c6dc6f63
AP		 1496static int cpu_x86_fill_model_id(char *str)
1497{
1498 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1499 int i;
1500
1501 for (i = 0; i < 3; i++) {
1502 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1503 memcpy(str + i * 16 + 0, &eax, 4);
1504 memcpy(str + i * 16 + 4, &ebx, 4);
1505 memcpy(str + i * 16 + 8, &ecx, 4);
1506 memcpy(str + i * 16 + 12, &edx, 4);
1507 }
1508 return 0;
1509}
1510
d940ee9b
EH		 1511static X86CPUDefinition host_cpudef;
1512
84f1b92f 1513static Property host_x86_cpu_properties[] = {
120eee7d 1514 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1515 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1516 DEFINE_PROP_END_OF_LIST()
1517};
1518
d940ee9b 1519/* class_init for the "host" CPU model
6e746f30 1520 *
d940ee9b 1521 * This function may be called before KVM is initialized.
6e746f30 1522 */
d940ee9b 1523static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1524{
84f1b92f 1525 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1526 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1527 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1528
d940ee9b 1529 xcc->kvm_required = true;
6e746f30 1530
c6dc6f63 1531 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1532 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1533
1534 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1535 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1536 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1537 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1538
d940ee9b 1539 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1540
d940ee9b 1541 xcc->cpu_def = &host_cpudef;
d940ee9b
EH		 1542
1543 /* level, xlevel, xlevel2, and the feature words are initialized on
1544 * instance_init, because they require KVM to be initialized.
1545 */
84f1b92f
EH		 1546
1547 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1548 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1549 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1550}
1551
1552static void host_x86_cpu_initfn(Object *obj)
1553{
1554 X86CPU *cpu = X86_CPU(obj);
1555 CPUX86State *env = &cpu->env;
1556 KVMState *s = kvm_state;
d940ee9b 1557
4d1b279b
EH		 1558 /* We can't fill the features array here because we don't know yet if
1559 * "migratable" is true or false.
1560 */
1561 cpu->host_features = true;
1562
104494ea 1563 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010
EH		 1564 if (kvm_enabled()) {
1565 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1566 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1567 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1568 }
2a573259 1569
d940ee9b 1570 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1571}
1572
d940ee9b
EH		 1573static const TypeInfo host_x86_cpu_type_info = {
1574 .name = X86_CPU_TYPE_NAME("host"),
1575 .parent = TYPE_X86_CPU,
1576 .instance_init = host_x86_cpu_initfn,
1577 .class_init = host_x86_cpu_class_init,
1578};
1579
1580#endif
1581
8459e396 1582static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1583{
8459e396 1584 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1585 int i;
1586
857aee33 1587 for (i = 0; i < 32; ++i) {
72370dc1 1588 if ((1UL << i) & mask) {
bffd67b0 1589 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1590 assert(reg);
fefb41bf 1591 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1592 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1593 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1594 f->cpuid_eax, reg,
1595 f->feat_names[i] ? "." : "",
1596 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1597 }
857aee33 1598 }
c6dc6f63
AP		 1599}
1600
d7bce999
EB		 1601static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1602 const char *name, void *opaque,
1603 Error **errp)
95b8519d
AF		 1604{
1605 X86CPU *cpu = X86_CPU(obj);
1606 CPUX86State *env = &cpu->env;
1607 int64_t value;
1608
1609 value = (env->cpuid_version >> 8) & 0xf;
1610 if (value == 0xf) {
1611 value += (env->cpuid_version >> 20) & 0xff;
1612 }
51e72bc1 1613 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1614}
1615
d7bce999
EB		 1616static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1617 const char *name, void *opaque,
1618 Error **errp)
ed5e1ec3 1619{
71ad61d3
AF		 1620 X86CPU *cpu = X86_CPU(obj);
1621 CPUX86State *env = &cpu->env;
1622 const int64_t min = 0;
1623 const int64_t max = 0xff + 0xf;
65cd9064 1624 Error *local_err = NULL;
71ad61d3
AF		 1625 int64_t value;
1626
51e72bc1 1627 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1628 if (local_err) {
1629 error_propagate(errp, local_err);
71ad61d3
AF		 1630 return;
1631 }
1632 if (value < min || value > max) {
c6bd8c70
MA		 1633 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1634 name ? name : "null", value, min, max);
71ad61d3
AF		 1635 return;
1636 }
1637
ed5e1ec3 1638 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1639 if (value > 0x0f) {
1640 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1641 } else {
71ad61d3 1642 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1643 }
1644}
1645
d7bce999
EB		 1646static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1647 const char *name, void *opaque,
1648 Error **errp)
67e30c83
AF		 1649{
1650 X86CPU *cpu = X86_CPU(obj);
1651 CPUX86State *env = &cpu->env;
1652 int64_t value;
1653
1654 value = (env->cpuid_version >> 4) & 0xf;
1655 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1656 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1657}
1658
d7bce999
EB		 1659static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1660 const char *name, void *opaque,
1661 Error **errp)
b0704cbd 1662{
c5291a4f
AF		 1663 X86CPU *cpu = X86_CPU(obj);
1664 CPUX86State *env = &cpu->env;
1665 const int64_t min = 0;
1666 const int64_t max = 0xff;
65cd9064 1667 Error *local_err = NULL;
c5291a4f
AF		 1668 int64_t value;
1669
51e72bc1 1670 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1671 if (local_err) {
1672 error_propagate(errp, local_err);
c5291a4f
AF		 1673 return;
1674 }
1675 if (value < min || value > max) {
c6bd8c70
MA		 1676 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1677 name ? name : "null", value, min, max);
c5291a4f
AF		 1678 return;
1679 }
1680
b0704cbd 1681 env->cpuid_version &= ~0xf00f0;
c5291a4f 1682 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1683}
1684
35112e41 1685static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1686 const char *name, void *opaque,
35112e41
AF		 1687 Error **errp)
1688{
1689 X86CPU *cpu = X86_CPU(obj);
1690 CPUX86State *env = &cpu->env;
1691 int64_t value;
1692
1693 value = env->cpuid_version & 0xf;
51e72bc1 1694 visit_type_int(v, name, &value, errp);
35112e41
AF		 1695}
1696
036e2222 1697static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1698 const char *name, void *opaque,
036e2222 1699 Error **errp)
38c3dc46 1700{
036e2222
AF		 1701 X86CPU *cpu = X86_CPU(obj);
1702 CPUX86State *env = &cpu->env;
1703 const int64_t min = 0;
1704 const int64_t max = 0xf;
65cd9064 1705 Error *local_err = NULL;
036e2222
AF		 1706 int64_t value;
1707
51e72bc1 1708 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1709 if (local_err) {
1710 error_propagate(errp, local_err);
036e2222
AF		 1711 return;
1712 }
1713 if (value < min || value > max) {
c6bd8c70
MA		 1714 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1715 name ? name : "null", value, min, max);
036e2222
AF		 1716 return;
1717 }
1718
38c3dc46 1719 env->cpuid_version &= ~0xf;
036e2222 1720 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1721}
1722
d480e1af
AF		 1723static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1724{
1725 X86CPU *cpu = X86_CPU(obj);
1726 CPUX86State *env = &cpu->env;
1727 char *value;
d480e1af 1728
e42a92ae 1729 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1730 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1731 env->cpuid_vendor3);
d480e1af
AF		 1732 return value;
1733}
1734
1735static void x86_cpuid_set_vendor(Object *obj, const char *value,
1736 Error **errp)
1737{
1738 X86CPU *cpu = X86_CPU(obj);
1739 CPUX86State *env = &cpu->env;
1740 int i;
1741
9df694ee 1742 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1743 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1744 return;
1745 }
1746
1747 env->cpuid_vendor1 = 0;
1748 env->cpuid_vendor2 = 0;
1749 env->cpuid_vendor3 = 0;
1750 for (i = 0; i < 4; i++) {
1751 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1752 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1753 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1754 }
d480e1af
AF		 1755}
1756
63e886eb
AF		 1757static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1758{
1759 X86CPU *cpu = X86_CPU(obj);
1760 CPUX86State *env = &cpu->env;
1761 char *value;
1762 int i;
1763
1764 value = g_malloc(48 + 1);
1765 for (i = 0; i < 48; i++) {
1766 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1767 }
1768 value[48] = '\0';
1769 return value;
1770}
1771
938d4c25
AF		 1772static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1773 Error **errp)
dcce6675 1774{
938d4c25
AF		 1775 X86CPU *cpu = X86_CPU(obj);
1776 CPUX86State *env = &cpu->env;
dcce6675
AF		 1777 int c, len, i;
1778
1779 if (model_id == NULL) {
1780 model_id = "";
1781 }
1782 len = strlen(model_id);
d0a6acf4 1783 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1784 for (i = 0; i < 48; i++) {
1785 if (i >= len) {
1786 c = '\0';
1787 } else {
1788 c = (uint8_t)model_id[i];
1789 }
1790 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1791 }
1792}
1793
d7bce999
EB		 1794static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1795 void *opaque, Error **errp)
89e48965
AF		 1796{
1797 X86CPU *cpu = X86_CPU(obj);
1798 int64_t value;
1799
1800 value = cpu->env.tsc_khz * 1000;
51e72bc1 1801 visit_type_int(v, name, &value, errp);
89e48965
AF		 1802}
1803
d7bce999
EB		 1804static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1805 void *opaque, Error **errp)
89e48965
AF		 1806{
1807 X86CPU *cpu = X86_CPU(obj);
1808 const int64_t min = 0;
2e84849a 1809 const int64_t max = INT64_MAX;
65cd9064 1810 Error *local_err = NULL;
89e48965
AF		 1811 int64_t value;
1812
51e72bc1 1813 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1814 if (local_err) {
1815 error_propagate(errp, local_err);
89e48965
AF		 1816 return;
1817 }
1818 if (value < min || value > max) {
c6bd8c70
MA		 1819 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1820 name ? name : "null", value, min, max);
89e48965
AF		 1821 return;
1822 }
1823
36f96c4b 1824 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1825}
1826
d7bce999
EB		 1827static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, const char *name,
1828 void *opaque, Error **errp)
31050930
IM		 1829{
1830 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1831 int64_t value = cpu->apic_id;
31050930 1832
51e72bc1 1833 visit_type_int(v, name, &value, errp);
31050930
IM		 1834}
1835
d7bce999
EB		 1836static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, const char *name,
1837 void *opaque, Error **errp)
31050930
IM		 1838{
1839 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1840 DeviceState *dev = DEVICE(obj);
31050930
IM		 1841 const int64_t min = 0;
1842 const int64_t max = UINT32_MAX;
1843 Error *error = NULL;
1844 int64_t value;
1845
8d6d4980
IM		 1846 if (dev->realized) {
1847 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1848 "it was realized", name, object_get_typename(obj));
1849 return;
1850 }
1851
51e72bc1 1852 visit_type_int(v, name, &value, &error);
31050930
IM		 1853 if (error) {
1854 error_propagate(errp, error);
1855 return;
1856 }
1857 if (value < min || value > max) {
1858 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1859 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1860 object_get_typename(obj), name, value, min, max);
1861 return;
1862 }
1863
7e72a45c 1864 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM		 1865 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1866 return;
1867 }
7e72a45c 1868 cpu->apic_id = value;
31050930
IM		 1869}
1870
7e5292b5 1871/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1872static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1873 const char *name, void *opaque,
1874 Error **errp)
8e8aba50 1875{
7e5292b5 1876 uint32_t *array = (uint32_t *)opaque;
8e8aba50
EH		 1877 FeatureWord w;
1878 Error *err = NULL;
1879 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1880 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1881 X86CPUFeatureWordInfoList *list = NULL;
1882
1883 for (w = 0; w < FEATURE_WORDS; w++) {
1884 FeatureWordInfo *wi = &feature_word_info[w];
1885 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1886 qwi->cpuid_input_eax = wi->cpuid_eax;
1887 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1888 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1889 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1890 qwi->features = array[w];
8e8aba50
EH		 1891
1892 /* List will be in reverse order, but order shouldn't matter */
1893 list_entries[w].next = list;
1894 list_entries[w].value = &word_infos[w];
1895 list = &list_entries[w];
1896 }
1897
51e72bc1 1898 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, &err);
8e8aba50
EH		 1899 error_propagate(errp, err);
1900}
1901
d7bce999
EB		 1902static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1903 void *opaque, Error **errp)
c8f0f88e
IM		 1904{
1905 X86CPU *cpu = X86_CPU(obj);
1906 int64_t value = cpu->hyperv_spinlock_attempts;
1907
51e72bc1 1908 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1909}
1910
d7bce999
EB		 1911static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1912 void *opaque, Error **errp)
c8f0f88e
IM		 1913{
1914 const int64_t min = 0xFFF;
1915 const int64_t max = UINT_MAX;
1916 X86CPU *cpu = X86_CPU(obj);
1917 Error *err = NULL;
1918 int64_t value;
1919
51e72bc1 1920 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1921 if (err) {
1922 error_propagate(errp, err);
1923 return;
1924 }
1925
1926 if (value < min || value > max) {
1927 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1928 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1929 object_get_typename(obj), name ? name : "null",
1930 value, min, max);
c8f0f88e
IM		 1931 return;
1932 }
1933 cpu->hyperv_spinlock_attempts = value;
1934}
1935
1936static PropertyInfo qdev_prop_spinlocks = {
1937 .name = "int",
1938 .get = x86_get_hv_spinlocks,
1939 .set = x86_set_hv_spinlocks,
1940};
1941
72ac2e87
IM		 1942/* Convert all '_' in a feature string option name to '-', to make feature
1943 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1944 */
1945static inline void feat2prop(char *s)
1946{
1947 while ((s = strchr(s, '_'))) {
1948 *s = '-';
1949 }
1950}
1951
dc15c051
IM		 1952/* Compatibily hack to maintain legacy +-feat semantic,
1953 * where +-feat overwrites any feature set by
1954 * feat=on|feat even if the later is parsed after +-feat
1955 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1956 */
1957static FeatureWordArray plus_features = { 0 };
1958static FeatureWordArray minus_features = { 0 };
1959
8f961357
EH		 1960/* Parse "+feature,-feature,feature=foo" CPU feature string
1961 */
94a444b2
AF		 1962static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1963 Error **errp)
8f961357 1964{
94a444b2 1965 X86CPU *cpu = X86_CPU(cs);
8f961357 1966 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 1967 Error *local_err = NULL;
8f961357 1968
8f961357 1969 featurestr = features ? strtok(features, ",") : NULL;
c6dc6f63
AP		 1970
1971 while (featurestr) {
1972 char *val;
1973 if (featurestr[0] == '+') {
c00c94ab 1974 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
c6dc6f63 1975 } else if (featurestr[0] == '-') {
c00c94ab 1976 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
c6dc6f63
AP		 1977 } else if ((val = strchr(featurestr, '='))) {
1978 *val = 0; val++;
72ac2e87 1979 feat2prop(featurestr);
c19b8521 1980 if (!strcmp(featurestr, "tsc-freq")) {
b862d1fe
JR		 1981 int64_t tsc_freq;
1982 char *err;
a91987c2 1983 char num[32];
b862d1fe 1984
4677bb40
MAL		 1985 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
1986 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 1987 if (tsc_freq < 0 || *err) {
6b1dd54b
PB		 1988 error_setg(errp, "bad numerical value %s", val);
1989 return;
b862d1fe 1990 }
a91987c2 1991 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
94a444b2
AF		 1992 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1993 &local_err);
c6dc6f63 1994 } else {
94a444b2 1995 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
c6dc6f63 1996 }
c6dc6f63 1997 } else {
258f5abe 1998 feat2prop(featurestr);
94a444b2 1999 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
a91987c2 2000 }
94a444b2
AF		 2001 if (local_err) {
2002 error_propagate(errp, local_err);
6b1dd54b 2003 return;
c6dc6f63
AP		 2004 }
2005 featurestr = strtok(NULL, ",");
2006 }
c6dc6f63
AP		 2007}
2008
8c3329e5 2009/* Print all cpuid feature names in featureset
c6dc6f63 2010 */
8c3329e5 2011static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2012{
8c3329e5
EH		 2013 int bit;
2014 bool first = true;
2015
2016 for (bit = 0; bit < 32; bit++) {
2017 if (featureset[bit]) {
2018 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2019 first = false;
c6dc6f63 2020 }
8c3329e5 2021 }
c6dc6f63
AP		 2022}
2023
e916cbf8
PM		 2024/* generate CPU information. */
2025void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2026{
9576de75 2027 X86CPUDefinition *def;
c6dc6f63 2028 char buf[256];
7fc9b714 2029 int i;
c6dc6f63 2030
7fc9b714
AF		 2031 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2032 def = &builtin_x86_defs[i];
c04321b3 2033 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2034 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2035 }
21ad7789
JK		 2036#ifdef CONFIG_KVM
2037 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2038 "KVM processor with all supported host features "
2039 "(only available in KVM mode)");
2040#endif
2041
6cdf8854 2042 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2043 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2044 FeatureWordInfo *fw = &feature_word_info[i];
2045
8c3329e5
EH		 2046 (*cpu_fprintf)(f, " ");
2047 listflags(f, cpu_fprintf, fw->feat_names);
2048 (*cpu_fprintf)(f, "\n");
3af60be2 2049 }
c6dc6f63
AP		 2050}
2051
76b64a7a 2052CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2053{
2054 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2055 X86CPUDefinition *def;
7fc9b714 2056 int i;
e3966126 2057
7fc9b714 2058 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2059 CpuDefinitionInfoList *entry;
2060 CpuDefinitionInfo *info;
2061
7fc9b714 2062 def = &builtin_x86_defs[i];
e3966126
AL		 2063 info = g_malloc0(sizeof(*info));
2064 info->name = g_strdup(def->name);
2065
2066 entry = g_malloc0(sizeof(*entry));
2067 entry->value = info;
2068 entry->next = cpu_list;
2069 cpu_list = entry;
2070 }
2071
2072 return cpu_list;
2073}
2074
84f1b92f
EH		 2075static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2076 bool migratable_only)
27418adf
EH		 2077{
2078 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2079 uint32_t r;
27418adf 2080
fefb41bf 2081 if (kvm_enabled()) {
84f1b92f
EH		 2082 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2083 wi->cpuid_ecx,
2084 wi->cpuid_reg);
fefb41bf 2085 } else if (tcg_enabled()) {
84f1b92f 2086 r = wi->tcg_features;
fefb41bf
EH		 2087 } else {
2088 return ~0;
2089 }
84f1b92f
EH		 2090 if (migratable_only) {
2091 r &= x86_cpu_get_migratable_flags(w);
2092 }
2093 return r;
27418adf
EH		 2094}
2095
51f63aed
EH		 2096/*
2097 * Filters CPU feature words based on host availability of each feature.
2098 *
51f63aed
EH		 2099 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2100 */
27418adf 2101static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2102{
2103 CPUX86State *env = &cpu->env;
bd87d2a2 2104 FeatureWord w;
51f63aed
EH		 2105 int rv = 0;
2106
bd87d2a2 2107 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2108 uint32_t host_feat =
2109 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2110 uint32_t requested_features = env->features[w];
2111 env->features[w] &= host_feat;
2112 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2113 if (cpu->filtered_features[w]) {
2114 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2115 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2116 }
2117 rv = 1;
2118 }
bd87d2a2 2119 }
51f63aed
EH		 2120
2121 return rv;
bc74b7db 2122}
bc74b7db 2123
5114e842
EH		 2124static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2125{
2126 PropValue *pv;
2127 for (pv = props; pv->prop; pv++) {
2128 if (!pv->value) {
2129 continue;
2130 }
2131 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2132 &error_abort);
2133 }
2134}
2135
d940ee9b 2136/* Load data from X86CPUDefinition
c080e30e 2137 */
d940ee9b 2138static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2139{
61dcd775 2140 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2141 const char *vendor;
2142 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2143 FeatureWord w;
c6dc6f63 2144
2d64255b
AF		 2145 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2146 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2147 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2148 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2149 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2150 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2d64255b 2151 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2152 for (w = 0; w < FEATURE_WORDS; w++) {
2153 env->features[w] = def->features[w];
2154 }
82beb536 2155
9576de75 2156 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2157 if (kvm_enabled()) {
492a4c94
LT		 2158 if (!kvm_irqchip_in_kernel()) {
2159 x86_cpu_change_kvm_default("x2apic", "off");
2160 }
2161
5114e842 2162 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2163 }
5fcca9ff 2164
82beb536 2165 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2166
2167 /* sysenter isn't supported in compatibility mode on AMD,
2168 * syscall isn't supported in compatibility mode on Intel.
2169 * Normally we advertise the actual CPU vendor, but you can
2170 * override this using the 'vendor' property if you want to use
2171 * KVM's sysenter/syscall emulation in compatibility mode and
2172 * when doing cross vendor migration
2173 */
74f54bc4 2174 vendor = def->vendor;
7c08db30
EH		 2175 if (kvm_enabled()) {
2176 uint32_t ebx = 0, ecx = 0, edx = 0;
2177 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2178 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2179 vendor = host_vendor;
2180 }
2181
2182 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2183
c6dc6f63
AP		 2184}
2185
e1570d00 2186X86CPU *cpu_x86_create(const char *cpu_model, Error **errp)
5c3c6a68 2187{
2d64255b 2188 X86CPU *cpu = NULL;
500050d1 2189 ObjectClass *oc;
2d64255b
AF		 2190 gchar **model_pieces;
2191 char *name, *features;
5c3c6a68
AF		 2192 Error *error = NULL;
2193
2d64255b
AF		 2194 model_pieces = g_strsplit(cpu_model, ",", 2);
2195 if (!model_pieces[0]) {
2196 error_setg(&error, "Invalid/empty CPU model name");
2197 goto out;
2198 }
2199 name = model_pieces[0];
2200 features = model_pieces[1];
2201
500050d1
AF		 2202 oc = x86_cpu_class_by_name(name);
2203 if (oc == NULL) {
2204 error_setg(&error, "Unable to find CPU definition: %s", name);
2205 goto out;
2206 }
285f025d 2207
d940ee9b
EH		 2208 cpu = X86_CPU(object_new(object_class_get_name(oc)));
2209
94a444b2 2210 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2d64255b
AF		 2211 if (error) {
2212 goto out;
5c3c6a68
AF		 2213 }
2214
7f833247 2215out:
cd7b87ff
AF		 2216 if (error != NULL) {
2217 error_propagate(errp, error);
500050d1
AF		 2218 if (cpu) {
2219 object_unref(OBJECT(cpu));
2220 cpu = NULL;
2221 }
cd7b87ff 2222 }
7f833247
IM		 2223 g_strfreev(model_pieces);
2224 return cpu;
2225}
2226
0856579c 2227X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2228{
a57d0163 2229 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2230}
2231
d940ee9b
EH		 2232static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2233{
2234 X86CPUDefinition *cpudef = data;
2235 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2236
2237 xcc->cpu_def = cpudef;
2238}
2239
2240static void x86_register_cpudef_type(X86CPUDefinition *def)
2241{
2242 char *typename = x86_cpu_type_name(def->name);
2243 TypeInfo ti = {
2244 .name = typename,
2245 .parent = TYPE_X86_CPU,
2246 .class_init = x86_cpu_cpudef_class_init,
2247 .class_data = def,
2248 };
2249
2250 type_register(&ti);
2251 g_free(typename);
2252}
2253
c6dc6f63 2254#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2255
0e26b7b8
BS		 2256void cpu_clear_apic_feature(CPUX86State *env)
2257{
0514ef2f 2258 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2259}
2260
c6dc6f63
AP		 2261#endif /* !CONFIG_USER_ONLY */
2262
c6dc6f63
AP		 2263void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2264 uint32_t *eax, uint32_t *ebx,
2265 uint32_t *ecx, uint32_t *edx)
2266{
a60f24b5
AF		 2267 X86CPU *cpu = x86_env_get_cpu(env);
2268 CPUState *cs = CPU(cpu);
2269
c6dc6f63
AP		 2270 /* test if maximum index reached */
2271 if (index & 0x80000000) {
b3baa152
BW		 2272 if (index > env->cpuid_xlevel) {
2273 if (env->cpuid_xlevel2 > 0) {
2274 /* Handle the Centaur's CPUID instruction. */
2275 if (index > env->cpuid_xlevel2) {
2276 index = env->cpuid_xlevel2;
2277 } else if (index < 0xC0000000) {
2278 index = env->cpuid_xlevel;
2279 }
2280 } else {
57f26ae7
EH		 2281 /* Intel documentation states that invalid EAX input will
2282 * return the same information as EAX=cpuid_level
2283 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2284 */
2285 index = env->cpuid_level;
b3baa152
BW		 2286 }
2287 }
c6dc6f63
AP		 2288 } else {
2289 if (index > env->cpuid_level)
2290 index = env->cpuid_level;
2291 }
2292
2293 switch(index) {
2294 case 0:
2295 *eax = env->cpuid_level;
5eb2f7a4
EH		 2296 *ebx = env->cpuid_vendor1;
2297 *edx = env->cpuid_vendor2;
2298 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2299 break;
2300 case 1:
2301 *eax = env->cpuid_version;
7e72a45c
EH		 2302 *ebx = (cpu->apic_id << 24) |
2303 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2304 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2305 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2306 *ecx |= CPUID_EXT_OSXSAVE;
2307 }
0514ef2f 2308 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2309 if (cs->nr_cores * cs->nr_threads > 1) {
2310 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2311 *edx |= CPUID_HT;
c6dc6f63
AP		 2312 }
2313 break;
2314 case 2:
2315 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2316 if (cpu->cache_info_passthrough) {
2317 host_cpuid(index, 0, eax, ebx, ecx, edx);
2318 break;
2319 }
5e891bf8 2320 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2321 *ebx = 0;
2322 *ecx = 0;
5e891bf8
EH		 2323 *edx = (L1D_DESCRIPTOR << 16) | \
2324 (L1I_DESCRIPTOR << 8) | \
2325 (L2_DESCRIPTOR);
c6dc6f63
AP		 2326 break;
2327 case 4:
2328 /* cache info: needed for Core compatibility */
787aaf57
BC		 2329 if (cpu->cache_info_passthrough) {
2330 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2331 *eax &= ~0xFC000000;
c6dc6f63 2332 } else {
2f7a21c4 2333 *eax = 0;
76c2975a 2334 switch (count) {
c6dc6f63 2335 case 0: /* L1 dcache info */
5e891bf8
EH		 2336 *eax |= CPUID_4_TYPE_DCACHE | \
2337 CPUID_4_LEVEL(1) | \
2338 CPUID_4_SELF_INIT_LEVEL;
2339 *ebx = (L1D_LINE_SIZE - 1) | \
2340 ((L1D_PARTITIONS - 1) << 12) | \
2341 ((L1D_ASSOCIATIVITY - 1) << 22);
2342 *ecx = L1D_SETS - 1;
2343 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2344 break;
2345 case 1: /* L1 icache info */
5e891bf8
EH		 2346 *eax |= CPUID_4_TYPE_ICACHE | \
2347 CPUID_4_LEVEL(1) | \
2348 CPUID_4_SELF_INIT_LEVEL;
2349 *ebx = (L1I_LINE_SIZE - 1) | \
2350 ((L1I_PARTITIONS - 1) << 12) | \
2351 ((L1I_ASSOCIATIVITY - 1) << 22);
2352 *ecx = L1I_SETS - 1;
2353 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2354 break;
2355 case 2: /* L2 cache info */
5e891bf8
EH		 2356 *eax |= CPUID_4_TYPE_UNIFIED | \
2357 CPUID_4_LEVEL(2) | \
2358 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2359 if (cs->nr_threads > 1) {
2360 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2361 }
5e891bf8
EH		 2362 *ebx = (L2_LINE_SIZE - 1) | \
2363 ((L2_PARTITIONS - 1) << 12) | \
2364 ((L2_ASSOCIATIVITY - 1) << 22);
2365 *ecx = L2_SETS - 1;
2366 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2367 break;
2368 default: /* end of info */
2369 *eax = 0;
2370 *ebx = 0;
2371 *ecx = 0;
2372 *edx = 0;
2373 break;
76c2975a
PB		 2374 }
2375 }
2376
2377 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2378 if ((*eax & 31) && cs->nr_cores > 1) {
2379 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2380 }
2381 break;
2382 case 5:
2383 /* mwait info: needed for Core compatibility */
2384 *eax = 0; /* Smallest monitor-line size in bytes */
2385 *ebx = 0; /* Largest monitor-line size in bytes */
2386 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2387 *edx = 0;
2388 break;
2389 case 6:
2390 /* Thermal and Power Leaf */
28b8e4d0 2391 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2392 *ebx = 0;
2393 *ecx = 0;
2394 *edx = 0;
2395 break;
f7911686 2396 case 7:
13526728
EH		 2397 /* Structured Extended Feature Flags Enumeration Leaf */
2398 if (count == 0) {
2399 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2400 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2401 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2402 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2403 *ecx |= CPUID_7_0_ECX_OSPKE;
2404 }
13526728 2405 *edx = 0; /* Reserved */
f7911686
YW		 2406 } else {
2407 *eax = 0;
2408 *ebx = 0;
2409 *ecx = 0;
2410 *edx = 0;
2411 }
2412 break;
c6dc6f63
AP		 2413 case 9:
2414 /* Direct Cache Access Information Leaf */
2415 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2416 *ebx = 0;
2417 *ecx = 0;
2418 *edx = 0;
2419 break;
2420 case 0xA:
2421 /* Architectural Performance Monitoring Leaf */
9337e3b6 2422 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2423 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2424
2425 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2426 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2427 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2428 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2429 } else {
2430 *eax = 0;
2431 *ebx = 0;
2432 *ecx = 0;
2433 *edx = 0;
2434 }
c6dc6f63 2435 break;
5232d00a
RK		 2436 case 0xB:
2437 /* Extended Topology Enumeration Leaf */
2438 if (!cpu->enable_cpuid_0xb) {
2439 *eax = *ebx = *ecx = *edx = 0;
2440 break;
2441 }
2442
2443 *ecx = count & 0xff;
2444 *edx = cpu->apic_id;
2445
2446 switch (count) {
2447 case 0:
2448 *eax = apicid_core_offset(smp_cores, smp_threads);
2449 *ebx = smp_threads;
2450 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2451 break;
2452 case 1:
2453 *eax = apicid_pkg_offset(smp_cores, smp_threads);
2454 *ebx = smp_cores * smp_threads;
2455 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2456 break;
2457 default:
2458 *eax = 0;
2459 *ebx = 0;
2460 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2461 }
2462
2463 assert(!(*eax & ~0x1f));
2464 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2465 break;
2560f19f
PB		 2466 case 0xD: {
2467 KVMState *s = cs->kvm_state;
19dc85db 2468 uint64_t ena_mask;
2560f19f
PB		 2469 int i;
2470
51e49430 2471 /* Processor Extended State */
2560f19f
PB		 2472 *eax = 0;
2473 *ebx = 0;
2474 *ecx = 0;
2475 *edx = 0;
19dc85db 2476 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2477 break;
2478 }
19dc85db
RH		 2479 if (kvm_enabled()) {
2480 ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2481 ena_mask <<= 32;
2482 ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2483 } else {
2484 ena_mask = -1;
2485 }
ba9bc59e 2486
2560f19f
PB		 2487 if (count == 0) {
2488 *ecx = 0x240;
f4f1110e
RH		 2489 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2490 const ExtSaveArea *esa = &x86_ext_save_areas[i];
19dc85db
RH		 2491 if ((env->features[esa->feature] & esa->bits) == esa->bits
2492 && ((ena_mask >> i) & 1) != 0) {
2560f19f 2493 if (i < 32) {
19dc85db 2494 *eax |= 1u << i;
2560f19f 2495 } else {
19dc85db 2496 *edx |= 1u << (i - 32);
2560f19f
PB		 2497 }
2498 *ecx = MAX(*ecx, esa->offset + esa->size);
2499 }
2500 }
cfc3b074 2501 *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2560f19f
PB		 2502 *ebx = *ecx;
2503 } else if (count == 1) {
0bb0b2d2 2504 *eax = env->features[FEAT_XSAVE];
f4f1110e
RH		 2505 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2506 const ExtSaveArea *esa = &x86_ext_save_areas[count];
19dc85db
RH		 2507 if ((env->features[esa->feature] & esa->bits) == esa->bits
2508 && ((ena_mask >> count) & 1) != 0) {
33f373d7
LJ		 2509 *eax = esa->size;
2510 *ebx = esa->offset;
2560f19f 2511 }
51e49430
SY		 2512 }
2513 break;
2560f19f 2514 }
c6dc6f63
AP		 2515 case 0x80000000:
2516 *eax = env->cpuid_xlevel;
2517 *ebx = env->cpuid_vendor1;
2518 *edx = env->cpuid_vendor2;
2519 *ecx = env->cpuid_vendor3;
2520 break;
2521 case 0x80000001:
2522 *eax = env->cpuid_version;
2523 *ebx = 0;
0514ef2f
EH		 2524 *ecx = env->features[FEAT_8000_0001_ECX];
2525 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2526
2527 /* The Linux kernel checks for the CMPLegacy bit and
2528 * discards multiple thread information if it is set.
cb8d4c8f 2529 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2530 */
ce3960eb 2531 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2532 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2533 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2534 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2535 *ecx |= 1 << 1; /* CmpLegacy bit */
2536 }
2537 }
c6dc6f63
AP		 2538 break;
2539 case 0x80000002:
2540 case 0x80000003:
2541 case 0x80000004:
2542 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2543 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2544 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2545 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2546 break;
2547 case 0x80000005:
2548 /* cache info (L1 cache) */
787aaf57
BC		 2549 if (cpu->cache_info_passthrough) {
2550 host_cpuid(index, 0, eax, ebx, ecx, edx);
2551 break;
2552 }
5e891bf8
EH		 2553 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2554 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2555 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2556 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2557 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2558 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2559 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2560 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2561 break;
2562 case 0x80000006:
2563 /* cache info (L2 cache) */
787aaf57
BC		 2564 if (cpu->cache_info_passthrough) {
2565 host_cpuid(index, 0, eax, ebx, ecx, edx);
2566 break;
2567 }
5e891bf8
EH		 2568 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2569 (L2_DTLB_2M_ENTRIES << 16) | \
2570 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2571 (L2_ITLB_2M_ENTRIES);
2572 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2573 (L2_DTLB_4K_ENTRIES << 16) | \
2574 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2575 (L2_ITLB_4K_ENTRIES);
2576 *ecx = (L2_SIZE_KB_AMD << 16) | \
2577 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2578 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2579 *edx = ((L3_SIZE_KB/512) << 18) | \
2580 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2581 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2582 break;
303752a9
MT		 2583 case 0x80000007:
2584 *eax = 0;
2585 *ebx = 0;
2586 *ecx = 0;
2587 *edx = env->features[FEAT_8000_0007_EDX];
2588 break;
c6dc6f63
AP		 2589 case 0x80000008:
2590 /* virtual & phys address size in low 2 bytes. */
2591/* XXX: This value must match the one used in the MMU code. */
0514ef2f 2592 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
c6dc6f63
AP		 2593 /* 64 bit processor */
2594/* XXX: The physical address space is limited to 42 bits in exec.c. */
dd13e088 2595 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
c6dc6f63 2596 } else {
0514ef2f 2597 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
c6dc6f63 2598 *eax = 0x00000024; /* 36 bits physical */
dd13e088 2599 } else {
c6dc6f63 2600 *eax = 0x00000020; /* 32 bits physical */
dd13e088 2601 }
c6dc6f63
AP		 2602 }
2603 *ebx = 0;
2604 *ecx = 0;
2605 *edx = 0;
ce3960eb
AF		 2606 if (cs->nr_cores * cs->nr_threads > 1) {
2607 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2608 }
2609 break;
2610 case 0x8000000A:
0514ef2f 2611 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2612 *eax = 0x00000001; /* SVM Revision */
2613 *ebx = 0x00000010; /* nr of ASIDs */
2614 *ecx = 0;
0514ef2f 2615 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2616 } else {
2617 *eax = 0;
2618 *ebx = 0;
2619 *ecx = 0;
2620 *edx = 0;
2621 }
c6dc6f63 2622 break;
b3baa152
BW		 2623 case 0xC0000000:
2624 *eax = env->cpuid_xlevel2;
2625 *ebx = 0;
2626 *ecx = 0;
2627 *edx = 0;
2628 break;
2629 case 0xC0000001:
2630 /* Support for VIA CPU's CPUID instruction */
2631 *eax = env->cpuid_version;
2632 *ebx = 0;
2633 *ecx = 0;
0514ef2f 2634 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2635 break;
2636 case 0xC0000002:
2637 case 0xC0000003:
2638 case 0xC0000004:
2639 /* Reserved for the future, and now filled with zero */
2640 *eax = 0;
2641 *ebx = 0;
2642 *ecx = 0;
2643 *edx = 0;
2644 break;
c6dc6f63
AP		 2645 default:
2646 /* reserved values: zero */
2647 *eax = 0;
2648 *ebx = 0;
2649 *ecx = 0;
2650 *edx = 0;
2651 break;
2652 }
2653}
5fd2087a
AF		 2654
2655/* CPUClass::reset() */
2656static void x86_cpu_reset(CPUState *s)
2657{
2658 X86CPU *cpu = X86_CPU(s);
2659 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2660 CPUX86State *env = &cpu->env;
a114d25d
RH		 2661 target_ulong cr4;
2662 uint64_t xcr0;
c1958aea
AF		 2663 int i;
2664
5fd2087a
AF		 2665 xcc->parent_reset(s);
2666
43175fa9 2667 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2668
00c8cb0a 2669 tlb_flush(s, 1);
c1958aea
AF		 2670
2671 env->old_exception = -1;
2672
2673 /* init to reset state */
2674
2675#ifdef CONFIG_SOFTMMU
2676 env->hflags |= HF_SOFTMMU_MASK;
2677#endif
2678 env->hflags2 |= HF2_GIF_MASK;
2679
2680 cpu_x86_update_cr0(env, 0x60000010);
2681 env->a20_mask = ~0x0;
2682 env->smbase = 0x30000;
2683
2684 env->idt.limit = 0xffff;
2685 env->gdt.limit = 0xffff;
2686 env->ldt.limit = 0xffff;
2687 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2688 env->tr.limit = 0xffff;
2689 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2690
2691 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2692 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2693 DESC_R_MASK | DESC_A_MASK);
2694 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2695 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2696 DESC_A_MASK);
2697 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2698 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2699 DESC_A_MASK);
2700 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2701 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2702 DESC_A_MASK);
2703 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2704 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2705 DESC_A_MASK);
2706 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2707 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2708 DESC_A_MASK);
2709
2710 env->eip = 0xfff0;
2711 env->regs[R_EDX] = env->cpuid_version;
2712
2713 env->eflags = 0x2;
2714
2715 /* FPU init */
2716 for (i = 0; i < 8; i++) {
2717 env->fptags[i] = 1;
2718 }
5bde1407 2719 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2720
2721 env->mxcsr = 0x1f80;
a114d25d
RH		 2722 /* All units are in INIT state. */
2723 env->xstate_bv = 0;
c1958aea
AF		 2724
2725 env->pat = 0x0007040600070406ULL;
2726 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2727
2728 memset(env->dr, 0, sizeof(env->dr));
2729 env->dr[6] = DR6_FIXED_1;
2730 env->dr[7] = DR7_FIXED_1;
b3310ab3 2731 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2732 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2733
a114d25d 2734 cr4 = 0;
cfc3b074 2735 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2736
2737#ifdef CONFIG_USER_ONLY
2738 /* Enable all the features for user-mode. */
2739 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2740 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2741 }
0f70ed47
PB		 2742 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2743 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2744 if ((env->features[esa->feature] & esa->bits) == esa->bits) {
2745 xcr0 |= 1ull << i;
2746 }
a114d25d 2747 }
0f70ed47 2748
a114d25d
RH		 2749 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2750 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2751 }
07929f2a
RH		 2752 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2753 cr4 |= CR4_FSGSBASE_MASK;
2754 }
a114d25d
RH		 2755#endif
2756
2757 env->xcr0 = xcr0;
2758 cpu_x86_update_cr4(env, cr4);
0522604b 2759
9db2efd9
AW		 2760 /*
2761 * SDM 11.11.5 requires:
2762 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2763 * - IA32_MTRR_PHYSMASKn.V = 0
2764 * All other bits are undefined. For simplification, zero it all.
2765 */
2766 env->mtrr_deftype = 0;
2767 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2768 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2769
dd673288
IM		 2770#if !defined(CONFIG_USER_ONLY)
2771 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2772 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2773
259186a7 2774 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2775
2776 if (kvm_enabled()) {
2777 kvm_arch_reset_vcpu(cpu);
2778 }
dd673288 2779#endif
5fd2087a
AF		 2780}
2781
dd673288
IM		 2782#ifndef CONFIG_USER_ONLY
2783bool cpu_is_bsp(X86CPU *cpu)
2784{
02e51483 2785 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2786}
65dee380
IM		 2787
2788/* TODO: remove me, when reset over QOM tree is implemented */
2789static void x86_cpu_machine_reset_cb(void *opaque)
2790{
2791 X86CPU *cpu = opaque;
2792 cpu_reset(CPU(cpu));
2793}
dd673288
IM		 2794#endif
2795
de024815
AF		 2796static void mce_init(X86CPU *cpu)
2797{
2798 CPUX86State *cenv = &cpu->env;
2799 unsigned int bank;
2800
2801 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2802 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815
AF		 2803 (CPUID_MCE | CPUID_MCA)) {
2804 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2805 cenv->mcg_ctl = ~(uint64_t)0;
2806 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2807 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2808 }
2809 }
2810}
2811
bdeec802 2812#ifndef CONFIG_USER_ONLY
d3c64d6a 2813static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2814{
449994eb 2815 APICCommonState *apic;
bdeec802
IM		 2816 const char *apic_type = "apic";
2817
15eafc2e 2818 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2819 apic_type = "kvm-apic";
2820 } else if (xen_enabled()) {
2821 apic_type = "xen-apic";
2822 }
2823
46232aaa 2824 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802
IM		 2825
2826 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2827 OBJECT(cpu->apic_state), NULL);
7e72a45c 2828 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2829 /* TODO: convert to link<> */
02e51483 2830 apic = APIC_COMMON(cpu->apic_state);
60671e58 2831 apic->cpu = cpu;
8d42d2d3 2832 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2833}
2834
2835static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2836{
8d42d2d3
CF		 2837 APICCommonState *apic;
2838 static bool apic_mmio_map_once;
2839
02e51483 2840 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2841 return;
2842 }
6e8e2651
MA		 2843 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2844 errp);
8d42d2d3
CF		 2845
2846 /* Map APIC MMIO area */
2847 apic = APIC_COMMON(cpu->apic_state);
2848 if (!apic_mmio_map_once) {
2849 memory_region_add_subregion_overlap(get_system_memory(),
2850 apic->apicbase &
2851 MSR_IA32_APICBASE_BASE,
2852 &apic->io_memory,
2853 0x1000);
2854 apic_mmio_map_once = true;
2855 }
bdeec802 2856}
f809c605
PB		 2857
2858static void x86_cpu_machine_done(Notifier *n, void *unused)
2859{
2860 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2861 MemoryRegion *smram =
2862 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2863
2864 if (smram) {
2865 cpu->smram = g_new(MemoryRegion, 1);
2866 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2867 smram, 0, 1ull << 32);
2868 memory_region_set_enabled(cpu->smram, false);
2869 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2870 }
2871}
d3c64d6a
IM		 2872#else
2873static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2874{
2875}
bdeec802
IM		 2876#endif
2877
e48638fd
WH		 2878
2879#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2880 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2881 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2882#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2883 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2884 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2885static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2886{
14a10fc3 2887 CPUState *cs = CPU(dev);
2b6f294c
AF		 2888 X86CPU *cpu = X86_CPU(dev);
2889 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2890 CPUX86State *env = &cpu->env;
2b6f294c 2891 Error *local_err = NULL;
e48638fd 2892 static bool ht_warned;
dc15c051 2893 FeatureWord w;
b34d12d1 2894
104494ea
IM		 2895 if (xcc->kvm_required && !kvm_enabled()) {
2896 char *name = x86_cpu_class_get_model_name(xcc);
2897 error_setg(&local_err, "CPU model '%s' requires KVM", name);
2898 g_free(name);
2899 goto out;
2900 }
2901
9886e834
EH		 2902 if (cpu->apic_id < 0) {
2903 error_setg(errp, "apic-id property was not initialized properly");
2904 return;
2905 }
2906
dc15c051
IM		 2907 /*TODO: cpu->host_features incorrectly overwrites features
2908 * set using "feat=on|off". Once we fix this, we can convert
2909 * plus_features & minus_features to global properties
2910 * inside x86_cpu_parse_featurestr() too.
2911 */
2912 if (cpu->host_features) {
2913 for (w = 0; w < FEATURE_WORDS; w++) {
2914 env->features[w] =
2915 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2916 }
2917 }
2918
2919 for (w = 0; w < FEATURE_WORDS; w++) {
2920 cpu->env.features[w] |= plus_features[w];
2921 cpu->env.features[w] &= ~minus_features[w];
2922 }
2923
0514ef2f 2924 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2925 env->cpuid_level = 7;
2926 }
7a059953 2927
9997cf7b
EH		 2928 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2929 error_setg(&local_err,
2930 kvm_enabled() ?
2931 "Host doesn't support requested features" :
2932 "TCG doesn't support requested features");
2933 goto out;
2934 }
2935
9b15cd9e
IM		 2936 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2937 * CPUID[1].EDX.
2938 */
e48638fd 2939 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2940 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2941 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 2942 & CPUID_EXT2_AMD_ALIASES);
2943 }
2944
fefb41bf 2945
42ecabaa
EH		 2946 cpu_exec_init(cs, &error_abort);
2947
57f2453a
EH		 2948 if (tcg_enabled()) {
2949 tcg_x86_init();
2950 }
2951
65dee380
IM		 2952#ifndef CONFIG_USER_ONLY
2953 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 2954
0514ef2f 2955 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 2956 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 2957 if (local_err != NULL) {
4dc1f449 2958 goto out;
bdeec802
IM		 2959 }
2960 }
65dee380
IM		 2961#endif
2962
7a059953 2963 mce_init(cpu);
2001d0cd
PB		 2964
2965#ifndef CONFIG_USER_ONLY
2966 if (tcg_enabled()) {
56943e8c
PM		 2967 AddressSpace *newas = g_new(AddressSpace, 1);
2968
f809c605 2969 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 2970 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 2971
2972 /* Outer container... */
2973 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 2974 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 2975
2976 /* ... with two regions inside: normal system memory with low
2977 * priority, and...
2978 */
2979 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
2980 get_system_memory(), 0, ~0ull);
2981 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
2982 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 2983 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 2984 cs->num_ases = 1;
56943e8c 2985 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 2986
2987 /* ... SMRAM with higher priority, linked from /machine/smram. */
2988 cpu->machine_done.notify = x86_cpu_machine_done;
2989 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 2990 }
2991#endif
2992
14a10fc3 2993 qemu_init_vcpu(cs);
d3c64d6a 2994
e48638fd
WH		 2995 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
2996 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
2997 * based on inputs (sockets,cores,threads), it is still better to gives
2998 * users a warning.
2999 *
3000 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3001 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3002 */
3003 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3004 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3005 " -smp options properly.");
3006 ht_warned = true;
3007 }
3008
d3c64d6a
IM		 3009 x86_cpu_apic_realize(cpu, &local_err);
3010 if (local_err != NULL) {
3011 goto out;
3012 }
14a10fc3 3013 cpu_reset(cs);
2b6f294c 3014
4dc1f449 3015 xcc->parent_realize(dev, &local_err);
2001d0cd 3016
4dc1f449
IM		 3017out:
3018 if (local_err != NULL) {
3019 error_propagate(errp, local_err);
3020 return;
3021 }
7a059953
AF		 3022}
3023
38e5c119
EH		 3024typedef struct BitProperty {
3025 uint32_t *ptr;
3026 uint32_t mask;
3027} BitProperty;
3028
d7bce999
EB		 3029static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3030 void *opaque, Error **errp)
38e5c119
EH		 3031{
3032 BitProperty *fp = opaque;
3033 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3034 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3035}
3036
d7bce999
EB		 3037static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3038 void *opaque, Error **errp)
38e5c119
EH		 3039{
3040 DeviceState *dev = DEVICE(obj);
3041 BitProperty *fp = opaque;
3042 Error *local_err = NULL;
3043 bool value;
3044
3045 if (dev->realized) {
3046 qdev_prop_set_after_realize(dev, name, errp);
3047 return;
3048 }
3049
51e72bc1 3050 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3051 if (local_err) {
3052 error_propagate(errp, local_err);
3053 return;
3054 }
3055
3056 if (value) {
3057 *fp->ptr |= fp->mask;
3058 } else {
3059 *fp->ptr &= ~fp->mask;
3060 }
3061}
3062
3063static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3064 void *opaque)
3065{
3066 BitProperty *prop = opaque;
3067 g_free(prop);
3068}
3069
3070/* Register a boolean property to get/set a single bit in a uint32_t field.
3071 *
3072 * The same property name can be registered multiple times to make it affect
3073 * multiple bits in the same FeatureWord. In that case, the getter will return
3074 * true only if all bits are set.
3075 */
3076static void x86_cpu_register_bit_prop(X86CPU *cpu,
3077 const char *prop_name,
3078 uint32_t *field,
3079 int bitnr)
3080{
3081 BitProperty *fp;
3082 ObjectProperty *op;
3083 uint32_t mask = (1UL << bitnr);
3084
3085 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3086 if (op) {
3087 fp = op->opaque;
3088 assert(fp->ptr == field);
3089 fp->mask |= mask;
3090 } else {
3091 fp = g_new0(BitProperty, 1);
3092 fp->ptr = field;
3093 fp->mask = mask;
3094 object_property_add(OBJECT(cpu), prop_name, "bool",
3095 x86_cpu_get_bit_prop,
3096 x86_cpu_set_bit_prop,
3097 x86_cpu_release_bit_prop, fp, &error_abort);
3098 }
3099}
3100
3101static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3102 FeatureWord w,
3103 int bitnr)
3104{
3105 Object *obj = OBJECT(cpu);
3106 int i;
3107 char **names;
3108 FeatureWordInfo *fi = &feature_word_info[w];
3109
3110 if (!fi->feat_names) {
3111 return;
3112 }
3113 if (!fi->feat_names[bitnr]) {
3114 return;
3115 }
3116
3117 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3118
3119 feat2prop(names[0]);
3120 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3121
3122 for (i = 1; names[i]; i++) {
3123 feat2prop(names[i]);
d461a44c 3124 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3125 &error_abort);
3126 }
3127
3128 g_strfreev(names);
3129}
3130
de024815
AF		 3131static void x86_cpu_initfn(Object *obj)
3132{
55e5c285 3133 CPUState *cs = CPU(obj);
de024815 3134 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3135 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3136 CPUX86State *env = &cpu->env;
38e5c119 3137 FeatureWord w;
de024815 3138
c05efcb1 3139 cs->env_ptr = env;
71ad61d3
AF		 3140
3141 object_property_add(obj, "family", "int",
95b8519d 3142 x86_cpuid_version_get_family,
71ad61d3 3143 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3144 object_property_add(obj, "model", "int",
67e30c83 3145 x86_cpuid_version_get_model,
c5291a4f 3146 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3147 object_property_add(obj, "stepping", "int",
35112e41 3148 x86_cpuid_version_get_stepping,
036e2222 3149 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3150 object_property_add_str(obj, "vendor",
3151 x86_cpuid_get_vendor,
3152 x86_cpuid_set_vendor, NULL);
938d4c25 3153 object_property_add_str(obj, "model-id",
63e886eb 3154 x86_cpuid_get_model_id,
938d4c25 3155 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3156 object_property_add(obj, "tsc-frequency", "int",
3157 x86_cpuid_get_tsc_freq,
3158 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3159 object_property_add(obj, "apic-id", "int",
3160 x86_cpuid_get_apic_id,
3161 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3162 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3163 x86_cpu_get_feature_words,
7e5292b5
EH		 3164 NULL, NULL, (void *)env->features, NULL);
3165 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3166 x86_cpu_get_feature_words,
3167 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3168
92067bf4 3169 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3170
9886e834
EH		 3171#ifndef CONFIG_USER_ONLY
3172 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3173 cpu->apic_id = -1;
3174#endif
3175
38e5c119
EH		 3176 for (w = 0; w < FEATURE_WORDS; w++) {
3177 int bitnr;
3178
3179 for (bitnr = 0; bitnr < 32; bitnr++) {
3180 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3181 }
3182 }
3183
d940ee9b 3184 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3185}
3186
997395d3
IM		 3187static int64_t x86_cpu_get_arch_id(CPUState *cs)
3188{
3189 X86CPU *cpu = X86_CPU(cs);
997395d3 3190
7e72a45c 3191 return cpu->apic_id;
997395d3
IM		 3192}
3193
444d5590
AF		 3194static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3195{
3196 X86CPU *cpu = X86_CPU(cs);
3197
3198 return cpu->env.cr[0] & CR0_PG_MASK;
3199}
3200
f45748f1
AF		 3201static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3202{
3203 X86CPU *cpu = X86_CPU(cs);
3204
3205 cpu->env.eip = value;
3206}
3207
bdf7ae5b
AF		 3208static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3209{
3210 X86CPU *cpu = X86_CPU(cs);
3211
3212 cpu->env.eip = tb->pc - tb->cs_base;
3213}
3214
8c2e1b00
AF		 3215static bool x86_cpu_has_work(CPUState *cs)
3216{
3217 X86CPU *cpu = X86_CPU(cs);
3218 CPUX86State *env = &cpu->env;
3219
6220e900
PD		 3220 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3221 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3222 (env->eflags & IF_MASK)) ||
3223 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3224 CPU_INTERRUPT_INIT |
3225 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3226 CPU_INTERRUPT_MCE)) ||
3227 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3228 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3229}
3230
9337e3b6
EH		 3231static Property x86_cpu_properties[] = {
3232 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3233 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3234 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3235 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3236 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3237 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3238 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3239 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3240 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3241 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3242 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3243 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3244 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3245 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
b9472b76
EH		 3246 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3247 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3248 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
1c4a55db 3249 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3250 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
9337e3b6
EH		 3251 DEFINE_PROP_END_OF_LIST()
3252};
3253
5fd2087a
AF		 3254static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3255{
3256 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3257 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3258 DeviceClass *dc = DEVICE_CLASS(oc);
3259
3260 xcc->parent_realize = dc->realize;
3261 dc->realize = x86_cpu_realizefn;
9337e3b6 3262 dc->props = x86_cpu_properties;
5fd2087a
AF		 3263
3264 xcc->parent_reset = cc->reset;
3265 cc->reset = x86_cpu_reset;
91b1df8c 3266 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3267
500050d1 3268 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3269 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3270 cc->has_work = x86_cpu_has_work;
97a8ea5a 3271 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3272 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3273 cc->dump_state = x86_cpu_dump_state;
f45748f1 3274 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3275 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3276 cc->gdb_read_register = x86_cpu_gdb_read_register;
3277 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3278 cc->get_arch_id = x86_cpu_get_arch_id;
3279 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3280#ifdef CONFIG_USER_ONLY
3281 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3282#else
a23bbfda 3283 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3284 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3285 cc->write_elf64_note = x86_cpu_write_elf64_note;
3286 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3287 cc->write_elf32_note = x86_cpu_write_elf32_note;
3288 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3289 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3290#endif
a0e372f0 3291 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3292#ifndef CONFIG_USER_ONLY
3293 cc->debug_excp_handler = breakpoint_handler;
3294#endif
374e0cd4
RH		 3295 cc->cpu_exec_enter = x86_cpu_exec_enter;
3296 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27
MA		 3297
3298 /*
3299 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3300 * object in cpus -> dangling pointer after final object_unref().
3301 */
3302 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3303}
3304
3305static const TypeInfo x86_cpu_type_info = {
3306 .name = TYPE_X86_CPU,
3307 .parent = TYPE_CPU,
3308 .instance_size = sizeof(X86CPU),
de024815 3309 .instance_init = x86_cpu_initfn,
d940ee9b 3310 .abstract = true,
5fd2087a
AF		 3311 .class_size = sizeof(X86CPUClass),
3312 .class_init = x86_cpu_common_class_init,
3313};
3314
3315static void x86_cpu_register_types(void)
3316{
d940ee9b
EH		 3317 int i;
3318
5fd2087a 3319 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3320 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3321 x86_register_cpudef_type(&builtin_x86_defs[i]);
3322 }
3323#ifdef CONFIG_KVM
3324 type_register_static(&host_x86_cpu_type_info);
3325#endif
5fd2087a
AF		 3326}
3327
3328type_init(x86_cpu_register_types)
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