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target-i386: Mask mtrr mask based on CPU physical address limits
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c6dc6f63
AP
1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP
21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB
29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH
33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM
50#endif
51
5e891bf8
EH
52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM
164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP
176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH
200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH
206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP
214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP
219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP
223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH
226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP
246};
247
c35bd19a
EY
248static const char *hyperv_priv_feature_name[] = {
249 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
250 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
251 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
252 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
253 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
254 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257 NULL, NULL, NULL, NULL,
258 NULL, NULL, NULL, NULL,
259 NULL, NULL, NULL, NULL,
260};
261
262static const char *hyperv_ident_feature_name[] = {
263 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
264 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
265 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
266 NULL /* hv_create_port */, NULL /* hv_connect_port */,
267 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
268 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
269 NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274};
275
276static const char *hyperv_misc_feature_name[] = {
277 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
278 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
279 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
280 NULL, NULL,
281 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286 NULL, NULL, NULL, NULL,
287};
288
296acb64
JR
289static const char *svm_feature_name[] = {
290 "npt", "lbrv", "svm_lock", "nrip_save",
291 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
292 NULL, NULL, "pause_filter", NULL,
293 "pfthreshold", NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296 NULL, NULL, NULL, NULL,
297 NULL, NULL, NULL, NULL,
298};
299
a9321a4d 300static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 301 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 302 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
f7fda280
XG
303 "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
304 "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA
305};
306
f74eefe0
HH
307static const char *cpuid_7_0_ecx_feature_name[] = {
308 NULL, NULL, NULL, "pku",
309 "ospke", NULL, NULL, NULL,
310 NULL, NULL, NULL, NULL,
311 NULL, NULL, NULL, NULL,
312 NULL, NULL, NULL, NULL,
313 NULL, NULL, NULL, NULL,
314 NULL, NULL, NULL, NULL,
315 NULL, NULL, NULL, NULL,
316};
317
303752a9
MT
318static const char *cpuid_apm_edx_feature_name[] = {
319 NULL, NULL, NULL, NULL,
320 NULL, NULL, NULL, NULL,
321 "invtsc", NULL, NULL, NULL,
322 NULL, NULL, NULL, NULL,
323 NULL, NULL, NULL, NULL,
324 NULL, NULL, NULL, NULL,
325 NULL, NULL, NULL, NULL,
326 NULL, NULL, NULL, NULL,
327};
328
0bb0b2d2
PB
329static const char *cpuid_xsave_feature_name[] = {
330 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
331 NULL, NULL, NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 NULL, NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338};
339
28b8e4d0
JK
340static const char *cpuid_6_feature_name[] = {
341 NULL, NULL, "arat", NULL,
342 NULL, NULL, NULL, NULL,
343 NULL, NULL, NULL, NULL,
344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349};
350
621626ce
EH
351#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
352#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
353 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
354#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
355 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
356 CPUID_PSE36 | CPUID_FXSR)
357#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
358#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
359 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
360 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
361 CPUID_PAE | CPUID_SEP | CPUID_APIC)
362
363#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
364 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
365 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
366 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 367 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH
368 /* partly implemented:
369 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
370 /* missing:
371 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
372#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
373 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
374 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 375 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH
376 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
377 /* missing:
378 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
379 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
380 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH
381 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
382 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH
383
384#ifdef TARGET_X86_64
385#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
386#else
387#define TCG_EXT2_X86_64_FEATURES 0
388#endif
389
390#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
391 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
392 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
393 TCG_EXT2_X86_64_FEATURES)
394#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
395 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
396#define TCG_EXT4_FEATURES 0
397#define TCG_SVM_FEATURES 0
398#define TCG_KVM_FEATURES 0
399#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG
400 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
401 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB
402 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
403 CPUID_7_0_EBX_ERMS)
621626ce 404 /* missing:
07929f2a 405 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 406 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 407 CPUID_7_0_EBX_RDSEED */
0f70ed47 408#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 409#define TCG_APM_FEATURES 0
28b8e4d0 410#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH
411#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
412 /* missing:
413 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 414
5ef57876
EH
415typedef struct FeatureWordInfo {
416 const char **feat_names;
04d104b6
EH
417 uint32_t cpuid_eax; /* Input EAX for CPUID */
418 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
419 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
420 int cpuid_reg; /* output register (R_* constant) */
37ce3522 421 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 422 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH
423} FeatureWordInfo;
424
425static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH
426 [FEAT_1_EDX] = {
427 .feat_names = feature_name,
428 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 429 .tcg_features = TCG_FEATURES,
bffd67b0
EH
430 },
431 [FEAT_1_ECX] = {
432 .feat_names = ext_feature_name,
433 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 434 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH
435 },
436 [FEAT_8000_0001_EDX] = {
437 .feat_names = ext2_feature_name,
438 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 439 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH
440 },
441 [FEAT_8000_0001_ECX] = {
442 .feat_names = ext3_feature_name,
443 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 444 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 445 },
89e49c8b
EH
446 [FEAT_C000_0001_EDX] = {
447 .feat_names = ext4_feature_name,
448 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 449 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 450 },
bffd67b0
EH
451 [FEAT_KVM] = {
452 .feat_names = kvm_feature_name,
453 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 454 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 455 },
c35bd19a
EY
456 [FEAT_HYPERV_EAX] = {
457 .feat_names = hyperv_priv_feature_name,
458 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
459 },
460 [FEAT_HYPERV_EBX] = {
461 .feat_names = hyperv_ident_feature_name,
462 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
463 },
464 [FEAT_HYPERV_EDX] = {
465 .feat_names = hyperv_misc_feature_name,
466 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
467 },
bffd67b0
EH
468 [FEAT_SVM] = {
469 .feat_names = svm_feature_name,
470 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 471 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH
472 },
473 [FEAT_7_0_EBX] = {
474 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH
475 .cpuid_eax = 7,
476 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
477 .cpuid_reg = R_EBX,
37ce3522 478 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 479 },
f74eefe0
HH
480 [FEAT_7_0_ECX] = {
481 .feat_names = cpuid_7_0_ecx_feature_name,
482 .cpuid_eax = 7,
483 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
484 .cpuid_reg = R_ECX,
485 .tcg_features = TCG_7_0_ECX_FEATURES,
486 },
303752a9
MT
487 [FEAT_8000_0007_EDX] = {
488 .feat_names = cpuid_apm_edx_feature_name,
489 .cpuid_eax = 0x80000007,
490 .cpuid_reg = R_EDX,
491 .tcg_features = TCG_APM_FEATURES,
492 .unmigratable_flags = CPUID_APM_INVTSC,
493 },
0bb0b2d2
PB
494 [FEAT_XSAVE] = {
495 .feat_names = cpuid_xsave_feature_name,
496 .cpuid_eax = 0xd,
497 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
498 .cpuid_reg = R_EAX,
c9cfe8f9 499 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 500 },
28b8e4d0
JK
501 [FEAT_6_EAX] = {
502 .feat_names = cpuid_6_feature_name,
503 .cpuid_eax = 6, .cpuid_reg = R_EAX,
504 .tcg_features = TCG_6_EAX_FEATURES,
505 },
5ef57876
EH
506};
507
8e8aba50
EH
508typedef struct X86RegisterInfo32 {
509 /* Name of register */
510 const char *name;
511 /* QAPI enum value register */
512 X86CPURegister32 qapi_enum;
513} X86RegisterInfo32;
514
515#define REGISTER(reg) \
5d371f41 516 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 517static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH
518 REGISTER(EAX),
519 REGISTER(ECX),
520 REGISTER(EDX),
521 REGISTER(EBX),
522 REGISTER(ESP),
523 REGISTER(EBP),
524 REGISTER(ESI),
525 REGISTER(EDI),
526};
527#undef REGISTER
528
f4f1110e 529const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB
530 [XSTATE_YMM_BIT] =
531 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH
532 .offset = offsetof(X86XSaveArea, avx_state),
533 .size = sizeof(XSaveAVX) },
cfc3b074
PB
534 [XSTATE_BNDREGS_BIT] =
535 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH
536 .offset = offsetof(X86XSaveArea, bndreg_state),
537 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB
538 [XSTATE_BNDCSR_BIT] =
539 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH
540 .offset = offsetof(X86XSaveArea, bndcsr_state),
541 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB
542 [XSTATE_OPMASK_BIT] =
543 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH
544 .offset = offsetof(X86XSaveArea, opmask_state),
545 .size = sizeof(XSaveOpmask) },
cfc3b074
PB
546 [XSTATE_ZMM_Hi256_BIT] =
547 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH
548 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
549 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB
550 [XSTATE_Hi16_ZMM_BIT] =
551 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH
552 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
553 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB
554 [XSTATE_PKRU_BIT] =
555 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH
556 .offset = offsetof(X86XSaveArea, pkru_state),
557 .size = sizeof(XSavePKRU) },
2560f19f 558};
8e8aba50 559
8b4beddc
EH
560const char *get_register_name_32(unsigned int reg)
561{
31ccdde2 562 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH
563 return NULL;
564 }
8e8aba50 565 return x86_reg_info_32[reg].name;
8b4beddc
EH
566}
567
84f1b92f
EH
568/*
569 * Returns the set of feature flags that are supported and migratable by
570 * QEMU, for a given FeatureWord.
571 */
572static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
573{
574 FeatureWordInfo *wi = &feature_word_info[w];
575 uint32_t r = 0;
576 int i;
577
578 for (i = 0; i < 32; i++) {
579 uint32_t f = 1U << i;
580 /* If the feature name is unknown, it is not supported by QEMU yet */
581 if (!wi->feat_names[i]) {
582 continue;
583 }
584 /* Skip features known to QEMU, but explicitly marked as unmigratable */
585 if (wi->unmigratable_flags & f) {
586 continue;
587 }
588 r |= f;
589 }
590 return r;
591}
592
bb44e0d1
JK
593void host_cpuid(uint32_t function, uint32_t count,
594 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 595{
a1fd24af
AL
596 uint32_t vec[4];
597
598#ifdef __x86_64__
599 asm volatile("cpuid"
600 : "=a"(vec[0]), "=b"(vec[1]),
601 "=c"(vec[2]), "=d"(vec[3])
602 : "0"(function), "c"(count) : "cc");
c1f41226 603#elif defined(__i386__)
a1fd24af
AL
604 asm volatile("pusha \n\t"
605 "cpuid \n\t"
606 "mov %%eax, 0(%2) \n\t"
607 "mov %%ebx, 4(%2) \n\t"
608 "mov %%ecx, 8(%2) \n\t"
609 "mov %%edx, 12(%2) \n\t"
610 "popa"
611 : : "a"(function), "c"(count), "S"(vec)
612 : "memory", "cc");
c1f41226
EH
613#else
614 abort();
a1fd24af
AL
615#endif
616
bdde476a 617 if (eax)
a1fd24af 618 *eax = vec[0];
bdde476a 619 if (ebx)
a1fd24af 620 *ebx = vec[1];
bdde476a 621 if (ecx)
a1fd24af 622 *ecx = vec[2];
bdde476a 623 if (edx)
a1fd24af 624 *edx = vec[3];
bdde476a 625}
c6dc6f63
AP
626
627#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
628
629/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
630 * a substring. ex if !NULL points to the first char after a substring,
631 * otherwise the string is assumed to sized by a terminating nul.
632 * Return lexical ordering of *s1:*s2.
633 */
8f9d989c
CF
634static int sstrcmp(const char *s1, const char *e1,
635 const char *s2, const char *e2)
c6dc6f63
AP
636{
637 for (;;) {
638 if (!*s1 || !*s2 || *s1 != *s2)
639 return (*s1 - *s2);
640 ++s1, ++s2;
641 if (s1 == e1 && s2 == e2)
642 return (0);
643 else if (s1 == e1)
644 return (*s2);
645 else if (s2 == e2)
646 return (*s1);
647 }
648}
649
650/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
651 * '|' delimited (possibly empty) strings in which case search for a match
652 * within the alternatives proceeds left to right. Return 0 for success,
653 * non-zero otherwise.
654 */
655static int altcmp(const char *s, const char *e, const char *altstr)
656{
657 const char *p, *q;
658
659 for (q = p = altstr; ; ) {
660 while (*p && *p != '|')
661 ++p;
662 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
663 return (0);
664 if (!*p)
665 return (1);
666 else
667 q = ++p;
668 }
669}
670
671/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 672 * *pval and return true, otherwise return false
c6dc6f63 673 */
e41e0fc6
JK
674static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
675 const char **featureset)
c6dc6f63
AP
676{
677 uint32_t mask;
678 const char **ppc;
e41e0fc6 679 bool found = false;
c6dc6f63 680
e41e0fc6 681 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP
682 if (*ppc && !altcmp(s, e, *ppc)) {
683 *pval |= mask;
e41e0fc6 684 found = true;
c6dc6f63 685 }
e41e0fc6
JK
686 }
687 return found;
c6dc6f63
AP
688}
689
5ef57876 690static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH
691 FeatureWordArray words,
692 Error **errp)
c6dc6f63 693{
5ef57876
EH
694 FeatureWord w;
695 for (w = 0; w < FEATURE_WORDS; w++) {
696 FeatureWordInfo *wi = &feature_word_info[w];
697 if (wi->feat_names &&
698 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
699 break;
700 }
701 }
702 if (w == FEATURE_WORDS) {
c00c94ab 703 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 704 }
c6dc6f63
AP
705}
706
d940ee9b
EH
707/* CPU class name definitions: */
708
709#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
710#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
711
712/* Return type name for a given CPU model name
713 * Caller is responsible for freeing the returned string.
714 */
715static char *x86_cpu_type_name(const char *model_name)
716{
717 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
718}
719
500050d1
AF
720static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
721{
d940ee9b
EH
722 ObjectClass *oc;
723 char *typename;
724
500050d1
AF
725 if (cpu_model == NULL) {
726 return NULL;
727 }
728
d940ee9b
EH
729 typename = x86_cpu_type_name(cpu_model);
730 oc = object_class_by_name(typename);
731 g_free(typename);
732 return oc;
500050d1
AF
733}
734
104494ea
IM
735static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
736{
737 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
738 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
739 return g_strndup(class_name,
740 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
741}
742
d940ee9b 743struct X86CPUDefinition {
c6dc6f63
AP
744 const char *name;
745 uint32_t level;
90e4b0c3
EH
746 uint32_t xlevel;
747 uint32_t xlevel2;
99b88a17
IM
748 /* vendor is zero-terminated, 12 character ASCII string */
749 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP
750 int family;
751 int model;
752 int stepping;
0514ef2f 753 FeatureWordArray features;
c6dc6f63 754 char model_id[48];
d940ee9b 755};
c6dc6f63 756
9576de75 757static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP
758 {
759 .name = "qemu64",
3046bb5d 760 .level = 0xd,
99b88a17 761 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 762 .family = 6,
f8e6a11a 763 .model = 6,
c6dc6f63 764 .stepping = 3,
0514ef2f 765 .features[FEAT_1_EDX] =
27861ecc 766 PPRO_FEATURES |
c6dc6f63 767 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 768 CPUID_PSE36,
0514ef2f 769 .features[FEAT_1_ECX] =
6aa91e4a 770 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 771 .features[FEAT_8000_0001_EDX] =
c6dc6f63 772 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 773 .features[FEAT_8000_0001_ECX] =
71195672 774 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 775 .xlevel = 0x8000000A,
9cf2cc3d 776 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP
777 },
778 {
779 .name = "phenom",
780 .level = 5,
99b88a17 781 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP
782 .family = 16,
783 .model = 2,
784 .stepping = 3,
b9fc20bc 785 /* Missing: CPUID_HT */
0514ef2f 786 .features[FEAT_1_EDX] =
27861ecc 787 PPRO_FEATURES |
c6dc6f63 788 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 789 CPUID_PSE36 | CPUID_VME,
0514ef2f 790 .features[FEAT_1_ECX] =
27861ecc 791 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 792 CPUID_EXT_POPCNT,
0514ef2f 793 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP
794 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
795 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 796 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP
797 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
798 CPUID_EXT3_CR8LEG,
799 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
800 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 801 .features[FEAT_8000_0001_ECX] =
27861ecc 802 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 803 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 804 /* Missing: CPUID_SVM_LBRV */
0514ef2f 805 .features[FEAT_SVM] =
b9fc20bc 806 CPUID_SVM_NPT,
c6dc6f63
AP
807 .xlevel = 0x8000001A,
808 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
809 },
810 {
811 .name = "core2duo",
812 .level = 10,
99b88a17 813 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
814 .family = 6,
815 .model = 15,
816 .stepping = 11,
b9fc20bc 817 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 818 .features[FEAT_1_EDX] =
27861ecc 819 PPRO_FEATURES |
c6dc6f63 820 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH
821 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
822 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 823 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 824 .features[FEAT_1_ECX] =
27861ecc 825 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 826 CPUID_EXT_CX16,
0514ef2f 827 .features[FEAT_8000_0001_EDX] =
27861ecc 828 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 829 .features[FEAT_8000_0001_ECX] =
27861ecc 830 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP
831 .xlevel = 0x80000008,
832 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
833 },
834 {
835 .name = "kvm64",
3046bb5d 836 .level = 0xd,
99b88a17 837 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
838 .family = 15,
839 .model = 6,
840 .stepping = 1,
b3a4f0b1 841 /* Missing: CPUID_HT */
0514ef2f 842 .features[FEAT_1_EDX] =
b3a4f0b1 843 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP
844 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
845 CPUID_PSE36,
846 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 847 .features[FEAT_1_ECX] =
27861ecc 848 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 849 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 850 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP
851 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
852 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
853 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
854 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
855 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 856 .features[FEAT_8000_0001_ECX] =
27861ecc 857 0,
c6dc6f63
AP
858 .xlevel = 0x80000008,
859 .model_id = "Common KVM processor"
860 },
c6dc6f63
AP
861 {
862 .name = "qemu32",
863 .level = 4,
99b88a17 864 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 865 .family = 6,
f8e6a11a 866 .model = 6,
c6dc6f63 867 .stepping = 3,
0514ef2f 868 .features[FEAT_1_EDX] =
27861ecc 869 PPRO_FEATURES,
0514ef2f 870 .features[FEAT_1_ECX] =
6aa91e4a 871 CPUID_EXT_SSE3,
58012d66 872 .xlevel = 0x80000004,
9cf2cc3d 873 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 874 },
eafaf1e5
AP
875 {
876 .name = "kvm32",
877 .level = 5,
99b88a17 878 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP
879 .family = 15,
880 .model = 6,
881 .stepping = 1,
0514ef2f 882 .features[FEAT_1_EDX] =
b3a4f0b1 883 PPRO_FEATURES | CPUID_VME |
eafaf1e5 884 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 885 .features[FEAT_1_ECX] =
27861ecc 886 CPUID_EXT_SSE3,
0514ef2f 887 .features[FEAT_8000_0001_ECX] =
27861ecc 888 0,
eafaf1e5
AP
889 .xlevel = 0x80000008,
890 .model_id = "Common 32-bit KVM processor"
891 },
c6dc6f63
AP
892 {
893 .name = "coreduo",
894 .level = 10,
99b88a17 895 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
896 .family = 6,
897 .model = 14,
898 .stepping = 8,
b9fc20bc 899 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 900 .features[FEAT_1_EDX] =
27861ecc 901 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH
902 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
903 CPUID_SS,
904 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 905 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 906 .features[FEAT_1_ECX] =
e93abc14 907 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 908 .features[FEAT_8000_0001_EDX] =
27861ecc 909 CPUID_EXT2_NX,
c6dc6f63
AP
910 .xlevel = 0x80000008,
911 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
912 },
913 {
914 .name = "486",
58012d66 915 .level = 1,
99b88a17 916 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 917 .family = 4,
b2a856d9 918 .model = 8,
c6dc6f63 919 .stepping = 0,
0514ef2f 920 .features[FEAT_1_EDX] =
27861ecc 921 I486_FEATURES,
c6dc6f63
AP
922 .xlevel = 0,
923 },
924 {
925 .name = "pentium",
926 .level = 1,
99b88a17 927 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
928 .family = 5,
929 .model = 4,
930 .stepping = 3,
0514ef2f 931 .features[FEAT_1_EDX] =
27861ecc 932 PENTIUM_FEATURES,
c6dc6f63
AP
933 .xlevel = 0,
934 },
935 {
936 .name = "pentium2",
937 .level = 2,
99b88a17 938 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
939 .family = 6,
940 .model = 5,
941 .stepping = 2,
0514ef2f 942 .features[FEAT_1_EDX] =
27861ecc 943 PENTIUM2_FEATURES,
c6dc6f63
AP
944 .xlevel = 0,
945 },
946 {
947 .name = "pentium3",
3046bb5d 948 .level = 3,
99b88a17 949 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
950 .family = 6,
951 .model = 7,
952 .stepping = 3,
0514ef2f 953 .features[FEAT_1_EDX] =
27861ecc 954 PENTIUM3_FEATURES,
c6dc6f63
AP
955 .xlevel = 0,
956 },
957 {
958 .name = "athlon",
959 .level = 2,
99b88a17 960 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP
961 .family = 6,
962 .model = 2,
963 .stepping = 3,
0514ef2f 964 .features[FEAT_1_EDX] =
27861ecc 965 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 966 CPUID_MCA,
0514ef2f 967 .features[FEAT_8000_0001_EDX] =
60032ac0 968 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 969 .xlevel = 0x80000008,
9cf2cc3d 970 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP
971 },
972 {
973 .name = "n270",
3046bb5d 974 .level = 10,
99b88a17 975 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP
976 .family = 6,
977 .model = 28,
978 .stepping = 2,
b9fc20bc 979 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 980 .features[FEAT_1_EDX] =
27861ecc 981 PPRO_FEATURES |
b9fc20bc
EH
982 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
983 CPUID_ACPI | CPUID_SS,
c6dc6f63 984 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH
985 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
986 * CPUID_EXT_XTPR */
0514ef2f 987 .features[FEAT_1_ECX] =
27861ecc 988 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 989 CPUID_EXT_MOVBE,
0514ef2f 990 .features[FEAT_8000_0001_EDX] =
60032ac0 991 CPUID_EXT2_NX,
0514ef2f 992 .features[FEAT_8000_0001_ECX] =
27861ecc 993 CPUID_EXT3_LAHF_LM,
3046bb5d 994 .xlevel = 0x80000008,
c6dc6f63
AP
995 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
996 },
3eca4642
EH
997 {
998 .name = "Conroe",
3046bb5d 999 .level = 10,
99b88a17 1000 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1001 .family = 6,
ffce9ebb 1002 .model = 15,
3eca4642 1003 .stepping = 3,
0514ef2f 1004 .features[FEAT_1_EDX] =
b3a4f0b1 1005 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1006 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1007 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1008 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1009 CPUID_DE | CPUID_FP87,
0514ef2f 1010 .features[FEAT_1_ECX] =
27861ecc 1011 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1014 .features[FEAT_8000_0001_ECX] =
27861ecc 1015 CPUID_EXT3_LAHF_LM,
3046bb5d 1016 .xlevel = 0x80000008,
3eca4642
EH
1017 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1018 },
1019 {
1020 .name = "Penryn",
3046bb5d 1021 .level = 10,
99b88a17 1022 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1023 .family = 6,
ffce9ebb 1024 .model = 23,
3eca4642 1025 .stepping = 3,
0514ef2f 1026 .features[FEAT_1_EDX] =
b3a4f0b1 1027 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1028 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1029 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1030 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1031 CPUID_DE | CPUID_FP87,
0514ef2f 1032 .features[FEAT_1_ECX] =
27861ecc 1033 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1034 CPUID_EXT_SSE3,
0514ef2f 1035 .features[FEAT_8000_0001_EDX] =
27861ecc 1036 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
3046bb5d 1039 .xlevel = 0x80000008,
3eca4642
EH
1040 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1041 },
1042 {
1043 .name = "Nehalem",
3046bb5d 1044 .level = 11,
99b88a17 1045 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1046 .family = 6,
ffce9ebb 1047 .model = 26,
3eca4642 1048 .stepping = 3,
0514ef2f 1049 .features[FEAT_1_EDX] =
b3a4f0b1 1050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
0514ef2f 1055 .features[FEAT_1_ECX] =
27861ecc 1056 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1057 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1058 .features[FEAT_8000_0001_EDX] =
27861ecc 1059 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1060 .features[FEAT_8000_0001_ECX] =
27861ecc 1061 CPUID_EXT3_LAHF_LM,
3046bb5d 1062 .xlevel = 0x80000008,
3eca4642
EH
1063 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1064 },
1065 {
1066 .name = "Westmere",
1067 .level = 11,
99b88a17 1068 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH
1069 .family = 6,
1070 .model = 44,
1071 .stepping = 1,
0514ef2f 1072 .features[FEAT_1_EDX] =
b3a4f0b1 1073 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1074 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1075 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1076 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1077 CPUID_DE | CPUID_FP87,
0514ef2f 1078 .features[FEAT_1_ECX] =
27861ecc 1079 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH
1080 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1081 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1082 .features[FEAT_8000_0001_EDX] =
27861ecc 1083 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1084 .features[FEAT_8000_0001_ECX] =
27861ecc 1085 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK
1086 .features[FEAT_6_EAX] =
1087 CPUID_6_EAX_ARAT,
3046bb5d 1088 .xlevel = 0x80000008,
3eca4642
EH
1089 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1090 },
1091 {
1092 .name = "SandyBridge",
1093 .level = 0xd,
99b88a17 1094 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH
1095 .family = 6,
1096 .model = 42,
1097 .stepping = 1,
0514ef2f 1098 .features[FEAT_1_EDX] =
b3a4f0b1 1099 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1100 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1101 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1102 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1103 CPUID_DE | CPUID_FP87,
0514ef2f 1104 .features[FEAT_1_ECX] =
27861ecc 1105 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH
1106 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1107 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1108 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1109 CPUID_EXT_SSE3,
0514ef2f 1110 .features[FEAT_8000_0001_EDX] =
27861ecc 1111 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1112 CPUID_EXT2_SYSCALL,
0514ef2f 1113 .features[FEAT_8000_0001_ECX] =
27861ecc 1114 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB
1115 .features[FEAT_XSAVE] =
1116 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK
1117 .features[FEAT_6_EAX] =
1118 CPUID_6_EAX_ARAT,
3046bb5d 1119 .xlevel = 0x80000008,
3eca4642
EH
1120 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1121 },
2f9ac42a
PB
1122 {
1123 .name = "IvyBridge",
1124 .level = 0xd,
1125 .vendor = CPUID_VENDOR_INTEL,
1126 .family = 6,
1127 .model = 58,
1128 .stepping = 9,
1129 .features[FEAT_1_EDX] =
1130 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1131 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1132 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1133 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1134 CPUID_DE | CPUID_FP87,
1135 .features[FEAT_1_ECX] =
1136 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1137 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1138 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1139 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1140 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1141 .features[FEAT_7_0_EBX] =
1142 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1143 CPUID_7_0_EBX_ERMS,
1144 .features[FEAT_8000_0001_EDX] =
1145 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1146 CPUID_EXT2_SYSCALL,
1147 .features[FEAT_8000_0001_ECX] =
1148 CPUID_EXT3_LAHF_LM,
1149 .features[FEAT_XSAVE] =
1150 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK
1151 .features[FEAT_6_EAX] =
1152 CPUID_6_EAX_ARAT,
3046bb5d 1153 .xlevel = 0x80000008,
2f9ac42a
PB
1154 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1155 },
37507094 1156 {
a356850b
EH
1157 .name = "Haswell-noTSX",
1158 .level = 0xd,
1159 .vendor = CPUID_VENDOR_INTEL,
1160 .family = 6,
1161 .model = 60,
1162 .stepping = 1,
1163 .features[FEAT_1_EDX] =
1164 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1165 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1166 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1167 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1168 CPUID_DE | CPUID_FP87,
1169 .features[FEAT_1_ECX] =
1170 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1171 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1172 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1173 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1174 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1175 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1176 .features[FEAT_8000_0001_EDX] =
1177 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1178 CPUID_EXT2_SYSCALL,
1179 .features[FEAT_8000_0001_ECX] =
becb6667 1180 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH
1181 .features[FEAT_7_0_EBX] =
1182 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1183 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1184 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1185 .features[FEAT_XSAVE] =
1186 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK
1187 .features[FEAT_6_EAX] =
1188 CPUID_6_EAX_ARAT,
3046bb5d 1189 .xlevel = 0x80000008,
a356850b
EH
1190 .model_id = "Intel Core Processor (Haswell, no TSX)",
1191 }, {
37507094
EH
1192 .name = "Haswell",
1193 .level = 0xd,
99b88a17 1194 .vendor = CPUID_VENDOR_INTEL,
37507094
EH
1195 .family = 6,
1196 .model = 60,
1197 .stepping = 1,
0514ef2f 1198 .features[FEAT_1_EDX] =
b3a4f0b1 1199 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1200 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1201 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1202 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1203 CPUID_DE | CPUID_FP87,
0514ef2f 1204 .features[FEAT_1_ECX] =
27861ecc 1205 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH
1206 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1207 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1208 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1209 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1210 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1211 .features[FEAT_8000_0001_EDX] =
27861ecc 1212 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1213 CPUID_EXT2_SYSCALL,
0514ef2f 1214 .features[FEAT_8000_0001_ECX] =
becb6667 1215 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1216 .features[FEAT_7_0_EBX] =
27861ecc 1217 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH
1218 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1219 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1220 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB
1221 .features[FEAT_XSAVE] =
1222 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK
1223 .features[FEAT_6_EAX] =
1224 CPUID_6_EAX_ARAT,
3046bb5d 1225 .xlevel = 0x80000008,
37507094
EH
1226 .model_id = "Intel Core Processor (Haswell)",
1227 },
a356850b
EH
1228 {
1229 .name = "Broadwell-noTSX",
1230 .level = 0xd,
1231 .vendor = CPUID_VENDOR_INTEL,
1232 .family = 6,
1233 .model = 61,
1234 .stepping = 2,
1235 .features[FEAT_1_EDX] =
1236 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1237 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1238 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1239 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1240 CPUID_DE | CPUID_FP87,
1241 .features[FEAT_1_ECX] =
1242 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1243 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1244 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1245 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1246 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1247 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1248 .features[FEAT_8000_0001_EDX] =
1249 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1250 CPUID_EXT2_SYSCALL,
1251 .features[FEAT_8000_0001_ECX] =
becb6667 1252 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH
1253 .features[FEAT_7_0_EBX] =
1254 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1255 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1256 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1257 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1258 CPUID_7_0_EBX_SMAP,
1259 .features[FEAT_XSAVE] =
1260 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK
1261 .features[FEAT_6_EAX] =
1262 CPUID_6_EAX_ARAT,
3046bb5d 1263 .xlevel = 0x80000008,
a356850b
EH
1264 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1265 },
ece01354
EH
1266 {
1267 .name = "Broadwell",
1268 .level = 0xd,
1269 .vendor = CPUID_VENDOR_INTEL,
1270 .family = 6,
1271 .model = 61,
1272 .stepping = 2,
1273 .features[FEAT_1_EDX] =
b3a4f0b1 1274 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH
1275 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1276 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1277 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1278 CPUID_DE | CPUID_FP87,
1279 .features[FEAT_1_ECX] =
1280 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1281 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1282 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1283 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1284 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1285 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH
1286 .features[FEAT_8000_0001_EDX] =
1287 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1288 CPUID_EXT2_SYSCALL,
1289 .features[FEAT_8000_0001_ECX] =
becb6667 1290 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH
1291 .features[FEAT_7_0_EBX] =
1292 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1293 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1294 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1295 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1296 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB
1297 .features[FEAT_XSAVE] =
1298 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK
1299 .features[FEAT_6_EAX] =
1300 CPUID_6_EAX_ARAT,
3046bb5d 1301 .xlevel = 0x80000008,
ece01354
EH
1302 .model_id = "Intel Core Processor (Broadwell)",
1303 },
f6f949e9
EH
1304 {
1305 .name = "Skylake-Client",
1306 .level = 0xd,
1307 .vendor = CPUID_VENDOR_INTEL,
1308 .family = 6,
1309 .model = 94,
1310 .stepping = 3,
1311 .features[FEAT_1_EDX] =
1312 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1313 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1314 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1315 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1316 CPUID_DE | CPUID_FP87,
1317 .features[FEAT_1_ECX] =
1318 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1319 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1320 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1321 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1322 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1323 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1324 .features[FEAT_8000_0001_EDX] =
1325 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1326 CPUID_EXT2_SYSCALL,
1327 .features[FEAT_8000_0001_ECX] =
1328 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1329 .features[FEAT_7_0_EBX] =
1330 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1331 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1332 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1333 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1334 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1335 /* Missing: XSAVES (not supported by some Linux versions,
1336 * including v4.1 to v4.6).
1337 * KVM doesn't yet expose any XSAVES state save component,
1338 * and the only one defined in Skylake (processor tracing)
1339 * probably will block migration anyway.
1340 */
1341 .features[FEAT_XSAVE] =
1342 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1343 CPUID_XSAVE_XGETBV1,
1344 .features[FEAT_6_EAX] =
1345 CPUID_6_EAX_ARAT,
1346 .xlevel = 0x80000008,
1347 .model_id = "Intel Core Processor (Skylake)",
1348 },
3eca4642
EH
1349 {
1350 .name = "Opteron_G1",
1351 .level = 5,
99b88a17 1352 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
1353 .family = 15,
1354 .model = 6,
1355 .stepping = 1,
0514ef2f 1356 .features[FEAT_1_EDX] =
b3a4f0b1 1357 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1358 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1359 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1360 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1361 CPUID_DE | CPUID_FP87,
0514ef2f 1362 .features[FEAT_1_ECX] =
27861ecc 1363 CPUID_EXT_SSE3,
0514ef2f 1364 .features[FEAT_8000_0001_EDX] =
27861ecc 1365 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH
1366 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1367 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1368 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1369 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1370 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH
1371 .xlevel = 0x80000008,
1372 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1373 },
1374 {
1375 .name = "Opteron_G2",
1376 .level = 5,
99b88a17 1377 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
1378 .family = 15,
1379 .model = 6,
1380 .stepping = 1,
0514ef2f 1381 .features[FEAT_1_EDX] =
b3a4f0b1 1382 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1383 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1384 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1385 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1386 CPUID_DE | CPUID_FP87,
0514ef2f 1387 .features[FEAT_1_ECX] =
27861ecc 1388 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1389 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1390 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1391 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH
1392 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1393 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1394 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1395 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1396 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1397 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1398 .features[FEAT_8000_0001_ECX] =
27861ecc 1399 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH
1400 .xlevel = 0x80000008,
1401 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1402 },
1403 {
1404 .name = "Opteron_G3",
1405 .level = 5,
99b88a17 1406 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
1407 .family = 15,
1408 .model = 6,
1409 .stepping = 1,
0514ef2f 1410 .features[FEAT_1_EDX] =
b3a4f0b1 1411 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1412 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1413 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1414 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1415 CPUID_DE | CPUID_FP87,
0514ef2f 1416 .features[FEAT_1_ECX] =
27861ecc 1417 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1418 CPUID_EXT_SSE3,
33b5e8c0 1419 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1420 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1421 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH
1422 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1423 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1424 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1425 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1426 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1427 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1428 .features[FEAT_8000_0001_ECX] =
27861ecc 1429 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1430 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH
1431 .xlevel = 0x80000008,
1432 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1433 },
1434 {
1435 .name = "Opteron_G4",
1436 .level = 0xd,
99b88a17 1437 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH
1438 .family = 21,
1439 .model = 1,
1440 .stepping = 2,
0514ef2f 1441 .features[FEAT_1_EDX] =
b3a4f0b1 1442 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1443 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1444 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1445 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1446 CPUID_DE | CPUID_FP87,
0514ef2f 1447 .features[FEAT_1_ECX] =
27861ecc 1448 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH
1449 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1450 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1451 CPUID_EXT_SSE3,
33b5e8c0 1452 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1453 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1454 CPUID_EXT2_LM |
b3fb3a20
EH
1455 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1456 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1457 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1458 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1459 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1460 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1461 .features[FEAT_8000_0001_ECX] =
27861ecc 1462 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH
1463 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1464 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1465 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1466 /* no xsaveopt! */
3eca4642
EH
1467 .xlevel = 0x8000001A,
1468 .model_id = "AMD Opteron 62xx class CPU",
1469 },
021941b9
AP
1470 {
1471 .name = "Opteron_G5",
1472 .level = 0xd,
99b88a17 1473 .vendor = CPUID_VENDOR_AMD,
021941b9
AP
1474 .family = 21,
1475 .model = 2,
1476 .stepping = 0,
0514ef2f 1477 .features[FEAT_1_EDX] =
b3a4f0b1 1478 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH
1479 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1480 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1481 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1482 CPUID_DE | CPUID_FP87,
0514ef2f 1483 .features[FEAT_1_ECX] =
27861ecc 1484 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH
1485 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1486 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1487 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1488 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1489 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1490 CPUID_EXT2_LM |
b3fb3a20
EH
1491 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1492 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1493 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1494 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1495 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1496 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1497 .features[FEAT_8000_0001_ECX] =
27861ecc 1498 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH
1499 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1500 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1501 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1502 /* no xsaveopt! */
021941b9
AP
1503 .xlevel = 0x8000001A,
1504 .model_id = "AMD Opteron 63xx class CPU",
1505 },
c6dc6f63
AP
1506};
1507
5114e842
EH
1508typedef struct PropValue {
1509 const char *prop, *value;
1510} PropValue;
1511
1512/* KVM-specific features that are automatically added/removed
1513 * from all CPU models when KVM is enabled.
1514 */
1515static PropValue kvm_default_props[] = {
1516 { "kvmclock", "on" },
1517 { "kvm-nopiodelay", "on" },
1518 { "kvm-asyncpf", "on" },
1519 { "kvm-steal-time", "on" },
1520 { "kvm-pv-eoi", "on" },
1521 { "kvmclock-stable-bit", "on" },
1522 { "x2apic", "on" },
1523 { "acpi", "off" },
1524 { "monitor", "off" },
1525 { "svm", "off" },
1526 { NULL, NULL },
1527};
1528
1529void x86_cpu_change_kvm_default(const char *prop, const char *value)
1530{
1531 PropValue *pv;
1532 for (pv = kvm_default_props; pv->prop; pv++) {
1533 if (!strcmp(pv->prop, prop)) {
1534 pv->value = value;
1535 break;
1536 }
1537 }
1538
1539 /* It is valid to call this function only for properties that
1540 * are already present in the kvm_default_props table.
1541 */
1542 assert(pv->prop);
1543}
1544
4d1b279b
EH
1545static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1546 bool migratable_only);
1547
d940ee9b
EH
1548#ifdef CONFIG_KVM
1549
40bfe48f
HZ
1550static bool lmce_supported(void)
1551{
1552 uint64_t mce_cap;
1553
1554 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1555 return false;
1556 }
1557
1558 return !!(mce_cap & MCG_LMCE_P);
1559}
1560
c6dc6f63
AP
1561static int cpu_x86_fill_model_id(char *str)
1562{
1563 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1564 int i;
1565
1566 for (i = 0; i < 3; i++) {
1567 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1568 memcpy(str + i * 16 + 0, &eax, 4);
1569 memcpy(str + i * 16 + 4, &ebx, 4);
1570 memcpy(str + i * 16 + 8, &ecx, 4);
1571 memcpy(str + i * 16 + 12, &edx, 4);
1572 }
1573 return 0;
1574}
1575
d940ee9b
EH
1576static X86CPUDefinition host_cpudef;
1577
84f1b92f 1578static Property host_x86_cpu_properties[] = {
120eee7d 1579 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1580 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH
1581 DEFINE_PROP_END_OF_LIST()
1582};
1583
d940ee9b 1584/* class_init for the "host" CPU model
6e746f30 1585 *
d940ee9b 1586 * This function may be called before KVM is initialized.
6e746f30 1587 */
d940ee9b 1588static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1589{
84f1b92f 1590 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1591 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP
1592 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1593
d940ee9b 1594 xcc->kvm_required = true;
6e746f30 1595
c6dc6f63 1596 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1597 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP
1598
1599 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH
1600 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1601 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1602 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1603
d940ee9b 1604 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1605
d940ee9b 1606 xcc->cpu_def = &host_cpudef;
d940ee9b
EH
1607
1608 /* level, xlevel, xlevel2, and the feature words are initialized on
1609 * instance_init, because they require KVM to be initialized.
1610 */
84f1b92f
EH
1611
1612 dc->props = host_x86_cpu_properties;
4c315c27
MA
1613 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1614 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH
1615}
1616
1617static void host_x86_cpu_initfn(Object *obj)
1618{
1619 X86CPU *cpu = X86_CPU(obj);
1620 CPUX86State *env = &cpu->env;
1621 KVMState *s = kvm_state;
d940ee9b 1622
4d1b279b
EH
1623 /* We can't fill the features array here because we don't know yet if
1624 * "migratable" is true or false.
1625 */
1626 cpu->host_features = true;
1627
104494ea 1628 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010
EH
1629 if (kvm_enabled()) {
1630 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1631 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1632 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ
1633
1634 if (lmce_supported()) {
1635 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1636 }
e4356010 1637 }
2a573259 1638
d940ee9b 1639 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP
1640}
1641
d940ee9b
EH
1642static const TypeInfo host_x86_cpu_type_info = {
1643 .name = X86_CPU_TYPE_NAME("host"),
1644 .parent = TYPE_X86_CPU,
1645 .instance_init = host_x86_cpu_initfn,
1646 .class_init = host_x86_cpu_class_init,
1647};
1648
1649#endif
1650
8459e396 1651static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1652{
8459e396 1653 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP
1654 int i;
1655
857aee33 1656 for (i = 0; i < 32; ++i) {
72370dc1 1657 if ((1UL << i) & mask) {
bffd67b0 1658 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1659 assert(reg);
fefb41bf 1660 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1661 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1662 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH
1663 f->cpuid_eax, reg,
1664 f->feat_names[i] ? "." : "",
1665 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1666 }
857aee33 1667 }
c6dc6f63
AP
1668}
1669
d7bce999
EB
1670static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1671 const char *name, void *opaque,
1672 Error **errp)
95b8519d
AF
1673{
1674 X86CPU *cpu = X86_CPU(obj);
1675 CPUX86State *env = &cpu->env;
1676 int64_t value;
1677
1678 value = (env->cpuid_version >> 8) & 0xf;
1679 if (value == 0xf) {
1680 value += (env->cpuid_version >> 20) & 0xff;
1681 }
51e72bc1 1682 visit_type_int(v, name, &value, errp);
95b8519d
AF
1683}
1684
d7bce999
EB
1685static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1686 const char *name, void *opaque,
1687 Error **errp)
ed5e1ec3 1688{
71ad61d3
AF
1689 X86CPU *cpu = X86_CPU(obj);
1690 CPUX86State *env = &cpu->env;
1691 const int64_t min = 0;
1692 const int64_t max = 0xff + 0xf;
65cd9064 1693 Error *local_err = NULL;
71ad61d3
AF
1694 int64_t value;
1695
51e72bc1 1696 visit_type_int(v, name, &value, &local_err);
65cd9064
MA
1697 if (local_err) {
1698 error_propagate(errp, local_err);
71ad61d3
AF
1699 return;
1700 }
1701 if (value < min || value > max) {
c6bd8c70
MA
1702 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1703 name ? name : "null", value, min, max);
71ad61d3
AF
1704 return;
1705 }
1706
ed5e1ec3 1707 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF
1708 if (value > 0x0f) {
1709 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1710 } else {
71ad61d3 1711 env->cpuid_version |= value << 8;
ed5e1ec3
AF
1712 }
1713}
1714
d7bce999
EB
1715static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1716 const char *name, void *opaque,
1717 Error **errp)
67e30c83
AF
1718{
1719 X86CPU *cpu = X86_CPU(obj);
1720 CPUX86State *env = &cpu->env;
1721 int64_t value;
1722
1723 value = (env->cpuid_version >> 4) & 0xf;
1724 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1725 visit_type_int(v, name, &value, errp);
67e30c83
AF
1726}
1727
d7bce999
EB
1728static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1729 const char *name, void *opaque,
1730 Error **errp)
b0704cbd 1731{
c5291a4f
AF
1732 X86CPU *cpu = X86_CPU(obj);
1733 CPUX86State *env = &cpu->env;
1734 const int64_t min = 0;
1735 const int64_t max = 0xff;
65cd9064 1736 Error *local_err = NULL;
c5291a4f
AF
1737 int64_t value;
1738
51e72bc1 1739 visit_type_int(v, name, &value, &local_err);
65cd9064
MA
1740 if (local_err) {
1741 error_propagate(errp, local_err);
c5291a4f
AF
1742 return;
1743 }
1744 if (value < min || value > max) {
c6bd8c70
MA
1745 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1746 name ? name : "null", value, min, max);
c5291a4f
AF
1747 return;
1748 }
1749
b0704cbd 1750 env->cpuid_version &= ~0xf00f0;
c5291a4f 1751 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF
1752}
1753
35112e41 1754static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1755 const char *name, void *opaque,
35112e41
AF
1756 Error **errp)
1757{
1758 X86CPU *cpu = X86_CPU(obj);
1759 CPUX86State *env = &cpu->env;
1760 int64_t value;
1761
1762 value = env->cpuid_version & 0xf;
51e72bc1 1763 visit_type_int(v, name, &value, errp);
35112e41
AF
1764}
1765
036e2222 1766static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1767 const char *name, void *opaque,
036e2222 1768 Error **errp)
38c3dc46 1769{
036e2222
AF
1770 X86CPU *cpu = X86_CPU(obj);
1771 CPUX86State *env = &cpu->env;
1772 const int64_t min = 0;
1773 const int64_t max = 0xf;
65cd9064 1774 Error *local_err = NULL;
036e2222
AF
1775 int64_t value;
1776
51e72bc1 1777 visit_type_int(v, name, &value, &local_err);
65cd9064
MA
1778 if (local_err) {
1779 error_propagate(errp, local_err);
036e2222
AF
1780 return;
1781 }
1782 if (value < min || value > max) {
c6bd8c70
MA
1783 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1784 name ? name : "null", value, min, max);
036e2222
AF
1785 return;
1786 }
1787
38c3dc46 1788 env->cpuid_version &= ~0xf;
036e2222 1789 env->cpuid_version |= value & 0xf;
38c3dc46
AF
1790}
1791
d480e1af
AF
1792static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1793{
1794 X86CPU *cpu = X86_CPU(obj);
1795 CPUX86State *env = &cpu->env;
1796 char *value;
d480e1af 1797
e42a92ae 1798 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM
1799 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1800 env->cpuid_vendor3);
d480e1af
AF
1801 return value;
1802}
1803
1804static void x86_cpuid_set_vendor(Object *obj, const char *value,
1805 Error **errp)
1806{
1807 X86CPU *cpu = X86_CPU(obj);
1808 CPUX86State *env = &cpu->env;
1809 int i;
1810
9df694ee 1811 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1812 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF
1813 return;
1814 }
1815
1816 env->cpuid_vendor1 = 0;
1817 env->cpuid_vendor2 = 0;
1818 env->cpuid_vendor3 = 0;
1819 for (i = 0; i < 4; i++) {
1820 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1821 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1822 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1823 }
d480e1af
AF
1824}
1825
63e886eb
AF
1826static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1827{
1828 X86CPU *cpu = X86_CPU(obj);
1829 CPUX86State *env = &cpu->env;
1830 char *value;
1831 int i;
1832
1833 value = g_malloc(48 + 1);
1834 for (i = 0; i < 48; i++) {
1835 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1836 }
1837 value[48] = '\0';
1838 return value;
1839}
1840
938d4c25
AF
1841static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1842 Error **errp)
dcce6675 1843{
938d4c25
AF
1844 X86CPU *cpu = X86_CPU(obj);
1845 CPUX86State *env = &cpu->env;
dcce6675
AF
1846 int c, len, i;
1847
1848 if (model_id == NULL) {
1849 model_id = "";
1850 }
1851 len = strlen(model_id);
d0a6acf4 1852 memset(env->cpuid_model, 0, 48);
dcce6675
AF
1853 for (i = 0; i < 48; i++) {
1854 if (i >= len) {
1855 c = '\0';
1856 } else {
1857 c = (uint8_t)model_id[i];
1858 }
1859 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1860 }
1861}
1862
d7bce999
EB
1863static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1864 void *opaque, Error **errp)
89e48965
AF
1865{
1866 X86CPU *cpu = X86_CPU(obj);
1867 int64_t value;
1868
1869 value = cpu->env.tsc_khz * 1000;
51e72bc1 1870 visit_type_int(v, name, &value, errp);
89e48965
AF
1871}
1872
d7bce999
EB
1873static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1874 void *opaque, Error **errp)
89e48965
AF
1875{
1876 X86CPU *cpu = X86_CPU(obj);
1877 const int64_t min = 0;
2e84849a 1878 const int64_t max = INT64_MAX;
65cd9064 1879 Error *local_err = NULL;
89e48965
AF
1880 int64_t value;
1881
51e72bc1 1882 visit_type_int(v, name, &value, &local_err);
65cd9064
MA
1883 if (local_err) {
1884 error_propagate(errp, local_err);
89e48965
AF
1885 return;
1886 }
1887 if (value < min || value > max) {
c6bd8c70
MA
1888 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1889 name ? name : "null", value, min, max);
89e48965
AF
1890 return;
1891 }
1892
36f96c4b 1893 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF
1894}
1895
d7bce999
EB
1896static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, const char *name,
1897 void *opaque, Error **errp)
31050930
IM
1898{
1899 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1900 int64_t value = cpu->apic_id;
31050930 1901
51e72bc1 1902 visit_type_int(v, name, &value, errp);
31050930
IM
1903}
1904
d7bce999
EB
1905static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, const char *name,
1906 void *opaque, Error **errp)
31050930
IM
1907{
1908 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1909 DeviceState *dev = DEVICE(obj);
31050930
IM
1910 const int64_t min = 0;
1911 const int64_t max = UINT32_MAX;
1912 Error *error = NULL;
1913 int64_t value;
1914
8d6d4980
IM
1915 if (dev->realized) {
1916 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1917 "it was realized", name, object_get_typename(obj));
1918 return;
1919 }
1920
51e72bc1 1921 visit_type_int(v, name, &value, &error);
31050930
IM
1922 if (error) {
1923 error_propagate(errp, error);
1924 return;
1925 }
1926 if (value < min || value > max) {
1927 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1928 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1929 object_get_typename(obj), name, value, min, max);
1930 return;
1931 }
1932
7e72a45c 1933 if ((value != cpu->apic_id) && cpu_exists(value)) {
31050930
IM
1934 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1935 return;
1936 }
7e72a45c 1937 cpu->apic_id = value;
31050930
IM
1938}
1939
7e5292b5 1940/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB
1941static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1942 const char *name, void *opaque,
1943 Error **errp)
8e8aba50 1944{
7e5292b5 1945 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1946 FeatureWord w;
8e8aba50
EH
1947 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1948 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1949 X86CPUFeatureWordInfoList *list = NULL;
1950
1951 for (w = 0; w < FEATURE_WORDS; w++) {
1952 FeatureWordInfo *wi = &feature_word_info[w];
1953 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1954 qwi->cpuid_input_eax = wi->cpuid_eax;
1955 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1956 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1957 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1958 qwi->features = array[w];
8e8aba50
EH
1959
1960 /* List will be in reverse order, but order shouldn't matter */
1961 list_entries[w].next = list;
1962 list_entries[w].value = &word_infos[w];
1963 list = &list_entries[w];
1964 }
1965
6b62d961 1966 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH
1967}
1968
d7bce999
EB
1969static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1970 void *opaque, Error **errp)
c8f0f88e
IM
1971{
1972 X86CPU *cpu = X86_CPU(obj);
1973 int64_t value = cpu->hyperv_spinlock_attempts;
1974
51e72bc1 1975 visit_type_int(v, name, &value, errp);
c8f0f88e
IM
1976}
1977
d7bce999
EB
1978static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1979 void *opaque, Error **errp)
c8f0f88e
IM
1980{
1981 const int64_t min = 0xFFF;
1982 const int64_t max = UINT_MAX;
1983 X86CPU *cpu = X86_CPU(obj);
1984 Error *err = NULL;
1985 int64_t value;
1986
51e72bc1 1987 visit_type_int(v, name, &value, &err);
c8f0f88e
IM
1988 if (err) {
1989 error_propagate(errp, err);
1990 return;
1991 }
1992
1993 if (value < min || value > max) {
1994 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1995 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1996 object_get_typename(obj), name ? name : "null",
1997 value, min, max);
c8f0f88e
IM
1998 return;
1999 }
2000 cpu->hyperv_spinlock_attempts = value;
2001}
2002
2003static PropertyInfo qdev_prop_spinlocks = {
2004 .name = "int",
2005 .get = x86_get_hv_spinlocks,
2006 .set = x86_set_hv_spinlocks,
2007};
2008
72ac2e87
IM
2009/* Convert all '_' in a feature string option name to '-', to make feature
2010 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2011 */
2012static inline void feat2prop(char *s)
2013{
2014 while ((s = strchr(s, '_'))) {
2015 *s = '-';
2016 }
2017}
2018
dc15c051
IM
2019/* Compatibily hack to maintain legacy +-feat semantic,
2020 * where +-feat overwrites any feature set by
2021 * feat=on|feat even if the later is parsed after +-feat
2022 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2023 */
2024static FeatureWordArray plus_features = { 0 };
2025static FeatureWordArray minus_features = { 0 };
2026
8f961357
EH
2027/* Parse "+feature,-feature,feature=foo" CPU feature string
2028 */
62a48a2a 2029static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2030 Error **errp)
8f961357 2031{
8f961357 2032 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 2033 Error *local_err = NULL;
62a48a2a
IM
2034 static bool cpu_globals_initialized;
2035
2036 if (cpu_globals_initialized) {
2037 return;
2038 }
2039 cpu_globals_initialized = true;
8f961357 2040
f6750e95
EH
2041 if (!features) {
2042 return;
2043 }
2044
2045 for (featurestr = strtok(features, ",");
2046 featurestr && !local_err;
2047 featurestr = strtok(NULL, ",")) {
2048 const char *name;
2049 const char *val = NULL;
2050 char *eq = NULL;
cf2887c9 2051 char num[32];
62a48a2a 2052 GlobalProperty *prop;
c6dc6f63 2053
f6750e95 2054 /* Compatibility syntax: */
c6dc6f63 2055 if (featurestr[0] == '+') {
c00c94ab 2056 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
f6750e95 2057 continue;
c6dc6f63 2058 } else if (featurestr[0] == '-') {
c00c94ab 2059 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
f6750e95
EH
2060 continue;
2061 }
2062
2063 eq = strchr(featurestr, '=');
2064 if (eq) {
2065 *eq++ = 0;
2066 val = eq;
c6dc6f63 2067 } else {
f6750e95 2068 val = "on";
a91987c2 2069 }
f6750e95
EH
2070
2071 feat2prop(featurestr);
2072 name = featurestr;
2073
2074 /* Special case: */
2075 if (!strcmp(name, "tsc-freq")) {
2076 int64_t tsc_freq;
2077 char *err;
f6750e95
EH
2078
2079 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2080 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2081 if (tsc_freq < 0 || *err) {
2082 error_setg(errp, "bad numerical value %s", val);
2083 return;
2084 }
2085 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2086 val = num;
2087 name = "tsc-frequency";
c6dc6f63 2088 }
f6750e95 2089
62a48a2a
IM
2090 prop = g_new0(typeof(*prop), 1);
2091 prop->driver = typename;
2092 prop->property = g_strdup(name);
2093 prop->value = g_strdup(val);
2094 prop->errp = &error_fatal;
2095 qdev_prop_register_global(prop);
f6750e95
EH
2096 }
2097
2098 if (local_err) {
2099 error_propagate(errp, local_err);
c6dc6f63 2100 }
c6dc6f63
AP
2101}
2102
8c3329e5 2103/* Print all cpuid feature names in featureset
c6dc6f63 2104 */
8c3329e5 2105static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2106{
8c3329e5
EH
2107 int bit;
2108 bool first = true;
2109
2110 for (bit = 0; bit < 32; bit++) {
2111 if (featureset[bit]) {
2112 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2113 first = false;
c6dc6f63 2114 }
8c3329e5 2115 }
c6dc6f63
AP
2116}
2117
e916cbf8
PM
2118/* generate CPU information. */
2119void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2120{
9576de75 2121 X86CPUDefinition *def;
c6dc6f63 2122 char buf[256];
7fc9b714 2123 int i;
c6dc6f63 2124
7fc9b714
AF
2125 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2126 def = &builtin_x86_defs[i];
c04321b3 2127 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2128 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2129 }
21ad7789
JK
2130#ifdef CONFIG_KVM
2131 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2132 "KVM processor with all supported host features "
2133 "(only available in KVM mode)");
2134#endif
2135
6cdf8854 2136 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK
2137 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2138 FeatureWordInfo *fw = &feature_word_info[i];
2139
8c3329e5
EH
2140 (*cpu_fprintf)(f, " ");
2141 listflags(f, cpu_fprintf, fw->feat_names);
2142 (*cpu_fprintf)(f, "\n");
3af60be2 2143 }
c6dc6f63
AP
2144}
2145
76b64a7a 2146CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL
2147{
2148 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2149 X86CPUDefinition *def;
7fc9b714 2150 int i;
e3966126 2151
7fc9b714 2152 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL
2153 CpuDefinitionInfoList *entry;
2154 CpuDefinitionInfo *info;
2155
7fc9b714 2156 def = &builtin_x86_defs[i];
e3966126
AL
2157 info = g_malloc0(sizeof(*info));
2158 info->name = g_strdup(def->name);
2159
2160 entry = g_malloc0(sizeof(*entry));
2161 entry->value = info;
2162 entry->next = cpu_list;
2163 cpu_list = entry;
2164 }
2165
2166 return cpu_list;
2167}
2168
84f1b92f
EH
2169static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2170 bool migratable_only)
27418adf
EH
2171{
2172 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2173 uint32_t r;
27418adf 2174
fefb41bf 2175 if (kvm_enabled()) {
84f1b92f
EH
2176 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2177 wi->cpuid_ecx,
2178 wi->cpuid_reg);
fefb41bf 2179 } else if (tcg_enabled()) {
84f1b92f 2180 r = wi->tcg_features;
fefb41bf
EH
2181 } else {
2182 return ~0;
2183 }
84f1b92f
EH
2184 if (migratable_only) {
2185 r &= x86_cpu_get_migratable_flags(w);
2186 }
2187 return r;
27418adf
EH
2188}
2189
51f63aed
EH
2190/*
2191 * Filters CPU feature words based on host availability of each feature.
2192 *
51f63aed
EH
2193 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2194 */
27418adf 2195static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH
2196{
2197 CPUX86State *env = &cpu->env;
bd87d2a2 2198 FeatureWord w;
51f63aed
EH
2199 int rv = 0;
2200
bd87d2a2 2201 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH
2202 uint32_t host_feat =
2203 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH
2204 uint32_t requested_features = env->features[w];
2205 env->features[w] &= host_feat;
2206 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH
2207 if (cpu->filtered_features[w]) {
2208 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2209 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH
2210 }
2211 rv = 1;
2212 }
bd87d2a2 2213 }
51f63aed
EH
2214
2215 return rv;
bc74b7db 2216}
bc74b7db 2217
5114e842
EH
2218static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2219{
2220 PropValue *pv;
2221 for (pv = props; pv->prop; pv++) {
2222 if (!pv->value) {
2223 continue;
2224 }
2225 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2226 &error_abort);
2227 }
2228}
2229
d940ee9b 2230/* Load data from X86CPUDefinition
c080e30e 2231 */
d940ee9b 2232static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2233{
61dcd775 2234 CPUX86State *env = &cpu->env;
74f54bc4
EH
2235 const char *vendor;
2236 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2237 FeatureWord w;
c6dc6f63 2238
2d64255b
AF
2239 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2240 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2241 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2242 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2243 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2244 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2d64255b 2245 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH
2246 for (w = 0; w < FEATURE_WORDS; w++) {
2247 env->features[w] = def->features[w];
2248 }
82beb536 2249
9576de75 2250 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2251 if (kvm_enabled()) {
492a4c94
LT
2252 if (!kvm_irqchip_in_kernel()) {
2253 x86_cpu_change_kvm_default("x2apic", "off");
2254 }
2255
5114e842 2256 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2257 }
5fcca9ff 2258
82beb536 2259 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH
2260
2261 /* sysenter isn't supported in compatibility mode on AMD,
2262 * syscall isn't supported in compatibility mode on Intel.
2263 * Normally we advertise the actual CPU vendor, but you can
2264 * override this using the 'vendor' property if you want to use
2265 * KVM's sysenter/syscall emulation in compatibility mode and
2266 * when doing cross vendor migration
2267 */
74f54bc4 2268 vendor = def->vendor;
7c08db30
EH
2269 if (kvm_enabled()) {
2270 uint32_t ebx = 0, ecx = 0, edx = 0;
2271 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2272 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2273 vendor = host_vendor;
2274 }
2275
2276 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2277
c6dc6f63
AP
2278}
2279
0856579c 2280X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2281{
a57d0163 2282 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF
2283}
2284
d940ee9b
EH
2285static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2286{
2287 X86CPUDefinition *cpudef = data;
2288 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2289
2290 xcc->cpu_def = cpudef;
2291}
2292
2293static void x86_register_cpudef_type(X86CPUDefinition *def)
2294{
2295 char *typename = x86_cpu_type_name(def->name);
2296 TypeInfo ti = {
2297 .name = typename,
2298 .parent = TYPE_X86_CPU,
2299 .class_init = x86_cpu_cpudef_class_init,
2300 .class_data = def,
2301 };
2302
2303 type_register(&ti);
2304 g_free(typename);
2305}
2306
c6dc6f63 2307#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2308
0e26b7b8
BS
2309void cpu_clear_apic_feature(CPUX86State *env)
2310{
0514ef2f 2311 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS
2312}
2313
c6dc6f63
AP
2314#endif /* !CONFIG_USER_ONLY */
2315
c6dc6f63
AP
2316void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2317 uint32_t *eax, uint32_t *ebx,
2318 uint32_t *ecx, uint32_t *edx)
2319{
a60f24b5
AF
2320 X86CPU *cpu = x86_env_get_cpu(env);
2321 CPUState *cs = CPU(cpu);
2322
c6dc6f63
AP
2323 /* test if maximum index reached */
2324 if (index & 0x80000000) {
b3baa152
BW
2325 if (index > env->cpuid_xlevel) {
2326 if (env->cpuid_xlevel2 > 0) {
2327 /* Handle the Centaur's CPUID instruction. */
2328 if (index > env->cpuid_xlevel2) {
2329 index = env->cpuid_xlevel2;
2330 } else if (index < 0xC0000000) {
2331 index = env->cpuid_xlevel;
2332 }
2333 } else {
57f26ae7
EH
2334 /* Intel documentation states that invalid EAX input will
2335 * return the same information as EAX=cpuid_level
2336 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2337 */
2338 index = env->cpuid_level;
b3baa152
BW
2339 }
2340 }
c6dc6f63
AP
2341 } else {
2342 if (index > env->cpuid_level)
2343 index = env->cpuid_level;
2344 }
2345
2346 switch(index) {
2347 case 0:
2348 *eax = env->cpuid_level;
5eb2f7a4
EH
2349 *ebx = env->cpuid_vendor1;
2350 *edx = env->cpuid_vendor2;
2351 *ecx = env->cpuid_vendor3;
c6dc6f63
AP
2352 break;
2353 case 1:
2354 *eax = env->cpuid_version;
7e72a45c
EH
2355 *ebx = (cpu->apic_id << 24) |
2356 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2357 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH
2358 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2359 *ecx |= CPUID_EXT_OSXSAVE;
2360 }
0514ef2f 2361 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF
2362 if (cs->nr_cores * cs->nr_threads > 1) {
2363 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2364 *edx |= CPUID_HT;
c6dc6f63
AP
2365 }
2366 break;
2367 case 2:
2368 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC
2369 if (cpu->cache_info_passthrough) {
2370 host_cpuid(index, 0, eax, ebx, ecx, edx);
2371 break;
2372 }
5e891bf8 2373 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP
2374 *ebx = 0;
2375 *ecx = 0;
5e891bf8
EH
2376 *edx = (L1D_DESCRIPTOR << 16) | \
2377 (L1I_DESCRIPTOR << 8) | \
2378 (L2_DESCRIPTOR);
c6dc6f63
AP
2379 break;
2380 case 4:
2381 /* cache info: needed for Core compatibility */
787aaf57
BC
2382 if (cpu->cache_info_passthrough) {
2383 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2384 *eax &= ~0xFC000000;
c6dc6f63 2385 } else {
2f7a21c4 2386 *eax = 0;
76c2975a 2387 switch (count) {
c6dc6f63 2388 case 0: /* L1 dcache info */
5e891bf8
EH
2389 *eax |= CPUID_4_TYPE_DCACHE | \
2390 CPUID_4_LEVEL(1) | \
2391 CPUID_4_SELF_INIT_LEVEL;
2392 *ebx = (L1D_LINE_SIZE - 1) | \
2393 ((L1D_PARTITIONS - 1) << 12) | \
2394 ((L1D_ASSOCIATIVITY - 1) << 22);
2395 *ecx = L1D_SETS - 1;
2396 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP
2397 break;
2398 case 1: /* L1 icache info */
5e891bf8
EH
2399 *eax |= CPUID_4_TYPE_ICACHE | \
2400 CPUID_4_LEVEL(1) | \
2401 CPUID_4_SELF_INIT_LEVEL;
2402 *ebx = (L1I_LINE_SIZE - 1) | \
2403 ((L1I_PARTITIONS - 1) << 12) | \
2404 ((L1I_ASSOCIATIVITY - 1) << 22);
2405 *ecx = L1I_SETS - 1;
2406 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP
2407 break;
2408 case 2: /* L2 cache info */
5e891bf8
EH
2409 *eax |= CPUID_4_TYPE_UNIFIED | \
2410 CPUID_4_LEVEL(2) | \
2411 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF
2412 if (cs->nr_threads > 1) {
2413 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2414 }
5e891bf8
EH
2415 *ebx = (L2_LINE_SIZE - 1) | \
2416 ((L2_PARTITIONS - 1) << 12) | \
2417 ((L2_ASSOCIATIVITY - 1) << 22);
2418 *ecx = L2_SETS - 1;
2419 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP
2420 break;
2421 default: /* end of info */
2422 *eax = 0;
2423 *ebx = 0;
2424 *ecx = 0;
2425 *edx = 0;
2426 break;
76c2975a
PB
2427 }
2428 }
2429
2430 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2431 if ((*eax & 31) && cs->nr_cores > 1) {
2432 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP
2433 }
2434 break;
2435 case 5:
2436 /* mwait info: needed for Core compatibility */
2437 *eax = 0; /* Smallest monitor-line size in bytes */
2438 *ebx = 0; /* Largest monitor-line size in bytes */
2439 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2440 *edx = 0;
2441 break;
2442 case 6:
2443 /* Thermal and Power Leaf */
28b8e4d0 2444 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP
2445 *ebx = 0;
2446 *ecx = 0;
2447 *edx = 0;
2448 break;
f7911686 2449 case 7:
13526728
EH
2450 /* Structured Extended Feature Flags Enumeration Leaf */
2451 if (count == 0) {
2452 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2453 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2454 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB
2455 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2456 *ecx |= CPUID_7_0_ECX_OSPKE;
2457 }
13526728 2458 *edx = 0; /* Reserved */
f7911686
YW
2459 } else {
2460 *eax = 0;
2461 *ebx = 0;
2462 *ecx = 0;
2463 *edx = 0;
2464 }
2465 break;
c6dc6f63
AP
2466 case 9:
2467 /* Direct Cache Access Information Leaf */
2468 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2469 *ebx = 0;
2470 *ecx = 0;
2471 *edx = 0;
2472 break;
2473 case 0xA:
2474 /* Architectural Performance Monitoring Leaf */
9337e3b6 2475 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2476 KVMState *s = cs->kvm_state;
a0fa8208
GN
2477
2478 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2479 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2480 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2481 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2482 } else {
2483 *eax = 0;
2484 *ebx = 0;
2485 *ecx = 0;
2486 *edx = 0;
2487 }
c6dc6f63 2488 break;
5232d00a
RK
2489 case 0xB:
2490 /* Extended Topology Enumeration Leaf */
2491 if (!cpu->enable_cpuid_0xb) {
2492 *eax = *ebx = *ecx = *edx = 0;
2493 break;
2494 }
2495
2496 *ecx = count & 0xff;
2497 *edx = cpu->apic_id;
2498
2499 switch (count) {
2500 case 0:
2501 *eax = apicid_core_offset(smp_cores, smp_threads);
2502 *ebx = smp_threads;
2503 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2504 break;
2505 case 1:
2506 *eax = apicid_pkg_offset(smp_cores, smp_threads);
2507 *ebx = smp_cores * smp_threads;
2508 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2509 break;
2510 default:
2511 *eax = 0;
2512 *ebx = 0;
2513 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2514 }
2515
2516 assert(!(*eax & ~0x1f));
2517 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2518 break;
2560f19f
PB
2519 case 0xD: {
2520 KVMState *s = cs->kvm_state;
19dc85db 2521 uint64_t ena_mask;
2560f19f
PB
2522 int i;
2523
51e49430 2524 /* Processor Extended State */
2560f19f
PB
2525 *eax = 0;
2526 *ebx = 0;
2527 *ecx = 0;
2528 *edx = 0;
19dc85db 2529 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY
2530 break;
2531 }
19dc85db
RH
2532 if (kvm_enabled()) {
2533 ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2534 ena_mask <<= 32;
2535 ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2536 } else {
2537 ena_mask = -1;
2538 }
ba9bc59e 2539
2560f19f
PB
2540 if (count == 0) {
2541 *ecx = 0x240;
f4f1110e
RH
2542 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2543 const ExtSaveArea *esa = &x86_ext_save_areas[i];
19dc85db
RH
2544 if ((env->features[esa->feature] & esa->bits) == esa->bits
2545 && ((ena_mask >> i) & 1) != 0) {
2560f19f 2546 if (i < 32) {
19dc85db 2547 *eax |= 1u << i;
2560f19f 2548 } else {
19dc85db 2549 *edx |= 1u << (i - 32);
2560f19f
PB
2550 }
2551 *ecx = MAX(*ecx, esa->offset + esa->size);
2552 }
2553 }
cfc3b074 2554 *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2560f19f
PB
2555 *ebx = *ecx;
2556 } else if (count == 1) {
0bb0b2d2 2557 *eax = env->features[FEAT_XSAVE];
f4f1110e
RH
2558 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2559 const ExtSaveArea *esa = &x86_ext_save_areas[count];
19dc85db
RH
2560 if ((env->features[esa->feature] & esa->bits) == esa->bits
2561 && ((ena_mask >> count) & 1) != 0) {
33f373d7
LJ
2562 *eax = esa->size;
2563 *ebx = esa->offset;
2560f19f 2564 }
51e49430
SY
2565 }
2566 break;
2560f19f 2567 }
c6dc6f63
AP
2568 case 0x80000000:
2569 *eax = env->cpuid_xlevel;
2570 *ebx = env->cpuid_vendor1;
2571 *edx = env->cpuid_vendor2;
2572 *ecx = env->cpuid_vendor3;
2573 break;
2574 case 0x80000001:
2575 *eax = env->cpuid_version;
2576 *ebx = 0;
0514ef2f
EH
2577 *ecx = env->features[FEAT_8000_0001_ECX];
2578 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP
2579
2580 /* The Linux kernel checks for the CMPLegacy bit and
2581 * discards multiple thread information if it is set.
cb8d4c8f 2582 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2583 */
ce3960eb 2584 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH
2585 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2586 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2587 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP
2588 *ecx |= 1 << 1; /* CmpLegacy bit */
2589 }
2590 }
c6dc6f63
AP
2591 break;
2592 case 0x80000002:
2593 case 0x80000003:
2594 case 0x80000004:
2595 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2596 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2597 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2598 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2599 break;
2600 case 0x80000005:
2601 /* cache info (L1 cache) */
787aaf57
BC
2602 if (cpu->cache_info_passthrough) {
2603 host_cpuid(index, 0, eax, ebx, ecx, edx);
2604 break;
2605 }
5e891bf8
EH
2606 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2607 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2608 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2609 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2610 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2611 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2612 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2613 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP
2614 break;
2615 case 0x80000006:
2616 /* cache info (L2 cache) */
787aaf57
BC
2617 if (cpu->cache_info_passthrough) {
2618 host_cpuid(index, 0, eax, ebx, ecx, edx);
2619 break;
2620 }
5e891bf8
EH
2621 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2622 (L2_DTLB_2M_ENTRIES << 16) | \
2623 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2624 (L2_ITLB_2M_ENTRIES);
2625 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2626 (L2_DTLB_4K_ENTRIES << 16) | \
2627 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2628 (L2_ITLB_4K_ENTRIES);
2629 *ecx = (L2_SIZE_KB_AMD << 16) | \
2630 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2631 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2632 *edx = ((L3_SIZE_KB/512) << 18) | \
2633 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2634 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2635 break;
303752a9
MT
2636 case 0x80000007:
2637 *eax = 0;
2638 *ebx = 0;
2639 *ecx = 0;
2640 *edx = env->features[FEAT_8000_0007_EDX];
2641 break;
c6dc6f63
AP
2642 case 0x80000008:
2643 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2644 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a
DDAG
2645 /* 64 bit processor, 48 bits virtual, configurable
2646 * physical bits.
2647 */
2648 *eax = 0x00003000 + cpu->phys_bits;
c6dc6f63 2649 } else {
af45907a 2650 *eax = cpu->phys_bits;
c6dc6f63
AP
2651 }
2652 *ebx = 0;
2653 *ecx = 0;
2654 *edx = 0;
ce3960eb
AF
2655 if (cs->nr_cores * cs->nr_threads > 1) {
2656 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP
2657 }
2658 break;
2659 case 0x8000000A:
0514ef2f 2660 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH
2661 *eax = 0x00000001; /* SVM Revision */
2662 *ebx = 0x00000010; /* nr of ASIDs */
2663 *ecx = 0;
0514ef2f 2664 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH
2665 } else {
2666 *eax = 0;
2667 *ebx = 0;
2668 *ecx = 0;
2669 *edx = 0;
2670 }
c6dc6f63 2671 break;
b3baa152
BW
2672 case 0xC0000000:
2673 *eax = env->cpuid_xlevel2;
2674 *ebx = 0;
2675 *ecx = 0;
2676 *edx = 0;
2677 break;
2678 case 0xC0000001:
2679 /* Support for VIA CPU's CPUID instruction */
2680 *eax = env->cpuid_version;
2681 *ebx = 0;
2682 *ecx = 0;
0514ef2f 2683 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW
2684 break;
2685 case 0xC0000002:
2686 case 0xC0000003:
2687 case 0xC0000004:
2688 /* Reserved for the future, and now filled with zero */
2689 *eax = 0;
2690 *ebx = 0;
2691 *ecx = 0;
2692 *edx = 0;
2693 break;
c6dc6f63
AP
2694 default:
2695 /* reserved values: zero */
2696 *eax = 0;
2697 *ebx = 0;
2698 *ecx = 0;
2699 *edx = 0;
2700 break;
2701 }
2702}
5fd2087a
AF
2703
2704/* CPUClass::reset() */
2705static void x86_cpu_reset(CPUState *s)
2706{
2707 X86CPU *cpu = X86_CPU(s);
2708 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2709 CPUX86State *env = &cpu->env;
a114d25d
RH
2710 target_ulong cr4;
2711 uint64_t xcr0;
c1958aea
AF
2712 int i;
2713
5fd2087a
AF
2714 xcc->parent_reset(s);
2715
43175fa9 2716 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2717
00c8cb0a 2718 tlb_flush(s, 1);
c1958aea
AF
2719
2720 env->old_exception = -1;
2721
2722 /* init to reset state */
2723
c1958aea
AF
2724 env->hflags2 |= HF2_GIF_MASK;
2725
2726 cpu_x86_update_cr0(env, 0x60000010);
2727 env->a20_mask = ~0x0;
2728 env->smbase = 0x30000;
2729
2730 env->idt.limit = 0xffff;
2731 env->gdt.limit = 0xffff;
2732 env->ldt.limit = 0xffff;
2733 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2734 env->tr.limit = 0xffff;
2735 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2736
2737 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2738 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2739 DESC_R_MASK | DESC_A_MASK);
2740 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2741 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2742 DESC_A_MASK);
2743 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2744 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2745 DESC_A_MASK);
2746 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2747 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2748 DESC_A_MASK);
2749 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2750 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2751 DESC_A_MASK);
2752 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2753 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2754 DESC_A_MASK);
2755
2756 env->eip = 0xfff0;
2757 env->regs[R_EDX] = env->cpuid_version;
2758
2759 env->eflags = 0x2;
2760
2761 /* FPU init */
2762 for (i = 0; i < 8; i++) {
2763 env->fptags[i] = 1;
2764 }
5bde1407 2765 cpu_set_fpuc(env, 0x37f);
c1958aea
AF
2766
2767 env->mxcsr = 0x1f80;
a114d25d
RH
2768 /* All units are in INIT state. */
2769 env->xstate_bv = 0;
c1958aea
AF
2770
2771 env->pat = 0x0007040600070406ULL;
2772 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2773
2774 memset(env->dr, 0, sizeof(env->dr));
2775 env->dr[6] = DR6_FIXED_1;
2776 env->dr[7] = DR7_FIXED_1;
b3310ab3 2777 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2778 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2779
a114d25d 2780 cr4 = 0;
cfc3b074 2781 xcr0 = XSTATE_FP_MASK;
a114d25d
RH
2782
2783#ifdef CONFIG_USER_ONLY
2784 /* Enable all the features for user-mode. */
2785 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2786 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2787 }
0f70ed47
PB
2788 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2789 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2790 if ((env->features[esa->feature] & esa->bits) == esa->bits) {
2791 xcr0 |= 1ull << i;
2792 }
a114d25d 2793 }
0f70ed47 2794
a114d25d
RH
2795 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2796 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2797 }
07929f2a
RH
2798 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2799 cr4 |= CR4_FSGSBASE_MASK;
2800 }
a114d25d
RH
2801#endif
2802
2803 env->xcr0 = xcr0;
2804 cpu_x86_update_cr4(env, cr4);
0522604b 2805
9db2efd9
AW
2806 /*
2807 * SDM 11.11.5 requires:
2808 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2809 * - IA32_MTRR_PHYSMASKn.V = 0
2810 * All other bits are undefined. For simplification, zero it all.
2811 */
2812 env->mtrr_deftype = 0;
2813 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2814 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2815
dd673288
IM
2816#if !defined(CONFIG_USER_ONLY)
2817 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2818 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2819
259186a7 2820 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB
2821
2822 if (kvm_enabled()) {
2823 kvm_arch_reset_vcpu(cpu);
2824 }
dd673288 2825#endif
5fd2087a
AF
2826}
2827
dd673288
IM
2828#ifndef CONFIG_USER_ONLY
2829bool cpu_is_bsp(X86CPU *cpu)
2830{
02e51483 2831 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2832}
65dee380
IM
2833
2834/* TODO: remove me, when reset over QOM tree is implemented */
2835static void x86_cpu_machine_reset_cb(void *opaque)
2836{
2837 X86CPU *cpu = opaque;
2838 cpu_reset(CPU(cpu));
2839}
dd673288
IM
2840#endif
2841
de024815
AF
2842static void mce_init(X86CPU *cpu)
2843{
2844 CPUX86State *cenv = &cpu->env;
2845 unsigned int bank;
2846
2847 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2848 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2849 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR
2850 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2851 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF
2852 cenv->mcg_ctl = ~(uint64_t)0;
2853 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2854 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2855 }
2856 }
2857}
2858
bdeec802 2859#ifndef CONFIG_USER_ONLY
d3c64d6a 2860static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2861{
449994eb 2862 APICCommonState *apic;
bdeec802
IM
2863 const char *apic_type = "apic";
2864
15eafc2e 2865 if (kvm_apic_in_kernel()) {
bdeec802
IM
2866 apic_type = "kvm-apic";
2867 } else if (xen_enabled()) {
2868 apic_type = "xen-apic";
2869 }
2870
46232aaa 2871 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802
IM
2872
2873 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2874 OBJECT(cpu->apic_state), NULL);
7e72a45c 2875 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2876 /* TODO: convert to link<> */
02e51483 2877 apic = APIC_COMMON(cpu->apic_state);
60671e58 2878 apic->cpu = cpu;
8d42d2d3 2879 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM
2880}
2881
2882static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2883{
8d42d2d3
CF
2884 APICCommonState *apic;
2885 static bool apic_mmio_map_once;
2886
02e51483 2887 if (cpu->apic_state == NULL) {
d3c64d6a
IM
2888 return;
2889 }
6e8e2651
MA
2890 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2891 errp);
8d42d2d3
CF
2892
2893 /* Map APIC MMIO area */
2894 apic = APIC_COMMON(cpu->apic_state);
2895 if (!apic_mmio_map_once) {
2896 memory_region_add_subregion_overlap(get_system_memory(),
2897 apic->apicbase &
2898 MSR_IA32_APICBASE_BASE,
2899 &apic->io_memory,
2900 0x1000);
2901 apic_mmio_map_once = true;
2902 }
bdeec802 2903}
f809c605
PB
2904
2905static void x86_cpu_machine_done(Notifier *n, void *unused)
2906{
2907 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2908 MemoryRegion *smram =
2909 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2910
2911 if (smram) {
2912 cpu->smram = g_new(MemoryRegion, 1);
2913 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2914 smram, 0, 1ull << 32);
2915 memory_region_set_enabled(cpu->smram, false);
2916 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2917 }
2918}
d3c64d6a
IM
2919#else
2920static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2921{
2922}
bdeec802
IM
2923#endif
2924
e48638fd
WH
2925
2926#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2927 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2928 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2929#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2930 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2931 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2932static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2933{
14a10fc3 2934 CPUState *cs = CPU(dev);
2b6f294c
AF
2935 X86CPU *cpu = X86_CPU(dev);
2936 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2937 CPUX86State *env = &cpu->env;
2b6f294c 2938 Error *local_err = NULL;
e48638fd 2939 static bool ht_warned;
dc15c051 2940 FeatureWord w;
b34d12d1 2941
104494ea
IM
2942 if (xcc->kvm_required && !kvm_enabled()) {
2943 char *name = x86_cpu_class_get_model_name(xcc);
2944 error_setg(&local_err, "CPU model '%s' requires KVM", name);
2945 g_free(name);
2946 goto out;
2947 }
2948
9886e834
EH
2949 if (cpu->apic_id < 0) {
2950 error_setg(errp, "apic-id property was not initialized properly");
2951 return;
2952 }
2953
dc15c051
IM
2954 /*TODO: cpu->host_features incorrectly overwrites features
2955 * set using "feat=on|off". Once we fix this, we can convert
2956 * plus_features & minus_features to global properties
2957 * inside x86_cpu_parse_featurestr() too.
2958 */
2959 if (cpu->host_features) {
2960 for (w = 0; w < FEATURE_WORDS; w++) {
2961 env->features[w] =
2962 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2963 }
2964 }
2965
2966 for (w = 0; w < FEATURE_WORDS; w++) {
2967 cpu->env.features[w] |= plus_features[w];
2968 cpu->env.features[w] &= ~minus_features[w];
2969 }
2970
0514ef2f 2971 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM
2972 env->cpuid_level = 7;
2973 }
7a059953 2974
9997cf7b
EH
2975 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2976 error_setg(&local_err,
2977 kvm_enabled() ?
2978 "Host doesn't support requested features" :
2979 "TCG doesn't support requested features");
2980 goto out;
2981 }
2982
9b15cd9e
IM
2983 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2984 * CPUID[1].EDX.
2985 */
e48638fd 2986 if (IS_AMD_CPU(env)) {
0514ef2f
EH
2987 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2988 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM
2989 & CPUID_EXT2_AMD_ALIASES);
2990 }
2991
af45907a
DDAG
2992 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2993 /* 0 means it was not explicitly set by the user (or by machine
2994 * compat_props). In this case, the default is the value used by
2995 * TCG (40).
2996 */
2997 if (cpu->phys_bits == 0) {
2998 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
2999 }
3000 if (kvm_enabled()) {
3001 if (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3002 cpu->phys_bits < 32) {
3003 error_setg(errp, "phys-bits should be between 32 and %u "
3004 " (but is %u)",
3005 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3006 return;
3007 }
3008 } else {
3009 if (cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
3010 error_setg(errp, "TCG only supports phys-bits=%u",
3011 TCG_PHYS_ADDR_BITS);
3012 return;
3013 }
3014 }
3015 } else {
3016 /* For 32 bit systems don't use the user set value, but keep
3017 * phys_bits consistent with what we tell the guest.
3018 */
3019 if (cpu->phys_bits != 0) {
3020 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3021 return;
3022 }
fefb41bf 3023
af45907a
DDAG
3024 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3025 cpu->phys_bits = 36;
3026 } else {
3027 cpu->phys_bits = 32;
3028 }
3029 }
42ecabaa
EH
3030 cpu_exec_init(cs, &error_abort);
3031
57f2453a
EH
3032 if (tcg_enabled()) {
3033 tcg_x86_init();
3034 }
3035
65dee380
IM
3036#ifndef CONFIG_USER_ONLY
3037 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3038
0514ef2f 3039 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3040 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3041 if (local_err != NULL) {
4dc1f449 3042 goto out;
bdeec802
IM
3043 }
3044 }
65dee380
IM
3045#endif
3046
7a059953 3047 mce_init(cpu);
2001d0cd
PB
3048
3049#ifndef CONFIG_USER_ONLY
3050 if (tcg_enabled()) {
56943e8c
PM
3051 AddressSpace *newas = g_new(AddressSpace, 1);
3052
f809c605 3053 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3054 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB
3055
3056 /* Outer container... */
3057 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3058 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB
3059
3060 /* ... with two regions inside: normal system memory with low
3061 * priority, and...
3062 */
3063 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3064 get_system_memory(), 0, ~0ull);
3065 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3066 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3067 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3068 cs->num_ases = 1;
56943e8c 3069 cpu_address_space_init(cs, newas, 0);
f809c605
PB
3070
3071 /* ... SMRAM with higher priority, linked from /machine/smram. */
3072 cpu->machine_done.notify = x86_cpu_machine_done;
3073 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB
3074 }
3075#endif
3076
14a10fc3 3077 qemu_init_vcpu(cs);
d3c64d6a 3078
e48638fd
WH
3079 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3080 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3081 * based on inputs (sockets,cores,threads), it is still better to gives
3082 * users a warning.
3083 *
3084 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3085 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3086 */
3087 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3088 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3089 " -smp options properly.");
3090 ht_warned = true;
3091 }
3092
d3c64d6a
IM
3093 x86_cpu_apic_realize(cpu, &local_err);
3094 if (local_err != NULL) {
3095 goto out;
3096 }
14a10fc3 3097 cpu_reset(cs);
2b6f294c 3098
4dc1f449 3099 xcc->parent_realize(dev, &local_err);
2001d0cd 3100
4dc1f449
IM
3101out:
3102 if (local_err != NULL) {
3103 error_propagate(errp, local_err);
3104 return;
3105 }
7a059953
AF
3106}
3107
38e5c119
EH
3108typedef struct BitProperty {
3109 uint32_t *ptr;
3110 uint32_t mask;
3111} BitProperty;
3112
d7bce999
EB
3113static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3114 void *opaque, Error **errp)
38e5c119
EH
3115{
3116 BitProperty *fp = opaque;
3117 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3118 visit_type_bool(v, name, &value, errp);
38e5c119
EH
3119}
3120
d7bce999
EB
3121static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3122 void *opaque, Error **errp)
38e5c119
EH
3123{
3124 DeviceState *dev = DEVICE(obj);
3125 BitProperty *fp = opaque;
3126 Error *local_err = NULL;
3127 bool value;
3128
3129 if (dev->realized) {
3130 qdev_prop_set_after_realize(dev, name, errp);
3131 return;
3132 }
3133
51e72bc1 3134 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH
3135 if (local_err) {
3136 error_propagate(errp, local_err);
3137 return;
3138 }
3139
3140 if (value) {
3141 *fp->ptr |= fp->mask;
3142 } else {
3143 *fp->ptr &= ~fp->mask;
3144 }
3145}
3146
3147static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3148 void *opaque)
3149{
3150 BitProperty *prop = opaque;
3151 g_free(prop);
3152}
3153
3154/* Register a boolean property to get/set a single bit in a uint32_t field.
3155 *
3156 * The same property name can be registered multiple times to make it affect
3157 * multiple bits in the same FeatureWord. In that case, the getter will return
3158 * true only if all bits are set.
3159 */
3160static void x86_cpu_register_bit_prop(X86CPU *cpu,
3161 const char *prop_name,
3162 uint32_t *field,
3163 int bitnr)
3164{
3165 BitProperty *fp;
3166 ObjectProperty *op;
3167 uint32_t mask = (1UL << bitnr);
3168
3169 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3170 if (op) {
3171 fp = op->opaque;
3172 assert(fp->ptr == field);
3173 fp->mask |= mask;
3174 } else {
3175 fp = g_new0(BitProperty, 1);
3176 fp->ptr = field;
3177 fp->mask = mask;
3178 object_property_add(OBJECT(cpu), prop_name, "bool",
3179 x86_cpu_get_bit_prop,
3180 x86_cpu_set_bit_prop,
3181 x86_cpu_release_bit_prop, fp, &error_abort);
3182 }
3183}
3184
3185static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3186 FeatureWord w,
3187 int bitnr)
3188{
3189 Object *obj = OBJECT(cpu);
3190 int i;
3191 char **names;
3192 FeatureWordInfo *fi = &feature_word_info[w];
3193
3194 if (!fi->feat_names) {
3195 return;
3196 }
3197 if (!fi->feat_names[bitnr]) {
3198 return;
3199 }
3200
3201 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3202
3203 feat2prop(names[0]);
3204 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3205
3206 for (i = 1; names[i]; i++) {
3207 feat2prop(names[i]);
d461a44c 3208 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH
3209 &error_abort);
3210 }
3211
3212 g_strfreev(names);
3213}
3214
de024815
AF
3215static void x86_cpu_initfn(Object *obj)
3216{
55e5c285 3217 CPUState *cs = CPU(obj);
de024815 3218 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3219 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3220 CPUX86State *env = &cpu->env;
38e5c119 3221 FeatureWord w;
de024815 3222
c05efcb1 3223 cs->env_ptr = env;
71ad61d3
AF
3224
3225 object_property_add(obj, "family", "int",
95b8519d 3226 x86_cpuid_version_get_family,
71ad61d3 3227 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3228 object_property_add(obj, "model", "int",
67e30c83 3229 x86_cpuid_version_get_model,
c5291a4f 3230 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3231 object_property_add(obj, "stepping", "int",
35112e41 3232 x86_cpuid_version_get_stepping,
036e2222 3233 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF
3234 object_property_add_str(obj, "vendor",
3235 x86_cpuid_get_vendor,
3236 x86_cpuid_set_vendor, NULL);
938d4c25 3237 object_property_add_str(obj, "model-id",
63e886eb 3238 x86_cpuid_get_model_id,
938d4c25 3239 x86_cpuid_set_model_id, NULL);
89e48965
AF
3240 object_property_add(obj, "tsc-frequency", "int",
3241 x86_cpuid_get_tsc_freq,
3242 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM
3243 object_property_add(obj, "apic-id", "int",
3244 x86_cpuid_get_apic_id,
3245 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH
3246 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3247 x86_cpu_get_feature_words,
7e5292b5
EH
3248 NULL, NULL, (void *)env->features, NULL);
3249 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3250 x86_cpu_get_feature_words,
3251 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3252
92067bf4 3253 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3254
9886e834
EH
3255#ifndef CONFIG_USER_ONLY
3256 /* Any code creating new X86CPU objects have to set apic-id explicitly */
3257 cpu->apic_id = -1;
3258#endif
3259
38e5c119
EH
3260 for (w = 0; w < FEATURE_WORDS; w++) {
3261 int bitnr;
3262
3263 for (bitnr = 0; bitnr < 32; bitnr++) {
3264 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3265 }
3266 }
3267
d940ee9b 3268 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF
3269}
3270
997395d3
IM
3271static int64_t x86_cpu_get_arch_id(CPUState *cs)
3272{
3273 X86CPU *cpu = X86_CPU(cs);
997395d3 3274
7e72a45c 3275 return cpu->apic_id;
997395d3
IM
3276}
3277
444d5590
AF
3278static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3279{
3280 X86CPU *cpu = X86_CPU(cs);
3281
3282 return cpu->env.cr[0] & CR0_PG_MASK;
3283}
3284
f45748f1
AF
3285static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3286{
3287 X86CPU *cpu = X86_CPU(cs);
3288
3289 cpu->env.eip = value;
3290}
3291
bdf7ae5b
AF
3292static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3293{
3294 X86CPU *cpu = X86_CPU(cs);
3295
3296 cpu->env.eip = tb->pc - tb->cs_base;
3297}
3298
8c2e1b00
AF
3299static bool x86_cpu_has_work(CPUState *cs)
3300{
3301 X86CPU *cpu = X86_CPU(cs);
3302 CPUX86State *env = &cpu->env;
3303
6220e900
PD
3304 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3305 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF
3306 (env->eflags & IF_MASK)) ||
3307 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3308 CPU_INTERRUPT_INIT |
3309 CPU_INTERRUPT_SIPI |
a9bad65d
PB
3310 CPU_INTERRUPT_MCE)) ||
3311 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3312 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF
3313}
3314
9337e3b6
EH
3315static Property x86_cpu_properties[] = {
3316 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3317 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3318 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3319 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3320 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3321 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3322 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3323 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3324 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3325 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3326 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3327 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3328 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3329 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3330 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
b9472b76
EH
3331 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3332 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3333 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
1c4a55db 3334 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3335 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3336 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
9337e3b6
EH
3337 DEFINE_PROP_END_OF_LIST()
3338};
3339
5fd2087a
AF
3340static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3341{
3342 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3343 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF
3344 DeviceClass *dc = DEVICE_CLASS(oc);
3345
3346 xcc->parent_realize = dc->realize;
3347 dc->realize = x86_cpu_realizefn;
9337e3b6 3348 dc->props = x86_cpu_properties;
5fd2087a
AF
3349
3350 xcc->parent_reset = cc->reset;
3351 cc->reset = x86_cpu_reset;
91b1df8c 3352 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3353
500050d1 3354 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3355 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3356 cc->has_work = x86_cpu_has_work;
97a8ea5a 3357 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3358 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3359 cc->dump_state = x86_cpu_dump_state;
f45748f1 3360 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3361 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF
3362 cc->gdb_read_register = x86_cpu_gdb_read_register;
3363 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF
3364 cc->get_arch_id = x86_cpu_get_arch_id;
3365 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF
3366#ifdef CONFIG_USER_ONLY
3367 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3368#else
a23bbfda 3369 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3370 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF
3371 cc->write_elf64_note = x86_cpu_write_elf64_note;
3372 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3373 cc->write_elf32_note = x86_cpu_write_elf32_note;
3374 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3375 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3376#endif
a0e372f0 3377 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM
3378#ifndef CONFIG_USER_ONLY
3379 cc->debug_excp_handler = breakpoint_handler;
3380#endif
374e0cd4
RH
3381 cc->cpu_exec_enter = x86_cpu_exec_enter;
3382 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27
MA
3383
3384 /*
3385 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3386 * object in cpus -> dangling pointer after final object_unref().
3387 */
3388 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF
3389}
3390
3391static const TypeInfo x86_cpu_type_info = {
3392 .name = TYPE_X86_CPU,
3393 .parent = TYPE_CPU,
3394 .instance_size = sizeof(X86CPU),
de024815 3395 .instance_init = x86_cpu_initfn,
d940ee9b 3396 .abstract = true,
5fd2087a
AF
3397 .class_size = sizeof(X86CPUClass),
3398 .class_init = x86_cpu_common_class_init,
3399};
3400
3401static void x86_cpu_register_types(void)
3402{
d940ee9b
EH
3403 int i;
3404
5fd2087a 3405 type_register_static(&x86_cpu_type_info);
d940ee9b
EH
3406 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3407 x86_register_cpudef_type(&builtin_x86_defs[i]);
3408 }
3409#ifdef CONFIG_KVM
3410 type_register_static(&host_x86_cpu_type_info);
3411#endif
5fd2087a
AF
3412}
3413
3414type_init(x86_cpu_register_types)