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KVM: x86: Support for disabling quirks
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
dab2087d 48#include <asm/apic.h>
6aa8b732 49
229456fc
MT		 50#include "trace.h"
51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6
SY		 534
535 bool rdtscp_enabled;
ec378aee 536
01e439be
YZ		 537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
539
ec378aee
NHE		 540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
a7653ecd
RK		 542
543 /* Dynamic PLE window. */
544 int ple_window;
545 bool ple_window_dirty;
843e4330
KH		 546
547 /* Support for PML */
548#define PML_ENTITY_NUM 512
549 struct page *pml_pg;
a2fa3e9f
GH		 550};
551
2fb92db1
AK		 552enum segment_cache_field {
553 SEG_FIELD_SEL = 0,
554 SEG_FIELD_BASE = 1,
555 SEG_FIELD_LIMIT = 2,
556 SEG_FIELD_AR = 3,
557
558 SEG_FIELD_NR = 4
559};
560
a2fa3e9f
GH		 561static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562{
fb3f0f51 563 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 564}
565
22bd0358
NHE		 566#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
4607c2d7 571
fe2b201b 572static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 573 /*
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
584 */
585 VM_EXIT_REASON,
586 VM_EXIT_INTR_INFO,
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
591 EXIT_QUALIFICATION,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
594};
fe2b201b 595static int max_shadow_read_only_fields =
4607c2d7
AG		 596 ARRAY_SIZE(shadow_read_only_fields);
597
fe2b201b 598static unsigned long shadow_read_write_fields[] = {
a7c0b07d 599 TPR_THRESHOLD,
4607c2d7
AG		 600 GUEST_RIP,
601 GUEST_RSP,
602 GUEST_CR0,
603 GUEST_CR3,
604 GUEST_CR4,
605 GUEST_INTERRUPTIBILITY_INFO,
606 GUEST_RFLAGS,
607 GUEST_CS_SELECTOR,
608 GUEST_CS_AR_BYTES,
609 GUEST_CS_LIMIT,
610 GUEST_CS_BASE,
611 GUEST_ES_BASE,
36be0b9d 612 GUEST_BNDCFGS,
4607c2d7
AG		 613 CR0_GUEST_HOST_MASK,
614 CR0_READ_SHADOW,
615 CR4_READ_SHADOW,
616 TSC_OFFSET,
617 EXCEPTION_BITMAP,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
623 HOST_FS_BASE,
624 HOST_GS_BASE,
625 HOST_FS_SELECTOR,
626 HOST_GS_SELECTOR
627};
fe2b201b 628static int max_shadow_read_write_fields =
4607c2d7
AG		 629 ARRAY_SIZE(shadow_read_write_fields);
630
772e0318 631static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 633 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 660 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
769};
22bd0358
NHE		 770
771static inline short vmcs_field_to_offset(unsigned long field)
772{
a2ae9df7
PB		 773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
777 return -ENOENT;
778
22bd0358
NHE		 779 return vmcs_field_to_offset_table[field];
780}
781
a9d30f33
NHE		 782static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783{
784 return to_vmx(vcpu)->nested.current_vmcs12;
785}
786
787static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788{
789 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 790 if (is_error_page(page))
a9d30f33 791 return NULL;
32cad84f 792
a9d30f33
NHE		 793 return page;
794}
795
796static void nested_release_page(struct page *page)
797{
798 kvm_release_page_dirty(page);
799}
800
801static void nested_release_page_clean(struct page *page)
802{
803 kvm_release_page_clean(page);
804}
805
bfd0a56b 806static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 807static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 808static void kvm_cpu_vmxon(u64 addr);
809static void kvm_cpu_vmxoff(void);
93c4adc7 810static bool vmx_mpx_supported(void);
f53cd63c 811static bool vmx_xsaves_supported(void);
705699a1 812static int vmx_vm_has_apicv(struct kvm *kvm);
776e58ea 813static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 814static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
d99e4152
GN		 818static bool guest_state_valid(struct kvm_vcpu *vcpu);
819static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 820static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 821static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 822static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 823static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 824
6aa8b732
AK		 825static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 827/*
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 */
831static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 832static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 833
3e7c73e9
AK		 834static unsigned long *vmx_io_bitmap_a;
835static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 836static unsigned long *vmx_msr_bitmap_legacy;
837static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 838static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 840static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 841static unsigned long *vmx_vmread_bitmap;
842static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 843
110312c8 844static bool cpu_has_load_ia32_efer;
8bf00a52 845static bool cpu_has_load_perf_global_ctrl;
110312c8 846
2384d2b3
SY		 847static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848static DEFINE_SPINLOCK(vmx_vpid_lock);
849
1c3d14fe 850static struct vmcs_config {
6aa8b732
AK		 851 int size;
852 int order;
853 u32 revision_id;
1c3d14fe
YS		 854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
f78e0e2e 856 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 857 u32 vmexit_ctrl;
858 u32 vmentry_ctrl;
859} vmcs_config;
6aa8b732 860
efff9e53 861static struct vmx_capability {
d56f546d
SY		 862 u32 ept;
863 u32 vpid;
864} vmx_capability;
865
6aa8b732
AK		 866#define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
872 }
873
772e0318 874static const struct kvm_vmx_segment_field {
6aa8b732
AK		 875 unsigned selector;
876 unsigned base;
877 unsigned limit;
878 unsigned ar_bytes;
879} kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
888};
889
26bb0981
AK		 890static u64 host_efer;
891
6de4f3ad
AK		 892static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
4d56c8a7 894/*
8c06585d 895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 896 * away by decrementing the array size.
897 */
6aa8b732 898static const u32 vmx_msr_index[] = {
05b3e0c2 899#ifdef CONFIG_X86_64
44ea2b17 900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 901#endif
8c06585d 902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 903};
6aa8b732 904
31299944 905static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 910}
911
31299944 912static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 917}
918
31299944 919static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 924}
925
31299944 926static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930}
931
31299944 932static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 933{
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937}
938
31299944 939static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 940{
04547156 941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 942}
943
31299944 944static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 945{
04547156 946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 947}
948
31299944 949static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 950{
04547156 951 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 952}
953
31299944 954static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 955{
04547156
SY		 956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 958}
959
774ead3a 960static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 961{
04547156
SY		 962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964}
965
8d14695f
YZ		 966static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967{
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970}
971
83d4c286
YZ		 972static inline bool cpu_has_vmx_apic_register_virt(void)
973{
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976}
977
c7c9c56c
YZ		 978static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982}
983
01e439be
YZ		 984static inline bool cpu_has_vmx_posted_intr(void)
985{
986 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
987}
988
989static inline bool cpu_has_vmx_apicv(void)
990{
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
994}
995
04547156
SY		 996static inline bool cpu_has_vmx_flexpriority(void)
997{
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1000}
1001
e799794e
MT		 1002static inline bool cpu_has_vmx_ept_execute_only(void)
1003{
31299944 1004 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1005}
1006
e799794e
MT		 1007static inline bool cpu_has_vmx_ept_2m_page(void)
1008{
31299944 1009 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1010}
1011
878403b7
SY		 1012static inline bool cpu_has_vmx_ept_1g_page(void)
1013{
31299944 1014 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1015}
1016
4bc9b982
SY		 1017static inline bool cpu_has_vmx_ept_4levels(void)
1018{
1019 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020}
1021
83c3a331
XH		 1022static inline bool cpu_has_vmx_ept_ad_bits(void)
1023{
1024 return vmx_capability.ept & VMX_EPT_AD_BIT;
1025}
1026
31299944 1027static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1028{
31299944 1029 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1033{
31299944 1034 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1035}
1036
518c8aee
GJ		 1037static inline bool cpu_has_vmx_invvpid_single(void)
1038{
1039 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040}
1041
b9d762fa
GJ		 1042static inline bool cpu_has_vmx_invvpid_global(void)
1043{
1044 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045}
1046
31299944 1047static inline bool cpu_has_vmx_ept(void)
d56f546d 1048{
04547156
SY		 1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1051}
1052
31299944 1053static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057}
1058
31299944 1059static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1060{
1061 return vmcs_config.cpu_based_2nd_exec_ctrl &
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063}
1064
31299944 1065static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1066{
6d3e435e 1067 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1068}
1069
31299944 1070static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1071{
04547156
SY		 1072 return vmcs_config.cpu_based_2nd_exec_ctrl &
1073 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1074}
1075
31299944 1076static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1077{
1078 return vmcs_config.cpu_based_2nd_exec_ctrl &
1079 SECONDARY_EXEC_RDTSCP;
1080}
1081
ad756a16
MJ		 1082static inline bool cpu_has_vmx_invpcid(void)
1083{
1084 return vmcs_config.cpu_based_2nd_exec_ctrl &
1085 SECONDARY_EXEC_ENABLE_INVPCID;
1086}
1087
31299944 1088static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1089{
1090 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f5f48ee1
SY		 1093static inline bool cpu_has_vmx_wbinvd_exit(void)
1094{
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_WBINVD_EXITING;
1097}
1098
abc4fc58
AG		 1099static inline bool cpu_has_vmx_shadow_vmcs(void)
1100{
1101 u64 vmx_msr;
1102 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105 return false;
1106
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_SHADOW_VMCS;
1109}
1110
843e4330
KH		 1111static inline bool cpu_has_vmx_pml(void)
1112{
1113 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114}
1115
04547156
SY		 1116static inline bool report_flexpriority(void)
1117{
1118 return flexpriority_enabled;
1119}
1120
fe3ef05c
NHE		 1121static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122{
1123 return vmcs12->cpu_based_vm_exec_control & bit;
1124}
1125
1126static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127{
1128 return (vmcs12->cpu_based_vm_exec_control &
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130 (vmcs12->secondary_vm_exec_control & bit);
1131}
1132
f5c4368f 1133static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1134{
1135 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136}
1137
f4124500
JK		 1138static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139{
1140 return vmcs12->pin_based_vm_exec_control &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1142}
1143
155a97a3
NHE		 1144static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145{
1146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147}
1148
81dc01f7
WL		 1149static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150{
1151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152 vmx_xsaves_supported();
1153}
1154
f2b93280
WV		 1155static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156{
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158}
1159
82f0dd4b
WV		 1160static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161{
1162 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163}
1164
608406e2
WV		 1165static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166{
1167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168}
1169
705699a1
WV		 1170static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171{
1172 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173}
1174
644d711a
NHE		 1175static inline bool is_exception(u32 intr_info)
1176{
1177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179}
1180
533558bc
JK		 1181static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182 u32 exit_intr_info,
1183 unsigned long exit_qualification);
7c177938
NHE		 1184static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185 struct vmcs12 *vmcs12,
1186 u32 reason, unsigned long qualification);
1187
8b9cf98c 1188static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1189{
1190 int i;
1191
a2fa3e9f 1192 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1194 return i;
1195 return -1;
1196}
1197
2384d2b3
SY		 1198static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199{
1200 struct {
1201 u64 vpid : 16;
1202 u64 rsvd : 48;
1203 u64 gva;
1204 } operand = { vpid, 0, gva };
1205
4ecac3fd 1206 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand), "c"(ext) : "cc", "memory");
1210}
1211
1439442c
SY		 1212static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213{
1214 struct {
1215 u64 eptp, gpa;
1216 } operand = {eptp, gpa};
1217
4ecac3fd 1218 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand), "c" (ext) : "cc", "memory");
1222}
1223
26bb0981 1224static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1225{
1226 int i;
1227
8b9cf98c 1228 i = __find_msr_index(vmx, msr);
a75beee6 1229 if (i >= 0)
a2fa3e9f 1230 return &vmx->guest_msrs[i];
8b6d44c7 1231 return NULL;
7725f0ba
AK		 1232}
1233
6aa8b732
AK		 1234static void vmcs_clear(struct vmcs *vmcs)
1235{
1236 u64 phys_addr = __pa(vmcs);
1237 u8 error;
1238
4ecac3fd 1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1240 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1241 : "cc", "memory");
1242 if (error)
1243 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244 vmcs, phys_addr);
1245}
1246
d462b819
NHE		 1247static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248{
1249 vmcs_clear(loaded_vmcs->vmcs);
1250 loaded_vmcs->cpu = -1;
1251 loaded_vmcs->launched = 0;
1252}
1253
7725b894
DX		 1254static void vmcs_load(struct vmcs *vmcs)
1255{
1256 u64 phys_addr = __pa(vmcs);
1257 u8 error;
1258
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1260 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1261 : "cc", "memory");
1262 if (error)
2844d849 1263 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1264 vmcs, phys_addr);
1265}
1266
8f536b76
ZY		 1267#ifdef CONFIG_KEXEC
1268/*
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1271 * default.
1272 */
1273static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275static inline void crash_enable_local_vmclear(int cpu)
1276{
1277 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278}
1279
1280static inline void crash_disable_local_vmclear(int cpu)
1281{
1282 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283}
1284
1285static inline int crash_local_vmclear_enabled(int cpu)
1286{
1287 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288}
1289
1290static void crash_vmclear_local_loaded_vmcss(void)
1291{
1292 int cpu = raw_smp_processor_id();
1293 struct loaded_vmcs *v;
1294
1295 if (!crash_local_vmclear_enabled(cpu))
1296 return;
1297
1298 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299 loaded_vmcss_on_cpu_link)
1300 vmcs_clear(v->vmcs);
1301}
1302#else
1303static inline void crash_enable_local_vmclear(int cpu) { }
1304static inline void crash_disable_local_vmclear(int cpu) { }
1305#endif /* CONFIG_KEXEC */
1306
d462b819 1307static void __loaded_vmcs_clear(void *arg)
6aa8b732 1308{
d462b819 1309 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1310 int cpu = raw_smp_processor_id();
6aa8b732 1311
d462b819
NHE		 1312 if (loaded_vmcs->cpu != cpu)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1315 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1316 crash_disable_local_vmclear(cpu);
d462b819 1317 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1318
1319 /*
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1324 */
1325 smp_wmb();
1326
d462b819 1327 loaded_vmcs_init(loaded_vmcs);
8f536b76 1328 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1329}
1330
d462b819 1331static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1332{
e6c7d321
XG		 1333 int cpu = loaded_vmcs->cpu;
1334
1335 if (cpu != -1)
1336 smp_call_function_single(cpu,
1337 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1338}
1339
1760dd49 1340static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1341{
1342 if (vmx->vpid == 0)
1343 return;
1344
518c8aee
GJ		 1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1347}
1348
b9d762fa
GJ		 1349static inline void vpid_sync_vcpu_global(void)
1350{
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353}
1354
1355static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356{
1357 if (cpu_has_vmx_invvpid_single())
1760dd49 1358 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1359 else
1360 vpid_sync_vcpu_global();
1361}
1362
1439442c
SY		 1363static inline void ept_sync_global(void)
1364{
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367}
1368
1369static inline void ept_sync_context(u64 eptp)
1370{
089d034e 1371 if (enable_ept) {
1439442c
SY		 1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374 else
1375 ept_sync_global();
1376 }
1377}
1378
96304217 1379static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1380{
5e520e62 1381 unsigned long value;
6aa8b732 1382
5e520e62
AK		 1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1385 return value;
1386}
1387
96304217 1388static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1389{
1390 return vmcs_readl(field);
1391}
1392
96304217 1393static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1394{
1395 return vmcs_readl(field);
1396}
1397
96304217 1398static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1399{
05b3e0c2 1400#ifdef CONFIG_X86_64
6aa8b732
AK		 1401 return vmcs_readl(field);
1402#else
1403 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404#endif
1405}
1406
e52de1b8
AK		 1407static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408{
1409 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411 dump_stack();
1412}
1413
6aa8b732
AK		 1414static void vmcs_writel(unsigned long field, unsigned long value)
1415{
1416 u8 error;
1417
4ecac3fd 1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1419 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1420 if (unlikely(error))
1421 vmwrite_error(field, value);
6aa8b732
AK		 1422}
1423
1424static void vmcs_write16(unsigned long field, u16 value)
1425{
1426 vmcs_writel(field, value);
1427}
1428
1429static void vmcs_write32(unsigned long field, u32 value)
1430{
1431 vmcs_writel(field, value);
1432}
1433
1434static void vmcs_write64(unsigned long field, u64 value)
1435{
6aa8b732 1436 vmcs_writel(field, value);
7682f2d0 1437#ifndef CONFIG_X86_64
6aa8b732
AK		 1438 asm volatile ("");
1439 vmcs_writel(field+1, value >> 32);
1440#endif
1441}
1442
2ab455cc
AL		 1443static void vmcs_clear_bits(unsigned long field, u32 mask)
1444{
1445 vmcs_writel(field, vmcs_readl(field) & ~mask);
1446}
1447
1448static void vmcs_set_bits(unsigned long field, u32 mask)
1449{
1450 vmcs_writel(field, vmcs_readl(field) | mask);
1451}
1452
2961e876
GN		 1453static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454{
1455 vmcs_write32(VM_ENTRY_CONTROLS, val);
1456 vmx->vm_entry_controls_shadow = val;
1457}
1458
1459static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460{
1461 if (vmx->vm_entry_controls_shadow != val)
1462 vm_entry_controls_init(vmx, val);
1463}
1464
1465static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466{
1467 return vmx->vm_entry_controls_shadow;
1468}
1469
1470
1471static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472{
1473 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474}
1475
1476static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477{
1478 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479}
1480
1481static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482{
1483 vmcs_write32(VM_EXIT_CONTROLS, val);
1484 vmx->vm_exit_controls_shadow = val;
1485}
1486
1487static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488{
1489 if (vmx->vm_exit_controls_shadow != val)
1490 vm_exit_controls_init(vmx, val);
1491}
1492
1493static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494{
1495 return vmx->vm_exit_controls_shadow;
1496}
1497
1498
1499static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500{
1501 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502}
1503
1504static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505{
1506 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507}
1508
2fb92db1
AK		 1509static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510{
1511 vmx->segment_cache.bitmask = 0;
1512}
1513
1514static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515 unsigned field)
1516{
1517 bool ret;
1518 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522 vmx->segment_cache.bitmask = 0;
1523 }
1524 ret = vmx->segment_cache.bitmask & mask;
1525 vmx->segment_cache.bitmask |= mask;
1526 return ret;
1527}
1528
1529static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530{
1531 u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535 return *p;
1536}
1537
1538static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539{
1540 ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544 return *p;
1545}
1546
1547static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548{
1549 u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553 return *p;
1554}
1555
1556static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557{
1558 u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562 return *p;
1563}
1564
abd3f2d6
AK		 1565static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566{
1567 u32 eb;
1568
fd7373cc
JK		 1569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571 if ((vcpu->guest_debug &
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574 eb |= 1u << BP_VECTOR;
7ffd92c5 1575 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1576 eb = ~0;
089d034e 1577 if (enable_ept)
1439442c 1578 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1579 if (vcpu->fpu_active)
1580 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1581
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1586 */
1587 if (is_guest_mode(vcpu))
1588 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
abd3f2d6
AK		 1590 vmcs_write32(EXCEPTION_BITMAP, eb);
1591}
1592
2961e876
GN		 1593static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594 unsigned long entry, unsigned long exit)
8bf00a52 1595{
2961e876
GN		 1596 vm_entry_controls_clearbit(vmx, entry);
1597 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1598}
1599
61d2ef2c
AK		 1600static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601{
1602 unsigned i;
1603 struct msr_autoload *m = &vmx->msr_autoload;
1604
8bf00a52
GN		 1605 switch (msr) {
1606 case MSR_EFER:
1607 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1608 clear_atomic_switch_msr_special(vmx,
1609 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1610 VM_EXIT_LOAD_IA32_EFER);
1611 return;
1612 }
1613 break;
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
2961e876 1616 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619 return;
1620 }
1621 break;
110312c8
AK		 1622 }
1623
61d2ef2c
AK		 1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1626 break;
1627
1628 if (i == m->nr)
1629 return;
1630 --m->nr;
1631 m->guest[i] = m->guest[m->nr];
1632 m->host[i] = m->host[m->nr];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635}
1636
2961e876
GN		 1637static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638 unsigned long entry, unsigned long exit,
1639 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640 u64 guest_val, u64 host_val)
8bf00a52
GN		 1641{
1642 vmcs_write64(guest_val_vmcs, guest_val);
1643 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1644 vm_entry_controls_setbit(vmx, entry);
1645 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1646}
1647
61d2ef2c
AK		 1648static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649 u64 guest_val, u64 host_val)
1650{
1651 unsigned i;
1652 struct msr_autoload *m = &vmx->msr_autoload;
1653
8bf00a52
GN		 1654 switch (msr) {
1655 case MSR_EFER:
1656 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1657 add_atomic_switch_msr_special(vmx,
1658 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1659 VM_EXIT_LOAD_IA32_EFER,
1660 GUEST_IA32_EFER,
1661 HOST_IA32_EFER,
1662 guest_val, host_val);
1663 return;
1664 }
1665 break;
1666 case MSR_CORE_PERF_GLOBAL_CTRL:
1667 if (cpu_has_load_perf_global_ctrl) {
2961e876 1668 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 GUEST_IA32_PERF_GLOBAL_CTRL,
1672 HOST_IA32_PERF_GLOBAL_CTRL,
1673 guest_val, host_val);
1674 return;
1675 }
1676 break;
110312c8
AK		 1677 }
1678
61d2ef2c
AK		 1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1681 break;
1682
e7fc6f93 1683 if (i == NR_AUTOLOAD_MSRS) {
60266204 1684 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1685 "Can't add msr %x\n", msr);
1686 return;
1687 } else if (i == m->nr) {
61d2ef2c
AK		 1688 ++m->nr;
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691 }
1692
1693 m->guest[i].index = msr;
1694 m->guest[i].value = guest_val;
1695 m->host[i].index = msr;
1696 m->host[i].value = host_val;
1697}
1698
33ed6329
AK		 1699static void reload_tss(void)
1700{
33ed6329
AK		 1701 /*
1702 * VT restores TR but not its size. Useless.
1703 */
89cbc767 1704 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1705 struct desc_struct *descs;
33ed6329 1706
d359192f 1707 descs = (void *)gdt->address;
33ed6329
AK		 1708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709 load_TR_desc();
33ed6329
AK		 1710}
1711
92c0d900 1712static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1713{
3a34a881 1714 u64 guest_efer;
51c6cf66
AK		 1715 u64 ignore_bits;
1716
f6801dff 1717 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1718
51c6cf66 1719 /*
0fa06071 1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1721 * outside long mode
1722 */
1723 ignore_bits = EFER_NX | EFER_SCE;
1724#ifdef CONFIG_X86_64
1725 ignore_bits |= EFER_LMA | EFER_LME;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer & EFER_LMA)
1728 ignore_bits &= ~(u64)EFER_SCE;
1729#endif
51c6cf66
AK		 1730 guest_efer &= ~ignore_bits;
1731 guest_efer |= host_efer & ignore_bits;
26bb0981 1732 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1734
1735 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1736
1737 /*
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1741 */
1742 if (cpu_has_load_ia32_efer ||
1743 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1744 guest_efer = vmx->vcpu.arch.efer;
1745 if (!(guest_efer & EFER_LMA))
1746 guest_efer &= ~EFER_LME;
54b98bff
AL		 1747 if (guest_efer != host_efer)
1748 add_atomic_switch_msr(vmx, MSR_EFER,
1749 guest_efer, host_efer);
84ad33ef
AK		 1750 return false;
1751 }
1752
26bb0981 1753 return true;
51c6cf66
AK		 1754}
1755
2d49ec72
GN		 1756static unsigned long segment_base(u16 selector)
1757{
89cbc767 1758 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1759 struct desc_struct *d;
1760 unsigned long table_base;
1761 unsigned long v;
1762
1763 if (!(selector & ~3))
1764 return 0;
1765
d359192f 1766 table_base = gdt->address;
2d49ec72
GN		 1767
1768 if (selector & 4) { /* from ldt */
1769 u16 ldt_selector = kvm_read_ldt();
1770
1771 if (!(ldt_selector & ~3))
1772 return 0;
1773
1774 table_base = segment_base(ldt_selector);
1775 }
1776 d = (struct desc_struct *)(table_base + (selector & ~7));
1777 v = get_desc_base(d);
1778#ifdef CONFIG_X86_64
1779 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781#endif
1782 return v;
1783}
1784
1785static inline unsigned long kvm_read_tr_base(void)
1786{
1787 u16 tr;
1788 asm("str %0" : "=g"(tr));
1789 return segment_base(tr);
1790}
1791
04d2cc77 1792static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1793{
04d2cc77 1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1795 int i;
04d2cc77 1796
a2fa3e9f 1797 if (vmx->host_state.loaded)
33ed6329
AK		 1798 return;
1799
a2fa3e9f 1800 vmx->host_state.loaded = 1;
33ed6329
AK		 1801 /*
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1804 */
d6e88aec 1805 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1806 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1807 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1808 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1809 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1810 vmx->host_state.fs_reload_needed = 0;
1811 } else {
33ed6329 1812 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1813 vmx->host_state.fs_reload_needed = 1;
33ed6329 1814 }
9581d442 1815 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1816 if (!(vmx->host_state.gs_sel & 7))
1817 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1818 else {
1819 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1820 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1821 }
1822
b2da15ac
AK		 1823#ifdef CONFIG_X86_64
1824 savesegment(ds, vmx->host_state.ds_sel);
1825 savesegment(es, vmx->host_state.es_sel);
1826#endif
1827
33ed6329
AK		 1828#ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831#else
a2fa3e9f
GH		 1832 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1834#endif
707c0874
AK		 1835
1836#ifdef CONFIG_X86_64
c8770e7b
AK		 1837 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838 if (is_long_mode(&vmx->vcpu))
44ea2b17 1839 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1840#endif
da8999d3
LJ		 1841 if (boot_cpu_has(X86_FEATURE_MPX))
1842 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1843 for (i = 0; i < vmx->save_nmsrs; ++i)
1844 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1845 vmx->guest_msrs[i].data,
1846 vmx->guest_msrs[i].mask);
33ed6329
AK		 1847}
1848
a9b21b62 1849static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1850{
a2fa3e9f 1851 if (!vmx->host_state.loaded)
33ed6329
AK		 1852 return;
1853
e1beb1d3 1854 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1855 vmx->host_state.loaded = 0;
c8770e7b
AK		 1856#ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx->vcpu))
1858 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859#endif
152d3f2f 1860 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1861 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1862#ifdef CONFIG_X86_64
9581d442 1863 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1864#else
1865 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1866#endif
33ed6329 1867 }
0a77fe4c
AK		 1868 if (vmx->host_state.fs_reload_needed)
1869 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1870#ifdef CONFIG_X86_64
1871 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872 loadsegment(ds, vmx->host_state.ds_sel);
1873 loadsegment(es, vmx->host_state.es_sel);
1874 }
b2da15ac 1875#endif
152d3f2f 1876 reload_tss();
44ea2b17 1877#ifdef CONFIG_X86_64
c8770e7b 1878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1879#endif
da8999d3
LJ		 1880 if (vmx->host_state.msr_host_bndcfgs)
1881 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1882 /*
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1885 */
1886 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1887 stts();
89cbc767 1888 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1889}
1890
a9b21b62
AK		 1891static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892{
1893 preempt_disable();
1894 __vmx_load_host_state(vmx);
1895 preempt_enable();
1896}
1897
6aa8b732
AK		 1898/*
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1901 */
15ad7146 1902static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1903{
a2fa3e9f 1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1905 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1906
4610c9cc
DX		 1907 if (!vmm_exclusive)
1908 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1909 else if (vmx->loaded_vmcs->cpu != cpu)
1910 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1911
d462b819
NHE		 1912 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1915 }
1916
d462b819 1917 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1918 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1919 unsigned long sysenter_esp;
1920
a8eeb04a 1921 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1922 local_irq_disable();
8f536b76 1923 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1924
1925 /*
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1929 */
1930 smp_rmb();
1931
d462b819
NHE		 1932 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1934 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1935 local_irq_enable();
1936
6aa8b732
AK		 1937 /*
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1939 * processors.
1940 */
d6e88aec 1941 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1942 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1943
1944 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1946 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1947 }
6aa8b732
AK		 1948}
1949
1950static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951{
a9b21b62 1952 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1953 if (!vmm_exclusive) {
d462b819
NHE		 1954 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955 vcpu->cpu = -1;
4610c9cc
DX		 1956 kvm_cpu_vmxoff();
1957 }
6aa8b732
AK		 1958}
1959
5fd86fcf
AK		 1960static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961{
81231c69
AK		 1962 ulong cr0;
1963
5fd86fcf
AK		 1964 if (vcpu->fpu_active)
1965 return;
1966 vcpu->fpu_active = 1;
81231c69
AK		 1967 cr0 = vmcs_readl(GUEST_CR0);
1968 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1971 update_exception_bitmap(vcpu);
edcafe3c 1972 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1973 if (is_guest_mode(vcpu))
1974 vcpu->arch.cr0_guest_owned_bits &=
1975 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1977}
1978
edcafe3c
AK		 1979static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
fe3ef05c
NHE		 1981/*
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1985 */
1986static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987{
1988 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990}
1991static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992{
1993 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995}
1996
5fd86fcf
AK		 1997static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998{
36cf24e0
NHE		 1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2001 */
edcafe3c 2002 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2003 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2004 update_exception_bitmap(vcpu);
edcafe3c
AK		 2005 vcpu->arch.cr0_guest_owned_bits = 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2007 if (is_guest_mode(vcpu)) {
2008 /*
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2015 */
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018 (vcpu->arch.cr0 & X86_CR0_TS);
2019 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020 } else
2021 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2022}
2023
6aa8b732
AK		 2024static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025{
78ac8b47 2026 unsigned long rflags, save_rflags;
345dcaa8 2027
6de12732
AK		 2028 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030 rflags = vmcs_readl(GUEST_RFLAGS);
2031 if (to_vmx(vcpu)->rmode.vm86_active) {
2032 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035 }
2036 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2037 }
6de12732 2038 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2039}
2040
2041static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042{
6de12732
AK		 2043 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2045 if (to_vmx(vcpu)->rmode.vm86_active) {
2046 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2047 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2048 }
6aa8b732
AK		 2049 vmcs_writel(GUEST_RFLAGS, rflags);
2050}
2051
37ccdcbe 2052static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2053{
2054 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055 int ret = 0;
2056
2057 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2058 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2059 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2060 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2061
37ccdcbe 2062 return ret;
2809f5d2
GC		 2063}
2064
2065static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066{
2067 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068 u32 interruptibility = interruptibility_old;
2069
2070 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
48005f64 2072 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2073 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2074 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2075 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077 if ((interruptibility != interruptibility_old))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079}
2080
6aa8b732
AK		 2081static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082{
2083 unsigned long rip;
6aa8b732 2084
5fdbf976 2085 rip = kvm_rip_read(vcpu);
6aa8b732 2086 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2087 kvm_rip_write(vcpu, rip);
6aa8b732 2088
2809f5d2
GC		 2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2091}
2092
0b6ac343
NHE		 2093/*
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2096 */
e011c663 2097static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2098{
2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
e011c663 2101 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2102 return 0;
2103
533558bc
JK		 2104 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105 vmcs_read32(VM_EXIT_INTR_INFO),
2106 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2107 return 1;
2108}
2109
298101da 2110static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2111 bool has_error_code, u32 error_code,
2112 bool reinject)
298101da 2113{
77ab6db0 2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2115 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2116
e011c663
GN		 2117 if (!reinject && is_guest_mode(vcpu) &&
2118 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2119 return;
2120
8ab2d2e2 2121 if (has_error_code) {
77ab6db0 2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2123 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124 }
77ab6db0 2125
7ffd92c5 2126 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2127 int inc_eip = 0;
2128 if (kvm_exception_is_soft(nr))
2129 inc_eip = vcpu->arch.event_exit_inst_len;
2130 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2132 return;
2133 }
2134
66fd3f7f
GN		 2135 if (kvm_exception_is_soft(nr)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2138 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139 } else
2140 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2143}
2144
4e47c7a6
SY		 2145static bool vmx_rdtscp_supported(void)
2146{
2147 return cpu_has_vmx_rdtscp();
2148}
2149
ad756a16
MJ		 2150static bool vmx_invpcid_supported(void)
2151{
2152 return cpu_has_vmx_invpcid() && enable_ept;
2153}
2154
a75beee6
ED		 2155/*
2156 * Swap MSR entry in host/guest MSR entry array.
2157 */
8b9cf98c 2158static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2159{
26bb0981 2160 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2161
2162 tmp = vmx->guest_msrs[to];
2163 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2165}
2166
8d14695f
YZ		 2167static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168{
2169 unsigned long *msr_bitmap;
2170
670125bd
WV		 2171 if (is_guest_mode(vcpu))
2172 msr_bitmap = vmx_msr_bitmap_nested;
2173 else if (irqchip_in_kernel(vcpu->kvm) &&
2174 apic_x2apic_mode(vcpu->arch.apic)) {
8d14695f
YZ		 2175 if (is_long_mode(vcpu))
2176 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2177 else
2178 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2179 } else {
2180 if (is_long_mode(vcpu))
2181 msr_bitmap = vmx_msr_bitmap_longmode;
2182 else
2183 msr_bitmap = vmx_msr_bitmap_legacy;
2184 }
2185
2186 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2187}
2188
e38aea3e
AK		 2189/*
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2193 */
8b9cf98c 2194static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2195{
26bb0981 2196 int save_nmsrs, index;
e38aea3e 2197
a75beee6
ED		 2198 save_nmsrs = 0;
2199#ifdef CONFIG_X86_64
8b9cf98c 2200 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2201 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2202 if (index >= 0)
8b9cf98c
RR		 2203 move_msr_up(vmx, index, save_nmsrs++);
2204 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2205 if (index >= 0)
8b9cf98c
RR		 2206 move_msr_up(vmx, index, save_nmsrs++);
2207 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2208 if (index >= 0)
8b9cf98c 2209 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2210 index = __find_msr_index(vmx, MSR_TSC_AUX);
2211 if (index >= 0 && vmx->rdtscp_enabled)
2212 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2213 /*
8c06585d 2214 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2215 * if efer.sce is enabled.
2216 */
8c06585d 2217 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2218 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2219 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2220 }
2221#endif
92c0d900
AK		 2222 index = __find_msr_index(vmx, MSR_EFER);
2223 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2224 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2225
26bb0981 2226 vmx->save_nmsrs = save_nmsrs;
5897297b 2227
8d14695f
YZ		 2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2230}
2231
6aa8b732
AK		 2232/*
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2235 */
2236static u64 guest_read_tsc(void)
2237{
2238 u64 host_tsc, tsc_offset;
2239
2240 rdtscll(host_tsc);
2241 tsc_offset = vmcs_read64(TSC_OFFSET);
2242 return host_tsc + tsc_offset;
2243}
2244
d5c1785d
NHE		 2245/*
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2248 */
48d89b92 2249static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2250{
886b470c 2251 u64 tsc_offset;
d5c1785d 2252
d5c1785d
NHE		 2253 tsc_offset = is_guest_mode(vcpu) ?
2254 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2255 vmcs_read64(TSC_OFFSET);
2256 return host_tsc + tsc_offset;
2257}
2258
4051b188 2259/*
cc578287
ZA		 2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
4051b188 2262 */
cc578287 2263static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2264{
cc578287
ZA		 2265 if (!scale)
2266 return;
2267
2268 if (user_tsc_khz > tsc_khz) {
2269 vcpu->arch.tsc_catchup = 1;
2270 vcpu->arch.tsc_always_catchup = 1;
2271 } else
2272 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2273}
2274
ba904635
WA		 2275static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2276{
2277 return vmcs_read64(TSC_OFFSET);
2278}
2279
6aa8b732 2280/*
99e3e30a 2281 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2282 */
99e3e30a 2283static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2284{
27fc51b2 2285 if (is_guest_mode(vcpu)) {
7991825b 2286 /*
27fc51b2
NHE		 2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
7991825b 2291 */
27fc51b2
NHE		 2292 struct vmcs12 *vmcs12;
2293 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12 = get_vmcs12(vcpu);
2296 vmcs_write64(TSC_OFFSET, offset +
2297 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2298 vmcs12->tsc_offset : 0));
2299 } else {
489223ed
YY		 2300 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2301 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2302 vmcs_write64(TSC_OFFSET, offset);
2303 }
6aa8b732
AK		 2304}
2305
f1e2b260 2306static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2307{
2308 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2309
e48672fa 2310 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2311 if (is_guest_mode(vcpu)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2314 } else
2315 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2316 offset + adjustment);
e48672fa
ZA		 2317}
2318
857e4099
JR		 2319static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2320{
2321 return target_tsc - native_read_tsc();
2322}
2323
801d3424
NHE		 2324static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2325{
2326 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2327 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2328}
2329
2330/*
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2335 */
2336static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2337{
2338 return nested && guest_cpuid_has_vmx(vcpu);
2339}
2340
b87a51ae
NHE		 2341/*
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
b87a51ae 2350 */
b9c237bb 2351static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2352{
2353 /*
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2366 */
2367
2368 /* pin-based controls */
eabeaacc 2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2370 vmx->nested.nested_vmx_pinbased_ctls_low,
2371 vmx->nested.nested_vmx_pinbased_ctls_high);
2372 vmx->nested.nested_vmx_pinbased_ctls_low |=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2374 vmx->nested.nested_vmx_pinbased_ctls_high &=
2375 PIN_BASED_EXT_INTR_MASK |
2376 PIN_BASED_NMI_EXITING |
2377 PIN_BASED_VIRTUAL_NMIS;
2378 vmx->nested.nested_vmx_pinbased_ctls_high |=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2380 PIN_BASED_VMX_PREEMPTION_TIMER;
705699a1
WV		 2381 if (vmx_vm_has_apicv(vmx->vcpu.kvm))
2382 vmx->nested.nested_vmx_pinbased_ctls_high |=
2383 PIN_BASED_POSTED_INTR;
b87a51ae 2384
3dbcd8da 2385 /* exit controls */
c0dfee58 2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2387 vmx->nested.nested_vmx_exit_ctls_low,
2388 vmx->nested.nested_vmx_exit_ctls_high);
2389 vmx->nested.nested_vmx_exit_ctls_low =
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2391
b9c237bb 2392 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2393#ifdef CONFIG_X86_64
c0dfee58 2394 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2395#endif
f4124500 2396 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2397 vmx->nested.nested_vmx_exit_ctls_high |=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2399 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2401
36be0b9d 2402 if (vmx_mpx_supported())
b9c237bb 2403 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2404
2996fca0 2405 /* We support free control of debug control saving. */
b9c237bb
WV		 2406 vmx->nested.nested_vmx_true_exit_ctls_low =
2407 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2409
b87a51ae
NHE		 2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2412 vmx->nested.nested_vmx_entry_ctls_low,
2413 vmx->nested.nested_vmx_entry_ctls_high);
2414 vmx->nested.nested_vmx_entry_ctls_low =
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2416 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2417#ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE |
2419#endif
2420 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2421 vmx->nested.nested_vmx_entry_ctls_high |=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2423 if (vmx_mpx_supported())
b9c237bb 2424 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2425
2996fca0 2426 /* We support free control of debug control loading. */
b9c237bb
WV		 2427 vmx->nested.nested_vmx_true_entry_ctls_low =
2428 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2430
b87a51ae
NHE		 2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2433 vmx->nested.nested_vmx_procbased_ctls_low,
2434 vmx->nested.nested_vmx_procbased_ctls_high);
2435 vmx->nested.nested_vmx_procbased_ctls_low =
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2437 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2438 CPU_BASED_VIRTUAL_INTR_PENDING |
2439 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2440 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2441 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2442 CPU_BASED_CR3_STORE_EXITING |
2443#ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2445#endif
2446 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2447 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2448 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2449 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2450 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2451 /*
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2456 */
b9c237bb
WV		 2457 vmx->nested.nested_vmx_procbased_ctls_high |=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2459 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2460
3dcdf3ec 2461 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2462 vmx->nested.nested_vmx_true_procbased_ctls_low =
2463 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2464 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2465
b87a51ae
NHE		 2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2468 vmx->nested.nested_vmx_secondary_ctls_low,
2469 vmx->nested.nested_vmx_secondary_ctls_high);
2470 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2471 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2473 SECONDARY_EXEC_RDTSCP |
f2b93280 2474 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2475 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7
WL		 2477 SECONDARY_EXEC_WBINVD_EXITING |
2478 SECONDARY_EXEC_XSAVES;
c18911a2 2479
afa61f75
NHE		 2480 if (enable_ept) {
2481 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2482 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2483 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2484 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2485 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2486 VMX_EPT_INVEPT_BIT;
b9c237bb 2487 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2488 /*
4b855078
BD		 2489 * For nested guests, we don't do anything specific
2490 * for single context invalidation. Hence, only advertise
2491 * support for global context invalidation.
afa61f75 2492 */
b9c237bb 2493 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2494 } else
b9c237bb 2495 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2496
0790ec17
RK		 2497 if (enable_unrestricted_guest)
2498 vmx->nested.nested_vmx_secondary_ctls_high |=
2499 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2500
c18911a2 2501 /* miscellaneous data */
b9c237bb
WV		 2502 rdmsr(MSR_IA32_VMX_MISC,
2503 vmx->nested.nested_vmx_misc_low,
2504 vmx->nested.nested_vmx_misc_high);
2505 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2506 vmx->nested.nested_vmx_misc_low |=
2507 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2508 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2509 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2510}
2511
2512static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2513{
2514 /*
2515 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2516 */
2517 return ((control & high) | low) == control;
2518}
2519
2520static inline u64 vmx_control_msr(u32 low, u32 high)
2521{
2522 return low | ((u64)high << 32);
2523}
2524
cae50139 2525/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2526static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2527{
b9c237bb
WV		 2528 struct vcpu_vmx *vmx = to_vmx(vcpu);
2529
b87a51ae 2530 switch (msr_index) {
b87a51ae
NHE		 2531 case MSR_IA32_VMX_BASIC:
2532 /*
2533 * This MSR reports some information about VMX support. We
2534 * should return information about the VMX we emulate for the
2535 * guest, and the VMCS structure we give it - not about the
2536 * VMX support of the underlying hardware.
2537 */
3dbcd8da 2538 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2539 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2540 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2541 break;
2542 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2543 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2544 *pdata = vmx_control_msr(
2545 vmx->nested.nested_vmx_pinbased_ctls_low,
2546 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2547 break;
2548 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2549 *pdata = vmx_control_msr(
2550 vmx->nested.nested_vmx_true_procbased_ctls_low,
2551 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2552 break;
b87a51ae 2553 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2554 *pdata = vmx_control_msr(
2555 vmx->nested.nested_vmx_procbased_ctls_low,
2556 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2557 break;
2558 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2559 *pdata = vmx_control_msr(
2560 vmx->nested.nested_vmx_true_exit_ctls_low,
2561 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2562 break;
b87a51ae 2563 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2564 *pdata = vmx_control_msr(
2565 vmx->nested.nested_vmx_exit_ctls_low,
2566 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2567 break;
2568 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2569 *pdata = vmx_control_msr(
2570 vmx->nested.nested_vmx_true_entry_ctls_low,
2571 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2572 break;
b87a51ae 2573 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2574 *pdata = vmx_control_msr(
2575 vmx->nested.nested_vmx_entry_ctls_low,
2576 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2577 break;
2578 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2579 *pdata = vmx_control_msr(
2580 vmx->nested.nested_vmx_misc_low,
2581 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2582 break;
2583 /*
2584 * These MSRs specify bits which the guest must keep fixed (on or off)
2585 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586 * We picked the standard core2 setting.
2587 */
2588#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2590 case MSR_IA32_VMX_CR0_FIXED0:
2591 *pdata = VMXON_CR0_ALWAYSON;
2592 break;
2593 case MSR_IA32_VMX_CR0_FIXED1:
2594 *pdata = -1ULL;
2595 break;
2596 case MSR_IA32_VMX_CR4_FIXED0:
2597 *pdata = VMXON_CR4_ALWAYSON;
2598 break;
2599 case MSR_IA32_VMX_CR4_FIXED1:
2600 *pdata = -1ULL;
2601 break;
2602 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2603 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2604 break;
2605 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2606 *pdata = vmx_control_msr(
2607 vmx->nested.nested_vmx_secondary_ctls_low,
2608 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2609 break;
2610 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2611 /* Currently, no nested vpid support */
b9c237bb 2612 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2613 break;
2614 default:
b87a51ae 2615 return 1;
b3897a49
NHE		 2616 }
2617
b87a51ae
NHE		 2618 return 0;
2619}
2620
6aa8b732
AK		 2621/*
2622 * Reads an msr value (of 'msr_index') into 'pdata'.
2623 * Returns 0 on success, non-0 otherwise.
2624 * Assumes vcpu_load() was already called.
2625 */
2626static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2627{
2628 u64 data;
26bb0981 2629 struct shared_msr_entry *msr;
6aa8b732
AK		 2630
2631 if (!pdata) {
2632 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2633 return -EINVAL;
2634 }
2635
2636 switch (msr_index) {
05b3e0c2 2637#ifdef CONFIG_X86_64
6aa8b732
AK		 2638 case MSR_FS_BASE:
2639 data = vmcs_readl(GUEST_FS_BASE);
2640 break;
2641 case MSR_GS_BASE:
2642 data = vmcs_readl(GUEST_GS_BASE);
2643 break;
44ea2b17
AK		 2644 case MSR_KERNEL_GS_BASE:
2645 vmx_load_host_state(to_vmx(vcpu));
2646 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2647 break;
26bb0981 2648#endif
6aa8b732 2649 case MSR_EFER:
3bab1f5d 2650 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2651 case MSR_IA32_TSC:
6aa8b732
AK		 2652 data = guest_read_tsc();
2653 break;
2654 case MSR_IA32_SYSENTER_CS:
2655 data = vmcs_read32(GUEST_SYSENTER_CS);
2656 break;
2657 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2658 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2659 break;
2660 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2661 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2662 break;
0dd376e7 2663 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2664 if (!vmx_mpx_supported())
2665 return 1;
0dd376e7
LJ		 2666 data = vmcs_read64(GUEST_BNDCFGS);
2667 break;
cae50139
JK		 2668 case MSR_IA32_FEATURE_CONTROL:
2669 if (!nested_vmx_allowed(vcpu))
2670 return 1;
2671 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2672 break;
2673 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2674 if (!nested_vmx_allowed(vcpu))
2675 return 1;
2676 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2677 case MSR_IA32_XSS:
2678 if (!vmx_xsaves_supported())
2679 return 1;
2680 data = vcpu->arch.ia32_xss;
2681 break;
4e47c7a6
SY		 2682 case MSR_TSC_AUX:
2683 if (!to_vmx(vcpu)->rdtscp_enabled)
2684 return 1;
2685 /* Otherwise falls through */
6aa8b732 2686 default:
8b9cf98c 2687 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2688 if (msr) {
2689 data = msr->data;
2690 break;
6aa8b732 2691 }
3bab1f5d 2692 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2693 }
2694
2695 *pdata = data;
2696 return 0;
2697}
2698
cae50139
JK		 2699static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2700
6aa8b732
AK		 2701/*
2702 * Writes msr value into into the appropriate "register".
2703 * Returns 0 on success, non-0 otherwise.
2704 * Assumes vcpu_load() was already called.
2705 */
8fe8ab46 2706static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2707{
a2fa3e9f 2708 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2709 struct shared_msr_entry *msr;
2cc51560 2710 int ret = 0;
8fe8ab46
WA		 2711 u32 msr_index = msr_info->index;
2712 u64 data = msr_info->data;
2cc51560 2713
6aa8b732 2714 switch (msr_index) {
3bab1f5d 2715 case MSR_EFER:
8fe8ab46 2716 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2717 break;
16175a79 2718#ifdef CONFIG_X86_64
6aa8b732 2719 case MSR_FS_BASE:
2fb92db1 2720 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2721 vmcs_writel(GUEST_FS_BASE, data);
2722 break;
2723 case MSR_GS_BASE:
2fb92db1 2724 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2725 vmcs_writel(GUEST_GS_BASE, data);
2726 break;
44ea2b17
AK		 2727 case MSR_KERNEL_GS_BASE:
2728 vmx_load_host_state(vmx);
2729 vmx->msr_guest_kernel_gs_base = data;
2730 break;
6aa8b732
AK		 2731#endif
2732 case MSR_IA32_SYSENTER_CS:
2733 vmcs_write32(GUEST_SYSENTER_CS, data);
2734 break;
2735 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2736 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2737 break;
2738 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2739 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2740 break;
0dd376e7 2741 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2742 if (!vmx_mpx_supported())
2743 return 1;
0dd376e7
LJ		 2744 vmcs_write64(GUEST_BNDCFGS, data);
2745 break;
af24a4e4 2746 case MSR_IA32_TSC:
8fe8ab46 2747 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2748 break;
468d472f
SY		 2749 case MSR_IA32_CR_PAT:
2750 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2751 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2752 return 1;
468d472f
SY		 2753 vmcs_write64(GUEST_IA32_PAT, data);
2754 vcpu->arch.pat = data;
2755 break;
2756 }
8fe8ab46 2757 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2758 break;
ba904635
WA		 2759 case MSR_IA32_TSC_ADJUST:
2760 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2761 break;
cae50139
JK		 2762 case MSR_IA32_FEATURE_CONTROL:
2763 if (!nested_vmx_allowed(vcpu) ||
2764 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2765 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2766 return 1;
2767 vmx->nested.msr_ia32_feature_control = data;
2768 if (msr_info->host_initiated && data == 0)
2769 vmx_leave_nested(vcpu);
2770 break;
2771 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2772 return 1; /* they are read-only */
20300099
WL		 2773 case MSR_IA32_XSS:
2774 if (!vmx_xsaves_supported())
2775 return 1;
2776 /*
2777 * The only supported bit as of Skylake is bit 8, but
2778 * it is not supported on KVM.
2779 */
2780 if (data != 0)
2781 return 1;
2782 vcpu->arch.ia32_xss = data;
2783 if (vcpu->arch.ia32_xss != host_xss)
2784 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2785 vcpu->arch.ia32_xss, host_xss);
2786 else
2787 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2788 break;
4e47c7a6
SY		 2789 case MSR_TSC_AUX:
2790 if (!vmx->rdtscp_enabled)
2791 return 1;
2792 /* Check reserved bit, higher 32 bits should be zero */
2793 if ((data >> 32) != 0)
2794 return 1;
2795 /* Otherwise falls through */
6aa8b732 2796 default:
8b9cf98c 2797 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2798 if (msr) {
8b3c3104 2799 u64 old_msr_data = msr->data;
3bab1f5d 2800 msr->data = data;
2225fd56
AK		 2801 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2802 preempt_disable();
8b3c3104
AH		 2803 ret = kvm_set_shared_msr(msr->index, msr->data,
2804 msr->mask);
2225fd56 2805 preempt_enable();
8b3c3104
AH		 2806 if (ret)
2807 msr->data = old_msr_data;
2225fd56 2808 }
3bab1f5d 2809 break;
6aa8b732 2810 }
8fe8ab46 2811 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2812 }
2813
2cc51560 2814 return ret;
6aa8b732
AK		 2815}
2816
5fdbf976 2817static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2818{
5fdbf976
MT		 2819 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2820 switch (reg) {
2821 case VCPU_REGS_RSP:
2822 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2823 break;
2824 case VCPU_REGS_RIP:
2825 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2826 break;
6de4f3ad
AK		 2827 case VCPU_EXREG_PDPTR:
2828 if (enable_ept)
2829 ept_save_pdptrs(vcpu);
2830 break;
5fdbf976
MT		 2831 default:
2832 break;
2833 }
6aa8b732
AK		 2834}
2835
6aa8b732
AK		 2836static __init int cpu_has_kvm_support(void)
2837{
6210e37b 2838 return cpu_has_vmx();
6aa8b732
AK		 2839}
2840
2841static __init int vmx_disabled_by_bios(void)
2842{
2843 u64 msr;
2844
2845 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2846 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2847 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2848 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2849 && tboot_enabled())
2850 return 1;
23f3e991 2851 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2852 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2853 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2854 && !tboot_enabled()) {
2855 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2856 "activate TXT before enabling KVM\n");
cafd6659 2857 return 1;
f9335afe 2858 }
23f3e991
JC		 2859 /* launched w/o TXT and VMX disabled */
2860 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2861 && !tboot_enabled())
2862 return 1;
cafd6659
SW		 2863 }
2864
2865 return 0;
6aa8b732
AK		 2866}
2867
7725b894
DX		 2868static void kvm_cpu_vmxon(u64 addr)
2869{
2870 asm volatile (ASM_VMX_VMXON_RAX
2871 : : "a"(&addr), "m"(addr)
2872 : "memory", "cc");
2873}
2874
13a34e06 2875static int hardware_enable(void)
6aa8b732
AK		 2876{
2877 int cpu = raw_smp_processor_id();
2878 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2879 u64 old, test_bits;
6aa8b732 2880
1e02ce4c 2881 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2882 return -EBUSY;
2883
d462b819 2884 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2885
2886 /*
2887 * Now we can enable the vmclear operation in kdump
2888 * since the loaded_vmcss_on_cpu list on this cpu
2889 * has been initialized.
2890 *
2891 * Though the cpu is not in VMX operation now, there
2892 * is no problem to enable the vmclear operation
2893 * for the loaded_vmcss_on_cpu list is empty!
2894 */
2895 crash_enable_local_vmclear(cpu);
2896
6aa8b732 2897 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2898
2899 test_bits = FEATURE_CONTROL_LOCKED;
2900 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2901 if (tboot_enabled())
2902 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2903
2904 if ((old & test_bits) != test_bits) {
6aa8b732 2905 /* enable and lock */
cafd6659
SW		 2906 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2907 }
375074cc 2908 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2909
4610c9cc
DX		 2910 if (vmm_exclusive) {
2911 kvm_cpu_vmxon(phys_addr);
2912 ept_sync_global();
2913 }
10474ae8 2914
89cbc767 2915 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2916
10474ae8 2917 return 0;
6aa8b732
AK		 2918}
2919
d462b819 2920static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2921{
2922 int cpu = raw_smp_processor_id();
d462b819 2923 struct loaded_vmcs *v, *n;
543e4243 2924
d462b819
NHE		 2925 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2926 loaded_vmcss_on_cpu_link)
2927 __loaded_vmcs_clear(v);
543e4243
AK		 2928}
2929
710ff4a8
EH		 2930
2931/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2932 * tricks.
2933 */
2934static void kvm_cpu_vmxoff(void)
6aa8b732 2935{
4ecac3fd 2936 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2937}
2938
13a34e06 2939static void hardware_disable(void)
710ff4a8 2940{
4610c9cc 2941 if (vmm_exclusive) {
d462b819 2942 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2943 kvm_cpu_vmxoff();
2944 }
375074cc 2945 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2946}
2947
1c3d14fe 2948static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2949 u32 msr, u32 *result)
1c3d14fe
YS		 2950{
2951 u32 vmx_msr_low, vmx_msr_high;
2952 u32 ctl = ctl_min | ctl_opt;
2953
2954 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2955
2956 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2957 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2958
2959 /* Ensure minimum (required) set of control bits are supported. */
2960 if (ctl_min & ~ctl)
002c7f7c 2961 return -EIO;
1c3d14fe
YS		 2962
2963 *result = ctl;
2964 return 0;
2965}
2966
110312c8
AK		 2967static __init bool allow_1_setting(u32 msr, u32 ctl)
2968{
2969 u32 vmx_msr_low, vmx_msr_high;
2970
2971 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2972 return vmx_msr_high & ctl;
2973}
2974
002c7f7c 2975static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2976{
2977 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2978 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2979 u32 _pin_based_exec_control = 0;
2980 u32 _cpu_based_exec_control = 0;
f78e0e2e 2981 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2982 u32 _vmexit_control = 0;
2983 u32 _vmentry_control = 0;
2984
10166744 2985 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2986#ifdef CONFIG_X86_64
2987 CPU_BASED_CR8_LOAD_EXITING |
2988 CPU_BASED_CR8_STORE_EXITING |
2989#endif
d56f546d
SY		 2990 CPU_BASED_CR3_LOAD_EXITING |
2991 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2992 CPU_BASED_USE_IO_BITMAPS |
2993 CPU_BASED_MOV_DR_EXITING |
a7052897 2994 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2995 CPU_BASED_MWAIT_EXITING |
2996 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2997 CPU_BASED_INVLPG_EXITING |
2998 CPU_BASED_RDPMC_EXITING;
443381a8 2999
f78e0e2e 3000 opt = CPU_BASED_TPR_SHADOW |
25c5f225 3001 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 3002 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 3003 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3004 &_cpu_based_exec_control) < 0)
002c7f7c 3005 return -EIO;
6e5d865c
YS		 3006#ifdef CONFIG_X86_64
3007 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3008 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3009 ~CPU_BASED_CR8_STORE_EXITING;
3010#endif
f78e0e2e 3011 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3012 min2 = 0;
3013 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3014 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3015 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3016 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3017 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3018 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3019 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3020 SECONDARY_EXEC_RDTSCP |
83d4c286 3021 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3022 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3023 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3024 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 3025 SECONDARY_EXEC_XSAVES |
3026 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 3027 if (adjust_vmx_controls(min2, opt2,
3028 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3029 &_cpu_based_2nd_exec_control) < 0)
3030 return -EIO;
3031 }
3032#ifndef CONFIG_X86_64
3033 if (!(_cpu_based_2nd_exec_control &
3034 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3035 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3036#endif
83d4c286
YZ		 3037
3038 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3039 _cpu_based_2nd_exec_control &= ~(
8d14695f 3040 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3041 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3042 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3043
d56f546d 3044 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3045 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3046 enabled */
5fff7d27
GN		 3047 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3048 CPU_BASED_CR3_STORE_EXITING |
3049 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3050 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3051 vmx_capability.ept, vmx_capability.vpid);
3052 }
1c3d14fe 3053
81908bf4 3054 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3055#ifdef CONFIG_X86_64
3056 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3057#endif
a547c6db 3058 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3059 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3060 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3061 &_vmexit_control) < 0)
002c7f7c 3062 return -EIO;
1c3d14fe 3063
01e439be
YZ		 3064 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3065 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3066 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3067 &_pin_based_exec_control) < 0)
3068 return -EIO;
3069
3070 if (!(_cpu_based_2nd_exec_control &
3071 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3072 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3073 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3074
c845f9c6 3075 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3076 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3077 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3078 &_vmentry_control) < 0)
002c7f7c 3079 return -EIO;
6aa8b732 3080
c68876fd 3081 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3082
3083 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3084 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3085 return -EIO;
1c3d14fe
YS		 3086
3087#ifdef CONFIG_X86_64
3088 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3089 if (vmx_msr_high & (1u<<16))
002c7f7c 3090 return -EIO;
1c3d14fe
YS		 3091#endif
3092
3093 /* Require Write-Back (WB) memory type for VMCS accesses. */
3094 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3095 return -EIO;
1c3d14fe 3096
002c7f7c
YS		 3097 vmcs_conf->size = vmx_msr_high & 0x1fff;
3098 vmcs_conf->order = get_order(vmcs_config.size);
3099 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3100
002c7f7c
YS		 3101 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3102 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3103 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3104 vmcs_conf->vmexit_ctrl = _vmexit_control;
3105 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3106
110312c8
AK		 3107 cpu_has_load_ia32_efer =
3108 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3109 VM_ENTRY_LOAD_IA32_EFER)
3110 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3111 VM_EXIT_LOAD_IA32_EFER);
3112
8bf00a52
GN		 3113 cpu_has_load_perf_global_ctrl =
3114 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3115 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3116 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3117 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3118
3119 /*
3120 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3121 * but due to arrata below it can't be used. Workaround is to use
3122 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3123 *
3124 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3125 *
3126 * AAK155 (model 26)
3127 * AAP115 (model 30)
3128 * AAT100 (model 37)
3129 * BC86,AAY89,BD102 (model 44)
3130 * BA97 (model 46)
3131 *
3132 */
3133 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3134 switch (boot_cpu_data.x86_model) {
3135 case 26:
3136 case 30:
3137 case 37:
3138 case 44:
3139 case 46:
3140 cpu_has_load_perf_global_ctrl = false;
3141 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3142 "does not work properly. Using workaround\n");
3143 break;
3144 default:
3145 break;
3146 }
3147 }
3148
20300099
WL		 3149 if (cpu_has_xsaves)
3150 rdmsrl(MSR_IA32_XSS, host_xss);
3151
1c3d14fe 3152 return 0;
c68876fd 3153}
6aa8b732
AK		 3154
3155static struct vmcs *alloc_vmcs_cpu(int cpu)
3156{
3157 int node = cpu_to_node(cpu);
3158 struct page *pages;
3159 struct vmcs *vmcs;
3160
6484eb3e 3161 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3162 if (!pages)
3163 return NULL;
3164 vmcs = page_address(pages);
1c3d14fe
YS		 3165 memset(vmcs, 0, vmcs_config.size);
3166 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3167 return vmcs;
3168}
3169
3170static struct vmcs *alloc_vmcs(void)
3171{
d3b2c338 3172 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3173}
3174
3175static void free_vmcs(struct vmcs *vmcs)
3176{
1c3d14fe 3177 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3178}
3179
d462b819
NHE		 3180/*
3181 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3182 */
3183static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3184{
3185 if (!loaded_vmcs->vmcs)
3186 return;
3187 loaded_vmcs_clear(loaded_vmcs);
3188 free_vmcs(loaded_vmcs->vmcs);
3189 loaded_vmcs->vmcs = NULL;
3190}
3191
39959588 3192static void free_kvm_area(void)
6aa8b732
AK		 3193{
3194 int cpu;
3195
3230bb47 3196 for_each_possible_cpu(cpu) {
6aa8b732 3197 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3198 per_cpu(vmxarea, cpu) = NULL;
3199 }
6aa8b732
AK		 3200}
3201
fe2b201b
BD		 3202static void init_vmcs_shadow_fields(void)
3203{
3204 int i, j;
3205
3206 /* No checks for read only fields yet */
3207
3208 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3209 switch (shadow_read_write_fields[i]) {
3210 case GUEST_BNDCFGS:
3211 if (!vmx_mpx_supported())
3212 continue;
3213 break;
3214 default:
3215 break;
3216 }
3217
3218 if (j < i)
3219 shadow_read_write_fields[j] =
3220 shadow_read_write_fields[i];
3221 j++;
3222 }
3223 max_shadow_read_write_fields = j;
3224
3225 /* shadowed fields guest access without vmexit */
3226 for (i = 0; i < max_shadow_read_write_fields; i++) {
3227 clear_bit(shadow_read_write_fields[i],
3228 vmx_vmwrite_bitmap);
3229 clear_bit(shadow_read_write_fields[i],
3230 vmx_vmread_bitmap);
3231 }
3232 for (i = 0; i < max_shadow_read_only_fields; i++)
3233 clear_bit(shadow_read_only_fields[i],
3234 vmx_vmread_bitmap);
3235}
3236
6aa8b732
AK		 3237static __init int alloc_kvm_area(void)
3238{
3239 int cpu;
3240
3230bb47 3241 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3242 struct vmcs *vmcs;
3243
3244 vmcs = alloc_vmcs_cpu(cpu);
3245 if (!vmcs) {
3246 free_kvm_area();
3247 return -ENOMEM;
3248 }
3249
3250 per_cpu(vmxarea, cpu) = vmcs;
3251 }
3252 return 0;
3253}
3254
14168786
GN		 3255static bool emulation_required(struct kvm_vcpu *vcpu)
3256{
3257 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3258}
3259
91b0aa2c 3260static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3261 struct kvm_segment *save)
6aa8b732 3262{
d99e4152
GN		 3263 if (!emulate_invalid_guest_state) {
3264 /*
3265 * CS and SS RPL should be equal during guest entry according
3266 * to VMX spec, but in reality it is not always so. Since vcpu
3267 * is in the middle of the transition from real mode to
3268 * protected mode it is safe to assume that RPL 0 is a good
3269 * default value.
3270 */
3271 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3272 save->selector &= ~SEGMENT_RPL_MASK;
3273 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3274 save->s = 1;
6aa8b732 3275 }
d99e4152 3276 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3277}
3278
3279static void enter_pmode(struct kvm_vcpu *vcpu)
3280{
3281 unsigned long flags;
a89a8fb9 3282 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3283
d99e4152
GN		 3284 /*
3285 * Update real mode segment cache. It may be not up-to-date if sement
3286 * register was written while vcpu was in a guest mode.
3287 */
3288 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3289 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3290 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3291 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3292 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3293 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3294
7ffd92c5 3295 vmx->rmode.vm86_active = 0;
6aa8b732 3296
2fb92db1
AK		 3297 vmx_segment_cache_clear(vmx);
3298
f5f7b2fe 3299 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3300
3301 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3302 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3303 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3304 vmcs_writel(GUEST_RFLAGS, flags);
3305
66aee91a
RR		 3306 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3307 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3308
3309 update_exception_bitmap(vcpu);
3310
91b0aa2c
GN		 3311 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3312 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3313 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3314 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3315 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3316 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3317}
3318
f5f7b2fe 3319static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3320{
772e0318 3321 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3322 struct kvm_segment var = *save;
3323
3324 var.dpl = 0x3;
3325 if (seg == VCPU_SREG_CS)
3326 var.type = 0x3;
3327
3328 if (!emulate_invalid_guest_state) {
3329 var.selector = var.base >> 4;
3330 var.base = var.base & 0xffff0;
3331 var.limit = 0xffff;
3332 var.g = 0;
3333 var.db = 0;
3334 var.present = 1;
3335 var.s = 1;
3336 var.l = 0;
3337 var.unusable = 0;
3338 var.type = 0x3;
3339 var.avl = 0;
3340 if (save->base & 0xf)
3341 printk_once(KERN_WARNING "kvm: segment base is not "
3342 "paragraph aligned when entering "
3343 "protected mode (seg=%d)", seg);
3344 }
6aa8b732 3345
d99e4152
GN		 3346 vmcs_write16(sf->selector, var.selector);
3347 vmcs_write32(sf->base, var.base);
3348 vmcs_write32(sf->limit, var.limit);
3349 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3350}
3351
3352static void enter_rmode(struct kvm_vcpu *vcpu)
3353{
3354 unsigned long flags;
a89a8fb9 3355 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3356
f5f7b2fe
AK		 3357 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3358 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3359 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3360 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3361 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3362 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3363 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3364
7ffd92c5 3365 vmx->rmode.vm86_active = 1;
6aa8b732 3366
776e58ea
GN		 3367 /*
3368 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3369 * vcpu. Warn the user that an update is overdue.
776e58ea 3370 */
4918c6ca 3371 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3372 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3373 "called before entering vcpu\n");
776e58ea 3374
2fb92db1
AK		 3375 vmx_segment_cache_clear(vmx);
3376
4918c6ca 3377 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3378 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3379 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3380
3381 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3382 vmx->rmode.save_rflags = flags;
6aa8b732 3383
053de044 3384 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3385
3386 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3387 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3388 update_exception_bitmap(vcpu);
3389
d99e4152
GN		 3390 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3391 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3392 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3393 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3394 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3395 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3396
8668a3c4 3397 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3398}
3399
401d10de
AS		 3400static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3401{
3402 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3403 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3404
3405 if (!msr)
3406 return;
401d10de 3407
44ea2b17
AK		 3408 /*
3409 * Force kernel_gs_base reloading before EFER changes, as control
3410 * of this msr depends on is_long_mode().
3411 */
3412 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3413 vcpu->arch.efer = efer;
401d10de 3414 if (efer & EFER_LMA) {
2961e876 3415 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3416 msr->data = efer;
3417 } else {
2961e876 3418 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3419
3420 msr->data = efer & ~EFER_LME;
3421 }
3422 setup_msrs(vmx);
3423}
3424
05b3e0c2 3425#ifdef CONFIG_X86_64
6aa8b732
AK		 3426
3427static void enter_lmode(struct kvm_vcpu *vcpu)
3428{
3429 u32 guest_tr_ar;
3430
2fb92db1
AK		 3431 vmx_segment_cache_clear(to_vmx(vcpu));
3432
6aa8b732
AK		 3433 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3434 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3435 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3436 __func__);
6aa8b732
AK		 3437 vmcs_write32(GUEST_TR_AR_BYTES,
3438 (guest_tr_ar & ~AR_TYPE_MASK)
3439 | AR_TYPE_BUSY_64_TSS);
3440 }
da38f438 3441 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3442}
3443
3444static void exit_lmode(struct kvm_vcpu *vcpu)
3445{
2961e876 3446 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3447 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3448}
3449
3450#endif
3451
2384d2b3
SY		 3452static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3453{
b9d762fa 3454 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3455 if (enable_ept) {
3456 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3457 return;
4e1096d2 3458 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3459 }
2384d2b3
SY		 3460}
3461
e8467fda
AK		 3462static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3463{
3464 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3465
3466 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3467 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3468}
3469
aff48baa
AK		 3470static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3471{
3472 if (enable_ept && is_paging(vcpu))
3473 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3474 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3475}
3476
25c4c276 3477static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3478{
fc78f519
AK		 3479 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3480
3481 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3482 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3483}
3484
1439442c
SY		 3485static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3486{
d0d538b9
GN		 3487 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3488
6de4f3ad
AK		 3489 if (!test_bit(VCPU_EXREG_PDPTR,
3490 (unsigned long *)&vcpu->arch.regs_dirty))
3491 return;
3492
1439442c 3493 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3494 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3495 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3496 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3497 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3498 }
3499}
3500
8f5d549f
AK		 3501static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3502{
d0d538b9
GN		 3503 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3504
8f5d549f 3505 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3506 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3507 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3508 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3509 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3510 }
6de4f3ad
AK		 3511
3512 __set_bit(VCPU_EXREG_PDPTR,
3513 (unsigned long *)&vcpu->arch.regs_avail);
3514 __set_bit(VCPU_EXREG_PDPTR,
3515 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3516}
3517
5e1746d6 3518static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3519
3520static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3521 unsigned long cr0,
3522 struct kvm_vcpu *vcpu)
3523{
5233dd51
MT		 3524 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3525 vmx_decache_cr3(vcpu);
1439442c
SY		 3526 if (!(cr0 & X86_CR0_PG)) {
3527 /* From paging/starting to nonpaging */
3528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3529 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3530 (CPU_BASED_CR3_LOAD_EXITING |
3531 CPU_BASED_CR3_STORE_EXITING));
3532 vcpu->arch.cr0 = cr0;
fc78f519 3533 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3534 } else if (!is_paging(vcpu)) {
3535 /* From nonpaging to paging */
3536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3537 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3538 ~(CPU_BASED_CR3_LOAD_EXITING |
3539 CPU_BASED_CR3_STORE_EXITING));
3540 vcpu->arch.cr0 = cr0;
fc78f519 3541 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3542 }
95eb84a7
SY		 3543
3544 if (!(cr0 & X86_CR0_WP))
3545 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3546}
3547
6aa8b732
AK		 3548static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3549{
7ffd92c5 3550 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3551 unsigned long hw_cr0;
3552
5037878e 3553 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3554 if (enable_unrestricted_guest)
5037878e 3555 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3556 else {
5037878e 3557 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3558
218e763f
GN		 3559 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3560 enter_pmode(vcpu);
6aa8b732 3561
218e763f
GN		 3562 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3563 enter_rmode(vcpu);
3564 }
6aa8b732 3565
05b3e0c2 3566#ifdef CONFIG_X86_64
f6801dff 3567 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3568 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3569 enter_lmode(vcpu);
707d92fa 3570 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3571 exit_lmode(vcpu);
3572 }
3573#endif
3574
089d034e 3575 if (enable_ept)
1439442c
SY		 3576 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3577
02daab21 3578 if (!vcpu->fpu_active)
81231c69 3579 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3580
6aa8b732 3581 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3582 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3583 vcpu->arch.cr0 = cr0;
14168786
GN		 3584
3585 /* depends on vcpu->arch.cr0 to be set to a new value */
3586 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3587}
3588
1439442c
SY		 3589static u64 construct_eptp(unsigned long root_hpa)
3590{
3591 u64 eptp;
3592
3593 /* TODO write the value reading from MSR */
3594 eptp = VMX_EPT_DEFAULT_MT |
3595 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3596 if (enable_ept_ad_bits)
3597 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3598 eptp |= (root_hpa & PAGE_MASK);
3599
3600 return eptp;
3601}
3602
6aa8b732
AK		 3603static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3604{
1439442c
SY		 3605 unsigned long guest_cr3;
3606 u64 eptp;
3607
3608 guest_cr3 = cr3;
089d034e 3609 if (enable_ept) {
1439442c
SY		 3610 eptp = construct_eptp(cr3);
3611 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3612 if (is_paging(vcpu) || is_guest_mode(vcpu))
3613 guest_cr3 = kvm_read_cr3(vcpu);
3614 else
3615 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3616 ept_load_pdptrs(vcpu);
1439442c
SY		 3617 }
3618
2384d2b3 3619 vmx_flush_tlb(vcpu);
1439442c 3620 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3621}
3622
5e1746d6 3623static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3624{
085e68ee
BS		 3625 /*
3626 * Pass through host's Machine Check Enable value to hw_cr4, which
3627 * is in force while we are in guest mode. Do not let guests control
3628 * this bit, even if host CR4.MCE == 0.
3629 */
3630 unsigned long hw_cr4 =
3631 (cr4_read_shadow() & X86_CR4_MCE) |
3632 (cr4 & ~X86_CR4_MCE) |
3633 (to_vmx(vcpu)->rmode.vm86_active ?
3634 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3635
5e1746d6
NHE		 3636 if (cr4 & X86_CR4_VMXE) {
3637 /*
3638 * To use VMXON (and later other VMX instructions), a guest
3639 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3640 * So basically the check on whether to allow nested VMX
3641 * is here.
3642 */
3643 if (!nested_vmx_allowed(vcpu))
3644 return 1;
1a0d74e6
JK		 3645 }
3646 if (to_vmx(vcpu)->nested.vmxon &&
3647 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3648 return 1;
3649
ad312c7c 3650 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3651 if (enable_ept) {
3652 if (!is_paging(vcpu)) {
3653 hw_cr4 &= ~X86_CR4_PAE;
3654 hw_cr4 |= X86_CR4_PSE;
c08800a5 3655 /*
e1e746b3
FW		 3656 * SMEP/SMAP is disabled if CPU is in non-paging mode
3657 * in hardware. However KVM always uses paging mode to
c08800a5 3658 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3659 * To emulate this behavior, SMEP/SMAP needs to be
3660 * manually disabled when guest switches to non-paging
3661 * mode.
c08800a5 3662 */
e1e746b3 3663 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3664 } else if (!(cr4 & X86_CR4_PAE)) {
3665 hw_cr4 &= ~X86_CR4_PAE;
3666 }
3667 }
1439442c
SY		 3668
3669 vmcs_writel(CR4_READ_SHADOW, cr4);
3670 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3671 return 0;
6aa8b732
AK		 3672}
3673
6aa8b732
AK		 3674static void vmx_get_segment(struct kvm_vcpu *vcpu,
3675 struct kvm_segment *var, int seg)
3676{
a9179499 3677 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3678 u32 ar;
3679
c6ad1153 3680 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3681 *var = vmx->rmode.segs[seg];
a9179499 3682 if (seg == VCPU_SREG_TR
2fb92db1 3683 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3684 return;
1390a28b
AK		 3685 var->base = vmx_read_guest_seg_base(vmx, seg);
3686 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3687 return;
a9179499 3688 }
2fb92db1
AK		 3689 var->base = vmx_read_guest_seg_base(vmx, seg);
3690 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3691 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3692 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3693 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3694 var->type = ar & 15;
3695 var->s = (ar >> 4) & 1;
3696 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3697 /*
3698 * Some userspaces do not preserve unusable property. Since usable
3699 * segment has to be present according to VMX spec we can use present
3700 * property to amend userspace bug by making unusable segment always
3701 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3702 * segment as unusable.
3703 */
3704 var->present = !var->unusable;
6aa8b732
AK		 3705 var->avl = (ar >> 12) & 1;
3706 var->l = (ar >> 13) & 1;
3707 var->db = (ar >> 14) & 1;
3708 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3709}
3710
a9179499
AK		 3711static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3712{
a9179499
AK		 3713 struct kvm_segment s;
3714
3715 if (to_vmx(vcpu)->rmode.vm86_active) {
3716 vmx_get_segment(vcpu, &s, seg);
3717 return s.base;
3718 }
2fb92db1 3719 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3720}
3721
b09408d0 3722static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3723{
b09408d0
MT		 3724 struct vcpu_vmx *vmx = to_vmx(vcpu);
3725
ae9fedc7 3726 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3727 return 0;
ae9fedc7
PB		 3728 else {
3729 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3730 return AR_DPL(ar);
69c73028 3731 }
69c73028
AK		 3732}
3733
653e3108 3734static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3735{
6aa8b732
AK		 3736 u32 ar;
3737
f0495f9b 3738 if (var->unusable || !var->present)
6aa8b732
AK		 3739 ar = 1 << 16;
3740 else {
3741 ar = var->type & 15;
3742 ar |= (var->s & 1) << 4;
3743 ar |= (var->dpl & 3) << 5;
3744 ar |= (var->present & 1) << 7;
3745 ar |= (var->avl & 1) << 12;
3746 ar |= (var->l & 1) << 13;
3747 ar |= (var->db & 1) << 14;
3748 ar |= (var->g & 1) << 15;
3749 }
653e3108
AK		 3750
3751 return ar;
3752}
3753
3754static void vmx_set_segment(struct kvm_vcpu *vcpu,
3755 struct kvm_segment *var, int seg)
3756{
7ffd92c5 3757 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3758 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3759
2fb92db1
AK		 3760 vmx_segment_cache_clear(vmx);
3761
1ecd50a9
GN		 3762 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3763 vmx->rmode.segs[seg] = *var;
3764 if (seg == VCPU_SREG_TR)
3765 vmcs_write16(sf->selector, var->selector);
3766 else if (var->s)
3767 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3768 goto out;
653e3108 3769 }
1ecd50a9 3770
653e3108
AK		 3771 vmcs_writel(sf->base, var->base);
3772 vmcs_write32(sf->limit, var->limit);
3773 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3774
3775 /*
3776 * Fix the "Accessed" bit in AR field of segment registers for older
3777 * qemu binaries.
3778 * IA32 arch specifies that at the time of processor reset the
3779 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3780 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3781 * state vmexit when "unrestricted guest" mode is turned on.
3782 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3783 * tree. Newer qemu binaries with that qemu fix would not need this
3784 * kvm hack.
3785 */
3786 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3787 var->type |= 0x1; /* Accessed */
3a624e29 3788
f924d66d 3789 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3790
3791out:
98eb2f8b 3792 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3793}
3794
6aa8b732
AK		 3795static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3796{
2fb92db1 3797 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3798
3799 *db = (ar >> 14) & 1;
3800 *l = (ar >> 13) & 1;
3801}
3802
89a27f4d 3803static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3804{
89a27f4d
GN		 3805 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3806 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3807}
3808
89a27f4d 3809static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3810{
89a27f4d
GN		 3811 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3812 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3813}
3814
89a27f4d 3815static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3816{
89a27f4d
GN		 3817 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3818 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3819}
3820
89a27f4d 3821static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3822{
89a27f4d
GN		 3823 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3824 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3825}
3826
648dfaa7
MG		 3827static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3828{
3829 struct kvm_segment var;
3830 u32 ar;
3831
3832 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3833 var.dpl = 0x3;
0647f4aa
GN		 3834 if (seg == VCPU_SREG_CS)
3835 var.type = 0x3;
648dfaa7
MG		 3836 ar = vmx_segment_access_rights(&var);
3837
3838 if (var.base != (var.selector << 4))
3839 return false;
89efbed0 3840 if (var.limit != 0xffff)
648dfaa7 3841 return false;
07f42f5f 3842 if (ar != 0xf3)
648dfaa7
MG		 3843 return false;
3844
3845 return true;
3846}
3847
3848static bool code_segment_valid(struct kvm_vcpu *vcpu)
3849{
3850 struct kvm_segment cs;
3851 unsigned int cs_rpl;
3852
3853 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3854 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3855
1872a3f4
AK		 3856 if (cs.unusable)
3857 return false;
648dfaa7
MG		 3858 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3859 return false;
3860 if (!cs.s)
3861 return false;
1872a3f4 3862 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3863 if (cs.dpl > cs_rpl)
3864 return false;
1872a3f4 3865 } else {
648dfaa7
MG		 3866 if (cs.dpl != cs_rpl)
3867 return false;
3868 }
3869 if (!cs.present)
3870 return false;
3871
3872 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3873 return true;
3874}
3875
3876static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3877{
3878 struct kvm_segment ss;
3879 unsigned int ss_rpl;
3880
3881 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3882 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3883
1872a3f4
AK		 3884 if (ss.unusable)
3885 return true;
3886 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3887 return false;
3888 if (!ss.s)
3889 return false;
3890 if (ss.dpl != ss_rpl) /* DPL != RPL */
3891 return false;
3892 if (!ss.present)
3893 return false;
3894
3895 return true;
3896}
3897
3898static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3899{
3900 struct kvm_segment var;
3901 unsigned int rpl;
3902
3903 vmx_get_segment(vcpu, &var, seg);
b32a9918 3904 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3905
1872a3f4
AK		 3906 if (var.unusable)
3907 return true;
648dfaa7
MG		 3908 if (!var.s)
3909 return false;
3910 if (!var.present)
3911 return false;
3912 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3913 if (var.dpl < rpl) /* DPL < RPL */
3914 return false;
3915 }
3916
3917 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3918 * rights flags
3919 */
3920 return true;
3921}
3922
3923static bool tr_valid(struct kvm_vcpu *vcpu)
3924{
3925 struct kvm_segment tr;
3926
3927 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3928
1872a3f4
AK		 3929 if (tr.unusable)
3930 return false;
b32a9918 3931 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3932 return false;
1872a3f4 3933 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3934 return false;
3935 if (!tr.present)
3936 return false;
3937
3938 return true;
3939}
3940
3941static bool ldtr_valid(struct kvm_vcpu *vcpu)
3942{
3943 struct kvm_segment ldtr;
3944
3945 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3946
1872a3f4
AK		 3947 if (ldtr.unusable)
3948 return true;
b32a9918 3949 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3950 return false;
3951 if (ldtr.type != 2)
3952 return false;
3953 if (!ldtr.present)
3954 return false;
3955
3956 return true;
3957}
3958
3959static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3960{
3961 struct kvm_segment cs, ss;
3962
3963 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3964 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3965
b32a9918
NA		 3966 return ((cs.selector & SEGMENT_RPL_MASK) ==
3967 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3968}
3969
3970/*
3971 * Check if guest state is valid. Returns true if valid, false if
3972 * not.
3973 * We assume that registers are always usable
3974 */
3975static bool guest_state_valid(struct kvm_vcpu *vcpu)
3976{
c5e97c80
GN		 3977 if (enable_unrestricted_guest)
3978 return true;
3979
648dfaa7 3980 /* real mode guest state checks */
f13882d8 3981 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3982 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3983 return false;
3984 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3985 return false;
3986 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3987 return false;
3988 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3989 return false;
3990 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3991 return false;
3992 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3993 return false;
3994 } else {
3995 /* protected mode guest state checks */
3996 if (!cs_ss_rpl_check(vcpu))
3997 return false;
3998 if (!code_segment_valid(vcpu))
3999 return false;
4000 if (!stack_segment_valid(vcpu))
4001 return false;
4002 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4003 return false;
4004 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4005 return false;
4006 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4007 return false;
4008 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4009 return false;
4010 if (!tr_valid(vcpu))
4011 return false;
4012 if (!ldtr_valid(vcpu))
4013 return false;
4014 }
4015 /* TODO:
4016 * - Add checks on RIP
4017 * - Add checks on RFLAGS
4018 */
4019
4020 return true;
4021}
4022
d77c26fc 4023static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4024{
40dcaa9f 4025 gfn_t fn;
195aefde 4026 u16 data = 0;
1f755a82 4027 int idx, r;
6aa8b732 4028
40dcaa9f 4029 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4030 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4031 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4032 if (r < 0)
10589a46 4033 goto out;
195aefde 4034 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4035 r = kvm_write_guest_page(kvm, fn++, &data,
4036 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4037 if (r < 0)
10589a46 4038 goto out;
195aefde
IE		 4039 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4040 if (r < 0)
10589a46 4041 goto out;
195aefde
IE		 4042 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4043 if (r < 0)
10589a46 4044 goto out;
195aefde 4045 data = ~0;
10589a46
MT		 4046 r = kvm_write_guest_page(kvm, fn, &data,
4047 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4048 sizeof(u8));
10589a46 4049out:
40dcaa9f 4050 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4051 return r;
6aa8b732
AK		 4052}
4053
b7ebfb05
SY		 4054static int init_rmode_identity_map(struct kvm *kvm)
4055{
f51770ed 4056 int i, idx, r = 0;
b7ebfb05
SY		 4057 pfn_t identity_map_pfn;
4058 u32 tmp;
4059
089d034e 4060 if (!enable_ept)
f51770ed 4061 return 0;
a255d479
TC		 4062
4063 /* Protect kvm->arch.ept_identity_pagetable_done. */
4064 mutex_lock(&kvm->slots_lock);
4065
f51770ed 4066 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4067 goto out2;
a255d479 4068
b927a3ce 4069 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4070
4071 r = alloc_identity_pagetable(kvm);
f51770ed 4072 if (r < 0)
a255d479
TC		 4073 goto out2;
4074
40dcaa9f 4075 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4076 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4077 if (r < 0)
4078 goto out;
4079 /* Set up identity-mapping pagetable for EPT in real mode */
4080 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4081 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4082 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4083 r = kvm_write_guest_page(kvm, identity_map_pfn,
4084 &tmp, i * sizeof(tmp), sizeof(tmp));
4085 if (r < 0)
4086 goto out;
4087 }
4088 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4089
b7ebfb05 4090out:
40dcaa9f 4091 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4092
4093out2:
4094 mutex_unlock(&kvm->slots_lock);
f51770ed 4095 return r;
b7ebfb05
SY		 4096}
4097
6aa8b732
AK		 4098static void seg_setup(int seg)
4099{
772e0318 4100 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4101 unsigned int ar;
6aa8b732
AK		 4102
4103 vmcs_write16(sf->selector, 0);
4104 vmcs_writel(sf->base, 0);
4105 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4106 ar = 0x93;
4107 if (seg == VCPU_SREG_CS)
4108 ar |= 0x08; /* code segment */
3a624e29
NK		 4109
4110 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4111}
4112
f78e0e2e
SY		 4113static int alloc_apic_access_page(struct kvm *kvm)
4114{
4484141a 4115 struct page *page;
f78e0e2e
SY		 4116 struct kvm_userspace_memory_region kvm_userspace_mem;
4117 int r = 0;
4118
79fac95e 4119 mutex_lock(&kvm->slots_lock);
c24ae0dc 4120 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4121 goto out;
4122 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4123 kvm_userspace_mem.flags = 0;
73a6d941 4124 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4125 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4126 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4127 if (r)
4128 goto out;
72dc67a6 4129
73a6d941 4130 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4131 if (is_error_page(page)) {
4132 r = -EFAULT;
4133 goto out;
4134 }
4135
c24ae0dc
TC		 4136 /*
4137 * Do not pin the page in memory, so that memory hot-unplug
4138 * is able to migrate it.
4139 */
4140 put_page(page);
4141 kvm->arch.apic_access_page_done = true;
f78e0e2e 4142out:
79fac95e 4143 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4144 return r;
4145}
4146
b7ebfb05
SY		 4147static int alloc_identity_pagetable(struct kvm *kvm)
4148{
a255d479
TC		 4149 /* Called with kvm->slots_lock held. */
4150
b7ebfb05
SY		 4151 struct kvm_userspace_memory_region kvm_userspace_mem;
4152 int r = 0;
4153
a255d479
TC		 4154 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4155
b7ebfb05
SY		 4156 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4157 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4158 kvm_userspace_mem.guest_phys_addr =
4159 kvm->arch.ept_identity_map_addr;
b7ebfb05 4160 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4161 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4162
b7ebfb05
SY		 4163 return r;
4164}
4165
2384d2b3
SY		 4166static void allocate_vpid(struct vcpu_vmx *vmx)
4167{
4168 int vpid;
4169
4170 vmx->vpid = 0;
919818ab 4171 if (!enable_vpid)
2384d2b3
SY		 4172 return;
4173 spin_lock(&vmx_vpid_lock);
4174 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4175 if (vpid < VMX_NR_VPIDS) {
4176 vmx->vpid = vpid;
4177 __set_bit(vpid, vmx_vpid_bitmap);
4178 }
4179 spin_unlock(&vmx_vpid_lock);
4180}
4181
cdbecfc3
LJ		 4182static void free_vpid(struct vcpu_vmx *vmx)
4183{
4184 if (!enable_vpid)
4185 return;
4186 spin_lock(&vmx_vpid_lock);
4187 if (vmx->vpid != 0)
4188 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4189 spin_unlock(&vmx_vpid_lock);
4190}
4191
8d14695f
YZ		 4192#define MSR_TYPE_R 1
4193#define MSR_TYPE_W 2
4194static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4195 u32 msr, int type)
25c5f225 4196{
3e7c73e9 4197 int f = sizeof(unsigned long);
25c5f225
SY		 4198
4199 if (!cpu_has_vmx_msr_bitmap())
4200 return;
4201
4202 /*
4203 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4204 * have the write-low and read-high bitmap offsets the wrong way round.
4205 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4206 */
25c5f225 4207 if (msr <= 0x1fff) {
8d14695f
YZ		 4208 if (type & MSR_TYPE_R)
4209 /* read-low */
4210 __clear_bit(msr, msr_bitmap + 0x000 / f);
4211
4212 if (type & MSR_TYPE_W)
4213 /* write-low */
4214 __clear_bit(msr, msr_bitmap + 0x800 / f);
4215
25c5f225
SY		 4216 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4217 msr &= 0x1fff;
8d14695f
YZ		 4218 if (type & MSR_TYPE_R)
4219 /* read-high */
4220 __clear_bit(msr, msr_bitmap + 0x400 / f);
4221
4222 if (type & MSR_TYPE_W)
4223 /* write-high */
4224 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4225
4226 }
4227}
4228
4229static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4230 u32 msr, int type)
4231{
4232 int f = sizeof(unsigned long);
4233
4234 if (!cpu_has_vmx_msr_bitmap())
4235 return;
4236
4237 /*
4238 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4239 * have the write-low and read-high bitmap offsets the wrong way round.
4240 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4241 */
4242 if (msr <= 0x1fff) {
4243 if (type & MSR_TYPE_R)
4244 /* read-low */
4245 __set_bit(msr, msr_bitmap + 0x000 / f);
4246
4247 if (type & MSR_TYPE_W)
4248 /* write-low */
4249 __set_bit(msr, msr_bitmap + 0x800 / f);
4250
4251 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4252 msr &= 0x1fff;
4253 if (type & MSR_TYPE_R)
4254 /* read-high */
4255 __set_bit(msr, msr_bitmap + 0x400 / f);
4256
4257 if (type & MSR_TYPE_W)
4258 /* write-high */
4259 __set_bit(msr, msr_bitmap + 0xc00 / f);
4260
25c5f225 4261 }
25c5f225
SY		 4262}
4263
f2b93280
WV		 4264/*
4265 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4266 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4267 */
4268static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4269 unsigned long *msr_bitmap_nested,
4270 u32 msr, int type)
4271{
4272 int f = sizeof(unsigned long);
4273
4274 if (!cpu_has_vmx_msr_bitmap()) {
4275 WARN_ON(1);
4276 return;
4277 }
4278
4279 /*
4280 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4281 * have the write-low and read-high bitmap offsets the wrong way round.
4282 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4283 */
4284 if (msr <= 0x1fff) {
4285 if (type & MSR_TYPE_R &&
4286 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4287 /* read-low */
4288 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4289
4290 if (type & MSR_TYPE_W &&
4291 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4292 /* write-low */
4293 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4294
4295 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4296 msr &= 0x1fff;
4297 if (type & MSR_TYPE_R &&
4298 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4299 /* read-high */
4300 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4301
4302 if (type & MSR_TYPE_W &&
4303 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4304 /* write-high */
4305 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4306
4307 }
4308}
4309
5897297b
AK		 4310static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4311{
4312 if (!longmode_only)
8d14695f
YZ		 4313 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4314 msr, MSR_TYPE_R | MSR_TYPE_W);
4315 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4316 msr, MSR_TYPE_R | MSR_TYPE_W);
4317}
4318
4319static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4320{
4321 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4322 msr, MSR_TYPE_R);
4323 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4324 msr, MSR_TYPE_R);
4325}
4326
4327static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4328{
4329 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4330 msr, MSR_TYPE_R);
4331 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4332 msr, MSR_TYPE_R);
4333}
4334
4335static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4336{
4337 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4338 msr, MSR_TYPE_W);
4339 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4340 msr, MSR_TYPE_W);
5897297b
AK		 4341}
4342
01e439be
YZ		 4343static int vmx_vm_has_apicv(struct kvm *kvm)
4344{
4345 return enable_apicv && irqchip_in_kernel(kvm);
4346}
4347
705699a1
WV		 4348static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4349{
4350 struct vcpu_vmx *vmx = to_vmx(vcpu);
4351 int max_irr;
4352 void *vapic_page;
4353 u16 status;
4354
4355 if (vmx->nested.pi_desc &&
4356 vmx->nested.pi_pending) {
4357 vmx->nested.pi_pending = false;
4358 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4359 return 0;
4360
4361 max_irr = find_last_bit(
4362 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4363
4364 if (max_irr == 256)
4365 return 0;
4366
4367 vapic_page = kmap(vmx->nested.virtual_apic_page);
4368 if (!vapic_page) {
4369 WARN_ON(1);
4370 return -ENOMEM;
4371 }
4372 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4373 kunmap(vmx->nested.virtual_apic_page);
4374
4375 status = vmcs_read16(GUEST_INTR_STATUS);
4376 if ((u8)max_irr > ((u8)status & 0xff)) {
4377 status &= ~0xff;
4378 status |= (u8)max_irr;
4379 vmcs_write16(GUEST_INTR_STATUS, status);
4380 }
4381 }
4382 return 0;
4383}
4384
21bc8dc5
RK		 4385static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4386{
4387#ifdef CONFIG_SMP
4388 if (vcpu->mode == IN_GUEST_MODE) {
4389 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4390 POSTED_INTR_VECTOR);
4391 return true;
4392 }
4393#endif
4394 return false;
4395}
4396
705699a1
WV		 4397static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4398 int vector)
4399{
4400 struct vcpu_vmx *vmx = to_vmx(vcpu);
4401
4402 if (is_guest_mode(vcpu) &&
4403 vector == vmx->nested.posted_intr_nv) {
4404 /* the PIR and ON have been set by L1. */
21bc8dc5 4405 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4406 /*
4407 * If a posted intr is not recognized by hardware,
4408 * we will accomplish it in the next vmentry.
4409 */
4410 vmx->nested.pi_pending = true;
4411 kvm_make_request(KVM_REQ_EVENT, vcpu);
4412 return 0;
4413 }
4414 return -1;
4415}
a20ed54d
YZ		 4416/*
4417 * Send interrupt to vcpu via posted interrupt way.
4418 * 1. If target vcpu is running(non-root mode), send posted interrupt
4419 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4420 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4421 * interrupt from PIR in next vmentry.
4422 */
4423static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4424{
4425 struct vcpu_vmx *vmx = to_vmx(vcpu);
4426 int r;
4427
705699a1
WV		 4428 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4429 if (!r)
4430 return;
4431
a20ed54d
YZ		 4432 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4433 return;
4434
4435 r = pi_test_and_set_on(&vmx->pi_desc);
4436 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4437 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4438 kvm_vcpu_kick(vcpu);
4439}
4440
4441static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4442{
4443 struct vcpu_vmx *vmx = to_vmx(vcpu);
4444
4445 if (!pi_test_and_clear_on(&vmx->pi_desc))
4446 return;
4447
4448 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4449}
4450
4451static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4452{
4453 return;
4454}
4455
a3a8ff8e
NHE		 4456/*
4457 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4458 * will not change in the lifetime of the guest.
4459 * Note that host-state that does change is set elsewhere. E.g., host-state
4460 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4461 */
a547c6db 4462static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4463{
4464 u32 low32, high32;
4465 unsigned long tmpl;
4466 struct desc_ptr dt;
d974baa3 4467 unsigned long cr4;
a3a8ff8e 4468
b1a74bf8 4469 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4470 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4471
d974baa3 4472 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4473 cr4 = cr4_read_shadow();
d974baa3
AL		 4474 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4475 vmx->host_state.vmcs_host_cr4 = cr4;
4476
a3a8ff8e 4477 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4478#ifdef CONFIG_X86_64
4479 /*
4480 * Load null selectors, so we can avoid reloading them in
4481 * __vmx_load_host_state(), in case userspace uses the null selectors
4482 * too (the expected case).
4483 */
4484 vmcs_write16(HOST_DS_SELECTOR, 0);
4485 vmcs_write16(HOST_ES_SELECTOR, 0);
4486#else
a3a8ff8e
NHE		 4487 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4488 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4489#endif
a3a8ff8e
NHE		 4490 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4491 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4492
4493 native_store_idt(&dt);
4494 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4495 vmx->host_idt_base = dt.address;
a3a8ff8e 4496
83287ea4 4497 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4498
4499 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4500 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4501 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4502 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4503
4504 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4505 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4506 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4507 }
4508}
4509
bf8179a0
NHE		 4510static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4511{
4512 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4513 if (enable_ept)
4514 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4515 if (is_guest_mode(&vmx->vcpu))
4516 vmx->vcpu.arch.cr4_guest_owned_bits &=
4517 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4518 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4519}
4520
01e439be
YZ		 4521static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4522{
4523 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4524
4525 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4526 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4527 return pin_based_exec_ctrl;
4528}
4529
bf8179a0
NHE		 4530static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4531{
4532 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4533
4534 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4535 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4536
bf8179a0
NHE		 4537 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4538 exec_control &= ~CPU_BASED_TPR_SHADOW;
4539#ifdef CONFIG_X86_64
4540 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4541 CPU_BASED_CR8_LOAD_EXITING;
4542#endif
4543 }
4544 if (!enable_ept)
4545 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4546 CPU_BASED_CR3_LOAD_EXITING |
4547 CPU_BASED_INVLPG_EXITING;
4548 return exec_control;
4549}
4550
4551static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4552{
4553 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4554 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4555 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4556 if (vmx->vpid == 0)
4557 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4558 if (!enable_ept) {
4559 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4560 enable_unrestricted_guest = 0;
ad756a16
MJ		 4561 /* Enable INVPCID for non-ept guests may cause performance regression. */
4562 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4563 }
4564 if (!enable_unrestricted_guest)
4565 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4566 if (!ple_gap)
4567 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4568 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4569 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4570 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4571 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4572 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4573 (handle_vmptrld).
4574 We can NOT enable shadow_vmcs here because we don't have yet
4575 a current VMCS12
4576 */
4577 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4578 /* PML is enabled/disabled in creating/destorying vcpu */
4579 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4580
bf8179a0
NHE		 4581 return exec_control;
4582}
4583
ce88decf
XG		 4584static void ept_set_mmio_spte_mask(void)
4585{
4586 /*
4587 * EPT Misconfigurations can be generated if the value of bits 2:0
4588 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4589 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4590 * spte.
4591 */
885032b9 4592 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4593}
4594
f53cd63c 4595#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4596/*
4597 * Sets up the vmcs for emulated real mode.
4598 */
8b9cf98c 4599static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4600{
2e4ce7f5 4601#ifdef CONFIG_X86_64
6aa8b732 4602 unsigned long a;
2e4ce7f5 4603#endif
6aa8b732 4604 int i;
6aa8b732 4605
6aa8b732 4606 /* I/O */
3e7c73e9
AK		 4607 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4608 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4609
4607c2d7
AG		 4610 if (enable_shadow_vmcs) {
4611 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4612 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4613 }
25c5f225 4614 if (cpu_has_vmx_msr_bitmap())
5897297b 4615 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4616
6aa8b732
AK		 4617 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4618
6aa8b732 4619 /* Control */
01e439be 4620 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4621
bf8179a0 4622 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4623
83ff3b9d 4624 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4625 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4626 vmx_secondary_exec_control(vmx));
83ff3b9d 4627 }
f78e0e2e 4628
01e439be 4629 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4630 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4631 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4632 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4633 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4634
4635 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4636
4637 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4638 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4639 }
4640
4b8d54f9
ZE		 4641 if (ple_gap) {
4642 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4643 vmx->ple_window = ple_window;
4644 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4645 }
4646
c3707958
XG		 4647 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4648 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4649 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4650
9581d442
AK		 4651 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4652 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4653 vmx_set_constant_host_state(vmx);
05b3e0c2 4654#ifdef CONFIG_X86_64
6aa8b732
AK		 4655 rdmsrl(MSR_FS_BASE, a);
4656 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4657 rdmsrl(MSR_GS_BASE, a);
4658 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4659#else
4660 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4661 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4662#endif
4663
2cc51560
ED		 4664 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4665 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4666 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4667 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4668 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4669
468d472f 4670 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4671 u32 msr_low, msr_high;
4672 u64 host_pat;
468d472f
SY		 4673 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4674 host_pat = msr_low | ((u64) msr_high << 32);
4675 /* Write the default value follow host pat */
4676 vmcs_write64(GUEST_IA32_PAT, host_pat);
4677 /* Keep arch.pat sync with GUEST_IA32_PAT */
4678 vmx->vcpu.arch.pat = host_pat;
4679 }
4680
03916db9 4681 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4682 u32 index = vmx_msr_index[i];
4683 u32 data_low, data_high;
a2fa3e9f 4684 int j = vmx->nmsrs;
6aa8b732
AK		 4685
4686 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4687 continue;
432bd6cb
AK		 4688 if (wrmsr_safe(index, data_low, data_high) < 0)
4689 continue;
26bb0981
AK		 4690 vmx->guest_msrs[j].index = i;
4691 vmx->guest_msrs[j].data = 0;
d5696725 4692 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4693 ++vmx->nmsrs;
6aa8b732 4694 }
6aa8b732 4695
2961e876
GN		 4696
4697 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4698
4699 /* 22.2.1, 20.8.1 */
2961e876 4700 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4701
e00c8cf2 4702 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4703 set_cr4_guest_host_mask(vmx);
e00c8cf2 4704
f53cd63c
WL		 4705 if (vmx_xsaves_supported())
4706 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4707
e00c8cf2
AK		 4708 return 0;
4709}
4710
57f252f2 4711static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4712{
4713 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4714 struct msr_data apic_base_msr;
e00c8cf2 4715
7ffd92c5 4716 vmx->rmode.vm86_active = 0;
e00c8cf2 4717
3b86cd99
JK		 4718 vmx->soft_vnmi_blocked = 0;
4719
ad312c7c 4720 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4721 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4722 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
58d269d8 4723 if (kvm_vcpu_is_reset_bsp(&vmx->vcpu))
58cb628d
JK		 4724 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4725 apic_base_msr.host_initiated = true;
4726 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4727
2fb92db1
AK		 4728 vmx_segment_cache_clear(vmx);
4729
5706be0d 4730 seg_setup(VCPU_SREG_CS);
66450a21 4731 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4732 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4733
4734 seg_setup(VCPU_SREG_DS);
4735 seg_setup(VCPU_SREG_ES);
4736 seg_setup(VCPU_SREG_FS);
4737 seg_setup(VCPU_SREG_GS);
4738 seg_setup(VCPU_SREG_SS);
4739
4740 vmcs_write16(GUEST_TR_SELECTOR, 0);
4741 vmcs_writel(GUEST_TR_BASE, 0);
4742 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4743 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4744
4745 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4746 vmcs_writel(GUEST_LDTR_BASE, 0);
4747 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4748 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4749
4750 vmcs_write32(GUEST_SYSENTER_CS, 0);
4751 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4752 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4753
4754 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4755 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4756
e00c8cf2
AK		 4757 vmcs_writel(GUEST_GDTR_BASE, 0);
4758 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4759
4760 vmcs_writel(GUEST_IDTR_BASE, 0);
4761 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4762
443381a8 4763 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4764 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4765 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4766
e00c8cf2
AK		 4767 /* Special registers */
4768 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4769
4770 setup_msrs(vmx);
4771
6aa8b732
AK		 4772 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4773
f78e0e2e
SY		 4774 if (cpu_has_vmx_tpr_shadow()) {
4775 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4776 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4777 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4778 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4779 vmcs_write32(TPR_THRESHOLD, 0);
4780 }
4781
a73896cb 4782 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4783
01e439be
YZ		 4784 if (vmx_vm_has_apicv(vcpu->kvm))
4785 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4786
2384d2b3
SY		 4787 if (vmx->vpid != 0)
4788 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4789
fa40052c 4790 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4791 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4792 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4793 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4794 vmx_fpu_activate(&vmx->vcpu);
4795 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4796
b9d762fa 4797 vpid_sync_context(vmx);
6aa8b732
AK		 4798}
4799
b6f1250e
NHE		 4800/*
4801 * In nested virtualization, check if L1 asked to exit on external interrupts.
4802 * For most existing hypervisors, this will always return true.
4803 */
4804static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4805{
4806 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4807 PIN_BASED_EXT_INTR_MASK;
4808}
4809
77b0f5d6
BD		 4810/*
4811 * In nested virtualization, check if L1 has set
4812 * VM_EXIT_ACK_INTR_ON_EXIT
4813 */
4814static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4815{
4816 return get_vmcs12(vcpu)->vm_exit_controls &
4817 VM_EXIT_ACK_INTR_ON_EXIT;
4818}
4819
ea8ceb83
JK		 4820static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4821{
4822 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4823 PIN_BASED_NMI_EXITING;
4824}
4825
c9a7953f 4826static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4827{
4828 u32 cpu_based_vm_exec_control;
730dca42 4829
3b86cd99
JK		 4830 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4831 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4832 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4833}
4834
c9a7953f 4835static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4836{
4837 u32 cpu_based_vm_exec_control;
4838
c9a7953f
JK		 4839 if (!cpu_has_virtual_nmis() ||
4840 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4841 enable_irq_window(vcpu);
4842 return;
4843 }
3b86cd99
JK		 4844
4845 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4846 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4847 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4848}
4849
66fd3f7f 4850static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4851{
9c8cba37 4852 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4853 uint32_t intr;
4854 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4855
229456fc 4856 trace_kvm_inj_virq(irq);
2714d1d3 4857
fa89a817 4858 ++vcpu->stat.irq_injections;
7ffd92c5 4859 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4860 int inc_eip = 0;
4861 if (vcpu->arch.interrupt.soft)
4862 inc_eip = vcpu->arch.event_exit_inst_len;
4863 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4864 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4865 return;
4866 }
66fd3f7f
GN		 4867 intr = irq | INTR_INFO_VALID_MASK;
4868 if (vcpu->arch.interrupt.soft) {
4869 intr |= INTR_TYPE_SOFT_INTR;
4870 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4871 vmx->vcpu.arch.event_exit_inst_len);
4872 } else
4873 intr |= INTR_TYPE_EXT_INTR;
4874 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4875}
4876
f08864b4
SY		 4877static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4878{
66a5a347
JK		 4879 struct vcpu_vmx *vmx = to_vmx(vcpu);
4880
0b6ac343
NHE		 4881 if (is_guest_mode(vcpu))
4882 return;
4883
3b86cd99
JK		 4884 if (!cpu_has_virtual_nmis()) {
4885 /*
4886 * Tracking the NMI-blocked state in software is built upon
4887 * finding the next open IRQ window. This, in turn, depends on
4888 * well-behaving guests: They have to keep IRQs disabled at
4889 * least as long as the NMI handler runs. Otherwise we may
4890 * cause NMI nesting, maybe breaking the guest. But as this is
4891 * highly unlikely, we can live with the residual risk.
4892 */
4893 vmx->soft_vnmi_blocked = 1;
4894 vmx->vnmi_blocked_time = 0;
4895 }
4896
487b391d 4897 ++vcpu->stat.nmi_injections;
9d58b931 4898 vmx->nmi_known_unmasked = false;
7ffd92c5 4899 if (vmx->rmode.vm86_active) {
71f9833b 4900 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4901 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4902 return;
4903 }
f08864b4
SY		 4904 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4905 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4906}
4907
3cfc3092
JK		 4908static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4909{
4910 if (!cpu_has_virtual_nmis())
4911 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4912 if (to_vmx(vcpu)->nmi_known_unmasked)
4913 return false;
c332c83a 4914 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4915}
4916
4917static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4918{
4919 struct vcpu_vmx *vmx = to_vmx(vcpu);
4920
4921 if (!cpu_has_virtual_nmis()) {
4922 if (vmx->soft_vnmi_blocked != masked) {
4923 vmx->soft_vnmi_blocked = masked;
4924 vmx->vnmi_blocked_time = 0;
4925 }
4926 } else {
9d58b931 4927 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4928 if (masked)
4929 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4930 GUEST_INTR_STATE_NMI);
4931 else
4932 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4933 GUEST_INTR_STATE_NMI);
4934 }
4935}
4936
2505dc9f
JK		 4937static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4938{
b6b8a145
JK		 4939 if (to_vmx(vcpu)->nested.nested_run_pending)
4940 return 0;
ea8ceb83 4941
2505dc9f
JK		 4942 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4943 return 0;
4944
4945 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4946 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4947 | GUEST_INTR_STATE_NMI));
4948}
4949
78646121
GN		 4950static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4951{
b6b8a145
JK		 4952 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4953 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4954 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4955 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4956}
4957
cbc94022
IE		 4958static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4959{
4960 int ret;
4961 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4962 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4963 .guest_phys_addr = addr,
4964 .memory_size = PAGE_SIZE * 3,
4965 .flags = 0,
4966 };
4967
47ae31e2 4968 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4969 if (ret)
4970 return ret;
bfc6d222 4971 kvm->arch.tss_addr = addr;
1f755a82 4972 return init_rmode_tss(kvm);
cbc94022
IE		 4973}
4974
0ca1b4f4 4975static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4976{
77ab6db0 4977 switch (vec) {
77ab6db0 4978 case BP_VECTOR:
c573cd22
JK		 4979 /*
4980 * Update instruction length as we may reinject the exception
4981 * from user space while in guest debugging mode.
4982 */
4983 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4984 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4985 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4986 return false;
4987 /* fall through */
4988 case DB_VECTOR:
4989 if (vcpu->guest_debug &
4990 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4991 return false;
d0bfb940
JK		 4992 /* fall through */
4993 case DE_VECTOR:
77ab6db0
JK		 4994 case OF_VECTOR:
4995 case BR_VECTOR:
4996 case UD_VECTOR:
4997 case DF_VECTOR:
4998 case SS_VECTOR:
4999 case GP_VECTOR:
5000 case MF_VECTOR:
0ca1b4f4
GN		 5001 return true;
5002 break;
77ab6db0 5003 }
0ca1b4f4
GN		 5004 return false;
5005}
5006
5007static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5008 int vec, u32 err_code)
5009{
5010 /*
5011 * Instruction with address size override prefix opcode 0x67
5012 * Cause the #SS fault with 0 error code in VM86 mode.
5013 */
5014 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5015 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5016 if (vcpu->arch.halt_request) {
5017 vcpu->arch.halt_request = 0;
5cb56059 5018 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5019 }
5020 return 1;
5021 }
5022 return 0;
5023 }
5024
5025 /*
5026 * Forward all other exceptions that are valid in real mode.
5027 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5028 * the required debugging infrastructure rework.
5029 */
5030 kvm_queue_exception(vcpu, vec);
5031 return 1;
6aa8b732
AK		 5032}
5033
a0861c02
AK		 5034/*
5035 * Trigger machine check on the host. We assume all the MSRs are already set up
5036 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5037 * We pass a fake environment to the machine check handler because we want
5038 * the guest to be always treated like user space, no matter what context
5039 * it used internally.
5040 */
5041static void kvm_machine_check(void)
5042{
5043#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5044 struct pt_regs regs = {
5045 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5046 .flags = X86_EFLAGS_IF,
5047 };
5048
5049 do_machine_check(&regs, 0);
5050#endif
5051}
5052
851ba692 5053static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5054{
5055 /* already handled by vcpu_run */
5056 return 1;
5057}
5058
851ba692 5059static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5060{
1155f76a 5061 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5062 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5063 u32 intr_info, ex_no, error_code;
42dbaa5a 5064 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5065 u32 vect_info;
5066 enum emulation_result er;
5067
1155f76a 5068 vect_info = vmx->idt_vectoring_info;
88786475 5069 intr_info = vmx->exit_intr_info;
6aa8b732 5070
a0861c02 5071 if (is_machine_check(intr_info))
851ba692 5072 return handle_machine_check(vcpu);
a0861c02 5073
e4a41889 5074 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5075 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5076
5077 if (is_no_device(intr_info)) {
5fd86fcf 5078 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5079 return 1;
5080 }
5081
7aa81cc0 5082 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5083 if (is_guest_mode(vcpu)) {
5084 kvm_queue_exception(vcpu, UD_VECTOR);
5085 return 1;
5086 }
51d8b661 5087 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5088 if (er != EMULATE_DONE)
7ee5d940 5089 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5090 return 1;
5091 }
5092
6aa8b732 5093 error_code = 0;
2e11384c 5094 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5095 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5096
5097 /*
5098 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5099 * MMIO, it is better to report an internal error.
5100 * See the comments in vmx_handle_exit.
5101 */
5102 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5103 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5104 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5105 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5106 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5107 vcpu->run->internal.data[0] = vect_info;
5108 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5109 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5110 return 0;
5111 }
5112
6aa8b732 5113 if (is_page_fault(intr_info)) {
1439442c 5114 /* EPT won't cause page fault directly */
cf3ace79 5115 BUG_ON(enable_ept);
6aa8b732 5116 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5117 trace_kvm_page_fault(cr2, error_code);
5118
3298b75c 5119 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5120 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5121 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5122 }
5123
d0bfb940 5124 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5125
5126 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5127 return handle_rmode_exception(vcpu, ex_no, error_code);
5128
42dbaa5a
JK		 5129 switch (ex_no) {
5130 case DB_VECTOR:
5131 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5132 if (!(vcpu->guest_debug &
5133 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5134 vcpu->arch.dr6 &= ~15;
6f43ed01 5135 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5136 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5137 skip_emulated_instruction(vcpu);
5138
42dbaa5a
JK		 5139 kvm_queue_exception(vcpu, DB_VECTOR);
5140 return 1;
5141 }
5142 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5143 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5144 /* fall through */
5145 case BP_VECTOR:
c573cd22
JK		 5146 /*
5147 * Update instruction length as we may reinject #BP from
5148 * user space while in guest debugging mode. Reading it for
5149 * #DB as well causes no harm, it is not used in that case.
5150 */
5151 vmx->vcpu.arch.event_exit_inst_len =
5152 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5153 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5154 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5155 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5156 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5157 break;
5158 default:
d0bfb940
JK		 5159 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5160 kvm_run->ex.exception = ex_no;
5161 kvm_run->ex.error_code = error_code;
42dbaa5a 5162 break;
6aa8b732 5163 }
6aa8b732
AK		 5164 return 0;
5165}
5166
851ba692 5167static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5168{
1165f5fe 5169 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5170 return 1;
5171}
5172
851ba692 5173static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5174{
851ba692 5175 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5176 return 0;
5177}
6aa8b732 5178
851ba692 5179static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5180{
bfdaab09 5181 unsigned long exit_qualification;
34c33d16 5182 int size, in, string;
039576c0 5183 unsigned port;
6aa8b732 5184
bfdaab09 5185 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5186 string = (exit_qualification & 16) != 0;
cf8f70bf 5187 in = (exit_qualification & 8) != 0;
e70669ab 5188
cf8f70bf 5189 ++vcpu->stat.io_exits;
e70669ab 5190
cf8f70bf 5191 if (string || in)
51d8b661 5192 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5193
cf8f70bf
GN		 5194 port = exit_qualification >> 16;
5195 size = (exit_qualification & 7) + 1;
e93f36bc 5196 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5197
5198 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5199}
5200
102d8325
IM		 5201static void
5202vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5203{
5204 /*
5205 * Patch in the VMCALL instruction:
5206 */
5207 hypercall[0] = 0x0f;
5208 hypercall[1] = 0x01;
5209 hypercall[2] = 0xc1;
102d8325
IM		 5210}
5211
b9c237bb 5212static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5213{
5214 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5215 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5216
b9c237bb 5217 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5218 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5219 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5220 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5221 return (val & always_on) == always_on;
5222}
5223
0fa06071 5224/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5225static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5226{
eeadf9e7 5227 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5228 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5229 unsigned long orig_val = val;
5230
eeadf9e7
NHE		 5231 /*
5232 * We get here when L2 changed cr0 in a way that did not change
5233 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5234 * but did change L0 shadowed bits. So we first calculate the
5235 * effective cr0 value that L1 would like to write into the
5236 * hardware. It consists of the L2-owned bits from the new
5237 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5238 */
1a0d74e6
JK		 5239 val = (val & ~vmcs12->cr0_guest_host_mask) |
5240 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5241
b9c237bb 5242 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5243 return 1;
1a0d74e6
JK		 5244
5245 if (kvm_set_cr0(vcpu, val))
5246 return 1;
5247 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5248 return 0;
1a0d74e6
JK		 5249 } else {
5250 if (to_vmx(vcpu)->nested.vmxon &&
5251 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5252 return 1;
eeadf9e7 5253 return kvm_set_cr0(vcpu, val);
1a0d74e6 5254 }
eeadf9e7
NHE		 5255}
5256
5257static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5258{
5259 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5260 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5261 unsigned long orig_val = val;
5262
5263 /* analogously to handle_set_cr0 */
5264 val = (val & ~vmcs12->cr4_guest_host_mask) |
5265 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5266 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5267 return 1;
1a0d74e6 5268 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5269 return 0;
5270 } else
5271 return kvm_set_cr4(vcpu, val);
5272}
5273
5274/* called to set cr0 as approriate for clts instruction exit. */
5275static void handle_clts(struct kvm_vcpu *vcpu)
5276{
5277 if (is_guest_mode(vcpu)) {
5278 /*
5279 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5280 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5281 * just pretend it's off (also in arch.cr0 for fpu_activate).
5282 */
5283 vmcs_writel(CR0_READ_SHADOW,
5284 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5285 vcpu->arch.cr0 &= ~X86_CR0_TS;
5286 } else
5287 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5288}
5289
851ba692 5290static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5291{
229456fc 5292 unsigned long exit_qualification, val;
6aa8b732
AK		 5293 int cr;
5294 int reg;
49a9b07e 5295 int err;
6aa8b732 5296
bfdaab09 5297 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5298 cr = exit_qualification & 15;
5299 reg = (exit_qualification >> 8) & 15;
5300 switch ((exit_qualification >> 4) & 3) {
5301 case 0: /* mov to cr */
1e32c079 5302 val = kvm_register_readl(vcpu, reg);
229456fc 5303 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5304 switch (cr) {
5305 case 0:
eeadf9e7 5306 err = handle_set_cr0(vcpu, val);
db8fcefa 5307 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5308 return 1;
5309 case 3:
2390218b 5310 err = kvm_set_cr3(vcpu, val);
db8fcefa 5311 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5312 return 1;
5313 case 4:
eeadf9e7 5314 err = handle_set_cr4(vcpu, val);
db8fcefa 5315 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5316 return 1;
0a5fff19
GN		 5317 case 8: {
5318 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5319 u8 cr8 = (u8)val;
eea1cff9 5320 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5321 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5322 if (irqchip_in_kernel(vcpu->kvm))
5323 return 1;
5324 if (cr8_prev <= cr8)
5325 return 1;
851ba692 5326 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5327 return 0;
5328 }
4b8073e4 5329 }
6aa8b732 5330 break;
25c4c276 5331 case 2: /* clts */
eeadf9e7 5332 handle_clts(vcpu);
4d4ec087 5333 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5334 skip_emulated_instruction(vcpu);
6b52d186 5335 vmx_fpu_activate(vcpu);
25c4c276 5336 return 1;
6aa8b732
AK		 5337 case 1: /*mov from cr*/
5338 switch (cr) {
5339 case 3:
9f8fe504
AK		 5340 val = kvm_read_cr3(vcpu);
5341 kvm_register_write(vcpu, reg, val);
5342 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5343 skip_emulated_instruction(vcpu);
5344 return 1;
5345 case 8:
229456fc
MT		 5346 val = kvm_get_cr8(vcpu);
5347 kvm_register_write(vcpu, reg, val);
5348 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5349 skip_emulated_instruction(vcpu);
5350 return 1;
5351 }
5352 break;
5353 case 3: /* lmsw */
a1f83a74 5354 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5355 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5356 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5357
5358 skip_emulated_instruction(vcpu);
5359 return 1;
5360 default:
5361 break;
5362 }
851ba692 5363 vcpu->run->exit_reason = 0;
a737f256 5364 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5365 (int)(exit_qualification >> 4) & 3, cr);
5366 return 0;
5367}
5368
851ba692 5369static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5370{
bfdaab09 5371 unsigned long exit_qualification;
16f8a6f9
NA		 5372 int dr, dr7, reg;
5373
5374 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5375 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5376
5377 /* First, if DR does not exist, trigger UD */
5378 if (!kvm_require_dr(vcpu, dr))
5379 return 1;
6aa8b732 5380
f2483415 5381 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5382 if (!kvm_require_cpl(vcpu, 0))
5383 return 1;
16f8a6f9
NA		 5384 dr7 = vmcs_readl(GUEST_DR7);
5385 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5386 /*
5387 * As the vm-exit takes precedence over the debug trap, we
5388 * need to emulate the latter, either for the host or the
5389 * guest debugging itself.
5390 */
5391 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5392 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5393 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5394 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5395 vcpu->run->debug.arch.exception = DB_VECTOR;
5396 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5397 return 0;
5398 } else {
7305eb5d 5399 vcpu->arch.dr6 &= ~15;
6f43ed01 5400 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5401 kvm_queue_exception(vcpu, DB_VECTOR);
5402 return 1;
5403 }
5404 }
5405
81908bf4
PB		 5406 if (vcpu->guest_debug == 0) {
5407 u32 cpu_based_vm_exec_control;
5408
5409 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5410 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5411 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5412
5413 /*
5414 * No more DR vmexits; force a reload of the debug registers
5415 * and reenter on this instruction. The next vmexit will
5416 * retrieve the full state of the debug registers.
5417 */
5418 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5419 return 1;
5420 }
5421
42dbaa5a
JK		 5422 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5423 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5424 unsigned long val;
4c4d563b
JK		 5425
5426 if (kvm_get_dr(vcpu, dr, &val))
5427 return 1;
5428 kvm_register_write(vcpu, reg, val);
020df079 5429 } else
5777392e 5430 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5431 return 1;
5432
6aa8b732
AK		 5433 skip_emulated_instruction(vcpu);
5434 return 1;
5435}
5436
73aaf249
JK		 5437static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5438{
5439 return vcpu->arch.dr6;
5440}
5441
5442static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5443{
5444}
5445
81908bf4
PB		 5446static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5447{
5448 u32 cpu_based_vm_exec_control;
5449
5450 get_debugreg(vcpu->arch.db[0], 0);
5451 get_debugreg(vcpu->arch.db[1], 1);
5452 get_debugreg(vcpu->arch.db[2], 2);
5453 get_debugreg(vcpu->arch.db[3], 3);
5454 get_debugreg(vcpu->arch.dr6, 6);
5455 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5456
5457 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5458
5459 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5460 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5461 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5462}
5463
020df079
GN		 5464static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5465{
5466 vmcs_writel(GUEST_DR7, val);
5467}
5468
851ba692 5469static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5470{
06465c5a
AK		 5471 kvm_emulate_cpuid(vcpu);
5472 return 1;
6aa8b732
AK		 5473}
5474
851ba692 5475static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5476{
ad312c7c 5477 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5478 u64 data;
5479
5480 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5481 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5482 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5483 return 1;
5484 }
5485
229456fc 5486 trace_kvm_msr_read(ecx, data);
2714d1d3 5487
6aa8b732 5488 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5489 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5490 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5491 skip_emulated_instruction(vcpu);
5492 return 1;
5493}
5494
851ba692 5495static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5496{
8fe8ab46 5497 struct msr_data msr;
ad312c7c
ZX		 5498 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5499 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5500 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5501
8fe8ab46
WA		 5502 msr.data = data;
5503 msr.index = ecx;
5504 msr.host_initiated = false;
854e8bb1 5505 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5506 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5507 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5508 return 1;
5509 }
5510
59200273 5511 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5512 skip_emulated_instruction(vcpu);
5513 return 1;
5514}
5515
851ba692 5516static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5517{
3842d135 5518 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5519 return 1;
5520}
5521
851ba692 5522static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5523{
85f455f7
ED		 5524 u32 cpu_based_vm_exec_control;
5525
5526 /* clear pending irq */
5527 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5528 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5530
3842d135
AK		 5531 kvm_make_request(KVM_REQ_EVENT, vcpu);
5532
a26bf12a 5533 ++vcpu->stat.irq_window_exits;
2714d1d3 5534
c1150d8c
DL		 5535 /*
5536 * If the user space waits to inject interrupts, exit as soon as
5537 * possible
5538 */
8061823a 5539 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5540 vcpu->run->request_interrupt_window &&
8061823a 5541 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5542 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5543 return 0;
5544 }
6aa8b732
AK		 5545 return 1;
5546}
5547
851ba692 5548static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5549{
d3bef15f 5550 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5551}
5552
851ba692 5553static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5554{
7aa81cc0
AL		 5555 kvm_emulate_hypercall(vcpu);
5556 return 1;
c21415e8
IM		 5557}
5558
ec25d5e6
GN		 5559static int handle_invd(struct kvm_vcpu *vcpu)
5560{
51d8b661 5561 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5562}
5563
851ba692 5564static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5565{
f9c617f6 5566 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5567
5568 kvm_mmu_invlpg(vcpu, exit_qualification);
5569 skip_emulated_instruction(vcpu);
5570 return 1;
5571}
5572
fee84b07
AK		 5573static int handle_rdpmc(struct kvm_vcpu *vcpu)
5574{
5575 int err;
5576
5577 err = kvm_rdpmc(vcpu);
5578 kvm_complete_insn_gp(vcpu, err);
5579
5580 return 1;
5581}
5582
851ba692 5583static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5584{
f5f48ee1 5585 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5586 return 1;
5587}
5588
2acf923e
DC		 5589static int handle_xsetbv(struct kvm_vcpu *vcpu)
5590{
5591 u64 new_bv = kvm_read_edx_eax(vcpu);
5592 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5593
5594 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5595 skip_emulated_instruction(vcpu);
5596 return 1;
5597}
5598
f53cd63c
WL		 5599static int handle_xsaves(struct kvm_vcpu *vcpu)
5600{
5601 skip_emulated_instruction(vcpu);
5602 WARN(1, "this should never happen\n");
5603 return 1;
5604}
5605
5606static int handle_xrstors(struct kvm_vcpu *vcpu)
5607{
5608 skip_emulated_instruction(vcpu);
5609 WARN(1, "this should never happen\n");
5610 return 1;
5611}
5612
851ba692 5613static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5614{
58fbbf26
KT		 5615 if (likely(fasteoi)) {
5616 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5617 int access_type, offset;
5618
5619 access_type = exit_qualification & APIC_ACCESS_TYPE;
5620 offset = exit_qualification & APIC_ACCESS_OFFSET;
5621 /*
5622 * Sane guest uses MOV to write EOI, with written value
5623 * not cared. So make a short-circuit here by avoiding
5624 * heavy instruction emulation.
5625 */
5626 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5627 (offset == APIC_EOI)) {
5628 kvm_lapic_set_eoi(vcpu);
5629 skip_emulated_instruction(vcpu);
5630 return 1;
5631 }
5632 }
51d8b661 5633 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5634}
5635
c7c9c56c
YZ		 5636static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5637{
5638 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5639 int vector = exit_qualification & 0xff;
5640
5641 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5642 kvm_apic_set_eoi_accelerated(vcpu, vector);
5643 return 1;
5644}
5645
83d4c286
YZ		 5646static int handle_apic_write(struct kvm_vcpu *vcpu)
5647{
5648 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5649 u32 offset = exit_qualification & 0xfff;
5650
5651 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5652 kvm_apic_write_nodecode(vcpu, offset);
5653 return 1;
5654}
5655
851ba692 5656static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5657{
60637aac 5658 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5659 unsigned long exit_qualification;
e269fb21
JK		 5660 bool has_error_code = false;
5661 u32 error_code = 0;
37817f29 5662 u16 tss_selector;
7f3d35fd 5663 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5664
5665 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5666 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5667 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5668
5669 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5670
5671 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5672 if (reason == TASK_SWITCH_GATE && idt_v) {
5673 switch (type) {
5674 case INTR_TYPE_NMI_INTR:
5675 vcpu->arch.nmi_injected = false;
654f06fc 5676 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5677 break;
5678 case INTR_TYPE_EXT_INTR:
66fd3f7f 5679 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5680 kvm_clear_interrupt_queue(vcpu);
5681 break;
5682 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5683 if (vmx->idt_vectoring_info &
5684 VECTORING_INFO_DELIVER_CODE_MASK) {
5685 has_error_code = true;
5686 error_code =
5687 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5688 }
5689 /* fall through */
64a7ec06
GN		 5690 case INTR_TYPE_SOFT_EXCEPTION:
5691 kvm_clear_exception_queue(vcpu);
5692 break;
5693 default:
5694 break;
5695 }
60637aac 5696 }
37817f29
IE		 5697 tss_selector = exit_qualification;
5698
64a7ec06
GN		 5699 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5700 type != INTR_TYPE_EXT_INTR &&
5701 type != INTR_TYPE_NMI_INTR))
5702 skip_emulated_instruction(vcpu);
5703
7f3d35fd
KW		 5704 if (kvm_task_switch(vcpu, tss_selector,
5705 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5706 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5707 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5708 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5709 vcpu->run->internal.ndata = 0;
42dbaa5a 5710 return 0;
acb54517 5711 }
42dbaa5a
JK		 5712
5713 /* clear all local breakpoint enable flags */
0e8a0996 5714 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5715
5716 /*
5717 * TODO: What about debug traps on tss switch?
5718 * Are we supposed to inject them and update dr6?
5719 */
5720
5721 return 1;
37817f29
IE		 5722}
5723
851ba692 5724static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5725{
f9c617f6 5726 unsigned long exit_qualification;
1439442c 5727 gpa_t gpa;
4f5982a5 5728 u32 error_code;
1439442c 5729 int gla_validity;
1439442c 5730
f9c617f6 5731 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5732
1439442c
SY		 5733 gla_validity = (exit_qualification >> 7) & 0x3;
5734 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5735 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5736 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5737 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5738 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5739 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5740 (long unsigned int)exit_qualification);
851ba692
AK		 5741 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5742 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5743 return 0;
1439442c
SY		 5744 }
5745
0be9c7a8
GN		 5746 /*
5747 * EPT violation happened while executing iret from NMI,
5748 * "blocked by NMI" bit has to be set before next VM entry.
5749 * There are errata that may cause this bit to not be set:
5750 * AAK134, BY25.
5751 */
bcd1c294
GN		 5752 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5753 cpu_has_virtual_nmis() &&
5754 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5755 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5756
1439442c 5757 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5758 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5759
5760 /* It is a write fault? */
81ed33e4 5761 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5762 /* It is a fetch fault? */
81ed33e4 5763 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5764 /* ept page table is present? */
81ed33e4 5765 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5766
25d92081
YZ		 5767 vcpu->arch.exit_qualification = exit_qualification;
5768
4f5982a5 5769 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5770}
5771
68f89400
MT		 5772static u64 ept_rsvd_mask(u64 spte, int level)
5773{
5774 int i;
5775 u64 mask = 0;
5776
5777 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5778 mask |= (1ULL << i);
5779
a32e8459 5780 if (level == 4)
68f89400
MT		 5781 /* bits 7:3 reserved */
5782 mask |= 0xf8;
a32e8459
WL		 5783 else if (spte & (1ULL << 7))
5784 /*
5785 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5786 * level == 1 if the hypervisor is using the ignored bit 7.
5787 */
5788 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5789 else if (level > 1)
5790 /* bits 6:3 reserved */
5791 mask |= 0x78;
68f89400
MT		 5792
5793 return mask;
5794}
5795
5796static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5797 int level)
5798{
5799 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5800
5801 /* 010b (write-only) */
5802 WARN_ON((spte & 0x7) == 0x2);
5803
5804 /* 110b (write/execute) */
5805 WARN_ON((spte & 0x7) == 0x6);
5806
5807 /* 100b (execute-only) and value not supported by logical processor */
5808 if (!cpu_has_vmx_ept_execute_only())
5809 WARN_ON((spte & 0x7) == 0x4);
5810
5811 /* not 000b */
5812 if ((spte & 0x7)) {
5813 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5814
5815 if (rsvd_bits != 0) {
5816 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5817 __func__, rsvd_bits);
5818 WARN_ON(1);
5819 }
5820
a32e8459
WL		 5821 /* bits 5:3 are _not_ reserved for large page or leaf page */
5822 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5823 u64 ept_mem_type = (spte & 0x38) >> 3;
5824
5825 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5826 ept_mem_type == 7) {
5827 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5828 __func__, ept_mem_type);
5829 WARN_ON(1);
5830 }
5831 }
5832 }
5833}
5834
851ba692 5835static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5836{
5837 u64 sptes[4];
ce88decf 5838 int nr_sptes, i, ret;
68f89400
MT		 5839 gpa_t gpa;
5840
5841 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5842 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1
MT		 5843 skip_emulated_instruction(vcpu);
5844 return 1;
5845 }
68f89400 5846
ce88decf 5847 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5848 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5849 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5850 EMULATE_DONE;
f8f55942
XG		 5851
5852 if (unlikely(ret == RET_MMIO_PF_INVALID))
5853 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5854
b37fbea6 5855 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5856 return 1;
5857
5858 /* It is the real ept misconfig */
68f89400
MT		 5859 printk(KERN_ERR "EPT: Misconfiguration.\n");
5860 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5861
5862 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5863
5864 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5865 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5866
851ba692
AK		 5867 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5868 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5869
5870 return 0;
5871}
5872
851ba692 5873static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5874{
5875 u32 cpu_based_vm_exec_control;
5876
5877 /* clear pending NMI */
5878 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5879 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5880 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5881 ++vcpu->stat.nmi_window_exits;
3842d135 5882 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5883
5884 return 1;
5885}
5886
80ced186 5887static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5888{
8b3079a5
AK		 5889 struct vcpu_vmx *vmx = to_vmx(vcpu);
5890 enum emulation_result err = EMULATE_DONE;
80ced186 5891 int ret = 1;
49e9d557
AK		 5892 u32 cpu_exec_ctrl;
5893 bool intr_window_requested;
b8405c18 5894 unsigned count = 130;
49e9d557
AK		 5895
5896 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5897 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5898
98eb2f8b 5899 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5900 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5901 return handle_interrupt_window(&vmx->vcpu);
5902
de87dcdd
AK		 5903 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5904 return 1;
5905
991eebf9 5906 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5907
ac0a48c3 5908 if (err == EMULATE_USER_EXIT) {
94452b9e 5909 ++vcpu->stat.mmio_exits;
80ced186
MG		 5910 ret = 0;
5911 goto out;
5912 }
1d5a4d9b 5913
de5f70e0
AK		 5914 if (err != EMULATE_DONE) {
5915 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5916 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5917 vcpu->run->internal.ndata = 0;
6d77dbfc 5918 return 0;
de5f70e0 5919 }
ea953ef0 5920
8d76c49e
GN		 5921 if (vcpu->arch.halt_request) {
5922 vcpu->arch.halt_request = 0;
5cb56059 5923 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5924 goto out;
5925 }
5926
ea953ef0 5927 if (signal_pending(current))
80ced186 5928 goto out;
ea953ef0
MG		 5929 if (need_resched())
5930 schedule();
5931 }
5932
80ced186
MG		 5933out:
5934 return ret;
ea953ef0
MG		 5935}
5936
b4a2d31d
RK		 5937static int __grow_ple_window(int val)
5938{
5939 if (ple_window_grow < 1)
5940 return ple_window;
5941
5942 val = min(val, ple_window_actual_max);
5943
5944 if (ple_window_grow < ple_window)
5945 val *= ple_window_grow;
5946 else
5947 val += ple_window_grow;
5948
5949 return val;
5950}
5951
5952static int __shrink_ple_window(int val, int modifier, int minimum)
5953{
5954 if (modifier < 1)
5955 return ple_window;
5956
5957 if (modifier < ple_window)
5958 val /= modifier;
5959 else
5960 val -= modifier;
5961
5962 return max(val, minimum);
5963}
5964
5965static void grow_ple_window(struct kvm_vcpu *vcpu)
5966{
5967 struct vcpu_vmx *vmx = to_vmx(vcpu);
5968 int old = vmx->ple_window;
5969
5970 vmx->ple_window = __grow_ple_window(old);
5971
5972 if (vmx->ple_window != old)
5973 vmx->ple_window_dirty = true;
7b46268d
RK		 5974
5975 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5976}
5977
5978static void shrink_ple_window(struct kvm_vcpu *vcpu)
5979{
5980 struct vcpu_vmx *vmx = to_vmx(vcpu);
5981 int old = vmx->ple_window;
5982
5983 vmx->ple_window = __shrink_ple_window(old,
5984 ple_window_shrink, ple_window);
5985
5986 if (vmx->ple_window != old)
5987 vmx->ple_window_dirty = true;
7b46268d
RK		 5988
5989 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5990}
5991
5992/*
5993 * ple_window_actual_max is computed to be one grow_ple_window() below
5994 * ple_window_max. (See __grow_ple_window for the reason.)
5995 * This prevents overflows, because ple_window_max is int.
5996 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5997 * this process.
5998 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5999 */
6000static void update_ple_window_actual_max(void)
6001{
6002 ple_window_actual_max =
6003 __shrink_ple_window(max(ple_window_max, ple_window),
6004 ple_window_grow, INT_MIN);
6005}
6006
f2c7648d
TC		 6007static __init int hardware_setup(void)
6008{
34a1cd60
TC		 6009 int r = -ENOMEM, i, msr;
6010
6011 rdmsrl_safe(MSR_EFER, &host_efer);
6012
6013 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6014 kvm_define_shared_msr(i, vmx_msr_index[i]);
6015
6016 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6017 if (!vmx_io_bitmap_a)
6018 return r;
6019
6020 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6021 if (!vmx_io_bitmap_b)
6022 goto out;
6023
6024 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6025 if (!vmx_msr_bitmap_legacy)
6026 goto out1;
6027
6028 vmx_msr_bitmap_legacy_x2apic =
6029 (unsigned long *)__get_free_page(GFP_KERNEL);
6030 if (!vmx_msr_bitmap_legacy_x2apic)
6031 goto out2;
6032
6033 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6034 if (!vmx_msr_bitmap_longmode)
6035 goto out3;
6036
6037 vmx_msr_bitmap_longmode_x2apic =
6038 (unsigned long *)__get_free_page(GFP_KERNEL);
6039 if (!vmx_msr_bitmap_longmode_x2apic)
6040 goto out4;
3af18d9c
WV		 6041
6042 if (nested) {
6043 vmx_msr_bitmap_nested =
6044 (unsigned long *)__get_free_page(GFP_KERNEL);
6045 if (!vmx_msr_bitmap_nested)
6046 goto out5;
6047 }
6048
34a1cd60
TC		 6049 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6050 if (!vmx_vmread_bitmap)
3af18d9c 6051 goto out6;
34a1cd60
TC		 6052
6053 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6054 if (!vmx_vmwrite_bitmap)
3af18d9c 6055 goto out7;
34a1cd60
TC		 6056
6057 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6058 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6059
6060 /*
6061 * Allow direct access to the PC debug port (it is often used for I/O
6062 * delays, but the vmexits simply slow things down).
6063 */
6064 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6065 clear_bit(0x80, vmx_io_bitmap_a);
6066
6067 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6068
6069 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6070 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 6071 if (nested)
6072 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 6073
34a1cd60
TC		 6074 if (setup_vmcs_config(&vmcs_config) < 0) {
6075 r = -EIO;
3af18d9c 6076 goto out8;
baa03522 6077 }
f2c7648d
TC		 6078
6079 if (boot_cpu_has(X86_FEATURE_NX))
6080 kvm_enable_efer_bits(EFER_NX);
6081
6082 if (!cpu_has_vmx_vpid())
6083 enable_vpid = 0;
6084 if (!cpu_has_vmx_shadow_vmcs())
6085 enable_shadow_vmcs = 0;
6086 if (enable_shadow_vmcs)
6087 init_vmcs_shadow_fields();
6088
6089 if (!cpu_has_vmx_ept() ||
6090 !cpu_has_vmx_ept_4levels()) {
6091 enable_ept = 0;
6092 enable_unrestricted_guest = 0;
6093 enable_ept_ad_bits = 0;
6094 }
6095
6096 if (!cpu_has_vmx_ept_ad_bits())
6097 enable_ept_ad_bits = 0;
6098
6099 if (!cpu_has_vmx_unrestricted_guest())
6100 enable_unrestricted_guest = 0;
6101
ad15a296 6102 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6103 flexpriority_enabled = 0;
6104
ad15a296
PB		 6105 /*
6106 * set_apic_access_page_addr() is used to reload apic access
6107 * page upon invalidation. No need to do anything if not
6108 * using the APIC_ACCESS_ADDR VMCS field.
6109 */
6110 if (!flexpriority_enabled)
f2c7648d 6111 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6112
6113 if (!cpu_has_vmx_tpr_shadow())
6114 kvm_x86_ops->update_cr8_intercept = NULL;
6115
6116 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6117 kvm_disable_largepages();
6118
6119 if (!cpu_has_vmx_ple())
6120 ple_gap = 0;
6121
6122 if (!cpu_has_vmx_apicv())
6123 enable_apicv = 0;
6124
6125 if (enable_apicv)
6126 kvm_x86_ops->update_cr8_intercept = NULL;
6127 else {
6128 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6129 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6130 kvm_x86_ops->deliver_posted_interrupt = NULL;
6131 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6132 }
6133
baa03522
TC		 6134 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6135 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6136 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6137 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6138 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6139 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6140 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6141
6142 memcpy(vmx_msr_bitmap_legacy_x2apic,
6143 vmx_msr_bitmap_legacy, PAGE_SIZE);
6144 memcpy(vmx_msr_bitmap_longmode_x2apic,
6145 vmx_msr_bitmap_longmode, PAGE_SIZE);
6146
6147 if (enable_apicv) {
6148 for (msr = 0x800; msr <= 0x8ff; msr++)
6149 vmx_disable_intercept_msr_read_x2apic(msr);
6150
6151 /* According SDM, in x2apic mode, the whole id reg is used.
6152 * But in KVM, it only use the highest eight bits. Need to
6153 * intercept it */
6154 vmx_enable_intercept_msr_read_x2apic(0x802);
6155 /* TMCCT */
6156 vmx_enable_intercept_msr_read_x2apic(0x839);
6157 /* TPR */
6158 vmx_disable_intercept_msr_write_x2apic(0x808);
6159 /* EOI */
6160 vmx_disable_intercept_msr_write_x2apic(0x80b);
6161 /* SELF-IPI */
6162 vmx_disable_intercept_msr_write_x2apic(0x83f);
6163 }
6164
6165 if (enable_ept) {
6166 kvm_mmu_set_mask_ptes(0ull,
6167 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6168 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6169 0ull, VMX_EPT_EXECUTABLE_MASK);
6170 ept_set_mmio_spte_mask();
6171 kvm_enable_tdp();
6172 } else
6173 kvm_disable_tdp();
6174
6175 update_ple_window_actual_max();
6176
843e4330
KH		 6177 /*
6178 * Only enable PML when hardware supports PML feature, and both EPT
6179 * and EPT A/D bit features are enabled -- PML depends on them to work.
6180 */
6181 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6182 enable_pml = 0;
6183
6184 if (!enable_pml) {
6185 kvm_x86_ops->slot_enable_log_dirty = NULL;
6186 kvm_x86_ops->slot_disable_log_dirty = NULL;
6187 kvm_x86_ops->flush_log_dirty = NULL;
6188 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6189 }
6190
f2c7648d 6191 return alloc_kvm_area();
34a1cd60 6192
3af18d9c 6193out8:
34a1cd60 6194 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6195out7:
34a1cd60 6196 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6197out6:
6198 if (nested)
6199 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6200out5:
6201 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6202out4:
6203 free_page((unsigned long)vmx_msr_bitmap_longmode);
6204out3:
6205 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6206out2:
6207 free_page((unsigned long)vmx_msr_bitmap_legacy);
6208out1:
6209 free_page((unsigned long)vmx_io_bitmap_b);
6210out:
6211 free_page((unsigned long)vmx_io_bitmap_a);
6212
6213 return r;
f2c7648d
TC		 6214}
6215
6216static __exit void hardware_unsetup(void)
6217{
34a1cd60
TC		 6218 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6219 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6220 free_page((unsigned long)vmx_msr_bitmap_legacy);
6221 free_page((unsigned long)vmx_msr_bitmap_longmode);
6222 free_page((unsigned long)vmx_io_bitmap_b);
6223 free_page((unsigned long)vmx_io_bitmap_a);
6224 free_page((unsigned long)vmx_vmwrite_bitmap);
6225 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6226 if (nested)
6227 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6228
f2c7648d
TC		 6229 free_kvm_area();
6230}
6231
4b8d54f9
ZE		 6232/*
6233 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6234 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6235 */
9fb41ba8 6236static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6237{
b4a2d31d
RK		 6238 if (ple_gap)
6239 grow_ple_window(vcpu);
6240
4b8d54f9
ZE		 6241 skip_emulated_instruction(vcpu);
6242 kvm_vcpu_on_spin(vcpu);
6243
6244 return 1;
6245}
6246
87c00572 6247static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6248{
87c00572 6249 skip_emulated_instruction(vcpu);
59708670
SY		 6250 return 1;
6251}
6252
87c00572
GS		 6253static int handle_mwait(struct kvm_vcpu *vcpu)
6254{
6255 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6256 return handle_nop(vcpu);
6257}
6258
6259static int handle_monitor(struct kvm_vcpu *vcpu)
6260{
6261 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6262 return handle_nop(vcpu);
6263}
6264
ff2f6fe9
NHE		 6265/*
6266 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6267 * We could reuse a single VMCS for all the L2 guests, but we also want the
6268 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6269 * allows keeping them loaded on the processor, and in the future will allow
6270 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6271 * every entry if they never change.
6272 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6273 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6274 *
6275 * The following functions allocate and free a vmcs02 in this pool.
6276 */
6277
6278/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6279static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6280{
6281 struct vmcs02_list *item;
6282 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6283 if (item->vmptr == vmx->nested.current_vmptr) {
6284 list_move(&item->list, &vmx->nested.vmcs02_pool);
6285 return &item->vmcs02;
6286 }
6287
6288 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6289 /* Recycle the least recently used VMCS. */
6290 item = list_entry(vmx->nested.vmcs02_pool.prev,
6291 struct vmcs02_list, list);
6292 item->vmptr = vmx->nested.current_vmptr;
6293 list_move(&item->list, &vmx->nested.vmcs02_pool);
6294 return &item->vmcs02;
6295 }
6296
6297 /* Create a new VMCS */
0fa24ce3 6298 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6299 if (!item)
6300 return NULL;
6301 item->vmcs02.vmcs = alloc_vmcs();
6302 if (!item->vmcs02.vmcs) {
6303 kfree(item);
6304 return NULL;
6305 }
6306 loaded_vmcs_init(&item->vmcs02);
6307 item->vmptr = vmx->nested.current_vmptr;
6308 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6309 vmx->nested.vmcs02_num++;
6310 return &item->vmcs02;
6311}
6312
6313/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6314static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6315{
6316 struct vmcs02_list *item;
6317 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6318 if (item->vmptr == vmptr) {
6319 free_loaded_vmcs(&item->vmcs02);
6320 list_del(&item->list);
6321 kfree(item);
6322 vmx->nested.vmcs02_num--;
6323 return;
6324 }
6325}
6326
6327/*
6328 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6329 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6330 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6331 */
6332static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6333{
6334 struct vmcs02_list *item, *n;
4fa7734c
PB		 6335
6336 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6337 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6338 /*
6339 * Something will leak if the above WARN triggers. Better than
6340 * a use-after-free.
6341 */
6342 if (vmx->loaded_vmcs == &item->vmcs02)
6343 continue;
6344
6345 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6346 list_del(&item->list);
6347 kfree(item);
4fa7734c 6348 vmx->nested.vmcs02_num--;
ff2f6fe9 6349 }
ff2f6fe9
NHE		 6350}
6351
0658fbaa
ACL		 6352/*
6353 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6354 * set the success or error code of an emulated VMX instruction, as specified
6355 * by Vol 2B, VMX Instruction Reference, "Conventions".
6356 */
6357static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6358{
6359 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6360 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6361 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6362}
6363
6364static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6365{
6366 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6367 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6368 X86_EFLAGS_SF | X86_EFLAGS_OF))
6369 | X86_EFLAGS_CF);
6370}
6371
145c28dd 6372static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6373 u32 vm_instruction_error)
6374{
6375 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6376 /*
6377 * failValid writes the error number to the current VMCS, which
6378 * can't be done there isn't a current VMCS.
6379 */
6380 nested_vmx_failInvalid(vcpu);
6381 return;
6382 }
6383 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6384 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6385 X86_EFLAGS_SF | X86_EFLAGS_OF))
6386 | X86_EFLAGS_ZF);
6387 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6388 /*
6389 * We don't need to force a shadow sync because
6390 * VM_INSTRUCTION_ERROR is not shadowed
6391 */
6392}
145c28dd 6393
ff651cb6
WV		 6394static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6395{
6396 /* TODO: not to reset guest simply here. */
6397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6398 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6399}
6400
f4124500
JK		 6401static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6402{
6403 struct vcpu_vmx *vmx =
6404 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6405
6406 vmx->nested.preemption_timer_expired = true;
6407 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6408 kvm_vcpu_kick(&vmx->vcpu);
6409
6410 return HRTIMER_NORESTART;
6411}
6412
19677e32
BD		 6413/*
6414 * Decode the memory-address operand of a vmx instruction, as recorded on an
6415 * exit caused by such an instruction (run by a guest hypervisor).
6416 * On success, returns 0. When the operand is invalid, returns 1 and throws
6417 * #UD or #GP.
6418 */
6419static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6420 unsigned long exit_qualification,
6421 u32 vmx_instruction_info, gva_t *ret)
6422{
6423 /*
6424 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6425 * Execution", on an exit, vmx_instruction_info holds most of the
6426 * addressing components of the operand. Only the displacement part
6427 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6428 * For how an actual address is calculated from all these components,
6429 * refer to Vol. 1, "Operand Addressing".
6430 */
6431 int scaling = vmx_instruction_info & 3;
6432 int addr_size = (vmx_instruction_info >> 7) & 7;
6433 bool is_reg = vmx_instruction_info & (1u << 10);
6434 int seg_reg = (vmx_instruction_info >> 15) & 7;
6435 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6436 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6437 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6438 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6439
6440 if (is_reg) {
6441 kvm_queue_exception(vcpu, UD_VECTOR);
6442 return 1;
6443 }
6444
6445 /* Addr = segment_base + offset */
6446 /* offset = base + [index * scale] + displacement */
6447 *ret = vmx_get_segment_base(vcpu, seg_reg);
6448 if (base_is_valid)
6449 *ret += kvm_register_read(vcpu, base_reg);
6450 if (index_is_valid)
6451 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6452 *ret += exit_qualification; /* holds the displacement */
6453
6454 if (addr_size == 1) /* 32 bit */
6455 *ret &= 0xffffffff;
6456
6457 /*
6458 * TODO: throw #GP (and return 1) in various cases that the VM*
6459 * instructions require it - e.g., offset beyond segment limit,
6460 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6461 * address, and so on. Currently these are not checked.
6462 */
6463 return 0;
6464}
6465
3573e22c
BD		 6466/*
6467 * This function performs the various checks including
6468 * - if it's 4KB aligned
6469 * - No bits beyond the physical address width are set
6470 * - Returns 0 on success or else 1
4291b588 6471 * (Intel SDM Section 30.3)
3573e22c 6472 */
4291b588
BD		 6473static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6474 gpa_t *vmpointer)
3573e22c
BD		 6475{
6476 gva_t gva;
6477 gpa_t vmptr;
6478 struct x86_exception e;
6479 struct page *page;
6480 struct vcpu_vmx *vmx = to_vmx(vcpu);
6481 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6482
6483 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6484 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6485 return 1;
6486
6487 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6488 sizeof(vmptr), &e)) {
6489 kvm_inject_page_fault(vcpu, &e);
6490 return 1;
6491 }
6492
6493 switch (exit_reason) {
6494 case EXIT_REASON_VMON:
6495 /*
6496 * SDM 3: 24.11.5
6497 * The first 4 bytes of VMXON region contain the supported
6498 * VMCS revision identifier
6499 *
6500 * Note - IA32_VMX_BASIC[48] will never be 1
6501 * for the nested case;
6502 * which replaces physical address width with 32
6503 *
6504 */
bc39c4db 6505 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6506 nested_vmx_failInvalid(vcpu);
6507 skip_emulated_instruction(vcpu);
6508 return 1;
6509 }
6510
6511 page = nested_get_page(vcpu, vmptr);
6512 if (page == NULL ||
6513 *(u32 *)kmap(page) != VMCS12_REVISION) {
6514 nested_vmx_failInvalid(vcpu);
6515 kunmap(page);
6516 skip_emulated_instruction(vcpu);
6517 return 1;
6518 }
6519 kunmap(page);
6520 vmx->nested.vmxon_ptr = vmptr;
6521 break;
4291b588 6522 case EXIT_REASON_VMCLEAR:
bc39c4db 6523 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6524 nested_vmx_failValid(vcpu,
6525 VMXERR_VMCLEAR_INVALID_ADDRESS);
6526 skip_emulated_instruction(vcpu);
6527 return 1;
6528 }
6529
6530 if (vmptr == vmx->nested.vmxon_ptr) {
6531 nested_vmx_failValid(vcpu,
6532 VMXERR_VMCLEAR_VMXON_POINTER);
6533 skip_emulated_instruction(vcpu);
6534 return 1;
6535 }
6536 break;
6537 case EXIT_REASON_VMPTRLD:
bc39c4db 6538 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6539 nested_vmx_failValid(vcpu,
6540 VMXERR_VMPTRLD_INVALID_ADDRESS);
6541 skip_emulated_instruction(vcpu);
6542 return 1;
6543 }
3573e22c 6544
4291b588
BD		 6545 if (vmptr == vmx->nested.vmxon_ptr) {
6546 nested_vmx_failValid(vcpu,
6547 VMXERR_VMCLEAR_VMXON_POINTER);
6548 skip_emulated_instruction(vcpu);
6549 return 1;
6550 }
6551 break;
3573e22c
BD		 6552 default:
6553 return 1; /* shouldn't happen */
6554 }
6555
4291b588
BD		 6556 if (vmpointer)
6557 *vmpointer = vmptr;
3573e22c
BD		 6558 return 0;
6559}
6560
ec378aee
NHE		 6561/*
6562 * Emulate the VMXON instruction.
6563 * Currently, we just remember that VMX is active, and do not save or even
6564 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6565 * do not currently need to store anything in that guest-allocated memory
6566 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6567 * argument is different from the VMXON pointer (which the spec says they do).
6568 */
6569static int handle_vmon(struct kvm_vcpu *vcpu)
6570{
6571 struct kvm_segment cs;
6572 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6573 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6574 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6575 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6576
6577 /* The Intel VMX Instruction Reference lists a bunch of bits that
6578 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6579 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6580 * Otherwise, we should fail with #UD. We test these now:
6581 */
6582 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6583 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6584 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6585 kvm_queue_exception(vcpu, UD_VECTOR);
6586 return 1;
6587 }
6588
6589 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6590 if (is_long_mode(vcpu) && !cs.l) {
6591 kvm_queue_exception(vcpu, UD_VECTOR);
6592 return 1;
6593 }
6594
6595 if (vmx_get_cpl(vcpu)) {
6596 kvm_inject_gp(vcpu, 0);
6597 return 1;
6598 }
3573e22c 6599
4291b588 6600 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6601 return 1;
6602
145c28dd
AG		 6603 if (vmx->nested.vmxon) {
6604 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6605 skip_emulated_instruction(vcpu);
6606 return 1;
6607 }
b3897a49
NHE		 6608
6609 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6610 != VMXON_NEEDED_FEATURES) {
6611 kvm_inject_gp(vcpu, 0);
6612 return 1;
6613 }
6614
8de48833
AG		 6615 if (enable_shadow_vmcs) {
6616 shadow_vmcs = alloc_vmcs();
6617 if (!shadow_vmcs)
6618 return -ENOMEM;
6619 /* mark vmcs as shadow */
6620 shadow_vmcs->revision_id |= (1u << 31);
6621 /* init shadow vmcs */
6622 vmcs_clear(shadow_vmcs);
6623 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6624 }
ec378aee 6625
ff2f6fe9
NHE		 6626 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6627 vmx->nested.vmcs02_num = 0;
6628
f4124500
JK		 6629 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6630 HRTIMER_MODE_REL);
6631 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6632
ec378aee
NHE		 6633 vmx->nested.vmxon = true;
6634
6635 skip_emulated_instruction(vcpu);
a25eb114 6636 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6637 return 1;
6638}
6639
6640/*
6641 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6642 * for running VMX instructions (except VMXON, whose prerequisites are
6643 * slightly different). It also specifies what exception to inject otherwise.
6644 */
6645static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6646{
6647 struct kvm_segment cs;
6648 struct vcpu_vmx *vmx = to_vmx(vcpu);
6649
6650 if (!vmx->nested.vmxon) {
6651 kvm_queue_exception(vcpu, UD_VECTOR);
6652 return 0;
6653 }
6654
6655 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6656 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6657 (is_long_mode(vcpu) && !cs.l)) {
6658 kvm_queue_exception(vcpu, UD_VECTOR);
6659 return 0;
6660 }
6661
6662 if (vmx_get_cpl(vcpu)) {
6663 kvm_inject_gp(vcpu, 0);
6664 return 0;
6665 }
6666
6667 return 1;
6668}
6669
e7953d7f
AG		 6670static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6671{
8a1b9dd0 6672 u32 exec_control;
9a2a05b9
PB		 6673 if (vmx->nested.current_vmptr == -1ull)
6674 return;
6675
6676 /* current_vmptr and current_vmcs12 are always set/reset together */
6677 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6678 return;
6679
012f83cb 6680 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6681 /* copy to memory all shadowed fields in case
6682 they were modified */
6683 copy_shadow_to_vmcs12(vmx);
6684 vmx->nested.sync_shadow_vmcs = false;
6685 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6686 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6687 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6688 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6689 }
705699a1 6690 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6691 kunmap(vmx->nested.current_vmcs12_page);
6692 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6693 vmx->nested.current_vmptr = -1ull;
6694 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6695}
6696
ec378aee
NHE		 6697/*
6698 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6699 * just stops using VMX.
6700 */
6701static void free_nested(struct vcpu_vmx *vmx)
6702{
6703 if (!vmx->nested.vmxon)
6704 return;
9a2a05b9 6705
ec378aee 6706 vmx->nested.vmxon = false;
9a2a05b9 6707 nested_release_vmcs12(vmx);
e7953d7f
AG		 6708 if (enable_shadow_vmcs)
6709 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6710 /* Unpin physical memory we referred to in current vmcs02 */
6711 if (vmx->nested.apic_access_page) {
6712 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6713 vmx->nested.apic_access_page = NULL;
fe3ef05c 6714 }
a7c0b07d
WL		 6715 if (vmx->nested.virtual_apic_page) {
6716 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6717 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6718 }
705699a1
WV		 6719 if (vmx->nested.pi_desc_page) {
6720 kunmap(vmx->nested.pi_desc_page);
6721 nested_release_page(vmx->nested.pi_desc_page);
6722 vmx->nested.pi_desc_page = NULL;
6723 vmx->nested.pi_desc = NULL;
6724 }
ff2f6fe9
NHE		 6725
6726 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6727}
6728
6729/* Emulate the VMXOFF instruction */
6730static int handle_vmoff(struct kvm_vcpu *vcpu)
6731{
6732 if (!nested_vmx_check_permission(vcpu))
6733 return 1;
6734 free_nested(to_vmx(vcpu));
6735 skip_emulated_instruction(vcpu);
a25eb114 6736 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6737 return 1;
6738}
6739
27d6c865
NHE		 6740/* Emulate the VMCLEAR instruction */
6741static int handle_vmclear(struct kvm_vcpu *vcpu)
6742{
6743 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6744 gpa_t vmptr;
6745 struct vmcs12 *vmcs12;
6746 struct page *page;
27d6c865
NHE		 6747
6748 if (!nested_vmx_check_permission(vcpu))
6749 return 1;
6750
4291b588 6751 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6752 return 1;
27d6c865 6753
9a2a05b9 6754 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6755 nested_release_vmcs12(vmx);
27d6c865
NHE		 6756
6757 page = nested_get_page(vcpu, vmptr);
6758 if (page == NULL) {
6759 /*
6760 * For accurate processor emulation, VMCLEAR beyond available
6761 * physical memory should do nothing at all. However, it is
6762 * possible that a nested vmx bug, not a guest hypervisor bug,
6763 * resulted in this case, so let's shut down before doing any
6764 * more damage:
6765 */
6766 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6767 return 1;
6768 }
6769 vmcs12 = kmap(page);
6770 vmcs12->launch_state = 0;
6771 kunmap(page);
6772 nested_release_page(page);
6773
6774 nested_free_vmcs02(vmx, vmptr);
6775
6776 skip_emulated_instruction(vcpu);
6777 nested_vmx_succeed(vcpu);
6778 return 1;
6779}
6780
cd232ad0
NHE		 6781static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6782
6783/* Emulate the VMLAUNCH instruction */
6784static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6785{
6786 return nested_vmx_run(vcpu, true);
6787}
6788
6789/* Emulate the VMRESUME instruction */
6790static int handle_vmresume(struct kvm_vcpu *vcpu)
6791{
6792
6793 return nested_vmx_run(vcpu, false);
6794}
6795
49f705c5
NHE		 6796enum vmcs_field_type {
6797 VMCS_FIELD_TYPE_U16 = 0,
6798 VMCS_FIELD_TYPE_U64 = 1,
6799 VMCS_FIELD_TYPE_U32 = 2,
6800 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6801};
6802
6803static inline int vmcs_field_type(unsigned long field)
6804{
6805 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6806 return VMCS_FIELD_TYPE_U32;
6807 return (field >> 13) & 0x3 ;
6808}
6809
6810static inline int vmcs_field_readonly(unsigned long field)
6811{
6812 return (((field >> 10) & 0x3) == 1);
6813}
6814
6815/*
6816 * Read a vmcs12 field. Since these can have varying lengths and we return
6817 * one type, we chose the biggest type (u64) and zero-extend the return value
6818 * to that size. Note that the caller, handle_vmread, might need to use only
6819 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6820 * 64-bit fields are to be returned).
6821 */
a2ae9df7
PB		 6822static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6823 unsigned long field, u64 *ret)
49f705c5
NHE		 6824{
6825 short offset = vmcs_field_to_offset(field);
6826 char *p;
6827
6828 if (offset < 0)
a2ae9df7 6829 return offset;
49f705c5
NHE		 6830
6831 p = ((char *)(get_vmcs12(vcpu))) + offset;
6832
6833 switch (vmcs_field_type(field)) {
6834 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6835 *ret = *((natural_width *)p);
a2ae9df7 6836 return 0;
49f705c5
NHE		 6837 case VMCS_FIELD_TYPE_U16:
6838 *ret = *((u16 *)p);
a2ae9df7 6839 return 0;
49f705c5
NHE		 6840 case VMCS_FIELD_TYPE_U32:
6841 *ret = *((u32 *)p);
a2ae9df7 6842 return 0;
49f705c5
NHE		 6843 case VMCS_FIELD_TYPE_U64:
6844 *ret = *((u64 *)p);
a2ae9df7 6845 return 0;
49f705c5 6846 default:
a2ae9df7
PB		 6847 WARN_ON(1);
6848 return -ENOENT;
49f705c5
NHE		 6849 }
6850}
6851
20b97fea 6852
a2ae9df7
PB		 6853static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6854 unsigned long field, u64 field_value){
20b97fea
AG		 6855 short offset = vmcs_field_to_offset(field);
6856 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6857 if (offset < 0)
a2ae9df7 6858 return offset;
20b97fea
AG		 6859
6860 switch (vmcs_field_type(field)) {
6861 case VMCS_FIELD_TYPE_U16:
6862 *(u16 *)p = field_value;
a2ae9df7 6863 return 0;
20b97fea
AG		 6864 case VMCS_FIELD_TYPE_U32:
6865 *(u32 *)p = field_value;
a2ae9df7 6866 return 0;
20b97fea
AG		 6867 case VMCS_FIELD_TYPE_U64:
6868 *(u64 *)p = field_value;
a2ae9df7 6869 return 0;
20b97fea
AG		 6870 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6871 *(natural_width *)p = field_value;
a2ae9df7 6872 return 0;
20b97fea 6873 default:
a2ae9df7
PB		 6874 WARN_ON(1);
6875 return -ENOENT;
20b97fea
AG		 6876 }
6877
6878}
6879
16f5b903
AG		 6880static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6881{
6882 int i;
6883 unsigned long field;
6884 u64 field_value;
6885 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6886 const unsigned long *fields = shadow_read_write_fields;
6887 const int num_fields = max_shadow_read_write_fields;
16f5b903 6888
282da870
JK		 6889 preempt_disable();
6890
16f5b903
AG		 6891 vmcs_load(shadow_vmcs);
6892
6893 for (i = 0; i < num_fields; i++) {
6894 field = fields[i];
6895 switch (vmcs_field_type(field)) {
6896 case VMCS_FIELD_TYPE_U16:
6897 field_value = vmcs_read16(field);
6898 break;
6899 case VMCS_FIELD_TYPE_U32:
6900 field_value = vmcs_read32(field);
6901 break;
6902 case VMCS_FIELD_TYPE_U64:
6903 field_value = vmcs_read64(field);
6904 break;
6905 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6906 field_value = vmcs_readl(field);
6907 break;
a2ae9df7
PB		 6908 default:
6909 WARN_ON(1);
6910 continue;
16f5b903
AG		 6911 }
6912 vmcs12_write_any(&vmx->vcpu, field, field_value);
6913 }
6914
6915 vmcs_clear(shadow_vmcs);
6916 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6917
6918 preempt_enable();
16f5b903
AG		 6919}
6920
c3114420
AG		 6921static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6922{
c2bae893
MK		 6923 const unsigned long *fields[] = {
6924 shadow_read_write_fields,
6925 shadow_read_only_fields
c3114420 6926 };
c2bae893 6927 const int max_fields[] = {
c3114420
AG		 6928 max_shadow_read_write_fields,
6929 max_shadow_read_only_fields
6930 };
6931 int i, q;
6932 unsigned long field;
6933 u64 field_value = 0;
6934 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6935
6936 vmcs_load(shadow_vmcs);
6937
c2bae893 6938 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6939 for (i = 0; i < max_fields[q]; i++) {
6940 field = fields[q][i];
6941 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6942
6943 switch (vmcs_field_type(field)) {
6944 case VMCS_FIELD_TYPE_U16:
6945 vmcs_write16(field, (u16)field_value);
6946 break;
6947 case VMCS_FIELD_TYPE_U32:
6948 vmcs_write32(field, (u32)field_value);
6949 break;
6950 case VMCS_FIELD_TYPE_U64:
6951 vmcs_write64(field, (u64)field_value);
6952 break;
6953 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6954 vmcs_writel(field, (long)field_value);
6955 break;
a2ae9df7
PB		 6956 default:
6957 WARN_ON(1);
6958 break;
c3114420
AG		 6959 }
6960 }
6961 }
6962
6963 vmcs_clear(shadow_vmcs);
6964 vmcs_load(vmx->loaded_vmcs->vmcs);
6965}
6966
49f705c5
NHE		 6967/*
6968 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6969 * used before) all generate the same failure when it is missing.
6970 */
6971static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6972{
6973 struct vcpu_vmx *vmx = to_vmx(vcpu);
6974 if (vmx->nested.current_vmptr == -1ull) {
6975 nested_vmx_failInvalid(vcpu);
6976 skip_emulated_instruction(vcpu);
6977 return 0;
6978 }
6979 return 1;
6980}
6981
6982static int handle_vmread(struct kvm_vcpu *vcpu)
6983{
6984 unsigned long field;
6985 u64 field_value;
6986 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6987 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6988 gva_t gva = 0;
6989
6990 if (!nested_vmx_check_permission(vcpu) ||
6991 !nested_vmx_check_vmcs12(vcpu))
6992 return 1;
6993
6994 /* Decode instruction info and find the field to read */
27e6fb5d 6995 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6996 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6997 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6998 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6999 skip_emulated_instruction(vcpu);
7000 return 1;
7001 }
7002 /*
7003 * Now copy part of this value to register or memory, as requested.
7004 * Note that the number of bits actually copied is 32 or 64 depending
7005 * on the guest's mode (32 or 64 bit), not on the given field's length.
7006 */
7007 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 7008 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 7009 field_value);
7010 } else {
7011 if (get_vmx_mem_address(vcpu, exit_qualification,
7012 vmx_instruction_info, &gva))
7013 return 1;
7014 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7015 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7016 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7017 }
7018
7019 nested_vmx_succeed(vcpu);
7020 skip_emulated_instruction(vcpu);
7021 return 1;
7022}
7023
7024
7025static int handle_vmwrite(struct kvm_vcpu *vcpu)
7026{
7027 unsigned long field;
7028 gva_t gva;
7029 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7030 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 7031 /* The value to write might be 32 or 64 bits, depending on L1's long
7032 * mode, and eventually we need to write that into a field of several
7033 * possible lengths. The code below first zero-extends the value to 64
7034 * bit (field_value), and then copies only the approriate number of
7035 * bits into the vmcs12 field.
7036 */
7037 u64 field_value = 0;
7038 struct x86_exception e;
7039
7040 if (!nested_vmx_check_permission(vcpu) ||
7041 !nested_vmx_check_vmcs12(vcpu))
7042 return 1;
7043
7044 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7045 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7046 (((vmx_instruction_info) >> 3) & 0xf));
7047 else {
7048 if (get_vmx_mem_address(vcpu, exit_qualification,
7049 vmx_instruction_info, &gva))
7050 return 1;
7051 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7052 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7053 kvm_inject_page_fault(vcpu, &e);
7054 return 1;
7055 }
7056 }
7057
7058
27e6fb5d 7059 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7060 if (vmcs_field_readonly(field)) {
7061 nested_vmx_failValid(vcpu,
7062 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7063 skip_emulated_instruction(vcpu);
7064 return 1;
7065 }
7066
a2ae9df7 7067 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7068 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7069 skip_emulated_instruction(vcpu);
7070 return 1;
7071 }
7072
7073 nested_vmx_succeed(vcpu);
7074 skip_emulated_instruction(vcpu);
7075 return 1;
7076}
7077
63846663
NHE		 7078/* Emulate the VMPTRLD instruction */
7079static int handle_vmptrld(struct kvm_vcpu *vcpu)
7080{
7081 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7082 gpa_t vmptr;
8a1b9dd0 7083 u32 exec_control;
63846663
NHE		 7084
7085 if (!nested_vmx_check_permission(vcpu))
7086 return 1;
7087
4291b588 7088 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7089 return 1;
63846663
NHE		 7090
7091 if (vmx->nested.current_vmptr != vmptr) {
7092 struct vmcs12 *new_vmcs12;
7093 struct page *page;
7094 page = nested_get_page(vcpu, vmptr);
7095 if (page == NULL) {
7096 nested_vmx_failInvalid(vcpu);
7097 skip_emulated_instruction(vcpu);
7098 return 1;
7099 }
7100 new_vmcs12 = kmap(page);
7101 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7102 kunmap(page);
7103 nested_release_page_clean(page);
7104 nested_vmx_failValid(vcpu,
7105 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7106 skip_emulated_instruction(vcpu);
7107 return 1;
7108 }
63846663 7109
9a2a05b9 7110 nested_release_vmcs12(vmx);
63846663
NHE		 7111 vmx->nested.current_vmptr = vmptr;
7112 vmx->nested.current_vmcs12 = new_vmcs12;
7113 vmx->nested.current_vmcs12_page = page;
012f83cb 7114 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7115 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7116 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7117 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7118 vmcs_write64(VMCS_LINK_POINTER,
7119 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7120 vmx->nested.sync_shadow_vmcs = true;
7121 }
63846663
NHE		 7122 }
7123
7124 nested_vmx_succeed(vcpu);
7125 skip_emulated_instruction(vcpu);
7126 return 1;
7127}
7128
6a4d7550
NHE		 7129/* Emulate the VMPTRST instruction */
7130static int handle_vmptrst(struct kvm_vcpu *vcpu)
7131{
7132 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7133 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7134 gva_t vmcs_gva;
7135 struct x86_exception e;
7136
7137 if (!nested_vmx_check_permission(vcpu))
7138 return 1;
7139
7140 if (get_vmx_mem_address(vcpu, exit_qualification,
7141 vmx_instruction_info, &vmcs_gva))
7142 return 1;
7143 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7144 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7145 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7146 sizeof(u64), &e)) {
7147 kvm_inject_page_fault(vcpu, &e);
7148 return 1;
7149 }
7150 nested_vmx_succeed(vcpu);
7151 skip_emulated_instruction(vcpu);
7152 return 1;
7153}
7154
bfd0a56b
NHE		 7155/* Emulate the INVEPT instruction */
7156static int handle_invept(struct kvm_vcpu *vcpu)
7157{
b9c237bb 7158 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7159 u32 vmx_instruction_info, types;
7160 unsigned long type;
7161 gva_t gva;
7162 struct x86_exception e;
7163 struct {
7164 u64 eptp, gpa;
7165 } operand;
bfd0a56b 7166
b9c237bb
WV		 7167 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7168 SECONDARY_EXEC_ENABLE_EPT) ||
7169 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7170 kvm_queue_exception(vcpu, UD_VECTOR);
7171 return 1;
7172 }
7173
7174 if (!nested_vmx_check_permission(vcpu))
7175 return 1;
7176
7177 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7178 kvm_queue_exception(vcpu, UD_VECTOR);
7179 return 1;
7180 }
7181
7182 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7183 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7184
b9c237bb 7185 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7186
7187 if (!(types & (1UL << type))) {
7188 nested_vmx_failValid(vcpu,
7189 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7190 return 1;
7191 }
7192
7193 /* According to the Intel VMX instruction reference, the memory
7194 * operand is read even if it isn't needed (e.g., for type==global)
7195 */
7196 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7197 vmx_instruction_info, &gva))
7198 return 1;
7199 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7200 sizeof(operand), &e)) {
7201 kvm_inject_page_fault(vcpu, &e);
7202 return 1;
7203 }
7204
7205 switch (type) {
bfd0a56b
NHE		 7206 case VMX_EPT_EXTENT_GLOBAL:
7207 kvm_mmu_sync_roots(vcpu);
77c3913b 7208 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7209 nested_vmx_succeed(vcpu);
7210 break;
7211 default:
4b855078 7212 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7213 BUG_ON(1);
7214 break;
7215 }
7216
7217 skip_emulated_instruction(vcpu);
7218 return 1;
7219}
7220
a642fc30
PM		 7221static int handle_invvpid(struct kvm_vcpu *vcpu)
7222{
7223 kvm_queue_exception(vcpu, UD_VECTOR);
7224 return 1;
7225}
7226
843e4330
KH		 7227static int handle_pml_full(struct kvm_vcpu *vcpu)
7228{
7229 unsigned long exit_qualification;
7230
7231 trace_kvm_pml_full(vcpu->vcpu_id);
7232
7233 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7234
7235 /*
7236 * PML buffer FULL happened while executing iret from NMI,
7237 * "blocked by NMI" bit has to be set before next VM entry.
7238 */
7239 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7240 cpu_has_virtual_nmis() &&
7241 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7242 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7243 GUEST_INTR_STATE_NMI);
7244
7245 /*
7246 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7247 * here.., and there's no userspace involvement needed for PML.
7248 */
7249 return 1;
7250}
7251
6aa8b732
AK		 7252/*
7253 * The exit handlers return 1 if the exit was handled fully and guest execution
7254 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7255 * to be done to userspace and return 0.
7256 */
772e0318 7257static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7258 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7259 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7260 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7261 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7262 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7263 [EXIT_REASON_CR_ACCESS] = handle_cr,
7264 [EXIT_REASON_DR_ACCESS] = handle_dr,
7265 [EXIT_REASON_CPUID] = handle_cpuid,
7266 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7267 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7268 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7269 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7270 [EXIT_REASON_INVD] = handle_invd,
a7052897 7271 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7272 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7273 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7274 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7275 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7276 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7277 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7278 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7279 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7280 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7281 [EXIT_REASON_VMOFF] = handle_vmoff,
7282 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7283 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7284 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7285 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7286 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7287 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7288 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7289 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7290 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7291 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7292 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7293 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7294 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7295 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7296 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7297 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7298 [EXIT_REASON_XSAVES] = handle_xsaves,
7299 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7300 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7301};
7302
7303static const int kvm_vmx_max_exit_handlers =
50a3485c 7304 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7305
908a7bdd
JK		 7306static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7307 struct vmcs12 *vmcs12)
7308{
7309 unsigned long exit_qualification;
7310 gpa_t bitmap, last_bitmap;
7311 unsigned int port;
7312 int size;
7313 u8 b;
7314
908a7bdd 7315 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7316 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7317
7318 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7319
7320 port = exit_qualification >> 16;
7321 size = (exit_qualification & 7) + 1;
7322
7323 last_bitmap = (gpa_t)-1;
7324 b = -1;
7325
7326 while (size > 0) {
7327 if (port < 0x8000)
7328 bitmap = vmcs12->io_bitmap_a;
7329 else if (port < 0x10000)
7330 bitmap = vmcs12->io_bitmap_b;
7331 else
1d804d07 7332 return true;
908a7bdd
JK		 7333 bitmap += (port & 0x7fff) / 8;
7334
7335 if (last_bitmap != bitmap)
7336 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
1d804d07 7337 return true;
908a7bdd 7338 if (b & (1 << (port & 7)))
1d804d07 7339 return true;
908a7bdd
JK		 7340
7341 port++;
7342 size--;
7343 last_bitmap = bitmap;
7344 }
7345
1d804d07 7346 return false;
908a7bdd
JK		 7347}
7348
644d711a
NHE		 7349/*
7350 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7351 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7352 * disinterest in the current event (read or write a specific MSR) by using an
7353 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7354 */
7355static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7356 struct vmcs12 *vmcs12, u32 exit_reason)
7357{
7358 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7359 gpa_t bitmap;
7360
cbd29cb6 7361 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7362 return true;
644d711a
NHE		 7363
7364 /*
7365 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7366 * for the four combinations of read/write and low/high MSR numbers.
7367 * First we need to figure out which of the four to use:
7368 */
7369 bitmap = vmcs12->msr_bitmap;
7370 if (exit_reason == EXIT_REASON_MSR_WRITE)
7371 bitmap += 2048;
7372 if (msr_index >= 0xc0000000) {
7373 msr_index -= 0xc0000000;
7374 bitmap += 1024;
7375 }
7376
7377 /* Then read the msr_index'th bit from this bitmap: */
7378 if (msr_index < 1024*8) {
7379 unsigned char b;
bd31a7f5 7380 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
1d804d07 7381 return true;
644d711a
NHE		 7382 return 1 & (b >> (msr_index & 7));
7383 } else
1d804d07 7384 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7385}
7386
7387/*
7388 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7389 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7390 * intercept (via guest_host_mask etc.) the current event.
7391 */
7392static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7393 struct vmcs12 *vmcs12)
7394{
7395 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7396 int cr = exit_qualification & 15;
7397 int reg = (exit_qualification >> 8) & 15;
1e32c079 7398 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7399
7400 switch ((exit_qualification >> 4) & 3) {
7401 case 0: /* mov to cr */
7402 switch (cr) {
7403 case 0:
7404 if (vmcs12->cr0_guest_host_mask &
7405 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7406 return true;
644d711a
NHE		 7407 break;
7408 case 3:
7409 if ((vmcs12->cr3_target_count >= 1 &&
7410 vmcs12->cr3_target_value0 == val) ||
7411 (vmcs12->cr3_target_count >= 2 &&
7412 vmcs12->cr3_target_value1 == val) ||
7413 (vmcs12->cr3_target_count >= 3 &&
7414 vmcs12->cr3_target_value2 == val) ||
7415 (vmcs12->cr3_target_count >= 4 &&
7416 vmcs12->cr3_target_value3 == val))
1d804d07 7417 return false;
644d711a 7418 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7419 return true;
644d711a
NHE		 7420 break;
7421 case 4:
7422 if (vmcs12->cr4_guest_host_mask &
7423 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7424 return true;
644d711a
NHE		 7425 break;
7426 case 8:
7427 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7428 return true;
644d711a
NHE		 7429 break;
7430 }
7431 break;
7432 case 2: /* clts */
7433 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7434 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7435 return true;
644d711a
NHE		 7436 break;
7437 case 1: /* mov from cr */
7438 switch (cr) {
7439 case 3:
7440 if (vmcs12->cpu_based_vm_exec_control &
7441 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7442 return true;
644d711a
NHE		 7443 break;
7444 case 8:
7445 if (vmcs12->cpu_based_vm_exec_control &
7446 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7447 return true;
644d711a
NHE		 7448 break;
7449 }
7450 break;
7451 case 3: /* lmsw */
7452 /*
7453 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7454 * cr0. Other attempted changes are ignored, with no exit.
7455 */
7456 if (vmcs12->cr0_guest_host_mask & 0xe &
7457 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7458 return true;
644d711a
NHE		 7459 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7460 !(vmcs12->cr0_read_shadow & 0x1) &&
7461 (val & 0x1))
1d804d07 7462 return true;
644d711a
NHE		 7463 break;
7464 }
1d804d07 7465 return false;
644d711a
NHE		 7466}
7467
7468/*
7469 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7470 * should handle it ourselves in L0 (and then continue L2). Only call this
7471 * when in is_guest_mode (L2).
7472 */
7473static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7474{
644d711a
NHE		 7475 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7476 struct vcpu_vmx *vmx = to_vmx(vcpu);
7477 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7478 u32 exit_reason = vmx->exit_reason;
644d711a 7479
542060ea
JK		 7480 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7481 vmcs_readl(EXIT_QUALIFICATION),
7482 vmx->idt_vectoring_info,
7483 intr_info,
7484 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7485 KVM_ISA_VMX);
7486
644d711a 7487 if (vmx->nested.nested_run_pending)
1d804d07 7488 return false;
644d711a
NHE		 7489
7490 if (unlikely(vmx->fail)) {
bd80158a
JK		 7491 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7492 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7493 return true;
644d711a
NHE		 7494 }
7495
7496 switch (exit_reason) {
7497 case EXIT_REASON_EXCEPTION_NMI:
7498 if (!is_exception(intr_info))
1d804d07 7499 return false;
644d711a
NHE		 7500 else if (is_page_fault(intr_info))
7501 return enable_ept;
e504c909 7502 else if (is_no_device(intr_info) &&
ccf9844e 7503 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7504 return false;
644d711a
NHE		 7505 return vmcs12->exception_bitmap &
7506 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7507 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7508 return false;
644d711a 7509 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7510 return true;
644d711a 7511 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7512 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7513 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7514 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7515 case EXIT_REASON_TASK_SWITCH:
1d804d07 7516 return true;
644d711a 7517 case EXIT_REASON_CPUID:
bc613494 7518 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7519 return false;
7520 return true;
644d711a
NHE		 7521 case EXIT_REASON_HLT:
7522 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7523 case EXIT_REASON_INVD:
1d804d07 7524 return true;
644d711a
NHE		 7525 case EXIT_REASON_INVLPG:
7526 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7527 case EXIT_REASON_RDPMC:
7528 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7529 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7530 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7531 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7532 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7533 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7534 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7535 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7536 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7537 /*
7538 * VMX instructions trap unconditionally. This allows L1 to
7539 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7540 */
1d804d07 7541 return true;
644d711a
NHE		 7542 case EXIT_REASON_CR_ACCESS:
7543 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7544 case EXIT_REASON_DR_ACCESS:
7545 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7546 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7547 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7548 case EXIT_REASON_MSR_READ:
7549 case EXIT_REASON_MSR_WRITE:
7550 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7551 case EXIT_REASON_INVALID_STATE:
1d804d07 7552 return true;
644d711a
NHE		 7553 case EXIT_REASON_MWAIT_INSTRUCTION:
7554 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7555 case EXIT_REASON_MONITOR_INSTRUCTION:
7556 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7557 case EXIT_REASON_PAUSE_INSTRUCTION:
7558 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7559 nested_cpu_has2(vmcs12,
7560 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7561 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7562 return false;
644d711a 7563 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7564 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7565 case EXIT_REASON_APIC_ACCESS:
7566 return nested_cpu_has2(vmcs12,
7567 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7568 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7569 case EXIT_REASON_EOI_INDUCED:
7570 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7571 return true;
644d711a 7572 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7573 /*
7574 * L0 always deals with the EPT violation. If nested EPT is
7575 * used, and the nested mmu code discovers that the address is
7576 * missing in the guest EPT table (EPT12), the EPT violation
7577 * will be injected with nested_ept_inject_page_fault()
7578 */
1d804d07 7579 return false;
644d711a 7580 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7581 /*
7582 * L2 never uses directly L1's EPT, but rather L0's own EPT
7583 * table (shadow on EPT) or a merged EPT table that L0 built
7584 * (EPT on EPT). So any problems with the structure of the
7585 * table is L0's fault.
7586 */
1d804d07 7587 return false;
644d711a
NHE		 7588 case EXIT_REASON_WBINVD:
7589 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7590 case EXIT_REASON_XSETBV:
1d804d07 7591 return true;
81dc01f7
WL		 7592 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7593 /*
7594 * This should never happen, since it is not possible to
7595 * set XSS to a non-zero value---neither in L1 nor in L2.
7596 * If if it were, XSS would have to be checked against
7597 * the XSS exit bitmap in vmcs12.
7598 */
7599 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a 7600 default:
1d804d07 7601 return true;
644d711a
NHE		 7602 }
7603}
7604
586f9607
AK		 7605static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7606{
7607 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7608 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7609}
7610
843e4330
KH		 7611static int vmx_enable_pml(struct vcpu_vmx *vmx)
7612{
7613 struct page *pml_pg;
7614 u32 exec_control;
7615
7616 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7617 if (!pml_pg)
7618 return -ENOMEM;
7619
7620 vmx->pml_pg = pml_pg;
7621
7622 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7623 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7624
7625 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7626 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7627 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7628
7629 return 0;
7630}
7631
7632static void vmx_disable_pml(struct vcpu_vmx *vmx)
7633{
7634 u32 exec_control;
7635
7636 ASSERT(vmx->pml_pg);
7637 __free_page(vmx->pml_pg);
7638 vmx->pml_pg = NULL;
7639
7640 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7641 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7642 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7643}
7644
7645static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7646{
7647 struct kvm *kvm = vmx->vcpu.kvm;
7648 u64 *pml_buf;
7649 u16 pml_idx;
7650
7651 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7652
7653 /* Do nothing if PML buffer is empty */
7654 if (pml_idx == (PML_ENTITY_NUM - 1))
7655 return;
7656
7657 /* PML index always points to next available PML buffer entity */
7658 if (pml_idx >= PML_ENTITY_NUM)
7659 pml_idx = 0;
7660 else
7661 pml_idx++;
7662
7663 pml_buf = page_address(vmx->pml_pg);
7664 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7665 u64 gpa;
7666
7667 gpa = pml_buf[pml_idx];
7668 WARN_ON(gpa & (PAGE_SIZE - 1));
7669 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7670 }
7671
7672 /* reset PML index */
7673 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7674}
7675
7676/*
7677 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7678 * Called before reporting dirty_bitmap to userspace.
7679 */
7680static void kvm_flush_pml_buffers(struct kvm *kvm)
7681{
7682 int i;
7683 struct kvm_vcpu *vcpu;
7684 /*
7685 * We only need to kick vcpu out of guest mode here, as PML buffer
7686 * is flushed at beginning of all VMEXITs, and it's obvious that only
7687 * vcpus running in guest are possible to have unflushed GPAs in PML
7688 * buffer.
7689 */
7690 kvm_for_each_vcpu(i, vcpu, kvm)
7691 kvm_vcpu_kick(vcpu);
7692}
7693
6aa8b732
AK		 7694/*
7695 * The guest has exited. See if we can fix it or if we need userspace
7696 * assistance.
7697 */
851ba692 7698static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7699{
29bd8a78 7700 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7701 u32 exit_reason = vmx->exit_reason;
1155f76a 7702 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7703
843e4330
KH		 7704 /*
7705 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7706 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7707 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7708 * mode as if vcpus is in root mode, the PML buffer must has been
7709 * flushed already.
7710 */
7711 if (enable_pml)
7712 vmx_flush_pml_buffer(vmx);
7713
80ced186 7714 /* If guest state is invalid, start emulating */
14168786 7715 if (vmx->emulation_required)
80ced186 7716 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7717
644d711a 7718 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7719 nested_vmx_vmexit(vcpu, exit_reason,
7720 vmcs_read32(VM_EXIT_INTR_INFO),
7721 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7722 return 1;
7723 }
7724
5120702e
MG		 7725 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7726 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7727 vcpu->run->fail_entry.hardware_entry_failure_reason
7728 = exit_reason;
7729 return 0;
7730 }
7731
29bd8a78 7732 if (unlikely(vmx->fail)) {
851ba692
AK		 7733 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7734 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7735 = vmcs_read32(VM_INSTRUCTION_ERROR);
7736 return 0;
7737 }
6aa8b732 7738
b9bf6882
XG		 7739 /*
7740 * Note:
7741 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7742 * delivery event since it indicates guest is accessing MMIO.
7743 * The vm-exit can be triggered again after return to guest that
7744 * will cause infinite loop.
7745 */
d77c26fc 7746 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7747 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7748 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7749 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7750 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7751 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7752 vcpu->run->internal.ndata = 2;
7753 vcpu->run->internal.data[0] = vectoring_info;
7754 vcpu->run->internal.data[1] = exit_reason;
7755 return 0;
7756 }
3b86cd99 7757
644d711a
NHE		 7758 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7759 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7760 get_vmcs12(vcpu))))) {
c4282df9 7761 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7762 vmx->soft_vnmi_blocked = 0;
3b86cd99 7763 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7764 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7765 /*
7766 * This CPU don't support us in finding the end of an
7767 * NMI-blocked window if the guest runs with IRQs
7768 * disabled. So we pull the trigger after 1 s of
7769 * futile waiting, but inform the user about this.
7770 */
7771 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7772 "state on VCPU %d after 1 s timeout\n",
7773 __func__, vcpu->vcpu_id);
7774 vmx->soft_vnmi_blocked = 0;
3b86cd99 7775 }
3b86cd99
JK		 7776 }
7777
6aa8b732
AK		 7778 if (exit_reason < kvm_vmx_max_exit_handlers
7779 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7780 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7781 else {
2bc19dc3
MT		 7782 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7783 kvm_queue_exception(vcpu, UD_VECTOR);
7784 return 1;
6aa8b732 7785 }
6aa8b732
AK		 7786}
7787
95ba8273 7788static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7789{
a7c0b07d
WL		 7790 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7791
7792 if (is_guest_mode(vcpu) &&
7793 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7794 return;
7795
95ba8273 7796 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7797 vmcs_write32(TPR_THRESHOLD, 0);
7798 return;
7799 }
7800
95ba8273 7801 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7802}
7803
8d14695f
YZ		 7804static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7805{
7806 u32 sec_exec_control;
7807
7808 /*
7809 * There is not point to enable virtualize x2apic without enable
7810 * apicv
7811 */
c7c9c56c
YZ		 7812 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7813 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7814 return;
7815
7816 if (!vm_need_tpr_shadow(vcpu->kvm))
7817 return;
7818
7819 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7820
7821 if (set) {
7822 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7823 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7824 } else {
7825 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7826 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7827 }
7828 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7829
7830 vmx_set_msr_bitmap(vcpu);
7831}
7832
38b99173
TC		 7833static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7834{
7835 struct vcpu_vmx *vmx = to_vmx(vcpu);
7836
7837 /*
7838 * Currently we do not handle the nested case where L2 has an
7839 * APIC access page of its own; that page is still pinned.
7840 * Hence, we skip the case where the VCPU is in guest mode _and_
7841 * L1 prepared an APIC access page for L2.
7842 *
7843 * For the case where L1 and L2 share the same APIC access page
7844 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7845 * in the vmcs12), this function will only update either the vmcs01
7846 * or the vmcs02. If the former, the vmcs02 will be updated by
7847 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7848 * the next L2->L1 exit.
7849 */
7850 if (!is_guest_mode(vcpu) ||
7851 !nested_cpu_has2(vmx->nested.current_vmcs12,
7852 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7853 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7854}
7855
c7c9c56c
YZ		 7856static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7857{
7858 u16 status;
7859 u8 old;
7860
c7c9c56c
YZ		 7861 if (isr == -1)
7862 isr = 0;
7863
7864 status = vmcs_read16(GUEST_INTR_STATUS);
7865 old = status >> 8;
7866 if (isr != old) {
7867 status &= 0xff;
7868 status |= isr << 8;
7869 vmcs_write16(GUEST_INTR_STATUS, status);
7870 }
7871}
7872
7873static void vmx_set_rvi(int vector)
7874{
7875 u16 status;
7876 u8 old;
7877
4114c27d
WW		 7878 if (vector == -1)
7879 vector = 0;
7880
c7c9c56c
YZ		 7881 status = vmcs_read16(GUEST_INTR_STATUS);
7882 old = (u8)status & 0xff;
7883 if ((u8)vector != old) {
7884 status &= ~0xff;
7885 status |= (u8)vector;
7886 vmcs_write16(GUEST_INTR_STATUS, status);
7887 }
7888}
7889
7890static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7891{
4114c27d
WW		 7892 if (!is_guest_mode(vcpu)) {
7893 vmx_set_rvi(max_irr);
7894 return;
7895 }
7896
c7c9c56c
YZ		 7897 if (max_irr == -1)
7898 return;
7899
963fee16 7900 /*
4114c27d
WW		 7901 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7902 * handles it.
963fee16 7903 */
4114c27d 7904 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7905 return;
7906
963fee16 7907 /*
4114c27d 7908 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7909 * is run without virtual interrupt delivery.
7910 */
7911 if (!kvm_event_needs_reinjection(vcpu) &&
7912 vmx_interrupt_allowed(vcpu)) {
7913 kvm_queue_interrupt(vcpu, max_irr, false);
7914 vmx_inject_irq(vcpu);
7915 }
c7c9c56c
YZ		 7916}
7917
7918static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7919{
3d81bc7e
YZ		 7920 if (!vmx_vm_has_apicv(vcpu->kvm))
7921 return;
7922
c7c9c56c
YZ		 7923 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7924 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7925 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7926 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7927}
7928
51aa01d1 7929static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7930{
00eba012
AK		 7931 u32 exit_intr_info;
7932
7933 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7934 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7935 return;
7936
c5ca8e57 7937 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7938 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7939
7940 /* Handle machine checks before interrupts are enabled */
00eba012 7941 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7942 kvm_machine_check();
7943
20f65983 7944 /* We need to handle NMIs before interrupts are enabled */
00eba012 7945 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7946 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7947 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7948 asm("int $2");
ff9d07a0
ZY		 7949 kvm_after_handle_nmi(&vmx->vcpu);
7950 }
51aa01d1 7951}
20f65983 7952
a547c6db
YZ		 7953static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7954{
7955 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7956
7957 /*
7958 * If external interrupt exists, IF bit is set in rflags/eflags on the
7959 * interrupt stack frame, and interrupt will be enabled on a return
7960 * from interrupt handler.
7961 */
7962 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7963 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7964 unsigned int vector;
7965 unsigned long entry;
7966 gate_desc *desc;
7967 struct vcpu_vmx *vmx = to_vmx(vcpu);
7968#ifdef CONFIG_X86_64
7969 unsigned long tmp;
7970#endif
7971
7972 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7973 desc = (gate_desc *)vmx->host_idt_base + vector;
7974 entry = gate_offset(*desc);
7975 asm volatile(
7976#ifdef CONFIG_X86_64
7977 "mov %%" _ASM_SP ", %[sp]\n\t"
7978 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7979 "push $%c[ss]\n\t"
7980 "push %[sp]\n\t"
7981#endif
7982 "pushf\n\t"
7983 "orl $0x200, (%%" _ASM_SP ")\n\t"
7984 __ASM_SIZE(push) " $%c[cs]\n\t"
7985 "call *%[entry]\n\t"
7986 :
7987#ifdef CONFIG_X86_64
7988 [sp]"=&r"(tmp)
7989#endif
7990 :
7991 [entry]"r"(entry),
7992 [ss]"i"(__KERNEL_DS),
7993 [cs]"i"(__KERNEL_CS)
7994 );
7995 } else
7996 local_irq_enable();
7997}
7998
da8999d3
LJ		 7999static bool vmx_mpx_supported(void)
8000{
8001 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8002 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8003}
8004
55412b2e
WL		 8005static bool vmx_xsaves_supported(void)
8006{
8007 return vmcs_config.cpu_based_2nd_exec_ctrl &
8008 SECONDARY_EXEC_XSAVES;
8009}
8010
51aa01d1
AK		 8011static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8012{
c5ca8e57 8013 u32 exit_intr_info;
51aa01d1
AK		 8014 bool unblock_nmi;
8015 u8 vector;
8016 bool idtv_info_valid;
8017
8018 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8019
cf393f75 8020 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8021 if (vmx->nmi_known_unmasked)
8022 return;
c5ca8e57
AK		 8023 /*
8024 * Can't use vmx->exit_intr_info since we're not sure what
8025 * the exit reason is.
8026 */
8027 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8028 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8029 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8030 /*
7b4a25cb 8031 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8032 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8033 * a guest IRET fault.
7b4a25cb
GN		 8034 * SDM 3: 23.2.2 (September 2008)
8035 * Bit 12 is undefined in any of the following cases:
8036 * If the VM exit sets the valid bit in the IDT-vectoring
8037 * information field.
8038 * If the VM exit is due to a double fault.
cf393f75 8039 */
7b4a25cb
GN		 8040 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8041 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8042 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8043 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8044 else
8045 vmx->nmi_known_unmasked =
8046 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8047 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8048 } else if (unlikely(vmx->soft_vnmi_blocked))
8049 vmx->vnmi_blocked_time +=
8050 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8051}
8052
3ab66e8a 8053static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8054 u32 idt_vectoring_info,
8055 int instr_len_field,
8056 int error_code_field)
51aa01d1 8057{
51aa01d1
AK		 8058 u8 vector;
8059 int type;
8060 bool idtv_info_valid;
8061
8062 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8063
3ab66e8a
JK		 8064 vcpu->arch.nmi_injected = false;
8065 kvm_clear_exception_queue(vcpu);
8066 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8067
8068 if (!idtv_info_valid)
8069 return;
8070
3ab66e8a 8071 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8072
668f612f
AK		 8073 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8074 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8075
64a7ec06 8076 switch (type) {
37b96e98 8077 case INTR_TYPE_NMI_INTR:
3ab66e8a 8078 vcpu->arch.nmi_injected = true;
668f612f 8079 /*
7b4a25cb 8080 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8081 * Clear bit "block by NMI" before VM entry if a NMI
8082 * delivery faulted.
668f612f 8083 */
3ab66e8a 8084 vmx_set_nmi_mask(vcpu, false);
37b96e98 8085 break;
37b96e98 8086 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8087 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8088 /* fall through */
8089 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8090 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8091 u32 err = vmcs_read32(error_code_field);
851eb667 8092 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8093 } else
851eb667 8094 kvm_requeue_exception(vcpu, vector);
37b96e98 8095 break;
66fd3f7f 8096 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8097 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8098 /* fall through */
37b96e98 8099 case INTR_TYPE_EXT_INTR:
3ab66e8a 8100 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8101 break;
8102 default:
8103 break;
f7d9238f 8104 }
cf393f75
AK		 8105}
8106
83422e17
AK		 8107static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8108{
3ab66e8a 8109 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8110 VM_EXIT_INSTRUCTION_LEN,
8111 IDT_VECTORING_ERROR_CODE);
8112}
8113
b463a6f7
AK		 8114static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8115{
3ab66e8a 8116 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8117 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8118 VM_ENTRY_INSTRUCTION_LEN,
8119 VM_ENTRY_EXCEPTION_ERROR_CODE);
8120
8121 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8122}
8123
d7cd9796
GN		 8124static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8125{
8126 int i, nr_msrs;
8127 struct perf_guest_switch_msr *msrs;
8128
8129 msrs = perf_guest_get_msrs(&nr_msrs);
8130
8131 if (!msrs)
8132 return;
8133
8134 for (i = 0; i < nr_msrs; i++)
8135 if (msrs[i].host == msrs[i].guest)
8136 clear_atomic_switch_msr(vmx, msrs[i].msr);
8137 else
8138 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8139 msrs[i].host);
8140}
8141
a3b5ba49 8142static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8143{
a2fa3e9f 8144 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8145 unsigned long debugctlmsr, cr4;
104f226b
AK		 8146
8147 /* Record the guest's net vcpu time for enforced NMI injections. */
8148 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8149 vmx->entry_time = ktime_get();
8150
8151 /* Don't enter VMX if guest state is invalid, let the exit handler
8152 start emulation until we arrive back to a valid state */
14168786 8153 if (vmx->emulation_required)
104f226b
AK		 8154 return;
8155
a7653ecd
RK		 8156 if (vmx->ple_window_dirty) {
8157 vmx->ple_window_dirty = false;
8158 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8159 }
8160
012f83cb
AG		 8161 if (vmx->nested.sync_shadow_vmcs) {
8162 copy_vmcs12_to_shadow(vmx);
8163 vmx->nested.sync_shadow_vmcs = false;
8164 }
8165
104f226b
AK		 8166 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8167 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8168 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8169 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8170
1e02ce4c 8171 cr4 = cr4_read_shadow();
d974baa3
AL		 8172 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8173 vmcs_writel(HOST_CR4, cr4);
8174 vmx->host_state.vmcs_host_cr4 = cr4;
8175 }
8176
104f226b
AK		 8177 /* When single-stepping over STI and MOV SS, we must clear the
8178 * corresponding interruptibility bits in the guest state. Otherwise
8179 * vmentry fails as it then expects bit 14 (BS) in pending debug
8180 * exceptions being set, but that's not correct for the guest debugging
8181 * case. */
8182 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8183 vmx_set_interrupt_shadow(vcpu, 0);
8184
d7cd9796 8185 atomic_switch_perf_msrs(vmx);
2a7921b7 8186 debugctlmsr = get_debugctlmsr();
d7cd9796 8187
d462b819 8188 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8189 asm(
6aa8b732 8190 /* Store host registers */
b188c81f
AK		 8191 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8192 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8193 "push %%" _ASM_CX " \n\t"
8194 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8195 "je 1f \n\t"
b188c81f 8196 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8197 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8198 "1: \n\t"
d3edefc0 8199 /* Reload cr2 if changed */
b188c81f
AK		 8200 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8201 "mov %%cr2, %%" _ASM_DX " \n\t"
8202 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8203 "je 2f \n\t"
b188c81f 8204 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8205 "2: \n\t"
6aa8b732 8206 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8207 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8208 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8209 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8210 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8211 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8212 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8213 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8214 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8215#ifdef CONFIG_X86_64
e08aa78a
AK		 8216 "mov %c[r8](%0), %%r8 \n\t"
8217 "mov %c[r9](%0), %%r9 \n\t"
8218 "mov %c[r10](%0), %%r10 \n\t"
8219 "mov %c[r11](%0), %%r11 \n\t"
8220 "mov %c[r12](%0), %%r12 \n\t"
8221 "mov %c[r13](%0), %%r13 \n\t"
8222 "mov %c[r14](%0), %%r14 \n\t"
8223 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8224#endif
b188c81f 8225 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8226
6aa8b732 8227 /* Enter guest mode */
83287ea4 8228 "jne 1f \n\t"
4ecac3fd 8229 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8230 "jmp 2f \n\t"
8231 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8232 "2: "
6aa8b732 8233 /* Save guest registers, load host registers, keep flags */
b188c81f 8234 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8235 "pop %0 \n\t"
b188c81f
AK		 8236 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8237 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8238 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8239 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8240 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8241 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8242 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8243#ifdef CONFIG_X86_64
e08aa78a
AK		 8244 "mov %%r8, %c[r8](%0) \n\t"
8245 "mov %%r9, %c[r9](%0) \n\t"
8246 "mov %%r10, %c[r10](%0) \n\t"
8247 "mov %%r11, %c[r11](%0) \n\t"
8248 "mov %%r12, %c[r12](%0) \n\t"
8249 "mov %%r13, %c[r13](%0) \n\t"
8250 "mov %%r14, %c[r14](%0) \n\t"
8251 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8252#endif
b188c81f
AK		 8253 "mov %%cr2, %%" _ASM_AX " \n\t"
8254 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8255
b188c81f 8256 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8257 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8258 ".pushsection .rodata \n\t"
8259 ".global vmx_return \n\t"
8260 "vmx_return: " _ASM_PTR " 2b \n\t"
8261 ".popsection"
e08aa78a 8262 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8263 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8264 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8265 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8266 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8267 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8268 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8269 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8270 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8271 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8272 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8273#ifdef CONFIG_X86_64
ad312c7c
ZX		 8274 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8275 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8276 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8277 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8278 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8279 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8280 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8281 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8282#endif
40712fae
AK		 8283 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8284 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8285 : "cc", "memory"
8286#ifdef CONFIG_X86_64
b188c81f 8287 , "rax", "rbx", "rdi", "rsi"
c2036300 8288 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8289#else
8290 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8291#endif
8292 );
6aa8b732 8293
2a7921b7
GN		 8294 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8295 if (debugctlmsr)
8296 update_debugctlmsr(debugctlmsr);
8297
aa67f609
AK		 8298#ifndef CONFIG_X86_64
8299 /*
8300 * The sysexit path does not restore ds/es, so we must set them to
8301 * a reasonable value ourselves.
8302 *
8303 * We can't defer this to vmx_load_host_state() since that function
8304 * may be executed in interrupt context, which saves and restore segments
8305 * around it, nullifying its effect.
8306 */
8307 loadsegment(ds, __USER_DS);
8308 loadsegment(es, __USER_DS);
8309#endif
8310
6de4f3ad 8311 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8312 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8313 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8314 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8315 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8316 vcpu->arch.regs_dirty = 0;
8317
1155f76a
AK		 8318 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8319
d462b819 8320 vmx->loaded_vmcs->launched = 1;
1b6269db 8321
51aa01d1 8322 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8323 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8324
e0b890d3
GN		 8325 /*
8326 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8327 * we did not inject a still-pending event to L1 now because of
8328 * nested_run_pending, we need to re-enable this bit.
8329 */
8330 if (vmx->nested.nested_run_pending)
8331 kvm_make_request(KVM_REQ_EVENT, vcpu);
8332
8333 vmx->nested.nested_run_pending = 0;
8334
51aa01d1
AK		 8335 vmx_complete_atomic_exit(vmx);
8336 vmx_recover_nmi_blocking(vmx);
cf393f75 8337 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8338}
8339
4fa7734c
PB		 8340static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8341{
8342 struct vcpu_vmx *vmx = to_vmx(vcpu);
8343 int cpu;
8344
8345 if (vmx->loaded_vmcs == &vmx->vmcs01)
8346 return;
8347
8348 cpu = get_cpu();
8349 vmx->loaded_vmcs = &vmx->vmcs01;
8350 vmx_vcpu_put(vcpu);
8351 vmx_vcpu_load(vcpu, cpu);
8352 vcpu->cpu = cpu;
8353 put_cpu();
8354}
8355
6aa8b732
AK		 8356static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8357{
fb3f0f51
RR		 8358 struct vcpu_vmx *vmx = to_vmx(vcpu);
8359
843e4330
KH		 8360 if (enable_pml)
8361 vmx_disable_pml(vmx);
cdbecfc3 8362 free_vpid(vmx);
4fa7734c
PB		 8363 leave_guest_mode(vcpu);
8364 vmx_load_vmcs01(vcpu);
26a865f4 8365 free_nested(vmx);
4fa7734c 8366 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8367 kfree(vmx->guest_msrs);
8368 kvm_vcpu_uninit(vcpu);
a4770347 8369 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8370}
8371
fb3f0f51 8372static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8373{
fb3f0f51 8374 int err;
c16f862d 8375 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8376 int cpu;
6aa8b732 8377
a2fa3e9f 8378 if (!vmx)
fb3f0f51
RR		 8379 return ERR_PTR(-ENOMEM);
8380
2384d2b3
SY		 8381 allocate_vpid(vmx);
8382
fb3f0f51
RR		 8383 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8384 if (err)
8385 goto free_vcpu;
965b58a5 8386
a2fa3e9f 8387 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8388 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8389 > PAGE_SIZE);
0123be42 8390
be6d05cf 8391 err = -ENOMEM;
fb3f0f51 8392 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8393 goto uninit_vcpu;
8394 }
965b58a5 8395
d462b819
NHE		 8396 vmx->loaded_vmcs = &vmx->vmcs01;
8397 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8398 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8399 goto free_msrs;
d462b819
NHE		 8400 if (!vmm_exclusive)
8401 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8402 loaded_vmcs_init(vmx->loaded_vmcs);
8403 if (!vmm_exclusive)
8404 kvm_cpu_vmxoff();
a2fa3e9f 8405
15ad7146
AK		 8406 cpu = get_cpu();
8407 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8408 vmx->vcpu.cpu = cpu;
8b9cf98c 8409 err = vmx_vcpu_setup(vmx);
fb3f0f51 8410 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8411 put_cpu();
fb3f0f51
RR		 8412 if (err)
8413 goto free_vmcs;
a63cb560 8414 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8415 err = alloc_apic_access_page(kvm);
8416 if (err)
5e4a0b3c 8417 goto free_vmcs;
a63cb560 8418 }
fb3f0f51 8419
b927a3ce
SY		 8420 if (enable_ept) {
8421 if (!kvm->arch.ept_identity_map_addr)
8422 kvm->arch.ept_identity_map_addr =
8423 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8424 err = init_rmode_identity_map(kvm);
8425 if (err)
93ea5388 8426 goto free_vmcs;
b927a3ce 8427 }
b7ebfb05 8428
b9c237bb
WV		 8429 if (nested)
8430 nested_vmx_setup_ctls_msrs(vmx);
8431
705699a1 8432 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8433 vmx->nested.current_vmptr = -1ull;
8434 vmx->nested.current_vmcs12 = NULL;
8435
843e4330
KH		 8436 /*
8437 * If PML is turned on, failure on enabling PML just results in failure
8438 * of creating the vcpu, therefore we can simplify PML logic (by
8439 * avoiding dealing with cases, such as enabling PML partially on vcpus
8440 * for the guest, etc.
8441 */
8442 if (enable_pml) {
8443 err = vmx_enable_pml(vmx);
8444 if (err)
8445 goto free_vmcs;
8446 }
8447
fb3f0f51
RR		 8448 return &vmx->vcpu;
8449
8450free_vmcs:
5f3fbc34 8451 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8452free_msrs:
fb3f0f51
RR		 8453 kfree(vmx->guest_msrs);
8454uninit_vcpu:
8455 kvm_vcpu_uninit(&vmx->vcpu);
8456free_vcpu:
cdbecfc3 8457 free_vpid(vmx);
a4770347 8458 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8459 return ERR_PTR(err);
6aa8b732
AK		 8460}
8461
002c7f7c
YS		 8462static void __init vmx_check_processor_compat(void *rtn)
8463{
8464 struct vmcs_config vmcs_conf;
8465
8466 *(int *)rtn = 0;
8467 if (setup_vmcs_config(&vmcs_conf) < 0)
8468 *(int *)rtn = -EIO;
8469 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8470 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8471 smp_processor_id());
8472 *(int *)rtn = -EIO;
8473 }
8474}
8475
67253af5
SY		 8476static int get_ept_level(void)
8477{
8478 return VMX_EPT_DEFAULT_GAW + 1;
8479}
8480
4b12f0de 8481static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8482{
4b12f0de
SY		 8483 u64 ret;
8484
522c68c4
SY		 8485 /* For VT-d and EPT combination
8486 * 1. MMIO: always map as UC
8487 * 2. EPT with VT-d:
8488 * a. VT-d without snooping control feature: can't guarantee the
8489 * result, try to trust guest.
8490 * b. VT-d with snooping control feature: snooping control feature of
8491 * VT-d engine can guarantee the cache correctness. Just set it
8492 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8493 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8494 * consistent with host MTRR
8495 */
4b12f0de
SY		 8496 if (is_mmio)
8497 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8498 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8499 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8500 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8501 else
522c68c4 8502 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8503 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8504
8505 return ret;
64d4d521
SY		 8506}
8507
17cc3935 8508static int vmx_get_lpage_level(void)
344f414f 8509{
878403b7
SY		 8510 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8511 return PT_DIRECTORY_LEVEL;
8512 else
8513 /* For shadow and EPT supported 1GB page */
8514 return PT_PDPE_LEVEL;
344f414f
JR		 8515}
8516
0e851880
SY		 8517static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8518{
4e47c7a6
SY		 8519 struct kvm_cpuid_entry2 *best;
8520 struct vcpu_vmx *vmx = to_vmx(vcpu);
8521 u32 exec_control;
8522
8523 vmx->rdtscp_enabled = false;
8524 if (vmx_rdtscp_supported()) {
8525 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8526 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8527 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8528 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8529 vmx->rdtscp_enabled = true;
8530 else {
8531 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8532 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8533 exec_control);
8534 }
8535 }
b3a2a907
JK		 8536 if (nested && !vmx->rdtscp_enabled)
8537 vmx->nested.nested_vmx_secondary_ctls_high &=
8538 ~SECONDARY_EXEC_RDTSCP;
4e47c7a6 8539 }
ad756a16 8540
ad756a16
MJ		 8541 /* Exposing INVPCID only when PCID is exposed */
8542 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8543 if (vmx_invpcid_supported() &&
4f977045 8544 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8545 guest_cpuid_has_pcid(vcpu)) {
29282fde 8546 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8547 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8548 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8549 exec_control);
8550 } else {
29282fde
TI		 8551 if (cpu_has_secondary_exec_ctrls()) {
8552 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8553 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8554 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8555 exec_control);
8556 }
ad756a16 8557 if (best)
4f977045 8558 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8559 }
0e851880
SY		 8560}
8561
d4330ef2
JR		 8562static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8563{
7b8050f5
NHE		 8564 if (func == 1 && nested)
8565 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8566}
8567
25d92081
YZ		 8568static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8569 struct x86_exception *fault)
8570{
533558bc
JK		 8571 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8572 u32 exit_reason;
25d92081
YZ		 8573
8574 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8575 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8576 else
533558bc
JK		 8577 exit_reason = EXIT_REASON_EPT_VIOLATION;
8578 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8579 vmcs12->guest_physical_address = fault->address;
8580}
8581
155a97a3
NHE		 8582/* Callbacks for nested_ept_init_mmu_context: */
8583
8584static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8585{
8586 /* return the page table to be shadowed - in our case, EPT12 */
8587 return get_vmcs12(vcpu)->ept_pointer;
8588}
8589
8a3c1a33 8590static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8591{
ad896af0
PB		 8592 WARN_ON(mmu_is_nested(vcpu));
8593 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8594 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8595 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8596 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8597 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8598 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8599
8600 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8601}
8602
8603static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8604{
8605 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8606}
8607
19d5f10b
EK		 8608static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8609 u16 error_code)
8610{
8611 bool inequality, bit;
8612
8613 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8614 inequality =
8615 (error_code & vmcs12->page_fault_error_code_mask) !=
8616 vmcs12->page_fault_error_code_match;
8617 return inequality ^ bit;
8618}
8619
feaf0c7d
GN		 8620static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8621 struct x86_exception *fault)
8622{
8623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8624
8625 WARN_ON(!is_guest_mode(vcpu));
8626
19d5f10b 8627 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8628 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8629 vmcs_read32(VM_EXIT_INTR_INFO),
8630 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8631 else
8632 kvm_inject_page_fault(vcpu, fault);
8633}
8634
a2bcba50
WL		 8635static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8636 struct vmcs12 *vmcs12)
8637{
8638 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8639 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8640
8641 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8642 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8643 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8644 return false;
8645
8646 /*
8647 * Translate L1 physical address to host physical
8648 * address for vmcs02. Keep the page pinned, so this
8649 * physical address remains valid. We keep a reference
8650 * to it so we can release it later.
8651 */
8652 if (vmx->nested.apic_access_page) /* shouldn't happen */
8653 nested_release_page(vmx->nested.apic_access_page);
8654 vmx->nested.apic_access_page =
8655 nested_get_page(vcpu, vmcs12->apic_access_addr);
8656 }
a7c0b07d
WL		 8657
8658 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8659 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8660 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8661 return false;
8662
8663 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8664 nested_release_page(vmx->nested.virtual_apic_page);
8665 vmx->nested.virtual_apic_page =
8666 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8667
8668 /*
8669 * Failing the vm entry is _not_ what the processor does
8670 * but it's basically the only possibility we have.
8671 * We could still enter the guest if CR8 load exits are
8672 * enabled, CR8 store exits are enabled, and virtualize APIC
8673 * access is disabled; in this case the processor would never
8674 * use the TPR shadow and we could simply clear the bit from
8675 * the execution control. But such a configuration is useless,
8676 * so let's keep the code simple.
8677 */
8678 if (!vmx->nested.virtual_apic_page)
8679 return false;
8680 }
8681
705699a1 8682 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8683 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8684 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8685 return false;
8686
8687 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8688 kunmap(vmx->nested.pi_desc_page);
8689 nested_release_page(vmx->nested.pi_desc_page);
8690 }
8691 vmx->nested.pi_desc_page =
8692 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8693 if (!vmx->nested.pi_desc_page)
8694 return false;
8695
8696 vmx->nested.pi_desc =
8697 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8698 if (!vmx->nested.pi_desc) {
8699 nested_release_page_clean(vmx->nested.pi_desc_page);
8700 return false;
8701 }
8702 vmx->nested.pi_desc =
8703 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8704 (unsigned long)(vmcs12->posted_intr_desc_addr &
8705 (PAGE_SIZE - 1)));
8706 }
8707
a2bcba50
WL		 8708 return true;
8709}
8710
f4124500
JK		 8711static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8712{
8713 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8714 struct vcpu_vmx *vmx = to_vmx(vcpu);
8715
8716 if (vcpu->arch.virtual_tsc_khz == 0)
8717 return;
8718
8719 /* Make sure short timeouts reliably trigger an immediate vmexit.
8720 * hrtimer_start does not guarantee this. */
8721 if (preemption_timeout <= 1) {
8722 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8723 return;
8724 }
8725
8726 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8727 preemption_timeout *= 1000000;
8728 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8729 hrtimer_start(&vmx->nested.preemption_timer,
8730 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8731}
8732
3af18d9c
WV		 8733static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8734 struct vmcs12 *vmcs12)
8735{
8736 int maxphyaddr;
8737 u64 addr;
8738
8739 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8740 return 0;
8741
8742 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8743 WARN_ON(1);
8744 return -EINVAL;
8745 }
8746 maxphyaddr = cpuid_maxphyaddr(vcpu);
8747
8748 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8749 ((addr + PAGE_SIZE) >> maxphyaddr))
8750 return -EINVAL;
8751
8752 return 0;
8753}
8754
8755/*
8756 * Merge L0's and L1's MSR bitmap, return false to indicate that
8757 * we do not use the hardware.
8758 */
8759static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8760 struct vmcs12 *vmcs12)
8761{
82f0dd4b 8762 int msr;
f2b93280
WV		 8763 struct page *page;
8764 unsigned long *msr_bitmap;
8765
8766 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8767 return false;
8768
8769 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8770 if (!page) {
8771 WARN_ON(1);
8772 return false;
8773 }
8774 msr_bitmap = (unsigned long *)kmap(page);
8775 if (!msr_bitmap) {
8776 nested_release_page_clean(page);
8777 WARN_ON(1);
8778 return false;
8779 }
8780
8781 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8782 if (nested_cpu_has_apic_reg_virt(vmcs12))
8783 for (msr = 0x800; msr <= 0x8ff; msr++)
8784 nested_vmx_disable_intercept_for_msr(
8785 msr_bitmap,
8786 vmx_msr_bitmap_nested,
8787 msr, MSR_TYPE_R);
f2b93280
WV		 8788 /* TPR is allowed */
8789 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8790 vmx_msr_bitmap_nested,
8791 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8792 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8793 if (nested_cpu_has_vid(vmcs12)) {
8794 /* EOI and self-IPI are allowed */
8795 nested_vmx_disable_intercept_for_msr(
8796 msr_bitmap,
8797 vmx_msr_bitmap_nested,
8798 APIC_BASE_MSR + (APIC_EOI >> 4),
8799 MSR_TYPE_W);
8800 nested_vmx_disable_intercept_for_msr(
8801 msr_bitmap,
8802 vmx_msr_bitmap_nested,
8803 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8804 MSR_TYPE_W);
8805 }
82f0dd4b
WV		 8806 } else {
8807 /*
8808 * Enable reading intercept of all the x2apic
8809 * MSRs. We should not rely on vmcs12 to do any
8810 * optimizations here, it may have been modified
8811 * by L1.
8812 */
8813 for (msr = 0x800; msr <= 0x8ff; msr++)
8814 __vmx_enable_intercept_for_msr(
8815 vmx_msr_bitmap_nested,
8816 msr,
8817 MSR_TYPE_R);
8818
f2b93280
WV		 8819 __vmx_enable_intercept_for_msr(
8820 vmx_msr_bitmap_nested,
8821 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8822 MSR_TYPE_W);
608406e2
WV		 8823 __vmx_enable_intercept_for_msr(
8824 vmx_msr_bitmap_nested,
8825 APIC_BASE_MSR + (APIC_EOI >> 4),
8826 MSR_TYPE_W);
8827 __vmx_enable_intercept_for_msr(
8828 vmx_msr_bitmap_nested,
8829 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8830 MSR_TYPE_W);
82f0dd4b 8831 }
f2b93280
WV		 8832 kunmap(page);
8833 nested_release_page_clean(page);
8834
8835 return true;
8836}
8837
8838static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8839 struct vmcs12 *vmcs12)
8840{
82f0dd4b 8841 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 8842 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 8843 !nested_cpu_has_vid(vmcs12) &&
8844 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 8845 return 0;
8846
8847 /*
8848 * If virtualize x2apic mode is enabled,
8849 * virtualize apic access must be disabled.
8850 */
82f0dd4b
WV		 8851 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8852 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 8853 return -EINVAL;
8854
608406e2
WV		 8855 /*
8856 * If virtual interrupt delivery is enabled,
8857 * we must exit on external interrupts.
8858 */
8859 if (nested_cpu_has_vid(vmcs12) &&
8860 !nested_exit_on_intr(vcpu))
8861 return -EINVAL;
8862
705699a1
WV		 8863 /*
8864 * bits 15:8 should be zero in posted_intr_nv,
8865 * the descriptor address has been already checked
8866 * in nested_get_vmcs12_pages.
8867 */
8868 if (nested_cpu_has_posted_intr(vmcs12) &&
8869 (!nested_cpu_has_vid(vmcs12) ||
8870 !nested_exit_intr_ack_set(vcpu) ||
8871 vmcs12->posted_intr_nv & 0xff00))
8872 return -EINVAL;
8873
f2b93280
WV		 8874 /* tpr shadow is needed by all apicv features. */
8875 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8876 return -EINVAL;
8877
8878 return 0;
3af18d9c
WV		 8879}
8880
e9ac033e
EK		 8881static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8882 unsigned long count_field,
92d71bc6 8883 unsigned long addr_field)
ff651cb6 8884{
92d71bc6 8885 int maxphyaddr;
e9ac033e
EK		 8886 u64 count, addr;
8887
8888 if (vmcs12_read_any(vcpu, count_field, &count) ||
8889 vmcs12_read_any(vcpu, addr_field, &addr)) {
8890 WARN_ON(1);
8891 return -EINVAL;
8892 }
8893 if (count == 0)
8894 return 0;
92d71bc6 8895 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 8896 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8897 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8898 pr_warn_ratelimited(
8899 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8900 addr_field, maxphyaddr, count, addr);
8901 return -EINVAL;
8902 }
8903 return 0;
8904}
8905
8906static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8907 struct vmcs12 *vmcs12)
8908{
e9ac033e
EK		 8909 if (vmcs12->vm_exit_msr_load_count == 0 &&
8910 vmcs12->vm_exit_msr_store_count == 0 &&
8911 vmcs12->vm_entry_msr_load_count == 0)
8912 return 0; /* Fast path */
e9ac033e 8913 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 8914 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 8915 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 8916 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 8917 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 8918 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 8919 return -EINVAL;
8920 return 0;
8921}
8922
8923static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8924 struct vmx_msr_entry *e)
8925{
8926 /* x2APIC MSR accesses are not allowed */
8927 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8928 return -EINVAL;
8929 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8930 e->index == MSR_IA32_UCODE_REV)
8931 return -EINVAL;
8932 if (e->reserved != 0)
ff651cb6
WV		 8933 return -EINVAL;
8934 return 0;
8935}
8936
e9ac033e
EK		 8937static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8938 struct vmx_msr_entry *e)
ff651cb6
WV		 8939{
8940 if (e->index == MSR_FS_BASE ||
8941 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8942 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8943 nested_vmx_msr_check_common(vcpu, e))
8944 return -EINVAL;
8945 return 0;
8946}
8947
8948static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8949 struct vmx_msr_entry *e)
8950{
8951 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8952 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8953 return -EINVAL;
8954 return 0;
8955}
8956
8957/*
8958 * Load guest's/host's msr at nested entry/exit.
8959 * return 0 for success, entry index for failure.
8960 */
8961static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8962{
8963 u32 i;
8964 struct vmx_msr_entry e;
8965 struct msr_data msr;
8966
8967 msr.host_initiated = false;
8968 for (i = 0; i < count; i++) {
e9ac033e
EK		 8969 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8970 &e, sizeof(e))) {
8971 pr_warn_ratelimited(
8972 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8973 __func__, i, gpa + i * sizeof(e));
ff651cb6 8974 goto fail;
e9ac033e
EK		 8975 }
8976 if (nested_vmx_load_msr_check(vcpu, &e)) {
8977 pr_warn_ratelimited(
8978 "%s check failed (%u, 0x%x, 0x%x)\n",
8979 __func__, i, e.index, e.reserved);
8980 goto fail;
8981 }
ff651cb6
WV		 8982 msr.index = e.index;
8983 msr.data = e.value;
e9ac033e
EK		 8984 if (kvm_set_msr(vcpu, &msr)) {
8985 pr_warn_ratelimited(
8986 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8987 __func__, i, e.index, e.value);
ff651cb6 8988 goto fail;
e9ac033e 8989 }
ff651cb6
WV		 8990 }
8991 return 0;
8992fail:
8993 return i + 1;
8994}
8995
8996static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8997{
8998 u32 i;
8999 struct vmx_msr_entry e;
9000
9001 for (i = 0; i < count; i++) {
e9ac033e
EK		 9002 if (kvm_read_guest(vcpu->kvm,
9003 gpa + i * sizeof(e),
9004 &e, 2 * sizeof(u32))) {
9005 pr_warn_ratelimited(
9006 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9007 __func__, i, gpa + i * sizeof(e));
ff651cb6 9008 return -EINVAL;
e9ac033e
EK		 9009 }
9010 if (nested_vmx_store_msr_check(vcpu, &e)) {
9011 pr_warn_ratelimited(
9012 "%s check failed (%u, 0x%x, 0x%x)\n",
9013 __func__, i, e.index, e.reserved);
ff651cb6 9014 return -EINVAL;
e9ac033e
EK		 9015 }
9016 if (kvm_get_msr(vcpu, e.index, &e.value)) {
9017 pr_warn_ratelimited(
9018 "%s cannot read MSR (%u, 0x%x)\n",
9019 __func__, i, e.index);
9020 return -EINVAL;
9021 }
9022 if (kvm_write_guest(vcpu->kvm,
9023 gpa + i * sizeof(e) +
ff651cb6 9024 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 9025 &e.value, sizeof(e.value))) {
9026 pr_warn_ratelimited(
9027 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9028 __func__, i, e.index, e.value);
9029 return -EINVAL;
9030 }
ff651cb6
WV		 9031 }
9032 return 0;
9033}
9034
fe3ef05c
NHE		 9035/*
9036 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9037 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9038 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9039 * guest in a way that will both be appropriate to L1's requests, and our
9040 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9041 * function also has additional necessary side-effects, like setting various
9042 * vcpu->arch fields.
9043 */
9044static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9045{
9046 struct vcpu_vmx *vmx = to_vmx(vcpu);
9047 u32 exec_control;
9048
9049 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9050 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9051 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9052 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9053 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9054 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9055 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9056 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9057 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9058 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9059 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9060 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9061 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9062 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9063 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9064 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9065 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9066 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9067 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9068 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9069 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9070 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9071 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9072 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9073 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9074 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9075 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9076 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9077 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9078 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9079 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9080 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9081 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9082 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9083 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9084 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9085
2996fca0
JK		 9086 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9087 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9088 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9089 } else {
9090 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9091 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9092 }
fe3ef05c
NHE		 9093 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9094 vmcs12->vm_entry_intr_info_field);
9095 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9096 vmcs12->vm_entry_exception_error_code);
9097 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9098 vmcs12->vm_entry_instruction_len);
9099 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9100 vmcs12->guest_interruptibility_info);
fe3ef05c 9101 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9102 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9103 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9104 vmcs12->guest_pending_dbg_exceptions);
9105 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9106 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9107
81dc01f7
WL		 9108 if (nested_cpu_has_xsaves(vmcs12))
9109 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9110 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9111
f4124500
JK		 9112 exec_control = vmcs12->pin_based_vm_exec_control;
9113 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9114 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9115
9116 if (nested_cpu_has_posted_intr(vmcs12)) {
9117 /*
9118 * Note that we use L0's vector here and in
9119 * vmx_deliver_nested_posted_interrupt.
9120 */
9121 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9122 vmx->nested.pi_pending = false;
9123 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9124 vmcs_write64(POSTED_INTR_DESC_ADDR,
9125 page_to_phys(vmx->nested.pi_desc_page) +
9126 (unsigned long)(vmcs12->posted_intr_desc_addr &
9127 (PAGE_SIZE - 1)));
9128 } else
9129 exec_control &= ~PIN_BASED_POSTED_INTR;
9130
f4124500 9131 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9132
f4124500
JK		 9133 vmx->nested.preemption_timer_expired = false;
9134 if (nested_cpu_has_preemption_timer(vmcs12))
9135 vmx_start_preemption_timer(vcpu);
0238ea91 9136
fe3ef05c
NHE		 9137 /*
9138 * Whether page-faults are trapped is determined by a combination of
9139 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9140 * If enable_ept, L0 doesn't care about page faults and we should
9141 * set all of these to L1's desires. However, if !enable_ept, L0 does
9142 * care about (at least some) page faults, and because it is not easy
9143 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9144 * to exit on each and every L2 page fault. This is done by setting
9145 * MASK=MATCH=0 and (see below) EB.PF=1.
9146 * Note that below we don't need special code to set EB.PF beyond the
9147 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9148 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9149 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9150 *
9151 * A problem with this approach (when !enable_ept) is that L1 may be
9152 * injected with more page faults than it asked for. This could have
9153 * caused problems, but in practice existing hypervisors don't care.
9154 * To fix this, we will need to emulate the PFEC checking (on the L1
9155 * page tables), using walk_addr(), when injecting PFs to L1.
9156 */
9157 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9158 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9159 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9160 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9161
9162 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9163 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 9164 if (!vmx->rdtscp_enabled)
9165 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9166 /* Take the following fields only from vmcs12 */
696dfd95 9167 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9168 SECONDARY_EXEC_RDTSCP |
696dfd95 9169 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
b3a2a907 9170 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 9171 if (nested_cpu_has(vmcs12,
9172 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9173 exec_control |= vmcs12->secondary_vm_exec_control;
9174
9175 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9176 /*
9177 * If translation failed, no matter: This feature asks
9178 * to exit when accessing the given address, and if it
9179 * can never be accessed, this feature won't do
9180 * anything anyway.
9181 */
9182 if (!vmx->nested.apic_access_page)
9183 exec_control &=
9184 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9185 else
9186 vmcs_write64(APIC_ACCESS_ADDR,
9187 page_to_phys(vmx->nested.apic_access_page));
f2b93280
WV		 9188 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9189 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
ca3f257a
JK		 9190 exec_control |=
9191 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9192 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9193 }
9194
608406e2
WV		 9195 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9196 vmcs_write64(EOI_EXIT_BITMAP0,
9197 vmcs12->eoi_exit_bitmap0);
9198 vmcs_write64(EOI_EXIT_BITMAP1,
9199 vmcs12->eoi_exit_bitmap1);
9200 vmcs_write64(EOI_EXIT_BITMAP2,
9201 vmcs12->eoi_exit_bitmap2);
9202 vmcs_write64(EOI_EXIT_BITMAP3,
9203 vmcs12->eoi_exit_bitmap3);
9204 vmcs_write16(GUEST_INTR_STATUS,
9205 vmcs12->guest_intr_status);
9206 }
9207
fe3ef05c
NHE		 9208 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9209 }
9210
9211
9212 /*
9213 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9214 * Some constant fields are set here by vmx_set_constant_host_state().
9215 * Other fields are different per CPU, and will be set later when
9216 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9217 */
a547c6db 9218 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9219
9220 /*
9221 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9222 * entry, but only if the current (host) sp changed from the value
9223 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9224 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9225 * here we just force the write to happen on entry.
9226 */
9227 vmx->host_rsp = 0;
9228
9229 exec_control = vmx_exec_control(vmx); /* L0's desires */
9230 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9231 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9232 exec_control &= ~CPU_BASED_TPR_SHADOW;
9233 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9234
9235 if (exec_control & CPU_BASED_TPR_SHADOW) {
9236 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9237 page_to_phys(vmx->nested.virtual_apic_page));
9238 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9239 }
9240
3af18d9c 9241 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9242 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9243 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9244 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9245 } else
9246 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9247
fe3ef05c 9248 /*
3af18d9c 9249 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9250 * Rather, exit every time.
9251 */
fe3ef05c
NHE		 9252 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9253 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9254
9255 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9256
9257 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9258 * bitwise-or of what L1 wants to trap for L2, and what we want to
9259 * trap. Note that CR0.TS also needs updating - we do this later.
9260 */
9261 update_exception_bitmap(vcpu);
9262 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9263 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9264
8049d651
NHE		 9265 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9266 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9267 * bits are further modified by vmx_set_efer() below.
9268 */
f4124500 9269 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9270
9271 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9272 * emulated by vmx_set_efer(), below.
9273 */
2961e876 9274 vm_entry_controls_init(vmx,
8049d651
NHE		 9275 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9276 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9277 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9278
44811c02 9279 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9280 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9281 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9282 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9283 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9284
9285
9286 set_cr4_guest_host_mask(vmx);
9287
36be0b9d
PB		 9288 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9289 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9290
27fc51b2
NHE		 9291 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9292 vmcs_write64(TSC_OFFSET,
9293 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9294 else
9295 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9296
9297 if (enable_vpid) {
9298 /*
9299 * Trivially support vpid by letting L2s share their parent
9300 * L1's vpid. TODO: move to a more elaborate solution, giving
9301 * each L2 its own vpid and exposing the vpid feature to L1.
9302 */
9303 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9304 vmx_flush_tlb(vcpu);
9305 }
9306
155a97a3
NHE		 9307 if (nested_cpu_has_ept(vmcs12)) {
9308 kvm_mmu_unload(vcpu);
9309 nested_ept_init_mmu_context(vcpu);
9310 }
9311
fe3ef05c
NHE		 9312 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9313 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9314 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9315 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9316 else
9317 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9318 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9319 vmx_set_efer(vcpu, vcpu->arch.efer);
9320
9321 /*
9322 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9323 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9324 * The CR0_READ_SHADOW is what L2 should have expected to read given
9325 * the specifications by L1; It's not enough to take
9326 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9327 * have more bits than L1 expected.
9328 */
9329 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9330 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9331
9332 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9333 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9334
9335 /* shadow page tables on either EPT or shadow page tables */
9336 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9337 kvm_mmu_reset_context(vcpu);
9338
feaf0c7d
GN		 9339 if (!enable_ept)
9340 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9341
3633cfc3
NHE		 9342 /*
9343 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9344 */
9345 if (enable_ept) {
9346 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9347 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9348 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9349 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9350 }
9351
fe3ef05c
NHE		 9352 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9353 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9354}
9355
cd232ad0
NHE		 9356/*
9357 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9358 * for running an L2 nested guest.
9359 */
9360static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9361{
9362 struct vmcs12 *vmcs12;
9363 struct vcpu_vmx *vmx = to_vmx(vcpu);
9364 int cpu;
9365 struct loaded_vmcs *vmcs02;
384bb783 9366 bool ia32e;
ff651cb6 9367 u32 msr_entry_idx;
cd232ad0
NHE		 9368
9369 if (!nested_vmx_check_permission(vcpu) ||
9370 !nested_vmx_check_vmcs12(vcpu))
9371 return 1;
9372
9373 skip_emulated_instruction(vcpu);
9374 vmcs12 = get_vmcs12(vcpu);
9375
012f83cb
AG		 9376 if (enable_shadow_vmcs)
9377 copy_shadow_to_vmcs12(vmx);
9378
7c177938
NHE		 9379 /*
9380 * The nested entry process starts with enforcing various prerequisites
9381 * on vmcs12 as required by the Intel SDM, and act appropriately when
9382 * they fail: As the SDM explains, some conditions should cause the
9383 * instruction to fail, while others will cause the instruction to seem
9384 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9385 * To speed up the normal (success) code path, we should avoid checking
9386 * for misconfigurations which will anyway be caught by the processor
9387 * when using the merged vmcs02.
9388 */
9389 if (vmcs12->launch_state == launch) {
9390 nested_vmx_failValid(vcpu,
9391 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9392 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9393 return 1;
9394 }
9395
6dfacadd
JK		 9396 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9397 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9398 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9399 return 1;
9400 }
9401
3af18d9c 9402 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9403 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9404 return 1;
9405 }
9406
3af18d9c 9407 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9408 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9409 return 1;
9410 }
9411
f2b93280
WV		 9412 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9413 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9414 return 1;
9415 }
9416
e9ac033e
EK		 9417 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9418 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9419 return 1;
9420 }
9421
7c177938 9422 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9423 vmx->nested.nested_vmx_true_procbased_ctls_low,
9424 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9425 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9426 vmx->nested.nested_vmx_secondary_ctls_low,
9427 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9428 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9429 vmx->nested.nested_vmx_pinbased_ctls_low,
9430 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9431 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9432 vmx->nested.nested_vmx_true_exit_ctls_low,
9433 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9434 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9435 vmx->nested.nested_vmx_true_entry_ctls_low,
9436 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9437 {
9438 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9439 return 1;
9440 }
9441
9442 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9443 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9444 nested_vmx_failValid(vcpu,
9445 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9446 return 1;
9447 }
9448
b9c237bb 9449 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9450 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9451 nested_vmx_entry_failure(vcpu, vmcs12,
9452 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9453 return 1;
9454 }
9455 if (vmcs12->vmcs_link_pointer != -1ull) {
9456 nested_vmx_entry_failure(vcpu, vmcs12,
9457 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9458 return 1;
9459 }
9460
384bb783 9461 /*
cb0c8cda 9462 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9463 * are performed on the field for the IA32_EFER MSR:
9464 * - Bits reserved in the IA32_EFER MSR must be 0.
9465 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9466 * the IA-32e mode guest VM-exit control. It must also be identical
9467 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9468 * CR0.PG) is 1.
9469 */
9470 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9471 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9472 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9473 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9474 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9475 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9476 nested_vmx_entry_failure(vcpu, vmcs12,
9477 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9478 return 1;
9479 }
9480 }
9481
9482 /*
9483 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9484 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9485 * the values of the LMA and LME bits in the field must each be that of
9486 * the host address-space size VM-exit control.
9487 */
9488 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9489 ia32e = (vmcs12->vm_exit_controls &
9490 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9491 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9492 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9493 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9494 nested_vmx_entry_failure(vcpu, vmcs12,
9495 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9496 return 1;
9497 }
9498 }
9499
7c177938
NHE		 9500 /*
9501 * We're finally done with prerequisite checking, and can start with
9502 * the nested entry.
9503 */
9504
cd232ad0
NHE		 9505 vmcs02 = nested_get_current_vmcs02(vmx);
9506 if (!vmcs02)
9507 return -ENOMEM;
9508
9509 enter_guest_mode(vcpu);
9510
9511 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9512
2996fca0
JK		 9513 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9514 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9515
cd232ad0
NHE		 9516 cpu = get_cpu();
9517 vmx->loaded_vmcs = vmcs02;
9518 vmx_vcpu_put(vcpu);
9519 vmx_vcpu_load(vcpu, cpu);
9520 vcpu->cpu = cpu;
9521 put_cpu();
9522
36c3cc42
JK		 9523 vmx_segment_cache_clear(vmx);
9524
cd232ad0
NHE		 9525 prepare_vmcs02(vcpu, vmcs12);
9526
ff651cb6
WV		 9527 msr_entry_idx = nested_vmx_load_msr(vcpu,
9528 vmcs12->vm_entry_msr_load_addr,
9529 vmcs12->vm_entry_msr_load_count);
9530 if (msr_entry_idx) {
9531 leave_guest_mode(vcpu);
9532 vmx_load_vmcs01(vcpu);
9533 nested_vmx_entry_failure(vcpu, vmcs12,
9534 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9535 return 1;
9536 }
9537
9538 vmcs12->launch_state = 1;
9539
6dfacadd 9540 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9541 return kvm_vcpu_halt(vcpu);
6dfacadd 9542
7af40ad3
JK		 9543 vmx->nested.nested_run_pending = 1;
9544
cd232ad0
NHE		 9545 /*
9546 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9547 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9548 * returned as far as L1 is concerned. It will only return (and set
9549 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9550 */
9551 return 1;
9552}
9553
4704d0be
NHE		 9554/*
9555 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9556 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9557 * This function returns the new value we should put in vmcs12.guest_cr0.
9558 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9559 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9560 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9561 * didn't trap the bit, because if L1 did, so would L0).
9562 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9563 * been modified by L2, and L1 knows it. So just leave the old value of
9564 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9565 * isn't relevant, because if L0 traps this bit it can set it to anything.
9566 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9567 * changed these bits, and therefore they need to be updated, but L0
9568 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9569 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9570 */
9571static inline unsigned long
9572vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9573{
9574 return
9575 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9576 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9577 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9578 vcpu->arch.cr0_guest_owned_bits));
9579}
9580
9581static inline unsigned long
9582vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9583{
9584 return
9585 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9586 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9587 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9588 vcpu->arch.cr4_guest_owned_bits));
9589}
9590
5f3d5799
JK		 9591static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9592 struct vmcs12 *vmcs12)
9593{
9594 u32 idt_vectoring;
9595 unsigned int nr;
9596
851eb667 9597 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9598 nr = vcpu->arch.exception.nr;
9599 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9600
9601 if (kvm_exception_is_soft(nr)) {
9602 vmcs12->vm_exit_instruction_len =
9603 vcpu->arch.event_exit_inst_len;
9604 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9605 } else
9606 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9607
9608 if (vcpu->arch.exception.has_error_code) {
9609 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9610 vmcs12->idt_vectoring_error_code =
9611 vcpu->arch.exception.error_code;
9612 }
9613
9614 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9615 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9616 vmcs12->idt_vectoring_info_field =
9617 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9618 } else if (vcpu->arch.interrupt.pending) {
9619 nr = vcpu->arch.interrupt.nr;
9620 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9621
9622 if (vcpu->arch.interrupt.soft) {
9623 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9624 vmcs12->vm_entry_instruction_len =
9625 vcpu->arch.event_exit_inst_len;
9626 } else
9627 idt_vectoring |= INTR_TYPE_EXT_INTR;
9628
9629 vmcs12->idt_vectoring_info_field = idt_vectoring;
9630 }
9631}
9632
b6b8a145
JK		 9633static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9634{
9635 struct vcpu_vmx *vmx = to_vmx(vcpu);
9636
f4124500
JK		 9637 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9638 vmx->nested.preemption_timer_expired) {
9639 if (vmx->nested.nested_run_pending)
9640 return -EBUSY;
9641 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9642 return 0;
9643 }
9644
b6b8a145 9645 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9646 if (vmx->nested.nested_run_pending ||
9647 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9648 return -EBUSY;
9649 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9650 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9651 INTR_INFO_VALID_MASK, 0);
9652 /*
9653 * The NMI-triggered VM exit counts as injection:
9654 * clear this one and block further NMIs.
9655 */
9656 vcpu->arch.nmi_pending = 0;
9657 vmx_set_nmi_mask(vcpu, true);
9658 return 0;
9659 }
9660
9661 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9662 nested_exit_on_intr(vcpu)) {
9663 if (vmx->nested.nested_run_pending)
9664 return -EBUSY;
9665 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9666 return 0;
b6b8a145
JK		 9667 }
9668
705699a1 9669 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9670}
9671
f4124500
JK		 9672static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9673{
9674 ktime_t remaining =
9675 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9676 u64 value;
9677
9678 if (ktime_to_ns(remaining) <= 0)
9679 return 0;
9680
9681 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9682 do_div(value, 1000000);
9683 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9684}
9685
4704d0be
NHE		 9686/*
9687 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9688 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9689 * and this function updates it to reflect the changes to the guest state while
9690 * L2 was running (and perhaps made some exits which were handled directly by L0
9691 * without going back to L1), and to reflect the exit reason.
9692 * Note that we do not have to copy here all VMCS fields, just those that
9693 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9694 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9695 * which already writes to vmcs12 directly.
9696 */
533558bc
JK		 9697static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9698 u32 exit_reason, u32 exit_intr_info,
9699 unsigned long exit_qualification)
4704d0be
NHE		 9700{
9701 /* update guest state fields: */
9702 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9703 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9704
4704d0be
NHE		 9705 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9706 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9707 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9708
9709 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9710 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9711 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9712 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9713 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9714 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9715 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9716 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9717 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9718 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9719 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9720 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9721 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9722 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9723 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9724 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9725 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9726 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9727 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9728 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9729 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9730 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9731 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9732 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9733 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9734 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9735 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9736 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9737 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9738 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9739 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9740 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9741 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9742 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9743 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9744 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9745
4704d0be
NHE		 9746 vmcs12->guest_interruptibility_info =
9747 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9748 vmcs12->guest_pending_dbg_exceptions =
9749 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9750 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9751 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9752 else
9753 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9754
f4124500
JK		 9755 if (nested_cpu_has_preemption_timer(vmcs12)) {
9756 if (vmcs12->vm_exit_controls &
9757 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9758 vmcs12->vmx_preemption_timer_value =
9759 vmx_get_preemption_timer_value(vcpu);
9760 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9761 }
7854cbca 9762
3633cfc3
NHE		 9763 /*
9764 * In some cases (usually, nested EPT), L2 is allowed to change its
9765 * own CR3 without exiting. If it has changed it, we must keep it.
9766 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9767 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9768 *
9769 * Additionally, restore L2's PDPTR to vmcs12.
9770 */
9771 if (enable_ept) {
9772 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9773 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9774 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9775 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9776 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9777 }
9778
608406e2
WV		 9779 if (nested_cpu_has_vid(vmcs12))
9780 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9781
c18911a2
JK		 9782 vmcs12->vm_entry_controls =
9783 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9784 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9785
2996fca0
JK		 9786 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9787 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9788 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9789 }
9790
4704d0be
NHE		 9791 /* TODO: These cannot have changed unless we have MSR bitmaps and
9792 * the relevant bit asks not to trap the change */
b8c07d55 9793 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9794 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9795 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9796 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9797 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9798 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9799 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9800 if (vmx_mpx_supported())
9801 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9802 if (nested_cpu_has_xsaves(vmcs12))
9803 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9804
9805 /* update exit information fields: */
9806
533558bc
JK		 9807 vmcs12->vm_exit_reason = exit_reason;
9808 vmcs12->exit_qualification = exit_qualification;
4704d0be 9809
533558bc 9810 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9811 if ((vmcs12->vm_exit_intr_info &
9812 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9813 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9814 vmcs12->vm_exit_intr_error_code =
9815 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9816 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9817 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9818 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9819
5f3d5799
JK		 9820 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9821 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9822 * instead of reading the real value. */
4704d0be 9823 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9824
9825 /*
9826 * Transfer the event that L0 or L1 may wanted to inject into
9827 * L2 to IDT_VECTORING_INFO_FIELD.
9828 */
9829 vmcs12_save_pending_event(vcpu, vmcs12);
9830 }
9831
9832 /*
9833 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9834 * preserved above and would only end up incorrectly in L1.
9835 */
9836 vcpu->arch.nmi_injected = false;
9837 kvm_clear_exception_queue(vcpu);
9838 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9839}
9840
9841/*
9842 * A part of what we need to when the nested L2 guest exits and we want to
9843 * run its L1 parent, is to reset L1's guest state to the host state specified
9844 * in vmcs12.
9845 * This function is to be called not only on normal nested exit, but also on
9846 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9847 * Failures During or After Loading Guest State").
9848 * This function should be called when the active VMCS is L1's (vmcs01).
9849 */
733568f9
JK		 9850static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9851 struct vmcs12 *vmcs12)
4704d0be 9852{
21feb4eb
ACL		 9853 struct kvm_segment seg;
9854
4704d0be
NHE		 9855 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9856 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9857 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9858 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9859 else
9860 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9861 vmx_set_efer(vcpu, vcpu->arch.efer);
9862
9863 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9864 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9865 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9866 /*
9867 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9868 * actually changed, because it depends on the current state of
9869 * fpu_active (which may have changed).
9870 * Note that vmx_set_cr0 refers to efer set above.
9871 */
9e3e4dbf 9872 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9873 /*
9874 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9875 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9876 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9877 */
9878 update_exception_bitmap(vcpu);
9879 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9880 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9881
9882 /*
9883 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9884 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9885 */
9886 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9887 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9888
29bf08f1 9889 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9890
4704d0be
NHE		 9891 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9892 kvm_mmu_reset_context(vcpu);
9893
feaf0c7d
GN		 9894 if (!enable_ept)
9895 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9896
4704d0be
NHE		 9897 if (enable_vpid) {
9898 /*
9899 * Trivially support vpid by letting L2s share their parent
9900 * L1's vpid. TODO: move to a more elaborate solution, giving
9901 * each L2 its own vpid and exposing the vpid feature to L1.
9902 */
9903 vmx_flush_tlb(vcpu);
9904 }
9905
9906
9907 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9908 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9909 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9910 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9911 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9912
36be0b9d
PB		 9913 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9914 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9915 vmcs_write64(GUEST_BNDCFGS, 0);
9916
44811c02 9917 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9918 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9919 vcpu->arch.pat = vmcs12->host_ia32_pat;
9920 }
4704d0be
NHE		 9921 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9922 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9923 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9924
21feb4eb
ACL		 9925 /* Set L1 segment info according to Intel SDM
9926 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9927 seg = (struct kvm_segment) {
9928 .base = 0,
9929 .limit = 0xFFFFFFFF,
9930 .selector = vmcs12->host_cs_selector,
9931 .type = 11,
9932 .present = 1,
9933 .s = 1,
9934 .g = 1
9935 };
9936 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9937 seg.l = 1;
9938 else
9939 seg.db = 1;
9940 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9941 seg = (struct kvm_segment) {
9942 .base = 0,
9943 .limit = 0xFFFFFFFF,
9944 .type = 3,
9945 .present = 1,
9946 .s = 1,
9947 .db = 1,
9948 .g = 1
9949 };
9950 seg.selector = vmcs12->host_ds_selector;
9951 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9952 seg.selector = vmcs12->host_es_selector;
9953 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9954 seg.selector = vmcs12->host_ss_selector;
9955 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9956 seg.selector = vmcs12->host_fs_selector;
9957 seg.base = vmcs12->host_fs_base;
9958 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9959 seg.selector = vmcs12->host_gs_selector;
9960 seg.base = vmcs12->host_gs_base;
9961 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9962 seg = (struct kvm_segment) {
205befd9 9963 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9964 .limit = 0x67,
9965 .selector = vmcs12->host_tr_selector,
9966 .type = 11,
9967 .present = 1
9968 };
9969 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9970
503cd0c5
JK		 9971 kvm_set_dr(vcpu, 7, 0x400);
9972 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 9973
3af18d9c
WV		 9974 if (cpu_has_vmx_msr_bitmap())
9975 vmx_set_msr_bitmap(vcpu);
9976
ff651cb6
WV		 9977 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9978 vmcs12->vm_exit_msr_load_count))
9979 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9980}
9981
9982/*
9983 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9984 * and modify vmcs12 to make it see what it would expect to see there if
9985 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9986 */
533558bc
JK		 9987static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9988 u32 exit_intr_info,
9989 unsigned long exit_qualification)
4704d0be
NHE		 9990{
9991 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9992 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9993
5f3d5799
JK		 9994 /* trying to cancel vmlaunch/vmresume is a bug */
9995 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9996
4704d0be 9997 leave_guest_mode(vcpu);
533558bc
JK		 9998 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9999 exit_qualification);
4704d0be 10000
ff651cb6
WV		 10001 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10002 vmcs12->vm_exit_msr_store_count))
10003 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10004
f3380ca5
WL		 10005 vmx_load_vmcs01(vcpu);
10006
77b0f5d6
BD		 10007 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10008 && nested_exit_intr_ack_set(vcpu)) {
10009 int irq = kvm_cpu_get_interrupt(vcpu);
10010 WARN_ON(irq < 0);
10011 vmcs12->vm_exit_intr_info = irq |
10012 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10013 }
10014
542060ea
JK		 10015 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10016 vmcs12->exit_qualification,
10017 vmcs12->idt_vectoring_info_field,
10018 vmcs12->vm_exit_intr_info,
10019 vmcs12->vm_exit_intr_error_code,
10020 KVM_ISA_VMX);
4704d0be 10021
2961e876
GN		 10022 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10023 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10024 vmx_segment_cache_clear(vmx);
10025
4704d0be
NHE		 10026 /* if no vmcs02 cache requested, remove the one we used */
10027 if (VMCS02_POOL_SIZE == 0)
10028 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10029
10030 load_vmcs12_host_state(vcpu, vmcs12);
10031
27fc51b2 10032 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10033 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10034
10035 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10036 vmx->host_rsp = 0;
10037
10038 /* Unpin physical memory we referred to in vmcs02 */
10039 if (vmx->nested.apic_access_page) {
10040 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10041 vmx->nested.apic_access_page = NULL;
4704d0be 10042 }
a7c0b07d
WL		 10043 if (vmx->nested.virtual_apic_page) {
10044 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10045 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10046 }
705699a1
WV		 10047 if (vmx->nested.pi_desc_page) {
10048 kunmap(vmx->nested.pi_desc_page);
10049 nested_release_page(vmx->nested.pi_desc_page);
10050 vmx->nested.pi_desc_page = NULL;
10051 vmx->nested.pi_desc = NULL;
10052 }
4704d0be 10053
38b99173
TC		 10054 /*
10055 * We are now running in L2, mmu_notifier will force to reload the
10056 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10057 */
10058 kvm_vcpu_reload_apic_access_page(vcpu);
10059
4704d0be
NHE		 10060 /*
10061 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10062 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10063 * success or failure flag accordingly.
10064 */
10065 if (unlikely(vmx->fail)) {
10066 vmx->fail = 0;
10067 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10068 } else
10069 nested_vmx_succeed(vcpu);
012f83cb
AG		 10070 if (enable_shadow_vmcs)
10071 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10072
10073 /* in case we halted in L2 */
10074 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10075}
10076
42124925
JK		 10077/*
10078 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10079 */
10080static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10081{
10082 if (is_guest_mode(vcpu))
533558bc 10083 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10084 free_nested(to_vmx(vcpu));
10085}
10086
7c177938
NHE		 10087/*
10088 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10089 * 23.7 "VM-entry failures during or after loading guest state" (this also
10090 * lists the acceptable exit-reason and exit-qualification parameters).
10091 * It should only be called before L2 actually succeeded to run, and when
10092 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10093 */
10094static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10095 struct vmcs12 *vmcs12,
10096 u32 reason, unsigned long qualification)
10097{
10098 load_vmcs12_host_state(vcpu, vmcs12);
10099 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10100 vmcs12->exit_qualification = qualification;
10101 nested_vmx_succeed(vcpu);
012f83cb
AG		 10102 if (enable_shadow_vmcs)
10103 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10104}
10105
8a76d7f2
JR		 10106static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10107 struct x86_instruction_info *info,
10108 enum x86_intercept_stage stage)
10109{
10110 return X86EMUL_CONTINUE;
10111}
10112
48d89b92 10113static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10114{
b4a2d31d
RK		 10115 if (ple_gap)
10116 shrink_ple_window(vcpu);
ae97a3b8
RK		 10117}
10118
843e4330
KH		 10119static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10120 struct kvm_memory_slot *slot)
10121{
10122 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10123 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10124}
10125
10126static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10127 struct kvm_memory_slot *slot)
10128{
10129 kvm_mmu_slot_set_dirty(kvm, slot);
10130}
10131
10132static void vmx_flush_log_dirty(struct kvm *kvm)
10133{
10134 kvm_flush_pml_buffers(kvm);
10135}
10136
10137static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10138 struct kvm_memory_slot *memslot,
10139 gfn_t offset, unsigned long mask)
10140{
10141 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10142}
10143
cbdd1bea 10144static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10145 .cpu_has_kvm_support = cpu_has_kvm_support,
10146 .disabled_by_bios = vmx_disabled_by_bios,
10147 .hardware_setup = hardware_setup,
10148 .hardware_unsetup = hardware_unsetup,
002c7f7c 10149 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10150 .hardware_enable = hardware_enable,
10151 .hardware_disable = hardware_disable,
04547156 10152 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 10153
10154 .vcpu_create = vmx_create_vcpu,
10155 .vcpu_free = vmx_free_vcpu,
04d2cc77 10156 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10157
04d2cc77 10158 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10159 .vcpu_load = vmx_vcpu_load,
10160 .vcpu_put = vmx_vcpu_put,
10161
c8639010 10162 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10163 .get_msr = vmx_get_msr,
10164 .set_msr = vmx_set_msr,
10165 .get_segment_base = vmx_get_segment_base,
10166 .get_segment = vmx_get_segment,
10167 .set_segment = vmx_set_segment,
2e4d2653 10168 .get_cpl = vmx_get_cpl,
6aa8b732 10169 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10170 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10171 .decache_cr3 = vmx_decache_cr3,
25c4c276 10172 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10173 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10174 .set_cr3 = vmx_set_cr3,
10175 .set_cr4 = vmx_set_cr4,
6aa8b732 10176 .set_efer = vmx_set_efer,
6aa8b732
AK		 10177 .get_idt = vmx_get_idt,
10178 .set_idt = vmx_set_idt,
10179 .get_gdt = vmx_get_gdt,
10180 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10181 .get_dr6 = vmx_get_dr6,
10182 .set_dr6 = vmx_set_dr6,
020df079 10183 .set_dr7 = vmx_set_dr7,
81908bf4 10184 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10185 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10186 .get_rflags = vmx_get_rflags,
10187 .set_rflags = vmx_set_rflags,
02daab21 10188 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10189
10190 .tlb_flush = vmx_flush_tlb,
6aa8b732 10191
6aa8b732 10192 .run = vmx_vcpu_run,
6062d012 10193 .handle_exit = vmx_handle_exit,
6aa8b732 10194 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10195 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10196 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10197 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10198 .set_irq = vmx_inject_irq,
95ba8273 10199 .set_nmi = vmx_inject_nmi,
298101da 10200 .queue_exception = vmx_queue_exception,
b463a6f7 10201 .cancel_injection = vmx_cancel_injection,
78646121 10202 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10203 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10204 .get_nmi_mask = vmx_get_nmi_mask,
10205 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10206 .enable_nmi_window = enable_nmi_window,
10207 .enable_irq_window = enable_irq_window,
10208 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10209 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10210 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 10211 .vm_has_apicv = vmx_vm_has_apicv,
10212 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10213 .hwapic_irr_update = vmx_hwapic_irr_update,
10214 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10215 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10216 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10217
cbc94022 10218 .set_tss_addr = vmx_set_tss_addr,
67253af5 10219 .get_tdp_level = get_ept_level,
4b12f0de 10220 .get_mt_mask = vmx_get_mt_mask,
229456fc 10221
586f9607 10222 .get_exit_info = vmx_get_exit_info,
586f9607 10223
17cc3935 10224 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10225
10226 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10227
10228 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10229 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10230
10231 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10232
10233 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10234
4051b188 10235 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10236 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10237 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10238 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10239 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10240 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10241
10242 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10243
10244 .check_intercept = vmx_check_intercept,
a547c6db 10245 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10246 .mpx_supported = vmx_mpx_supported,
55412b2e 10247 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10248
10249 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10250
10251 .sched_in = vmx_sched_in,
843e4330
KH		 10252
10253 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10254 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10255 .flush_log_dirty = vmx_flush_log_dirty,
10256 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 10257};
10258
10259static int __init vmx_init(void)
10260{
34a1cd60
TC		 10261 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10262 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10263 if (r)
34a1cd60 10264 return r;
25c5f225 10265
8f536b76
ZY		 10266#ifdef CONFIG_KEXEC
10267 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10268 crash_vmclear_local_loaded_vmcss);
10269#endif
10270
fdef3ad1 10271 return 0;
6aa8b732
AK		 10272}
10273
10274static void __exit vmx_exit(void)
10275{
8f536b76 10276#ifdef CONFIG_KEXEC
3b63a43f 10277 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10278 synchronize_rcu();
10279#endif
10280
cb498ea2 10281 kvm_exit();
6aa8b732
AK		 10282}
10283
10284module_init(vmx_init)
10285module_exit(vmx_exit)
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