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pc: cpu: Consolidate apic-id validity checks in pc_cpu_pre_plug()
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
99b88a17
IM		 164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
c6dc6f63
AP		 176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
f370be3c 191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 192 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 193 "tm2", "ssse3", "cid", NULL,
e117f772 194 "fma", "cx16", "xtpr", "pdcm",
434acb81 195 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 197 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 198 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 199};
3b671a40
EH		 200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
c6dc6f63 205static const char *ext2_feature_name[] = {
3b671a40
EH		 206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 213 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 218 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 223 NULL, NULL, NULL, NULL,
224};
225
89e49c8b
EH		 226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
c6dc6f63 237static const char *kvm_feature_name[] = {
c3d39807 238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
8248c36a 244 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 245 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 246};
247
c35bd19a
EY		 248static const char *hyperv_priv_feature_name[] = {
249 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
250 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
251 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
252 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
253 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
254 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257 NULL, NULL, NULL, NULL,
258 NULL, NULL, NULL, NULL,
259 NULL, NULL, NULL, NULL,
260};
261
262static const char *hyperv_ident_feature_name[] = {
263 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
264 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
265 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
266 NULL /* hv_create_port */, NULL /* hv_connect_port */,
267 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
268 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
269 NULL, NULL,
270 NULL, NULL, NULL, NULL,
271 NULL, NULL, NULL, NULL,
272 NULL, NULL, NULL, NULL,
273 NULL, NULL, NULL, NULL,
274};
275
276static const char *hyperv_misc_feature_name[] = {
277 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
278 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
279 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
280 NULL, NULL,
281 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
282 NULL, NULL, NULL, NULL,
283 NULL, NULL, NULL, NULL,
284 NULL, NULL, NULL, NULL,
285 NULL, NULL, NULL, NULL,
286 NULL, NULL, NULL, NULL,
287};
288
296acb64
JR		 289static const char *svm_feature_name[] = {
290 "npt", "lbrv", "svm_lock", "nrip_save",
291 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
292 NULL, NULL, "pause_filter", NULL,
293 "pfthreshold", NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 NULL, NULL, NULL, NULL,
296 NULL, NULL, NULL, NULL,
297 NULL, NULL, NULL, NULL,
298};
299
a9321a4d 300static const char *cpuid_7_0_ebx_feature_name[] = {
7b458bfd 301 "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
5bd8ff07 302 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
f7fda280
XG		 303 "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt",
304 "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
a9321a4d
PA		 305};
306
f74eefe0
HH		 307static const char *cpuid_7_0_ecx_feature_name[] = {
308 NULL, NULL, NULL, "pku",
309 "ospke", NULL, NULL, NULL,
310 NULL, NULL, NULL, NULL,
311 NULL, NULL, NULL, NULL,
312 NULL, NULL, NULL, NULL,
313 NULL, NULL, NULL, NULL,
314 NULL, NULL, NULL, NULL,
315 NULL, NULL, NULL, NULL,
316};
317
303752a9
MT		 318static const char *cpuid_apm_edx_feature_name[] = {
319 NULL, NULL, NULL, NULL,
320 NULL, NULL, NULL, NULL,
321 "invtsc", NULL, NULL, NULL,
322 NULL, NULL, NULL, NULL,
323 NULL, NULL, NULL, NULL,
324 NULL, NULL, NULL, NULL,
325 NULL, NULL, NULL, NULL,
326 NULL, NULL, NULL, NULL,
327};
328
0bb0b2d2
PB		 329static const char *cpuid_xsave_feature_name[] = {
330 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
331 NULL, NULL, NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 NULL, NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338};
339
28b8e4d0
JK		 340static const char *cpuid_6_feature_name[] = {
341 NULL, NULL, "arat", NULL,
342 NULL, NULL, NULL, NULL,
343 NULL, NULL, NULL, NULL,
344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349};
350
621626ce
EH		 351#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
352#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
353 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
354#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
355 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
356 CPUID_PSE36 | CPUID_FXSR)
357#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
358#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
359 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
360 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
361 CPUID_PAE | CPUID_SEP | CPUID_APIC)
362
363#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
364 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
365 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
366 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 367 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 368 /* partly implemented:
369 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
370 /* missing:
371 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
372#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
373 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
374 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 375 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 376 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
377 /* missing:
378 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
379 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
380 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 381 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
382 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 383
384#ifdef TARGET_X86_64
385#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
386#else
387#define TCG_EXT2_X86_64_FEATURES 0
388#endif
389
390#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
391 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
392 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
393 TCG_EXT2_X86_64_FEATURES)
394#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
395 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
396#define TCG_EXT4_FEATURES 0
397#define TCG_SVM_FEATURES 0
398#define TCG_KVM_FEATURES 0
399#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 400 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
401 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 402 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
403 CPUID_7_0_EBX_ERMS)
621626ce 404 /* missing:
07929f2a 405 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 406 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 407 CPUID_7_0_EBX_RDSEED */
0f70ed47 408#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 409#define TCG_APM_FEATURES 0
28b8e4d0 410#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 411#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
412 /* missing:
413 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 414
5ef57876
EH		 415typedef struct FeatureWordInfo {
416 const char **feat_names;
04d104b6
EH		 417 uint32_t cpuid_eax; /* Input EAX for CPUID */
418 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
419 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
420 int cpuid_reg; /* output register (R_* constant) */
37ce3522 421 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 422 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 423} FeatureWordInfo;
424
425static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 426 [FEAT_1_EDX] = {
427 .feat_names = feature_name,
428 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 429 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 430 },
431 [FEAT_1_ECX] = {
432 .feat_names = ext_feature_name,
433 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 434 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 435 },
436 [FEAT_8000_0001_EDX] = {
437 .feat_names = ext2_feature_name,
438 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 439 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 440 },
441 [FEAT_8000_0001_ECX] = {
442 .feat_names = ext3_feature_name,
443 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 444 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 445 },
89e49c8b
EH		 446 [FEAT_C000_0001_EDX] = {
447 .feat_names = ext4_feature_name,
448 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 449 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 450 },
bffd67b0
EH		 451 [FEAT_KVM] = {
452 .feat_names = kvm_feature_name,
453 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 454 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 455 },
c35bd19a
EY		 456 [FEAT_HYPERV_EAX] = {
457 .feat_names = hyperv_priv_feature_name,
458 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
459 },
460 [FEAT_HYPERV_EBX] = {
461 .feat_names = hyperv_ident_feature_name,
462 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
463 },
464 [FEAT_HYPERV_EDX] = {
465 .feat_names = hyperv_misc_feature_name,
466 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
467 },
bffd67b0
EH		 468 [FEAT_SVM] = {
469 .feat_names = svm_feature_name,
470 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 471 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 472 },
473 [FEAT_7_0_EBX] = {
474 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 475 .cpuid_eax = 7,
476 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
477 .cpuid_reg = R_EBX,
37ce3522 478 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 479 },
f74eefe0
HH		 480 [FEAT_7_0_ECX] = {
481 .feat_names = cpuid_7_0_ecx_feature_name,
482 .cpuid_eax = 7,
483 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
484 .cpuid_reg = R_ECX,
485 .tcg_features = TCG_7_0_ECX_FEATURES,
486 },
303752a9
MT		 487 [FEAT_8000_0007_EDX] = {
488 .feat_names = cpuid_apm_edx_feature_name,
489 .cpuid_eax = 0x80000007,
490 .cpuid_reg = R_EDX,
491 .tcg_features = TCG_APM_FEATURES,
492 .unmigratable_flags = CPUID_APM_INVTSC,
493 },
0bb0b2d2
PB		 494 [FEAT_XSAVE] = {
495 .feat_names = cpuid_xsave_feature_name,
496 .cpuid_eax = 0xd,
497 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
498 .cpuid_reg = R_EAX,
c9cfe8f9 499 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 500 },
28b8e4d0
JK		 501 [FEAT_6_EAX] = {
502 .feat_names = cpuid_6_feature_name,
503 .cpuid_eax = 6, .cpuid_reg = R_EAX,
504 .tcg_features = TCG_6_EAX_FEATURES,
505 },
5ef57876
EH		 506};
507
8e8aba50
EH		 508typedef struct X86RegisterInfo32 {
509 /* Name of register */
510 const char *name;
511 /* QAPI enum value register */
512 X86CPURegister32 qapi_enum;
513} X86RegisterInfo32;
514
515#define REGISTER(reg) \
5d371f41 516 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 517static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 518 REGISTER(EAX),
519 REGISTER(ECX),
520 REGISTER(EDX),
521 REGISTER(EBX),
522 REGISTER(ESP),
523 REGISTER(EBP),
524 REGISTER(ESI),
525 REGISTER(EDI),
526};
527#undef REGISTER
528
f4f1110e 529const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB		 530 [XSTATE_YMM_BIT] =
531 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 532 .offset = offsetof(X86XSaveArea, avx_state),
533 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 534 [XSTATE_BNDREGS_BIT] =
535 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 536 .offset = offsetof(X86XSaveArea, bndreg_state),
537 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 538 [XSTATE_BNDCSR_BIT] =
539 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 540 .offset = offsetof(X86XSaveArea, bndcsr_state),
541 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 542 [XSTATE_OPMASK_BIT] =
543 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 544 .offset = offsetof(X86XSaveArea, opmask_state),
545 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 546 [XSTATE_ZMM_Hi256_BIT] =
547 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 548 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
549 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 550 [XSTATE_Hi16_ZMM_BIT] =
551 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 552 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
553 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 554 [XSTATE_PKRU_BIT] =
555 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 556 .offset = offsetof(X86XSaveArea, pkru_state),
557 .size = sizeof(XSavePKRU) },
2560f19f 558};
8e8aba50 559
8b4beddc
EH		 560const char *get_register_name_32(unsigned int reg)
561{
31ccdde2 562 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 563 return NULL;
564 }
8e8aba50 565 return x86_reg_info_32[reg].name;
8b4beddc
EH		 566}
567
84f1b92f
EH		 568/*
569 * Returns the set of feature flags that are supported and migratable by
570 * QEMU, for a given FeatureWord.
571 */
572static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
573{
574 FeatureWordInfo *wi = &feature_word_info[w];
575 uint32_t r = 0;
576 int i;
577
578 for (i = 0; i < 32; i++) {
579 uint32_t f = 1U << i;
580 /* If the feature name is unknown, it is not supported by QEMU yet */
581 if (!wi->feat_names[i]) {
582 continue;
583 }
584 /* Skip features known to QEMU, but explicitly marked as unmigratable */
585 if (wi->unmigratable_flags & f) {
586 continue;
587 }
588 r |= f;
589 }
590 return r;
591}
592
bb44e0d1
JK		 593void host_cpuid(uint32_t function, uint32_t count,
594 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 595{
a1fd24af
AL		 596 uint32_t vec[4];
597
598#ifdef __x86_64__
599 asm volatile("cpuid"
600 : "=a"(vec[0]), "=b"(vec[1]),
601 "=c"(vec[2]), "=d"(vec[3])
602 : "0"(function), "c"(count) : "cc");
c1f41226 603#elif defined(__i386__)
a1fd24af
AL		 604 asm volatile("pusha \n\t"
605 "cpuid \n\t"
606 "mov %%eax, 0(%2) \n\t"
607 "mov %%ebx, 4(%2) \n\t"
608 "mov %%ecx, 8(%2) \n\t"
609 "mov %%edx, 12(%2) \n\t"
610 "popa"
611 : : "a"(function), "c"(count), "S"(vec)
612 : "memory", "cc");
c1f41226
EH		 613#else
614 abort();
a1fd24af
AL		 615#endif
616
bdde476a 617 if (eax)
a1fd24af 618 *eax = vec[0];
bdde476a 619 if (ebx)
a1fd24af 620 *ebx = vec[1];
bdde476a 621 if (ecx)
a1fd24af 622 *ecx = vec[2];
bdde476a 623 if (edx)
a1fd24af 624 *edx = vec[3];
bdde476a 625}
c6dc6f63
AP		 626
627#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
628
629/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
630 * a substring. ex if !NULL points to the first char after a substring,
631 * otherwise the string is assumed to sized by a terminating nul.
632 * Return lexical ordering of *s1:*s2.
633 */
8f9d989c
CF		 634static int sstrcmp(const char *s1, const char *e1,
635 const char *s2, const char *e2)
c6dc6f63
AP		 636{
637 for (;;) {
638 if (!*s1 || !*s2 || *s1 != *s2)
639 return (*s1 - *s2);
640 ++s1, ++s2;
641 if (s1 == e1 && s2 == e2)
642 return (0);
643 else if (s1 == e1)
644 return (*s2);
645 else if (s2 == e2)
646 return (*s1);
647 }
648}
649
650/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
651 * '|' delimited (possibly empty) strings in which case search for a match
652 * within the alternatives proceeds left to right. Return 0 for success,
653 * non-zero otherwise.
654 */
655static int altcmp(const char *s, const char *e, const char *altstr)
656{
657 const char *p, *q;
658
659 for (q = p = altstr; ; ) {
660 while (*p && *p != '|')
661 ++p;
662 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
663 return (0);
664 if (!*p)
665 return (1);
666 else
667 q = ++p;
668 }
669}
670
671/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 672 * *pval and return true, otherwise return false
c6dc6f63 673 */
e41e0fc6
JK		 674static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
675 const char **featureset)
c6dc6f63
AP		 676{
677 uint32_t mask;
678 const char **ppc;
e41e0fc6 679 bool found = false;
c6dc6f63 680
e41e0fc6 681 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 682 if (*ppc && !altcmp(s, e, *ppc)) {
683 *pval |= mask;
e41e0fc6 684 found = true;
c6dc6f63 685 }
e41e0fc6
JK		 686 }
687 return found;
c6dc6f63
AP		 688}
689
5ef57876 690static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 691 FeatureWordArray words,
692 Error **errp)
c6dc6f63 693{
5ef57876
EH		 694 FeatureWord w;
695 for (w = 0; w < FEATURE_WORDS; w++) {
696 FeatureWordInfo *wi = &feature_word_info[w];
697 if (wi->feat_names &&
698 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
699 break;
700 }
701 }
702 if (w == FEATURE_WORDS) {
c00c94ab 703 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 704 }
c6dc6f63
AP		 705}
706
d940ee9b
EH		 707/* CPU class name definitions: */
708
709#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
710#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
711
712/* Return type name for a given CPU model name
713 * Caller is responsible for freeing the returned string.
714 */
715static char *x86_cpu_type_name(const char *model_name)
716{
717 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
718}
719
500050d1
AF		 720static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
721{
d940ee9b
EH		 722 ObjectClass *oc;
723 char *typename;
724
500050d1
AF		 725 if (cpu_model == NULL) {
726 return NULL;
727 }
728
d940ee9b
EH		 729 typename = x86_cpu_type_name(cpu_model);
730 oc = object_class_by_name(typename);
731 g_free(typename);
732 return oc;
500050d1
AF		 733}
734
104494ea
IM		 735static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
736{
737 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
738 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
739 return g_strndup(class_name,
740 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
741}
742
d940ee9b 743struct X86CPUDefinition {
c6dc6f63
AP		 744 const char *name;
745 uint32_t level;
90e4b0c3
EH		 746 uint32_t xlevel;
747 uint32_t xlevel2;
99b88a17
IM		 748 /* vendor is zero-terminated, 12 character ASCII string */
749 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 750 int family;
751 int model;
752 int stepping;
0514ef2f 753 FeatureWordArray features;
c6dc6f63 754 char model_id[48];
d940ee9b 755};
c6dc6f63 756
9576de75 757static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 758 {
759 .name = "qemu64",
3046bb5d 760 .level = 0xd,
99b88a17 761 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 762 .family = 6,
f8e6a11a 763 .model = 6,
c6dc6f63 764 .stepping = 3,
0514ef2f 765 .features[FEAT_1_EDX] =
27861ecc 766 PPRO_FEATURES |
c6dc6f63 767 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 768 CPUID_PSE36,
0514ef2f 769 .features[FEAT_1_ECX] =
6aa91e4a 770 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 771 .features[FEAT_8000_0001_EDX] =
c6dc6f63 772 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 773 .features[FEAT_8000_0001_ECX] =
71195672 774 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 775 .xlevel = 0x8000000A,
9cf2cc3d 776 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 777 },
778 {
779 .name = "phenom",
780 .level = 5,
99b88a17 781 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 782 .family = 16,
783 .model = 2,
784 .stepping = 3,
b9fc20bc 785 /* Missing: CPUID_HT */
0514ef2f 786 .features[FEAT_1_EDX] =
27861ecc 787 PPRO_FEATURES |
c6dc6f63 788 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 789 CPUID_PSE36 | CPUID_VME,
0514ef2f 790 .features[FEAT_1_ECX] =
27861ecc 791 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 792 CPUID_EXT_POPCNT,
0514ef2f 793 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 794 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
795 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 796 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 797 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
798 CPUID_EXT3_CR8LEG,
799 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
800 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 801 .features[FEAT_8000_0001_ECX] =
27861ecc 802 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 803 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 804 /* Missing: CPUID_SVM_LBRV */
0514ef2f 805 .features[FEAT_SVM] =
b9fc20bc 806 CPUID_SVM_NPT,
c6dc6f63
AP		 807 .xlevel = 0x8000001A,
808 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
809 },
810 {
811 .name = "core2duo",
812 .level = 10,
99b88a17 813 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 814 .family = 6,
815 .model = 15,
816 .stepping = 11,
b9fc20bc 817 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 818 .features[FEAT_1_EDX] =
27861ecc 819 PPRO_FEATURES |
c6dc6f63 820 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 821 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
822 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 823 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 824 .features[FEAT_1_ECX] =
27861ecc 825 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 826 CPUID_EXT_CX16,
0514ef2f 827 .features[FEAT_8000_0001_EDX] =
27861ecc 828 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 829 .features[FEAT_8000_0001_ECX] =
27861ecc 830 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 831 .xlevel = 0x80000008,
832 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
833 },
834 {
835 .name = "kvm64",
3046bb5d 836 .level = 0xd,
99b88a17 837 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 838 .family = 15,
839 .model = 6,
840 .stepping = 1,
b3a4f0b1 841 /* Missing: CPUID_HT */
0514ef2f 842 .features[FEAT_1_EDX] =
b3a4f0b1 843 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 844 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
845 CPUID_PSE36,
846 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 847 .features[FEAT_1_ECX] =
27861ecc 848 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 849 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 850 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 851 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
852 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
853 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
854 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
855 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 856 .features[FEAT_8000_0001_ECX] =
27861ecc 857 0,
c6dc6f63
AP		 858 .xlevel = 0x80000008,
859 .model_id = "Common KVM processor"
860 },
c6dc6f63
AP		 861 {
862 .name = "qemu32",
863 .level = 4,
99b88a17 864 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 865 .family = 6,
f8e6a11a 866 .model = 6,
c6dc6f63 867 .stepping = 3,
0514ef2f 868 .features[FEAT_1_EDX] =
27861ecc 869 PPRO_FEATURES,
0514ef2f 870 .features[FEAT_1_ECX] =
6aa91e4a 871 CPUID_EXT_SSE3,
58012d66 872 .xlevel = 0x80000004,
9cf2cc3d 873 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 874 },
eafaf1e5
AP		 875 {
876 .name = "kvm32",
877 .level = 5,
99b88a17 878 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 879 .family = 15,
880 .model = 6,
881 .stepping = 1,
0514ef2f 882 .features[FEAT_1_EDX] =
b3a4f0b1 883 PPRO_FEATURES | CPUID_VME |
eafaf1e5 884 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 885 .features[FEAT_1_ECX] =
27861ecc 886 CPUID_EXT_SSE3,
0514ef2f 887 .features[FEAT_8000_0001_ECX] =
27861ecc 888 0,
eafaf1e5
AP		 889 .xlevel = 0x80000008,
890 .model_id = "Common 32-bit KVM processor"
891 },
c6dc6f63
AP		 892 {
893 .name = "coreduo",
894 .level = 10,
99b88a17 895 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 896 .family = 6,
897 .model = 14,
898 .stepping = 8,
b9fc20bc 899 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 900 .features[FEAT_1_EDX] =
27861ecc 901 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 902 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
903 CPUID_SS,
904 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 905 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 906 .features[FEAT_1_ECX] =
e93abc14 907 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 908 .features[FEAT_8000_0001_EDX] =
27861ecc 909 CPUID_EXT2_NX,
c6dc6f63
AP		 910 .xlevel = 0x80000008,
911 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
912 },
913 {
914 .name = "486",
58012d66 915 .level = 1,
99b88a17 916 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 917 .family = 4,
b2a856d9 918 .model = 8,
c6dc6f63 919 .stepping = 0,
0514ef2f 920 .features[FEAT_1_EDX] =
27861ecc 921 I486_FEATURES,
c6dc6f63
AP		 922 .xlevel = 0,
923 },
924 {
925 .name = "pentium",
926 .level = 1,
99b88a17 927 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 928 .family = 5,
929 .model = 4,
930 .stepping = 3,
0514ef2f 931 .features[FEAT_1_EDX] =
27861ecc 932 PENTIUM_FEATURES,
c6dc6f63
AP		 933 .xlevel = 0,
934 },
935 {
936 .name = "pentium2",
937 .level = 2,
99b88a17 938 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 939 .family = 6,
940 .model = 5,
941 .stepping = 2,
0514ef2f 942 .features[FEAT_1_EDX] =
27861ecc 943 PENTIUM2_FEATURES,
c6dc6f63
AP		 944 .xlevel = 0,
945 },
946 {
947 .name = "pentium3",
3046bb5d 948 .level = 3,
99b88a17 949 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 950 .family = 6,
951 .model = 7,
952 .stepping = 3,
0514ef2f 953 .features[FEAT_1_EDX] =
27861ecc 954 PENTIUM3_FEATURES,
c6dc6f63
AP		 955 .xlevel = 0,
956 },
957 {
958 .name = "athlon",
959 .level = 2,
99b88a17 960 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 961 .family = 6,
962 .model = 2,
963 .stepping = 3,
0514ef2f 964 .features[FEAT_1_EDX] =
27861ecc 965 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 966 CPUID_MCA,
0514ef2f 967 .features[FEAT_8000_0001_EDX] =
60032ac0 968 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 969 .xlevel = 0x80000008,
9cf2cc3d 970 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 971 },
972 {
973 .name = "n270",
3046bb5d 974 .level = 10,
99b88a17 975 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 976 .family = 6,
977 .model = 28,
978 .stepping = 2,
b9fc20bc 979 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 980 .features[FEAT_1_EDX] =
27861ecc 981 PPRO_FEATURES |
b9fc20bc
EH		 982 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
983 CPUID_ACPI | CPUID_SS,
c6dc6f63 984 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 985 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
986 * CPUID_EXT_XTPR */
0514ef2f 987 .features[FEAT_1_ECX] =
27861ecc 988 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 989 CPUID_EXT_MOVBE,
0514ef2f 990 .features[FEAT_8000_0001_EDX] =
60032ac0 991 CPUID_EXT2_NX,
0514ef2f 992 .features[FEAT_8000_0001_ECX] =
27861ecc 993 CPUID_EXT3_LAHF_LM,
3046bb5d 994 .xlevel = 0x80000008,
c6dc6f63
AP		 995 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
996 },
3eca4642
EH		 997 {
998 .name = "Conroe",
3046bb5d 999 .level = 10,
99b88a17 1000 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1001 .family = 6,
ffce9ebb 1002 .model = 15,
3eca4642 1003 .stepping = 3,
0514ef2f 1004 .features[FEAT_1_EDX] =
b3a4f0b1 1005 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1006 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1007 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1008 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1009 CPUID_DE | CPUID_FP87,
0514ef2f 1010 .features[FEAT_1_ECX] =
27861ecc 1011 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1012 .features[FEAT_8000_0001_EDX] =
27861ecc 1013 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1014 .features[FEAT_8000_0001_ECX] =
27861ecc 1015 CPUID_EXT3_LAHF_LM,
3046bb5d 1016 .xlevel = 0x80000008,
3eca4642
EH		 1017 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1018 },
1019 {
1020 .name = "Penryn",
3046bb5d 1021 .level = 10,
99b88a17 1022 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1023 .family = 6,
ffce9ebb 1024 .model = 23,
3eca4642 1025 .stepping = 3,
0514ef2f 1026 .features[FEAT_1_EDX] =
b3a4f0b1 1027 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1028 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1029 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1030 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1031 CPUID_DE | CPUID_FP87,
0514ef2f 1032 .features[FEAT_1_ECX] =
27861ecc 1033 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1034 CPUID_EXT_SSE3,
0514ef2f 1035 .features[FEAT_8000_0001_EDX] =
27861ecc 1036 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1037 .features[FEAT_8000_0001_ECX] =
27861ecc 1038 CPUID_EXT3_LAHF_LM,
3046bb5d 1039 .xlevel = 0x80000008,
3eca4642
EH		 1040 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1041 },
1042 {
1043 .name = "Nehalem",
3046bb5d 1044 .level = 11,
99b88a17 1045 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1046 .family = 6,
ffce9ebb 1047 .model = 26,
3eca4642 1048 .stepping = 3,
0514ef2f 1049 .features[FEAT_1_EDX] =
b3a4f0b1 1050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
0514ef2f 1055 .features[FEAT_1_ECX] =
27861ecc 1056 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1057 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1058 .features[FEAT_8000_0001_EDX] =
27861ecc 1059 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1060 .features[FEAT_8000_0001_ECX] =
27861ecc 1061 CPUID_EXT3_LAHF_LM,
3046bb5d 1062 .xlevel = 0x80000008,
3eca4642
EH		 1063 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1064 },
1065 {
1066 .name = "Westmere",
1067 .level = 11,
99b88a17 1068 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1069 .family = 6,
1070 .model = 44,
1071 .stepping = 1,
0514ef2f 1072 .features[FEAT_1_EDX] =
b3a4f0b1 1073 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1074 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1075 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1076 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1077 CPUID_DE | CPUID_FP87,
0514ef2f 1078 .features[FEAT_1_ECX] =
27861ecc 1079 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1080 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1081 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1082 .features[FEAT_8000_0001_EDX] =
27861ecc 1083 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1084 .features[FEAT_8000_0001_ECX] =
27861ecc 1085 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1086 .features[FEAT_6_EAX] =
1087 CPUID_6_EAX_ARAT,
3046bb5d 1088 .xlevel = 0x80000008,
3eca4642
EH		 1089 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1090 },
1091 {
1092 .name = "SandyBridge",
1093 .level = 0xd,
99b88a17 1094 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1095 .family = 6,
1096 .model = 42,
1097 .stepping = 1,
0514ef2f 1098 .features[FEAT_1_EDX] =
b3a4f0b1 1099 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1100 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1101 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1102 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1103 CPUID_DE | CPUID_FP87,
0514ef2f 1104 .features[FEAT_1_ECX] =
27861ecc 1105 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1106 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1107 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1108 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1109 CPUID_EXT_SSE3,
0514ef2f 1110 .features[FEAT_8000_0001_EDX] =
27861ecc 1111 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1112 CPUID_EXT2_SYSCALL,
0514ef2f 1113 .features[FEAT_8000_0001_ECX] =
27861ecc 1114 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1115 .features[FEAT_XSAVE] =
1116 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1117 .features[FEAT_6_EAX] =
1118 CPUID_6_EAX_ARAT,
3046bb5d 1119 .xlevel = 0x80000008,
3eca4642
EH		 1120 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1121 },
2f9ac42a
PB		 1122 {
1123 .name = "IvyBridge",
1124 .level = 0xd,
1125 .vendor = CPUID_VENDOR_INTEL,
1126 .family = 6,
1127 .model = 58,
1128 .stepping = 9,
1129 .features[FEAT_1_EDX] =
1130 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1131 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1132 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1133 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1134 CPUID_DE | CPUID_FP87,
1135 .features[FEAT_1_ECX] =
1136 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1137 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1138 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1139 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1140 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1141 .features[FEAT_7_0_EBX] =
1142 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1143 CPUID_7_0_EBX_ERMS,
1144 .features[FEAT_8000_0001_EDX] =
1145 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1146 CPUID_EXT2_SYSCALL,
1147 .features[FEAT_8000_0001_ECX] =
1148 CPUID_EXT3_LAHF_LM,
1149 .features[FEAT_XSAVE] =
1150 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1151 .features[FEAT_6_EAX] =
1152 CPUID_6_EAX_ARAT,
3046bb5d 1153 .xlevel = 0x80000008,
2f9ac42a
PB		 1154 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1155 },
37507094 1156 {
a356850b
EH		 1157 .name = "Haswell-noTSX",
1158 .level = 0xd,
1159 .vendor = CPUID_VENDOR_INTEL,
1160 .family = 6,
1161 .model = 60,
1162 .stepping = 1,
1163 .features[FEAT_1_EDX] =
1164 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1165 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1166 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1167 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1168 CPUID_DE | CPUID_FP87,
1169 .features[FEAT_1_ECX] =
1170 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1171 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1172 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1173 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1174 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1175 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1176 .features[FEAT_8000_0001_EDX] =
1177 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1178 CPUID_EXT2_SYSCALL,
1179 .features[FEAT_8000_0001_ECX] =
becb6667 1180 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1181 .features[FEAT_7_0_EBX] =
1182 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1183 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1184 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1185 .features[FEAT_XSAVE] =
1186 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1187 .features[FEAT_6_EAX] =
1188 CPUID_6_EAX_ARAT,
3046bb5d 1189 .xlevel = 0x80000008,
a356850b
EH		 1190 .model_id = "Intel Core Processor (Haswell, no TSX)",
1191 }, {
37507094
EH		 1192 .name = "Haswell",
1193 .level = 0xd,
99b88a17 1194 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1195 .family = 6,
1196 .model = 60,
1197 .stepping = 1,
0514ef2f 1198 .features[FEAT_1_EDX] =
b3a4f0b1 1199 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1200 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1201 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1202 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1203 CPUID_DE | CPUID_FP87,
0514ef2f 1204 .features[FEAT_1_ECX] =
27861ecc 1205 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1206 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1207 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1208 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1209 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1210 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1211 .features[FEAT_8000_0001_EDX] =
27861ecc 1212 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1213 CPUID_EXT2_SYSCALL,
0514ef2f 1214 .features[FEAT_8000_0001_ECX] =
becb6667 1215 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1216 .features[FEAT_7_0_EBX] =
27861ecc 1217 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1218 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1219 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1220 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1221 .features[FEAT_XSAVE] =
1222 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1223 .features[FEAT_6_EAX] =
1224 CPUID_6_EAX_ARAT,
3046bb5d 1225 .xlevel = 0x80000008,
37507094
EH		 1226 .model_id = "Intel Core Processor (Haswell)",
1227 },
a356850b
EH		 1228 {
1229 .name = "Broadwell-noTSX",
1230 .level = 0xd,
1231 .vendor = CPUID_VENDOR_INTEL,
1232 .family = 6,
1233 .model = 61,
1234 .stepping = 2,
1235 .features[FEAT_1_EDX] =
1236 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1237 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1238 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1239 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1240 CPUID_DE | CPUID_FP87,
1241 .features[FEAT_1_ECX] =
1242 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1243 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1244 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1245 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1246 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1247 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1248 .features[FEAT_8000_0001_EDX] =
1249 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1250 CPUID_EXT2_SYSCALL,
1251 .features[FEAT_8000_0001_ECX] =
becb6667 1252 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1253 .features[FEAT_7_0_EBX] =
1254 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1255 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1256 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1257 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1258 CPUID_7_0_EBX_SMAP,
1259 .features[FEAT_XSAVE] =
1260 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1261 .features[FEAT_6_EAX] =
1262 CPUID_6_EAX_ARAT,
3046bb5d 1263 .xlevel = 0x80000008,
a356850b
EH		 1264 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1265 },
ece01354
EH		 1266 {
1267 .name = "Broadwell",
1268 .level = 0xd,
1269 .vendor = CPUID_VENDOR_INTEL,
1270 .family = 6,
1271 .model = 61,
1272 .stepping = 2,
1273 .features[FEAT_1_EDX] =
b3a4f0b1 1274 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1275 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1276 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1277 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1278 CPUID_DE | CPUID_FP87,
1279 .features[FEAT_1_ECX] =
1280 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1281 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1282 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1283 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1284 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1285 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1286 .features[FEAT_8000_0001_EDX] =
1287 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1288 CPUID_EXT2_SYSCALL,
1289 .features[FEAT_8000_0001_ECX] =
becb6667 1290 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1291 .features[FEAT_7_0_EBX] =
1292 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1293 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1294 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1295 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1296 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1297 .features[FEAT_XSAVE] =
1298 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1299 .features[FEAT_6_EAX] =
1300 CPUID_6_EAX_ARAT,
3046bb5d 1301 .xlevel = 0x80000008,
ece01354
EH		 1302 .model_id = "Intel Core Processor (Broadwell)",
1303 },
f6f949e9
EH		 1304 {
1305 .name = "Skylake-Client",
1306 .level = 0xd,
1307 .vendor = CPUID_VENDOR_INTEL,
1308 .family = 6,
1309 .model = 94,
1310 .stepping = 3,
1311 .features[FEAT_1_EDX] =
1312 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1313 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1314 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1315 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1316 CPUID_DE | CPUID_FP87,
1317 .features[FEAT_1_ECX] =
1318 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1319 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1320 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1321 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1322 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1323 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1324 .features[FEAT_8000_0001_EDX] =
1325 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1326 CPUID_EXT2_SYSCALL,
1327 .features[FEAT_8000_0001_ECX] =
1328 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1329 .features[FEAT_7_0_EBX] =
1330 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1331 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1332 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1333 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1334 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1335 /* Missing: XSAVES (not supported by some Linux versions,
1336 * including v4.1 to v4.6).
1337 * KVM doesn't yet expose any XSAVES state save component,
1338 * and the only one defined in Skylake (processor tracing)
1339 * probably will block migration anyway.
1340 */
1341 .features[FEAT_XSAVE] =
1342 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1343 CPUID_XSAVE_XGETBV1,
1344 .features[FEAT_6_EAX] =
1345 CPUID_6_EAX_ARAT,
1346 .xlevel = 0x80000008,
1347 .model_id = "Intel Core Processor (Skylake)",
1348 },
3eca4642
EH		 1349 {
1350 .name = "Opteron_G1",
1351 .level = 5,
99b88a17 1352 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1353 .family = 15,
1354 .model = 6,
1355 .stepping = 1,
0514ef2f 1356 .features[FEAT_1_EDX] =
b3a4f0b1 1357 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1358 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1359 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1360 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1361 CPUID_DE | CPUID_FP87,
0514ef2f 1362 .features[FEAT_1_ECX] =
27861ecc 1363 CPUID_EXT_SSE3,
0514ef2f 1364 .features[FEAT_8000_0001_EDX] =
27861ecc 1365 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1366 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1367 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1368 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1369 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1370 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1371 .xlevel = 0x80000008,
1372 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1373 },
1374 {
1375 .name = "Opteron_G2",
1376 .level = 5,
99b88a17 1377 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1378 .family = 15,
1379 .model = 6,
1380 .stepping = 1,
0514ef2f 1381 .features[FEAT_1_EDX] =
b3a4f0b1 1382 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1383 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1384 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1385 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1386 CPUID_DE | CPUID_FP87,
0514ef2f 1387 .features[FEAT_1_ECX] =
27861ecc 1388 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1389 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1390 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1391 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1392 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1393 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1394 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1395 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1396 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1397 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1398 .features[FEAT_8000_0001_ECX] =
27861ecc 1399 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1400 .xlevel = 0x80000008,
1401 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1402 },
1403 {
1404 .name = "Opteron_G3",
1405 .level = 5,
99b88a17 1406 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1407 .family = 15,
1408 .model = 6,
1409 .stepping = 1,
0514ef2f 1410 .features[FEAT_1_EDX] =
b3a4f0b1 1411 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1412 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1413 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1414 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1415 CPUID_DE | CPUID_FP87,
0514ef2f 1416 .features[FEAT_1_ECX] =
27861ecc 1417 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1418 CPUID_EXT_SSE3,
33b5e8c0 1419 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1420 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1421 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1422 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1423 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1424 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1425 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1426 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1427 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1428 .features[FEAT_8000_0001_ECX] =
27861ecc 1429 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1430 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1431 .xlevel = 0x80000008,
1432 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1433 },
1434 {
1435 .name = "Opteron_G4",
1436 .level = 0xd,
99b88a17 1437 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1438 .family = 21,
1439 .model = 1,
1440 .stepping = 2,
0514ef2f 1441 .features[FEAT_1_EDX] =
b3a4f0b1 1442 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1443 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1444 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1445 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1446 CPUID_DE | CPUID_FP87,
0514ef2f 1447 .features[FEAT_1_ECX] =
27861ecc 1448 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1449 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1450 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1451 CPUID_EXT_SSE3,
33b5e8c0 1452 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1453 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1454 CPUID_EXT2_LM |
b3fb3a20
EH		 1455 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1456 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1457 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1458 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1459 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1460 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1461 .features[FEAT_8000_0001_ECX] =
27861ecc 1462 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1463 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1464 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1465 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1466 /* no xsaveopt! */
3eca4642
EH		 1467 .xlevel = 0x8000001A,
1468 .model_id = "AMD Opteron 62xx class CPU",
1469 },
021941b9
AP		 1470 {
1471 .name = "Opteron_G5",
1472 .level = 0xd,
99b88a17 1473 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1474 .family = 21,
1475 .model = 2,
1476 .stepping = 0,
0514ef2f 1477 .features[FEAT_1_EDX] =
b3a4f0b1 1478 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1479 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1480 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1481 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1482 CPUID_DE | CPUID_FP87,
0514ef2f 1483 .features[FEAT_1_ECX] =
27861ecc 1484 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1485 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1486 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1487 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1488 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1489 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1490 CPUID_EXT2_LM |
b3fb3a20
EH		 1491 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1492 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1493 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1494 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1495 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1496 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1497 .features[FEAT_8000_0001_ECX] =
27861ecc 1498 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1499 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1500 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1501 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1502 /* no xsaveopt! */
021941b9
AP		 1503 .xlevel = 0x8000001A,
1504 .model_id = "AMD Opteron 63xx class CPU",
1505 },
c6dc6f63
AP		 1506};
1507
5114e842
EH		 1508typedef struct PropValue {
1509 const char *prop, *value;
1510} PropValue;
1511
1512/* KVM-specific features that are automatically added/removed
1513 * from all CPU models when KVM is enabled.
1514 */
1515static PropValue kvm_default_props[] = {
1516 { "kvmclock", "on" },
1517 { "kvm-nopiodelay", "on" },
1518 { "kvm-asyncpf", "on" },
1519 { "kvm-steal-time", "on" },
1520 { "kvm-pv-eoi", "on" },
1521 { "kvmclock-stable-bit", "on" },
1522 { "x2apic", "on" },
1523 { "acpi", "off" },
1524 { "monitor", "off" },
1525 { "svm", "off" },
1526 { NULL, NULL },
1527};
1528
1529void x86_cpu_change_kvm_default(const char *prop, const char *value)
1530{
1531 PropValue *pv;
1532 for (pv = kvm_default_props; pv->prop; pv++) {
1533 if (!strcmp(pv->prop, prop)) {
1534 pv->value = value;
1535 break;
1536 }
1537 }
1538
1539 /* It is valid to call this function only for properties that
1540 * are already present in the kvm_default_props table.
1541 */
1542 assert(pv->prop);
1543}
1544
4d1b279b
EH		 1545static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1546 bool migratable_only);
1547
d940ee9b
EH		 1548#ifdef CONFIG_KVM
1549
40bfe48f
HZ		 1550static bool lmce_supported(void)
1551{
1552 uint64_t mce_cap;
1553
1554 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1555 return false;
1556 }
1557
1558 return !!(mce_cap & MCG_LMCE_P);
1559}
1560
c6dc6f63
AP		 1561static int cpu_x86_fill_model_id(char *str)
1562{
1563 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1564 int i;
1565
1566 for (i = 0; i < 3; i++) {
1567 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1568 memcpy(str + i * 16 + 0, &eax, 4);
1569 memcpy(str + i * 16 + 4, &ebx, 4);
1570 memcpy(str + i * 16 + 8, &ecx, 4);
1571 memcpy(str + i * 16 + 12, &edx, 4);
1572 }
1573 return 0;
1574}
1575
d940ee9b
EH		 1576static X86CPUDefinition host_cpudef;
1577
84f1b92f 1578static Property host_x86_cpu_properties[] = {
120eee7d 1579 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1580 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1581 DEFINE_PROP_END_OF_LIST()
1582};
1583
d940ee9b 1584/* class_init for the "host" CPU model
6e746f30 1585 *
d940ee9b 1586 * This function may be called before KVM is initialized.
6e746f30 1587 */
d940ee9b 1588static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1589{
84f1b92f 1590 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1591 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1592 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1593
d940ee9b 1594 xcc->kvm_required = true;
6e746f30 1595
c6dc6f63 1596 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1597 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1598
1599 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1600 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1601 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1602 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1603
d940ee9b 1604 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1605
d940ee9b 1606 xcc->cpu_def = &host_cpudef;
d940ee9b
EH		 1607
1608 /* level, xlevel, xlevel2, and the feature words are initialized on
1609 * instance_init, because they require KVM to be initialized.
1610 */
84f1b92f
EH		 1611
1612 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1613 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1614 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1615}
1616
1617static void host_x86_cpu_initfn(Object *obj)
1618{
1619 X86CPU *cpu = X86_CPU(obj);
1620 CPUX86State *env = &cpu->env;
1621 KVMState *s = kvm_state;
d940ee9b 1622
4d1b279b
EH		 1623 /* We can't fill the features array here because we don't know yet if
1624 * "migratable" is true or false.
1625 */
1626 cpu->host_features = true;
1627
104494ea 1628 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010
EH		 1629 if (kvm_enabled()) {
1630 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1631 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1632 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1633
1634 if (lmce_supported()) {
1635 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1636 }
e4356010 1637 }
2a573259 1638
d940ee9b 1639 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1640}
1641
d940ee9b
EH		 1642static const TypeInfo host_x86_cpu_type_info = {
1643 .name = X86_CPU_TYPE_NAME("host"),
1644 .parent = TYPE_X86_CPU,
1645 .instance_init = host_x86_cpu_initfn,
1646 .class_init = host_x86_cpu_class_init,
1647};
1648
1649#endif
1650
8459e396 1651static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1652{
8459e396 1653 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1654 int i;
1655
857aee33 1656 for (i = 0; i < 32; ++i) {
72370dc1 1657 if ((1UL << i) & mask) {
bffd67b0 1658 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1659 assert(reg);
fefb41bf 1660 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1661 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1662 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1663 f->cpuid_eax, reg,
1664 f->feat_names[i] ? "." : "",
1665 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1666 }
857aee33 1667 }
c6dc6f63
AP		 1668}
1669
d7bce999
EB		 1670static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1671 const char *name, void *opaque,
1672 Error **errp)
95b8519d
AF		 1673{
1674 X86CPU *cpu = X86_CPU(obj);
1675 CPUX86State *env = &cpu->env;
1676 int64_t value;
1677
1678 value = (env->cpuid_version >> 8) & 0xf;
1679 if (value == 0xf) {
1680 value += (env->cpuid_version >> 20) & 0xff;
1681 }
51e72bc1 1682 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1683}
1684
d7bce999
EB		 1685static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1686 const char *name, void *opaque,
1687 Error **errp)
ed5e1ec3 1688{
71ad61d3
AF		 1689 X86CPU *cpu = X86_CPU(obj);
1690 CPUX86State *env = &cpu->env;
1691 const int64_t min = 0;
1692 const int64_t max = 0xff + 0xf;
65cd9064 1693 Error *local_err = NULL;
71ad61d3
AF		 1694 int64_t value;
1695
51e72bc1 1696 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1697 if (local_err) {
1698 error_propagate(errp, local_err);
71ad61d3
AF		 1699 return;
1700 }
1701 if (value < min || value > max) {
c6bd8c70
MA		 1702 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1703 name ? name : "null", value, min, max);
71ad61d3
AF		 1704 return;
1705 }
1706
ed5e1ec3 1707 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1708 if (value > 0x0f) {
1709 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1710 } else {
71ad61d3 1711 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1712 }
1713}
1714
d7bce999
EB		 1715static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1716 const char *name, void *opaque,
1717 Error **errp)
67e30c83
AF		 1718{
1719 X86CPU *cpu = X86_CPU(obj);
1720 CPUX86State *env = &cpu->env;
1721 int64_t value;
1722
1723 value = (env->cpuid_version >> 4) & 0xf;
1724 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1725 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1726}
1727
d7bce999
EB		 1728static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1729 const char *name, void *opaque,
1730 Error **errp)
b0704cbd 1731{
c5291a4f
AF		 1732 X86CPU *cpu = X86_CPU(obj);
1733 CPUX86State *env = &cpu->env;
1734 const int64_t min = 0;
1735 const int64_t max = 0xff;
65cd9064 1736 Error *local_err = NULL;
c5291a4f
AF		 1737 int64_t value;
1738
51e72bc1 1739 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1740 if (local_err) {
1741 error_propagate(errp, local_err);
c5291a4f
AF		 1742 return;
1743 }
1744 if (value < min || value > max) {
c6bd8c70
MA		 1745 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1746 name ? name : "null", value, min, max);
c5291a4f
AF		 1747 return;
1748 }
1749
b0704cbd 1750 env->cpuid_version &= ~0xf00f0;
c5291a4f 1751 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1752}
1753
35112e41 1754static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1755 const char *name, void *opaque,
35112e41
AF		 1756 Error **errp)
1757{
1758 X86CPU *cpu = X86_CPU(obj);
1759 CPUX86State *env = &cpu->env;
1760 int64_t value;
1761
1762 value = env->cpuid_version & 0xf;
51e72bc1 1763 visit_type_int(v, name, &value, errp);
35112e41
AF		 1764}
1765
036e2222 1766static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1767 const char *name, void *opaque,
036e2222 1768 Error **errp)
38c3dc46 1769{
036e2222
AF		 1770 X86CPU *cpu = X86_CPU(obj);
1771 CPUX86State *env = &cpu->env;
1772 const int64_t min = 0;
1773 const int64_t max = 0xf;
65cd9064 1774 Error *local_err = NULL;
036e2222
AF		 1775 int64_t value;
1776
51e72bc1 1777 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1778 if (local_err) {
1779 error_propagate(errp, local_err);
036e2222
AF		 1780 return;
1781 }
1782 if (value < min || value > max) {
c6bd8c70
MA		 1783 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1784 name ? name : "null", value, min, max);
036e2222
AF		 1785 return;
1786 }
1787
38c3dc46 1788 env->cpuid_version &= ~0xf;
036e2222 1789 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1790}
1791
d480e1af
AF		 1792static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1793{
1794 X86CPU *cpu = X86_CPU(obj);
1795 CPUX86State *env = &cpu->env;
1796 char *value;
d480e1af 1797
e42a92ae 1798 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1799 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1800 env->cpuid_vendor3);
d480e1af
AF		 1801 return value;
1802}
1803
1804static void x86_cpuid_set_vendor(Object *obj, const char *value,
1805 Error **errp)
1806{
1807 X86CPU *cpu = X86_CPU(obj);
1808 CPUX86State *env = &cpu->env;
1809 int i;
1810
9df694ee 1811 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1812 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1813 return;
1814 }
1815
1816 env->cpuid_vendor1 = 0;
1817 env->cpuid_vendor2 = 0;
1818 env->cpuid_vendor3 = 0;
1819 for (i = 0; i < 4; i++) {
1820 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1821 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1822 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1823 }
d480e1af
AF		 1824}
1825
63e886eb
AF		 1826static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1827{
1828 X86CPU *cpu = X86_CPU(obj);
1829 CPUX86State *env = &cpu->env;
1830 char *value;
1831 int i;
1832
1833 value = g_malloc(48 + 1);
1834 for (i = 0; i < 48; i++) {
1835 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1836 }
1837 value[48] = '\0';
1838 return value;
1839}
1840
938d4c25
AF		 1841static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1842 Error **errp)
dcce6675 1843{
938d4c25
AF		 1844 X86CPU *cpu = X86_CPU(obj);
1845 CPUX86State *env = &cpu->env;
dcce6675
AF		 1846 int c, len, i;
1847
1848 if (model_id == NULL) {
1849 model_id = "";
1850 }
1851 len = strlen(model_id);
d0a6acf4 1852 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1853 for (i = 0; i < 48; i++) {
1854 if (i >= len) {
1855 c = '\0';
1856 } else {
1857 c = (uint8_t)model_id[i];
1858 }
1859 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1860 }
1861}
1862
d7bce999
EB		 1863static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1864 void *opaque, Error **errp)
89e48965
AF		 1865{
1866 X86CPU *cpu = X86_CPU(obj);
1867 int64_t value;
1868
1869 value = cpu->env.tsc_khz * 1000;
51e72bc1 1870 visit_type_int(v, name, &value, errp);
89e48965
AF		 1871}
1872
d7bce999
EB		 1873static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1874 void *opaque, Error **errp)
89e48965
AF		 1875{
1876 X86CPU *cpu = X86_CPU(obj);
1877 const int64_t min = 0;
2e84849a 1878 const int64_t max = INT64_MAX;
65cd9064 1879 Error *local_err = NULL;
89e48965
AF		 1880 int64_t value;
1881
51e72bc1 1882 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1883 if (local_err) {
1884 error_propagate(errp, local_err);
89e48965
AF		 1885 return;
1886 }
1887 if (value < min || value > max) {
c6bd8c70
MA		 1888 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1889 name ? name : "null", value, min, max);
89e48965
AF		 1890 return;
1891 }
1892
36f96c4b 1893 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1894}
1895
d7bce999
EB		 1896static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, const char *name,
1897 void *opaque, Error **errp)
31050930
IM		 1898{
1899 X86CPU *cpu = X86_CPU(obj);
7e72a45c 1900 int64_t value = cpu->apic_id;
31050930 1901
51e72bc1 1902 visit_type_int(v, name, &value, errp);
31050930
IM		 1903}
1904
d7bce999
EB		 1905static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, const char *name,
1906 void *opaque, Error **errp)
31050930
IM		 1907{
1908 X86CPU *cpu = X86_CPU(obj);
8d6d4980 1909 DeviceState *dev = DEVICE(obj);
31050930
IM		 1910 Error *error = NULL;
1911 int64_t value;
1912
8d6d4980
IM		 1913 if (dev->realized) {
1914 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1915 "it was realized", name, object_get_typename(obj));
1916 return;
1917 }
1918
51e72bc1 1919 visit_type_int(v, name, &value, &error);
31050930
IM		 1920 if (error) {
1921 error_propagate(errp, error);
1922 return;
1923 }
7e72a45c 1924 cpu->apic_id = value;
31050930
IM		 1925}
1926
7e5292b5 1927/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1928static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1929 const char *name, void *opaque,
1930 Error **errp)
8e8aba50 1931{
7e5292b5 1932 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1933 FeatureWord w;
8e8aba50
EH		 1934 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1935 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1936 X86CPUFeatureWordInfoList *list = NULL;
1937
1938 for (w = 0; w < FEATURE_WORDS; w++) {
1939 FeatureWordInfo *wi = &feature_word_info[w];
1940 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1941 qwi->cpuid_input_eax = wi->cpuid_eax;
1942 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1943 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1944 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1945 qwi->features = array[w];
8e8aba50
EH		 1946
1947 /* List will be in reverse order, but order shouldn't matter */
1948 list_entries[w].next = list;
1949 list_entries[w].value = &word_infos[w];
1950 list = &list_entries[w];
1951 }
1952
6b62d961 1953 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1954}
1955
d7bce999
EB		 1956static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1957 void *opaque, Error **errp)
c8f0f88e
IM		 1958{
1959 X86CPU *cpu = X86_CPU(obj);
1960 int64_t value = cpu->hyperv_spinlock_attempts;
1961
51e72bc1 1962 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1963}
1964
d7bce999
EB		 1965static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1966 void *opaque, Error **errp)
c8f0f88e
IM		 1967{
1968 const int64_t min = 0xFFF;
1969 const int64_t max = UINT_MAX;
1970 X86CPU *cpu = X86_CPU(obj);
1971 Error *err = NULL;
1972 int64_t value;
1973
51e72bc1 1974 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1975 if (err) {
1976 error_propagate(errp, err);
1977 return;
1978 }
1979
1980 if (value < min || value > max) {
1981 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1982 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1983 object_get_typename(obj), name ? name : "null",
1984 value, min, max);
c8f0f88e
IM		 1985 return;
1986 }
1987 cpu->hyperv_spinlock_attempts = value;
1988}
1989
1990static PropertyInfo qdev_prop_spinlocks = {
1991 .name = "int",
1992 .get = x86_get_hv_spinlocks,
1993 .set = x86_set_hv_spinlocks,
1994};
1995
72ac2e87
IM		 1996/* Convert all '_' in a feature string option name to '-', to make feature
1997 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1998 */
1999static inline void feat2prop(char *s)
2000{
2001 while ((s = strchr(s, '_'))) {
2002 *s = '-';
2003 }
2004}
2005
dc15c051
IM		 2006/* Compatibily hack to maintain legacy +-feat semantic,
2007 * where +-feat overwrites any feature set by
2008 * feat=on|feat even if the later is parsed after +-feat
2009 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2010 */
2011static FeatureWordArray plus_features = { 0 };
2012static FeatureWordArray minus_features = { 0 };
2013
8f961357
EH		 2014/* Parse "+feature,-feature,feature=foo" CPU feature string
2015 */
62a48a2a 2016static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 2017 Error **errp)
8f961357 2018{
8f961357 2019 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 2020 Error *local_err = NULL;
62a48a2a
IM		 2021 static bool cpu_globals_initialized;
2022
2023 if (cpu_globals_initialized) {
2024 return;
2025 }
2026 cpu_globals_initialized = true;
8f961357 2027
f6750e95
EH		 2028 if (!features) {
2029 return;
2030 }
2031
2032 for (featurestr = strtok(features, ",");
2033 featurestr && !local_err;
2034 featurestr = strtok(NULL, ",")) {
2035 const char *name;
2036 const char *val = NULL;
2037 char *eq = NULL;
cf2887c9 2038 char num[32];
62a48a2a 2039 GlobalProperty *prop;
c6dc6f63 2040
f6750e95 2041 /* Compatibility syntax: */
c6dc6f63 2042 if (featurestr[0] == '+') {
c00c94ab 2043 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
f6750e95 2044 continue;
c6dc6f63 2045 } else if (featurestr[0] == '-') {
c00c94ab 2046 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
f6750e95
EH		 2047 continue;
2048 }
2049
2050 eq = strchr(featurestr, '=');
2051 if (eq) {
2052 *eq++ = 0;
2053 val = eq;
c6dc6f63 2054 } else {
f6750e95 2055 val = "on";
a91987c2 2056 }
f6750e95
EH		 2057
2058 feat2prop(featurestr);
2059 name = featurestr;
2060
2061 /* Special case: */
2062 if (!strcmp(name, "tsc-freq")) {
2063 int64_t tsc_freq;
2064 char *err;
f6750e95
EH		 2065
2066 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2067 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2068 if (tsc_freq < 0 || *err) {
2069 error_setg(errp, "bad numerical value %s", val);
2070 return;
2071 }
2072 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2073 val = num;
2074 name = "tsc-frequency";
c6dc6f63 2075 }
f6750e95 2076
62a48a2a
IM		 2077 prop = g_new0(typeof(*prop), 1);
2078 prop->driver = typename;
2079 prop->property = g_strdup(name);
2080 prop->value = g_strdup(val);
2081 prop->errp = &error_fatal;
2082 qdev_prop_register_global(prop);
f6750e95
EH		 2083 }
2084
2085 if (local_err) {
2086 error_propagate(errp, local_err);
c6dc6f63 2087 }
c6dc6f63
AP		 2088}
2089
8c3329e5 2090/* Print all cpuid feature names in featureset
c6dc6f63 2091 */
8c3329e5 2092static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2093{
8c3329e5
EH		 2094 int bit;
2095 bool first = true;
2096
2097 for (bit = 0; bit < 32; bit++) {
2098 if (featureset[bit]) {
2099 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2100 first = false;
c6dc6f63 2101 }
8c3329e5 2102 }
c6dc6f63
AP		 2103}
2104
e916cbf8
PM		 2105/* generate CPU information. */
2106void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2107{
9576de75 2108 X86CPUDefinition *def;
c6dc6f63 2109 char buf[256];
7fc9b714 2110 int i;
c6dc6f63 2111
7fc9b714
AF		 2112 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2113 def = &builtin_x86_defs[i];
c04321b3 2114 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2115 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2116 }
21ad7789
JK		 2117#ifdef CONFIG_KVM
2118 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2119 "KVM processor with all supported host features "
2120 "(only available in KVM mode)");
2121#endif
2122
6cdf8854 2123 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2124 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2125 FeatureWordInfo *fw = &feature_word_info[i];
2126
8c3329e5
EH		 2127 (*cpu_fprintf)(f, " ");
2128 listflags(f, cpu_fprintf, fw->feat_names);
2129 (*cpu_fprintf)(f, "\n");
3af60be2 2130 }
c6dc6f63
AP		 2131}
2132
76b64a7a 2133CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2134{
2135 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2136 X86CPUDefinition *def;
7fc9b714 2137 int i;
e3966126 2138
7fc9b714 2139 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2140 CpuDefinitionInfoList *entry;
2141 CpuDefinitionInfo *info;
2142
7fc9b714 2143 def = &builtin_x86_defs[i];
e3966126
AL		 2144 info = g_malloc0(sizeof(*info));
2145 info->name = g_strdup(def->name);
2146
2147 entry = g_malloc0(sizeof(*entry));
2148 entry->value = info;
2149 entry->next = cpu_list;
2150 cpu_list = entry;
2151 }
2152
2153 return cpu_list;
2154}
2155
84f1b92f
EH		 2156static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2157 bool migratable_only)
27418adf
EH		 2158{
2159 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2160 uint32_t r;
27418adf 2161
fefb41bf 2162 if (kvm_enabled()) {
84f1b92f
EH		 2163 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2164 wi->cpuid_ecx,
2165 wi->cpuid_reg);
fefb41bf 2166 } else if (tcg_enabled()) {
84f1b92f 2167 r = wi->tcg_features;
fefb41bf
EH		 2168 } else {
2169 return ~0;
2170 }
84f1b92f
EH		 2171 if (migratable_only) {
2172 r &= x86_cpu_get_migratable_flags(w);
2173 }
2174 return r;
27418adf
EH		 2175}
2176
51f63aed
EH		 2177/*
2178 * Filters CPU feature words based on host availability of each feature.
2179 *
51f63aed
EH		 2180 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2181 */
27418adf 2182static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2183{
2184 CPUX86State *env = &cpu->env;
bd87d2a2 2185 FeatureWord w;
51f63aed
EH		 2186 int rv = 0;
2187
bd87d2a2 2188 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2189 uint32_t host_feat =
2190 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2191 uint32_t requested_features = env->features[w];
2192 env->features[w] &= host_feat;
2193 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2194 if (cpu->filtered_features[w]) {
2195 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2196 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2197 }
2198 rv = 1;
2199 }
bd87d2a2 2200 }
51f63aed
EH		 2201
2202 return rv;
bc74b7db 2203}
bc74b7db 2204
5114e842
EH		 2205static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2206{
2207 PropValue *pv;
2208 for (pv = props; pv->prop; pv++) {
2209 if (!pv->value) {
2210 continue;
2211 }
2212 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2213 &error_abort);
2214 }
2215}
2216
d940ee9b 2217/* Load data from X86CPUDefinition
c080e30e 2218 */
d940ee9b 2219static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2220{
61dcd775 2221 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2222 const char *vendor;
2223 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2224 FeatureWord w;
c6dc6f63 2225
2d64255b
AF		 2226 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2227 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2228 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2229 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2230 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2231 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2d64255b 2232 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2233 for (w = 0; w < FEATURE_WORDS; w++) {
2234 env->features[w] = def->features[w];
2235 }
82beb536 2236
9576de75 2237 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2238 if (kvm_enabled()) {
492a4c94
LT		 2239 if (!kvm_irqchip_in_kernel()) {
2240 x86_cpu_change_kvm_default("x2apic", "off");
2241 }
2242
5114e842 2243 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2244 }
5fcca9ff 2245
82beb536 2246 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2247
2248 /* sysenter isn't supported in compatibility mode on AMD,
2249 * syscall isn't supported in compatibility mode on Intel.
2250 * Normally we advertise the actual CPU vendor, but you can
2251 * override this using the 'vendor' property if you want to use
2252 * KVM's sysenter/syscall emulation in compatibility mode and
2253 * when doing cross vendor migration
2254 */
74f54bc4 2255 vendor = def->vendor;
7c08db30
EH		 2256 if (kvm_enabled()) {
2257 uint32_t ebx = 0, ecx = 0, edx = 0;
2258 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2259 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2260 vendor = host_vendor;
2261 }
2262
2263 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2264
c6dc6f63
AP		 2265}
2266
0856579c 2267X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2268{
a57d0163 2269 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2270}
2271
d940ee9b
EH		 2272static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2273{
2274 X86CPUDefinition *cpudef = data;
2275 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2276
2277 xcc->cpu_def = cpudef;
2278}
2279
2280static void x86_register_cpudef_type(X86CPUDefinition *def)
2281{
2282 char *typename = x86_cpu_type_name(def->name);
2283 TypeInfo ti = {
2284 .name = typename,
2285 .parent = TYPE_X86_CPU,
2286 .class_init = x86_cpu_cpudef_class_init,
2287 .class_data = def,
2288 };
2289
2290 type_register(&ti);
2291 g_free(typename);
2292}
2293
c6dc6f63 2294#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2295
0e26b7b8
BS		 2296void cpu_clear_apic_feature(CPUX86State *env)
2297{
0514ef2f 2298 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2299}
2300
c6dc6f63
AP		 2301#endif /* !CONFIG_USER_ONLY */
2302
c6dc6f63
AP		 2303void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2304 uint32_t *eax, uint32_t *ebx,
2305 uint32_t *ecx, uint32_t *edx)
2306{
a60f24b5
AF		 2307 X86CPU *cpu = x86_env_get_cpu(env);
2308 CPUState *cs = CPU(cpu);
2309
c6dc6f63
AP		 2310 /* test if maximum index reached */
2311 if (index & 0x80000000) {
b3baa152
BW		 2312 if (index > env->cpuid_xlevel) {
2313 if (env->cpuid_xlevel2 > 0) {
2314 /* Handle the Centaur's CPUID instruction. */
2315 if (index > env->cpuid_xlevel2) {
2316 index = env->cpuid_xlevel2;
2317 } else if (index < 0xC0000000) {
2318 index = env->cpuid_xlevel;
2319 }
2320 } else {
57f26ae7
EH		 2321 /* Intel documentation states that invalid EAX input will
2322 * return the same information as EAX=cpuid_level
2323 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2324 */
2325 index = env->cpuid_level;
b3baa152
BW		 2326 }
2327 }
c6dc6f63
AP		 2328 } else {
2329 if (index > env->cpuid_level)
2330 index = env->cpuid_level;
2331 }
2332
2333 switch(index) {
2334 case 0:
2335 *eax = env->cpuid_level;
5eb2f7a4
EH		 2336 *ebx = env->cpuid_vendor1;
2337 *edx = env->cpuid_vendor2;
2338 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2339 break;
2340 case 1:
2341 *eax = env->cpuid_version;
7e72a45c
EH		 2342 *ebx = (cpu->apic_id << 24) |
2343 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2344 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2345 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2346 *ecx |= CPUID_EXT_OSXSAVE;
2347 }
0514ef2f 2348 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2349 if (cs->nr_cores * cs->nr_threads > 1) {
2350 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2351 *edx |= CPUID_HT;
c6dc6f63
AP		 2352 }
2353 break;
2354 case 2:
2355 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2356 if (cpu->cache_info_passthrough) {
2357 host_cpuid(index, 0, eax, ebx, ecx, edx);
2358 break;
2359 }
5e891bf8 2360 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63
AP		 2361 *ebx = 0;
2362 *ecx = 0;
5e891bf8
EH		 2363 *edx = (L1D_DESCRIPTOR << 16) | \
2364 (L1I_DESCRIPTOR << 8) | \
2365 (L2_DESCRIPTOR);
c6dc6f63
AP		 2366 break;
2367 case 4:
2368 /* cache info: needed for Core compatibility */
787aaf57
BC		 2369 if (cpu->cache_info_passthrough) {
2370 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2371 *eax &= ~0xFC000000;
c6dc6f63 2372 } else {
2f7a21c4 2373 *eax = 0;
76c2975a 2374 switch (count) {
c6dc6f63 2375 case 0: /* L1 dcache info */
5e891bf8
EH		 2376 *eax |= CPUID_4_TYPE_DCACHE | \
2377 CPUID_4_LEVEL(1) | \
2378 CPUID_4_SELF_INIT_LEVEL;
2379 *ebx = (L1D_LINE_SIZE - 1) | \
2380 ((L1D_PARTITIONS - 1) << 12) | \
2381 ((L1D_ASSOCIATIVITY - 1) << 22);
2382 *ecx = L1D_SETS - 1;
2383 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2384 break;
2385 case 1: /* L1 icache info */
5e891bf8
EH		 2386 *eax |= CPUID_4_TYPE_ICACHE | \
2387 CPUID_4_LEVEL(1) | \
2388 CPUID_4_SELF_INIT_LEVEL;
2389 *ebx = (L1I_LINE_SIZE - 1) | \
2390 ((L1I_PARTITIONS - 1) << 12) | \
2391 ((L1I_ASSOCIATIVITY - 1) << 22);
2392 *ecx = L1I_SETS - 1;
2393 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2394 break;
2395 case 2: /* L2 cache info */
5e891bf8
EH		 2396 *eax |= CPUID_4_TYPE_UNIFIED | \
2397 CPUID_4_LEVEL(2) | \
2398 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2399 if (cs->nr_threads > 1) {
2400 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2401 }
5e891bf8
EH		 2402 *ebx = (L2_LINE_SIZE - 1) | \
2403 ((L2_PARTITIONS - 1) << 12) | \
2404 ((L2_ASSOCIATIVITY - 1) << 22);
2405 *ecx = L2_SETS - 1;
2406 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2407 break;
2408 default: /* end of info */
2409 *eax = 0;
2410 *ebx = 0;
2411 *ecx = 0;
2412 *edx = 0;
2413 break;
76c2975a
PB		 2414 }
2415 }
2416
2417 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2418 if ((*eax & 31) && cs->nr_cores > 1) {
2419 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2420 }
2421 break;
2422 case 5:
2423 /* mwait info: needed for Core compatibility */
2424 *eax = 0; /* Smallest monitor-line size in bytes */
2425 *ebx = 0; /* Largest monitor-line size in bytes */
2426 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2427 *edx = 0;
2428 break;
2429 case 6:
2430 /* Thermal and Power Leaf */
28b8e4d0 2431 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2432 *ebx = 0;
2433 *ecx = 0;
2434 *edx = 0;
2435 break;
f7911686 2436 case 7:
13526728
EH		 2437 /* Structured Extended Feature Flags Enumeration Leaf */
2438 if (count == 0) {
2439 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2440 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2441 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2442 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2443 *ecx |= CPUID_7_0_ECX_OSPKE;
2444 }
13526728 2445 *edx = 0; /* Reserved */
f7911686
YW		 2446 } else {
2447 *eax = 0;
2448 *ebx = 0;
2449 *ecx = 0;
2450 *edx = 0;
2451 }
2452 break;
c6dc6f63
AP		 2453 case 9:
2454 /* Direct Cache Access Information Leaf */
2455 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2456 *ebx = 0;
2457 *ecx = 0;
2458 *edx = 0;
2459 break;
2460 case 0xA:
2461 /* Architectural Performance Monitoring Leaf */
9337e3b6 2462 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2463 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2464
2465 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2466 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2467 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2468 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2469 } else {
2470 *eax = 0;
2471 *ebx = 0;
2472 *ecx = 0;
2473 *edx = 0;
2474 }
c6dc6f63 2475 break;
5232d00a
RK		 2476 case 0xB:
2477 /* Extended Topology Enumeration Leaf */
2478 if (!cpu->enable_cpuid_0xb) {
2479 *eax = *ebx = *ecx = *edx = 0;
2480 break;
2481 }
2482
2483 *ecx = count & 0xff;
2484 *edx = cpu->apic_id;
2485
2486 switch (count) {
2487 case 0:
2488 *eax = apicid_core_offset(smp_cores, smp_threads);
2489 *ebx = smp_threads;
2490 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2491 break;
2492 case 1:
2493 *eax = apicid_pkg_offset(smp_cores, smp_threads);
2494 *ebx = smp_cores * smp_threads;
2495 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2496 break;
2497 default:
2498 *eax = 0;
2499 *ebx = 0;
2500 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2501 }
2502
2503 assert(!(*eax & ~0x1f));
2504 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2505 break;
2560f19f
PB		 2506 case 0xD: {
2507 KVMState *s = cs->kvm_state;
19dc85db 2508 uint64_t ena_mask;
2560f19f
PB		 2509 int i;
2510
51e49430 2511 /* Processor Extended State */
2560f19f
PB		 2512 *eax = 0;
2513 *ebx = 0;
2514 *ecx = 0;
2515 *edx = 0;
19dc85db 2516 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2517 break;
2518 }
19dc85db
RH		 2519 if (kvm_enabled()) {
2520 ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2521 ena_mask <<= 32;
2522 ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2523 } else {
2524 ena_mask = -1;
2525 }
ba9bc59e 2526
2560f19f
PB		 2527 if (count == 0) {
2528 *ecx = 0x240;
f4f1110e
RH		 2529 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2530 const ExtSaveArea *esa = &x86_ext_save_areas[i];
19dc85db
RH		 2531 if ((env->features[esa->feature] & esa->bits) == esa->bits
2532 && ((ena_mask >> i) & 1) != 0) {
2560f19f 2533 if (i < 32) {
19dc85db 2534 *eax |= 1u << i;
2560f19f 2535 } else {
19dc85db 2536 *edx |= 1u << (i - 32);
2560f19f
PB		 2537 }
2538 *ecx = MAX(*ecx, esa->offset + esa->size);
2539 }
2540 }
cfc3b074 2541 *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2560f19f
PB		 2542 *ebx = *ecx;
2543 } else if (count == 1) {
0bb0b2d2 2544 *eax = env->features[FEAT_XSAVE];
f4f1110e
RH		 2545 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2546 const ExtSaveArea *esa = &x86_ext_save_areas[count];
19dc85db
RH		 2547 if ((env->features[esa->feature] & esa->bits) == esa->bits
2548 && ((ena_mask >> count) & 1) != 0) {
33f373d7
LJ		 2549 *eax = esa->size;
2550 *ebx = esa->offset;
2560f19f 2551 }
51e49430
SY		 2552 }
2553 break;
2560f19f 2554 }
c6dc6f63
AP		 2555 case 0x80000000:
2556 *eax = env->cpuid_xlevel;
2557 *ebx = env->cpuid_vendor1;
2558 *edx = env->cpuid_vendor2;
2559 *ecx = env->cpuid_vendor3;
2560 break;
2561 case 0x80000001:
2562 *eax = env->cpuid_version;
2563 *ebx = 0;
0514ef2f
EH		 2564 *ecx = env->features[FEAT_8000_0001_ECX];
2565 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2566
2567 /* The Linux kernel checks for the CMPLegacy bit and
2568 * discards multiple thread information if it is set.
cb8d4c8f 2569 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2570 */
ce3960eb 2571 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2572 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2573 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2574 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2575 *ecx |= 1 << 1; /* CmpLegacy bit */
2576 }
2577 }
c6dc6f63
AP		 2578 break;
2579 case 0x80000002:
2580 case 0x80000003:
2581 case 0x80000004:
2582 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2583 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2584 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2585 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2586 break;
2587 case 0x80000005:
2588 /* cache info (L1 cache) */
787aaf57
BC		 2589 if (cpu->cache_info_passthrough) {
2590 host_cpuid(index, 0, eax, ebx, ecx, edx);
2591 break;
2592 }
5e891bf8
EH		 2593 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2594 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2595 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2596 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2597 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2598 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2599 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2600 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2601 break;
2602 case 0x80000006:
2603 /* cache info (L2 cache) */
787aaf57
BC		 2604 if (cpu->cache_info_passthrough) {
2605 host_cpuid(index, 0, eax, ebx, ecx, edx);
2606 break;
2607 }
5e891bf8
EH		 2608 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2609 (L2_DTLB_2M_ENTRIES << 16) | \
2610 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2611 (L2_ITLB_2M_ENTRIES);
2612 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2613 (L2_DTLB_4K_ENTRIES << 16) | \
2614 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2615 (L2_ITLB_4K_ENTRIES);
2616 *ecx = (L2_SIZE_KB_AMD << 16) | \
2617 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2618 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2619 *edx = ((L3_SIZE_KB/512) << 18) | \
2620 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2621 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
c6dc6f63 2622 break;
303752a9
MT		 2623 case 0x80000007:
2624 *eax = 0;
2625 *ebx = 0;
2626 *ecx = 0;
2627 *edx = env->features[FEAT_8000_0007_EDX];
2628 break;
c6dc6f63
AP		 2629 case 0x80000008:
2630 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2631 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a
DDAG		 2632 /* 64 bit processor, 48 bits virtual, configurable
2633 * physical bits.
2634 */
2635 *eax = 0x00003000 + cpu->phys_bits;
c6dc6f63 2636 } else {
af45907a 2637 *eax = cpu->phys_bits;
c6dc6f63
AP		 2638 }
2639 *ebx = 0;
2640 *ecx = 0;
2641 *edx = 0;
ce3960eb
AF		 2642 if (cs->nr_cores * cs->nr_threads > 1) {
2643 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2644 }
2645 break;
2646 case 0x8000000A:
0514ef2f 2647 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2648 *eax = 0x00000001; /* SVM Revision */
2649 *ebx = 0x00000010; /* nr of ASIDs */
2650 *ecx = 0;
0514ef2f 2651 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2652 } else {
2653 *eax = 0;
2654 *ebx = 0;
2655 *ecx = 0;
2656 *edx = 0;
2657 }
c6dc6f63 2658 break;
b3baa152
BW		 2659 case 0xC0000000:
2660 *eax = env->cpuid_xlevel2;
2661 *ebx = 0;
2662 *ecx = 0;
2663 *edx = 0;
2664 break;
2665 case 0xC0000001:
2666 /* Support for VIA CPU's CPUID instruction */
2667 *eax = env->cpuid_version;
2668 *ebx = 0;
2669 *ecx = 0;
0514ef2f 2670 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2671 break;
2672 case 0xC0000002:
2673 case 0xC0000003:
2674 case 0xC0000004:
2675 /* Reserved for the future, and now filled with zero */
2676 *eax = 0;
2677 *ebx = 0;
2678 *ecx = 0;
2679 *edx = 0;
2680 break;
c6dc6f63
AP		 2681 default:
2682 /* reserved values: zero */
2683 *eax = 0;
2684 *ebx = 0;
2685 *ecx = 0;
2686 *edx = 0;
2687 break;
2688 }
2689}
5fd2087a
AF		 2690
2691/* CPUClass::reset() */
2692static void x86_cpu_reset(CPUState *s)
2693{
2694 X86CPU *cpu = X86_CPU(s);
2695 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2696 CPUX86State *env = &cpu->env;
a114d25d
RH		 2697 target_ulong cr4;
2698 uint64_t xcr0;
c1958aea
AF		 2699 int i;
2700
5fd2087a
AF		 2701 xcc->parent_reset(s);
2702
43175fa9 2703 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2704
00c8cb0a 2705 tlb_flush(s, 1);
c1958aea
AF		 2706
2707 env->old_exception = -1;
2708
2709 /* init to reset state */
2710
c1958aea
AF		 2711 env->hflags2 |= HF2_GIF_MASK;
2712
2713 cpu_x86_update_cr0(env, 0x60000010);
2714 env->a20_mask = ~0x0;
2715 env->smbase = 0x30000;
2716
2717 env->idt.limit = 0xffff;
2718 env->gdt.limit = 0xffff;
2719 env->ldt.limit = 0xffff;
2720 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2721 env->tr.limit = 0xffff;
2722 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2723
2724 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2725 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2726 DESC_R_MASK | DESC_A_MASK);
2727 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2728 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2729 DESC_A_MASK);
2730 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2731 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2732 DESC_A_MASK);
2733 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2734 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2735 DESC_A_MASK);
2736 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2737 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2738 DESC_A_MASK);
2739 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2740 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2741 DESC_A_MASK);
2742
2743 env->eip = 0xfff0;
2744 env->regs[R_EDX] = env->cpuid_version;
2745
2746 env->eflags = 0x2;
2747
2748 /* FPU init */
2749 for (i = 0; i < 8; i++) {
2750 env->fptags[i] = 1;
2751 }
5bde1407 2752 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2753
2754 env->mxcsr = 0x1f80;
a114d25d
RH		 2755 /* All units are in INIT state. */
2756 env->xstate_bv = 0;
c1958aea
AF		 2757
2758 env->pat = 0x0007040600070406ULL;
2759 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2760
2761 memset(env->dr, 0, sizeof(env->dr));
2762 env->dr[6] = DR6_FIXED_1;
2763 env->dr[7] = DR7_FIXED_1;
b3310ab3 2764 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2765 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2766
a114d25d 2767 cr4 = 0;
cfc3b074 2768 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2769
2770#ifdef CONFIG_USER_ONLY
2771 /* Enable all the features for user-mode. */
2772 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2773 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2774 }
0f70ed47
PB		 2775 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2776 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2777 if ((env->features[esa->feature] & esa->bits) == esa->bits) {
2778 xcr0 |= 1ull << i;
2779 }
a114d25d 2780 }
0f70ed47 2781
a114d25d
RH		 2782 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2783 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2784 }
07929f2a
RH		 2785 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2786 cr4 |= CR4_FSGSBASE_MASK;
2787 }
a114d25d
RH		 2788#endif
2789
2790 env->xcr0 = xcr0;
2791 cpu_x86_update_cr4(env, cr4);
0522604b 2792
9db2efd9
AW		 2793 /*
2794 * SDM 11.11.5 requires:
2795 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2796 * - IA32_MTRR_PHYSMASKn.V = 0
2797 * All other bits are undefined. For simplification, zero it all.
2798 */
2799 env->mtrr_deftype = 0;
2800 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2801 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2802
dd673288
IM		 2803#if !defined(CONFIG_USER_ONLY)
2804 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2805 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2806
259186a7 2807 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2808
2809 if (kvm_enabled()) {
2810 kvm_arch_reset_vcpu(cpu);
2811 }
dd673288 2812#endif
5fd2087a
AF		 2813}
2814
dd673288
IM		 2815#ifndef CONFIG_USER_ONLY
2816bool cpu_is_bsp(X86CPU *cpu)
2817{
02e51483 2818 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2819}
65dee380
IM		 2820
2821/* TODO: remove me, when reset over QOM tree is implemented */
2822static void x86_cpu_machine_reset_cb(void *opaque)
2823{
2824 X86CPU *cpu = opaque;
2825 cpu_reset(CPU(cpu));
2826}
dd673288
IM		 2827#endif
2828
de024815
AF		 2829static void mce_init(X86CPU *cpu)
2830{
2831 CPUX86State *cenv = &cpu->env;
2832 unsigned int bank;
2833
2834 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2835 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2836 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2837 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2838 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2839 cenv->mcg_ctl = ~(uint64_t)0;
2840 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2841 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2842 }
2843 }
2844}
2845
bdeec802 2846#ifndef CONFIG_USER_ONLY
d3c64d6a 2847static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2848{
449994eb 2849 APICCommonState *apic;
bdeec802
IM		 2850 const char *apic_type = "apic";
2851
15eafc2e 2852 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2853 apic_type = "kvm-apic";
2854 } else if (xen_enabled()) {
2855 apic_type = "xen-apic";
2856 }
2857
46232aaa 2858 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802
IM		 2859
2860 object_property_add_child(OBJECT(cpu), "apic",
02e51483 2861 OBJECT(cpu->apic_state), NULL);
7e72a45c 2862 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2863 /* TODO: convert to link<> */
02e51483 2864 apic = APIC_COMMON(cpu->apic_state);
60671e58 2865 apic->cpu = cpu;
8d42d2d3 2866 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2867}
2868
2869static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2870{
8d42d2d3
CF		 2871 APICCommonState *apic;
2872 static bool apic_mmio_map_once;
2873
02e51483 2874 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2875 return;
2876 }
6e8e2651
MA		 2877 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2878 errp);
8d42d2d3
CF		 2879
2880 /* Map APIC MMIO area */
2881 apic = APIC_COMMON(cpu->apic_state);
2882 if (!apic_mmio_map_once) {
2883 memory_region_add_subregion_overlap(get_system_memory(),
2884 apic->apicbase &
2885 MSR_IA32_APICBASE_BASE,
2886 &apic->io_memory,
2887 0x1000);
2888 apic_mmio_map_once = true;
2889 }
bdeec802 2890}
f809c605
PB		 2891
2892static void x86_cpu_machine_done(Notifier *n, void *unused)
2893{
2894 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2895 MemoryRegion *smram =
2896 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2897
2898 if (smram) {
2899 cpu->smram = g_new(MemoryRegion, 1);
2900 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2901 smram, 0, 1ull << 32);
2902 memory_region_set_enabled(cpu->smram, false);
2903 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2904 }
2905}
d3c64d6a
IM		 2906#else
2907static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2908{
2909}
bdeec802
IM		 2910#endif
2911
11f6fee5
DDAG		 2912/* Note: Only safe for use on x86(-64) hosts */
2913static uint32_t x86_host_phys_bits(void)
2914{
2915 uint32_t eax;
2916 uint32_t host_phys_bits;
2917
2918 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
2919 if (eax >= 0x80000008) {
2920 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
2921 /* Note: According to AMD doc 25481 rev 2.34 they have a field
2922 * at 23:16 that can specify a maximum physical address bits for
2923 * the guest that can override this value; but I've not seen
2924 * anything with that set.
2925 */
2926 host_phys_bits = eax & 0xff;
2927 } else {
2928 /* It's an odd 64 bit machine that doesn't have the leaf for
2929 * physical address bits; fall back to 36 that's most older
2930 * Intel.
2931 */
2932 host_phys_bits = 36;
2933 }
2934
2935 return host_phys_bits;
2936}
e48638fd
WH		 2937
2938#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2939 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2940 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2941#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2942 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2943 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2944static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2945{
14a10fc3 2946 CPUState *cs = CPU(dev);
2b6f294c
AF		 2947 X86CPU *cpu = X86_CPU(dev);
2948 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2949 CPUX86State *env = &cpu->env;
2b6f294c 2950 Error *local_err = NULL;
e48638fd 2951 static bool ht_warned;
dc15c051 2952 FeatureWord w;
b34d12d1 2953
104494ea
IM		 2954 if (xcc->kvm_required && !kvm_enabled()) {
2955 char *name = x86_cpu_class_get_model_name(xcc);
2956 error_setg(&local_err, "CPU model '%s' requires KVM", name);
2957 g_free(name);
2958 goto out;
2959 }
2960
d9c84f19 2961 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
9886e834
EH		 2962 error_setg(errp, "apic-id property was not initialized properly");
2963 return;
2964 }
2965
dc15c051
IM		 2966 /*TODO: cpu->host_features incorrectly overwrites features
2967 * set using "feat=on|off". Once we fix this, we can convert
2968 * plus_features & minus_features to global properties
2969 * inside x86_cpu_parse_featurestr() too.
2970 */
2971 if (cpu->host_features) {
2972 for (w = 0; w < FEATURE_WORDS; w++) {
2973 env->features[w] =
2974 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2975 }
2976 }
2977
2978 for (w = 0; w < FEATURE_WORDS; w++) {
2979 cpu->env.features[w] |= plus_features[w];
2980 cpu->env.features[w] &= ~minus_features[w];
2981 }
2982
0514ef2f 2983 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2984 env->cpuid_level = 7;
2985 }
7a059953 2986
9997cf7b
EH		 2987 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2988 error_setg(&local_err,
2989 kvm_enabled() ?
2990 "Host doesn't support requested features" :
2991 "TCG doesn't support requested features");
2992 goto out;
2993 }
2994
9b15cd9e
IM		 2995 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2996 * CPUID[1].EDX.
2997 */
e48638fd 2998 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 2999 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3000 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3001 & CPUID_EXT2_AMD_ALIASES);
3002 }
3003
11f6fee5
DDAG		 3004 /* For 64bit systems think about the number of physical bits to present.
3005 * ideally this should be the same as the host; anything other than matching
3006 * the host can cause incorrect guest behaviour.
3007 * QEMU used to pick the magic value of 40 bits that corresponds to
3008 * consumer AMD devices but nothing else.
3009 */
af45907a 3010 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3011 if (kvm_enabled()) {
11f6fee5
DDAG		 3012 uint32_t host_phys_bits = x86_host_phys_bits();
3013 static bool warned;
3014
3015 if (cpu->host_phys_bits) {
3016 /* The user asked for us to use the host physical bits */
3017 cpu->phys_bits = host_phys_bits;
3018 }
3019
3020 /* Print a warning if the user set it to a value that's not the
3021 * host value.
3022 */
3023 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3024 !warned) {
3025 error_report("Warning: Host physical bits (%u)"
3026 " does not match phys-bits property (%u)",
3027 host_phys_bits, cpu->phys_bits);
3028 warned = true;
3029 }
3030
3031 if (cpu->phys_bits &&
3032 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3033 cpu->phys_bits < 32)) {
af45907a
DDAG		 3034 error_setg(errp, "phys-bits should be between 32 and %u "
3035 " (but is %u)",
3036 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3037 return;
3038 }
3039 } else {
11f6fee5 3040 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3041 error_setg(errp, "TCG only supports phys-bits=%u",
3042 TCG_PHYS_ADDR_BITS);
3043 return;
3044 }
3045 }
11f6fee5
DDAG		 3046 /* 0 means it was not explicitly set by the user (or by machine
3047 * compat_props or by the host code above). In this case, the default
3048 * is the value used by TCG (40).
3049 */
3050 if (cpu->phys_bits == 0) {
3051 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3052 }
af45907a
DDAG		 3053 } else {
3054 /* For 32 bit systems don't use the user set value, but keep
3055 * phys_bits consistent with what we tell the guest.
3056 */
3057 if (cpu->phys_bits != 0) {
3058 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3059 return;
3060 }
fefb41bf 3061
af45907a
DDAG		 3062 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3063 cpu->phys_bits = 36;
3064 } else {
3065 cpu->phys_bits = 32;
3066 }
3067 }
42ecabaa
EH		 3068 cpu_exec_init(cs, &error_abort);
3069
57f2453a
EH		 3070 if (tcg_enabled()) {
3071 tcg_x86_init();
3072 }
3073
65dee380
IM		 3074#ifndef CONFIG_USER_ONLY
3075 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3076
0514ef2f 3077 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3078 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3079 if (local_err != NULL) {
4dc1f449 3080 goto out;
bdeec802
IM		 3081 }
3082 }
65dee380
IM		 3083#endif
3084
7a059953 3085 mce_init(cpu);
2001d0cd
PB		 3086
3087#ifndef CONFIG_USER_ONLY
3088 if (tcg_enabled()) {
56943e8c
PM		 3089 AddressSpace *newas = g_new(AddressSpace, 1);
3090
f809c605 3091 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3092 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3093
3094 /* Outer container... */
3095 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3096 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3097
3098 /* ... with two regions inside: normal system memory with low
3099 * priority, and...
3100 */
3101 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3102 get_system_memory(), 0, ~0ull);
3103 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3104 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3105 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3106 cs->num_ases = 1;
56943e8c 3107 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3108
3109 /* ... SMRAM with higher priority, linked from /machine/smram. */
3110 cpu->machine_done.notify = x86_cpu_machine_done;
3111 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3112 }
3113#endif
3114
14a10fc3 3115 qemu_init_vcpu(cs);
d3c64d6a 3116
e48638fd
WH		 3117 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3118 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3119 * based on inputs (sockets,cores,threads), it is still better to gives
3120 * users a warning.
3121 *
3122 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3123 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3124 */
3125 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3126 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3127 " -smp options properly.");
3128 ht_warned = true;
3129 }
3130
d3c64d6a
IM		 3131 x86_cpu_apic_realize(cpu, &local_err);
3132 if (local_err != NULL) {
3133 goto out;
3134 }
14a10fc3 3135 cpu_reset(cs);
2b6f294c 3136
4dc1f449 3137 xcc->parent_realize(dev, &local_err);
2001d0cd 3138
4dc1f449
IM		 3139out:
3140 if (local_err != NULL) {
3141 error_propagate(errp, local_err);
3142 return;
3143 }
7a059953
AF		 3144}
3145
38e5c119
EH		 3146typedef struct BitProperty {
3147 uint32_t *ptr;
3148 uint32_t mask;
3149} BitProperty;
3150
d7bce999
EB		 3151static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3152 void *opaque, Error **errp)
38e5c119
EH		 3153{
3154 BitProperty *fp = opaque;
3155 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3156 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3157}
3158
d7bce999
EB		 3159static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3160 void *opaque, Error **errp)
38e5c119
EH		 3161{
3162 DeviceState *dev = DEVICE(obj);
3163 BitProperty *fp = opaque;
3164 Error *local_err = NULL;
3165 bool value;
3166
3167 if (dev->realized) {
3168 qdev_prop_set_after_realize(dev, name, errp);
3169 return;
3170 }
3171
51e72bc1 3172 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3173 if (local_err) {
3174 error_propagate(errp, local_err);
3175 return;
3176 }
3177
3178 if (value) {
3179 *fp->ptr |= fp->mask;
3180 } else {
3181 *fp->ptr &= ~fp->mask;
3182 }
3183}
3184
3185static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3186 void *opaque)
3187{
3188 BitProperty *prop = opaque;
3189 g_free(prop);
3190}
3191
3192/* Register a boolean property to get/set a single bit in a uint32_t field.
3193 *
3194 * The same property name can be registered multiple times to make it affect
3195 * multiple bits in the same FeatureWord. In that case, the getter will return
3196 * true only if all bits are set.
3197 */
3198static void x86_cpu_register_bit_prop(X86CPU *cpu,
3199 const char *prop_name,
3200 uint32_t *field,
3201 int bitnr)
3202{
3203 BitProperty *fp;
3204 ObjectProperty *op;
3205 uint32_t mask = (1UL << bitnr);
3206
3207 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3208 if (op) {
3209 fp = op->opaque;
3210 assert(fp->ptr == field);
3211 fp->mask |= mask;
3212 } else {
3213 fp = g_new0(BitProperty, 1);
3214 fp->ptr = field;
3215 fp->mask = mask;
3216 object_property_add(OBJECT(cpu), prop_name, "bool",
3217 x86_cpu_get_bit_prop,
3218 x86_cpu_set_bit_prop,
3219 x86_cpu_release_bit_prop, fp, &error_abort);
3220 }
3221}
3222
3223static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3224 FeatureWord w,
3225 int bitnr)
3226{
3227 Object *obj = OBJECT(cpu);
3228 int i;
3229 char **names;
3230 FeatureWordInfo *fi = &feature_word_info[w];
3231
3232 if (!fi->feat_names) {
3233 return;
3234 }
3235 if (!fi->feat_names[bitnr]) {
3236 return;
3237 }
3238
3239 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3240
3241 feat2prop(names[0]);
3242 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3243
3244 for (i = 1; names[i]; i++) {
3245 feat2prop(names[i]);
d461a44c 3246 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3247 &error_abort);
3248 }
3249
3250 g_strfreev(names);
3251}
3252
de024815
AF		 3253static void x86_cpu_initfn(Object *obj)
3254{
55e5c285 3255 CPUState *cs = CPU(obj);
de024815 3256 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3257 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3258 CPUX86State *env = &cpu->env;
38e5c119 3259 FeatureWord w;
de024815 3260
c05efcb1 3261 cs->env_ptr = env;
71ad61d3
AF		 3262
3263 object_property_add(obj, "family", "int",
95b8519d 3264 x86_cpuid_version_get_family,
71ad61d3 3265 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3266 object_property_add(obj, "model", "int",
67e30c83 3267 x86_cpuid_version_get_model,
c5291a4f 3268 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3269 object_property_add(obj, "stepping", "int",
35112e41 3270 x86_cpuid_version_get_stepping,
036e2222 3271 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3272 object_property_add_str(obj, "vendor",
3273 x86_cpuid_get_vendor,
3274 x86_cpuid_set_vendor, NULL);
938d4c25 3275 object_property_add_str(obj, "model-id",
63e886eb 3276 x86_cpuid_get_model_id,
938d4c25 3277 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3278 object_property_add(obj, "tsc-frequency", "int",
3279 x86_cpuid_get_tsc_freq,
3280 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
31050930
IM		 3281 object_property_add(obj, "apic-id", "int",
3282 x86_cpuid_get_apic_id,
3283 x86_cpuid_set_apic_id, NULL, NULL, NULL);
8e8aba50
EH		 3284 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3285 x86_cpu_get_feature_words,
7e5292b5
EH		 3286 NULL, NULL, (void *)env->features, NULL);
3287 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3288 x86_cpu_get_feature_words,
3289 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3290
92067bf4 3291 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3292
9886e834
EH		 3293#ifndef CONFIG_USER_ONLY
3294 /* Any code creating new X86CPU objects have to set apic-id explicitly */
d9c84f19 3295 cpu->apic_id = UNASSIGNED_APIC_ID;
9886e834
EH		 3296#endif
3297
38e5c119
EH		 3298 for (w = 0; w < FEATURE_WORDS; w++) {
3299 int bitnr;
3300
3301 for (bitnr = 0; bitnr < 32; bitnr++) {
3302 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3303 }
3304 }
3305
d940ee9b 3306 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3307}
3308
997395d3
IM		 3309static int64_t x86_cpu_get_arch_id(CPUState *cs)
3310{
3311 X86CPU *cpu = X86_CPU(cs);
997395d3 3312
7e72a45c 3313 return cpu->apic_id;
997395d3
IM		 3314}
3315
444d5590
AF		 3316static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3317{
3318 X86CPU *cpu = X86_CPU(cs);
3319
3320 return cpu->env.cr[0] & CR0_PG_MASK;
3321}
3322
f45748f1
AF		 3323static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3324{
3325 X86CPU *cpu = X86_CPU(cs);
3326
3327 cpu->env.eip = value;
3328}
3329
bdf7ae5b
AF		 3330static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3331{
3332 X86CPU *cpu = X86_CPU(cs);
3333
3334 cpu->env.eip = tb->pc - tb->cs_base;
3335}
3336
8c2e1b00
AF		 3337static bool x86_cpu_has_work(CPUState *cs)
3338{
3339 X86CPU *cpu = X86_CPU(cs);
3340 CPUX86State *env = &cpu->env;
3341
6220e900
PD		 3342 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3343 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3344 (env->eflags & IF_MASK)) ||
3345 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3346 CPU_INTERRUPT_INIT |
3347 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3348 CPU_INTERRUPT_MCE)) ||
3349 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3350 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3351}
3352
9337e3b6
EH		 3353static Property x86_cpu_properties[] = {
3354 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3355 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3356 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3357 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3358 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3359 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3360 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3361 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3362 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3363 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3364 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3365 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3366 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3367 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3368 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3369 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3370 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
b9472b76
EH		 3371 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3372 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3373 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
1c4a55db 3374 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3375 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3376 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
9337e3b6
EH		 3377 DEFINE_PROP_END_OF_LIST()
3378};
3379
5fd2087a
AF		 3380static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3381{
3382 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3383 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3384 DeviceClass *dc = DEVICE_CLASS(oc);
3385
3386 xcc->parent_realize = dc->realize;
3387 dc->realize = x86_cpu_realizefn;
9337e3b6 3388 dc->props = x86_cpu_properties;
5fd2087a
AF		 3389
3390 xcc->parent_reset = cc->reset;
3391 cc->reset = x86_cpu_reset;
91b1df8c 3392 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3393
500050d1 3394 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3395 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3396 cc->has_work = x86_cpu_has_work;
97a8ea5a 3397 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3398 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3399 cc->dump_state = x86_cpu_dump_state;
f45748f1 3400 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3401 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3402 cc->gdb_read_register = x86_cpu_gdb_read_register;
3403 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3404 cc->get_arch_id = x86_cpu_get_arch_id;
3405 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3406#ifdef CONFIG_USER_ONLY
3407 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3408#else
a23bbfda 3409 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3410 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3411 cc->write_elf64_note = x86_cpu_write_elf64_note;
3412 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3413 cc->write_elf32_note = x86_cpu_write_elf32_note;
3414 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3415 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3416#endif
a0e372f0 3417 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3418#ifndef CONFIG_USER_ONLY
3419 cc->debug_excp_handler = breakpoint_handler;
3420#endif
374e0cd4
RH		 3421 cc->cpu_exec_enter = x86_cpu_exec_enter;
3422 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27
MA		 3423
3424 /*
3425 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3426 * object in cpus -> dangling pointer after final object_unref().
3427 */
3428 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3429}
3430
3431static const TypeInfo x86_cpu_type_info = {
3432 .name = TYPE_X86_CPU,
3433 .parent = TYPE_CPU,
3434 .instance_size = sizeof(X86CPU),
de024815 3435 .instance_init = x86_cpu_initfn,
d940ee9b 3436 .abstract = true,
5fd2087a
AF		 3437 .class_size = sizeof(X86CPUClass),
3438 .class_init = x86_cpu_common_class_init,
3439};
3440
3441static void x86_cpu_register_types(void)
3442{
d940ee9b
EH		 3443 int i;
3444
5fd2087a 3445 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3446 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3447 x86_register_cpudef_type(&builtin_x86_defs[i]);
3448 }
3449#ifdef CONFIG_KVM
3450 type_register_static(&host_x86_cpu_type_info);
3451#endif
5fd2087a
AF		 3452}
3453
3454type_init(x86_cpu_register_types)
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