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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2016-09-19' into staging
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
1ef26b1f 19#include "qemu/osdep.h"
f348b6d1 20#include "qemu/cutils.h"
c6dc6f63
AP		 21
22#include "cpu.h"
63c91552 23#include "exec/exec-all.h"
9c17d615 24#include "sysemu/kvm.h"
8932cfdf 25#include "sysemu/cpus.h"
50a2c6e5 26#include "kvm_i386.h"
c6dc6f63 27
d49b6836 28#include "qemu/error-report.h"
1de7afc9
PB		 29#include "qemu/option.h"
30#include "qemu/config-file.h"
7b1b5d19 31#include "qapi/qmp/qerror.h"
c6dc6f63 32
8e8aba50
EH		 33#include "qapi-types.h"
34#include "qapi-visit.h"
7b1b5d19 35#include "qapi/visitor.h"
9c17d615 36#include "sysemu/arch_init.h"
71ad61d3 37
b834b508 38#if defined(CONFIG_KVM)
ef8621b1 39#include <linux/kvm_para.h>
b834b508 40#endif
65dee380 41
9c17d615 42#include "sysemu/sysemu.h"
53a89e26 43#include "hw/qdev-properties.h"
5232d00a 44#include "hw/i386/topology.h"
bdeec802 45#ifndef CONFIG_USER_ONLY
2001d0cd 46#include "exec/address-spaces.h"
741da0d3 47#include "hw/hw.h"
0d09e41a 48#include "hw/xen/xen.h"
0d09e41a 49#include "hw/i386/apic_internal.h"
bdeec802
IM		 50#endif
51
5e891bf8
EH		 52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
14c985cf 60#define CPUID_2_L3_16MB_16WAY_64B 0x4d
5e891bf8
EH		 61
62
63/* CPUID Leaf 4 constants: */
64
65/* EAX: */
66#define CPUID_4_TYPE_DCACHE 1
67#define CPUID_4_TYPE_ICACHE 2
68#define CPUID_4_TYPE_UNIFIED 3
69
70#define CPUID_4_LEVEL(l) ((l) << 5)
71
72#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73#define CPUID_4_FULLY_ASSOC (1 << 9)
74
75/* EDX: */
76#define CPUID_4_NO_INVD_SHARING (1 << 0)
77#define CPUID_4_INCLUSIVE (1 << 1)
78#define CPUID_4_COMPLEX_IDX (1 << 2)
79
80#define ASSOC_FULL 0xFF
81
82/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97/* Definitions of the hardcoded cache entries we expose: */
98
99/* L1 data cache: */
100#define L1D_LINE_SIZE 64
101#define L1D_ASSOCIATIVITY 8
102#define L1D_SETS 64
103#define L1D_PARTITIONS 1
104/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107#define L1D_LINES_PER_TAG 1
108#define L1D_SIZE_KB_AMD 64
109#define L1D_ASSOCIATIVITY_AMD 2
110
111/* L1 instruction cache: */
112#define L1I_LINE_SIZE 64
113#define L1I_ASSOCIATIVITY 8
114#define L1I_SETS 64
115#define L1I_PARTITIONS 1
116/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119#define L1I_LINES_PER_TAG 1
120#define L1I_SIZE_KB_AMD 64
121#define L1I_ASSOCIATIVITY_AMD 2
122
123/* Level 2 unified cache: */
124#define L2_LINE_SIZE 64
125#define L2_ASSOCIATIVITY 16
126#define L2_SETS 4096
127#define L2_PARTITIONS 1
128/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132#define L2_LINES_PER_TAG 1
133#define L2_SIZE_KB_AMD 512
134
14c985cf 135/* Level 3 unified cache: */
5e891bf8
EH		 136#define L3_SIZE_KB 0 /* disabled */
137#define L3_ASSOCIATIVITY 0 /* disabled */
138#define L3_LINES_PER_TAG 0 /* disabled */
139#define L3_LINE_SIZE 0 /* disabled */
14c985cf
LM		 140#define L3_N_LINE_SIZE 64
141#define L3_N_ASSOCIATIVITY 16
142#define L3_N_SETS 16384
143#define L3_N_PARTITIONS 1
144#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145#define L3_N_LINES_PER_TAG 1
146#define L3_N_SIZE_KB_AMD 16384
5e891bf8
EH		 147
148/* TLB definitions: */
149
150#define L1_DTLB_2M_ASSOC 1
151#define L1_DTLB_2M_ENTRIES 255
152#define L1_DTLB_4K_ASSOC 1
153#define L1_DTLB_4K_ENTRIES 255
154
155#define L1_ITLB_2M_ASSOC 1
156#define L1_ITLB_2M_ENTRIES 255
157#define L1_ITLB_4K_ASSOC 1
158#define L1_ITLB_4K_ENTRIES 255
159
160#define L2_DTLB_2M_ASSOC 0 /* disabled */
161#define L2_DTLB_2M_ENTRIES 0 /* disabled */
162#define L2_DTLB_4K_ASSOC 4
163#define L2_DTLB_4K_ENTRIES 512
164
165#define L2_ITLB_2M_ASSOC 0 /* disabled */
166#define L2_ITLB_2M_ENTRIES 0 /* disabled */
167#define L2_ITLB_4K_ASSOC 4
168#define L2_ITLB_4K_ENTRIES 512
169
170
171
99b88a17
IM		 172static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174{
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182}
183
c6dc6f63
AP		 184/* feature flags taken from "Intel Processor Identification and the CPUID
185 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
186 * between feature naming conventions, aliases may be added.
187 */
188static const char *feature_name[] = {
189 "fpu", "vme", "de", "pse",
190 "tsc", "msr", "pae", "mce",
191 "cx8", "apic", NULL, "sep",
192 "mtrr", "pge", "mca", "cmov",
193 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
194 NULL, "ds" /* Intel dts */, "acpi", "mmx",
195 "fxsr", "sse", "sse2", "ss",
196 "ht" /* Intel htt */, "tm", "ia64", "pbe",
197};
198static const char *ext_feature_name[] = {
f370be3c 199 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 200 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 201 "tm2", "ssse3", "cid", NULL,
e117f772 202 "fma", "cx16", "xtpr", "pdcm",
434acb81 203 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 204 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 205 "tsc-deadline", "aes", "xsave", "osxsave",
c8acc380 206 "avx", "f16c", "rdrand", "hypervisor",
c6dc6f63 207};
3b671a40
EH		 208/* Feature names that are already defined on feature_name[] but are set on
209 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
210 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
211 * if and only if CPU vendor is AMD.
212 */
c6dc6f63 213static const char *ext2_feature_name[] = {
3b671a40
EH		 214 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
215 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
216 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
217 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
218 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
219 "nx|xd", NULL, "mmxext", NULL /* mmx */,
220 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
01f590d5 221 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 222};
223static const char *ext3_feature_name[] = {
224 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
225 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 226 "3dnowprefetch", "osvw", "ibs", "xop",
c8acc380
AP		 227 "skinit", "wdt", NULL, "lwp",
228 "fma4", "tce", NULL, "nodeid_msr",
229 NULL, "tbm", "topoext", "perfctr_core",
230 "perfctr_nb", NULL, NULL, NULL,
c6dc6f63
AP		 231 NULL, NULL, NULL, NULL,
232};
233
89e49c8b
EH		 234static const char *ext4_feature_name[] = {
235 NULL, NULL, "xstore", "xstore-en",
236 NULL, NULL, "xcrypt", "xcrypt-en",
237 "ace2", "ace2-en", "phe", "phe-en",
238 "pmm", "pmm-en", NULL, NULL,
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243};
244
c6dc6f63 245static const char *kvm_feature_name[] = {
c3d39807 246 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
f010bc64 247 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
c3d39807
DS		 248 NULL, NULL, NULL, NULL,
249 NULL, NULL, NULL, NULL,
250 NULL, NULL, NULL, NULL,
251 NULL, NULL, NULL, NULL,
8248c36a 252 "kvmclock-stable-bit", NULL, NULL, NULL,
c3d39807 253 NULL, NULL, NULL, NULL,
c6dc6f63
AP		 254};
255
c35bd19a
EY		 256static const char *hyperv_priv_feature_name[] = {
257 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
258 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
259 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
260 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
261 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
262 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
263 NULL, NULL, NULL, NULL,
264 NULL, NULL, NULL, NULL,
265 NULL, NULL, NULL, NULL,
266 NULL, NULL, NULL, NULL,
267 NULL, NULL, NULL, NULL,
268};
269
270static const char *hyperv_ident_feature_name[] = {
271 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
272 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
273 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
274 NULL /* hv_create_port */, NULL /* hv_connect_port */,
275 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
276 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
277 NULL, NULL,
278 NULL, NULL, NULL, NULL,
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282};
283
284static const char *hyperv_misc_feature_name[] = {
285 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
286 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
287 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
288 NULL, NULL,
289 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
290 NULL, NULL, NULL, NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295};
296
296acb64
JR		 297static const char *svm_feature_name[] = {
298 "npt", "lbrv", "svm_lock", "nrip_save",
299 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
300 NULL, NULL, "pause_filter", NULL,
301 "pfthreshold", NULL, NULL, NULL,
302 NULL, NULL, NULL, NULL,
303 NULL, NULL, NULL, NULL,
304 NULL, NULL, NULL, NULL,
305 NULL, NULL, NULL, NULL,
306};
307
a9321a4d 308static const char *cpuid_7_0_ebx_feature_name[] = {
cc728d14
LK		 309 "fsgsbase", "tsc_adjust", NULL, "bmi1",
310 "hle", "avx2", NULL, "smep",
311 "bmi2", "erms", "invpcid", "rtm",
312 NULL, NULL, "mpx", NULL,
313 "avx512f", "avx512dq", "rdseed", "adx",
314 "smap", "avx512ifma", "pcommit", "clflushopt",
315 "clwb", NULL, "avx512pf", "avx512er",
316 "avx512cd", NULL, "avx512bw", "avx512vl",
a9321a4d
PA		 317};
318
f74eefe0 319static const char *cpuid_7_0_ecx_feature_name[] = {
cc728d14 320 NULL, "avx512vbmi", "umip", "pku",
f74eefe0
HH		 321 "ospke", NULL, NULL, NULL,
322 NULL, NULL, NULL, NULL,
323 NULL, NULL, NULL, NULL,
324 NULL, NULL, NULL, NULL,
c2f193b5 325 NULL, NULL, "rdpid", NULL,
f74eefe0
HH		 326 NULL, NULL, NULL, NULL,
327 NULL, NULL, NULL, NULL,
328};
329
303752a9
MT		 330static const char *cpuid_apm_edx_feature_name[] = {
331 NULL, NULL, NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 "invtsc", NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 NULL, NULL, NULL, NULL,
339};
340
0bb0b2d2
PB		 341static const char *cpuid_xsave_feature_name[] = {
342 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
343 NULL, NULL, NULL, NULL,
344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350};
351
28b8e4d0
JK		 352static const char *cpuid_6_feature_name[] = {
353 NULL, NULL, "arat", NULL,
354 NULL, NULL, NULL, NULL,
355 NULL, NULL, NULL, NULL,
356 NULL, NULL, NULL, NULL,
357 NULL, NULL, NULL, NULL,
358 NULL, NULL, NULL, NULL,
359 NULL, NULL, NULL, NULL,
360 NULL, NULL, NULL, NULL,
361};
362
621626ce
EH		 363#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
364#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
365 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
366#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
367 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
368 CPUID_PSE36 | CPUID_FXSR)
369#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
370#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
371 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
372 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
373 CPUID_PAE | CPUID_SEP | CPUID_APIC)
374
375#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
376 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
377 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
378 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 379 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 380 /* partly implemented:
381 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
382 /* missing:
383 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
384#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
385 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
386 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 387 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 388 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
389 /* missing:
390 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
391 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
392 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 393 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
394 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 395
396#ifdef TARGET_X86_64
397#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
398#else
399#define TCG_EXT2_X86_64_FEATURES 0
400#endif
401
402#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
403 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
404 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
405 TCG_EXT2_X86_64_FEATURES)
406#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
407 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
408#define TCG_EXT4_FEATURES 0
409#define TCG_SVM_FEATURES 0
410#define TCG_KVM_FEATURES 0
411#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 412 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
413 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 414 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
415 CPUID_7_0_EBX_ERMS)
621626ce 416 /* missing:
07929f2a 417 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 418 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 419 CPUID_7_0_EBX_RDSEED */
0f70ed47 420#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
303752a9 421#define TCG_APM_FEATURES 0
28b8e4d0 422#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 423#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
424 /* missing:
425 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 426
5ef57876
EH		 427typedef struct FeatureWordInfo {
428 const char **feat_names;
04d104b6
EH		 429 uint32_t cpuid_eax; /* Input EAX for CPUID */
430 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
431 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
432 int cpuid_reg; /* output register (R_* constant) */
37ce3522 433 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 434 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
5ef57876
EH		 435} FeatureWordInfo;
436
437static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0
EH		 438 [FEAT_1_EDX] = {
439 .feat_names = feature_name,
440 .cpuid_eax = 1, .cpuid_reg = R_EDX,
37ce3522 441 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 442 },
443 [FEAT_1_ECX] = {
444 .feat_names = ext_feature_name,
445 .cpuid_eax = 1, .cpuid_reg = R_ECX,
37ce3522 446 .tcg_features = TCG_EXT_FEATURES,
bffd67b0
EH		 447 },
448 [FEAT_8000_0001_EDX] = {
449 .feat_names = ext2_feature_name,
450 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
37ce3522 451 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 452 },
453 [FEAT_8000_0001_ECX] = {
454 .feat_names = ext3_feature_name,
455 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
37ce3522 456 .tcg_features = TCG_EXT3_FEATURES,
bffd67b0 457 },
89e49c8b
EH		 458 [FEAT_C000_0001_EDX] = {
459 .feat_names = ext4_feature_name,
460 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
37ce3522 461 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 462 },
bffd67b0
EH		 463 [FEAT_KVM] = {
464 .feat_names = kvm_feature_name,
465 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
37ce3522 466 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 467 },
c35bd19a
EY		 468 [FEAT_HYPERV_EAX] = {
469 .feat_names = hyperv_priv_feature_name,
470 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
471 },
472 [FEAT_HYPERV_EBX] = {
473 .feat_names = hyperv_ident_feature_name,
474 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
475 },
476 [FEAT_HYPERV_EDX] = {
477 .feat_names = hyperv_misc_feature_name,
478 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
479 },
bffd67b0
EH		 480 [FEAT_SVM] = {
481 .feat_names = svm_feature_name,
482 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
37ce3522 483 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 484 },
485 [FEAT_7_0_EBX] = {
486 .feat_names = cpuid_7_0_ebx_feature_name,
04d104b6
EH		 487 .cpuid_eax = 7,
488 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
489 .cpuid_reg = R_EBX,
37ce3522 490 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 491 },
f74eefe0
HH		 492 [FEAT_7_0_ECX] = {
493 .feat_names = cpuid_7_0_ecx_feature_name,
494 .cpuid_eax = 7,
495 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
496 .cpuid_reg = R_ECX,
497 .tcg_features = TCG_7_0_ECX_FEATURES,
498 },
303752a9
MT		 499 [FEAT_8000_0007_EDX] = {
500 .feat_names = cpuid_apm_edx_feature_name,
501 .cpuid_eax = 0x80000007,
502 .cpuid_reg = R_EDX,
503 .tcg_features = TCG_APM_FEATURES,
504 .unmigratable_flags = CPUID_APM_INVTSC,
505 },
0bb0b2d2
PB		 506 [FEAT_XSAVE] = {
507 .feat_names = cpuid_xsave_feature_name,
508 .cpuid_eax = 0xd,
509 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
510 .cpuid_reg = R_EAX,
c9cfe8f9 511 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 512 },
28b8e4d0
JK		 513 [FEAT_6_EAX] = {
514 .feat_names = cpuid_6_feature_name,
515 .cpuid_eax = 6, .cpuid_reg = R_EAX,
516 .tcg_features = TCG_6_EAX_FEATURES,
517 },
5ef57876
EH		 518};
519
8e8aba50
EH		 520typedef struct X86RegisterInfo32 {
521 /* Name of register */
522 const char *name;
523 /* QAPI enum value register */
524 X86CPURegister32 qapi_enum;
525} X86RegisterInfo32;
526
527#define REGISTER(reg) \
5d371f41 528 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 529static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 530 REGISTER(EAX),
531 REGISTER(ECX),
532 REGISTER(EDX),
533 REGISTER(EBX),
534 REGISTER(ESP),
535 REGISTER(EBP),
536 REGISTER(ESI),
537 REGISTER(EDI),
538};
539#undef REGISTER
540
f4f1110e 541const ExtSaveArea x86_ext_save_areas[] = {
cfc3b074
PB		 542 [XSTATE_YMM_BIT] =
543 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 544 .offset = offsetof(X86XSaveArea, avx_state),
545 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 546 [XSTATE_BNDREGS_BIT] =
547 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 548 .offset = offsetof(X86XSaveArea, bndreg_state),
549 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 550 [XSTATE_BNDCSR_BIT] =
551 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 552 .offset = offsetof(X86XSaveArea, bndcsr_state),
553 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 554 [XSTATE_OPMASK_BIT] =
555 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 556 .offset = offsetof(X86XSaveArea, opmask_state),
557 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 558 [XSTATE_ZMM_Hi256_BIT] =
559 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 560 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
561 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 562 [XSTATE_Hi16_ZMM_BIT] =
563 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 564 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
565 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 566 [XSTATE_PKRU_BIT] =
567 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 568 .offset = offsetof(X86XSaveArea, pkru_state),
569 .size = sizeof(XSavePKRU) },
2560f19f 570};
8e8aba50 571
8b4beddc
EH		 572const char *get_register_name_32(unsigned int reg)
573{
31ccdde2 574 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 575 return NULL;
576 }
8e8aba50 577 return x86_reg_info_32[reg].name;
8b4beddc
EH		 578}
579
84f1b92f
EH		 580/*
581 * Returns the set of feature flags that are supported and migratable by
582 * QEMU, for a given FeatureWord.
583 */
584static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
585{
586 FeatureWordInfo *wi = &feature_word_info[w];
587 uint32_t r = 0;
588 int i;
589
590 for (i = 0; i < 32; i++) {
591 uint32_t f = 1U << i;
592 /* If the feature name is unknown, it is not supported by QEMU yet */
593 if (!wi->feat_names[i]) {
594 continue;
595 }
596 /* Skip features known to QEMU, but explicitly marked as unmigratable */
597 if (wi->unmigratable_flags & f) {
598 continue;
599 }
600 r |= f;
601 }
602 return r;
603}
604
bb44e0d1
JK		 605void host_cpuid(uint32_t function, uint32_t count,
606 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 607{
a1fd24af
AL		 608 uint32_t vec[4];
609
610#ifdef __x86_64__
611 asm volatile("cpuid"
612 : "=a"(vec[0]), "=b"(vec[1]),
613 "=c"(vec[2]), "=d"(vec[3])
614 : "0"(function), "c"(count) : "cc");
c1f41226 615#elif defined(__i386__)
a1fd24af
AL		 616 asm volatile("pusha \n\t"
617 "cpuid \n\t"
618 "mov %%eax, 0(%2) \n\t"
619 "mov %%ebx, 4(%2) \n\t"
620 "mov %%ecx, 8(%2) \n\t"
621 "mov %%edx, 12(%2) \n\t"
622 "popa"
623 : : "a"(function), "c"(count), "S"(vec)
624 : "memory", "cc");
c1f41226
EH		 625#else
626 abort();
a1fd24af
AL		 627#endif
628
bdde476a 629 if (eax)
a1fd24af 630 *eax = vec[0];
bdde476a 631 if (ebx)
a1fd24af 632 *ebx = vec[1];
bdde476a 633 if (ecx)
a1fd24af 634 *ecx = vec[2];
bdde476a 635 if (edx)
a1fd24af 636 *edx = vec[3];
bdde476a 637}
c6dc6f63
AP		 638
639#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
640
641/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
642 * a substring. ex if !NULL points to the first char after a substring,
643 * otherwise the string is assumed to sized by a terminating nul.
644 * Return lexical ordering of *s1:*s2.
645 */
8f9d989c
CF		 646static int sstrcmp(const char *s1, const char *e1,
647 const char *s2, const char *e2)
c6dc6f63
AP		 648{
649 for (;;) {
650 if (!*s1 || !*s2 || *s1 != *s2)
651 return (*s1 - *s2);
652 ++s1, ++s2;
653 if (s1 == e1 && s2 == e2)
654 return (0);
655 else if (s1 == e1)
656 return (*s2);
657 else if (s2 == e2)
658 return (*s1);
659 }
660}
661
662/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
663 * '|' delimited (possibly empty) strings in which case search for a match
664 * within the alternatives proceeds left to right. Return 0 for success,
665 * non-zero otherwise.
666 */
667static int altcmp(const char *s, const char *e, const char *altstr)
668{
669 const char *p, *q;
670
671 for (q = p = altstr; ; ) {
672 while (*p && *p != '|')
673 ++p;
674 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
675 return (0);
676 if (!*p)
677 return (1);
678 else
679 q = ++p;
680 }
681}
682
683/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 684 * *pval and return true, otherwise return false
c6dc6f63 685 */
e41e0fc6
JK		 686static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
687 const char **featureset)
c6dc6f63
AP		 688{
689 uint32_t mask;
690 const char **ppc;
e41e0fc6 691 bool found = false;
c6dc6f63 692
e41e0fc6 693 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 694 if (*ppc && !altcmp(s, e, *ppc)) {
695 *pval |= mask;
e41e0fc6 696 found = true;
c6dc6f63 697 }
e41e0fc6
JK		 698 }
699 return found;
c6dc6f63
AP		 700}
701
5ef57876 702static void add_flagname_to_bitmaps(const char *flagname,
c00c94ab
EH		 703 FeatureWordArray words,
704 Error **errp)
c6dc6f63 705{
5ef57876
EH		 706 FeatureWord w;
707 for (w = 0; w < FEATURE_WORDS; w++) {
708 FeatureWordInfo *wi = &feature_word_info[w];
709 if (wi->feat_names &&
710 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
711 break;
712 }
713 }
714 if (w == FEATURE_WORDS) {
c00c94ab 715 error_setg(errp, "CPU feature %s not found", flagname);
5ef57876 716 }
c6dc6f63
AP		 717}
718
d940ee9b
EH		 719/* CPU class name definitions: */
720
721#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
722#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
723
724/* Return type name for a given CPU model name
725 * Caller is responsible for freeing the returned string.
726 */
727static char *x86_cpu_type_name(const char *model_name)
728{
729 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
730}
731
500050d1
AF		 732static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
733{
d940ee9b
EH		 734 ObjectClass *oc;
735 char *typename;
736
500050d1
AF		 737 if (cpu_model == NULL) {
738 return NULL;
739 }
740
d940ee9b
EH		 741 typename = x86_cpu_type_name(cpu_model);
742 oc = object_class_by_name(typename);
743 g_free(typename);
744 return oc;
500050d1
AF		 745}
746
104494ea
IM		 747static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
748{
749 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
750 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
751 return g_strndup(class_name,
752 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
753}
754
d940ee9b 755struct X86CPUDefinition {
c6dc6f63
AP		 756 const char *name;
757 uint32_t level;
90e4b0c3
EH		 758 uint32_t xlevel;
759 uint32_t xlevel2;
99b88a17
IM		 760 /* vendor is zero-terminated, 12 character ASCII string */
761 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 762 int family;
763 int model;
764 int stepping;
0514ef2f 765 FeatureWordArray features;
c6dc6f63 766 char model_id[48];
d940ee9b 767};
c6dc6f63 768
9576de75 769static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 770 {
771 .name = "qemu64",
3046bb5d 772 .level = 0xd,
99b88a17 773 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 774 .family = 6,
f8e6a11a 775 .model = 6,
c6dc6f63 776 .stepping = 3,
0514ef2f 777 .features[FEAT_1_EDX] =
27861ecc 778 PPRO_FEATURES |
c6dc6f63 779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 780 CPUID_PSE36,
0514ef2f 781 .features[FEAT_1_ECX] =
6aa91e4a 782 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 783 .features[FEAT_8000_0001_EDX] =
c6dc6f63 784 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 785 .features[FEAT_8000_0001_ECX] =
71195672 786 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 787 .xlevel = 0x8000000A,
9cf2cc3d 788 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 789 },
790 {
791 .name = "phenom",
792 .level = 5,
99b88a17 793 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 794 .family = 16,
795 .model = 2,
796 .stepping = 3,
b9fc20bc 797 /* Missing: CPUID_HT */
0514ef2f 798 .features[FEAT_1_EDX] =
27861ecc 799 PPRO_FEATURES |
c6dc6f63 800 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 801 CPUID_PSE36 | CPUID_VME,
0514ef2f 802 .features[FEAT_1_ECX] =
27861ecc 803 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 804 CPUID_EXT_POPCNT,
0514ef2f 805 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 806 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
807 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 808 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 809 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
810 CPUID_EXT3_CR8LEG,
811 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
812 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 813 .features[FEAT_8000_0001_ECX] =
27861ecc 814 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 815 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 816 /* Missing: CPUID_SVM_LBRV */
0514ef2f 817 .features[FEAT_SVM] =
b9fc20bc 818 CPUID_SVM_NPT,
c6dc6f63
AP		 819 .xlevel = 0x8000001A,
820 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
821 },
822 {
823 .name = "core2duo",
824 .level = 10,
99b88a17 825 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 826 .family = 6,
827 .model = 15,
828 .stepping = 11,
b9fc20bc 829 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 830 .features[FEAT_1_EDX] =
27861ecc 831 PPRO_FEATURES |
c6dc6f63 832 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 833 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
834 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 835 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 836 .features[FEAT_1_ECX] =
27861ecc 837 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 838 CPUID_EXT_CX16,
0514ef2f 839 .features[FEAT_8000_0001_EDX] =
27861ecc 840 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 841 .features[FEAT_8000_0001_ECX] =
27861ecc 842 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 843 .xlevel = 0x80000008,
844 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
845 },
846 {
847 .name = "kvm64",
3046bb5d 848 .level = 0xd,
99b88a17 849 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 850 .family = 15,
851 .model = 6,
852 .stepping = 1,
b3a4f0b1 853 /* Missing: CPUID_HT */
0514ef2f 854 .features[FEAT_1_EDX] =
b3a4f0b1 855 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 856 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
857 CPUID_PSE36,
858 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 859 .features[FEAT_1_ECX] =
27861ecc 860 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 861 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 862 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 863 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
864 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
865 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
866 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
867 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 868 .features[FEAT_8000_0001_ECX] =
27861ecc 869 0,
c6dc6f63
AP		 870 .xlevel = 0x80000008,
871 .model_id = "Common KVM processor"
872 },
c6dc6f63
AP		 873 {
874 .name = "qemu32",
875 .level = 4,
99b88a17 876 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 877 .family = 6,
f8e6a11a 878 .model = 6,
c6dc6f63 879 .stepping = 3,
0514ef2f 880 .features[FEAT_1_EDX] =
27861ecc 881 PPRO_FEATURES,
0514ef2f 882 .features[FEAT_1_ECX] =
6aa91e4a 883 CPUID_EXT_SSE3,
58012d66 884 .xlevel = 0x80000004,
9cf2cc3d 885 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 886 },
eafaf1e5
AP		 887 {
888 .name = "kvm32",
889 .level = 5,
99b88a17 890 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 891 .family = 15,
892 .model = 6,
893 .stepping = 1,
0514ef2f 894 .features[FEAT_1_EDX] =
b3a4f0b1 895 PPRO_FEATURES | CPUID_VME |
eafaf1e5 896 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 897 .features[FEAT_1_ECX] =
27861ecc 898 CPUID_EXT_SSE3,
0514ef2f 899 .features[FEAT_8000_0001_ECX] =
27861ecc 900 0,
eafaf1e5
AP		 901 .xlevel = 0x80000008,
902 .model_id = "Common 32-bit KVM processor"
903 },
c6dc6f63
AP		 904 {
905 .name = "coreduo",
906 .level = 10,
99b88a17 907 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 908 .family = 6,
909 .model = 14,
910 .stepping = 8,
b9fc20bc 911 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 912 .features[FEAT_1_EDX] =
27861ecc 913 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 914 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
915 CPUID_SS,
916 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 917 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 918 .features[FEAT_1_ECX] =
e93abc14 919 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 920 .features[FEAT_8000_0001_EDX] =
27861ecc 921 CPUID_EXT2_NX,
c6dc6f63
AP		 922 .xlevel = 0x80000008,
923 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
924 },
925 {
926 .name = "486",
58012d66 927 .level = 1,
99b88a17 928 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 929 .family = 4,
b2a856d9 930 .model = 8,
c6dc6f63 931 .stepping = 0,
0514ef2f 932 .features[FEAT_1_EDX] =
27861ecc 933 I486_FEATURES,
c6dc6f63
AP		 934 .xlevel = 0,
935 },
936 {
937 .name = "pentium",
938 .level = 1,
99b88a17 939 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 940 .family = 5,
941 .model = 4,
942 .stepping = 3,
0514ef2f 943 .features[FEAT_1_EDX] =
27861ecc 944 PENTIUM_FEATURES,
c6dc6f63
AP		 945 .xlevel = 0,
946 },
947 {
948 .name = "pentium2",
949 .level = 2,
99b88a17 950 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 951 .family = 6,
952 .model = 5,
953 .stepping = 2,
0514ef2f 954 .features[FEAT_1_EDX] =
27861ecc 955 PENTIUM2_FEATURES,
c6dc6f63
AP		 956 .xlevel = 0,
957 },
958 {
959 .name = "pentium3",
3046bb5d 960 .level = 3,
99b88a17 961 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 962 .family = 6,
963 .model = 7,
964 .stepping = 3,
0514ef2f 965 .features[FEAT_1_EDX] =
27861ecc 966 PENTIUM3_FEATURES,
c6dc6f63
AP		 967 .xlevel = 0,
968 },
969 {
970 .name = "athlon",
971 .level = 2,
99b88a17 972 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 973 .family = 6,
974 .model = 2,
975 .stepping = 3,
0514ef2f 976 .features[FEAT_1_EDX] =
27861ecc 977 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 978 CPUID_MCA,
0514ef2f 979 .features[FEAT_8000_0001_EDX] =
60032ac0 980 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 981 .xlevel = 0x80000008,
9cf2cc3d 982 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 983 },
984 {
985 .name = "n270",
3046bb5d 986 .level = 10,
99b88a17 987 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 988 .family = 6,
989 .model = 28,
990 .stepping = 2,
b9fc20bc 991 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 992 .features[FEAT_1_EDX] =
27861ecc 993 PPRO_FEATURES |
b9fc20bc
EH		 994 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
995 CPUID_ACPI | CPUID_SS,
c6dc6f63 996 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 997 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
998 * CPUID_EXT_XTPR */
0514ef2f 999 .features[FEAT_1_ECX] =
27861ecc 1000 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1001 CPUID_EXT_MOVBE,
0514ef2f 1002 .features[FEAT_8000_0001_EDX] =
60032ac0 1003 CPUID_EXT2_NX,
0514ef2f 1004 .features[FEAT_8000_0001_ECX] =
27861ecc 1005 CPUID_EXT3_LAHF_LM,
3046bb5d 1006 .xlevel = 0x80000008,
c6dc6f63
AP		 1007 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1008 },
3eca4642
EH		 1009 {
1010 .name = "Conroe",
3046bb5d 1011 .level = 10,
99b88a17 1012 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1013 .family = 6,
ffce9ebb 1014 .model = 15,
3eca4642 1015 .stepping = 3,
0514ef2f 1016 .features[FEAT_1_EDX] =
b3a4f0b1 1017 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1018 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1019 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1020 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1021 CPUID_DE | CPUID_FP87,
0514ef2f 1022 .features[FEAT_1_ECX] =
27861ecc 1023 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1024 .features[FEAT_8000_0001_EDX] =
27861ecc 1025 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1026 .features[FEAT_8000_0001_ECX] =
27861ecc 1027 CPUID_EXT3_LAHF_LM,
3046bb5d 1028 .xlevel = 0x80000008,
3eca4642
EH		 1029 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1030 },
1031 {
1032 .name = "Penryn",
3046bb5d 1033 .level = 10,
99b88a17 1034 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1035 .family = 6,
ffce9ebb 1036 .model = 23,
3eca4642 1037 .stepping = 3,
0514ef2f 1038 .features[FEAT_1_EDX] =
b3a4f0b1 1039 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1040 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1041 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1042 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1043 CPUID_DE | CPUID_FP87,
0514ef2f 1044 .features[FEAT_1_ECX] =
27861ecc 1045 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1046 CPUID_EXT_SSE3,
0514ef2f 1047 .features[FEAT_8000_0001_EDX] =
27861ecc 1048 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1049 .features[FEAT_8000_0001_ECX] =
27861ecc 1050 CPUID_EXT3_LAHF_LM,
3046bb5d 1051 .xlevel = 0x80000008,
3eca4642
EH		 1052 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1053 },
1054 {
1055 .name = "Nehalem",
3046bb5d 1056 .level = 11,
99b88a17 1057 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1058 .family = 6,
ffce9ebb 1059 .model = 26,
3eca4642 1060 .stepping = 3,
0514ef2f 1061 .features[FEAT_1_EDX] =
b3a4f0b1 1062 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1063 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1064 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1065 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1066 CPUID_DE | CPUID_FP87,
0514ef2f 1067 .features[FEAT_1_ECX] =
27861ecc 1068 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1069 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1070 .features[FEAT_8000_0001_EDX] =
27861ecc 1071 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1072 .features[FEAT_8000_0001_ECX] =
27861ecc 1073 CPUID_EXT3_LAHF_LM,
3046bb5d 1074 .xlevel = 0x80000008,
3eca4642
EH		 1075 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1076 },
1077 {
1078 .name = "Westmere",
1079 .level = 11,
99b88a17 1080 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1081 .family = 6,
1082 .model = 44,
1083 .stepping = 1,
0514ef2f 1084 .features[FEAT_1_EDX] =
b3a4f0b1 1085 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1086 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1087 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1088 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1089 CPUID_DE | CPUID_FP87,
0514ef2f 1090 .features[FEAT_1_ECX] =
27861ecc 1091 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1092 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1093 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1094 .features[FEAT_8000_0001_EDX] =
27861ecc 1095 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1096 .features[FEAT_8000_0001_ECX] =
27861ecc 1097 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1098 .features[FEAT_6_EAX] =
1099 CPUID_6_EAX_ARAT,
3046bb5d 1100 .xlevel = 0x80000008,
3eca4642
EH		 1101 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1102 },
1103 {
1104 .name = "SandyBridge",
1105 .level = 0xd,
99b88a17 1106 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1107 .family = 6,
1108 .model = 42,
1109 .stepping = 1,
0514ef2f 1110 .features[FEAT_1_EDX] =
b3a4f0b1 1111 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1112 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1113 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1114 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1115 CPUID_DE | CPUID_FP87,
0514ef2f 1116 .features[FEAT_1_ECX] =
27861ecc 1117 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1118 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1119 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1120 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1121 CPUID_EXT_SSE3,
0514ef2f 1122 .features[FEAT_8000_0001_EDX] =
27861ecc 1123 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1124 CPUID_EXT2_SYSCALL,
0514ef2f 1125 .features[FEAT_8000_0001_ECX] =
27861ecc 1126 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1127 .features[FEAT_XSAVE] =
1128 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1129 .features[FEAT_6_EAX] =
1130 CPUID_6_EAX_ARAT,
3046bb5d 1131 .xlevel = 0x80000008,
3eca4642
EH		 1132 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1133 },
2f9ac42a
PB		 1134 {
1135 .name = "IvyBridge",
1136 .level = 0xd,
1137 .vendor = CPUID_VENDOR_INTEL,
1138 .family = 6,
1139 .model = 58,
1140 .stepping = 9,
1141 .features[FEAT_1_EDX] =
1142 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1143 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1144 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1145 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1146 CPUID_DE | CPUID_FP87,
1147 .features[FEAT_1_ECX] =
1148 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1149 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1150 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1151 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1152 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1153 .features[FEAT_7_0_EBX] =
1154 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1155 CPUID_7_0_EBX_ERMS,
1156 .features[FEAT_8000_0001_EDX] =
1157 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1158 CPUID_EXT2_SYSCALL,
1159 .features[FEAT_8000_0001_ECX] =
1160 CPUID_EXT3_LAHF_LM,
1161 .features[FEAT_XSAVE] =
1162 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1163 .features[FEAT_6_EAX] =
1164 CPUID_6_EAX_ARAT,
3046bb5d 1165 .xlevel = 0x80000008,
2f9ac42a
PB		 1166 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1167 },
37507094 1168 {
a356850b
EH		 1169 .name = "Haswell-noTSX",
1170 .level = 0xd,
1171 .vendor = CPUID_VENDOR_INTEL,
1172 .family = 6,
1173 .model = 60,
1174 .stepping = 1,
1175 .features[FEAT_1_EDX] =
1176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1180 CPUID_DE | CPUID_FP87,
1181 .features[FEAT_1_ECX] =
1182 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1183 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1185 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1186 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1187 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1188 .features[FEAT_8000_0001_EDX] =
1189 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1190 CPUID_EXT2_SYSCALL,
1191 .features[FEAT_8000_0001_ECX] =
becb6667 1192 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 1193 .features[FEAT_7_0_EBX] =
1194 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1195 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1196 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1197 .features[FEAT_XSAVE] =
1198 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1199 .features[FEAT_6_EAX] =
1200 CPUID_6_EAX_ARAT,
3046bb5d 1201 .xlevel = 0x80000008,
a356850b
EH		 1202 .model_id = "Intel Core Processor (Haswell, no TSX)",
1203 }, {
37507094
EH		 1204 .name = "Haswell",
1205 .level = 0xd,
99b88a17 1206 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 1207 .family = 6,
1208 .model = 60,
1209 .stepping = 1,
0514ef2f 1210 .features[FEAT_1_EDX] =
b3a4f0b1 1211 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1212 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1213 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1214 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1215 CPUID_DE | CPUID_FP87,
0514ef2f 1216 .features[FEAT_1_ECX] =
27861ecc 1217 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1218 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1219 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1220 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1221 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1222 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 1223 .features[FEAT_8000_0001_EDX] =
27861ecc 1224 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1225 CPUID_EXT2_SYSCALL,
0514ef2f 1226 .features[FEAT_8000_0001_ECX] =
becb6667 1227 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 1228 .features[FEAT_7_0_EBX] =
27861ecc 1229 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 1230 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1231 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1232 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 1233 .features[FEAT_XSAVE] =
1234 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1235 .features[FEAT_6_EAX] =
1236 CPUID_6_EAX_ARAT,
3046bb5d 1237 .xlevel = 0x80000008,
37507094
EH		 1238 .model_id = "Intel Core Processor (Haswell)",
1239 },
a356850b
EH		 1240 {
1241 .name = "Broadwell-noTSX",
1242 .level = 0xd,
1243 .vendor = CPUID_VENDOR_INTEL,
1244 .family = 6,
1245 .model = 61,
1246 .stepping = 2,
1247 .features[FEAT_1_EDX] =
1248 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1249 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1250 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1251 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1252 CPUID_DE | CPUID_FP87,
1253 .features[FEAT_1_ECX] =
1254 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1255 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1256 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1257 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1258 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1259 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1260 .features[FEAT_8000_0001_EDX] =
1261 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1262 CPUID_EXT2_SYSCALL,
1263 .features[FEAT_8000_0001_ECX] =
becb6667 1264 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 1265 .features[FEAT_7_0_EBX] =
1266 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1267 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1268 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1269 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1270 CPUID_7_0_EBX_SMAP,
1271 .features[FEAT_XSAVE] =
1272 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1273 .features[FEAT_6_EAX] =
1274 CPUID_6_EAX_ARAT,
3046bb5d 1275 .xlevel = 0x80000008,
a356850b
EH		 1276 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1277 },
ece01354
EH		 1278 {
1279 .name = "Broadwell",
1280 .level = 0xd,
1281 .vendor = CPUID_VENDOR_INTEL,
1282 .family = 6,
1283 .model = 61,
1284 .stepping = 2,
1285 .features[FEAT_1_EDX] =
b3a4f0b1 1286 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 1287 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1288 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1289 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1290 CPUID_DE | CPUID_FP87,
1291 .features[FEAT_1_ECX] =
1292 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1293 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1294 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1295 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1296 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 1297 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 1298 .features[FEAT_8000_0001_EDX] =
1299 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1300 CPUID_EXT2_SYSCALL,
1301 .features[FEAT_8000_0001_ECX] =
becb6667 1302 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 1303 .features[FEAT_7_0_EBX] =
1304 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 1305 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 1306 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 1307 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 1308 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 1309 .features[FEAT_XSAVE] =
1310 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1311 .features[FEAT_6_EAX] =
1312 CPUID_6_EAX_ARAT,
3046bb5d 1313 .xlevel = 0x80000008,
ece01354
EH		 1314 .model_id = "Intel Core Processor (Broadwell)",
1315 },
f6f949e9
EH		 1316 {
1317 .name = "Skylake-Client",
1318 .level = 0xd,
1319 .vendor = CPUID_VENDOR_INTEL,
1320 .family = 6,
1321 .model = 94,
1322 .stepping = 3,
1323 .features[FEAT_1_EDX] =
1324 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1325 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1326 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1327 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1328 CPUID_DE | CPUID_FP87,
1329 .features[FEAT_1_ECX] =
1330 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1331 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1332 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1333 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1334 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1335 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1336 .features[FEAT_8000_0001_EDX] =
1337 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1338 CPUID_EXT2_SYSCALL,
1339 .features[FEAT_8000_0001_ECX] =
1340 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1341 .features[FEAT_7_0_EBX] =
1342 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1343 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1344 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1345 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1346 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1347 /* Missing: XSAVES (not supported by some Linux versions,
1348 * including v4.1 to v4.6).
1349 * KVM doesn't yet expose any XSAVES state save component,
1350 * and the only one defined in Skylake (processor tracing)
1351 * probably will block migration anyway.
1352 */
1353 .features[FEAT_XSAVE] =
1354 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1355 CPUID_XSAVE_XGETBV1,
1356 .features[FEAT_6_EAX] =
1357 CPUID_6_EAX_ARAT,
1358 .xlevel = 0x80000008,
1359 .model_id = "Intel Core Processor (Skylake)",
1360 },
3eca4642
EH		 1361 {
1362 .name = "Opteron_G1",
1363 .level = 5,
99b88a17 1364 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1365 .family = 15,
1366 .model = 6,
1367 .stepping = 1,
0514ef2f 1368 .features[FEAT_1_EDX] =
b3a4f0b1 1369 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1370 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1371 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1372 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1373 CPUID_DE | CPUID_FP87,
0514ef2f 1374 .features[FEAT_1_ECX] =
27861ecc 1375 CPUID_EXT_SSE3,
0514ef2f 1376 .features[FEAT_8000_0001_EDX] =
27861ecc 1377 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
b3fb3a20
EH		 1378 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1379 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1380 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1381 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1382 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
3eca4642
EH		 1383 .xlevel = 0x80000008,
1384 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1385 },
1386 {
1387 .name = "Opteron_G2",
1388 .level = 5,
99b88a17 1389 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1390 .family = 15,
1391 .model = 6,
1392 .stepping = 1,
0514ef2f 1393 .features[FEAT_1_EDX] =
b3a4f0b1 1394 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1395 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1396 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1397 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1398 CPUID_DE | CPUID_FP87,
0514ef2f 1399 .features[FEAT_1_ECX] =
27861ecc 1400 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 1401 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1402 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1403 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1404 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1405 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1406 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1407 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1408 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1409 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1410 .features[FEAT_8000_0001_ECX] =
27861ecc 1411 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1412 .xlevel = 0x80000008,
1413 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1414 },
1415 {
1416 .name = "Opteron_G3",
1417 .level = 5,
99b88a17 1418 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1419 .family = 15,
1420 .model = 6,
1421 .stepping = 1,
0514ef2f 1422 .features[FEAT_1_EDX] =
b3a4f0b1 1423 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1424 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1425 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1426 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1427 CPUID_DE | CPUID_FP87,
0514ef2f 1428 .features[FEAT_1_ECX] =
27861ecc 1429 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 1430 CPUID_EXT_SSE3,
33b5e8c0 1431 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1432 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1433 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
b3fb3a20
EH		 1434 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1435 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1436 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1437 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1438 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1439 CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1440 .features[FEAT_8000_0001_ECX] =
27861ecc 1441 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 1442 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 1443 .xlevel = 0x80000008,
1444 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1445 },
1446 {
1447 .name = "Opteron_G4",
1448 .level = 0xd,
99b88a17 1449 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 1450 .family = 21,
1451 .model = 1,
1452 .stepping = 2,
0514ef2f 1453 .features[FEAT_1_EDX] =
b3a4f0b1 1454 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1455 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1456 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1457 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1458 CPUID_DE | CPUID_FP87,
0514ef2f 1459 .features[FEAT_1_ECX] =
27861ecc 1460 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1461 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1462 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1463 CPUID_EXT_SSE3,
33b5e8c0 1464 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1465 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1466 CPUID_EXT2_LM |
b3fb3a20
EH		 1467 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1468 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1469 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1470 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1471 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1472 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1473 .features[FEAT_8000_0001_ECX] =
27861ecc 1474 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1475 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1476 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1477 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1478 /* no xsaveopt! */
3eca4642
EH		 1479 .xlevel = 0x8000001A,
1480 .model_id = "AMD Opteron 62xx class CPU",
1481 },
021941b9
AP		 1482 {
1483 .name = "Opteron_G5",
1484 .level = 0xd,
99b88a17 1485 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 1486 .family = 21,
1487 .model = 2,
1488 .stepping = 0,
0514ef2f 1489 .features[FEAT_1_EDX] =
b3a4f0b1 1490 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1491 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1492 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1493 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1494 CPUID_DE | CPUID_FP87,
0514ef2f 1495 .features[FEAT_1_ECX] =
27861ecc 1496 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 1497 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1498 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1499 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 1500 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 1501 .features[FEAT_8000_0001_EDX] =
33b5e8c0 1502 CPUID_EXT2_LM |
b3fb3a20
EH		 1503 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1504 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1505 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1506 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1507 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1508 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
0514ef2f 1509 .features[FEAT_8000_0001_ECX] =
27861ecc 1510 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 1511 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1512 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1513 CPUID_EXT3_LAHF_LM,
0bb0b2d2 1514 /* no xsaveopt! */
021941b9
AP		 1515 .xlevel = 0x8000001A,
1516 .model_id = "AMD Opteron 63xx class CPU",
1517 },
c6dc6f63
AP		 1518};
1519
5114e842
EH		 1520typedef struct PropValue {
1521 const char *prop, *value;
1522} PropValue;
1523
1524/* KVM-specific features that are automatically added/removed
1525 * from all CPU models when KVM is enabled.
1526 */
1527static PropValue kvm_default_props[] = {
1528 { "kvmclock", "on" },
1529 { "kvm-nopiodelay", "on" },
1530 { "kvm-asyncpf", "on" },
1531 { "kvm-steal-time", "on" },
1532 { "kvm-pv-eoi", "on" },
1533 { "kvmclock-stable-bit", "on" },
1534 { "x2apic", "on" },
1535 { "acpi", "off" },
1536 { "monitor", "off" },
1537 { "svm", "off" },
1538 { NULL, NULL },
1539};
1540
1541void x86_cpu_change_kvm_default(const char *prop, const char *value)
1542{
1543 PropValue *pv;
1544 for (pv = kvm_default_props; pv->prop; pv++) {
1545 if (!strcmp(pv->prop, prop)) {
1546 pv->value = value;
1547 break;
1548 }
1549 }
1550
1551 /* It is valid to call this function only for properties that
1552 * are already present in the kvm_default_props table.
1553 */
1554 assert(pv->prop);
1555}
1556
4d1b279b
EH		 1557static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1558 bool migratable_only);
1559
d940ee9b
EH		 1560#ifdef CONFIG_KVM
1561
40bfe48f
HZ		 1562static bool lmce_supported(void)
1563{
1564 uint64_t mce_cap;
1565
1566 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1567 return false;
1568 }
1569
1570 return !!(mce_cap & MCG_LMCE_P);
1571}
1572
c6dc6f63
AP		 1573static int cpu_x86_fill_model_id(char *str)
1574{
1575 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1576 int i;
1577
1578 for (i = 0; i < 3; i++) {
1579 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1580 memcpy(str + i * 16 + 0, &eax, 4);
1581 memcpy(str + i * 16 + 4, &ebx, 4);
1582 memcpy(str + i * 16 + 8, &ecx, 4);
1583 memcpy(str + i * 16 + 12, &edx, 4);
1584 }
1585 return 0;
1586}
1587
d940ee9b
EH		 1588static X86CPUDefinition host_cpudef;
1589
84f1b92f 1590static Property host_x86_cpu_properties[] = {
120eee7d 1591 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 1592 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 1593 DEFINE_PROP_END_OF_LIST()
1594};
1595
d940ee9b 1596/* class_init for the "host" CPU model
6e746f30 1597 *
d940ee9b 1598 * This function may be called before KVM is initialized.
6e746f30 1599 */
d940ee9b 1600static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 1601{
84f1b92f 1602 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 1603 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63
AP		 1604 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1605
d940ee9b 1606 xcc->kvm_required = true;
6e746f30 1607
c6dc6f63 1608 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
d940ee9b 1609 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
c6dc6f63
AP		 1610
1611 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
d940ee9b
EH		 1612 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1613 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1614 host_cpudef.stepping = eax & 0x0F;
c6dc6f63 1615
d940ee9b 1616 cpu_x86_fill_model_id(host_cpudef.model_id);
2a573259 1617
d940ee9b 1618 xcc->cpu_def = &host_cpudef;
d940ee9b
EH		 1619
1620 /* level, xlevel, xlevel2, and the feature words are initialized on
1621 * instance_init, because they require KVM to be initialized.
1622 */
84f1b92f
EH		 1623
1624 dc->props = host_x86_cpu_properties;
4c315c27
MA		 1625 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1626 dc->cannot_destroy_with_object_finalize_yet = true;
d940ee9b
EH		 1627}
1628
1629static void host_x86_cpu_initfn(Object *obj)
1630{
1631 X86CPU *cpu = X86_CPU(obj);
1632 CPUX86State *env = &cpu->env;
1633 KVMState *s = kvm_state;
d940ee9b 1634
4d1b279b
EH		 1635 /* We can't fill the features array here because we don't know yet if
1636 * "migratable" is true or false.
1637 */
1638 cpu->host_features = true;
1639
104494ea 1640 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
e4356010
EH		 1641 if (kvm_enabled()) {
1642 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1643 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1644 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
40bfe48f
HZ		 1645
1646 if (lmce_supported()) {
1647 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1648 }
e4356010 1649 }
2a573259 1650
d940ee9b 1651 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 1652}
1653
d940ee9b
EH		 1654static const TypeInfo host_x86_cpu_type_info = {
1655 .name = X86_CPU_TYPE_NAME("host"),
1656 .parent = TYPE_X86_CPU,
1657 .instance_init = host_x86_cpu_initfn,
1658 .class_init = host_x86_cpu_class_init,
1659};
1660
1661#endif
1662
8459e396 1663static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 1664{
8459e396 1665 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 1666 int i;
1667
857aee33 1668 for (i = 0; i < 32; ++i) {
72370dc1 1669 if ((1UL << i) & mask) {
bffd67b0 1670 const char *reg = get_register_name_32(f->cpuid_reg);
8b4beddc 1671 assert(reg);
fefb41bf 1672 fprintf(stderr, "warning: %s doesn't support requested feature: "
8b4beddc 1673 "CPUID.%02XH:%s%s%s [bit %d]\n",
fefb41bf 1674 kvm_enabled() ? "host" : "TCG",
bffd67b0
EH		 1675 f->cpuid_eax, reg,
1676 f->feat_names[i] ? "." : "",
1677 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 1678 }
857aee33 1679 }
c6dc6f63
AP		 1680}
1681
d7bce999
EB		 1682static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1683 const char *name, void *opaque,
1684 Error **errp)
95b8519d
AF		 1685{
1686 X86CPU *cpu = X86_CPU(obj);
1687 CPUX86State *env = &cpu->env;
1688 int64_t value;
1689
1690 value = (env->cpuid_version >> 8) & 0xf;
1691 if (value == 0xf) {
1692 value += (env->cpuid_version >> 20) & 0xff;
1693 }
51e72bc1 1694 visit_type_int(v, name, &value, errp);
95b8519d
AF		 1695}
1696
d7bce999
EB		 1697static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1698 const char *name, void *opaque,
1699 Error **errp)
ed5e1ec3 1700{
71ad61d3
AF		 1701 X86CPU *cpu = X86_CPU(obj);
1702 CPUX86State *env = &cpu->env;
1703 const int64_t min = 0;
1704 const int64_t max = 0xff + 0xf;
65cd9064 1705 Error *local_err = NULL;
71ad61d3
AF		 1706 int64_t value;
1707
51e72bc1 1708 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1709 if (local_err) {
1710 error_propagate(errp, local_err);
71ad61d3
AF		 1711 return;
1712 }
1713 if (value < min || value > max) {
c6bd8c70
MA		 1714 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1715 name ? name : "null", value, min, max);
71ad61d3
AF		 1716 return;
1717 }
1718
ed5e1ec3 1719 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 1720 if (value > 0x0f) {
1721 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 1722 } else {
71ad61d3 1723 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 1724 }
1725}
1726
d7bce999
EB		 1727static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1728 const char *name, void *opaque,
1729 Error **errp)
67e30c83
AF		 1730{
1731 X86CPU *cpu = X86_CPU(obj);
1732 CPUX86State *env = &cpu->env;
1733 int64_t value;
1734
1735 value = (env->cpuid_version >> 4) & 0xf;
1736 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 1737 visit_type_int(v, name, &value, errp);
67e30c83
AF		 1738}
1739
d7bce999
EB		 1740static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1741 const char *name, void *opaque,
1742 Error **errp)
b0704cbd 1743{
c5291a4f
AF		 1744 X86CPU *cpu = X86_CPU(obj);
1745 CPUX86State *env = &cpu->env;
1746 const int64_t min = 0;
1747 const int64_t max = 0xff;
65cd9064 1748 Error *local_err = NULL;
c5291a4f
AF		 1749 int64_t value;
1750
51e72bc1 1751 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1752 if (local_err) {
1753 error_propagate(errp, local_err);
c5291a4f
AF		 1754 return;
1755 }
1756 if (value < min || value > max) {
c6bd8c70
MA		 1757 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1758 name ? name : "null", value, min, max);
c5291a4f
AF		 1759 return;
1760 }
1761
b0704cbd 1762 env->cpuid_version &= ~0xf00f0;
c5291a4f 1763 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 1764}
1765
35112e41 1766static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 1767 const char *name, void *opaque,
35112e41
AF		 1768 Error **errp)
1769{
1770 X86CPU *cpu = X86_CPU(obj);
1771 CPUX86State *env = &cpu->env;
1772 int64_t value;
1773
1774 value = env->cpuid_version & 0xf;
51e72bc1 1775 visit_type_int(v, name, &value, errp);
35112e41
AF		 1776}
1777
036e2222 1778static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 1779 const char *name, void *opaque,
036e2222 1780 Error **errp)
38c3dc46 1781{
036e2222
AF		 1782 X86CPU *cpu = X86_CPU(obj);
1783 CPUX86State *env = &cpu->env;
1784 const int64_t min = 0;
1785 const int64_t max = 0xf;
65cd9064 1786 Error *local_err = NULL;
036e2222
AF		 1787 int64_t value;
1788
51e72bc1 1789 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1790 if (local_err) {
1791 error_propagate(errp, local_err);
036e2222
AF		 1792 return;
1793 }
1794 if (value < min || value > max) {
c6bd8c70
MA		 1795 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1796 name ? name : "null", value, min, max);
036e2222
AF		 1797 return;
1798 }
1799
38c3dc46 1800 env->cpuid_version &= ~0xf;
036e2222 1801 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 1802}
1803
d480e1af
AF		 1804static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1805{
1806 X86CPU *cpu = X86_CPU(obj);
1807 CPUX86State *env = &cpu->env;
1808 char *value;
d480e1af 1809
e42a92ae 1810 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 1811 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1812 env->cpuid_vendor3);
d480e1af
AF		 1813 return value;
1814}
1815
1816static void x86_cpuid_set_vendor(Object *obj, const char *value,
1817 Error **errp)
1818{
1819 X86CPU *cpu = X86_CPU(obj);
1820 CPUX86State *env = &cpu->env;
1821 int i;
1822
9df694ee 1823 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 1824 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 1825 return;
1826 }
1827
1828 env->cpuid_vendor1 = 0;
1829 env->cpuid_vendor2 = 0;
1830 env->cpuid_vendor3 = 0;
1831 for (i = 0; i < 4; i++) {
1832 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1833 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1834 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1835 }
d480e1af
AF		 1836}
1837
63e886eb
AF		 1838static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1839{
1840 X86CPU *cpu = X86_CPU(obj);
1841 CPUX86State *env = &cpu->env;
1842 char *value;
1843 int i;
1844
1845 value = g_malloc(48 + 1);
1846 for (i = 0; i < 48; i++) {
1847 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1848 }
1849 value[48] = '\0';
1850 return value;
1851}
1852
938d4c25
AF		 1853static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1854 Error **errp)
dcce6675 1855{
938d4c25
AF		 1856 X86CPU *cpu = X86_CPU(obj);
1857 CPUX86State *env = &cpu->env;
dcce6675
AF		 1858 int c, len, i;
1859
1860 if (model_id == NULL) {
1861 model_id = "";
1862 }
1863 len = strlen(model_id);
d0a6acf4 1864 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 1865 for (i = 0; i < 48; i++) {
1866 if (i >= len) {
1867 c = '\0';
1868 } else {
1869 c = (uint8_t)model_id[i];
1870 }
1871 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1872 }
1873}
1874
d7bce999
EB		 1875static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1876 void *opaque, Error **errp)
89e48965
AF		 1877{
1878 X86CPU *cpu = X86_CPU(obj);
1879 int64_t value;
1880
1881 value = cpu->env.tsc_khz * 1000;
51e72bc1 1882 visit_type_int(v, name, &value, errp);
89e48965
AF		 1883}
1884
d7bce999
EB		 1885static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1886 void *opaque, Error **errp)
89e48965
AF		 1887{
1888 X86CPU *cpu = X86_CPU(obj);
1889 const int64_t min = 0;
2e84849a 1890 const int64_t max = INT64_MAX;
65cd9064 1891 Error *local_err = NULL;
89e48965
AF		 1892 int64_t value;
1893
51e72bc1 1894 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 1895 if (local_err) {
1896 error_propagate(errp, local_err);
89e48965
AF		 1897 return;
1898 }
1899 if (value < min || value > max) {
c6bd8c70
MA		 1900 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1901 name ? name : "null", value, min, max);
89e48965
AF		 1902 return;
1903 }
1904
36f96c4b 1905 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 1906}
1907
7e5292b5 1908/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 1909static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1910 const char *name, void *opaque,
1911 Error **errp)
8e8aba50 1912{
7e5292b5 1913 uint32_t *array = (uint32_t *)opaque;
8e8aba50 1914 FeatureWord w;
8e8aba50
EH		 1915 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1916 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1917 X86CPUFeatureWordInfoList *list = NULL;
1918
1919 for (w = 0; w < FEATURE_WORDS; w++) {
1920 FeatureWordInfo *wi = &feature_word_info[w];
1921 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1922 qwi->cpuid_input_eax = wi->cpuid_eax;
1923 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1924 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1925 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
7e5292b5 1926 qwi->features = array[w];
8e8aba50
EH		 1927
1928 /* List will be in reverse order, but order shouldn't matter */
1929 list_entries[w].next = list;
1930 list_entries[w].value = &word_infos[w];
1931 list = &list_entries[w];
1932 }
1933
6b62d961 1934 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 1935}
1936
d7bce999
EB		 1937static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1938 void *opaque, Error **errp)
c8f0f88e
IM		 1939{
1940 X86CPU *cpu = X86_CPU(obj);
1941 int64_t value = cpu->hyperv_spinlock_attempts;
1942
51e72bc1 1943 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 1944}
1945
d7bce999
EB		 1946static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1947 void *opaque, Error **errp)
c8f0f88e
IM		 1948{
1949 const int64_t min = 0xFFF;
1950 const int64_t max = UINT_MAX;
1951 X86CPU *cpu = X86_CPU(obj);
1952 Error *err = NULL;
1953 int64_t value;
1954
51e72bc1 1955 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 1956 if (err) {
1957 error_propagate(errp, err);
1958 return;
1959 }
1960
1961 if (value < min || value > max) {
1962 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 1963 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1964 object_get_typename(obj), name ? name : "null",
1965 value, min, max);
c8f0f88e
IM		 1966 return;
1967 }
1968 cpu->hyperv_spinlock_attempts = value;
1969}
1970
1971static PropertyInfo qdev_prop_spinlocks = {
1972 .name = "int",
1973 .get = x86_get_hv_spinlocks,
1974 .set = x86_set_hv_spinlocks,
1975};
1976
72ac2e87
IM		 1977/* Convert all '_' in a feature string option name to '-', to make feature
1978 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1979 */
1980static inline void feat2prop(char *s)
1981{
1982 while ((s = strchr(s, '_'))) {
1983 *s = '-';
1984 }
1985}
1986
dc15c051
IM		 1987/* Compatibily hack to maintain legacy +-feat semantic,
1988 * where +-feat overwrites any feature set by
1989 * feat=on|feat even if the later is parsed after +-feat
1990 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1991 */
1992static FeatureWordArray plus_features = { 0 };
1993static FeatureWordArray minus_features = { 0 };
1994
8f961357
EH		 1995/* Parse "+feature,-feature,feature=foo" CPU feature string
1996 */
62a48a2a 1997static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 1998 Error **errp)
8f961357 1999{
8f961357 2000 char *featurestr; /* Single 'key=value" string being parsed */
94a444b2 2001 Error *local_err = NULL;
62a48a2a
IM		 2002 static bool cpu_globals_initialized;
2003
2004 if (cpu_globals_initialized) {
2005 return;
2006 }
2007 cpu_globals_initialized = true;
8f961357 2008
f6750e95
EH		 2009 if (!features) {
2010 return;
2011 }
2012
2013 for (featurestr = strtok(features, ",");
2014 featurestr && !local_err;
2015 featurestr = strtok(NULL, ",")) {
2016 const char *name;
2017 const char *val = NULL;
2018 char *eq = NULL;
cf2887c9 2019 char num[32];
62a48a2a 2020 GlobalProperty *prop;
c6dc6f63 2021
f6750e95 2022 /* Compatibility syntax: */
c6dc6f63 2023 if (featurestr[0] == '+') {
c00c94ab 2024 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
f6750e95 2025 continue;
c6dc6f63 2026 } else if (featurestr[0] == '-') {
c00c94ab 2027 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
f6750e95
EH		 2028 continue;
2029 }
2030
2031 eq = strchr(featurestr, '=');
2032 if (eq) {
2033 *eq++ = 0;
2034 val = eq;
c6dc6f63 2035 } else {
f6750e95 2036 val = "on";
a91987c2 2037 }
f6750e95
EH		 2038
2039 feat2prop(featurestr);
2040 name = featurestr;
2041
2042 /* Special case: */
2043 if (!strcmp(name, "tsc-freq")) {
2044 int64_t tsc_freq;
2045 char *err;
f6750e95
EH		 2046
2047 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2048 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2049 if (tsc_freq < 0 || *err) {
2050 error_setg(errp, "bad numerical value %s", val);
2051 return;
2052 }
2053 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2054 val = num;
2055 name = "tsc-frequency";
c6dc6f63 2056 }
f6750e95 2057
62a48a2a
IM		 2058 prop = g_new0(typeof(*prop), 1);
2059 prop->driver = typename;
2060 prop->property = g_strdup(name);
2061 prop->value = g_strdup(val);
2062 prop->errp = &error_fatal;
2063 qdev_prop_register_global(prop);
f6750e95
EH		 2064 }
2065
2066 if (local_err) {
2067 error_propagate(errp, local_err);
c6dc6f63 2068 }
c6dc6f63
AP		 2069}
2070
8c3329e5 2071/* Print all cpuid feature names in featureset
c6dc6f63 2072 */
8c3329e5 2073static void listflags(FILE *f, fprintf_function print, const char **featureset)
0856579c 2074{
8c3329e5
EH		 2075 int bit;
2076 bool first = true;
2077
2078 for (bit = 0; bit < 32; bit++) {
2079 if (featureset[bit]) {
2080 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2081 first = false;
c6dc6f63 2082 }
8c3329e5 2083 }
c6dc6f63
AP		 2084}
2085
e916cbf8
PM		 2086/* generate CPU information. */
2087void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 2088{
9576de75 2089 X86CPUDefinition *def;
c6dc6f63 2090 char buf[256];
7fc9b714 2091 int i;
c6dc6f63 2092
7fc9b714
AF		 2093 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2094 def = &builtin_x86_defs[i];
c04321b3 2095 snprintf(buf, sizeof(buf), "%s", def->name);
6cdf8854 2096 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
c6dc6f63 2097 }
21ad7789
JK		 2098#ifdef CONFIG_KVM
2099 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2100 "KVM processor with all supported host features "
2101 "(only available in KVM mode)");
2102#endif
2103
6cdf8854 2104 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3af60be2
JK		 2105 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2106 FeatureWordInfo *fw = &feature_word_info[i];
2107
8c3329e5
EH		 2108 (*cpu_fprintf)(f, " ");
2109 listflags(f, cpu_fprintf, fw->feat_names);
2110 (*cpu_fprintf)(f, "\n");
3af60be2 2111 }
c6dc6f63
AP		 2112}
2113
76b64a7a 2114CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 2115{
2116 CpuDefinitionInfoList *cpu_list = NULL;
9576de75 2117 X86CPUDefinition *def;
7fc9b714 2118 int i;
e3966126 2119
7fc9b714 2120 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
e3966126
AL		 2121 CpuDefinitionInfoList *entry;
2122 CpuDefinitionInfo *info;
2123
7fc9b714 2124 def = &builtin_x86_defs[i];
e3966126
AL		 2125 info = g_malloc0(sizeof(*info));
2126 info->name = g_strdup(def->name);
2127
2128 entry = g_malloc0(sizeof(*entry));
2129 entry->value = info;
2130 entry->next = cpu_list;
2131 cpu_list = entry;
2132 }
2133
2134 return cpu_list;
2135}
2136
84f1b92f
EH		 2137static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2138 bool migratable_only)
27418adf
EH		 2139{
2140 FeatureWordInfo *wi = &feature_word_info[w];
84f1b92f 2141 uint32_t r;
27418adf 2142
fefb41bf 2143 if (kvm_enabled()) {
84f1b92f
EH		 2144 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2145 wi->cpuid_ecx,
2146 wi->cpuid_reg);
fefb41bf 2147 } else if (tcg_enabled()) {
84f1b92f 2148 r = wi->tcg_features;
fefb41bf
EH		 2149 } else {
2150 return ~0;
2151 }
84f1b92f
EH		 2152 if (migratable_only) {
2153 r &= x86_cpu_get_migratable_flags(w);
2154 }
2155 return r;
27418adf
EH		 2156}
2157
51f63aed
EH		 2158/*
2159 * Filters CPU feature words based on host availability of each feature.
2160 *
51f63aed
EH		 2161 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2162 */
27418adf 2163static int x86_cpu_filter_features(X86CPU *cpu)
bc74b7db
EH		 2164{
2165 CPUX86State *env = &cpu->env;
bd87d2a2 2166 FeatureWord w;
51f63aed
EH		 2167 int rv = 0;
2168
bd87d2a2 2169 for (w = 0; w < FEATURE_WORDS; w++) {
84f1b92f
EH		 2170 uint32_t host_feat =
2171 x86_cpu_get_supported_feature_word(w, cpu->migratable);
034acf4a
EH		 2172 uint32_t requested_features = env->features[w];
2173 env->features[w] &= host_feat;
2174 cpu->filtered_features[w] = requested_features & ~env->features[w];
51f63aed
EH		 2175 if (cpu->filtered_features[w]) {
2176 if (cpu->check_cpuid || cpu->enforce_cpuid) {
8459e396 2177 report_unavailable_features(w, cpu->filtered_features[w]);
51f63aed
EH		 2178 }
2179 rv = 1;
2180 }
bd87d2a2 2181 }
51f63aed
EH		 2182
2183 return rv;
bc74b7db 2184}
bc74b7db 2185
5114e842
EH		 2186static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2187{
2188 PropValue *pv;
2189 for (pv = props; pv->prop; pv++) {
2190 if (!pv->value) {
2191 continue;
2192 }
2193 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2194 &error_abort);
2195 }
2196}
2197
d940ee9b 2198/* Load data from X86CPUDefinition
c080e30e 2199 */
d940ee9b 2200static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 2201{
61dcd775 2202 CPUX86State *env = &cpu->env;
74f54bc4
EH		 2203 const char *vendor;
2204 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 2205 FeatureWord w;
c6dc6f63 2206
2d64255b
AF		 2207 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2208 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2209 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2210 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 2211 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
01431f3c 2212 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2d64255b 2213 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 2214 for (w = 0; w < FEATURE_WORDS; w++) {
2215 env->features[w] = def->features[w];
2216 }
82beb536 2217
9576de75 2218 /* Special cases not set in the X86CPUDefinition structs: */
82beb536 2219 if (kvm_enabled()) {
492a4c94
LT		 2220 if (!kvm_irqchip_in_kernel()) {
2221 x86_cpu_change_kvm_default("x2apic", "off");
2222 }
2223
5114e842 2224 x86_cpu_apply_props(cpu, kvm_default_props);
82beb536 2225 }
5fcca9ff 2226
82beb536 2227 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 2228
2229 /* sysenter isn't supported in compatibility mode on AMD,
2230 * syscall isn't supported in compatibility mode on Intel.
2231 * Normally we advertise the actual CPU vendor, but you can
2232 * override this using the 'vendor' property if you want to use
2233 * KVM's sysenter/syscall emulation in compatibility mode and
2234 * when doing cross vendor migration
2235 */
74f54bc4 2236 vendor = def->vendor;
7c08db30
EH		 2237 if (kvm_enabled()) {
2238 uint32_t ebx = 0, ecx = 0, edx = 0;
2239 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2240 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2241 vendor = host_vendor;
2242 }
2243
2244 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2245
c6dc6f63
AP		 2246}
2247
0856579c 2248X86CPU *cpu_x86_init(const char *cpu_model)
7f833247 2249{
a57d0163 2250 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
5c3c6a68
AF		 2251}
2252
d940ee9b
EH		 2253static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2254{
2255 X86CPUDefinition *cpudef = data;
2256 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2257
2258 xcc->cpu_def = cpudef;
2259}
2260
2261static void x86_register_cpudef_type(X86CPUDefinition *def)
2262{
2263 char *typename = x86_cpu_type_name(def->name);
2264 TypeInfo ti = {
2265 .name = typename,
2266 .parent = TYPE_X86_CPU,
2267 .class_init = x86_cpu_cpudef_class_init,
2268 .class_data = def,
2269 };
2270
2271 type_register(&ti);
2272 g_free(typename);
2273}
2274
c6dc6f63 2275#if !defined(CONFIG_USER_ONLY)
c6dc6f63 2276
0e26b7b8
BS		 2277void cpu_clear_apic_feature(CPUX86State *env)
2278{
0514ef2f 2279 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 2280}
2281
c6dc6f63
AP		 2282#endif /* !CONFIG_USER_ONLY */
2283
c6dc6f63
AP		 2284void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2285 uint32_t *eax, uint32_t *ebx,
2286 uint32_t *ecx, uint32_t *edx)
2287{
a60f24b5
AF		 2288 X86CPU *cpu = x86_env_get_cpu(env);
2289 CPUState *cs = CPU(cpu);
14c985cf 2290 uint32_t pkg_offset;
a60f24b5 2291
c6dc6f63
AP		 2292 /* test if maximum index reached */
2293 if (index & 0x80000000) {
b3baa152
BW		 2294 if (index > env->cpuid_xlevel) {
2295 if (env->cpuid_xlevel2 > 0) {
2296 /* Handle the Centaur's CPUID instruction. */
2297 if (index > env->cpuid_xlevel2) {
2298 index = env->cpuid_xlevel2;
2299 } else if (index < 0xC0000000) {
2300 index = env->cpuid_xlevel;
2301 }
2302 } else {
57f26ae7
EH		 2303 /* Intel documentation states that invalid EAX input will
2304 * return the same information as EAX=cpuid_level
2305 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2306 */
2307 index = env->cpuid_level;
b3baa152
BW		 2308 }
2309 }
c6dc6f63
AP		 2310 } else {
2311 if (index > env->cpuid_level)
2312 index = env->cpuid_level;
2313 }
2314
2315 switch(index) {
2316 case 0:
2317 *eax = env->cpuid_level;
5eb2f7a4
EH		 2318 *ebx = env->cpuid_vendor1;
2319 *edx = env->cpuid_vendor2;
2320 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 2321 break;
2322 case 1:
2323 *eax = env->cpuid_version;
7e72a45c
EH		 2324 *ebx = (cpu->apic_id << 24) |
2325 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 2326 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 2327 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2328 *ecx |= CPUID_EXT_OSXSAVE;
2329 }
0514ef2f 2330 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 2331 if (cs->nr_cores * cs->nr_threads > 1) {
2332 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 2333 *edx |= CPUID_HT;
c6dc6f63
AP		 2334 }
2335 break;
2336 case 2:
2337 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 2338 if (cpu->cache_info_passthrough) {
2339 host_cpuid(index, 0, eax, ebx, ecx, edx);
2340 break;
2341 }
5e891bf8 2342 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 2343 *ebx = 0;
14c985cf
LM		 2344 if (!cpu->enable_l3_cache) {
2345 *ecx = 0;
2346 } else {
2347 *ecx = L3_N_DESCRIPTOR;
2348 }
5e891bf8
EH		 2349 *edx = (L1D_DESCRIPTOR << 16) | \
2350 (L1I_DESCRIPTOR << 8) | \
2351 (L2_DESCRIPTOR);
c6dc6f63
AP		 2352 break;
2353 case 4:
2354 /* cache info: needed for Core compatibility */
787aaf57
BC		 2355 if (cpu->cache_info_passthrough) {
2356 host_cpuid(index, count, eax, ebx, ecx, edx);
76c2975a 2357 *eax &= ~0xFC000000;
c6dc6f63 2358 } else {
2f7a21c4 2359 *eax = 0;
76c2975a 2360 switch (count) {
c6dc6f63 2361 case 0: /* L1 dcache info */
5e891bf8
EH		 2362 *eax |= CPUID_4_TYPE_DCACHE | \
2363 CPUID_4_LEVEL(1) | \
2364 CPUID_4_SELF_INIT_LEVEL;
2365 *ebx = (L1D_LINE_SIZE - 1) | \
2366 ((L1D_PARTITIONS - 1) << 12) | \
2367 ((L1D_ASSOCIATIVITY - 1) << 22);
2368 *ecx = L1D_SETS - 1;
2369 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2370 break;
2371 case 1: /* L1 icache info */
5e891bf8
EH		 2372 *eax |= CPUID_4_TYPE_ICACHE | \
2373 CPUID_4_LEVEL(1) | \
2374 CPUID_4_SELF_INIT_LEVEL;
2375 *ebx = (L1I_LINE_SIZE - 1) | \
2376 ((L1I_PARTITIONS - 1) << 12) | \
2377 ((L1I_ASSOCIATIVITY - 1) << 22);
2378 *ecx = L1I_SETS - 1;
2379 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63
AP		 2380 break;
2381 case 2: /* L2 cache info */
5e891bf8
EH		 2382 *eax |= CPUID_4_TYPE_UNIFIED | \
2383 CPUID_4_LEVEL(2) | \
2384 CPUID_4_SELF_INIT_LEVEL;
ce3960eb
AF		 2385 if (cs->nr_threads > 1) {
2386 *eax |= (cs->nr_threads - 1) << 14;
c6dc6f63 2387 }
5e891bf8
EH		 2388 *ebx = (L2_LINE_SIZE - 1) | \
2389 ((L2_PARTITIONS - 1) << 12) | \
2390 ((L2_ASSOCIATIVITY - 1) << 22);
2391 *ecx = L2_SETS - 1;
2392 *edx = CPUID_4_NO_INVD_SHARING;
c6dc6f63 2393 break;
14c985cf
LM		 2394 case 3: /* L3 cache info */
2395 if (!cpu->enable_l3_cache) {
2396 *eax = 0;
2397 *ebx = 0;
2398 *ecx = 0;
2399 *edx = 0;
2400 break;
2401 }
2402 *eax |= CPUID_4_TYPE_UNIFIED | \
2403 CPUID_4_LEVEL(3) | \
2404 CPUID_4_SELF_INIT_LEVEL;
2405 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2406 *eax |= ((1 << pkg_offset) - 1) << 14;
2407 *ebx = (L3_N_LINE_SIZE - 1) | \
2408 ((L3_N_PARTITIONS - 1) << 12) | \
2409 ((L3_N_ASSOCIATIVITY - 1) << 22);
2410 *ecx = L3_N_SETS - 1;
2411 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2412 break;
c6dc6f63
AP		 2413 default: /* end of info */
2414 *eax = 0;
2415 *ebx = 0;
2416 *ecx = 0;
2417 *edx = 0;
2418 break;
76c2975a
PB		 2419 }
2420 }
2421
2422 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2423 if ((*eax & 31) && cs->nr_cores > 1) {
2424 *eax |= (cs->nr_cores - 1) << 26;
c6dc6f63
AP		 2425 }
2426 break;
2427 case 5:
2428 /* mwait info: needed for Core compatibility */
2429 *eax = 0; /* Smallest monitor-line size in bytes */
2430 *ebx = 0; /* Largest monitor-line size in bytes */
2431 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2432 *edx = 0;
2433 break;
2434 case 6:
2435 /* Thermal and Power Leaf */
28b8e4d0 2436 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 2437 *ebx = 0;
2438 *ecx = 0;
2439 *edx = 0;
2440 break;
f7911686 2441 case 7:
13526728
EH		 2442 /* Structured Extended Feature Flags Enumeration Leaf */
2443 if (count == 0) {
2444 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 2445 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 2446 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 2447 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2448 *ecx |= CPUID_7_0_ECX_OSPKE;
2449 }
13526728 2450 *edx = 0; /* Reserved */
f7911686
YW		 2451 } else {
2452 *eax = 0;
2453 *ebx = 0;
2454 *ecx = 0;
2455 *edx = 0;
2456 }
2457 break;
c6dc6f63
AP		 2458 case 9:
2459 /* Direct Cache Access Information Leaf */
2460 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2461 *ebx = 0;
2462 *ecx = 0;
2463 *edx = 0;
2464 break;
2465 case 0xA:
2466 /* Architectural Performance Monitoring Leaf */
9337e3b6 2467 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 2468 KVMState *s = cs->kvm_state;
a0fa8208
GN		 2469
2470 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2471 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2472 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2473 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2474 } else {
2475 *eax = 0;
2476 *ebx = 0;
2477 *ecx = 0;
2478 *edx = 0;
2479 }
c6dc6f63 2480 break;
5232d00a
RK		 2481 case 0xB:
2482 /* Extended Topology Enumeration Leaf */
2483 if (!cpu->enable_cpuid_0xb) {
2484 *eax = *ebx = *ecx = *edx = 0;
2485 break;
2486 }
2487
2488 *ecx = count & 0xff;
2489 *edx = cpu->apic_id;
2490
2491 switch (count) {
2492 case 0:
2493 *eax = apicid_core_offset(smp_cores, smp_threads);
2494 *ebx = smp_threads;
2495 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2496 break;
2497 case 1:
2498 *eax = apicid_pkg_offset(smp_cores, smp_threads);
2499 *ebx = smp_cores * smp_threads;
2500 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2501 break;
2502 default:
2503 *eax = 0;
2504 *ebx = 0;
2505 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2506 }
2507
2508 assert(!(*eax & ~0x1f));
2509 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2510 break;
2560f19f
PB		 2511 case 0xD: {
2512 KVMState *s = cs->kvm_state;
19dc85db 2513 uint64_t ena_mask;
2560f19f
PB		 2514 int i;
2515
51e49430 2516 /* Processor Extended State */
2560f19f
PB		 2517 *eax = 0;
2518 *ebx = 0;
2519 *ecx = 0;
2520 *edx = 0;
19dc85db 2521 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 2522 break;
2523 }
19dc85db
RH		 2524 if (kvm_enabled()) {
2525 ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2526 ena_mask <<= 32;
2527 ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2528 } else {
2529 ena_mask = -1;
2530 }
ba9bc59e 2531
2560f19f
PB		 2532 if (count == 0) {
2533 *ecx = 0x240;
f4f1110e
RH		 2534 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2535 const ExtSaveArea *esa = &x86_ext_save_areas[i];
19dc85db
RH		 2536 if ((env->features[esa->feature] & esa->bits) == esa->bits
2537 && ((ena_mask >> i) & 1) != 0) {
2560f19f 2538 if (i < 32) {
19dc85db 2539 *eax |= 1u << i;
2560f19f 2540 } else {
19dc85db 2541 *edx |= 1u << (i - 32);
2560f19f
PB		 2542 }
2543 *ecx = MAX(*ecx, esa->offset + esa->size);
2544 }
2545 }
cfc3b074 2546 *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2560f19f
PB		 2547 *ebx = *ecx;
2548 } else if (count == 1) {
0bb0b2d2 2549 *eax = env->features[FEAT_XSAVE];
f4f1110e
RH		 2550 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2551 const ExtSaveArea *esa = &x86_ext_save_areas[count];
19dc85db
RH		 2552 if ((env->features[esa->feature] & esa->bits) == esa->bits
2553 && ((ena_mask >> count) & 1) != 0) {
33f373d7
LJ		 2554 *eax = esa->size;
2555 *ebx = esa->offset;
2560f19f 2556 }
51e49430
SY		 2557 }
2558 break;
2560f19f 2559 }
c6dc6f63
AP		 2560 case 0x80000000:
2561 *eax = env->cpuid_xlevel;
2562 *ebx = env->cpuid_vendor1;
2563 *edx = env->cpuid_vendor2;
2564 *ecx = env->cpuid_vendor3;
2565 break;
2566 case 0x80000001:
2567 *eax = env->cpuid_version;
2568 *ebx = 0;
0514ef2f
EH		 2569 *ecx = env->features[FEAT_8000_0001_ECX];
2570 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 2571
2572 /* The Linux kernel checks for the CMPLegacy bit and
2573 * discards multiple thread information if it is set.
cb8d4c8f 2574 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 2575 */
ce3960eb 2576 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 2577 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2578 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2579 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 2580 *ecx |= 1 << 1; /* CmpLegacy bit */
2581 }
2582 }
c6dc6f63
AP		 2583 break;
2584 case 0x80000002:
2585 case 0x80000003:
2586 case 0x80000004:
2587 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2588 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2589 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2590 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2591 break;
2592 case 0x80000005:
2593 /* cache info (L1 cache) */
787aaf57
BC		 2594 if (cpu->cache_info_passthrough) {
2595 host_cpuid(index, 0, eax, ebx, ecx, edx);
2596 break;
2597 }
5e891bf8
EH		 2598 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2599 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2600 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2601 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2602 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2603 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2604 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2605 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
c6dc6f63
AP		 2606 break;
2607 case 0x80000006:
2608 /* cache info (L2 cache) */
787aaf57
BC		 2609 if (cpu->cache_info_passthrough) {
2610 host_cpuid(index, 0, eax, ebx, ecx, edx);
2611 break;
2612 }
5e891bf8
EH		 2613 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2614 (L2_DTLB_2M_ENTRIES << 16) | \
2615 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2616 (L2_ITLB_2M_ENTRIES);
2617 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2618 (L2_DTLB_4K_ENTRIES << 16) | \
2619 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2620 (L2_ITLB_4K_ENTRIES);
2621 *ecx = (L2_SIZE_KB_AMD << 16) | \
2622 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2623 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
14c985cf
LM		 2624 if (!cpu->enable_l3_cache) {
2625 *edx = ((L3_SIZE_KB / 512) << 18) | \
2626 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2627 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2628 } else {
2629 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2630 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2631 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2632 }
c6dc6f63 2633 break;
303752a9
MT		 2634 case 0x80000007:
2635 *eax = 0;
2636 *ebx = 0;
2637 *ecx = 0;
2638 *edx = env->features[FEAT_8000_0007_EDX];
2639 break;
c6dc6f63
AP		 2640 case 0x80000008:
2641 /* virtual & phys address size in low 2 bytes. */
0514ef2f 2642 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a
DDAG		 2643 /* 64 bit processor, 48 bits virtual, configurable
2644 * physical bits.
2645 */
2646 *eax = 0x00003000 + cpu->phys_bits;
c6dc6f63 2647 } else {
af45907a 2648 *eax = cpu->phys_bits;
c6dc6f63
AP		 2649 }
2650 *ebx = 0;
2651 *ecx = 0;
2652 *edx = 0;
ce3960eb
AF		 2653 if (cs->nr_cores * cs->nr_threads > 1) {
2654 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 2655 }
2656 break;
2657 case 0x8000000A:
0514ef2f 2658 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 2659 *eax = 0x00000001; /* SVM Revision */
2660 *ebx = 0x00000010; /* nr of ASIDs */
2661 *ecx = 0;
0514ef2f 2662 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 2663 } else {
2664 *eax = 0;
2665 *ebx = 0;
2666 *ecx = 0;
2667 *edx = 0;
2668 }
c6dc6f63 2669 break;
b3baa152
BW		 2670 case 0xC0000000:
2671 *eax = env->cpuid_xlevel2;
2672 *ebx = 0;
2673 *ecx = 0;
2674 *edx = 0;
2675 break;
2676 case 0xC0000001:
2677 /* Support for VIA CPU's CPUID instruction */
2678 *eax = env->cpuid_version;
2679 *ebx = 0;
2680 *ecx = 0;
0514ef2f 2681 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 2682 break;
2683 case 0xC0000002:
2684 case 0xC0000003:
2685 case 0xC0000004:
2686 /* Reserved for the future, and now filled with zero */
2687 *eax = 0;
2688 *ebx = 0;
2689 *ecx = 0;
2690 *edx = 0;
2691 break;
c6dc6f63
AP		 2692 default:
2693 /* reserved values: zero */
2694 *eax = 0;
2695 *ebx = 0;
2696 *ecx = 0;
2697 *edx = 0;
2698 break;
2699 }
2700}
5fd2087a
AF		 2701
2702/* CPUClass::reset() */
2703static void x86_cpu_reset(CPUState *s)
2704{
2705 X86CPU *cpu = X86_CPU(s);
2706 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2707 CPUX86State *env = &cpu->env;
a114d25d
RH		 2708 target_ulong cr4;
2709 uint64_t xcr0;
c1958aea
AF		 2710 int i;
2711
5fd2087a
AF		 2712 xcc->parent_reset(s);
2713
43175fa9 2714 memset(env, 0, offsetof(CPUX86State, cpuid_level));
c1958aea 2715
00c8cb0a 2716 tlb_flush(s, 1);
c1958aea
AF		 2717
2718 env->old_exception = -1;
2719
2720 /* init to reset state */
2721
c1958aea
AF		 2722 env->hflags2 |= HF2_GIF_MASK;
2723
2724 cpu_x86_update_cr0(env, 0x60000010);
2725 env->a20_mask = ~0x0;
2726 env->smbase = 0x30000;
2727
2728 env->idt.limit = 0xffff;
2729 env->gdt.limit = 0xffff;
2730 env->ldt.limit = 0xffff;
2731 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2732 env->tr.limit = 0xffff;
2733 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2734
2735 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2736 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2737 DESC_R_MASK | DESC_A_MASK);
2738 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2739 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2740 DESC_A_MASK);
2741 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2742 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2743 DESC_A_MASK);
2744 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2745 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2746 DESC_A_MASK);
2747 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2748 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2749 DESC_A_MASK);
2750 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2751 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2752 DESC_A_MASK);
2753
2754 env->eip = 0xfff0;
2755 env->regs[R_EDX] = env->cpuid_version;
2756
2757 env->eflags = 0x2;
2758
2759 /* FPU init */
2760 for (i = 0; i < 8; i++) {
2761 env->fptags[i] = 1;
2762 }
5bde1407 2763 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 2764
2765 env->mxcsr = 0x1f80;
a114d25d
RH		 2766 /* All units are in INIT state. */
2767 env->xstate_bv = 0;
c1958aea
AF		 2768
2769 env->pat = 0x0007040600070406ULL;
2770 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2771
2772 memset(env->dr, 0, sizeof(env->dr));
2773 env->dr[6] = DR6_FIXED_1;
2774 env->dr[7] = DR7_FIXED_1;
b3310ab3 2775 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 2776 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 2777
a114d25d 2778 cr4 = 0;
cfc3b074 2779 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 2780
2781#ifdef CONFIG_USER_ONLY
2782 /* Enable all the features for user-mode. */
2783 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 2784 xcr0 |= XSTATE_SSE_MASK;
a114d25d 2785 }
0f70ed47
PB		 2786 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2787 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2788 if ((env->features[esa->feature] & esa->bits) == esa->bits) {
2789 xcr0 |= 1ull << i;
2790 }
a114d25d 2791 }
0f70ed47 2792
a114d25d
RH		 2793 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2794 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2795 }
07929f2a
RH		 2796 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2797 cr4 |= CR4_FSGSBASE_MASK;
2798 }
a114d25d
RH		 2799#endif
2800
2801 env->xcr0 = xcr0;
2802 cpu_x86_update_cr4(env, cr4);
0522604b 2803
9db2efd9
AW		 2804 /*
2805 * SDM 11.11.5 requires:
2806 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2807 * - IA32_MTRR_PHYSMASKn.V = 0
2808 * All other bits are undefined. For simplification, zero it all.
2809 */
2810 env->mtrr_deftype = 0;
2811 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2812 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2813
dd673288
IM		 2814#if !defined(CONFIG_USER_ONLY)
2815 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 2816 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 2817
259186a7 2818 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 2819
2820 if (kvm_enabled()) {
2821 kvm_arch_reset_vcpu(cpu);
2822 }
dd673288 2823#endif
5fd2087a
AF		 2824}
2825
dd673288
IM		 2826#ifndef CONFIG_USER_ONLY
2827bool cpu_is_bsp(X86CPU *cpu)
2828{
02e51483 2829 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 2830}
65dee380
IM		 2831
2832/* TODO: remove me, when reset over QOM tree is implemented */
2833static void x86_cpu_machine_reset_cb(void *opaque)
2834{
2835 X86CPU *cpu = opaque;
2836 cpu_reset(CPU(cpu));
2837}
dd673288
IM		 2838#endif
2839
de024815
AF		 2840static void mce_init(X86CPU *cpu)
2841{
2842 CPUX86State *cenv = &cpu->env;
2843 unsigned int bank;
2844
2845 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 2846 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 2847 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 2848 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2849 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 2850 cenv->mcg_ctl = ~(uint64_t)0;
2851 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2852 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2853 }
2854 }
2855}
2856
bdeec802 2857#ifndef CONFIG_USER_ONLY
d3c64d6a 2858static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
bdeec802 2859{
449994eb 2860 APICCommonState *apic;
bdeec802
IM		 2861 const char *apic_type = "apic";
2862
15eafc2e 2863 if (kvm_apic_in_kernel()) {
bdeec802
IM		 2864 apic_type = "kvm-apic";
2865 } else if (xen_enabled()) {
2866 apic_type = "xen-apic";
2867 }
2868
46232aaa 2869 cpu->apic_state = DEVICE(object_new(apic_type));
bdeec802 2870
6816b1b3
IM		 2871 object_property_add_child(OBJECT(cpu), "lapic",
2872 OBJECT(cpu->apic_state), &error_abort);
67e55caa 2873 object_unref(OBJECT(cpu->apic_state));
6816b1b3 2874
7e72a45c 2875 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
bdeec802 2876 /* TODO: convert to link<> */
02e51483 2877 apic = APIC_COMMON(cpu->apic_state);
60671e58 2878 apic->cpu = cpu;
8d42d2d3 2879 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 2880}
2881
2882static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2883{
8d42d2d3
CF		 2884 APICCommonState *apic;
2885 static bool apic_mmio_map_once;
2886
02e51483 2887 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 2888 return;
2889 }
6e8e2651
MA		 2890 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2891 errp);
8d42d2d3
CF		 2892
2893 /* Map APIC MMIO area */
2894 apic = APIC_COMMON(cpu->apic_state);
2895 if (!apic_mmio_map_once) {
2896 memory_region_add_subregion_overlap(get_system_memory(),
2897 apic->apicbase &
2898 MSR_IA32_APICBASE_BASE,
2899 &apic->io_memory,
2900 0x1000);
2901 apic_mmio_map_once = true;
2902 }
bdeec802 2903}
f809c605
PB		 2904
2905static void x86_cpu_machine_done(Notifier *n, void *unused)
2906{
2907 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2908 MemoryRegion *smram =
2909 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2910
2911 if (smram) {
2912 cpu->smram = g_new(MemoryRegion, 1);
2913 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2914 smram, 0, 1ull << 32);
2915 memory_region_set_enabled(cpu->smram, false);
2916 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2917 }
2918}
d3c64d6a
IM		 2919#else
2920static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2921{
2922}
bdeec802
IM		 2923#endif
2924
11f6fee5
DDAG		 2925/* Note: Only safe for use on x86(-64) hosts */
2926static uint32_t x86_host_phys_bits(void)
2927{
2928 uint32_t eax;
2929 uint32_t host_phys_bits;
2930
2931 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
2932 if (eax >= 0x80000008) {
2933 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
2934 /* Note: According to AMD doc 25481 rev 2.34 they have a field
2935 * at 23:16 that can specify a maximum physical address bits for
2936 * the guest that can override this value; but I've not seen
2937 * anything with that set.
2938 */
2939 host_phys_bits = eax & 0xff;
2940 } else {
2941 /* It's an odd 64 bit machine that doesn't have the leaf for
2942 * physical address bits; fall back to 36 that's most older
2943 * Intel.
2944 */
2945 host_phys_bits = 36;
2946 }
2947
2948 return host_phys_bits;
2949}
e48638fd
WH		 2950
2951#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2952 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2953 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2954#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2955 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2956 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2b6f294c 2957static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7a059953 2958{
14a10fc3 2959 CPUState *cs = CPU(dev);
2b6f294c
AF		 2960 X86CPU *cpu = X86_CPU(dev);
2961 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
b34d12d1 2962 CPUX86State *env = &cpu->env;
2b6f294c 2963 Error *local_err = NULL;
e48638fd 2964 static bool ht_warned;
dc15c051 2965 FeatureWord w;
b34d12d1 2966
104494ea
IM		 2967 if (xcc->kvm_required && !kvm_enabled()) {
2968 char *name = x86_cpu_class_get_model_name(xcc);
2969 error_setg(&local_err, "CPU model '%s' requires KVM", name);
2970 g_free(name);
2971 goto out;
2972 }
2973
d9c84f19 2974 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
9886e834
EH		 2975 error_setg(errp, "apic-id property was not initialized properly");
2976 return;
2977 }
2978
dc15c051
IM		 2979 /*TODO: cpu->host_features incorrectly overwrites features
2980 * set using "feat=on|off". Once we fix this, we can convert
2981 * plus_features & minus_features to global properties
2982 * inside x86_cpu_parse_featurestr() too.
2983 */
2984 if (cpu->host_features) {
2985 for (w = 0; w < FEATURE_WORDS; w++) {
2986 env->features[w] =
2987 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2988 }
2989 }
2990
2991 for (w = 0; w < FEATURE_WORDS; w++) {
2992 cpu->env.features[w] |= plus_features[w];
2993 cpu->env.features[w] &= ~minus_features[w];
2994 }
2995
0514ef2f 2996 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
b34d12d1
IM		 2997 env->cpuid_level = 7;
2998 }
7a059953 2999
9997cf7b
EH		 3000 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
3001 error_setg(&local_err,
3002 kvm_enabled() ?
3003 "Host doesn't support requested features" :
3004 "TCG doesn't support requested features");
3005 goto out;
3006 }
3007
9b15cd9e
IM		 3008 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3009 * CPUID[1].EDX.
3010 */
e48638fd 3011 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 3012 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3013 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 3014 & CPUID_EXT2_AMD_ALIASES);
3015 }
3016
11f6fee5
DDAG		 3017 /* For 64bit systems think about the number of physical bits to present.
3018 * ideally this should be the same as the host; anything other than matching
3019 * the host can cause incorrect guest behaviour.
3020 * QEMU used to pick the magic value of 40 bits that corresponds to
3021 * consumer AMD devices but nothing else.
3022 */
af45907a 3023 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
af45907a 3024 if (kvm_enabled()) {
11f6fee5
DDAG		 3025 uint32_t host_phys_bits = x86_host_phys_bits();
3026 static bool warned;
3027
3028 if (cpu->host_phys_bits) {
3029 /* The user asked for us to use the host physical bits */
3030 cpu->phys_bits = host_phys_bits;
3031 }
3032
3033 /* Print a warning if the user set it to a value that's not the
3034 * host value.
3035 */
3036 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3037 !warned) {
3038 error_report("Warning: Host physical bits (%u)"
3039 " does not match phys-bits property (%u)",
3040 host_phys_bits, cpu->phys_bits);
3041 warned = true;
3042 }
3043
3044 if (cpu->phys_bits &&
3045 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3046 cpu->phys_bits < 32)) {
af45907a
DDAG		 3047 error_setg(errp, "phys-bits should be between 32 and %u "
3048 " (but is %u)",
3049 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3050 return;
3051 }
3052 } else {
11f6fee5 3053 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 3054 error_setg(errp, "TCG only supports phys-bits=%u",
3055 TCG_PHYS_ADDR_BITS);
3056 return;
3057 }
3058 }
11f6fee5
DDAG		 3059 /* 0 means it was not explicitly set by the user (or by machine
3060 * compat_props or by the host code above). In this case, the default
3061 * is the value used by TCG (40).
3062 */
3063 if (cpu->phys_bits == 0) {
3064 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3065 }
af45907a
DDAG		 3066 } else {
3067 /* For 32 bit systems don't use the user set value, but keep
3068 * phys_bits consistent with what we tell the guest.
3069 */
3070 if (cpu->phys_bits != 0) {
3071 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3072 return;
3073 }
fefb41bf 3074
af45907a
DDAG		 3075 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3076 cpu->phys_bits = 36;
3077 } else {
3078 cpu->phys_bits = 32;
3079 }
3080 }
42ecabaa
EH		 3081 cpu_exec_init(cs, &error_abort);
3082
57f2453a
EH		 3083 if (tcg_enabled()) {
3084 tcg_x86_init();
3085 }
3086
65dee380
IM		 3087#ifndef CONFIG_USER_ONLY
3088 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 3089
0514ef2f 3090 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 3091 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 3092 if (local_err != NULL) {
4dc1f449 3093 goto out;
bdeec802
IM		 3094 }
3095 }
65dee380
IM		 3096#endif
3097
7a059953 3098 mce_init(cpu);
2001d0cd
PB		 3099
3100#ifndef CONFIG_USER_ONLY
3101 if (tcg_enabled()) {
56943e8c
PM		 3102 AddressSpace *newas = g_new(AddressSpace, 1);
3103
f809c605 3104 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 3105 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 3106
3107 /* Outer container... */
3108 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 3109 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 3110
3111 /* ... with two regions inside: normal system memory with low
3112 * priority, and...
3113 */
3114 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3115 get_system_memory(), 0, ~0ull);
3116 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3117 memory_region_set_enabled(cpu->cpu_as_mem, true);
56943e8c 3118 address_space_init(newas, cpu->cpu_as_root, "CPU");
12ebc9a7 3119 cs->num_ases = 1;
56943e8c 3120 cpu_address_space_init(cs, newas, 0);
f809c605
PB		 3121
3122 /* ... SMRAM with higher priority, linked from /machine/smram. */
3123 cpu->machine_done.notify = x86_cpu_machine_done;
3124 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 3125 }
3126#endif
3127
14a10fc3 3128 qemu_init_vcpu(cs);
d3c64d6a 3129
e48638fd
WH		 3130 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3131 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3132 * based on inputs (sockets,cores,threads), it is still better to gives
3133 * users a warning.
3134 *
3135 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3136 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3137 */
3138 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3139 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3140 " -smp options properly.");
3141 ht_warned = true;
3142 }
3143
d3c64d6a
IM		 3144 x86_cpu_apic_realize(cpu, &local_err);
3145 if (local_err != NULL) {
3146 goto out;
3147 }
14a10fc3 3148 cpu_reset(cs);
2b6f294c 3149
4dc1f449 3150 xcc->parent_realize(dev, &local_err);
2001d0cd 3151
4dc1f449
IM		 3152out:
3153 if (local_err != NULL) {
3154 error_propagate(errp, local_err);
3155 return;
3156 }
7a059953
AF		 3157}
3158
c884776e
IM		 3159static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3160{
3161 X86CPU *cpu = X86_CPU(dev);
3162
3163#ifndef CONFIG_USER_ONLY
3164 cpu_remove_sync(CPU(dev));
3165 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3166#endif
3167
3168 if (cpu->apic_state) {
3169 object_unparent(OBJECT(cpu->apic_state));
3170 cpu->apic_state = NULL;
3171 }
3172}
3173
38e5c119
EH		 3174typedef struct BitProperty {
3175 uint32_t *ptr;
3176 uint32_t mask;
3177} BitProperty;
3178
d7bce999
EB		 3179static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3180 void *opaque, Error **errp)
38e5c119
EH		 3181{
3182 BitProperty *fp = opaque;
3183 bool value = (*fp->ptr & fp->mask) == fp->mask;
51e72bc1 3184 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 3185}
3186
d7bce999
EB		 3187static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3188 void *opaque, Error **errp)
38e5c119
EH		 3189{
3190 DeviceState *dev = DEVICE(obj);
3191 BitProperty *fp = opaque;
3192 Error *local_err = NULL;
3193 bool value;
3194
3195 if (dev->realized) {
3196 qdev_prop_set_after_realize(dev, name, errp);
3197 return;
3198 }
3199
51e72bc1 3200 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 3201 if (local_err) {
3202 error_propagate(errp, local_err);
3203 return;
3204 }
3205
3206 if (value) {
3207 *fp->ptr |= fp->mask;
3208 } else {
3209 *fp->ptr &= ~fp->mask;
3210 }
3211}
3212
3213static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3214 void *opaque)
3215{
3216 BitProperty *prop = opaque;
3217 g_free(prop);
3218}
3219
3220/* Register a boolean property to get/set a single bit in a uint32_t field.
3221 *
3222 * The same property name can be registered multiple times to make it affect
3223 * multiple bits in the same FeatureWord. In that case, the getter will return
3224 * true only if all bits are set.
3225 */
3226static void x86_cpu_register_bit_prop(X86CPU *cpu,
3227 const char *prop_name,
3228 uint32_t *field,
3229 int bitnr)
3230{
3231 BitProperty *fp;
3232 ObjectProperty *op;
3233 uint32_t mask = (1UL << bitnr);
3234
3235 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3236 if (op) {
3237 fp = op->opaque;
3238 assert(fp->ptr == field);
3239 fp->mask |= mask;
3240 } else {
3241 fp = g_new0(BitProperty, 1);
3242 fp->ptr = field;
3243 fp->mask = mask;
3244 object_property_add(OBJECT(cpu), prop_name, "bool",
3245 x86_cpu_get_bit_prop,
3246 x86_cpu_set_bit_prop,
3247 x86_cpu_release_bit_prop, fp, &error_abort);
3248 }
3249}
3250
3251static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3252 FeatureWord w,
3253 int bitnr)
3254{
3255 Object *obj = OBJECT(cpu);
3256 int i;
3257 char **names;
3258 FeatureWordInfo *fi = &feature_word_info[w];
3259
3260 if (!fi->feat_names) {
3261 return;
3262 }
3263 if (!fi->feat_names[bitnr]) {
3264 return;
3265 }
3266
3267 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3268
3269 feat2prop(names[0]);
3270 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3271
3272 for (i = 1; names[i]; i++) {
3273 feat2prop(names[i]);
d461a44c 3274 object_property_add_alias(obj, names[i], obj, names[0],
38e5c119
EH		 3275 &error_abort);
3276 }
3277
3278 g_strfreev(names);
3279}
3280
de024815
AF		 3281static void x86_cpu_initfn(Object *obj)
3282{
55e5c285 3283 CPUState *cs = CPU(obj);
de024815 3284 X86CPU *cpu = X86_CPU(obj);
d940ee9b 3285 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 3286 CPUX86State *env = &cpu->env;
38e5c119 3287 FeatureWord w;
de024815 3288
c05efcb1 3289 cs->env_ptr = env;
71ad61d3
AF		 3290
3291 object_property_add(obj, "family", "int",
95b8519d 3292 x86_cpuid_version_get_family,
71ad61d3 3293 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 3294 object_property_add(obj, "model", "int",
67e30c83 3295 x86_cpuid_version_get_model,
c5291a4f 3296 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 3297 object_property_add(obj, "stepping", "int",
35112e41 3298 x86_cpuid_version_get_stepping,
036e2222 3299 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 3300 object_property_add_str(obj, "vendor",
3301 x86_cpuid_get_vendor,
3302 x86_cpuid_set_vendor, NULL);
938d4c25 3303 object_property_add_str(obj, "model-id",
63e886eb 3304 x86_cpuid_get_model_id,
938d4c25 3305 x86_cpuid_set_model_id, NULL);
89e48965
AF		 3306 object_property_add(obj, "tsc-frequency", "int",
3307 x86_cpuid_get_tsc_freq,
3308 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 3309 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3310 x86_cpu_get_feature_words,
7e5292b5
EH		 3311 NULL, NULL, (void *)env->features, NULL);
3312 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3313 x86_cpu_get_feature_words,
3314 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 3315
92067bf4 3316 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 3317
38e5c119
EH		 3318 for (w = 0; w < FEATURE_WORDS; w++) {
3319 int bitnr;
3320
3321 for (bitnr = 0; bitnr < 32; bitnr++) {
3322 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3323 }
3324 }
3325
d940ee9b 3326 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
de024815
AF		 3327}
3328
997395d3
IM		 3329static int64_t x86_cpu_get_arch_id(CPUState *cs)
3330{
3331 X86CPU *cpu = X86_CPU(cs);
997395d3 3332
7e72a45c 3333 return cpu->apic_id;
997395d3
IM		 3334}
3335
444d5590
AF		 3336static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3337{
3338 X86CPU *cpu = X86_CPU(cs);
3339
3340 return cpu->env.cr[0] & CR0_PG_MASK;
3341}
3342
f45748f1
AF		 3343static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3344{
3345 X86CPU *cpu = X86_CPU(cs);
3346
3347 cpu->env.eip = value;
3348}
3349
bdf7ae5b
AF		 3350static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3351{
3352 X86CPU *cpu = X86_CPU(cs);
3353
3354 cpu->env.eip = tb->pc - tb->cs_base;
3355}
3356
8c2e1b00
AF		 3357static bool x86_cpu_has_work(CPUState *cs)
3358{
3359 X86CPU *cpu = X86_CPU(cs);
3360 CPUX86State *env = &cpu->env;
3361
6220e900
PD		 3362 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3363 CPU_INTERRUPT_POLL)) &&
8c2e1b00
AF		 3364 (env->eflags & IF_MASK)) ||
3365 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3366 CPU_INTERRUPT_INIT |
3367 CPU_INTERRUPT_SIPI |
a9bad65d
PB		 3368 CPU_INTERRUPT_MCE)) ||
3369 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3370 !(env->hflags & HF_SMM_MASK));
8c2e1b00
AF		 3371}
3372
9337e3b6 3373static Property x86_cpu_properties[] = {
2da00e31
IM		 3374#ifdef CONFIG_USER_ONLY
3375 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3376 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 3377 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3378 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3379 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 3380#else
3381 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 3382 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3383 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3384 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 3385#endif
9337e3b6 3386 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 3387 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 3388 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 3389 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 3390 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 3391 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 3392 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 3393 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 3394 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 3395 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 3396 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
15e41345 3397 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 3398 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 3399 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 3400 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 3401 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 3402 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
b9472b76
EH		 3403 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3404 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
01431f3c 3405 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
1c4a55db 3406 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 3407 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 3408 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 3409 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
9337e3b6
EH		 3410 DEFINE_PROP_END_OF_LIST()
3411};
3412
5fd2087a
AF		 3413static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3414{
3415 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3416 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 3417 DeviceClass *dc = DEVICE_CLASS(oc);
3418
3419 xcc->parent_realize = dc->realize;
3420 dc->realize = x86_cpu_realizefn;
c884776e 3421 dc->unrealize = x86_cpu_unrealizefn;
9337e3b6 3422 dc->props = x86_cpu_properties;
5fd2087a
AF		 3423
3424 xcc->parent_reset = cc->reset;
3425 cc->reset = x86_cpu_reset;
91b1df8c 3426 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 3427
500050d1 3428 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 3429 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 3430 cc->has_work = x86_cpu_has_work;
97a8ea5a 3431 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 3432 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
878096ee 3433 cc->dump_state = x86_cpu_dump_state;
f45748f1 3434 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 3435 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 3436 cc->gdb_read_register = x86_cpu_gdb_read_register;
3437 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 3438 cc->get_arch_id = x86_cpu_get_arch_id;
3439 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 3440#ifdef CONFIG_USER_ONLY
3441 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3442#else
a23bbfda 3443 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 3444 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 3445 cc->write_elf64_note = x86_cpu_write_elf64_note;
3446 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3447 cc->write_elf32_note = x86_cpu_write_elf32_note;
3448 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 3449 cc->vmsd = &vmstate_x86_cpu;
c72bf468 3450#endif
a0e372f0 3451 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
86025ee4
PM		 3452#ifndef CONFIG_USER_ONLY
3453 cc->debug_excp_handler = breakpoint_handler;
3454#endif
374e0cd4
RH		 3455 cc->cpu_exec_enter = x86_cpu_exec_enter;
3456 cc->cpu_exec_exit = x86_cpu_exec_exit;
4c315c27 3457
edd12111 3458 dc->cannot_instantiate_with_device_add_yet = false;
4c315c27
MA		 3459 /*
3460 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3461 * object in cpus -> dangling pointer after final object_unref().
3462 */
3463 dc->cannot_destroy_with_object_finalize_yet = true;
5fd2087a
AF		 3464}
3465
3466static const TypeInfo x86_cpu_type_info = {
3467 .name = TYPE_X86_CPU,
3468 .parent = TYPE_CPU,
3469 .instance_size = sizeof(X86CPU),
de024815 3470 .instance_init = x86_cpu_initfn,
d940ee9b 3471 .abstract = true,
5fd2087a
AF		 3472 .class_size = sizeof(X86CPUClass),
3473 .class_init = x86_cpu_common_class_init,
3474};
3475
3476static void x86_cpu_register_types(void)
3477{
d940ee9b
EH		 3478 int i;
3479
5fd2087a 3480 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 3481 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3482 x86_register_cpudef_type(&builtin_x86_defs[i]);
3483 }
3484#ifdef CONFIG_KVM
3485 type_register_static(&host_x86_cpu_type_info);
3486#endif
5fd2087a
AF		 3487}
3488
3489type_init(x86_cpu_register_types)
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