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kvm/x86: Hyper-V HV_X64_MSR_VP_RUNTIME support
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
af658dca 31#include <linux/trace_events.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
952f07ec 43#include <asm/fpu/internal.h>
d7cd9796 44#include <asm/perf_event.h>
81908bf4 45#include <asm/debugreg.h>
8f536b76 46#include <asm/kexec.h>
dab2087d 47#include <asm/apic.h>
6aa8b732 48
229456fc 49#include "trace.h"
25462f7f 50#include "pmu.h"
229456fc 51
4ecac3fd 52#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 53#define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 55
6aa8b732
AK		 56MODULE_AUTHOR("Qumranet");
57MODULE_LICENSE("GPL");
58
e9bda3b3
JT		 59static const struct x86_cpu_id vmx_cpu_id[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX),
61 {}
62};
63MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
64
476bc001 65static bool __read_mostly enable_vpid = 1;
736caefe 66module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 67
476bc001 68static bool __read_mostly flexpriority_enabled = 1;
736caefe 69module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 70
476bc001 71static bool __read_mostly enable_ept = 1;
736caefe 72module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 73
476bc001 74static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 75module_param_named(unrestricted_guest,
76 enable_unrestricted_guest, bool, S_IRUGO);
77
83c3a331
XH		 78static bool __read_mostly enable_ept_ad_bits = 1;
79module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
80
a27685c3 81static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 82module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 83
476bc001 84static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 85module_param(vmm_exclusive, bool, S_IRUGO);
86
476bc001 87static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 88module_param(fasteoi, bool, S_IRUGO);
89
5a71785d 90static bool __read_mostly enable_apicv = 1;
01e439be 91module_param(enable_apicv, bool, S_IRUGO);
83d4c286 92
abc4fc58
AG		 93static bool __read_mostly enable_shadow_vmcs = 1;
94module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 95/*
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
99 */
476bc001 100static bool __read_mostly nested = 0;
801d3424
NHE		 101module_param(nested, bool, S_IRUGO);
102
20300099
WL		 103static u64 __read_mostly host_xss;
104
843e4330
KH		 105static bool __read_mostly enable_pml = 1;
106module_param_named(pml, enable_pml, bool, S_IRUGO);
107
5037878e
GN		 108#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 110#define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 112#define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 115
cdc0e244
AK		 116#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
118
78ac8b47
AK		 119#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
120
f4124500
JK		 121#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
122
4b8d54f9
ZE		 123/*
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 127 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
133 */
b4a2d31d
RK		 134#define KVM_VMX_DEFAULT_PLE_GAP 128
135#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
140
4b8d54f9
ZE		 141static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
142module_param(ple_gap, int, S_IRUGO);
143
144static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
145module_param(ple_window, int, S_IRUGO);
146
b4a2d31d
RK		 147/* Default doubles per-vcpu window every exit. */
148static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
149module_param(ple_window_grow, int, S_IRUGO);
150
151/* Default resets per-vcpu window every exit to ple_window. */
152static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
153module_param(ple_window_shrink, int, S_IRUGO);
154
155/* Default is to compute the maximum so we can never overflow. */
156static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
158module_param(ple_window_max, int, S_IRUGO);
159
83287ea4
AK		 160extern const ulong vmx_return;
161
8bf00a52 162#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 163#define VMCS02_POOL_SIZE 1
61d2ef2c 164
a2fa3e9f
GH		 165struct vmcs {
166 u32 revision_id;
167 u32 abort;
168 char data[0];
169};
170
d462b819
NHE		 171/*
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
175 */
176struct loaded_vmcs {
177 struct vmcs *vmcs;
178 int cpu;
179 int launched;
180 struct list_head loaded_vmcss_on_cpu_link;
181};
182
26bb0981
AK		 183struct shared_msr_entry {
184 unsigned index;
185 u64 data;
d5696725 186 u64 mask;
26bb0981
AK		 187};
188
a9d30f33
NHE		 189/*
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
201 */
22bd0358 202typedef u64 natural_width;
a9d30f33
NHE		 203struct __packed vmcs12 {
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
206 */
207 u32 revision_id;
208 u32 abort;
22bd0358 209
27d6c865
NHE		 210 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding[7]; /* room for future expansion */
212
22bd0358
NHE		 213 u64 io_bitmap_a;
214 u64 io_bitmap_b;
215 u64 msr_bitmap;
216 u64 vm_exit_msr_store_addr;
217 u64 vm_exit_msr_load_addr;
218 u64 vm_entry_msr_load_addr;
219 u64 tsc_offset;
220 u64 virtual_apic_page_addr;
221 u64 apic_access_addr;
705699a1 222 u64 posted_intr_desc_addr;
22bd0358 223 u64 ept_pointer;
608406e2
WV		 224 u64 eoi_exit_bitmap0;
225 u64 eoi_exit_bitmap1;
226 u64 eoi_exit_bitmap2;
227 u64 eoi_exit_bitmap3;
81dc01f7 228 u64 xss_exit_bitmap;
22bd0358
NHE		 229 u64 guest_physical_address;
230 u64 vmcs_link_pointer;
231 u64 guest_ia32_debugctl;
232 u64 guest_ia32_pat;
233 u64 guest_ia32_efer;
234 u64 guest_ia32_perf_global_ctrl;
235 u64 guest_pdptr0;
236 u64 guest_pdptr1;
237 u64 guest_pdptr2;
238 u64 guest_pdptr3;
36be0b9d 239 u64 guest_bndcfgs;
22bd0358
NHE		 240 u64 host_ia32_pat;
241 u64 host_ia32_efer;
242 u64 host_ia32_perf_global_ctrl;
243 u64 padding64[8]; /* room for future expansion */
244 /*
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
249 */
250 natural_width cr0_guest_host_mask;
251 natural_width cr4_guest_host_mask;
252 natural_width cr0_read_shadow;
253 natural_width cr4_read_shadow;
254 natural_width cr3_target_value0;
255 natural_width cr3_target_value1;
256 natural_width cr3_target_value2;
257 natural_width cr3_target_value3;
258 natural_width exit_qualification;
259 natural_width guest_linear_address;
260 natural_width guest_cr0;
261 natural_width guest_cr3;
262 natural_width guest_cr4;
263 natural_width guest_es_base;
264 natural_width guest_cs_base;
265 natural_width guest_ss_base;
266 natural_width guest_ds_base;
267 natural_width guest_fs_base;
268 natural_width guest_gs_base;
269 natural_width guest_ldtr_base;
270 natural_width guest_tr_base;
271 natural_width guest_gdtr_base;
272 natural_width guest_idtr_base;
273 natural_width guest_dr7;
274 natural_width guest_rsp;
275 natural_width guest_rip;
276 natural_width guest_rflags;
277 natural_width guest_pending_dbg_exceptions;
278 natural_width guest_sysenter_esp;
279 natural_width guest_sysenter_eip;
280 natural_width host_cr0;
281 natural_width host_cr3;
282 natural_width host_cr4;
283 natural_width host_fs_base;
284 natural_width host_gs_base;
285 natural_width host_tr_base;
286 natural_width host_gdtr_base;
287 natural_width host_idtr_base;
288 natural_width host_ia32_sysenter_esp;
289 natural_width host_ia32_sysenter_eip;
290 natural_width host_rsp;
291 natural_width host_rip;
292 natural_width paddingl[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control;
294 u32 cpu_based_vm_exec_control;
295 u32 exception_bitmap;
296 u32 page_fault_error_code_mask;
297 u32 page_fault_error_code_match;
298 u32 cr3_target_count;
299 u32 vm_exit_controls;
300 u32 vm_exit_msr_store_count;
301 u32 vm_exit_msr_load_count;
302 u32 vm_entry_controls;
303 u32 vm_entry_msr_load_count;
304 u32 vm_entry_intr_info_field;
305 u32 vm_entry_exception_error_code;
306 u32 vm_entry_instruction_len;
307 u32 tpr_threshold;
308 u32 secondary_vm_exec_control;
309 u32 vm_instruction_error;
310 u32 vm_exit_reason;
311 u32 vm_exit_intr_info;
312 u32 vm_exit_intr_error_code;
313 u32 idt_vectoring_info_field;
314 u32 idt_vectoring_error_code;
315 u32 vm_exit_instruction_len;
316 u32 vmx_instruction_info;
317 u32 guest_es_limit;
318 u32 guest_cs_limit;
319 u32 guest_ss_limit;
320 u32 guest_ds_limit;
321 u32 guest_fs_limit;
322 u32 guest_gs_limit;
323 u32 guest_ldtr_limit;
324 u32 guest_tr_limit;
325 u32 guest_gdtr_limit;
326 u32 guest_idtr_limit;
327 u32 guest_es_ar_bytes;
328 u32 guest_cs_ar_bytes;
329 u32 guest_ss_ar_bytes;
330 u32 guest_ds_ar_bytes;
331 u32 guest_fs_ar_bytes;
332 u32 guest_gs_ar_bytes;
333 u32 guest_ldtr_ar_bytes;
334 u32 guest_tr_ar_bytes;
335 u32 guest_interruptibility_info;
336 u32 guest_activity_state;
337 u32 guest_sysenter_cs;
338 u32 host_ia32_sysenter_cs;
0238ea91
JK		 339 u32 vmx_preemption_timer_value;
340 u32 padding32[7]; /* room for future expansion */
22bd0358 341 u16 virtual_processor_id;
705699a1 342 u16 posted_intr_nv;
22bd0358
NHE		 343 u16 guest_es_selector;
344 u16 guest_cs_selector;
345 u16 guest_ss_selector;
346 u16 guest_ds_selector;
347 u16 guest_fs_selector;
348 u16 guest_gs_selector;
349 u16 guest_ldtr_selector;
350 u16 guest_tr_selector;
608406e2 351 u16 guest_intr_status;
22bd0358
NHE		 352 u16 host_es_selector;
353 u16 host_cs_selector;
354 u16 host_ss_selector;
355 u16 host_ds_selector;
356 u16 host_fs_selector;
357 u16 host_gs_selector;
358 u16 host_tr_selector;
a9d30f33
NHE		 359};
360
361/*
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
365 */
366#define VMCS12_REVISION 0x11e57ed0
367
368/*
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
372 */
373#define VMCS12_SIZE 0x1000
374
ff2f6fe9
NHE		 375/* Used to remember the last vmcs02 used for some recently used vmcs12s */
376struct vmcs02_list {
377 struct list_head list;
378 gpa_t vmptr;
379 struct loaded_vmcs vmcs02;
380};
381
ec378aee
NHE		 382/*
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
385 */
386struct nested_vmx {
387 /* Has the level1 guest done vmxon? */
388 bool vmxon;
3573e22c 389 gpa_t vmxon_ptr;
a9d30f33
NHE		 390
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
392 gpa_t current_vmptr;
393 /* The host-usable pointer to the above */
394 struct page *current_vmcs12_page;
395 struct vmcs12 *current_vmcs12;
8de48833 396 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 397 /*
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
400 */
401 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 402
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool;
405 int vmcs02_num;
fe3ef05c 406 u64 vmcs01_tsc_offset;
644d711a
NHE		 407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending;
fe3ef05c
NHE		 409 /*
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
412 */
413 struct page *apic_access_page;
a7c0b07d 414 struct page *virtual_apic_page;
705699a1
WV		 415 struct page *pi_desc_page;
416 struct pi_desc *pi_desc;
417 bool pi_pending;
418 u16 posted_intr_nv;
b3897a49 419 u64 msr_ia32_feature_control;
f4124500
JK		 420
421 struct hrtimer preemption_timer;
422 bool preemption_timer_expired;
2996fca0
JK		 423
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
425 u64 vmcs01_debugctl;
b9c237bb
WV		 426
427 u32 nested_vmx_procbased_ctls_low;
428 u32 nested_vmx_procbased_ctls_high;
429 u32 nested_vmx_true_procbased_ctls_low;
430 u32 nested_vmx_secondary_ctls_low;
431 u32 nested_vmx_secondary_ctls_high;
432 u32 nested_vmx_pinbased_ctls_low;
433 u32 nested_vmx_pinbased_ctls_high;
434 u32 nested_vmx_exit_ctls_low;
435 u32 nested_vmx_exit_ctls_high;
436 u32 nested_vmx_true_exit_ctls_low;
437 u32 nested_vmx_entry_ctls_low;
438 u32 nested_vmx_entry_ctls_high;
439 u32 nested_vmx_true_entry_ctls_low;
440 u32 nested_vmx_misc_low;
441 u32 nested_vmx_misc_high;
442 u32 nested_vmx_ept_caps;
ec378aee
NHE		 443};
444
01e439be
YZ		 445#define POSTED_INTR_ON 0
446/* Posted-Interrupt Descriptor */
447struct pi_desc {
448 u32 pir[8]; /* Posted interrupt requested */
449 u32 control; /* bit 0 of control is outstanding notification bit */
450 u32 rsvd[7];
451} __aligned(64);
452
a20ed54d
YZ		 453static bool pi_test_and_set_on(struct pi_desc *pi_desc)
454{
455 return test_and_set_bit(POSTED_INTR_ON,
456 (unsigned long *)&pi_desc->control);
457}
458
459static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
460{
461 return test_and_clear_bit(POSTED_INTR_ON,
462 (unsigned long *)&pi_desc->control);
463}
464
465static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
466{
467 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
468}
469
a2fa3e9f 470struct vcpu_vmx {
fb3f0f51 471 struct kvm_vcpu vcpu;
313dbd49 472 unsigned long host_rsp;
29bd8a78 473 u8 fail;
9d58b931 474 bool nmi_known_unmasked;
51aa01d1 475 u32 exit_intr_info;
1155f76a 476 u32 idt_vectoring_info;
6de12732 477 ulong rflags;
26bb0981 478 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 479 int nmsrs;
480 int save_nmsrs;
a547c6db 481 unsigned long host_idt_base;
a2fa3e9f 482#ifdef CONFIG_X86_64
44ea2b17
AK		 483 u64 msr_host_kernel_gs_base;
484 u64 msr_guest_kernel_gs_base;
a2fa3e9f 485#endif
2961e876
GN		 486 u32 vm_entry_controls_shadow;
487 u32 vm_exit_controls_shadow;
d462b819
NHE		 488 /*
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
492 */
493 struct loaded_vmcs vmcs01;
494 struct loaded_vmcs *loaded_vmcs;
495 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 496 struct msr_autoload {
497 unsigned nr;
498 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
499 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
500 } msr_autoload;
a2fa3e9f
GH		 501 struct {
502 int loaded;
503 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 504#ifdef CONFIG_X86_64
505 u16 ds_sel, es_sel;
506#endif
152d3f2f
LV		 507 int gs_ldt_reload_needed;
508 int fs_reload_needed;
da8999d3 509 u64 msr_host_bndcfgs;
d974baa3 510 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 511 } host_state;
9c8cba37 512 struct {
7ffd92c5 513 int vm86_active;
78ac8b47 514 ulong save_rflags;
f5f7b2fe
AK		 515 struct kvm_segment segs[8];
516 } rmode;
517 struct {
518 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 519 struct kvm_save_segment {
520 u16 selector;
521 unsigned long base;
522 u32 limit;
523 u32 ar;
f5f7b2fe 524 } seg[8];
2fb92db1 525 } segment_cache;
2384d2b3 526 int vpid;
04fa4d32 527 bool emulation_required;
3b86cd99
JK		 528
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked;
531 ktime_t entry_time;
532 s64 vnmi_blocked_time;
a0861c02 533 u32 exit_reason;
4e47c7a6
SY		 534
535 bool rdtscp_enabled;
ec378aee 536
01e439be
YZ		 537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc;
539
ec378aee
NHE		 540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested;
a7653ecd
RK		 542
543 /* Dynamic PLE window. */
544 int ple_window;
545 bool ple_window_dirty;
843e4330
KH		 546
547 /* Support for PML */
548#define PML_ENTITY_NUM 512
549 struct page *pml_pg;
a2fa3e9f
GH		 550};
551
2fb92db1
AK		 552enum segment_cache_field {
553 SEG_FIELD_SEL = 0,
554 SEG_FIELD_BASE = 1,
555 SEG_FIELD_LIMIT = 2,
556 SEG_FIELD_AR = 3,
557
558 SEG_FIELD_NR = 4
559};
560
a2fa3e9f
GH		 561static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
562{
fb3f0f51 563 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 564}
565
22bd0358
NHE		 566#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
570
4607c2d7 571
fe2b201b 572static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 573 /*
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
584 */
585 VM_EXIT_REASON,
586 VM_EXIT_INTR_INFO,
587 VM_EXIT_INSTRUCTION_LEN,
588 IDT_VECTORING_INFO_FIELD,
589 IDT_VECTORING_ERROR_CODE,
590 VM_EXIT_INTR_ERROR_CODE,
591 EXIT_QUALIFICATION,
592 GUEST_LINEAR_ADDRESS,
593 GUEST_PHYSICAL_ADDRESS
594};
fe2b201b 595static int max_shadow_read_only_fields =
4607c2d7
AG		 596 ARRAY_SIZE(shadow_read_only_fields);
597
fe2b201b 598static unsigned long shadow_read_write_fields[] = {
a7c0b07d 599 TPR_THRESHOLD,
4607c2d7
AG		 600 GUEST_RIP,
601 GUEST_RSP,
602 GUEST_CR0,
603 GUEST_CR3,
604 GUEST_CR4,
605 GUEST_INTERRUPTIBILITY_INFO,
606 GUEST_RFLAGS,
607 GUEST_CS_SELECTOR,
608 GUEST_CS_AR_BYTES,
609 GUEST_CS_LIMIT,
610 GUEST_CS_BASE,
611 GUEST_ES_BASE,
36be0b9d 612 GUEST_BNDCFGS,
4607c2d7
AG		 613 CR0_GUEST_HOST_MASK,
614 CR0_READ_SHADOW,
615 CR4_READ_SHADOW,
616 TSC_OFFSET,
617 EXCEPTION_BITMAP,
618 CPU_BASED_VM_EXEC_CONTROL,
619 VM_ENTRY_EXCEPTION_ERROR_CODE,
620 VM_ENTRY_INTR_INFO_FIELD,
621 VM_ENTRY_INSTRUCTION_LEN,
622 VM_ENTRY_EXCEPTION_ERROR_CODE,
623 HOST_FS_BASE,
624 HOST_GS_BASE,
625 HOST_FS_SELECTOR,
626 HOST_GS_SELECTOR
627};
fe2b201b 628static int max_shadow_read_write_fields =
4607c2d7
AG		 629 ARRAY_SIZE(shadow_read_write_fields);
630
772e0318 631static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358 632 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
705699a1 633 FIELD(POSTED_INTR_NV, posted_intr_nv),
22bd0358
NHE		 634 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
635 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
636 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
637 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
638 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
639 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
640 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
641 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
608406e2 642 FIELD(GUEST_INTR_STATUS, guest_intr_status),
22bd0358
NHE		 643 FIELD(HOST_ES_SELECTOR, host_es_selector),
644 FIELD(HOST_CS_SELECTOR, host_cs_selector),
645 FIELD(HOST_SS_SELECTOR, host_ss_selector),
646 FIELD(HOST_DS_SELECTOR, host_ds_selector),
647 FIELD(HOST_FS_SELECTOR, host_fs_selector),
648 FIELD(HOST_GS_SELECTOR, host_gs_selector),
649 FIELD(HOST_TR_SELECTOR, host_tr_selector),
650 FIELD64(IO_BITMAP_A, io_bitmap_a),
651 FIELD64(IO_BITMAP_B, io_bitmap_b),
652 FIELD64(MSR_BITMAP, msr_bitmap),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
656 FIELD64(TSC_OFFSET, tsc_offset),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
658 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
705699a1 659 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
22bd0358 660 FIELD64(EPT_POINTER, ept_pointer),
608406e2
WV		 661 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
662 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
663 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
664 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
81dc01f7 665 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 666 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
667 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
668 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
669 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
670 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
672 FIELD64(GUEST_PDPTR0, guest_pdptr0),
673 FIELD64(GUEST_PDPTR1, guest_pdptr1),
674 FIELD64(GUEST_PDPTR2, guest_pdptr2),
675 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 676 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 677 FIELD64(HOST_IA32_PAT, host_ia32_pat),
678 FIELD64(HOST_IA32_EFER, host_ia32_efer),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
682 FIELD(EXCEPTION_BITMAP, exception_bitmap),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
685 FIELD(CR3_TARGET_COUNT, cr3_target_count),
686 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
687 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
689 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
694 FIELD(TPR_THRESHOLD, tpr_threshold),
695 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
696 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
697 FIELD(VM_EXIT_REASON, vm_exit_reason),
698 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
699 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
700 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
701 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
702 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
703 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
704 FIELD(GUEST_ES_LIMIT, guest_es_limit),
705 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
706 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
707 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
708 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
709 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
710 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
711 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
712 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
713 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
714 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
715 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
716 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
717 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
718 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
719 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
720 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
721 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
723 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
724 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
725 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 726 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 727 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
728 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
729 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
730 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
731 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
732 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
733 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
734 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
735 FIELD(EXIT_QUALIFICATION, exit_qualification),
736 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
737 FIELD(GUEST_CR0, guest_cr0),
738 FIELD(GUEST_CR3, guest_cr3),
739 FIELD(GUEST_CR4, guest_cr4),
740 FIELD(GUEST_ES_BASE, guest_es_base),
741 FIELD(GUEST_CS_BASE, guest_cs_base),
742 FIELD(GUEST_SS_BASE, guest_ss_base),
743 FIELD(GUEST_DS_BASE, guest_ds_base),
744 FIELD(GUEST_FS_BASE, guest_fs_base),
745 FIELD(GUEST_GS_BASE, guest_gs_base),
746 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
747 FIELD(GUEST_TR_BASE, guest_tr_base),
748 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
749 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
750 FIELD(GUEST_DR7, guest_dr7),
751 FIELD(GUEST_RSP, guest_rsp),
752 FIELD(GUEST_RIP, guest_rip),
753 FIELD(GUEST_RFLAGS, guest_rflags),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
755 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
756 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
757 FIELD(HOST_CR0, host_cr0),
758 FIELD(HOST_CR3, host_cr3),
759 FIELD(HOST_CR4, host_cr4),
760 FIELD(HOST_FS_BASE, host_fs_base),
761 FIELD(HOST_GS_BASE, host_gs_base),
762 FIELD(HOST_TR_BASE, host_tr_base),
763 FIELD(HOST_GDTR_BASE, host_gdtr_base),
764 FIELD(HOST_IDTR_BASE, host_idtr_base),
765 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
766 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
767 FIELD(HOST_RSP, host_rsp),
768 FIELD(HOST_RIP, host_rip),
769};
22bd0358
NHE		 770
771static inline short vmcs_field_to_offset(unsigned long field)
772{
a2ae9df7
PB		 773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
774
775 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
776 vmcs_field_to_offset_table[field] == 0)
777 return -ENOENT;
778
22bd0358
NHE		 779 return vmcs_field_to_offset_table[field];
780}
781
a9d30f33
NHE		 782static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
783{
784 return to_vmx(vcpu)->nested.current_vmcs12;
785}
786
787static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
788{
54bf36aa 789 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
32cad84f 790 if (is_error_page(page))
a9d30f33 791 return NULL;
32cad84f 792
a9d30f33
NHE		 793 return page;
794}
795
796static void nested_release_page(struct page *page)
797{
798 kvm_release_page_dirty(page);
799}
800
801static void nested_release_page_clean(struct page *page)
802{
803 kvm_release_page_clean(page);
804}
805
bfd0a56b 806static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 807static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 808static void kvm_cpu_vmxon(u64 addr);
809static void kvm_cpu_vmxoff(void);
93c4adc7 810static bool vmx_mpx_supported(void);
f53cd63c 811static bool vmx_xsaves_supported(void);
d50ab6c1 812static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
776e58ea 813static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 814static void vmx_set_segment(struct kvm_vcpu *vcpu,
815 struct kvm_segment *var, int seg);
816static void vmx_get_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg);
d99e4152
GN		 818static bool guest_state_valid(struct kvm_vcpu *vcpu);
819static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 820static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 821static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 822static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 823static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 824
6aa8b732
AK		 825static DEFINE_PER_CPU(struct vmcs *, vmxarea);
826static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 827/*
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
830 */
831static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 832static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 833
3e7c73e9
AK		 834static unsigned long *vmx_io_bitmap_a;
835static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 836static unsigned long *vmx_msr_bitmap_legacy;
837static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 838static unsigned long *vmx_msr_bitmap_legacy_x2apic;
839static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 840static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 841static unsigned long *vmx_vmread_bitmap;
842static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 843
110312c8 844static bool cpu_has_load_ia32_efer;
8bf00a52 845static bool cpu_has_load_perf_global_ctrl;
110312c8 846
2384d2b3
SY		 847static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
848static DEFINE_SPINLOCK(vmx_vpid_lock);
849
1c3d14fe 850static struct vmcs_config {
6aa8b732
AK		 851 int size;
852 int order;
853 u32 revision_id;
1c3d14fe
YS		 854 u32 pin_based_exec_ctrl;
855 u32 cpu_based_exec_ctrl;
f78e0e2e 856 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 857 u32 vmexit_ctrl;
858 u32 vmentry_ctrl;
859} vmcs_config;
6aa8b732 860
efff9e53 861static struct vmx_capability {
d56f546d
SY		 862 u32 ept;
863 u32 vpid;
864} vmx_capability;
865
6aa8b732
AK		 866#define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
872 }
873
772e0318 874static const struct kvm_vmx_segment_field {
6aa8b732
AK		 875 unsigned selector;
876 unsigned base;
877 unsigned limit;
878 unsigned ar_bytes;
879} kvm_vmx_segment_fields[] = {
880 VMX_SEGMENT_FIELD(CS),
881 VMX_SEGMENT_FIELD(DS),
882 VMX_SEGMENT_FIELD(ES),
883 VMX_SEGMENT_FIELD(FS),
884 VMX_SEGMENT_FIELD(GS),
885 VMX_SEGMENT_FIELD(SS),
886 VMX_SEGMENT_FIELD(TR),
887 VMX_SEGMENT_FIELD(LDTR),
888};
889
26bb0981
AK		 890static u64 host_efer;
891
6de4f3ad
AK		 892static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
893
4d56c8a7 894/*
8c06585d 895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 896 * away by decrementing the array size.
897 */
6aa8b732 898static const u32 vmx_msr_index[] = {
05b3e0c2 899#ifdef CONFIG_X86_64
44ea2b17 900 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 901#endif
8c06585d 902 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 903};
6aa8b732 904
31299944 905static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
908 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 909 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 910}
911
31299944 912static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 913{
914 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
915 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 916 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 917}
918
31299944 919static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 920{
921 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
922 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 923 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 924}
925
31299944 926static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 927{
928 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
929 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
930}
931
31299944 932static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 933{
934 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
935 INTR_INFO_VALID_MASK)) ==
936 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
937}
938
31299944 939static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 940{
04547156 941 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 942}
943
31299944 944static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 945{
04547156 946 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 947}
948
35754c98 949static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
6e5d865c 950{
35754c98 951 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
6e5d865c
YS		 952}
953
31299944 954static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 955{
04547156
SY		 956 return vmcs_config.cpu_based_exec_ctrl &
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 958}
959
774ead3a 960static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 961{
04547156
SY		 962 return vmcs_config.cpu_based_2nd_exec_ctrl &
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
964}
965
8d14695f
YZ		 966static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
967{
968 return vmcs_config.cpu_based_2nd_exec_ctrl &
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
970}
971
83d4c286
YZ		 972static inline bool cpu_has_vmx_apic_register_virt(void)
973{
974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_APIC_REGISTER_VIRT;
976}
977
c7c9c56c
YZ		 978static inline bool cpu_has_vmx_virtual_intr_delivery(void)
979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
982}
983
01e439be
YZ		 984static inline bool cpu_has_vmx_posted_intr(void)
985{
986 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
987}
988
989static inline bool cpu_has_vmx_apicv(void)
990{
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
994}
995
04547156
SY		 996static inline bool cpu_has_vmx_flexpriority(void)
997{
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 1000}
1001
e799794e
MT		 1002static inline bool cpu_has_vmx_ept_execute_only(void)
1003{
31299944 1004 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 1005}
1006
e799794e
MT		 1007static inline bool cpu_has_vmx_ept_2m_page(void)
1008{
31299944 1009 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 1010}
1011
878403b7
SY		 1012static inline bool cpu_has_vmx_ept_1g_page(void)
1013{
31299944 1014 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 1015}
1016
4bc9b982
SY		 1017static inline bool cpu_has_vmx_ept_4levels(void)
1018{
1019 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1020}
1021
83c3a331
XH		 1022static inline bool cpu_has_vmx_ept_ad_bits(void)
1023{
1024 return vmx_capability.ept & VMX_EPT_AD_BIT;
1025}
1026
31299944 1027static inline bool cpu_has_vmx_invept_context(void)
d56f546d 1028{
31299944 1029 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 1030}
1031
31299944 1032static inline bool cpu_has_vmx_invept_global(void)
d56f546d 1033{
31299944 1034 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 1035}
1036
518c8aee
GJ		 1037static inline bool cpu_has_vmx_invvpid_single(void)
1038{
1039 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1040}
1041
b9d762fa
GJ		 1042static inline bool cpu_has_vmx_invvpid_global(void)
1043{
1044 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1045}
1046
31299944 1047static inline bool cpu_has_vmx_ept(void)
d56f546d 1048{
04547156
SY		 1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1051}
1052
31299944 1053static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1054{
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1057}
1058
31299944 1059static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1060{
1061 return vmcs_config.cpu_based_2nd_exec_ctrl &
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1063}
1064
35754c98 1065static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 1066{
35754c98 1067 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 1068}
1069
31299944 1070static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1071{
04547156
SY		 1072 return vmcs_config.cpu_based_2nd_exec_ctrl &
1073 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1074}
1075
31299944 1076static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1077{
1078 return vmcs_config.cpu_based_2nd_exec_ctrl &
1079 SECONDARY_EXEC_RDTSCP;
1080}
1081
ad756a16
MJ		 1082static inline bool cpu_has_vmx_invpcid(void)
1083{
1084 return vmcs_config.cpu_based_2nd_exec_ctrl &
1085 SECONDARY_EXEC_ENABLE_INVPCID;
1086}
1087
31299944 1088static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1089{
1090 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1091}
1092
f5f48ee1
SY		 1093static inline bool cpu_has_vmx_wbinvd_exit(void)
1094{
1095 return vmcs_config.cpu_based_2nd_exec_ctrl &
1096 SECONDARY_EXEC_WBINVD_EXITING;
1097}
1098
abc4fc58
AG		 1099static inline bool cpu_has_vmx_shadow_vmcs(void)
1100{
1101 u64 vmx_msr;
1102 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1105 return false;
1106
1107 return vmcs_config.cpu_based_2nd_exec_ctrl &
1108 SECONDARY_EXEC_SHADOW_VMCS;
1109}
1110
843e4330
KH		 1111static inline bool cpu_has_vmx_pml(void)
1112{
1113 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1114}
1115
04547156
SY		 1116static inline bool report_flexpriority(void)
1117{
1118 return flexpriority_enabled;
1119}
1120
fe3ef05c
NHE		 1121static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1122{
1123 return vmcs12->cpu_based_vm_exec_control & bit;
1124}
1125
1126static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1127{
1128 return (vmcs12->cpu_based_vm_exec_control &
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1130 (vmcs12->secondary_vm_exec_control & bit);
1131}
1132
f5c4368f 1133static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1134{
1135 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1136}
1137
f4124500
JK		 1138static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1139{
1140 return vmcs12->pin_based_vm_exec_control &
1141 PIN_BASED_VMX_PREEMPTION_TIMER;
1142}
1143
155a97a3
NHE		 1144static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1145{
1146 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1147}
1148
81dc01f7
WL		 1149static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1150{
1151 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1152 vmx_xsaves_supported();
1153}
1154
f2b93280
WV		 1155static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1156{
1157 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1158}
1159
82f0dd4b
WV		 1160static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1161{
1162 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1163}
1164
608406e2
WV		 1165static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1166{
1167 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1168}
1169
705699a1
WV		 1170static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1171{
1172 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1173}
1174
644d711a
NHE		 1175static inline bool is_exception(u32 intr_info)
1176{
1177 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1178 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1179}
1180
533558bc
JK		 1181static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1182 u32 exit_intr_info,
1183 unsigned long exit_qualification);
7c177938
NHE		 1184static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1185 struct vmcs12 *vmcs12,
1186 u32 reason, unsigned long qualification);
1187
8b9cf98c 1188static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1189{
1190 int i;
1191
a2fa3e9f 1192 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1193 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1194 return i;
1195 return -1;
1196}
1197
2384d2b3
SY		 1198static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1199{
1200 struct {
1201 u64 vpid : 16;
1202 u64 rsvd : 48;
1203 u64 gva;
1204 } operand = { vpid, 0, gva };
1205
4ecac3fd 1206 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand), "c"(ext) : "cc", "memory");
1210}
1211
1439442c
SY		 1212static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1213{
1214 struct {
1215 u64 eptp, gpa;
1216 } operand = {eptp, gpa};
1217
4ecac3fd 1218 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand), "c" (ext) : "cc", "memory");
1222}
1223
26bb0981 1224static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1225{
1226 int i;
1227
8b9cf98c 1228 i = __find_msr_index(vmx, msr);
a75beee6 1229 if (i >= 0)
a2fa3e9f 1230 return &vmx->guest_msrs[i];
8b6d44c7 1231 return NULL;
7725f0ba
AK		 1232}
1233
6aa8b732
AK		 1234static void vmcs_clear(struct vmcs *vmcs)
1235{
1236 u64 phys_addr = __pa(vmcs);
1237 u8 error;
1238
4ecac3fd 1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1240 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1241 : "cc", "memory");
1242 if (error)
1243 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1244 vmcs, phys_addr);
1245}
1246
d462b819
NHE		 1247static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1248{
1249 vmcs_clear(loaded_vmcs->vmcs);
1250 loaded_vmcs->cpu = -1;
1251 loaded_vmcs->launched = 0;
1252}
1253
7725b894
DX		 1254static void vmcs_load(struct vmcs *vmcs)
1255{
1256 u64 phys_addr = __pa(vmcs);
1257 u8 error;
1258
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1260 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1261 : "cc", "memory");
1262 if (error)
2844d849 1263 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1264 vmcs, phys_addr);
1265}
1266
2965faa5 1267#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 1268/*
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1271 * default.
1272 */
1273static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1274
1275static inline void crash_enable_local_vmclear(int cpu)
1276{
1277 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1278}
1279
1280static inline void crash_disable_local_vmclear(int cpu)
1281{
1282 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1283}
1284
1285static inline int crash_local_vmclear_enabled(int cpu)
1286{
1287 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1288}
1289
1290static void crash_vmclear_local_loaded_vmcss(void)
1291{
1292 int cpu = raw_smp_processor_id();
1293 struct loaded_vmcs *v;
1294
1295 if (!crash_local_vmclear_enabled(cpu))
1296 return;
1297
1298 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1299 loaded_vmcss_on_cpu_link)
1300 vmcs_clear(v->vmcs);
1301}
1302#else
1303static inline void crash_enable_local_vmclear(int cpu) { }
1304static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 1305#endif /* CONFIG_KEXEC_CORE */
8f536b76 1306
d462b819 1307static void __loaded_vmcs_clear(void *arg)
6aa8b732 1308{
d462b819 1309 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1310 int cpu = raw_smp_processor_id();
6aa8b732 1311
d462b819
NHE		 1312 if (loaded_vmcs->cpu != cpu)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1315 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1316 crash_disable_local_vmclear(cpu);
d462b819 1317 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1318
1319 /*
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1324 */
1325 smp_wmb();
1326
d462b819 1327 loaded_vmcs_init(loaded_vmcs);
8f536b76 1328 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1329}
1330
d462b819 1331static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1332{
e6c7d321
XG		 1333 int cpu = loaded_vmcs->cpu;
1334
1335 if (cpu != -1)
1336 smp_call_function_single(cpu,
1337 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1338}
1339
1760dd49 1340static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1341{
1342 if (vmx->vpid == 0)
1343 return;
1344
518c8aee
GJ		 1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1347}
1348
b9d762fa
GJ		 1349static inline void vpid_sync_vcpu_global(void)
1350{
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1353}
1354
1355static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1356{
1357 if (cpu_has_vmx_invvpid_single())
1760dd49 1358 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1359 else
1360 vpid_sync_vcpu_global();
1361}
1362
1439442c
SY		 1363static inline void ept_sync_global(void)
1364{
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1367}
1368
1369static inline void ept_sync_context(u64 eptp)
1370{
089d034e 1371 if (enable_ept) {
1439442c
SY		 1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1374 else
1375 ept_sync_global();
1376 }
1377}
1378
96304217 1379static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1380{
5e520e62 1381 unsigned long value;
6aa8b732 1382
5e520e62
AK		 1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1384 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1385 return value;
1386}
1387
96304217 1388static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1389{
1390 return vmcs_readl(field);
1391}
1392
96304217 1393static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1394{
1395 return vmcs_readl(field);
1396}
1397
96304217 1398static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1399{
05b3e0c2 1400#ifdef CONFIG_X86_64
6aa8b732
AK		 1401 return vmcs_readl(field);
1402#else
1403 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1404#endif
1405}
1406
e52de1b8
AK		 1407static noinline void vmwrite_error(unsigned long field, unsigned long value)
1408{
1409 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1410 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1411 dump_stack();
1412}
1413
6aa8b732
AK		 1414static void vmcs_writel(unsigned long field, unsigned long value)
1415{
1416 u8 error;
1417
4ecac3fd 1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1419 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1420 if (unlikely(error))
1421 vmwrite_error(field, value);
6aa8b732
AK		 1422}
1423
1424static void vmcs_write16(unsigned long field, u16 value)
1425{
1426 vmcs_writel(field, value);
1427}
1428
1429static void vmcs_write32(unsigned long field, u32 value)
1430{
1431 vmcs_writel(field, value);
1432}
1433
1434static void vmcs_write64(unsigned long field, u64 value)
1435{
6aa8b732 1436 vmcs_writel(field, value);
7682f2d0 1437#ifndef CONFIG_X86_64
6aa8b732
AK		 1438 asm volatile ("");
1439 vmcs_writel(field+1, value >> 32);
1440#endif
1441}
1442
2ab455cc
AL		 1443static void vmcs_clear_bits(unsigned long field, u32 mask)
1444{
1445 vmcs_writel(field, vmcs_readl(field) & ~mask);
1446}
1447
1448static void vmcs_set_bits(unsigned long field, u32 mask)
1449{
1450 vmcs_writel(field, vmcs_readl(field) | mask);
1451}
1452
2961e876
GN		 1453static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1454{
1455 vmcs_write32(VM_ENTRY_CONTROLS, val);
1456 vmx->vm_entry_controls_shadow = val;
1457}
1458
1459static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1460{
1461 if (vmx->vm_entry_controls_shadow != val)
1462 vm_entry_controls_init(vmx, val);
1463}
1464
1465static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1466{
1467 return vmx->vm_entry_controls_shadow;
1468}
1469
1470
1471static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1472{
1473 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1474}
1475
1476static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1477{
1478 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1479}
1480
1481static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1482{
1483 vmcs_write32(VM_EXIT_CONTROLS, val);
1484 vmx->vm_exit_controls_shadow = val;
1485}
1486
1487static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1488{
1489 if (vmx->vm_exit_controls_shadow != val)
1490 vm_exit_controls_init(vmx, val);
1491}
1492
1493static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1494{
1495 return vmx->vm_exit_controls_shadow;
1496}
1497
1498
1499static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1500{
1501 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1502}
1503
1504static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1505{
1506 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1507}
1508
2fb92db1
AK		 1509static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1510{
1511 vmx->segment_cache.bitmask = 0;
1512}
1513
1514static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1515 unsigned field)
1516{
1517 bool ret;
1518 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1519
1520 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1521 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1522 vmx->segment_cache.bitmask = 0;
1523 }
1524 ret = vmx->segment_cache.bitmask & mask;
1525 vmx->segment_cache.bitmask |= mask;
1526 return ret;
1527}
1528
1529static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1530{
1531 u16 *p = &vmx->segment_cache.seg[seg].selector;
1532
1533 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1534 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1535 return *p;
1536}
1537
1538static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1539{
1540 ulong *p = &vmx->segment_cache.seg[seg].base;
1541
1542 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1543 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1544 return *p;
1545}
1546
1547static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1548{
1549 u32 *p = &vmx->segment_cache.seg[seg].limit;
1550
1551 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1552 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1553 return *p;
1554}
1555
1556static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1557{
1558 u32 *p = &vmx->segment_cache.seg[seg].ar;
1559
1560 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1561 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1562 return *p;
1563}
1564
abd3f2d6
AK		 1565static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1566{
1567 u32 eb;
1568
fd7373cc
JK		 1569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1570 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1571 if ((vcpu->guest_debug &
1572 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1573 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1574 eb |= 1u << BP_VECTOR;
7ffd92c5 1575 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1576 eb = ~0;
089d034e 1577 if (enable_ept)
1439442c 1578 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1579 if (vcpu->fpu_active)
1580 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1581
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1586 */
1587 if (is_guest_mode(vcpu))
1588 eb |= get_vmcs12(vcpu)->exception_bitmap;
1589
abd3f2d6
AK		 1590 vmcs_write32(EXCEPTION_BITMAP, eb);
1591}
1592
2961e876
GN		 1593static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1594 unsigned long entry, unsigned long exit)
8bf00a52 1595{
2961e876
GN		 1596 vm_entry_controls_clearbit(vmx, entry);
1597 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1598}
1599
61d2ef2c
AK		 1600static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1601{
1602 unsigned i;
1603 struct msr_autoload *m = &vmx->msr_autoload;
1604
8bf00a52
GN		 1605 switch (msr) {
1606 case MSR_EFER:
1607 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1608 clear_atomic_switch_msr_special(vmx,
1609 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1610 VM_EXIT_LOAD_IA32_EFER);
1611 return;
1612 }
1613 break;
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
2961e876 1616 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1619 return;
1620 }
1621 break;
110312c8
AK		 1622 }
1623
61d2ef2c
AK		 1624 for (i = 0; i < m->nr; ++i)
1625 if (m->guest[i].index == msr)
1626 break;
1627
1628 if (i == m->nr)
1629 return;
1630 --m->nr;
1631 m->guest[i] = m->guest[m->nr];
1632 m->host[i] = m->host[m->nr];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1635}
1636
2961e876
GN		 1637static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1638 unsigned long entry, unsigned long exit,
1639 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1640 u64 guest_val, u64 host_val)
8bf00a52
GN		 1641{
1642 vmcs_write64(guest_val_vmcs, guest_val);
1643 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1644 vm_entry_controls_setbit(vmx, entry);
1645 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1646}
1647
61d2ef2c
AK		 1648static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1649 u64 guest_val, u64 host_val)
1650{
1651 unsigned i;
1652 struct msr_autoload *m = &vmx->msr_autoload;
1653
8bf00a52
GN		 1654 switch (msr) {
1655 case MSR_EFER:
1656 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1657 add_atomic_switch_msr_special(vmx,
1658 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1659 VM_EXIT_LOAD_IA32_EFER,
1660 GUEST_IA32_EFER,
1661 HOST_IA32_EFER,
1662 guest_val, host_val);
1663 return;
1664 }
1665 break;
1666 case MSR_CORE_PERF_GLOBAL_CTRL:
1667 if (cpu_has_load_perf_global_ctrl) {
2961e876 1668 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1671 GUEST_IA32_PERF_GLOBAL_CTRL,
1672 HOST_IA32_PERF_GLOBAL_CTRL,
1673 guest_val, host_val);
1674 return;
1675 }
1676 break;
110312c8
AK		 1677 }
1678
61d2ef2c
AK		 1679 for (i = 0; i < m->nr; ++i)
1680 if (m->guest[i].index == msr)
1681 break;
1682
e7fc6f93 1683 if (i == NR_AUTOLOAD_MSRS) {
60266204 1684 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1685 "Can't add msr %x\n", msr);
1686 return;
1687 } else if (i == m->nr) {
61d2ef2c
AK		 1688 ++m->nr;
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1691 }
1692
1693 m->guest[i].index = msr;
1694 m->guest[i].value = guest_val;
1695 m->host[i].index = msr;
1696 m->host[i].value = host_val;
1697}
1698
33ed6329
AK		 1699static void reload_tss(void)
1700{
33ed6329
AK		 1701 /*
1702 * VT restores TR but not its size. Useless.
1703 */
89cbc767 1704 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1705 struct desc_struct *descs;
33ed6329 1706
d359192f 1707 descs = (void *)gdt->address;
33ed6329
AK		 1708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1709 load_TR_desc();
33ed6329
AK		 1710}
1711
92c0d900 1712static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1713{
3a34a881 1714 u64 guest_efer;
51c6cf66
AK		 1715 u64 ignore_bits;
1716
f6801dff 1717 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1718
51c6cf66 1719 /*
0fa06071 1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1721 * outside long mode
1722 */
1723 ignore_bits = EFER_NX | EFER_SCE;
1724#ifdef CONFIG_X86_64
1725 ignore_bits |= EFER_LMA | EFER_LME;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer & EFER_LMA)
1728 ignore_bits &= ~(u64)EFER_SCE;
1729#endif
51c6cf66
AK		 1730 guest_efer &= ~ignore_bits;
1731 guest_efer |= host_efer & ignore_bits;
26bb0981 1732 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1734
1735 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1736
1737 /*
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1741 */
1742 if (cpu_has_load_ia32_efer ||
1743 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1744 guest_efer = vmx->vcpu.arch.efer;
1745 if (!(guest_efer & EFER_LMA))
1746 guest_efer &= ~EFER_LME;
54b98bff
AL		 1747 if (guest_efer != host_efer)
1748 add_atomic_switch_msr(vmx, MSR_EFER,
1749 guest_efer, host_efer);
84ad33ef
AK		 1750 return false;
1751 }
1752
26bb0981 1753 return true;
51c6cf66
AK		 1754}
1755
2d49ec72
GN		 1756static unsigned long segment_base(u16 selector)
1757{
89cbc767 1758 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1759 struct desc_struct *d;
1760 unsigned long table_base;
1761 unsigned long v;
1762
1763 if (!(selector & ~3))
1764 return 0;
1765
d359192f 1766 table_base = gdt->address;
2d49ec72
GN		 1767
1768 if (selector & 4) { /* from ldt */
1769 u16 ldt_selector = kvm_read_ldt();
1770
1771 if (!(ldt_selector & ~3))
1772 return 0;
1773
1774 table_base = segment_base(ldt_selector);
1775 }
1776 d = (struct desc_struct *)(table_base + (selector & ~7));
1777 v = get_desc_base(d);
1778#ifdef CONFIG_X86_64
1779 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1780 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1781#endif
1782 return v;
1783}
1784
1785static inline unsigned long kvm_read_tr_base(void)
1786{
1787 u16 tr;
1788 asm("str %0" : "=g"(tr));
1789 return segment_base(tr);
1790}
1791
04d2cc77 1792static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1793{
04d2cc77 1794 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1795 int i;
04d2cc77 1796
a2fa3e9f 1797 if (vmx->host_state.loaded)
33ed6329
AK		 1798 return;
1799
a2fa3e9f 1800 vmx->host_state.loaded = 1;
33ed6329
AK		 1801 /*
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1804 */
d6e88aec 1805 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1806 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1807 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1808 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1809 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1810 vmx->host_state.fs_reload_needed = 0;
1811 } else {
33ed6329 1812 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1813 vmx->host_state.fs_reload_needed = 1;
33ed6329 1814 }
9581d442 1815 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1816 if (!(vmx->host_state.gs_sel & 7))
1817 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1818 else {
1819 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1820 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1821 }
1822
b2da15ac
AK		 1823#ifdef CONFIG_X86_64
1824 savesegment(ds, vmx->host_state.ds_sel);
1825 savesegment(es, vmx->host_state.es_sel);
1826#endif
1827
33ed6329
AK		 1828#ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1830 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1831#else
a2fa3e9f
GH		 1832 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1833 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1834#endif
707c0874
AK		 1835
1836#ifdef CONFIG_X86_64
c8770e7b
AK		 1837 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1838 if (is_long_mode(&vmx->vcpu))
44ea2b17 1839 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1840#endif
da8999d3
LJ		 1841 if (boot_cpu_has(X86_FEATURE_MPX))
1842 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1843 for (i = 0; i < vmx->save_nmsrs; ++i)
1844 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1845 vmx->guest_msrs[i].data,
1846 vmx->guest_msrs[i].mask);
33ed6329
AK		 1847}
1848
a9b21b62 1849static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1850{
a2fa3e9f 1851 if (!vmx->host_state.loaded)
33ed6329
AK		 1852 return;
1853
e1beb1d3 1854 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1855 vmx->host_state.loaded = 0;
c8770e7b
AK		 1856#ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx->vcpu))
1858 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1859#endif
152d3f2f 1860 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1861 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1862#ifdef CONFIG_X86_64
9581d442 1863 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1864#else
1865 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1866#endif
33ed6329 1867 }
0a77fe4c
AK		 1868 if (vmx->host_state.fs_reload_needed)
1869 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1870#ifdef CONFIG_X86_64
1871 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1872 loadsegment(ds, vmx->host_state.ds_sel);
1873 loadsegment(es, vmx->host_state.es_sel);
1874 }
b2da15ac 1875#endif
152d3f2f 1876 reload_tss();
44ea2b17 1877#ifdef CONFIG_X86_64
c8770e7b 1878 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1879#endif
da8999d3
LJ		 1880 if (vmx->host_state.msr_host_bndcfgs)
1881 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1882 /*
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1885 */
3c6dffa9 1886 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
b1a74bf8 1887 stts();
89cbc767 1888 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1889}
1890
a9b21b62
AK		 1891static void vmx_load_host_state(struct vcpu_vmx *vmx)
1892{
1893 preempt_disable();
1894 __vmx_load_host_state(vmx);
1895 preempt_enable();
1896}
1897
6aa8b732
AK		 1898/*
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1901 */
15ad7146 1902static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1903{
a2fa3e9f 1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1905 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1906
4610c9cc
DX		 1907 if (!vmm_exclusive)
1908 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1909 else if (vmx->loaded_vmcs->cpu != cpu)
1910 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1911
d462b819
NHE		 1912 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1913 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1914 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1915 }
1916
d462b819 1917 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1918 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1919 unsigned long sysenter_esp;
1920
a8eeb04a 1921 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1922 local_irq_disable();
8f536b76 1923 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1924
1925 /*
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1929 */
1930 smp_rmb();
1931
d462b819
NHE		 1932 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1933 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1934 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1935 local_irq_enable();
1936
6aa8b732
AK		 1937 /*
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1939 * processors.
1940 */
d6e88aec 1941 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1942 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1943
1944 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1946 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1947 }
6aa8b732
AK		 1948}
1949
1950static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1951{
a9b21b62 1952 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1953 if (!vmm_exclusive) {
d462b819
NHE		 1954 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1955 vcpu->cpu = -1;
4610c9cc
DX		 1956 kvm_cpu_vmxoff();
1957 }
6aa8b732
AK		 1958}
1959
5fd86fcf
AK		 1960static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1961{
81231c69
AK		 1962 ulong cr0;
1963
5fd86fcf
AK		 1964 if (vcpu->fpu_active)
1965 return;
1966 vcpu->fpu_active = 1;
81231c69
AK		 1967 cr0 = vmcs_readl(GUEST_CR0);
1968 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1969 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1970 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1971 update_exception_bitmap(vcpu);
edcafe3c 1972 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1973 if (is_guest_mode(vcpu))
1974 vcpu->arch.cr0_guest_owned_bits &=
1975 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1976 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1977}
1978
edcafe3c
AK		 1979static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1980
fe3ef05c
NHE		 1981/*
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1985 */
1986static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1987{
1988 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1989 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1990}
1991static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1992{
1993 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1994 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1995}
1996
5fd86fcf
AK		 1997static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1998{
36cf24e0
NHE		 1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2001 */
edcafe3c 2002 vmx_decache_cr0_guest_bits(vcpu);
81231c69 2003 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 2004 update_exception_bitmap(vcpu);
edcafe3c
AK		 2005 vcpu->arch.cr0_guest_owned_bits = 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 2007 if (is_guest_mode(vcpu)) {
2008 /*
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2015 */
2016 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2017 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2018 (vcpu->arch.cr0 & X86_CR0_TS);
2019 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2020 } else
2021 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 2022}
2023
6aa8b732
AK		 2024static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2025{
78ac8b47 2026 unsigned long rflags, save_rflags;
345dcaa8 2027
6de12732
AK		 2028 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2029 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2030 rflags = vmcs_readl(GUEST_RFLAGS);
2031 if (to_vmx(vcpu)->rmode.vm86_active) {
2032 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2033 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2034 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2035 }
2036 to_vmx(vcpu)->rflags = rflags;
78ac8b47 2037 }
6de12732 2038 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 2039}
2040
2041static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2042{
6de12732
AK		 2043 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2044 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 2045 if (to_vmx(vcpu)->rmode.vm86_active) {
2046 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 2047 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 2048 }
6aa8b732
AK		 2049 vmcs_writel(GUEST_RFLAGS, rflags);
2050}
2051
37ccdcbe 2052static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2053{
2054 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2055 int ret = 0;
2056
2057 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2058 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2059 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2060 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2061
37ccdcbe 2062 return ret;
2809f5d2
GC		 2063}
2064
2065static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2066{
2067 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2068 u32 interruptibility = interruptibility_old;
2069
2070 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2071
48005f64 2072 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2073 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2074 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2075 interruptibility |= GUEST_INTR_STATE_STI;
2076
2077 if ((interruptibility != interruptibility_old))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2079}
2080
6aa8b732
AK		 2081static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2082{
2083 unsigned long rip;
6aa8b732 2084
5fdbf976 2085 rip = kvm_rip_read(vcpu);
6aa8b732 2086 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2087 kvm_rip_write(vcpu, rip);
6aa8b732 2088
2809f5d2
GC		 2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2091}
2092
0b6ac343
NHE		 2093/*
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2096 */
e011c663 2097static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2098{
2099 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2100
e011c663 2101 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2102 return 0;
2103
533558bc
JK		 2104 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2105 vmcs_read32(VM_EXIT_INTR_INFO),
2106 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2107 return 1;
2108}
2109
298101da 2110static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2111 bool has_error_code, u32 error_code,
2112 bool reinject)
298101da 2113{
77ab6db0 2114 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2115 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2116
e011c663
GN		 2117 if (!reinject && is_guest_mode(vcpu) &&
2118 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2119 return;
2120
8ab2d2e2 2121 if (has_error_code) {
77ab6db0 2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2123 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2124 }
77ab6db0 2125
7ffd92c5 2126 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2127 int inc_eip = 0;
2128 if (kvm_exception_is_soft(nr))
2129 inc_eip = vcpu->arch.event_exit_inst_len;
2130 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2132 return;
2133 }
2134
66fd3f7f
GN		 2135 if (kvm_exception_is_soft(nr)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2137 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2138 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2139 } else
2140 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2141
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2143}
2144
4e47c7a6
SY		 2145static bool vmx_rdtscp_supported(void)
2146{
2147 return cpu_has_vmx_rdtscp();
2148}
2149
ad756a16
MJ		 2150static bool vmx_invpcid_supported(void)
2151{
2152 return cpu_has_vmx_invpcid() && enable_ept;
2153}
2154
a75beee6
ED		 2155/*
2156 * Swap MSR entry in host/guest MSR entry array.
2157 */
8b9cf98c 2158static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2159{
26bb0981 2160 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2161
2162 tmp = vmx->guest_msrs[to];
2163 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2164 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2165}
2166
8d14695f
YZ		 2167static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2168{
2169 unsigned long *msr_bitmap;
2170
670125bd
WV		 2171 if (is_guest_mode(vcpu))
2172 msr_bitmap = vmx_msr_bitmap_nested;
8a9781f7 2173 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
8d14695f
YZ		 2174 if (is_long_mode(vcpu))
2175 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2176 else
2177 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2178 } else {
2179 if (is_long_mode(vcpu))
2180 msr_bitmap = vmx_msr_bitmap_longmode;
2181 else
2182 msr_bitmap = vmx_msr_bitmap_legacy;
2183 }
2184
2185 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2186}
2187
e38aea3e
AK		 2188/*
2189 * Set up the vmcs to automatically save and restore system
2190 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2191 * mode, as fiddling with msrs is very expensive.
2192 */
8b9cf98c 2193static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2194{
26bb0981 2195 int save_nmsrs, index;
e38aea3e 2196
a75beee6
ED		 2197 save_nmsrs = 0;
2198#ifdef CONFIG_X86_64
8b9cf98c 2199 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2200 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2201 if (index >= 0)
8b9cf98c
RR		 2202 move_msr_up(vmx, index, save_nmsrs++);
2203 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2204 if (index >= 0)
8b9cf98c
RR		 2205 move_msr_up(vmx, index, save_nmsrs++);
2206 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2207 if (index >= 0)
8b9cf98c 2208 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2209 index = __find_msr_index(vmx, MSR_TSC_AUX);
2210 if (index >= 0 && vmx->rdtscp_enabled)
2211 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2212 /*
8c06585d 2213 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2214 * if efer.sce is enabled.
2215 */
8c06585d 2216 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2217 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2218 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2219 }
2220#endif
92c0d900
AK		 2221 index = __find_msr_index(vmx, MSR_EFER);
2222 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2223 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2224
26bb0981 2225 vmx->save_nmsrs = save_nmsrs;
5897297b 2226
8d14695f
YZ		 2227 if (cpu_has_vmx_msr_bitmap())
2228 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2229}
2230
6aa8b732
AK		 2231/*
2232 * reads and returns guest's timestamp counter "register"
2233 * guest_tsc = host_tsc + tsc_offset -- 21.3
2234 */
2235static u64 guest_read_tsc(void)
2236{
2237 u64 host_tsc, tsc_offset;
2238
4ea1636b 2239 host_tsc = rdtsc();
6aa8b732
AK		 2240 tsc_offset = vmcs_read64(TSC_OFFSET);
2241 return host_tsc + tsc_offset;
2242}
2243
d5c1785d
NHE		 2244/*
2245 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2246 * counter, even if a nested guest (L2) is currently running.
2247 */
48d89b92 2248static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2249{
886b470c 2250 u64 tsc_offset;
d5c1785d 2251
d5c1785d
NHE		 2252 tsc_offset = is_guest_mode(vcpu) ?
2253 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2254 vmcs_read64(TSC_OFFSET);
2255 return host_tsc + tsc_offset;
2256}
2257
4051b188 2258/*
cc578287
ZA		 2259 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2260 * software catchup for faster rates on slower CPUs.
4051b188 2261 */
cc578287 2262static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2263{
cc578287
ZA		 2264 if (!scale)
2265 return;
2266
2267 if (user_tsc_khz > tsc_khz) {
2268 vcpu->arch.tsc_catchup = 1;
2269 vcpu->arch.tsc_always_catchup = 1;
2270 } else
2271 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2272}
2273
ba904635
WA		 2274static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2275{
2276 return vmcs_read64(TSC_OFFSET);
2277}
2278
6aa8b732 2279/*
99e3e30a 2280 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2281 */
99e3e30a 2282static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2283{
27fc51b2 2284 if (is_guest_mode(vcpu)) {
7991825b 2285 /*
27fc51b2
NHE		 2286 * We're here if L1 chose not to trap WRMSR to TSC. According
2287 * to the spec, this should set L1's TSC; The offset that L1
2288 * set for L2 remains unchanged, and still needs to be added
2289 * to the newly set TSC to get L2's TSC.
7991825b 2290 */
27fc51b2
NHE		 2291 struct vmcs12 *vmcs12;
2292 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2293 /* recalculate vmcs02.TSC_OFFSET: */
2294 vmcs12 = get_vmcs12(vcpu);
2295 vmcs_write64(TSC_OFFSET, offset +
2296 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2297 vmcs12->tsc_offset : 0));
2298 } else {
489223ed
YY		 2299 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2300 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2301 vmcs_write64(TSC_OFFSET, offset);
2302 }
6aa8b732
AK		 2303}
2304
f1e2b260 2305static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2306{
2307 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2308
e48672fa 2309 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2310 if (is_guest_mode(vcpu)) {
2311 /* Even when running L2, the adjustment needs to apply to L1 */
2312 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2313 } else
2314 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2315 offset + adjustment);
e48672fa
ZA		 2316}
2317
857e4099
JR		 2318static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2319{
4ea1636b 2320 return target_tsc - rdtsc();
857e4099
JR		 2321}
2322
801d3424
NHE		 2323static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2324{
2325 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2326 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2327}
2328
2329/*
2330 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2331 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2332 * all guests if the "nested" module option is off, and can also be disabled
2333 * for a single guest by disabling its VMX cpuid bit.
2334 */
2335static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2336{
2337 return nested && guest_cpuid_has_vmx(vcpu);
2338}
2339
b87a51ae
NHE		 2340/*
2341 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2342 * returned for the various VMX controls MSRs when nested VMX is enabled.
2343 * The same values should also be used to verify that vmcs12 control fields are
2344 * valid during nested entry from L1 to L2.
2345 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2346 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2347 * bit in the high half is on if the corresponding bit in the control field
2348 * may be on. See also vmx_control_verify().
b87a51ae 2349 */
b9c237bb 2350static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
b87a51ae
NHE		 2351{
2352 /*
2353 * Note that as a general rule, the high half of the MSRs (bits in
2354 * the control fields which may be 1) should be initialized by the
2355 * intersection of the underlying hardware's MSR (i.e., features which
2356 * can be supported) and the list of features we want to expose -
2357 * because they are known to be properly supported in our code.
2358 * Also, usually, the low half of the MSRs (bits which must be 1) can
2359 * be set to 0, meaning that L1 may turn off any of these bits. The
2360 * reason is that if one of these bits is necessary, it will appear
2361 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2362 * fields of vmcs01 and vmcs02, will turn these bits off - and
2363 * nested_vmx_exit_handled() will not pass related exits to L1.
2364 * These rules have exceptions below.
2365 */
2366
2367 /* pin-based controls */
eabeaacc 2368 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
b9c237bb
WV		 2369 vmx->nested.nested_vmx_pinbased_ctls_low,
2370 vmx->nested.nested_vmx_pinbased_ctls_high);
2371 vmx->nested.nested_vmx_pinbased_ctls_low |=
2372 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2373 vmx->nested.nested_vmx_pinbased_ctls_high &=
2374 PIN_BASED_EXT_INTR_MASK |
2375 PIN_BASED_NMI_EXITING |
2376 PIN_BASED_VIRTUAL_NMIS;
2377 vmx->nested.nested_vmx_pinbased_ctls_high |=
2378 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2379 PIN_BASED_VMX_PREEMPTION_TIMER;
35754c98 2380 if (vmx_cpu_uses_apicv(&vmx->vcpu))
705699a1
WV		 2381 vmx->nested.nested_vmx_pinbased_ctls_high |=
2382 PIN_BASED_POSTED_INTR;
b87a51ae 2383
3dbcd8da 2384 /* exit controls */
c0dfee58 2385 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
b9c237bb
WV		 2386 vmx->nested.nested_vmx_exit_ctls_low,
2387 vmx->nested.nested_vmx_exit_ctls_high);
2388 vmx->nested.nested_vmx_exit_ctls_low =
2389 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2390
b9c237bb 2391 vmx->nested.nested_vmx_exit_ctls_high &=
b87a51ae 2392#ifdef CONFIG_X86_64
c0dfee58 2393 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2394#endif
f4124500 2395 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
b9c237bb
WV		 2396 vmx->nested.nested_vmx_exit_ctls_high |=
2397 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
f4124500 2398 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2399 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2400
36be0b9d 2401 if (vmx_mpx_supported())
b9c237bb 2402 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2403
2996fca0 2404 /* We support free control of debug control saving. */
b9c237bb
WV		 2405 vmx->nested.nested_vmx_true_exit_ctls_low =
2406 vmx->nested.nested_vmx_exit_ctls_low &
2996fca0
JK		 2407 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2408
b87a51ae
NHE		 2409 /* entry controls */
2410 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
b9c237bb
WV		 2411 vmx->nested.nested_vmx_entry_ctls_low,
2412 vmx->nested.nested_vmx_entry_ctls_high);
2413 vmx->nested.nested_vmx_entry_ctls_low =
2414 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2415 vmx->nested.nested_vmx_entry_ctls_high &=
57435349
JK		 2416#ifdef CONFIG_X86_64
2417 VM_ENTRY_IA32E_MODE |
2418#endif
2419 VM_ENTRY_LOAD_IA32_PAT;
b9c237bb
WV		 2420 vmx->nested.nested_vmx_entry_ctls_high |=
2421 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
36be0b9d 2422 if (vmx_mpx_supported())
b9c237bb 2423 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2424
2996fca0 2425 /* We support free control of debug control loading. */
b9c237bb
WV		 2426 vmx->nested.nested_vmx_true_entry_ctls_low =
2427 vmx->nested.nested_vmx_entry_ctls_low &
2996fca0
JK		 2428 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2429
b87a51ae
NHE		 2430 /* cpu-based controls */
2431 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
b9c237bb
WV		 2432 vmx->nested.nested_vmx_procbased_ctls_low,
2433 vmx->nested.nested_vmx_procbased_ctls_high);
2434 vmx->nested.nested_vmx_procbased_ctls_low =
2435 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2436 vmx->nested.nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2437 CPU_BASED_VIRTUAL_INTR_PENDING |
2438 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2439 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2440 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2441 CPU_BASED_CR3_STORE_EXITING |
2442#ifdef CONFIG_X86_64
2443 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2444#endif
2445 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
5f3d45e7
MD		 2446 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2447 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2448 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2449 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
b87a51ae
NHE		 2450 /*
2451 * We can allow some features even when not supported by the
2452 * hardware. For example, L1 can specify an MSR bitmap - and we
2453 * can use it to avoid exits to L1 - even when L0 runs L2
2454 * without MSR bitmaps.
2455 */
b9c237bb
WV		 2456 vmx->nested.nested_vmx_procbased_ctls_high |=
2457 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
560b7ee1 2458 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2459
3dcdf3ec 2460 /* We support free control of CR3 access interception. */
b9c237bb
WV		 2461 vmx->nested.nested_vmx_true_procbased_ctls_low =
2462 vmx->nested.nested_vmx_procbased_ctls_low &
3dcdf3ec
JK		 2463 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2464
b87a51ae
NHE		 2465 /* secondary cpu-based controls */
2466 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
b9c237bb
WV		 2467 vmx->nested.nested_vmx_secondary_ctls_low,
2468 vmx->nested.nested_vmx_secondary_ctls_high);
2469 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2470 vmx->nested.nested_vmx_secondary_ctls_high &=
d6851fbe 2471 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 2472 SECONDARY_EXEC_RDTSCP |
f2b93280 2473 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
82f0dd4b 2474 SECONDARY_EXEC_APIC_REGISTER_VIRT |
608406e2 2475 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
81dc01f7
WL		 2476 SECONDARY_EXEC_WBINVD_EXITING |
2477 SECONDARY_EXEC_XSAVES;
c18911a2 2478
afa61f75
NHE		 2479 if (enable_ept) {
2480 /* nested EPT: emulate EPT also to L1 */
b9c237bb 2481 vmx->nested.nested_vmx_secondary_ctls_high |=
0790ec17 2482 SECONDARY_EXEC_ENABLE_EPT;
b9c237bb 2483 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2484 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2485 VMX_EPT_INVEPT_BIT;
b9c237bb 2486 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
afa61f75 2487 /*
4b855078
BD		 2488 * For nested guests, we don't do anything specific
2489 * for single context invalidation. Hence, only advertise
2490 * support for global context invalidation.
afa61f75 2491 */
b9c237bb 2492 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75 2493 } else
b9c237bb 2494 vmx->nested.nested_vmx_ept_caps = 0;
afa61f75 2495
0790ec17
RK		 2496 if (enable_unrestricted_guest)
2497 vmx->nested.nested_vmx_secondary_ctls_high |=
2498 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2499
c18911a2 2500 /* miscellaneous data */
b9c237bb
WV		 2501 rdmsr(MSR_IA32_VMX_MISC,
2502 vmx->nested.nested_vmx_misc_low,
2503 vmx->nested.nested_vmx_misc_high);
2504 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2505 vmx->nested.nested_vmx_misc_low |=
2506 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
f4124500 2507 VMX_MISC_ACTIVITY_HLT;
b9c237bb 2508 vmx->nested.nested_vmx_misc_high = 0;
b87a51ae
NHE		 2509}
2510
2511static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2512{
2513 /*
2514 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2515 */
2516 return ((control & high) | low) == control;
2517}
2518
2519static inline u64 vmx_control_msr(u32 low, u32 high)
2520{
2521 return low | ((u64)high << 32);
2522}
2523
cae50139 2524/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2525static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2526{
b9c237bb
WV		 2527 struct vcpu_vmx *vmx = to_vmx(vcpu);
2528
b87a51ae 2529 switch (msr_index) {
b87a51ae
NHE		 2530 case MSR_IA32_VMX_BASIC:
2531 /*
2532 * This MSR reports some information about VMX support. We
2533 * should return information about the VMX we emulate for the
2534 * guest, and the VMCS structure we give it - not about the
2535 * VMX support of the underlying hardware.
2536 */
3dbcd8da 2537 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2538 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2539 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2540 break;
2541 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2542 case MSR_IA32_VMX_PINBASED_CTLS:
b9c237bb
WV		 2543 *pdata = vmx_control_msr(
2544 vmx->nested.nested_vmx_pinbased_ctls_low,
2545 vmx->nested.nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2546 break;
2547 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
b9c237bb
WV		 2548 *pdata = vmx_control_msr(
2549 vmx->nested.nested_vmx_true_procbased_ctls_low,
2550 vmx->nested.nested_vmx_procbased_ctls_high);
3dcdf3ec 2551 break;
b87a51ae 2552 case MSR_IA32_VMX_PROCBASED_CTLS:
b9c237bb
WV		 2553 *pdata = vmx_control_msr(
2554 vmx->nested.nested_vmx_procbased_ctls_low,
2555 vmx->nested.nested_vmx_procbased_ctls_high);
b87a51ae
NHE		 2556 break;
2557 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
b9c237bb
WV		 2558 *pdata = vmx_control_msr(
2559 vmx->nested.nested_vmx_true_exit_ctls_low,
2560 vmx->nested.nested_vmx_exit_ctls_high);
2996fca0 2561 break;
b87a51ae 2562 case MSR_IA32_VMX_EXIT_CTLS:
b9c237bb
WV		 2563 *pdata = vmx_control_msr(
2564 vmx->nested.nested_vmx_exit_ctls_low,
2565 vmx->nested.nested_vmx_exit_ctls_high);
b87a51ae
NHE		 2566 break;
2567 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
b9c237bb
WV		 2568 *pdata = vmx_control_msr(
2569 vmx->nested.nested_vmx_true_entry_ctls_low,
2570 vmx->nested.nested_vmx_entry_ctls_high);
2996fca0 2571 break;
b87a51ae 2572 case MSR_IA32_VMX_ENTRY_CTLS:
b9c237bb
WV		 2573 *pdata = vmx_control_msr(
2574 vmx->nested.nested_vmx_entry_ctls_low,
2575 vmx->nested.nested_vmx_entry_ctls_high);
b87a51ae
NHE		 2576 break;
2577 case MSR_IA32_VMX_MISC:
b9c237bb
WV		 2578 *pdata = vmx_control_msr(
2579 vmx->nested.nested_vmx_misc_low,
2580 vmx->nested.nested_vmx_misc_high);
b87a51ae
NHE		 2581 break;
2582 /*
2583 * These MSRs specify bits which the guest must keep fixed (on or off)
2584 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2585 * We picked the standard core2 setting.
2586 */
2587#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2588#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2589 case MSR_IA32_VMX_CR0_FIXED0:
2590 *pdata = VMXON_CR0_ALWAYSON;
2591 break;
2592 case MSR_IA32_VMX_CR0_FIXED1:
2593 *pdata = -1ULL;
2594 break;
2595 case MSR_IA32_VMX_CR4_FIXED0:
2596 *pdata = VMXON_CR4_ALWAYSON;
2597 break;
2598 case MSR_IA32_VMX_CR4_FIXED1:
2599 *pdata = -1ULL;
2600 break;
2601 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2602 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2603 break;
2604 case MSR_IA32_VMX_PROCBASED_CTLS2:
b9c237bb
WV		 2605 *pdata = vmx_control_msr(
2606 vmx->nested.nested_vmx_secondary_ctls_low,
2607 vmx->nested.nested_vmx_secondary_ctls_high);
b87a51ae
NHE		 2608 break;
2609 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75 2610 /* Currently, no nested vpid support */
b9c237bb 2611 *pdata = vmx->nested.nested_vmx_ept_caps;
b87a51ae
NHE		 2612 break;
2613 default:
b87a51ae 2614 return 1;
b3897a49
NHE		 2615 }
2616
b87a51ae
NHE		 2617 return 0;
2618}
2619
6aa8b732
AK		 2620/*
2621 * Reads an msr value (of 'msr_index') into 'pdata'.
2622 * Returns 0 on success, non-0 otherwise.
2623 * Assumes vcpu_load() was already called.
2624 */
609e36d3 2625static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2626{
26bb0981 2627 struct shared_msr_entry *msr;
6aa8b732 2628
609e36d3 2629 switch (msr_info->index) {
05b3e0c2 2630#ifdef CONFIG_X86_64
6aa8b732 2631 case MSR_FS_BASE:
609e36d3 2632 msr_info->data = vmcs_readl(GUEST_FS_BASE);
6aa8b732
AK		 2633 break;
2634 case MSR_GS_BASE:
609e36d3 2635 msr_info->data = vmcs_readl(GUEST_GS_BASE);
6aa8b732 2636 break;
44ea2b17
AK		 2637 case MSR_KERNEL_GS_BASE:
2638 vmx_load_host_state(to_vmx(vcpu));
609e36d3 2639 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
44ea2b17 2640 break;
26bb0981 2641#endif
6aa8b732 2642 case MSR_EFER:
609e36d3 2643 return kvm_get_msr_common(vcpu, msr_info);
af24a4e4 2644 case MSR_IA32_TSC:
609e36d3 2645 msr_info->data = guest_read_tsc();
6aa8b732
AK		 2646 break;
2647 case MSR_IA32_SYSENTER_CS:
609e36d3 2648 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 2649 break;
2650 case MSR_IA32_SYSENTER_EIP:
609e36d3 2651 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2652 break;
2653 case MSR_IA32_SYSENTER_ESP:
609e36d3 2654 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2655 break;
0dd376e7 2656 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2657 if (!vmx_mpx_supported())
2658 return 1;
609e36d3 2659 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 2660 break;
cae50139
JK		 2661 case MSR_IA32_FEATURE_CONTROL:
2662 if (!nested_vmx_allowed(vcpu))
2663 return 1;
609e36d3 2664 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
cae50139
JK		 2665 break;
2666 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2667 if (!nested_vmx_allowed(vcpu))
2668 return 1;
609e36d3 2669 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
20300099
WL		 2670 case MSR_IA32_XSS:
2671 if (!vmx_xsaves_supported())
2672 return 1;
609e36d3 2673 msr_info->data = vcpu->arch.ia32_xss;
20300099 2674 break;
4e47c7a6
SY		 2675 case MSR_TSC_AUX:
2676 if (!to_vmx(vcpu)->rdtscp_enabled)
2677 return 1;
2678 /* Otherwise falls through */
6aa8b732 2679 default:
609e36d3 2680 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3bab1f5d 2681 if (msr) {
609e36d3 2682 msr_info->data = msr->data;
3bab1f5d 2683 break;
6aa8b732 2684 }
609e36d3 2685 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2686 }
2687
6aa8b732
AK		 2688 return 0;
2689}
2690
cae50139
JK		 2691static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2692
6aa8b732
AK		 2693/*
2694 * Writes msr value into into the appropriate "register".
2695 * Returns 0 on success, non-0 otherwise.
2696 * Assumes vcpu_load() was already called.
2697 */
8fe8ab46 2698static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2699{
a2fa3e9f 2700 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2701 struct shared_msr_entry *msr;
2cc51560 2702 int ret = 0;
8fe8ab46
WA		 2703 u32 msr_index = msr_info->index;
2704 u64 data = msr_info->data;
2cc51560 2705
6aa8b732 2706 switch (msr_index) {
3bab1f5d 2707 case MSR_EFER:
8fe8ab46 2708 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2709 break;
16175a79 2710#ifdef CONFIG_X86_64
6aa8b732 2711 case MSR_FS_BASE:
2fb92db1 2712 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2713 vmcs_writel(GUEST_FS_BASE, data);
2714 break;
2715 case MSR_GS_BASE:
2fb92db1 2716 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2717 vmcs_writel(GUEST_GS_BASE, data);
2718 break;
44ea2b17
AK		 2719 case MSR_KERNEL_GS_BASE:
2720 vmx_load_host_state(vmx);
2721 vmx->msr_guest_kernel_gs_base = data;
2722 break;
6aa8b732
AK		 2723#endif
2724 case MSR_IA32_SYSENTER_CS:
2725 vmcs_write32(GUEST_SYSENTER_CS, data);
2726 break;
2727 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2728 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2729 break;
2730 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2731 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2732 break;
0dd376e7 2733 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2734 if (!vmx_mpx_supported())
2735 return 1;
0dd376e7
LJ		 2736 vmcs_write64(GUEST_BNDCFGS, data);
2737 break;
af24a4e4 2738 case MSR_IA32_TSC:
8fe8ab46 2739 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2740 break;
468d472f
SY		 2741 case MSR_IA32_CR_PAT:
2742 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2743 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2744 return 1;
468d472f
SY		 2745 vmcs_write64(GUEST_IA32_PAT, data);
2746 vcpu->arch.pat = data;
2747 break;
2748 }
8fe8ab46 2749 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2750 break;
ba904635
WA		 2751 case MSR_IA32_TSC_ADJUST:
2752 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2753 break;
cae50139
JK		 2754 case MSR_IA32_FEATURE_CONTROL:
2755 if (!nested_vmx_allowed(vcpu) ||
2756 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2757 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2758 return 1;
2759 vmx->nested.msr_ia32_feature_control = data;
2760 if (msr_info->host_initiated && data == 0)
2761 vmx_leave_nested(vcpu);
2762 break;
2763 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2764 return 1; /* they are read-only */
20300099
WL		 2765 case MSR_IA32_XSS:
2766 if (!vmx_xsaves_supported())
2767 return 1;
2768 /*
2769 * The only supported bit as of Skylake is bit 8, but
2770 * it is not supported on KVM.
2771 */
2772 if (data != 0)
2773 return 1;
2774 vcpu->arch.ia32_xss = data;
2775 if (vcpu->arch.ia32_xss != host_xss)
2776 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2777 vcpu->arch.ia32_xss, host_xss);
2778 else
2779 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2780 break;
4e47c7a6
SY		 2781 case MSR_TSC_AUX:
2782 if (!vmx->rdtscp_enabled)
2783 return 1;
2784 /* Check reserved bit, higher 32 bits should be zero */
2785 if ((data >> 32) != 0)
2786 return 1;
2787 /* Otherwise falls through */
6aa8b732 2788 default:
8b9cf98c 2789 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2790 if (msr) {
8b3c3104 2791 u64 old_msr_data = msr->data;
3bab1f5d 2792 msr->data = data;
2225fd56
AK		 2793 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2794 preempt_disable();
8b3c3104
AH		 2795 ret = kvm_set_shared_msr(msr->index, msr->data,
2796 msr->mask);
2225fd56 2797 preempt_enable();
8b3c3104
AH		 2798 if (ret)
2799 msr->data = old_msr_data;
2225fd56 2800 }
3bab1f5d 2801 break;
6aa8b732 2802 }
8fe8ab46 2803 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2804 }
2805
2cc51560 2806 return ret;
6aa8b732
AK		 2807}
2808
5fdbf976 2809static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2810{
5fdbf976
MT		 2811 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2812 switch (reg) {
2813 case VCPU_REGS_RSP:
2814 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2815 break;
2816 case VCPU_REGS_RIP:
2817 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2818 break;
6de4f3ad
AK		 2819 case VCPU_EXREG_PDPTR:
2820 if (enable_ept)
2821 ept_save_pdptrs(vcpu);
2822 break;
5fdbf976
MT		 2823 default:
2824 break;
2825 }
6aa8b732
AK		 2826}
2827
6aa8b732
AK		 2828static __init int cpu_has_kvm_support(void)
2829{
6210e37b 2830 return cpu_has_vmx();
6aa8b732
AK		 2831}
2832
2833static __init int vmx_disabled_by_bios(void)
2834{
2835 u64 msr;
2836
2837 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2838 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2839 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2840 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2841 && tboot_enabled())
2842 return 1;
23f3e991 2843 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2844 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2845 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2846 && !tboot_enabled()) {
2847 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2848 "activate TXT before enabling KVM\n");
cafd6659 2849 return 1;
f9335afe 2850 }
23f3e991
JC		 2851 /* launched w/o TXT and VMX disabled */
2852 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2853 && !tboot_enabled())
2854 return 1;
cafd6659
SW		 2855 }
2856
2857 return 0;
6aa8b732
AK		 2858}
2859
7725b894
DX		 2860static void kvm_cpu_vmxon(u64 addr)
2861{
2862 asm volatile (ASM_VMX_VMXON_RAX
2863 : : "a"(&addr), "m"(addr)
2864 : "memory", "cc");
2865}
2866
13a34e06 2867static int hardware_enable(void)
6aa8b732
AK		 2868{
2869 int cpu = raw_smp_processor_id();
2870 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2871 u64 old, test_bits;
6aa8b732 2872
1e02ce4c 2873 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 2874 return -EBUSY;
2875
d462b819 2876 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2877
2878 /*
2879 * Now we can enable the vmclear operation in kdump
2880 * since the loaded_vmcss_on_cpu list on this cpu
2881 * has been initialized.
2882 *
2883 * Though the cpu is not in VMX operation now, there
2884 * is no problem to enable the vmclear operation
2885 * for the loaded_vmcss_on_cpu list is empty!
2886 */
2887 crash_enable_local_vmclear(cpu);
2888
6aa8b732 2889 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2890
2891 test_bits = FEATURE_CONTROL_LOCKED;
2892 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2893 if (tboot_enabled())
2894 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2895
2896 if ((old & test_bits) != test_bits) {
6aa8b732 2897 /* enable and lock */
cafd6659
SW		 2898 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2899 }
375074cc 2900 cr4_set_bits(X86_CR4_VMXE);
10474ae8 2901
4610c9cc
DX		 2902 if (vmm_exclusive) {
2903 kvm_cpu_vmxon(phys_addr);
2904 ept_sync_global();
2905 }
10474ae8 2906
89cbc767 2907 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2908
10474ae8 2909 return 0;
6aa8b732
AK		 2910}
2911
d462b819 2912static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2913{
2914 int cpu = raw_smp_processor_id();
d462b819 2915 struct loaded_vmcs *v, *n;
543e4243 2916
d462b819
NHE		 2917 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2918 loaded_vmcss_on_cpu_link)
2919 __loaded_vmcs_clear(v);
543e4243
AK		 2920}
2921
710ff4a8
EH		 2922
2923/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2924 * tricks.
2925 */
2926static void kvm_cpu_vmxoff(void)
6aa8b732 2927{
4ecac3fd 2928 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2929}
2930
13a34e06 2931static void hardware_disable(void)
710ff4a8 2932{
4610c9cc 2933 if (vmm_exclusive) {
d462b819 2934 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2935 kvm_cpu_vmxoff();
2936 }
375074cc 2937 cr4_clear_bits(X86_CR4_VMXE);
710ff4a8
EH		 2938}
2939
1c3d14fe 2940static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2941 u32 msr, u32 *result)
1c3d14fe
YS		 2942{
2943 u32 vmx_msr_low, vmx_msr_high;
2944 u32 ctl = ctl_min | ctl_opt;
2945
2946 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2947
2948 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2949 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2950
2951 /* Ensure minimum (required) set of control bits are supported. */
2952 if (ctl_min & ~ctl)
002c7f7c 2953 return -EIO;
1c3d14fe
YS		 2954
2955 *result = ctl;
2956 return 0;
2957}
2958
110312c8
AK		 2959static __init bool allow_1_setting(u32 msr, u32 ctl)
2960{
2961 u32 vmx_msr_low, vmx_msr_high;
2962
2963 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2964 return vmx_msr_high & ctl;
2965}
2966
002c7f7c 2967static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2968{
2969 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2970 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2971 u32 _pin_based_exec_control = 0;
2972 u32 _cpu_based_exec_control = 0;
f78e0e2e 2973 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2974 u32 _vmexit_control = 0;
2975 u32 _vmentry_control = 0;
2976
10166744 2977 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2978#ifdef CONFIG_X86_64
2979 CPU_BASED_CR8_LOAD_EXITING |
2980 CPU_BASED_CR8_STORE_EXITING |
2981#endif
d56f546d
SY		 2982 CPU_BASED_CR3_LOAD_EXITING |
2983 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2984 CPU_BASED_USE_IO_BITMAPS |
2985 CPU_BASED_MOV_DR_EXITING |
a7052897 2986 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2987 CPU_BASED_MWAIT_EXITING |
2988 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2989 CPU_BASED_INVLPG_EXITING |
2990 CPU_BASED_RDPMC_EXITING;
443381a8 2991
f78e0e2e 2992 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2993 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2994 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2995 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2996 &_cpu_based_exec_control) < 0)
002c7f7c 2997 return -EIO;
6e5d865c
YS		 2998#ifdef CONFIG_X86_64
2999 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3000 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3001 ~CPU_BASED_CR8_STORE_EXITING;
3002#endif
f78e0e2e 3003 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 3004 min2 = 0;
3005 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 3006 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 3007 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 3008 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 3009 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 3010 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 3011 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 3012 SECONDARY_EXEC_RDTSCP |
83d4c286 3013 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 3014 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 3015 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 3016 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 3017 SECONDARY_EXEC_XSAVES |
3018 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 3019 if (adjust_vmx_controls(min2, opt2,
3020 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 3021 &_cpu_based_2nd_exec_control) < 0)
3022 return -EIO;
3023 }
3024#ifndef CONFIG_X86_64
3025 if (!(_cpu_based_2nd_exec_control &
3026 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3027 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3028#endif
83d4c286
YZ		 3029
3030 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3031 _cpu_based_2nd_exec_control &= ~(
8d14695f 3032 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 3033 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3034 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 3035
d56f546d 3036 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 3037 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3038 enabled */
5fff7d27
GN		 3039 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3040 CPU_BASED_CR3_STORE_EXITING |
3041 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 3042 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3043 vmx_capability.ept, vmx_capability.vpid);
3044 }
1c3d14fe 3045
81908bf4 3046 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 3047#ifdef CONFIG_X86_64
3048 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3049#endif
a547c6db 3050 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 3051 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 3052 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3053 &_vmexit_control) < 0)
002c7f7c 3054 return -EIO;
1c3d14fe 3055
01e439be
YZ		 3056 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3057 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3058 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3059 &_pin_based_exec_control) < 0)
3060 return -EIO;
3061
3062 if (!(_cpu_based_2nd_exec_control &
3063 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3064 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3065 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3066
c845f9c6 3067 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 3068 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 3069 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3070 &_vmentry_control) < 0)
002c7f7c 3071 return -EIO;
6aa8b732 3072
c68876fd 3073 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 3074
3075 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3076 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3077 return -EIO;
1c3d14fe
YS		 3078
3079#ifdef CONFIG_X86_64
3080 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3081 if (vmx_msr_high & (1u<<16))
002c7f7c 3082 return -EIO;
1c3d14fe
YS		 3083#endif
3084
3085 /* Require Write-Back (WB) memory type for VMCS accesses. */
3086 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3087 return -EIO;
1c3d14fe 3088
002c7f7c
YS		 3089 vmcs_conf->size = vmx_msr_high & 0x1fff;
3090 vmcs_conf->order = get_order(vmcs_config.size);
3091 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3092
002c7f7c
YS		 3093 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3094 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3095 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3096 vmcs_conf->vmexit_ctrl = _vmexit_control;
3097 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3098
110312c8
AK		 3099 cpu_has_load_ia32_efer =
3100 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3101 VM_ENTRY_LOAD_IA32_EFER)
3102 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3103 VM_EXIT_LOAD_IA32_EFER);
3104
8bf00a52
GN		 3105 cpu_has_load_perf_global_ctrl =
3106 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3107 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3108 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3109 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3110
3111 /*
3112 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3113 * but due to arrata below it can't be used. Workaround is to use
3114 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3115 *
3116 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3117 *
3118 * AAK155 (model 26)
3119 * AAP115 (model 30)
3120 * AAT100 (model 37)
3121 * BC86,AAY89,BD102 (model 44)
3122 * BA97 (model 46)
3123 *
3124 */
3125 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3126 switch (boot_cpu_data.x86_model) {
3127 case 26:
3128 case 30:
3129 case 37:
3130 case 44:
3131 case 46:
3132 cpu_has_load_perf_global_ctrl = false;
3133 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3134 "does not work properly. Using workaround\n");
3135 break;
3136 default:
3137 break;
3138 }
3139 }
3140
20300099
WL		 3141 if (cpu_has_xsaves)
3142 rdmsrl(MSR_IA32_XSS, host_xss);
3143
1c3d14fe 3144 return 0;
c68876fd 3145}
6aa8b732
AK		 3146
3147static struct vmcs *alloc_vmcs_cpu(int cpu)
3148{
3149 int node = cpu_to_node(cpu);
3150 struct page *pages;
3151 struct vmcs *vmcs;
3152
96db800f 3153 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3154 if (!pages)
3155 return NULL;
3156 vmcs = page_address(pages);
1c3d14fe
YS		 3157 memset(vmcs, 0, vmcs_config.size);
3158 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3159 return vmcs;
3160}
3161
3162static struct vmcs *alloc_vmcs(void)
3163{
d3b2c338 3164 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3165}
3166
3167static void free_vmcs(struct vmcs *vmcs)
3168{
1c3d14fe 3169 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3170}
3171
d462b819
NHE		 3172/*
3173 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3174 */
3175static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3176{
3177 if (!loaded_vmcs->vmcs)
3178 return;
3179 loaded_vmcs_clear(loaded_vmcs);
3180 free_vmcs(loaded_vmcs->vmcs);
3181 loaded_vmcs->vmcs = NULL;
3182}
3183
39959588 3184static void free_kvm_area(void)
6aa8b732
AK		 3185{
3186 int cpu;
3187
3230bb47 3188 for_each_possible_cpu(cpu) {
6aa8b732 3189 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3190 per_cpu(vmxarea, cpu) = NULL;
3191 }
6aa8b732
AK		 3192}
3193
fe2b201b
BD		 3194static void init_vmcs_shadow_fields(void)
3195{
3196 int i, j;
3197
3198 /* No checks for read only fields yet */
3199
3200 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3201 switch (shadow_read_write_fields[i]) {
3202 case GUEST_BNDCFGS:
3203 if (!vmx_mpx_supported())
3204 continue;
3205 break;
3206 default:
3207 break;
3208 }
3209
3210 if (j < i)
3211 shadow_read_write_fields[j] =
3212 shadow_read_write_fields[i];
3213 j++;
3214 }
3215 max_shadow_read_write_fields = j;
3216
3217 /* shadowed fields guest access without vmexit */
3218 for (i = 0; i < max_shadow_read_write_fields; i++) {
3219 clear_bit(shadow_read_write_fields[i],
3220 vmx_vmwrite_bitmap);
3221 clear_bit(shadow_read_write_fields[i],
3222 vmx_vmread_bitmap);
3223 }
3224 for (i = 0; i < max_shadow_read_only_fields; i++)
3225 clear_bit(shadow_read_only_fields[i],
3226 vmx_vmread_bitmap);
3227}
3228
6aa8b732
AK		 3229static __init int alloc_kvm_area(void)
3230{
3231 int cpu;
3232
3230bb47 3233 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3234 struct vmcs *vmcs;
3235
3236 vmcs = alloc_vmcs_cpu(cpu);
3237 if (!vmcs) {
3238 free_kvm_area();
3239 return -ENOMEM;
3240 }
3241
3242 per_cpu(vmxarea, cpu) = vmcs;
3243 }
3244 return 0;
3245}
3246
14168786
GN		 3247static bool emulation_required(struct kvm_vcpu *vcpu)
3248{
3249 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3250}
3251
91b0aa2c 3252static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3253 struct kvm_segment *save)
6aa8b732 3254{
d99e4152
GN		 3255 if (!emulate_invalid_guest_state) {
3256 /*
3257 * CS and SS RPL should be equal during guest entry according
3258 * to VMX spec, but in reality it is not always so. Since vcpu
3259 * is in the middle of the transition from real mode to
3260 * protected mode it is safe to assume that RPL 0 is a good
3261 * default value.
3262 */
3263 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 3264 save->selector &= ~SEGMENT_RPL_MASK;
3265 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 3266 save->s = 1;
6aa8b732 3267 }
d99e4152 3268 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3269}
3270
3271static void enter_pmode(struct kvm_vcpu *vcpu)
3272{
3273 unsigned long flags;
a89a8fb9 3274 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3275
d99e4152
GN		 3276 /*
3277 * Update real mode segment cache. It may be not up-to-date if sement
3278 * register was written while vcpu was in a guest mode.
3279 */
3280 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3281 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3282 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3283 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3284 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3285 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3286
7ffd92c5 3287 vmx->rmode.vm86_active = 0;
6aa8b732 3288
2fb92db1
AK		 3289 vmx_segment_cache_clear(vmx);
3290
f5f7b2fe 3291 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3292
3293 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3294 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3295 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3296 vmcs_writel(GUEST_RFLAGS, flags);
3297
66aee91a
RR		 3298 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3299 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3300
3301 update_exception_bitmap(vcpu);
3302
91b0aa2c
GN		 3303 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3304 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3305 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3306 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3307 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3308 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3309}
3310
f5f7b2fe 3311static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3312{
772e0318 3313 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3314 struct kvm_segment var = *save;
3315
3316 var.dpl = 0x3;
3317 if (seg == VCPU_SREG_CS)
3318 var.type = 0x3;
3319
3320 if (!emulate_invalid_guest_state) {
3321 var.selector = var.base >> 4;
3322 var.base = var.base & 0xffff0;
3323 var.limit = 0xffff;
3324 var.g = 0;
3325 var.db = 0;
3326 var.present = 1;
3327 var.s = 1;
3328 var.l = 0;
3329 var.unusable = 0;
3330 var.type = 0x3;
3331 var.avl = 0;
3332 if (save->base & 0xf)
3333 printk_once(KERN_WARNING "kvm: segment base is not "
3334 "paragraph aligned when entering "
3335 "protected mode (seg=%d)", seg);
3336 }
6aa8b732 3337
d99e4152
GN		 3338 vmcs_write16(sf->selector, var.selector);
3339 vmcs_write32(sf->base, var.base);
3340 vmcs_write32(sf->limit, var.limit);
3341 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3342}
3343
3344static void enter_rmode(struct kvm_vcpu *vcpu)
3345{
3346 unsigned long flags;
a89a8fb9 3347 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3348
f5f7b2fe
AK		 3349 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3350 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3351 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3352 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3353 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3354 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3355 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3356
7ffd92c5 3357 vmx->rmode.vm86_active = 1;
6aa8b732 3358
776e58ea
GN		 3359 /*
3360 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3361 * vcpu. Warn the user that an update is overdue.
776e58ea 3362 */
4918c6ca 3363 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3364 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3365 "called before entering vcpu\n");
776e58ea 3366
2fb92db1
AK		 3367 vmx_segment_cache_clear(vmx);
3368
4918c6ca 3369 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3370 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3371 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3372
3373 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3374 vmx->rmode.save_rflags = flags;
6aa8b732 3375
053de044 3376 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3377
3378 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3379 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3380 update_exception_bitmap(vcpu);
3381
d99e4152
GN		 3382 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3383 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3384 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3385 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3386 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3387 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3388
8668a3c4 3389 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3390}
3391
401d10de
AS		 3392static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3393{
3394 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3395 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3396
3397 if (!msr)
3398 return;
401d10de 3399
44ea2b17
AK		 3400 /*
3401 * Force kernel_gs_base reloading before EFER changes, as control
3402 * of this msr depends on is_long_mode().
3403 */
3404 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3405 vcpu->arch.efer = efer;
401d10de 3406 if (efer & EFER_LMA) {
2961e876 3407 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3408 msr->data = efer;
3409 } else {
2961e876 3410 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3411
3412 msr->data = efer & ~EFER_LME;
3413 }
3414 setup_msrs(vmx);
3415}
3416
05b3e0c2 3417#ifdef CONFIG_X86_64
6aa8b732
AK		 3418
3419static void enter_lmode(struct kvm_vcpu *vcpu)
3420{
3421 u32 guest_tr_ar;
3422
2fb92db1
AK		 3423 vmx_segment_cache_clear(to_vmx(vcpu));
3424
6aa8b732 3425 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 3426 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3427 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3428 __func__);
6aa8b732 3429 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 3430 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3431 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 3432 }
da38f438 3433 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3434}
3435
3436static void exit_lmode(struct kvm_vcpu *vcpu)
3437{
2961e876 3438 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3439 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3440}
3441
3442#endif
3443
2384d2b3
SY		 3444static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3445{
b9d762fa 3446 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3447 if (enable_ept) {
3448 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3449 return;
4e1096d2 3450 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3451 }
2384d2b3
SY		 3452}
3453
e8467fda
AK		 3454static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3455{
3456 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3457
3458 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3459 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3460}
3461
aff48baa
AK		 3462static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3463{
3464 if (enable_ept && is_paging(vcpu))
3465 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3466 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3467}
3468
25c4c276 3469static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3470{
fc78f519
AK		 3471 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3472
3473 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3474 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3475}
3476
1439442c
SY		 3477static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3478{
d0d538b9
GN		 3479 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3480
6de4f3ad
AK		 3481 if (!test_bit(VCPU_EXREG_PDPTR,
3482 (unsigned long *)&vcpu->arch.regs_dirty))
3483 return;
3484
1439442c 3485 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3486 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3487 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3488 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3489 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3490 }
3491}
3492
8f5d549f
AK		 3493static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3494{
d0d538b9
GN		 3495 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3496
8f5d549f 3497 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3498 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3499 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3500 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3501 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3502 }
6de4f3ad
AK		 3503
3504 __set_bit(VCPU_EXREG_PDPTR,
3505 (unsigned long *)&vcpu->arch.regs_avail);
3506 __set_bit(VCPU_EXREG_PDPTR,
3507 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3508}
3509
5e1746d6 3510static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3511
3512static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3513 unsigned long cr0,
3514 struct kvm_vcpu *vcpu)
3515{
5233dd51
MT		 3516 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3517 vmx_decache_cr3(vcpu);
1439442c
SY		 3518 if (!(cr0 & X86_CR0_PG)) {
3519 /* From paging/starting to nonpaging */
3520 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3521 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3522 (CPU_BASED_CR3_LOAD_EXITING |
3523 CPU_BASED_CR3_STORE_EXITING));
3524 vcpu->arch.cr0 = cr0;
fc78f519 3525 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3526 } else if (!is_paging(vcpu)) {
3527 /* From nonpaging to paging */
3528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3529 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3530 ~(CPU_BASED_CR3_LOAD_EXITING |
3531 CPU_BASED_CR3_STORE_EXITING));
3532 vcpu->arch.cr0 = cr0;
fc78f519 3533 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3534 }
95eb84a7
SY		 3535
3536 if (!(cr0 & X86_CR0_WP))
3537 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3538}
3539
6aa8b732
AK		 3540static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3541{
7ffd92c5 3542 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3543 unsigned long hw_cr0;
3544
5037878e 3545 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3546 if (enable_unrestricted_guest)
5037878e 3547 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3548 else {
5037878e 3549 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3550
218e763f
GN		 3551 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3552 enter_pmode(vcpu);
6aa8b732 3553
218e763f
GN		 3554 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3555 enter_rmode(vcpu);
3556 }
6aa8b732 3557
05b3e0c2 3558#ifdef CONFIG_X86_64
f6801dff 3559 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3560 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3561 enter_lmode(vcpu);
707d92fa 3562 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3563 exit_lmode(vcpu);
3564 }
3565#endif
3566
089d034e 3567 if (enable_ept)
1439442c
SY		 3568 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3569
02daab21 3570 if (!vcpu->fpu_active)
81231c69 3571 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3572
6aa8b732 3573 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3574 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3575 vcpu->arch.cr0 = cr0;
14168786
GN		 3576
3577 /* depends on vcpu->arch.cr0 to be set to a new value */
3578 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3579}
3580
1439442c
SY		 3581static u64 construct_eptp(unsigned long root_hpa)
3582{
3583 u64 eptp;
3584
3585 /* TODO write the value reading from MSR */
3586 eptp = VMX_EPT_DEFAULT_MT |
3587 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3588 if (enable_ept_ad_bits)
3589 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3590 eptp |= (root_hpa & PAGE_MASK);
3591
3592 return eptp;
3593}
3594
6aa8b732
AK		 3595static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3596{
1439442c
SY		 3597 unsigned long guest_cr3;
3598 u64 eptp;
3599
3600 guest_cr3 = cr3;
089d034e 3601 if (enable_ept) {
1439442c
SY		 3602 eptp = construct_eptp(cr3);
3603 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3604 if (is_paging(vcpu) || is_guest_mode(vcpu))
3605 guest_cr3 = kvm_read_cr3(vcpu);
3606 else
3607 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3608 ept_load_pdptrs(vcpu);
1439442c
SY		 3609 }
3610
2384d2b3 3611 vmx_flush_tlb(vcpu);
1439442c 3612 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3613}
3614
5e1746d6 3615static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3616{
085e68ee
BS		 3617 /*
3618 * Pass through host's Machine Check Enable value to hw_cr4, which
3619 * is in force while we are in guest mode. Do not let guests control
3620 * this bit, even if host CR4.MCE == 0.
3621 */
3622 unsigned long hw_cr4 =
3623 (cr4_read_shadow() & X86_CR4_MCE) |
3624 (cr4 & ~X86_CR4_MCE) |
3625 (to_vmx(vcpu)->rmode.vm86_active ?
3626 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1439442c 3627
5e1746d6
NHE		 3628 if (cr4 & X86_CR4_VMXE) {
3629 /*
3630 * To use VMXON (and later other VMX instructions), a guest
3631 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3632 * So basically the check on whether to allow nested VMX
3633 * is here.
3634 */
3635 if (!nested_vmx_allowed(vcpu))
3636 return 1;
1a0d74e6
JK		 3637 }
3638 if (to_vmx(vcpu)->nested.vmxon &&
3639 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3640 return 1;
3641
ad312c7c 3642 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3643 if (enable_ept) {
3644 if (!is_paging(vcpu)) {
3645 hw_cr4 &= ~X86_CR4_PAE;
3646 hw_cr4 |= X86_CR4_PSE;
c08800a5 3647 /*
e1e746b3
FW		 3648 * SMEP/SMAP is disabled if CPU is in non-paging mode
3649 * in hardware. However KVM always uses paging mode to
c08800a5 3650 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3651 * To emulate this behavior, SMEP/SMAP needs to be
3652 * manually disabled when guest switches to non-paging
3653 * mode.
c08800a5 3654 */
e1e746b3 3655 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3656 } else if (!(cr4 & X86_CR4_PAE)) {
3657 hw_cr4 &= ~X86_CR4_PAE;
3658 }
3659 }
1439442c
SY		 3660
3661 vmcs_writel(CR4_READ_SHADOW, cr4);
3662 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3663 return 0;
6aa8b732
AK		 3664}
3665
6aa8b732
AK		 3666static void vmx_get_segment(struct kvm_vcpu *vcpu,
3667 struct kvm_segment *var, int seg)
3668{
a9179499 3669 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3670 u32 ar;
3671
c6ad1153 3672 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3673 *var = vmx->rmode.segs[seg];
a9179499 3674 if (seg == VCPU_SREG_TR
2fb92db1 3675 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3676 return;
1390a28b
AK		 3677 var->base = vmx_read_guest_seg_base(vmx, seg);
3678 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3679 return;
a9179499 3680 }
2fb92db1
AK		 3681 var->base = vmx_read_guest_seg_base(vmx, seg);
3682 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3683 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3684 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3685 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3686 var->type = ar & 15;
3687 var->s = (ar >> 4) & 1;
3688 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3689 /*
3690 * Some userspaces do not preserve unusable property. Since usable
3691 * segment has to be present according to VMX spec we can use present
3692 * property to amend userspace bug by making unusable segment always
3693 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3694 * segment as unusable.
3695 */
3696 var->present = !var->unusable;
6aa8b732
AK		 3697 var->avl = (ar >> 12) & 1;
3698 var->l = (ar >> 13) & 1;
3699 var->db = (ar >> 14) & 1;
3700 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3701}
3702
a9179499
AK		 3703static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3704{
a9179499
AK		 3705 struct kvm_segment s;
3706
3707 if (to_vmx(vcpu)->rmode.vm86_active) {
3708 vmx_get_segment(vcpu, &s, seg);
3709 return s.base;
3710 }
2fb92db1 3711 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3712}
3713
b09408d0 3714static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3715{
b09408d0
MT		 3716 struct vcpu_vmx *vmx = to_vmx(vcpu);
3717
ae9fedc7 3718 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3719 return 0;
ae9fedc7
PB		 3720 else {
3721 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 3722 return VMX_AR_DPL(ar);
69c73028 3723 }
69c73028
AK		 3724}
3725
653e3108 3726static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3727{
6aa8b732
AK		 3728 u32 ar;
3729
f0495f9b 3730 if (var->unusable || !var->present)
6aa8b732
AK		 3731 ar = 1 << 16;
3732 else {
3733 ar = var->type & 15;
3734 ar |= (var->s & 1) << 4;
3735 ar |= (var->dpl & 3) << 5;
3736 ar |= (var->present & 1) << 7;
3737 ar |= (var->avl & 1) << 12;
3738 ar |= (var->l & 1) << 13;
3739 ar |= (var->db & 1) << 14;
3740 ar |= (var->g & 1) << 15;
3741 }
653e3108
AK		 3742
3743 return ar;
3744}
3745
3746static void vmx_set_segment(struct kvm_vcpu *vcpu,
3747 struct kvm_segment *var, int seg)
3748{
7ffd92c5 3749 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3750 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3751
2fb92db1
AK		 3752 vmx_segment_cache_clear(vmx);
3753
1ecd50a9
GN		 3754 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3755 vmx->rmode.segs[seg] = *var;
3756 if (seg == VCPU_SREG_TR)
3757 vmcs_write16(sf->selector, var->selector);
3758 else if (var->s)
3759 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3760 goto out;
653e3108 3761 }
1ecd50a9 3762
653e3108
AK		 3763 vmcs_writel(sf->base, var->base);
3764 vmcs_write32(sf->limit, var->limit);
3765 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3766
3767 /*
3768 * Fix the "Accessed" bit in AR field of segment registers for older
3769 * qemu binaries.
3770 * IA32 arch specifies that at the time of processor reset the
3771 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3772 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3773 * state vmexit when "unrestricted guest" mode is turned on.
3774 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3775 * tree. Newer qemu binaries with that qemu fix would not need this
3776 * kvm hack.
3777 */
3778 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3779 var->type |= 0x1; /* Accessed */
3a624e29 3780
f924d66d 3781 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3782
3783out:
98eb2f8b 3784 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3785}
3786
6aa8b732
AK		 3787static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3788{
2fb92db1 3789 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3790
3791 *db = (ar >> 14) & 1;
3792 *l = (ar >> 13) & 1;
3793}
3794
89a27f4d 3795static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3796{
89a27f4d
GN		 3797 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3798 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3799}
3800
89a27f4d 3801static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3802{
89a27f4d
GN		 3803 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3804 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3805}
3806
89a27f4d 3807static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3808{
89a27f4d
GN		 3809 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3810 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3811}
3812
89a27f4d 3813static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3814{
89a27f4d
GN		 3815 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3816 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3817}
3818
648dfaa7
MG		 3819static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3820{
3821 struct kvm_segment var;
3822 u32 ar;
3823
3824 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3825 var.dpl = 0x3;
0647f4aa
GN		 3826 if (seg == VCPU_SREG_CS)
3827 var.type = 0x3;
648dfaa7
MG		 3828 ar = vmx_segment_access_rights(&var);
3829
3830 if (var.base != (var.selector << 4))
3831 return false;
89efbed0 3832 if (var.limit != 0xffff)
648dfaa7 3833 return false;
07f42f5f 3834 if (ar != 0xf3)
648dfaa7
MG		 3835 return false;
3836
3837 return true;
3838}
3839
3840static bool code_segment_valid(struct kvm_vcpu *vcpu)
3841{
3842 struct kvm_segment cs;
3843 unsigned int cs_rpl;
3844
3845 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 3846 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 3847
1872a3f4
AK		 3848 if (cs.unusable)
3849 return false;
4d283ec9 3850 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 3851 return false;
3852 if (!cs.s)
3853 return false;
4d283ec9 3854 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3855 if (cs.dpl > cs_rpl)
3856 return false;
1872a3f4 3857 } else {
648dfaa7
MG		 3858 if (cs.dpl != cs_rpl)
3859 return false;
3860 }
3861 if (!cs.present)
3862 return false;
3863
3864 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3865 return true;
3866}
3867
3868static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3869{
3870 struct kvm_segment ss;
3871 unsigned int ss_rpl;
3872
3873 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 3874 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 3875
1872a3f4
AK		 3876 if (ss.unusable)
3877 return true;
3878 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3879 return false;
3880 if (!ss.s)
3881 return false;
3882 if (ss.dpl != ss_rpl) /* DPL != RPL */
3883 return false;
3884 if (!ss.present)
3885 return false;
3886
3887 return true;
3888}
3889
3890static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3891{
3892 struct kvm_segment var;
3893 unsigned int rpl;
3894
3895 vmx_get_segment(vcpu, &var, seg);
b32a9918 3896 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 3897
1872a3f4
AK		 3898 if (var.unusable)
3899 return true;
648dfaa7
MG		 3900 if (!var.s)
3901 return false;
3902 if (!var.present)
3903 return false;
4d283ec9 3904 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 3905 if (var.dpl < rpl) /* DPL < RPL */
3906 return false;
3907 }
3908
3909 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3910 * rights flags
3911 */
3912 return true;
3913}
3914
3915static bool tr_valid(struct kvm_vcpu *vcpu)
3916{
3917 struct kvm_segment tr;
3918
3919 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3920
1872a3f4
AK		 3921 if (tr.unusable)
3922 return false;
b32a9918 3923 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 3924 return false;
1872a3f4 3925 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3926 return false;
3927 if (!tr.present)
3928 return false;
3929
3930 return true;
3931}
3932
3933static bool ldtr_valid(struct kvm_vcpu *vcpu)
3934{
3935 struct kvm_segment ldtr;
3936
3937 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3938
1872a3f4
AK		 3939 if (ldtr.unusable)
3940 return true;
b32a9918 3941 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 3942 return false;
3943 if (ldtr.type != 2)
3944 return false;
3945 if (!ldtr.present)
3946 return false;
3947
3948 return true;
3949}
3950
3951static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3952{
3953 struct kvm_segment cs, ss;
3954
3955 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3956 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3957
b32a9918
NA		 3958 return ((cs.selector & SEGMENT_RPL_MASK) ==
3959 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 3960}
3961
3962/*
3963 * Check if guest state is valid. Returns true if valid, false if
3964 * not.
3965 * We assume that registers are always usable
3966 */
3967static bool guest_state_valid(struct kvm_vcpu *vcpu)
3968{
c5e97c80
GN		 3969 if (enable_unrestricted_guest)
3970 return true;
3971
648dfaa7 3972 /* real mode guest state checks */
f13882d8 3973 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3974 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3975 return false;
3976 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3977 return false;
3978 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3979 return false;
3980 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3981 return false;
3982 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3983 return false;
3984 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3985 return false;
3986 } else {
3987 /* protected mode guest state checks */
3988 if (!cs_ss_rpl_check(vcpu))
3989 return false;
3990 if (!code_segment_valid(vcpu))
3991 return false;
3992 if (!stack_segment_valid(vcpu))
3993 return false;
3994 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3995 return false;
3996 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3997 return false;
3998 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3999 return false;
4000 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4001 return false;
4002 if (!tr_valid(vcpu))
4003 return false;
4004 if (!ldtr_valid(vcpu))
4005 return false;
4006 }
4007 /* TODO:
4008 * - Add checks on RIP
4009 * - Add checks on RFLAGS
4010 */
4011
4012 return true;
4013}
4014
d77c26fc 4015static int init_rmode_tss(struct kvm *kvm)
6aa8b732 4016{
40dcaa9f 4017 gfn_t fn;
195aefde 4018 u16 data = 0;
1f755a82 4019 int idx, r;
6aa8b732 4020
40dcaa9f 4021 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 4022 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 4023 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4024 if (r < 0)
10589a46 4025 goto out;
195aefde 4026 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 4027 r = kvm_write_guest_page(kvm, fn++, &data,
4028 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 4029 if (r < 0)
10589a46 4030 goto out;
195aefde
IE		 4031 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4032 if (r < 0)
10589a46 4033 goto out;
195aefde
IE		 4034 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4035 if (r < 0)
10589a46 4036 goto out;
195aefde 4037 data = ~0;
10589a46
MT		 4038 r = kvm_write_guest_page(kvm, fn, &data,
4039 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4040 sizeof(u8));
10589a46 4041out:
40dcaa9f 4042 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 4043 return r;
6aa8b732
AK		 4044}
4045
b7ebfb05
SY		 4046static int init_rmode_identity_map(struct kvm *kvm)
4047{
f51770ed 4048 int i, idx, r = 0;
b7ebfb05
SY		 4049 pfn_t identity_map_pfn;
4050 u32 tmp;
4051
089d034e 4052 if (!enable_ept)
f51770ed 4053 return 0;
a255d479
TC		 4054
4055 /* Protect kvm->arch.ept_identity_pagetable_done. */
4056 mutex_lock(&kvm->slots_lock);
4057
f51770ed 4058 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 4059 goto out2;
a255d479 4060
b927a3ce 4061 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 4062
4063 r = alloc_identity_pagetable(kvm);
f51770ed 4064 if (r < 0)
a255d479
TC		 4065 goto out2;
4066
40dcaa9f 4067 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 4068 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4069 if (r < 0)
4070 goto out;
4071 /* Set up identity-mapping pagetable for EPT in real mode */
4072 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4073 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4074 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4075 r = kvm_write_guest_page(kvm, identity_map_pfn,
4076 &tmp, i * sizeof(tmp), sizeof(tmp));
4077 if (r < 0)
4078 goto out;
4079 }
4080 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 4081
b7ebfb05 4082out:
40dcaa9f 4083 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4084
4085out2:
4086 mutex_unlock(&kvm->slots_lock);
f51770ed 4087 return r;
b7ebfb05
SY		 4088}
4089
6aa8b732
AK		 4090static void seg_setup(int seg)
4091{
772e0318 4092 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4093 unsigned int ar;
6aa8b732
AK		 4094
4095 vmcs_write16(sf->selector, 0);
4096 vmcs_writel(sf->base, 0);
4097 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4098 ar = 0x93;
4099 if (seg == VCPU_SREG_CS)
4100 ar |= 0x08; /* code segment */
3a624e29
NK		 4101
4102 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4103}
4104
f78e0e2e
SY		 4105static int alloc_apic_access_page(struct kvm *kvm)
4106{
4484141a 4107 struct page *page;
f78e0e2e
SY		 4108 struct kvm_userspace_memory_region kvm_userspace_mem;
4109 int r = 0;
4110
79fac95e 4111 mutex_lock(&kvm->slots_lock);
c24ae0dc 4112 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4113 goto out;
4114 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4115 kvm_userspace_mem.flags = 0;
73a6d941 4116 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4117 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4118 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4119 if (r)
4120 goto out;
72dc67a6 4121
73a6d941 4122 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4123 if (is_error_page(page)) {
4124 r = -EFAULT;
4125 goto out;
4126 }
4127
c24ae0dc
TC		 4128 /*
4129 * Do not pin the page in memory, so that memory hot-unplug
4130 * is able to migrate it.
4131 */
4132 put_page(page);
4133 kvm->arch.apic_access_page_done = true;
f78e0e2e 4134out:
79fac95e 4135 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4136 return r;
4137}
4138
b7ebfb05
SY		 4139static int alloc_identity_pagetable(struct kvm *kvm)
4140{
a255d479
TC		 4141 /* Called with kvm->slots_lock held. */
4142
b7ebfb05
SY		 4143 struct kvm_userspace_memory_region kvm_userspace_mem;
4144 int r = 0;
4145
a255d479
TC		 4146 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4147
b7ebfb05
SY		 4148 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4149 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4150 kvm_userspace_mem.guest_phys_addr =
4151 kvm->arch.ept_identity_map_addr;
b7ebfb05 4152 kvm_userspace_mem.memory_size = PAGE_SIZE;
9da0e4d5 4153 r = __x86_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4154
b7ebfb05
SY		 4155 return r;
4156}
4157
2384d2b3
SY		 4158static void allocate_vpid(struct vcpu_vmx *vmx)
4159{
4160 int vpid;
4161
4162 vmx->vpid = 0;
919818ab 4163 if (!enable_vpid)
2384d2b3
SY		 4164 return;
4165 spin_lock(&vmx_vpid_lock);
4166 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4167 if (vpid < VMX_NR_VPIDS) {
4168 vmx->vpid = vpid;
4169 __set_bit(vpid, vmx_vpid_bitmap);
4170 }
4171 spin_unlock(&vmx_vpid_lock);
4172}
4173
cdbecfc3
LJ		 4174static void free_vpid(struct vcpu_vmx *vmx)
4175{
4176 if (!enable_vpid)
4177 return;
4178 spin_lock(&vmx_vpid_lock);
4179 if (vmx->vpid != 0)
4180 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4181 spin_unlock(&vmx_vpid_lock);
4182}
4183
8d14695f
YZ		 4184#define MSR_TYPE_R 1
4185#define MSR_TYPE_W 2
4186static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4187 u32 msr, int type)
25c5f225 4188{
3e7c73e9 4189 int f = sizeof(unsigned long);
25c5f225
SY		 4190
4191 if (!cpu_has_vmx_msr_bitmap())
4192 return;
4193
4194 /*
4195 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4196 * have the write-low and read-high bitmap offsets the wrong way round.
4197 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4198 */
25c5f225 4199 if (msr <= 0x1fff) {
8d14695f
YZ		 4200 if (type & MSR_TYPE_R)
4201 /* read-low */
4202 __clear_bit(msr, msr_bitmap + 0x000 / f);
4203
4204 if (type & MSR_TYPE_W)
4205 /* write-low */
4206 __clear_bit(msr, msr_bitmap + 0x800 / f);
4207
25c5f225
SY		 4208 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4209 msr &= 0x1fff;
8d14695f
YZ		 4210 if (type & MSR_TYPE_R)
4211 /* read-high */
4212 __clear_bit(msr, msr_bitmap + 0x400 / f);
4213
4214 if (type & MSR_TYPE_W)
4215 /* write-high */
4216 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4217
4218 }
4219}
4220
4221static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4222 u32 msr, int type)
4223{
4224 int f = sizeof(unsigned long);
4225
4226 if (!cpu_has_vmx_msr_bitmap())
4227 return;
4228
4229 /*
4230 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4231 * have the write-low and read-high bitmap offsets the wrong way round.
4232 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4233 */
4234 if (msr <= 0x1fff) {
4235 if (type & MSR_TYPE_R)
4236 /* read-low */
4237 __set_bit(msr, msr_bitmap + 0x000 / f);
4238
4239 if (type & MSR_TYPE_W)
4240 /* write-low */
4241 __set_bit(msr, msr_bitmap + 0x800 / f);
4242
4243 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4244 msr &= 0x1fff;
4245 if (type & MSR_TYPE_R)
4246 /* read-high */
4247 __set_bit(msr, msr_bitmap + 0x400 / f);
4248
4249 if (type & MSR_TYPE_W)
4250 /* write-high */
4251 __set_bit(msr, msr_bitmap + 0xc00 / f);
4252
25c5f225 4253 }
25c5f225
SY		 4254}
4255
f2b93280
WV		 4256/*
4257 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4258 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4259 */
4260static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4261 unsigned long *msr_bitmap_nested,
4262 u32 msr, int type)
4263{
4264 int f = sizeof(unsigned long);
4265
4266 if (!cpu_has_vmx_msr_bitmap()) {
4267 WARN_ON(1);
4268 return;
4269 }
4270
4271 /*
4272 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4273 * have the write-low and read-high bitmap offsets the wrong way round.
4274 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4275 */
4276 if (msr <= 0x1fff) {
4277 if (type & MSR_TYPE_R &&
4278 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4279 /* read-low */
4280 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4281
4282 if (type & MSR_TYPE_W &&
4283 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4284 /* write-low */
4285 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4286
4287 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4288 msr &= 0x1fff;
4289 if (type & MSR_TYPE_R &&
4290 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4291 /* read-high */
4292 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4293
4294 if (type & MSR_TYPE_W &&
4295 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4296 /* write-high */
4297 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4298
4299 }
4300}
4301
5897297b
AK		 4302static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4303{
4304 if (!longmode_only)
8d14695f
YZ		 4305 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4306 msr, MSR_TYPE_R | MSR_TYPE_W);
4307 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4308 msr, MSR_TYPE_R | MSR_TYPE_W);
4309}
4310
4311static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4312{
4313 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4314 msr, MSR_TYPE_R);
4315 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4316 msr, MSR_TYPE_R);
4317}
4318
4319static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4320{
4321 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4322 msr, MSR_TYPE_R);
4323 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4324 msr, MSR_TYPE_R);
4325}
4326
4327static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4328{
4329 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4330 msr, MSR_TYPE_W);
4331 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4332 msr, MSR_TYPE_W);
5897297b
AK		 4333}
4334
d50ab6c1
PB		 4335static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4336{
35754c98 4337 return enable_apicv && lapic_in_kernel(vcpu);
d50ab6c1
PB		 4338}
4339
705699a1
WV		 4340static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4341{
4342 struct vcpu_vmx *vmx = to_vmx(vcpu);
4343 int max_irr;
4344 void *vapic_page;
4345 u16 status;
4346
4347 if (vmx->nested.pi_desc &&
4348 vmx->nested.pi_pending) {
4349 vmx->nested.pi_pending = false;
4350 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4351 return 0;
4352
4353 max_irr = find_last_bit(
4354 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4355
4356 if (max_irr == 256)
4357 return 0;
4358
4359 vapic_page = kmap(vmx->nested.virtual_apic_page);
4360 if (!vapic_page) {
4361 WARN_ON(1);
4362 return -ENOMEM;
4363 }
4364 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4365 kunmap(vmx->nested.virtual_apic_page);
4366
4367 status = vmcs_read16(GUEST_INTR_STATUS);
4368 if ((u8)max_irr > ((u8)status & 0xff)) {
4369 status &= ~0xff;
4370 status |= (u8)max_irr;
4371 vmcs_write16(GUEST_INTR_STATUS, status);
4372 }
4373 }
4374 return 0;
4375}
4376
21bc8dc5
RK		 4377static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4378{
4379#ifdef CONFIG_SMP
4380 if (vcpu->mode == IN_GUEST_MODE) {
4381 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4382 POSTED_INTR_VECTOR);
4383 return true;
4384 }
4385#endif
4386 return false;
4387}
4388
705699a1
WV		 4389static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4390 int vector)
4391{
4392 struct vcpu_vmx *vmx = to_vmx(vcpu);
4393
4394 if (is_guest_mode(vcpu) &&
4395 vector == vmx->nested.posted_intr_nv) {
4396 /* the PIR and ON have been set by L1. */
21bc8dc5 4397 kvm_vcpu_trigger_posted_interrupt(vcpu);
705699a1
WV		 4398 /*
4399 * If a posted intr is not recognized by hardware,
4400 * we will accomplish it in the next vmentry.
4401 */
4402 vmx->nested.pi_pending = true;
4403 kvm_make_request(KVM_REQ_EVENT, vcpu);
4404 return 0;
4405 }
4406 return -1;
4407}
a20ed54d
YZ		 4408/*
4409 * Send interrupt to vcpu via posted interrupt way.
4410 * 1. If target vcpu is running(non-root mode), send posted interrupt
4411 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4412 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4413 * interrupt from PIR in next vmentry.
4414 */
4415static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4416{
4417 struct vcpu_vmx *vmx = to_vmx(vcpu);
4418 int r;
4419
705699a1
WV		 4420 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4421 if (!r)
4422 return;
4423
a20ed54d
YZ		 4424 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4425 return;
4426
4427 r = pi_test_and_set_on(&vmx->pi_desc);
4428 kvm_make_request(KVM_REQ_EVENT, vcpu);
21bc8dc5 4429 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
a20ed54d
YZ		 4430 kvm_vcpu_kick(vcpu);
4431}
4432
4433static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4434{
4435 struct vcpu_vmx *vmx = to_vmx(vcpu);
4436
4437 if (!pi_test_and_clear_on(&vmx->pi_desc))
4438 return;
4439
4440 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4441}
4442
4443static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4444{
4445 return;
4446}
4447
a3a8ff8e
NHE		 4448/*
4449 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4450 * will not change in the lifetime of the guest.
4451 * Note that host-state that does change is set elsewhere. E.g., host-state
4452 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4453 */
a547c6db 4454static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4455{
4456 u32 low32, high32;
4457 unsigned long tmpl;
4458 struct desc_ptr dt;
d974baa3 4459 unsigned long cr4;
a3a8ff8e 4460
b1a74bf8 4461 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4462 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4463
d974baa3 4464 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 4465 cr4 = cr4_read_shadow();
d974baa3
AL		 4466 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4467 vmx->host_state.vmcs_host_cr4 = cr4;
4468
a3a8ff8e 4469 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4470#ifdef CONFIG_X86_64
4471 /*
4472 * Load null selectors, so we can avoid reloading them in
4473 * __vmx_load_host_state(), in case userspace uses the null selectors
4474 * too (the expected case).
4475 */
4476 vmcs_write16(HOST_DS_SELECTOR, 0);
4477 vmcs_write16(HOST_ES_SELECTOR, 0);
4478#else
a3a8ff8e
NHE		 4479 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4480 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4481#endif
a3a8ff8e
NHE		 4482 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4483 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4484
4485 native_store_idt(&dt);
4486 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4487 vmx->host_idt_base = dt.address;
a3a8ff8e 4488
83287ea4 4489 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4490
4491 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4492 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4493 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4494 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4495
4496 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4497 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4498 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4499 }
4500}
4501
bf8179a0
NHE		 4502static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4503{
4504 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4505 if (enable_ept)
4506 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4507 if (is_guest_mode(&vmx->vcpu))
4508 vmx->vcpu.arch.cr4_guest_owned_bits &=
4509 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4510 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4511}
4512
01e439be
YZ		 4513static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4514{
4515 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4516
35754c98 4517 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
01e439be
YZ		 4518 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4519 return pin_based_exec_ctrl;
4520}
4521
bf8179a0
NHE		 4522static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4523{
4524 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4525
4526 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4527 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4528
35754c98 4529 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
bf8179a0
NHE		 4530 exec_control &= ~CPU_BASED_TPR_SHADOW;
4531#ifdef CONFIG_X86_64
4532 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4533 CPU_BASED_CR8_LOAD_EXITING;
4534#endif
4535 }
4536 if (!enable_ept)
4537 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4538 CPU_BASED_CR3_LOAD_EXITING |
4539 CPU_BASED_INVLPG_EXITING;
4540 return exec_control;
4541}
4542
4543static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4544{
4545 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
35754c98 4546 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
bf8179a0
NHE		 4547 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4548 if (vmx->vpid == 0)
4549 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4550 if (!enable_ept) {
4551 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4552 enable_unrestricted_guest = 0;
ad756a16
MJ		 4553 /* Enable INVPCID for non-ept guests may cause performance regression. */
4554 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4555 }
4556 if (!enable_unrestricted_guest)
4557 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4558 if (!ple_gap)
4559 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
35754c98 4560 if (!vmx_cpu_uses_apicv(&vmx->vcpu))
c7c9c56c
YZ		 4561 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4562 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4563 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4564 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4565 (handle_vmptrld).
4566 We can NOT enable shadow_vmcs here because we don't have yet
4567 a current VMCS12
4568 */
4569 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4570 /* PML is enabled/disabled in creating/destorying vcpu */
4571 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4572
bf8179a0
NHE		 4573 return exec_control;
4574}
4575
ce88decf
XG		 4576static void ept_set_mmio_spte_mask(void)
4577{
4578 /*
4579 * EPT Misconfigurations can be generated if the value of bits 2:0
4580 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4581 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4582 * spte.
4583 */
885032b9 4584 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4585}
4586
f53cd63c 4587#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4588/*
4589 * Sets up the vmcs for emulated real mode.
4590 */
8b9cf98c 4591static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4592{
2e4ce7f5 4593#ifdef CONFIG_X86_64
6aa8b732 4594 unsigned long a;
2e4ce7f5 4595#endif
6aa8b732 4596 int i;
6aa8b732 4597
6aa8b732 4598 /* I/O */
3e7c73e9
AK		 4599 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4600 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4601
4607c2d7
AG		 4602 if (enable_shadow_vmcs) {
4603 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4604 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4605 }
25c5f225 4606 if (cpu_has_vmx_msr_bitmap())
5897297b 4607 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4608
6aa8b732
AK		 4609 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4610
6aa8b732 4611 /* Control */
01e439be 4612 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4613
bf8179a0 4614 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4615
83ff3b9d 4616 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4617 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4618 vmx_secondary_exec_control(vmx));
83ff3b9d 4619 }
f78e0e2e 4620
35754c98 4621 if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
c7c9c56c
YZ		 4622 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4623 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4624 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4625 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4626
4627 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4628
4629 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4630 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4631 }
4632
4b8d54f9
ZE		 4633 if (ple_gap) {
4634 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4635 vmx->ple_window = ple_window;
4636 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4637 }
4638
c3707958
XG		 4639 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4640 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4641 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4642
9581d442
AK		 4643 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4644 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4645 vmx_set_constant_host_state(vmx);
05b3e0c2 4646#ifdef CONFIG_X86_64
6aa8b732
AK		 4647 rdmsrl(MSR_FS_BASE, a);
4648 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4649 rdmsrl(MSR_GS_BASE, a);
4650 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4651#else
4652 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4653 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4654#endif
4655
2cc51560
ED		 4656 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4657 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4658 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4659 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4660 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4661
74545705
RK		 4662 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4663 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 4664
03916db9 4665 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4666 u32 index = vmx_msr_index[i];
4667 u32 data_low, data_high;
a2fa3e9f 4668 int j = vmx->nmsrs;
6aa8b732
AK		 4669
4670 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4671 continue;
432bd6cb
AK		 4672 if (wrmsr_safe(index, data_low, data_high) < 0)
4673 continue;
26bb0981
AK		 4674 vmx->guest_msrs[j].index = i;
4675 vmx->guest_msrs[j].data = 0;
d5696725 4676 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4677 ++vmx->nmsrs;
6aa8b732 4678 }
6aa8b732 4679
2961e876
GN		 4680
4681 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4682
4683 /* 22.2.1, 20.8.1 */
2961e876 4684 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4685
e00c8cf2 4686 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4687 set_cr4_guest_host_mask(vmx);
e00c8cf2 4688
f53cd63c
WL		 4689 if (vmx_xsaves_supported())
4690 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4691
e00c8cf2
AK		 4692 return 0;
4693}
4694
d28bc9dd 4695static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 4696{
4697 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4698 struct msr_data apic_base_msr;
d28bc9dd 4699 u64 cr0;
e00c8cf2 4700
7ffd92c5 4701 vmx->rmode.vm86_active = 0;
e00c8cf2 4702
3b86cd99
JK		 4703 vmx->soft_vnmi_blocked = 0;
4704
ad312c7c 4705 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 4706 kvm_set_cr8(vcpu, 0);
4707
4708 if (!init_event) {
4709 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4710 MSR_IA32_APICBASE_ENABLE;
4711 if (kvm_vcpu_is_reset_bsp(vcpu))
4712 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4713 apic_base_msr.host_initiated = true;
4714 kvm_set_apic_base(vcpu, &apic_base_msr);
4715 }
e00c8cf2 4716
2fb92db1
AK		 4717 vmx_segment_cache_clear(vmx);
4718
5706be0d 4719 seg_setup(VCPU_SREG_CS);
66450a21 4720 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4721 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4722
4723 seg_setup(VCPU_SREG_DS);
4724 seg_setup(VCPU_SREG_ES);
4725 seg_setup(VCPU_SREG_FS);
4726 seg_setup(VCPU_SREG_GS);
4727 seg_setup(VCPU_SREG_SS);
4728
4729 vmcs_write16(GUEST_TR_SELECTOR, 0);
4730 vmcs_writel(GUEST_TR_BASE, 0);
4731 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4732 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4733
4734 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4735 vmcs_writel(GUEST_LDTR_BASE, 0);
4736 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4737 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4738
d28bc9dd
NA		 4739 if (!init_event) {
4740 vmcs_write32(GUEST_SYSENTER_CS, 0);
4741 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4742 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4743 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4744 }
e00c8cf2
AK		 4745
4746 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4747 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4748
e00c8cf2
AK		 4749 vmcs_writel(GUEST_GDTR_BASE, 0);
4750 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4751
4752 vmcs_writel(GUEST_IDTR_BASE, 0);
4753 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4754
443381a8 4755 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4756 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4757 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4758
e00c8cf2
AK		 4759 setup_msrs(vmx);
4760
6aa8b732
AK		 4761 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4762
d28bc9dd 4763 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 4764 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 4765 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 4766 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 4767 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 4768 vmcs_write32(TPR_THRESHOLD, 0);
4769 }
4770
a73896cb 4771 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4772
35754c98 4773 if (vmx_cpu_uses_apicv(vcpu))
01e439be
YZ		 4774 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4775
2384d2b3
SY		 4776 if (vmx->vpid != 0)
4777 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4778
d28bc9dd
NA		 4779 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4780 vmx_set_cr0(vcpu, cr0); /* enter rmode */
4781 vmx->vcpu.arch.cr0 = cr0;
4782 vmx_set_cr4(vcpu, 0);
4783 if (!init_event)
4784 vmx_set_efer(vcpu, 0);
4785 vmx_fpu_activate(vcpu);
4786 update_exception_bitmap(vcpu);
6aa8b732 4787
b9d762fa 4788 vpid_sync_context(vmx);
6aa8b732
AK		 4789}
4790
b6f1250e
NHE		 4791/*
4792 * In nested virtualization, check if L1 asked to exit on external interrupts.
4793 * For most existing hypervisors, this will always return true.
4794 */
4795static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4796{
4797 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4798 PIN_BASED_EXT_INTR_MASK;
4799}
4800
77b0f5d6
BD		 4801/*
4802 * In nested virtualization, check if L1 has set
4803 * VM_EXIT_ACK_INTR_ON_EXIT
4804 */
4805static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4806{
4807 return get_vmcs12(vcpu)->vm_exit_controls &
4808 VM_EXIT_ACK_INTR_ON_EXIT;
4809}
4810
ea8ceb83
JK		 4811static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4812{
4813 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4814 PIN_BASED_NMI_EXITING;
4815}
4816
c9a7953f 4817static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4818{
4819 u32 cpu_based_vm_exec_control;
730dca42 4820
3b86cd99
JK		 4821 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4822 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4823 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4824}
4825
c9a7953f 4826static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4827{
4828 u32 cpu_based_vm_exec_control;
4829
c9a7953f
JK		 4830 if (!cpu_has_virtual_nmis() ||
4831 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4832 enable_irq_window(vcpu);
4833 return;
4834 }
3b86cd99
JK		 4835
4836 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4837 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4838 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4839}
4840
66fd3f7f 4841static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4842{
9c8cba37 4843 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4844 uint32_t intr;
4845 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4846
229456fc 4847 trace_kvm_inj_virq(irq);
2714d1d3 4848
fa89a817 4849 ++vcpu->stat.irq_injections;
7ffd92c5 4850 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4851 int inc_eip = 0;
4852 if (vcpu->arch.interrupt.soft)
4853 inc_eip = vcpu->arch.event_exit_inst_len;
4854 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4855 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4856 return;
4857 }
66fd3f7f
GN		 4858 intr = irq | INTR_INFO_VALID_MASK;
4859 if (vcpu->arch.interrupt.soft) {
4860 intr |= INTR_TYPE_SOFT_INTR;
4861 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4862 vmx->vcpu.arch.event_exit_inst_len);
4863 } else
4864 intr |= INTR_TYPE_EXT_INTR;
4865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4866}
4867
f08864b4
SY		 4868static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4869{
66a5a347
JK		 4870 struct vcpu_vmx *vmx = to_vmx(vcpu);
4871
0b6ac343
NHE		 4872 if (is_guest_mode(vcpu))
4873 return;
4874
3b86cd99
JK		 4875 if (!cpu_has_virtual_nmis()) {
4876 /*
4877 * Tracking the NMI-blocked state in software is built upon
4878 * finding the next open IRQ window. This, in turn, depends on
4879 * well-behaving guests: They have to keep IRQs disabled at
4880 * least as long as the NMI handler runs. Otherwise we may
4881 * cause NMI nesting, maybe breaking the guest. But as this is
4882 * highly unlikely, we can live with the residual risk.
4883 */
4884 vmx->soft_vnmi_blocked = 1;
4885 vmx->vnmi_blocked_time = 0;
4886 }
4887
487b391d 4888 ++vcpu->stat.nmi_injections;
9d58b931 4889 vmx->nmi_known_unmasked = false;
7ffd92c5 4890 if (vmx->rmode.vm86_active) {
71f9833b 4891 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4892 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4893 return;
4894 }
f08864b4
SY		 4895 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4896 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4897}
4898
3cfc3092
JK		 4899static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4900{
4901 if (!cpu_has_virtual_nmis())
4902 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4903 if (to_vmx(vcpu)->nmi_known_unmasked)
4904 return false;
c332c83a 4905 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4906}
4907
4908static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4909{
4910 struct vcpu_vmx *vmx = to_vmx(vcpu);
4911
4912 if (!cpu_has_virtual_nmis()) {
4913 if (vmx->soft_vnmi_blocked != masked) {
4914 vmx->soft_vnmi_blocked = masked;
4915 vmx->vnmi_blocked_time = 0;
4916 }
4917 } else {
9d58b931 4918 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4919 if (masked)
4920 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4921 GUEST_INTR_STATE_NMI);
4922 else
4923 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4924 GUEST_INTR_STATE_NMI);
4925 }
4926}
4927
2505dc9f
JK		 4928static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4929{
b6b8a145
JK		 4930 if (to_vmx(vcpu)->nested.nested_run_pending)
4931 return 0;
ea8ceb83 4932
2505dc9f
JK		 4933 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4934 return 0;
4935
4936 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4937 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4938 | GUEST_INTR_STATE_NMI));
4939}
4940
78646121
GN		 4941static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4942{
b6b8a145
JK		 4943 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4944 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4945 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4946 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4947}
4948
cbc94022
IE		 4949static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4950{
4951 int ret;
4952 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4953 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4954 .guest_phys_addr = addr,
4955 .memory_size = PAGE_SIZE * 3,
4956 .flags = 0,
4957 };
4958
9da0e4d5 4959 ret = x86_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4960 if (ret)
4961 return ret;
bfc6d222 4962 kvm->arch.tss_addr = addr;
1f755a82 4963 return init_rmode_tss(kvm);
cbc94022
IE		 4964}
4965
0ca1b4f4 4966static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4967{
77ab6db0 4968 switch (vec) {
77ab6db0 4969 case BP_VECTOR:
c573cd22
JK		 4970 /*
4971 * Update instruction length as we may reinject the exception
4972 * from user space while in guest debugging mode.
4973 */
4974 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4975 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4976 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4977 return false;
4978 /* fall through */
4979 case DB_VECTOR:
4980 if (vcpu->guest_debug &
4981 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4982 return false;
d0bfb940
JK		 4983 /* fall through */
4984 case DE_VECTOR:
77ab6db0
JK		 4985 case OF_VECTOR:
4986 case BR_VECTOR:
4987 case UD_VECTOR:
4988 case DF_VECTOR:
4989 case SS_VECTOR:
4990 case GP_VECTOR:
4991 case MF_VECTOR:
0ca1b4f4
GN		 4992 return true;
4993 break;
77ab6db0 4994 }
0ca1b4f4
GN		 4995 return false;
4996}
4997
4998static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4999 int vec, u32 err_code)
5000{
5001 /*
5002 * Instruction with address size override prefix opcode 0x67
5003 * Cause the #SS fault with 0 error code in VM86 mode.
5004 */
5005 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5006 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5007 if (vcpu->arch.halt_request) {
5008 vcpu->arch.halt_request = 0;
5cb56059 5009 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 5010 }
5011 return 1;
5012 }
5013 return 0;
5014 }
5015
5016 /*
5017 * Forward all other exceptions that are valid in real mode.
5018 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5019 * the required debugging infrastructure rework.
5020 */
5021 kvm_queue_exception(vcpu, vec);
5022 return 1;
6aa8b732
AK		 5023}
5024
a0861c02
AK		 5025/*
5026 * Trigger machine check on the host. We assume all the MSRs are already set up
5027 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5028 * We pass a fake environment to the machine check handler because we want
5029 * the guest to be always treated like user space, no matter what context
5030 * it used internally.
5031 */
5032static void kvm_machine_check(void)
5033{
5034#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5035 struct pt_regs regs = {
5036 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5037 .flags = X86_EFLAGS_IF,
5038 };
5039
5040 do_machine_check(&regs, 0);
5041#endif
5042}
5043
851ba692 5044static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 5045{
5046 /* already handled by vcpu_run */
5047 return 1;
5048}
5049
851ba692 5050static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 5051{
1155f76a 5052 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 5053 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 5054 u32 intr_info, ex_no, error_code;
42dbaa5a 5055 unsigned long cr2, rip, dr6;
6aa8b732
AK		 5056 u32 vect_info;
5057 enum emulation_result er;
5058
1155f76a 5059 vect_info = vmx->idt_vectoring_info;
88786475 5060 intr_info = vmx->exit_intr_info;
6aa8b732 5061
a0861c02 5062 if (is_machine_check(intr_info))
851ba692 5063 return handle_machine_check(vcpu);
a0861c02 5064
e4a41889 5065 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 5066 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 5067
5068 if (is_no_device(intr_info)) {
5fd86fcf 5069 vmx_fpu_activate(vcpu);
2ab455cc
AL		 5070 return 1;
5071 }
5072
7aa81cc0 5073 if (is_invalid_opcode(intr_info)) {
ae1f5767
JK		 5074 if (is_guest_mode(vcpu)) {
5075 kvm_queue_exception(vcpu, UD_VECTOR);
5076 return 1;
5077 }
51d8b661 5078 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 5079 if (er != EMULATE_DONE)
7ee5d940 5080 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 5081 return 1;
5082 }
5083
6aa8b732 5084 error_code = 0;
2e11384c 5085 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 5086 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 5087
5088 /*
5089 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5090 * MMIO, it is better to report an internal error.
5091 * See the comments in vmx_handle_exit.
5092 */
5093 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5094 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5095 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5096 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 5097 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 5098 vcpu->run->internal.data[0] = vect_info;
5099 vcpu->run->internal.data[1] = intr_info;
80f0e95d 5100 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 5101 return 0;
5102 }
5103
6aa8b732 5104 if (is_page_fault(intr_info)) {
1439442c 5105 /* EPT won't cause page fault directly */
cf3ace79 5106 BUG_ON(enable_ept);
6aa8b732 5107 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 5108 trace_kvm_page_fault(cr2, error_code);
5109
3298b75c 5110 if (kvm_event_needs_reinjection(vcpu))
577bdc49 5111 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 5112 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 5113 }
5114
d0bfb940 5115 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 5116
5117 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5118 return handle_rmode_exception(vcpu, ex_no, error_code);
5119
42dbaa5a
JK		 5120 switch (ex_no) {
5121 case DB_VECTOR:
5122 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5123 if (!(vcpu->guest_debug &
5124 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 5125 vcpu->arch.dr6 &= ~15;
6f43ed01 5126 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 5127 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5128 skip_emulated_instruction(vcpu);
5129
42dbaa5a
JK		 5130 kvm_queue_exception(vcpu, DB_VECTOR);
5131 return 1;
5132 }
5133 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5134 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5135 /* fall through */
5136 case BP_VECTOR:
c573cd22
JK		 5137 /*
5138 * Update instruction length as we may reinject #BP from
5139 * user space while in guest debugging mode. Reading it for
5140 * #DB as well causes no harm, it is not used in that case.
5141 */
5142 vmx->vcpu.arch.event_exit_inst_len =
5143 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 5144 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 5145 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 5146 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5147 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 5148 break;
5149 default:
d0bfb940
JK		 5150 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5151 kvm_run->ex.exception = ex_no;
5152 kvm_run->ex.error_code = error_code;
42dbaa5a 5153 break;
6aa8b732 5154 }
6aa8b732
AK		 5155 return 0;
5156}
5157
851ba692 5158static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5159{
1165f5fe 5160 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5161 return 1;
5162}
5163
851ba692 5164static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5165{
851ba692 5166 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5167 return 0;
5168}
6aa8b732 5169
851ba692 5170static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5171{
bfdaab09 5172 unsigned long exit_qualification;
34c33d16 5173 int size, in, string;
039576c0 5174 unsigned port;
6aa8b732 5175
bfdaab09 5176 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5177 string = (exit_qualification & 16) != 0;
cf8f70bf 5178 in = (exit_qualification & 8) != 0;
e70669ab 5179
cf8f70bf 5180 ++vcpu->stat.io_exits;
e70669ab 5181
cf8f70bf 5182 if (string || in)
51d8b661 5183 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5184
cf8f70bf
GN		 5185 port = exit_qualification >> 16;
5186 size = (exit_qualification & 7) + 1;
e93f36bc 5187 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5188
5189 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5190}
5191
102d8325
IM		 5192static void
5193vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5194{
5195 /*
5196 * Patch in the VMCALL instruction:
5197 */
5198 hypercall[0] = 0x0f;
5199 hypercall[1] = 0x01;
5200 hypercall[2] = 0xc1;
102d8325
IM		 5201}
5202
b9c237bb 5203static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
92fbc7b1
JK		 5204{
5205 unsigned long always_on = VMXON_CR0_ALWAYSON;
b9c237bb 5206 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
92fbc7b1 5207
b9c237bb 5208 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
92fbc7b1
JK		 5209 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5210 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5211 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5212 return (val & always_on) == always_on;
5213}
5214
0fa06071 5215/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5216static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5217{
eeadf9e7 5218 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5219 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5220 unsigned long orig_val = val;
5221
eeadf9e7
NHE		 5222 /*
5223 * We get here when L2 changed cr0 in a way that did not change
5224 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5225 * but did change L0 shadowed bits. So we first calculate the
5226 * effective cr0 value that L1 would like to write into the
5227 * hardware. It consists of the L2-owned bits from the new
5228 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5229 */
1a0d74e6
JK		 5230 val = (val & ~vmcs12->cr0_guest_host_mask) |
5231 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5232
b9c237bb 5233 if (!nested_cr0_valid(vcpu, val))
eeadf9e7 5234 return 1;
1a0d74e6
JK		 5235
5236 if (kvm_set_cr0(vcpu, val))
5237 return 1;
5238 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5239 return 0;
1a0d74e6
JK		 5240 } else {
5241 if (to_vmx(vcpu)->nested.vmxon &&
5242 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5243 return 1;
eeadf9e7 5244 return kvm_set_cr0(vcpu, val);
1a0d74e6 5245 }
eeadf9e7
NHE		 5246}
5247
5248static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5249{
5250 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5251 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5252 unsigned long orig_val = val;
5253
5254 /* analogously to handle_set_cr0 */
5255 val = (val & ~vmcs12->cr4_guest_host_mask) |
5256 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5257 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5258 return 1;
1a0d74e6 5259 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5260 return 0;
5261 } else
5262 return kvm_set_cr4(vcpu, val);
5263}
5264
5265/* called to set cr0 as approriate for clts instruction exit. */
5266static void handle_clts(struct kvm_vcpu *vcpu)
5267{
5268 if (is_guest_mode(vcpu)) {
5269 /*
5270 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5271 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5272 * just pretend it's off (also in arch.cr0 for fpu_activate).
5273 */
5274 vmcs_writel(CR0_READ_SHADOW,
5275 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5276 vcpu->arch.cr0 &= ~X86_CR0_TS;
5277 } else
5278 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5279}
5280
851ba692 5281static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5282{
229456fc 5283 unsigned long exit_qualification, val;
6aa8b732
AK		 5284 int cr;
5285 int reg;
49a9b07e 5286 int err;
6aa8b732 5287
bfdaab09 5288 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5289 cr = exit_qualification & 15;
5290 reg = (exit_qualification >> 8) & 15;
5291 switch ((exit_qualification >> 4) & 3) {
5292 case 0: /* mov to cr */
1e32c079 5293 val = kvm_register_readl(vcpu, reg);
229456fc 5294 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5295 switch (cr) {
5296 case 0:
eeadf9e7 5297 err = handle_set_cr0(vcpu, val);
db8fcefa 5298 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5299 return 1;
5300 case 3:
2390218b 5301 err = kvm_set_cr3(vcpu, val);
db8fcefa 5302 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5303 return 1;
5304 case 4:
eeadf9e7 5305 err = handle_set_cr4(vcpu, val);
db8fcefa 5306 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5307 return 1;
0a5fff19
GN		 5308 case 8: {
5309 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5310 u8 cr8 = (u8)val;
eea1cff9 5311 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5312 kvm_complete_insn_gp(vcpu, err);
35754c98 5313 if (lapic_in_kernel(vcpu))
0a5fff19
GN		 5314 return 1;
5315 if (cr8_prev <= cr8)
5316 return 1;
851ba692 5317 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5318 return 0;
5319 }
4b8073e4 5320 }
6aa8b732 5321 break;
25c4c276 5322 case 2: /* clts */
eeadf9e7 5323 handle_clts(vcpu);
4d4ec087 5324 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5325 skip_emulated_instruction(vcpu);
6b52d186 5326 vmx_fpu_activate(vcpu);
25c4c276 5327 return 1;
6aa8b732
AK		 5328 case 1: /*mov from cr*/
5329 switch (cr) {
5330 case 3:
9f8fe504
AK		 5331 val = kvm_read_cr3(vcpu);
5332 kvm_register_write(vcpu, reg, val);
5333 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5334 skip_emulated_instruction(vcpu);
5335 return 1;
5336 case 8:
229456fc
MT		 5337 val = kvm_get_cr8(vcpu);
5338 kvm_register_write(vcpu, reg, val);
5339 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5340 skip_emulated_instruction(vcpu);
5341 return 1;
5342 }
5343 break;
5344 case 3: /* lmsw */
a1f83a74 5345 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5346 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5347 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5348
5349 skip_emulated_instruction(vcpu);
5350 return 1;
5351 default:
5352 break;
5353 }
851ba692 5354 vcpu->run->exit_reason = 0;
a737f256 5355 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5356 (int)(exit_qualification >> 4) & 3, cr);
5357 return 0;
5358}
5359
851ba692 5360static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5361{
bfdaab09 5362 unsigned long exit_qualification;
16f8a6f9
NA		 5363 int dr, dr7, reg;
5364
5365 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5366 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5367
5368 /* First, if DR does not exist, trigger UD */
5369 if (!kvm_require_dr(vcpu, dr))
5370 return 1;
6aa8b732 5371
f2483415 5372 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5373 if (!kvm_require_cpl(vcpu, 0))
5374 return 1;
16f8a6f9
NA		 5375 dr7 = vmcs_readl(GUEST_DR7);
5376 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5377 /*
5378 * As the vm-exit takes precedence over the debug trap, we
5379 * need to emulate the latter, either for the host or the
5380 * guest debugging itself.
5381 */
5382 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5383 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5384 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5385 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5386 vcpu->run->debug.arch.exception = DB_VECTOR;
5387 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5388 return 0;
5389 } else {
7305eb5d 5390 vcpu->arch.dr6 &= ~15;
6f43ed01 5391 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5392 kvm_queue_exception(vcpu, DB_VECTOR);
5393 return 1;
5394 }
5395 }
5396
81908bf4
PB		 5397 if (vcpu->guest_debug == 0) {
5398 u32 cpu_based_vm_exec_control;
5399
5400 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5401 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5402 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5403
5404 /*
5405 * No more DR vmexits; force a reload of the debug registers
5406 * and reenter on this instruction. The next vmexit will
5407 * retrieve the full state of the debug registers.
5408 */
5409 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5410 return 1;
5411 }
5412
42dbaa5a
JK		 5413 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5414 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5415 unsigned long val;
4c4d563b
JK		 5416
5417 if (kvm_get_dr(vcpu, dr, &val))
5418 return 1;
5419 kvm_register_write(vcpu, reg, val);
020df079 5420 } else
5777392e 5421 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5422 return 1;
5423
6aa8b732
AK		 5424 skip_emulated_instruction(vcpu);
5425 return 1;
5426}
5427
73aaf249
JK		 5428static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5429{
5430 return vcpu->arch.dr6;
5431}
5432
5433static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5434{
5435}
5436
81908bf4
PB		 5437static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5438{
5439 u32 cpu_based_vm_exec_control;
5440
5441 get_debugreg(vcpu->arch.db[0], 0);
5442 get_debugreg(vcpu->arch.db[1], 1);
5443 get_debugreg(vcpu->arch.db[2], 2);
5444 get_debugreg(vcpu->arch.db[3], 3);
5445 get_debugreg(vcpu->arch.dr6, 6);
5446 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5447
5448 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5449
5450 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5451 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5453}
5454
020df079
GN		 5455static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5456{
5457 vmcs_writel(GUEST_DR7, val);
5458}
5459
851ba692 5460static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5461{
06465c5a
AK		 5462 kvm_emulate_cpuid(vcpu);
5463 return 1;
6aa8b732
AK		 5464}
5465
851ba692 5466static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5467{
ad312c7c 5468 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 5469 struct msr_data msr_info;
6aa8b732 5470
609e36d3
PB		 5471 msr_info.index = ecx;
5472 msr_info.host_initiated = false;
5473 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 5474 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5475 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5476 return 1;
5477 }
5478
609e36d3 5479 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 5480
6aa8b732 5481 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 5482 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5483 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6aa8b732
AK		 5484 skip_emulated_instruction(vcpu);
5485 return 1;
5486}
5487
851ba692 5488static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5489{
8fe8ab46 5490 struct msr_data msr;
ad312c7c
ZX		 5491 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5492 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5493 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5494
8fe8ab46
WA		 5495 msr.data = data;
5496 msr.index = ecx;
5497 msr.host_initiated = false;
854e8bb1 5498 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5499 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5500 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5501 return 1;
5502 }
5503
59200273 5504 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5505 skip_emulated_instruction(vcpu);
5506 return 1;
5507}
5508
851ba692 5509static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5510{
3842d135 5511 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5512 return 1;
5513}
5514
851ba692 5515static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5516{
85f455f7
ED		 5517 u32 cpu_based_vm_exec_control;
5518
5519 /* clear pending irq */
5520 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5521 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5522 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5523
3842d135
AK		 5524 kvm_make_request(KVM_REQ_EVENT, vcpu);
5525
a26bf12a 5526 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 5527 return 1;
5528}
5529
851ba692 5530static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 5531{
d3bef15f 5532 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5533}
5534
851ba692 5535static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5536{
7aa81cc0
AL		 5537 kvm_emulate_hypercall(vcpu);
5538 return 1;
c21415e8
IM		 5539}
5540
ec25d5e6
GN		 5541static int handle_invd(struct kvm_vcpu *vcpu)
5542{
51d8b661 5543 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5544}
5545
851ba692 5546static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5547{
f9c617f6 5548 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5549
5550 kvm_mmu_invlpg(vcpu, exit_qualification);
5551 skip_emulated_instruction(vcpu);
5552 return 1;
5553}
5554
fee84b07
AK		 5555static int handle_rdpmc(struct kvm_vcpu *vcpu)
5556{
5557 int err;
5558
5559 err = kvm_rdpmc(vcpu);
5560 kvm_complete_insn_gp(vcpu, err);
5561
5562 return 1;
5563}
5564
851ba692 5565static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 5566{
f5f48ee1 5567 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5568 return 1;
5569}
5570
2acf923e
DC		 5571static int handle_xsetbv(struct kvm_vcpu *vcpu)
5572{
5573 u64 new_bv = kvm_read_edx_eax(vcpu);
5574 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5575
5576 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5577 skip_emulated_instruction(vcpu);
5578 return 1;
5579}
5580
f53cd63c
WL		 5581static int handle_xsaves(struct kvm_vcpu *vcpu)
5582{
5583 skip_emulated_instruction(vcpu);
5584 WARN(1, "this should never happen\n");
5585 return 1;
5586}
5587
5588static int handle_xrstors(struct kvm_vcpu *vcpu)
5589{
5590 skip_emulated_instruction(vcpu);
5591 WARN(1, "this should never happen\n");
5592 return 1;
5593}
5594
851ba692 5595static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5596{
58fbbf26
KT		 5597 if (likely(fasteoi)) {
5598 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5599 int access_type, offset;
5600
5601 access_type = exit_qualification & APIC_ACCESS_TYPE;
5602 offset = exit_qualification & APIC_ACCESS_OFFSET;
5603 /*
5604 * Sane guest uses MOV to write EOI, with written value
5605 * not cared. So make a short-circuit here by avoiding
5606 * heavy instruction emulation.
5607 */
5608 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5609 (offset == APIC_EOI)) {
5610 kvm_lapic_set_eoi(vcpu);
5611 skip_emulated_instruction(vcpu);
5612 return 1;
5613 }
5614 }
51d8b661 5615 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5616}
5617
c7c9c56c
YZ		 5618static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5619{
5620 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5621 int vector = exit_qualification & 0xff;
5622
5623 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5624 kvm_apic_set_eoi_accelerated(vcpu, vector);
5625 return 1;
5626}
5627
83d4c286
YZ		 5628static int handle_apic_write(struct kvm_vcpu *vcpu)
5629{
5630 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5631 u32 offset = exit_qualification & 0xfff;
5632
5633 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5634 kvm_apic_write_nodecode(vcpu, offset);
5635 return 1;
5636}
5637
851ba692 5638static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5639{
60637aac 5640 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5641 unsigned long exit_qualification;
e269fb21
JK		 5642 bool has_error_code = false;
5643 u32 error_code = 0;
37817f29 5644 u16 tss_selector;
7f3d35fd 5645 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5646
5647 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5648 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5649 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5650
5651 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5652
5653 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5654 if (reason == TASK_SWITCH_GATE && idt_v) {
5655 switch (type) {
5656 case INTR_TYPE_NMI_INTR:
5657 vcpu->arch.nmi_injected = false;
654f06fc 5658 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5659 break;
5660 case INTR_TYPE_EXT_INTR:
66fd3f7f 5661 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5662 kvm_clear_interrupt_queue(vcpu);
5663 break;
5664 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5665 if (vmx->idt_vectoring_info &
5666 VECTORING_INFO_DELIVER_CODE_MASK) {
5667 has_error_code = true;
5668 error_code =
5669 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5670 }
5671 /* fall through */
64a7ec06
GN		 5672 case INTR_TYPE_SOFT_EXCEPTION:
5673 kvm_clear_exception_queue(vcpu);
5674 break;
5675 default:
5676 break;
5677 }
60637aac 5678 }
37817f29
IE		 5679 tss_selector = exit_qualification;
5680
64a7ec06
GN		 5681 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5682 type != INTR_TYPE_EXT_INTR &&
5683 type != INTR_TYPE_NMI_INTR))
5684 skip_emulated_instruction(vcpu);
5685
7f3d35fd
KW		 5686 if (kvm_task_switch(vcpu, tss_selector,
5687 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5688 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5689 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5690 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5691 vcpu->run->internal.ndata = 0;
42dbaa5a 5692 return 0;
acb54517 5693 }
42dbaa5a 5694
42dbaa5a
JK		 5695 /*
5696 * TODO: What about debug traps on tss switch?
5697 * Are we supposed to inject them and update dr6?
5698 */
5699
5700 return 1;
37817f29
IE		 5701}
5702
851ba692 5703static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5704{
f9c617f6 5705 unsigned long exit_qualification;
1439442c 5706 gpa_t gpa;
4f5982a5 5707 u32 error_code;
1439442c 5708 int gla_validity;
1439442c 5709
f9c617f6 5710 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5711
1439442c
SY		 5712 gla_validity = (exit_qualification >> 7) & 0x3;
5713 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5714 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5715 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5716 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5717 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5718 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5719 (long unsigned int)exit_qualification);
851ba692
AK		 5720 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5721 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5722 return 0;
1439442c
SY		 5723 }
5724
0be9c7a8
GN		 5725 /*
5726 * EPT violation happened while executing iret from NMI,
5727 * "blocked by NMI" bit has to be set before next VM entry.
5728 * There are errata that may cause this bit to not be set:
5729 * AAK134, BY25.
5730 */
bcd1c294
GN		 5731 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5732 cpu_has_virtual_nmis() &&
5733 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5734 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5735
1439442c 5736 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5737 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5738
5739 /* It is a write fault? */
81ed33e4 5740 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5741 /* It is a fetch fault? */
81ed33e4 5742 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5743 /* ept page table is present? */
81ed33e4 5744 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5745
25d92081
YZ		 5746 vcpu->arch.exit_qualification = exit_qualification;
5747
4f5982a5 5748 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5749}
5750
851ba692 5751static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 5752{
f735d4af 5753 int ret;
68f89400
MT		 5754 gpa_t gpa;
5755
5756 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
e32edf4f 5757 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
68c3b4d1 5758 skip_emulated_instruction(vcpu);
931c33b1 5759 trace_kvm_fast_mmio(gpa);
68c3b4d1
MT		 5760 return 1;
5761 }
68f89400 5762
ce88decf 5763 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5764 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5765 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5766 EMULATE_DONE;
f8f55942
XG		 5767
5768 if (unlikely(ret == RET_MMIO_PF_INVALID))
5769 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5770
b37fbea6 5771 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5772 return 1;
5773
5774 /* It is the real ept misconfig */
f735d4af 5775 WARN_ON(1);
68f89400 5776
851ba692
AK		 5777 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5778 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5779
5780 return 0;
5781}
5782
851ba692 5783static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5784{
5785 u32 cpu_based_vm_exec_control;
5786
5787 /* clear pending NMI */
5788 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5789 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5790 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5791 ++vcpu->stat.nmi_window_exits;
3842d135 5792 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5793
5794 return 1;
5795}
5796
80ced186 5797static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5798{
8b3079a5
AK		 5799 struct vcpu_vmx *vmx = to_vmx(vcpu);
5800 enum emulation_result err = EMULATE_DONE;
80ced186 5801 int ret = 1;
49e9d557
AK		 5802 u32 cpu_exec_ctrl;
5803 bool intr_window_requested;
b8405c18 5804 unsigned count = 130;
49e9d557
AK		 5805
5806 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5807 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5808
98eb2f8b 5809 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5810 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5811 return handle_interrupt_window(&vmx->vcpu);
5812
de87dcdd
AK		 5813 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5814 return 1;
5815
991eebf9 5816 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5817
ac0a48c3 5818 if (err == EMULATE_USER_EXIT) {
94452b9e 5819 ++vcpu->stat.mmio_exits;
80ced186
MG		 5820 ret = 0;
5821 goto out;
5822 }
1d5a4d9b 5823
de5f70e0
AK		 5824 if (err != EMULATE_DONE) {
5825 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5826 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5827 vcpu->run->internal.ndata = 0;
6d77dbfc 5828 return 0;
de5f70e0 5829 }
ea953ef0 5830
8d76c49e
GN		 5831 if (vcpu->arch.halt_request) {
5832 vcpu->arch.halt_request = 0;
5cb56059 5833 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 5834 goto out;
5835 }
5836
ea953ef0 5837 if (signal_pending(current))
80ced186 5838 goto out;
ea953ef0
MG		 5839 if (need_resched())
5840 schedule();
5841 }
5842
80ced186
MG		 5843out:
5844 return ret;
ea953ef0
MG		 5845}
5846
b4a2d31d
RK		 5847static int __grow_ple_window(int val)
5848{
5849 if (ple_window_grow < 1)
5850 return ple_window;
5851
5852 val = min(val, ple_window_actual_max);
5853
5854 if (ple_window_grow < ple_window)
5855 val *= ple_window_grow;
5856 else
5857 val += ple_window_grow;
5858
5859 return val;
5860}
5861
5862static int __shrink_ple_window(int val, int modifier, int minimum)
5863{
5864 if (modifier < 1)
5865 return ple_window;
5866
5867 if (modifier < ple_window)
5868 val /= modifier;
5869 else
5870 val -= modifier;
5871
5872 return max(val, minimum);
5873}
5874
5875static void grow_ple_window(struct kvm_vcpu *vcpu)
5876{
5877 struct vcpu_vmx *vmx = to_vmx(vcpu);
5878 int old = vmx->ple_window;
5879
5880 vmx->ple_window = __grow_ple_window(old);
5881
5882 if (vmx->ple_window != old)
5883 vmx->ple_window_dirty = true;
7b46268d
RK		 5884
5885 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5886}
5887
5888static void shrink_ple_window(struct kvm_vcpu *vcpu)
5889{
5890 struct vcpu_vmx *vmx = to_vmx(vcpu);
5891 int old = vmx->ple_window;
5892
5893 vmx->ple_window = __shrink_ple_window(old,
5894 ple_window_shrink, ple_window);
5895
5896 if (vmx->ple_window != old)
5897 vmx->ple_window_dirty = true;
7b46268d
RK		 5898
5899 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5900}
5901
5902/*
5903 * ple_window_actual_max is computed to be one grow_ple_window() below
5904 * ple_window_max. (See __grow_ple_window for the reason.)
5905 * This prevents overflows, because ple_window_max is int.
5906 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5907 * this process.
5908 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5909 */
5910static void update_ple_window_actual_max(void)
5911{
5912 ple_window_actual_max =
5913 __shrink_ple_window(max(ple_window_max, ple_window),
5914 ple_window_grow, INT_MIN);
5915}
5916
f2c7648d
TC		 5917static __init int hardware_setup(void)
5918{
34a1cd60
TC		 5919 int r = -ENOMEM, i, msr;
5920
5921 rdmsrl_safe(MSR_EFER, &host_efer);
5922
5923 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5924 kvm_define_shared_msr(i, vmx_msr_index[i]);
5925
5926 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5927 if (!vmx_io_bitmap_a)
5928 return r;
5929
5930 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5931 if (!vmx_io_bitmap_b)
5932 goto out;
5933
5934 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5935 if (!vmx_msr_bitmap_legacy)
5936 goto out1;
5937
5938 vmx_msr_bitmap_legacy_x2apic =
5939 (unsigned long *)__get_free_page(GFP_KERNEL);
5940 if (!vmx_msr_bitmap_legacy_x2apic)
5941 goto out2;
5942
5943 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5944 if (!vmx_msr_bitmap_longmode)
5945 goto out3;
5946
5947 vmx_msr_bitmap_longmode_x2apic =
5948 (unsigned long *)__get_free_page(GFP_KERNEL);
5949 if (!vmx_msr_bitmap_longmode_x2apic)
5950 goto out4;
3af18d9c
WV		 5951
5952 if (nested) {
5953 vmx_msr_bitmap_nested =
5954 (unsigned long *)__get_free_page(GFP_KERNEL);
5955 if (!vmx_msr_bitmap_nested)
5956 goto out5;
5957 }
5958
34a1cd60
TC		 5959 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5960 if (!vmx_vmread_bitmap)
3af18d9c 5961 goto out6;
34a1cd60
TC		 5962
5963 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5964 if (!vmx_vmwrite_bitmap)
3af18d9c 5965 goto out7;
34a1cd60
TC		 5966
5967 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5968 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5969
5970 /*
5971 * Allow direct access to the PC debug port (it is often used for I/O
5972 * delays, but the vmexits simply slow things down).
5973 */
5974 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5975 clear_bit(0x80, vmx_io_bitmap_a);
5976
5977 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5978
5979 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5980 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 5981 if (nested)
5982 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 5983
34a1cd60
TC		 5984 if (setup_vmcs_config(&vmcs_config) < 0) {
5985 r = -EIO;
3af18d9c 5986 goto out8;
baa03522 5987 }
f2c7648d
TC		 5988
5989 if (boot_cpu_has(X86_FEATURE_NX))
5990 kvm_enable_efer_bits(EFER_NX);
5991
5992 if (!cpu_has_vmx_vpid())
5993 enable_vpid = 0;
5994 if (!cpu_has_vmx_shadow_vmcs())
5995 enable_shadow_vmcs = 0;
5996 if (enable_shadow_vmcs)
5997 init_vmcs_shadow_fields();
5998
5999 if (!cpu_has_vmx_ept() ||
6000 !cpu_has_vmx_ept_4levels()) {
6001 enable_ept = 0;
6002 enable_unrestricted_guest = 0;
6003 enable_ept_ad_bits = 0;
6004 }
6005
6006 if (!cpu_has_vmx_ept_ad_bits())
6007 enable_ept_ad_bits = 0;
6008
6009 if (!cpu_has_vmx_unrestricted_guest())
6010 enable_unrestricted_guest = 0;
6011
ad15a296 6012 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 6013 flexpriority_enabled = 0;
6014
ad15a296
PB		 6015 /*
6016 * set_apic_access_page_addr() is used to reload apic access
6017 * page upon invalidation. No need to do anything if not
6018 * using the APIC_ACCESS_ADDR VMCS field.
6019 */
6020 if (!flexpriority_enabled)
f2c7648d 6021 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 6022
6023 if (!cpu_has_vmx_tpr_shadow())
6024 kvm_x86_ops->update_cr8_intercept = NULL;
6025
6026 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6027 kvm_disable_largepages();
6028
6029 if (!cpu_has_vmx_ple())
6030 ple_gap = 0;
6031
6032 if (!cpu_has_vmx_apicv())
6033 enable_apicv = 0;
6034
6035 if (enable_apicv)
6036 kvm_x86_ops->update_cr8_intercept = NULL;
6037 else {
6038 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 6039 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 6040 kvm_x86_ops->deliver_posted_interrupt = NULL;
6041 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6042 }
6043
baa03522
TC		 6044 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6045 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6046 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6047 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6048 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6049 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6050 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6051
6052 memcpy(vmx_msr_bitmap_legacy_x2apic,
6053 vmx_msr_bitmap_legacy, PAGE_SIZE);
6054 memcpy(vmx_msr_bitmap_longmode_x2apic,
6055 vmx_msr_bitmap_longmode, PAGE_SIZE);
6056
04bb92e4
WL		 6057 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6058
baa03522
TC		 6059 if (enable_apicv) {
6060 for (msr = 0x800; msr <= 0x8ff; msr++)
6061 vmx_disable_intercept_msr_read_x2apic(msr);
6062
6063 /* According SDM, in x2apic mode, the whole id reg is used.
6064 * But in KVM, it only use the highest eight bits. Need to
6065 * intercept it */
6066 vmx_enable_intercept_msr_read_x2apic(0x802);
6067 /* TMCCT */
6068 vmx_enable_intercept_msr_read_x2apic(0x839);
6069 /* TPR */
6070 vmx_disable_intercept_msr_write_x2apic(0x808);
6071 /* EOI */
6072 vmx_disable_intercept_msr_write_x2apic(0x80b);
6073 /* SELF-IPI */
6074 vmx_disable_intercept_msr_write_x2apic(0x83f);
6075 }
6076
6077 if (enable_ept) {
6078 kvm_mmu_set_mask_ptes(0ull,
6079 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6080 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6081 0ull, VMX_EPT_EXECUTABLE_MASK);
6082 ept_set_mmio_spte_mask();
6083 kvm_enable_tdp();
6084 } else
6085 kvm_disable_tdp();
6086
6087 update_ple_window_actual_max();
6088
843e4330
KH		 6089 /*
6090 * Only enable PML when hardware supports PML feature, and both EPT
6091 * and EPT A/D bit features are enabled -- PML depends on them to work.
6092 */
6093 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6094 enable_pml = 0;
6095
6096 if (!enable_pml) {
6097 kvm_x86_ops->slot_enable_log_dirty = NULL;
6098 kvm_x86_ops->slot_disable_log_dirty = NULL;
6099 kvm_x86_ops->flush_log_dirty = NULL;
6100 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6101 }
6102
f2c7648d 6103 return alloc_kvm_area();
34a1cd60 6104
3af18d9c 6105out8:
34a1cd60 6106 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6107out7:
34a1cd60 6108 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6109out6:
6110 if (nested)
6111 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6112out5:
6113 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6114out4:
6115 free_page((unsigned long)vmx_msr_bitmap_longmode);
6116out3:
6117 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6118out2:
6119 free_page((unsigned long)vmx_msr_bitmap_legacy);
6120out1:
6121 free_page((unsigned long)vmx_io_bitmap_b);
6122out:
6123 free_page((unsigned long)vmx_io_bitmap_a);
6124
6125 return r;
f2c7648d
TC		 6126}
6127
6128static __exit void hardware_unsetup(void)
6129{
34a1cd60
TC		 6130 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6131 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6132 free_page((unsigned long)vmx_msr_bitmap_legacy);
6133 free_page((unsigned long)vmx_msr_bitmap_longmode);
6134 free_page((unsigned long)vmx_io_bitmap_b);
6135 free_page((unsigned long)vmx_io_bitmap_a);
6136 free_page((unsigned long)vmx_vmwrite_bitmap);
6137 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6138 if (nested)
6139 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6140
f2c7648d
TC		 6141 free_kvm_area();
6142}
6143
4b8d54f9
ZE		 6144/*
6145 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6146 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6147 */
9fb41ba8 6148static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6149{
b4a2d31d
RK		 6150 if (ple_gap)
6151 grow_ple_window(vcpu);
6152
4b8d54f9
ZE		 6153 skip_emulated_instruction(vcpu);
6154 kvm_vcpu_on_spin(vcpu);
6155
6156 return 1;
6157}
6158
87c00572 6159static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6160{
87c00572 6161 skip_emulated_instruction(vcpu);
59708670
SY		 6162 return 1;
6163}
6164
87c00572
GS		 6165static int handle_mwait(struct kvm_vcpu *vcpu)
6166{
6167 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6168 return handle_nop(vcpu);
6169}
6170
5f3d45e7
MD		 6171static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6172{
6173 return 1;
6174}
6175
87c00572
GS		 6176static int handle_monitor(struct kvm_vcpu *vcpu)
6177{
6178 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6179 return handle_nop(vcpu);
6180}
6181
ff2f6fe9
NHE		 6182/*
6183 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6184 * We could reuse a single VMCS for all the L2 guests, but we also want the
6185 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6186 * allows keeping them loaded on the processor, and in the future will allow
6187 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6188 * every entry if they never change.
6189 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6190 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6191 *
6192 * The following functions allocate and free a vmcs02 in this pool.
6193 */
6194
6195/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6196static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6197{
6198 struct vmcs02_list *item;
6199 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6200 if (item->vmptr == vmx->nested.current_vmptr) {
6201 list_move(&item->list, &vmx->nested.vmcs02_pool);
6202 return &item->vmcs02;
6203 }
6204
6205 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6206 /* Recycle the least recently used VMCS. */
6207 item = list_entry(vmx->nested.vmcs02_pool.prev,
6208 struct vmcs02_list, list);
6209 item->vmptr = vmx->nested.current_vmptr;
6210 list_move(&item->list, &vmx->nested.vmcs02_pool);
6211 return &item->vmcs02;
6212 }
6213
6214 /* Create a new VMCS */
0fa24ce3 6215 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6216 if (!item)
6217 return NULL;
6218 item->vmcs02.vmcs = alloc_vmcs();
6219 if (!item->vmcs02.vmcs) {
6220 kfree(item);
6221 return NULL;
6222 }
6223 loaded_vmcs_init(&item->vmcs02);
6224 item->vmptr = vmx->nested.current_vmptr;
6225 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6226 vmx->nested.vmcs02_num++;
6227 return &item->vmcs02;
6228}
6229
6230/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6231static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6232{
6233 struct vmcs02_list *item;
6234 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6235 if (item->vmptr == vmptr) {
6236 free_loaded_vmcs(&item->vmcs02);
6237 list_del(&item->list);
6238 kfree(item);
6239 vmx->nested.vmcs02_num--;
6240 return;
6241 }
6242}
6243
6244/*
6245 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6246 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6247 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6248 */
6249static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6250{
6251 struct vmcs02_list *item, *n;
4fa7734c
PB		 6252
6253 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6254 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6255 /*
6256 * Something will leak if the above WARN triggers. Better than
6257 * a use-after-free.
6258 */
6259 if (vmx->loaded_vmcs == &item->vmcs02)
6260 continue;
6261
6262 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6263 list_del(&item->list);
6264 kfree(item);
4fa7734c 6265 vmx->nested.vmcs02_num--;
ff2f6fe9 6266 }
ff2f6fe9
NHE		 6267}
6268
0658fbaa
ACL		 6269/*
6270 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6271 * set the success or error code of an emulated VMX instruction, as specified
6272 * by Vol 2B, VMX Instruction Reference, "Conventions".
6273 */
6274static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6275{
6276 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6277 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6278 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6279}
6280
6281static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6282{
6283 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6284 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6285 X86_EFLAGS_SF | X86_EFLAGS_OF))
6286 | X86_EFLAGS_CF);
6287}
6288
145c28dd 6289static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6290 u32 vm_instruction_error)
6291{
6292 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6293 /*
6294 * failValid writes the error number to the current VMCS, which
6295 * can't be done there isn't a current VMCS.
6296 */
6297 nested_vmx_failInvalid(vcpu);
6298 return;
6299 }
6300 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6301 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6302 X86_EFLAGS_SF | X86_EFLAGS_OF))
6303 | X86_EFLAGS_ZF);
6304 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6305 /*
6306 * We don't need to force a shadow sync because
6307 * VM_INSTRUCTION_ERROR is not shadowed
6308 */
6309}
145c28dd 6310
ff651cb6
WV		 6311static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6312{
6313 /* TODO: not to reset guest simply here. */
6314 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6315 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6316}
6317
f4124500
JK		 6318static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6319{
6320 struct vcpu_vmx *vmx =
6321 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6322
6323 vmx->nested.preemption_timer_expired = true;
6324 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6325 kvm_vcpu_kick(&vmx->vcpu);
6326
6327 return HRTIMER_NORESTART;
6328}
6329
19677e32
BD		 6330/*
6331 * Decode the memory-address operand of a vmx instruction, as recorded on an
6332 * exit caused by such an instruction (run by a guest hypervisor).
6333 * On success, returns 0. When the operand is invalid, returns 1 and throws
6334 * #UD or #GP.
6335 */
6336static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6337 unsigned long exit_qualification,
f9eb4af6 6338 u32 vmx_instruction_info, bool wr, gva_t *ret)
19677e32 6339{
f9eb4af6
EK		 6340 gva_t off;
6341 bool exn;
6342 struct kvm_segment s;
6343
19677e32
BD		 6344 /*
6345 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6346 * Execution", on an exit, vmx_instruction_info holds most of the
6347 * addressing components of the operand. Only the displacement part
6348 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6349 * For how an actual address is calculated from all these components,
6350 * refer to Vol. 1, "Operand Addressing".
6351 */
6352 int scaling = vmx_instruction_info & 3;
6353 int addr_size = (vmx_instruction_info >> 7) & 7;
6354 bool is_reg = vmx_instruction_info & (1u << 10);
6355 int seg_reg = (vmx_instruction_info >> 15) & 7;
6356 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6357 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6358 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6359 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6360
6361 if (is_reg) {
6362 kvm_queue_exception(vcpu, UD_VECTOR);
6363 return 1;
6364 }
6365
6366 /* Addr = segment_base + offset */
6367 /* offset = base + [index * scale] + displacement */
f9eb4af6 6368 off = exit_qualification; /* holds the displacement */
19677e32 6369 if (base_is_valid)
f9eb4af6 6370 off += kvm_register_read(vcpu, base_reg);
19677e32 6371 if (index_is_valid)
f9eb4af6
EK		 6372 off += kvm_register_read(vcpu, index_reg)<<scaling;
6373 vmx_get_segment(vcpu, &s, seg_reg);
6374 *ret = s.base + off;
19677e32
BD		 6375
6376 if (addr_size == 1) /* 32 bit */
6377 *ret &= 0xffffffff;
6378
f9eb4af6
EK		 6379 /* Checks for #GP/#SS exceptions. */
6380 exn = false;
6381 if (is_protmode(vcpu)) {
6382 /* Protected mode: apply checks for segment validity in the
6383 * following order:
6384 * - segment type check (#GP(0) may be thrown)
6385 * - usability check (#GP(0)/#SS(0))
6386 * - limit check (#GP(0)/#SS(0))
6387 */
6388 if (wr)
6389 /* #GP(0) if the destination operand is located in a
6390 * read-only data segment or any code segment.
6391 */
6392 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6393 else
6394 /* #GP(0) if the source operand is located in an
6395 * execute-only code segment
6396 */
6397 exn = ((s.type & 0xa) == 8);
6398 }
6399 if (exn) {
6400 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6401 return 1;
6402 }
6403 if (is_long_mode(vcpu)) {
6404 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6405 * non-canonical form. This is an only check for long mode.
6406 */
6407 exn = is_noncanonical_address(*ret);
6408 } else if (is_protmode(vcpu)) {
6409 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6410 */
6411 exn = (s.unusable != 0);
6412 /* Protected mode: #GP(0)/#SS(0) if the memory
6413 * operand is outside the segment limit.
6414 */
6415 exn = exn || (off + sizeof(u64) > s.limit);
6416 }
6417 if (exn) {
6418 kvm_queue_exception_e(vcpu,
6419 seg_reg == VCPU_SREG_SS ?
6420 SS_VECTOR : GP_VECTOR,
6421 0);
6422 return 1;
6423 }
6424
19677e32
BD		 6425 return 0;
6426}
6427
3573e22c
BD		 6428/*
6429 * This function performs the various checks including
6430 * - if it's 4KB aligned
6431 * - No bits beyond the physical address width are set
6432 * - Returns 0 on success or else 1
4291b588 6433 * (Intel SDM Section 30.3)
3573e22c 6434 */
4291b588
BD		 6435static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6436 gpa_t *vmpointer)
3573e22c
BD		 6437{
6438 gva_t gva;
6439 gpa_t vmptr;
6440 struct x86_exception e;
6441 struct page *page;
6442 struct vcpu_vmx *vmx = to_vmx(vcpu);
6443 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6444
6445 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 6446 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
3573e22c
BD		 6447 return 1;
6448
6449 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6450 sizeof(vmptr), &e)) {
6451 kvm_inject_page_fault(vcpu, &e);
6452 return 1;
6453 }
6454
6455 switch (exit_reason) {
6456 case EXIT_REASON_VMON:
6457 /*
6458 * SDM 3: 24.11.5
6459 * The first 4 bytes of VMXON region contain the supported
6460 * VMCS revision identifier
6461 *
6462 * Note - IA32_VMX_BASIC[48] will never be 1
6463 * for the nested case;
6464 * which replaces physical address width with 32
6465 *
6466 */
bc39c4db 6467 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6468 nested_vmx_failInvalid(vcpu);
6469 skip_emulated_instruction(vcpu);
6470 return 1;
6471 }
6472
6473 page = nested_get_page(vcpu, vmptr);
6474 if (page == NULL ||
6475 *(u32 *)kmap(page) != VMCS12_REVISION) {
6476 nested_vmx_failInvalid(vcpu);
6477 kunmap(page);
6478 skip_emulated_instruction(vcpu);
6479 return 1;
6480 }
6481 kunmap(page);
6482 vmx->nested.vmxon_ptr = vmptr;
6483 break;
4291b588 6484 case EXIT_REASON_VMCLEAR:
bc39c4db 6485 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6486 nested_vmx_failValid(vcpu,
6487 VMXERR_VMCLEAR_INVALID_ADDRESS);
6488 skip_emulated_instruction(vcpu);
6489 return 1;
6490 }
6491
6492 if (vmptr == vmx->nested.vmxon_ptr) {
6493 nested_vmx_failValid(vcpu,
6494 VMXERR_VMCLEAR_VMXON_POINTER);
6495 skip_emulated_instruction(vcpu);
6496 return 1;
6497 }
6498 break;
6499 case EXIT_REASON_VMPTRLD:
bc39c4db 6500 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6501 nested_vmx_failValid(vcpu,
6502 VMXERR_VMPTRLD_INVALID_ADDRESS);
6503 skip_emulated_instruction(vcpu);
6504 return 1;
6505 }
3573e22c 6506
4291b588
BD		 6507 if (vmptr == vmx->nested.vmxon_ptr) {
6508 nested_vmx_failValid(vcpu,
6509 VMXERR_VMCLEAR_VMXON_POINTER);
6510 skip_emulated_instruction(vcpu);
6511 return 1;
6512 }
6513 break;
3573e22c
BD		 6514 default:
6515 return 1; /* shouldn't happen */
6516 }
6517
4291b588
BD		 6518 if (vmpointer)
6519 *vmpointer = vmptr;
3573e22c
BD		 6520 return 0;
6521}
6522
ec378aee
NHE		 6523/*
6524 * Emulate the VMXON instruction.
6525 * Currently, we just remember that VMX is active, and do not save or even
6526 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6527 * do not currently need to store anything in that guest-allocated memory
6528 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6529 * argument is different from the VMXON pointer (which the spec says they do).
6530 */
6531static int handle_vmon(struct kvm_vcpu *vcpu)
6532{
6533 struct kvm_segment cs;
6534 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6535 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6536 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6537 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6538
6539 /* The Intel VMX Instruction Reference lists a bunch of bits that
6540 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6541 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6542 * Otherwise, we should fail with #UD. We test these now:
6543 */
6544 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6545 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6546 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6547 kvm_queue_exception(vcpu, UD_VECTOR);
6548 return 1;
6549 }
6550
6551 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6552 if (is_long_mode(vcpu) && !cs.l) {
6553 kvm_queue_exception(vcpu, UD_VECTOR);
6554 return 1;
6555 }
6556
6557 if (vmx_get_cpl(vcpu)) {
6558 kvm_inject_gp(vcpu, 0);
6559 return 1;
6560 }
3573e22c 6561
4291b588 6562 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6563 return 1;
6564
145c28dd
AG		 6565 if (vmx->nested.vmxon) {
6566 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6567 skip_emulated_instruction(vcpu);
6568 return 1;
6569 }
b3897a49
NHE		 6570
6571 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6572 != VMXON_NEEDED_FEATURES) {
6573 kvm_inject_gp(vcpu, 0);
6574 return 1;
6575 }
6576
8de48833
AG		 6577 if (enable_shadow_vmcs) {
6578 shadow_vmcs = alloc_vmcs();
6579 if (!shadow_vmcs)
6580 return -ENOMEM;
6581 /* mark vmcs as shadow */
6582 shadow_vmcs->revision_id |= (1u << 31);
6583 /* init shadow vmcs */
6584 vmcs_clear(shadow_vmcs);
6585 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6586 }
ec378aee 6587
ff2f6fe9
NHE		 6588 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6589 vmx->nested.vmcs02_num = 0;
6590
f4124500
JK		 6591 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6592 HRTIMER_MODE_REL);
6593 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6594
ec378aee
NHE		 6595 vmx->nested.vmxon = true;
6596
6597 skip_emulated_instruction(vcpu);
a25eb114 6598 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6599 return 1;
6600}
6601
6602/*
6603 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6604 * for running VMX instructions (except VMXON, whose prerequisites are
6605 * slightly different). It also specifies what exception to inject otherwise.
6606 */
6607static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6608{
6609 struct kvm_segment cs;
6610 struct vcpu_vmx *vmx = to_vmx(vcpu);
6611
6612 if (!vmx->nested.vmxon) {
6613 kvm_queue_exception(vcpu, UD_VECTOR);
6614 return 0;
6615 }
6616
6617 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6618 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6619 (is_long_mode(vcpu) && !cs.l)) {
6620 kvm_queue_exception(vcpu, UD_VECTOR);
6621 return 0;
6622 }
6623
6624 if (vmx_get_cpl(vcpu)) {
6625 kvm_inject_gp(vcpu, 0);
6626 return 0;
6627 }
6628
6629 return 1;
6630}
6631
e7953d7f
AG		 6632static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6633{
8a1b9dd0 6634 u32 exec_control;
9a2a05b9
PB		 6635 if (vmx->nested.current_vmptr == -1ull)
6636 return;
6637
6638 /* current_vmptr and current_vmcs12 are always set/reset together */
6639 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6640 return;
6641
012f83cb 6642 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6643 /* copy to memory all shadowed fields in case
6644 they were modified */
6645 copy_shadow_to_vmcs12(vmx);
6646 vmx->nested.sync_shadow_vmcs = false;
6647 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6648 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6649 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6650 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6651 }
705699a1 6652 vmx->nested.posted_intr_nv = -1;
e7953d7f
AG		 6653 kunmap(vmx->nested.current_vmcs12_page);
6654 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6655 vmx->nested.current_vmptr = -1ull;
6656 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6657}
6658
ec378aee
NHE		 6659/*
6660 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6661 * just stops using VMX.
6662 */
6663static void free_nested(struct vcpu_vmx *vmx)
6664{
6665 if (!vmx->nested.vmxon)
6666 return;
9a2a05b9 6667
ec378aee 6668 vmx->nested.vmxon = false;
9a2a05b9 6669 nested_release_vmcs12(vmx);
e7953d7f
AG		 6670 if (enable_shadow_vmcs)
6671 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6672 /* Unpin physical memory we referred to in current vmcs02 */
6673 if (vmx->nested.apic_access_page) {
6674 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6675 vmx->nested.apic_access_page = NULL;
fe3ef05c 6676 }
a7c0b07d
WL		 6677 if (vmx->nested.virtual_apic_page) {
6678 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6679 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6680 }
705699a1
WV		 6681 if (vmx->nested.pi_desc_page) {
6682 kunmap(vmx->nested.pi_desc_page);
6683 nested_release_page(vmx->nested.pi_desc_page);
6684 vmx->nested.pi_desc_page = NULL;
6685 vmx->nested.pi_desc = NULL;
6686 }
ff2f6fe9
NHE		 6687
6688 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6689}
6690
6691/* Emulate the VMXOFF instruction */
6692static int handle_vmoff(struct kvm_vcpu *vcpu)
6693{
6694 if (!nested_vmx_check_permission(vcpu))
6695 return 1;
6696 free_nested(to_vmx(vcpu));
6697 skip_emulated_instruction(vcpu);
a25eb114 6698 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6699 return 1;
6700}
6701
27d6c865
NHE		 6702/* Emulate the VMCLEAR instruction */
6703static int handle_vmclear(struct kvm_vcpu *vcpu)
6704{
6705 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6706 gpa_t vmptr;
6707 struct vmcs12 *vmcs12;
6708 struct page *page;
27d6c865
NHE		 6709
6710 if (!nested_vmx_check_permission(vcpu))
6711 return 1;
6712
4291b588 6713 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6714 return 1;
27d6c865 6715
9a2a05b9 6716 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6717 nested_release_vmcs12(vmx);
27d6c865
NHE		 6718
6719 page = nested_get_page(vcpu, vmptr);
6720 if (page == NULL) {
6721 /*
6722 * For accurate processor emulation, VMCLEAR beyond available
6723 * physical memory should do nothing at all. However, it is
6724 * possible that a nested vmx bug, not a guest hypervisor bug,
6725 * resulted in this case, so let's shut down before doing any
6726 * more damage:
6727 */
6728 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6729 return 1;
6730 }
6731 vmcs12 = kmap(page);
6732 vmcs12->launch_state = 0;
6733 kunmap(page);
6734 nested_release_page(page);
6735
6736 nested_free_vmcs02(vmx, vmptr);
6737
6738 skip_emulated_instruction(vcpu);
6739 nested_vmx_succeed(vcpu);
6740 return 1;
6741}
6742
cd232ad0
NHE		 6743static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6744
6745/* Emulate the VMLAUNCH instruction */
6746static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6747{
6748 return nested_vmx_run(vcpu, true);
6749}
6750
6751/* Emulate the VMRESUME instruction */
6752static int handle_vmresume(struct kvm_vcpu *vcpu)
6753{
6754
6755 return nested_vmx_run(vcpu, false);
6756}
6757
49f705c5
NHE		 6758enum vmcs_field_type {
6759 VMCS_FIELD_TYPE_U16 = 0,
6760 VMCS_FIELD_TYPE_U64 = 1,
6761 VMCS_FIELD_TYPE_U32 = 2,
6762 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6763};
6764
6765static inline int vmcs_field_type(unsigned long field)
6766{
6767 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6768 return VMCS_FIELD_TYPE_U32;
6769 return (field >> 13) & 0x3 ;
6770}
6771
6772static inline int vmcs_field_readonly(unsigned long field)
6773{
6774 return (((field >> 10) & 0x3) == 1);
6775}
6776
6777/*
6778 * Read a vmcs12 field. Since these can have varying lengths and we return
6779 * one type, we chose the biggest type (u64) and zero-extend the return value
6780 * to that size. Note that the caller, handle_vmread, might need to use only
6781 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6782 * 64-bit fields are to be returned).
6783 */
a2ae9df7
PB		 6784static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6785 unsigned long field, u64 *ret)
49f705c5
NHE		 6786{
6787 short offset = vmcs_field_to_offset(field);
6788 char *p;
6789
6790 if (offset < 0)
a2ae9df7 6791 return offset;
49f705c5
NHE		 6792
6793 p = ((char *)(get_vmcs12(vcpu))) + offset;
6794
6795 switch (vmcs_field_type(field)) {
6796 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6797 *ret = *((natural_width *)p);
a2ae9df7 6798 return 0;
49f705c5
NHE		 6799 case VMCS_FIELD_TYPE_U16:
6800 *ret = *((u16 *)p);
a2ae9df7 6801 return 0;
49f705c5
NHE		 6802 case VMCS_FIELD_TYPE_U32:
6803 *ret = *((u32 *)p);
a2ae9df7 6804 return 0;
49f705c5
NHE		 6805 case VMCS_FIELD_TYPE_U64:
6806 *ret = *((u64 *)p);
a2ae9df7 6807 return 0;
49f705c5 6808 default:
a2ae9df7
PB		 6809 WARN_ON(1);
6810 return -ENOENT;
49f705c5
NHE		 6811 }
6812}
6813
20b97fea 6814
a2ae9df7
PB		 6815static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6816 unsigned long field, u64 field_value){
20b97fea
AG		 6817 short offset = vmcs_field_to_offset(field);
6818 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6819 if (offset < 0)
a2ae9df7 6820 return offset;
20b97fea
AG		 6821
6822 switch (vmcs_field_type(field)) {
6823 case VMCS_FIELD_TYPE_U16:
6824 *(u16 *)p = field_value;
a2ae9df7 6825 return 0;
20b97fea
AG		 6826 case VMCS_FIELD_TYPE_U32:
6827 *(u32 *)p = field_value;
a2ae9df7 6828 return 0;
20b97fea
AG		 6829 case VMCS_FIELD_TYPE_U64:
6830 *(u64 *)p = field_value;
a2ae9df7 6831 return 0;
20b97fea
AG		 6832 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6833 *(natural_width *)p = field_value;
a2ae9df7 6834 return 0;
20b97fea 6835 default:
a2ae9df7
PB		 6836 WARN_ON(1);
6837 return -ENOENT;
20b97fea
AG		 6838 }
6839
6840}
6841
16f5b903
AG		 6842static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6843{
6844 int i;
6845 unsigned long field;
6846 u64 field_value;
6847 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6848 const unsigned long *fields = shadow_read_write_fields;
6849 const int num_fields = max_shadow_read_write_fields;
16f5b903 6850
282da870
JK		 6851 preempt_disable();
6852
16f5b903
AG		 6853 vmcs_load(shadow_vmcs);
6854
6855 for (i = 0; i < num_fields; i++) {
6856 field = fields[i];
6857 switch (vmcs_field_type(field)) {
6858 case VMCS_FIELD_TYPE_U16:
6859 field_value = vmcs_read16(field);
6860 break;
6861 case VMCS_FIELD_TYPE_U32:
6862 field_value = vmcs_read32(field);
6863 break;
6864 case VMCS_FIELD_TYPE_U64:
6865 field_value = vmcs_read64(field);
6866 break;
6867 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6868 field_value = vmcs_readl(field);
6869 break;
a2ae9df7
PB		 6870 default:
6871 WARN_ON(1);
6872 continue;
16f5b903
AG		 6873 }
6874 vmcs12_write_any(&vmx->vcpu, field, field_value);
6875 }
6876
6877 vmcs_clear(shadow_vmcs);
6878 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6879
6880 preempt_enable();
16f5b903
AG		 6881}
6882
c3114420
AG		 6883static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6884{
c2bae893
MK		 6885 const unsigned long *fields[] = {
6886 shadow_read_write_fields,
6887 shadow_read_only_fields
c3114420 6888 };
c2bae893 6889 const int max_fields[] = {
c3114420
AG		 6890 max_shadow_read_write_fields,
6891 max_shadow_read_only_fields
6892 };
6893 int i, q;
6894 unsigned long field;
6895 u64 field_value = 0;
6896 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6897
6898 vmcs_load(shadow_vmcs);
6899
c2bae893 6900 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6901 for (i = 0; i < max_fields[q]; i++) {
6902 field = fields[q][i];
6903 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6904
6905 switch (vmcs_field_type(field)) {
6906 case VMCS_FIELD_TYPE_U16:
6907 vmcs_write16(field, (u16)field_value);
6908 break;
6909 case VMCS_FIELD_TYPE_U32:
6910 vmcs_write32(field, (u32)field_value);
6911 break;
6912 case VMCS_FIELD_TYPE_U64:
6913 vmcs_write64(field, (u64)field_value);
6914 break;
6915 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6916 vmcs_writel(field, (long)field_value);
6917 break;
a2ae9df7
PB		 6918 default:
6919 WARN_ON(1);
6920 break;
c3114420
AG		 6921 }
6922 }
6923 }
6924
6925 vmcs_clear(shadow_vmcs);
6926 vmcs_load(vmx->loaded_vmcs->vmcs);
6927}
6928
49f705c5
NHE		 6929/*
6930 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6931 * used before) all generate the same failure when it is missing.
6932 */
6933static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6934{
6935 struct vcpu_vmx *vmx = to_vmx(vcpu);
6936 if (vmx->nested.current_vmptr == -1ull) {
6937 nested_vmx_failInvalid(vcpu);
6938 skip_emulated_instruction(vcpu);
6939 return 0;
6940 }
6941 return 1;
6942}
6943
6944static int handle_vmread(struct kvm_vcpu *vcpu)
6945{
6946 unsigned long field;
6947 u64 field_value;
6948 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6949 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6950 gva_t gva = 0;
6951
6952 if (!nested_vmx_check_permission(vcpu) ||
6953 !nested_vmx_check_vmcs12(vcpu))
6954 return 1;
6955
6956 /* Decode instruction info and find the field to read */
27e6fb5d 6957 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6958 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6959 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6960 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6961 skip_emulated_instruction(vcpu);
6962 return 1;
6963 }
6964 /*
6965 * Now copy part of this value to register or memory, as requested.
6966 * Note that the number of bits actually copied is 32 or 64 depending
6967 * on the guest's mode (32 or 64 bit), not on the given field's length.
6968 */
6969 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6970 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6971 field_value);
6972 } else {
6973 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 6974 vmx_instruction_info, true, &gva))
49f705c5
NHE		 6975 return 1;
6976 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6977 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6978 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6979 }
6980
6981 nested_vmx_succeed(vcpu);
6982 skip_emulated_instruction(vcpu);
6983 return 1;
6984}
6985
6986
6987static int handle_vmwrite(struct kvm_vcpu *vcpu)
6988{
6989 unsigned long field;
6990 gva_t gva;
6991 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6992 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6993 /* The value to write might be 32 or 64 bits, depending on L1's long
6994 * mode, and eventually we need to write that into a field of several
6995 * possible lengths. The code below first zero-extends the value to 64
6996 * bit (field_value), and then copies only the approriate number of
6997 * bits into the vmcs12 field.
6998 */
6999 u64 field_value = 0;
7000 struct x86_exception e;
7001
7002 if (!nested_vmx_check_permission(vcpu) ||
7003 !nested_vmx_check_vmcs12(vcpu))
7004 return 1;
7005
7006 if (vmx_instruction_info & (1u << 10))
27e6fb5d 7007 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 7008 (((vmx_instruction_info) >> 3) & 0xf));
7009 else {
7010 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7011 vmx_instruction_info, false, &gva))
49f705c5
NHE		 7012 return 1;
7013 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 7014 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 7015 kvm_inject_page_fault(vcpu, &e);
7016 return 1;
7017 }
7018 }
7019
7020
27e6fb5d 7021 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 7022 if (vmcs_field_readonly(field)) {
7023 nested_vmx_failValid(vcpu,
7024 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7025 skip_emulated_instruction(vcpu);
7026 return 1;
7027 }
7028
a2ae9df7 7029 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 7030 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7031 skip_emulated_instruction(vcpu);
7032 return 1;
7033 }
7034
7035 nested_vmx_succeed(vcpu);
7036 skip_emulated_instruction(vcpu);
7037 return 1;
7038}
7039
63846663
NHE		 7040/* Emulate the VMPTRLD instruction */
7041static int handle_vmptrld(struct kvm_vcpu *vcpu)
7042{
7043 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 7044 gpa_t vmptr;
8a1b9dd0 7045 u32 exec_control;
63846663
NHE		 7046
7047 if (!nested_vmx_check_permission(vcpu))
7048 return 1;
7049
4291b588 7050 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 7051 return 1;
63846663
NHE		 7052
7053 if (vmx->nested.current_vmptr != vmptr) {
7054 struct vmcs12 *new_vmcs12;
7055 struct page *page;
7056 page = nested_get_page(vcpu, vmptr);
7057 if (page == NULL) {
7058 nested_vmx_failInvalid(vcpu);
7059 skip_emulated_instruction(vcpu);
7060 return 1;
7061 }
7062 new_vmcs12 = kmap(page);
7063 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7064 kunmap(page);
7065 nested_release_page_clean(page);
7066 nested_vmx_failValid(vcpu,
7067 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7068 skip_emulated_instruction(vcpu);
7069 return 1;
7070 }
63846663 7071
9a2a05b9 7072 nested_release_vmcs12(vmx);
63846663
NHE		 7073 vmx->nested.current_vmptr = vmptr;
7074 vmx->nested.current_vmcs12 = new_vmcs12;
7075 vmx->nested.current_vmcs12_page = page;
012f83cb 7076 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 7077 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7078 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
7079 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7080 vmcs_write64(VMCS_LINK_POINTER,
7081 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 7082 vmx->nested.sync_shadow_vmcs = true;
7083 }
63846663
NHE		 7084 }
7085
7086 nested_vmx_succeed(vcpu);
7087 skip_emulated_instruction(vcpu);
7088 return 1;
7089}
7090
6a4d7550
NHE		 7091/* Emulate the VMPTRST instruction */
7092static int handle_vmptrst(struct kvm_vcpu *vcpu)
7093{
7094 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7095 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7096 gva_t vmcs_gva;
7097 struct x86_exception e;
7098
7099 if (!nested_vmx_check_permission(vcpu))
7100 return 1;
7101
7102 if (get_vmx_mem_address(vcpu, exit_qualification,
f9eb4af6 7103 vmx_instruction_info, true, &vmcs_gva))
6a4d7550
NHE		 7104 return 1;
7105 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7106 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7107 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7108 sizeof(u64), &e)) {
7109 kvm_inject_page_fault(vcpu, &e);
7110 return 1;
7111 }
7112 nested_vmx_succeed(vcpu);
7113 skip_emulated_instruction(vcpu);
7114 return 1;
7115}
7116
bfd0a56b
NHE		 7117/* Emulate the INVEPT instruction */
7118static int handle_invept(struct kvm_vcpu *vcpu)
7119{
b9c237bb 7120 struct vcpu_vmx *vmx = to_vmx(vcpu);
bfd0a56b
NHE		 7121 u32 vmx_instruction_info, types;
7122 unsigned long type;
7123 gva_t gva;
7124 struct x86_exception e;
7125 struct {
7126 u64 eptp, gpa;
7127 } operand;
bfd0a56b 7128
b9c237bb
WV		 7129 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7130 SECONDARY_EXEC_ENABLE_EPT) ||
7131 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
bfd0a56b
NHE		 7132 kvm_queue_exception(vcpu, UD_VECTOR);
7133 return 1;
7134 }
7135
7136 if (!nested_vmx_check_permission(vcpu))
7137 return 1;
7138
7139 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7140 kvm_queue_exception(vcpu, UD_VECTOR);
7141 return 1;
7142 }
7143
7144 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7145 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b 7146
b9c237bb 7147 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
bfd0a56b
NHE		 7148
7149 if (!(types & (1UL << type))) {
7150 nested_vmx_failValid(vcpu,
7151 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7152 return 1;
7153 }
7154
7155 /* According to the Intel VMX instruction reference, the memory
7156 * operand is read even if it isn't needed (e.g., for type==global)
7157 */
7158 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
f9eb4af6 7159 vmx_instruction_info, false, &gva))
bfd0a56b
NHE		 7160 return 1;
7161 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7162 sizeof(operand), &e)) {
7163 kvm_inject_page_fault(vcpu, &e);
7164 return 1;
7165 }
7166
7167 switch (type) {
bfd0a56b
NHE		 7168 case VMX_EPT_EXTENT_GLOBAL:
7169 kvm_mmu_sync_roots(vcpu);
77c3913b 7170 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7171 nested_vmx_succeed(vcpu);
7172 break;
7173 default:
4b855078 7174 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7175 BUG_ON(1);
7176 break;
7177 }
7178
7179 skip_emulated_instruction(vcpu);
7180 return 1;
7181}
7182
a642fc30
PM		 7183static int handle_invvpid(struct kvm_vcpu *vcpu)
7184{
7185 kvm_queue_exception(vcpu, UD_VECTOR);
7186 return 1;
7187}
7188
843e4330
KH		 7189static int handle_pml_full(struct kvm_vcpu *vcpu)
7190{
7191 unsigned long exit_qualification;
7192
7193 trace_kvm_pml_full(vcpu->vcpu_id);
7194
7195 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7196
7197 /*
7198 * PML buffer FULL happened while executing iret from NMI,
7199 * "blocked by NMI" bit has to be set before next VM entry.
7200 */
7201 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7202 cpu_has_virtual_nmis() &&
7203 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7204 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7205 GUEST_INTR_STATE_NMI);
7206
7207 /*
7208 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7209 * here.., and there's no userspace involvement needed for PML.
7210 */
7211 return 1;
7212}
7213
6aa8b732
AK		 7214/*
7215 * The exit handlers return 1 if the exit was handled fully and guest execution
7216 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7217 * to be done to userspace and return 0.
7218 */
772e0318 7219static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7220 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7221 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7222 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7223 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7224 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7225 [EXIT_REASON_CR_ACCESS] = handle_cr,
7226 [EXIT_REASON_DR_ACCESS] = handle_dr,
7227 [EXIT_REASON_CPUID] = handle_cpuid,
7228 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7229 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7230 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7231 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7232 [EXIT_REASON_INVD] = handle_invd,
a7052897 7233 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7234 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7235 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7236 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7237 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7238 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7239 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7240 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7241 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7242 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7243 [EXIT_REASON_VMOFF] = handle_vmoff,
7244 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7245 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7246 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7247 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7248 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7249 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7250 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7251 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7252 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7253 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7254 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7255 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572 7256 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5f3d45e7 7257 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
87c00572 7258 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7259 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7260 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7261 [EXIT_REASON_XSAVES] = handle_xsaves,
7262 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7263 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7264};
7265
7266static const int kvm_vmx_max_exit_handlers =
50a3485c 7267 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7268
908a7bdd
JK		 7269static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7270 struct vmcs12 *vmcs12)
7271{
7272 unsigned long exit_qualification;
7273 gpa_t bitmap, last_bitmap;
7274 unsigned int port;
7275 int size;
7276 u8 b;
7277
908a7bdd 7278 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7279 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7280
7281 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7282
7283 port = exit_qualification >> 16;
7284 size = (exit_qualification & 7) + 1;
7285
7286 last_bitmap = (gpa_t)-1;
7287 b = -1;
7288
7289 while (size > 0) {
7290 if (port < 0x8000)
7291 bitmap = vmcs12->io_bitmap_a;
7292 else if (port < 0x10000)
7293 bitmap = vmcs12->io_bitmap_b;
7294 else
1d804d07 7295 return true;
908a7bdd
JK		 7296 bitmap += (port & 0x7fff) / 8;
7297
7298 if (last_bitmap != bitmap)
54bf36aa 7299 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
1d804d07 7300 return true;
908a7bdd 7301 if (b & (1 << (port & 7)))
1d804d07 7302 return true;
908a7bdd
JK		 7303
7304 port++;
7305 size--;
7306 last_bitmap = bitmap;
7307 }
7308
1d804d07 7309 return false;
908a7bdd
JK		 7310}
7311
644d711a
NHE		 7312/*
7313 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7314 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7315 * disinterest in the current event (read or write a specific MSR) by using an
7316 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7317 */
7318static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7319 struct vmcs12 *vmcs12, u32 exit_reason)
7320{
7321 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7322 gpa_t bitmap;
7323
cbd29cb6 7324 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
1d804d07 7325 return true;
644d711a
NHE		 7326
7327 /*
7328 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7329 * for the four combinations of read/write and low/high MSR numbers.
7330 * First we need to figure out which of the four to use:
7331 */
7332 bitmap = vmcs12->msr_bitmap;
7333 if (exit_reason == EXIT_REASON_MSR_WRITE)
7334 bitmap += 2048;
7335 if (msr_index >= 0xc0000000) {
7336 msr_index -= 0xc0000000;
7337 bitmap += 1024;
7338 }
7339
7340 /* Then read the msr_index'th bit from this bitmap: */
7341 if (msr_index < 1024*8) {
7342 unsigned char b;
54bf36aa 7343 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
1d804d07 7344 return true;
644d711a
NHE		 7345 return 1 & (b >> (msr_index & 7));
7346 } else
1d804d07 7347 return true; /* let L1 handle the wrong parameter */
644d711a
NHE		 7348}
7349
7350/*
7351 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7352 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7353 * intercept (via guest_host_mask etc.) the current event.
7354 */
7355static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7356 struct vmcs12 *vmcs12)
7357{
7358 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7359 int cr = exit_qualification & 15;
7360 int reg = (exit_qualification >> 8) & 15;
1e32c079 7361 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7362
7363 switch ((exit_qualification >> 4) & 3) {
7364 case 0: /* mov to cr */
7365 switch (cr) {
7366 case 0:
7367 if (vmcs12->cr0_guest_host_mask &
7368 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7369 return true;
644d711a
NHE		 7370 break;
7371 case 3:
7372 if ((vmcs12->cr3_target_count >= 1 &&
7373 vmcs12->cr3_target_value0 == val) ||
7374 (vmcs12->cr3_target_count >= 2 &&
7375 vmcs12->cr3_target_value1 == val) ||
7376 (vmcs12->cr3_target_count >= 3 &&
7377 vmcs12->cr3_target_value2 == val) ||
7378 (vmcs12->cr3_target_count >= 4 &&
7379 vmcs12->cr3_target_value3 == val))
1d804d07 7380 return false;
644d711a 7381 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
1d804d07 7382 return true;
644d711a
NHE		 7383 break;
7384 case 4:
7385 if (vmcs12->cr4_guest_host_mask &
7386 (vmcs12->cr4_read_shadow ^ val))
1d804d07 7387 return true;
644d711a
NHE		 7388 break;
7389 case 8:
7390 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
1d804d07 7391 return true;
644d711a
NHE		 7392 break;
7393 }
7394 break;
7395 case 2: /* clts */
7396 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7397 (vmcs12->cr0_read_shadow & X86_CR0_TS))
1d804d07 7398 return true;
644d711a
NHE		 7399 break;
7400 case 1: /* mov from cr */
7401 switch (cr) {
7402 case 3:
7403 if (vmcs12->cpu_based_vm_exec_control &
7404 CPU_BASED_CR3_STORE_EXITING)
1d804d07 7405 return true;
644d711a
NHE		 7406 break;
7407 case 8:
7408 if (vmcs12->cpu_based_vm_exec_control &
7409 CPU_BASED_CR8_STORE_EXITING)
1d804d07 7410 return true;
644d711a
NHE		 7411 break;
7412 }
7413 break;
7414 case 3: /* lmsw */
7415 /*
7416 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7417 * cr0. Other attempted changes are ignored, with no exit.
7418 */
7419 if (vmcs12->cr0_guest_host_mask & 0xe &
7420 (val ^ vmcs12->cr0_read_shadow))
1d804d07 7421 return true;
644d711a
NHE		 7422 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7423 !(vmcs12->cr0_read_shadow & 0x1) &&
7424 (val & 0x1))
1d804d07 7425 return true;
644d711a
NHE		 7426 break;
7427 }
1d804d07 7428 return false;
644d711a
NHE		 7429}
7430
7431/*
7432 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7433 * should handle it ourselves in L0 (and then continue L2). Only call this
7434 * when in is_guest_mode (L2).
7435 */
7436static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7437{
644d711a
NHE		 7438 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7439 struct vcpu_vmx *vmx = to_vmx(vcpu);
7440 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7441 u32 exit_reason = vmx->exit_reason;
644d711a 7442
542060ea
JK		 7443 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7444 vmcs_readl(EXIT_QUALIFICATION),
7445 vmx->idt_vectoring_info,
7446 intr_info,
7447 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7448 KVM_ISA_VMX);
7449
644d711a 7450 if (vmx->nested.nested_run_pending)
1d804d07 7451 return false;
644d711a
NHE		 7452
7453 if (unlikely(vmx->fail)) {
bd80158a
JK		 7454 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7455 vmcs_read32(VM_INSTRUCTION_ERROR));
1d804d07 7456 return true;
644d711a
NHE		 7457 }
7458
7459 switch (exit_reason) {
7460 case EXIT_REASON_EXCEPTION_NMI:
7461 if (!is_exception(intr_info))
1d804d07 7462 return false;
644d711a
NHE		 7463 else if (is_page_fault(intr_info))
7464 return enable_ept;
e504c909 7465 else if (is_no_device(intr_info) &&
ccf9844e 7466 !(vmcs12->guest_cr0 & X86_CR0_TS))
1d804d07 7467 return false;
644d711a
NHE		 7468 return vmcs12->exception_bitmap &
7469 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7470 case EXIT_REASON_EXTERNAL_INTERRUPT:
1d804d07 7471 return false;
644d711a 7472 case EXIT_REASON_TRIPLE_FAULT:
1d804d07 7473 return true;
644d711a 7474 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7475 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7476 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7477 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a 7478 case EXIT_REASON_TASK_SWITCH:
1d804d07 7479 return true;
644d711a 7480 case EXIT_REASON_CPUID:
bc613494 7481 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
1d804d07
JP		 7482 return false;
7483 return true;
644d711a
NHE		 7484 case EXIT_REASON_HLT:
7485 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7486 case EXIT_REASON_INVD:
1d804d07 7487 return true;
644d711a
NHE		 7488 case EXIT_REASON_INVLPG:
7489 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7490 case EXIT_REASON_RDPMC:
7491 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
b3a2a907 7492 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
644d711a
NHE		 7493 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7494 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7495 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7496 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7497 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7498 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7499 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7500 /*
7501 * VMX instructions trap unconditionally. This allows L1 to
7502 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7503 */
1d804d07 7504 return true;
644d711a
NHE		 7505 case EXIT_REASON_CR_ACCESS:
7506 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7507 case EXIT_REASON_DR_ACCESS:
7508 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7509 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7510 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7511 case EXIT_REASON_MSR_READ:
7512 case EXIT_REASON_MSR_WRITE:
7513 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7514 case EXIT_REASON_INVALID_STATE:
1d804d07 7515 return true;
644d711a
NHE		 7516 case EXIT_REASON_MWAIT_INSTRUCTION:
7517 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5f3d45e7
MD		 7518 case EXIT_REASON_MONITOR_TRAP_FLAG:
7519 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
644d711a
NHE		 7520 case EXIT_REASON_MONITOR_INSTRUCTION:
7521 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7522 case EXIT_REASON_PAUSE_INSTRUCTION:
7523 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7524 nested_cpu_has2(vmcs12,
7525 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7526 case EXIT_REASON_MCE_DURING_VMENTRY:
1d804d07 7527 return false;
644d711a 7528 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7529 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7530 case EXIT_REASON_APIC_ACCESS:
7531 return nested_cpu_has2(vmcs12,
7532 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
82f0dd4b 7533 case EXIT_REASON_APIC_WRITE:
608406e2
WV		 7534 case EXIT_REASON_EOI_INDUCED:
7535 /* apic_write and eoi_induced should exit unconditionally. */
1d804d07 7536 return true;
644d711a 7537 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7538 /*
7539 * L0 always deals with the EPT violation. If nested EPT is
7540 * used, and the nested mmu code discovers that the address is
7541 * missing in the guest EPT table (EPT12), the EPT violation
7542 * will be injected with nested_ept_inject_page_fault()
7543 */
1d804d07 7544 return false;
644d711a 7545 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7546 /*
7547 * L2 never uses directly L1's EPT, but rather L0's own EPT
7548 * table (shadow on EPT) or a merged EPT table that L0 built
7549 * (EPT on EPT). So any problems with the structure of the
7550 * table is L0's fault.
7551 */
1d804d07 7552 return false;
644d711a
NHE		 7553 case EXIT_REASON_WBINVD:
7554 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7555 case EXIT_REASON_XSETBV:
1d804d07 7556 return true;
81dc01f7
WL		 7557 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7558 /*
7559 * This should never happen, since it is not possible to
7560 * set XSS to a non-zero value---neither in L1 nor in L2.
7561 * If if it were, XSS would have to be checked against
7562 * the XSS exit bitmap in vmcs12.
7563 */
7564 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a 7565 default:
1d804d07 7566 return true;
644d711a
NHE		 7567 }
7568}
7569
586f9607
AK		 7570static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7571{
7572 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7573 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7574}
7575
843e4330
KH		 7576static int vmx_enable_pml(struct vcpu_vmx *vmx)
7577{
7578 struct page *pml_pg;
7579 u32 exec_control;
7580
7581 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7582 if (!pml_pg)
7583 return -ENOMEM;
7584
7585 vmx->pml_pg = pml_pg;
7586
7587 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7588 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7589
7590 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7591 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7592 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7593
7594 return 0;
7595}
7596
7597static void vmx_disable_pml(struct vcpu_vmx *vmx)
7598{
7599 u32 exec_control;
7600
7601 ASSERT(vmx->pml_pg);
7602 __free_page(vmx->pml_pg);
7603 vmx->pml_pg = NULL;
7604
7605 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7606 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7607 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7608}
7609
54bf36aa 7610static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
843e4330 7611{
54bf36aa 7612 struct vcpu_vmx *vmx = to_vmx(vcpu);
843e4330
KH		 7613 u64 *pml_buf;
7614 u16 pml_idx;
7615
7616 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7617
7618 /* Do nothing if PML buffer is empty */
7619 if (pml_idx == (PML_ENTITY_NUM - 1))
7620 return;
7621
7622 /* PML index always points to next available PML buffer entity */
7623 if (pml_idx >= PML_ENTITY_NUM)
7624 pml_idx = 0;
7625 else
7626 pml_idx++;
7627
7628 pml_buf = page_address(vmx->pml_pg);
7629 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7630 u64 gpa;
7631
7632 gpa = pml_buf[pml_idx];
7633 WARN_ON(gpa & (PAGE_SIZE - 1));
54bf36aa 7634 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
843e4330
KH		 7635 }
7636
7637 /* reset PML index */
7638 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7639}
7640
7641/*
7642 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7643 * Called before reporting dirty_bitmap to userspace.
7644 */
7645static void kvm_flush_pml_buffers(struct kvm *kvm)
7646{
7647 int i;
7648 struct kvm_vcpu *vcpu;
7649 /*
7650 * We only need to kick vcpu out of guest mode here, as PML buffer
7651 * is flushed at beginning of all VMEXITs, and it's obvious that only
7652 * vcpus running in guest are possible to have unflushed GPAs in PML
7653 * buffer.
7654 */
7655 kvm_for_each_vcpu(i, vcpu, kvm)
7656 kvm_vcpu_kick(vcpu);
7657}
7658
4eb64dce
PB		 7659static void vmx_dump_sel(char *name, uint32_t sel)
7660{
7661 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7662 name, vmcs_read32(sel),
7663 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7664 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7665 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7666}
7667
7668static void vmx_dump_dtsel(char *name, uint32_t limit)
7669{
7670 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7671 name, vmcs_read32(limit),
7672 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7673}
7674
7675static void dump_vmcs(void)
7676{
7677 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7678 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7679 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7680 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7681 u32 secondary_exec_control = 0;
7682 unsigned long cr4 = vmcs_readl(GUEST_CR4);
7683 u64 efer = vmcs_readl(GUEST_IA32_EFER);
7684 int i, n;
7685
7686 if (cpu_has_secondary_exec_ctrls())
7687 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7688
7689 pr_err("*** Guest State ***\n");
7690 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7691 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7692 vmcs_readl(CR0_GUEST_HOST_MASK));
7693 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7694 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7695 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7696 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7697 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7698 {
7699 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7700 vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7701 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7702 vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7703 }
7704 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7705 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7706 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7707 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7708 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7709 vmcs_readl(GUEST_SYSENTER_ESP),
7710 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7711 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
7712 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
7713 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
7714 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
7715 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
7716 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
7717 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7718 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7719 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7720 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
7721 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7722 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7723 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7724 efer, vmcs_readl(GUEST_IA32_PAT));
7725 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7726 vmcs_readl(GUEST_IA32_DEBUGCTL),
7727 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7728 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7729 pr_err("PerfGlobCtl = 0x%016lx\n",
7730 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7731 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7732 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7733 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7734 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7735 vmcs_read32(GUEST_ACTIVITY_STATE));
7736 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7737 pr_err("InterruptStatus = %04x\n",
7738 vmcs_read16(GUEST_INTR_STATUS));
7739
7740 pr_err("*** Host State ***\n");
7741 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7742 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7743 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7744 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7745 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7746 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7747 vmcs_read16(HOST_TR_SELECTOR));
7748 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7749 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7750 vmcs_readl(HOST_TR_BASE));
7751 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7752 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7753 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7754 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7755 vmcs_readl(HOST_CR4));
7756 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7757 vmcs_readl(HOST_IA32_SYSENTER_ESP),
7758 vmcs_read32(HOST_IA32_SYSENTER_CS),
7759 vmcs_readl(HOST_IA32_SYSENTER_EIP));
7760 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7761 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7762 vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7763 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7764 pr_err("PerfGlobCtl = 0x%016lx\n",
7765 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7766
7767 pr_err("*** Control State ***\n");
7768 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7769 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7770 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7771 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7772 vmcs_read32(EXCEPTION_BITMAP),
7773 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7774 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7775 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7776 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7777 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7778 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
7779 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7780 vmcs_read32(VM_EXIT_INTR_INFO),
7781 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7782 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
7783 pr_err(" reason=%08x qualification=%016lx\n",
7784 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
7785 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7786 vmcs_read32(IDT_VECTORING_INFO_FIELD),
7787 vmcs_read32(IDT_VECTORING_ERROR_CODE));
7788 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
7789 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
7790 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
7791 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
7792 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
7793 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
7794 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
7795 n = vmcs_read32(CR3_TARGET_COUNT);
7796 for (i = 0; i + 1 < n; i += 4)
7797 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7798 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
7799 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
7800 if (i < n)
7801 pr_err("CR3 target%u=%016lx\n",
7802 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
7803 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
7804 pr_err("PLE Gap=%08x Window=%08x\n",
7805 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
7806 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
7807 pr_err("Virtual processor ID = 0x%04x\n",
7808 vmcs_read16(VIRTUAL_PROCESSOR_ID));
7809}
7810
6aa8b732
AK		 7811/*
7812 * The guest has exited. See if we can fix it or if we need userspace
7813 * assistance.
7814 */
851ba692 7815static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7816{
29bd8a78 7817 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7818 u32 exit_reason = vmx->exit_reason;
1155f76a 7819 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7820
843e4330
KH		 7821 /*
7822 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7823 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7824 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7825 * mode as if vcpus is in root mode, the PML buffer must has been
7826 * flushed already.
7827 */
7828 if (enable_pml)
54bf36aa 7829 vmx_flush_pml_buffer(vcpu);
843e4330 7830
80ced186 7831 /* If guest state is invalid, start emulating */
14168786 7832 if (vmx->emulation_required)
80ced186 7833 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7834
644d711a 7835 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7836 nested_vmx_vmexit(vcpu, exit_reason,
7837 vmcs_read32(VM_EXIT_INTR_INFO),
7838 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7839 return 1;
7840 }
7841
5120702e 7842 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4eb64dce 7843 dump_vmcs();
5120702e
MG		 7844 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7845 vcpu->run->fail_entry.hardware_entry_failure_reason
7846 = exit_reason;
7847 return 0;
7848 }
7849
29bd8a78 7850 if (unlikely(vmx->fail)) {
851ba692
AK		 7851 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7852 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7853 = vmcs_read32(VM_INSTRUCTION_ERROR);
7854 return 0;
7855 }
6aa8b732 7856
b9bf6882
XG		 7857 /*
7858 * Note:
7859 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7860 * delivery event since it indicates guest is accessing MMIO.
7861 * The vm-exit can be triggered again after return to guest that
7862 * will cause infinite loop.
7863 */
d77c26fc 7864 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7865 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7866 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7867 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7868 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7869 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7870 vcpu->run->internal.ndata = 2;
7871 vcpu->run->internal.data[0] = vectoring_info;
7872 vcpu->run->internal.data[1] = exit_reason;
7873 return 0;
7874 }
3b86cd99 7875
644d711a
NHE		 7876 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7877 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7878 get_vmcs12(vcpu))))) {
c4282df9 7879 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7880 vmx->soft_vnmi_blocked = 0;
3b86cd99 7881 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7882 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7883 /*
7884 * This CPU don't support us in finding the end of an
7885 * NMI-blocked window if the guest runs with IRQs
7886 * disabled. So we pull the trigger after 1 s of
7887 * futile waiting, but inform the user about this.
7888 */
7889 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7890 "state on VCPU %d after 1 s timeout\n",
7891 __func__, vcpu->vcpu_id);
7892 vmx->soft_vnmi_blocked = 0;
3b86cd99 7893 }
3b86cd99
JK		 7894 }
7895
6aa8b732
AK		 7896 if (exit_reason < kvm_vmx_max_exit_handlers
7897 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7898 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7899 else {
2bc19dc3
MT		 7900 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7901 kvm_queue_exception(vcpu, UD_VECTOR);
7902 return 1;
6aa8b732 7903 }
6aa8b732
AK		 7904}
7905
95ba8273 7906static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7907{
a7c0b07d
WL		 7908 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7909
7910 if (is_guest_mode(vcpu) &&
7911 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7912 return;
7913
95ba8273 7914 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7915 vmcs_write32(TPR_THRESHOLD, 0);
7916 return;
7917 }
7918
95ba8273 7919 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7920}
7921
8d14695f
YZ		 7922static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7923{
7924 u32 sec_exec_control;
7925
7926 /*
7927 * There is not point to enable virtualize x2apic without enable
7928 * apicv
7929 */
c7c9c56c 7930 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
35754c98 7931 !vmx_cpu_uses_apicv(vcpu))
8d14695f
YZ		 7932 return;
7933
35754c98 7934 if (!cpu_need_tpr_shadow(vcpu))
8d14695f
YZ		 7935 return;
7936
7937 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7938
7939 if (set) {
7940 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7941 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7942 } else {
7943 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7944 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7945 }
7946 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7947
7948 vmx_set_msr_bitmap(vcpu);
7949}
7950
38b99173
TC		 7951static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7952{
7953 struct vcpu_vmx *vmx = to_vmx(vcpu);
7954
7955 /*
7956 * Currently we do not handle the nested case where L2 has an
7957 * APIC access page of its own; that page is still pinned.
7958 * Hence, we skip the case where the VCPU is in guest mode _and_
7959 * L1 prepared an APIC access page for L2.
7960 *
7961 * For the case where L1 and L2 share the same APIC access page
7962 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7963 * in the vmcs12), this function will only update either the vmcs01
7964 * or the vmcs02. If the former, the vmcs02 will be updated by
7965 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7966 * the next L2->L1 exit.
7967 */
7968 if (!is_guest_mode(vcpu) ||
7969 !nested_cpu_has2(vmx->nested.current_vmcs12,
7970 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7971 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7972}
7973
c7c9c56c
YZ		 7974static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7975{
7976 u16 status;
7977 u8 old;
7978
c7c9c56c
YZ		 7979 if (isr == -1)
7980 isr = 0;
7981
7982 status = vmcs_read16(GUEST_INTR_STATUS);
7983 old = status >> 8;
7984 if (isr != old) {
7985 status &= 0xff;
7986 status |= isr << 8;
7987 vmcs_write16(GUEST_INTR_STATUS, status);
7988 }
7989}
7990
7991static void vmx_set_rvi(int vector)
7992{
7993 u16 status;
7994 u8 old;
7995
4114c27d
WW		 7996 if (vector == -1)
7997 vector = 0;
7998
c7c9c56c
YZ		 7999 status = vmcs_read16(GUEST_INTR_STATUS);
8000 old = (u8)status & 0xff;
8001 if ((u8)vector != old) {
8002 status &= ~0xff;
8003 status |= (u8)vector;
8004 vmcs_write16(GUEST_INTR_STATUS, status);
8005 }
8006}
8007
8008static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8009{
4114c27d
WW		 8010 if (!is_guest_mode(vcpu)) {
8011 vmx_set_rvi(max_irr);
8012 return;
8013 }
8014
c7c9c56c
YZ		 8015 if (max_irr == -1)
8016 return;
8017
963fee16 8018 /*
4114c27d
WW		 8019 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8020 * handles it.
963fee16 8021 */
4114c27d 8022 if (nested_exit_on_intr(vcpu))
963fee16
WL		 8023 return;
8024
963fee16 8025 /*
4114c27d 8026 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 8027 * is run without virtual interrupt delivery.
8028 */
8029 if (!kvm_event_needs_reinjection(vcpu) &&
8030 vmx_interrupt_allowed(vcpu)) {
8031 kvm_queue_interrupt(vcpu, max_irr, false);
8032 vmx_inject_irq(vcpu);
8033 }
c7c9c56c
YZ		 8034}
8035
3bb345f3 8036static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
c7c9c56c 8037{
3bb345f3 8038 u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
35754c98 8039 if (!vmx_cpu_uses_apicv(vcpu))
3d81bc7e
YZ		 8040 return;
8041
c7c9c56c
YZ		 8042 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8043 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8044 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8045 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8046}
8047
51aa01d1 8048static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 8049{
00eba012
AK		 8050 u32 exit_intr_info;
8051
8052 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8053 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8054 return;
8055
c5ca8e57 8056 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 8057 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 8058
8059 /* Handle machine checks before interrupts are enabled */
00eba012 8060 if (is_machine_check(exit_intr_info))
a0861c02
AK		 8061 kvm_machine_check();
8062
20f65983 8063 /* We need to handle NMIs before interrupts are enabled */
00eba012 8064 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 8065 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8066 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 8067 asm("int $2");
ff9d07a0
ZY		 8068 kvm_after_handle_nmi(&vmx->vcpu);
8069 }
51aa01d1 8070}
20f65983 8071
a547c6db
YZ		 8072static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8073{
8074 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8075
8076 /*
8077 * If external interrupt exists, IF bit is set in rflags/eflags on the
8078 * interrupt stack frame, and interrupt will be enabled on a return
8079 * from interrupt handler.
8080 */
8081 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8082 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8083 unsigned int vector;
8084 unsigned long entry;
8085 gate_desc *desc;
8086 struct vcpu_vmx *vmx = to_vmx(vcpu);
8087#ifdef CONFIG_X86_64
8088 unsigned long tmp;
8089#endif
8090
8091 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8092 desc = (gate_desc *)vmx->host_idt_base + vector;
8093 entry = gate_offset(*desc);
8094 asm volatile(
8095#ifdef CONFIG_X86_64
8096 "mov %%" _ASM_SP ", %[sp]\n\t"
8097 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8098 "push $%c[ss]\n\t"
8099 "push %[sp]\n\t"
8100#endif
8101 "pushf\n\t"
8102 "orl $0x200, (%%" _ASM_SP ")\n\t"
8103 __ASM_SIZE(push) " $%c[cs]\n\t"
8104 "call *%[entry]\n\t"
8105 :
8106#ifdef CONFIG_X86_64
8107 [sp]"=&r"(tmp)
8108#endif
8109 :
8110 [entry]"r"(entry),
8111 [ss]"i"(__KERNEL_DS),
8112 [cs]"i"(__KERNEL_CS)
8113 );
8114 } else
8115 local_irq_enable();
8116}
8117
6d396b55
PB		 8118static bool vmx_has_high_real_mode_segbase(void)
8119{
8120 return enable_unrestricted_guest || emulate_invalid_guest_state;
8121}
8122
da8999d3
LJ		 8123static bool vmx_mpx_supported(void)
8124{
8125 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8126 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8127}
8128
55412b2e
WL		 8129static bool vmx_xsaves_supported(void)
8130{
8131 return vmcs_config.cpu_based_2nd_exec_ctrl &
8132 SECONDARY_EXEC_XSAVES;
8133}
8134
51aa01d1
AK		 8135static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8136{
c5ca8e57 8137 u32 exit_intr_info;
51aa01d1
AK		 8138 bool unblock_nmi;
8139 u8 vector;
8140 bool idtv_info_valid;
8141
8142 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 8143
cf393f75 8144 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 8145 if (vmx->nmi_known_unmasked)
8146 return;
c5ca8e57
AK		 8147 /*
8148 * Can't use vmx->exit_intr_info since we're not sure what
8149 * the exit reason is.
8150 */
8151 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 8152 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8153 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8154 /*
7b4a25cb 8155 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 8156 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8157 * a guest IRET fault.
7b4a25cb
GN		 8158 * SDM 3: 23.2.2 (September 2008)
8159 * Bit 12 is undefined in any of the following cases:
8160 * If the VM exit sets the valid bit in the IDT-vectoring
8161 * information field.
8162 * If the VM exit is due to a double fault.
cf393f75 8163 */
7b4a25cb
GN		 8164 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8165 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 8166 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8167 GUEST_INTR_STATE_NMI);
9d58b931
AK		 8168 else
8169 vmx->nmi_known_unmasked =
8170 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8171 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 8172 } else if (unlikely(vmx->soft_vnmi_blocked))
8173 vmx->vnmi_blocked_time +=
8174 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 8175}
8176
3ab66e8a 8177static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 8178 u32 idt_vectoring_info,
8179 int instr_len_field,
8180 int error_code_field)
51aa01d1 8181{
51aa01d1
AK		 8182 u8 vector;
8183 int type;
8184 bool idtv_info_valid;
8185
8186 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 8187
3ab66e8a
JK		 8188 vcpu->arch.nmi_injected = false;
8189 kvm_clear_exception_queue(vcpu);
8190 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 8191
8192 if (!idtv_info_valid)
8193 return;
8194
3ab66e8a 8195 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 8196
668f612f
AK		 8197 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8198 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 8199
64a7ec06 8200 switch (type) {
37b96e98 8201 case INTR_TYPE_NMI_INTR:
3ab66e8a 8202 vcpu->arch.nmi_injected = true;
668f612f 8203 /*
7b4a25cb 8204 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 8205 * Clear bit "block by NMI" before VM entry if a NMI
8206 * delivery faulted.
668f612f 8207 */
3ab66e8a 8208 vmx_set_nmi_mask(vcpu, false);
37b96e98 8209 break;
37b96e98 8210 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 8211 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 8212 /* fall through */
8213 case INTR_TYPE_HARD_EXCEPTION:
35920a35 8214 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 8215 u32 err = vmcs_read32(error_code_field);
851eb667 8216 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 8217 } else
851eb667 8218 kvm_requeue_exception(vcpu, vector);
37b96e98 8219 break;
66fd3f7f 8220 case INTR_TYPE_SOFT_INTR:
3ab66e8a 8221 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 8222 /* fall through */
37b96e98 8223 case INTR_TYPE_EXT_INTR:
3ab66e8a 8224 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 8225 break;
8226 default:
8227 break;
f7d9238f 8228 }
cf393f75
AK		 8229}
8230
83422e17
AK		 8231static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8232{
3ab66e8a 8233 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 8234 VM_EXIT_INSTRUCTION_LEN,
8235 IDT_VECTORING_ERROR_CODE);
8236}
8237
b463a6f7
AK		 8238static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8239{
3ab66e8a 8240 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 8241 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8242 VM_ENTRY_INSTRUCTION_LEN,
8243 VM_ENTRY_EXCEPTION_ERROR_CODE);
8244
8245 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8246}
8247
d7cd9796
GN		 8248static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8249{
8250 int i, nr_msrs;
8251 struct perf_guest_switch_msr *msrs;
8252
8253 msrs = perf_guest_get_msrs(&nr_msrs);
8254
8255 if (!msrs)
8256 return;
8257
8258 for (i = 0; i < nr_msrs; i++)
8259 if (msrs[i].host == msrs[i].guest)
8260 clear_atomic_switch_msr(vmx, msrs[i].msr);
8261 else
8262 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8263 msrs[i].host);
8264}
8265
a3b5ba49 8266static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 8267{
a2fa3e9f 8268 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 8269 unsigned long debugctlmsr, cr4;
104f226b
AK		 8270
8271 /* Record the guest's net vcpu time for enforced NMI injections. */
8272 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8273 vmx->entry_time = ktime_get();
8274
8275 /* Don't enter VMX if guest state is invalid, let the exit handler
8276 start emulation until we arrive back to a valid state */
14168786 8277 if (vmx->emulation_required)
104f226b
AK		 8278 return;
8279
a7653ecd
RK		 8280 if (vmx->ple_window_dirty) {
8281 vmx->ple_window_dirty = false;
8282 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8283 }
8284
012f83cb
AG		 8285 if (vmx->nested.sync_shadow_vmcs) {
8286 copy_vmcs12_to_shadow(vmx);
8287 vmx->nested.sync_shadow_vmcs = false;
8288 }
8289
104f226b
AK		 8290 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8291 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8292 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8293 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8294
1e02ce4c 8295 cr4 = cr4_read_shadow();
d974baa3
AL		 8296 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8297 vmcs_writel(HOST_CR4, cr4);
8298 vmx->host_state.vmcs_host_cr4 = cr4;
8299 }
8300
104f226b
AK		 8301 /* When single-stepping over STI and MOV SS, we must clear the
8302 * corresponding interruptibility bits in the guest state. Otherwise
8303 * vmentry fails as it then expects bit 14 (BS) in pending debug
8304 * exceptions being set, but that's not correct for the guest debugging
8305 * case. */
8306 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8307 vmx_set_interrupt_shadow(vcpu, 0);
8308
d7cd9796 8309 atomic_switch_perf_msrs(vmx);
2a7921b7 8310 debugctlmsr = get_debugctlmsr();
d7cd9796 8311
d462b819 8312 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8313 asm(
6aa8b732 8314 /* Store host registers */
b188c81f
AK		 8315 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8316 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8317 "push %%" _ASM_CX " \n\t"
8318 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8319 "je 1f \n\t"
b188c81f 8320 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8321 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8322 "1: \n\t"
d3edefc0 8323 /* Reload cr2 if changed */
b188c81f
AK		 8324 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8325 "mov %%cr2, %%" _ASM_DX " \n\t"
8326 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8327 "je 2f \n\t"
b188c81f 8328 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8329 "2: \n\t"
6aa8b732 8330 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8331 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8332 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8333 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8334 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8335 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8336 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8337 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8338 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8339#ifdef CONFIG_X86_64
e08aa78a
AK		 8340 "mov %c[r8](%0), %%r8 \n\t"
8341 "mov %c[r9](%0), %%r9 \n\t"
8342 "mov %c[r10](%0), %%r10 \n\t"
8343 "mov %c[r11](%0), %%r11 \n\t"
8344 "mov %c[r12](%0), %%r12 \n\t"
8345 "mov %c[r13](%0), %%r13 \n\t"
8346 "mov %c[r14](%0), %%r14 \n\t"
8347 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8348#endif
b188c81f 8349 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8350
6aa8b732 8351 /* Enter guest mode */
83287ea4 8352 "jne 1f \n\t"
4ecac3fd 8353 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8354 "jmp 2f \n\t"
8355 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8356 "2: "
6aa8b732 8357 /* Save guest registers, load host registers, keep flags */
b188c81f 8358 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8359 "pop %0 \n\t"
b188c81f
AK		 8360 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8361 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8362 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8363 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8364 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8365 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8366 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8367#ifdef CONFIG_X86_64
e08aa78a
AK		 8368 "mov %%r8, %c[r8](%0) \n\t"
8369 "mov %%r9, %c[r9](%0) \n\t"
8370 "mov %%r10, %c[r10](%0) \n\t"
8371 "mov %%r11, %c[r11](%0) \n\t"
8372 "mov %%r12, %c[r12](%0) \n\t"
8373 "mov %%r13, %c[r13](%0) \n\t"
8374 "mov %%r14, %c[r14](%0) \n\t"
8375 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8376#endif
b188c81f
AK		 8377 "mov %%cr2, %%" _ASM_AX " \n\t"
8378 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8379
b188c81f 8380 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8381 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8382 ".pushsection .rodata \n\t"
8383 ".global vmx_return \n\t"
8384 "vmx_return: " _ASM_PTR " 2b \n\t"
8385 ".popsection"
e08aa78a 8386 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8387 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8388 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8389 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8390 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8391 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8392 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8393 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8394 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8395 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8396 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8397#ifdef CONFIG_X86_64
ad312c7c
ZX		 8398 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8399 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8400 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8401 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8402 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8403 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8404 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8405 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8406#endif
40712fae
AK		 8407 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8408 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8409 : "cc", "memory"
8410#ifdef CONFIG_X86_64
b188c81f 8411 , "rax", "rbx", "rdi", "rsi"
c2036300 8412 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8413#else
8414 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8415#endif
8416 );
6aa8b732 8417
2a7921b7
GN		 8418 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8419 if (debugctlmsr)
8420 update_debugctlmsr(debugctlmsr);
8421
aa67f609
AK		 8422#ifndef CONFIG_X86_64
8423 /*
8424 * The sysexit path does not restore ds/es, so we must set them to
8425 * a reasonable value ourselves.
8426 *
8427 * We can't defer this to vmx_load_host_state() since that function
8428 * may be executed in interrupt context, which saves and restore segments
8429 * around it, nullifying its effect.
8430 */
8431 loadsegment(ds, __USER_DS);
8432 loadsegment(es, __USER_DS);
8433#endif
8434
6de4f3ad 8435 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8436 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8437 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8438 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8439 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8440 vcpu->arch.regs_dirty = 0;
8441
1155f76a
AK		 8442 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8443
d462b819 8444 vmx->loaded_vmcs->launched = 1;
1b6269db 8445
51aa01d1 8446 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8447 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8448
e0b890d3
GN		 8449 /*
8450 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8451 * we did not inject a still-pending event to L1 now because of
8452 * nested_run_pending, we need to re-enable this bit.
8453 */
8454 if (vmx->nested.nested_run_pending)
8455 kvm_make_request(KVM_REQ_EVENT, vcpu);
8456
8457 vmx->nested.nested_run_pending = 0;
8458
51aa01d1
AK		 8459 vmx_complete_atomic_exit(vmx);
8460 vmx_recover_nmi_blocking(vmx);
cf393f75 8461 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8462}
8463
4fa7734c
PB		 8464static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8465{
8466 struct vcpu_vmx *vmx = to_vmx(vcpu);
8467 int cpu;
8468
8469 if (vmx->loaded_vmcs == &vmx->vmcs01)
8470 return;
8471
8472 cpu = get_cpu();
8473 vmx->loaded_vmcs = &vmx->vmcs01;
8474 vmx_vcpu_put(vcpu);
8475 vmx_vcpu_load(vcpu, cpu);
8476 vcpu->cpu = cpu;
8477 put_cpu();
8478}
8479
6aa8b732
AK		 8480static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8481{
fb3f0f51
RR		 8482 struct vcpu_vmx *vmx = to_vmx(vcpu);
8483
843e4330
KH		 8484 if (enable_pml)
8485 vmx_disable_pml(vmx);
cdbecfc3 8486 free_vpid(vmx);
4fa7734c
PB		 8487 leave_guest_mode(vcpu);
8488 vmx_load_vmcs01(vcpu);
26a865f4 8489 free_nested(vmx);
4fa7734c 8490 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8491 kfree(vmx->guest_msrs);
8492 kvm_vcpu_uninit(vcpu);
a4770347 8493 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8494}
8495
fb3f0f51 8496static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8497{
fb3f0f51 8498 int err;
c16f862d 8499 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8500 int cpu;
6aa8b732 8501
a2fa3e9f 8502 if (!vmx)
fb3f0f51
RR		 8503 return ERR_PTR(-ENOMEM);
8504
2384d2b3
SY		 8505 allocate_vpid(vmx);
8506
fb3f0f51
RR		 8507 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8508 if (err)
8509 goto free_vcpu;
965b58a5 8510
a2fa3e9f 8511 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8512 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8513 > PAGE_SIZE);
0123be42 8514
be6d05cf 8515 err = -ENOMEM;
fb3f0f51 8516 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8517 goto uninit_vcpu;
8518 }
965b58a5 8519
d462b819
NHE		 8520 vmx->loaded_vmcs = &vmx->vmcs01;
8521 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8522 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8523 goto free_msrs;
d462b819
NHE		 8524 if (!vmm_exclusive)
8525 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8526 loaded_vmcs_init(vmx->loaded_vmcs);
8527 if (!vmm_exclusive)
8528 kvm_cpu_vmxoff();
a2fa3e9f 8529
15ad7146
AK		 8530 cpu = get_cpu();
8531 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8532 vmx->vcpu.cpu = cpu;
8b9cf98c 8533 err = vmx_vcpu_setup(vmx);
fb3f0f51 8534 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8535 put_cpu();
fb3f0f51
RR		 8536 if (err)
8537 goto free_vmcs;
35754c98 8538 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
be6d05cf
JK		 8539 err = alloc_apic_access_page(kvm);
8540 if (err)
5e4a0b3c 8541 goto free_vmcs;
a63cb560 8542 }
fb3f0f51 8543
b927a3ce
SY		 8544 if (enable_ept) {
8545 if (!kvm->arch.ept_identity_map_addr)
8546 kvm->arch.ept_identity_map_addr =
8547 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8548 err = init_rmode_identity_map(kvm);
8549 if (err)
93ea5388 8550 goto free_vmcs;
b927a3ce 8551 }
b7ebfb05 8552
b9c237bb
WV		 8553 if (nested)
8554 nested_vmx_setup_ctls_msrs(vmx);
8555
705699a1 8556 vmx->nested.posted_intr_nv = -1;
a9d30f33
NHE		 8557 vmx->nested.current_vmptr = -1ull;
8558 vmx->nested.current_vmcs12 = NULL;
8559
843e4330
KH		 8560 /*
8561 * If PML is turned on, failure on enabling PML just results in failure
8562 * of creating the vcpu, therefore we can simplify PML logic (by
8563 * avoiding dealing with cases, such as enabling PML partially on vcpus
8564 * for the guest, etc.
8565 */
8566 if (enable_pml) {
8567 err = vmx_enable_pml(vmx);
8568 if (err)
8569 goto free_vmcs;
8570 }
8571
fb3f0f51
RR		 8572 return &vmx->vcpu;
8573
8574free_vmcs:
5f3fbc34 8575 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8576free_msrs:
fb3f0f51
RR		 8577 kfree(vmx->guest_msrs);
8578uninit_vcpu:
8579 kvm_vcpu_uninit(&vmx->vcpu);
8580free_vcpu:
cdbecfc3 8581 free_vpid(vmx);
a4770347 8582 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8583 return ERR_PTR(err);
6aa8b732
AK		 8584}
8585
002c7f7c
YS		 8586static void __init vmx_check_processor_compat(void *rtn)
8587{
8588 struct vmcs_config vmcs_conf;
8589
8590 *(int *)rtn = 0;
8591 if (setup_vmcs_config(&vmcs_conf) < 0)
8592 *(int *)rtn = -EIO;
8593 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8594 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8595 smp_processor_id());
8596 *(int *)rtn = -EIO;
8597 }
8598}
8599
67253af5
SY		 8600static int get_ept_level(void)
8601{
8602 return VMX_EPT_DEFAULT_GAW + 1;
8603}
8604
4b12f0de 8605static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8606{
b18d5431
XG		 8607 u8 cache;
8608 u64 ipat = 0;
4b12f0de 8609
522c68c4 8610 /* For VT-d and EPT combination
606decd6 8611 * 1. MMIO: always map as UC
522c68c4
SY		 8612 * 2. EPT with VT-d:
8613 * a. VT-d without snooping control feature: can't guarantee the
606decd6 8614 * result, try to trust guest.
522c68c4
SY		 8615 * b. VT-d with snooping control feature: snooping control feature of
8616 * VT-d engine can guarantee the cache correctness. Just set it
8617 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8618 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8619 * consistent with host MTRR
8620 */
606decd6
PB		 8621 if (is_mmio) {
8622 cache = MTRR_TYPE_UNCACHABLE;
8623 goto exit;
8624 }
8625
8626 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
b18d5431
XG		 8627 ipat = VMX_EPT_IPAT_BIT;
8628 cache = MTRR_TYPE_WRBACK;
8629 goto exit;
8630 }
8631
8632 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8633 ipat = VMX_EPT_IPAT_BIT;
0da029ed 8634 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
fb279950
XG		 8635 cache = MTRR_TYPE_WRBACK;
8636 else
8637 cache = MTRR_TYPE_UNCACHABLE;
b18d5431
XG		 8638 goto exit;
8639 }
8640
ff53604b 8641 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
b18d5431
XG		 8642
8643exit:
8644 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
64d4d521
SY		 8645}
8646
17cc3935 8647static int vmx_get_lpage_level(void)
344f414f 8648{
878403b7
SY		 8649 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8650 return PT_DIRECTORY_LEVEL;
8651 else
8652 /* For shadow and EPT supported 1GB page */
8653 return PT_PDPE_LEVEL;
344f414f
JR		 8654}
8655
0e851880
SY		 8656static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8657{
4e47c7a6
SY		 8658 struct kvm_cpuid_entry2 *best;
8659 struct vcpu_vmx *vmx = to_vmx(vcpu);
8660 u32 exec_control;
8661
8662 vmx->rdtscp_enabled = false;
8663 if (vmx_rdtscp_supported()) {
8664 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8665 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8666 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8667 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8668 vmx->rdtscp_enabled = true;
8669 else {
8670 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8671 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8672 exec_control);
8673 }
8674 }
b3a2a907
JK		 8675 if (nested && !vmx->rdtscp_enabled)
8676 vmx->nested.nested_vmx_secondary_ctls_high &=
8677 ~SECONDARY_EXEC_RDTSCP;
4e47c7a6 8678 }
ad756a16 8679
ad756a16
MJ		 8680 /* Exposing INVPCID only when PCID is exposed */
8681 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8682 if (vmx_invpcid_supported() &&
4f977045 8683 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8684 guest_cpuid_has_pcid(vcpu)) {
29282fde 8685 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8686 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8687 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8688 exec_control);
8689 } else {
29282fde
TI		 8690 if (cpu_has_secondary_exec_ctrls()) {
8691 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8692 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8693 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8694 exec_control);
8695 }
ad756a16 8696 if (best)
4f977045 8697 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8698 }
0e851880
SY		 8699}
8700
d4330ef2
JR		 8701static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8702{
7b8050f5
NHE		 8703 if (func == 1 && nested)
8704 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8705}
8706
25d92081
YZ		 8707static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8708 struct x86_exception *fault)
8709{
533558bc
JK		 8710 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8711 u32 exit_reason;
25d92081
YZ		 8712
8713 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8714 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8715 else
533558bc
JK		 8716 exit_reason = EXIT_REASON_EPT_VIOLATION;
8717 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8718 vmcs12->guest_physical_address = fault->address;
8719}
8720
155a97a3
NHE		 8721/* Callbacks for nested_ept_init_mmu_context: */
8722
8723static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8724{
8725 /* return the page table to be shadowed - in our case, EPT12 */
8726 return get_vmcs12(vcpu)->ept_pointer;
8727}
8728
8a3c1a33 8729static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8730{
ad896af0
PB		 8731 WARN_ON(mmu_is_nested(vcpu));
8732 kvm_init_shadow_ept_mmu(vcpu,
b9c237bb
WV		 8733 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8734 VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8735 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8736 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8737 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8738
8739 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8740}
8741
8742static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8743{
8744 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8745}
8746
19d5f10b
EK		 8747static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8748 u16 error_code)
8749{
8750 bool inequality, bit;
8751
8752 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8753 inequality =
8754 (error_code & vmcs12->page_fault_error_code_mask) !=
8755 vmcs12->page_fault_error_code_match;
8756 return inequality ^ bit;
8757}
8758
feaf0c7d
GN		 8759static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8760 struct x86_exception *fault)
8761{
8762 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8763
8764 WARN_ON(!is_guest_mode(vcpu));
8765
19d5f10b 8766 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8767 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8768 vmcs_read32(VM_EXIT_INTR_INFO),
8769 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8770 else
8771 kvm_inject_page_fault(vcpu, fault);
8772}
8773
a2bcba50
WL		 8774static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8775 struct vmcs12 *vmcs12)
8776{
8777 struct vcpu_vmx *vmx = to_vmx(vcpu);
9090422f 8778 int maxphyaddr = cpuid_maxphyaddr(vcpu);
a2bcba50
WL		 8779
8780 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9090422f
EK		 8781 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
8782 vmcs12->apic_access_addr >> maxphyaddr)
a2bcba50
WL		 8783 return false;
8784
8785 /*
8786 * Translate L1 physical address to host physical
8787 * address for vmcs02. Keep the page pinned, so this
8788 * physical address remains valid. We keep a reference
8789 * to it so we can release it later.
8790 */
8791 if (vmx->nested.apic_access_page) /* shouldn't happen */
8792 nested_release_page(vmx->nested.apic_access_page);
8793 vmx->nested.apic_access_page =
8794 nested_get_page(vcpu, vmcs12->apic_access_addr);
8795 }
a7c0b07d
WL		 8796
8797 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9090422f
EK		 8798 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
8799 vmcs12->virtual_apic_page_addr >> maxphyaddr)
a7c0b07d
WL		 8800 return false;
8801
8802 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8803 nested_release_page(vmx->nested.virtual_apic_page);
8804 vmx->nested.virtual_apic_page =
8805 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8806
8807 /*
8808 * Failing the vm entry is _not_ what the processor does
8809 * but it's basically the only possibility we have.
8810 * We could still enter the guest if CR8 load exits are
8811 * enabled, CR8 store exits are enabled, and virtualize APIC
8812 * access is disabled; in this case the processor would never
8813 * use the TPR shadow and we could simply clear the bit from
8814 * the execution control. But such a configuration is useless,
8815 * so let's keep the code simple.
8816 */
8817 if (!vmx->nested.virtual_apic_page)
8818 return false;
8819 }
8820
705699a1 8821 if (nested_cpu_has_posted_intr(vmcs12)) {
9090422f
EK		 8822 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
8823 vmcs12->posted_intr_desc_addr >> maxphyaddr)
705699a1
WV		 8824 return false;
8825
8826 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
8827 kunmap(vmx->nested.pi_desc_page);
8828 nested_release_page(vmx->nested.pi_desc_page);
8829 }
8830 vmx->nested.pi_desc_page =
8831 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
8832 if (!vmx->nested.pi_desc_page)
8833 return false;
8834
8835 vmx->nested.pi_desc =
8836 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
8837 if (!vmx->nested.pi_desc) {
8838 nested_release_page_clean(vmx->nested.pi_desc_page);
8839 return false;
8840 }
8841 vmx->nested.pi_desc =
8842 (struct pi_desc *)((void *)vmx->nested.pi_desc +
8843 (unsigned long)(vmcs12->posted_intr_desc_addr &
8844 (PAGE_SIZE - 1)));
8845 }
8846
a2bcba50
WL		 8847 return true;
8848}
8849
f4124500
JK		 8850static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8851{
8852 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8853 struct vcpu_vmx *vmx = to_vmx(vcpu);
8854
8855 if (vcpu->arch.virtual_tsc_khz == 0)
8856 return;
8857
8858 /* Make sure short timeouts reliably trigger an immediate vmexit.
8859 * hrtimer_start does not guarantee this. */
8860 if (preemption_timeout <= 1) {
8861 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8862 return;
8863 }
8864
8865 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8866 preemption_timeout *= 1000000;
8867 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8868 hrtimer_start(&vmx->nested.preemption_timer,
8869 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8870}
8871
3af18d9c
WV		 8872static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8873 struct vmcs12 *vmcs12)
8874{
8875 int maxphyaddr;
8876 u64 addr;
8877
8878 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8879 return 0;
8880
8881 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8882 WARN_ON(1);
8883 return -EINVAL;
8884 }
8885 maxphyaddr = cpuid_maxphyaddr(vcpu);
8886
8887 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8888 ((addr + PAGE_SIZE) >> maxphyaddr))
8889 return -EINVAL;
8890
8891 return 0;
8892}
8893
8894/*
8895 * Merge L0's and L1's MSR bitmap, return false to indicate that
8896 * we do not use the hardware.
8897 */
8898static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8899 struct vmcs12 *vmcs12)
8900{
82f0dd4b 8901 int msr;
f2b93280
WV		 8902 struct page *page;
8903 unsigned long *msr_bitmap;
8904
8905 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8906 return false;
8907
8908 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8909 if (!page) {
8910 WARN_ON(1);
8911 return false;
8912 }
8913 msr_bitmap = (unsigned long *)kmap(page);
8914 if (!msr_bitmap) {
8915 nested_release_page_clean(page);
8916 WARN_ON(1);
8917 return false;
8918 }
8919
8920 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
82f0dd4b
WV		 8921 if (nested_cpu_has_apic_reg_virt(vmcs12))
8922 for (msr = 0x800; msr <= 0x8ff; msr++)
8923 nested_vmx_disable_intercept_for_msr(
8924 msr_bitmap,
8925 vmx_msr_bitmap_nested,
8926 msr, MSR_TYPE_R);
f2b93280
WV		 8927 /* TPR is allowed */
8928 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8929 vmx_msr_bitmap_nested,
8930 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8931 MSR_TYPE_R | MSR_TYPE_W);
608406e2
WV		 8932 if (nested_cpu_has_vid(vmcs12)) {
8933 /* EOI and self-IPI are allowed */
8934 nested_vmx_disable_intercept_for_msr(
8935 msr_bitmap,
8936 vmx_msr_bitmap_nested,
8937 APIC_BASE_MSR + (APIC_EOI >> 4),
8938 MSR_TYPE_W);
8939 nested_vmx_disable_intercept_for_msr(
8940 msr_bitmap,
8941 vmx_msr_bitmap_nested,
8942 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8943 MSR_TYPE_W);
8944 }
82f0dd4b
WV		 8945 } else {
8946 /*
8947 * Enable reading intercept of all the x2apic
8948 * MSRs. We should not rely on vmcs12 to do any
8949 * optimizations here, it may have been modified
8950 * by L1.
8951 */
8952 for (msr = 0x800; msr <= 0x8ff; msr++)
8953 __vmx_enable_intercept_for_msr(
8954 vmx_msr_bitmap_nested,
8955 msr,
8956 MSR_TYPE_R);
8957
f2b93280
WV		 8958 __vmx_enable_intercept_for_msr(
8959 vmx_msr_bitmap_nested,
8960 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
82f0dd4b 8961 MSR_TYPE_W);
608406e2
WV		 8962 __vmx_enable_intercept_for_msr(
8963 vmx_msr_bitmap_nested,
8964 APIC_BASE_MSR + (APIC_EOI >> 4),
8965 MSR_TYPE_W);
8966 __vmx_enable_intercept_for_msr(
8967 vmx_msr_bitmap_nested,
8968 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
8969 MSR_TYPE_W);
82f0dd4b 8970 }
f2b93280
WV		 8971 kunmap(page);
8972 nested_release_page_clean(page);
8973
8974 return true;
8975}
8976
8977static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8978 struct vmcs12 *vmcs12)
8979{
82f0dd4b 8980 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
608406e2 8981 !nested_cpu_has_apic_reg_virt(vmcs12) &&
705699a1
WV		 8982 !nested_cpu_has_vid(vmcs12) &&
8983 !nested_cpu_has_posted_intr(vmcs12))
f2b93280
WV		 8984 return 0;
8985
8986 /*
8987 * If virtualize x2apic mode is enabled,
8988 * virtualize apic access must be disabled.
8989 */
82f0dd4b
WV		 8990 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
8991 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
f2b93280
WV		 8992 return -EINVAL;
8993
608406e2
WV		 8994 /*
8995 * If virtual interrupt delivery is enabled,
8996 * we must exit on external interrupts.
8997 */
8998 if (nested_cpu_has_vid(vmcs12) &&
8999 !nested_exit_on_intr(vcpu))
9000 return -EINVAL;
9001
705699a1
WV		 9002 /*
9003 * bits 15:8 should be zero in posted_intr_nv,
9004 * the descriptor address has been already checked
9005 * in nested_get_vmcs12_pages.
9006 */
9007 if (nested_cpu_has_posted_intr(vmcs12) &&
9008 (!nested_cpu_has_vid(vmcs12) ||
9009 !nested_exit_intr_ack_set(vcpu) ||
9010 vmcs12->posted_intr_nv & 0xff00))
9011 return -EINVAL;
9012
f2b93280
WV		 9013 /* tpr shadow is needed by all apicv features. */
9014 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9015 return -EINVAL;
9016
9017 return 0;
3af18d9c
WV		 9018}
9019
e9ac033e
EK		 9020static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9021 unsigned long count_field,
92d71bc6 9022 unsigned long addr_field)
ff651cb6 9023{
92d71bc6 9024 int maxphyaddr;
e9ac033e
EK		 9025 u64 count, addr;
9026
9027 if (vmcs12_read_any(vcpu, count_field, &count) ||
9028 vmcs12_read_any(vcpu, addr_field, &addr)) {
9029 WARN_ON(1);
9030 return -EINVAL;
9031 }
9032 if (count == 0)
9033 return 0;
92d71bc6 9034 maxphyaddr = cpuid_maxphyaddr(vcpu);
e9ac033e
EK		 9035 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9036 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9037 pr_warn_ratelimited(
9038 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9039 addr_field, maxphyaddr, count, addr);
9040 return -EINVAL;
9041 }
9042 return 0;
9043}
9044
9045static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9046 struct vmcs12 *vmcs12)
9047{
e9ac033e
EK		 9048 if (vmcs12->vm_exit_msr_load_count == 0 &&
9049 vmcs12->vm_exit_msr_store_count == 0 &&
9050 vmcs12->vm_entry_msr_load_count == 0)
9051 return 0; /* Fast path */
e9ac033e 9052 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
92d71bc6 9053 VM_EXIT_MSR_LOAD_ADDR) ||
e9ac033e 9054 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
92d71bc6 9055 VM_EXIT_MSR_STORE_ADDR) ||
e9ac033e 9056 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
92d71bc6 9057 VM_ENTRY_MSR_LOAD_ADDR))
e9ac033e
EK		 9058 return -EINVAL;
9059 return 0;
9060}
9061
9062static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9063 struct vmx_msr_entry *e)
9064{
9065 /* x2APIC MSR accesses are not allowed */
8a9781f7 9066 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
e9ac033e
EK		 9067 return -EINVAL;
9068 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9069 e->index == MSR_IA32_UCODE_REV)
9070 return -EINVAL;
9071 if (e->reserved != 0)
ff651cb6
WV		 9072 return -EINVAL;
9073 return 0;
9074}
9075
e9ac033e
EK		 9076static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9077 struct vmx_msr_entry *e)
ff651cb6
WV		 9078{
9079 if (e->index == MSR_FS_BASE ||
9080 e->index == MSR_GS_BASE ||
e9ac033e
EK		 9081 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9082 nested_vmx_msr_check_common(vcpu, e))
9083 return -EINVAL;
9084 return 0;
9085}
9086
9087static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9088 struct vmx_msr_entry *e)
9089{
9090 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9091 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 9092 return -EINVAL;
9093 return 0;
9094}
9095
9096/*
9097 * Load guest's/host's msr at nested entry/exit.
9098 * return 0 for success, entry index for failure.
9099 */
9100static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9101{
9102 u32 i;
9103 struct vmx_msr_entry e;
9104 struct msr_data msr;
9105
9106 msr.host_initiated = false;
9107 for (i = 0; i < count; i++) {
54bf36aa
PB		 9108 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9109 &e, sizeof(e))) {
e9ac033e
EK		 9110 pr_warn_ratelimited(
9111 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9112 __func__, i, gpa + i * sizeof(e));
ff651cb6 9113 goto fail;
e9ac033e
EK		 9114 }
9115 if (nested_vmx_load_msr_check(vcpu, &e)) {
9116 pr_warn_ratelimited(
9117 "%s check failed (%u, 0x%x, 0x%x)\n",
9118 __func__, i, e.index, e.reserved);
9119 goto fail;
9120 }
ff651cb6
WV		 9121 msr.index = e.index;
9122 msr.data = e.value;
e9ac033e
EK		 9123 if (kvm_set_msr(vcpu, &msr)) {
9124 pr_warn_ratelimited(
9125 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9126 __func__, i, e.index, e.value);
ff651cb6 9127 goto fail;
e9ac033e 9128 }
ff651cb6
WV		 9129 }
9130 return 0;
9131fail:
9132 return i + 1;
9133}
9134
9135static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9136{
9137 u32 i;
9138 struct vmx_msr_entry e;
9139
9140 for (i = 0; i < count; i++) {
609e36d3 9141 struct msr_data msr_info;
54bf36aa
PB		 9142 if (kvm_vcpu_read_guest(vcpu,
9143 gpa + i * sizeof(e),
9144 &e, 2 * sizeof(u32))) {
e9ac033e
EK		 9145 pr_warn_ratelimited(
9146 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9147 __func__, i, gpa + i * sizeof(e));
ff651cb6 9148 return -EINVAL;
e9ac033e
EK		 9149 }
9150 if (nested_vmx_store_msr_check(vcpu, &e)) {
9151 pr_warn_ratelimited(
9152 "%s check failed (%u, 0x%x, 0x%x)\n",
9153 __func__, i, e.index, e.reserved);
ff651cb6 9154 return -EINVAL;
e9ac033e 9155 }
609e36d3
PB		 9156 msr_info.host_initiated = false;
9157 msr_info.index = e.index;
9158 if (kvm_get_msr(vcpu, &msr_info)) {
e9ac033e
EK		 9159 pr_warn_ratelimited(
9160 "%s cannot read MSR (%u, 0x%x)\n",
9161 __func__, i, e.index);
9162 return -EINVAL;
9163 }
54bf36aa
PB		 9164 if (kvm_vcpu_write_guest(vcpu,
9165 gpa + i * sizeof(e) +
9166 offsetof(struct vmx_msr_entry, value),
9167 &msr_info.data, sizeof(msr_info.data))) {
e9ac033e
EK		 9168 pr_warn_ratelimited(
9169 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
609e36d3 9170 __func__, i, e.index, msr_info.data);
e9ac033e
EK		 9171 return -EINVAL;
9172 }
ff651cb6
WV		 9173 }
9174 return 0;
9175}
9176
fe3ef05c
NHE		 9177/*
9178 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9179 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 9180 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 9181 * guest in a way that will both be appropriate to L1's requests, and our
9182 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9183 * function also has additional necessary side-effects, like setting various
9184 * vcpu->arch fields.
9185 */
9186static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9187{
9188 struct vcpu_vmx *vmx = to_vmx(vcpu);
9189 u32 exec_control;
9190
9191 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9192 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9193 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9194 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9195 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9196 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9197 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9198 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9199 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9200 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9201 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9202 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9203 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9204 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9205 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9206 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9207 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9208 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9209 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9210 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9211 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9212 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9213 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9214 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9215 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9216 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9217 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9218 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9219 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9220 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9221 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9222 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9223 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9224 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9225 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9226 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9227
2996fca0
JK		 9228 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9229 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9230 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9231 } else {
9232 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9233 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9234 }
fe3ef05c
NHE		 9235 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9236 vmcs12->vm_entry_intr_info_field);
9237 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9238 vmcs12->vm_entry_exception_error_code);
9239 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9240 vmcs12->vm_entry_instruction_len);
9241 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9242 vmcs12->guest_interruptibility_info);
fe3ef05c 9243 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 9244 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 9245 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9246 vmcs12->guest_pending_dbg_exceptions);
9247 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9248 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9249
81dc01f7
WL		 9250 if (nested_cpu_has_xsaves(vmcs12))
9251 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 9252 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9253
f4124500
JK		 9254 exec_control = vmcs12->pin_based_vm_exec_control;
9255 exec_control |= vmcs_config.pin_based_exec_ctrl;
705699a1
WV		 9256 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9257
9258 if (nested_cpu_has_posted_intr(vmcs12)) {
9259 /*
9260 * Note that we use L0's vector here and in
9261 * vmx_deliver_nested_posted_interrupt.
9262 */
9263 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9264 vmx->nested.pi_pending = false;
9265 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9266 vmcs_write64(POSTED_INTR_DESC_ADDR,
9267 page_to_phys(vmx->nested.pi_desc_page) +
9268 (unsigned long)(vmcs12->posted_intr_desc_addr &
9269 (PAGE_SIZE - 1)));
9270 } else
9271 exec_control &= ~PIN_BASED_POSTED_INTR;
9272
f4124500 9273 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 9274
f4124500
JK		 9275 vmx->nested.preemption_timer_expired = false;
9276 if (nested_cpu_has_preemption_timer(vmcs12))
9277 vmx_start_preemption_timer(vcpu);
0238ea91 9278
fe3ef05c
NHE		 9279 /*
9280 * Whether page-faults are trapped is determined by a combination of
9281 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9282 * If enable_ept, L0 doesn't care about page faults and we should
9283 * set all of these to L1's desires. However, if !enable_ept, L0 does
9284 * care about (at least some) page faults, and because it is not easy
9285 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9286 * to exit on each and every L2 page fault. This is done by setting
9287 * MASK=MATCH=0 and (see below) EB.PF=1.
9288 * Note that below we don't need special code to set EB.PF beyond the
9289 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9290 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9291 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9292 *
9293 * A problem with this approach (when !enable_ept) is that L1 may be
9294 * injected with more page faults than it asked for. This could have
9295 * caused problems, but in practice existing hypervisors don't care.
9296 * To fix this, we will need to emulate the PFEC checking (on the L1
9297 * page tables), using walk_addr(), when injecting PFs to L1.
9298 */
9299 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9300 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9301 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9302 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9303
9304 if (cpu_has_secondary_exec_ctrls()) {
f4124500 9305 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 9306 if (!vmx->rdtscp_enabled)
9307 exec_control &= ~SECONDARY_EXEC_RDTSCP;
9308 /* Take the following fields only from vmcs12 */
696dfd95 9309 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
b3a2a907 9310 SECONDARY_EXEC_RDTSCP |
696dfd95 9311 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
b3a2a907 9312 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 9313 if (nested_cpu_has(vmcs12,
9314 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9315 exec_control |= vmcs12->secondary_vm_exec_control;
9316
9317 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 9318 /*
9319 * If translation failed, no matter: This feature asks
9320 * to exit when accessing the given address, and if it
9321 * can never be accessed, this feature won't do
9322 * anything anyway.
9323 */
9324 if (!vmx->nested.apic_access_page)
9325 exec_control &=
9326 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9327 else
9328 vmcs_write64(APIC_ACCESS_ADDR,
9329 page_to_phys(vmx->nested.apic_access_page));
f2b93280 9330 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
35754c98 9331 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
ca3f257a
JK		 9332 exec_control |=
9333 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 9334 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 9335 }
9336
608406e2
WV		 9337 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9338 vmcs_write64(EOI_EXIT_BITMAP0,
9339 vmcs12->eoi_exit_bitmap0);
9340 vmcs_write64(EOI_EXIT_BITMAP1,
9341 vmcs12->eoi_exit_bitmap1);
9342 vmcs_write64(EOI_EXIT_BITMAP2,
9343 vmcs12->eoi_exit_bitmap2);
9344 vmcs_write64(EOI_EXIT_BITMAP3,
9345 vmcs12->eoi_exit_bitmap3);
9346 vmcs_write16(GUEST_INTR_STATUS,
9347 vmcs12->guest_intr_status);
9348 }
9349
fe3ef05c
NHE		 9350 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9351 }
9352
9353
9354 /*
9355 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9356 * Some constant fields are set here by vmx_set_constant_host_state().
9357 * Other fields are different per CPU, and will be set later when
9358 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9359 */
a547c6db 9360 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 9361
9362 /*
9363 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9364 * entry, but only if the current (host) sp changed from the value
9365 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9366 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9367 * here we just force the write to happen on entry.
9368 */
9369 vmx->host_rsp = 0;
9370
9371 exec_control = vmx_exec_control(vmx); /* L0's desires */
9372 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9373 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9374 exec_control &= ~CPU_BASED_TPR_SHADOW;
9375 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 9376
9377 if (exec_control & CPU_BASED_TPR_SHADOW) {
9378 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9379 page_to_phys(vmx->nested.virtual_apic_page));
9380 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9381 }
9382
3af18d9c 9383 if (cpu_has_vmx_msr_bitmap() &&
670125bd
WV		 9384 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9385 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9386 /* MSR_BITMAP will be set by following vmx_set_efer. */
3af18d9c
WV		 9387 } else
9388 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9389
fe3ef05c 9390 /*
3af18d9c 9391 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 9392 * Rather, exit every time.
9393 */
fe3ef05c
NHE		 9394 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9395 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9396
9397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9398
9399 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9400 * bitwise-or of what L1 wants to trap for L2, and what we want to
9401 * trap. Note that CR0.TS also needs updating - we do this later.
9402 */
9403 update_exception_bitmap(vcpu);
9404 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9405 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9406
8049d651
NHE		 9407 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9408 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9409 * bits are further modified by vmx_set_efer() below.
9410 */
f4124500 9411 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 9412
9413 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9414 * emulated by vmx_set_efer(), below.
9415 */
2961e876 9416 vm_entry_controls_init(vmx,
8049d651
NHE		 9417 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9418 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 9419 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9420
44811c02 9421 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 9422 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 9423 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9424 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 9425 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9426
9427
9428 set_cr4_guest_host_mask(vmx);
9429
36be0b9d
PB		 9430 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9431 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9432
27fc51b2
NHE		 9433 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9434 vmcs_write64(TSC_OFFSET,
9435 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9436 else
9437 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 9438
9439 if (enable_vpid) {
9440 /*
9441 * Trivially support vpid by letting L2s share their parent
9442 * L1's vpid. TODO: move to a more elaborate solution, giving
9443 * each L2 its own vpid and exposing the vpid feature to L1.
9444 */
9445 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9446 vmx_flush_tlb(vcpu);
9447 }
9448
155a97a3
NHE		 9449 if (nested_cpu_has_ept(vmcs12)) {
9450 kvm_mmu_unload(vcpu);
9451 nested_ept_init_mmu_context(vcpu);
9452 }
9453
fe3ef05c
NHE		 9454 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9455 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9456 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9457 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9458 else
9459 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9460 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9461 vmx_set_efer(vcpu, vcpu->arch.efer);
9462
9463 /*
9464 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9465 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9466 * The CR0_READ_SHADOW is what L2 should have expected to read given
9467 * the specifications by L1; It's not enough to take
9468 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9469 * have more bits than L1 expected.
9470 */
9471 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9472 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9473
9474 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9475 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9476
9477 /* shadow page tables on either EPT or shadow page tables */
9478 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9479 kvm_mmu_reset_context(vcpu);
9480
feaf0c7d
GN		 9481 if (!enable_ept)
9482 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9483
3633cfc3
NHE		 9484 /*
9485 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9486 */
9487 if (enable_ept) {
9488 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9489 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9490 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9491 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9492 }
9493
fe3ef05c
NHE		 9494 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9495 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9496}
9497
cd232ad0
NHE		 9498/*
9499 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9500 * for running an L2 nested guest.
9501 */
9502static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9503{
9504 struct vmcs12 *vmcs12;
9505 struct vcpu_vmx *vmx = to_vmx(vcpu);
9506 int cpu;
9507 struct loaded_vmcs *vmcs02;
384bb783 9508 bool ia32e;
ff651cb6 9509 u32 msr_entry_idx;
cd232ad0
NHE		 9510
9511 if (!nested_vmx_check_permission(vcpu) ||
9512 !nested_vmx_check_vmcs12(vcpu))
9513 return 1;
9514
9515 skip_emulated_instruction(vcpu);
9516 vmcs12 = get_vmcs12(vcpu);
9517
012f83cb
AG		 9518 if (enable_shadow_vmcs)
9519 copy_shadow_to_vmcs12(vmx);
9520
7c177938
NHE		 9521 /*
9522 * The nested entry process starts with enforcing various prerequisites
9523 * on vmcs12 as required by the Intel SDM, and act appropriately when
9524 * they fail: As the SDM explains, some conditions should cause the
9525 * instruction to fail, while others will cause the instruction to seem
9526 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9527 * To speed up the normal (success) code path, we should avoid checking
9528 * for misconfigurations which will anyway be caught by the processor
9529 * when using the merged vmcs02.
9530 */
9531 if (vmcs12->launch_state == launch) {
9532 nested_vmx_failValid(vcpu,
9533 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9534 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9535 return 1;
9536 }
9537
6dfacadd
JK		 9538 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9539 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9540 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9541 return 1;
9542 }
9543
3af18d9c 9544 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9545 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9546 return 1;
9547 }
9548
3af18d9c 9549 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9550 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9551 return 1;
9552 }
9553
f2b93280
WV		 9554 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9555 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9556 return 1;
9557 }
9558
e9ac033e
EK		 9559 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9560 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9561 return 1;
9562 }
9563
7c177938 9564 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
b9c237bb
WV		 9565 vmx->nested.nested_vmx_true_procbased_ctls_low,
9566 vmx->nested.nested_vmx_procbased_ctls_high) ||
7c177938 9567 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
b9c237bb
WV		 9568 vmx->nested.nested_vmx_secondary_ctls_low,
9569 vmx->nested.nested_vmx_secondary_ctls_high) ||
7c177938 9570 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
b9c237bb
WV		 9571 vmx->nested.nested_vmx_pinbased_ctls_low,
9572 vmx->nested.nested_vmx_pinbased_ctls_high) ||
7c177938 9573 !vmx_control_verify(vmcs12->vm_exit_controls,
b9c237bb
WV		 9574 vmx->nested.nested_vmx_true_exit_ctls_low,
9575 vmx->nested.nested_vmx_exit_ctls_high) ||
7c177938 9576 !vmx_control_verify(vmcs12->vm_entry_controls,
b9c237bb
WV		 9577 vmx->nested.nested_vmx_true_entry_ctls_low,
9578 vmx->nested.nested_vmx_entry_ctls_high))
7c177938
NHE		 9579 {
9580 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9581 return 1;
9582 }
9583
9584 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9585 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9586 nested_vmx_failValid(vcpu,
9587 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9588 return 1;
9589 }
9590
b9c237bb 9591 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
7c177938
NHE		 9592 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9593 nested_vmx_entry_failure(vcpu, vmcs12,
9594 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9595 return 1;
9596 }
9597 if (vmcs12->vmcs_link_pointer != -1ull) {
9598 nested_vmx_entry_failure(vcpu, vmcs12,
9599 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9600 return 1;
9601 }
9602
384bb783 9603 /*
cb0c8cda 9604 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9605 * are performed on the field for the IA32_EFER MSR:
9606 * - Bits reserved in the IA32_EFER MSR must be 0.
9607 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9608 * the IA-32e mode guest VM-exit control. It must also be identical
9609 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9610 * CR0.PG) is 1.
9611 */
9612 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9613 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9614 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9615 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9616 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9617 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9618 nested_vmx_entry_failure(vcpu, vmcs12,
9619 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9620 return 1;
9621 }
9622 }
9623
9624 /*
9625 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9626 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9627 * the values of the LMA and LME bits in the field must each be that of
9628 * the host address-space size VM-exit control.
9629 */
9630 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9631 ia32e = (vmcs12->vm_exit_controls &
9632 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9633 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9634 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9635 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9636 nested_vmx_entry_failure(vcpu, vmcs12,
9637 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9638 return 1;
9639 }
9640 }
9641
7c177938
NHE		 9642 /*
9643 * We're finally done with prerequisite checking, and can start with
9644 * the nested entry.
9645 */
9646
cd232ad0
NHE		 9647 vmcs02 = nested_get_current_vmcs02(vmx);
9648 if (!vmcs02)
9649 return -ENOMEM;
9650
9651 enter_guest_mode(vcpu);
9652
9653 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9654
2996fca0
JK		 9655 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9656 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9657
cd232ad0
NHE		 9658 cpu = get_cpu();
9659 vmx->loaded_vmcs = vmcs02;
9660 vmx_vcpu_put(vcpu);
9661 vmx_vcpu_load(vcpu, cpu);
9662 vcpu->cpu = cpu;
9663 put_cpu();
9664
36c3cc42
JK		 9665 vmx_segment_cache_clear(vmx);
9666
cd232ad0
NHE		 9667 prepare_vmcs02(vcpu, vmcs12);
9668
ff651cb6
WV		 9669 msr_entry_idx = nested_vmx_load_msr(vcpu,
9670 vmcs12->vm_entry_msr_load_addr,
9671 vmcs12->vm_entry_msr_load_count);
9672 if (msr_entry_idx) {
9673 leave_guest_mode(vcpu);
9674 vmx_load_vmcs01(vcpu);
9675 nested_vmx_entry_failure(vcpu, vmcs12,
9676 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9677 return 1;
9678 }
9679
9680 vmcs12->launch_state = 1;
9681
6dfacadd 9682 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
5cb56059 9683 return kvm_vcpu_halt(vcpu);
6dfacadd 9684
7af40ad3
JK		 9685 vmx->nested.nested_run_pending = 1;
9686
cd232ad0
NHE		 9687 /*
9688 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9689 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9690 * returned as far as L1 is concerned. It will only return (and set
9691 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9692 */
9693 return 1;
9694}
9695
4704d0be
NHE		 9696/*
9697 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9698 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9699 * This function returns the new value we should put in vmcs12.guest_cr0.
9700 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9701 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9702 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9703 * didn't trap the bit, because if L1 did, so would L0).
9704 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9705 * been modified by L2, and L1 knows it. So just leave the old value of
9706 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9707 * isn't relevant, because if L0 traps this bit it can set it to anything.
9708 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9709 * changed these bits, and therefore they need to be updated, but L0
9710 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9711 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9712 */
9713static inline unsigned long
9714vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9715{
9716 return
9717 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9718 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9719 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9720 vcpu->arch.cr0_guest_owned_bits));
9721}
9722
9723static inline unsigned long
9724vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9725{
9726 return
9727 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9728 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9729 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9730 vcpu->arch.cr4_guest_owned_bits));
9731}
9732
5f3d5799
JK		 9733static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9734 struct vmcs12 *vmcs12)
9735{
9736 u32 idt_vectoring;
9737 unsigned int nr;
9738
851eb667 9739 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9740 nr = vcpu->arch.exception.nr;
9741 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9742
9743 if (kvm_exception_is_soft(nr)) {
9744 vmcs12->vm_exit_instruction_len =
9745 vcpu->arch.event_exit_inst_len;
9746 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9747 } else
9748 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9749
9750 if (vcpu->arch.exception.has_error_code) {
9751 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9752 vmcs12->idt_vectoring_error_code =
9753 vcpu->arch.exception.error_code;
9754 }
9755
9756 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9757 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9758 vmcs12->idt_vectoring_info_field =
9759 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9760 } else if (vcpu->arch.interrupt.pending) {
9761 nr = vcpu->arch.interrupt.nr;
9762 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9763
9764 if (vcpu->arch.interrupt.soft) {
9765 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9766 vmcs12->vm_entry_instruction_len =
9767 vcpu->arch.event_exit_inst_len;
9768 } else
9769 idt_vectoring |= INTR_TYPE_EXT_INTR;
9770
9771 vmcs12->idt_vectoring_info_field = idt_vectoring;
9772 }
9773}
9774
b6b8a145
JK		 9775static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9776{
9777 struct vcpu_vmx *vmx = to_vmx(vcpu);
9778
f4124500
JK		 9779 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9780 vmx->nested.preemption_timer_expired) {
9781 if (vmx->nested.nested_run_pending)
9782 return -EBUSY;
9783 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9784 return 0;
9785 }
9786
b6b8a145 9787 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9788 if (vmx->nested.nested_run_pending ||
9789 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9790 return -EBUSY;
9791 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9792 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9793 INTR_INFO_VALID_MASK, 0);
9794 /*
9795 * The NMI-triggered VM exit counts as injection:
9796 * clear this one and block further NMIs.
9797 */
9798 vcpu->arch.nmi_pending = 0;
9799 vmx_set_nmi_mask(vcpu, true);
9800 return 0;
9801 }
9802
9803 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9804 nested_exit_on_intr(vcpu)) {
9805 if (vmx->nested.nested_run_pending)
9806 return -EBUSY;
9807 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
705699a1 9808 return 0;
b6b8a145
JK		 9809 }
9810
705699a1 9811 return vmx_complete_nested_posted_interrupt(vcpu);
b6b8a145
JK		 9812}
9813
f4124500
JK		 9814static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9815{
9816 ktime_t remaining =
9817 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9818 u64 value;
9819
9820 if (ktime_to_ns(remaining) <= 0)
9821 return 0;
9822
9823 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9824 do_div(value, 1000000);
9825 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9826}
9827
4704d0be
NHE		 9828/*
9829 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9830 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9831 * and this function updates it to reflect the changes to the guest state while
9832 * L2 was running (and perhaps made some exits which were handled directly by L0
9833 * without going back to L1), and to reflect the exit reason.
9834 * Note that we do not have to copy here all VMCS fields, just those that
9835 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9836 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9837 * which already writes to vmcs12 directly.
9838 */
533558bc
JK		 9839static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9840 u32 exit_reason, u32 exit_intr_info,
9841 unsigned long exit_qualification)
4704d0be
NHE		 9842{
9843 /* update guest state fields: */
9844 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9845 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9846
4704d0be
NHE		 9847 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9848 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9849 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9850
9851 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9852 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9853 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9854 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9855 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9856 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9857 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9858 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9859 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9860 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9861 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9862 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9863 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9864 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9865 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9866 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9867 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9868 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9869 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9870 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9871 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9872 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9873 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9874 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9875 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9876 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9877 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9878 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9879 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9880 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9881 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9882 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9883 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9884 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9885 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9886 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9887
4704d0be
NHE		 9888 vmcs12->guest_interruptibility_info =
9889 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9890 vmcs12->guest_pending_dbg_exceptions =
9891 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9892 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9893 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9894 else
9895 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9896
f4124500
JK		 9897 if (nested_cpu_has_preemption_timer(vmcs12)) {
9898 if (vmcs12->vm_exit_controls &
9899 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9900 vmcs12->vmx_preemption_timer_value =
9901 vmx_get_preemption_timer_value(vcpu);
9902 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9903 }
7854cbca 9904
3633cfc3
NHE		 9905 /*
9906 * In some cases (usually, nested EPT), L2 is allowed to change its
9907 * own CR3 without exiting. If it has changed it, we must keep it.
9908 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9909 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9910 *
9911 * Additionally, restore L2's PDPTR to vmcs12.
9912 */
9913 if (enable_ept) {
9914 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9915 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9916 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9917 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9918 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9919 }
9920
608406e2
WV		 9921 if (nested_cpu_has_vid(vmcs12))
9922 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
9923
c18911a2
JK		 9924 vmcs12->vm_entry_controls =
9925 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9926 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9927
2996fca0
JK		 9928 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9929 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9930 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9931 }
9932
4704d0be
NHE		 9933 /* TODO: These cannot have changed unless we have MSR bitmaps and
9934 * the relevant bit asks not to trap the change */
b8c07d55 9935 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9936 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9937 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9938 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9939 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9940 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9941 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9942 if (vmx_mpx_supported())
9943 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9944 if (nested_cpu_has_xsaves(vmcs12))
9945 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9946
9947 /* update exit information fields: */
9948
533558bc
JK		 9949 vmcs12->vm_exit_reason = exit_reason;
9950 vmcs12->exit_qualification = exit_qualification;
4704d0be 9951
533558bc 9952 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9953 if ((vmcs12->vm_exit_intr_info &
9954 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9955 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9956 vmcs12->vm_exit_intr_error_code =
9957 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9958 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9959 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9960 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9961
5f3d5799
JK		 9962 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9963 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9964 * instead of reading the real value. */
4704d0be 9965 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9966
9967 /*
9968 * Transfer the event that L0 or L1 may wanted to inject into
9969 * L2 to IDT_VECTORING_INFO_FIELD.
9970 */
9971 vmcs12_save_pending_event(vcpu, vmcs12);
9972 }
9973
9974 /*
9975 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9976 * preserved above and would only end up incorrectly in L1.
9977 */
9978 vcpu->arch.nmi_injected = false;
9979 kvm_clear_exception_queue(vcpu);
9980 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9981}
9982
9983/*
9984 * A part of what we need to when the nested L2 guest exits and we want to
9985 * run its L1 parent, is to reset L1's guest state to the host state specified
9986 * in vmcs12.
9987 * This function is to be called not only on normal nested exit, but also on
9988 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9989 * Failures During or After Loading Guest State").
9990 * This function should be called when the active VMCS is L1's (vmcs01).
9991 */
733568f9
JK		 9992static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9993 struct vmcs12 *vmcs12)
4704d0be 9994{
21feb4eb
ACL		 9995 struct kvm_segment seg;
9996
4704d0be
NHE		 9997 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9998 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9999 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 10000 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10001 else
10002 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10003 vmx_set_efer(vcpu, vcpu->arch.efer);
10004
10005 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10006 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 10007 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 10008 /*
10009 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10010 * actually changed, because it depends on the current state of
10011 * fpu_active (which may have changed).
10012 * Note that vmx_set_cr0 refers to efer set above.
10013 */
9e3e4dbf 10014 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 10015 /*
10016 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10017 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10018 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10019 */
10020 update_exception_bitmap(vcpu);
10021 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10022 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10023
10024 /*
10025 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10026 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10027 */
10028 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10029 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10030
29bf08f1 10031 nested_ept_uninit_mmu_context(vcpu);
155a97a3 10032
4704d0be
NHE		 10033 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10034 kvm_mmu_reset_context(vcpu);
10035
feaf0c7d
GN		 10036 if (!enable_ept)
10037 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10038
4704d0be
NHE		 10039 if (enable_vpid) {
10040 /*
10041 * Trivially support vpid by letting L2s share their parent
10042 * L1's vpid. TODO: move to a more elaborate solution, giving
10043 * each L2 its own vpid and exposing the vpid feature to L1.
10044 */
10045 vmx_flush_tlb(vcpu);
10046 }
10047
10048
10049 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10050 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10051 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10052 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10053 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 10054
36be0b9d
PB		 10055 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10056 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10057 vmcs_write64(GUEST_BNDCFGS, 0);
10058
44811c02 10059 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 10060 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 10061 vcpu->arch.pat = vmcs12->host_ia32_pat;
10062 }
4704d0be
NHE		 10063 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10064 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10065 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 10066
21feb4eb
ACL		 10067 /* Set L1 segment info according to Intel SDM
10068 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10069 seg = (struct kvm_segment) {
10070 .base = 0,
10071 .limit = 0xFFFFFFFF,
10072 .selector = vmcs12->host_cs_selector,
10073 .type = 11,
10074 .present = 1,
10075 .s = 1,
10076 .g = 1
10077 };
10078 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10079 seg.l = 1;
10080 else
10081 seg.db = 1;
10082 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10083 seg = (struct kvm_segment) {
10084 .base = 0,
10085 .limit = 0xFFFFFFFF,
10086 .type = 3,
10087 .present = 1,
10088 .s = 1,
10089 .db = 1,
10090 .g = 1
10091 };
10092 seg.selector = vmcs12->host_ds_selector;
10093 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10094 seg.selector = vmcs12->host_es_selector;
10095 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10096 seg.selector = vmcs12->host_ss_selector;
10097 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10098 seg.selector = vmcs12->host_fs_selector;
10099 seg.base = vmcs12->host_fs_base;
10100 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10101 seg.selector = vmcs12->host_gs_selector;
10102 seg.base = vmcs12->host_gs_base;
10103 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10104 seg = (struct kvm_segment) {
205befd9 10105 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 10106 .limit = 0x67,
10107 .selector = vmcs12->host_tr_selector,
10108 .type = 11,
10109 .present = 1
10110 };
10111 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10112
503cd0c5
JK		 10113 kvm_set_dr(vcpu, 7, 0x400);
10114 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 10115
3af18d9c
WV		 10116 if (cpu_has_vmx_msr_bitmap())
10117 vmx_set_msr_bitmap(vcpu);
10118
ff651cb6
WV		 10119 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10120 vmcs12->vm_exit_msr_load_count))
10121 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 10122}
10123
10124/*
10125 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10126 * and modify vmcs12 to make it see what it would expect to see there if
10127 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10128 */
533558bc
JK		 10129static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10130 u32 exit_intr_info,
10131 unsigned long exit_qualification)
4704d0be
NHE		 10132{
10133 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 10134 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10135
5f3d5799
JK		 10136 /* trying to cancel vmlaunch/vmresume is a bug */
10137 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10138
4704d0be 10139 leave_guest_mode(vcpu);
533558bc
JK		 10140 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10141 exit_qualification);
4704d0be 10142
ff651cb6
WV		 10143 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10144 vmcs12->vm_exit_msr_store_count))
10145 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10146
f3380ca5
WL		 10147 vmx_load_vmcs01(vcpu);
10148
77b0f5d6
BD		 10149 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10150 && nested_exit_intr_ack_set(vcpu)) {
10151 int irq = kvm_cpu_get_interrupt(vcpu);
10152 WARN_ON(irq < 0);
10153 vmcs12->vm_exit_intr_info = irq |
10154 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10155 }
10156
542060ea
JK		 10157 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10158 vmcs12->exit_qualification,
10159 vmcs12->idt_vectoring_info_field,
10160 vmcs12->vm_exit_intr_info,
10161 vmcs12->vm_exit_intr_error_code,
10162 KVM_ISA_VMX);
4704d0be 10163
2961e876
GN		 10164 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10165 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 10166 vmx_segment_cache_clear(vmx);
10167
4704d0be
NHE		 10168 /* if no vmcs02 cache requested, remove the one we used */
10169 if (VMCS02_POOL_SIZE == 0)
10170 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10171
10172 load_vmcs12_host_state(vcpu, vmcs12);
10173
27fc51b2 10174 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 10175 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10176
10177 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10178 vmx->host_rsp = 0;
10179
10180 /* Unpin physical memory we referred to in vmcs02 */
10181 if (vmx->nested.apic_access_page) {
10182 nested_release_page(vmx->nested.apic_access_page);
48d89b92 10183 vmx->nested.apic_access_page = NULL;
4704d0be 10184 }
a7c0b07d
WL		 10185 if (vmx->nested.virtual_apic_page) {
10186 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 10187 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 10188 }
705699a1
WV		 10189 if (vmx->nested.pi_desc_page) {
10190 kunmap(vmx->nested.pi_desc_page);
10191 nested_release_page(vmx->nested.pi_desc_page);
10192 vmx->nested.pi_desc_page = NULL;
10193 vmx->nested.pi_desc = NULL;
10194 }
4704d0be 10195
38b99173
TC		 10196 /*
10197 * We are now running in L2, mmu_notifier will force to reload the
10198 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10199 */
10200 kvm_vcpu_reload_apic_access_page(vcpu);
10201
4704d0be
NHE		 10202 /*
10203 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10204 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10205 * success or failure flag accordingly.
10206 */
10207 if (unlikely(vmx->fail)) {
10208 vmx->fail = 0;
10209 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10210 } else
10211 nested_vmx_succeed(vcpu);
012f83cb
AG		 10212 if (enable_shadow_vmcs)
10213 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 10214
10215 /* in case we halted in L2 */
10216 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 10217}
10218
42124925
JK		 10219/*
10220 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10221 */
10222static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10223{
10224 if (is_guest_mode(vcpu))
533558bc 10225 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 10226 free_nested(to_vmx(vcpu));
10227}
10228
7c177938
NHE		 10229/*
10230 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10231 * 23.7 "VM-entry failures during or after loading guest state" (this also
10232 * lists the acceptable exit-reason and exit-qualification parameters).
10233 * It should only be called before L2 actually succeeded to run, and when
10234 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10235 */
10236static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10237 struct vmcs12 *vmcs12,
10238 u32 reason, unsigned long qualification)
10239{
10240 load_vmcs12_host_state(vcpu, vmcs12);
10241 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10242 vmcs12->exit_qualification = qualification;
10243 nested_vmx_succeed(vcpu);
012f83cb
AG		 10244 if (enable_shadow_vmcs)
10245 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 10246}
10247
8a76d7f2
JR		 10248static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10249 struct x86_instruction_info *info,
10250 enum x86_intercept_stage stage)
10251{
10252 return X86EMUL_CONTINUE;
10253}
10254
48d89b92 10255static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 10256{
b4a2d31d
RK		 10257 if (ple_gap)
10258 shrink_ple_window(vcpu);
ae97a3b8
RK		 10259}
10260
843e4330
KH		 10261static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10262 struct kvm_memory_slot *slot)
10263{
10264 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10265 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10266}
10267
10268static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10269 struct kvm_memory_slot *slot)
10270{
10271 kvm_mmu_slot_set_dirty(kvm, slot);
10272}
10273
10274static void vmx_flush_log_dirty(struct kvm *kvm)
10275{
10276 kvm_flush_pml_buffers(kvm);
10277}
10278
10279static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10280 struct kvm_memory_slot *memslot,
10281 gfn_t offset, unsigned long mask)
10282{
10283 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10284}
10285
cbdd1bea 10286static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 10287 .cpu_has_kvm_support = cpu_has_kvm_support,
10288 .disabled_by_bios = vmx_disabled_by_bios,
10289 .hardware_setup = hardware_setup,
10290 .hardware_unsetup = hardware_unsetup,
002c7f7c 10291 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 10292 .hardware_enable = hardware_enable,
10293 .hardware_disable = hardware_disable,
04547156 10294 .cpu_has_accelerated_tpr = report_flexpriority,
6d396b55 10295 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
6aa8b732
AK		 10296
10297 .vcpu_create = vmx_create_vcpu,
10298 .vcpu_free = vmx_free_vcpu,
04d2cc77 10299 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 10300
04d2cc77 10301 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 10302 .vcpu_load = vmx_vcpu_load,
10303 .vcpu_put = vmx_vcpu_put,
10304
c8639010 10305 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 10306 .get_msr = vmx_get_msr,
10307 .set_msr = vmx_set_msr,
10308 .get_segment_base = vmx_get_segment_base,
10309 .get_segment = vmx_get_segment,
10310 .set_segment = vmx_set_segment,
2e4d2653 10311 .get_cpl = vmx_get_cpl,
6aa8b732 10312 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 10313 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 10314 .decache_cr3 = vmx_decache_cr3,
25c4c276 10315 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 10316 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 10317 .set_cr3 = vmx_set_cr3,
10318 .set_cr4 = vmx_set_cr4,
6aa8b732 10319 .set_efer = vmx_set_efer,
6aa8b732
AK		 10320 .get_idt = vmx_get_idt,
10321 .set_idt = vmx_set_idt,
10322 .get_gdt = vmx_get_gdt,
10323 .set_gdt = vmx_set_gdt,
73aaf249
JK		 10324 .get_dr6 = vmx_get_dr6,
10325 .set_dr6 = vmx_set_dr6,
020df079 10326 .set_dr7 = vmx_set_dr7,
81908bf4 10327 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 10328 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 10329 .get_rflags = vmx_get_rflags,
10330 .set_rflags = vmx_set_rflags,
0fdd74f7 10331 .fpu_activate = vmx_fpu_activate,
02daab21 10332 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 10333
10334 .tlb_flush = vmx_flush_tlb,
6aa8b732 10335
6aa8b732 10336 .run = vmx_vcpu_run,
6062d012 10337 .handle_exit = vmx_handle_exit,
6aa8b732 10338 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 10339 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10340 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 10341 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 10342 .set_irq = vmx_inject_irq,
95ba8273 10343 .set_nmi = vmx_inject_nmi,
298101da 10344 .queue_exception = vmx_queue_exception,
b463a6f7 10345 .cancel_injection = vmx_cancel_injection,
78646121 10346 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 10347 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 10348 .get_nmi_mask = vmx_get_nmi_mask,
10349 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 10350 .enable_nmi_window = enable_nmi_window,
10351 .enable_irq_window = enable_irq_window,
10352 .update_cr8_intercept = update_cr8_intercept,
8d14695f 10353 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 10354 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d50ab6c1 10355 .cpu_uses_apicv = vmx_cpu_uses_apicv,
c7c9c56c
YZ		 10356 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10357 .hwapic_irr_update = vmx_hwapic_irr_update,
10358 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 10359 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10360 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 10361
cbc94022 10362 .set_tss_addr = vmx_set_tss_addr,
67253af5 10363 .get_tdp_level = get_ept_level,
4b12f0de 10364 .get_mt_mask = vmx_get_mt_mask,
229456fc 10365
586f9607 10366 .get_exit_info = vmx_get_exit_info,
586f9607 10367
17cc3935 10368 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 10369
10370 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 10371
10372 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 10373 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 10374
10375 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 10376
10377 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 10378
4051b188 10379 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 10380 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 10381 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 10382 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 10383 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 10384 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 10385
10386 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 10387
10388 .check_intercept = vmx_check_intercept,
a547c6db 10389 .handle_external_intr = vmx_handle_external_intr,
da8999d3 10390 .mpx_supported = vmx_mpx_supported,
55412b2e 10391 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 10392
10393 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 10394
10395 .sched_in = vmx_sched_in,
843e4330
KH		 10396
10397 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10398 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10399 .flush_log_dirty = vmx_flush_log_dirty,
10400 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
25462f7f
WH		 10401
10402 .pmu_ops = &intel_pmu_ops,
6aa8b732
AK		 10403};
10404
10405static int __init vmx_init(void)
10406{
34a1cd60
TC		 10407 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10408 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 10409 if (r)
34a1cd60 10410 return r;
25c5f225 10411
2965faa5 10412#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 10413 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10414 crash_vmclear_local_loaded_vmcss);
10415#endif
10416
fdef3ad1 10417 return 0;
6aa8b732
AK		 10418}
10419
10420static void __exit vmx_exit(void)
10421{
2965faa5 10422#ifdef CONFIG_KEXEC_CORE
3b63a43f 10423 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 10424 synchronize_rcu();
10425#endif
10426
cb498ea2 10427 kvm_exit();
6aa8b732
AK		 10428}
10429
10430module_init(vmx_init)
10431module_exit(vmx_exit)
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